Merge tag 'u-boot-stm32-20220907' of https://source.denx.de/u-boot/custodians/u-boot-stm
- simplify the STM32MP15x package parsing code
- remove test on CONFIG_DM_REGULATOR in stm32mp1 board
and enable CONFIG_DM_REGULATOR for stm32f769-disco
- handle ck_usbo_48m clock provided by USBPHYC to fix the command 'usb start'
after alignment with Linux kernel v5.19 DT (clocks = <&usbphyc>)
- Fix SYS_HZ_CLOCK value for stih410-b2260 board
- Switch STMM32MP15x DHSOM to FMC2 EBI driver
- Remove hwlocks from pinctrl in STM32MP15x to avoid issue with kernel
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
index 5f09ef0..3a4b665 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
@@ -67,11 +67,24 @@
#endif
}
+void tzpc_init(void)
+{
+ /*
+ * Mark the whole OCRAM as non-secure, otherwise DMA devices cannot
+ * access it. This is for example necessary for MMC boot.
+ */
+#ifdef TZPCR0SIZE_BASE
+ out_le32(TZPCR0SIZE_BASE, 0);
+#endif
+}
+
void board_init_f(ulong dummy)
{
int ret;
icache_enable();
+ tzpc_init();
+
/* Clear global data */
memset((void *)gd, 0, sizeof(gd_t));
if (IS_ENABLED(CONFIG_DEBUG_UART))
diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c
index 7e6e406..540436b 100644
--- a/arch/arm/cpu/armv8/sec_firmware.c
+++ b/arch/arm/cpu/armv8/sec_firmware.c
@@ -36,9 +36,6 @@
#ifndef SEC_FIRMWARE_FIT_IMAGE
#define SEC_FIRMWARE_FIT_IMAGE "firmware"
#endif
-#ifndef SEC_FIRMWARE_FIT_CNF_NAME
-#define SEC_FIRMWARE_FIT_CNF_NAME "config-1"
-#endif
#ifndef SEC_FIRMWARE_TARGET_EL
#define SEC_FIRMWARE_TARGET_EL 2
#endif
@@ -46,46 +43,8 @@
static int sec_firmware_get_data(const void *sec_firmware_img,
const void **data, size_t *size)
{
- int conf_node_off, fw_node_off;
- char *conf_node_name = NULL;
- char *desc;
- int ret;
-
- conf_node_name = SEC_FIRMWARE_FIT_CNF_NAME;
-
- conf_node_off = fit_conf_get_node(sec_firmware_img, conf_node_name);
- if (conf_node_off < 0) {
- printf("SEC Firmware: %s: no such config\n", conf_node_name);
- return -ENOENT;
- }
-
- fw_node_off = fit_conf_get_prop_node(sec_firmware_img, conf_node_off,
- SEC_FIRMWARE_FIT_IMAGE);
- if (fw_node_off < 0) {
- printf("SEC Firmware: No '%s' in config\n",
- SEC_FIRMWARE_FIT_IMAGE);
- return -ENOLINK;
- }
-
- /* Verify secure firmware image */
- if (!(fit_image_verify(sec_firmware_img, fw_node_off))) {
- printf("SEC Firmware: Bad firmware image (bad CRC)\n");
- return -EINVAL;
- }
-
- if (fit_image_get_data(sec_firmware_img, fw_node_off, data, size)) {
- printf("SEC Firmware: Can't get %s subimage data/size",
- SEC_FIRMWARE_FIT_IMAGE);
- return -ENOENT;
- }
-
- ret = fit_get_desc(sec_firmware_img, fw_node_off, &desc);
- if (ret)
- printf("SEC Firmware: Can't get description\n");
- else
- printf("%s\n", desc);
-
- return ret;
+ return fit_get_data_conf_prop(sec_firmware_img, SEC_FIRMWARE_FIT_IMAGE,
+ data, size);
}
/*
@@ -124,18 +83,15 @@
{
phys_addr_t sec_firmware_loadable_addr = 0;
int conf_node_off, ld_node_off, images;
- char *conf_node_name = NULL;
const void *data;
size_t size;
ulong load;
const char *name, *str, *type;
int len;
- conf_node_name = SEC_FIRMWARE_FIT_CNF_NAME;
-
- conf_node_off = fit_conf_get_node(sec_firmware_img, conf_node_name);
+ conf_node_off = fit_conf_get_node(sec_firmware_img, NULL);
if (conf_node_off < 0) {
- printf("SEC Firmware: %s: no such config\n", conf_node_name);
+ puts("SEC Firmware: no config\n");
return -ENOENT;
}
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 1b6cdc4..14d5c56 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -44,7 +44,9 @@
{
/* Do nothing */
}
+void board_reset_prepare(void) __attribute__((weak, alias("__board_reset")));
void board_reset(void) __attribute__((weak, alias("__board_reset")));
+void board_reset_last(void) __attribute__((weak, alias("__board_reset")));
int checkcpu (void)
{
@@ -319,12 +321,18 @@
#else
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ /* Call board-specific preparation for reset */
+ board_reset_prepare();
+
/* Attempt board-specific reset */
board_reset();
/* Next try asserting HRESET_REQ */
out_be32(&gur->rstcr, 0x2);
udelay(100);
+
+ /* Attempt last-stage board-specific reset */
+ board_reset_last();
#endif
return 1;
diff --git a/arch/riscv/dts/fu740-c000-u-boot.dtsi b/arch/riscv/dts/fu740-c000-u-boot.dtsi
index a6f7a08..917e9bf 100644
--- a/arch/riscv/dts/fu740-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu740-c000-u-boot.dtsi
@@ -7,11 +7,11 @@
/ {
cpus {
- assigned-clocks = <&prci PRCI_CLK_COREPLL>;
+ assigned-clocks = <&prci FU740_PRCI_CLK_COREPLL>;
assigned-clock-rates = <1200000000>;
u-boot,dm-spl;
cpu0: cpu@0 {
- clocks = <&prci PRCI_CLK_COREPLL>;
+ clocks = <&prci FU740_PRCI_CLK_COREPLL>;
u-boot,dm-spl;
status = "okay";
cpu0_intc: interrupt-controller {
@@ -19,28 +19,28 @@
};
};
cpu1: cpu@1 {
- clocks = <&prci PRCI_CLK_COREPLL>;
+ clocks = <&prci FU740_PRCI_CLK_COREPLL>;
u-boot,dm-spl;
cpu1_intc: interrupt-controller {
u-boot,dm-spl;
};
};
cpu2: cpu@2 {
- clocks = <&prci PRCI_CLK_COREPLL>;
+ clocks = <&prci FU740_PRCI_CLK_COREPLL>;
u-boot,dm-spl;
cpu2_intc: interrupt-controller {
u-boot,dm-spl;
};
};
cpu3: cpu@3 {
- clocks = <&prci PRCI_CLK_COREPLL>;
+ clocks = <&prci FU740_PRCI_CLK_COREPLL>;
u-boot,dm-spl;
cpu3_intc: interrupt-controller {
u-boot,dm-spl;
};
};
cpu4: cpu@4 {
- clocks = <&prci PRCI_CLK_COREPLL>;
+ clocks = <&prci FU740_PRCI_CLK_COREPLL>;
u-boot,dm-spl;
cpu4_intc: interrupt-controller {
u-boot,dm-spl;
@@ -76,7 +76,7 @@
reg = <0x0 0x100b0000 0x0 0x0800
0x0 0x100b2000 0x0 0x2000
0x0 0x100b8000 0x0 0x1000>;
- clocks = <&prci PRCI_CLK_DDRPLL>;
+ clocks = <&prci FU740_PRCI_CLK_DDRPLL>;
clock-frequency = <933333324>;
u-boot,dm-spl;
};
@@ -100,7 +100,7 @@
};
ð0 {
- assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>;
+ assigned-clocks = <&prci FU740_PRCI_CLK_GEMGXLPLL>;
assigned-clock-rates = <125125000>;
};
diff --git a/arch/riscv/dts/fu740-c000.dtsi b/arch/riscv/dts/fu740-c000.dtsi
index 649efe4..7b77c13 100644
--- a/arch/riscv/dts/fu740-c000.dtsi
+++ b/arch/riscv/dts/fu740-c000.dtsi
@@ -1,10 +1,9 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/* Copyright (c) 2020-2021 SiFive, Inc */
+/* Copyright (c) 2020 SiFive, Inc */
/dts-v1/;
#include <dt-bindings/clock/sifive-fu740-prci.h>
-#include <dt-bindings/reset/sifive-fu740-prci.h>
/ {
#address-cells = <2>;
@@ -139,20 +138,21 @@
soc {
#address-cells = <2>;
#size-cells = <2>;
- compatible = "sifive,fu740-c000", "sifive,fu740", "simple-bus";
+ compatible = "simple-bus";
ranges;
plic0: interrupt-controller@c000000 {
#interrupt-cells = <1>;
- compatible = "sifive,plic-1.0.0";
+ #address-cells = <0>;
+ compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
reg = <0x0 0xc000000 0x0 0x4000000>;
riscv,ndev = <69>;
interrupt-controller;
- interrupts-extended = <
- &cpu0_intc 0xffffffff
- &cpu1_intc 0xffffffff &cpu1_intc 9
- &cpu2_intc 0xffffffff &cpu2_intc 9
- &cpu3_intc 0xffffffff &cpu3_intc 9
- &cpu4_intc 0xffffffff &cpu4_intc 9>;
+ interrupts-extended =
+ <&cpu0_intc 0xffffffff>,
+ <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>,
+ <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>,
+ <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>,
+ <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>;
};
prci: clock-controller@10000000 {
compatible = "sifive,fu740-c000-prci";
@@ -166,7 +166,7 @@
reg = <0x0 0x10010000 0x0 0x1000>;
interrupt-parent = <&plic0>;
interrupts = <39>;
- clocks = <&prci PRCI_CLK_PCLK>;
+ clocks = <&prci FU740_PRCI_CLK_PCLK>;
status = "disabled";
};
uart1: serial@10011000 {
@@ -174,7 +174,7 @@
reg = <0x0 0x10011000 0x0 0x1000>;
interrupt-parent = <&plic0>;
interrupts = <40>;
- clocks = <&prci PRCI_CLK_PCLK>;
+ clocks = <&prci FU740_PRCI_CLK_PCLK>;
status = "disabled";
};
i2c0: i2c@10030000 {
@@ -182,7 +182,7 @@
reg = <0x0 0x10030000 0x0 0x1000>;
interrupt-parent = <&plic0>;
interrupts = <52>;
- clocks = <&prci PRCI_CLK_PCLK>;
+ clocks = <&prci FU740_PRCI_CLK_PCLK>;
reg-shift = <2>;
reg-io-width = <1>;
#address-cells = <1>;
@@ -194,7 +194,7 @@
reg = <0x0 0x10031000 0x0 0x1000>;
interrupt-parent = <&plic0>;
interrupts = <53>;
- clocks = <&prci PRCI_CLK_PCLK>;
+ clocks = <&prci FU740_PRCI_CLK_PCLK>;
reg-shift = <2>;
reg-io-width = <1>;
#address-cells = <1>;
@@ -203,22 +203,22 @@
};
qspi0: spi@10040000 {
compatible = "sifive,fu740-c000-spi", "sifive,spi0";
- reg = <0x0 0x10040000 0x0 0x1000
- 0x0 0x20000000 0x0 0x10000000>;
+ reg = <0x0 0x10040000 0x0 0x1000>,
+ <0x0 0x20000000 0x0 0x10000000>;
interrupt-parent = <&plic0>;
interrupts = <41>;
- clocks = <&prci PRCI_CLK_PCLK>;
+ clocks = <&prci FU740_PRCI_CLK_PCLK>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
qspi1: spi@10041000 {
compatible = "sifive,fu740-c000-spi", "sifive,spi0";
- reg = <0x0 0x10041000 0x0 0x1000
- 0x0 0x30000000 0x0 0x10000000>;
+ reg = <0x0 0x10041000 0x0 0x1000>,
+ <0x0 0x30000000 0x0 0x10000000>;
interrupt-parent = <&plic0>;
interrupts = <42>;
- clocks = <&prci PRCI_CLK_PCLK>;
+ clocks = <&prci FU740_PRCI_CLK_PCLK>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -228,7 +228,7 @@
reg = <0x0 0x10050000 0x0 0x1000>;
interrupt-parent = <&plic0>;
interrupts = <43>;
- clocks = <&prci PRCI_CLK_PCLK>;
+ clocks = <&prci FU740_PRCI_CLK_PCLK>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -237,12 +237,12 @@
compatible = "sifive,fu540-c000-gem";
interrupt-parent = <&plic0>;
interrupts = <55>;
- reg = <0x0 0x10090000 0x0 0x2000
- 0x0 0x100a0000 0x0 0x1000>;
+ reg = <0x0 0x10090000 0x0 0x2000>,
+ <0x0 0x100a0000 0x0 0x1000>;
local-mac-address = [00 00 00 00 00 00];
clock-names = "pclk", "hclk";
- clocks = <&prci PRCI_CLK_GEMGXLPLL>,
- <&prci PRCI_CLK_GEMGXLPLL>;
+ clocks = <&prci FU740_PRCI_CLK_GEMGXLPLL>,
+ <&prci FU740_PRCI_CLK_GEMGXLPLL>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -251,8 +251,8 @@
compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
reg = <0x0 0x10020000 0x0 0x1000>;
interrupt-parent = <&plic0>;
- interrupts = <44 45 46 47>;
- clocks = <&prci PRCI_CLK_PCLK>;
+ interrupts = <44>, <45>, <46>, <47>;
+ clocks = <&prci FU740_PRCI_CLK_PCLK>;
#pwm-cells = <3>;
status = "disabled";
};
@@ -260,8 +260,8 @@
compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
reg = <0x0 0x10021000 0x0 0x1000>;
interrupt-parent = <&plic0>;
- interrupts = <48 49 50 51>;
- clocks = <&prci PRCI_CLK_PCLK>;
+ interrupts = <48>, <49>, <50>, <51>;
+ clocks = <&prci FU740_PRCI_CLK_PCLK>;
#pwm-cells = <3>;
status = "disabled";
};
@@ -273,7 +273,7 @@
cache-size = <2097152>;
cache-unified;
interrupt-parent = <&plic0>;
- interrupts = <19 21 22 20>;
+ interrupts = <19>, <21>, <22>, <20>;
reg = <0x0 0x2010000 0x0 0x1000>;
};
gpio: gpio@10060000 {
@@ -287,28 +287,27 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&prci PRCI_CLK_PCLK>;
+ clocks = <&prci FU740_PRCI_CLK_PCLK>;
status = "disabled";
};
pcie@e00000000 {
+ compatible = "sifive,fu740-pcie";
#address-cells = <3>;
- #interrupt-cells = <1>;
- #num-lanes = <8>;
#size-cells = <2>;
- compatible = "sifive,fu740-pcie";
- reg = <0xe 0x00000000 0x1 0x0
- 0xd 0xf0000000 0x0 0x10000000
- 0x0 0x100d0000 0x0 0x1000>;
+ #interrupt-cells = <1>;
+ reg = <0xe 0x00000000 0x0 0x80000000>,
+ <0xd 0xf0000000 0x0 0x10000000>,
+ <0x0 0x100d0000 0x0 0x1000>;
reg-names = "dbi", "config", "mgmt";
device_type = "pci";
dma-coherent;
bus-range = <0x0 0xff>;
- ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000
- 0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000
- 0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000
- 0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>;
+ ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000>, /* I/O */
+ <0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000>, /* mem */
+ <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000>, /* mem */
+ <0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */
num-lanes = <0x8>;
- interrupts = <56 57 58 59 60 61 62 63 64>;
+ interrupts = <56>, <57>, <58>, <59>, <60>, <61>, <62>, <63>, <64>;
interrupt-names = "msi", "inta", "intb", "intc", "intd";
interrupt-parent = <&plic0>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
@@ -316,13 +315,11 @@
<0x0 0x0 0x0 0x2 &plic0 58>,
<0x0 0x0 0x0 0x3 &plic0 59>,
<0x0 0x0 0x0 0x4 &plic0 60>;
+ clock-names = "pcie_aux";
+ clocks = <&prci FU740_PRCI_CLK_PCIE_AUX>;
pwren-gpios = <&gpio 5 0>;
reset-gpios = <&gpio 8 0>;
- clocks = <&prci PRCI_CLK_PCIEAUX>;
- clock-names = "pcieaux";
- resets = <&prci PRCI_RST_PCIE_POWER_UP_N>;
- reset-names = "rst_n";
-
+ resets = <&prci 4>;
status = "okay";
};
};
diff --git a/arch/riscv/dts/hifive-unmatched-a00.dts b/arch/riscv/dts/hifive-unmatched-a00.dts
index b44e8c1..c4ed9ef 100644
--- a/arch/riscv/dts/hifive-unmatched-a00.dts
+++ b/arch/riscv/dts/hifive-unmatched-a00.dts
@@ -1,5 +1,5 @@
-// SPDX-License-Identifier: GPL-2.0+
-/* Copyright (c) 2019-2021 SiFive, Inc */
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020 SiFive, Inc */
#include "fu740-c000.dtsi"
#include <dt-bindings/gpio/gpio.h>
@@ -9,8 +9,6 @@
#define RTCCLK_FREQ 1000000
/ {
- #address-cells = <2>;
- #size-cells = <2>;
model = "SiFive HiFive Unmatched A00";
compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000",
"sifive,fu740";
@@ -28,9 +26,6 @@
reg = <0x0 0x80000000 0x4 0x00000000>;
};
- soc {
- };
-
hfclk: hfclk {
#clock-cells = <0>;
compatible = "fixed-clock";
@@ -65,10 +60,21 @@
temperature-sensor@4c {
compatible = "ti,tmp451";
reg = <0x4c>;
+ vcc-supply = <&vdd_bpro>;
interrupt-parent = <&gpio>;
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
};
+ eeprom@54 {
+ compatible = "microchip,24c02", "atmel,24c02";
+ reg = <0x54>;
+ vcc-supply = <&vdd_bpro>;
+ label = "board-id";
+ pagesize = <16>;
+ read-only;
+ size = <256>;
+ };
+
pmic@58 {
compatible = "dlg,da9063";
reg = <0x58>;
@@ -76,40 +82,44 @@
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
- regulators {
- vdd_bcore1: bcore1 {
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1050000>;
- regulator-min-microamp = <5000000>;
- regulator-max-microamp = <5000000>;
- regulator-always-on;
- };
+ onkey {
+ compatible = "dlg,da9063-onkey";
+ };
+
+ rtc {
+ compatible = "dlg,da9063-rtc";
+ };
+
+ wdt {
+ compatible = "dlg,da9063-watchdog";
+ };
- vdd_bcore2: bcore2 {
+ regulators {
+ vdd_bcore: bcores-merged {
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
- regulator-min-microamp = <5000000>;
- regulator-max-microamp = <5000000>;
+ regulator-min-microamp = <4800000>;
+ regulator-max-microamp = <4800000>;
regulator-always-on;
};
vdd_bpro: bpro {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
- regulator-min-microamp = <2500000>;
- regulator-max-microamp = <2500000>;
+ regulator-min-microamp = <2400000>;
+ regulator-max-microamp = <2400000>;
regulator-always-on;
};
vdd_bperi: bperi {
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1050000>;
+ regulator-min-microvolt = <1060000>;
+ regulator-max-microvolt = <1060000>;
regulator-min-microamp = <1500000>;
regulator-max-microamp = <1500000>;
regulator-always-on;
};
- vdd_bmem: bmem {
+ vdd_bmem_bio: bmem-bio-merged {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-min-microamp = <3000000>;
@@ -117,97 +127,69 @@
regulator-always-on;
};
- vdd_bio: bio {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-min-microamp = <3000000>;
- regulator-max-microamp = <3000000>;
- regulator-always-on;
- };
-
vdd_ldo1: ldo1 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
- regulator-min-microamp = <100000>;
- regulator-max-microamp = <100000>;
regulator-always-on;
};
vdd_ldo2: ldo2 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
- regulator-min-microamp = <200000>;
- regulator-max-microamp = <200000>;
regulator-always-on;
};
vdd_ldo3: ldo3 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- regulator-min-microamp = <200000>;
- regulator-max-microamp = <200000>;
regulator-always-on;
};
vdd_ldo4: ldo4 {
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
- regulator-min-microamp = <200000>;
- regulator-max-microamp = <200000>;
regulator-always-on;
};
vdd_ldo5: ldo5 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- regulator-min-microamp = <100000>;
- regulator-max-microamp = <100000>;
regulator-always-on;
};
vdd_ldo6: ldo6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
- regulator-min-microamp = <200000>;
- regulator-max-microamp = <200000>;
regulator-always-on;
};
vdd_ldo7: ldo7 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- regulator-min-microamp = <200000>;
- regulator-max-microamp = <200000>;
regulator-always-on;
};
vdd_ldo8: ldo8 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- regulator-min-microamp = <200000>;
- regulator-max-microamp = <200000>;
regulator-always-on;
};
vdd_ld09: ldo9 {
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
- regulator-min-microamp = <200000>;
- regulator-max-microamp = <200000>;
+ regulator-always-on;
};
vdd_ldo10: ldo10 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
- regulator-min-microamp = <300000>;
- regulator-max-microamp = <300000>;
+ regulator-always-on;
};
vdd_ldo11: ldo11 {
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
- regulator-min-microamp = <300000>;
- regulator-max-microamp = <300000>;
regulator-always-on;
};
};
@@ -217,7 +199,7 @@
&qspi0 {
status = "okay";
flash@0 {
- compatible = "issi,is25wp256", "jedec,spi-nor";
+ compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
m25p,fast-read;
@@ -234,6 +216,7 @@
spi-max-frequency = <20000000>;
voltage-ranges = <3300 3300>;
disable-wp;
+ gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
};
};
@@ -256,4 +239,8 @@
&gpio {
status = "okay";
+ gpio-line-names = "J29.1", "PMICNTB", "PMICSHDN", "J8.1", "J8.3",
+ "PCIe_PWREN", "THERM", "UBRDG_RSTN", "PCIe_PERSTN",
+ "ULPI_RSTN", "J8.2", "UHUB_RSTN", "GEMGXL_RST", "J8.4",
+ "EN_VDD_SD", "SD_CD";
};
diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c
index 08b43ff..4d2fce3 100644
--- a/board/freescale/ls1043ardb/ddr.c
+++ b/board/freescale/ls1043ardb/ddr.c
@@ -114,7 +114,7 @@
.mirrored_dimm = 0,
.n_row_addr = 15,
.n_col_addr = 10,
- .bank_addr_bits = 0,
+ .bank_addr_bits = 2,
.bank_group_bits = 2,
.edc_config = 0,
.burst_lengths_bitmask = 0x0c,
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index a71952d..b301491 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -83,7 +83,19 @@
#define CPLD_FXS_LED 0x0F
#define CPLD_SYS_RST 0x00
-void board_reset(void)
+void board_reset_prepare(void)
+{
+ /*
+ * During reset preparation, turn off external watchdog.
+ * This ensures that external watchdog does not trigger
+ * another reset or possible infinite reset loop.
+ */
+ struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+ out_8(&cpld_data->wd_cfg, CPLD_WD_CFG);
+ in_8(&cpld_data->wd_cfg); /* Read back to sync write */
+}
+
+void board_reset_last(void)
{
struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
out_8(&cpld_data->system_rst, 1);
@@ -92,12 +104,46 @@
void board_cpld_init(void)
{
struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+ u8 prev_wd_cfg = in_8(&cpld_data->wd_cfg);
out_8(&cpld_data->wd_cfg, CPLD_WD_CFG);
out_8(&cpld_data->status_led, CPLD_STATUS_LED);
out_8(&cpld_data->fxo_led, CPLD_FXO_LED);
out_8(&cpld_data->fxs_led, CPLD_FXS_LED);
+
+ /*
+ * CPLD's system reset register on P1/P2 RDB boards is not autocleared
+ * after flipping it. If this register is set to one then CPLD triggers
+ * reset of CPU in few ms.
+ *
+ * CPLD does not trigger reset of CPU for 100ms after the last reset.
+ *
+ * This means that trying to reset board via CPLD system reset register
+ * cause reboot loop. To prevent this reboot loop, the only workaround
+ * is to try to clear CPLD's system reset register as early as possible
+ * and it has to be done in 100ms since the last start of reset.
+ */
out_8(&cpld_data->system_rst, CPLD_SYS_RST);
+
+ /*
+ * If watchdog timer was already set to non-disabled value then it means
+ * that watchdog timer was already activated, has already expired and
+ * caused CPU reset. If this happened then due to CPLD firmware bug,
+ * writing to wd_cfg register has no effect and therefore it is not
+ * possible to reactivate watchdog timer again. Also if CPU was reset
+ * via watchdog then some peripherals like i2c do not work. Watchdog and
+ * i2c start working again after CPU reset via non-watchdog method.
+ *
+ * So in case watchdog timer register in CPLD was already enabled then
+ * disable it in CPLD and reset CPU which cause new boot. Watchdog timer
+ * is disabled few lines above, after reading CPLD previous value.
+ * This logic (disabling timer before reset) prevents reboot loop.
+ */
+ if (prev_wd_cfg != CPLD_WD_CFG) {
+ eieio();
+ do_reset(NULL, 0, 0, NULL);
+ while (1); /* do_reset() does not occur immediately */
+ }
}
void board_gpio_init(void)
@@ -368,6 +414,24 @@
}
#endif
+#if defined(CONFIG_OF_BOARD_SETUP) || defined(CONFIG_OF_BOARD_FIXUP)
+static void fix_max6370_watchdog(void *blob)
+{
+ int off = fdt_node_offset_by_compatible(blob, -1, "maxim,max6370");
+ ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+ u32 gpioval = in_be32(&pgpio->gpdat);
+
+ /*
+ * Delete watchdog max6370 node in load_default mode (detected by
+ * GPIO7 - LOAD_DEFAULT_N) because CPLD in load_default mode ignores
+ * watchdog reset signal. CPLD in load_default mode does not reset
+ * board when watchdog triggers reset signal.
+ */
+ if (!(gpioval & BIT(31-7)) && off >= 0)
+ fdt_del_node(blob, off);
+}
+#endif
+
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, struct bd_info *bd)
{
@@ -393,6 +457,8 @@
sizeof("okay"), 0);
#endif
+ fix_max6370_watchdog(blob);
+
#if defined(CONFIG_HAS_FSL_DR_USB)
fsl_fdt_fixup_dr_usb(blob, bd);
#endif
@@ -444,3 +510,11 @@
return 0;
}
#endif
+
+#ifdef CONFIG_OF_BOARD_FIXUP
+int board_fix_fdt(void *blob)
+{
+ fix_max6370_watchdog(blob);
+ return 0;
+}
+#endif
diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c
index b60027e..eda84bf 100644
--- a/board/freescale/p1_p2_rdb_pc/spl.c
+++ b/board/freescale/p1_p2_rdb_pc/spl.c
@@ -31,6 +31,12 @@
u32 plat_ratio, bus_clk;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ /*
+ * Call board_early_init_f() as early as possible as it workarounds
+ * reboot loop due to broken CPLD state machine for reset line.
+ */
+ board_early_init_f();
+
console_init_f();
/* Set pmuxcr to allow both i2c1 and i2c2 */
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c
index 105d9e3..65cedd4 100644
--- a/board/freescale/p1_p2_rdb_pc/tlb.c
+++ b/board/freescale/p1_p2_rdb_pc/tlb.c
@@ -61,11 +61,11 @@
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_1M, 1),
#endif
+#endif /* not SPL */
SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_1M, 1),
-#endif /* not SPL */
#ifdef CONFIG_SYS_NAND_BASE
/* *I*G - NAND */
diff --git a/board/kontron/sl28/common.c b/board/kontron/sl28/common.c
index 33c6843..331de29 100644
--- a/board/kontron/sl28/common.c
+++ b/board/kontron/sl28/common.c
@@ -2,6 +2,9 @@
#include <common.h>
#include <asm/global_data.h>
+#include <asm/io.h>
+
+#include "sl28.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -9,3 +12,22 @@
{
return gd->bus_clk / CONFIG_SYS_FSL_LPUART_CLK_DIV;
}
+
+enum boot_source sl28_boot_source(void)
+{
+ u32 rcw_src = in_le32(DCFG_BASE + DCFG_PORSR1) & DCFG_PORSR1_RCW_SRC;
+
+ switch (rcw_src) {
+ case DCFG_PORSR1_RCW_SRC_SDHC1:
+ return BOOT_SOURCE_SDHC;
+ case DCFG_PORSR1_RCW_SRC_SDHC2:
+ return BOOT_SOURCE_MMC;
+ case DCFG_PORSR1_RCW_SRC_I2C:
+ return BOOT_SOURCE_I2C;
+ case DCFG_PORSR1_RCW_SRC_FSPI_NOR:
+ return BOOT_SOURCE_SPI;
+ default:
+ debug("unknown bootsource (%08x)\n", rcw_src);
+ return BOOT_SOURCE_UNKNOWN;
+ }
+}
diff --git a/board/kontron/sl28/sl28.c b/board/kontron/sl28/sl28.c
index 32e9694..0576b3e 100644
--- a/board/kontron/sl28/sl28.c
+++ b/board/kontron/sl28/sl28.c
@@ -24,6 +24,8 @@
#include <fdtdec.h>
#include <miiphy.h>
+#include "sl28.h"
+
DECLARE_GLOBAL_DATA_PTR;
#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT)
@@ -60,6 +62,27 @@
return pci_eth_init(bis);
}
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ enum boot_source src = sl28_boot_source();
+
+ if (prio)
+ return ENVL_UNKNOWN;
+
+ if (!CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH))
+ return ENVL_NOWHERE;
+
+ /* write and erase always operate on the environment */
+ if (op == ENVOP_SAVE || op == ENVOP_ERASE)
+ return ENVL_SPI_FLASH;
+
+ /* failsafe boot will always use the compiled-in default environment */
+ if (src == BOOT_SOURCE_SPI)
+ return ENVL_NOWHERE;
+
+ return ENVL_SPI_FLASH;
+}
+
static int __sl28cpld_read(uint reg)
{
struct udevice *dev;
@@ -103,8 +126,28 @@
wdt_stop(dev);
}
+static void sl28_set_prompt(void)
+{
+ enum boot_source src = sl28_boot_source();
+
+ switch (src) {
+ case BOOT_SOURCE_SPI:
+ env_set("PS1", "[FAILSAFE] => ");
+ break;
+ case BOOT_SOURCE_SDHC:
+ env_set("PS1", "[SDHC] => ");
+ break;
+ default:
+ env_set("PS1", NULL);
+ break;
+ }
+}
+
int fsl_board_late_init(void)
{
+ if (IS_ENABLED(CONFIG_CMDLINE_PS_SUPPORT))
+ sl28_set_prompt();
+
/*
* Usually, the after a board reset, the watchdog is enabled by
* default. This is to supervise the bootloader boot-up. Therefore,
diff --git a/board/kontron/sl28/sl28.h b/board/kontron/sl28/sl28.h
new file mode 100644
index 0000000..7f01050
--- /dev/null
+++ b/board/kontron/sl28/sl28.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __SL28_H
+#define __SL28_H
+
+enum boot_source {
+ BOOT_SOURCE_UNKNOWN,
+ BOOT_SOURCE_SDHC,
+ BOOT_SOURCE_MMC,
+ BOOT_SOURCE_I2C,
+ BOOT_SOURCE_SPI,
+};
+
+enum boot_source sl28_boot_source(void);
+
+#endif
diff --git a/board/kontron/sl28/spl.c b/board/kontron/sl28/spl.c
index 0e6ad5f..ffaf517 100644
--- a/board/kontron/sl28/spl.c
+++ b/board/kontron/sl28/spl.c
@@ -5,6 +5,9 @@
#include <asm/spl.h>
#include <asm/arch-fsl-layerscape/fsl_serdes.h>
#include <asm/arch-fsl-layerscape/soc.h>
+#include <spi_flash.h>
+
+#include "sl28.h"
#define DCFG_RCWSR25 0x160
#define GPINFO_HW_VARIANT_MASK 0xff
@@ -58,7 +61,56 @@
void board_boot_order(u32 *spl_boot_list)
{
+ enum boot_source src = sl28_boot_source();
+
+ switch (src) {
+ case BOOT_SOURCE_SDHC:
+ spl_boot_list[0] = BOOT_DEVICE_MMC2;
+ break;
+ case BOOT_SOURCE_SPI:
+ case BOOT_SOURCE_I2C:
+ spl_boot_list[0] = BOOT_DEVICE_SPI;
+ break;
+ case BOOT_SOURCE_MMC:
+ spl_boot_list[0] = BOOT_DEVICE_MMC1;
+ break;
+ default:
+ panic("unexpected bootsource (%d)\n", src);
+ break;
+ }
+}
+
+unsigned int spl_spi_get_uboot_offs(struct spi_flash *flash)
+{
+ enum boot_source src = sl28_boot_source();
+
+ switch (src) {
+ case BOOT_SOURCE_SPI:
+ return 0x000000;
+ case BOOT_SOURCE_I2C:
+ return 0x230000;
+ default:
+ panic("unexpected bootsource (%d)\n", src);
+ break;
+ }
+}
+
+const char *spl_board_loader_name(u32 boot_device)
+{
- spl_boot_list[0] = BOOT_DEVICE_SPI;
+ enum boot_source src = sl28_boot_source();
+
+ switch (src) {
+ case BOOT_SOURCE_SDHC:
+ return "SD card (Test mode)";
+ case BOOT_SOURCE_SPI:
+ return "Failsafe SPI flash";
+ case BOOT_SOURCE_I2C:
+ return "SPI flash";
+ case BOOT_SOURCE_MMC:
+ return "eMMC";
+ default:
+ return "(unknown)";
+ }
}
int board_early_init_f(void)
diff --git a/boot/image-fit.c b/boot/image-fit.c
index 21dbd05..f16eab9 100644
--- a/boot/image-fit.c
+++ b/boot/image-fit.c
@@ -1916,6 +1916,43 @@
return fit_conf_get_prop_node_index(fit, noffset, prop_name, 0);
}
+static int fit_get_data_tail(const void *fit, int noffset,
+ const void **data, size_t *size)
+{
+ char *desc;
+
+ if (noffset < 0)
+ return noffset;
+
+ if (!fit_image_verify(fit, noffset))
+ return -EINVAL;
+
+ if (fit_image_get_data_and_size(fit, noffset, data, size))
+ return -ENOENT;
+
+ if (!fit_get_desc(fit, noffset, &desc))
+ printf("%s\n", desc);
+
+ return 0;
+}
+
+int fit_get_data_node(const void *fit, const char *image_uname,
+ const void **data, size_t *size)
+{
+ int noffset = fit_image_get_node(fit, image_uname);
+
+ return fit_get_data_tail(fit, noffset, data, size);
+}
+
+int fit_get_data_conf_prop(const void *fit, const char *prop_name,
+ const void **data, size_t *size)
+{
+ int noffset = fit_conf_get_node(fit, NULL);
+
+ noffset = fit_conf_get_prop_node(fit, noffset, prop_name);
+ return fit_get_data_tail(fit, noffset, data, size);
+}
+
static int fit_image_select(const void *fit, int rd_noffset, int verify)
{
fit_image_print(fit, rd_noffset, " ");
diff --git a/cmd/fpga.c b/cmd/fpga.c
index c4651dd..9cf7651 100644
--- a/cmd/fpga.c
+++ b/cmd/fpga.c
@@ -322,7 +322,7 @@
case IMAGE_FORMAT_FIT:
{
const void *fit_hdr = (const void *)fpga_data;
- int noffset;
+ int err;
const void *fit_data;
if (!fit_uname) {
@@ -335,23 +335,11 @@
return CMD_RET_FAILURE;
}
- /* get fpga component image node offset */
- noffset = fit_image_get_node(fit_hdr, fit_uname);
- if (noffset < 0) {
- printf("Can't find '%s' FIT subimage\n", fit_uname);
- return CMD_RET_FAILURE;
- }
-
- /* verify integrity */
- if (!fit_image_verify(fit_hdr, noffset)) {
- puts("Bad Data Hash\n");
- return CMD_RET_FAILURE;
- }
-
- /* get fpga subimage/external data address and length */
- if (fit_image_get_data_and_size(fit_hdr, noffset,
- &fit_data, &data_size)) {
- puts("Fpga subimage data not found\n");
+ err = fit_get_data_node(fit_hdr, fit_uname, &fit_data,
+ &data_size);
+ if (err) {
+ printf("Could not load '%s' subimage (err %d)\n",
+ fit_uname, err);
return CMD_RET_FAILURE;
}
diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c
index ee11e0f..522f502 100644
--- a/cmd/riscv/sbi.c
+++ b/cmd/riscv/sbi.c
@@ -68,11 +68,21 @@
ret = sbi_get_impl_version(&vers);
if (ret < 0)
break;
- if (impl_id == 1)
+ switch (impl_id) {
+ case 1: /* OpenSBI */
printf("%ld.%ld",
vers >> 16, vers & 0xffff);
- else
+ break;
+ case 3: /* KVM */
+ printf("%ld.%ld.%ld",
+ vers >> 16,
+ (vers >> 8) & 0xff,
+ vers & 0xff);
+ break;
+ default:
printf("0x%lx", vers);
+ break;
+ }
break;
}
}
diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig
index b0b5fb1..fc1c607 100644
--- a/configs/kontron_sl28_defconfig
+++ b/configs/kontron_sl28_defconfig
@@ -12,6 +12,7 @@
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-kontron-sl28"
CONFIG_SPL_TEXT_BASE=0x18010000
CONFIG_SYS_FSL_SDHC_CLK_DIV=1
+CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_SIZE_LIMIT=0x20000
CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x0
@@ -46,12 +47,15 @@
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK=0x18009ff0
CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x900
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x230000
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
CONFIG_SYS_BOOTM_LEN=0x800000
+CONFIG_CMDLINE_PS_SUPPORT=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_NVEDIT_EFI=y
diff --git a/drivers/clk/sifive/fu740-prci.c b/drivers/clk/sifive/fu740-prci.c
index b025050..5edc864 100644
--- a/drivers/clk/sifive/fu740-prci.c
+++ b/drivers/clk/sifive/fu740-prci.c
@@ -103,53 +103,53 @@
/* List of clock controls provided by the PRCI */
struct __prci_clock __prci_init_clocks_fu740[] = {
- [PRCI_CLK_COREPLL] = {
+ [FU740_PRCI_CLK_COREPLL] = {
.name = "corepll",
.parent_name = "hfclk",
.ops = &sifive_fu740_prci_wrpll_clk_ops,
.pwd = &__prci_corepll_data,
},
- [PRCI_CLK_DDRPLL] = {
+ [FU740_PRCI_CLK_DDRPLL] = {
.name = "ddrpll",
.parent_name = "hfclk",
.ops = &sifive_fu740_prci_wrpll_clk_ops,
.pwd = &__prci_ddrpll_data,
},
- [PRCI_CLK_GEMGXLPLL] = {
+ [FU740_PRCI_CLK_GEMGXLPLL] = {
.name = "gemgxlpll",
.parent_name = "hfclk",
.ops = &sifive_fu740_prci_wrpll_clk_ops,
.pwd = &__prci_gemgxlpll_data,
},
- [PRCI_CLK_DVFSCOREPLL] = {
+ [FU740_PRCI_CLK_DVFSCOREPLL] = {
.name = "dvfscorepll",
.parent_name = "hfclk",
.ops = &sifive_fu740_prci_wrpll_clk_ops,
.pwd = &__prci_dvfscorepll_data,
},
- [PRCI_CLK_HFPCLKPLL] = {
+ [FU740_PRCI_CLK_HFPCLKPLL] = {
.name = "hfpclkpll",
.parent_name = "hfclk",
.ops = &sifive_fu740_prci_wrpll_clk_ops,
.pwd = &__prci_hfpclkpll_data,
},
- [PRCI_CLK_CLTXPLL] = {
+ [FU740_PRCI_CLK_CLTXPLL] = {
.name = "cltxpll",
.parent_name = "hfclk",
.ops = &sifive_fu740_prci_wrpll_clk_ops,
.pwd = &__prci_cltxpll_data,
},
- [PRCI_CLK_TLCLK] = {
+ [FU740_PRCI_CLK_TLCLK] = {
.name = "tlclk",
.parent_name = "corepll",
.ops = &sifive_fu740_prci_tlclksel_clk_ops,
},
- [PRCI_CLK_PCLK] = {
+ [FU740_PRCI_CLK_PCLK] = {
.name = "pclk",
.parent_name = "hfpclkpll",
.ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops,
},
- [PRCI_CLK_PCIEAUX] {
+ [FU740_PRCI_CLK_PCIE_AUX] {
.name = "pcieaux",
.parent_name = "",
.ops = &sifive_fu740_prci_pcieaux_clk_ops,
diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c
index 52ae268..c8fb600 100644
--- a/drivers/clk/sifive/sifive-prci.c
+++ b/drivers/clk/sifive/sifive-prci.c
@@ -685,14 +685,14 @@
* case the design uses hfpclk to drive
* Chiplink
*/
- pc = &data->clks[PRCI_CLK_HFPCLKPLL];
+ pc = &data->clks[FU740_PRCI_CLK_HFPCLKPLL];
parent_rate = sifive_prci_parent_rate(pc, data);
sifive_prci_wrpll_set_rate(pc, 260000000,
parent_rate);
pc->ops->enable_clk(pc, 1);
} else if (prci_pll_reg & PRCI_PRCIPLL_CLTXPLL) {
/* CLTX pll init */
- pc = &data->clks[PRCI_CLK_CLTXPLL];
+ pc = &data->clks[FU740_PRCI_CLK_CLTXPLL];
parent_rate = sifive_prci_parent_rate(pc, data);
sifive_prci_wrpll_set_rate(pc, 260000000,
parent_rate);
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index b5122d1..0b0b4e5 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -214,7 +214,7 @@
odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
#ifdef CONFIG_SYS_FSL_DDR4
- ba_bits_cs_n = dimm_params[dimm_number].bank_addr_bits;
+ ba_bits_cs_n = dimm_params[dimm_number].bank_addr_bits - 2;
bg_bits_cs_n = dimm_params[dimm_number].bank_group_bits;
#else
n_banks_per_sdram_device
diff --git a/drivers/ddr/fsl/ddr4_dimm_params.c b/drivers/ddr/fsl/ddr4_dimm_params.c
index e2bdc12..ea79162 100644
--- a/drivers/ddr/fsl/ddr4_dimm_params.c
+++ b/drivers/ddr/fsl/ddr4_dimm_params.c
@@ -246,7 +246,7 @@
/* SDRAM device parameters */
pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12;
pdimm->n_col_addr = (spd->addressing & 0x7) + 9;
- pdimm->bank_addr_bits = (spd->density_banks >> 4) & 0x3;
+ pdimm->bank_addr_bits = ((spd->density_banks >> 4) & 0x3) + 2;
pdimm->bank_group_bits = (spd->density_banks >> 6) & 0x3;
/*
diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c
index 2f76beb..eb2f06e 100644
--- a/drivers/ddr/fsl/interactive.c
+++ b/drivers/ddr/fsl/interactive.c
@@ -27,9 +27,9 @@
/* Option parameter Structures */
struct options_string {
const char *option_name;
- size_t offset;
- unsigned int size;
- const char printhex;
+ u32 offset : 9;
+ u32 size : 4;
+ u32 printhex : 1;
};
static unsigned int picos_to_mhz(unsigned int picos)
diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index d0b492b..ee96abb 100644
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
#include <env.h>
+#include <image.h>
#include <malloc.h>
#include <asm/io.h>
#include <linux/errno.h>
@@ -513,6 +514,23 @@
void *addr = NULL;
#endif
+ rc = fit_check_format(addr, CONFIG_SYS_QE_FMAN_FW_LENGTH);
+ if (!rc) {
+ size_t unused;
+ const void *new_addr;
+
+ rc = fit_get_data_conf_prop(addr, "fman", &new_addr, &unused);
+ if (rc)
+ return rc;
+ addr = (void *)new_addr;
+ } else if (CONFIG_IS_ENABLED(FIT_SIGNATURE)) {
+ /*
+ * Using a (signed) FIT wrapper is mandatory if we are
+ * doing verified boot.
+ */
+ return rc;
+ }
+
/* Upload the Fman microcode if it's present */
rc = fman_upload_firmware(index, ®->fm_imem, addr);
if (rc)
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index bc1c31d..68833f9 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -137,13 +137,7 @@
size_t *raw_image_size)
{
int format;
- void *fit_hdr;
- int node_offset;
- const void *data;
- size_t size;
- const char *uname = "firmware";
-
- fit_hdr = (void *)mc_fw_addr;
+ void *fit_hdr = (void *)mc_fw_addr;
/* Check if Image is in FIT format */
format = genimg_get_format(fit_hdr);
@@ -158,26 +152,8 @@
return -EINVAL;
}
- node_offset = fit_image_get_node(fit_hdr, uname);
-
- if (node_offset < 0) {
- printf("fsl-mc: ERR: Bad firmware image (missing subimage)\n");
- return -ENOENT;
- }
-
- /* Verify MC firmware image */
- if (!(fit_image_verify(fit_hdr, node_offset))) {
- printf("fsl-mc: ERR: Bad firmware image (bad CRC)\n");
- return -EINVAL;
- }
-
- /* Get address and size of raw image */
- fit_image_get_data(fit_hdr, node_offset, &data, &size);
-
- *raw_image_addr = data;
- *raw_image_size = size;
-
- return 0;
+ return fit_get_data_node(fit_hdr, "firmware", raw_image_addr,
+ raw_image_size);
}
#endif
diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c
index cd4c2c2..835e5bd 100644
--- a/drivers/net/fsl_enetc.c
+++ b/drivers/net/fsl_enetc.c
@@ -22,6 +22,8 @@
#define ENETC_DRIVER_NAME "enetc_eth"
+static int enetc_remove(struct udevice *dev);
+
/*
* sets the MAC address in IERB registers, this setting is persistent and
* carried over to Linux.
@@ -319,6 +321,7 @@
static int enetc_probe(struct udevice *dev)
{
struct enetc_priv *priv = dev_get_priv(dev);
+ int res;
if (ofnode_valid(dev_ofnode(dev)) && !ofnode_is_available(dev_ofnode(dev))) {
enetc_dbg(dev, "interface disabled\n");
@@ -350,7 +353,10 @@
enetc_start_pcs(dev);
- return enetc_config_phy(dev);
+ res = enetc_config_phy(dev);
+ if(res)
+ enetc_remove(dev);
+ return res;
}
/*
diff --git a/drivers/net/pfe_eth/pfe_firmware.c b/drivers/net/pfe_eth/pfe_firmware.c
index 82a4aa8..da4f2ca 100644
--- a/drivers/net/pfe_eth/pfe_firmware.c
+++ b/drivers/net/pfe_eth/pfe_firmware.c
@@ -104,45 +104,7 @@
static int pfe_get_fw(const void **data,
size_t *size, char *fw_name)
{
- int conf_node_off, fw_node_off;
- char *conf_node_name = NULL;
- char *desc;
- int ret = 0;
-
- conf_node_name = PFE_FIRMWARE_FIT_CNF_NAME;
-
- conf_node_off = fit_conf_get_node(pfe_fit_addr, conf_node_name);
- if (conf_node_off < 0) {
- printf("PFE Firmware: %s: no such config\n", conf_node_name);
- return -ENOENT;
- }
-
- fw_node_off = fit_conf_get_prop_node(pfe_fit_addr, conf_node_off,
- fw_name);
- if (fw_node_off < 0) {
- printf("PFE Firmware: No '%s' in config\n",
- fw_name);
- return -ENOLINK;
- }
-
- if (!(fit_image_verify(pfe_fit_addr, fw_node_off))) {
- printf("PFE Firmware: Bad firmware image (bad CRC)\n");
- return -EINVAL;
- }
-
- if (fit_image_get_data(pfe_fit_addr, fw_node_off, data, size)) {
- printf("PFE Firmware: Can't get %s subimage data/size",
- fw_name);
- return -ENOENT;
- }
-
- ret = fit_get_desc(pfe_fit_addr, fw_node_off, &desc);
- if (ret)
- printf("PFE Firmware: Can't get description\n");
- else
- printf("%s\n", desc);
-
- return ret;
+ return fit_get_data_conf_prop(pfe_fit_addr, fw_name, data, size);
}
/*
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index a0acffa..03f7fdd 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -113,6 +113,7 @@
config SYSRESET_SBI
bool "Enable support for SBI System Reset"
depends on RISCV_SMODE && SBI_V02
+ default y
select SYSRESET_CMD_POWEROFF if CMD_POWEROFF
help
Enable system reset and poweroff via the SBI system reset extension.
diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h
index 38063ba..df46e58 100644
--- a/include/configs/kontron_sl28.h
+++ b/include/configs/kontron_sl28.h
@@ -37,8 +37,6 @@
/* serial port */
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
-#define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4)
-
/* SPL */
#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
diff --git a/include/configs/p1_p2_bootsrc.h b/include/configs/p1_p2_bootsrc.h
index 13e4fdb..d155e55 100644
--- a/include/configs/p1_p2_bootsrc.h
+++ b/include/configs/p1_p2_bootsrc.h
@@ -34,6 +34,18 @@
#define RST_NOR_CMD(var, ...) ""
#endif
+#ifdef __SW_BOOT_NOR_BANK_LO
+#define RST_NOR_LO_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_NOR_BANK_LO, __SW_BOOT_MASK))
+#else
+#define RST_NOR_LO_CMD(var, ...) ""
+#endif
+
+#ifdef __SW_BOOT_NOR_BANK_UP
+#define RST_NOR_UP_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_NOR_BANK_UP, __SW_BOOT_MASK))
+#else
+#define RST_NOR_UP_CMD(var, ...) ""
+#endif
+
#ifdef __SW_BOOT_SPI
#define RST_SPI_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_SPI, __SW_BOOT_MASK))
#else
@@ -46,6 +58,12 @@
#define RST_SD_CMD(var, ...) ""
#endif
+#ifdef __SW_BOOT_SD2
+#define RST_SD2_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_SD2, __SW_BOOT_MASK))
+#else
+#define RST_SD2_CMD(var, ...) ""
+#endif
+
#ifdef __SW_BOOT_NAND
#define RST_NAND_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_NAND, __SW_BOOT_MASK))
#else
@@ -57,3 +75,5 @@
#else
#define RST_PCIE_CMD(var, ...) ""
#endif
+
+#define RST_DEF_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(0x00, 0xff))
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index f7d8723..d201c72 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -24,6 +24,9 @@
#define __SW_NOR_BANK_MASK 0xfd
#define __SW_NOR_BANK_UP 0x00
#define __SW_NOR_BANK_LO 0x02
+#define __SW_BOOT_NOR_BANK_UP 0x5c /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */
+#define __SW_BOOT_NOR_BANK_LO 0x5e /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */
+#define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */
#define CONFIG_SYS_L2_SIZE (256 << 10)
#endif
@@ -52,6 +55,9 @@
#define __SW_NOR_BANK_MASK 0xfd
#define __SW_NOR_BANK_UP 0x00
#define __SW_NOR_BANK_LO 0x02
+#define __SW_BOOT_NOR_BANK_UP 0x64 /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */
+#define __SW_BOOT_NOR_BANK_LO 0x66 /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */
+#define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */
#define CONFIG_SYS_L2_SIZE (256 << 10)
/*
* Dynamic MTD Partition support with mtdparts
@@ -70,6 +76,9 @@
#define __SW_NOR_BANK_MASK 0xfd
#define __SW_NOR_BANK_UP 0x00
#define __SW_NOR_BANK_LO 0x02
+#define __SW_BOOT_NOR_BANK_UP 0xc8 /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */
+#define __SW_BOOT_NOR_BANK_LO 0xca /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */
+#define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */
#define CONFIG_SYS_L2_SIZE (512 << 10)
/*
* Dynamic MTD Partition support with mtdparts
@@ -80,7 +89,11 @@
#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_MMC_U_BOOT_DST CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MMC_U_BOOT_START CONFIG_SYS_TEXT_BASE
+#ifdef CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR
+#define CONFIG_SYS_MMC_U_BOOT_OFFS (CONFIG_SPL_PAD_TO - CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA*512)
+#else
#define CONFIG_SYS_MMC_U_BOOT_OFFS CONFIG_SPL_PAD_TO
+#endif
#elif defined(CONFIG_SPIFLASH)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST CONFIG_SYS_TEXT_BASE
@@ -465,10 +478,14 @@
MAP_NOR_LO_CMD(map_lowernorbank) \
MAP_NOR_UP_CMD(map_uppernorbank) \
RST_NOR_CMD(norboot) \
+RST_NOR_LO_CMD(norlowerboot) \
+RST_NOR_UP_CMD(norupperboot) \
RST_SPI_CMD(spiboot) \
RST_SD_CMD(sdboot) \
+RST_SD2_CMD(sd2boot) \
RST_NAND_CMD(nandboot) \
RST_PCIE_CMD(pciboot) \
+RST_DEF_CMD(defboot) \
""
#define CONFIG_USB_FAT_BOOT \
diff --git a/include/dt-bindings/clock/sifive-fu740-prci.h b/include/dt-bindings/clock/sifive-fu740-prci.h
index c122478..672bdad 100644
--- a/include/dt-bindings/clock/sifive-fu740-prci.h
+++ b/include/dt-bindings/clock/sifive-fu740-prci.h
@@ -1,10 +1,9 @@
-/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
- * Copyright (C) 2020-2021 SiFive, Inc.
+ * Copyright (C) 2019 SiFive, Inc.
* Wesley Terpstra
* Paul Walmsley
* Zong Li
- * Pragnesh Patel
*/
#ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H
@@ -12,14 +11,14 @@
/* Clock indexes for use by Device Tree data and the PRCI driver */
-#define PRCI_CLK_COREPLL 0
-#define PRCI_CLK_DDRPLL 1
-#define PRCI_CLK_GEMGXLPLL 2
-#define PRCI_CLK_DVFSCOREPLL 3
-#define PRCI_CLK_HFPCLKPLL 4
-#define PRCI_CLK_CLTXPLL 5
-#define PRCI_CLK_TLCLK 6
-#define PRCI_CLK_PCLK 7
-#define PRCI_CLK_PCIEAUX 8
+#define FU740_PRCI_CLK_COREPLL 0
+#define FU740_PRCI_CLK_DDRPLL 1
+#define FU740_PRCI_CLK_GEMGXLPLL 2
+#define FU740_PRCI_CLK_DVFSCOREPLL 3
+#define FU740_PRCI_CLK_HFPCLKPLL 4
+#define FU740_PRCI_CLK_CLTXPLL 5
+#define FU740_PRCI_CLK_TLCLK 6
+#define FU740_PRCI_CLK_PCLK 7
+#define FU740_PRCI_CLK_PCIE_AUX 8
-#endif
+#endif /* __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H */
diff --git a/include/image.h b/include/image.h
index e4c6a50..d7d756c 100644
--- a/include/image.h
+++ b/include/image.h
@@ -1014,6 +1014,76 @@
int fit_image_get_data_and_size(const void *fit, int noffset,
const void **data, size_t *size);
+/**
+ * fit_get_data_node() - Get verified image data for an image
+ * @fit: Pointer to the FIT format image header
+ * @image_uname: The name of the image node
+ * @data: A pointer which will be filled with the location of the image data
+ * @size: A pointer which will be filled with the size of the image data
+ *
+ * This function looks up the location and size of an image specified by its
+ * name. For example, if you had a FIT like::
+ *
+ * images {
+ * my-firmware {
+ * ...
+ * };
+ * };
+ *
+ * Then you could look up the data location and size of the my-firmware image
+ * by calling this function with @image_uname set to "my-firmware". This
+ * function also verifies the image data (if enabled) before returning. The
+ * image description is printed out on success. @data and @size will not be
+ * modified on faulure.
+ *
+ * Return:
+ * * 0 on success
+ * * -EINVAL if the image could not be verified
+ * * -ENOENT if there was a problem getting the data/size
+ * * Another negative error if there was a problem looking up the image node.
+ */
+int fit_get_data_node(const void *fit, const char *image_uname,
+ const void **data, size_t *size);
+
+/**
+ * fit_get_data_conf_prop() - Get verified image data for a property in /conf
+ * @fit: Pointer to the FIT format image header
+ * @prop_name: The name of the property in /conf referencing the image
+ * @data: A pointer which will be filled with the location of the image data
+ * @size: A pointer which will be filled with the size of the image data
+ *
+ * This function looks up the location and size of an image specified by a
+ * property in /conf. For example, if you had a FIT like::
+ *
+ * images {
+ * my-firmware {
+ * ...
+ * };
+ * };
+ *
+ * configurations {
+ * default = "conf-1";
+ * conf-1 {
+ * some-firmware = "my-firmware";
+ * };
+ * };
+ *
+ * Then you could look up the data location and size of the my-firmware image
+ * by calling this function with @prop_name set to "some-firmware". This
+ * function also verifies the image data (if enabled) before returning. The
+ * image description is printed out on success. @data and @size will not be
+ * modified on faulure.
+ *
+ * Return:
+ * * 0 on success
+ * * -EINVAL if the image could not be verified
+ * * -ENOENT if there was a problem getting the data/size
+ * * Another negative error if there was a problem looking up the configuration
+ * or image node.
+ */
+int fit_get_data_conf_prop(const void *fit, const char *prop_name,
+ const void **data, size_t *size);
+
int fit_image_hash_get_algo(const void *fit, int noffset, const char **algo);
int fit_image_hash_get_value(const void *fit, int noffset, uint8_t **value,
int *value_len);
diff --git a/tools/binman/bintool.py b/tools/binman/bintool.py
index ec30cef..032179a 100644
--- a/tools/binman/bintool.py
+++ b/tools/binman/bintool.py
@@ -53,9 +53,11 @@
# List of bintools to regard as missing
missing_list = []
- def __init__(self, name, desc):
+ def __init__(self, name, desc, version_regex=None, version_args='-V'):
self.name = name
self.desc = desc
+ self.version_regex = version_regex
+ self.version_args = version_args
@staticmethod
def find_bintool_class(btype):
@@ -464,16 +466,27 @@
print(f"No method to fetch bintool '{self.name}'")
return False
- # pylint: disable=R0201
def version(self):
"""Version handler for a bintool
- This should be implemented by the base class
-
Returns:
str: Version string for this bintool
"""
- return 'unknown'
+ if self.version_regex is None:
+ return 'unknown'
+
+ import re
+
+ result = self.run_cmd_result(self.version_args)
+ out = result.stdout.strip()
+ if not out:
+ out = result.stderr.strip()
+ if not out:
+ return 'unknown'
+
+ m_version = re.search(self.version_regex, out)
+ return m_version.group(1) if m_version else out
+
class BintoolPacker(Bintool):
"""Tool which compression / decompression entry contents
@@ -495,9 +508,9 @@
"""
def __init__(self, name, compression=None, compress_args=None,
decompress_args=None, fetch_package=None,
- version_regex=r'(v[0-9.]+)'):
+ version_regex=r'(v[0-9.]+)', version_args='-V'):
desc = '%s compression' % (compression if compression else name)
- super().__init__(name, desc)
+ super().__init__(name, desc, version_regex, version_args)
if compress_args is None:
compress_args = ['--compress']
self.compress_args = compress_args
@@ -507,7 +520,6 @@
if fetch_package is None:
fetch_package = name
self.fetch_package = fetch_package
- self.version_regex = version_regex
def compress(self, indata):
"""Compress data
@@ -557,21 +569,3 @@
if method != FETCH_BIN:
return None
return self.apt_install(self.fetch_package)
-
- def version(self):
- """Version handler
-
- Returns:
- str: Version number
- """
- import re
-
- result = self.run_cmd_result('-V')
- out = result.stdout.strip()
- if not out:
- out = result.stderr.strip()
- if not out:
- return super().version()
-
- m_version = re.search(self.version_regex, out)
- return m_version.group(1) if m_version else out
diff --git a/tools/binman/btool/btool_gzip.py b/tools/binman/btool/btool_gzip.py
index 7bea300..70cbc19 100644
--- a/tools/binman/btool/btool_gzip.py
+++ b/tools/binman/btool/btool_gzip.py
@@ -27,5 +27,5 @@
man gzip
"""
def __init__(self, name):
- super().__init__(name, compress_args=[],
+ super().__init__("gzip", compress_args=[],
version_regex=r'gzip ([0-9.]+)')
diff --git a/tools/binman/btool/bzip2.py b/tools/binman/btool/bzip2.py
index 9be87a6..c3897d6 100644
--- a/tools/binman/btool/bzip2.py
+++ b/tools/binman/btool/bzip2.py
@@ -27,4 +27,4 @@
man bzip2
"""
def __init__(self, name):
- super().__init__(name, version_regex=r'bzip2.*Version ([0-9.]+)')
+ super().__init__(name, version_regex=r'bzip2.*Version ([0-9.]+)', version_args='--help')
diff --git a/tools/binman/btool/fiptool.py b/tools/binman/btool/fiptool.py
index c6d71ce..c80f827 100644
--- a/tools/binman/btool/fiptool.py
+++ b/tools/binman/btool/fiptool.py
@@ -49,7 +49,7 @@
https://trustedfirmware-a.readthedocs.io/en/latest/getting_started/tools-build.html?highlight=fiptool#building-and-using-the-fip-tool
"""
def __init__(self, name):
- super().__init__(name, 'Manipulate ATF FIP files')
+ super().__init__(name, 'Manipulate ATF FIP files', r'^(.*)$', 'version')
def info(self, fname):
"""Get info on a FIP image
@@ -112,12 +112,3 @@
'fiptool',
'tools/fiptool/fiptool')
return result
-
- def version(self):
- """Version handler for fiptool
-
- Returns:
- str: Version number of fiptool
- """
- out = self.run_cmd('version').strip()
- return out or super().version()
diff --git a/tools/binman/btool/futility.py b/tools/binman/btool/futility.py
index 8d00966..75a05c2 100644
--- a/tools/binman/btool/futility.py
+++ b/tools/binman/btool/futility.py
@@ -69,7 +69,7 @@
https://chromium.googlesource.com/chromiumos/platform/vboot/+/refs/heads/main/_vboot_reference/README
"""
def __init__(self, name):
- super().__init__(name, 'Chromium OS firmware utility')
+ super().__init__(name, 'Chromium OS firmware utility', r'^(.*)$', 'version')
def gbb_create(self, fname, sizes):
"""Create a new Google Binary Block
@@ -165,14 +165,3 @@
fname, tmpdir = self.fetch_from_drive(
'1hdsInzsE4aJbmBeJ663kYgjOQyW1I-E0')
return fname, tmpdir
-
- def version(self):
- """Version handler for futility
-
- Returns:
- str: Version string for futility
- """
- out = self.run_cmd('version').strip()
- if not out:
- return super().version()
- return out
diff --git a/tools/binman/btool/lz4.py b/tools/binman/btool/lz4.py
index f09c5c8..dc9e379 100644
--- a/tools/binman/btool/lz4.py
+++ b/tools/binman/btool/lz4.py
@@ -76,7 +76,7 @@
man lz4
"""
def __init__(self, name):
- super().__init__(name, 'lz4 compression')
+ super().__init__(name, 'lz4 compression', r'.* (v[0-9.]*),.*')
def compress(self, indata):
"""Compress data with lz4
@@ -126,15 +126,3 @@
if method != bintool.FETCH_BIN:
return None
return self.apt_install('lz4')
-
- def version(self):
- """Version handler
-
- Returns:
- str: Version number of lz4
- """
- out = self.run_cmd('-V').strip()
- if not out:
- return super().version()
- m_version = re.match(r'.* (v[0-9.]*),.*', out)
- return m_version.group(1) if m_version else out
diff --git a/tools/binman/btool/mkimage.py b/tools/binman/btool/mkimage.py
index c85bfe0..da5f344 100644
--- a/tools/binman/btool/mkimage.py
+++ b/tools/binman/btool/mkimage.py
@@ -18,11 +18,11 @@
Support is provided for fetching this on Debian-like systems, using apt.
"""
def __init__(self, name):
- super().__init__(name, 'Generate image for U-Boot')
+ super().__init__(name, 'Generate image for U-Boot', r'mkimage version (.*)')
# pylint: disable=R0913
def run(self, reset_timestamp=False, output_fname=None, external=False,
- pad=None, version=False):
+ pad=None):
"""Run mkimage
Args:
@@ -44,8 +44,6 @@
args.append('-t')
if output_fname:
args += ['-F', output_fname]
- if version:
- args.append('-V')
return self.run_cmd(*args)
def fetch(self, method):
@@ -66,15 +64,3 @@
if method != bintool.FETCH_BIN:
return None
return self.apt_install('u-boot-tools')
-
- def version(self):
- """Version handler for mkimage
-
- Returns:
- str: Version string for mkimage
- """
- out = self.run(version=True).strip()
- if not out:
- return super().version()
- m_version = re.match(r'mkimage version (.*)', out)
- return m_version.group(1) if m_version else out