tsec: arrange the code to avoid useless function declaration
This is merely a rearrangement. No changes to the code, except
to remove now-useless declarations.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Detlev Zundel <dzu@denx.de>
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index a2705e1..a3857b3 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -44,31 +44,6 @@
#error "rtx must be 64-bit aligned"
#endif
-static int tsec_send(struct eth_device *dev,
- volatile void *packet, int length);
-static int tsec_recv(struct eth_device *dev);
-static int tsec_init(struct eth_device *dev, bd_t * bd);
-static int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info);
-static void tsec_halt(struct eth_device *dev);
-static void init_registers(tsec_t *regs);
-static void startup_tsec(struct eth_device *dev);
-static int init_phy(struct eth_device *dev);
-void write_phy_reg(struct tsec_private *priv, uint regnum, uint value);
-uint read_phy_reg(struct tsec_private *priv, uint regnum);
-static struct phy_info *get_phy_info(struct eth_device *dev);
-static void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd);
-static void adjust_link(struct eth_device *dev);
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
- && !defined(BITBANGMII)
-static int tsec_miiphy_write(const char *devname, unsigned char addr,
- unsigned char reg, unsigned short value);
-static int tsec_miiphy_read(const char *devname, unsigned char addr,
- unsigned char reg, unsigned short *value);
-#endif
-#ifdef CONFIG_MCAST_TFTP
-static int tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set);
-#endif
-
/* Default initializations for TSEC controllers. */
static struct tsec_info_struct tsec_info[] = {
@@ -95,140 +70,6 @@
#endif
};
-/*
- * Initialize all the TSEC devices
- *
- * Returns the number of TSEC devices that were initialized
- */
-int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
-{
- int i;
- int ret, count = 0;
-
- for (i = 0; i < num; i++) {
- ret = tsec_initialize(bis, &tsecs[i]);
- if (ret > 0)
- count += ret;
- }
-
- return count;
-}
-
-int tsec_standard_init(bd_t *bis)
-{
- return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
-}
-
-/* Initialize device structure. Returns success if PHY
- * initialization succeeded (i.e. if it recognizes the PHY)
- */
-static int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info)
-{
- struct eth_device *dev;
- int i;
- struct tsec_private *priv;
-
- dev = (struct eth_device *)malloc(sizeof *dev);
-
- if (NULL == dev)
- return 0;
-
- memset(dev, 0, sizeof *dev);
-
- priv = (struct tsec_private *)malloc(sizeof(*priv));
-
- if (NULL == priv)
- return 0;
-
- privlist[num_tsecs++] = priv;
- priv->regs = tsec_info->regs;
- priv->phyregs = tsec_info->miiregs;
- priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
-
- priv->phyaddr = tsec_info->phyaddr;
- priv->flags = tsec_info->flags;
-
- sprintf(dev->name, tsec_info->devname);
- dev->iobase = 0;
- dev->priv = priv;
- dev->init = tsec_init;
- dev->halt = tsec_halt;
- dev->send = tsec_send;
- dev->recv = tsec_recv;
-#ifdef CONFIG_MCAST_TFTP
- dev->mcast = tsec_mcast_addr;
-#endif
-
- /* Tell u-boot to get the addr from the env */
- for (i = 0; i < 6; i++)
- dev->enetaddr[i] = 0;
-
- eth_register(dev);
-
- /* Reset the MAC */
- setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
- udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
- clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
- && !defined(BITBANGMII)
- miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write);
-#endif
-
- /* Try to initialize PHY here, and return */
- return init_phy(dev);
-}
-
-/* Initializes data structures and registers for the controller,
- * and brings the interface up. Returns the link status, meaning
- * that it returns success if the link is up, failure otherwise.
- * This allows u-boot to find the first active controller.
- */
-static int tsec_init(struct eth_device *dev, bd_t * bd)
-{
- uint tempval;
- char tmpbuf[MAC_ADDR_LEN];
- int i;
- struct tsec_private *priv = (struct tsec_private *)dev->priv;
- tsec_t *regs = priv->regs;
-
- /* Make sure the controller is stopped */
- tsec_halt(dev);
-
- /* Init MACCFG2. Defaults to GMII */
- out_be32(®s->maccfg2, MACCFG2_INIT_SETTINGS);
-
- /* Init ECNTRL */
- out_be32(®s->ecntrl, ECNTRL_INIT_SETTINGS);
-
- /* Copy the station address into the address registers.
- * Backwards, because little endian MACS are dumb */
- for (i = 0; i < MAC_ADDR_LEN; i++) {
- tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
- }
- tempval = (tmpbuf[0] << 24) | (tmpbuf[1] << 16) | (tmpbuf[2] << 8) |
- tmpbuf[3];
-
- out_be32(®s->macstnaddr1, tempval);
-
- tempval = *((uint *) (tmpbuf + 4));
-
- out_be32(®s->macstnaddr2, tempval);
-
- /* reset the indices to zero */
- rxIdx = 0;
- txIdx = 0;
-
- /* Clear out (for the most part) the other registers */
- init_registers(regs);
-
- /* Ready the device for tx/rx */
- startup_tsec(dev);
-
- /* If there's no link, fail */
- return (priv->link ? 0 : -1);
-}
-
/* Writes the given phy's reg with value, using the specified MDIO regs */
static void tsec_local_mdio_write(tsec_mdio_t *phyregs, uint addr,
uint reg, uint value)
@@ -243,7 +84,6 @@
;
}
-
/* Provide the default behavior of writing the PHY of this ethernet device */
#define write_phy_reg(priv, regnum, value) \
tsec_local_mdio_write(priv->phyregs,priv->phyaddr,regnum,value)
@@ -311,46 +151,6 @@
CONFIG_TSEC_TBICR_SETTINGS);
}
-/* Discover which PHY is attached to the device, and configure it
- * properly. If the PHY is not recognized, then return 0
- * (failure). Otherwise, return 1
- */
-static int init_phy(struct eth_device *dev)
-{
- struct tsec_private *priv = (struct tsec_private *)dev->priv;
- struct phy_info *curphy;
- tsec_t *regs = priv->regs;
-
- /* Assign a Physical address to the TBI */
- out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE);
-
- /* Reset MII (due to new addresses) */
- out_be32(&priv->phyregs->miimcfg, MIIMCFG_RESET);
- out_be32(&priv->phyregs->miimcfg, MIIMCFG_INIT_VALUE);
- while (in_be32(&priv->phyregs->miimind) & MIIMIND_BUSY)
- ;
-
- /* Get the cmd structure corresponding to the attached
- * PHY */
- curphy = get_phy_info(dev);
-
- if (curphy == NULL) {
- priv->phyinfo = NULL;
- printf("%s: No PHY found\n", dev->name);
-
- return 0;
- }
-
- if (in_be32(®s->ecntrl) & ECNTRL_SGMII_MODE)
- tsec_configure_serdes(priv);
-
- priv->phyinfo = curphy;
-
- phy_run_commands(priv, priv->phyinfo->config);
-
- return 1;
-}
-
/*
* Returns which value to write to the control register.
* For 10/100, the value is slightly different
@@ -866,344 +666,104 @@
return mii_data;
}
-/* Initialized required registers to appropriate values, zeroing
- * those we don't care about (unless zero is bad, in which case,
- * choose a more appropriate value)
- */
-static void init_registers(tsec_t *regs)
-{
- /* Clear IEVENT */
- out_be32(®s->ievent, IEVENT_INIT_CLEAR);
-
- out_be32(®s->imask, IMASK_INIT_CLEAR);
+static struct phy_info phy_info_M88E1149S = {
+ 0x1410ca,
+ "Marvell 88E1149S",
+ 4,
+ (struct phy_cmd[]) { /* config */
+ /* Reset and configure the PHY */
+ {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
+ {0x1d, 0x1f, NULL},
+ {0x1e, 0x200c, NULL},
+ {0x1d, 0x5, NULL},
+ {0x1e, 0x0, NULL},
+ {0x1e, 0x100, NULL},
+ {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
+ {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
+ {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
+ {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
+ {miim_end,}
+ },
+ (struct phy_cmd[]) { /* startup */
+ /* Status is read once to clear old link state */
+ {MIIM_STATUS, miim_read, NULL},
+ /* Auto-negotiate */
+ {MIIM_STATUS, miim_read, &mii_parse_sr},
+ /* Read the status */
+ {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
+ {miim_end,}
+ },
+ (struct phy_cmd[]) { /* shutdown */
+ {miim_end,}
+ },
+};
- out_be32(®s->hash.iaddr0, 0);
- out_be32(®s->hash.iaddr1, 0);
- out_be32(®s->hash.iaddr2, 0);
- out_be32(®s->hash.iaddr3, 0);
- out_be32(®s->hash.iaddr4, 0);
- out_be32(®s->hash.iaddr5, 0);
- out_be32(®s->hash.iaddr6, 0);
- out_be32(®s->hash.iaddr7, 0);
+/* The 5411 id is 0x206070, the 5421 is 0x2060e0 */
+static struct phy_info phy_info_BCM5461S = {
+ 0x02060c1, /* 5461 ID */
+ "Broadcom BCM5461S",
+ 0, /* not clear to me what minor revisions we can shift away */
+ (struct phy_cmd[]) { /* config */
+ /* Reset and configure the PHY */
+ {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
+ {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
+ {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
+ {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
+ {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
+ {miim_end,}
+ },
+ (struct phy_cmd[]) { /* startup */
+ /* Status is read once to clear old link state */
+ {MIIM_STATUS, miim_read, NULL},
+ /* Auto-negotiate */
+ {MIIM_STATUS, miim_read, &mii_parse_sr},
+ /* Read the status */
+ {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
+ {miim_end,}
+ },
+ (struct phy_cmd[]) { /* shutdown */
+ {miim_end,}
+ },
+};
- out_be32(®s->hash.gaddr0, 0);
- out_be32(®s->hash.gaddr1, 0);
- out_be32(®s->hash.gaddr2, 0);
- out_be32(®s->hash.gaddr3, 0);
- out_be32(®s->hash.gaddr4, 0);
- out_be32(®s->hash.gaddr5, 0);
- out_be32(®s->hash.gaddr6, 0);
- out_be32(®s->hash.gaddr7, 0);
-
- out_be32(®s->rctrl, 0x00000000);
-
- /* Init RMON mib registers */
- memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
-
- out_be32(®s->rmon.cam1, 0xffffffff);
- out_be32(®s->rmon.cam2, 0xffffffff);
-
- out_be32(®s->mrblr, MRBLR_INIT_SETTINGS);
-
- out_be32(®s->minflr, MINFLR_INIT_SETTINGS);
-
- out_be32(®s->attr, ATTR_INIT_SETTINGS);
- out_be32(®s->attreli, ATTRELI_INIT_SETTINGS);
-
-}
-
-/* Configure maccfg2 based on negotiated speed and duplex
- * reported by PHY handling code
- */
-static void adjust_link(struct eth_device *dev)
-{
- struct tsec_private *priv = (struct tsec_private *)dev->priv;
- tsec_t *regs = priv->regs;
- u32 ecntrl, maccfg2;
-
- if (!priv->link) {
- printf("%s: No link.\n", dev->name);
- return;
- }
-
- /* clear all bits relative with interface mode */
- ecntrl = in_be32(®s->ecntrl);
- ecntrl &= ~ECNTRL_R100;
-
- maccfg2 = in_be32(®s->maccfg2);
- maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX);
-
- if (priv->duplexity)
- maccfg2 |= MACCFG2_FULL_DUPLEX;
-
- switch (priv->speed) {
- case 1000:
- maccfg2 |= MACCFG2_GMII;
- break;
- case 100:
- case 10:
- maccfg2 |= MACCFG2_MII;
-
- /* Set R100 bit in all modes although
- * it is only used in RGMII mode
- */
- if (priv->speed == 100)
- ecntrl |= ECNTRL_R100;
- break;
- default:
- printf("%s: Speed was bad\n", dev->name);
- break;
- }
-
- out_be32(®s->ecntrl, ecntrl);
- out_be32(®s->maccfg2, maccfg2);
-
- printf("Speed: %d, %s duplex%s\n", priv->speed,
- (priv->duplexity) ? "full" : "half",
- (priv->flags & TSEC_FIBER) ? ", fiber mode" : "");
-}
-
-/* Set up the buffers and their descriptors, and bring up the
- * interface
- */
-static void startup_tsec(struct eth_device *dev)
-{
- int i;
- struct tsec_private *priv = (struct tsec_private *)dev->priv;
- tsec_t *regs = priv->regs;
-
- /* Point to the buffer descriptors */
- out_be32(®s->tbase, (unsigned int)(&rtx.txbd[txIdx]));
- out_be32(®s->rbase, (unsigned int)(&rtx.rxbd[rxIdx]));
-
- /* Initialize the Rx Buffer descriptors */
- for (i = 0; i < PKTBUFSRX; i++) {
- rtx.rxbd[i].status = RXBD_EMPTY;
- rtx.rxbd[i].length = 0;
- rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i];
- }
- rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP;
-
- /* Initialize the TX Buffer Descriptors */
- for (i = 0; i < TX_BUF_CNT; i++) {
- rtx.txbd[i].status = 0;
- rtx.txbd[i].length = 0;
- rtx.txbd[i].bufPtr = 0;
- }
- rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP;
-
- /* Start up the PHY */
- if(priv->phyinfo)
- phy_run_commands(priv, priv->phyinfo->startup);
-
- adjust_link(dev);
-
- /* Enable Transmit and Receive */
- setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
-
- /* Tell the DMA it is clear to go */
- setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS);
- out_be32(®s->tstat, TSTAT_CLEAR_THALT);
- out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
- clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
-}
-
-/* This returns the status bits of the device. The return value
- * is never checked, and this is what the 8260 driver did, so we
- * do the same. Presumably, this would be zero if there were no
- * errors
- */
-static int tsec_send(struct eth_device *dev, volatile void *packet, int length)
-{
- int i;
- int result = 0;
- struct tsec_private *priv = (struct tsec_private *)dev->priv;
- tsec_t *regs = priv->regs;
-
- /* Find an empty buffer descriptor */
- for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
- if (i >= TOUT_LOOP) {
- debug("%s: tsec: tx buffers full\n", dev->name);
- return result;
- }
- }
-
- rtx.txbd[txIdx].bufPtr = (uint) packet;
- rtx.txbd[txIdx].length = length;
- rtx.txbd[txIdx].status |=
- (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
-
- /* Tell the DMA to go */
- out_be32(®s->tstat, TSTAT_CLEAR_THALT);
-
- /* Wait for buffer to be transmitted */
- for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
- if (i >= TOUT_LOOP) {
- debug("%s: tsec: tx error\n", dev->name);
- return result;
- }
- }
-
- txIdx = (txIdx + 1) % TX_BUF_CNT;
- result = rtx.txbd[txIdx].status & TXBD_STATS;
-
- return result;
-}
-
-static int tsec_recv(struct eth_device *dev)
-{
- int length;
- struct tsec_private *priv = (struct tsec_private *)dev->priv;
- tsec_t *regs = priv->regs;
-
- while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
-
- length = rtx.rxbd[rxIdx].length;
-
- /* Send the packet up if there were no errors */
- if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
- NetReceive(NetRxPackets[rxIdx], length - 4);
- } else {
- printf("Got error %x\n",
- (rtx.rxbd[rxIdx].status & RXBD_STATS));
- }
-
- rtx.rxbd[rxIdx].length = 0;
-
- /* Set the wrap bit if this is the last element in the list */
- rtx.rxbd[rxIdx].status =
- RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
-
- rxIdx = (rxIdx + 1) % PKTBUFSRX;
- }
-
- if (in_be32(®s->ievent) & IEVENT_BSY) {
- out_be32(®s->ievent, IEVENT_BSY);
- out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
- }
-
- return -1;
-
-}
-
-/* Stop the interface */
-static void tsec_halt(struct eth_device *dev)
-{
- struct tsec_private *priv = (struct tsec_private *)dev->priv;
- tsec_t *regs = priv->regs;
-
- clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
- setbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
-
- while ((in_be32(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
- != (IEVENT_GRSC | IEVENT_GTSC))
- ;
-
- clrbits_be32(®s->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
-
- /* Shut down the PHY, as needed */
- if(priv->phyinfo)
- phy_run_commands(priv, priv->phyinfo->shutdown);
-}
-
-static struct phy_info phy_info_M88E1149S = {
- 0x1410ca,
- "Marvell 88E1149S",
- 4,
- (struct phy_cmd[]) { /* config */
+static struct phy_info phy_info_BCM5464S = {
+ 0x02060b1, /* 5464 ID */
+ "Broadcom BCM5464S",
+ 0, /* not clear to me what minor revisions we can shift away */
+ (struct phy_cmd[]) { /* config */
/* Reset and configure the PHY */
{MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
- {0x1d, 0x1f, NULL},
- {0x1e, 0x200c, NULL},
- {0x1d, 0x5, NULL},
- {0x1e, 0x0, NULL},
- {0x1e, 0x100, NULL},
{MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
{MIIM_ANAR, MIIM_ANAR_INIT, NULL},
{MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
{MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
{miim_end,}
},
- (struct phy_cmd[]) { /* startup */
+ (struct phy_cmd[]) { /* startup */
/* Status is read once to clear old link state */
{MIIM_STATUS, miim_read, NULL},
/* Auto-negotiate */
{MIIM_STATUS, miim_read, &mii_parse_sr},
/* Read the status */
- {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
+ {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
{miim_end,}
},
- (struct phy_cmd[]) { /* shutdown */
+ (struct phy_cmd[]) { /* shutdown */
{miim_end,}
},
};
-/* The 5411 id is 0x206070, the 5421 is 0x2060e0 */
-static struct phy_info phy_info_BCM5461S = {
- 0x02060c1, /* 5461 ID */
- "Broadcom BCM5461S",
- 0, /* not clear to me what minor revisions we can shift away */
+static struct phy_info phy_info_BCM5482S = {
+ 0x0143bcb,
+ "Broadcom BCM5482S",
+ 4,
(struct phy_cmd[]) { /* config */
/* Reset and configure the PHY */
{MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
- {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
- {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
- {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
- {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup */
- /* Status is read once to clear old link state */
- {MIIM_STATUS, miim_read, NULL},
- /* Auto-negotiate */
- {MIIM_STATUS, miim_read, &mii_parse_sr},
- /* Read the status */
- {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown */
- {miim_end,}
- },
-};
-
-static struct phy_info phy_info_BCM5464S = {
- 0x02060b1, /* 5464 ID */
- "Broadcom BCM5464S",
- 0, /* not clear to me what minor revisions we can shift away */
- (struct phy_cmd[]) { /* config */
- /* Reset and configure the PHY */
- {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
- {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
- {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
- {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
- {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup */
- /* Status is read once to clear old link state */
- {MIIM_STATUS, miim_read, NULL},
- /* Auto-negotiate */
- {MIIM_STATUS, miim_read, &mii_parse_sr},
- /* Read the status */
- {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown */
- {miim_end,}
- },
-};
-
-static struct phy_info phy_info_BCM5482S = {
- 0x0143bcb,
- "Broadcom BCM5482S",
- 4,
- (struct phy_cmd[]) { /* config */
- /* Reset and configure the PHY */
- {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
- /* Setup read from auxilary control shadow register 7 */
- {MIIM_BCM54xx_AUXCNTL, MIIM_BCM54xx_AUXCNTL_ENCODE(7), NULL},
- /* Read Misc Control register and or in Ethernet@Wirespeed */
- {MIIM_BCM54xx_AUXCNTL, 0, &mii_BCM54xx_wirespeed},
+ /* Setup read from auxilary control shadow register 7 */
+ {MIIM_BCM54xx_AUXCNTL, MIIM_BCM54xx_AUXCNTL_ENCODE(7), NULL},
+ /* Read Misc Control register and or in Ethernet@Wirespeed */
+ {MIIM_BCM54xx_AUXCNTL, 0, &mii_BCM54xx_wirespeed},
{MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
/* Initial config/enable of secondary SerDes interface */
{MIIM_BCM54XX_SHD, MIIM_BCM54XX_SHD_WR_ENCODE(0x14, 0xf), NULL},
@@ -1711,317 +1271,732 @@
priv->duplexity = 0;
}
+ return 0;
+}
+
+static struct phy_info phy_info_lxt971 = {
+ 0x0001378e,
+ "LXT971",
+ 4,
+ (struct phy_cmd[]) { /* config */
+ {MIIM_CR, MIIM_CR_INIT, mii_cr_init}, /* autonegotiate */
+ {miim_end,}
+ },
+ (struct phy_cmd[]) { /* startup - enable interrupts */
+ /* { 0x12, 0x00f2, NULL }, */
+ {MIIM_STATUS, miim_read, NULL},
+ {MIIM_STATUS, miim_read, &mii_parse_sr},
+ {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2},
+ {miim_end,}
+ },
+ (struct phy_cmd[]) { /* shutdown - disable interrupts */
+ {miim_end,}
+ },
+};
+
+/* Parse the DP83865's link and auto-neg status register for speed and duplex
+ * information
+ */
+static uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv)
+{
+ switch (mii_reg & MIIM_DP83865_SPD_MASK) {
+
+ case MIIM_DP83865_SPD_1000:
+ priv->speed = 1000;
+ break;
+
+ case MIIM_DP83865_SPD_100:
+ priv->speed = 100;
+ break;
+
+ default:
+ priv->speed = 10;
+ break;
+
+ }
+
+ if (mii_reg & MIIM_DP83865_DPX_FULL)
+ priv->duplexity = 1;
+ else
+ priv->duplexity = 0;
+
+ return 0;
+}
+
+static struct phy_info phy_info_dp83865 = {
+ 0x20005c7,
+ "NatSemi DP83865",
+ 4,
+ (struct phy_cmd[]) { /* config */
+ {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL},
+ {miim_end,}
+ },
+ (struct phy_cmd[]) { /* startup */
+ /* Status is read once to clear old link state */
+ {MIIM_STATUS, miim_read, NULL},
+ /* Auto-negotiate */
+ {MIIM_STATUS, miim_read, &mii_parse_sr},
+ /* Read the link and auto-neg status */
+ {MIIM_DP83865_LANR, miim_read, &mii_parse_dp83865_lanr},
+ {miim_end,}
+ },
+ (struct phy_cmd[]) { /* shutdown */
+ {miim_end,}
+ },
+};
+
+static struct phy_info phy_info_rtl8211b = {
+ 0x001cc91,
+ "RealTek RTL8211B",
+ 4,
+ (struct phy_cmd[]) { /* config */
+ /* Reset and configure the PHY */
+ {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
+ {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
+ {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
+ {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
+ {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
+ {miim_end,}
+ },
+ (struct phy_cmd[]) { /* startup */
+ /* Status is read once to clear old link state */
+ {MIIM_STATUS, miim_read, NULL},
+ /* Auto-negotiate */
+ {MIIM_STATUS, miim_read, &mii_parse_sr},
+ /* Read the status */
+ {MIIM_RTL8211B_PHY_STATUS, miim_read, &mii_parse_RTL8211B_sr},
+ {miim_end,}
+ },
+ (struct phy_cmd[]) { /* shutdown */
+ {miim_end,}
+ },
+};
+
+struct phy_info phy_info_AR8021 = {
+ 0x4dd04,
+ "AR8021",
+ 4,
+ (struct phy_cmd[]) { /* config */
+ {MII_BMCR, BMCR_RESET, NULL},
+ {MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART, NULL},
+ {0x1d, 0x05, NULL},
+ {0x1e, 0x3D47, NULL},
+ {miim_end,}
+ },
+ (struct phy_cmd[]) { /* startup */
+ {MII_BMSR, miim_read, NULL},
+ {MII_BMSR, miim_read, &mii_parse_sr},
+ {MII_BMSR, miim_read, &mii_parse_link},
+ {miim_end,}
+ },
+ (struct phy_cmd[]) { /* shutdown */
+ {miim_end,}
+ }
+};
+
+static struct phy_info *phy_info[] = {
+ &phy_info_cis8204,
+ &phy_info_cis8201,
+ &phy_info_BCM5461S,
+ &phy_info_BCM5464S,
+ &phy_info_BCM5482S,
+ &phy_info_M88E1011S,
+ &phy_info_M88E1111S,
+ &phy_info_M88E1118,
+ &phy_info_M88E1121R,
+ &phy_info_M88E1145,
+ &phy_info_M88E1149S,
+ &phy_info_dm9161,
+ &phy_info_ksz804,
+ &phy_info_lxt971,
+ &phy_info_VSC8211,
+ &phy_info_VSC8244,
+ &phy_info_VSC8601,
+ &phy_info_VSC8641,
+ &phy_info_VSC8221,
+ &phy_info_dp83865,
+ &phy_info_rtl8211b,
+ &phy_info_AR8021,
+ &phy_info_generic, /* must be last; has ID 0 and 32 bit mask */
+ NULL
+};
+
+/* Grab the identifier of the device's PHY, and search through
+ * all of the known PHYs to see if one matches. If so, return
+ * it, if not, return NULL
+ */
+static struct phy_info *get_phy_info(struct eth_device *dev)
+{
+ struct tsec_private *priv = (struct tsec_private *)dev->priv;
+ uint phy_reg, phy_ID;
+ int i;
+ struct phy_info *theInfo = NULL;
+
+ /* Grab the bits from PHYIR1, and put them in the upper half */
+ phy_reg = read_phy_reg(priv, MIIM_PHYIR1);
+ phy_ID = (phy_reg & 0xffff) << 16;
+
+ /* Grab the bits from PHYIR2, and put them in the lower half */
+ phy_reg = read_phy_reg(priv, MIIM_PHYIR2);
+ phy_ID |= (phy_reg & 0xffff);
+
+ /* loop through all the known PHY types, and find one that */
+ /* matches the ID we read from the PHY. */
+ for (i = 0; phy_info[i]; i++) {
+ if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) {
+ theInfo = phy_info[i];
+ break;
+ }
+ }
+
+ if (theInfo == &phy_info_generic) {
+ printf("%s: No support for PHY id %x; assuming generic\n",
+ dev->name, phy_ID);
+ } else {
+ debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID);
+ }
+
+ return theInfo;
+}
+
+/* Execute the given series of commands on the given device's
+ * PHY, running functions as necessary
+ */
+static void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd)
+{
+ int i;
+ uint result;
+ tsec_mdio_t *phyregs = priv->phyregs;
+
+ out_be32(&phyregs->miimcfg, MIIMCFG_RESET);
+
+ out_be32(&phyregs->miimcfg, MIIMCFG_INIT_VALUE);
+
+ while (in_be32(&phyregs->miimind) & MIIMIND_BUSY)
+ ;
+
+ for (i = 0; cmd->mii_reg != miim_end; i++) {
+ if (cmd->mii_data == miim_read) {
+ result = read_phy_reg(priv, cmd->mii_reg);
+
+ if (cmd->funct != NULL)
+ (*(cmd->funct)) (result, priv);
+
+ } else {
+ if (cmd->funct != NULL)
+ result = (*(cmd->funct)) (cmd->mii_reg, priv);
+ else
+ result = cmd->mii_data;
+
+ write_phy_reg(priv, cmd->mii_reg, result);
+
+ }
+ cmd++;
+ }
+}
+
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
+ && !defined(BITBANGMII)
+
+/*
+ * Read a MII PHY register.
+ *
+ * Returns:
+ * 0 on success
+ */
+static int tsec_miiphy_read(const char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value)
+{
+ unsigned short ret;
+ struct tsec_private *priv = privlist[0];
+
+ if (NULL == priv) {
+ printf("Can't read PHY at address %d\n", addr);
+ return -1;
+ }
+
+ ret = (unsigned short)tsec_local_mdio_read(priv->phyregs, addr, reg);
+ *value = ret;
+
+ return 0;
+}
+
+/*
+ * Write a MII PHY register.
+ *
+ * Returns:
+ * 0 on success
+ */
+static int tsec_miiphy_write(const char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value)
+{
+ struct tsec_private *priv = privlist[0];
+
+ if (NULL == priv) {
+ printf("Can't write PHY at address %d\n", addr);
+ return -1;
+ }
+
+ tsec_local_mdio_write(priv->phyregs, addr, reg, value);
+
+ return 0;
+}
+
+#endif
+
+#ifdef CONFIG_MCAST_TFTP
+
+/* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
+
+/* Set the appropriate hash bit for the given addr */
+
+/* The algorithm works like so:
+ * 1) Take the Destination Address (ie the multicast address), and
+ * do a CRC on it (little endian), and reverse the bits of the
+ * result.
+ * 2) Use the 8 most significant bits as a hash into a 256-entry
+ * table. The table is controlled through 8 32-bit registers:
+ * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
+ * gaddr7. This means that the 3 most significant bits in the
+ * hash index which gaddr register to use, and the 5 other bits
+ * indicate which bit (assuming an IBM numbering scheme, which
+ * for PowerPC (tm) is usually the case) in the tregister holds
+ * the entry. */
+static int
+tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set)
+{
+ struct tsec_private *priv = privlist[1];
+ volatile tsec_t *regs = priv->regs;
+ volatile u32 *reg_array, value;
+ u8 result, whichbit, whichreg;
+
+ result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff);
+ whichbit = result & 0x1f; /* the 5 LSB = which bit to set */
+ whichreg = result >> 5; /* the 3 MSB = which reg to set it in */
+ value = (1 << (31-whichbit));
+
+ reg_array = &(regs->hash.gaddr0);
+
+ if (set) {
+ reg_array[whichreg] |= value;
+ } else {
+ reg_array[whichreg] &= ~value;
+ }
+ return 0;
+}
+#endif /* Multicast TFTP ? */
+
+/* Initialized required registers to appropriate values, zeroing
+ * those we don't care about (unless zero is bad, in which case,
+ * choose a more appropriate value)
+ */
+static void init_registers(tsec_t *regs)
+{
+ /* Clear IEVENT */
+ out_be32(®s->ievent, IEVENT_INIT_CLEAR);
+
+ out_be32(®s->imask, IMASK_INIT_CLEAR);
+
+ out_be32(®s->hash.iaddr0, 0);
+ out_be32(®s->hash.iaddr1, 0);
+ out_be32(®s->hash.iaddr2, 0);
+ out_be32(®s->hash.iaddr3, 0);
+ out_be32(®s->hash.iaddr4, 0);
+ out_be32(®s->hash.iaddr5, 0);
+ out_be32(®s->hash.iaddr6, 0);
+ out_be32(®s->hash.iaddr7, 0);
+
+ out_be32(®s->hash.gaddr0, 0);
+ out_be32(®s->hash.gaddr1, 0);
+ out_be32(®s->hash.gaddr2, 0);
+ out_be32(®s->hash.gaddr3, 0);
+ out_be32(®s->hash.gaddr4, 0);
+ out_be32(®s->hash.gaddr5, 0);
+ out_be32(®s->hash.gaddr6, 0);
+ out_be32(®s->hash.gaddr7, 0);
+
+ out_be32(®s->rctrl, 0x00000000);
+
+ /* Init RMON mib registers */
+ memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
+
+ out_be32(®s->rmon.cam1, 0xffffffff);
+ out_be32(®s->rmon.cam2, 0xffffffff);
+
+ out_be32(®s->mrblr, MRBLR_INIT_SETTINGS);
+
+ out_be32(®s->minflr, MINFLR_INIT_SETTINGS);
+
+ out_be32(®s->attr, ATTR_INIT_SETTINGS);
+ out_be32(®s->attreli, ATTRELI_INIT_SETTINGS);
+
+}
+
+/* Configure maccfg2 based on negotiated speed and duplex
+ * reported by PHY handling code
+ */
+static void adjust_link(struct eth_device *dev)
+{
+ struct tsec_private *priv = (struct tsec_private *)dev->priv;
+ tsec_t *regs = priv->regs;
+ u32 ecntrl, maccfg2;
+
+ if (!priv->link) {
+ printf("%s: No link.\n", dev->name);
+ return;
+ }
+
+ /* clear all bits relative with interface mode */
+ ecntrl = in_be32(®s->ecntrl);
+ ecntrl &= ~ECNTRL_R100;
+
+ maccfg2 = in_be32(®s->maccfg2);
+ maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX);
+
+ if (priv->duplexity)
+ maccfg2 |= MACCFG2_FULL_DUPLEX;
+
+ switch (priv->speed) {
+ case 1000:
+ maccfg2 |= MACCFG2_GMII;
+ break;
+ case 100:
+ case 10:
+ maccfg2 |= MACCFG2_MII;
+
+ /* Set R100 bit in all modes although
+ * it is only used in RGMII mode
+ */
+ if (priv->speed == 100)
+ ecntrl |= ECNTRL_R100;
+ break;
+ default:
+ printf("%s: Speed was bad\n", dev->name);
+ break;
+ }
+
- return 0;
-}
+ out_be32(®s->ecntrl, ecntrl);
+ out_be32(®s->maccfg2, maccfg2);
-static struct phy_info phy_info_lxt971 = {
- 0x0001378e,
- "LXT971",
- 4,
- (struct phy_cmd[]) { /* config */
- {MIIM_CR, MIIM_CR_INIT, mii_cr_init}, /* autonegotiate */
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup - enable interrupts */
- /* { 0x12, 0x00f2, NULL }, */
- {MIIM_STATUS, miim_read, NULL},
- {MIIM_STATUS, miim_read, &mii_parse_sr},
- {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown - disable interrupts */
- {miim_end,}
- },
-};
+ printf("Speed: %d, %s duplex%s\n", priv->speed,
+ (priv->duplexity) ? "full" : "half",
+ (priv->flags & TSEC_FIBER) ? ", fiber mode" : "");
+}
-/* Parse the DP83865's link and auto-neg status register for speed and duplex
- * information
+/* Set up the buffers and their descriptors, and bring up the
+ * interface
*/
-static uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv)
+static void startup_tsec(struct eth_device *dev)
{
- switch (mii_reg & MIIM_DP83865_SPD_MASK) {
-
- case MIIM_DP83865_SPD_1000:
- priv->speed = 1000;
- break;
+ int i;
+ struct tsec_private *priv = (struct tsec_private *)dev->priv;
+ tsec_t *regs = priv->regs;
- case MIIM_DP83865_SPD_100:
- priv->speed = 100;
- break;
+ /* Point to the buffer descriptors */
+ out_be32(®s->tbase, (unsigned int)(&rtx.txbd[txIdx]));
+ out_be32(®s->rbase, (unsigned int)(&rtx.rxbd[rxIdx]));
- default:
- priv->speed = 10;
- break;
+ /* Initialize the Rx Buffer descriptors */
+ for (i = 0; i < PKTBUFSRX; i++) {
+ rtx.rxbd[i].status = RXBD_EMPTY;
+ rtx.rxbd[i].length = 0;
+ rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i];
+ }
+ rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP;
+ /* Initialize the TX Buffer Descriptors */
+ for (i = 0; i < TX_BUF_CNT; i++) {
+ rtx.txbd[i].status = 0;
+ rtx.txbd[i].length = 0;
+ rtx.txbd[i].bufPtr = 0;
}
+ rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP;
- if (mii_reg & MIIM_DP83865_DPX_FULL)
- priv->duplexity = 1;
- else
- priv->duplexity = 0;
+ /* Start up the PHY */
+ if (priv->phyinfo)
+ phy_run_commands(priv, priv->phyinfo->startup);
- return 0;
+ adjust_link(dev);
+
+ /* Enable Transmit and Receive */
+ setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
+
+ /* Tell the DMA it is clear to go */
+ setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS);
+ out_be32(®s->tstat, TSTAT_CLEAR_THALT);
+ out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
+ clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
}
-static struct phy_info phy_info_dp83865 = {
- 0x20005c7,
- "NatSemi DP83865",
- 4,
- (struct phy_cmd[]) { /* config */
- {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup */
- /* Status is read once to clear old link state */
- {MIIM_STATUS, miim_read, NULL},
- /* Auto-negotiate */
- {MIIM_STATUS, miim_read, &mii_parse_sr},
- /* Read the link and auto-neg status */
- {MIIM_DP83865_LANR, miim_read, &mii_parse_dp83865_lanr},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown */
- {miim_end,}
- },
-};
+/* This returns the status bits of the device. The return value
+ * is never checked, and this is what the 8260 driver did, so we
+ * do the same. Presumably, this would be zero if there were no
+ * errors
+ */
+static int tsec_send(struct eth_device *dev, volatile void *packet, int length)
+{
+ int i;
+ int result = 0;
+ struct tsec_private *priv = (struct tsec_private *)dev->priv;
+ tsec_t *regs = priv->regs;
-static struct phy_info phy_info_rtl8211b = {
- 0x001cc91,
- "RealTek RTL8211B",
- 4,
- (struct phy_cmd[]) { /* config */
- /* Reset and configure the PHY */
- {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
- {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
- {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
- {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
- {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup */
- /* Status is read once to clear old link state */
- {MIIM_STATUS, miim_read, NULL},
- /* Auto-negotiate */
- {MIIM_STATUS, miim_read, &mii_parse_sr},
- /* Read the status */
- {MIIM_RTL8211B_PHY_STATUS, miim_read, &mii_parse_RTL8211B_sr},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown */
- {miim_end,}
- },
-};
+ /* Find an empty buffer descriptor */
+ for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
+ if (i >= TOUT_LOOP) {
+ debug("%s: tsec: tx buffers full\n", dev->name);
+ return result;
+ }
+ }
-struct phy_info phy_info_AR8021 = {
- 0x4dd04,
- "AR8021",
- 4,
- (struct phy_cmd[]) { /* config */
- {MII_BMCR, BMCR_RESET, NULL},
- {MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART, NULL},
- {0x1d, 0x05, NULL},
- {0x1e, 0x3D47, NULL},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup */
- {MII_BMSR, miim_read, NULL},
- {MII_BMSR, miim_read, &mii_parse_sr},
- {MII_BMSR, miim_read, &mii_parse_link},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown */
- {miim_end,}
- }
-};
+ rtx.txbd[txIdx].bufPtr = (uint) packet;
+ rtx.txbd[txIdx].length = length;
+ rtx.txbd[txIdx].status |=
+ (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
-static struct phy_info *phy_info[] = {
- &phy_info_cis8204,
- &phy_info_cis8201,
- &phy_info_BCM5461S,
- &phy_info_BCM5464S,
- &phy_info_BCM5482S,
- &phy_info_M88E1011S,
- &phy_info_M88E1111S,
- &phy_info_M88E1118,
- &phy_info_M88E1121R,
- &phy_info_M88E1145,
- &phy_info_M88E1149S,
- &phy_info_dm9161,
- &phy_info_ksz804,
- &phy_info_lxt971,
- &phy_info_VSC8211,
- &phy_info_VSC8244,
- &phy_info_VSC8601,
- &phy_info_VSC8641,
- &phy_info_VSC8221,
- &phy_info_dp83865,
- &phy_info_rtl8211b,
- &phy_info_AR8021,
- &phy_info_generic, /* must be last; has ID 0 and 32 bit mask */
- NULL
-};
+ /* Tell the DMA to go */
+ out_be32(®s->tstat, TSTAT_CLEAR_THALT);
-/* Grab the identifier of the device's PHY, and search through
- * all of the known PHYs to see if one matches. If so, return
- * it, if not, return NULL
- */
-static struct phy_info *get_phy_info(struct eth_device *dev)
+ /* Wait for buffer to be transmitted */
+ for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
+ if (i >= TOUT_LOOP) {
+ debug("%s: tsec: tx error\n", dev->name);
+ return result;
+ }
+ }
+
+ txIdx = (txIdx + 1) % TX_BUF_CNT;
+ result = rtx.txbd[txIdx].status & TXBD_STATS;
+
+ return result;
+}
+
+static int tsec_recv(struct eth_device *dev)
{
+ int length;
struct tsec_private *priv = (struct tsec_private *)dev->priv;
- uint phy_reg, phy_ID;
- int i;
- struct phy_info *theInfo = NULL;
+ tsec_t *regs = priv->regs;
- /* Grab the bits from PHYIR1, and put them in the upper half */
- phy_reg = read_phy_reg(priv, MIIM_PHYIR1);
- phy_ID = (phy_reg & 0xffff) << 16;
+ while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
- /* Grab the bits from PHYIR2, and put them in the lower half */
- phy_reg = read_phy_reg(priv, MIIM_PHYIR2);
- phy_ID |= (phy_reg & 0xffff);
+ length = rtx.rxbd[rxIdx].length;
- /* loop through all the known PHY types, and find one that */
- /* matches the ID we read from the PHY. */
- for (i = 0; phy_info[i]; i++) {
- if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) {
- theInfo = phy_info[i];
- break;
+ /* Send the packet up if there were no errors */
+ if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
+ NetReceive(NetRxPackets[rxIdx], length - 4);
+ } else {
+ printf("Got error %x\n",
+ (rtx.rxbd[rxIdx].status & RXBD_STATS));
}
+
+ rtx.rxbd[rxIdx].length = 0;
+
+ /* Set the wrap bit if this is the last element in the list */
+ rtx.rxbd[rxIdx].status =
+ RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
+
+ rxIdx = (rxIdx + 1) % PKTBUFSRX;
}
- if (theInfo == &phy_info_generic) {
- printf("%s: No support for PHY id %x; assuming generic\n",
- dev->name, phy_ID);
- } else {
- debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID);
+ if (in_be32(®s->ievent) & IEVENT_BSY) {
+ out_be32(®s->ievent, IEVENT_BSY);
+ out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
}
- return theInfo;
+ return -1;
+
}
-/* Execute the given series of commands on the given device's
- * PHY, running functions as necessary
+/* Stop the interface */
+static void tsec_halt(struct eth_device *dev)
+{
+ struct tsec_private *priv = (struct tsec_private *)dev->priv;
+ tsec_t *regs = priv->regs;
+
+ clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
+ setbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
+
+ while ((in_be32(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
+ != (IEVENT_GRSC | IEVENT_GTSC))
+ ;
+
+ clrbits_be32(®s->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
+
+ /* Shut down the PHY, as needed */
+ if (priv->phyinfo)
+ phy_run_commands(priv, priv->phyinfo->shutdown);
+}
+
+/* Initializes data structures and registers for the controller,
+ * and brings the interface up. Returns the link status, meaning
+ * that it returns success if the link is up, failure otherwise.
+ * This allows u-boot to find the first active controller.
*/
-static void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd)
+static int tsec_init(struct eth_device *dev, bd_t * bd)
{
+ uint tempval;
+ char tmpbuf[MAC_ADDR_LEN];
int i;
- uint result;
- tsec_mdio_t *phyregs = priv->phyregs;
+ struct tsec_private *priv = (struct tsec_private *)dev->priv;
+ tsec_t *regs = priv->regs;
- out_be32(&phyregs->miimcfg, MIIMCFG_RESET);
+ /* Make sure the controller is stopped */
+ tsec_halt(dev);
- out_be32(&phyregs->miimcfg, MIIMCFG_INIT_VALUE);
+ /* Init MACCFG2. Defaults to GMII */
+ out_be32(®s->maccfg2, MACCFG2_INIT_SETTINGS);
- while (in_be32(&phyregs->miimind) & MIIMIND_BUSY)
- ;
+ /* Init ECNTRL */
+ out_be32(®s->ecntrl, ECNTRL_INIT_SETTINGS);
- for (i = 0; cmd->mii_reg != miim_end; i++) {
- if (cmd->mii_data == miim_read) {
- result = read_phy_reg(priv, cmd->mii_reg);
+ /* Copy the station address into the address registers.
+ * Backwards, because little endian MACS are dumb */
+ for (i = 0; i < MAC_ADDR_LEN; i++)
+ tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
- if (cmd->funct != NULL)
- (*(cmd->funct)) (result, priv);
+ tempval = (tmpbuf[0] << 24) | (tmpbuf[1] << 16) | (tmpbuf[2] << 8) |
+ tmpbuf[3];
- } else {
- if (cmd->funct != NULL)
- result = (*(cmd->funct)) (cmd->mii_reg, priv);
- else
- result = cmd->mii_data;
+ out_be32(®s->macstnaddr1, tempval);
- write_phy_reg(priv, cmd->mii_reg, result);
+ tempval = *((uint *) (tmpbuf + 4));
- }
- cmd++;
- }
-}
+ out_be32(®s->macstnaddr2, tempval);
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
- && !defined(BITBANGMII)
+ /* reset the indices to zero */
+ rxIdx = 0;
+ txIdx = 0;
-/*
- * Read a MII PHY register.
- *
- * Returns:
- * 0 on success
+ /* Clear out (for the most part) the other registers */
+ init_registers(regs);
+
+ /* Ready the device for tx/rx */
+ startup_tsec(dev);
+
+ /* If there's no link, fail */
+ return priv->link ? 0 : -1;
+}
+
+/* Discover which PHY is attached to the device, and configure it
+ * properly. If the PHY is not recognized, then return 0
+ * (failure). Otherwise, return 1
*/
-static int tsec_miiphy_read(const char *devname, unsigned char addr,
- unsigned char reg, unsigned short *value)
+static int init_phy(struct eth_device *dev)
{
- unsigned short ret;
- struct tsec_private *priv = privlist[0];
+ struct tsec_private *priv = (struct tsec_private *)dev->priv;
+ struct phy_info *curphy;
+ tsec_t *regs = priv->regs;
- if (NULL == priv) {
- printf("Can't read PHY at address %d\n", addr);
- return -1;
+ /* Assign a Physical address to the TBI */
+ out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE);
+
+ /* Reset MII (due to new addresses) */
+ out_be32(&priv->phyregs->miimcfg, MIIMCFG_RESET);
+ out_be32(&priv->phyregs->miimcfg, MIIMCFG_INIT_VALUE);
+ while (in_be32(&priv->phyregs->miimind) & MIIMIND_BUSY)
+ ;
+
+ /* Get the cmd structure corresponding to the attached
+ * PHY */
+ curphy = get_phy_info(dev);
+
+ if (curphy == NULL) {
+ priv->phyinfo = NULL;
+ printf("%s: No PHY found\n", dev->name);
+
+ return 0;
}
- ret = (unsigned short)tsec_local_mdio_read(priv->phyregs, addr, reg);
- *value = ret;
+ if (in_be32(®s->ecntrl) & ECNTRL_SGMII_MODE)
+ tsec_configure_serdes(priv);
- return 0;
+ priv->phyinfo = curphy;
+
+ phy_run_commands(priv, priv->phyinfo->config);
+
+ return 1;
}
-/*
- * Write a MII PHY register.
- *
- * Returns:
- * 0 on success
+/* Initialize device structure. Returns success if PHY
+ * initialization succeeded (i.e. if it recognizes the PHY)
*/
-static int tsec_miiphy_write(const char *devname, unsigned char addr,
- unsigned char reg, unsigned short value)
+static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info)
{
- struct tsec_private *priv = privlist[0];
+ struct eth_device *dev;
+ int i;
+ struct tsec_private *priv;
- if (NULL == priv) {
- printf("Can't write PHY at address %d\n", addr);
- return -1;
- }
+ dev = (struct eth_device *)malloc(sizeof *dev);
- tsec_local_mdio_write(priv->phyregs, addr, reg, value);
+ if (NULL == dev)
+ return 0;
- return 0;
-}
+ memset(dev, 0, sizeof *dev);
-#endif
+ priv = (struct tsec_private *)malloc(sizeof(*priv));
+
+ if (NULL == priv)
+ return 0;
+
+ privlist[num_tsecs++] = priv;
+ priv->regs = tsec_info->regs;
+ priv->phyregs = tsec_info->miiregs;
+ priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
+
+ priv->phyaddr = tsec_info->phyaddr;
+ priv->flags = tsec_info->flags;
+ sprintf(dev->name, tsec_info->devname);
+ dev->iobase = 0;
+ dev->priv = priv;
+ dev->init = tsec_init;
+ dev->halt = tsec_halt;
+ dev->send = tsec_send;
+ dev->recv = tsec_recv;
#ifdef CONFIG_MCAST_TFTP
+ dev->mcast = tsec_mcast_addr;
+#endif
-/* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
+ /* Tell u-boot to get the addr from the env */
+ for (i = 0; i < 6; i++)
+ dev->enetaddr[i] = 0;
-/* Set the appropriate hash bit for the given addr */
+ eth_register(dev);
-/* The algorithm works like so:
- * 1) Take the Destination Address (ie the multicast address), and
- * do a CRC on it (little endian), and reverse the bits of the
- * result.
- * 2) Use the 8 most significant bits as a hash into a 256-entry
- * table. The table is controlled through 8 32-bit registers:
- * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
- * gaddr7. This means that the 3 most significant bits in the
- * hash index which gaddr register to use, and the 5 other bits
- * indicate which bit (assuming an IBM numbering scheme, which
- * for PowerPC (tm) is usually the case) in the tregister holds
- * the entry. */
-static int
-tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set)
-{
- struct tsec_private *priv = privlist[1];
- volatile tsec_t *regs = priv->regs;
- volatile u32 *reg_array, value;
- u8 result, whichbit, whichreg;
+ /* Reset the MAC */
+ setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
+ udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
+ clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
- result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff);
- whichbit = result & 0x1f; /* the 5 LSB = which bit to set */
- whichreg = result >> 5; /* the 3 MSB = which reg to set it in */
- value = (1 << (31-whichbit));
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
+ && !defined(BITBANGMII)
+ miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write);
+#endif
- reg_array = &(regs->hash.gaddr0);
+ /* Try to initialize PHY here, and return */
+ return init_phy(dev);
+}
- if (set) {
- reg_array[whichreg] |= value;
- } else {
- reg_array[whichreg] &= ~value;
+/*
+ * Initialize all the TSEC devices
+ *
+ * Returns the number of TSEC devices that were initialized
+ */
+int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
+{
+ int i;
+ int ret, count = 0;
+
+ for (i = 0; i < num; i++) {
+ ret = tsec_initialize(bis, &tsecs[i]);
+ if (ret > 0)
+ count += ret;
}
- return 0;
+
+ return count;
}
-#endif /* Multicast TFTP ? */
+
+int tsec_standard_init(bd_t *bis)
+{
+ return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
+}
+