arm: socfpga: clock: Clean up bit definitions
Clean up the clock code definitions so they are aligned with mainline
standards. There are no functional changes in this patch.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c b/arch/arm/cpu/armv7/socfpga/clock_manager.c
index ed2b419..1cf0d77 100644
--- a/arch/arm/cpu/armv7/socfpga/clock_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c
@@ -13,25 +13,6 @@
static const struct socfpga_clock_manager *clock_manager_base =
(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
-#define CLKMGR_BYPASS_ENABLE 1
-#define CLKMGR_BYPASS_DISABLE 0
-#define CLKMGR_STAT_IDLE 0
-#define CLKMGR_STAT_BUSY 1
-#define CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1 0
-#define CLKMGR_BYPASS_PERPLLSRC_SELECT_INPUT_MUX 1
-#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1 0
-#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_INPUT_MUX 1
-
-#define CLEAR_BGP_EN_PWRDN \
- (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
- CLKMGR_MAINPLLGRP_VCO_EN_SET(0)| \
- CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
-
-#define VCO_EN_BASE \
- (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
- CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \
- CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
-
static void cm_wait_for_lock(uint32_t mask)
{
register uint32_t inter_val;
@@ -130,14 +111,8 @@
writel(0, &clock_manager_base->per_pll.en);
/* Put all plls in bypass */
- cm_write_bypass(
- CLKMGR_BYPASS_PERPLLSRC_SET(
- CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) |
- CLKMGR_BYPASS_SDRPLLSRC_SET(
- CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) |
- CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_ENABLE) |
- CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_ENABLE) |
- CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_ENABLE));
+ cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL |
+ CLKMGR_BYPASS_MAINPLL);
/*
* Put all plls VCO registers back to reset value.
@@ -172,19 +147,14 @@
* We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
* with numerator and denominator.
*/
- writel(cfg->main_vco_base | CLEAR_BGP_EN_PWRDN |
- CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
- &clock_manager_base->main_pll.vco);
+ writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
+ &clock_manager_base->main_pll.vco);
- writel(cfg->peri_vco_base | CLEAR_BGP_EN_PWRDN |
- CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
- &clock_manager_base->per_pll.vco);
+ writel(cfg->peri_vco_base | CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
+ &clock_manager_base->per_pll.vco);
- writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
- CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
- cfg->sdram_vco_base | CLEAR_BGP_EN_PWRDN |
- CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
- &clock_manager_base->sdr_pll.vco);
+ writel(cfg->sdram_vco_base | CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
+ &clock_manager_base->sdr_pll.vco);
/*
* Time starts here
@@ -234,18 +204,16 @@
/* Enable vco */
/* main pll vco */
- writel(cfg->main_vco_base | VCO_EN_BASE,
+ writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
&clock_manager_base->main_pll.vco);
/* periferal pll */
- writel(cfg->peri_vco_base | VCO_EN_BASE,
+ writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
&clock_manager_base->per_pll.vco);
/* sdram pll vco */
- writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
- CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
- cfg->sdram_vco_base | VCO_EN_BASE,
- &clock_manager_base->sdr_pll.vco);
+ writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
+ &clock_manager_base->sdr_pll.vco);
/* L3 MP and L3 SP */
writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv);
@@ -296,8 +264,8 @@
&clock_manager_base->per_pll.vco);
/* assert sdram outresetall */
- writel(cfg->sdram_vco_base | VCO_EN_BASE|
- CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(1),
+ writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN|
+ CLKMGR_SDRPLLGRP_VCO_OUTRESETALL,
&clock_manager_base->sdr_pll.vco);
/* deassert main outresetall */
@@ -309,9 +277,8 @@
&clock_manager_base->per_pll.vco);
/* deassert sdram outresetall */
- writel(CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
- cfg->sdram_vco_base | VCO_EN_BASE,
- &clock_manager_base->sdr_pll.vco);
+ writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
+ &clock_manager_base->sdr_pll.vco);
/*
* now that we've toggled outreset all, all the clocks
@@ -335,18 +302,10 @@
CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
/* Take all three PLLs out of bypass when safe mode is cleared. */
- cm_write_bypass(
- CLKMGR_BYPASS_PERPLLSRC_SET(
- CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) |
- CLKMGR_BYPASS_SDRPLLSRC_SET(
- CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) |
- CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_DISABLE) |
- CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_DISABLE) |
- CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_DISABLE));
+ cm_write_bypass(0);
/* clear safe mode */
- cm_write_ctrl(readl(&clock_manager_base->ctrl) |
- CLKMGR_CTRL_SAFEMODE_SET(CLKMGR_CTRL_SAFEMODE_MASK));
+ cm_write_ctrl(readl(&clock_manager_base->ctrl) | CLKMGR_CTRL_SAFEMODE);
/*
* now that safe mode is clear with clocks gated
@@ -367,9 +326,11 @@
/* get the main VCO clock */
reg = readl(&clock_manager_base->main_pll.vco);
- clock = CONFIG_HPS_CLK_OSC1_HZ /
- (CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1);
- clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1);
+ clock = CONFIG_HPS_CLK_OSC1_HZ;
+ clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >>
+ CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1;
+ clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >>
+ CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) + 1;
return clock;
}
@@ -380,7 +341,8 @@
/* identify PER PLL clock source */
reg = readl(&clock_manager_base->per_pll.vco);
- reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg);
+ reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >>
+ CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET;
if (reg == CLKMGR_VCO_SSRC_EOSC1)
clock = CONFIG_HPS_CLK_OSC1_HZ;
else if (reg == CLKMGR_VCO_SSRC_EOSC2)
@@ -390,8 +352,10 @@
/* get the PER VCO clock */
reg = readl(&clock_manager_base->per_pll.vco);
- clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1);
- clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1);
+ clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >>
+ CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) + 1;
+ clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >>
+ CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) + 1;
return clock;
}
@@ -416,7 +380,8 @@
/* identify SDRAM PLL clock source */
reg = readl(&clock_manager_base->sdr_pll.vco);
- reg = CLKMGR_SDRPLLGRP_VCO_SSRC_GET(reg);
+ reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >>
+ CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET;
if (reg == CLKMGR_VCO_SSRC_EOSC1)
clock = CONFIG_HPS_CLK_OSC1_HZ;
else if (reg == CLKMGR_VCO_SSRC_EOSC2)
@@ -426,12 +391,15 @@
/* get the SDRAM VCO clock */
reg = readl(&clock_manager_base->sdr_pll.vco);
- clock /= (CLKMGR_SDRPLLGRP_VCO_DENOM_GET(reg) + 1);
- clock *= (CLKMGR_SDRPLLGRP_VCO_NUMER_GET(reg) + 1);
+ clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >>
+ CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) + 1;
+ clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >>
+ CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) + 1;
/* get the SDRAM (DDR_DQS) clock */
reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk);
- reg = CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_GET(reg);
+ reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >>
+ CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET;
clock /= (reg + 1);
return clock;
@@ -443,7 +411,8 @@
/* identify the source of L4 SP clock */
reg = readl(&clock_manager_base->main_pll.l4src);
- reg = CLKMGR_MAINPLLGRP_L4SRC_L4SP_GET(reg);
+ reg = (reg & CLKMGR_MAINPLLGRP_L4SRC_L4SP) >>
+ CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET;
if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) {
clock = cm_get_main_vco_clk_hz();
@@ -463,7 +432,8 @@
/* get the L4 SP clock which supplied to UART */
reg = readl(&clock_manager_base->main_pll.maindiv);
- reg = CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_GET(reg);
+ reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >>
+ CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET;
clock = clock / (1 << reg);
return clock;
@@ -475,7 +445,8 @@
/* identify the source of MMC clock */
reg = readl(&clock_manager_base->per_pll.src);
- reg = CLKMGR_PERPLLGRP_SRC_SDMMC_GET(reg);
+ reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >>
+ CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET;
if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) {
clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
@@ -504,7 +475,8 @@
/* identify the source of QSPI clock */
reg = readl(&clock_manager_base->per_pll.src);
- reg = CLKMGR_PERPLLGRP_SRC_QSPI_GET(reg);
+ reg = (reg & CLKMGR_PERPLLGRP_SRC_QSPI_MASK) >>
+ CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET;
if (reg == CLKMGR_QSPI_CLK_SRC_F2S) {
clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;