tree b11673f68aab900900c598d8dfbbe27a004e27a9
parent cf73de122151c8138f70064047a5b421c6df4587
author Michal Simek <michal.simek@xilinx.com> 1584535521 +0100
committer Michal Simek <michal.simek@xilinx.com> 1586170365 +0200

arm64: versal: Disable DDR cache mapping if DDR is not enabled

Similar change was done in past by commit 3b644a3c2f69
("arm64: zynqmp: Provide a config to not map DDR region in MMU table").

Signed-off-by: Michal Simek <michal.simek@xilinx.com>