dts/upstream/Bindings/pinctrl/qcom,sm4450-tlmm.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sm4450-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. SM4450 TLMM block

maintainers:
  - Tengfei Fan <quic_tengfan@quicinc.com>

description:
  Top Level Mode Multiplexer pin controller in Qualcomm SM4450 SoC.

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

properties:
  compatible:
    const: qcom,sm4450-tlmm

  reg:
    maxItems: 1

  interrupts: true
  interrupt-controller: true
  "#interrupt-cells": true
  gpio-controller: true

  gpio-reserved-ranges:
    minItems: 1
    maxItems: 68

  gpio-line-names:
    maxItems: 136

  "#gpio-cells": true
  gpio-ranges: true
  wakeup-parent: true

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-sm4450-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-sm4450-tlmm-state"
        additionalProperties: false

$defs:
  qcom-sm4450-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
    unevaluatedProperties: false

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-5])$"
            - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
          minItems: 1
          maxItems: 36

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.
        enum: [ gpio, atest_char, atest_usb0, audio_ref_clk, cam_mclk,
                cci_async_in0, cci_i2c, cci, cmu_rng, coex_uart1_rx,
                coex_uart1_tx, cri_trng, dbg_out_clk, ddr_bist,
                ddr_pxi0_test, ddr_pxi1_test, gcc_gp1_clk, gcc_gp2_clk,
                gcc_gp3_clk, host2wlan_sol, ibi_i3c_qup0, ibi_i3c_qup1,
                jitter_bist_ref, mdp_vsync0_out, mdp_vsync1_out,
                mdp_vsync2_out, mdp_vsync3_out, mdp_vsync, nav,
                pcie0_clk_req, phase_flag, pll_bist_sync, pll_clk_aux,
                prng_rosc, qdss_cti_trig0, qdss_cti_trig1, qdss_gpio,
                qlink0_enable, qlink0_request, qlink0_wmss_reset,
                qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4,
                qup1_se0, qup1_se1, qup1_se2, qup1_se2_l2, qup1_se3,
                qup1_se4, sd_write_protect, tb_trig_sdc1, tb_trig_sdc2,
                tgu_ch0_trigout, tgu_ch1_trigout, tgu_ch2_trigout,
                tgu_ch3_trigout, tmess_prng, tsense_pwm1_out,
                tsense_pwm2_out, uim0, uim1, usb0_hs_ac, usb0_phy_ps,
                vfr_0_mira, vfr_0_mirb, vfr_1, vsense_trigger_mirnat,
                wlan1_adc_dtest0, wlan1_adc_dtest1 ]

        required:
          - pins

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    tlmm: pinctrl@f100000 {
        compatible = "qcom,sm4450-tlmm";
        reg = <0x0f100000 0x300000>;
        gpio-controller;
        #gpio-cells = <2>;
        gpio-ranges = <&tlmm 0 0 137>;
        interrupt-controller;
        #interrupt-cells = <2>;
        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;

        gpio-wo-state {
            pins = "gpio1";
            function = "gpio";
        };

        uart-w-state {
            rx-pins {
                pins = "gpio23";
                function = "qup1_se2";
                bias-pull-up;
            };

            tx-pins {
                pins = "gpio22";
                function = "qup1_se2";
                bias-disable;
            };
        };
    };
...