tree e273cc045a144e5f14a10494761123a622ac323a
parent ec9b27c443c655637b6f0184f42fc30dbeca5e06
author Jernej Skrabec <jernej.skrabec@gmail.com> 1741501902 +0100
committer Andre Przywara <andre.przywara@arm.com> 1743035195 +0000

sunxi: h616: dram: Rework size detection

Since there is quite a few possible DRAM configurations in terms of bus
width, rank and rows and columns count, size detection algorithm must be
very careful not to test combination which would be bigger than H616 is
actually capable of handling.

Ideally, we should always detect memory aliasing, even for 4 GB memory
size, which is the maximum amount of memory that H616 is capable of
handling. For this reason, we have to configure minimum amount of
supported rows when testing for columns and vice versa. This way test
code will never step out of 4 GB boundary.

While at it, check for 17 rows maximum. This aligns code with BSP DRAM
driver. There is probably no such configuration which would make sense
with 4 GB memory.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Icenowy Zheng <uwu@icenowy.me>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>