commit dde220fd944fa7a7f67b7a240ff773cd7c86356a
author Hideyuki Sano <hideyuki.sano.dn@renesas.com> Mon Jun 25 10:29:56 2012 +0900
committer Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Wed Aug 08 09:52:06 2012 +0900
tree a3636a247351d72b41230411bf39c5f264554e7e
parent 866515f38984050d1e09217b70c4c7d8ba528632

serial: sh: Add support Renesas R8A7740

The serial device of R8A7740 has the same structure as SH7372 of SH, etc.

Signed-off-by: Hideyuki Sano <hideyuki.sano.dn@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

drivers/serial/serial_sh.h

diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
index 96509e1..a33334e 100644
--- a/drivers/serial/serial_sh.h
+++ b/drivers/serial/serial_sh.h
@@ -46,7 +46,8 @@
 	defined(CONFIG_ARCH_SH7367) || \
 	defined(CONFIG_ARCH_SH7377) || \
 	defined(CONFIG_ARCH_SH7372) || \
-	defined(CONFIG_SH73A0)
+	defined(CONFIG_SH73A0) || \
+	defined(CONFIG_R8A7740)
 # define SCSCR_INIT(port)  0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
 # define PORT_PTCR	   0xA405011EUL
 # define PORT_PVCR	   0xA4050122UL
@@ -284,7 +285,8 @@
 	defined(CONFIG_ARCH_SH7367) || \
 	defined(CONFIG_ARCH_SH7377) || \
 	defined(CONFIG_ARCH_SH7372) || \
-	defined(CONFIG_SH73A0)
+	defined(CONFIG_SH73A0) || \
+	defined(CONFIG_R8A7740)
 # define SCIF_ORER    0x0200
 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
 # define SCIF_RFDC_MASK 0x007f
@@ -329,7 +331,8 @@
 	defined(CONFIG_ARCH_SH7367) || \
 	defined(CONFIG_ARCH_SH7377) || \
 	defined(CONFIG_ARCH_SH7372) || \
-	defined(CONFIG_SH73A0)
+	defined(CONFIG_SH73A0) || \
+	defined(CONFIG_R8A7740)
 # define SCxSR_RDxF_CLEAR(port)	 (sci_in(port, SCxSR) & 0xfffc)
 # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
 # define SCxSR_TDxE_CLEAR(port)	 (sci_in(port, SCxSR) & 0xffdf)
@@ -424,7 +427,8 @@
 	defined(CONFIG_ARCH_SH7367) || \
 	defined(CONFIG_ARCH_SH7377) || \
 	defined(CONFIG_ARCH_SH7372) || \
-	defined(CONFIG_SH73A0)
+	defined(CONFIG_SH73A0) || \
+	defined(CONFIG_R8A7740)
 #if defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
 				sh4_sci_offset, sh4_sci_size, \
@@ -444,7 +448,8 @@
 	defined(CONFIG_SH73A0)
 #define SCIF_FNS(name, scif_offset, scif_size) \
 	CPU_SCIF_FNS(name, scif_offset, scif_size)
-#elif defined(CONFIG_ARCH_SH7372)
+#elif defined(CONFIG_ARCH_SH7372) || \
+	defined(CONFIG_R8A7740)
 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
 				sh4_scifb_offset, sh4_scifb_size) \
 	CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
@@ -511,7 +516,8 @@
 SCIF_FNS(SCxTDR, 0x20,  8)
 SCIF_FNS(SCxRDR, 0x24,  8)
 SCIF_FNS(SCLSR,  0x00,  0)
-#elif defined(CONFIG_ARCH_SH7372)
+#elif defined(CONFIG_ARCH_SH7372) || \
+	defined(CONFIG_R8A7740)
 SCIF_FNS(SCSMR,  0x00, 16)
 SCIF_FNS(SCBRR,  0x04,  8)
 SCIF_FNS(SCSCR,  0x08, 16)
@@ -699,7 +705,8 @@
 	defined(CONFIG_ARCH_SH7367) || \
 	defined(CONFIG_ARCH_SH7377) || \
 	defined(CONFIG_ARCH_SH7372) || \
-	defined(CONFIG_SH73A0)
+	defined(CONFIG_SH73A0) || \
+	defined(CONFIG_R8A7740)
 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
 #elif defined(CONFIG_CPU_SH7723) ||\
 	defined(CONFIG_CPU_SH7724)