mmc: matsushita-common: Handle Renesas div-by-1
On the Renesas version of the IP, the /1 divider is realized by
setting the clock register [7:0] to 0xff instead of setting bit
10 of the register. Check the quirk and handle accordingly.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
diff --git a/drivers/mmc/matsushita-common.c b/drivers/mmc/matsushita-common.c
index 449f533..7e05b1f 100644
--- a/drivers/mmc/matsushita-common.c
+++ b/drivers/mmc/matsushita-common.c
@@ -542,7 +542,8 @@
divisor = DIV_ROUND_UP(priv->mclk, mmc->clock);
if (divisor <= 1)
- val = MATSU_SD_CLKCTL_DIV1;
+ val = (priv->caps & MATSU_SD_CAP_RCAR) ?
+ MATSU_SD_CLKCTL_RCAR_DIV1 : MATSU_SD_CLKCTL_DIV1;
else if (divisor <= 2)
val = MATSU_SD_CLKCTL_DIV2;
else if (divisor <= 4)