diff --git a/board/is1/qts/sdram_config.h b/board/is1/qts/sdram_config.h
index 2573171..d8521a7 100644
--- a/board/is1/qts/sdram_config.h
+++ b/board/is1/qts/sdram_config.h
@@ -7,76 +7,76 @@
 #define __SOCFPGA_SDRAM_CONFIG_H__
 
 /* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR		0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP		0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH		0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP		0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER		0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN			0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN		0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN			0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL			8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE			2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS			0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN		1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT		10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH		1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS		3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS		10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS			1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS		14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH		8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH		16
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN			0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ			0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE			1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL			0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL			7
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL			6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW			16
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC			64
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD			3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD		6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI		3120
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP		6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR		6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR		4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD			4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD			4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS			14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC			20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		512
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE			0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST			0x777
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK		3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES	0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES	8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0	0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32	0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0	0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4	0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36	0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY		0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0	0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32	0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0	0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14	0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46	0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0		0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN		0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP		0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL			2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA		0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP		0x980543
+#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR		0x5A56A
+#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP		0xB00088
+#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH		0x44555
+#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP		0x2C011000
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER		0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN			0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN		0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN			0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL			8
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE			2
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS			0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN		1
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT		10
+#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH		1
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS		3
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS		10
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS			1
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS		14
+#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH		8
+#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH		16
+#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN			0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ			0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE			1
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL			0
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL			7
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL			6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW			16
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC			64
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD			3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD		6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI		3120
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP		6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR		6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR		4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD			4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD			4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS			14
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC			20
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		512
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE			0
+#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST			0x777
+#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK		3
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES	0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES	8
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0	0x20820820
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32	0x8208208
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0	0
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4	0x41041041
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36	0x410410
+#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY		0x3FFD1088
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0	0x21084210
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32	0x1EF84
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0	0x2020
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14	0x0
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46	0xF800
+#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0		0x200
+#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN		0
+#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP		0x760210
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL			2
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA		0
+#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP		0x980543
 
 /* Sequencer auto configuration */
 #define RW_MGR_ACTIVATE_0_AND_1	0x0D