diff --git a/arch/arm/mach-socfpga/qts-filter.sh b/arch/arm/mach-socfpga/qts-filter.sh
index a49cd1b..6416252 100755
--- a/arch/arm/mach-socfpga/qts-filter.sh
+++ b/arch/arm/mach-socfpga/qts-filter.sh
@@ -36,7 +36,7 @@
 	# Retrieve the scan chain lengths
 	fix_newlines_in_macros \
 		${in_bsp_dir}/generated/iocsr_config_${soc}.h |
-	grep 'CONFIG_HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH'	| tr -d "()"
+	grep 'CFG_HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH'	| tr -d "()"
 
 	echo ""
 
@@ -115,7 +115,7 @@
 	# Retrieve the pll config and zap parenthesis
 	fix_newlines_in_macros \
 		${in_bsp_dir}/generated/pll_config.h |
-	sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}'
+	sed -n '/CFG_HPS/ !b; :next {/CFG_HPS/ s/[()]//g;/endif/ b;p;n;b next}'
 
 	cat << EOF
 
@@ -128,7 +128,7 @@
 # Filter out only the macros which are actually used by the code
 #
 grep_sdram_config() {
-	egrep "#define (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN|CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA|CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP|CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR|CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN|CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC|CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46|CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4|CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64|RW_MGR_ACTIVATE_0_AND_1|RW_MGR_ACTIVATE_0_AND_1_WAIT1|RW_MGR_ACTIVATE_0_AND_1_WAIT2|RW_MGR_ACTIVATE_1|RW_MGR_CLEAR_DQS_ENABLE|RW_MGR_EMR_OCD_ENABLE|RW_MGR_EMR|RW_MGR_EMR2|RW_MGR_EMR3|RW_MGR_GUARANTEED_READ|RW_MGR_GUARANTEED_READ_CONT|RW_MGR_GUARANTEED_WRITE|RW_MGR_GUARANTEED_WRITE_WAIT0|RW_MGR_GUARANTEED_WRITE_WAIT1|RW_MGR_GUARANTEED_WRITE_WAIT2|RW_MGR_GUARANTEED_WRITE_WAIT3|RW_MGR_IDLE|RW_MGR_IDLE_LOOP1|RW_MGR_IDLE_LOOP2|RW_MGR_INIT_RESET_0_CKE_0|RW_MGR_INIT_RESET_1_CKE_0|RW_MGR_INIT_CKE_0|RW_MGR_LFSR_WR_RD_BANK_0|RW_MGR_LFSR_WR_RD_BANK_0_DATA|RW_MGR_LFSR_WR_RD_BANK_0_DQS|RW_MGR_LFSR_WR_RD_BANK_0_NOP|RW_MGR_LFSR_WR_RD_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_BANK_0_WL_1|RW_MGR_LFSR_WR_RD_DM_BANK_0|RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA|RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS|RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP|RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1|RW_MGR_MR_CALIB|RW_MGR_MR_USER|RW_MGR_MR_DLL_RESET|RW_MGR_MRS0_DLL_RESET|RW_MGR_MRS0_DLL_RESET_MIRR|RW_MGR_MRS0_USER|RW_MGR_MRS0_USER_MIRR|RW_MGR_MRS1|RW_MGR_MRS1_MIRR|RW_MGR_MRS2|RW_MGR_MRS2_MIRR|RW_MGR_MRS3|RW_MGR_MRS3_MIRR|RW_MGR_NOP|RW_MGR_PRECHARGE_ALL|RW_MGR_READ_B2B|RW_MGR_READ_B2B_WAIT1|RW_MGR_READ_B2B_WAIT2|RW_MGR_REFRESH|RW_MGR_REFRESH_ALL|RW_MGR_RETURN|RW_MGR_SGLE_READ|RW_MGR_ZQCL|RW_MGR_TRUE_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_ADDRESS_MIRRORING|RW_MGR_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_DATA_WIDTH|RW_MGR_MEM_DQ_PER_READ_DQS|RW_MGR_MEM_DQ_PER_WRITE_DQS|RW_MGR_MEM_IF_READ_DQS_WIDTH|RW_MGR_MEM_IF_WRITE_DQS_WIDTH|RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM|RW_MGR_MEM_NUMBER_OF_RANKS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS|IO_DELAY_PER_DCHAIN_TAP|IO_DELAY_PER_DQS_EN_DCHAIN_TAP|IO_DELAY_PER_OPA_TAP|IO_DLL_CHAIN_LENGTH|IO_DQDQS_OUT_PHASE_MAX|IO_DQS_EN_DELAY_MAX|IO_DQS_EN_DELAY_OFFSET|IO_DQS_EN_PHASE_MAX|IO_DQS_IN_DELAY_MAX|IO_DQS_IN_RESERVE|IO_DQS_OUT_RESERVE|IO_IO_IN_DELAY_MAX|IO_IO_OUT1_DELAY_MAX|IO_IO_OUT2_DELAY_MAX|IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS|AFI_RATE_RATIO|AFI_CLK_FREQ|CALIB_LFIFO_OFFSET|CALIB_VFIFO_OFFSET|ENABLE_SUPER_QUICK_CALIBRATION|MAX_LATENCY_COUNT_WIDTH|READ_VALID_FIFO_SIZE|REG_FILE_INIT_SEQ_SIGNATURE|TINIT_CNTR0_VAL|TINIT_CNTR1_VAL|TINIT_CNTR2_VAL|TRESET_CNTR0_VAL|TRESET_CNTR1_VAL|TRESET_CNTR2_VAL|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP)[[:space:]]"
+	egrep "#define (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE|CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL|CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER|CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN|CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN|CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN|CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT|CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN|CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC|CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI|CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD|CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP|CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR|CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR|CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP|CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS|CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC|CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD|CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD|CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT|CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT|CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES|CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES|CFG_HPS_SDR_CTRLCFG_DRAMODT_READ|CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE|CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS|CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS|CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS|CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS|CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH|CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH|CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN|CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK|CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL|CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA|CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH|CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH|CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP|CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP|CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP|CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP|CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR|CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN|CFG_HPS_SDR_CTRLCFG_FPGAPORTRST|CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE|CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC|CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY|CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0|CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32|CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0|CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14|CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46|CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0|CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0|CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32|CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0|CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4|CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36|CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0|CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32|CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64|RW_MGR_ACTIVATE_0_AND_1|RW_MGR_ACTIVATE_0_AND_1_WAIT1|RW_MGR_ACTIVATE_0_AND_1_WAIT2|RW_MGR_ACTIVATE_1|RW_MGR_CLEAR_DQS_ENABLE|RW_MGR_EMR_OCD_ENABLE|RW_MGR_EMR|RW_MGR_EMR2|RW_MGR_EMR3|RW_MGR_GUARANTEED_READ|RW_MGR_GUARANTEED_READ_CONT|RW_MGR_GUARANTEED_WRITE|RW_MGR_GUARANTEED_WRITE_WAIT0|RW_MGR_GUARANTEED_WRITE_WAIT1|RW_MGR_GUARANTEED_WRITE_WAIT2|RW_MGR_GUARANTEED_WRITE_WAIT3|RW_MGR_IDLE|RW_MGR_IDLE_LOOP1|RW_MGR_IDLE_LOOP2|RW_MGR_INIT_RESET_0_CKE_0|RW_MGR_INIT_RESET_1_CKE_0|RW_MGR_INIT_CKE_0|RW_MGR_LFSR_WR_RD_BANK_0|RW_MGR_LFSR_WR_RD_BANK_0_DATA|RW_MGR_LFSR_WR_RD_BANK_0_DQS|RW_MGR_LFSR_WR_RD_BANK_0_NOP|RW_MGR_LFSR_WR_RD_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_BANK_0_WL_1|RW_MGR_LFSR_WR_RD_DM_BANK_0|RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA|RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS|RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP|RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1|RW_MGR_MR_CALIB|RW_MGR_MR_USER|RW_MGR_MR_DLL_RESET|RW_MGR_MRS0_DLL_RESET|RW_MGR_MRS0_DLL_RESET_MIRR|RW_MGR_MRS0_USER|RW_MGR_MRS0_USER_MIRR|RW_MGR_MRS1|RW_MGR_MRS1_MIRR|RW_MGR_MRS2|RW_MGR_MRS2_MIRR|RW_MGR_MRS3|RW_MGR_MRS3_MIRR|RW_MGR_NOP|RW_MGR_PRECHARGE_ALL|RW_MGR_READ_B2B|RW_MGR_READ_B2B_WAIT1|RW_MGR_READ_B2B_WAIT2|RW_MGR_REFRESH|RW_MGR_REFRESH_ALL|RW_MGR_RETURN|RW_MGR_SGLE_READ|RW_MGR_ZQCL|RW_MGR_TRUE_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_ADDRESS_MIRRORING|RW_MGR_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_DATA_WIDTH|RW_MGR_MEM_DQ_PER_READ_DQS|RW_MGR_MEM_DQ_PER_WRITE_DQS|RW_MGR_MEM_IF_READ_DQS_WIDTH|RW_MGR_MEM_IF_WRITE_DQS_WIDTH|RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM|RW_MGR_MEM_NUMBER_OF_RANKS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS|IO_DELAY_PER_DCHAIN_TAP|IO_DELAY_PER_DQS_EN_DCHAIN_TAP|IO_DELAY_PER_OPA_TAP|IO_DLL_CHAIN_LENGTH|IO_DQDQS_OUT_PHASE_MAX|IO_DQS_EN_DELAY_MAX|IO_DQS_EN_DELAY_OFFSET|IO_DQS_EN_PHASE_MAX|IO_DQS_IN_DELAY_MAX|IO_DQS_IN_RESERVE|IO_DQS_OUT_RESERVE|IO_IO_IN_DELAY_MAX|IO_IO_OUT1_DELAY_MAX|IO_IO_OUT2_DELAY_MAX|IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS|AFI_RATE_RATIO|AFI_CLK_FREQ|CALIB_LFIFO_OFFSET|CALIB_VFIFO_OFFSET|ENABLE_SUPER_QUICK_CALIBRATION|MAX_LATENCY_COUNT_WIDTH|READ_VALID_FIFO_SIZE|REG_FILE_INIT_SEQ_SIGNATURE|TINIT_CNTR0_VAL|TINIT_CNTR1_VAL|TINIT_CNTR2_VAL|TRESET_CNTR0_VAL|TRESET_CNTR1_VAL|TRESET_CNTR2_VAL|CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR|CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC|CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP)[[:space:]]"
 }
 
 #
@@ -161,7 +161,7 @@
 	fix_newlines_in_macros \
 		${in_bsp_dir}/generated/sdram/sdram_config.h |
 	sed -n "/\\\\$/ {N;s/ \\\\\n/\t/};p" |
-	sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' |
+	sed -n '/CFG_HPS/ !b; :next {/CFG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' |
 		sort -u | grep_sdram_config
 
 	echo ""
diff --git a/arch/arm/mach-socfpga/wrap_iocsr_config.c b/arch/arm/mach-socfpga/wrap_iocsr_config.c
index f810fad..ce86f04 100644
--- a/arch/arm/mach-socfpga/wrap_iocsr_config.c
+++ b/arch/arm/mach-socfpga/wrap_iocsr_config.c
@@ -17,19 +17,19 @@
 	switch (chain_id) {
 	case 0:
 		*table = iocsr_scan_chain0_table;
-		*table_len = CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH;
+		*table_len = CFG_HPS_IOCSR_SCANCHAIN0_LENGTH;
 		break;
 	case 1:
 		*table = iocsr_scan_chain1_table;
-		*table_len = CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH;
+		*table_len = CFG_HPS_IOCSR_SCANCHAIN1_LENGTH;
 		break;
 	case 2:
 		*table = iocsr_scan_chain2_table;
-		*table_len = CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH;
+		*table_len = CFG_HPS_IOCSR_SCANCHAIN2_LENGTH;
 		break;
 	case 3:
 		*table = iocsr_scan_chain3_table;
-		*table_len = CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH;
+		*table_len = CFG_HPS_IOCSR_SCANCHAIN3_LENGTH;
 		break;
 	default:
 		return -EINVAL;
diff --git a/arch/arm/mach-socfpga/wrap_pll_config.c b/arch/arm/mach-socfpga/wrap_pll_config.c
index bd631e0..0c40ae98 100644
--- a/arch/arm/mach-socfpga/wrap_pll_config.c
+++ b/arch/arm/mach-socfpga/wrap_pll_config.c
@@ -8,116 +8,116 @@
 #include <qts/pll_config.h>
 
 #define MAIN_VCO_BASE (					\
-	(CONFIG_HPS_MAINPLLGRP_VCO_DENOM <<		\
+	(CFG_HPS_MAINPLLGRP_VCO_DENOM <<		\
 		CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) |	\
-	(CONFIG_HPS_MAINPLLGRP_VCO_NUMER <<		\
+	(CFG_HPS_MAINPLLGRP_VCO_NUMER <<		\
 		CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET)	\
 	)
 
 #define PERI_VCO_BASE (					\
-	(CONFIG_HPS_PERPLLGRP_VCO_PSRC <<		\
+	(CFG_HPS_PERPLLGRP_VCO_PSRC <<		\
 		CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) |	\
-	(CONFIG_HPS_PERPLLGRP_VCO_DENOM <<		\
+	(CFG_HPS_PERPLLGRP_VCO_DENOM <<		\
 		CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) |	\
-	(CONFIG_HPS_PERPLLGRP_VCO_NUMER <<		\
+	(CFG_HPS_PERPLLGRP_VCO_NUMER <<		\
 		CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET)	\
 	)
 
 #define SDR_VCO_BASE (					\
-	(CONFIG_HPS_SDRPLLGRP_VCO_SSRC <<		\
+	(CFG_HPS_SDRPLLGRP_VCO_SSRC <<		\
 		CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) |	\
-	(CONFIG_HPS_SDRPLLGRP_VCO_DENOM <<		\
+	(CFG_HPS_SDRPLLGRP_VCO_DENOM <<		\
 		CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) |	\
-	(CONFIG_HPS_SDRPLLGRP_VCO_NUMER <<		\
+	(CFG_HPS_SDRPLLGRP_VCO_NUMER <<		\
 		CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET)	\
 	)
 
 static const struct cm_config cm_default_cfg = {
 	/* main group */
 	MAIN_VCO_BASE,
-	(CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT <<
+	(CFG_HPS_MAINPLLGRP_MPUCLK_CNT <<
 		CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),
-	(CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<
+	(CFG_HPS_MAINPLLGRP_MAINCLK_CNT <<
 		CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET),
-	(CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
+	(CFG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
 		CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),
-	(CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
+	(CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
 		CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),
-	(CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
+	(CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
 		CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
-	(CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
+	(CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
 		CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),
-	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
+	(CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
 		CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) |
-	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
+	(CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
 		CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) |
-	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
+	(CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
 		CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) |
-	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
+	(CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
 		CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),
-	(CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
+	(CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
 		CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) |
-	(CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
+	(CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
 		CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET),
-	(CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
+	(CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
 		CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),
-	(CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP <<
+	(CFG_HPS_MAINPLLGRP_L4SRC_L4MP <<
 		CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) |
-	(CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP <<
+	(CFG_HPS_MAINPLLGRP_L4SRC_L4SP <<
 		CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
 
 	/* peripheral group */
 	PERI_VCO_BASE,
-	(CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
+	(CFG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
 		CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),
-	(CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
+	(CFG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
 		CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET),
-	(CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
+	(CFG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
 		CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET),
-	(CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
+	(CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
 		CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
-	(CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT <<
+	(CFG_HPS_PERPLLGRP_PERBASECLK_CNT <<
 		CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET),
-	(CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
+	(CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
 		CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),
-	(CONFIG_HPS_PERPLLGRP_DIV_USBCLK <<
+	(CFG_HPS_PERPLLGRP_DIV_USBCLK <<
 		CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) |
-	(CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK <<
+	(CFG_HPS_PERPLLGRP_DIV_SPIMCLK <<
 		CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) |
-	(CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK <<
+	(CFG_HPS_PERPLLGRP_DIV_CAN0CLK <<
 		CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) |
-	(CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK <<
+	(CFG_HPS_PERPLLGRP_DIV_CAN1CLK <<
 		CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),
-	(CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
+	(CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
 		CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET),
-	(CONFIG_HPS_PERPLLGRP_SRC_QSPI <<
+	(CFG_HPS_PERPLLGRP_SRC_QSPI <<
 		CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) |
-	(CONFIG_HPS_PERPLLGRP_SRC_NAND <<
+	(CFG_HPS_PERPLLGRP_SRC_NAND <<
 		CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) |
-	(CONFIG_HPS_PERPLLGRP_SRC_SDMMC <<
+	(CFG_HPS_PERPLLGRP_SRC_SDMMC <<
 		CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),
 
 	/* sdram pll group */
 	SDR_VCO_BASE,
-	(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
+	(CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
 		CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) |
-	(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
+	(CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
 		CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
-	(CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
+	(CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
 		CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) |
-	(CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
+	(CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
 		CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),
-	(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
+	(CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
 		CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |
-	(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
+	(CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
 		CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),
-	(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
+	(CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
 		CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
-	(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
+	(CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
 		CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
 
 	/* altera group */
-	CONFIG_HPS_ALTERAGRP_MPUCLK,
+	CFG_HPS_ALTERAGRP_MPUCLK,
 };
 
 const struct cm_config * const cm_get_default_config(void)
@@ -128,19 +128,19 @@
 const unsigned int cm_get_osc_clk_hz(const int osc)
 {
 	if (osc == 1)
-		return CONFIG_HPS_CLK_OSC1_HZ;
+		return CFG_HPS_CLK_OSC1_HZ;
 	else if (osc == 2)
-		return CONFIG_HPS_CLK_OSC2_HZ;
+		return CFG_HPS_CLK_OSC2_HZ;
 	else
 		return 0;
 }
 
 const unsigned int cm_get_f2s_per_ref_clk_hz(void)
 {
-	return CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+	return CFG_HPS_CLK_F2S_PER_REF_HZ;
 }
 
 const unsigned int cm_get_f2s_sdr_ref_clk_hz(void)
 {
-	return CONFIG_HPS_CLK_F2S_SDR_REF_HZ;
+	return CFG_HPS_CLK_F2S_SDR_REF_HZ;
 }
diff --git a/arch/arm/mach-socfpga/wrap_sdram_config.c b/arch/arm/mach-socfpga/wrap_sdram_config.c
index 4ea32e7..cd3a0f6 100644
--- a/arch/arm/mach-socfpga/wrap_sdram_config.c
+++ b/arch/arm/mach-socfpga/wrap_sdram_config.c
@@ -12,180 +12,180 @@
 
 static const struct socfpga_sdram_config sdram_config = {
 	.ctrl_cfg =
-		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
+		(CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
 			SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
+		(CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
 			SDR_CTRLGRP_CTRLCFG_MEMBL_LSB)			|
-		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER <<
+		(CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER <<
 			SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
+		(CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
 			SDR_CTRLGRP_CTRLCFG_ECCEN_LSB)			|
-		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
+		(CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
 			SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
+		(CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
 			SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
+		(CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
 			SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
+		(CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
 			SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
+		(CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
 			SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB),
 	.dram_timing1 =
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
+		(CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
 			SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
+		(CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
 			SDR_CTRLGRP_DRAMTIMING1_TAL_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
+		(CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
 			SDR_CTRLGRP_DRAMTIMING1_TCL_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
+		(CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
 			SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
+		(CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
 			SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
+		(CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
 			SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB),
 	.dram_timing2 =
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
+		(CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
 			SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
+		(CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
 			SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
+		(CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
 			SDR_CTRLGRP_DRAMTIMING2_TRP_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
+		(CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
 			SDR_CTRLGRP_DRAMTIMING2_TWR_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
+		(CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
 			SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB),
 	.dram_timing3 =
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
+		(CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
 			SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
+		(CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
 			SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
+		(CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
 			SDR_CTRLGRP_DRAMTIMING3_TRC_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
+		(CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
 			SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
+		(CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
 			SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB),
 	.dram_timing4 =
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
+		(CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
 			SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB)	|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
+		(CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
 			SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB),
 	.lowpwr_timing =
-		(CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
+		(CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
 			SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB)	|
-		(CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
+		(CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
 			SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB),
 	.dram_odt =
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
+		(CFG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
 			SDR_CTRLGRP_DRAMODT_READ_LSB)			|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
+		(CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
 			SDR_CTRLGRP_DRAMODT_WRITE_LSB),
-#if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 2)	/* DDR3 */
+#if (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 2)	/* DDR3 */
 	.extratime1 =
-		(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR <<
+		(CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR <<
 				SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC <<
+		(CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC <<
 				SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP <<
+		(CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP <<
 				SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB),
 #endif
 	.dram_addrw =
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
+		(CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
 			SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS <<
+		(CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS <<
 			SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
+		(CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
 			SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB)		|
-		((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
+		((CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
 			SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB),
 	.dram_if_width =
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
+		(CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
 			SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB),
 	.dram_dev_width =
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
+		(CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
 			SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB),
 	.dram_intr =
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
+		(CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
 			SDR_CTRLGRP_DRAMINTR_INTREN_LSB),
 	.lowpwr_eq =
-		(CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
+		(CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
 			SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB),
 	.static_cfg =
-		(CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
+		(CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
 			SDR_CTRLGRP_STATICCFG_MEMBL_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
+		(CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
 			SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB),
 	.ctrl_width =
-		(CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
+		(CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
 			SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB),
 	.cport_width =
-		(CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
+		(CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
 			SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB),
 	.cport_wmap =
-		(CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
+		(CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
 			SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB),
 	.cport_rmap =
-		(CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
+		(CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
 			SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB),
 	.rfifo_cmap =
-		(CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
+		(CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
 			SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB),
 	.wfifo_cmap =
-		(CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
+		(CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
 			SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB),
 	.cport_rdwr =
-		(CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
+		(CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
 			SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB),
 	.port_cfg =
-		(CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
+		(CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
 			SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB),
-	.fpgaport_rst = CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST,
+	.fpgaport_rst = CFG_HPS_SDR_CTRLCFG_FPGAPORTRST,
 	.fifo_cfg =
-		(CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
+		(CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
 			SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
+		(CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
 			SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB),
 	.mp_priority =
-		(CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
+		(CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
 			SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB),
 	.mp_weight0 =
-		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
+		(CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
 			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB),
 	.mp_weight1 =
-		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
+		(CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
 			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) |
-		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
+		(CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
 			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB),
 	.mp_weight2 =
-		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
+		(CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
 			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB),
 	.mp_weight3 =
-		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
+		(CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
 			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB),
 	.mp_pacing0 =
-		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
+		(CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
 			SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB),
 	.mp_pacing1 =
-		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
+		(CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
 			SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) |
-		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
+		(CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
 			SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB),
 	.mp_pacing2 =
-		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
+		(CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
 			SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB),
 	.mp_pacing3 =
-		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
+		(CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
 			SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB),
 	.mp_threshold0 =
-		(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
+		(CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
 			SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB),
 	.mp_threshold1 =
-		(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
+		(CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
 			SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB),
 	.mp_threshold2 =
-		(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
+		(CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
 			SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB),
-	.phy_ctrl0 = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,
+	.phy_ctrl0 = CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,
 };
 
 static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = {
@@ -202,7 +202,7 @@
 	.guaranteed_write_wait3		= RW_MGR_GUARANTEED_WRITE_WAIT3,
 	.idle_loop1			= RW_MGR_IDLE_LOOP1,
 	.idle_loop2			= RW_MGR_IDLE_LOOP2,
-#if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 1)	/* DDR2 */
+#if (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 1)	/* DDR2 */
 	.emr				= RW_MGR_EMR,
 	.emr2				= RW_MGR_EMR2,
 	.emr3				= RW_MGR_EMR3,
@@ -213,7 +213,7 @@
 	.mr_user			= RW_MGR_MR_USER,
 	.mr_dll_reset			= RW_MGR_MR_DLL_RESET,
 	.emr_ocd_enable			= RW_MGR_EMR_OCD_ENABLE,
-#elif (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 2)	/* DDR3 */
+#elif (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 2)	/* DDR3 */
 	.activate_1			= RW_MGR_ACTIVATE_1,
 	.idle				= RW_MGR_IDLE,
 	.init_reset_0_cke_0		= RW_MGR_INIT_RESET_0_CKE_0,
@@ -287,7 +287,7 @@
 };
 
 static const struct socfpga_sdram_misc_config misc_config = {
-#if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 1)	/* DDR2 */
+#if (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 1)	/* DDR2 */
 	.afi_clk_freq			= AFI_CLK_FREQ,
 #endif
 	.afi_rate_ratio			= AFI_RATE_RATIO,