| commit | ad6385b08f2c457aec30b22f428a44d0c661e430 | [log] [tgz] |
|---|---|---|
| author | Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> | Thu Apr 03 19:07:02 2025 -0700 |
| committer | Tien Fong Chee <tien.fong.chee@intel.com> | Tue Apr 22 11:47:39 2025 +0800 |
| tree | 97149ff2ca69eabffcd2b78b76d60eefd9dadd81 | |
| parent | a7e1ba3586135c4a2af54aebcf8088c414277b30 [diff] |
arm: socfpga: soc64: Update reset manager registers for F2S bridge Add reset manager registers in preparation for F2S bridge reset support as well as the mask support to enable/disable the bridges. Mask value: BIT0: soc2fpga BIT1: lwhps2fpga BIT2: fpga2soc These bridges are available only in Stratix10: BIT3: f2sdram0 BIT4: f2sdram1 BIT5: f2sdram2 Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>