// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2019, 2021 NXP
 */

#include "imx8mp-u-boot.dtsi"

/ {
	wdt-reboot {
		compatible = "wdt-reboot";
		wdt = <&wdog1>;
		bootph-pre-ram;
	};
	firmware {
		optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};
	};
};

&reg_usdhc2_vmmc {
	u-boot,off-on-delay-us = <20000>;
};

&reg_usdhc2_vmmc {
	bootph-pre-ram;
};

&pinctrl_uart2 {
	bootph-pre-ram;
};

&pinctrl_usdhc2_gpio {
	bootph-pre-ram;
};

&pinctrl_usdhc2 {
	bootph-pre-ram;
};

&pinctrl_usdhc3 {
	bootph-pre-ram;
};

&pinctrl_wdog {
	bootph-pre-ram;
};

&gpio1 {
	bootph-pre-ram;
};

&gpio2 {
	bootph-pre-ram;
};

&gpio3 {
	bootph-pre-ram;
};

&gpio4 {
	bootph-pre-ram;
};

&gpio5 {
	bootph-pre-ram;
};

&uart2 {
	bootph-pre-ram;
};

&crypto {
	bootph-pre-ram;
};

&sec_jr0 {
	bootph-pre-ram;
};

&sec_jr1 {
	bootph-pre-ram;
};

&sec_jr2 {
	bootph-pre-ram;
};

&i2c1 {
	bootph-pre-ram;
};

&i2c2 {
	bootph-pre-ram;
};

&i2c3 {
	bootph-pre-ram;
};

&i2c4 {
	bootph-pre-ram;
};

&i2c5 {
	bootph-pre-ram;
};

&i2c6 {
	bootph-pre-ram;
};

&usdhc1 {
	bootph-pre-ram;
};

&usdhc2 {
	bootph-pre-ram;
	sd-uhs-sdr104;
	sd-uhs-ddr50;
};

&usdhc3 {
	bootph-pre-ram;
	mmc-hs400-1_8v;
	mmc-hs400-enhanced-strobe;
};

&wdog1 {
	bootph-pre-ram;
};

&eqos {
	/delete-property/ assigned-clocks;
	/delete-property/ assigned-clock-parents;
	/delete-property/ assigned-clock-rates;
};

&ethphy0 {
	reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
	reset-delay-us = <15000>;
	reset-post-delay-us = <100000>;
};

&fec {
	phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <15>;
	phy-reset-post-delay = <100>;
};