diff --git a/board/freescale/mpc8308rdb/mpc8308rdb.c b/board/freescale/mpc8308rdb/mpc8308rdb.c
index a864189..fb29abf 100644
--- a/board/freescale/mpc8308rdb/mpc8308rdb.c
+++ b/board/freescale/mpc8308rdb/mpc8308rdb.c
@@ -36,16 +36,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int board_early_init_f(void)
-{
-	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-
-	if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF)
-		gd->flags |= GD_FLG_SILENT;
-
-	return 0;
-}
-
 static u8 read_board_info(void)
 {
 	u8 val8;
@@ -96,16 +86,12 @@
 {
 	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
 	sysconf83xx_t *sysconf = &immr->sysconf;
-	clk83xx_t *clk = (clk83xx_t *)&immr->clk;
 	law83xx_t *pcie_law = sysconf->pcielaw;
 	struct pci_region *pcie_reg[] = { pcie_regions_0 };
 
 	fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
 					FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
 
-	clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM ,
-				    SCCR_PCIEXP1CM_1);
-
 	/* Deassert the resets in the control register */
 	out_be32(&sysconf->pecr1, 0xE0008000);
 	udelay(2000);
@@ -146,12 +132,14 @@
 	int rv, num_if = 0;
 
 	/* Initialize TSECs first */
-	if ((rv = cpu_eth_init(bis)) >= 0)
+	rv = cpu_eth_init(bis);
+	if (rv >= 0)
 		num_if += rv;
 	else
 		printf("ERROR: failed to initialize TSECs.\n");
 
-	if ((rv = pci_eth_init(bis)) >= 0)
+	rv = pci_eth_init(bis);
+	if (rv >= 0)
 		num_if += rv;
 	else
 		printf("ERROR: failed to initialize PCI Ethernet.\n");
diff --git a/board/freescale/mpc8308rdb/sdram.c b/board/freescale/mpc8308rdb/sdram.c
index 939c1b8..1a6b9c7 100644
--- a/board/freescale/mpc8308rdb/sdram.c
+++ b/board/freescale/mpc8308rdb/sdram.c
@@ -38,20 +38,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static void resume_from_sleep(void)
-{
-	u32 magic = *(u32 *)0;
-
-	typedef void (*func_t)(void);
-	func_t resume = *(func_t *)4;
-
-	if (magic == 0xf5153ae5)
-		resume();
-
-	gd->flags &= ~GD_FLG_SILENT;
-	puts("\nResume from sleep failed: bad magic word\n");
-}
-
 /* Fixed sdram init -- doesn't use serial presence detect.
  *
  * This is useful for faster booting in configs where the RAM is unlikely
@@ -68,12 +54,6 @@
 	out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
 	out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
 
-	/*
-	 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
-	 * or the DDR2 controller may fail to initialize correctly.
-	 */
-	udelay(50000);
-
 	out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
 	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
 
@@ -86,13 +66,7 @@
 	out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
 	out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
 
-	if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF) {
-		out_be32(&im->ddr.sdram_cfg,
-			CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI);
-	} else {
-		out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
-	}
-
+	out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
 	out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
 	out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
 	out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
@@ -118,9 +92,6 @@
 	/* DDR SDRAM */
 	msize = fixed_sdram();
 
-	if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF)
-		resume_from_sleep();
-
 	/* return total bus SDRAM size(bytes)  -- DDR */
 	return msize;
 }