tree 893e659f70e6061811312a32a27536010fa65d1d
parent f3a599724922f9f789ba16ca436a4407219257a9
author Patrick Delaunay <patrick.delaunay@foss.st.com> 1663745833 +0200
committer Patrice Chotard <patrice.chotard@foss.st.com> 1663936545 +0200

ARM: dts: stm32mp15: update DDR node

Remove the unnecessary nodes for TFABOOT and keep the mandatory part
in SOC dtsi, only the DDRCTRL and DDRPHY addresses.
This patch allows to manage the DDR configuration setting in U-Boot
device tree only if it is needed, when CONFIG_SPL is defined.

With TFABOOT, the DDR configuration is done in TF-A BL2 and the DDR size
is dynamically computed in U-Boot since commit d72e7bbe7c28 ("ram:
stm32mp1: compute DDR size from DDRCTL registers").

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>