arm: add support for Hisilicon HiSTB family SoCs
First supported chip is hi3798mv200 (which is similar to Hi3798cv200
used by poplar).
Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
diff --git a/arch/arm/mach-histb/Kconfig b/arch/arm/mach-histb/Kconfig
new file mode 100644
index 0000000..78d4085
--- /dev/null
+++ b/arch/arm/mach-histb/Kconfig
@@ -0,0 +1,14 @@
+if ARCH_HISTB
+
+choice
+ prompt "Select a HiSTB SoC"
+
+config ARCH_HI3798MV2X
+ bool "Hi3798M V2XX series SoC"
+ select ARM64
+ help
+ Support for Hi3798MV2XX series SoCs.
+
+endchoice
+
+endif
diff --git a/arch/arm/mach-histb/Makefile b/arch/arm/mach-histb/Makefile
new file mode 100644
index 0000000..7975c0f
--- /dev/null
+++ b/arch/arm/mach-histb/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += sysmap-histb.o
+obj-y += board_common.o
diff --git a/arch/arm/mach-histb/board_common.c b/arch/arm/mach-histb/board_common.c
new file mode 100644
index 0000000..a26c206
--- /dev/null
+++ b/arch/arm/mach-histb/board_common.c
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board init file for all histb boards
+ *
+ * (C) Copyright 2023 Yang Xiwen <forbidden405@outlook.com>
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <init.h>
+#include <asm/system.h>
+
+int __weak board_init(void)
+{
+ return 0;
+}
+
+int __weak dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
+
+int __weak dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+void __weak reset_cpu(void)
+{
+ psci_system_reset();
+}
diff --git a/arch/arm/mach-histb/sysmap-histb.c b/arch/arm/mach-histb/sysmap-histb.c
new file mode 100644
index 0000000..83a2bb9
--- /dev/null
+++ b/arch/arm/mach-histb/sysmap-histb.c
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Hisilicon HiSTB memory map
+ *
+ * (C) Copyright 2023 Yang Xiwen <forbidden405@outlook.com>
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+
+static struct mm_region histb_mem_map[] = {
+ {
+ .virt = 0x0UL, /* DRAM */
+ .phys = 0x0UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x80000000UL, /* Peripheral block */
+ .phys = 0x80000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* Terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = histb_mem_map;