tree 4e30bec98504a3923d40df2594b48c173032e192
parent 2bf60fe7ca748db208f4fea7f31bfa4ed2e05f17
parent 28043e246f88466a0da2fef995bb8f036fcee061
author Tom Rini <trini@konsulko.com> 1583158812 -0500
committer Tom Rini <trini@konsulko.com> 1583158812 -0500

Merge tag 'xilinx-for-v2020.04-rc4' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx fixes for v2020.04-rc4

- Fix link good bit handling in dp83867
- Rename generic Zynq defconfig
- Fix zybo z7 low leve setup
- Fix error path in zynq_gem driver and fix 64bit usage
- Fix invalid clock name quieries for Versal
- Fix zynq/zynqmp SPL low level configuration via DT selection