diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index 930fa71..8704014 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -132,6 +132,12 @@
 		(0x80000000 >> (28 + CFG_NAND_CS));
 	mtsdr(SDR0_CUST0, sdr0_cust0);
 
+	/* Update EBC speed after booting from i2c bootstrap settings
+	 * on newer boards with 33.333 MHZ Clocks
+	 */
+	if (in8(CFG_BCSR_BASE + 3) & 0x80)
+		mtcpr(0xe0, 0x02000000);
+
 	return 0;
 }
 
@@ -363,8 +369,8 @@
 	printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
 #endif
 
-	rev = *(u8 *)(CFG_BCSR_BASE + 0);
-	val = *(u8 *)(CFG_BCSR_BASE + 5) & 0x01;
+	rev = in8(CFG_BCSR_BASE + 0);
+	val = in8(CFG_BCSR_BASE + 5) & 0x01;
 	printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
 
 	if (s != NULL) {
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index b7f79c2..e1572ba 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -40,7 +40,7 @@
 #define CONFIG_4xx		1		/* ... PPC4xx family	*/
 /* Detect Sequoia PLL input clock automatically via CPLD bit		*/
 #define CONFIG_SYS_CLK_FREQ    ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \
-				3333333 : 33000000)
+				33333333 : 33000000)
 
 #define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f */
 #define CONFIG_MISC_INIT_R	1		/* Call misc_init_r	*/
diff --git a/include/ppc440.h b/include/ppc440.h
index bc1d7aa..07f75de 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -1425,9 +1425,6 @@
 /*----------------------------------------------------------------------------+
 | Clock / Power-on-reset DCR's.
 +----------------------------------------------------------------------------*/
-#define CPR0_CFGADDR			0x00C
-#define CPR0_CFGDATA			0x00D
-
 #define CPR0_CLKUPD			0x20
 #define CPR0_CLKUPD_BSY_MASK		0x80000000
 #define CPR0_CLKUPD_BSY_COMPLETED	0x00000000
@@ -3314,6 +3311,23 @@
 #define mtsdr(reg, data)	do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); } while (0)
 #define mfsdr(reg, data)	do { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); } while (0)
 
+/*
+ * All 44x except 440GP have CPR registers (indirect DCR)
+ */
+#if !defined(CONFIG_440GP)
+#define CPR0_CFGADDR		0x00C
+#define CPR0_CFGDATA		0x00D
+
+#define mtcpr(reg, data)	do { \
+		mtdcr(CPR0_CFGADDR, reg); \
+		mtdcr(CPR0_CFGDATA, data); \
+	} while (0)
+
+#define mfcpr(reg, data)	do { \
+		mtdcr(CPR0_CFGADDR, reg); \
+		data = mfdcr(CPR0_CFGDATA); \
+	} while (0)
+#endif
 
 #ifndef __ASSEMBLY__
 
diff --git a/lib_ppc/board.c b/lib_ppc/board.c
index 1e7f172..9e85cdd 100644
--- a/lib_ppc/board.c
+++ b/lib_ppc/board.c
@@ -564,7 +564,9 @@
 
 	bd->bi_procfreq = gd->cpu_clk;	/* Processor Speed, In Hz */
 	bd->bi_plb_busfreq = gd->bus_clk;
-#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
+    defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 	bd->bi_pci_busfreq = get_PCI_freq ();
 	bd->bi_opbfreq = get_OPB_freq ();
 #elif defined(CONFIG_XILINX_ML300)