arm64: gic: Add power up sequence for GIC-600
Arm's GIC-600 features a Power Register (GICR_PWRR),
which needs to be programmed to enable redistributor
operation. Power on the redistributor and wait until
the power on state is reflected by checking the bit
GICR_PWRR.RDPD == 0. While running U-Boot in EL3
without enabling this register, GICR_WAKER.ChildrenAsleep
bit is not getting cleared and loops infinitely.
This register(GICR_PWRR) must be programmed to mark the frame
as powered on, before accessing other registers in the frame.
Rest of initialization sequence remains the same.
ARM GIC-600 IP complies with ARM GICv3 architecture.
Enable this config if GIC-600 IP present.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0d978c0..a0842e1 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -124,6 +124,15 @@
ARM GICV3 has limitation, once the LPI table is enabled, LPI
configuration table can not be re-programmed, unless GICV3 reset.
+config GICV3_SUPPORT_GIC600
+ bool "ARM GICV3 GIC600 SUPPORT"
+ help
+ ARM GIC-600 IP complies with ARM GICv3 architecture, but among others,
+ implements a power control register in the Redistributor frame.This
+ register must be programmed to mark the frame as powered on, before
+ accessing other registers in the frame. Rest of initialization sequence
+ remains the same.
+
config STATIC_RELA
bool
default y if ARM64