tree ff94f77aa0bb50d3fd07ced4b4e0ea279c49a9d0
parent 27d3b1988d18f81ef90727bc21b51d726475681a
author Paul Burton <paul.burton@imgtec.com> 1493582228 +0200
committer Joe Hershberger <joe.hershberger@ni.com> 1496432660 -0500

net: pch_gbe: Add cache maintenance

On MIPS systems DMA isn't coherent with the CPU caches unless an IOCU is
present. When there is no IOCU we need to writeback or invalidate the
data caches at appropriate points. Perform this cache maintenance in
the pch_gbe driver which is used on the MIPS Boston development board.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>