arm: octeontx2: Add support for OcteonTX2 SoC platforms
This patch adds support for all OcteonTX2 96xx/95xx
boards from Marvell.
For 96xx boards, use octeontx_96xx_defconfig and
for 95xx boards, use octeontx_95xx_defconfig.
Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f5f6689..8706207 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1736,6 +1736,16 @@
select OF_LIVE
select BOARD_LATE_INIT
select SYS_CACHE_SHIFT_7
+
+config ARCH_OCTEONTX2
+ bool "Support OcteonTX2 SoCs"
+ select DM
+ select ARM64
+ select OF_CONTROL
+ select OF_LIVE
+ select BOARD_LATE_INIT
+ select SYS_CACHE_SHIFT_7
+
config TARGET_THUNDERX_88XX
bool "Support ThunderX 88xx"
select ARM64
@@ -1835,6 +1845,9 @@
source "arch/arm/mach-mvebu/Kconfig"
source "arch/arm/mach-octeontx/Kconfig"
+
+source "arch/arm/mach-octeontx2/Kconfig"
+
source "arch/arm/cpu/armv7/ls102xa/Kconfig"
source "arch/arm/mach-imx/mx2/Kconfig"
@@ -1919,6 +1932,7 @@
source "board/Marvell/aspenite/Kconfig"
source "board/Marvell/gplugd/Kconfig"
source "board/Marvell/octeontx/Kconfig"
+source "board/Marvell/octeontx2/Kconfig"
source "board/armadeus/apf27/Kconfig"
source "board/armltd/vexpress/Kconfig"
source "board/armltd/vexpress64/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 87b4198..28b523b 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -81,6 +81,7 @@
machine-$(CONFIG_ARCH_TEGRA) += tegra
machine-$(CONFIG_ARCH_U8500) += u8500
machine-$(CONFIG_ARCH_OCTEONTX) += octeontx
+machine-$(CONFIG_ARCH_OCTEONTX2) += octeontx2
machine-$(CONFIG_ARCH_UNIPHIER) += uniphier
machine-$(CONFIG_ARCH_VERSAL) += versal
machine-$(CONFIG_ARCH_ZYNQ) += zynq
diff --git a/arch/arm/mach-octeontx2/Kconfig b/arch/arm/mach-octeontx2/Kconfig
new file mode 100644
index 0000000..8e5cb0f
--- /dev/null
+++ b/arch/arm/mach-octeontx2/Kconfig
@@ -0,0 +1,23 @@
+if ARCH_OCTEONTX2
+
+choice
+ prompt "OcteonTX2 board select"
+ optional
+
+config TARGET_OCTEONTX2_95XX
+ bool "Marvell OcteonTX2 CN95XX"
+
+config TARGET_OCTEONTX2_96XX
+ bool "Marvell OcteonTX2 CN96XX"
+
+endchoice
+
+config SYS_SOC
+ string
+ default "octeontx2"
+
+config SYS_PCI_64BIT
+ bool
+ default y
+
+endif
diff --git a/arch/arm/mach-octeontx2/Makefile b/arch/arm/mach-octeontx2/Makefile
new file mode 100644
index 0000000..c319234
--- /dev/null
+++ b/arch/arm/mach-octeontx2/Makefile
@@ -0,0 +1,9 @@
+#/*
+# * Copyright (C) 2018 Marvell International Ltd.
+# *
+# * SPDX-License-Identifier: GPL-2.0
+# * https://spdx.org/licenses
+# */
+
+obj-y += lowlevel_init.o clock.o cpu.o
+
diff --git a/arch/arm/mach-octeontx2/clock.c b/arch/arm/mach-octeontx2/clock.c
new file mode 100644
index 0000000..9da2107
--- /dev/null
+++ b/arch/arm/mach-octeontx2/clock.c
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/board.h>
+#include <asm/arch/clock.h>
+
+/**
+ * Returns the I/O clock speed in Hz
+ */
+u64 octeontx_get_io_clock(void)
+{
+ union rst_boot rst_boot;
+
+ rst_boot.u = readq(RST_BOOT);
+
+ return rst_boot.s.pnr_mul * PLL_REF_CLK;
+}
+
+/**
+ * Returns the core clock speed in Hz
+ */
+u64 octeontx_get_core_clock(void)
+{
+ union rst_boot rst_boot;
+
+ rst_boot.u = readq(RST_BOOT);
+
+ return rst_boot.s.c_mul * PLL_REF_CLK;
+}
diff --git a/arch/arm/mach-octeontx2/config.mk b/arch/arm/mach-octeontx2/config.mk
new file mode 100644
index 0000000..9214f6b
--- /dev/null
+++ b/arch/arm/mach-octeontx2/config.mk
@@ -0,0 +1,4 @@
+ifeq ($(CONFIG_ARCH_OCTEONTX2),y)
+PLATFORM_CPPFLAGS += $(call cc-option,-march=armv8.2-a,)
+PLATFORM_CPPFLAGS += $(call cc-option,-mtune=octeontx2,)
+endif
diff --git a/arch/arm/mach-octeontx2/cpu.c b/arch/arm/mach-octeontx2/cpu.c
new file mode 100644
index 0000000..2a6d5e8
--- /dev/null
+++ b/arch/arm/mach-octeontx2/cpu.c
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+#include <asm/io.h>
+#include <asm/arch/board.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define OTX2_MEM_MAP_USED 4
+
+/* +1 is end of list which needs to be empty */
+#define OTX2_MEM_MAP_MAX (OTX2_MEM_MAP_USED + CONFIG_NR_DRAM_BANKS + 1)
+
+static struct mm_region otx2_mem_map[OTX2_MEM_MAP_MAX] = {
+ {
+ .virt = 0x800000000000UL,
+ .phys = 0x800000000000UL,
+ .size = 0x40000000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE
+ }, {
+ .virt = 0x840000000000UL,
+ .phys = 0x840000000000UL,
+ .size = 0x40000000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE
+ }, {
+ .virt = 0x880000000000UL,
+ .phys = 0x880000000000UL,
+ .size = 0x40000000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE
+ }, {
+ .virt = 0x8c0000000000UL,
+ .phys = 0x8c0000000000UL,
+ .size = 0x40000000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE
+ }
+};
+
+struct mm_region *mem_map = otx2_mem_map;
+
+void mem_map_fill(void)
+{
+ int banks = OTX2_MEM_MAP_USED;
+ u32 dram_start = CONFIG_SYS_TEXT_BASE;
+
+ for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ otx2_mem_map[banks].virt = dram_start;
+ otx2_mem_map[banks].phys = dram_start;
+ otx2_mem_map[banks].size = gd->ram_size;
+ otx2_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_NON_SHARE;
+ banks = banks + 1;
+ }
+}
+
+u64 get_page_table_size(void)
+{
+ return 0x80000;
+}
+
+void reset_cpu(ulong addr)
+{
+}
diff --git a/arch/arm/mach-octeontx2/lowlevel_init.S b/arch/arm/mach-octeontx2/lowlevel_init.S
new file mode 100644
index 0000000..41a9f08
--- /dev/null
+++ b/arch/arm/mach-octeontx2/lowlevel_init.S
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/macro.h>
+
+.align 8
+.global fdt_base_addr
+fdt_base_addr:
+ .dword 0x0
+
+.global save_boot_params
+save_boot_params:
+ /* Read FDT base from x1 register passed by ATF */
+ adr x21, fdt_base_addr
+ str x1, [x21]
+
+ /* Returns */
+ b save_boot_params_ret
+
+ENTRY(lowlevel_init)
+ mov x29, lr /* Save LR */
+
+ /* any lowlevel init should go here */
+
+ mov lr, x29 /* Restore LR */
+ ret
+ENDPROC(lowlevel_init)