Merge patch series "test: Avoid needing sudo for image-creation"

Simon Glass <sjg@chromium.org> says:

This series rebases and tidies up a series sent by Richard Weinberger
to use unprivileged code to build the test images.

Link: https://patchwork.ozlabs.org/project/uboot/list/?series=417786&state=*
Link: https://lore.kernel.org/r/20241121223217.330117-1-sjg@chromium.org
Signed-off-by: Tom Rini <trini@konsulko.com>
diff --git a/.gitignore b/.gitignore
index 502a7e6..e93c33d 100644
--- a/.gitignore
+++ b/.gitignore
@@ -75,6 +75,9 @@
 /keep-syms-lto.*
 /*imx8mimage*
 /*imx8mcst*
+/drivers/video/u_boot_logo.S
+/test/overlay/test-fdt-overlay.dtbo.S
+/test/overlay/test-fdt-overlay-stacked.dtbo.S
 
 #
 # Generated include files
@@ -83,6 +86,8 @@
 /include/config.h
 /include/config/
 /include/generated/
+/include/bmp_logo.h
+/include/bmp_logo_data.h
 
 # stgit generated dirs
 patches-*
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 0aeda53..2164ad7 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -3,6 +3,7 @@
 variables:
   DEFAULT_TAG: ""
   MIRROR_DOCKER: docker.io
+  SJG_LAB: ""
 
 default:
   tags:
@@ -16,6 +17,7 @@
 stages:
   - testsuites
   - test.py
+  - sjg-lab
   - world build
 
 .buildman_and_testpy_template: &buildman_and_testpy_dfn
@@ -521,3 +523,158 @@
     TEST_PY_TEST_SPEC: "not sleep"
     TEST_PY_ID: "--id qemu"
   <<: *buildman_and_testpy_dfn
+
+.lab_template: &lab_dfn
+  stage: sjg-lab
+  rules:
+    - if: $SJG_LAB == "1"
+      when: always
+    - if: $SJG_LAB != "1"
+      when: manual
+      allow_failure: true
+  tags: [ 'lab' ]
+  script:
+    - if [[ -z "${SJG_LAB}" ]]; then
+        exit 0;
+      fi
+    # Environment:
+    #   SRC  - source tree
+    #   OUT  - output directory for builds
+    - export SRC="$(pwd)"
+    - export OUT="${SRC}/build/${BOARD}"
+    - export PATH=$PATH:~/bin
+    - export PATH=$PATH:/vid/software/devel/ubtest/u-boot-test-hooks/bin
+
+    # Load it on the device
+    - ret=0
+    - echo "role ${ROLE}"
+    - export strategy="-s uboot -e off"
+    - export USE_LABGRID_SJG=1
+    # export verbose="-v"
+    - ${SRC}/test/py/test.py --role ${ROLE} --build-dir "${OUT}"
+        --capture=tee-sys -k "not bootstd" || ret=$?
+    - U_BOOT_BOARD_IDENTITY="${ROLE}" u-boot-test-release || true
+    - if [[ $ret -ne 0 ]]; then
+        exit $ret;
+      fi
+  artifacts:
+    when: always
+    paths:
+      - "build/${BOARD}/test-log.html"
+      - "build/${BOARD}/multiplexed_log.css"
+    expire_in: 1 week
+
+rpi3:
+  variables:
+    ROLE: rpi3
+  <<: *lab_dfn
+
+opi_pc:
+  variables:
+    ROLE: opi_pc
+  <<: *lab_dfn
+
+pcduino3_nano:
+  variables:
+    ROLE: pcduino3_nano
+  <<: *lab_dfn
+
+samus:
+  variables:
+    ROLE: samus
+  <<: *lab_dfn
+
+link:
+  variables:
+    ROLE: link
+  <<: *lab_dfn
+
+jerry:
+  variables:
+    ROLE: jerry
+  <<: *lab_dfn
+
+minnowmax:
+  variables:
+    ROLE: minnowmax
+  <<: *lab_dfn
+
+opi_pc2:
+  variables:
+    ROLE: opi_pc2
+  <<: *lab_dfn
+
+bpi:
+  variables:
+    ROLE: bpi
+  <<: *lab_dfn
+
+rpi2:
+  variables:
+    ROLE: rpi2
+  <<: *lab_dfn
+
+bob:
+  variables:
+    ROLE: bob
+  <<: *lab_dfn
+
+ff3399:
+  variables:
+    ROLE: ff3399
+  <<: *lab_dfn
+
+coral:
+  variables:
+    ROLE: coral
+  <<: *lab_dfn
+
+rpi3z:
+  variables:
+    ROLE: rpi3z
+  <<: *lab_dfn
+
+bbb:
+  variables:
+    ROLE: bbb
+  <<: *lab_dfn
+
+kevin:
+  variables:
+    ROLE: kevin
+  <<: *lab_dfn
+
+pine64:
+  variables:
+    ROLE: pine64
+  <<: *lab_dfn
+
+c4:
+  variables:
+    ROLE: c4
+  <<: *lab_dfn
+
+rpi4:
+  variables:
+    ROLE: rpi4
+  <<: *lab_dfn
+
+rpi0:
+  variables:
+    ROLE: rpi0
+  <<: *lab_dfn
+
+snow:
+  variables:
+    ROLE: snow
+  <<: *lab_dfn
+
+pcduino3:
+  variables:
+    ROLE: pcduino3
+  <<: *lab_dfn
+
+nyan-big:
+  variables:
+    ROLE: nyan-big
+  <<: *lab_dfn
diff --git a/Kconfig b/Kconfig
index bd63fea..2e63896 100644
--- a/Kconfig
+++ b/Kconfig
@@ -744,10 +744,15 @@
 
 config NO_NET
 	bool "No networking support"
+	help
+	  Do not include networking support
 
 config NET
 	bool "Legacy U-Boot networking stack"
 	imply NETDEVICES
+	help
+	  Include networking support with U-Boot's internal implementation of
+	  the TCP/IP protocol stack.
 
 config NET_LWIP
 	bool "Use lwIP for networking stack"
diff --git a/MAINTAINERS b/MAINTAINERS
index 0399ed1..8c6c0c2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -860,6 +860,7 @@
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
 F:	arch/arm/mach-zynqmp/
+F:	drivers/bootcount/bootcount_zynqmp.c
 F:	drivers/clk/clk_zynqmp.c
 F:	driver/firmware/firmware-zynqmp.c
 F:	drivers/fpga/zynqpl.c
@@ -1551,6 +1552,7 @@
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
 F:	arch/sandbox/
+F:	configs/sandbox*
 F:	doc/arch/sandbox.rst
 F:	drivers/*/*sandbox*.c
 F:	include/dt-bindings/*/sandbox*.h
@@ -1697,6 +1699,7 @@
 F:	cmd/tpm*
 F:	drivers/tpm/
 F:	include/tpm*
+F:	lib/tpm*
 
 TQ GROUP
 #M:	Martin Krause <martin.krause@tq-systems.de>
diff --git a/Makefile b/Makefile
index 81b73a1..22953bd 100644
--- a/Makefile
+++ b/Makefile
@@ -3,7 +3,7 @@
 VERSION = 2025
 PATCHLEVEL = 01
 SUBLEVEL =
-EXTRAVERSION = -rc2
+EXTRAVERSION = -rc3
 NAME =
 
 # *DOCUMENTATION*
@@ -21,7 +21,7 @@
 ifeq ("", "$(CROSS_COMPILE)")
   MK_ARCH="${shell uname -m}"
 else
-  MK_ARCH="${shell echo $(CROSS_COMPILE) | sed -n 's/^[[:space:]]*\([^\/]*\/\)*\([^-]*\)-[^[:space:]]*/\2/p'}"
+  MK_ARCH="${shell echo $(CROSS_COMPILE) | sed -n 's/^\(ccache\)\?[[:space:]]*\([^\/]*\/\)*\([^-]*\)-[^[:space:]]*/\3/p'}"
 endif
 unexport HOST_ARCH
 ifeq ("x86_64", $(MK_ARCH))
@@ -1398,7 +1398,8 @@
                 --toolpath $(objtree)/tools \
 		$(if $(BINMAN_VERBOSE),-v$(BINMAN_VERBOSE)) \
 		build -u -d u-boot.dtb -O . -m \
-		--allow-missing $(if $(BINMAN_ALLOW_MISSING),--ignore-missing) \
+		--allow-missing --fake-ext-blobs \
+		$(if $(BINMAN_ALLOW_MISSING),--ignore-missing) \
 		-I . -I $(srctree) -I $(srctree)/board/$(BOARDDIR) \
 		$(foreach f,$(of_list_dirs),-I $(f)) -a of-list=$(of_list) \
 		$(foreach f,$(BINMAN_INDIRS),-I $(f)) \
diff --git a/arch/Kconfig b/arch/Kconfig
index c39efb4..6258788 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -8,6 +8,11 @@
 config HAVE_ARCH_IOREMAP
 	bool
 
+config HAVE_SETJMP
+	bool
+	help
+	 The architecture supports setjmp() and longjmp().
+
 config SUPPORT_BIG_ENDIAN
 	bool
 
@@ -73,6 +78,7 @@
 
 config ARM
 	bool "ARM architecture"
+	select HAVE_SETJMP
 	select ARCH_SUPPORTS_LTO
 	select CREATE_ARCH_SYMLINK
 	select HAVE_PRIVATE_LIBGCC if !ARM64
@@ -129,6 +135,7 @@
 config RISCV
 	bool "RISC-V architecture"
 	select CREATE_ARCH_SYMLINK
+	select HAVE_SETJMP
 	select SUPPORT_ACPI
 	select SUPPORT_LITTLE_ENDIAN
 	select SUPPORT_OF_CONTROL
@@ -154,6 +161,7 @@
 
 config SANDBOX
 	bool "Sandbox"
+	select HAVE_SETJMP
 	select ARCH_SUPPORTS_LTO
 	select BOARD_LATE_INIT
 	select BZIP2
@@ -249,6 +257,7 @@
 
 config X86
 	bool "x86 architecture"
+	select HAVE_SETJMP
 	select SUPPORT_SPL
 	select SUPPORT_TPL
 	select SUPPORT_LITTLE_ENDIAN
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 042282f..d81a9f9 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -935,8 +935,7 @@
 	fsl-imx8qxp-ai_ml.dtb \
 	fsl-imx8qxp-colibri.dtb \
 	fsl-imx8qxp-mek.dtb \
-	imx8-deneb.dtb \
-	imx8-giedi.dtb
+	imx8-capricorn-cxg3.dtb \
 
 dtb-$(CONFIG_ARCH_IMX8ULP) += \
 	imx8ulp-evk.dtb
diff --git a/arch/arm/dts/imx8-capricorn-cxg3.dts b/arch/arm/dts/imx8-capricorn-cxg3.dts
new file mode 100644
index 0000000..2f85975
--- /dev/null
+++ b/arch/arm/dts/imx8-capricorn-cxg3.dts
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Siemens AG
+ */
+
+#include "imx8-capricorn.dtsi"
+
+/ {
+	model = "Siemens CXG3";
+
+	leds_default: leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_leds>;
+
+		run {
+			label = "run";
+			gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		flt {
+			label = "flt";
+			gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		svc {
+			label = "svc";
+			gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		com1_tx {
+			label = "com1-tx";
+			gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		com1_rx {
+			label = "com1-rx";
+			gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		com2_tx {
+			label = "com2-tx";
+			gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		com2_rx {
+			label = "com2-rx";
+			gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		cloud {
+			label = "cloud";
+			gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		wlan {
+			label = "wlan";
+			gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		apps {
+			label = "apps";
+			gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		dbg2 {
+			label = "dbg2";
+			gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		dbg3 {
+			label = "dbg3";
+			gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		dbg4 {
+			label = "dbg4";
+			gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&iomuxc {
+	pinctrl-0 = <&pinctrl_gpio_keys>;
+
+	muxcgrp: imx8qxp-som {
+		pinctrl_gpio_leds: gpioledsgrp {
+			fsl,pins = <
+			SC_P_ESAI0_FST_LSIO_GPIO0_IO01		0x06000021
+			SC_P_ESAI0_TX0_LSIO_GPIO0_IO04		0x06000021
+			SC_P_SAI0_TXC_LSIO_GPIO0_IO26		0x06000021
+			SC_P_SAI1_RXD_LSIO_GPIO0_IO29		0x06000021
+			SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17	0x06000021
+			SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18	0x06000021
+			SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17	0x06000021
+			SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18	0x06000021
+			SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19	0x06000021
+			SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03	0x06000021
+			SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00	0x06000021
+			SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01	0x06000021
+			SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09	0x06000021
+			>;
+		};
+	};
+
+	pinctrl_gpio_keys: gpiokeysgrp {
+		fsl,pins = <
+		SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 0x06000021
+		>;
+	};
+};
diff --git a/arch/arm/dts/imx8-capricorn-u-boot.dtsi b/arch/arm/dts/imx8-capricorn-u-boot.dtsi
new file mode 100644
index 0000000..ad5309b
--- /dev/null
+++ b/arch/arm/dts/imx8-capricorn-u-boot.dtsi
@@ -0,0 +1,138 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Siemens AG
+ */
+
+#include "imx8qxp-u-boot.dtsi"
+
+&{/imx8qx-pm} {
+	bootph-all;
+};
+
+&A35_0 {
+        bootph-all;
+};
+
+&mu {
+	bootph-all;
+};
+
+&clk {
+	bootph-all;
+};
+
+&iomuxc {
+	bootph-all;
+};
+
+&pd_lsio {
+	bootph-all;
+};
+
+&pd_lsio_gpio0 {
+	bootph-all;
+};
+
+&pd_lsio_gpio1 {
+	bootph-all;
+};
+
+&pd_lsio_gpio2 {
+	bootph-all;
+};
+
+&pd_lsio_gpio3 {
+	bootph-all;
+};
+
+&pd_lsio_gpio4 {
+	bootph-all;
+};
+
+&pd_lsio_gpio5 {
+	bootph-all;
+};
+
+&pd_lsio_gpio6 {
+	bootph-all;
+};
+
+&pd_lsio_gpio7 {
+	bootph-all;
+};
+
+&pd_dma {
+	bootph-all;
+};
+
+&pd_dma_lpuart0 {
+	bootph-all;
+};
+
+&pd_dma_lpuart2 {
+	bootph-all;
+};
+
+&pd_conn {
+	bootph-all;
+};
+
+&pd_conn_sdch0 {
+	bootph-all;
+};
+
+&pd_conn_sdch1 {
+	bootph-all;
+};
+
+&pd_conn_sdch2 {
+	bootph-all;
+};
+
+&gpio0 {
+	bootph-all;
+};
+
+&gpio1 {
+	bootph-all;
+};
+
+&gpio2 {
+	bootph-all;
+};
+
+&gpio3 {
+	bootph-all;
+};
+
+&gpio4 {
+	bootph-all;
+};
+
+&gpio5 {
+	bootph-all;
+};
+
+&gpio6 {
+	bootph-all;
+};
+
+&gpio7 {
+	bootph-all;
+};
+
+&lpuart0 {
+	bootph-all;
+};
+
+&lpuart2 {
+	bootph-all;
+};
+
+&usdhc1 {
+	bootph-all;
+};
+
+&usdhc2 {
+	bootph-all;
+};
diff --git a/arch/arm/dts/imx8qxp-capricorn.dtsi b/arch/arm/dts/imx8-capricorn.dtsi
similarity index 64%
rename from arch/arm/dts/imx8qxp-capricorn.dtsi
rename to arch/arm/dts/imx8-capricorn.dtsi
index db5653e..3734a9d 100644
--- a/arch/arm/dts/imx8qxp-capricorn.dtsi
+++ b/arch/arm/dts/imx8-capricorn.dtsi
@@ -9,124 +9,25 @@
 /dts-v1/;
 
 #include "fsl-imx8qxp.dtsi"
-#include "imx8qxp-capricorn-u-boot.dtsi"
+#include "imx8-capricorn-u-boot.dtsi"
 
 / {
-	model = "Siemens Giedi";
-	compatible = "siemens,capricorn", "fsl,imx8qxp";
-
 	chosen {
 		bootargs = "console=ttyLP2,115200 earlycon=lpuart32,0x5a080000,115200";
 		stdout-path = &lpuart2;
 	};
 
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_gpio_leds>;
-
-		run {
-			label = "run";
-			gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-
-		flt {
-			label = "flt";
-			gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-
-		svc {
-			label = "svc";
-			gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-
-		com1_tx {
-			label = "com1-tx";
-			gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-
-		com1_rx {
-			label = "com1-rx";
-			gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-
-		com2_tx {
-			label = "com2-tx";
-			gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-
-		com2_rx {
-			label = "com2-rx";
-			gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-
-		cloud {
-			label = "cloud";
-			gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-
-		wlan {
-			label = "wlan";
-			gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-
-		dbg1 {
-			label = "dbg1";
-			gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-
-		dbg2 {
-			label = "dbg2";
-			gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-
-		dbg3 {
-			label = "dbg3";
-			gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-
-		dbg4 {
-			label = "dbg4";
-			gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
+	/* create device for u-boot wdt command */
+	scu-wdt {
+		compatible = "siemens,scu-wdt";
 	};
+
 };
 
 &iomuxc {
 	pinctrl-names = "default";
 
 	muxcgrp: imx8qxp-som {
-		pinctrl_gpio_leds: gpioledsgrp {
-			fsl,pins = <
-			SC_P_ESAI0_FST_LSIO_GPIO0_IO01		0x06000021
-			SC_P_ESAI0_TX0_LSIO_GPIO0_IO04		0x06000021
-			SC_P_SAI0_TXC_LSIO_GPIO0_IO26		0x06000021
-			SC_P_SAI1_RXD_LSIO_GPIO0_IO29		0x06000021
-			SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17	0x06000021
-			SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18	0x06000021
-			SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17	0x06000021
-			SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18	0x06000021
-			SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19	0x06000021
-			SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03	0x06000021
-			SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00	0x06000021
-			SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01	0x06000021
-			SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09	0x06000021
-			>;
-		};
-
 		pinctrl_lpi2c0: lpi2c0grp {
 			fsl,pins = <
 			SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL	0x0C000020
diff --git a/arch/arm/dts/imx8-deneb.dts b/arch/arm/dts/imx8-deneb.dts
deleted file mode 100644
index 04c764a..0000000
--- a/arch/arm/dts/imx8-deneb.dts
+++ /dev/null
@@ -1,10 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2019 Siemens AG
- */
-
-#include "imx8qxp-capricorn.dtsi"
-
-/ {
-	model = "Siemens Deneb";
-};
diff --git a/arch/arm/dts/imx8-giedi.dts b/arch/arm/dts/imx8-giedi.dts
deleted file mode 100644
index 0dbfef2..0000000
--- a/arch/arm/dts/imx8-giedi.dts
+++ /dev/null
@@ -1,10 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2019 Siemens AG
- */
-
-#include "imx8qxp-capricorn.dtsi"
-
-/ {
-	model = "Siemens Giedi";
-};
diff --git a/arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi b/arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi
index 516e52e..512dbc9 100644
--- a/arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi
@@ -14,6 +14,10 @@
 	};
 };
 
+&pinctrl_i2c1 {
+	bootph-pre-ram;
+};
+
 &pinctrl_uart3 {
 	bootph-pre-ram;
 };
@@ -54,6 +58,10 @@
 	bootph-pre-ram;
 };
 
+&i2c1 {
+	bootph-pre-ram;
+};
+
 &uart3 {
 	bootph-pre-ram;
 };
diff --git a/arch/arm/dts/imx8mn-u-boot.dtsi b/arch/arm/dts/imx8mn-u-boot.dtsi
index 6875c6d..6d80d85 100644
--- a/arch/arm/dts/imx8mn-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-u-boot.dtsi
@@ -68,6 +68,11 @@
 	bootph-all;
 };
 
+&osc_32k {
+	bootph-pre-ram;
+	bootph-all;
+};
+
 #ifdef CONFIG_FSL_CAAM
 &sec_jr0 {
 	bootph-pre-ram;
diff --git a/arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi b/arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi
deleted file mode 100644
index cba5618..0000000
--- a/arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi
+++ /dev/null
@@ -1,135 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2019 Siemens AG
- */
-
-#include "imx8qxp-u-boot.dtsi"
-
-&{/imx8qx-pm} {
-
-	bootph-pre-ram;
-};
-
-&mu {
-	bootph-pre-ram;
-};
-
-&clk {
-	bootph-pre-ram;
-};
-
-&iomuxc {
-	bootph-pre-ram;
-};
-
-&pd_lsio {
-	bootph-pre-ram;
-};
-
-&pd_lsio_gpio0 {
-	bootph-pre-ram;
-};
-
-&pd_lsio_gpio1 {
-	bootph-pre-ram;
-};
-
-&pd_lsio_gpio2 {
-	bootph-pre-ram;
-};
-
-&pd_lsio_gpio3 {
-	bootph-pre-ram;
-};
-
-&pd_lsio_gpio4 {
-	bootph-pre-ram;
-};
-
-&pd_lsio_gpio5 {
-	bootph-pre-ram;
-};
-
-&pd_lsio_gpio6 {
-	bootph-pre-ram;
-};
-
-&pd_lsio_gpio7 {
-	bootph-pre-ram;
-};
-
-&pd_dma {
-	bootph-pre-ram;
-};
-
-&pd_dma_lpuart0 {
-	bootph-pre-ram;
-};
-
-&pd_dma_lpuart2 {
-	bootph-pre-ram;
-};
-
-&pd_conn {
-	bootph-pre-ram;
-};
-
-&pd_conn_sdch0 {
-	bootph-pre-ram;
-};
-
-&pd_conn_sdch1 {
-	bootph-pre-ram;
-};
-
-&pd_conn_sdch2 {
-	bootph-pre-ram;
-};
-
-&gpio0 {
-	bootph-pre-ram;
-};
-
-&gpio1 {
-	bootph-pre-ram;
-};
-
-&gpio2 {
-	bootph-pre-ram;
-};
-
-&gpio3 {
-	bootph-pre-ram;
-};
-
-&gpio4 {
-	bootph-pre-ram;
-};
-
-&gpio5 {
-	bootph-pre-ram;
-};
-
-&gpio6 {
-	bootph-pre-ram;
-};
-
-&gpio7 {
-	bootph-pre-ram;
-};
-
-&lpuart0 {
-	bootph-pre-ram;
-};
-
-&lpuart2 {
-	bootph-pre-ram;
-};
-
-&usdhc1 {
-	bootph-pre-ram;
-};
-
-&usdhc2 {
-	bootph-pre-ram;
-};
diff --git a/arch/arm/dts/imx8qxp-u-boot.dtsi b/arch/arm/dts/imx8qxp-u-boot.dtsi
index 62791c3..8058caa 100644
--- a/arch/arm/dts/imx8qxp-u-boot.dtsi
+++ b/arch/arm/dts/imx8qxp-u-boot.dtsi
@@ -120,6 +120,7 @@
 		};
 	};
 
+#ifdef CONFIG_XPL_BUILD
 	imx-boot {
 		filename = "flash.bin";
 		pad-byte = <0x00>;
@@ -130,4 +131,5 @@
 			type = "blob-ext";
 		};
 	};
+#endif
 };
diff --git a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
index 6897c91..0c3ca29 100644
--- a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
+++ b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
@@ -2,15 +2,22 @@
 /*
  * Copyright (C) 2023 PHYTEC Messtechnik GmbH
  * Christoph Stoidner <c.stoidner@phytec.de>
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
  *
  * Product homepage:
- * phyBOARD-Segin carrier board is reused for the i.MX93 design.
- * https://www.phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6ul/
+   https://www.phytec.de/produkte/system-on-modules/phycore-imx-91-93/
  */
 
 #include "imx93-u-boot.dtsi"
 
 / {
+	/*
+	 * The phyCORE-i.MX93 u-boot uses the imx93-phyboard-segin.dts as
+	 * reference, but does only make use of its SoM (phyCORE) contained
+	 * periphery.
+	 */
+	model = "PHYTEC phyCORE-i.MX93";
+
 	wdt-reboot {
 		compatible = "wdt-reboot";
 		wdt = <&wdog3>;
@@ -139,6 +146,13 @@
 &usdhc1 {
 	bootph-pre-ram;
 	bootph-some-ram;
+	/*
+	 * Remove pinctrl assignments once they are added to imx93-phycore-som.dtsi
+	 */
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 };
 
 &usdhc2 {
@@ -215,6 +229,48 @@
 			MX93_PAD_ENET2_RD3__GPIO4_IO27			0x31e
 		>;
 	};
+
+	/*
+	 * Remove pinctrl_usdhc1_100mhz and pinctrl_usdhc1_200mhz once they
+	 * are added to imx93-phycore-som.dtsi
+	 */
+	/* need to config the SION for data and cmd pad, refer to ERR052021 */
+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+		bootph-pre-ram;
+		bootph-some-ram;
+		fsl,pins = <
+			MX93_PAD_SD1_CLK__USDHC1_CLK		0x17be
+			MX93_PAD_SD1_CMD__USDHC1_CMD		0x4000139e
+			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x4000138e
+			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x4000139e
+			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x400013be
+			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x4000139e
+			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x4000139e
+			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x4000139e
+			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x4000139e
+			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x4000139e
+			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x179e
+		>;
+	};
+
+	/* need to config the SION for data and cmd pad, refer to ERR052021 */
+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+		bootph-pre-ram;
+		bootph-some-ram;
+		fsl,pins = <
+			MX93_PAD_SD1_CLK__USDHC1_CLK		0x17be
+			MX93_PAD_SD1_CMD__USDHC1_CMD		0x4000139e
+			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x4000139e
+			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x400013be
+			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x400013be
+			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x400013be
+			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x400013be
+			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x400013be
+			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x400013be
+			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x400013be
+			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x179e
+		>;
+	};
 };
 
 &lpi2c3 {
@@ -305,4 +361,13 @@
 			};
 		};
 	};
+
+	eeprom@50 {
+		bootph-pre-ram;
+		bootph-some-ram;
+		compatible = "atmel,24c32";
+		reg = <0x50>;
+		pagesize = <32>;
+		vcc-supply = <&buck4>;
+	};
 };
diff --git a/arch/arm/dts/k3-am625-phycore-som-binman.dtsi b/arch/arm/dts/k3-am625-phycore-som-binman.dtsi
index 0961ca6..63f2eed 100644
--- a/arch/arm/dts/k3-am625-phycore-som-binman.dtsi
+++ b/arch/arm/dts/k3-am625-phycore-som-binman.dtsi
@@ -301,6 +301,54 @@
 					description = "U-Boot for phyCORE-AM62x";
 				};
 
+				som-no-rtc {
+					description = "k3-am6xx-phycore-disable-rtc";
+					type = "flat_dt";
+					compression = "none";
+					load = <0x8F000000>;
+					arch = "arm";
+
+					blob-ext {
+						filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-rtc.dtbo";
+					};
+				};
+
+				som-no-spi {
+					description = "k3-am6xx-phycore-disable-spi-nor";
+					type = "flat_dt";
+					compression = "none";
+					load = <0x8F001000>;
+					arch = "arm";
+
+					blob-ext {
+						filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-spi-nor.dtbo";
+					};
+				};
+
+				som-no-eth {
+					description = "k3-am6xx-phycore-disable-eth-phy";
+					type = "flat_dt";
+					compression = "none";
+					load = <0x8F002000>;
+					arch = "arm";
+
+					blob-ext {
+						filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-eth-phy.dtbo";
+					};
+				};
+
+				som-qspi {
+					description = "k3-am6xx-phycore-qspi-nor";
+					type = "flat_dt";
+					compression = "none";
+					load = <0x8F003000>;
+					arch = "arm";
+
+					blob-ext {
+						filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-qspi-nor.dtbo";
+					};
+				};
+
 				fdt-0 {
 					description = "k3-am625-phyboard-lyra-rdk";
 					type = "flat_dt";
@@ -325,7 +373,11 @@
 				conf-0 {
 					description = "k3-am625-phyboard-lyra-rdk";
 					firmware = "uboot";
-					loadables = "uboot";
+					loadables = "uboot",
+						    "som-no-rtc",
+						    "som-no-spi",
+						    "som-no-eth",
+						    "som-qspi";
 					fdt = "fdt-0";
 				};
 			};
diff --git a/arch/arm/dts/k3-am642-phycore-som-binman.dtsi b/arch/arm/dts/k3-am642-phycore-som-binman.dtsi
index dd09670..88d6c40 100644
--- a/arch/arm/dts/k3-am642-phycore-som-binman.dtsi
+++ b/arch/arm/dts/k3-am642-phycore-som-binman.dtsi
@@ -344,6 +344,54 @@
 					description = "U-Boot for AM64 board";
 				};
 
+				som-no-rtc {
+					description = "k3-am6xx-phycore-disable-rtc";
+					type = "flat_dt";
+					compression = "none";
+					load = <0x8F000000>;
+					arch = "arm";
+
+					blob-ext {
+						filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-rtc.dtbo";
+					};
+				};
+
+				som-no-spi {
+					description = "k3-am6xx-phycore-disable-spi-nor";
+					type = "flat_dt";
+					compression = "none";
+					load = <0x8F001000>;
+					arch = "arm";
+
+					blob-ext {
+						filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-spi-nor.dtbo";
+					};
+				};
+
+				som-no-eth {
+					description = "k3-am6xx-phycore-disable-eth-phy";
+					type = "flat_dt";
+					compression = "none";
+					load = <0x8F002000>;
+					arch = "arm";
+
+					blob-ext {
+						filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-eth-phy.dtbo";
+					};
+				};
+
+				som-qspi {
+					description = "k3-am6xx-phycore-qspi-nor";
+					type = "flat_dt";
+					compression = "none";
+					load = <0x8F003000>;
+					arch = "arm";
+
+					blob-ext {
+						filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-qspi-nor.dtbo";
+					};
+				};
+
 				fdt-0 {
 					description = "k3-am642-phyboard-electra-rdk";
 					type = "flat_dt";
@@ -368,7 +416,11 @@
 				conf-0 {
 					description = "k3-am642-phyboard-electra-rdk";
 					firmware = "uboot";
-					loadables = "uboot";
+					loadables = "uboot",
+						    "som-no-rtc",
+						    "som-no-spi",
+						    "som-no-eth",
+						    "som-qspi";
 					fdt = "fdt-0";
 				};
 			};
diff --git a/arch/arm/dts/stm32mp13xx-dhcor-som.dtsi b/arch/arm/dts/stm32mp13xx-dhcor-som.dtsi
deleted file mode 100644
index ddad649..0000000
--- a/arch/arm/dts/stm32mp13xx-dhcor-som.dtsi
+++ /dev/null
@@ -1,308 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) 2024 Marek Vasut <marex@denx.de>
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/mfd/st,stpmic1.h>
-#include <dt-bindings/regulator/st,stm32mp13-regulator.h>
-#include "stm32mp13-pinctrl.dtsi"
-
-/ {
-	model = "DH electronics STM32MP13xx DHCOR SoM";
-	compatible = "dh,stm32mp131a-dhcor-som",
-		     "st,stm32mp131";
-
-	aliases {
-		mmc0 = &sdmmc2;
-		mmc1 = &sdmmc1;
-		serial0 = &uart4;
-		serial1 = &uart7;
-		rtc0 = &rv3032;
-		spi0 = &qspi;
-	};
-
-	memory@c0000000 {
-		device_type = "memory";
-		reg = <0xc0000000 0x20000000>;
-	};
-
-	reserved-memory {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		optee@dd000000 {
-			reg = <0xdd000000 0x3000000>;
-			no-map;
-		};
-	};
-
-	sdio_pwrseq: sdio-pwrseq {
-		compatible = "mmc-pwrseq-simple";
-		reset-gpios = <&gpiof 12 GPIO_ACTIVE_LOW>;
-	};
-
-	vin: vin {
-		compatible = "regulator-fixed";
-		regulator-name = "vin";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		regulator-always-on;
-	};
-};
-
-&i2c3 {
-	i2c-scl-rising-time-ns = <96>;
-	i2c-scl-falling-time-ns = <3>;
-	clock-frequency = <400000>;
-	status = "okay";
-	/* spare dmas for other usage */
-	/delete-property/dmas;
-	/delete-property/dma-names;
-
-	pmic: stpmic@33 {
-		compatible = "st,stpmic1";
-		reg = <0x33>;
-		interrupts-extended = <&gpioi 3 IRQ_TYPE_EDGE_FALLING>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		status = "okay";
-
-		regulators {
-			compatible = "st,stpmic1-regulators";
-
-			ldo1-supply = <&vin>;
-			ldo2-supply = <&vin>;
-			ldo3-supply = <&vin>;
-			ldo4-supply = <&vin>;
-			ldo5-supply = <&vin>;
-			ldo6-supply = <&vin>;
-			pwr_sw1-supply = <&bst_out>;
-			pwr_sw2-supply = <&bst_out>;
-
-			vddcpu: buck1 { /* VDD_CPU_1V2 */
-				regulator-name = "vddcpu";
-				regulator-min-microvolt = <1250000>;
-				regulator-max-microvolt = <1250000>;
-				regulator-always-on;
-				regulator-initial-mode = <0>;
-				regulator-over-current-protection;
-			};
-
-			vdd_ddr: buck2 { /* VDD_DDR_1V35 */
-				regulator-name = "vdd_ddr";
-				regulator-min-microvolt = <1350000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-always-on;
-				regulator-initial-mode = <0>;
-				regulator-over-current-protection;
-			};
-
-			vdd: buck3 { /* VDD_3V3_1V8 */
-				regulator-name = "vdd";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-always-on;
-				regulator-initial-mode = <0>;
-				regulator-over-current-protection;
-			};
-
-			vddcore: buck4 { /* VDD_CORE_1V2 */
-				regulator-name = "vddcore";
-				regulator-min-microvolt = <1250000>;
-				regulator-max-microvolt = <1250000>;
-				regulator-always-on;
-				regulator-initial-mode = <0>;
-				regulator-over-current-protection;
-			};
-
-			vdd_adc: ldo1 { /* VDD_ADC_1V8 */
-				regulator-name = "vdd_adc";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				interrupts = <IT_CURLIM_LDO1 0>;
-			};
-
-			vdd_ldo2: ldo2 { /* LDO2_OUT_1V8 */
-				regulator-name = "vdd_ldo2";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				interrupts = <IT_CURLIM_LDO2 0>;
-			};
-
-			vdd_ldo3: ldo3 { /* LDO3_OUT */
-				regulator-name = "vdd_ldo3";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				interrupts = <IT_CURLIM_LDO3 0>;
-			};
-
-			vdd_usb: ldo4 { /* VDD_USB_3V3 */
-				regulator-name = "vdd_usb";
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				interrupts = <IT_CURLIM_LDO4 0>;
-			};
-
-			vdd_sd: ldo5 { /* VDD_SD_3V3_1V8 */
-				regulator-name = "vdd_sd";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
-				interrupts = <IT_CURLIM_LDO5 0>;
-			};
-
-			vdd_sd2: ldo6 { /* VDD_SD2_3V3_1V8 */
-				regulator-name = "vdd_sd2";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
-				interrupts = <IT_CURLIM_LDO6 0>;
-			};
-
-			vref_ddr: vref_ddr { /* VREF_DDR_0V675 */
-				regulator-name = "vref_ddr";
-				regulator-always-on;
-			};
-
-			bst_out: boost { /* BST_OUT_5V2 */
-				regulator-name = "bst_out";
-			};
-
-			vbus_otg: pwr_sw1 {
-				regulator-name = "vbus_otg";
-				interrupts = <IT_OCP_OTG 0>;
-			};
-
-			vbus_sw: pwr_sw2 {
-				regulator-name = "vbus_sw";
-				interrupts = <IT_OCP_SWOUT 0>;
-				regulator-active-discharge = <1>;
-			};
-		};
-
-		onkey {
-			compatible = "st,stpmic1-onkey";
-			interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>;
-			interrupt-names = "onkey-falling", "onkey-rising";
-			status = "okay";
-		};
-
-		watchdog {
-			compatible = "st,stpmic1-wdt";
-			status = "disabled";
-		};
-	};
-
-	eeprom0: eeprom@50 {
-		compatible = "atmel,24c256";	/* ST M24256 */
-		reg = <0x50>;
-		pagesize = <64>;
-	};
-
-	rv3032: rtc@51 {
-		compatible = "microcrystal,rv3032";
-		reg = <0x51>;
-		interrupts-extended = <&gpioi 0 IRQ_TYPE_EDGE_FALLING>;
-	};
-};
-
-&iwdg2 {
-	timeout-sec = <32>;
-	status = "okay";
-};
-
-&qspi {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&qspi_clk_pins_a
-		     &qspi_bk1_pins_a
-		     &qspi_cs1_pins_a>;
-	pinctrl-1 = <&qspi_clk_sleep_pins_a
-		     &qspi_bk1_sleep_pins_a
-		     &qspi_cs1_sleep_pins_a>;
-	#address-cells = <1>;
-	#size-cells = <0>;
-	status = "okay";
-
-	flash0: flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-rx-bus-width = <4>;
-		spi-max-frequency = <108000000>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-	};
-};
-
-/* Console UART */
-&uart4 {
-	pinctrl-names = "default", "sleep", "idle";
-	pinctrl-0 = <&uart4_pins_b>;
-	pinctrl-1 = <&uart4_sleep_pins_b>;
-	pinctrl-2 = <&uart4_idle_pins_b>;
-	/delete-property/dmas;
-	/delete-property/dma-names;
-	status = "okay";
-};
-
-/* Bluetooth */
-&uart7 {
-	pinctrl-names = "default", "sleep", "idle";
-	pinctrl-0 = <&uart7_pins_a>;
-	pinctrl-1 = <&uart7_sleep_pins_a>;
-	pinctrl-2 = <&uart7_idle_pins_a>;
-	uart-has-rtscts;
-	status = "okay";
-
-	bluetooth {
-		compatible = "infineon,cyw43439-bt", "brcm,bcm4329-bt";
-		max-speed = <3000000>;
-		device-wakeup-gpios = <&gpiog 9 GPIO_ACTIVE_HIGH>;
-		shutdown-gpios = <&gpioi 2 GPIO_ACTIVE_HIGH>;
-	};
-};
-
-/* SDIO WiFi */
-&sdmmc1 {
-	pinctrl-names = "default", "opendrain", "sleep";
-	pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>;
-	pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>;
-	pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
-	bus-width = <4>;
-	cap-power-off-card;
-	keep-power-in-suspend;
-	non-removable;
-	st,neg-edge;
-	vmmc-supply = <&vdd>;
-	mmc-pwrseq = <&sdio_pwrseq>;
-	status = "okay";
-
-	#address-cells = <1>;
-	#size-cells = <0>;
-
-	brcmf: bcrmf@1 {	/* muRata 1YN */
-		reg = <1>;
-		compatible = "infineon,cyw43439-fmac", "brcm,bcm4329-fmac";
-		interrupt-parent = <&gpioe>;
-		interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
-		interrupt-names = "host-wake";
-	};
-};
-
-/* eMMC */
-&sdmmc2 {
-	pinctrl-names = "default", "opendrain", "sleep";
-	pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a &sdmmc2_clk_pins_a>;
-	pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a &sdmmc2_clk_pins_a>;
-	pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
-	bus-width = <8>;
-	mmc-ddr-3_3v;
-	no-sd;
-	no-sdio;
-	non-removable;
-	st,neg-edge;
-	vmmc-supply = <&vdd>;
-	vqmmc-supply = <&vdd>;
-	status = "okay";
-};
diff --git a/arch/arm/dts/stm32mp153c-dhcor-drc-compact.dts b/arch/arm/dts/stm32mp153c-dhcor-drc-compact.dts
deleted file mode 100644
index c8b9818..0000000
--- a/arch/arm/dts/stm32mp153c-dhcor-drc-compact.dts
+++ /dev/null
@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
-/*
- * Copyright (C) 2022 Marek Vasut <marex@denx.de>
- *
- * DHCOR STM32MP1 variant:
- * DHCR-STM32MP153C-C065-R051-V33-SPI-I-01LG
- * DHCOR PCB number: 586-100 or newer
- * DRC Compact PCB number: 627-100 or newer
- */
-
-/dts-v1/;
-
-#include "stm32mp153.dtsi"
-#include "stm32mp15xc.dtsi"
-#include "stm32mp15xx-dhcor-som.dtsi"
-#include "stm32mp15xx-dhcor-drc-compact.dtsi"
-
-/ {
-	model = "DH electronics STM32MP153C DHCOR DRC Compact";
-	compatible = "dh,stm32mp153c-dhcor-drc-compact",
-		     "dh,stm32mp153c-dhcor-som",
-		     "st,stm32mp153";
-};
-
-&m_can1 {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&m_can1_pins_c>;
-	pinctrl-1 = <&m_can1_sleep_pins_c>;
-	status = "okay";
-};
diff --git a/arch/arm/dts/stm32mp157a-dhcor-avenger96.dts b/arch/arm/dts/stm32mp157a-dhcor-avenger96.dts
deleted file mode 100644
index 2e3c9fb..0000000
--- a/arch/arm/dts/stm32mp157a-dhcor-avenger96.dts
+++ /dev/null
@@ -1,38 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
-/*
- * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
- * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- * Copyright (C) 2020 Marek Vasut <marex@denx.de>
- *
- * DHCOR STM32MP1 variant:
- * DHCR-STM32MP157A-C065-R102-V18-SPI-C-01LG
- * DHCOR PCB number: 586-100 or newer
- * Avenger96 PCB number: 588-200 or newer
- */
-
-/dts-v1/;
-
-#include "stm32mp157.dtsi"
-#include "stm32mp15xc.dtsi"
-#include "stm32mp15xx-dhcor-som.dtsi"
-#include "stm32mp15xx-dhcor-avenger96.dtsi"
-
-/ {
-	model = "Arrow Electronics STM32MP157A Avenger96 board";
-	compatible = "arrow,stm32mp157a-avenger96", "dh,stm32mp157a-dhcor-som",
-		     "st,stm32mp157";
-};
-
-&m_can1 {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&m_can1_pins_b>;
-	pinctrl-1 = <&m_can1_sleep_pins_b>;
-	status = "disabled";
-};
-
-&m_can2 {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&m_can2_pins_a>;
-	pinctrl-1 = <&m_can2_sleep_pins_a>;
-	status = "disabled";
-};
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
index dd67e96..4c334e4 100644
--- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
@@ -12,6 +12,7 @@
 
 / {
 	aliases {
+		eeprom0 = &eeprom0;
 		i2c1 = &i2c2;
 		i2c3 = &i2c4;
 		i2c4 = &i2c5;
@@ -19,15 +20,14 @@
 		mmc1 = &sdmmc2;
 		spi0 = &qspi;
 		usb0 = &usbotg_hs;
-		eeprom0 = &eeprom0;
 	};
 
 	config {
-		u-boot,boot-led = "heartbeat";
-		u-boot,error-led = "error";
-		dh,som-coding-gpios = <&gpiof 12 0>, <&gpiof 13 0>, <&gpiof 15 0>;
 		dh,ddr3-coding-gpios = <&gpioz 6 0>, <&gpioz 7 0>;
 		dh,mac-coding-gpios = <&gpioc 3 0>;
+		dh,som-coding-gpios = <&gpiof 12 0>, <&gpiof 13 0>, <&gpiof 15 0>;
+		u-boot,boot-led = "heartbeat";
+		u-boot,error-led = "error";
 	};
 };
 
@@ -36,17 +36,6 @@
 	/delete-property/ st,eth-ref-clk-sel;
 };
 
-&ethernet0_rmii_pins_a {
-	pins1 {
-		pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
-			 <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
-			 <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
-			 <STM32_PINMUX('A', 1, AF11)>,  /* ETH1_RMII_REF_CLK */
-			 <STM32_PINMUX('A', 2, AF11)>,  /* ETH1_MDIO */
-			 <STM32_PINMUX('C', 1, AF11)>;  /* ETH1_MDC */
-	};
-};
-
 &i2c4 {
 	bootph-all;
 	bootph-pre-ram;
@@ -62,36 +51,6 @@
 	};
 };
 
-&phy0 {
-	/delete-property/ reset-gpios;
-};
-
-&pinctrl {
-	mco2_pins_a: mco2-0 {
-		pins {
-			pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */
-			bias-disable;
-			drive-push-pull;
-			slew-rate = <2>;
-		};
-	};
-
-	mco2_sleep_pins_a: mco2-sleep-0 {
-		pins {
-			pinmux = <STM32_PINMUX('G', 2, ANALOG)>; /* MCO2 */
-		};
-	};
-};
-
-&pmic {
-	bootph-all;
-	bootph-pre-ram;
-
-	regulators {
-		bootph-pre-ram;
-	};
-};
-
 &flash0 {
 	bootph-pre-ram;
 
@@ -123,6 +82,19 @@
 	};
 };
 
+&phy0 {
+	/delete-property/ reset-gpios;
+};
+
+&pmic {
+	bootph-all;
+	bootph-pre-ram;
+
+	regulators {
+		bootph-pre-ram;
+	};
+};
+
 &qspi {
 	bootph-pre-ram;
 };
@@ -269,6 +241,14 @@
 	};
 };
 
+&reg11 {
+	bootph-pre-ram;
+};
+
+&reg18 {
+	bootph-pre-ram;
+};
+
 &sdmmc1 {
 	bootph-pre-ram;
 	st,use-ckin;
@@ -331,14 +311,6 @@
 	};
 };
 
-&reg11 {
-	bootph-pre-ram;
-};
-
-&reg18 {
-	bootph-pre-ram;
-};
-
 &usb33 {
 	bootph-pre-ram;
 };
diff --git a/arch/arm/dts/zynqmp-sc-revB.dts b/arch/arm/dts/zynqmp-sc-revB.dts
index 1af3f64..c4f7058 100644
--- a/arch/arm/dts/zynqmp-sc-revB.dts
+++ b/arch/arm/dts/zynqmp-sc-revB.dts
@@ -3,7 +3,7 @@
  * dts file for Xilinx ZynqMP Generic System Controller
  *
  * (C) Copyright 2021 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2024, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek@amd.com>
  */
@@ -80,7 +80,7 @@
 	pwm-fan {
 		compatible = "pwm-fan";
 		status = "okay";
-		pwms = <&ttc0 2 40000 1>;
+		pwms = <&ttc0 2 40000 0>;
 	};
 };
 
diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts
index 8056f6b..8c43ade 100644
--- a/arch/arm/dts/zynqmp-sm-k26-revA.dts
+++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts
@@ -387,6 +387,7 @@
 
 &rtc {
 	status = "okay";
+	calibration = <0x7fff>;
 };
 
 &lpd_dma_chan1 {
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 192c120..974cbfe 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -73,11 +73,10 @@
 	 * Call remove function of all devices with a removal flag set.
 	 * This may be useful for last-stage operations, like cancelling
 	 * of DMA operation or releasing device internal buffers.
+	 * dm_remove_devices_active() ensures that vital devices are removed in
+	 * a second round.
 	 */
-	dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL | DM_REMOVE_NON_VITAL);
-
-	/* Remove all active vital devices next */
-	dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL);
+	dm_remove_devices_active();
 
 	cleanup_before_linux();
 }
diff --git a/arch/arm/mach-aspeed/ast2600/spl.c b/arch/arm/mach-aspeed/ast2600/spl.c
index 05390c1..0c5a82e 100644
--- a/arch/arm/mach-aspeed/ast2600/spl.c
+++ b/arch/arm/mach-aspeed/ast2600/spl.c
@@ -45,10 +45,10 @@
 	}
 
 	/* boot from UART has higher priority */
-	if (scu->hwstrap2 & SCU_HWSTRAP2_BOOT_UART)
+	if (readl(&scu->hwstrap2) & SCU_HWSTRAP2_BOOT_UART)
 		return BOOT_DEVICE_UART;
 
-	if (scu->hwstrap1 & SCU_HWSTRAP1_BOOT_EMMC)
+	if (readl(&scu->hwstrap1) & SCU_HWSTRAP1_BOOT_EMMC)
 		return BOOT_DEVICE_MMC1;
 
 out:
diff --git a/arch/arm/mach-imx/fdt.c b/arch/arm/mach-imx/fdt.c
index ac782e3..103c1fc5 100644
--- a/arch/arm/mach-imx/fdt.c
+++ b/arch/arm/mach-imx/fdt.c
@@ -115,7 +115,7 @@
 
 		temp = 0;
 		if (!strcmp(type, "critical"))
-			temp = 1000 * (maxc - 5);
+			temp = 1000 * maxc;
 		else if (!strcmp(type, "passive"))
 			temp = 1000 * (maxc - 10);
 		if (temp) {
diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
index 59d11b3..9a43bed 100644
--- a/arch/arm/mach-imx/imx8/Kconfig
+++ b/arch/arm/mach-imx/imx8/Kconfig
@@ -54,15 +54,8 @@
 	select BOARD_LATE_INIT
 	select IMX8QXP
 
-config TARGET_DENEB
-	bool "Support i.MX8QXP Capricorn Deneb board"
-	select BINMAN
-	select BOARD_LATE_INIT
-	select FACTORYSET
-	select IMX8QXP
-
-config TARGET_GIEDI
-	bool "Support i.MX8QXP Capricorn Giedi board"
+config TARGET_CAPRICORN
+	bool "Support i.MX8QXP Capricorn board"
 	select BINMAN
 	select BOARD_LATE_INIT
 	select FACTORYSET
diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig
index 5c10541..2465e31 100644
--- a/arch/arm/mach-imx/imx9/Kconfig
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -45,6 +45,8 @@
 	bool "phycore_imx93"
 	select IMX93
 	select IMX9_LPDDR4X
+	select OF_BOARD_FIXUP
+	select OF_BOARD_SETUP
 
 endchoice
 
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 21e0e7d..6837ac8 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -634,7 +634,7 @@
 	return 0;
 }
 
-#ifdef CONFIG_OF_BOARD_FIXUP
+#if defined(CONFIG_OF_BOARD_FIXUP) && !defined(CONFIG_TARGET_PHYCORE_IMX93)
 #ifndef CONFIG_XPL_BUILD
 int board_fix_fdt(void *fdt)
 {
diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig
index 536960b..976c0e3 100644
--- a/arch/arm/mach-snapdragon/Kconfig
+++ b/arch/arm/mach-snapdragon/Kconfig
@@ -11,6 +11,9 @@
 	  Based on this option board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD>
 	  will be used as the custom board directory.
 
+config SYS_MALLOC_LEN
+	default 0x10000000
+
 config SYS_MALLOC_F_LEN
 	default 0x2000
 
@@ -20,6 +23,9 @@
 config SPL_SYS_MALLOC_F_LEN
 	default 0x2000
 
+config SYS_MALLOC_LEN
+	default 0x800000
+
 config LNX_KRNL_IMG_TEXT_OFFSET_BASE
 	default 0x80000000
 
diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile
index 7a4495c..343e825 100644
--- a/arch/arm/mach-snapdragon/Makefile
+++ b/arch/arm/mach-snapdragon/Makefile
@@ -3,4 +3,5 @@
 # (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
 
 obj-y += board.o
+obj-$(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) += capsule_update.o
 obj-$(CONFIG_OF_LIVE) += of_fixup.o
diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c
index 2ab2ceb..75a880f 100644
--- a/arch/arm/mach-snapdragon/board.c
+++ b/arch/arm/mach-snapdragon/board.c
@@ -6,7 +6,9 @@
  * Author: Caleb Connolly <caleb.connolly@linaro.org>
  */
 
-#include "time.h"
+#define LOG_CATEGORY LOGC_BOARD
+#define pr_fmt(fmt) "QCOM: " fmt
+
 #include <asm/armv8/mmu.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
@@ -29,6 +31,7 @@
 #include <fdt_support.h>
 #include <usb.h>
 #include <sort.h>
+#include <time.h>
 
 #include "qcom-priv.h"
 
@@ -448,6 +451,9 @@
 	configure_env();
 	qcom_late_init();
 
+	/* Configure the dfu_string for capsule updates */
+	qcom_configure_capsule_updates();
+
 	return 0;
 }
 
diff --git a/arch/arm/mach-snapdragon/capsule_update.c b/arch/arm/mach-snapdragon/capsule_update.c
new file mode 100644
index 0000000..bf75a9a
--- /dev/null
+++ b/arch/arm/mach-snapdragon/capsule_update.c
@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Capsule update support for Qualcomm boards.
+ *
+ * Copyright (c) 2024 Linaro Ltd.
+ * Author: Caleb Connolly <caleb.connolly@linaro.org>
+ */
+
+#define pr_fmt(fmt) "QCOM-FMP: " fmt
+
+#include <dm/device.h>
+#include <dm/uclass.h>
+#include <efi.h>
+#include <efi_loader.h>
+#include <malloc.h>
+#include <scsi.h>
+#include <part.h>
+#include <linux/err.h>
+
+#include "qcom-priv.h"
+
+/*
+ * NOTE: for now this implementation only supports the rb3gen2. Supporting other
+ * boards that boot in different ways (e.g. chainloaded from ABL) will require
+ * additional complexity to properly create the dfu string and fw_images array.
+ */
+
+/*
+ * To handle different variants like chainloaded U-Boot here we'll need to
+ * build the fw_images array dynamically at runtime. It looks like
+ * mach-rockchip is a good example for how to do this.
+ * Detecting which image types a board uses is TBD, hence for now we only
+ * support the one new board that runs U-Boot as its primary bootloader.
+ */
+struct efi_fw_image fw_images[] = {
+	{
+		/* U-Boot flashed to the uefi_X partition (e.g. rb3gen2) */
+		.fw_name = u"UBOOT_UEFI_PARTITION",
+		.image_index = 1,
+	},
+};
+
+struct efi_capsule_update_info update_info = {
+	/* Filled in by configure_dfu_string() */
+	.dfu_string = NULL,
+	.num_images = ARRAY_SIZE(fw_images),
+	.images = fw_images,
+};
+
+/* LSB first */
+struct part_slot_status {
+	u16: 2;
+	u16 active : 1;
+	u16: 3;
+	u16 successful : 1;
+	u16 unbootable : 1;
+	u16 tries_remaining : 4;
+};
+
+static int find_boot_partition(const char *partname, struct blk_desc *blk_dev, char *name)
+{
+	int ret;
+	int partnum;
+	struct disk_partition info;
+	struct part_slot_status *slot_status;
+
+	for (partnum = 1;; partnum++) {
+		ret = part_get_info(blk_dev, partnum, &info);
+		if (ret)
+			return ret;
+
+		slot_status = (struct part_slot_status *)&info.type_flags;
+		log_io("%16s: Active: %1d, Successful: %1d, Unbootable: %1d, Tries left: %1d\n",
+		       info.name, slot_status->active,
+		       slot_status->successful, slot_status->unbootable,
+		       slot_status->tries_remaining);
+		/*
+		 * FIXME: eventually we'll want to find the active/inactive variant of the partition
+		 * but on the rb3gen2 these values might all be 0
+		 */
+		if (!strncmp(info.name, partname, strlen(partname))) {
+			log_debug("Found active %s partition: '%s'!\n", partname, info.name);
+			strlcpy(name, info.name, sizeof(info.name));
+			return partnum;
+		}
+	}
+
+	return -1;
+}
+
+/**
+ * qcom_configure_capsule_updates() - Configure the DFU string for capsule updates
+ *
+ * U-Boot is flashed to the boot partition on Qualcomm boards. In most cases there
+ * are two boot partitions, boot_a and boot_b. As we don't currently support doing
+ * full A/B updates, we only support updating the currently active boot partition.
+ *
+ * So we need to find the current slot suffix and the associated boot partition.
+ * We do this by looking for the boot partition that has the 'active' flag set
+ * in the GPT partition vendor attribute bits.
+ */
+void qcom_configure_capsule_updates(void)
+{
+	struct blk_desc *desc;
+	int ret = 0, partnum = -1, devnum;
+	static char dfu_string[32] = { 0 };
+	char name[32]; /* GPT partition name */
+	char *partname = "uefi_a";
+	struct udevice *dev = NULL;
+
+	if (IS_ENABLED(CONFIG_SCSI)) {
+		/* Scan for SCSI devices */
+		ret = scsi_scan(false);
+		if (ret) {
+			debug("Failed to scan SCSI devices: %d\n", ret);
+			return;
+		}
+	}
+
+	uclass_foreach_dev_probe(UCLASS_BLK, dev) {
+		if (device_get_uclass_id(dev) != UCLASS_BLK)
+			continue;
+
+		desc = dev_get_uclass_plat(dev);
+		if (!desc || desc->part_type == PART_TYPE_UNKNOWN)
+			continue;
+		devnum = desc->devnum;
+		partnum = find_boot_partition(partname, desc,
+					      name);
+		if (partnum >= 0)
+			break;
+	}
+
+	if (partnum < 0) {
+		log_err("Failed to find boot partition\n");
+		return;
+	}
+
+	switch (desc->uclass_id) {
+	case UCLASS_SCSI:
+		snprintf(dfu_string, 32, "scsi %d=u-boot.bin part %d", devnum, partnum);
+		break;
+	case UCLASS_MMC:
+		snprintf(dfu_string, 32, "mmc 0=u-boot.bin part %d %d", devnum, partnum);
+		break;
+	default:
+		debug("Unsupported storage uclass: %d\n", desc->uclass_id);
+		return;
+	}
+	log_debug("boot partition is %s, DFU string: '%s'\n", name, dfu_string);
+
+	update_info.dfu_string = dfu_string;
+}
diff --git a/arch/arm/mach-snapdragon/qcom-priv.h b/arch/arm/mach-snapdragon/qcom-priv.h
index 0a7ed5e..74d3919 100644
--- a/arch/arm/mach-snapdragon/qcom-priv.h
+++ b/arch/arm/mach-snapdragon/qcom-priv.h
@@ -3,6 +3,12 @@
 #ifndef __QCOM_PRIV_H__
 #define __QCOM_PRIV_H__
 
+#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
+void qcom_configure_capsule_updates(void);
+#else
+void qcom_configure_capsule_updates(void) {}
+#endif /* EFI_HAVE_CAPSULE_SUPPORT */
+
 #if CONFIG_IS_ENABLED(OF_LIVE)
 /**
  * qcom_of_fixup_nodes() - Fixup Qualcomm DT nodes
diff --git a/arch/arm/mach-zynqmp/include/mach/hardware.h b/arch/arm/mach-zynqmp/include/mach/hardware.h
index 49e449e..3c372bd 100644
--- a/arch/arm/mach-zynqmp/include/mach/hardware.h
+++ b/arch/arm/mach-zynqmp/include/mach/hardware.h
@@ -188,6 +188,8 @@
 	u32 gen_storage4; /* 0x40 */
 	u32 reserved1[1];
 	u32 gen_storage6; /* 0x48 */
+	u32 reserved2[3];
+	u32 pers_gen_storage2; /* 0x58 */
 };
 
 #define pmu_base ((struct pmu_regs *)ZYNQMP_PMU_BASEADDR)
diff --git a/arch/arm/mach-zynqmp/mp.c b/arch/arm/mach-zynqmp/mp.c
index 6e6da80..448bc53 100644
--- a/arch/arm/mach-zynqmp/mp.c
+++ b/arch/arm/mach-zynqmp/mp.c
@@ -352,7 +352,7 @@
 		 */
 		flush_dcache_all();
 
-		if (!strncmp(argv[1], "lockstep", 8)) {
+		if (!strcmp(argv[1], "lockstep") || !strcmp(argv[1], "0")) {
 			if (nr != ZYNQMP_CORE_RPU0) {
 				printf("Lockstep mode should run on ZYNQMP_CORE_RPU0\n");
 				return 1;
@@ -369,7 +369,7 @@
 			dcache_enable();
 			set_r5_halt_mode(nr, RELEASE, LOCK);
 			mark_r5_used(nr, LOCK);
-		} else if (!strncmp(argv[1], "split", 5)) {
+		} else if (!strcmp(argv[1], "split") || !strcmp(argv[1], "1")) {
 			printf("R5 split mode\n");
 			set_r5_reset(nr, SPLIT);
 			set_r5_tcm_mode(SPLIT);
diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c
index 8250297..76c610b 100644
--- a/arch/riscv/lib/bootm.c
+++ b/arch/riscv/lib/bootm.c
@@ -57,7 +57,7 @@
 	 * This may be useful for last-stage operations, like cancelling
 	 * of DMA operation or releasing device internal buffers.
 	 */
-	dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL);
+	dm_remove_devices_active();
 
 	cleanup_before_linux();
 }
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index dee2801..36cfbf2 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -44,6 +44,7 @@
 		mmc5 = "/mmc5";
 		mmc6 = "/mmc6";
 		mmc7 = "/mmc7";
+		mmc8 = "/mmc8";
 		pci0 = &pci0;
 		pci1 = &pci1;
 		pci2 = &pci2;
@@ -1138,13 +1139,20 @@
 		filename = "mmc6.img";
 	};
 
-	/* This is used for Android tests */
+	/* This is used for Android boot image v4 tests */
 	mmc7 {
 		status = "disabled";
 		compatible = "sandbox,mmc";
 		filename = "mmc7.img";
 	};
 
+	/* This is used for Android boot image v2 tests. */
+	mmc8 {
+		status = "disabled";
+		compatible = "sandbox,mmc";
+		filename = "mmc8.img";
+	};
+
 	pch {
 		compatible = "sandbox,pch";
 	};
diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c
index 55f5818..0f79a5d 100644
--- a/arch/x86/lib/bootm.c
+++ b/arch/x86/lib/bootm.c
@@ -49,7 +49,7 @@
 	 * This may be useful for last-stage operations, like cancelling
 	 * of DMA operation or releasing device internal buffers.
 	 */
-	dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL);
+	dm_remove_devices_active();
 }
 
 #if defined(CONFIG_OF_LIBFDT) && !defined(CONFIG_OF_NO_KERNEL)
diff --git a/board/armltd/total_compute/MAINTAINERS b/board/armltd/total_compute/MAINTAINERS
index 3dc1cd1..92486f4 100644
--- a/board/armltd/total_compute/MAINTAINERS
+++ b/board/armltd/total_compute/MAINTAINERS
@@ -1,5 +1,5 @@
 TOTAL_COMPUTE BOARD
-M:	Usama Arif <usama.arif@arm.com>
+M:	Ben Horgan <ben.horgan@arm.com>
 S:	Maintained
 F:	board/armltd/total_compute/
 F:	include/configs/total_compute.h
diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c
index b85fd806..1adee9a 100644
--- a/board/boundary/nitrogen6x/nitrogen6x.c
+++ b/board/boundary/nitrogen6x/nitrogen6x.c
@@ -281,7 +281,7 @@
 	setup_iomux_enet();
 
 #ifdef CONFIG_FEC_MXC
-	bus = fec_get_miibus(base, -1);
+	bus = fec_get_miibus(NULL, base, -1);
 	if (!bus)
 		return -EINVAL;
 	/* scan phy 4,5,6,7 */
diff --git a/board/emulation/qemu-arm/Kconfig b/board/emulation/qemu-arm/Kconfig
index e21c135..80ab9d8 100644
--- a/board/emulation/qemu-arm/Kconfig
+++ b/board/emulation/qemu-arm/Kconfig
@@ -5,6 +5,7 @@
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
+	select HAS_CUSTOM_SYS_INIT_SP_ADDR
 	select QFW if ACPI
 	select QFW_MMIO if CMD_QFW
 	imply VIRTIO_MMIO
diff --git a/board/phytec/common/Kconfig b/board/phytec/common/Kconfig
index f394ace..bc55117 100644
--- a/board/phytec/common/Kconfig
+++ b/board/phytec/common/Kconfig
@@ -19,6 +19,14 @@
 	  Support of I2C EEPROM based SoM detection. Supported
 	  for PHYTEC i.MX8MM/i.MX8MP boards
 
+config PHYTEC_IMX93_SOM_DETECTION
+	bool "Support SoM detection for i.MX93 PHYTEC platforms"
+	depends on ARCH_IMX9 && PHYTEC_SOM_DETECTION
+	default y
+	help
+	  Support of I2C EEPROM based SoM detection. Supported
+	  for PHYTEC i.MX93 based boards
+
 config PHYTEC_AM62_SOM_DETECTION
 	bool "Support SoM detection for AM62x PHYTEC platforms"
 	depends on (TARGET_PHYCORE_AM62X_A53 || TARGET_PHYCORE_AM62X_R5) && \
diff --git a/board/phytec/common/Makefile b/board/phytec/common/Makefile
index cd78f76..8126f73 100644
--- a/board/phytec/common/Makefile
+++ b/board/phytec/common/Makefile
@@ -10,3 +10,4 @@
 obj-y += phytec_som_detection.o phytec_som_detection_blocks.o
 obj-$(CONFIG_ARCH_K3) += am6_som_detection.o k3/
 obj-$(CONFIG_ARCH_IMX8M) += imx8m_som_detection.o
+obj-$(CONFIG_ARCH_IMX9) += imx93_som_detection.o
diff --git a/board/phytec/common/imx93_som_detection.c b/board/phytec/common/imx93_som_detection.c
new file mode 100644
index 0000000..eb9574d
--- /dev/null
+++ b/board/phytec/common/imx93_som_detection.c
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
+ * Author: Primoz Fiser <primoz.fiser@norik.com>
+ */
+
+#include <asm/arch/sys_proto.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+#include <i2c.h>
+#include <u-boot/crc.h>
+
+#include "imx93_som_detection.h"
+
+extern struct phytec_eeprom_data eeprom_data;
+
+#if IS_ENABLED(CONFIG_PHYTEC_IMX93_SOM_DETECTION)
+
+/* Check if the SoM is actually one of the following products:
+ * - i.MX93
+ *
+ * Returns 0 in case it's a known SoM. Otherwise, returns 1.
+ */
+u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data)
+{
+	u8 som;
+
+	if (!data)
+		data = &eeprom_data;
+
+	/* Early API revisions are not supported */
+	if (!data->valid || data->payload.api_rev < PHYTEC_API_REV2)
+		return 1;
+
+	som = data->payload.data.data_api2.som_no;
+	debug("%s: som id: %u\n", __func__, som);
+
+	if (som == PHYTEC_IMX93_SOM && is_imx93())
+		return 0;
+
+	pr_err("%s: SoM ID does not match. Wrong EEPROM data?\n", __func__);
+	return 1;
+}
+
+/*
+ * Filter PHYTEC i.MX93 SoM options by option index
+ *
+ * Returns:
+ *  - option value
+ *  - PHYTEC_EEPROM_INVAL when the data is invalid
+ *
+ */
+u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data,
+				       enum phytec_imx93_option_index idx)
+{
+	char *opt;
+	u8 opt_id;
+
+	if (!data)
+		data = &eeprom_data;
+
+	if (!data->valid || data->payload.api_rev < PHYTEC_API_REV2)
+		return PHYTEC_EEPROM_INVAL;
+
+	opt = phytec_get_opt(data);
+	if (opt)
+		opt_id = PHYTEC_GET_OPTION(opt[idx]);
+	else
+		opt_id = PHYTEC_EEPROM_INVAL;
+
+	debug("%s: opt[%d] id: %u\n", __func__, idx, opt_id);
+	return opt_id;
+}
+
+/*
+ * Filter PHYTEC i.MX93 SoM voltage
+ *
+ * Returns:
+ *  - PHYTEC_IMX93_VOLTAGE_1V8 or PHYTEC_IMX93_VOLTAGE_3V3
+ *  - PHYTEC_EEPROM_INVAL when the data is invalid
+ *
+ */
+enum phytec_imx93_voltage __maybe_unused phytec_imx93_get_voltage(struct phytec_eeprom_data *data)
+{
+	u8 option = phytec_imx93_get_opt(data, PHYTEC_IMX93_OPT_FEAT);
+
+	if (option == PHYTEC_EEPROM_INVAL)
+		return PHYTEC_IMX93_VOLTAGE_INVALID;
+	return (option & 0x01) ? PHYTEC_IMX93_VOLTAGE_1V8 : PHYTEC_IMX93_VOLTAGE_3V3;
+}
+
+#else
+
+inline u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data)
+{
+	return 1;
+}
+
+inline u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data,
+					      enum phytec_imx93_option_index idx)
+{
+	return PHYTEC_EEPROM_INVAL;
+}
+
+inline enum phytec_imx93_voltage __maybe_unused phytec_imx93_get_voltage
+	(struct phytec_eeprom_data *data)
+{
+	return PHYTEC_EEPROM_INVAL;
+}
+
+#endif /* IS_ENABLED(CONFIG_PHYTEC_IMX93_SOM_DETECTION) */
diff --git a/board/phytec/common/imx93_som_detection.h b/board/phytec/common/imx93_som_detection.h
new file mode 100644
index 0000000..a0803b4
--- /dev/null
+++ b/board/phytec/common/imx93_som_detection.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
+ * Author: Primoz Fiser <primoz.fiser@norik.com>
+ */
+
+#ifndef _PHYTEC_IMX93_SOM_DETECTION_H
+#define _PHYTEC_IMX93_SOM_DETECTION_H
+
+#include "phytec_som_detection.h"
+
+#define PHYTEC_IMX93_SOM	77
+
+enum phytec_imx93_option_index {
+	PHYTEC_IMX93_OPT_DDR = 0,
+	PHYTEC_IMX93_OPT_EMMC = 1,
+	PHYTEC_IMX93_OPT_CPU = 2,
+	PHYTEC_IMX93_OPT_FREQ = 3,
+	PHYTEC_IMX93_OPT_NPU = 4,
+	PHYTEC_IMX93_OPT_DISP = 5,
+	PHYTEC_IMX93_OPT_ETH = 6,
+	PHYTEC_IMX93_OPT_FEAT = 7,
+	PHYTEC_IMX93_OPT_TEMP = 8,
+	PHYTEC_IMX93_OPT_BOOT = 9,
+	PHYTEC_IMX93_OPT_LED = 10,
+	PHYTEC_IMX93_OPT_EEPROM = 11,
+};
+
+enum phytec_imx93_voltage {
+	PHYTEC_IMX93_VOLTAGE_INVALID = PHYTEC_EEPROM_INVAL,
+	PHYTEC_IMX93_VOLTAGE_3V3 = 0,
+	PHYTEC_IMX93_VOLTAGE_1V8 = 1,
+};
+
+enum phytec_imx93_ddr_eeprom_code {
+	PHYTEC_IMX93_DDR_INVALID = PHYTEC_EEPROM_INVAL,
+	PHYTEC_IMX93_LPDDR4X_512MB = 0,
+	PHYTEC_IMX93_LPDDR4X_1GB = 1,
+	PHYTEC_IMX93_LPDDR4X_2GB = 2,
+	PHYTEC_IMX93_LPDDR4_512MB = 3,
+	PHYTEC_IMX93_LPDDR4_1GB = 4,
+	PHYTEC_IMX93_LPDDR4_2GB = 5,
+};
+
+u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data);
+u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data,
+				       enum phytec_imx93_option_index idx);
+enum phytec_imx93_voltage __maybe_unused phytec_imx93_get_voltage
+	(struct phytec_eeprom_data *data);
+
+#endif /* _PHYTEC_IMX93_SOM_DETECTION_H */
diff --git a/board/phytec/common/k3/board.c b/board/phytec/common/k3/board.c
index 3d7e090..346b2b6 100644
--- a/board/phytec/common/k3/board.c
+++ b/board/phytec/common/k3/board.c
@@ -6,7 +6,9 @@
 
 #include <env_internal.h>
 #include <fdt_support.h>
+#include <dm/ofnode.h>
 #include <spl.h>
+#include <malloc.h>
 #include <asm/arch/hardware.h>
 
 #include "../am6_som_detection.h"
@@ -97,8 +99,79 @@
 #endif
 
 #if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP)
+static int fdt_apply_overlay_from_fit(const char *overlay_path, void *fdt)
+{
+	u64 loadaddr;
+	ofnode node;
+	int ret;
+
+	node = ofnode_path(overlay_path);
+	if (!ofnode_valid(node))
+		return -FDT_ERR_NOTFOUND;
+
+	ret = ofnode_read_u64(node, "load", &loadaddr);
+	if (ret)
+		return ret;
+
+	return fdt_overlay_apply_verbose(fdt, (void *)loadaddr);
+}
+
+static void fdt_apply_som_overlays(void *blob)
+{
+	void *fdt_copy;
+	u32 fdt_size;
+	struct phytec_eeprom_data data;
+	int err;
+
+	fdt_size = fdt_totalsize(blob);
+	fdt_copy = malloc(fdt_size);
+	if (!fdt_copy)
+		goto fixup_error;
+
+	memcpy(fdt_copy, blob, fdt_size);
+
+	err = phytec_eeprom_data_setup(&data, 0, EEPROM_ADDR);
+	if (err)
+		goto fixup_error;
+
+	if (phytec_get_am6_rtc(&data) == 0) {
+		err = fdt_apply_overlay_from_fit("/fit-images/som-no-rtc", fdt_copy);
+		if (err)
+			goto fixup_error;
+	}
+
+	if (phytec_get_am6_spi(&data) == PHYTEC_EEPROM_VALUE_X) {
+		err = fdt_apply_overlay_from_fit("/fit-images/som-no-spi", fdt_copy);
+		if (err)
+			goto fixup_error;
+	}
+
+	if (phytec_get_am6_eth(&data) == 0) {
+		err = fdt_apply_overlay_from_fit("/fit-images/som-no-eth", fdt_copy);
+		if (err)
+			goto fixup_error;
+	}
+
+	if (phytec_am6_is_qspi(&data)) {
+		err = fdt_apply_overlay_from_fit("/fit-images/som-qspi-nor", fdt_copy);
+		if (err)
+			goto fixup_error;
+	}
+
+	memcpy(blob, fdt_copy, fdt_size);
+
+cleanup:
+	free(fdt_copy);
+	return;
+
+fixup_error:
+	pr_err("Failed to apply SoM overlays\n");
+	goto cleanup;
+}
+
 int ft_board_setup(void *blob, struct bd_info *bd)
 {
+	fdt_apply_som_overlays(blob);
 	fdt_copy_fixed_partitions(blob);
 
 	return 0;
diff --git a/board/phytec/phycore_imx8mm/Kconfig b/board/phytec/phycore_imx8mm/Kconfig
index 25e4bf2..0644912 100644
--- a/board/phytec/phycore_imx8mm/Kconfig
+++ b/board/phytec/phycore_imx8mm/Kconfig
@@ -12,4 +12,5 @@
 config IMX_CONFIG
 	default "board/phytec/phycore_imx8mm/imximage-8mm-sd.cfg"
 
+source "board/phytec/common/Kconfig"
 endif
diff --git a/board/phytec/phycore_imx8mm/spl.c b/board/phytec/phycore_imx8mm/spl.c
index 8d85859..faff064 100644
--- a/board/phytec/phycore_imx8mm/spl.c
+++ b/board/phytec/phycore_imx8mm/spl.c
@@ -17,8 +17,13 @@
 #include <log.h>
 #include <spl.h>
 
+#include "../common/imx8m_som_detection.h"
+
 DECLARE_GLOBAL_DATA_PTR;
 
+#define EEPROM_ADDR		0x51
+#define EEPROM_ADDR_FALLBACK	0x59
+
 int spl_board_boot_device(enum boot_device boot_dev_spl)
 {
 	switch (boot_dev_spl) {
@@ -39,6 +44,18 @@
 
 static void spl_dram_init(void)
 {
+	int ret;
+
+	ret = phytec_eeprom_data_setup_fallback(NULL, 0, EEPROM_ADDR,
+			EEPROM_ADDR_FALLBACK);
+	if (ret)
+		goto out;
+
+	ret = phytec_imx8m_detect(NULL);
+	if (!ret)
+		phytec_print_som_info(NULL);
+
+out:
 	ddr_init(&dram_timing);
 }
 
diff --git a/board/phytec/phycore_imx93/Kconfig b/board/phytec/phycore_imx93/Kconfig
index a70104c..09f26e8 100644
--- a/board/phytec/phycore_imx93/Kconfig
+++ b/board/phytec/phycore_imx93/Kconfig
@@ -10,4 +10,32 @@
 config SYS_CONFIG_NAME
 	default "phycore_imx93"
 
+config PHYCORE_IMX93_RAM_TYPE_FIX
+	bool "Set phyCORE-i.MX93 RAM type and size fix instead of detecting"
+	default false
+	help
+	  RAM type and size is being automatically detected with the help
+	  of the PHYTEC EEPROM introspection data.
+	  Set RAM type to a fix value instead.
+
+choice
+	prompt "phyCORE-i.MX93 RAM type"
+	depends on PHYCORE_IMX93_RAM_TYPE_FIX
+	default PHYCORE_IMX93_RAM_TYPE_LPDDR4X_1GB
+
+config PHYCORE_IMX93_RAM_TYPE_LPDDR4X_1GB
+	bool "LPDDR4X 1GB RAM"
+	help
+	  Set RAM type fixed to LPDDR4X and RAM size fixed to 1GB
+	  for phyCORE-i.MX93.
+
+config PHYCORE_IMX93_RAM_TYPE_LPDDR4X_2GB
+	bool "LPDDR4X 2GB RAM"
+	help
+	  Set RAM type fixed to LPDDR4X and RAM size fixed to 2GB
+	  for phyCORE-i.MX93.
+
+endchoice
+
+source "board/phytec/common/Kconfig"
 endif
diff --git a/board/phytec/phycore_imx93/MAINTAINERS b/board/phytec/phycore_imx93/MAINTAINERS
index 9e91a29..718f89a 100644
--- a/board/phytec/phycore_imx93/MAINTAINERS
+++ b/board/phytec/phycore_imx93/MAINTAINERS
@@ -1,10 +1,13 @@
 phyCORE-i.MX93
-M:	Mathieu Othacehe <m.othacehe@gmail.com>
+M:      Mathieu Othacehe <m.othacehe@gmail.com>
+R:      Christoph Stoidner <c.stoidner@phytec.de>
 W:      https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/
 S:      Maintained
 F:      arch/arm/dts/imx93-phyboard-segin.dts
 F:      arch/arm/dts/imx93-phycore-som.dtsi
 F:      arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
 F:      board/phytec/phycore_imx93/
-F:      configs/imx93-phyboard-segin_defconfig
+F:      board/phytec/common/imx93_som_detection.c
+F:      board/phytec/common/imx93_som_detection.h
+F:      configs/imx93-phycore_defconfig
 F:      include/configs/phycore_imx93.h
diff --git a/board/phytec/phycore_imx93/lpddr4_timing.c b/board/phytec/phycore_imx93/lpddr4_timing.c
index 2111972..f1261f6 100644
--- a/board/phytec/phycore_imx93/lpddr4_timing.c
+++ b/board/phytec/phycore_imx93/lpddr4_timing.c
@@ -1,24 +1,24 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2023 NXP
- * Copyright (C) 2023 PHYTEC Messtechnik GmbH
+ * Copyright 2024 NXP
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
  * Christoph Stoidner <c.stoidner@phytec.de>
  *
- * Code generated with DDR Tool v1.0.0.
+ * Code generated with DDR Tool v3.1.0_7.4.
  */
 
 #include <linux/kernel.h>
 #include <asm/arch/ddr.h>
 
+/* Initialize DDRC registers */
 static struct dram_cfg_param ddr_ddrc_cfg[] = {
-	/** Initialize DDRC registers **/
 	{0x4e300110, 0x44100001},
 	{0x4e300000, 0x8000bf},
 	{0x4e300008, 0x0},
 	{0x4e300080, 0x80000412},
 	{0x4e300084, 0x0},
 	{0x4e300114, 0x1002},
-	{0x4e300260, 0x4080},
+	{0x4e300260, 0x80},
 	{0x4e300f04, 0x80},
 	{0x4e300800, 0x43b30002},
 	{0x4e300804, 0x1f1f1f1f},
@@ -31,18 +31,17 @@
 	{0x4e301254, 0x0},
 	{0x4e301258, 0x0},
 	{0x4e30125c, 0x0},
-
 };
 
 /* dram fsp cfg */
 static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = {
 	{
 		{
-			{0x4e300100, 0x24A0421B},
+			{0x4e300100, 0x24A0321B},
 			{0x4e300104, 0xF8EE001B},
-			{0x4e300108, 0x2F263233},
-			{0x4e30010C, 0x0005E18B},
-			{0x4e300124, 0x1C770000},
+			{0x4e300108, 0x2F2E3233},
+			{0x4e30010C, 0x0005C18B},
+			{0x4e300124, 0x1C790000},
 			{0x4e300160, 0x00009102},
 			{0x4e30016C, 0x35F00000},
 			{0x4e300170, 0x8B0B0608},
@@ -50,21 +49,73 @@
 			{0x4e300254, 0x00FE00FE},
 			{0x4e300258, 0x00000008},
 			{0x4e30025C, 0x00000400},
-			{0x4e300300, 0x224F2215},
+			{0x4e300300, 0x224F2213},
 			{0x4e300304, 0x00FE2213},
-			{0x4e300308, 0x0A3C0E3C},
+			{0x4e300308, 0x0A380E3D},
 		},
 		{
 			{0x01, 0xE4},
 			{0x02, 0x36},
-			{0x03, 0xF2},
-			{0x0b, 0x46},
-			{0x0c, 0x11},
-			{0x0e, 0x11},
+			{0x03, 0x22},
+			{0x0b, 0x44},
+			{0x0c, 0x1E},
+			{0x0e, 0x12},
+			{0x16, 0x04},
+		},
+		0,
+	},
+	{
+		{
+			{0x4e300100, 0x124F2100},
+			{0x4e300104, 0xF877000E},
+			{0x4e300108, 0x1816E4AA},
+			{0x4e30010C, 0x005101E6},
+			{0x4e300124, 0x0E3C0000},
+			{0x4e300160, 0x00009101},
+			{0x4e30016C, 0x30900000},
+			{0x4e300170, 0x8A0A0508},
+			{0x4e300250, 0x00000014},
+			{0x4e300254, 0x007B007B},
+			{0x4e300258, 0x00000008},
+			{0x4e30025C, 0x00000400},
+		},
+		{
+			{0x01, 0xB4},
+			{0x02, 0x1B},
+			{0x03, 0x22},
+			{0x0b, 0x44},
+			{0x0c, 0x1E},
+			{0x0e, 0x12},
 			{0x16, 0x04},
 		},
 		0,
 	},
+	{
+		{
+			{0x4e300100, 0x00051000},
+			{0x4e300104, 0xF855000A},
+			{0x4e300108, 0x6E620A48},
+			{0x4e30010C, 0x0031010D},
+			{0x4e300124, 0x04C50000},
+			{0x4e300160, 0x00009100},
+			{0x4e30016C, 0x30000000},
+			{0x4e300170, 0x89090408},
+			{0x4e300250, 0x00000007},
+			{0x4e300254, 0x00240024},
+			{0x4e300258, 0x00000008},
+			{0x4e30025C, 0x00000400},
+		},
+		{
+			{0x01, 0x94},
+			{0x02, 0x9},
+			{0x03, 0x22},
+			{0x0b, 0x44},
+			{0x0c, 0x1E},
+			{0x0e, 0x12},
+			{0x16, 0x04},
+		},
+		1,
+	},
 
 };
 
@@ -90,25 +141,65 @@
 	{0x1015f, 0x5ff},
 	{0x1105f, 0x5ff},
 	{0x1115f, 0x5ff},
+	{0x11005f, 0x5ff},
+	{0x11015f, 0x5ff},
+	{0x11105f, 0x5ff},
+	{0x11115f, 0x5ff},
+	{0x21005f, 0x5ff},
+	{0x21015f, 0x5ff},
+	{0x21105f, 0x5ff},
+	{0x21115f, 0x5ff},
 	{0x55, 0x1ff},
 	{0x1055, 0x1ff},
 	{0x2055, 0x1ff},
 	{0x200c5, 0x19},
+	{0x1200c5, 0xb},
+	{0x2200c5, 0x7},
 	{0x2002e, 0x2},
+	{0x12002e, 0x2},
+	{0x22002e, 0x2},
 	{0x90204, 0x0},
+	{0x190204, 0x0},
+	{0x290204, 0x0},
 	{0x20024, 0x1e3},
 	{0x2003a, 0x2},
 	{0x2007d, 0x212},
 	{0x2007c, 0x61},
+	{0x120024, 0x1e3},
+	{0x2003a, 0x2},
+	{0x12007d, 0x212},
+	{0x12007c, 0x61},
+	{0x220024, 0x1e3},
+	{0x2003a, 0x2},
+	{0x22007d, 0x212},
+	{0x22007c, 0x61},
 	{0x20056, 0x3},
+	{0x120056, 0x3},
+	{0x220056, 0x3},
 	{0x1004d, 0x600},
 	{0x1014d, 0x600},
 	{0x1104d, 0x600},
 	{0x1114d, 0x600},
-	{0x10049, 0xe00},
-	{0x10149, 0xe00},
-	{0x11049, 0xe00},
-	{0x11149, 0xe00},
+	{0x11004d, 0x600},
+	{0x11014d, 0x600},
+	{0x11104d, 0x600},
+	{0x11114d, 0x600},
+	{0x21004d, 0x600},
+	{0x21014d, 0x600},
+	{0x21104d, 0x600},
+	{0x21114d, 0x600},
+	{0x10049, 0x604},
+	{0x10149, 0x604},
+	{0x11049, 0x604},
+	{0x11149, 0x604},
+	{0x110049, 0x604},
+	{0x110149, 0x604},
+	{0x111049, 0x604},
+	{0x111149, 0x604},
+	{0x210049, 0x604},
+	{0x210149, 0x604},
+	{0x211049, 0x604},
+	{0x211149, 0x604},
 	{0x43, 0x60},
 	{0x1043, 0x60},
 	{0x2043, 0x60},
@@ -117,14 +208,30 @@
 	{0x20050, 0x0},
 	{0x2009b, 0x2},
 	{0x20008, 0x3a5},
+	{0x120008, 0x1d3},
+	{0x220008, 0x9c},
 	{0x20088, 0x9},
-	{0x200b2, 0x10c},
+	{0x200b2, 0x104},
 	{0x10043, 0x5a1},
 	{0x10143, 0x5a1},
 	{0x11043, 0x5a1},
 	{0x11143, 0x5a1},
+	{0x1200b2, 0x104},
+	{0x110043, 0x5a1},
+	{0x110143, 0x5a1},
+	{0x111043, 0x5a1},
+	{0x111143, 0x5a1},
+	{0x2200b2, 0x104},
+	{0x210043, 0x5a1},
+	{0x210143, 0x5a1},
+	{0x211043, 0x5a1},
+	{0x211143, 0x5a1},
 	{0x200fa, 0x2},
+	{0x1200fa, 0x2},
+	{0x2200fa, 0x2},
 	{0x20019, 0x1},
+	{0x120019, 0x1},
+	{0x220019, 0x1},
 	{0x200f0, 0x600},
 	{0x200f1, 0x0},
 	{0x200f2, 0x4444},
@@ -133,42 +240,83 @@
 	{0x200f5, 0x0},
 	{0x200f6, 0x0},
 	{0x200f7, 0xf000},
+	{0x1004a, 0x500},
+	{0x1104a, 0x500},
 	{0x20025, 0x0},
-	{0x2002d, 0x1},
+	{0x2002d, 0x0},
+	{0x12002d, 0x0},
+	{0x22002d, 0x0},
 	{0x2002c, 0x0},
 	{0x20021, 0x0},
 	{0x200c7, 0x21},
 	{0x1200c7, 0x21},
 	{0x200ca, 0x24},
 	{0x1200ca, 0x24},
-
 };
 
-/* ddr phy trained csr */
+/* PHY trained csr */
 static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
 	{0x1005f, 0x0},
 	{0x1015f, 0x0},
 	{0x1105f, 0x0},
 	{0x1115f, 0x0},
+	{0x11005f, 0x0},
+	{0x11015f, 0x0},
+	{0x11105f, 0x0},
+	{0x11115f, 0x0},
+	{0x21005f, 0x0},
+	{0x21015f, 0x0},
+	{0x21105f, 0x0},
+	{0x21115f, 0x0},
 	{0x55, 0x0},
 	{0x1055, 0x0},
 	{0x2055, 0x0},
 	{0x200c5, 0x0},
+	{0x1200c5, 0x0},
+	{0x2200c5, 0x0},
 	{0x2002e, 0x0},
+	{0x12002e, 0x0},
+	{0x22002e, 0x0},
 	{0x90204, 0x0},
+	{0x190204, 0x0},
+	{0x290204, 0x0},
 	{0x20024, 0x0},
 	{0x2003a, 0x0},
 	{0x2007d, 0x0},
 	{0x2007c, 0x0},
+	{0x120024, 0x0},
+	{0x12007d, 0x0},
+	{0x12007c, 0x0},
+	{0x220024, 0x0},
+	{0x22007d, 0x0},
+	{0x22007c, 0x0},
 	{0x20056, 0x0},
+	{0x120056, 0x0},
+	{0x220056, 0x0},
 	{0x1004d, 0x0},
 	{0x1014d, 0x0},
 	{0x1104d, 0x0},
 	{0x1114d, 0x0},
+	{0x11004d, 0x0},
+	{0x11014d, 0x0},
+	{0x11104d, 0x0},
+	{0x11114d, 0x0},
+	{0x21004d, 0x0},
+	{0x21014d, 0x0},
+	{0x21104d, 0x0},
+	{0x21114d, 0x0},
 	{0x10049, 0x0},
 	{0x10149, 0x0},
 	{0x11049, 0x0},
 	{0x11149, 0x0},
+	{0x110049, 0x0},
+	{0x110149, 0x0},
+	{0x111049, 0x0},
+	{0x111149, 0x0},
+	{0x210049, 0x0},
+	{0x210149, 0x0},
+	{0x211049, 0x0},
+	{0x211149, 0x0},
 	{0x43, 0x0},
 	{0x1043, 0x0},
 	{0x2043, 0x0},
@@ -177,14 +325,30 @@
 	{0x20050, 0x0},
 	{0x2009b, 0x0},
 	{0x20008, 0x0},
+	{0x120008, 0x0},
+	{0x220008, 0x0},
 	{0x20088, 0x0},
 	{0x200b2, 0x0},
 	{0x10043, 0x0},
 	{0x10143, 0x0},
 	{0x11043, 0x0},
 	{0x11143, 0x0},
+	{0x1200b2, 0x0},
+	{0x110043, 0x0},
+	{0x110143, 0x0},
+	{0x111043, 0x0},
+	{0x111143, 0x0},
+	{0x2200b2, 0x0},
+	{0x210043, 0x0},
+	{0x210143, 0x0},
+	{0x211043, 0x0},
+	{0x211143, 0x0},
 	{0x200fa, 0x0},
+	{0x1200fa, 0x0},
+	{0x2200fa, 0x0},
 	{0x20019, 0x0},
+	{0x120019, 0x0},
+	{0x220019, 0x0},
 	{0x200f0, 0x0},
 	{0x200f1, 0x0},
 	{0x200f2, 0x0},
@@ -193,8 +357,12 @@
 	{0x200f5, 0x0},
 	{0x200f6, 0x0},
 	{0x200f7, 0x0},
+	{0x1004a, 0x0},
+	{0x1104a, 0x0},
 	{0x20025, 0x0},
 	{0x2002d, 0x0},
+	{0x12002d, 0x0},
+	{0x22002d, 0x0},
 	{0x2002c, 0x0},
 	{0xd0000, 0x0},
 	{0x90000, 0x0},
@@ -682,6 +850,14 @@
 	{0x2000c, 0x0},
 	{0x2000d, 0x0},
 	{0x2000e, 0x0},
+	{0x12000b, 0x0},
+	{0x12000c, 0x0},
+	{0x12000d, 0x0},
+	{0x12000e, 0x0},
+	{0x22000b, 0x0},
+	{0x22000c, 0x0},
+	{0x22000d, 0x0},
+	{0x22000e, 0x0},
 	{0x9000c, 0x0},
 	{0x9000d, 0x0},
 	{0x9000e, 0x0},
@@ -692,12 +868,26 @@
 	{0x90013, 0x0},
 	{0x20010, 0x0},
 	{0x20011, 0x0},
+	{0x120010, 0x0},
+	{0x120011, 0x0},
 	{0x40080, 0x0},
 	{0x40081, 0x0},
 	{0x40082, 0x0},
 	{0x40083, 0x0},
 	{0x40084, 0x0},
 	{0x40085, 0x0},
+	{0x140080, 0x0},
+	{0x140081, 0x0},
+	{0x140082, 0x0},
+	{0x140083, 0x0},
+	{0x140084, 0x0},
+	{0x140085, 0x0},
+	{0x240080, 0x0},
+	{0x240081, 0x0},
+	{0x240082, 0x0},
+	{0x240083, 0x0},
+	{0x240084, 0x0},
+	{0x240085, 0x0},
 	{0x400fd, 0x0},
 	{0x400f1, 0x0},
 	{0x10011, 0x0},
@@ -866,6 +1056,160 @@
 	{0x90207, 0x0},
 	{0x90208, 0x0},
 	{0x20020, 0x0},
+	{0x100080, 0x0},
+	{0x101080, 0x0},
+	{0x102080, 0x0},
+	{0x110020, 0x0},
+	{0x110080, 0x0},
+	{0x110081, 0x0},
+	{0x1100d0, 0x0},
+	{0x1100d1, 0x0},
+	{0x11008c, 0x0},
+	{0x11008d, 0x0},
+	{0x110180, 0x0},
+	{0x110181, 0x0},
+	{0x1101d0, 0x0},
+	{0x1101d1, 0x0},
+	{0x11018c, 0x0},
+	{0x11018d, 0x0},
+	{0x1100c0, 0x0},
+	{0x1100c1, 0x0},
+	{0x1101c0, 0x0},
+	{0x1101c1, 0x0},
+	{0x1102c0, 0x0},
+	{0x1102c1, 0x0},
+	{0x1103c0, 0x0},
+	{0x1103c1, 0x0},
+	{0x1104c0, 0x0},
+	{0x1104c1, 0x0},
+	{0x1105c0, 0x0},
+	{0x1105c1, 0x0},
+	{0x1106c0, 0x0},
+	{0x1106c1, 0x0},
+	{0x1107c0, 0x0},
+	{0x1107c1, 0x0},
+	{0x1108c0, 0x0},
+	{0x1108c1, 0x0},
+	{0x1100ae, 0x0},
+	{0x1100af, 0x0},
+	{0x111020, 0x0},
+	{0x111080, 0x0},
+	{0x111081, 0x0},
+	{0x1110d0, 0x0},
+	{0x1110d1, 0x0},
+	{0x11108c, 0x0},
+	{0x11108d, 0x0},
+	{0x111180, 0x0},
+	{0x111181, 0x0},
+	{0x1111d0, 0x0},
+	{0x1111d1, 0x0},
+	{0x11118c, 0x0},
+	{0x11118d, 0x0},
+	{0x1110c0, 0x0},
+	{0x1110c1, 0x0},
+	{0x1111c0, 0x0},
+	{0x1111c1, 0x0},
+	{0x1112c0, 0x0},
+	{0x1112c1, 0x0},
+	{0x1113c0, 0x0},
+	{0x1113c1, 0x0},
+	{0x1114c0, 0x0},
+	{0x1114c1, 0x0},
+	{0x1115c0, 0x0},
+	{0x1115c1, 0x0},
+	{0x1116c0, 0x0},
+	{0x1116c1, 0x0},
+	{0x1117c0, 0x0},
+	{0x1117c1, 0x0},
+	{0x1118c0, 0x0},
+	{0x1118c1, 0x0},
+	{0x1110ae, 0x0},
+	{0x1110af, 0x0},
+	{0x190201, 0x0},
+	{0x190202, 0x0},
+	{0x190203, 0x0},
+	{0x190205, 0x0},
+	{0x190206, 0x0},
+	{0x190207, 0x0},
+	{0x190208, 0x0},
+	{0x120020, 0x0},
+	{0x200080, 0x0},
+	{0x201080, 0x0},
+	{0x202080, 0x0},
+	{0x210020, 0x0},
+	{0x210080, 0x0},
+	{0x210081, 0x0},
+	{0x2100d0, 0x0},
+	{0x2100d1, 0x0},
+	{0x21008c, 0x0},
+	{0x21008d, 0x0},
+	{0x210180, 0x0},
+	{0x210181, 0x0},
+	{0x2101d0, 0x0},
+	{0x2101d1, 0x0},
+	{0x21018c, 0x0},
+	{0x21018d, 0x0},
+	{0x2100c0, 0x0},
+	{0x2100c1, 0x0},
+	{0x2101c0, 0x0},
+	{0x2101c1, 0x0},
+	{0x2102c0, 0x0},
+	{0x2102c1, 0x0},
+	{0x2103c0, 0x0},
+	{0x2103c1, 0x0},
+	{0x2104c0, 0x0},
+	{0x2104c1, 0x0},
+	{0x2105c0, 0x0},
+	{0x2105c1, 0x0},
+	{0x2106c0, 0x0},
+	{0x2106c1, 0x0},
+	{0x2107c0, 0x0},
+	{0x2107c1, 0x0},
+	{0x2108c0, 0x0},
+	{0x2108c1, 0x0},
+	{0x2100ae, 0x0},
+	{0x2100af, 0x0},
+	{0x211020, 0x0},
+	{0x211080, 0x0},
+	{0x211081, 0x0},
+	{0x2110d0, 0x0},
+	{0x2110d1, 0x0},
+	{0x21108c, 0x0},
+	{0x21108d, 0x0},
+	{0x211180, 0x0},
+	{0x211181, 0x0},
+	{0x2111d0, 0x0},
+	{0x2111d1, 0x0},
+	{0x21118c, 0x0},
+	{0x21118d, 0x0},
+	{0x2110c0, 0x0},
+	{0x2110c1, 0x0},
+	{0x2111c0, 0x0},
+	{0x2111c1, 0x0},
+	{0x2112c0, 0x0},
+	{0x2112c1, 0x0},
+	{0x2113c0, 0x0},
+	{0x2113c1, 0x0},
+	{0x2114c0, 0x0},
+	{0x2114c1, 0x0},
+	{0x2115c0, 0x0},
+	{0x2115c1, 0x0},
+	{0x2116c0, 0x0},
+	{0x2116c1, 0x0},
+	{0x2117c0, 0x0},
+	{0x2117c1, 0x0},
+	{0x2118c0, 0x0},
+	{0x2118c1, 0x0},
+	{0x2110ae, 0x0},
+	{0x2110af, 0x0},
+	{0x290201, 0x0},
+	{0x290202, 0x0},
+	{0x290203, 0x0},
+	{0x290205, 0x0},
+	{0x290206, 0x0},
+	{0x290207, 0x0},
+	{0x290208, 0x0},
+	{0x220020, 0x0},
 	{0x20077, 0x0},
 	{0x20072, 0x0},
 	{0x20073, 0x0},
@@ -888,7 +1232,6 @@
 	{0x11640, 0x0},
 	{0x11740, 0x0},
 	{0x11840, 0x0},
-
 };
 
 /* P0 message block parameter for training firmware */
@@ -896,7 +1239,7 @@
 	{0xd0000, 0x0},
 	{0x54003, 0xe94},
 	{0x54004, 0x4},
-	{0x54006, 0x15},
+	{0x54006, 0x14},
 	{0x54008, 0x131f},
 	{0x54009, 0xc8},
 	{0x5400b, 0x4},
@@ -904,36 +1247,112 @@
 	{0x5400f, 0x100},
 	{0x54012, 0x110},
 	{0x54019, 0x36e4},
-	{0x5401a, 0xf2},
-	{0x5401b, 0x1146},
-	{0x5401c, 0x1108},
+	{0x5401a, 0x22},
+	{0x5401b, 0x1e44},
+	{0x5401c, 0x1208},
 	{0x5401e, 0x4},
 	{0x5401f, 0x36e4},
-	{0x54020, 0xf2},
-	{0x54021, 0x1146},
-	{0x54022, 0x1108},
+	{0x54020, 0x22},
+	{0x54021, 0x1e44},
+	{0x54022, 0x1208},
 	{0x54024, 0x4},
 	{0x54032, 0xe400},
-	{0x54033, 0xf236},
-	{0x54034, 0x4600},
-	{0x54035, 0x811},
-	{0x54036, 0x11},
+	{0x54033, 0x2236},
+	{0x54034, 0x4400},
+	{0x54035, 0x81e},
+	{0x54036, 0x12},
 	{0x54037, 0x400},
 	{0x54038, 0xe400},
-	{0x54039, 0xf236},
-	{0x5403a, 0x4600},
-	{0x5403b, 0x811},
-	{0x5403c, 0x11},
+	{0x54039, 0x2236},
+	{0x5403a, 0x4400},
+	{0x5403b, 0x81e},
+	{0x5403c, 0x12},
 	{0x5403d, 0x400},
 	{0xd0000, 0x1}
 };
 
+/* P1 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54002, 0x1},
+	{0x54003, 0x74a},
+	{0x54004, 0x4},
+	{0x54006, 0x14},
+	{0x54008, 0x121f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x4},
+	{0x5400d, 0x100},
+	{0x5400f, 0x100},
+	{0x54012, 0x110},
+	{0x54019, 0x1bb4},
+	{0x5401a, 0x22},
+	{0x5401b, 0x1e44},
+	{0x5401c, 0x1208},
+	{0x5401e, 0x4},
+	{0x5401f, 0x1bb4},
+	{0x54020, 0x22},
+	{0x54021, 0x1e44},
+	{0x54022, 0x1208},
+	{0x54024, 0x4},
+	{0x54032, 0xb400},
+	{0x54033, 0x221b},
+	{0x54034, 0x4400},
+	{0x54035, 0x81e},
+	{0x54036, 0x12},
+	{0x54037, 0x400},
+	{0x54038, 0xb400},
+	{0x54039, 0x221b},
+	{0x5403a, 0x4400},
+	{0x5403b, 0x81e},
+	{0x5403c, 0x12},
+	{0x5403d, 0x400},
+	{0xd0000, 0x1}
+};
+
+/* P2 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54002, 0x102},
+	{0x54003, 0x270},
+	{0x54004, 0x4},
+	{0x54006, 0x14},
+	{0x54008, 0x121f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x4},
+	{0x5400d, 0x100},
+	{0x5400f, 0x100},
+	{0x54012, 0x110},
+	{0x54019, 0x994},
+	{0x5401a, 0x22},
+	{0x5401b, 0x1e44},
+	{0x5401c, 0x1200},
+	{0x5401e, 0x4},
+	{0x5401f, 0x994},
+	{0x54020, 0x22},
+	{0x54021, 0x1e44},
+	{0x54022, 0x1200},
+	{0x54024, 0x4},
+	{0x54032, 0x9400},
+	{0x54033, 0x2209},
+	{0x54034, 0x4400},
+	{0x54035, 0x1e},
+	{0x54036, 0x12},
+	{0x54037, 0x400},
+	{0x54038, 0x9400},
+	{0x54039, 0x2209},
+	{0x5403a, 0x4400},
+	{0x5403b, 0x1e},
+	{0x5403c, 0x12},
+	{0x5403d, 0x400},
+	{0xd0000, 0x1}
+};
+
 /* P0 2D message block parameter for training firmware */
 static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
 	{0xd0000, 0x0},
 	{0x54003, 0xe94},
 	{0x54004, 0x4},
-	{0x54006, 0x15},
+	{0x54006, 0x14},
 	{0x54008, 0x61},
 	{0x54009, 0xc8},
 	{0x5400b, 0x4},
@@ -942,26 +1361,26 @@
 	{0x54010, 0x2080},
 	{0x54012, 0x110},
 	{0x54019, 0x36e4},
-	{0x5401a, 0xf2},
-	{0x5401b, 0x1146},
-	{0x5401c, 0x1108},
+	{0x5401a, 0x22},
+	{0x5401b, 0x1e44},
+	{0x5401c, 0x1208},
 	{0x5401e, 0x4},
 	{0x5401f, 0x36e4},
-	{0x54020, 0xf2},
-	{0x54021, 0x1146},
-	{0x54022, 0x1108},
+	{0x54020, 0x22},
+	{0x54021, 0x1e44},
+	{0x54022, 0x1208},
 	{0x54024, 0x4},
 	{0x54032, 0xe400},
-	{0x54033, 0xf236},
-	{0x54034, 0x4600},
-	{0x54035, 0x811},
-	{0x54036, 0x11},
+	{0x54033, 0x2236},
+	{0x54034, 0x4400},
+	{0x54035, 0x81e},
+	{0x54036, 0x12},
 	{0x54037, 0x400},
 	{0x54038, 0xe400},
-	{0x54039, 0xf236},
-	{0x5403a, 0x4600},
-	{0x5403b, 0x811},
-	{0x5403c, 0x11},
+	{0x54039, 0x2236},
+	{0x5403a, 0x4400},
+	{0x5403b, 0x81e},
+	{0x5403c, 0x12},
 	{0x5403d, 0x400},
 	{0xd0000, 0x1}
 };
@@ -1451,10 +1870,18 @@
 	{0x400d7, 0x20b},
 	{0x2003a, 0x2},
 	{0x200be, 0x3},
-	{0x2000b, 0x75},
+	{0x2000b, 0x41a},
 	{0x2000c, 0xe9},
 	{0x2000d, 0x91c},
 	{0x2000e, 0x2c},
+	{0x12000b, 0x20d},
+	{0x12000c, 0x74},
+	{0x12000d, 0x48e},
+	{0x12000e, 0x2c},
+	{0x22000b, 0xb0},
+	{0x22000c, 0x27},
+	{0x22000d, 0x186},
+	{0x22000e, 0x10},
 	{0x9000c, 0x0},
 	{0x9000d, 0x173},
 	{0x9000e, 0x60},
@@ -1465,12 +1892,26 @@
 	{0x90013, 0x6152},
 	{0x20010, 0x5a},
 	{0x20011, 0x3},
+	{0x120010, 0x5a},
+	{0x120011, 0x3},
 	{0x40080, 0xe0},
 	{0x40081, 0x12},
 	{0x40082, 0xe0},
 	{0x40083, 0x12},
 	{0x40084, 0xe0},
 	{0x40085, 0x12},
+	{0x140080, 0xe0},
+	{0x140081, 0x12},
+	{0x140082, 0xe0},
+	{0x140083, 0x12},
+	{0x140084, 0xe0},
+	{0x140085, 0x12},
+	{0x240080, 0xe0},
+	{0x240081, 0x12},
+	{0x240082, 0xe0},
+	{0x240083, 0x12},
+	{0x240084, 0xe0},
+	{0x240085, 0x12},
 	{0x400fd, 0xf},
 	{0x400f1, 0xe},
 	{0x10011, 0x1},
@@ -1505,7 +1946,6 @@
 	{0x20088, 0x19},
 	{0xc0080, 0x0},
 	{0xd0000, 0x1},
-
 };
 
 static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
@@ -1515,9 +1955,21 @@
 		.fw_type = FW_1D_IMAGE,
 		.fsp_cfg = ddr_fsp0_cfg,
 		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
-
 	},
-
+	{
+		/* P1 1866mts 1D */
+		.drate = 1866,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P2 625mts 1D */
+		.drate = 625,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+	},
 	{
 		/* P0 3733mts 2D */
 		.drate = 3733,
@@ -1525,7 +1977,6 @@
 		.fsp_cfg = ddr_fsp0_2d_cfg,
 		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
 	},
-
 };
 
 /* ddr timing config params */
@@ -1540,7 +1991,227 @@
 	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
 	.ddrphy_pie = ddr_phy_pie,
 	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
-	.fsp_table = { 3733, },
+	.fsp_table = { 3733, 1866, 625, },
 	.fsp_cfg = ddr_dram_fsp_cfg,
 	.fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg),
 };
+
+void set_dram_timings_2gb_lpddr4x(void)
+{
+	/* Initialize DDRC registers */
+	dram_timing.ddrc_cfg[1].val = 0x8000ff;
+	dram_timing.ddrc_cfg[3].val = 0x80000512;
+
+	/* dram fsp cfg */
+	dram_timing.fsp_cfg[0].ddrc_cfg[0].val = 0x24AB321B;
+	dram_timing.fsp_cfg[0].ddrc_cfg[2].val = 0x2F2EE233;
+	dram_timing.fsp_cfg[0].ddrc_cfg[9].val = 0x015B015B;
+	dram_timing.fsp_cfg[0].ddrc_cfg[13].val = 0x015B2213;
+	dram_timing.fsp_cfg[0].mr_cfg[4].val = 0x20;
+	dram_timing.fsp_cfg[0].mr_cfg[5].val = 0x13;
+
+	dram_timing.fsp_cfg[1].ddrc_cfg[0].val = 0x12552100;
+	dram_timing.fsp_cfg[1].ddrc_cfg[2].val = 0x1816B4AA;
+	dram_timing.fsp_cfg[1].ddrc_cfg[9].val = 0x00AA00AA;
+	dram_timing.fsp_cfg[1].mr_cfg[4].val = 0x20;
+	dram_timing.fsp_cfg[1].mr_cfg[5].val = 0x13;
+
+	dram_timing.fsp_cfg[2].ddrc_cfg[0].val = 0x00061000;
+	dram_timing.fsp_cfg[2].ddrc_cfg[2].val = 0x6E62FA48;
+	dram_timing.fsp_cfg[2].ddrc_cfg[9].val = 0x00340034;
+	dram_timing.fsp_cfg[2].mr_cfg[4].val = 0x20;
+	dram_timing.fsp_cfg[2].mr_cfg[5].val = 0x13;
+
+	/* P0 message block parameter for training firmware */
+	dram_timing.fsp_msg[0].fsp_cfg[12].val = 0x2044;
+	dram_timing.fsp_msg[0].fsp_cfg[13].val = 0x1308;
+	dram_timing.fsp_msg[0].fsp_cfg[17].val = 0x2044;
+	dram_timing.fsp_msg[0].fsp_cfg[18].val = 0x1308;
+	dram_timing.fsp_msg[0].fsp_cfg[23].val = 0x820;
+	dram_timing.fsp_msg[0].fsp_cfg[24].val = 0x13;
+	dram_timing.fsp_msg[0].fsp_cfg[29].val = 0x820;
+	dram_timing.fsp_msg[0].fsp_cfg[30].val = 0x13;
+
+	/* P1 message block parameter for training firmware */
+	dram_timing.fsp_msg[1].fsp_cfg[13].val = 0x2044;
+	dram_timing.fsp_msg[1].fsp_cfg[14].val = 0x1308;
+	dram_timing.fsp_msg[1].fsp_cfg[18].val = 0x2044;
+	dram_timing.fsp_msg[1].fsp_cfg[19].val = 0x1308;
+	dram_timing.fsp_msg[1].fsp_cfg[24].val = 0x820;
+	dram_timing.fsp_msg[1].fsp_cfg[25].val = 0x13;
+	dram_timing.fsp_msg[1].fsp_cfg[30].val = 0x820;
+	dram_timing.fsp_msg[1].fsp_cfg[31].val = 0x13;
+
+	/* P2 message block parameter for training firmware */
+	dram_timing.fsp_msg[2].fsp_cfg[13].val = 0x2044;
+	dram_timing.fsp_msg[2].fsp_cfg[14].val = 0x1300;
+	dram_timing.fsp_msg[2].fsp_cfg[18].val = 0x2044;
+	dram_timing.fsp_msg[2].fsp_cfg[19].val = 0x1300;
+	dram_timing.fsp_msg[2].fsp_cfg[24].val = 0x20;
+	dram_timing.fsp_msg[2].fsp_cfg[25].val = 0x13;
+	dram_timing.fsp_msg[2].fsp_cfg[30].val = 0x20;
+	dram_timing.fsp_msg[2].fsp_cfg[31].val = 0x13;
+
+	/* P0 2D message block parameter for training firmware */
+	dram_timing.fsp_msg[3].fsp_cfg[13].val = 0x2044;
+	dram_timing.fsp_msg[3].fsp_cfg[14].val = 0x1308;
+	dram_timing.fsp_msg[3].fsp_cfg[18].val = 0x2044;
+	dram_timing.fsp_msg[3].fsp_cfg[19].val = 0x1308;
+	dram_timing.fsp_msg[3].fsp_cfg[24].val = 0x820;
+	dram_timing.fsp_msg[3].fsp_cfg[25].val = 0x13;
+	dram_timing.fsp_msg[3].fsp_cfg[30].val = 0x820;
+	dram_timing.fsp_msg[3].fsp_cfg[31].val = 0x13;
+}
+
+/* Generated with DDR Tool v3.3.0_7.8-d1cdb7d3 */
+void set_dram_timings_1gb_lpddr4x_900mhz(void)
+{
+	/* Initialize DDRC registers */
+	dram_timing.ddrc_cfg[6].val = 0x4080;
+
+	/* dram fsp cfg */
+	dram_timing.fsp_cfg[0].ddrc_cfg[0].val = 0x124F2100;
+	dram_timing.fsp_cfg[0].ddrc_cfg[1].val = 0xF877000E;
+	dram_timing.fsp_cfg[0].ddrc_cfg[2].val = 0x181AE4AA;
+	dram_timing.fsp_cfg[0].ddrc_cfg[3].val = 0x005101E6;
+	dram_timing.fsp_cfg[0].ddrc_cfg[4].val = 0x0E3C0000;
+	dram_timing.fsp_cfg[0].ddrc_cfg[5].val = 0x00009101;
+	dram_timing.fsp_cfg[0].ddrc_cfg[6].val = 0x30900000;
+	dram_timing.fsp_cfg[0].ddrc_cfg[7].val = 0x8A0A0508;
+	dram_timing.fsp_cfg[0].ddrc_cfg[8].val = 0x00000014;
+	dram_timing.fsp_cfg[0].ddrc_cfg[9].val = 0x007B007B;
+	dram_timing.fsp_cfg[0].ddrc_cfg[12].val = 0x1128110B;
+	dram_timing.fsp_cfg[0].ddrc_cfg[13].val = 0x007B140A;
+	dram_timing.fsp_cfg[0].ddrc_cfg[14].val = 0x0620071E;
+	dram_timing.fsp_cfg[0].mr_cfg[0].val = 0xB4;
+	dram_timing.fsp_cfg[0].mr_cfg[1].val = 0x1B;
+	dram_timing.fsp_cfg[0].mr_cfg[2].val = 0xE2;
+	dram_timing.fsp_cfg[0].mr_cfg[4].val = 0x20;
+	dram_timing.fsp_cfg[0].mr_cfg[5].val = 0x15;
+
+	dram_timing.fsp_cfg[1].ddrc_cfg[2].val = 0x181AE4AA;
+	dram_timing.fsp_cfg[1].mr_cfg[2].val = 0xE2;
+	dram_timing.fsp_cfg[1].mr_cfg[4].val = 0x20;
+	dram_timing.fsp_cfg[1].mr_cfg[5].val = 0x15;
+
+	dram_timing.fsp_cfg[2].ddrc_cfg[2].val = 0x6E660A48;
+	dram_timing.fsp_cfg[2].mr_cfg[2].val = 0xE2;
+	dram_timing.fsp_cfg[2].mr_cfg[4].val = 0x20;
+	dram_timing.fsp_cfg[2].mr_cfg[5].val = 0x15;
+
+	/* PHY Initialize Configuration */
+	dram_timing.ddrphy_cfg[31].val = 0xb;
+	dram_timing.ddrphy_cfg[86].val = 0x1d3;
+	dram_timing.ddrphy_cfg[90].val = 0x10c;
+	dram_timing.ddrphy_cfg[95].val = 0x10c;
+	dram_timing.ddrphy_cfg[100].val = 0x10c;
+	dram_timing.ddrphy_cfg[122].val = 0x1;
+	/**
+	 * NOTE:
+	 * In the output from DDR Tool v3.3.0_7.8-d1cdb7d3, array members 119
+	 * (reg=0x1004a, val=0x500) and 120 (reg=0x1104a, val=0x500) are not
+	 * present in the ddr_ddrphy_cfg array. However they were present in array
+	 * generated with previous DDR Tool v3.1.0_7.4. We simply set both values
+	 * to default value of 0x400 (read with dwc_ddrphy_apb_rd()) here to avoid
+	 * any negative side-effects.
+	 */
+	dram_timing.ddrphy_cfg[119].val = 0x400;
+	dram_timing.ddrphy_cfg[120].val = 0x400;
+
+	/**
+	 * NOTE:
+	 * In the output from DDR Tool v3.3.0_7.8-d1cdb7d3, array members 101
+	 * (reg=0x1004a, val=0x0) and 120 (reg=0x1104a, val=0x0) are not present
+	 * in the ddr_ddrphy_trained_csr array. However they were present in array
+	 * generated with previous DDR Tool v3.1.0_7.4. We simply set both values
+	 * to default 0x0 (like all other ddrphy_trained_csr values) here to avoid
+	 * any negative side-effects.
+	 */
+	/* PHY trained csr */
+	dram_timing.ddrphy_trained_csr[101].val = 0x0;
+	dram_timing.ddrphy_trained_csr[102].val = 0x0;
+
+	/* P0 message block parameter for training firmware */
+	dram_timing.fsp_msg[0].fsp_cfg[1].val = 0x74a;
+	dram_timing.fsp_msg[0].fsp_cfg[3].val = 0x15;
+	dram_timing.fsp_msg[0].fsp_cfg[10].val = 0x1bb4;
+	dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xe2;
+	dram_timing.fsp_msg[0].fsp_cfg[12].val = 0x2044;
+	dram_timing.fsp_msg[0].fsp_cfg[13].val = 0x1508;
+	dram_timing.fsp_msg[0].fsp_cfg[15].val = 0x1bb4;
+	dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xe2;
+	dram_timing.fsp_msg[0].fsp_cfg[17].val = 0x2044;
+	dram_timing.fsp_msg[0].fsp_cfg[18].val = 0x1508;
+	dram_timing.fsp_msg[0].fsp_cfg[20].val = 0xb400;
+	dram_timing.fsp_msg[0].fsp_cfg[21].val = 0xe21b;
+	dram_timing.fsp_msg[0].fsp_cfg[23].val = 0x820;
+	dram_timing.fsp_msg[0].fsp_cfg[24].val = 0x15;
+	dram_timing.fsp_msg[0].fsp_cfg[26].val = 0xb400;
+	dram_timing.fsp_msg[0].fsp_cfg[27].val = 0xe21b;
+	dram_timing.fsp_msg[0].fsp_cfg[29].val = 0x820;
+	dram_timing.fsp_msg[0].fsp_cfg[30].val = 0x15;
+
+	/* P1 message block parameter for training firmware */
+	dram_timing.fsp_msg[1].fsp_cfg[4].val = 0x15;
+	dram_timing.fsp_msg[1].fsp_cfg[12].val = 0xe2;
+	dram_timing.fsp_msg[1].fsp_cfg[13].val = 0x2044;
+	dram_timing.fsp_msg[1].fsp_cfg[14].val = 0x1508;
+	dram_timing.fsp_msg[1].fsp_cfg[17].val = 0xe2;
+	dram_timing.fsp_msg[1].fsp_cfg[18].val = 0x2044;
+	dram_timing.fsp_msg[1].fsp_cfg[19].val = 0x1508;
+	dram_timing.fsp_msg[1].fsp_cfg[22].val = 0xe21b;
+	dram_timing.fsp_msg[1].fsp_cfg[24].val = 0x820;
+	dram_timing.fsp_msg[1].fsp_cfg[25].val = 0x15;
+	dram_timing.fsp_msg[1].fsp_cfg[28].val = 0xe21b;
+	dram_timing.fsp_msg[1].fsp_cfg[30].val = 0x820;
+	dram_timing.fsp_msg[1].fsp_cfg[31].val = 0x15;
+
+	/* P2 message block parameter for training firmware */
+	dram_timing.fsp_msg[2].fsp_cfg[4].val = 0x15;
+	dram_timing.fsp_msg[2].fsp_cfg[12].val = 0xe2;
+	dram_timing.fsp_msg[2].fsp_cfg[13].val = 0x2044;
+	dram_timing.fsp_msg[2].fsp_cfg[14].val = 0x1500;
+	dram_timing.fsp_msg[2].fsp_cfg[17].val = 0xe2;
+	dram_timing.fsp_msg[2].fsp_cfg[18].val = 0x2044;
+	dram_timing.fsp_msg[2].fsp_cfg[19].val = 0x1500;
+	dram_timing.fsp_msg[2].fsp_cfg[22].val = 0xe209;
+	dram_timing.fsp_msg[2].fsp_cfg[24].val = 0x20;
+	dram_timing.fsp_msg[2].fsp_cfg[25].val = 0x15;
+	dram_timing.fsp_msg[2].fsp_cfg[28].val = 0xe209;
+	dram_timing.fsp_msg[2].fsp_cfg[30].val = 0x20;
+	dram_timing.fsp_msg[2].fsp_cfg[31].val = 0x15;
+
+	/* P0 2D message block parameter for training firmware */
+	dram_timing.fsp_msg[3].fsp_cfg[1].val = 0x74a;
+	dram_timing.fsp_msg[3].fsp_cfg[3].val = 0x15;
+	dram_timing.fsp_msg[3].fsp_cfg[11].val = 0x1bb4;
+	dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xe2;
+	dram_timing.fsp_msg[3].fsp_cfg[13].val = 0x2044;
+	dram_timing.fsp_msg[3].fsp_cfg[14].val = 0x1508;
+	dram_timing.fsp_msg[3].fsp_cfg[16].val = 0x1bb4;
+	dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xe2;
+	dram_timing.fsp_msg[3].fsp_cfg[18].val = 0x2044;
+	dram_timing.fsp_msg[3].fsp_cfg[19].val = 0x1508;
+	dram_timing.fsp_msg[3].fsp_cfg[21].val = 0xb400;
+	dram_timing.fsp_msg[3].fsp_cfg[22].val = 0xe21b;
+	dram_timing.fsp_msg[3].fsp_cfg[24].val = 0x820;
+	dram_timing.fsp_msg[3].fsp_cfg[25].val = 0x15;
+	dram_timing.fsp_msg[3].fsp_cfg[27].val = 0xb400;
+	dram_timing.fsp_msg[3].fsp_cfg[28].val = 0xe21b;
+	dram_timing.fsp_msg[3].fsp_cfg[30].val = 0x820;
+	dram_timing.fsp_msg[3].fsp_cfg[31].val = 0x15;
+
+	/* DRAM PHY init engine image */
+	dram_timing.ddrphy_pie[483].val = 0x20d;
+	dram_timing.ddrphy_pie[484].val = 0x74;
+	dram_timing.ddrphy_pie[485].val = 0x48e;
+
+	/* P0 3733mts 1D */
+	dram_timing.fsp_msg[0].drate = 1866;
+
+	/* P0 1866mts 2D */
+	dram_timing.fsp_msg[3].drate = 1866;
+
+	/* ddr timing config params */
+	dram_timing.fsp_table[0] = 1866;
+}
diff --git a/board/phytec/phycore_imx93/phycore-imx93.c b/board/phytec/phycore_imx93/phycore-imx93.c
index 085c8e1..a55795e 100644
--- a/board/phytec/phycore_imx93/phycore-imx93.c
+++ b/board/phytec/phycore_imx93/phycore-imx93.c
@@ -3,6 +3,7 @@
  * Copyright (C) 2023 PHYTEC Messtechnik GmbH
  * Author: Christoph Stoidner <c.stoidner@phytec.de>
  * Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com>
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
  */
 
 #include <asm/arch-imx9/ccm_regs.h>
@@ -12,11 +13,21 @@
 #include <asm/global_data.h>
 #include <asm/mach-imx/boot_mode.h>
 #include <env.h>
+#include <fdt_support.h>
+
+#include "../common/imx93_som_detection.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define EEPROM_ADDR            0x50
+
 int board_init(void)
 {
+	int ret = phytec_eeprom_data_setup(NULL, 2, EEPROM_ADDR);
+
+	if (ret)
+		printf("%s: EEPROM data init failed\n", __func__);
+
 	return 0;
 }
 
@@ -38,5 +49,45 @@
 		break;
 	}
 
+	return 0;
+}
+
+static void emmc_fixup(void *blob, struct phytec_eeprom_data *data)
+{
+	enum phytec_imx93_voltage voltage = phytec_imx93_get_voltage(data);
+	int offset;
+
+	if (voltage == PHYTEC_IMX93_VOLTAGE_INVALID)
+		goto err;
+
+	if (voltage == PHYTEC_IMX93_VOLTAGE_1V8) {
+		offset = fdt_node_offset_by_compat_reg(blob, "fsl,imx93-usdhc",
+						       0x42850000);
+		if (offset)
+			fdt_delprop(blob, offset, "no-1-8-v");
+		else
+			goto err;
+	}
+
+	return;
+err:
+	printf("Could not detect eMMC VDD-IO. Fall back to default.\n");
+}
+
+int board_fix_fdt(void *blob)
+{
+	struct phytec_eeprom_data data;
+
+	phytec_eeprom_data_setup(&data, 2, EEPROM_ADDR);
+
+	emmc_fixup(blob, &data);
+
+	return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	emmc_fixup(blob, NULL);
+
 	return 0;
 }
diff --git a/board/phytec/phycore_imx93/spl.c b/board/phytec/phycore_imx93/spl.c
index 17a8736..a4d2aaa 100644
--- a/board/phytec/phycore_imx93/spl.c
+++ b/board/phytec/phycore_imx93/spl.c
@@ -3,6 +3,7 @@
  * Copyright (C) 2023 PHYTEC Messtechnik GmbH
  * Author: Christoph Stoidner <c.stoidner@phytec.de>
  * Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com>
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
  */
 
 #include <asm/arch/clock.h>
@@ -20,6 +21,8 @@
 #include <power/pca9450.h>
 #include <spl.h>
 
+#include "../common/imx93_som_detection.h"
+
 DECLARE_GLOBAL_DATA_PTR;
 
 /*
@@ -27,6 +30,13 @@
  * when pca9451a support is added.
  */
 #define PCA9450_REG_PWRCTRL_TOFF_DEB    BIT(5)
+#define EEPROM_ADDR            0x50
+
+/*
+ * Prototypes of automatically generated ram config file
+ */
+void set_dram_timings_2gb_lpddr4x(void);
+void set_dram_timings_1gb_lpddr4x_900mhz(void);
 
 int spl_board_boot_device(enum boot_device boot_dev_spl)
 {
@@ -46,6 +56,44 @@
 
 void spl_dram_init(void)
 {
+	int ret;
+	enum phytec_imx93_ddr_eeprom_code ddr_opt = PHYTEC_IMX93_DDR_INVALID;
+
+	/* NOTE: In SPL lpi2c3 is mapped to bus 0 */
+	ret = phytec_eeprom_data_setup(NULL, 0, EEPROM_ADDR);
+	if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_FIX))
+		goto out;
+
+	ret = phytec_imx93_detect(NULL);
+	if (!ret)
+		phytec_print_som_info(NULL);
+
+	if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_FIX)) {
+		if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_LPDDR4X_1GB))
+			ddr_opt = PHYTEC_IMX93_LPDDR4X_1GB;
+		else if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_LPDDR4X_2GB))
+			ddr_opt = PHYTEC_IMX93_LPDDR4X_2GB;
+	} else {
+		ddr_opt = phytec_imx93_get_opt(NULL, PHYTEC_IMX93_OPT_DDR);
+	}
+
+	switch (ddr_opt) {
+	case PHYTEC_IMX93_LPDDR4X_1GB:
+		if (is_voltage_mode(VOLT_LOW_DRIVE))
+			set_dram_timings_1gb_lpddr4x_900mhz();
+		break;
+	case PHYTEC_IMX93_LPDDR4X_2GB:
+		set_dram_timings_2gb_lpddr4x();
+		break;
+	default:
+		goto out;
+	}
+	ddr_init(&dram_timing);
+	return;
+out:
+	puts("Could not detect correct RAM type and size. Fall back to default.\n");
+	if (is_voltage_mode(VOLT_LOW_DRIVE))
+		set_dram_timings_1gb_lpddr4x_900mhz();
 	ddr_init(&dram_timing);
 }
 
diff --git a/board/siemens/capricorn/Kconfig b/board/siemens/capricorn/Kconfig
index c5a28ff..fe23097 100644
--- a/board/siemens/capricorn/Kconfig
+++ b/board/siemens/capricorn/Kconfig
@@ -1,4 +1,5 @@
-if TARGET_GIEDI
+if TARGET_CAPRICORN
+
 
 config SYS_BOARD
 	default "capricorn"
@@ -7,24 +8,18 @@
 	default "siemens"
 
 config SYS_CONFIG_NAME
-	default "giedi"
+	default "capricorn-common"
 
 config IMX_CONFIG
 	default "board/siemens/capricorn/imximage.cfg"
-endif
 
-if TARGET_DENEB
-
-config SYS_BOARD
-	default "capricorn"
-
-config SYS_VENDOR
-	default "siemens"
+endif
 
-config SYS_CONFIG_NAME
-	default "deneb"
 
-config IMX_CONFIG
-	default "board/siemens/capricorn/imximage.cfg"
+config SPL_CMT
+	bool "Enable Siemens SPL RAM test"
+	depends on SPL
+	help
+	  Enable SIemens SPL RAM test.
 
-endif
+source "board/siemens/common/Kconfig"
diff --git a/board/siemens/capricorn/MAINTAINERS b/board/siemens/capricorn/MAINTAINERS
index b4c5203..5f467aa 100644
--- a/board/siemens/capricorn/MAINTAINERS
+++ b/board/siemens/capricorn/MAINTAINERS
@@ -1,10 +1,12 @@
 CAPRICORN BOARD
+M:	Alexander Sverdlin <alexander.sverdlin@siemens.com>
 M:	Anatolij Gustschin <agust@denx.de>
+M:	Heiko Schocher <hs@denx.de>
+M:	Walter Schweizer <walter.schweizer@siemens.com>
 S:	Maintained
+F:	arch/arm/dts/imx8-capricorn-cxg3.dts
+F:	arch/arm/dts/imx8-capricorn-u-boot.dtsi
+F:	arch/arm/dts/imx8-capricorn.dtsi
 F:	board/siemens/capricorn/
+F:	configs/capricorn_cxg3_defconfig
 F:	include/configs/capricorn-common.h
-F:	include/configs/deneb.h
-F:	include/configs/giedi.h
-F:	include/configs/siemens-env-common.h
-F:	configs/deneb_defconfig
-F:	configs/giedi_defconfig
diff --git a/board/siemens/capricorn/Makefile b/board/siemens/capricorn/Makefile
index e8a24c4..a03d54e 100644
--- a/board/siemens/capricorn/Makefile
+++ b/board/siemens/capricorn/Makefile
@@ -8,6 +8,8 @@
 
 ifdef CONFIG_XPL_BUILD
 obj-y += spl.o
+obj-$(CONFIG_SPL_CMT) += spl_memory_test.o
 else
 obj-y += ../common/factoryset.o
+obj-$(CONFIG_DDR_SI_TEST) += ../common/ddr_si_test.o
 endif
diff --git a/board/siemens/capricorn/board.c b/board/siemens/capricorn/board.c
index ad474d9..390a7b0 100644
--- a/board/siemens/capricorn/board.c
+++ b/board/siemens/capricorn/board.c
@@ -26,6 +26,7 @@
 #include <asm/arch-imx8/clock.h>
 #endif
 #include <linux/delay.h>
+#include "../common/board.h"
 #include "../common/eeprom.h"
 #include "../common/factoryset.h"
 
@@ -63,8 +64,7 @@
 	sc_pm_clock_rate_t rate = SC_80MHZ;
 	int ret;
 
-	ret = sc_pm_setup_uart(SC_R_UART_0, rate);
-	ret |= sc_pm_setup_uart(SC_R_UART_2, rate);
+	ret = sc_pm_setup_uart(SC_R_UART_2, rate);
 	if (ret)
 		return ret;
 
@@ -73,6 +73,40 @@
 	return 0;
 }
 
+#ifndef CONFIG_XPL_BUILD
+void board_mem_get_layout(u64 *phys_sdram_1_start,
+			  u64 *phys_sdram_1_size,
+			  u64 *phys_sdram_2_start,
+			  u64 *phys_sdram_2_size)
+{
+	sc_faddr_t addr_start, addr_end;
+	sc_faddr_t sdram_1_size, sdram_2_size;
+	sc_err_t sc_err;
+
+	sc_err = sc_rm_get_memreg_info(-1, 6, &addr_start, &addr_end);
+	if (sc_err == SC_ERR_NONE) {
+		if (addr_end < 0x100000000) {
+			/* only lower RAM available */
+			sdram_1_size = (addr_end + 1) - PHYS_SDRAM_1;
+			sdram_2_size = 0;
+		} else {
+			/* lower RAM (2 GB) und upper RAM available */
+			sdram_1_size = SZ_2G;
+			sdram_2_size = (addr_end + 1) - PHYS_SDRAM_2;
+		}
+	} else {
+		/* Get default in case it would fail */
+		sdram_1_size = PHYS_SDRAM_1_SIZE;
+		sdram_2_size = PHYS_SDRAM_2_SIZE;
+	}
+
+	*phys_sdram_1_start = PHYS_SDRAM_1;
+	*phys_sdram_1_size = sdram_1_size;
+	*phys_sdram_2_start = PHYS_SDRAM_2;
+	*phys_sdram_2_size = sdram_2_size;
+}
+#endif /* ! CONFIG_XPL_BUILD */
+
 #define ENET_PHY_RESET	IMX_GPIO_NR(0, 3)
 #define ENET_TEST_1	IMX_GPIO_NR(0, 8)
 #define ENET_TEST_2	IMX_GPIO_NR(0, 9)
@@ -271,11 +305,7 @@
 {
 	puts("Board: Capricorn\n");
 
-	/*
-	 * Running build_info() doesn't work with current SCFW blob.
-	 * Uncomment below call when new blob is available.
-	 */
-	/*build_info();*/
+	build_info();
 
 	print_bootinfo();
 	return 0;
@@ -283,6 +313,32 @@
 
 int board_init(void)
 {
+	struct chip_data eeprom_data = {};
+	char module_name[16];
+	int ret;
+
+	ret = siemens_ee_setup();
+	if (ret) {
+		printf("'siemens_ee_setup' failed, ret: %d\n", ret);
+		goto skip;
+	}
+
+	/* Get module name from EEPROM */
+	siemens_ee_read_data(SIEMENS_EE_ADDR_DDR3, module_name,
+			     sizeof(module_name));
+	printf("CPU module: %s\n", module_name);
+
+	ret = siemens_ee_read_data(SIEMENS_EE_ADDR_CHIP,
+				   (uchar *)&eeprom_data,
+				   sizeof(eeprom_data));
+	if (ret) {
+		printf("'siemens_ee_read_data' failed, ret: %d\n", ret);
+		goto skip;
+	}
+
+	printf("HW Version: %s\n", eeprom_data.shwver);
+skip:
+
 	setup_fec();
 	return 0;
 }
diff --git a/board/siemens/capricorn/imximage.cfg b/board/siemens/capricorn/imximage.cfg
index 4350e29..7fd3fb8 100644
--- a/board/siemens/capricorn/imximage.cfg
+++ b/board/siemens/capricorn/imximage.cfg
@@ -9,13 +9,24 @@
 
 /* Boot from SD, sector size 0x400 */
 BOOT_FROM	sd
+
+/* skip DCD data, as firmware initializes the RAM */
+DCD_SKIP true
+
 /* SoC type IMX8QX */
 SOC_TYPE IMX8QX
-/* Append seco container image */
-APPEND ahab-container.img
+/*
+ * Append seco container image,
+ * use same name as in arch/arm/dts/imx8qxp-u-boot.dtsi
+ */
+APPEND mx8qxc0-ahab-container.img
 /* Create the 2nd container */
 CONTAINER
-/* Add scfw image with exec attribute */
-IMAGE SCU capricorn-scfw-tcm.bin
-/* Add ATF image with exec attribute */
+/*
+ * Add scfw image with exec attribute
+ * use same name as in arch/arm/dts/imx8qxp-u-boot.dtsi
+ */
+IMAGE SCU mx8qx-mek-scfw-tcm.bin
+
+/* Add SPL image with exec attribute */
 IMAGE A35 spl/u-boot-spl.bin 0x00100000
diff --git a/board/siemens/capricorn/spl.c b/board/siemens/capricorn/spl.c
index 696b5eb..5865cde 100644
--- a/board/siemens/capricorn/spl.c
+++ b/board/siemens/capricorn/spl.c
@@ -15,12 +15,31 @@
 #include <dm/uclass-internal.h>
 #include <dm/device-internal.h>
 
+#include <firmware/imx/sci/sci.h>
+#include <asm/arch/imx8-pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include "spl_memory_test.h"
+
 DECLARE_GLOBAL_DATA_PTR;
 
+#define GPIO_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
+			(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+			(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+			(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define USDHC2_SD_PWR IMX_GPIO_NR(4, 19)
+static iomux_cfg_t usdhc2_sd_pwr[] = {
+	SC_P_USDHC1_RESET_B | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+};
+
 void spl_board_init(void)
 {
 	struct udevice *dev;
 
+	uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(imx8_scu), &dev);
+
 	uclass_find_first_device(UCLASS_MISC, &dev);
 
 	for (; dev; uclass_find_next_device(&dev)) {
@@ -34,8 +53,32 @@
 
 	timer_init();
 
+	imx8_iomux_setup_multiple_pads(usdhc2_sd_pwr, ARRAY_SIZE(usdhc2_sd_pwr));
+	gpio_direction_output(USDHC2_SD_PWR, 0);
+
 	preloader_console_init();
+
+	puts("Normal Boot\n");
+
+#if IS_ENABLED(CONFIG_SPL_CMT)
+	spl_siemens_memory_full_test();
+#endif
+}
+
+void spl_board_prepare_for_boot(void)
+{
+	imx8_power_off_pd_devices(NULL, 0);
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
 }
+#endif
 
 void board_init_f(ulong dummy)
 {
diff --git a/board/siemens/capricorn/spl_memory_test.c b/board/siemens/capricorn/spl_memory_test.c
new file mode 100644
index 0000000..84c97e7
--- /dev/null
+++ b/board/siemens/capricorn/spl_memory_test.c
@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright Siemens AG 2020
+ *
+ * SPL Full Memory Test
+ * - memory test through the full DDR area
+ * - refresh over temperature torture (write all, read all)
+ *
+ * Remark:
+ * This test has ran properly with the definition of the RAM sizes in board
+ * headers. Since these headers are removed it's necessary to set the correct
+ * values to PHYS_SDRAM_1_SIZE & PHYS_SDRAM_2_SIZE before to recompile.
+ *
+ * An alternative is to refactor the code to get the size info from system
+ * controller
+ */
+
+#include <init.h>
+#include <log.h>
+
+/* ----- Defines ----- */
+#define CHECK_LOWER_UPPER
+
+#define LEVEL2_PRINT    0x0FFFFFFF
+
+/* use 0x7FFF0000 for shorter loop test */
+#define BASE_OFFSET	0x00000000
+
+/* ----- Types ----- */
+struct ct_t {
+	unsigned long *start;
+	unsigned long *end;
+};
+
+/* ----- Variables ----- */
+static struct ct_t ct;
+static unsigned long error_counter;
+
+static void print_parameters(void)
+{
+	printf("\nstart addr: %p\n", ct.start);
+	printf("end addr  : %p\n", ct.end);
+}
+
+static void run_test(void)
+{
+	/* moved full test in one void */
+	unsigned long *address; /* 512 */
+	unsigned long ebyte1;
+	unsigned long ebyte2;
+	unsigned int i;
+	unsigned long rpattern;
+
+	for (i = 0; i <= 255; i++) {
+		memset(&ebyte1, i, sizeof(ebyte1));
+		ebyte2 = ~ebyte1;
+		printf("LWord: %016lx  #LWord: %016lx\n", ebyte1, ebyte2);
+
+		/* write  all bytes -> duration ~ 150 s */
+		for (address = ct.start; address <= ct.end; address++) {
+#ifdef LEVEL2_PRINT
+			if (((unsigned long)address & LEVEL2_PRINT) == 0)
+				printf("write to %p - %p\n", address,
+				       (void *)((unsigned long)address +
+				       LEVEL2_PRINT));
+#endif
+			*address = ebyte1;
+			address++;
+			*address = ebyte2;
+		}
+
+		/* check all bytes */
+		for (address = ct.start; address <= ct.end; address++) {
+#ifdef LEVEL2_PRINT
+			if (((unsigned long)address & LEVEL2_PRINT) == 0)
+				printf("check from %p - %p\n", address,
+				       (void *)((unsigned long)address +
+				       LEVEL2_PRINT));
+#endif
+
+			rpattern = *address;
+			if (rpattern != ebyte1) {
+				error_counter++;
+				printf("Error! Read: %016lX Wrote: %016lX Address: %p\n",
+				       rpattern, ebyte1, address);
+			}
+
+			address++;
+			rpattern = *address;
+			if (rpattern != ebyte2) {
+				error_counter++;
+				printf("Error! Read: %016lX Wrote: %016lX Address: %p\n",
+				       rpattern, ebyte2, address);
+			}
+		}
+	}
+}
+
+#ifdef CHECK_LOWER_UPPER
+void test_lower_upper(void)
+{
+	/*
+	 * write different values at the same address of both memory areas
+	 * and check them
+	 */
+#define TEST_ADDRESS	 0x12345670UL
+#define LOWER_ADDRESS	(PHYS_SDRAM_1 + TEST_ADDRESS)
+#define UPPER_ADDRESS	(PHYS_SDRAM_2 + TEST_ADDRESS)
+#define LOWER_VALUE	0x0011223344556677
+#define UPPER_VALUE	0x89ab89abffeeddcc
+
+	*(unsigned long *)LOWER_ADDRESS = LOWER_VALUE;
+	*(unsigned long *)UPPER_ADDRESS = UPPER_VALUE;
+
+	puts("\nlower-upper memory area test\n");
+	printf("write %016lx to   lower address %010lx\n", LOWER_VALUE,
+	       LOWER_ADDRESS);
+	printf("write %016lx to   upper address %010lx\n", UPPER_VALUE,
+	       UPPER_ADDRESS);
+	printf("read  %016lx from lower address %010lx\n",
+	       *(unsigned long *)LOWER_ADDRESS, LOWER_ADDRESS);
+	printf("read  %016lx from upper address %010lx\n",
+	       *(unsigned long *)UPPER_ADDRESS, UPPER_ADDRESS);
+}
+#endif
+
+void spl_siemens_memory_full_test(void)
+{
+	unsigned long loopc = 0;
+
+	puts("\nSPL: memory cell test\n");
+
+#ifdef CHECK_LOWER_UPPER
+	if (PHYS_SDRAM_2_SIZE != 0)
+		test_lower_upper();
+#endif
+
+	while (true) {
+		/* imx8x has 2 memory areas up to 2 GB */
+
+		/* 1st memory area @ 0x80000000 */
+		ct.start = (unsigned long *)(PHYS_SDRAM_1 + BASE_OFFSET);
+		ct.end = (unsigned long *)(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - 1);
+		print_parameters();
+		run_test();
+
+		/* 2nd memory area @ 0x880000000 */
+		if (PHYS_SDRAM_2_SIZE != 0) {
+			ct.start = (unsigned long *)(PHYS_SDRAM_2 + BASE_OFFSET);
+			ct.end = (unsigned long *)(PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE - 1);
+			print_parameters();
+			run_test();
+		}
+
+		loopc++;
+		printf("loop: %ld, errors: %ld\n\n", loopc, error_counter);
+	};
+}
diff --git a/board/siemens/capricorn/spl_memory_test.h b/board/siemens/capricorn/spl_memory_test.h
new file mode 100644
index 0000000..28df284
--- /dev/null
+++ b/board/siemens/capricorn/spl_memory_test.h
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright Siemens AG 2020
+ *
+ */
+
+void spl_siemens_memory_full_test(void);
diff --git a/board/siemens/common/Kconfig b/board/siemens/common/Kconfig
index 131439f..4ae12b1 100644
--- a/board/siemens/common/Kconfig
+++ b/board/siemens/common/Kconfig
@@ -1,2 +1,6 @@
 config FACTORYSET
 	bool
+
+config DDR_SI_TEST
+	bool "DDR signal integrity test implementations"
+	default y
diff --git a/board/siemens/common/board.h b/board/siemens/common/board.h
new file mode 100644
index 0000000..db34bc7
--- /dev/null
+++ b/board/siemens/common/board.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Common board functions for siemens based boards
+ * (C) Copyright 2022 Siemens Schweiz AG
+ */
+
+#ifndef __COMMON_BOARD_H
+#define __COMMON_BOARD_H
+
+/*
+ * Chip data
+ * Offset in EEPROM: 0x120 - 0x14F
+ *
+ * -----------------------------------------------------------------------------------
+ * | Address range |                          Content                                |
+ * -----------------------------------------------------------------------------------
+ * | 0x120 - 0x123 |  Magic Number - 0x43484950 (4 byte)                             |
+ * -----------------------------------------------------------------------------------
+ * | 0x124 - 0x133 |  Device Nomenclature (15 + 1 byte)                              |
+ * -----------------------------------------------------------------------------------
+ * | 0x134 - 0x13A |  HW Version of the form "v00.00" (6 + 1 byte)                 |
+ * |               |   - First 2 digits: Layout revision (starting from 1)           |
+ * |               |   - Last 2 digits: Assembly variant revision (starting from 1)  |
+ * -----------------------------------------------------------------------------------
+ * | 0x13B - 0x13F |  Flash Size in Gibit (4 + 1 byte)                               |
+ * -----------------------------------------------------------------------------------
+ * | 0x140 - 0x144 |  Ram Size in Gibit (4 + 1 byte)                                 |
+ * -----------------------------------------------------------------------------------
+ * | 0x145 - 0x14F |  Sequence number, equals DMC-code (10 + 1 byte) [OBSOLETE]      |
+ * -----------------------------------------------------------------------------------
+ */
+
+#define MAGIC_CHIP		0x50494843
+#define EEPROM_CHIP_OFFSET	0x120
+
+struct chip_data {
+	unsigned int magic;
+	char sdevname[16];
+	char shwver[7];
+	char flash_size[5];
+	char ram_size[5];
+};
+
+#endif /* __COMMON_BOARD_H */
diff --git a/board/siemens/common/ddr_si_test.c b/board/siemens/common/ddr_si_test.c
new file mode 100644
index 0000000..c1f523e
--- /dev/null
+++ b/board/siemens/common/ddr_si_test.c
@@ -0,0 +1,348 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright Siemens AG 2023
+ *
+ * DDR signal integrity test
+ *   Check signals on DDR lines
+ *   - signals must be as fast as possible and generate long burst
+ *   - signals must be unidirectional (to DDR or from DDR only)
+ *
+ *   Set pattern: define 2^n 32-bit patterns (up to 4)
+ *   Addresses: must be multiple of 16 to avoid checks in loops
+ *   Test functions
+ *   - write: write pattern to memory area for iteration times
+ *   - read: write pattern once to memory area, read for iteration times
+ */
+
+#include <command.h>
+#include <exports.h>
+#include <time.h>
+#if CONFIG_IS_ENABLED(AM33XX)
+#include <asm/arch-am33xx/hardware_am33xx.h>
+#include <asm/arch-am33xx/cpu.h>
+#include <asm/io.h>
+#endif
+
+/* enable some print for debugging */
+#ifdef PR_DEBUG
+	#define PDEBUG(fmt, args...) printf(fmt, ## args)
+#else
+	#define PDEBUG(fmt, args...)
+#endif
+
+/* define 4 32-bit patterns */
+#define MAX_PTN_SIZE (128)
+#define PTN_ARRAY_SIZE (MAX_PTN_SIZE / (8 * sizeof(u32)))
+
+/* define test direction */
+#define DIR_READ	0
+#define DIR_WRITE	1
+
+static union {
+	u64 l[2];
+	u32 s[4];
+	} test_pattern;
+static int num_ptn32;
+
+#if CONFIG_IS_ENABLED(AM33XX)
+static inline void wdt_disable(void)
+{
+	struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+
+	writel(0xAAAA, &wdtimer->wdtwspr);
+	while (readl(&wdtimer->wdtwwps) != 0x0)
+		;
+	writel(0x5555, &wdtimer->wdtwspr);
+	while (readl(&wdtimer->wdtwwps) != 0x0)
+		;
+}
+
+static inline void wdt_enable(void)
+{
+	struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+
+	writel(0xBBBB, &wdtimer->wdtwspr);
+	while (readl(&wdtimer->wdtwwps) != 0x0)
+		;
+	writel(0x4444, &wdtimer->wdtwspr);
+	while (readl(&wdtimer->wdtwwps) != 0x0)
+		;
+}
+#else /* ! */
+static inline void wdt_disable(void) {}
+
+static inline void wdt_enable(void) {}
+#endif /* CONFIG_IS_ENABLED(AM33XX) */
+
+static int do_ddr_set_ptn(struct cmd_tbl *cmdtp, int flag, int argc,
+			  char *const argv[])
+{
+	int i, n;
+
+	if (argc < 1)
+		return CMD_RET_USAGE;
+
+	/* number of patterns: 2 exponent */
+	n = argc - 1;
+	if (n > PTN_ARRAY_SIZE || (n & (n - 1)))
+		return CMD_RET_USAGE;
+	num_ptn32 = n;
+
+	/* get patterns */
+	for (i = 0; i < n; i++)
+		test_pattern.s[i] = simple_strtoul(argv[i + 1], NULL, 0);
+
+	printf("Test pattern set\n");
+
+	return CMD_RET_SUCCESS;
+}
+
+static int do_ddr_show_ptn(struct cmd_tbl *cmdtp, int flag, int argc,
+			   char *const argv[])
+{
+	if (!num_ptn32) {
+		printf("No pattern available\n");
+	} else {
+		u32 *buf = test_pattern.s;
+		int len = num_ptn32;
+		int i;
+
+		printf("Pattern: ");
+		for (i = 0 ; i < len; i++)
+			printf("0x%08X ", *buf++);
+
+		printf("\n");
+	}
+
+	return CMD_RET_SUCCESS;
+}
+
+static void ddr_read32(u64 start_addr, u64 n_word, unsigned long iter)
+{
+	while (iter--) {
+		register volatile u32 *addr = (u32 *)start_addr;
+		register u64 count = n_word;
+
+		while (count) {
+			(void)*addr++;
+			PDEBUG("Read 0x%08X from 0x%p\n", val, addr - 1);
+			count--;
+		}
+	}
+}
+
+static void ddr_read64(u64 start_addr, u64 n_word, unsigned long iter)
+{
+	while (iter--) {
+		register volatile u64 *addr = (u64 *)start_addr;
+		register u64 count = n_word;
+
+		if (num_ptn32 == 4)
+			count *= 2;
+
+		/*
+		 * 64 & 128 bit pattern. Increase the nummber of read
+		 * commands in the loop to generate longer burst signal
+		 */
+		while (count) {
+			(void)*addr++;
+			PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1);
+			(void)*addr++;
+			PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1);
+			(void)*addr++;
+			PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1);
+			(void)*addr++;
+			PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1);
+			(void)*addr++;
+			PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1);
+			(void)*addr++;
+			PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1);
+			(void)*addr++;
+			PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1);
+			(void)*addr++;
+			PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1);
+			/*
+			 * underflow cannot happen since n_word = end -
+			 * start, end & start addresses are checked to be
+			 * multiple of 16
+			 */
+			count -= 8;
+		}
+	}
+}
+
+static void ddr_write32(u64 start_addr, u64 n_word, unsigned long iter)
+{
+	while (iter--) {
+		register u32 *addr = (u32 *)start_addr;
+		register u32 ptn = *test_pattern.s;
+		register u64 count = n_word;
+
+		while (count) {
+			PDEBUG("Write 0x%08X to 0x%p\n", ptn, addr);
+			*addr++ = ptn;
+			count--;
+		}
+	}
+}
+
+static void ddr_write64(u64 start_addr, u64 n_word, unsigned long iter)
+{
+	while (iter--) {
+		register u64 *addr = (u64 *)start_addr;
+		register u64 ptnA = test_pattern.l[0];
+		register u64 ptnB = test_pattern.l[1];
+		register u64 count = n_word;
+
+		if (num_ptn32 == 2)
+			ptnB = ptnA;
+		else
+			count *= 2;
+
+		/*
+		 * 64 & 128 bit pattern. Increase the nummber of write
+		 * commands in the loop to generate longer burst signal
+		 */
+		while (count) {
+			PDEBUG("Write 0x%016llX to 0x%p\n", ptnA, addr);
+			*addr++ = ptnA;
+			PDEBUG("Write 0x%016llX to 0x%p\n", ptnB, addr);
+			*addr++ = ptnB;
+			PDEBUG("Write 0x%016llX to 0x%p\n", ptnA, addr);
+			*addr++ = ptnA;
+			PDEBUG("Write 0x%016llX to 0x%p\n", ptnB, addr);
+			*addr++ = ptnB;
+			PDEBUG("Write 0x%016llX to 0x%p\n", ptnA, addr);
+			*addr++ = ptnA;
+			PDEBUG("Write 0x%016llX to 0x%p\n", ptnB, addr);
+			*addr++ = ptnB;
+			PDEBUG("Write 0x%016llX to 0x%p\n", ptnA, addr);
+			*addr++ = ptnA;
+			PDEBUG("Write 0x%016llX to 0x%p\n", ptnB, addr);
+			*addr++ = ptnB;
+			/*
+			 * underflow cannot happen since n_word = end -
+			 * start, end & start addresses are checked to be
+			 * multiple of 16
+			 */
+			count -= 8;
+		}
+	}
+}
+
+static int do_ddr_si_test(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	u64 start_addr, end_addr, n_word;
+	u64 ts_start, ts_end;
+	unsigned long iteration, wr_iter;
+	int direction, i;
+
+	if (argc < 3 || argc > 4)
+		return CMD_RET_USAGE;
+
+	/* get arguments */
+	direction = strcmp(argv[0], "read") ? DIR_WRITE : DIR_READ;
+	start_addr = simple_strtoul(argv[1], NULL, 0);
+	end_addr = simple_strtoul(argv[2], NULL, 0);
+	iteration = simple_strtoul(argv[3], NULL, 10);
+
+	n_word = (end_addr - start_addr) / (num_ptn32 * 4);
+	printf("\nDDR signal integrity %s test: start\n", argv[0]);
+	/* checks */
+	if (start_addr & 0xF) {
+		printf("ERROR: start_address should be 16 bytes aligned\n\n");
+		return CMD_RET_USAGE;
+	}
+
+	if (end_addr & 0xF) {
+		printf("ERROR: end_address should be 16 bytes aligned\n\n");
+		return CMD_RET_USAGE;
+	}
+
+	if (start_addr >= end_addr) {
+		printf("ERROR: end_address is not bigger than start_address\n\n");
+		return CMD_RET_USAGE;
+	}
+
+	if (!iteration) {
+		printf("ERROR: no iteration specified\n\n");
+		return CMD_RET_USAGE;
+	}
+
+	if (!num_ptn32) {
+		printf("ERROR: no test pattern specified\n\n");
+		return CMD_RET_USAGE;
+	}
+
+	/* print parameters */
+	printf("start_address = 0x%016llX\n", start_addr);
+	printf("end_address   = 0x%016llX\n", end_addr);
+	printf("iterations = %lu\n", iteration);
+
+	/* print pattern */
+	printf("test pattern 0x");
+	for (i = 0; i < num_ptn32; i++)
+		printf("%08X", test_pattern.s[i]);
+
+	printf("\n");
+
+	wdt_disable();
+
+	/* writing */
+	printf("Writing..\n");
+	ts_start = get_timer_us(0);
+
+	if (direction == DIR_READ)
+		wr_iter = 1;
+	else
+		wr_iter = iteration;
+
+	if (num_ptn32 == 1)
+		ddr_write32(start_addr, n_word, wr_iter);
+	else
+		ddr_write64(start_addr, n_word, wr_iter);
+
+	ts_end = get_timer_us(0);
+
+	/* reading */
+	if (direction == DIR_READ) {
+		printf("Reading..\n");
+		/* we need read time, just overwrite */
+		ts_start = get_timer_us(0);
+
+		if (num_ptn32 == 1)
+			ddr_read32(start_addr, n_word, iteration);
+		else
+			ddr_read64(start_addr, n_word, iteration);
+
+		ts_end = get_timer_us(0);
+	}
+
+	wdt_enable();
+
+	/* print stats */
+	printf("DONE.");
+	printf(" Bytes=%llu ", n_word * num_ptn32 * 4 * iteration);
+	printf(" Time=%llu us ", ts_end - ts_start);
+	printf("\nDDR signal integrity %s test: end\n", argv[0]);
+
+	return CMD_RET_SUCCESS;
+}
+
+static char ddr_si_help_text[] =
+	"- DDR signal integrity test\n\n"
+	"ddr_si setptn <pattern> [<pattern>] : set [1,2,4] 32-bit patterns\n"
+	"ddr_si showptn : show patterns\n"
+	"ddr_si read <start> <end> <iterations> : run test for reading\n"
+	"ddr_si write <start> <end> <iterations> : run test for writing\n"
+	"\nWith\n"
+	"\t<pattern>: 32-bit pattern in hex format\n"
+	"\t<start>: test start address in hex format\n"
+	"\t<end>: test end address in hex format\n"
+	"\t<iterations>: number of iterations\n";
+
+U_BOOT_CMD_WITH_SUBCMDS(ddr_si, "DDR si test", ddr_si_help_text,
+			U_BOOT_SUBCMD_MKENT(setptn, 5, 0, do_ddr_set_ptn),
+			U_BOOT_SUBCMD_MKENT(showptn, 1, 0, do_ddr_show_ptn),
+			U_BOOT_SUBCMD_MKENT(read, 4, 0, do_ddr_si_test),
+			U_BOOT_SUBCMD_MKENT(write, 4, 0, do_ddr_si_test));
diff --git a/board/siemens/draco/board.h b/board/siemens/draco/board.h
index 935f340..77f35a6 100644
--- a/board/siemens/draco/board.h
+++ b/board/siemens/draco/board.h
@@ -11,6 +11,8 @@
 #ifndef _BOARD_DRACO_H_
 #define _BOARD_DRACO_H_
 
+#include "../common/board.h"
+
 #define PARGS(x)	#x , /* Parameter Name */ \
 			settings.ddr3.x, /* EEPROM Value */ \
 			ddr3_default.x, /* Default Value */ \
@@ -18,8 +20,6 @@
 
 #define PRINTARGS(y)	printf("%-20s, %8x, %8x, %4d\n", PARGS(y))
 
-#define MAGIC_CHIP	0x50494843
-
 /* Automatic generated definition */
 /* Wed, 16 Apr 2014 16:50:41 +0200 */
 /* From file: draco/ddr3-data-universal-default@303MHz-i0-ES3.txt */
@@ -43,12 +43,6 @@
 	char manu_marking[32];			/* "default \0" */
 };
 
-struct chip_data {
-	unsigned int  magic;
-	char sdevname[16];
-	char shwver[7];
-};
-
 struct draco_baseboard_id {
 	struct ddr3_data ddr3;
 	struct chip_data chip;
diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index e9269ef..b543bf8 100644
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -385,7 +385,7 @@
 	int phy_addr = -ENOENT;
 
 #ifdef CONFIG_FEC_MXC
-	bus = fec_get_miibus(ENET_BASE_ADDR, -1);
+	bus = fec_get_miibus(NULL, ENET_BASE_ADDR, -1);
 	if (!bus)
 		return -ENOENT;
 
diff --git a/board/xilinx/Kconfig b/board/xilinx/Kconfig
index 0ff8440..f7152d6 100644
--- a/board/xilinx/Kconfig
+++ b/board/xilinx/Kconfig
@@ -40,6 +40,15 @@
 
 endif
 
+config XILINX_MINI
+	bool "Mini configuration"
+	depends on ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2
+	help
+	  This option disables features which are not needed for Mini U-Boot
+	  configurations. Mini U-Boot is running in EL3 mostly on size contrained
+	  systems. It's purpose is to program non volatile memories or running
+	  initial memory tests.
+
 config XILINX_OF_BOARD_DTB_ADDR
 	hex "Default DTB pickup address"
 	default 0x1000 if ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2
diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
index 38dd805..a12dccd 100644
--- a/board/xilinx/common/board.c
+++ b/board/xilinx/common/board.c
@@ -19,6 +19,7 @@
 #include <i2c.h>
 #include <linux/sizes.h>
 #include <malloc.h>
+#include <memtop.h>
 #include <mtd_node.h>
 #include "board.h"
 #include <dm.h>
@@ -676,3 +677,31 @@
 	return 0;
 }
 #endif
+
+#ifndef CONFIG_XILINX_MINI
+
+#ifndef MMU_SECTION_SIZE
+#define MMU_SECTION_SIZE        (1 * 1024 * 1024)
+#endif
+
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
+{
+	phys_size_t size;
+	phys_addr_t reg;
+
+	if (!total_size)
+		return gd->ram_top;
+
+	if (!IS_ALIGNED((ulong)gd->fdt_blob, 0x8))
+		panic("Not 64bit aligned DT location: %p\n", gd->fdt_blob);
+
+	size = ALIGN(CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE);
+	reg = get_mem_top(gd->ram_base, gd->ram_size, size,
+			  (void *)gd->fdt_blob);
+	if (!reg)
+		reg = gd->ram_top - size;
+
+	return reg + size;
+}
+
+#endif
diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c
index 3947467..fd5c6ce 100644
--- a/board/xilinx/versal/board.c
+++ b/board/xilinx/versal/board.c
@@ -12,12 +12,15 @@
 #include <env_internal.h>
 #include <log.h>
 #include <malloc.h>
+#include <memalign.h>
+#include <mmc.h>
 #include <time.h>
 #include <asm/cache.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
+#include <linux/sizes.h>
 #include <dm/device.h>
 #include <dm/uclass.h>
 #include <versalpl.h>
@@ -301,9 +304,11 @@
 	return 0;
 }
 
+#if !CONFIG_IS_ENABLED(SYSRESET)
 void reset_cpu(void)
 {
 }
+#endif
 
 #if defined(CONFIG_ENV_IS_NOWHERE)
 enum env_location env_get_location(enum env_operation op, int prio)
@@ -336,3 +341,41 @@
 	}
 }
 #endif
+
+#if defined(CONFIG_SET_DFU_ALT_INFO)
+
+#define DFU_ALT_BUF_LEN		SZ_1K
+
+void set_dfu_alt_info(char *interface, char *devstr)
+{
+	int bootseq = 0, len = 0;
+	u32 bootmode = versal_get_bootmode();
+
+	ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
+
+	if (env_get("dfu_alt_info"))
+		return;
+
+	memset(buf, 0, sizeof(buf));
+
+	switch (bootmode) {
+	case EMMC_MODE:
+	case SD_MODE:
+	case SD1_LSHFT_MODE:
+	case SD_MODE1:
+		bootseq = mmc_get_env_dev();
+
+		len += snprintf(buf + len, DFU_ALT_BUF_LEN, "mmc %d=boot",
+			       bootseq);
+
+		len += snprintf(buf + len, DFU_ALT_BUF_LEN, ".bin fat %d 1",
+			       bootseq);
+		break;
+	default:
+		return;
+	}
+
+	env_set("dfu_alt_info", buf);
+	puts("DFU alt info setting: done\n");
+}
+#endif
diff --git a/board/xilinx/zynqmp/zynqmp_kria.env b/board/xilinx/zynqmp/zynqmp_kria.env
index 927f398..ff3a092 100644
--- a/board/xilinx/zynqmp/zynqmp_kria.env
+++ b/board/xilinx/zynqmp/zynqmp_kria.env
@@ -77,6 +77,7 @@
 tpm_kd240=if test ${card1_rev} = A; then run tpm_reset; fi
 
 board_setup=\
+rtc dev 0; \
 zynqmp mmio_write 0xFFCA0010 0xfff 0; \
 if test ${card1_name} = SCK-KV-G; then run kv260_setup; run tpm_kv260; fi;\
 if test ${card1_name} = SCK-KR-G; then run kr260_setup; run tpm_reset; fi;\
diff --git a/boot/Kconfig b/boot/Kconfig
index 7dd30a0..661e89c 100644
--- a/boot/Kconfig
+++ b/boot/Kconfig
@@ -500,7 +500,6 @@
 	bool "Bootdev support for Android"
 	depends on X86 || ARM || SANDBOX
 	depends on CMDLINE
-	select ANDROID_AB
 	select ANDROID_BOOT_IMAGE
 	select CMD_BCB
 	imply CMD_FASTBOOT
diff --git a/boot/bootmeth_android.c b/boot/bootmeth_android.c
index 19b1f2c..3a5144a 100644
--- a/boot/bootmeth_android.c
+++ b/boot/bootmeth_android.c
@@ -29,6 +29,7 @@
 #define BCB_PART_NAME "misc"
 #define BOOT_PART_NAME "boot"
 #define VENDOR_BOOT_PART_NAME "vendor_boot"
+#define SLOT_LEN 2
 
 /**
  * struct android_priv - Private data
@@ -42,8 +43,10 @@
  */
 struct android_priv {
 	enum android_boot_mode boot_mode;
-	char slot[2];
+	char *slot;
 	u32 header_version;
+	u32 boot_img_size;
+	u32 vendor_boot_img_size;
 };
 
 static int android_check(struct udevice *dev, struct bootflow_iter *iter)
@@ -71,7 +74,11 @@
 	char *buf;
 	int ret;
 
-	sprintf(partname, BOOT_PART_NAME "_%s", priv->slot);
+	if (priv->slot)
+		sprintf(partname, BOOT_PART_NAME "_%s", priv->slot);
+	else
+		sprintf(partname, BOOT_PART_NAME);
+
 	ret = part_get_info_by_name(desc, partname, &partition);
 	if (ret < 0)
 		return log_msg_ret("part info", ret);
@@ -93,7 +100,13 @@
 		return log_msg_ret("header", -ENOENT);
 	}
 
+	if (!android_image_get_bootimg_size(buf, &priv->boot_img_size)) {
+		free(buf);
+		return log_msg_ret("get bootimg size", -EINVAL);
+	}
+
 	priv->header_version = ((struct andr_boot_img_hdr_v0 *)buf)->header_version;
+
 	free(buf);
 
 	return 0;
@@ -108,7 +121,11 @@
 	char *buf;
 	int ret;
 
+	if (priv->slot)
+		sprintf(partname, VENDOR_BOOT_PART_NAME "_%s", priv->slot);
+	else
+		sprintf(partname, VENDOR_BOOT_PART_NAME);
+
-	sprintf(partname, VENDOR_BOOT_PART_NAME "_%s", priv->slot);
 	ret = part_get_info_by_name(desc, partname, &partition);
 	if (ret < 0)
 		return log_msg_ret("part info", ret);
@@ -129,6 +146,12 @@
 		free(buf);
 		return log_msg_ret("header", -ENOENT);
 	}
+
+	if (!android_image_get_vendor_bootimg_size(buf, &priv->vendor_boot_img_size)) {
+		free(buf);
+		return log_msg_ret("get vendor bootimg size", -EINVAL);
+	}
+
 	free(buf);
 
 	return 0;
@@ -142,6 +165,11 @@
 	char slot_suffix[3];
 	int ret;
 
+	if (!CONFIG_IS_ENABLED(ANDROID_AB)) {
+		priv->slot = NULL;
+		return 0;
+	}
+
 	ret = part_get_info_by_name(desc, BCB_PART_NAME, &misc);
 	if (ret < 0)
 		return log_msg_ret("part", ret);
@@ -150,6 +178,7 @@
 	if (ret < 0)
 		return log_msg_ret("slot", ret);
 
+	priv->slot = malloc(SLOT_LEN);
 	priv->slot[0] = BOOT_SLOT_NAME(ret);
 	priv->slot[1] = '\0';
 
@@ -259,16 +288,12 @@
 		goto free_priv;
 	}
 
-	if (priv->header_version != 4) {
-		log_debug("only boot.img v4 is supported %u\n", priv->header_version);
-		ret = -EINVAL;
-		goto free_priv;
-	}
-
-	ret = scan_vendor_boot_part(bflow->blk, priv);
-	if (ret < 0) {
-		log_debug("scan vendor_boot failed: err=%d\n", ret);
-		goto free_priv;
+	if (priv->header_version >= 3) {
+		ret = scan_vendor_boot_part(bflow->blk, priv);
+		if (ret < 0) {
+			log_debug("scan vendor_boot failed: err=%d\n", ret);
+			goto free_priv;
+		}
 	}
 
 	/*
@@ -278,7 +303,7 @@
 	configure_serialno(bflow);
 	configure_bootloader_version(bflow);
 
-	if (priv->boot_mode == ANDROID_BOOT_MODE_NORMAL) {
+	if (priv->boot_mode == ANDROID_BOOT_MODE_NORMAL && priv->slot) {
 		ret = bootflow_cmdline_set_arg(bflow, "androidboot.force_normal_boot",
 					       "1", false);
 		if (ret < 0) {
@@ -319,28 +344,44 @@
  * @blk: Block device to read
  * @name: Partition name to read
  * @slot: Nul-terminated slot suffixed to partition name ("a\0" or "b\0")
+ * @image_size: Image size in bytes used when reading the partition
  * @addr: Address where the partition content is loaded into
  * Return: 0 if OK, negative errno on failure.
  */
 static int read_slotted_partition(struct blk_desc *desc, const char *const name,
-				  const char slot[2], ulong addr)
+				  const char slot[2], ulong image_size, ulong addr)
 {
 	struct disk_partition partition;
 	char partname[PART_NAME_LEN];
+	size_t partname_len;
+	ulong num_blks = DIV_ROUND_UP(image_size, desc->blksz);
 	int ret;
 	u32 n;
 
+	/*
+	 * Ensure name fits in partname.
+	 * For A/B, it should be <name>_<slot>\0
+	 * For non A/B, it should be <name>\0
+	 */
+	if (CONFIG_IS_ENABLED(ANDROID_AB))
+		partname_len = PART_NAME_LEN - 2 - 1;
+	else
+		partname_len = PART_NAME_LEN - 1;
+
-	/* Ensure name fits in partname it should be: <name>_<slot>\0 */
-	if (strlen(name) > (PART_NAME_LEN - 2 - 1))
+	if (strlen(name) > partname_len)
 		return log_msg_ret("name too long", -EINVAL);
 
-	sprintf(partname, "%s_%s", name, slot);
+	if (slot)
+		sprintf(partname, "%s_%s", name, slot);
+	else
+		sprintf(partname, "%s", name);
+
 	ret = part_get_info_by_name(desc, partname, &partition);
 	if (ret < 0)
 		return log_msg_ret("part", ret);
 
-	n = blk_dread(desc, partition.start, partition.size, map_sysmem(addr, 0));
-	if (n < partition.size)
+	n = blk_dread(desc, partition.start, num_blks, map_sysmem(addr, 0));
+	if (n < num_blks)
 		return log_msg_ret("part read", -EIO);
 
 	return 0;
@@ -386,7 +427,7 @@
 	AvbSlotVerifyData *out_data;
 	enum avb_boot_state boot_state;
 	char *extra_args;
-	char slot_suffix[3];
+	char slot_suffix[3] = "";
 	bool unlocked = false;
 	int ret;
 
@@ -394,7 +435,8 @@
 	if (!avb_ops)
 		return log_msg_ret("avb ops", -ENOMEM);
 
-	sprintf(slot_suffix, "_%s", priv->slot);
+	if (priv->slot)
+		sprintf(slot_suffix, "_%s", priv->slot);
 
 	ret = avb_ops->read_is_device_unlocked(avb_ops, &unlocked);
 	if (ret != AVB_IO_RESULT_OK)
@@ -472,16 +514,22 @@
 	if (ret < 0)
 		return log_msg_ret("read slot", ret);
 
-	ret = read_slotted_partition(desc, "boot", priv->slot, loadaddr);
+	ret = read_slotted_partition(desc, "boot", priv->slot, priv->boot_img_size,
+				     loadaddr);
 	if (ret < 0)
 		return log_msg_ret("read boot", ret);
 
-	ret = read_slotted_partition(desc, "vendor_boot", priv->slot, vloadaddr);
-	if (ret < 0)
-		return log_msg_ret("read vendor_boot", ret);
-
+	if (priv->header_version >= 3) {
+		ret = read_slotted_partition(desc, "vendor_boot", priv->slot,
+					     priv->vendor_boot_img_size, vloadaddr);
+		if (ret < 0)
+			return log_msg_ret("read vendor_boot", ret);
+		set_avendor_bootimg_addr(vloadaddr);
+	}
 	set_abootimg_addr(loadaddr);
-	set_avendor_bootimg_addr(vloadaddr);
+
+	if (priv->slot)
+		free(priv->slot);
 
 	ret = bootm_boot_start(loadaddr, bflow->cmdline);
 
diff --git a/boot/bootmeth_extlinux.c b/boot/bootmeth_extlinux.c
index be8fbf4..c6ae6df 100644
--- a/boot/bootmeth_extlinux.c
+++ b/boot/bootmeth_extlinux.c
@@ -8,6 +8,7 @@
 
 #define LOG_CATEGORY UCLASS_BOOTSTD
 
+#include <asm/cache.h>
 #include <bootdev.h>
 #include <bootflow.h>
 #include <bootmeth.h>
@@ -159,7 +160,7 @@
 		return log_msg_ret("try", ret);
 	size = bflow->size;
 
-	ret = bootmeth_alloc_file(bflow, 0x10000, 1);
+	ret = bootmeth_alloc_file(bflow, 0x10000, ARCH_DMA_MINALIGN);
 	if (ret)
 		return log_msg_ret("read", ret);
 
diff --git a/boot/image-android.c b/boot/image-android.c
index cd01278..93b54bf 100644
--- a/boot/image-android.c
+++ b/boot/image-android.c
@@ -178,6 +178,51 @@
 	data->boot_img_total_size = end - (ulong)hdr;
 }
 
+bool android_image_get_bootimg_size(const void *hdr, u32 *boot_img_size)
+{
+	struct andr_image_data data;
+
+	if (!hdr || !boot_img_size) {
+		printf("hdr or boot_img_size can't be NULL\n");
+		return false;
+	}
+
+	if (!is_android_boot_image_header(hdr)) {
+		printf("Incorrect boot image header\n");
+		return false;
+	}
+
+	if (((struct andr_boot_img_hdr_v0 *)hdr)->header_version <= 2)
+		android_boot_image_v0_v1_v2_parse_hdr(hdr, &data);
+	else
+		android_boot_image_v3_v4_parse_hdr(hdr, &data);
+
+	*boot_img_size = data.boot_img_total_size;
+
+	return true;
+}
+
+bool android_image_get_vendor_bootimg_size(const void *hdr, u32 *vendor_boot_img_size)
+{
+	struct andr_image_data data;
+
+	if (!hdr || !vendor_boot_img_size) {
+		printf("hdr or vendor_boot_img_size can't be NULL\n");
+		return false;
+	}
+
+	if (!is_android_vendor_boot_image_header(hdr)) {
+		printf("Incorrect vendor boot image header\n");
+		return false;
+	}
+
+	android_vendor_boot_image_v3_v4_parse_hdr(hdr, &data);
+
+	*vendor_boot_img_size = data.vendor_boot_img_total_size;
+
+	return true;
+}
+
 bool android_image_get_data(const void *boot_hdr, const void *vendor_boot_hdr,
 			    struct andr_image_data *data)
 {
diff --git a/boot/image-board.c b/boot/image-board.c
index 1757e58..b726bd6 100644
--- a/boot/image-board.c
+++ b/boot/image-board.c
@@ -624,9 +624,10 @@
 	void *buf;
 	int conf_noffset;
 	int fit_img_result;
-	const char *uname, *name;
+	const char *uname, *name, *compatible;
 	int err;
 	int devnum = 0; /* TODO support multi fpga platforms */
+	int flags = 0;
 
 	if (!IS_ENABLED(CONFIG_FPGA))
 		return -ENOSYS;
@@ -674,20 +675,29 @@
 			return fit_img_result;
 		}
 
+		conf_noffset = fit_image_get_node(buf, uname);
+		compatible = fdt_getprop(buf, conf_noffset, "compatible", NULL);
+		if (!compatible) {
+			printf("'fpga' image without 'compatible' property\n");
+		} else {
+			if (CONFIG_IS_ENABLED(FPGA_LOAD_SECURE))
+				flags = fpga_compatible2flag(devnum, compatible);
+		}
+
 		if (!fpga_is_partial_data(devnum, img_len)) {
 			name = "full";
 			err = fpga_loadbitstream(devnum, (char *)img_data,
 						 img_len, BIT_FULL);
 			if (err)
 				err = fpga_load(devnum, (const void *)img_data,
-						img_len, BIT_FULL, 0);
+						img_len, BIT_FULL, flags);
 		} else {
 			name = "partial";
 			err = fpga_loadbitstream(devnum, (char *)img_data,
 						 img_len, BIT_PARTIAL);
 			if (err)
 				err = fpga_load(devnum, (const void *)img_data,
-						img_len, BIT_PARTIAL, 0);
+						img_len, BIT_PARTIAL, flags);
 		}
 
 		if (err)
diff --git a/boot/upl_read.c b/boot/upl_read.c
index 5063897..be3e1d1 100644
--- a/boot/upl_read.c
+++ b/boot/upl_read.c
@@ -520,7 +520,7 @@
 		return log_msg_ret("reg", -EINVAL);
 	}
 
-	len = decode_addr_size(upl, buf, sizeof(buf), &gra->reg);
+	len = decode_addr_size(upl, buf, size, &gra->reg);
 	if (len < 0)
 		return log_msg_ret("buf", len);
 
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 8f3ad94..702adfd 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -2016,7 +2016,9 @@
 config CMD_CDP
 	bool "cdp"
 	help
-	  Perform CDP network configuration
+	  The cdp command is used to announce the U-Boot device in the network
+	  and to retrieve configuration data including the VLAN id using the
+	  proprietary Cisco Discovery Protocol (CDP).
 
 config CMD_SNTP
 	bool "sntp"
@@ -2121,6 +2123,25 @@
 	  wget is a simple command to download kernel, or other files,
 	  from a http server over TCP.
 
+config WGET_HTTPS
+	bool "wget https"
+	depends on CMD_WGET
+	depends on PROT_TCP_LWIP
+	depends on MBEDTLS_LIB
+        select SHA256
+        select RSA
+        select ASYMMETRIC_KEY_TYPE
+        select ASYMMETRIC_PUBLIC_KEY_SUBTYPE
+        select X509_CERTIFICATE_PARSER
+        select PKCS7_MESSAGE_PARSER
+	select MBEDTLS_LIB_CRYPTO
+	select MBEDTLS_LIB_TLS
+	select RSA_VERIFY_WITH_PKEY
+	select X509_CERTIFICATE_PARSER
+	select PKCS7_MESSAGE_PARSER
+	help
+	  Enable TLS over http for wget.
+
 endif  # if CMD_NET
 
 config CMD_PXE
diff --git a/cmd/hash.c b/cmd/hash.c
index 60d482b..5b40982 100644
--- a/cmd/hash.c
+++ b/cmd/hash.c
@@ -25,7 +25,7 @@
 	char *s;
 	int flags = HASH_FLAG_ENV;
 
-	if (argc < (HARGS - 1))
+	if (argc < 4)
 		return CMD_RET_USAGE;
 
 #if IS_ENABLED(CONFIG_HASH_VERIFY)
diff --git a/cmd/net-common.c b/cmd/net-common.c
index 1c9fb83..1c6f11c 100644
--- a/cmd/net-common.c
+++ b/cmd/net-common.c
@@ -101,9 +101,6 @@
 	return cp->cmd(cmdtp, flag, argc, argv);
 }
 
-U_BOOT_CMD(
-	net, 3, 1, do_net,
-	"NET sub-system",
-	"list - list available devices\n"
-	"stats <device> - dump statistics for specified device\n"
-);
+U_BOOT_CMD(net, 3, 1, do_net, "NET sub-system",
+	   "list - list available devices\n"
+	   "stats <device> - dump statistics for specified device\n");
diff --git a/cmd/net-lwip.c b/cmd/net-lwip.c
index 42f8bd6..0fd446e 100644
--- a/cmd/net-lwip.c
+++ b/cmd/net-lwip.c
@@ -5,41 +5,31 @@
 #include <net.h>
 
 #if defined(CONFIG_CMD_DHCP)
-U_BOOT_CMD(
-        dhcp,   3,      1,      do_dhcp,
-        "boot image via network using DHCP/TFTP protocol",
-        "[loadAddress] [[hostIPaddr:]bootfilename]"
-);
+U_BOOT_CMD(dhcp, 3, 1, do_dhcp,
+	   "boot image via network using DHCP/TFTP protocol",
+	   "[loadAddress] [[hostIPaddr:]bootfilename]");
 #endif
 
 #if defined(CONFIG_CMD_PING)
-U_BOOT_CMD(
-	ping,	2,	1,	do_ping,
-	"send ICMP ECHO_REQUEST to network host",
-	"pingAddress"
-);
+U_BOOT_CMD(ping, 2, 1, do_ping, "send ICMP ECHO_REQUEST to network host",
+	   "pingAddress");
 #endif
 
 #if defined(CONFIG_CMD_TFTPBOOT)
-U_BOOT_CMD(
-	tftpboot,	3,	0,	do_tftpb,
-	"boot image via network using TFTP protocol\n",
-	"[loadAddress] [[hostIPaddr:]bootfilename]"
-);
+U_BOOT_CMD(tftpboot, 3, 0, do_tftpb,
+	   "boot image via network using TFTP protocol\n",
+	   "[loadAddress] [[hostIPaddr:]bootfilename]");
 #endif
 
 #if defined(CONFIG_CMD_DNS)
-U_BOOT_CMD(
-	dns,	3,	1,	do_dns,
-	"lookup the IP of a hostname",
-	"hostname [envvar]"
-);
+U_BOOT_CMD(dns, 3, 1, do_dns, "lookup the IP of a hostname",
+	   "hostname [envvar]");
 #endif
 
 #if defined(CONFIG_CMD_WGET)
-U_BOOT_CMD(
-	wget,   3,      1,      do_wget,
-	"boot image via network using HTTP protocol",
-	"[loadAddress] URL"
+U_BOOT_CMD(wget, 3, 1, do_wget,
+	   "boot image via network using HTTP/HTTPS protocol",
+	   "[loadAddress] url\n"
+	   "wget [loadAddress] [host:]path"
 );
 #endif
diff --git a/cmd/upl.c b/cmd/upl.c
index 4996f36..c9a823b 100644
--- a/cmd/upl.c
+++ b/cmd/upl.c
@@ -50,7 +50,7 @@
 			char *const argv[])
 {
 	struct upl s_upl, *upl = &s_upl;
-	struct unit_test_state uts;
+	struct unit_test_state uts = { 0 };
 	struct abuf buf;
 	oftree tree;
 	ulong addr;
diff --git a/common/Makefile b/common/Makefile
index 2ee5ef9..3599156 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -7,6 +7,7 @@
 ifndef CONFIG_XPL_BUILD
 obj-y += init/
 obj-y += main.o
+obj-y += memtop.o
 obj-y += exports.o
 obj-y += cli_getch.o cli_simple.o cli_readline.o
 obj-$(CONFIG_HUSH_OLD_PARSER) += cli_hush.o
diff --git a/common/memtop.c b/common/memtop.c
new file mode 100644
index 0000000..841d89e
--- /dev/null
+++ b/common/memtop.c
@@ -0,0 +1,171 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024, Linaro Limited
+ */
+
+#include <fdt_support.h>
+#include <fdtdec.h>
+#include <memtop.h>
+
+#include <asm/types.h>
+
+#define MEM_RGN_COUNT	16
+
+struct region {
+	phys_addr_t base;
+	phys_size_t size;
+};
+
+struct mem_region {
+	struct region rgn[MEM_RGN_COUNT];
+	uint count;
+};
+
+static void add_mem_region(struct mem_region *mem_rgn, phys_addr_t base,
+			   phys_size_t size)
+{
+	long i;
+
+	for (i = mem_rgn->count; i >= 0; i--) {
+		if (i && base < mem_rgn->rgn[i - 1].base) {
+			mem_rgn->rgn[i] = mem_rgn->rgn[i - 1];
+		} else {
+			mem_rgn->rgn[i].base = base;
+			mem_rgn->rgn[i].size = size;
+			break;
+		}
+	}
+
+	mem_rgn->count++;
+}
+
+static void mem_regions_init(struct mem_region *mem)
+{
+	uint i;
+
+	mem->count = 0;
+	for (i = 0; i < MEM_RGN_COUNT; i++) {
+		mem->rgn[i].base = 0;
+		mem->rgn[i].size = 0;
+	}
+}
+
+static int fdt_add_reserved_regions(struct mem_region *free_mem,
+				    struct mem_region *reserved_mem,
+				    void *fdt_blob)
+{
+	u64 addr, size;
+	int i, total, ret;
+	int nodeoffset, subnode;
+	struct fdt_resource res;
+
+	if (fdt_check_header(fdt_blob) != 0)
+		return -1;
+
+	/* process memreserve sections */
+	total = fdt_num_mem_rsv(fdt_blob);
+	assert_noisy(total < MEM_RGN_COUNT);
+	for (i = 0; i < total; i++) {
+		if (fdt_get_mem_rsv(fdt_blob, i, &addr, &size) != 0)
+			continue;
+		add_mem_region(reserved_mem, addr, size);
+	}
+
+	i = 0;
+	/* process reserved-memory */
+	nodeoffset = fdt_subnode_offset(fdt_blob, 0, "reserved-memory");
+	if (nodeoffset >= 0) {
+		subnode = fdt_first_subnode(fdt_blob, nodeoffset);
+		while (subnode >= 0) {
+			/* check if this subnode has a reg property */
+			ret = fdt_get_resource(fdt_blob, subnode, "reg", 0,
+					       &res);
+			if (!ret && fdtdec_get_is_enabled(fdt_blob, subnode)) {
+				addr = res.start;
+				size = res.end - res.start + 1;
+				assert_noisy(i < MEM_RGN_COUNT);
+				add_mem_region(reserved_mem, addr, size);
+			}
+
+			subnode = fdt_next_subnode(fdt_blob, subnode);
+			++i;
+		}
+	}
+
+	return 0;
+}
+
+static long addrs_overlap(phys_addr_t base1, phys_size_t size1,
+			  phys_addr_t base2, phys_size_t size2)
+{
+	const phys_addr_t base1_end = base1 + size1 - 1;
+	const phys_addr_t base2_end = base2 + size2 - 1;
+
+	return ((base1 <= base2_end) && (base2 <= base1_end));
+}
+
+static long region_overlap_check(struct mem_region *mem_rgn, phys_addr_t base,
+				 phys_size_t size)
+{
+	unsigned long i;
+	struct region *rgn = mem_rgn->rgn;
+
+	for (i = 0; i < mem_rgn->count; i++) {
+		phys_addr_t rgnbase = rgn[i].base;
+		phys_size_t rgnsize = rgn[i].size;
+
+		if (addrs_overlap(base, size, rgnbase, rgnsize))
+			break;
+	}
+
+	return (i < mem_rgn->count) ? i : -1;
+}
+
+static int find_ram_top(struct mem_region *free_mem,
+			struct mem_region *reserved_mem, phys_size_t size)
+{
+	long i, rgn;
+	phys_addr_t base = 0;
+	phys_addr_t res_base;
+
+	for (i = free_mem->count - 1; i >= 0; i--) {
+		phys_addr_t rgnbase = free_mem->rgn[i].base;
+		phys_size_t rgnsize = free_mem->rgn[i].size;
+
+		if (rgnsize < size)
+			continue;
+
+		base = rgnbase + rgnsize - size;
+		while (base && rgnbase <= base) {
+			rgn = region_overlap_check(reserved_mem, base, size);
+			if (rgn < 0)
+				return base;
+
+			res_base = reserved_mem->rgn[rgn].base;
+			if (res_base < size)
+				break;
+			base = res_base - size;
+		}
+	}
+
+	return 0;
+}
+
+phys_addr_t get_mem_top(phys_addr_t ram_start, phys_size_t ram_size,
+			phys_size_t size, void *fdt)
+{
+	int i;
+	struct mem_region free_mem;
+	struct mem_region reserved_mem;
+
+	mem_regions_init(&free_mem);
+	mem_regions_init(&reserved_mem);
+
+	add_mem_region(&free_mem, ram_start, ram_size);
+
+	i = fdt_add_reserved_regions(&free_mem, &reserved_mem, fdt);
+	if (i < 0)
+		return 0;
+
+	return find_ram_top(&free_mem, &reserved_mem, size);
+}
diff --git a/common/usb_onboard_hub.c b/common/usb_onboard_hub.c
index 68a04ac..6f28036 100644
--- a/common/usb_onboard_hub.c
+++ b/common/usb_onboard_hub.c
@@ -7,37 +7,203 @@
  * Mostly inspired by Linux kernel v6.1 onboard_usb_hub driver
  */
 
+#include <asm/gpio.h>
 #include <dm.h>
 #include <dm/device_compat.h>
+#include <i2c.h>
+#include <linux/delay.h>
 #include <power/regulator.h>
 
+#define USB5744_COMMAND_ATTACH		0x0056
+#define USB5744_COMMAND_ATTACH_LSB	0xAA
+#define USB5744_CONFIG_REG_ACCESS	0x0037
+#define USB5744_CONFIG_REG_ACCESS_LSB	0x99
+
 struct onboard_hub {
 	struct udevice *vdd;
+	struct gpio_desc *reset_gpio;
+};
+
+struct onboard_hub_data {
+	unsigned long reset_us;
+	unsigned long power_on_delay_us;
+	int (*init)(struct udevice *dev);
 };
 
+static int usb5744_i2c_init(struct udevice *dev)
+{
+	/*
+	 *  Prevent the MCU from the putting the HUB in suspend mode through register write.
+	 *  The BYPASS_UDC_SUSPEND bit (Bit 3) of the RuntimeFlags2 register at address
+	 *  0x411D controls this aspect of the hub.
+	 *  Format to write to hub registers via SMBus- 2D 00 00 05 00 01 41 1D 08
+	 *  Byte 0: Address of slave 2D
+	 *  Byte 1: Memory address 00
+	 *  Byte 2: Memory address 00
+	 *  Byte 3: Number of bytes to write to memory
+	 *  Byte 4: Write configuration register (00)
+	 *  Byte 5: Write the number of data bytes (01- 1 data byte)
+	 *  Byte 6: LSB of register address 0x41
+	 *  Byte 7: MSB of register address 0x1D
+	 *  Byte 8: value to be written to the register
+	 */
+	u8 data_buf[8] = {0x0, 0x5, 0x0, 0x1, 0x41, 0x1D, 0x08};
+	u8 config_reg_access_buf = USB5744_CONFIG_REG_ACCESS;
+	struct udevice *i2c_bus = NULL, *i2c_dev;
+	struct ofnode_phandle_args phandle;
+	u8 buf = USB5744_COMMAND_ATTACH;
+	struct dm_i2c_chip *i2c_chip;
+	int ret, slave_addr;
+
+	ret = dev_read_phandle_with_args(dev, "i2c-bus", NULL, 0, 0, &phandle);
+	if (ret) {
+		dev_err(dev, "i2c-bus not specified\n");
+		return ret;
+	}
+
+	ret = device_get_global_by_ofnode(ofnode_get_parent(phandle.node), &i2c_bus);
+	if (ret) {
+		dev_err(dev, "Failed to get i2c node, err: %d\n", ret);
+		return ret;
+	}
+
+	ret = ofnode_read_u32(phandle.node, "reg", &slave_addr);
+	if (ret)
+		return ret;
+
+	ret = i2c_get_chip(i2c_bus, slave_addr, 1, &i2c_dev);
+	if (ret) {
+		dev_err(dev, "%s: can't find i2c chip device for addr 0x%x\n", __func__,
+			slave_addr);
+		return ret;
+	}
+
+	i2c_chip = dev_get_parent_plat(i2c_dev);
+	if (!i2c_chip) {
+		dev_err(dev, "parent platform data not found\n");
+		return -EINVAL;
+	}
+
+	i2c_chip->flags &= ~DM_I2C_CHIP_WR_ADDRESS;
+	/* SMBus write command */
+	ret = dm_i2c_write(i2c_dev, 0, (uint8_t *)&data_buf, 8);
+	if (ret) {
+		dev_err(dev, "data_buf i2c_write failed, err:%d\n", ret);
+		return ret;
+	}
+
+	/* Configuration register access command */
+	ret = dm_i2c_write(i2c_dev, USB5744_CONFIG_REG_ACCESS_LSB,
+			   &config_reg_access_buf, 2);
+	if (ret) {
+		dev_err(dev, "config_reg_access i2c_write failed, err: %d\n", ret);
+		return ret;
+	}
+
+	/* USB Attach with SMBus */
+	ret = dm_i2c_write(i2c_dev, USB5744_COMMAND_ATTACH_LSB, &buf, 2);
+	if (ret) {
+		dev_err(dev, "usb_attach i2c_write failed, err: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+int usb_onboard_hub_reset(struct udevice *dev)
+{
+	struct onboard_hub_data *data =
+		(struct onboard_hub_data *)dev_get_driver_data(dev);
+	struct onboard_hub *hub = dev_get_priv(dev);
+	int ret;
+
+	hub->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_IS_OUT);
+
+	/* property is optional, don't return error! */
+	if (!hub->reset_gpio)
+		return 0;
+
+	ret = dm_gpio_set_value(hub->reset_gpio, 1);
+	if (ret)
+		return ret;
+
+	udelay(data->reset_us);
+
+	ret = dm_gpio_set_value(hub->reset_gpio, 0);
+	if (ret)
+		return ret;
+
+	udelay(data->power_on_delay_us);
+
+	return 0;
+}
+
 static int usb_onboard_hub_probe(struct udevice *dev)
 {
+	struct onboard_hub_data *data =
+		(struct onboard_hub_data *)dev_get_driver_data(dev);
 	struct onboard_hub *hub = dev_get_priv(dev);
 	int ret;
 
 	ret = device_get_supply_regulator(dev, "vdd-supply", &hub->vdd);
-	if (ret) {
+	if (ret && ret != -ENOENT) {
 		dev_err(dev, "can't get vdd-supply: %d\n", ret);
 		return ret;
 	}
 
-	ret = regulator_set_enable_if_allowed(hub->vdd, true);
+	if (hub->vdd) {
+		ret = regulator_set_enable_if_allowed(hub->vdd, true);
+		if (ret && ret != -ENOSYS) {
+			dev_err(dev, "can't enable vdd-supply: %d\n", ret);
+			return ret;
+		}
+	}
+
+	ret = usb_onboard_hub_reset(dev);
 	if (ret)
-		dev_err(dev, "can't enable vdd-supply: %d\n", ret);
+		return ret;
 
+	if (data->init) {
+		ret = data->init(dev);
+		if (ret) {
+			dev_err(dev, "onboard i2c init failed: %d\n", ret);
+			goto err;
+		}
+	}
+	return 0;
+err:
+	dm_gpio_set_value(hub->reset_gpio, 0);
 	return ret;
 }
 
+static int usb_onboard_hub_bind(struct udevice *dev)
+{
+	struct ofnode_phandle_args phandle;
+	const void *fdt = gd->fdt_blob;
+	int ret, off;
+
+	ret = dev_read_phandle_with_args(dev, "peer-hub", NULL, 0, 0, &phandle);
+	if (ret)  {
+		dev_err(dev, "peer-hub not specified\n");
+		return ret;
+	}
+
+	off = ofnode_to_offset(phandle.node);
+	ret = fdt_node_check_compatible(fdt, off, "usb424,5744");
+	if (!ret)
+		return 0;
+
+	return -ENODEV;
+}
+
 static int usb_onboard_hub_remove(struct udevice *dev)
 {
 	struct onboard_hub *hub = dev_get_priv(dev);
 	int ret;
 
+	if (hub->reset_gpio)
+		dm_gpio_free(hub->reset_gpio->dev, hub->reset_gpio);
+
 	ret = regulator_set_enable_if_allowed(hub->vdd, false);
 	if (ret)
 		dev_err(dev, "can't disable vdd-supply: %d\n", ret);
@@ -45,15 +211,34 @@
 	return ret;
 }
 
+static const struct onboard_hub_data usb2514_data = {
+	.power_on_delay_us = 500,
+	.reset_us = 1,
+};
+
+static const struct onboard_hub_data usb5744_data = {
+	.init = usb5744_i2c_init,
+	.power_on_delay_us = 1000,
+	.reset_us = 5,
+};
+
 static const struct udevice_id usb_onboard_hub_ids[] = {
 	/* Use generic usbVID,PID dt-bindings (usb-device.yaml) */
-	{ .compatible = "usb424,2514" }, /* USB2514B USB 2.0 */
-	{ }
+	{	.compatible = "usb424,2514",	/* USB2514B USB 2.0 */
+		.data = (ulong)&usb2514_data,
+	}, {
+		.compatible = "usb424,2744",	/* USB2744 USB 2.0 */
+		.data = (ulong)&usb5744_data,
+	}, {
+		.compatible = "usb424,5744",	/* USB5744 USB 3.0 */
+		.data = (ulong)&usb5744_data,
+	}
 };
 
 U_BOOT_DRIVER(usb_onboard_hub) = {
 	.name	= "usb_onboard_hub",
 	.id	= UCLASS_USB_HUB,
+	.bind   = usb_onboard_hub_bind,
 	.probe = usb_onboard_hub_probe,
 	.remove = usb_onboard_hub_remove,
 	.of_match = usb_onboard_hub_ids,
diff --git a/common/xyzModem.c b/common/xyzModem.c
index 09f74a1..698a538 100644
--- a/common/xyzModem.c
+++ b/common/xyzModem.c
@@ -280,6 +280,7 @@
 	    {
 	    case SOH:
 	      xyz.total_SOH++;
+	      fallthrough;
 	    case STX:
 	      if (c == STX)
 		xyz.total_STX++;
diff --git a/configs/10m50_defconfig b/configs/10m50_defconfig
index c4b4dfe..8180ed5 100644
--- a/configs/10m50_defconfig
+++ b/configs/10m50_defconfig
@@ -24,15 +24,15 @@
 # CONFIG_CMD_XIMG is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_ITEST is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_VERSION_VARIABLE=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SYS_RX_ETH_BUFFER=0
 CONFIG_ALTERA_PIO=y
 CONFIG_MISC=y
diff --git a/configs/3c120_defconfig b/configs/3c120_defconfig
index 077506e..0a6eae4 100644
--- a/configs/3c120_defconfig
+++ b/configs/3c120_defconfig
@@ -24,15 +24,15 @@
 # CONFIG_CMD_XIMG is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_ITEST is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_VERSION_VARIABLE=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SYS_RX_ETH_BUFFER=0
 CONFIG_ALTERA_PIO=y
 CONFIG_MISC=y
diff --git a/configs/CMPCPRO_defconfig b/configs/CMPCPRO_defconfig
index e92dc0c..7607135 100644
--- a/configs/CMPCPRO_defconfig
+++ b/configs/CMPCPRO_defconfig
@@ -135,8 +135,8 @@
 CONFIG_CMD_MTD=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_TEMPERATURE=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_SLEEP is not set
diff --git a/configs/M5235EVB_Flash32_defconfig b/configs/M5235EVB_Flash32_defconfig
index bf57c06..8aa8068 100644
--- a/configs/M5235EVB_Flash32_defconfig
+++ b/configs/M5235EVB_Flash32_defconfig
@@ -24,8 +24,8 @@
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_PCI=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_MII_INIT=y
 CONFIG_CMD_PING=y
diff --git a/configs/M5235EVB_defconfig b/configs/M5235EVB_defconfig
index 7cfec24..c76d655 100644
--- a/configs/M5235EVB_defconfig
+++ b/configs/M5235EVB_defconfig
@@ -23,8 +23,8 @@
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_PCI=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_MII_INIT=y
 CONFIG_CMD_PING=y
diff --git a/configs/M5275EVB_defconfig b/configs/M5275EVB_defconfig
index effff66..599eaf7 100644
--- a/configs/M5275EVB_defconfig
+++ b/configs/M5275EVB_defconfig
@@ -23,8 +23,8 @@
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_MII_INIT=y
 CONFIG_CMD_PING=y
diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig
index 8670712..37fe513 100644
--- a/configs/MPC8548CDS_36BIT_defconfig
+++ b/configs/MPC8548CDS_36BIT_defconfig
@@ -37,8 +37,8 @@
 CONFIG_LOADS_ECHO=y
 CONFIG_SYS_LOADS_BAUD_CHANGE=y
 CONFIG_CMD_PCI=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_HASH is not set
diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig
index e10e61a..4bc3ebe 100644
--- a/configs/MPC8548CDS_defconfig
+++ b/configs/MPC8548CDS_defconfig
@@ -36,8 +36,8 @@
 CONFIG_LOADS_ECHO=y
 CONFIG_SYS_LOADS_BAUD_CHANGE=y
 CONFIG_CMD_PCI=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_HASH is not set
diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig
index 9587975..2a22b8a 100644
--- a/configs/P1010RDB-PA_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig
@@ -5,7 +5,6 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
-CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_TPL_TEXT_BASE=0xD0000000
@@ -13,6 +12,7 @@
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_TPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SPL=y
 CONFIG_TPL_MAX_SIZE=0x20000
 CONFIG_MPC85xx=y
diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
index e703424..d2ac0b4 100644
--- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
@@ -7,11 +7,11 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x0
 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
-CONFIG_SPL_TEXT_BASE=0xD0000000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xD0000000
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
index 374879e..4913034 100644
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
@@ -8,10 +8,10 @@
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
-CONFIG_SPL_TEXT_BASE=0xD0000000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xD0000000
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig
index cd0117b..56e7357 100644
--- a/configs/P1010RDB-PA_NAND_defconfig
+++ b/configs/P1010RDB-PA_NAND_defconfig
@@ -5,7 +5,6 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
-CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_TPL_TEXT_BASE=0xD0000000
@@ -13,6 +12,7 @@
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_TPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SPL=y
 CONFIG_TPL_MAX_SIZE=0x20000
 CONFIG_MPC85xx=y
diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig
index af0fe29..1beb5bb 100644
--- a/configs/P1010RDB-PA_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_SDCARD_defconfig
@@ -7,11 +7,11 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x0
 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
-CONFIG_SPL_TEXT_BASE=0xD0000000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xD0000000
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig
index 8ed9d1a..a9275e5 100644
--- a/configs/P1010RDB-PA_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_SPIFLASH_defconfig
@@ -8,10 +8,10 @@
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
-CONFIG_SPL_TEXT_BASE=0xD0000000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xD0000000
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig
index 004ec92..d180f34 100644
--- a/configs/P1010RDB-PB_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig
@@ -5,7 +5,6 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
-CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_TPL_TEXT_BASE=0xD0000000
@@ -13,6 +12,7 @@
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_TPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SPL=y
 CONFIG_TPL_MAX_SIZE=0x20000
 CONFIG_MPC85xx=y
diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
index 635045f..4237dc9 100644
--- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
@@ -7,11 +7,11 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x0
 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
-CONFIG_SPL_TEXT_BASE=0xD0000000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xD0000000
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
index 4b7c8d2..3b5f6be 100644
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
@@ -8,10 +8,10 @@
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
-CONFIG_SPL_TEXT_BASE=0xD0000000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xD0000000
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig
index 3b29f1d..25c51c2 100644
--- a/configs/P1010RDB-PB_NAND_defconfig
+++ b/configs/P1010RDB-PB_NAND_defconfig
@@ -5,7 +5,6 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
-CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_TPL_TEXT_BASE=0xD0000000
@@ -13,6 +12,7 @@
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_TPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SPL=y
 CONFIG_TPL_MAX_SIZE=0x20000
 CONFIG_MPC85xx=y
diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig
index f12469d..5324e7b 100644
--- a/configs/P1010RDB-PB_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_SDCARD_defconfig
@@ -7,11 +7,11 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x0
 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
-CONFIG_SPL_TEXT_BASE=0xD0000000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xD0000000
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig
index 8c377d3..7bfa4eb 100644
--- a/configs/P1010RDB-PB_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_SPIFLASH_defconfig
@@ -8,10 +8,10 @@
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
-CONFIG_SPL_TEXT_BASE=0xD0000000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xD0000000
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig
index 36ef896..c889714 100644
--- a/configs/P1020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig
@@ -5,13 +5,13 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b"
-CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_TPL_TEXT_BASE=0xF8F80000
 CONFIG_TPL_LIBCOMMON_SUPPORT=y
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_TPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SPL=y
 CONFIG_TPL_MAX_SIZE=0x20000
 CONFIG_MPC85xx=y
diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
index b23add9..d1e097e 100644
--- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
@@ -7,10 +7,10 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x0
 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b"
-CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
index 98a48ef..ad7d5b6 100644
--- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -8,9 +8,9 @@
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b"
-CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig
index 6f19aac..2d5c83c 100644
--- a/configs/P1020RDB-PC_NAND_defconfig
+++ b/configs/P1020RDB-PC_NAND_defconfig
@@ -5,13 +5,13 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
-CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_TPL_TEXT_BASE=0xF8F80000
 CONFIG_TPL_LIBCOMMON_SUPPORT=y
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_TPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SPL=y
 CONFIG_TPL_MAX_SIZE=0x20000
 CONFIG_MPC85xx=y
diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig
index f439e56..679c6fe 100644
--- a/configs/P1020RDB-PC_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_SDCARD_defconfig
@@ -7,10 +7,10 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x0
 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
-CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig
index 43aba38..2ccb202 100644
--- a/configs/P1020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_SPIFLASH_defconfig
@@ -8,9 +8,9 @@
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
-CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig
index 7dd0048..118f510 100644
--- a/configs/P1020RDB-PD_NAND_defconfig
+++ b/configs/P1020RDB-PD_NAND_defconfig
@@ -5,13 +5,13 @@
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
-CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_TPL_TEXT_BASE=0xF8F80000
 CONFIG_TPL_LIBCOMMON_SUPPORT=y
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_TPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SPL=y
 CONFIG_TPL_MAX_SIZE=0x20000
 CONFIG_MPC85xx=y
diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig
index e7daa79..6b6b35a 100644
--- a/configs/P1020RDB-PD_SDCARD_defconfig
+++ b/configs/P1020RDB-PD_SDCARD_defconfig
@@ -7,10 +7,10 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x0
 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
-CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig
index 08d0951..e30b541 100644
--- a/configs/P1020RDB-PD_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PD_SPIFLASH_defconfig
@@ -8,9 +8,9 @@
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
-CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig
index d7fcab1..ec80871 100644
--- a/configs/P2020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig
@@ -5,13 +5,13 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
-CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_TPL_TEXT_BASE=0xF8F80000
 CONFIG_TPL_LIBCOMMON_SUPPORT=y
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_TPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SPL=y
 CONFIG_TPL_MAX_SIZE=0x20000
 CONFIG_MPC85xx=y
diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
index 22243cc..0a65873 100644
--- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
@@ -7,10 +7,10 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x0
 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
-CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
index d2bd375..ce95ab8 100644
--- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -8,9 +8,9 @@
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
-CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig
index b8543d9..618e827 100644
--- a/configs/P2020RDB-PC_NAND_defconfig
+++ b/configs/P2020RDB-PC_NAND_defconfig
@@ -5,13 +5,13 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
-CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_TPL_TEXT_BASE=0xF8F80000
 CONFIG_TPL_LIBCOMMON_SUPPORT=y
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_TPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SPL=y
 CONFIG_TPL_MAX_SIZE=0x20000
 CONFIG_MPC85xx=y
diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig
index a62ecfe..eb9ee65 100644
--- a/configs/P2020RDB-PC_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_SDCARD_defconfig
@@ -7,10 +7,10 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x0
 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
-CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig
index 9e6e43d..f73ddc3 100644
--- a/configs/P2020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_SPIFLASH_defconfig
@@ -8,9 +8,9 @@
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
-CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
diff --git a/configs/SBx81LIFKW_defconfig b/configs/SBx81LIFKW_defconfig
index bc10b6e..35f5b5b 100644
--- a/configs/SBx81LIFKW_defconfig
+++ b/configs/SBx81LIFKW_defconfig
@@ -27,11 +27,11 @@
 CONFIG_CMD_DM=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_NTPSERVER=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
 CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)"
 CONFIG_DOS_PARTITION=y
 CONFIG_OF_CONTROL=y
@@ -40,8 +40,8 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_ENV_SPI_MAX_HZ=20000000
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM_PCA953X=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_MVTWSI=y
diff --git a/configs/SBx81LIFXCAT_defconfig b/configs/SBx81LIFXCAT_defconfig
index 427b48b..ed3bc5b 100644
--- a/configs/SBx81LIFXCAT_defconfig
+++ b/configs/SBx81LIFXCAT_defconfig
@@ -27,11 +27,11 @@
 CONFIG_CMD_DM=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_NTPSERVER=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
 # CONFIG_CMD_LED is not set
 CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)"
 CONFIG_DOS_PARTITION=y
diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig
index 34ef789..37dfdb4 100644
--- a/configs/T1024RDB_NAND_defconfig
+++ b/configs/T1024RDB_NAND_defconfig
@@ -7,10 +7,10 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig
index 3dc29f7..72630f1 100644
--- a/configs/T1024RDB_SDCARD_defconfig
+++ b/configs/T1024RDB_SDCARD_defconfig
@@ -7,11 +7,11 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig
index 6b43fd7..8d48b39 100644
--- a/configs/T1024RDB_SPIFLASH_defconfig
+++ b/configs/T1024RDB_SPIFLASH_defconfig
@@ -8,10 +8,10 @@
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig
index 7d2b5ea..01a8594 100644
--- a/configs/T1042D4RDB_NAND_defconfig
+++ b/configs/T1042D4RDB_NAND_defconfig
@@ -6,10 +6,10 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x180000
 CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb"
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig
index e26fe8f..26de5bf 100644
--- a/configs/T1042D4RDB_SDCARD_defconfig
+++ b/configs/T1042D4RDB_SDCARD_defconfig
@@ -6,11 +6,11 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb"
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig
index f63e9de..674246a 100644
--- a/configs/T1042D4RDB_SPIFLASH_defconfig
+++ b/configs/T1042D4RDB_SPIFLASH_defconfig
@@ -7,10 +7,10 @@
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb"
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig
index 1ca48d3..8d7ca9b 100644
--- a/configs/T2080QDS_NAND_defconfig
+++ b/configs/T2080QDS_NAND_defconfig
@@ -6,10 +6,10 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x140000
 CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig
index b70c3f6..3ba3022 100644
--- a/configs/T2080QDS_SDCARD_defconfig
+++ b/configs/T2080QDS_SDCARD_defconfig
@@ -6,11 +6,11 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig
index 94991cd..1cdcd0d 100644
--- a/configs/T2080QDS_SPIFLASH_defconfig
+++ b/configs/T2080QDS_SPIFLASH_defconfig
@@ -7,10 +7,10 @@
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig
index 7b015ed..63db57b 100644
--- a/configs/T2080RDB_NAND_defconfig
+++ b/configs/T2080RDB_NAND_defconfig
@@ -6,10 +6,10 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig
index 0e9ebaa..04cc53d 100644
--- a/configs/T2080RDB_SDCARD_defconfig
+++ b/configs/T2080RDB_SDCARD_defconfig
@@ -6,11 +6,11 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig
index 1552319..26c479f 100644
--- a/configs/T2080RDB_SPIFLASH_defconfig
+++ b/configs/T2080RDB_SPIFLASH_defconfig
@@ -7,10 +7,10 @@
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
diff --git a/configs/T2080RDB_revD_NAND_defconfig b/configs/T2080RDB_revD_NAND_defconfig
index b98c861..995dc7e 100644
--- a/configs/T2080RDB_revD_NAND_defconfig
+++ b/configs/T2080RDB_revD_NAND_defconfig
@@ -6,10 +6,10 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
diff --git a/configs/T2080RDB_revD_SDCARD_defconfig b/configs/T2080RDB_revD_SDCARD_defconfig
index f97bf90..a66dba3 100644
--- a/configs/T2080RDB_revD_SDCARD_defconfig
+++ b/configs/T2080RDB_revD_SDCARD_defconfig
@@ -6,11 +6,11 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
diff --git a/configs/T2080RDB_revD_SPIFLASH_defconfig b/configs/T2080RDB_revD_SPIFLASH_defconfig
index 15cb9b2..8a87a1b 100644
--- a/configs/T2080RDB_revD_SPIFLASH_defconfig
+++ b/configs/T2080RDB_revD_SPIFLASH_defconfig
@@ -7,10 +7,10 @@
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig
index 4881efc..8d03c7d 100644
--- a/configs/T4240RDB_SDCARD_defconfig
+++ b/configs/T4240RDB_SDCARD_defconfig
@@ -6,11 +6,11 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="t4240rdb"
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
diff --git a/configs/ae350_rv32_falcon_xip_defconfig b/configs/ae350_rv32_falcon_xip_defconfig
index 116fd21..a2f8d4c 100644
--- a/configs/ae350_rv32_falcon_xip_defconfig
+++ b/configs/ae350_rv32_falcon_xip_defconfig
@@ -6,9 +6,9 @@
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000000
 CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
-CONFIG_SPL_TEXT_BASE=0x80000000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000
+CONFIG_SPL_TEXT_BASE=0x80000000
 CONFIG_SPL_BSS_START_ADDR=0x400000
 CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_SYS_LOAD_ADDR=0x100000
diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig
index 642fb7b..2392788 100644
--- a/configs/ae350_rv32_spl_xip_defconfig
+++ b/configs/ae350_rv32_spl_xip_defconfig
@@ -6,9 +6,9 @@
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000000
 CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
-CONFIG_SPL_TEXT_BASE=0x80000000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000
+CONFIG_SPL_TEXT_BASE=0x80000000
 CONFIG_SPL_BSS_START_ADDR=0x400000
 CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_SYS_LOAD_ADDR=0x100000
diff --git a/configs/ae350_rv64_falcon_xip_defconfig b/configs/ae350_rv64_falcon_xip_defconfig
index eb69e59..e072f7c 100644
--- a/configs/ae350_rv64_falcon_xip_defconfig
+++ b/configs/ae350_rv64_falcon_xip_defconfig
@@ -6,8 +6,8 @@
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000000
 CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
-CONFIG_SPL_TEXT_BASE=0x80000000
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000
+CONFIG_SPL_TEXT_BASE=0x80000000
 CONFIG_SPL_BSS_START_ADDR=0x400000
 CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_SYS_LOAD_ADDR=0x100000
diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig
index 9b80234..5ad1751 100644
--- a/configs/ae350_rv64_spl_xip_defconfig
+++ b/configs/ae350_rv64_spl_xip_defconfig
@@ -6,8 +6,8 @@
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000000
 CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
-CONFIG_SPL_TEXT_BASE=0x80000000
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000
+CONFIG_SPL_TEXT_BASE=0x80000000
 CONFIG_SPL_BSS_START_ADDR=0x400000
 CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_SYS_LOAD_ADDR=0x100000
diff --git a/configs/am335x_hs_evm_defconfig b/configs/am335x_hs_evm_defconfig
index 2c23c9b..396e743 100644
--- a/configs/am335x_hs_evm_defconfig
+++ b/configs/am335x_hs_evm_defconfig
@@ -5,10 +5,10 @@
 CONFIG_TI_COMMON_CMD_OPTIONS=y
 CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
-CONFIG_SPL_TEXT_BASE=0x40300350
 CONFIG_AM33XX=y
 CONFIG_CLOCK_SYNTHESIZER=y
 # CONFIG_OF_LIBFDT_OVERLAY is not set
+CONFIG_SPL_TEXT_BASE=0x40300350
 CONFIG_SYS_BOOTM_LEN=0x1000000
 CONFIG_SPL=y
 CONFIG_TIMESTAMP=y
diff --git a/configs/am335x_hs_evm_uart_defconfig b/configs/am335x_hs_evm_uart_defconfig
index afa6e49..4be0b2f 100644
--- a/configs/am335x_hs_evm_uart_defconfig
+++ b/configs/am335x_hs_evm_uart_defconfig
@@ -5,11 +5,11 @@
 CONFIG_TI_COMMON_CMD_OPTIONS=y
 CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
-CONFIG_SPL_TEXT_BASE=0x40301950
 CONFIG_AM33XX=y
 CONFIG_CLOCK_SYNTHESIZER=y
 # CONFIG_OF_LIBFDT_OVERLAY is not set
 # CONFIG_SPL_MMC is not set
+CONFIG_SPL_TEXT_BASE=0x40301950
 CONFIG_SYS_BOOTM_LEN=0x1000000
 CONFIG_SPL=y
 # CONFIG_SPL_FS_FAT is not set
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index c4693bc..8dab015 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -6,8 +6,8 @@
 CONFIG_ENV_SIZE=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
-CONFIG_SPL_TEXT_BASE=0x40300350
 CONFIG_AM43XX=y
+CONFIG_SPL_TEXT_BASE=0x40300350
 CONFIG_SPL=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig
index 980ef13..419bcb7 100644
--- a/configs/am43xx_hs_evm_defconfig
+++ b/configs/am43xx_hs_evm_defconfig
@@ -8,12 +8,12 @@
 CONFIG_ENV_SIZE=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
-CONFIG_SPL_TEXT_BASE=0x403018e0
 CONFIG_AM43XX=y
 CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
 CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
 CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0x403018e0
 CONFIG_SPL=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index b793f00..d10d2a5 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -5,9 +5,9 @@
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="am572x-idk"
-CONFIG_SPL_TEXT_BASE=0x40300000
 CONFIG_OMAP54XX=y
 CONFIG_TARGET_AM57XX_EVM=y
+CONFIG_SPL_TEXT_BASE=0x40300000
 CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_SPL=y
 CONFIG_ENV_OFFSET_REDUND=0x280000
diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig
index 2d8068e..d865b12 100644
--- a/configs/am57xx_hs_evm_usb_defconfig
+++ b/configs/am57xx_hs_evm_usb_defconfig
@@ -6,12 +6,12 @@
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="am57xx-beagle-x15"
-CONFIG_SPL_TEXT_BASE=0x40306D50
 CONFIG_OMAP54XX=y
 CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
 CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
 CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000
 CONFIG_TARGET_AM57XX_EVM=y
+CONFIG_SPL_TEXT_BASE=0x40306D50
 CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_SPL=y
 CONFIG_ENV_OFFSET_REDUND=0x280000
diff --git a/configs/am62ax_evm_a53_defconfig b/configs/am62ax_evm_a53_defconfig
index c396171..7d63340 100644
--- a/configs/am62ax_evm_a53_defconfig
+++ b/configs/am62ax_evm_a53_defconfig
@@ -9,12 +9,12 @@
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
 CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am62a7-sk"
-CONFIG_SPL_TEXT_BASE=0x80080000
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_TEXT_BASE=0x80080000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x80a00000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
diff --git a/configs/am62ax_evm_r5_defconfig b/configs/am62ax_evm_r5_defconfig
index 2e758b4..ec712b1 100644
--- a/configs/am62ax_evm_r5_defconfig
+++ b/configs/am62ax_evm_r5_defconfig
@@ -11,12 +11,12 @@
 CONFIG_ENV_OFFSET=0x680000
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="k3-am62a7-r5-sk"
-CONFIG_SPL_TEXT_BASE=0x43c00000
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x7145
+CONFIG_SPL_TEXT_BASE=0x43c00000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x43c3b000
 CONFIG_SPL_BSS_MAX_SIZE=0x3000
diff --git a/configs/am62px_evm_r5_defconfig b/configs/am62px_evm_r5_defconfig
index 5fed277..a93c33c 100644
--- a/configs/am62px_evm_r5_defconfig
+++ b/configs/am62px_evm_r5_defconfig
@@ -13,12 +13,12 @@
 CONFIG_ENV_OFFSET=0x680000
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="k3-am62p5-r5-sk"
-CONFIG_SPL_TEXT_BASE=0x43c00000
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_TEXT_BASE=0x43c00000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x43c4b000
 CONFIG_SPL_BSS_MAX_SIZE=0x3000
diff --git a/configs/am62x_a53_android.config b/configs/am62x_a53_android.config
index adbe2b8..2aca51e 100644
--- a/configs/am62x_a53_android.config
+++ b/configs/am62x_a53_android.config
@@ -11,6 +11,7 @@
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 # Enable Android boot flow
 CONFIG_BOOTMETH_ANDROID=y
+CONFIG_ANDROID_AB=y
 CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_SYS_MALLOC_LEN=0x08000000
 CONFIG_AVB_VERIFY=y
diff --git a/configs/am62x_beagleplay_r5_defconfig b/configs/am62x_beagleplay_r5_defconfig
index 9daee2a..d0c09b9 100644
--- a/configs/am62x_beagleplay_r5_defconfig
+++ b/configs/am62x_beagleplay_r5_defconfig
@@ -13,13 +13,13 @@
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="k3-am625-r5-beagleplay"
-CONFIG_SPL_TEXT_BASE=0x43c00000
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x7000
+CONFIG_SPL_TEXT_BASE=0x43c00000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x43c3b000
 CONFIG_SPL_BSS_MAX_SIZE=0x3000
diff --git a/configs/am62x_evm_r5_defconfig b/configs/am62x_evm_r5_defconfig
index 6ff0782..fcc5eb0 100644
--- a/configs/am62x_evm_r5_defconfig
+++ b/configs/am62x_evm_r5_defconfig
@@ -15,13 +15,13 @@
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="k3-am625-r5-sk"
-CONFIG_SPL_TEXT_BASE=0x43c00000
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x7000
+CONFIG_SPL_TEXT_BASE=0x43c00000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x43c3b000
 CONFIG_SPL_BSS_MAX_SIZE=0x3000
diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig
index 599115a..c4e498a 100644
--- a/configs/am64x_evm_r5_defconfig
+++ b/configs/am64x_evm_r5_defconfig
@@ -16,12 +16,12 @@
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="k3-am642-r5-evm"
-CONFIG_SPL_TEXT_BASE=0x70000000
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_TEXT_BASE=0x70000000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x7019b800
 CONFIG_SPL_BSS_MAX_SIZE=0x4000
diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig
index 9dc3f15..cf7a211 100644
--- a/configs/am65x_evm_a53_defconfig
+++ b/configs/am65x_evm_a53_defconfig
@@ -15,12 +15,12 @@
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="k3-am654-base-board"
-CONFIG_SPL_TEXT_BASE=0x80080000
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_TEXT_BASE=0x80080000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x80a00000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig
index f60003b..083522c 100644
--- a/configs/am65x_evm_r5_defconfig
+++ b/configs/am65x_evm_r5_defconfig
@@ -15,12 +15,12 @@
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board"
-CONFIG_SPL_TEXT_BASE=0x41c00000
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_TEXT_BASE=0x41c00000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x41c7effc
 CONFIG_SPL_BSS_MAX_SIZE=0xc00
diff --git a/configs/am65x_evm_r5_usbdfu_defconfig b/configs/am65x_evm_r5_usbdfu_defconfig
index 036b30d..e60e0d6 100644
--- a/configs/am65x_evm_r5_usbdfu_defconfig
+++ b/configs/am65x_evm_r5_usbdfu_defconfig
@@ -14,11 +14,11 @@
 CONFIG_ENV_SIZE=0x20000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board"
-CONFIG_SPL_TEXT_BASE=0x41c00000
 CONFIG_DM_RESET=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_TEXT_BASE=0x41c00000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x41c7effc
 CONFIG_SPL_BSS_MAX_SIZE=0xc00
diff --git a/configs/am65x_evm_r5_usbmsc_defconfig b/configs/am65x_evm_r5_usbmsc_defconfig
index 44c18ce..ecd48c4 100644
--- a/configs/am65x_evm_r5_usbmsc_defconfig
+++ b/configs/am65x_evm_r5_usbmsc_defconfig
@@ -14,11 +14,11 @@
 CONFIG_ENV_SIZE=0x20000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board"
-CONFIG_SPL_TEXT_BASE=0x41c00000
 CONFIG_DM_RESET=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_TEXT_BASE=0x41c00000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x41c7effc
 CONFIG_SPL_BSS_MAX_SIZE=0xc00
diff --git a/configs/amd_versal2_mini_defconfig b/configs/amd_versal2_mini_defconfig
index ea22541..4c902e4 100644
--- a/configs/amd_versal2_mini_defconfig
+++ b/configs/amd_versal2_mini_defconfig
@@ -15,6 +15,7 @@
 CONFIG_SYS_LOAD_ADDR=0xBBF80000
 CONFIG_DEBUG_UART_BASE=0xf1920000
 CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_XILINX_MINI=y
 CONFIG_SYS_MEM_RSVD_FOR_MMU=y
 # CONFIG_PSCI_RESET is not set
 CONFIG_DEBUG_UART=y
diff --git a/configs/amd_versal2_mini_emmc_defconfig b/configs/amd_versal2_mini_emmc_defconfig
index 6d4b261..da3eebe 100644
--- a/configs/amd_versal2_mini_emmc_defconfig
+++ b/configs/amd_versal2_mini_emmc_defconfig
@@ -12,6 +12,7 @@
 CONFIG_SYS_LOAD_ADDR=0x8000000
 CONFIG_DEBUG_UART_BASE=0xf1920000
 CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_XILINX_MINI=y
 # CONFIG_PSCI_RESET is not set
 CONFIG_DEBUG_UART=y
 # CONFIG_EXPERT is not set
diff --git a/configs/amd_versal2_mini_ospi_defconfig b/configs/amd_versal2_mini_ospi_defconfig
index 71bd667..d881cd4 100644
--- a/configs/amd_versal2_mini_ospi_defconfig
+++ b/configs/amd_versal2_mini_ospi_defconfig
@@ -15,6 +15,7 @@
 CONFIG_SYS_LOAD_ADDR=0xBBF80000
 CONFIG_DEBUG_UART_BASE=0xf1920000
 CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_XILINX_MINI=y
 CONFIG_SYS_MEM_RSVD_FOR_MMU=y
 # CONFIG_PSCI_RESET is not set
 CONFIG_DEBUG_UART=y
diff --git a/configs/amd_versal2_mini_qspi_defconfig b/configs/amd_versal2_mini_qspi_defconfig
index ee87d45..eb63f06 100644
--- a/configs/amd_versal2_mini_qspi_defconfig
+++ b/configs/amd_versal2_mini_qspi_defconfig
@@ -15,6 +15,7 @@
 CONFIG_SYS_LOAD_ADDR=0xBBF80000
 CONFIG_DEBUG_UART_BASE=0xf1920000
 CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_XILINX_MINI=y
 CONFIG_SYS_MEM_RSVD_FOR_MMU=y
 # CONFIG_PSCI_RESET is not set
 CONFIG_DEBUG_UART=y
@@ -64,10 +65,6 @@
 # CONFIG_I2C is not set
 # CONFIG_INPUT is not set
 # CONFIG_MMC is not set
-CONFIG_DM_SPI_FLASH=y
-# CONFIG_SPI_FLASH_LOCK is not set
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 # CONFIG_POWER is not set
 CONFIG_DEBUG_UART_PL011=y
 CONFIG_DEBUG_UART_ANNOUNCE=y
diff --git a/configs/amd_versal2_virt_defconfig b/configs/amd_versal2_virt_defconfig
index 8c308f3..08e6077 100644
--- a/configs/amd_versal2_virt_defconfig
+++ b/configs/amd_versal2_virt_defconfig
@@ -67,10 +67,10 @@
 CONFIG_MULTI_DTB_FIT=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
 CONFIG_IP_DEFRAG=y
 CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_TFTP_BLOCKSIZE=4096
 CONFIG_SIMPLE_PM_BUS=y
 CONFIG_CLK_CCF=y
diff --git a/configs/aml-a311d-cc_defconfig b/configs/aml-a311d-cc_defconfig
index c8e2220..6d0d5eb 100644
--- a/configs/aml-a311d-cc_defconfig
+++ b/configs/aml-a311d-cc_defconfig
@@ -14,12 +14,14 @@
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_MESON_G12A=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
 CONFIG_DEBUG_UART_BASE=0xff803000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_IDENT_STRING="aml-a311d-cc"
-CONFIG_SYS_LOAD_ADDR=0x1000000
 CONFIG_DEBUG_UART=y
 CONFIG_REMAKE_ELF=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
@@ -30,8 +32,8 @@
 CONFIG_SYS_MAXARGS=32
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_IMI is not set
-CONFIG_CMD_DFU=y
 CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_MMC=y
@@ -39,8 +41,8 @@
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_EFIDEBUG=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_EFIDEBUG=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
@@ -51,7 +53,6 @@
 CONFIG_BUTTON_ADC=y
 CONFIG_DFU_RAM=y
 CONFIG_DFU_SF=y
-CONFIG_SET_DFU_ALT_INFO=y
 CONFIG_MMC_MESON_GX=y
 CONFIG_MTD=y
 CONFIG_DM_MTD=y
@@ -104,5 +105,3 @@
 CONFIG_BMP_16BPP=y
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y
-CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
-CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
diff --git a/configs/aml-s905d3-cc_defconfig b/configs/aml-s905d3-cc_defconfig
index a6e5d58..1975c67 100644
--- a/configs/aml-s905d3-cc_defconfig
+++ b/configs/aml-s905d3-cc_defconfig
@@ -14,12 +14,14 @@
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_MESON_G12A=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
 CONFIG_DEBUG_UART_BASE=0xff803000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_IDENT_STRING="aml-s905d3-cc"
-CONFIG_SYS_LOAD_ADDR=0x1000000
 CONFIG_DEBUG_UART=y
 CONFIG_REMAKE_ELF=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
@@ -30,8 +32,8 @@
 CONFIG_SYS_MAXARGS=32
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_IMI is not set
-CONFIG_CMD_DFU=y
 CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_MMC=y
@@ -39,8 +41,8 @@
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_EFIDEBUG=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_EFIDEBUG=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
@@ -51,7 +53,6 @@
 CONFIG_BUTTON_ADC=y
 CONFIG_DFU_RAM=y
 CONFIG_DFU_SF=y
-CONFIG_SET_DFU_ALT_INFO=y
 CONFIG_MMC_MESON_GX=y
 CONFIG_MTD=y
 CONFIG_DM_MTD=y
@@ -104,5 +105,3 @@
 CONFIG_BMP_16BPP=y
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y
-CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
-CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
diff --git a/configs/anbernic-rgxx3-rk3566_defconfig b/configs/anbernic-rgxx3-rk3566_defconfig
index d3216ec..14c97b4 100644
--- a/configs/anbernic-rgxx3-rk3566_defconfig
+++ b/configs/anbernic-rgxx3-rk3566_defconfig
@@ -70,7 +70,6 @@
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_SPL_RAM=y
 # CONFIG_RAM_ROCKCHIP_DEBUG is not set
-# CONFIG_RNG_SMCCC_TRNG is not set
 CONFIG_BAUDRATE=1500000
 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
 CONFIG_DEBUG_UART_SHIFT=2
diff --git a/configs/apalis-imx8_defconfig b/configs/apalis-imx8_defconfig
index 795cdc2..6afda7f 100644
--- a/configs/apalis-imx8_defconfig
+++ b/configs/apalis-imx8_defconfig
@@ -53,9 +53,7 @@
 CONFIG_SYS_MMC_ENV_PART=1
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_VERSION_VARIABLE=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_IP_DEFRAG=y
-CONFIG_TFTP_BLOCKSIZE=4096
 CONFIG_TFTP_TSIZE=y
 CONFIG_USE_IPADDR=y
 CONFIG_IPADDR="192.168.10.2"
@@ -63,6 +61,8 @@
 CONFIG_NETMASK="255.255.255.0"
 CONFIG_USE_SERVERIP=y
 CONFIG_SERVERIP="192.168.10.1"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TFTP_BLOCKSIZE=4096
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_BOOTCOUNT_ENV=y
 CONFIG_CLK_IMX8=y
diff --git a/configs/apalis-tk1_defconfig b/configs/apalis-tk1_defconfig
index baab3bf..ef982f7 100644
--- a/configs/apalis-tk1_defconfig
+++ b/configs/apalis-tk1_defconfig
@@ -8,9 +8,9 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFDE00
 CONFIG_DEFAULT_DEVICE_TREE="tegra124-apalis"
-CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_STACK=0x800ffffc
+CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SYS_LOAD_ADDR=0x81000000
 CONFIG_TEGRA124=y
 CONFIG_TARGET_APALIS_TK1=y
@@ -53,9 +53,7 @@
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SYS_MMC_ENV_PART=1
 CONFIG_VERSION_VARIABLE=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_IP_DEFRAG=y
-CONFIG_TFTP_BLOCKSIZE=16352
 CONFIG_TFTP_TSIZE=y
 CONFIG_USE_IPADDR=y
 CONFIG_IPADDR="192.168.10.2"
@@ -63,6 +61,8 @@
 CONFIG_NETMASK="255.255.255.0"
 CONFIG_USE_SERVERIP=y
 CONFIG_SERVERIP="192.168.10.1"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TFTP_BLOCKSIZE=16352
 CONFIG_SYS_I2C_TEGRA=y
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK=y
diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig
index b44861d..a3f65c5 100644
--- a/configs/apalis_imx6_defconfig
+++ b/configs/apalis_imx6_defconfig
@@ -73,15 +73,15 @@
 CONFIG_SYS_MMC_ENV_PART=1
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_VERSION_VARIABLE=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_IP_DEFRAG=y
-CONFIG_TFTP_BLOCKSIZE=4096
 CONFIG_USE_IPADDR=y
 CONFIG_IPADDR="192.168.10.2"
 CONFIG_USE_NETMASK=y
 CONFIG_NETMASK="255.255.255.0"
 CONFIG_USE_SERVERIP=y
 CONFIG_SERVERIP="192.168.10.1"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TFTP_BLOCKSIZE=4096
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_DWC_AHSATA=y
 CONFIG_LBA48=y
diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig
index 963b280..3143566 100644
--- a/configs/apalis_t30_defconfig
+++ b/configs/apalis_t30_defconfig
@@ -8,9 +8,9 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFDE00
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-apalis"
-CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_STACK=0x800ffffc
+CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SYS_LOAD_ADDR=0x81000000
 CONFIG_TEGRA30=y
 CONFIG_TARGET_APALIS_T30=y
@@ -46,10 +46,10 @@
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SYS_MMC_ENV_PART=1
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_IP_DEFRAG=y
-CONFIG_TFTP_BLOCKSIZE=16352
 CONFIG_TFTP_TSIZE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TFTP_BLOCKSIZE=16352
 CONFIG_SYS_I2C_TEGRA=y
 CONFIG_E1000=y
 CONFIG_E1000_NO_NVM=y
diff --git a/configs/at91sam9260ek_dataflash_cs0_defconfig b/configs/at91sam9260ek_dataflash_cs0_defconfig
index 6c8e4b2..9b07709 100644
--- a/configs/at91sam9260ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9260ek_dataflash_cs0_defconfig
@@ -34,8 +34,8 @@
 CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
diff --git a/configs/at91sam9260ek_dataflash_cs1_defconfig b/configs/at91sam9260ek_dataflash_cs1_defconfig
index cfffdfa..dafbc76 100644
--- a/configs/at91sam9260ek_dataflash_cs1_defconfig
+++ b/configs/at91sam9260ek_dataflash_cs1_defconfig
@@ -34,8 +34,8 @@
 CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
diff --git a/configs/at91sam9260ek_nandflash_defconfig b/configs/at91sam9260ek_nandflash_defconfig
index dc633aa..4ee101f 100644
--- a/configs/at91sam9260ek_nandflash_defconfig
+++ b/configs/at91sam9260ek_nandflash_defconfig
@@ -33,8 +33,8 @@
 CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
diff --git a/configs/at91sam9261ek_dataflash_cs0_defconfig b/configs/at91sam9261ek_dataflash_cs0_defconfig
index 4883a80..09095e9 100644
--- a/configs/at91sam9261ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9261ek_dataflash_cs0_defconfig
@@ -34,8 +34,8 @@
 CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
diff --git a/configs/at91sam9261ek_dataflash_cs3_defconfig b/configs/at91sam9261ek_dataflash_cs3_defconfig
index c4fdc9c..d594d96 100644
--- a/configs/at91sam9261ek_dataflash_cs3_defconfig
+++ b/configs/at91sam9261ek_dataflash_cs3_defconfig
@@ -34,8 +34,8 @@
 CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
diff --git a/configs/at91sam9261ek_nandflash_defconfig b/configs/at91sam9261ek_nandflash_defconfig
index 9051db4..f53bf3c 100644
--- a/configs/at91sam9261ek_nandflash_defconfig
+++ b/configs/at91sam9261ek_nandflash_defconfig
@@ -33,8 +33,8 @@
 CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
diff --git a/configs/at91sam9263ek_dataflash_cs0_defconfig b/configs/at91sam9263ek_dataflash_cs0_defconfig
index 3feb7c0..9bfda68 100644
--- a/configs/at91sam9263ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9263ek_dataflash_cs0_defconfig
@@ -37,8 +37,8 @@
 CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
diff --git a/configs/at91sam9263ek_dataflash_defconfig b/configs/at91sam9263ek_dataflash_defconfig
index 3feb7c0..9bfda68 100644
--- a/configs/at91sam9263ek_dataflash_defconfig
+++ b/configs/at91sam9263ek_dataflash_defconfig
@@ -37,8 +37,8 @@
 CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
diff --git a/configs/at91sam9263ek_nandflash_defconfig b/configs/at91sam9263ek_nandflash_defconfig
index d7c850e..e515818 100644
--- a/configs/at91sam9263ek_nandflash_defconfig
+++ b/configs/at91sam9263ek_nandflash_defconfig
@@ -36,8 +36,8 @@
 CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
diff --git a/configs/at91sam9263ek_norflash_boot_defconfig b/configs/at91sam9263ek_norflash_boot_defconfig
index 102dedb..488c370 100644
--- a/configs/at91sam9263ek_norflash_boot_defconfig
+++ b/configs/at91sam9263ek_norflash_boot_defconfig
@@ -35,8 +35,8 @@
 CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
diff --git a/configs/at91sam9263ek_norflash_defconfig b/configs/at91sam9263ek_norflash_defconfig
index c8783b0..d8c490d 100644
--- a/configs/at91sam9263ek_norflash_defconfig
+++ b/configs/at91sam9263ek_norflash_defconfig
@@ -36,8 +36,8 @@
 CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
diff --git a/configs/at91sam9g10ek_dataflash_cs0_defconfig b/configs/at91sam9g10ek_dataflash_cs0_defconfig
index 4c07fce..211b20b 100644
--- a/configs/at91sam9g10ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9g10ek_dataflash_cs0_defconfig
@@ -34,8 +34,8 @@
 CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
diff --git a/configs/at91sam9g10ek_dataflash_cs3_defconfig b/configs/at91sam9g10ek_dataflash_cs3_defconfig
index 64ec4bb..f6529b1 100644
--- a/configs/at91sam9g10ek_dataflash_cs3_defconfig
+++ b/configs/at91sam9g10ek_dataflash_cs3_defconfig
@@ -34,8 +34,8 @@
 CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
diff --git a/configs/at91sam9g10ek_nandflash_defconfig b/configs/at91sam9g10ek_nandflash_defconfig
index 6d95555..580960e 100644
--- a/configs/at91sam9g10ek_nandflash_defconfig
+++ b/configs/at91sam9g10ek_nandflash_defconfig
@@ -33,8 +33,8 @@
 CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
diff --git a/configs/at91sam9g20ek_2mmc_defconfig b/configs/at91sam9g20ek_2mmc_defconfig
index 256552f..273e93c 100644
--- a/configs/at91sam9g20ek_2mmc_defconfig
+++ b/configs/at91sam9g20ek_2mmc_defconfig
@@ -36,8 +36,8 @@
 CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
diff --git a/configs/at91sam9g20ek_2mmc_nandflash_defconfig b/configs/at91sam9g20ek_2mmc_nandflash_defconfig
index 5c134c9..c4d1252 100644
--- a/configs/at91sam9g20ek_2mmc_nandflash_defconfig
+++ b/configs/at91sam9g20ek_2mmc_nandflash_defconfig
@@ -35,8 +35,8 @@
 CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
diff --git a/configs/at91sam9g20ek_dataflash_cs0_defconfig b/configs/at91sam9g20ek_dataflash_cs0_defconfig
index b403766..7520316 100644
--- a/configs/at91sam9g20ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9g20ek_dataflash_cs0_defconfig
@@ -34,8 +34,8 @@
 CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
diff --git a/configs/at91sam9g20ek_dataflash_cs1_defconfig b/configs/at91sam9g20ek_dataflash_cs1_defconfig
index 878c04c..adf3c10 100644
--- a/configs/at91sam9g20ek_dataflash_cs1_defconfig
+++ b/configs/at91sam9g20ek_dataflash_cs1_defconfig
@@ -34,8 +34,8 @@
 CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
diff --git a/configs/at91sam9g20ek_nandflash_defconfig b/configs/at91sam9g20ek_nandflash_defconfig
index f8173f4..e68f503 100644
--- a/configs/at91sam9g20ek_nandflash_defconfig
+++ b/configs/at91sam9g20ek_nandflash_defconfig
@@ -33,8 +33,8 @@
 CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
diff --git a/configs/at91sam9m10g45ek_mmc_defconfig b/configs/at91sam9m10g45ek_mmc_defconfig
index 34d8264..796181b 100644
--- a/configs/at91sam9m10g45ek_mmc_defconfig
+++ b/configs/at91sam9m10g45ek_mmc_defconfig
@@ -38,8 +38,8 @@
 CONFIG_CMD_NAND=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
diff --git a/configs/at91sam9m10g45ek_nandflash_defconfig b/configs/at91sam9m10g45ek_nandflash_defconfig
index ad8a82b..e57bd2c 100644
--- a/configs/at91sam9m10g45ek_nandflash_defconfig
+++ b/configs/at91sam9m10g45ek_nandflash_defconfig
@@ -38,8 +38,8 @@
 CONFIG_CMD_NAND=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
diff --git a/configs/at91sam9n12ek_mmc_defconfig b/configs/at91sam9n12ek_mmc_defconfig
index 88e0f6c..c50842a 100644
--- a/configs/at91sam9n12ek_mmc_defconfig
+++ b/configs/at91sam9n12ek_mmc_defconfig
@@ -31,8 +31,8 @@
 CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_MTDPARTS=y
diff --git a/configs/at91sam9n12ek_nandflash_defconfig b/configs/at91sam9n12ek_nandflash_defconfig
index 0bfc856..e7b4107 100644
--- a/configs/at91sam9n12ek_nandflash_defconfig
+++ b/configs/at91sam9n12ek_nandflash_defconfig
@@ -31,8 +31,8 @@
 CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_MTDPARTS=y
diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig
index b329a96..cb4f0b5 100644
--- a/configs/at91sam9n12ek_spiflash_defconfig
+++ b/configs/at91sam9n12ek_spiflash_defconfig
@@ -33,8 +33,8 @@
 CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_MTDPARTS=y
diff --git a/configs/at91sam9x5ek_dataflash_defconfig b/configs/at91sam9x5ek_dataflash_defconfig
index 633dae9..c40319e 100644
--- a/configs/at91sam9x5ek_dataflash_defconfig
+++ b/configs/at91sam9x5ek_dataflash_defconfig
@@ -39,8 +39,8 @@
 CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_MTDPARTS=y
diff --git a/configs/at91sam9x5ek_mmc_defconfig b/configs/at91sam9x5ek_mmc_defconfig
index 82db49e..8db86c7 100644
--- a/configs/at91sam9x5ek_mmc_defconfig
+++ b/configs/at91sam9x5ek_mmc_defconfig
@@ -36,8 +36,8 @@
 CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_MTDPARTS=y
diff --git a/configs/at91sam9x5ek_nandflash_defconfig b/configs/at91sam9x5ek_nandflash_defconfig
index d512dd6..3f59395 100644
--- a/configs/at91sam9x5ek_nandflash_defconfig
+++ b/configs/at91sam9x5ek_nandflash_defconfig
@@ -38,8 +38,8 @@
 CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_MTDPARTS=y
diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig
index ba5b9c6..12336d0 100644
--- a/configs/at91sam9x5ek_spiflash_defconfig
+++ b/configs/at91sam9x5ek_spiflash_defconfig
@@ -40,8 +40,8 @@
 CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_MTDPARTS=y
diff --git a/configs/at91sam9xeek_dataflash_cs0_defconfig b/configs/at91sam9xeek_dataflash_cs0_defconfig
index 6c8e4b2..9b07709 100644
--- a/configs/at91sam9xeek_dataflash_cs0_defconfig
+++ b/configs/at91sam9xeek_dataflash_cs0_defconfig
@@ -34,8 +34,8 @@
 CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
diff --git a/configs/at91sam9xeek_dataflash_cs1_defconfig b/configs/at91sam9xeek_dataflash_cs1_defconfig
index cfffdfa..dafbc76 100644
--- a/configs/at91sam9xeek_dataflash_cs1_defconfig
+++ b/configs/at91sam9xeek_dataflash_cs1_defconfig
@@ -34,8 +34,8 @@
 CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
diff --git a/configs/at91sam9xeek_nandflash_defconfig b/configs/at91sam9xeek_nandflash_defconfig
index dc633aa..4ee101f 100644
--- a/configs/at91sam9xeek_nandflash_defconfig
+++ b/configs/at91sam9xeek_nandflash_defconfig
@@ -33,8 +33,8 @@
 CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig
index 4a893ed..c32d535 100644
--- a/configs/bayleybay_defconfig
+++ b/configs/bayleybay_defconfig
@@ -34,8 +34,8 @@
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
diff --git a/configs/bcm96846_defconfig b/configs/bcm96846_defconfig
index 877a606..8bc6ac1 100644
--- a/configs/bcm96846_defconfig
+++ b/configs/bcm96846_defconfig
@@ -14,22 +14,18 @@
 CONFIG_SYS_LOAD_ADDR=0x01000000
 CONFIG_IDENT_STRING=" Broadcom BCM6846"
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_OF_UPSTREAM=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_HUSH_PARSER=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_UBI=y
-CONFIG_CMD_UBIFS=y
 CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nand0=nand0"
+CONFIG_CMD_UBI=y
 CONFIG_OF_EMBED=y
 CONFIG_CLK=y
 CONFIG_MTD=y
-CONFIG_MTDIDS_DEFAULT="nand0=nand0"
 CONFIG_DM_MTD=y
-CONFIG_MTD_RAW_NAND=y
 CONFIG_MTD_UBI_FASTMAP=y
 CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
-CONFIG_SYS_NAND_ONFI_DETECTION=n
diff --git a/configs/beaver_defconfig b/configs/beaver_defconfig
index 17a1b18..71037ee 100644
--- a/configs/beaver_defconfig
+++ b/configs/beaver_defconfig
@@ -9,8 +9,8 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFE000
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-beaver"
-CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SPL_STACK=0x800ffffc
+CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SYS_LOAD_ADDR=0x81000000
 CONFIG_TEGRA30=y
 CONFIG_TARGET_BEAVER=y
diff --git a/configs/bitmain_antminer_s9_defconfig b/configs/bitmain_antminer_s9_defconfig
index f8ea8f9..afff2d5 100644
--- a/configs/bitmain_antminer_s9_defconfig
+++ b/configs/bitmain_antminer_s9_defconfig
@@ -54,9 +54,9 @@
 CONFIG_CMD_NAND_LOCK_UNLOCK=y
 CONFIG_CMD_PART=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_MAY_FAIL=y
 CONFIG_SYS_DISABLE_AUTOLOAD=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_PXE=y
@@ -74,9 +74,9 @@
 CONFIG_ENV_IS_IN_FAT=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
 CONFIG_BOOTP_SERVERIP=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_DFU_TIMEOUT=y
diff --git a/configs/bk4r1_defconfig b/configs/bk4r1_defconfig
index 2cd3762..3ed587a 100644
--- a/configs/bk4r1_defconfig
+++ b/configs/bk4r1_defconfig
@@ -42,8 +42,8 @@
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_NAND_TRIMFFS=y
-CONFIG_CMD_DHCP=y
 CONFIG_SYS_DISABLE_AUTOLOAD=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_BOOTCOUNT=y
diff --git a/configs/boston32r2_defconfig b/configs/boston32r2_defconfig
index cc4ba11..6f4dfad 100644
--- a/configs/boston32r2_defconfig
+++ b/configs/boston32r2_defconfig
@@ -31,8 +31,8 @@
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_PCI=y
 CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
 CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DNS=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_DOS_PARTITION is not set
diff --git a/configs/boston32r2el_defconfig b/configs/boston32r2el_defconfig
index f983150..cdf13c8 100644
--- a/configs/boston32r2el_defconfig
+++ b/configs/boston32r2el_defconfig
@@ -32,8 +32,8 @@
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_PCI=y
 CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
 CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DNS=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_DOS_PARTITION is not set
diff --git a/configs/boston32r6_defconfig b/configs/boston32r6_defconfig
index 4a404f0..d8fb956 100644
--- a/configs/boston32r6_defconfig
+++ b/configs/boston32r6_defconfig
@@ -32,8 +32,8 @@
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_PCI=y
 CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
 CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DNS=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_DOS_PARTITION is not set
diff --git a/configs/boston32r6el_defconfig b/configs/boston32r6el_defconfig
index 49fb759..b6d3102 100644
--- a/configs/boston32r6el_defconfig
+++ b/configs/boston32r6el_defconfig
@@ -33,8 +33,8 @@
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_PCI=y
 CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
 CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DNS=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_DOS_PARTITION is not set
diff --git a/configs/boston64r2_defconfig b/configs/boston64r2_defconfig
index 5b710fc..6b23d18 100644
--- a/configs/boston64r2_defconfig
+++ b/configs/boston64r2_defconfig
@@ -32,8 +32,8 @@
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_PCI=y
 CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
 CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DNS=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_DOS_PARTITION is not set
diff --git a/configs/boston64r2el_defconfig b/configs/boston64r2el_defconfig
index 1d4bb7d..ff4b526 100644
--- a/configs/boston64r2el_defconfig
+++ b/configs/boston64r2el_defconfig
@@ -33,8 +33,8 @@
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_PCI=y
 CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
 CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DNS=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_DOS_PARTITION is not set
diff --git a/configs/boston64r6_defconfig b/configs/boston64r6_defconfig
index b736534..a7446ec 100644
--- a/configs/boston64r6_defconfig
+++ b/configs/boston64r6_defconfig
@@ -32,8 +32,8 @@
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_PCI=y
 CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
 CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DNS=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_DOS_PARTITION is not set
diff --git a/configs/boston64r6el_defconfig b/configs/boston64r6el_defconfig
index caf5da3..0dab8ef 100644
--- a/configs/boston64r6el_defconfig
+++ b/configs/boston64r6el_defconfig
@@ -33,8 +33,8 @@
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_PCI=y
 CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
 CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DNS=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_DOS_PARTITION is not set
diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig
index 4691bc6..d96fdaa 100644
--- a/configs/brppt1_mmc_defconfig
+++ b/configs/brppt1_mmc_defconfig
@@ -61,9 +61,9 @@
 CONFIG_CMD_PART=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_ITEST is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_MAY_FAIL=y
 CONFIG_SYS_DISABLE_AUTOLOAD=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_BOOTCOUNT=y
@@ -86,8 +86,8 @@
 CONFIG_VERSION_VARIABLE=y
 CONFIG_NET_RETRY_COUNT=10
 CONFIG_BOOTP_SEND_HOSTNAME=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SPL_OF_TRANSLATE=y
diff --git a/configs/brppt2_defconfig b/configs/brppt2_defconfig
index 0bbb682..f02aef2 100644
--- a/configs/brppt2_defconfig
+++ b/configs/brppt2_defconfig
@@ -51,9 +51,9 @@
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_MAY_FAIL=y
 CONFIG_SYS_DISABLE_AUTOLOAD=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
@@ -69,8 +69,8 @@
 CONFIG_ARP_TIMEOUT=1500
 CONFIG_NET_RETRY_COUNT=10
 CONFIG_BOOTP_SEND_HOSTNAME=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_SPL_DM_SEQ_ALIAS=y
 # CONFIG_OF_TRANSLATE is not set
diff --git a/configs/brsmarc1_defconfig b/configs/brsmarc1_defconfig
index 2c13976..ee70220 100644
--- a/configs/brsmarc1_defconfig
+++ b/configs/brsmarc1_defconfig
@@ -61,7 +61,6 @@
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_EDITENV is not set
 # CONFIG_CMD_CRC32 is not set
-CONFIG_CMD_CLK=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_LOADS is not set
@@ -69,9 +68,9 @@
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_ITEST is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_MAY_FAIL=y
 CONFIG_SYS_DISABLE_AUTOLOAD=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
@@ -89,8 +88,8 @@
 CONFIG_VERSION_VARIABLE=y
 CONFIG_NET_RETRY_COUNT=10
 CONFIG_BOOTP_SEND_HOSTNAME=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 # CONFIG_OF_TRANSLATE is not set
diff --git a/configs/brxre1_defconfig b/configs/brxre1_defconfig
index d5f378f..245e4a5 100644
--- a/configs/brxre1_defconfig
+++ b/configs/brxre1_defconfig
@@ -59,9 +59,9 @@
 CONFIG_CMD_PART=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_ITEST is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_MAY_FAIL=y
 CONFIG_SYS_DISABLE_AUTOLOAD=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
@@ -80,8 +80,8 @@
 CONFIG_VERSION_VARIABLE=y
 CONFIG_NET_RETRY_COUNT=10
 CONFIG_BOOTP_SEND_HOSTNAME=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 # CONFIG_OF_TRANSLATE is not set
diff --git a/configs/deneb_defconfig b/configs/capricorn_cxg3_defconfig
similarity index 88%
rename from configs/deneb_defconfig
rename to configs/capricorn_cxg3_defconfig
index b220dc8..2764455 100644
--- a/configs/deneb_defconfig
+++ b/configs/capricorn_cxg3_defconfig
@@ -10,22 +10,23 @@
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
+CONFIG_ENV_OFFSET=0x200000
 CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8-deneb"
+CONFIG_DEFAULT_DEVICE_TREE="imx8-capricorn-cxg3"
 CONFIG_SPL_TEXT_BASE=0x100000
-CONFIG_TARGET_DENEB=y
+CONFIG_TARGET_CAPRICORN=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x13e000
+CONFIG_SPL_TEXT_BASE=0x100000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x128000
 CONFIG_SPL_BSS_MAX_SIZE=0x1000
 CONFIG_SYS_BOOTM_LEN=0x800000
 CONFIG_SYS_LOAD_ADDR=0x80280000
 CONFIG_SPL=y
-CONFIG_ENV_OFFSET_REDUND=0x2000
+CONFIG_ENV_OFFSET_REDUND=0x202000
 CONFIG_IDENT_STRING=" ##v01.06"
 CONFIG_REMAKE_ELF=y
 # CONFIG_EFI_LOADER is not set
@@ -55,9 +56,10 @@
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000
-CONFIG_SPL_SYS_MALLOC_SIZE=0x3000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x4000
 CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
 CONFIG_SPL_POWER_DOMAIN=y
 CONFIG_SPL_WATCHDOG=y
 CONFIG_HUSH_PARSER=y
@@ -112,10 +114,13 @@
 CONFIG_MV88E61XX_SWITCH=y
 CONFIG_MV88E61XX_CPU_PORT=5
 CONFIG_MV88E61XX_PHY_PORTS=0x7
+CONFIG_DM_ETH_PHY=y
 CONFIG_FEC_MXC_SHARE_MDIO=y
 CONFIG_FEC_MXC_MDIO_BASE=0x5B050000
 CONFIG_FEC_MXC=y
 CONFIG_MII=y
+CONFIG_PHY=y
+CONFIG_NOP_PHY=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_IMX8=y
@@ -129,5 +134,7 @@
 CONFIG_FSL_LPUART=y
 CONFIG_DM_THERMAL=y
 CONFIG_IMX_SCU_THERMAL=y
-# CONFIG_SPL_WDT is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_WDT=y
+CONFIG_WDT_SIEMENS_PMIC=y
 CONFIG_SPL_TINY_MEMSET=y
diff --git a/configs/cardhu_defconfig b/configs/cardhu_defconfig
index 3fca1ae..57978de 100644
--- a/configs/cardhu_defconfig
+++ b/configs/cardhu_defconfig
@@ -9,8 +9,8 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFE000
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-cardhu"
-CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SPL_STACK=0x800ffffc
+CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SYS_LOAD_ADDR=0x81000000
 CONFIG_TEGRA30=y
 CONFIG_TARGET_CARDHU=y
diff --git a/configs/cei-tk1-som_defconfig b/configs/cei-tk1-som_defconfig
index 2829025..d2778fb 100644
--- a/configs/cei-tk1-som_defconfig
+++ b/configs/cei-tk1-som_defconfig
@@ -9,8 +9,8 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFE000
 CONFIG_DEFAULT_DEVICE_TREE="tegra124-cei-tk1-som"
-CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SPL_STACK=0x800ffffc
+CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SYS_LOAD_ADDR=0x81000000
 CONFIG_TEGRA124=y
 CONFIG_TARGET_CEI_TK1_SOM=y
diff --git a/configs/cherryhill_defconfig b/configs/cherryhill_defconfig
index a84d4cc..d247505 100644
--- a/configs/cherryhill_defconfig
+++ b/configs/cherryhill_defconfig
@@ -25,8 +25,8 @@
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT2=y
diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig
index cd8dbfc..874f266 100644
--- a/configs/chromebit_mickey_defconfig
+++ b/configs/chromebit_mickey_defconfig
@@ -9,7 +9,6 @@
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
 CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-mickey"
-CONFIG_SPL_TEXT_BASE=0xff704000
 CONFIG_DM_RESET=y
 CONFIG_SYS_MONITOR_LEN=614400
 CONFIG_ROCKCHIP_RK3288=y
@@ -17,6 +16,7 @@
 CONFIG_TARGET_CHROMEBIT_MICKEY=y
 CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_SPL_STACK=0xff718000
+CONFIG_SPL_TEXT_BASE=0xff704000
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
 CONFIG_SYS_BOOTM_LEN=0x4000000
diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig
index 4dc9cb8..decac2e 100644
--- a/configs/chromebook_bob_defconfig
+++ b/configs/chromebook_bob_defconfig
@@ -11,13 +11,13 @@
 CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-gru-bob"
-CONFIG_SPL_TEXT_BASE=0xff8c2000
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3399=y
 CONFIG_ROCKCHIP_BOOT_MODE_REG=0
 CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
 # CONFIG_SPL_MMC is not set
 CONFIG_SPL_STACK=0xff8effff
+CONFIG_SPL_TEXT_BASE=0xff8c2000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0xff8e0000
 CONFIG_SPL_BSS_MAX_SIZE=0x10000
diff --git a/configs/chromebook_coral_defconfig b/configs/chromebook_coral_defconfig
index 00b655e..0fb7304 100644
--- a/configs/chromebook_coral_defconfig
+++ b/configs/chromebook_coral_defconfig
@@ -6,9 +6,9 @@
 CONFIG_MAX_CPUS=8
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="chromebook_coral"
-CONFIG_SPL_TEXT_BASE=0xfef10000
 CONFIG_TPL_TEXT_BASE=0xffff8000
 CONFIG_SPL_SYS_MALLOC_F_LEN=0xf000
+CONFIG_SPL_TEXT_BASE=0xfef10000
 CONFIG_DEBUG_UART_BASE=0xde000000
 CONFIG_DEBUG_UART_CLOCK=1843200
 CONFIG_DEBUG_UART_BOARD_INIT=y
diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig
index f719cff..f40b8e8 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -9,13 +9,13 @@
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
 CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-jerry"
-CONFIG_SPL_TEXT_BASE=0xff704000
 CONFIG_DM_RESET=y
 CONFIG_SYS_MONITOR_LEN=614400
 CONFIG_ROCKCHIP_RK3288=y
 # CONFIG_SPL_MMC is not set
 CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_SPL_STACK=0xff718000
+CONFIG_SPL_TEXT_BASE=0xff704000
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
 CONFIG_SYS_BOOTM_LEN=0x4000000
diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig
index 9b9fb80..5bbea6c 100644
--- a/configs/chromebook_kevin_defconfig
+++ b/configs/chromebook_kevin_defconfig
@@ -11,7 +11,6 @@
 CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-gru-kevin"
-CONFIG_SPL_TEXT_BASE=0xff8c2000
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3399=y
 CONFIG_ROCKCHIP_BOOT_MODE_REG=0
@@ -19,6 +18,7 @@
 # CONFIG_SPL_MMC is not set
 CONFIG_TARGET_CHROMEBOOK_KEVIN=y
 CONFIG_SPL_STACK=0xff8effff
+CONFIG_SPL_TEXT_BASE=0xff8c2000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0xff8e0000
 CONFIG_SPL_BSS_MAX_SIZE=0x10000
diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig
index 9583f87..0fc1279 100644
--- a/configs/chromebook_link64_defconfig
+++ b/configs/chromebook_link64_defconfig
@@ -47,8 +47,8 @@
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig
index ef4bfc9..a2231cc 100644
--- a/configs/chromebook_link_defconfig
+++ b/configs/chromebook_link_defconfig
@@ -37,8 +37,8 @@
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_SOUND=y
diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig
index c973fe7..2f125ba 100644
--- a/configs/chromebook_minnie_defconfig
+++ b/configs/chromebook_minnie_defconfig
@@ -9,7 +9,6 @@
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
 CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-minnie"
-CONFIG_SPL_TEXT_BASE=0xff704000
 CONFIG_DM_RESET=y
 CONFIG_SYS_MONITOR_LEN=614400
 CONFIG_ROCKCHIP_RK3288=y
@@ -17,6 +16,7 @@
 CONFIG_TARGET_CHROMEBOOK_MINNIE=y
 CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_SPL_STACK=0xff718000
+CONFIG_SPL_TEXT_BASE=0xff704000
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
 CONFIG_SYS_BOOTM_LEN=0x4000000
diff --git a/configs/chromebook_samus_defconfig b/configs/chromebook_samus_defconfig
index 67ebbe3..6e9aa60 100644
--- a/configs/chromebook_samus_defconfig
+++ b/configs/chromebook_samus_defconfig
@@ -37,8 +37,8 @@
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_SOUND=y
diff --git a/configs/chromebook_samus_tpl_defconfig b/configs/chromebook_samus_tpl_defconfig
index 075e3f1..fc524da 100644
--- a/configs/chromebook_samus_tpl_defconfig
+++ b/configs/chromebook_samus_tpl_defconfig
@@ -7,10 +7,10 @@
 CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="chromebook_samus"
-CONFIG_SPL_TEXT_BASE=0xffe70000
 CONFIG_TPL_TEXT_BASE=0xfffd8100
 CONFIG_TPL_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x3000
+CONFIG_SPL_TEXT_BASE=0xffe70000
 CONFIG_DEBUG_UART_BASE=0x3f8
 CONFIG_DEBUG_UART_CLOCK=1843200
 CONFIG_DEBUG_UART_BOARD_INIT=y
diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig
index 401fead..c19b090 100644
--- a/configs/chromebook_speedy_defconfig
+++ b/configs/chromebook_speedy_defconfig
@@ -9,7 +9,6 @@
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
 CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-speedy"
-CONFIG_SPL_TEXT_BASE=0xff704000
 CONFIG_DM_RESET=y
 CONFIG_SYS_MONITOR_LEN=614400
 CONFIG_ROCKCHIP_RK3288=y
@@ -17,6 +16,7 @@
 CONFIG_TARGET_CHROMEBOOK_SPEEDY=y
 CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_SPL_STACK=0xff718000
+CONFIG_SPL_TEXT_BASE=0xff704000
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
 CONFIG_SYS_BOOTM_LEN=0x4000000
diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig
index b7396fa..a1561fd 100644
--- a/configs/chromebox_panther_defconfig
+++ b/configs/chromebox_panther_defconfig
@@ -29,8 +29,8 @@
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
diff --git a/configs/ci20_mmc_defconfig b/configs/ci20_mmc_defconfig
index a541d95..2d094bd 100644
--- a/configs/ci20_mmc_defconfig
+++ b/configs/ci20_mmc_defconfig
@@ -8,10 +8,10 @@
 CONFIG_ENV_SIZE=0x8000
 CONFIG_ENV_OFFSET=0x83800
 CONFIG_DEFAULT_DEVICE_TREE="ci20"
-CONFIG_SPL_TEXT_BASE=0xf4000a00
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_STACK=0xf4008000
+CONFIG_SPL_TEXT_BASE=0xf4000a00
 CONFIG_SPL_BSS_START_ADDR=0xf4004000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
 CONFIG_SYS_BOOTM_LEN=0x4000000
diff --git a/configs/cl-som-imx7_defconfig b/configs/cl-som-imx7_defconfig
index 217617e..b023106 100644
--- a/configs/cl-som-imx7_defconfig
+++ b/configs/cl-som-imx7_defconfig
@@ -53,8 +53,8 @@
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
 CONFIG_SYS_DISABLE_AUTOLOAD=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 # CONFIG_CMD_MDIO is not set
 CONFIG_CMD_PING=y
diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig
index bba25e0..6f6597c 100644
--- a/configs/clearfog_defconfig
+++ b/configs/clearfog_defconfig
@@ -11,9 +11,9 @@
 CONFIG_TARGET_CLEARFOG=y
 CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC=y
 CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog"
-CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK=0x4002c000
+CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x40023000
 CONFIG_SPL_BSS_MAX_SIZE=0x4000
diff --git a/configs/clearfog_sata_defconfig b/configs/clearfog_sata_defconfig
index b82d604..491a273 100644
--- a/configs/clearfog_sata_defconfig
+++ b/configs/clearfog_sata_defconfig
@@ -11,9 +11,9 @@
 CONFIG_TARGET_CLEARFOG=y
 CONFIG_MVEBU_SPL_BOOT_DEVICE_SATA=y
 CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog"
-CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK=0x4002c000
+CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x40023000
 CONFIG_SPL_BSS_MAX_SIZE=0x4000
diff --git a/configs/clearfog_spi_defconfig b/configs/clearfog_spi_defconfig
index cef80d6..d3de165 100644
--- a/configs/clearfog_spi_defconfig
+++ b/configs/clearfog_spi_defconfig
@@ -11,9 +11,9 @@
 CONFIG_TARGET_CLEARFOG=y
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog"
-CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK=0x4002c000
+CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x40023000
 CONFIG_SPL_BSS_MAX_SIZE=0x4000
diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig
index edc27eb..a7940c2 100644
--- a/configs/cm_t43_defconfig
+++ b/configs/cm_t43_defconfig
@@ -12,12 +12,12 @@
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="am437x-cm-t43"
-CONFIG_SPL_TEXT_BASE=0x40300350
 CONFIG_AM43XX=y
 CONFIG_TARGET_CM_T43=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0x40300350
 CONFIG_SPL=y
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
diff --git a/configs/colibri-imx6ull-emmc_defconfig b/configs/colibri-imx6ull-emmc_defconfig
index c9ab51d..ba65a3c 100644
--- a/configs/colibri-imx6ull-emmc_defconfig
+++ b/configs/colibri-imx6ull-emmc_defconfig
@@ -51,9 +51,7 @@
 CONFIG_SYS_MMC_ENV_PART=1
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_VERSION_VARIABLE=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_IP_DEFRAG=y
-CONFIG_TFTP_BLOCKSIZE=16352
 CONFIG_TFTP_TSIZE=y
 CONFIG_USE_IPADDR=y
 CONFIG_IPADDR="192.168.10.2"
@@ -61,6 +59,8 @@
 CONFIG_NETMASK="255.255.255.0"
 CONFIG_USE_SERVERIP=y
 CONFIG_SERVERIP="192.168.10.1"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TFTP_BLOCKSIZE=16352
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_BOOTCOUNT_ENV=y
diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig
index 4a0ff02..785e8a6 100644
--- a/configs/colibri-imx6ull_defconfig
+++ b/configs/colibri-imx6ull_defconfig
@@ -61,9 +61,7 @@
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_VERSION_VARIABLE=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_IP_DEFRAG=y
-CONFIG_TFTP_BLOCKSIZE=16352
 CONFIG_TFTP_TSIZE=y
 CONFIG_USE_IPADDR=y
 CONFIG_IPADDR="192.168.10.2"
@@ -71,6 +69,8 @@
 CONFIG_NETMASK="255.255.255.0"
 CONFIG_USE_SERVERIP=y
 CONFIG_SERVERIP="192.168.10.1"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TFTP_BLOCKSIZE=16352
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_BOOTCOUNT_ENV=y
diff --git a/configs/colibri-imx8x_defconfig b/configs/colibri-imx8x_defconfig
index 42569ec..3d576da 100644
--- a/configs/colibri-imx8x_defconfig
+++ b/configs/colibri-imx8x_defconfig
@@ -54,9 +54,7 @@
 CONFIG_SYS_MMC_ENV_PART=1
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_VERSION_VARIABLE=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_IP_DEFRAG=y
-CONFIG_TFTP_BLOCKSIZE=4096
 CONFIG_TFTP_TSIZE=y
 CONFIG_USE_IPADDR=y
 CONFIG_IPADDR="192.168.10.2"
@@ -64,6 +62,8 @@
 CONFIG_NETMASK="255.255.255.0"
 CONFIG_USE_SERVERIP=y
 CONFIG_SERVERIP="192.168.10.1"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TFTP_BLOCKSIZE=4096
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_BOOTCOUNT_ENV=y
 CONFIG_CLK_IMX8=y
diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig
index facf0b2..4c6ba80 100644
--- a/configs/colibri_imx6_defconfig
+++ b/configs/colibri_imx6_defconfig
@@ -72,15 +72,15 @@
 CONFIG_SYS_MMC_ENV_PART=1
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_VERSION_VARIABLE=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_IP_DEFRAG=y
-CONFIG_TFTP_BLOCKSIZE=16352
 CONFIG_USE_IPADDR=y
 CONFIG_IPADDR="192.168.10.2"
 CONFIG_USE_NETMASK=y
 CONFIG_NETMASK="255.255.255.0"
 CONFIG_USE_SERVERIP=y
 CONFIG_SERVERIP="192.168.10.1"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TFTP_BLOCKSIZE=16352
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_BOOTCOUNT_ENV=y
diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig
index cc616f4..7885d0e 100644
--- a/configs/colibri_imx7_defconfig
+++ b/configs/colibri_imx7_defconfig
@@ -61,15 +61,15 @@
 CONFIG_ENV_RANGE=0x80000
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_IP_DEFRAG=y
-CONFIG_TFTP_BLOCKSIZE=16352
 CONFIG_USE_IPADDR=y
 CONFIG_IPADDR="192.168.10.2"
 CONFIG_USE_NETMASK=y
 CONFIG_NETMASK="255.255.255.0"
 CONFIG_USE_SERVERIP=y
 CONFIG_SERVERIP="192.168.10.1"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TFTP_BLOCKSIZE=16352
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_BOOTCOUNT_ENV=y
diff --git a/configs/colibri_imx7_emmc_defconfig b/configs/colibri_imx7_emmc_defconfig
index 57d5017..ab6a156 100644
--- a/configs/colibri_imx7_emmc_defconfig
+++ b/configs/colibri_imx7_emmc_defconfig
@@ -50,15 +50,15 @@
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SYS_MMC_ENV_PART=1
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_IP_DEFRAG=y
-CONFIG_TFTP_BLOCKSIZE=16352
 CONFIG_USE_IPADDR=y
 CONFIG_IPADDR="192.168.10.2"
 CONFIG_USE_NETMASK=y
 CONFIG_NETMASK="255.255.255.0"
 CONFIG_USE_SERVERIP=y
 CONFIG_SERVERIP="192.168.10.1"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TFTP_BLOCKSIZE=16352
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_BOOTCOUNT_ENV=y
 CONFIG_FSL_CAAM_JR_NTZ_ACCESS=y
diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig
index a1a12e2..6c5c1a9 100644
--- a/configs/colibri_t20_defconfig
+++ b/configs/colibri_t20_defconfig
@@ -8,9 +8,9 @@
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x200000
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-colibri"
-CONFIG_SPL_TEXT_BASE=0x00108000
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_STACK=0xffffc
+CONFIG_SPL_TEXT_BASE=0x00108000
 CONFIG_SYS_LOAD_ADDR=0x1000000
 CONFIG_TEGRA20=y
 CONFIG_TARGET_COLIBRI_T20=y
@@ -50,10 +50,10 @@
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_IP_DEFRAG=y
-CONFIG_TFTP_BLOCKSIZE=1536
 CONFIG_TFTP_TSIZE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TFTP_BLOCKSIZE=1536
 CONFIG_SYS_I2C_TEGRA=y
 CONFIG_DM_MTD=y
 CONFIG_MTD_RAW_NAND=y
diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig
index 3be175b..4f2dde6 100644
--- a/configs/colibri_t30_defconfig
+++ b/configs/colibri_t30_defconfig
@@ -8,9 +8,9 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFDE00
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-colibri"
-CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_STACK=0x800ffffc
+CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SYS_LOAD_ADDR=0x81000000
 CONFIG_TEGRA30=y
 CONFIG_TARGET_COLIBRI_T30=y
@@ -44,10 +44,10 @@
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SYS_MMC_ENV_PART=1
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_IP_DEFRAG=y
-CONFIG_TFTP_BLOCKSIZE=16352
 CONFIG_TFTP_TSIZE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TFTP_BLOCKSIZE=16352
 CONFIG_SYS_I2C_TEGRA=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig
index de3cf23..3a80624 100644
--- a/configs/colibri_vf_defconfig
+++ b/configs/colibri_vf_defconfig
@@ -66,13 +66,13 @@
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_VERSION_VARIABLE=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_USE_IPADDR=y
 CONFIG_IPADDR="192.168.10.2"
 CONFIG_USE_NETMASK=y
 CONFIG_NETMASK="255.255.255.0"
 CONFIG_USE_SERVERIP=y
 CONFIG_SERVERIP="192.168.10.1"
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DFU_NAND=y
 CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
 CONFIG_VYBRID_GPIO=y
diff --git a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
index 2512307..bb3d721 100644
--- a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
+++ b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
@@ -41,8 +41,8 @@
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig
index f511932..c5fb5a9 100644
--- a/configs/conga-qeval20-qa3-e3845_defconfig
+++ b/configs/conga-qeval20-qa3-e3845_defconfig
@@ -37,8 +37,8 @@
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
diff --git a/configs/controlcenterdc_defconfig b/configs/controlcenterdc_defconfig
index cced383..2d6c83a 100644
--- a/configs/controlcenterdc_defconfig
+++ b/configs/controlcenterdc_defconfig
@@ -14,9 +14,9 @@
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DEFAULT_DEVICE_TREE="armada-38x-controlcenterdc"
-CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK=0x40031000
+CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x40028000
 CONFIG_SPL_BSS_MAX_SIZE=0x4000
diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig
index b1e3ee0..ce2f4f7 100644
--- a/configs/corvus_defconfig
+++ b/configs/corvus_defconfig
@@ -18,9 +18,9 @@
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x70007f00
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="at91sam9g45-corvus"
-CONFIG_SPL_TEXT_BASE=0x300000
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK=0x4000
+CONFIG_SPL_TEXT_BASE=0x300000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x3000
 CONFIG_SPL_BSS_MAX_SIZE=0x800
@@ -59,8 +59,8 @@
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_DOS_PARTITION=y
diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig
index b733a57..134b353 100644
--- a/configs/cougarcanyon2_defconfig
+++ b/configs/cougarcanyon2_defconfig
@@ -28,8 +28,8 @@
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT2=y
diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig
index 58c9770..3129cbf 100644
--- a/configs/crownbay_defconfig
+++ b/configs/crownbay_defconfig
@@ -30,8 +30,8 @@
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_SOUND=y
diff --git a/configs/d2net_v2_defconfig b/configs/d2net_v2_defconfig
index 1fe21be..c5e4bb0 100644
--- a/configs/d2net_v2_defconfig
+++ b/configs/d2net_v2_defconfig
@@ -36,8 +36,8 @@
 CONFIG_CMD_SATA=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_SYS_DISABLE_AUTOLOAD=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_EXT2=y
diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig
index dbc9bf4..4cddc7f 100644
--- a/configs/da850evm_defconfig
+++ b/configs/da850evm_defconfig
@@ -19,9 +19,9 @@
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="ti/davinci/da850-evm"
-CONFIG_SPL_TEXT_BASE=0x80000000
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK=0x8001ff00
+CONFIG_SPL_TEXT_BASE=0x80000000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0xc0000000
 CONFIG_SYS_LOAD_ADDR=0xc0700000
diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig
index 0513648..b8b1a96 100644
--- a/configs/da850evm_nand_defconfig
+++ b/configs/da850evm_nand_defconfig
@@ -16,9 +16,9 @@
 CONFIG_ENV_OFFSET=0x0
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="ti/davinci/da850-evm"
-CONFIG_SPL_TEXT_BASE=0x80000000
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK=0x8001ff00
+CONFIG_SPL_TEXT_BASE=0x80000000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0xc0000000
 CONFIG_SYS_LOAD_ADDR=0xc0700000
diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig
index 865aca7..4dba371 100644
--- a/configs/dalmore_defconfig
+++ b/configs/dalmore_defconfig
@@ -8,8 +8,8 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFE000
 CONFIG_DEFAULT_DEVICE_TREE="tegra114-dalmore"
-CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SPL_STACK=0x800ffffc
+CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SYS_LOAD_ADDR=0x81000000
 CONFIG_TEGRA114=y
 CONFIG_TARGET_DALMORE=y
diff --git a/configs/db-88f6720_defconfig b/configs/db-88f6720_defconfig
index 31645f0..d2f400d 100644
--- a/configs/db-88f6720_defconfig
+++ b/configs/db-88f6720_defconfig
@@ -12,9 +12,9 @@
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="armada-375-db"
-CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK=0x4002c000
+CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x40020000
 CONFIG_SPL_BSS_MAX_SIZE=0x4000
@@ -38,8 +38,8 @@
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
diff --git a/configs/db-88f6820-amc_defconfig b/configs/db-88f6820-amc_defconfig
index 3b91ebc..23fe44f 100644
--- a/configs/db-88f6820-amc_defconfig
+++ b/configs/db-88f6820-amc_defconfig
@@ -12,9 +12,9 @@
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DEFAULT_DEVICE_TREE="armada-385-db-88f6820-amc"
-CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK=0x4002c000
+CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x40023000
 CONFIG_SPL_BSS_MAX_SIZE=0x4000
@@ -42,8 +42,8 @@
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
diff --git a/configs/db-88f6820-amc_nand_defconfig b/configs/db-88f6820-amc_nand_defconfig
index 60caed4..f0dd977 100644
--- a/configs/db-88f6820-amc_nand_defconfig
+++ b/configs/db-88f6820-amc_nand_defconfig
@@ -14,9 +14,9 @@
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DEFAULT_DEVICE_TREE="armada-385-db-88f6820-amc"
-CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK=0x4002c000
+CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x40023000
 CONFIG_SPL_BSS_MAX_SIZE=0x4000
@@ -44,8 +44,8 @@
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig
index 5b69a20..cb017a7 100644
--- a/configs/db-88f6820-gp_defconfig
+++ b/configs/db-88f6820-gp_defconfig
@@ -12,9 +12,9 @@
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DEFAULT_DEVICE_TREE="armada-388-gp"
-CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK=0x4002c000
+CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x40023000
 CONFIG_SPL_BSS_MAX_SIZE=0x4000
@@ -41,8 +41,8 @@
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
diff --git a/configs/db-mv784mp-gp_defconfig b/configs/db-mv784mp-gp_defconfig
index 7e1495b..a417c94 100644
--- a/configs/db-mv784mp-gp_defconfig
+++ b/configs/db-mv784mp-gp_defconfig
@@ -12,9 +12,9 @@
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="armada-xp-gp"
-CONFIG_SPL_TEXT_BASE=0x40004030
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK=0x4002c000
+CONFIG_SPL_TEXT_BASE=0x40004030
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x40020000
 CONFIG_SPL_BSS_MAX_SIZE=0x4000
@@ -41,8 +41,8 @@
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
diff --git a/configs/db-xc3-24g4xg_defconfig b/configs/db-xc3-24g4xg_defconfig
index 78ee3bd..06e52cc 100644
--- a/configs/db-xc3-24g4xg_defconfig
+++ b/configs/db-xc3-24g4xg_defconfig
@@ -26,8 +26,8 @@
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
diff --git a/configs/dfi-bt700-q7x-151_defconfig b/configs/dfi-bt700-q7x-151_defconfig
index ea0d30e..d9fff4e 100644
--- a/configs/dfi-bt700-q7x-151_defconfig
+++ b/configs/dfi-bt700-q7x-151_defconfig
@@ -35,8 +35,8 @@
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
diff --git a/configs/dns325_defconfig b/configs/dns325_defconfig
index 9cbe788..323e2f5 100644
--- a/configs/dns325_defconfig
+++ b/configs/dns325_defconfig
@@ -27,8 +27,8 @@
 CONFIG_CMD_NAND=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_SYS_DISABLE_AUTOLOAD=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_EXT2=y
diff --git a/configs/dockstar_defconfig b/configs/dockstar_defconfig
index e2bb60f..e35ca16 100644
--- a/configs/dockstar_defconfig
+++ b/configs/dockstar_defconfig
@@ -42,9 +42,9 @@
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_NAND=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
 CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
+CONFIG_NET_RANDOM_ETHADDR=y
 # CONFIG_MMC is not set
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 7061339..2448bef 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -6,9 +6,9 @@
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
-CONFIG_SPL_TEXT_BASE=0x40300000
 CONFIG_OMAP54XX=y
 CONFIG_TARGET_DRA7XX_EVM=y
+CONFIG_SPL_TEXT_BASE=0x40300000
 CONFIG_SPL=y
 CONFIG_ENV_OFFSET_REDUND=0x280000
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
diff --git a/configs/dra7xx_hs_evm_usb_defconfig b/configs/dra7xx_hs_evm_usb_defconfig
index fca69a4..850ccd9 100644
--- a/configs/dra7xx_hs_evm_usb_defconfig
+++ b/configs/dra7xx_hs_evm_usb_defconfig
@@ -7,12 +7,12 @@
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
-CONFIG_SPL_TEXT_BASE=0x40306D50
 CONFIG_OMAP54XX=y
 CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
 CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
 CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000
 CONFIG_TARGET_DRA7XX_EVM=y
+CONFIG_SPL_TEXT_BASE=0x40306D50
 CONFIG_SPL=y
 CONFIG_ENV_OFFSET_REDUND=0x280000
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
diff --git a/configs/draco-etamin_defconfig b/configs/draco-etamin_defconfig
index 8c902e4..f650dbc 100644
--- a/configs/draco-etamin_defconfig
+++ b/configs/draco-etamin_defconfig
@@ -53,8 +53,8 @@
 CONFIG_CMD_NAND=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_DNS2=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
diff --git a/configs/draco-rastaban_defconfig b/configs/draco-rastaban_defconfig
index 3953a1a..511956e 100644
--- a/configs/draco-rastaban_defconfig
+++ b/configs/draco-rastaban_defconfig
@@ -50,8 +50,8 @@
 CONFIG_CMD_NAND=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_DNS2=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
diff --git a/configs/draco-thuban_defconfig b/configs/draco-thuban_defconfig
index 2851336..1b2ce3b 100644
--- a/configs/draco-thuban_defconfig
+++ b/configs/draco-thuban_defconfig
@@ -50,8 +50,8 @@
 CONFIG_CMD_NAND=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_DNS2=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
diff --git a/configs/dreamplug_defconfig b/configs/dreamplug_defconfig
index 7ef8ed0..f347c09 100644
--- a/configs/dreamplug_defconfig
+++ b/configs/dreamplug_defconfig
@@ -39,9 +39,9 @@
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_ENV_SPI_MAX_HZ=50000000
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
 CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SATA_MV=y
 CONFIG_SYS_SATA_MAX_DEVICE=1
 CONFIG_SYS_ATA_STRIDE=4
diff --git a/configs/ds116_defconfig b/configs/ds116_defconfig
index c321e6f..8562874 100644
--- a/configs/ds116_defconfig
+++ b/configs/ds116_defconfig
@@ -17,9 +17,9 @@
 CONFIG_ENV_OFFSET=0x7E0000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="marvell/armada-385-synology-ds116"
-CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK=0x4002c000
+CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x40023000
 CONFIG_SPL_BSS_MAX_SIZE=0x4000
@@ -62,8 +62,8 @@
 CONFIG_VERSION_VARIABLE=y
 CONFIG_ARP_TIMEOUT=200
 CONFIG_NET_RETRY_COUNT=50
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_AHCI_GENERIC=y
 CONFIG_LBA48=y
diff --git a/configs/ds414_defconfig b/configs/ds414_defconfig
index 4676c55..25e5be3 100644
--- a/configs/ds414_defconfig
+++ b/configs/ds414_defconfig
@@ -17,9 +17,9 @@
 CONFIG_ENV_OFFSET=0x7E0000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="armada-xp-synology-ds414"
-CONFIG_SPL_TEXT_BASE=0x40004030
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK=0x4002c000
+CONFIG_SPL_TEXT_BASE=0x40004030
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x40020000
 CONFIG_SPL_BSS_MAX_SIZE=0x4000
diff --git a/configs/eb_cpu5282_defconfig b/configs/eb_cpu5282_defconfig
index 271dbdf..1c52322 100644
--- a/configs/eb_cpu5282_defconfig
+++ b/configs/eb_cpu5282_defconfig
@@ -26,8 +26,8 @@
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_MII_INIT=y
 CONFIG_OVERWRITE_ETHADDR_ONCE=y
diff --git a/configs/eb_cpu5282_internal_defconfig b/configs/eb_cpu5282_internal_defconfig
index 89a7925..a8c1b99 100644
--- a/configs/eb_cpu5282_internal_defconfig
+++ b/configs/eb_cpu5282_internal_defconfig
@@ -24,8 +24,8 @@
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_MII_INIT=y
 CONFIG_OVERWRITE_ETHADDR_ONCE=y
diff --git a/configs/efi-x86_payload32_defconfig b/configs/efi-x86_payload32_defconfig
index 071ddb8..957fd83 100644
--- a/configs/efi-x86_payload32_defconfig
+++ b/configs/efi-x86_payload32_defconfig
@@ -24,8 +24,8 @@
 CONFIG_CMD_PART=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT2=y
diff --git a/configs/endeavoru_defconfig b/configs/endeavoru_defconfig
index f0c8ce1..1d1f104 100644
--- a/configs/endeavoru_defconfig
+++ b/configs/endeavoru_defconfig
@@ -9,8 +9,8 @@
 CONFIG_ENV_SIZE=0x3000
 CONFIG_ENV_OFFSET=0xFFFFD000
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-htc-endeavoru"
-CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SPL_STACK=0x800ffffc
+CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SYS_LOAD_ADDR=0x82000000
 CONFIG_TEGRA30=y
 CONFIG_TARGET_ENDEAVORU=y
diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig
index 78b0a5c..544ac82 100644
--- a/configs/evb-ast2500_defconfig
+++ b/configs/evb-ast2500_defconfig
@@ -27,11 +27,11 @@
 CONFIG_CMD_EEPROM=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_NCSI=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
-CONFIG_CMD_NCSI=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index 7cf97ee..c9d75e0 100644
--- a/configs/evb-ast2600_defconfig
+++ b/configs/evb-ast2600_defconfig
@@ -63,11 +63,11 @@
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_NCSI=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
-CONFIG_CMD_NCSI=y
 CONFIG_CMD_EXT4=y
 CONFIG_DOS_PARTITION=y
 # CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig
index 69c6d7e..ba79960 100644
--- a/configs/evb-rk3036_defconfig
+++ b/configs/evb-rk3036_defconfig
@@ -12,10 +12,10 @@
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000
 CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk"
-CONFIG_SPL_TEXT_BASE=0x10081000
 CONFIG_ROCKCHIP_RK3036=y
 CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_SPL_STACK=0x10081fff
+CONFIG_SPL_TEXT_BASE=0x10081000
 CONFIG_SPL_STACK_R=y
 CONFIG_SYS_LOAD_ADDR=0x60800800
 CONFIG_DEBUG_UART_BASE=0x20068000
diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig
index 7118a4f..3cbc226 100644
--- a/configs/evb-rk3229_defconfig
+++ b/configs/evb-rk3229_defconfig
@@ -10,10 +10,10 @@
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x61100000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3229-evb"
-CONFIG_SPL_TEXT_BASE=0x60000000
 CONFIG_ROCKCHIP_RK322X=y
 CONFIG_TARGET_EVB_RK3229=y
 CONFIG_SPL_STACK_R_ADDR=0x60600000
+CONFIG_SPL_TEXT_BASE=0x60000000
 CONFIG_SPL_STACK_R=y
 CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_SYS_LOAD_ADDR=0x61800800
diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig
index 6091319..fd52853 100644
--- a/configs/evb-rk3328_defconfig
+++ b/configs/evb-rk3328_defconfig
@@ -86,7 +86,6 @@
 CONFIG_SYSRESET=y
 # CONFIG_TPL_SYSRESET is not set
 CONFIG_USB=y
-CONFIG_DM_USB_GADGET=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig
index 63df818..b9e53ec 100644
--- a/configs/galileo_defconfig
+++ b/configs/galileo_defconfig
@@ -27,8 +27,8 @@
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT2=y
@@ -42,9 +42,9 @@
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_USE_BOOTFILE=y
 CONFIG_BOOTFILE="bzImage"
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_TFTP_TSIZE=y
 CONFIG_USE_ROOTPATH=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CPU=y
diff --git a/configs/gardena-smart-gateway-at91sam_defconfig b/configs/gardena-smart-gateway-at91sam_defconfig
index 243a4c3..c9eb661 100644
--- a/configs/gardena-smart-gateway-at91sam_defconfig
+++ b/configs/gardena-smart-gateway-at91sam_defconfig
@@ -15,11 +15,11 @@
 CONFIG_ENV_SIZE=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91sam9g25-gardena-smart-gateway"
-CONFIG_SPL_TEXT_BASE=0x300000
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK=0x308000
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000
+CONFIG_SPL_TEXT_BASE=0x300000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x20000000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
diff --git a/configs/ge_b1x5v2_defconfig b/configs/ge_b1x5v2_defconfig
index cfa51b2..215858c 100644
--- a/configs/ge_b1x5v2_defconfig
+++ b/configs/ge_b1x5v2_defconfig
@@ -54,11 +54,11 @@
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_SDP=y
+CONFIG_CMD_SNTP=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_DNS=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_BOOTCOUNT=y
 CONFIG_CMD_CACHE=y
diff --git a/configs/giedi_defconfig b/configs/giedi_defconfig
deleted file mode 100644
index e54d7ef..0000000
--- a/configs/giedi_defconfig
+++ /dev/null
@@ -1,133 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_IMX8=y
-CONFIG_TEXT_BASE=0x80020000
-CONFIG_SYS_MALLOC_LEN=0x2800000
-CONFIG_SYS_MALLOC_F_LEN=0x4000
-CONFIG_SPL_GPIO=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=3
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8-giedi"
-CONFIG_SPL_TEXT_BASE=0x100000
-CONFIG_TARGET_GIEDI=y
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK=0x13e000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x128000
-CONFIG_SPL_BSS_MAX_SIZE=0x1000
-CONFIG_SYS_BOOTM_LEN=0x800000
-CONFIG_SYS_LOAD_ADDR=0x80280000
-CONFIG_SPL=y
-CONFIG_ENV_OFFSET_REDUND=0x2000
-CONFIG_IDENT_STRING=" ##v01.07"
-CONFIG_REMAKE_ELF=y
-# CONFIG_EFI_LOADER is not set
-CONFIG_FIT=y
-CONFIG_FIT_EXTERNAL_OFFSET=0x3000
-CONFIG_BOOTDELAY=3
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
-CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
-CONFIG_AUTOBOOT_KEYED_CTRLC=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="if usrbutton; then run flash_self_test; reset; fi;run flash_self;reset;"
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2073
-CONFIG_LOG=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_MAX_SIZE=0x1f000
-CONFIG_SPL_BOARD_INIT=y
-# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_LEGACY_IMAGE_FORMAT is not set
-CONFIG_SPL_LOAD_IMX_CONTAINER=y
-CONFIG_IMX_CONTAINER_CFG="board/siemens/capricorn/uboot-container.cfg"
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_SYS_MALLOC=y
-CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
-CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000
-CONFIG_SPL_SYS_MALLOC_SIZE=0x3000
-CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
-CONFIG_SPL_POWER_DOMAIN=y
-CONFIG_SPL_WATCHDOG=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="U-Boot# "
-CONFIG_CMD_CPU=y
-# CONFIG_BOOTM_NETBSD is not set
-# CONFIG_CMD_EXPORTENV is not set
-# CONFIG_CMD_IMPORTENV is not set
-# CONFIG_CMD_CRC32 is not set
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DM=y
-CONFIG_CMD_FUSE=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_READ=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_MMC_ENV_PART=2
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="eth1"
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_BOOTCOUNT_ENV=y
-CONFIG_SPL_CLK=y
-CONFIG_CLK_IMX8=y
-CONFIG_CPU=y
-CONFIG_MXC_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_IMX_LPI2C=y
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_MISC=y
-CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_MMC_IO_VOLTAGE=y
-CONFIG_MMC_UHS_SUPPORT=y
-CONFIG_MMC_HS400_SUPPORT=y
-CONFIG_FSL_USDHC=y
-CONFIG_PHYLIB=y
-CONFIG_MV88E61XX_SWITCH=y
-CONFIG_MV88E61XX_CPU_PORT=5
-CONFIG_MV88E61XX_PHY_PORTS=0x7
-CONFIG_FEC_MXC_SHARE_MDIO=y
-CONFIG_FEC_MXC_MDIO_BASE=0x5B050000
-CONFIG_FEC_MXC=y
-CONFIG_MII=y
-CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
-CONFIG_PINCTRL_IMX8=y
-CONFIG_POWER_DOMAIN=y
-CONFIG_IMX8_POWER_DOMAIN=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SPL_DM_REGULATOR_GPIO=y
-CONFIG_DM_SERIAL=y
-CONFIG_FSL_LPUART=y
-CONFIG_DM_THERMAL=y
-CONFIG_IMX_SCU_THERMAL=y
-# CONFIG_SPL_WDT is not set
-CONFIG_SPL_TINY_MEMSET=y
diff --git a/configs/goflexhome_defconfig b/configs/goflexhome_defconfig
index e1ee43d..af758fc 100644
--- a/configs/goflexhome_defconfig
+++ b/configs/goflexhome_defconfig
@@ -44,9 +44,9 @@
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_NAND=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
 CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SATA_MV=y
 CONFIG_SYS_SATA_MAX_DEVICE=1
 CONFIG_LBA48=y
diff --git a/configs/grouper_defconfig b/configs/grouper_defconfig
index d07d740..9221ffb 100644
--- a/configs/grouper_defconfig
+++ b/configs/grouper_defconfig
@@ -9,8 +9,8 @@
 CONFIG_ENV_SIZE=0x3000
 CONFIG_ENV_OFFSET=0xFFFFD000
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-nexus7-grouper-E1565"
-CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SPL_STACK=0x800ffffc
+CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SYS_LOAD_ADDR=0x82000000
 CONFIG_TEGRA30=y
 CONFIG_TARGET_GROUPER=y
diff --git a/configs/grpeach_defconfig b/configs/grpeach_defconfig
index fcc079e..a400543 100644
--- a/configs/grpeach_defconfig
+++ b/configs/grpeach_defconfig
@@ -29,10 +29,10 @@
 # CONFIG_CMD_ELF is not set
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_SNTP=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
diff --git a/configs/gurnard_defconfig b/configs/gurnard_defconfig
index d42d47f..9929d58 100644
--- a/configs/gurnard_defconfig
+++ b/configs/gurnard_defconfig
@@ -30,8 +30,8 @@
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 # CONFIG_CMD_MDIO is not set
 CONFIG_CMD_PING=y
diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig
index a64e751..d8cc845 100644
--- a/configs/harmony_defconfig
+++ b/configs/harmony_defconfig
@@ -6,8 +6,8 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x1FFE0000
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-harmony"
-CONFIG_SPL_TEXT_BASE=0x00108000
 CONFIG_SPL_STACK=0xffffc
+CONFIG_SPL_TEXT_BASE=0x00108000
 CONFIG_SYS_LOAD_ADDR=0x1000000
 CONFIG_TEGRA20=y
 CONFIG_TARGET_HARMONY=y
diff --git a/configs/helios4_defconfig b/configs/helios4_defconfig
index e45446c..2778cb7 100644
--- a/configs/helios4_defconfig
+++ b/configs/helios4_defconfig
@@ -11,9 +11,9 @@
 CONFIG_TARGET_HELIOS4=y
 CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC=y
 CONFIG_DEFAULT_DEVICE_TREE="armada-388-helios4"
-CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK=0x4002c000
+CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x40023000
 CONFIG_SPL_BSS_MAX_SIZE=0x4000
diff --git a/configs/hmibsc_defconfig b/configs/hmibsc_defconfig
index 38bc73f..88c9c70 100644
--- a/configs/hmibsc_defconfig
+++ b/configs/hmibsc_defconfig
@@ -31,8 +31,8 @@
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PART=y
 CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIMER=y
diff --git a/configs/ibex-ast2700_defconfig b/configs/ibex-ast2700_defconfig
index e1d5be2..e4b9a9a 100644
--- a/configs/ibex-ast2700_defconfig
+++ b/configs/ibex-ast2700_defconfig
@@ -11,8 +11,8 @@
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x14bd7800
 CONFIG_ENV_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="ast2700-ibex"
-CONFIG_SPL_TEXT_BASE=0x14bc0080
 CONFIG_DM_RESET=y
+CONFIG_SPL_TEXT_BASE=0x14bc0080
 CONFIG_SPL_BSS_START_ADDR=0x14bd7800
 CONFIG_SPL_BSS_MAX_SIZE=0x800
 CONFIG_SYS_BOOTM_LEN=0x4000000
@@ -68,7 +68,6 @@
 CONFIG_DEVICE_TREE_INCLUDES="ast2700-u-boot.dtsi"
 # CONFIG_OF_TAG_MIGRATE is not set
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
 CONFIG_SYS_RX_ETH_BUFFER=2
 # CONFIG_DM_DEVICE_REMOVE is not set
 # CONFIG_DM_SEQ_ALIAS is not set
diff --git a/configs/iconnect_defconfig b/configs/iconnect_defconfig
index 2823965..9d195e1 100644
--- a/configs/iconnect_defconfig
+++ b/configs/iconnect_defconfig
@@ -45,9 +45,9 @@
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
 CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
+CONFIG_NET_RANDOM_ETHADDR=y
 # CONFIG_MMC is not set
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
diff --git a/configs/ideapad-yoga-11_defconfig b/configs/ideapad-yoga-11_defconfig
index a9dd521..3c152cb 100644
--- a/configs/ideapad-yoga-11_defconfig
+++ b/configs/ideapad-yoga-11_defconfig
@@ -9,8 +9,8 @@
 CONFIG_ENV_SIZE=0x3000
 CONFIG_ENV_OFFSET=0xFFFFD000
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-lenovo-ideapad-yoga-11"
-CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SPL_STACK=0x800ffffc
+CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SYS_LOAD_ADDR=0x82000000
 CONFIG_TEGRA30=y
 CONFIG_TARGET_IDEAPAD_YOGA_11=y
diff --git a/configs/imgtec_xilfpga_defconfig b/configs/imgtec_xilfpga_defconfig
index 914e293..233c89c 100644
--- a/configs/imgtec_xilfpga_defconfig
+++ b/configs/imgtec_xilfpga_defconfig
@@ -29,8 +29,8 @@
 CONFIG_CMD_TIME=y
 # CONFIG_ISO_PARTITION is not set
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_CLK=y
 CONFIG_XILINX_EMACLITE=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/imx28_xea_defconfig b/configs/imx28_xea_defconfig
index c7212d7..38282e6 100644
--- a/configs/imx28_xea_defconfig
+++ b/configs/imx28_xea_defconfig
@@ -12,7 +12,6 @@
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="imx28-xea"
-CONFIG_SPL_TEXT_BASE=0x1000
 CONFIG_TARGET_XEA=y
 CONFIG_SPL_MXS_PMU_MINIMAL_VDD5V_CURRENT=y
 CONFIG_SPL_MXS_PMU_DISABLE_BATT_CHARGE=y
@@ -21,6 +20,7 @@
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK=0x20000
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000
+CONFIG_SPL_TEXT_BASE=0x1000
 CONFIG_SYS_LOAD_ADDR=0x42000000
 CONFIG_SF_DEFAULT_BUS=2
 CONFIG_SPL_SIZE_LIMIT=0xa000
diff --git a/configs/imx28_xea_sb_defconfig b/configs/imx28_xea_sb_defconfig
index 39e1d1c..c7751b5 100644
--- a/configs/imx28_xea_sb_defconfig
+++ b/configs/imx28_xea_sb_defconfig
@@ -10,8 +10,8 @@
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="imx28-xea"
-CONFIG_SPL_TEXT_BASE=0x1000
 CONFIG_TARGET_XEA=y
+CONFIG_SPL_TEXT_BASE=0x1000
 CONFIG_SYS_LOAD_ADDR=0x42000000
 CONFIG_SF_DEFAULT_BUS=2
 CONFIG_SPL=y
diff --git a/configs/imx8mm-cl-iot-gate-optee_defconfig b/configs/imx8mm-cl-iot-gate-optee_defconfig
index 7ae8d54..722a596 100644
--- a/configs/imx8mm-cl-iot-gate-optee_defconfig
+++ b/configs/imx8mm-cl-iot-gate-optee_defconfig
@@ -8,7 +8,6 @@
 CONFIG_ENV_OFFSET=0x4400
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx8mm-cl-iot-gate-optee"
-CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_TARGET_IMX8MM_CL_IOT_GATE_OPTEE=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_MONITOR_LEN=524288
@@ -16,6 +15,7 @@
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x920000
+CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x910000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mm-cl-iot-gate_defconfig b/configs/imx8mm-cl-iot-gate_defconfig
index ca0335b..1aa42ef 100644
--- a/configs/imx8mm-cl-iot-gate_defconfig
+++ b/configs/imx8mm-cl-iot-gate_defconfig
@@ -9,7 +9,6 @@
 CONFIG_ENV_OFFSET=0x200000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx8mm-cl-iot-gate"
-CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_TARGET_IMX8MM_CL_IOT_GATE=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_MONITOR_LEN=524288
@@ -17,6 +16,7 @@
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x920000
+CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x910000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
index 14f8bfe..db44145 100644
--- a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
+++ b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
@@ -9,13 +9,13 @@
 CONFIG_ENV_OFFSET=0x400000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx8mm-icore-mx8mm-ctouch2"
-CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_TARGET_IMX8MM_ICORE_MX8MM=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x920000
+CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x910000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
index d0d46d2..94b4a95 100644
--- a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
+++ b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
@@ -9,13 +9,13 @@
 CONFIG_ENV_OFFSET=0x400000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx8mm-icore-mx8mm-edimm2.2"
-CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_TARGET_IMX8MM_ICORE_MX8MM=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x920000
+CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x910000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mm-mx8menlo_defconfig b/configs/imx8mm-mx8menlo_defconfig
index d4ceca7..ae9595e 100644
--- a/configs/imx8mm-mx8menlo_defconfig
+++ b/configs/imx8mm-mx8menlo_defconfig
@@ -9,7 +9,6 @@
 CONFIG_ENV_OFFSET=0xFFFFDE00
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx8mm-mx8menlo"
-CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_TARGET_IMX8MM_MX8MENLO=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_MONITOR_LEN=524288
@@ -19,6 +18,7 @@
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
 CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090
 CONFIG_SPL_STACK=0x920000
+CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x910000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
@@ -97,8 +97,8 @@
 CONFIG_USE_ETHPRIME=y
 CONFIG_ETHPRIME="eth0"
 CONFIG_VERSION_VARIABLE=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_IP_DEFRAG=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_TFTP_BLOCKSIZE=4096
 CONFIG_SPL_DM=y
 CONFIG_BOOTCOUNT_LIMIT=y
diff --git a/configs/imx8mm-phygate-tauri-l_defconfig b/configs/imx8mm-phygate-tauri-l_defconfig
index c69fe50..18fffa7 100644
--- a/configs/imx8mm-phygate-tauri-l_defconfig
+++ b/configs/imx8mm-phygate-tauri-l_defconfig
@@ -9,13 +9,13 @@
 CONFIG_ENV_OFFSET=0x3C0000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-phygate-tauri-l"
-CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_TARGET_PHYCORE_IMX8MM=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x920000
+CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x910000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig
index 3411d2b..56e1889 100644
--- a/configs/imx8mm_beacon_defconfig
+++ b/configs/imx8mm_beacon_defconfig
@@ -11,13 +11,13 @@
 CONFIG_ENV_OFFSET=0xFFFFDE00
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-beacon-kit"
-CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_TARGET_IMX8MM_BEACON=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x920000
+CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x910000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mm_beacon_fspi_defconfig b/configs/imx8mm_beacon_fspi_defconfig
index 44af74b..2a8bd2d 100644
--- a/configs/imx8mm_beacon_fspi_defconfig
+++ b/configs/imx8mm_beacon_fspi_defconfig
@@ -12,12 +12,12 @@
 CONFIG_IMX_CONFIG="board/freescale/imx8mm_evk/imximage-8mm-lpddr4-fspi.cfg"
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-beacon-kit"
-CONFIG_SPL_TEXT_BASE=0x7E2000
 CONFIG_TARGET_IMX8MM_BEACON=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x920000
+CONFIG_SPL_TEXT_BASE=0x7E2000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x910000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig b/configs/imx8mm_data_modul_edm_sbc_defconfig
index 77bdefd..105fbfb 100644
--- a/configs/imx8mm_data_modul_edm_sbc_defconfig
+++ b/configs/imx8mm_data_modul_edm_sbc_defconfig
@@ -12,7 +12,6 @@
 CONFIG_IMX_CONFIG="board/data_modul/imx8mm_edm_sbc/imximage.cfg"
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx8mm-data-modul-edm-sbc"
-CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_TARGET_IMX8MM_DATA_MODUL_EDM_SBC=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
@@ -23,6 +22,7 @@
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
 CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090
 CONFIG_SPL_STACK=0x920000
+CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x910000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
@@ -36,7 +36,6 @@
 CONFIG_FIT=y
 CONFIG_FIT_EXTERNAL_OFFSET=0x3000
 CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_USE_BOOTARGS=y
@@ -107,12 +106,12 @@
 CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_CAT=y
 CONFIG_CMD_XXD=y
-CONFIG_CMD_DHCP=y
 CONFIG_CMD_DHCP6=y
 CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_WGET=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_WGET=y
 CONFIG_CMD_PXE=y
 CONFIG_CMD_BOOTCOUNT=y
 CONFIG_CMD_CACHE=y
@@ -146,12 +145,12 @@
 CONFIG_SYS_MMC_ENV_PART=1
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_VERSION_VARIABLE=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
 CONFIG_IP_DEFRAG=y
 CONFIG_TFTP_TSIZE=y
 CONFIG_PROT_TCP_SACK=y
 CONFIG_IPV6=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig
index 1a15292..9075710 100644
--- a/configs/imx8mm_evk_defconfig
+++ b/configs/imx8mm_evk_defconfig
@@ -9,13 +9,13 @@
 CONFIG_ENV_OFFSET=0x400000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-evk"
-CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_TARGET_IMX8MM_EVK=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x920000
+CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x910000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mm_evk_fspi_defconfig b/configs/imx8mm_evk_fspi_defconfig
index 4898384..fb4a442 100644
--- a/configs/imx8mm_evk_fspi_defconfig
+++ b/configs/imx8mm_evk_fspi_defconfig
@@ -12,13 +12,13 @@
 CONFIG_IMX_CONFIG="board/freescale/imx8mm_evk/imximage-8mm-lpddr4-fspi.cfg"
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-evk"
-CONFIG_SPL_TEXT_BASE=0x7E2000
 CONFIG_TARGET_IMX8MM_EVK=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x920000
+CONFIG_SPL_TEXT_BASE=0x7E2000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x910000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mm_phg_defconfig b/configs/imx8mm_phg_defconfig
index f0867e6..384f2cc 100644
--- a/configs/imx8mm_phg_defconfig
+++ b/configs/imx8mm_phg_defconfig
@@ -9,13 +9,13 @@
 CONFIG_ENV_OFFSET=0x200000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx8mm-phg"
-CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_TARGET_IMX8MM_PHG=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x920000
+CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x910000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig
index 4a4e554..da248e4 100644
--- a/configs/imx8mm_venice_defconfig
+++ b/configs/imx8mm_venice_defconfig
@@ -9,7 +9,6 @@
 CONFIG_ENV_OFFSET=0x3f0000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-venice-gw71xx-0x"
-CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_TARGET_IMX8MM_VENICE=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
@@ -18,6 +17,7 @@
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x920000
+CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x910000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
@@ -87,11 +87,11 @@
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_USE_ETHPRIME=y
 CONFIG_ETHPRIME="eth0"
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_IP_DEFRAG=y
-CONFIG_TFTP_BLOCKSIZE=4096
 CONFIG_PROT_TCP_SACK=y
 CONFIG_IPV6=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TFTP_BLOCKSIZE=4096
 CONFIG_SPL_DM=y
 CONFIG_SPL_CLK_COMPOSITE_CCF=y
 CONFIG_CLK_COMPOSITE_CCF=y
diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig
index 23bfaf2..b72fa93 100644
--- a/configs/imx8mn_beacon_2g_defconfig
+++ b/configs/imx8mn_beacon_2g_defconfig
@@ -12,7 +12,6 @@
 CONFIG_ENV_OFFSET=0xFFFFDE00
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mn-beacon-kit"
-CONFIG_SPL_TEXT_BASE=0x912000
 CONFIG_TARGET_IMX8MN_BEACON=y
 CONFIG_IMX8MN_BEACON_2GB_LPDDR=y
 CONFIG_OF_LIBFDT_OVERLAY=y
@@ -21,6 +20,7 @@
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x980000
+CONFIG_SPL_TEXT_BASE=0x912000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x950000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig
index aa83412..69af7ce 100644
--- a/configs/imx8mn_beacon_defconfig
+++ b/configs/imx8mn_beacon_defconfig
@@ -12,7 +12,6 @@
 CONFIG_ENV_OFFSET=0xFFFFDE00
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mn-beacon-kit"
-CONFIG_SPL_TEXT_BASE=0x912000
 CONFIG_TARGET_IMX8MN_BEACON=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
@@ -20,6 +19,7 @@
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x980000
+CONFIG_SPL_TEXT_BASE=0x912000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x950000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mn_beacon_fspi_defconfig b/configs/imx8mn_beacon_fspi_defconfig
index 3a92f0b..b90cb90 100644
--- a/configs/imx8mn_beacon_fspi_defconfig
+++ b/configs/imx8mn_beacon_fspi_defconfig
@@ -12,7 +12,6 @@
 CONFIG_ENV_OFFSET=0xFFFFDE00
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mn-beacon-kit"
-CONFIG_SPL_TEXT_BASE=0x912000
 CONFIG_TARGET_IMX8MN_BEACON=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
@@ -20,6 +19,7 @@
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x980000
+CONFIG_SPL_TEXT_BASE=0x912000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x950000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mn_bsh_smm_s2_defconfig b/configs/imx8mn_bsh_smm_s2_defconfig
index 364f25f..f4a0474 100644
--- a/configs/imx8mn_bsh_smm_s2_defconfig
+++ b/configs/imx8mn_bsh_smm_s2_defconfig
@@ -9,7 +9,6 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mn-bsh-smm-s2"
-CONFIG_SPL_TEXT_BASE=0x912000
 CONFIG_TARGET_IMX8MN_BSH_SMM_S2=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_MONITOR_LEN=524288
@@ -17,6 +16,7 @@
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x980000
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_TEXT_BASE=0x912000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x950000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mn_bsh_smm_s2pro_defconfig b/configs/imx8mn_bsh_smm_s2pro_defconfig
index e8f3d40..9ca96a7 100644
--- a/configs/imx8mn_bsh_smm_s2pro_defconfig
+++ b/configs/imx8mn_bsh_smm_s2pro_defconfig
@@ -9,7 +9,6 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mn-bsh-smm-s2pro"
-CONFIG_SPL_TEXT_BASE=0x912000
 CONFIG_TARGET_IMX8MN_BSH_SMM_S2PRO=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_MONITOR_LEN=524288
@@ -18,6 +17,7 @@
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x980000
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_TEXT_BASE=0x912000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x950000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig
index b20d0b0..3eb58d6 100644
--- a/configs/imx8mn_ddr4_evk_defconfig
+++ b/configs/imx8mn_ddr4_evk_defconfig
@@ -9,13 +9,13 @@
 CONFIG_ENV_OFFSET=0x400000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mn-ddr4-evk"
-CONFIG_SPL_TEXT_BASE=0x912000
 CONFIG_TARGET_IMX8MN_DDR4_EVK=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x980000
+CONFIG_SPL_TEXT_BASE=0x912000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x950000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mn_evk_defconfig b/configs/imx8mn_evk_defconfig
index ee571c7..43860fe 100644
--- a/configs/imx8mn_evk_defconfig
+++ b/configs/imx8mn_evk_defconfig
@@ -9,13 +9,13 @@
 CONFIG_ENV_OFFSET=0x400000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mn-evk"
-CONFIG_SPL_TEXT_BASE=0x912000
 CONFIG_TARGET_IMX8MN_EVK=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x980000
+CONFIG_SPL_TEXT_BASE=0x912000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x950000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig
index 1922f2d..9016c40 100644
--- a/configs/imx8mn_var_som_defconfig
+++ b/configs/imx8mn_var_som_defconfig
@@ -10,7 +10,6 @@
 CONFIG_ENV_OFFSET=0xFFFFDE00
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx8mn-var-som-symphony"
-CONFIG_SPL_TEXT_BASE=0x912000
 CONFIG_TARGET_IMX8MN_VAR_SOM=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_MONITOR_LEN=524288
@@ -19,6 +18,7 @@
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x980000
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_TEXT_BASE=0x912000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x950000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig
index b0a7f07..44af3e6 100644
--- a/configs/imx8mn_venice_defconfig
+++ b/configs/imx8mn_venice_defconfig
@@ -9,7 +9,6 @@
 CONFIG_ENV_OFFSET=0x3f0000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mn-venice-gw7902"
-CONFIG_SPL_TEXT_BASE=0x912000
 CONFIG_TARGET_IMX8MN_VENICE=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_MONITOR_LEN=524288
@@ -17,6 +16,7 @@
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x980000
+CONFIG_SPL_TEXT_BASE=0x912000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x950000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
@@ -86,11 +86,11 @@
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_USE_ETHPRIME=y
 CONFIG_ETHPRIME="eth0"
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_IP_DEFRAG=y
-CONFIG_TFTP_BLOCKSIZE=4096
 CONFIG_PROT_TCP_SACK=y
 CONFIG_IPV6=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TFTP_BLOCKSIZE=4096
 CONFIG_SPL_DM=y
 CONFIG_SPL_CLK_IMX8MN=y
 CONFIG_CLK_IMX8MN=y
diff --git a/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig b/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig
index 58c525d..d7d5df7 100644
--- a/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig
+++ b/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig
@@ -12,13 +12,13 @@
 CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx8mp-icore-mx8mp-edimm2.2"
-CONFIG_SPL_TEXT_BASE=0x920000
 CONFIG_TARGET_IMX8MP_ICORE_MX8MP=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x960000
+CONFIG_SPL_TEXT_BASE=0x920000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x98fc00
 CONFIG_SPL_BSS_MAX_SIZE=0x400
diff --git a/configs/imx8mp_beacon_defconfig b/configs/imx8mp_beacon_defconfig
index 2a54c76..f39e4f5 100644
--- a/configs/imx8mp_beacon_defconfig
+++ b/configs/imx8mp_beacon_defconfig
@@ -13,7 +13,6 @@
 CONFIG_ENV_OFFSET=0xFFFFDE00
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-beacon-kit"
-CONFIG_SPL_TEXT_BASE=0x920000
 CONFIG_TARGET_IMX8MP_BEACON=y
 CONFIG_DM_RESET=y
 CONFIG_SYS_MONITOR_LEN=524288
@@ -21,6 +20,7 @@
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x960000
+CONFIG_SPL_TEXT_BASE=0x920000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x98fc00
 CONFIG_SPL_BSS_MAX_SIZE=0x400
diff --git a/configs/imx8mp_data_modul_edm_sbc_defconfig b/configs/imx8mp_data_modul_edm_sbc_defconfig
index 7559c9d..f809d23 100644
--- a/configs/imx8mp_data_modul_edm_sbc_defconfig
+++ b/configs/imx8mp_data_modul_edm_sbc_defconfig
@@ -13,7 +13,6 @@
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="imx8mp-data-modul-edm-sbc"
-CONFIG_SPL_TEXT_BASE=0x920000
 CONFIG_TARGET_IMX8MP_DATA_MODUL_EDM_SBC=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
@@ -24,6 +23,7 @@
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
 CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090
 CONFIG_SPL_STACK=0x96fc00
+CONFIG_SPL_TEXT_BASE=0x920000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x96fc00
 CONFIG_SPL_BSS_MAX_SIZE=0x400
@@ -43,7 +43,6 @@
 CONFIG_FIT=y
 CONFIG_FIT_EXTERNAL_OFFSET=0x3000
 CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_USE_BOOTARGS=y
@@ -115,12 +114,12 @@
 CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_CAT=y
 CONFIG_CMD_XXD=y
-CONFIG_CMD_DHCP=y
 CONFIG_CMD_DHCP6=y
 CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_WGET=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_WGET=y
 CONFIG_CMD_PXE=y
 CONFIG_CMD_BOOTCOUNT=y
 CONFIG_CMD_CACHE=y
@@ -155,12 +154,12 @@
 CONFIG_SYS_MMC_ENV_PART=1
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_VERSION_VARIABLE=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
 CONFIG_IP_DEFRAG=y
 CONFIG_TFTP_TSIZE=y
 CONFIG_PROT_TCP_SACK=y
 CONFIG_IPV6=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
diff --git a/configs/imx8mp_debix_model_a_defconfig b/configs/imx8mp_debix_model_a_defconfig
index 9f75ab1..560ac12 100644
--- a/configs/imx8mp_debix_model_a_defconfig
+++ b/configs/imx8mp_debix_model_a_defconfig
@@ -9,13 +9,13 @@
 CONFIG_ENV_OFFSET=0x400000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-debix-model-a"
-CONFIG_SPL_TEXT_BASE=0x920000
 CONFIG_TARGET_IMX8MP_DEBIX_MODEL_A=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x960000
+CONFIG_SPL_TEXT_BASE=0x920000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x98fc00
 CONFIG_SPL_BSS_MAX_SIZE=0x400
diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig
index ecf75a0..5369f8b 100644
--- a/configs/imx8mp_evk_defconfig
+++ b/configs/imx8mp_evk_defconfig
@@ -9,13 +9,13 @@
 CONFIG_ENV_OFFSET=0x400000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-evk"
-CONFIG_SPL_TEXT_BASE=0x920000
 CONFIG_TARGET_IMX8MP_EVK=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x960000
+CONFIG_SPL_TEXT_BASE=0x920000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x98fc00
 CONFIG_SPL_BSS_MAX_SIZE=0x400
diff --git a/configs/imx8mp_navqp_defconfig b/configs/imx8mp_navqp_defconfig
index d4c10fe..6c7eb33 100644
--- a/configs/imx8mp_navqp_defconfig
+++ b/configs/imx8mp_navqp_defconfig
@@ -9,13 +9,13 @@
 CONFIG_ENV_OFFSET=0x400000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-navqp"
-CONFIG_SPL_TEXT_BASE=0x920000
 CONFIG_TARGET_IMX8MP_NAVQP=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x960000
+CONFIG_SPL_TEXT_BASE=0x920000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x98fc00
 CONFIG_SPL_BSS_MAX_SIZE=0x400
diff --git a/configs/imx8mp_rsb3720a1_4G_defconfig b/configs/imx8mp_rsb3720a1_4G_defconfig
index 898ed0e..bfcda77 100644
--- a/configs/imx8mp_rsb3720a1_4G_defconfig
+++ b/configs/imx8mp_rsb3720a1_4G_defconfig
@@ -14,7 +14,6 @@
 CONFIG_IMX_CONFIG="board/advantech/imx8mp_rsb3720a1/imximage-8mp-lpddr4.cfg"
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx8mp-rsb3720-a1"
-CONFIG_SPL_TEXT_BASE=0x920000
 CONFIG_TARGET_IMX8MP_RSB3720A1_4G=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_MONITOR_LEN=524288
@@ -22,6 +21,7 @@
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x960000
+CONFIG_SPL_TEXT_BASE=0x920000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x98fc00
 CONFIG_SPL_BSS_MAX_SIZE=0x400
diff --git a/configs/imx8mp_rsb3720a1_6G_defconfig b/configs/imx8mp_rsb3720a1_6G_defconfig
index 5eeb3fd..69e67bc 100644
--- a/configs/imx8mp_rsb3720a1_6G_defconfig
+++ b/configs/imx8mp_rsb3720a1_6G_defconfig
@@ -14,7 +14,6 @@
 CONFIG_IMX_CONFIG="board/advantech/imx8mp_rsb3720a1/imximage-8mp-lpddr4.cfg"
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx8mp-rsb3720-a1"
-CONFIG_SPL_TEXT_BASE=0x920000
 CONFIG_TARGET_IMX8MP_RSB3720A1_6G=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_MONITOR_LEN=524288
@@ -22,6 +21,7 @@
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x960000
+CONFIG_SPL_TEXT_BASE=0x920000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x98fc00
 CONFIG_SPL_BSS_MAX_SIZE=0x400
diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig
index 4b93e0c..bf296b1 100644
--- a/configs/imx8mp_venice_defconfig
+++ b/configs/imx8mp_venice_defconfig
@@ -9,7 +9,6 @@
 CONFIG_ENV_OFFSET=0x3f0000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-venice-gw71xx-2x"
-CONFIG_SPL_TEXT_BASE=0x920000
 CONFIG_TARGET_IMX8MP_VENICE=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
@@ -18,6 +17,7 @@
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x960000
+CONFIG_SPL_TEXT_BASE=0x920000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x98fc00
 CONFIG_SPL_BSS_MAX_SIZE=0x400
@@ -87,11 +87,11 @@
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_SYS_MMC_ENV_DEV=2
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_IP_DEFRAG=y
-CONFIG_TFTP_BLOCKSIZE=4096
 CONFIG_PROT_TCP_SACK=y
 CONFIG_IPV6=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TFTP_BLOCKSIZE=4096
 CONFIG_SPL_DM=y
 CONFIG_CLK_COMPOSITE_CCF=y
 CONFIG_CLK_IMX8MP=y
diff --git a/configs/imx8mq_cm_defconfig b/configs/imx8mq_cm_defconfig
index 8e0b7a7..7444b64 100644
--- a/configs/imx8mq_cm_defconfig
+++ b/configs/imx8mq_cm_defconfig
@@ -12,12 +12,12 @@
 CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx8mq-cm"
-CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_TARGET_IMX8MQ_CM=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK=0x187ff0
+CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x180000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig
index fd129da..a3a2333 100644
--- a/configs/imx8mq_evk_defconfig
+++ b/configs/imx8mq_evk_defconfig
@@ -12,7 +12,6 @@
 CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mq-evk"
-CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_TARGET_IMX8MQ_EVK=y
 CONFIG_DM_RESET=y
 CONFIG_SYS_MONITOR_LEN=524288
@@ -20,6 +19,7 @@
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x187ff0
+CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x180000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mq_phanbell_defconfig b/configs/imx8mq_phanbell_defconfig
index 487dae6..a372739 100644
--- a/configs/imx8mq_phanbell_defconfig
+++ b/configs/imx8mq_phanbell_defconfig
@@ -12,7 +12,6 @@
 CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx8mq-phanbell"
-CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_TARGET_IMX8MQ_PHANBELL=y
 CONFIG_DM_RESET=y
 CONFIG_SYS_MONITOR_LEN=524288
@@ -20,6 +19,7 @@
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x187ff0
+CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x180000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mq_reform2_defconfig b/configs/imx8mq_reform2_defconfig
index 475320b..1a6d6dc 100644
--- a/configs/imx8mq_reform2_defconfig
+++ b/configs/imx8mq_reform2_defconfig
@@ -12,7 +12,6 @@
 CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx8mq-mnt-reform2"
-CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_TARGET_IMX8MQ_REFORM2=y
 CONFIG_DM_RESET=y
 CONFIG_SYS_MONITOR_LEN=524288
@@ -20,6 +19,7 @@
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x187ff0
+CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x180000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig
index 779ae9a..9bbbc6a 100644
--- a/configs/imx8qm_mek_defconfig
+++ b/configs/imx8qm_mek_defconfig
@@ -13,12 +13,12 @@
 CONFIG_ENV_OFFSET=0x400000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek"
-CONFIG_SPL_TEXT_BASE=0x100000
 CONFIG_TARGET_IMX8QM_MEK=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x13e000
+CONFIG_SPL_TEXT_BASE=0x100000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x128000
 CONFIG_SPL_BSS_MAX_SIZE=0x1000
diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig
index 539debc..dfb288b 100644
--- a/configs/imx8qxp_mek_defconfig
+++ b/configs/imx8qxp_mek_defconfig
@@ -13,12 +13,12 @@
 CONFIG_ENV_OFFSET=0x400000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek"
-CONFIG_SPL_TEXT_BASE=0x100000
 CONFIG_TARGET_IMX8QXP_MEK=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x13e000
+CONFIG_SPL_TEXT_BASE=0x100000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x128000
 CONFIG_SPL_BSS_MAX_SIZE=0x1000
diff --git a/configs/imx8ulp_evk_defconfig b/configs/imx8ulp_evk_defconfig
index 1e421d4..cccc315 100644
--- a/configs/imx8ulp_evk_defconfig
+++ b/configs/imx8ulp_evk_defconfig
@@ -11,12 +11,12 @@
 CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx8ulp/imximage.cfg"
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx8ulp-evk"
-CONFIG_SPL_TEXT_BASE=0x22020000
 CONFIG_TARGET_IMX8ULP_EVK=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x22050000
+CONFIG_SPL_TEXT_BASE=0x22020000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x22048000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx93-phyboard-segin_defconfig b/configs/imx93-phycore_defconfig
similarity index 97%
rename from configs/imx93-phyboard-segin_defconfig
rename to configs/imx93-phycore_defconfig
index 18a4087..cf98001 100644
--- a/configs/imx93-phyboard-segin_defconfig
+++ b/configs/imx93-phycore_defconfig
@@ -6,13 +6,13 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
+CONFIG_PHYTEC_SOM_DETECTION=y
 CONFIG_ENV_SOURCE_FILE="phycore_imx93"
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x700000
 CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg"
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx93-phyboard-segin"
-CONFIG_SPL_TEXT_BASE=0x2049A000
 CONFIG_AHAB_BOOT=y
 CONFIG_TARGET_PHYCORE_IMX93=y
 CONFIG_OF_LIBFDT_OVERLAY=y
@@ -20,6 +20,7 @@
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x20519dd0
+CONFIG_SPL_TEXT_BASE=0x2049A000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x2051a000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
@@ -31,6 +32,7 @@
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x90000000
 CONFIG_REMAKE_ELF=y
+# CONFIG_ANDROID_BOOT_IMAGE is not set
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; else run netboot; fi; fi;"
diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig
index a4acb77..df62eec 100644
--- a/configs/imx93_11x11_evk_defconfig
+++ b/configs/imx93_11x11_evk_defconfig
@@ -11,12 +11,12 @@
 CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg"
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="freescale/imx93-11x11-evk"
-CONFIG_SPL_TEXT_BASE=0x2049A000
 CONFIG_TARGET_IMX93_11X11_EVK=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x20519dd0
+CONFIG_SPL_TEXT_BASE=0x2049A000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x2051a000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx93_9x9_qsb_defconfig b/configs/imx93_9x9_qsb_defconfig
index 74460a7..582fe5a 100644
--- a/configs/imx93_9x9_qsb_defconfig
+++ b/configs/imx93_9x9_qsb_defconfig
@@ -13,13 +13,13 @@
 CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg"
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="freescale/imx93-9x9-qsb"
-CONFIG_SPL_TEXT_BASE=0x2049A000
 CONFIG_TARGET_IMX93_9X9_QSB=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x20519dd0
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x18000
+CONFIG_SPL_TEXT_BASE=0x2049A000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x2051a000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx93_9x9_qsb_inline_ecc_defconfig b/configs/imx93_9x9_qsb_inline_ecc_defconfig
index 4b39db4..c95145c 100644
--- a/configs/imx93_9x9_qsb_inline_ecc_defconfig
+++ b/configs/imx93_9x9_qsb_inline_ecc_defconfig
@@ -13,13 +13,13 @@
 CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg"
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="freescale/imx93-9x9-qsb"
-CONFIG_SPL_TEXT_BASE=0x2049A000
 CONFIG_TARGET_IMX93_9X9_QSB=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x20519dd0
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x18000
+CONFIG_SPL_TEXT_BASE=0x2049A000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x2051a000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx93_var_som_defconfig b/configs/imx93_var_som_defconfig
index cb102f2..96cd862 100644
--- a/configs/imx93_var_som_defconfig
+++ b/configs/imx93_var_som_defconfig
@@ -11,13 +11,13 @@
 CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg"
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx93-var-som-symphony"
-CONFIG_SPL_TEXT_BASE=0x2049A000
 CONFIG_AHAB_BOOT=y
 CONFIG_TARGET_IMX93_VAR_SOM=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x20519dd0
+CONFIG_SPL_TEXT_BASE=0x2049A000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x2051a000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imxrt1020-evk_defconfig b/configs/imxrt1020-evk_defconfig
index 58a3e92..b67dc39 100644
--- a/configs/imxrt1020-evk_defconfig
+++ b/configs/imxrt1020-evk_defconfig
@@ -12,10 +12,10 @@
 CONFIG_ENV_OFFSET=0x80000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imxrt1020-evk"
-CONFIG_SPL_TEXT_BASE=0x20209000
 CONFIG_TARGET_IMXRT1020_EVK=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0x20209000
 CONFIG_SYS_LOAD_ADDR=0x20209000
 CONFIG_SPL_SIZE_LIMIT=0x20000
 CONFIG_SPL=y
diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig
index 141303c..b488ff1 100644
--- a/configs/imxrt1050-evk_defconfig
+++ b/configs/imxrt1050-evk_defconfig
@@ -14,17 +14,16 @@
 CONFIG_ENV_OFFSET=0x80000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imxrt1050-evk"
-CONFIG_SPL_TEXT_BASE=0x20002000
 CONFIG_TARGET_IMXRT1050_EVK=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0x20002000
 CONFIG_SYS_LOAD_ADDR=0x20002000
 CONFIG_SPL_SIZE_LIMIT=0x20000
 CONFIG_SPL=y
 CONFIG_HAVE_SYS_UBOOT_START=y
 CONFIG_SYS_UBOOT_START=0x800023FD
 CONFIG_BOOTSTD_FULL=y
-CONFIG_BOOTSTD_DEFAULTS=y
 CONFIG_SD_BOOT=y
 CONFIG_SPI_BOOT=y
 CONFIG_SYS_CBSIZE=256
diff --git a/configs/imxrt1050-evk_fspi_defconfig b/configs/imxrt1050-evk_fspi_defconfig
index b77dbab..5d58e72 100644
--- a/configs/imxrt1050-evk_fspi_defconfig
+++ b/configs/imxrt1050-evk_fspi_defconfig
@@ -16,17 +16,16 @@
 CONFIG_IMX_CONFIG="board/freescale/imxrt1050-evk/imximage-nor.cfg"
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imxrt1050-evk"
-CONFIG_SPL_TEXT_BASE=0x20002000
 CONFIG_TARGET_IMXRT1050_EVK=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0x20002000
 CONFIG_SYS_LOAD_ADDR=0x20002000
 CONFIG_SPL_SIZE_LIMIT=0x20000
 CONFIG_SPL=y
 CONFIG_HAVE_SYS_UBOOT_START=y
 CONFIG_SYS_UBOOT_START=0x800023FD
 CONFIG_BOOTSTD_FULL=y
-CONFIG_BOOTSTD_DEFAULTS=y
 CONFIG_SD_BOOT=y
 CONFIG_SPI_BOOT=y
 CONFIG_SYS_CBSIZE=256
diff --git a/configs/imxrt1170-evk_defconfig b/configs/imxrt1170-evk_defconfig
index 487da27..32107fa 100644
--- a/configs/imxrt1170-evk_defconfig
+++ b/configs/imxrt1170-evk_defconfig
@@ -14,10 +14,10 @@
 CONFIG_ENV_OFFSET=0x80000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imxrt1170-evk"
-CONFIG_SPL_TEXT_BASE=0x202C0000
 CONFIG_TARGET_IMXRT1170_EVK=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0x202C0000
 CONFIG_SYS_LOAD_ADDR=0x202C0000
 CONFIG_SPL_SIZE_LIMIT=0x20000
 CONFIG_SPL=y
diff --git a/configs/inetspace_v2_defconfig b/configs/inetspace_v2_defconfig
index 97ec66f..cb09739 100644
--- a/configs/inetspace_v2_defconfig
+++ b/configs/inetspace_v2_defconfig
@@ -36,8 +36,8 @@
 CONFIG_CMD_SATA=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_SYS_DISABLE_AUTOLOAD=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_EXT2=y
diff --git a/configs/iot2050_defconfig b/configs/iot2050_defconfig
index 2624f0c..d158886 100644
--- a/configs/iot2050_defconfig
+++ b/configs/iot2050_defconfig
@@ -18,11 +18,11 @@
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am6528-iot2050-basic"
-CONFIG_SPL_TEXT_BASE=0x80080000
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_TEXT_BASE=0x80080000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x80a00000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig
index 03849b9..eb6203f 100644
--- a/configs/j7200_evm_a72_defconfig
+++ b/configs/j7200_evm_a72_defconfig
@@ -16,13 +16,13 @@
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="ti/k3-j7200-common-proc-board"
-CONFIG_SPL_TEXT_BASE=0x80080000
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_TEXT_BASE=0x80080000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x80a00000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig
index 1db9251..f036a6f 100644
--- a/configs/j7200_evm_r5_defconfig
+++ b/configs/j7200_evm_r5_defconfig
@@ -16,12 +16,12 @@
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="k3-j7200-r5-common-proc-board"
-CONFIG_SPL_TEXT_BASE=0x41c00000
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_TEXT_BASE=0x41c00000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x41cf5bfc
 CONFIG_SPL_BSS_MAX_SIZE=0xa000
diff --git a/configs/j721e_beagleboneai64_r5_defconfig b/configs/j721e_beagleboneai64_r5_defconfig
index 9662423..77e4496 100644
--- a/configs/j721e_beagleboneai64_r5_defconfig
+++ b/configs/j721e_beagleboneai64_r5_defconfig
@@ -13,12 +13,12 @@
 CONFIG_ENV_SIZE=0x20000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-r5-beagleboneai64"
-CONFIG_SPL_TEXT_BASE=0x41c00000
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_TEXT_BASE=0x41c00000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x41cf59f0
 CONFIG_SPL_BSS_MAX_SIZE=0xa000
diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig
index ad6dbbc..00546ae 100644
--- a/configs/j721e_evm_r5_defconfig
+++ b/configs/j721e_evm_r5_defconfig
@@ -16,12 +16,12 @@
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-r5-common-proc-board"
-CONFIG_SPL_TEXT_BASE=0x41c00000
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_TEXT_BASE=0x41c00000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x41cf59f0
 CONFIG_SPL_BSS_MAX_SIZE=0xa000
diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig
index d619ac8..2a0ccfb 100644
--- a/configs/j721s2_evm_a72_defconfig
+++ b/configs/j721s2_evm_a72_defconfig
@@ -15,13 +15,13 @@
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="ti/k3-j721s2-common-proc-board"
-CONFIG_SPL_TEXT_BASE=0x80080000
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_TEXT_BASE=0x80080000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x80a00000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig
index d647f7c..f4441d6 100644
--- a/configs/j721s2_evm_r5_defconfig
+++ b/configs/j721s2_evm_r5_defconfig
@@ -16,12 +16,12 @@
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="k3-j721s2-r5-common-proc-board"
-CONFIG_SPL_TEXT_BASE=0x41c00000
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_TEXT_BASE=0x41c00000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x41c76000
 CONFIG_SPL_BSS_MAX_SIZE=0xa000
diff --git a/configs/j722s_evm_a53_defconfig b/configs/j722s_evm_a53_defconfig
index 1fdfdb5..35329fb 100644
--- a/configs/j722s_evm_a53_defconfig
+++ b/configs/j722s_evm_a53_defconfig
@@ -14,12 +14,12 @@
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="ti/k3-j722s-evm"
-CONFIG_SPL_TEXT_BASE=0x80080000
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_TEXT_BASE=0x80080000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x80a00000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
diff --git a/configs/j722s_evm_r5_defconfig b/configs/j722s_evm_r5_defconfig
index e6a573d..a3c13fe 100644
--- a/configs/j722s_evm_r5_defconfig
+++ b/configs/j722s_evm_r5_defconfig
@@ -13,12 +13,12 @@
 CONFIG_ENV_OFFSET=0x680000
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="k3-j722s-r5-evm"
-CONFIG_SPL_TEXT_BASE=0x43c00000
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_TEXT_BASE=0x43c00000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x43c7b000
 CONFIG_SPL_BSS_MAX_SIZE=0x3000
diff --git a/configs/j784s4_evm_r5_defconfig b/configs/j784s4_evm_r5_defconfig
index 0b5441f..3f1f66d 100644
--- a/configs/j784s4_evm_r5_defconfig
+++ b/configs/j784s4_evm_r5_defconfig
@@ -16,12 +16,12 @@
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="k3-j784s4-r5-evm"
-CONFIG_SPL_TEXT_BASE=0x41c00000
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_TEXT_BASE=0x41c00000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x41c76000
 CONFIG_SPL_BSS_MAX_SIZE=0xa000
diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig
index c13edd8..b92590e 100644
--- a/configs/jetson-tk1_defconfig
+++ b/configs/jetson-tk1_defconfig
@@ -9,8 +9,8 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFE000
 CONFIG_DEFAULT_DEVICE_TREE="tegra124-jetson-tk1"
-CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SPL_STACK=0x800ffffc
+CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SYS_LOAD_ADDR=0x81000000
 CONFIG_TEGRA124=y
 CONFIG_TARGET_JETSON_TK1=y
diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig
index b87defb..c207309 100644
--- a/configs/k2e_evm_defconfig
+++ b/configs/k2e_evm_defconfig
@@ -19,9 +19,9 @@
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="ti/keystone/keystone-k2e-evm"
-CONFIG_SPL_TEXT_BASE=0xC100000
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK=0xc1223f4
+CONFIG_SPL_TEXT_BASE=0xC100000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0xc10fff8
 CONFIG_SPL_BSS_MAX_SIZE=0x8000
diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
index 740a436..c93e82a 100644
--- a/configs/k2g_evm_defconfig
+++ b/configs/k2g_evm_defconfig
@@ -18,9 +18,9 @@
 CONFIG_ENV_SIZE=0x40000
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="ti/keystone/keystone-k2g-evm"
-CONFIG_SPL_TEXT_BASE=0xC0A0000
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK=0xc0c23f4
+CONFIG_SPL_TEXT_BASE=0xC0A0000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0xc0afff8
 CONFIG_SPL_BSS_MAX_SIZE=0x8000
diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig
index 782cb1d..7ae7a3b 100644
--- a/configs/k2hk_evm_defconfig
+++ b/configs/k2hk_evm_defconfig
@@ -19,9 +19,9 @@
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="ti/keystone/keystone-k2hk-evm"
-CONFIG_SPL_TEXT_BASE=0xC200000
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK=0xc2223f4
+CONFIG_SPL_TEXT_BASE=0xC200000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0xc20fff8
 CONFIG_SPL_BSS_MAX_SIZE=0x8000
diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
index 3a87e48..9f08e9d 100644
--- a/configs/k2l_evm_defconfig
+++ b/configs/k2l_evm_defconfig
@@ -19,9 +19,9 @@
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="ti/keystone/keystone-k2l-evm"
-CONFIG_SPL_TEXT_BASE=0xC100000
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK=0xc1223f4
+CONFIG_SPL_TEXT_BASE=0xC100000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0xc10fff8
 CONFIG_SPL_BSS_MAX_SIZE=0x8000
diff --git a/configs/khadas-vim3_android_ab_defconfig b/configs/khadas-vim3_android_ab_defconfig
index de5357c..a078c5d 100644
--- a/configs/khadas-vim3_android_ab_defconfig
+++ b/configs/khadas-vim3_android_ab_defconfig
@@ -24,6 +24,12 @@
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTMETH_ANDROID=y
+# CONFIG_BOOTMETH_EXTLINUX is not set
+# CONFIG_BOOTMETH_EXTLINUX_PXE is not set
+# CONFIG_BOOTMETH_EFILOADER is not set
+# CONFIG_BOOTMETH_EFI_BOOTMGR is not set
+# CONFIG_BOOTMETH_VBE is not set
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_OF_BOARD_SETUP=y
 # CONFIG_DISPLAY_CPUINFO is not set
@@ -35,7 +41,6 @@
 CONFIG_CMD_ADTIMG=y
 CONFIG_CMD_ABOOTIMG=y
 # CONFIG_CMD_IMI is not set
-CONFIG_CMD_BCB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
diff --git a/configs/khadas-vim3_android_defconfig b/configs/khadas-vim3_android_defconfig
index a0d9c42..b77a44c 100644
--- a/configs/khadas-vim3_android_defconfig
+++ b/configs/khadas-vim3_android_defconfig
@@ -24,6 +24,12 @@
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTMETH_ANDROID=y
+# CONFIG_BOOTMETH_EXTLINUX is not set
+# CONFIG_BOOTMETH_EXTLINUX_PXE is not set
+# CONFIG_BOOTMETH_EFILOADER is not set
+# CONFIG_BOOTMETH_EFI_BOOTMGR is not set
+# CONFIG_BOOTMETH_VBE is not set
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_OF_BOARD_SETUP=y
 # CONFIG_DISPLAY_CPUINFO is not set
@@ -34,7 +40,6 @@
 CONFIG_CMD_ADTIMG=y
 CONFIG_CMD_ABOOTIMG=y
 # CONFIG_CMD_IMI is not set
-CONFIG_CMD_BCB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
diff --git a/configs/khadas-vim3l_android_ab_defconfig b/configs/khadas-vim3l_android_ab_defconfig
index 4d7b90f..43db610 100644
--- a/configs/khadas-vim3l_android_ab_defconfig
+++ b/configs/khadas-vim3l_android_ab_defconfig
@@ -24,6 +24,12 @@
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTMETH_ANDROID=y
+# CONFIG_BOOTMETH_EXTLINUX is not set
+# CONFIG_BOOTMETH_EXTLINUX_PXE is not set
+# CONFIG_BOOTMETH_EFILOADER is not set
+# CONFIG_BOOTMETH_EFI_BOOTMGR is not set
+# CONFIG_BOOTMETH_VBE is not set
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_OF_BOARD_SETUP=y
 # CONFIG_DISPLAY_CPUINFO is not set
@@ -35,7 +41,6 @@
 CONFIG_CMD_ADTIMG=y
 CONFIG_CMD_ABOOTIMG=y
 # CONFIG_CMD_IMI is not set
-CONFIG_CMD_BCB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
diff --git a/configs/khadas-vim3l_android_defconfig b/configs/khadas-vim3l_android_defconfig
index 4ec2726..32d57a5 100644
--- a/configs/khadas-vim3l_android_defconfig
+++ b/configs/khadas-vim3l_android_defconfig
@@ -24,6 +24,12 @@
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTMETH_ANDROID=y
+# CONFIG_BOOTMETH_EXTLINUX is not set
+# CONFIG_BOOTMETH_EXTLINUX_PXE is not set
+# CONFIG_BOOTMETH_EFILOADER is not set
+# CONFIG_BOOTMETH_EFI_BOOTMGR is not set
+# CONFIG_BOOTMETH_VBE is not set
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_OF_BOARD_SETUP=y
 # CONFIG_DISPLAY_CPUINFO is not set
@@ -34,7 +40,6 @@
 CONFIG_CMD_ADTIMG=y
 CONFIG_CMD_ABOOTIMG=y
 # CONFIG_CMD_IMI is not set
-CONFIG_CMD_BCB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
diff --git a/configs/kmcent2_defconfig b/configs/kmcent2_defconfig
index a50822e..4e37df2 100644
--- a/configs/kmcent2_defconfig
+++ b/configs/kmcent2_defconfig
@@ -42,8 +42,8 @@
 CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_SPI=y
 CONFIG_BOOTP_BOOTFILESIZE=y
-CONFIG_CMD_PING=y
 CONFIG_CMD_ETHSW=y
+CONFIG_CMD_PING=y
 CONFIG_CMD_CRAMFS=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig
index a9ed1ba..6b2fc2e 100644
--- a/configs/kmcoge5ne_defconfig
+++ b/configs/kmcoge5ne_defconfig
@@ -148,11 +148,10 @@
 CONFIG_SYS_LOADS_BAUD_CHANGE=y
 CONFIG_CMD_NAND=y
 # CONFIG_CMD_PINMUX is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
-CONFIG_CMD_JFFS2=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=boot,nand0=app"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);app:-(ubi1);"
diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig
index 1d3c757..55e87b0 100644
--- a/configs/kmeter1_defconfig
+++ b/configs/kmeter1_defconfig
@@ -127,11 +127,10 @@
 CONFIG_LOADS_ECHO=y
 CONFIG_SYS_LOADS_BAUD_CHANGE=y
 # CONFIG_CMD_PINMUX is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
-CONFIG_CMD_JFFS2=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=boot"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);"
diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig
index b036ede..df419b0 100644
--- a/configs/kmopti2_defconfig
+++ b/configs/kmopti2_defconfig
@@ -134,11 +134,10 @@
 CONFIG_LOADS_ECHO=y
 CONFIG_SYS_LOADS_BAUD_CHANGE=y
 # CONFIG_CMD_PINMUX is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
-CONFIG_CMD_JFFS2=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=boot"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);"
diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig
index a6741b4..1436860 100644
--- a/configs/kmsupx5_defconfig
+++ b/configs/kmsupx5_defconfig
@@ -119,11 +119,10 @@
 CONFIG_CMD_I2C=y
 CONFIG_LOADS_ECHO=y
 CONFIG_SYS_LOADS_BAUD_CHANGE=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
-CONFIG_CMD_JFFS2=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=boot"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);"
diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig
index c8bfc99..cce7a04 100644
--- a/configs/kmtepr2_defconfig
+++ b/configs/kmtepr2_defconfig
@@ -133,11 +133,10 @@
 CONFIG_CMD_I2C=y
 CONFIG_LOADS_ECHO=y
 CONFIG_SYS_LOADS_BAUD_CHANGE=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
-CONFIG_CMD_JFFS2=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=boot"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);"
diff --git a/configs/kontron-sl-mx8mm_defconfig b/configs/kontron-sl-mx8mm_defconfig
index baefb27..f2d5bc1 100644
--- a/configs/kontron-sl-mx8mm_defconfig
+++ b/configs/kontron-sl-mx8mm_defconfig
@@ -13,13 +13,13 @@
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="imx8mm-kontron-bl"
-CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_TARGET_KONTRON_MX8MM=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
 CONFIG_SPL_STACK=0x91fff0
+CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x910000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/kontron_pitx_imx8m_defconfig b/configs/kontron_pitx_imx8m_defconfig
index f155c94..6e21870 100644
--- a/configs/kontron_pitx_imx8m_defconfig
+++ b/configs/kontron_pitx_imx8m_defconfig
@@ -12,7 +12,6 @@
 CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx8mq-kontron-pitx-imx8m"
-CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_TARGET_KONTRON_PITX_IMX8M=y
 CONFIG_DM_RESET=y
 CONFIG_SYS_MONITOR_LEN=524288
@@ -20,6 +19,7 @@
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x187ff0
+CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x180000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig
index 7073553..35894a1 100644
--- a/configs/kontron_sl28_defconfig
+++ b/configs/kontron_sl28_defconfig
@@ -12,13 +12,13 @@
 CONFIG_ENV_OFFSET=0x3e0000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="freescale/fsl-ls1028a-kontron-sl28"
-CONFIG_SPL_TEXT_BASE=0x18010000
 CONFIG_SYS_FSL_SDHC_CLK_DIV=1
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_MONITOR_LEN=1048576
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK=0x18009ff0
+CONFIG_SPL_TEXT_BASE=0x18010000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x80100000
 CONFIG_SPL_BSS_MAX_SIZE=0x100000
diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig
index 6a402ac..dd25fd6 100644
--- a/configs/kylin-rk3036_defconfig
+++ b/configs/kylin-rk3036_defconfig
@@ -13,11 +13,11 @@
 CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk"
-CONFIG_SPL_TEXT_BASE=0x10081000
 CONFIG_ROCKCHIP_RK3036=y
 CONFIG_TARGET_KYLIN_RK3036=y
 CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_SPL_STACK=0x10081fff
+CONFIG_SPL_TEXT_BASE=0x10081000
 CONFIG_SPL_STACK_R=y
 CONFIG_SYS_LOAD_ADDR=0x60800800
 CONFIG_DEBUG_UART_BASE=0x20068000
diff --git a/configs/librem5_defconfig b/configs/librem5_defconfig
index ad49889..f81e828 100644
--- a/configs/librem5_defconfig
+++ b/configs/librem5_defconfig
@@ -12,7 +12,6 @@
 CONFIG_SYS_I2C_MXC_I2C4=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx8mq-librem5-r4"
-CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_TARGET_LIBREM5=y
 CONFIG_DM_RESET=y
 CONFIG_SYS_MONITOR_LEN=524288
@@ -20,6 +19,7 @@
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x187ff0
+CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x180000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/libretech-ac_defconfig b/configs/libretech-ac_defconfig
index a20ddbc..1784163 100644
--- a/configs/libretech-ac_defconfig
+++ b/configs/libretech-ac_defconfig
@@ -1,7 +1,7 @@
 CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="libretech-ac"
 CONFIG_SYS_VENDOR="libre-computer"
 CONFIG_SYS_BOARD="aml-s805x-ac"
+CONFIG_SYS_CONFIG_NAME="libretech-ac"
 CONFIG_ARCH_MESON=y
 CONFIG_TEXT_BASE=0x01000000
 CONFIG_NR_DRAM_BANKS=1
@@ -21,6 +21,8 @@
 CONFIG_IDENT_STRING=" libretech-ac"
 CONFIG_DEBUG_UART=y
 CONFIG_REMAKE_ELF=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
@@ -33,9 +35,9 @@
 CONFIG_SYS_MAXARGS=32
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_IMI is not set
+CONFIG_CMD_NVEDIT_EFI=y
 CONFIG_CMD_ADC=y
 CONFIG_CMD_DFU=y
-CONFIG_CMD_NVEDIT_EFI=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_MMC=y
@@ -43,8 +45,8 @@
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_EFIDEBUG=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_EFIDEBUG=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
@@ -52,7 +54,6 @@
 CONFIG_SARADC_MESON=y
 CONFIG_DFU_RAM=y
 CONFIG_DFU_SF=y
-CONFIG_SET_DFU_ALT_INFO=y
 CONFIG_MMC_MESON_GX=y
 CONFIG_MTD=y
 CONFIG_DM_MTD=y
@@ -102,5 +103,3 @@
 CONFIG_BMP_16BPP=y
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y
-CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
-CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig
index 46a2531..f195d07 100644
--- a/configs/ls1021aiot_sdcard_defconfig
+++ b/configs/ls1021aiot_sdcard_defconfig
@@ -13,11 +13,11 @@
 CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart"
-CONFIG_SPL_TEXT_BASE=0x10000000
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK=0x1001d000
+CONFIG_SPL_TEXT_BASE=0x10000000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x80100000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig
index e47b5da..97d0122 100644
--- a/configs/ls1021aqds_nand_defconfig
+++ b/configs/ls1021aqds_nand_defconfig
@@ -15,11 +15,11 @@
 CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
-CONFIG_SPL_TEXT_BASE=0x10000000
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x1001d000
+CONFIG_SPL_TEXT_BASE=0x10000000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x80100000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig
index 54c4bd2..96314d5 100644
--- a/configs/ls1021aqds_sdcard_ifc_defconfig
+++ b/configs/ls1021aqds_sdcard_ifc_defconfig
@@ -15,12 +15,12 @@
 CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
-CONFIG_SPL_TEXT_BASE=0x10000000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x1001d000
+CONFIG_SPL_TEXT_BASE=0x10000000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x80100000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig
index 9dbd83a..e466c3d 100644
--- a/configs/ls1021aqds_sdcard_qspi_defconfig
+++ b/configs/ls1021aqds_sdcard_qspi_defconfig
@@ -15,12 +15,12 @@
 CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
-CONFIG_SPL_TEXT_BASE=0x10000000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x1001d000
+CONFIG_SPL_TEXT_BASE=0x10000000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x80100000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig
index a42122a..86ee531 100644
--- a/configs/ls1021atsn_sdcard_defconfig
+++ b/configs/ls1021atsn_sdcard_defconfig
@@ -13,11 +13,11 @@
 CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-tsn"
-CONFIG_SPL_TEXT_BASE=0x10000000
 CONFIG_SYS_MONITOR_LEN=1048576
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK=0x1001d000
+CONFIG_SPL_TEXT_BASE=0x10000000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x80100000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
index 021c2b1..7dc3241 100644
--- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
@@ -14,12 +14,12 @@
 CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
-CONFIG_SPL_TEXT_BASE=0x10000000
 CONFIG_SYS_MONITOR_LEN=1064960
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x1001d000
+CONFIG_SPL_TEXT_BASE=0x10000000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x80100000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig
index 4924a6a..d621262 100644
--- a/configs/ls1021atwr_sdcard_ifc_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_defconfig
@@ -15,11 +15,11 @@
 CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
-CONFIG_SPL_TEXT_BASE=0x10000000
 CONFIG_SYS_MONITOR_LEN=1048576
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK=0x1001d000
+CONFIG_SPL_TEXT_BASE=0x10000000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x80100000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig
index 146ebf4..53f487d 100644
--- a/configs/ls1021atwr_sdcard_qspi_defconfig
+++ b/configs/ls1021atwr_sdcard_qspi_defconfig
@@ -15,11 +15,11 @@
 CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
-CONFIG_SPL_TEXT_BASE=0x10000000
 CONFIG_SYS_MONITOR_LEN=1048576
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK=0x1001d000
+CONFIG_SPL_TEXT_BASE=0x10000000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x80100000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
index d9c2526..97eb7d9 100644
--- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
@@ -48,8 +48,8 @@
 CONFIG_CMD_CACHE=y
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SYS_RX_ETH_BUFFER=8
 CONFIG_SATA=y
 CONFIG_SCSI_AHCI=y
diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig
index fcf5695..cc53c17 100644
--- a/configs/ls1028aqds_tfa_defconfig
+++ b/configs/ls1028aqds_tfa_defconfig
@@ -53,8 +53,8 @@
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SYS_RX_ETH_BUFFER=8
 CONFIG_SATA=y
 CONFIG_SCSI_AHCI=y
diff --git a/configs/ls1028aqds_tfa_lpuart_defconfig b/configs/ls1028aqds_tfa_lpuart_defconfig
index 78ad887..8da7271 100644
--- a/configs/ls1028aqds_tfa_lpuart_defconfig
+++ b/configs/ls1028aqds_tfa_lpuart_defconfig
@@ -52,8 +52,8 @@
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SYS_RX_ETH_BUFFER=8
 CONFIG_SATA=y
 CONFIG_SCSI_AHCI=y
diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
index adcae63..3f71a37 100644
--- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
@@ -47,8 +47,8 @@
 CONFIG_CMD_CACHE=y
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SYS_RX_ETH_BUFFER=8
 CONFIG_SATA=y
 CONFIG_SCSI_AHCI=y
diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig
index 17230d0..09d5dee 100644
--- a/configs/ls1028ardb_tfa_defconfig
+++ b/configs/ls1028ardb_tfa_defconfig
@@ -52,8 +52,8 @@
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SYS_RX_ETH_BUFFER=8
 CONFIG_SATA=y
 CONFIG_SCSI_AHCI=y
diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig
index 0066414..755411e 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -13,11 +13,11 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xE0000
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
-CONFIG_SPL_TEXT_BASE=0x1800a000
 CONFIG_SYS_MONITOR_LEN=1048576
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x18009ff0
+CONFIG_SPL_TEXT_BASE=0x1800a000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x80100000
 CONFIG_SPL_BSS_MAX_SIZE=0x100000
diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig
index cbc8d6a..1be0b4e 100644
--- a/configs/ls2080ardb_nand_defconfig
+++ b/configs/ls2080ardb_nand_defconfig
@@ -13,11 +13,11 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x200000
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
-CONFIG_SPL_TEXT_BASE=0x1800a000
 CONFIG_SYS_MONITOR_LEN=1048576
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x18009ff0
+CONFIG_SPL_TEXT_BASE=0x1800a000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x80100000
 CONFIG_SPL_BSS_MAX_SIZE=0x100000
diff --git a/configs/lschlv2_defconfig b/configs/lschlv2_defconfig
index 521a925..18de0ad 100644
--- a/configs/lschlv2_defconfig
+++ b/configs/lschlv2_defconfig
@@ -41,9 +41,9 @@
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
 CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SATA_MV=y
 CONFIG_SYS_SATA_MAX_DEVICE=1
 CONFIG_LBA48=y
diff --git a/configs/lsxhl_defconfig b/configs/lsxhl_defconfig
index 1872774..018d489 100644
--- a/configs/lsxhl_defconfig
+++ b/configs/lsxhl_defconfig
@@ -42,9 +42,9 @@
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
 CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SATA_MV=y
 CONFIG_SYS_SATA_MAX_DEVICE=1
 CONFIG_LBA48=y
diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig
index d7324ce..6130cd8 100644
--- a/configs/m53menlo_defconfig
+++ b/configs/m53menlo_defconfig
@@ -13,11 +13,11 @@
 CONFIG_TARGET_M53MENLO=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx53-m53menlo"
-CONFIG_SPL_TEXT_BASE=0x70008000
 CONFIG_SPL_SERIAL=y
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
 CONFIG_SYS_BOOTCOUNT_ADDR=0x53FA401C
 CONFIG_SPL_STACK=0x70004000
+CONFIG_SPL_TEXT_BASE=0x70008000
 CONFIG_SYS_LOAD_ADDR=0x70800000
 CONFIG_WATCHDOG_TIMEOUT_MSECS=8000
 CONFIG_SPL=y
diff --git a/configs/maxbcm_defconfig b/configs/maxbcm_defconfig
index ba3631f..bf9cbff 100644
--- a/configs/maxbcm_defconfig
+++ b/configs/maxbcm_defconfig
@@ -12,9 +12,9 @@
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="armada-xp-maxbcm"
-CONFIG_SPL_TEXT_BASE=0x40004030
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK=0x4002c000
+CONFIG_SPL_TEXT_BASE=0x40004030
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x40020000
 CONFIG_SPL_BSS_MAX_SIZE=0x4000
@@ -37,8 +37,8 @@
 CONFIG_CMD_I2C=y
 CONFIG_CMD_SPI=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
diff --git a/configs/mccmon6_nor_defconfig b/configs/mccmon6_nor_defconfig
index 9b60ce3..682ce30 100644
--- a/configs/mccmon6_nor_defconfig
+++ b/configs/mccmon6_nor_defconfig
@@ -34,7 +34,6 @@
 CONFIG_CMD_SPL=y
 CONFIG_CMD_SPL_NOR_OFS=0x09600000
 CONFIG_CMD_SPL_WRITE_SIZE=0x20000
-CONFIG_CMD_CLK=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
diff --git a/configs/mccmon6_sd_defconfig b/configs/mccmon6_sd_defconfig
index ecd3e31..665dc9e 100644
--- a/configs/mccmon6_sd_defconfig
+++ b/configs/mccmon6_sd_defconfig
@@ -32,7 +32,6 @@
 CONFIG_CMD_SPL=y
 CONFIG_CMD_SPL_NOR_OFS=0x09600000
 CONFIG_CMD_SPL_WRITE_SIZE=0x20000
-CONFIG_CMD_CLK=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
diff --git a/configs/medcom-wide_defconfig b/configs/medcom-wide_defconfig
index ec7318c..def3f98 100644
--- a/configs/medcom-wide_defconfig
+++ b/configs/medcom-wide_defconfig
@@ -6,8 +6,8 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x1FFE0000
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-medcom-wide"
-CONFIG_SPL_TEXT_BASE=0x00108000
 CONFIG_SPL_STACK=0xffffc
+CONFIG_SPL_TEXT_BASE=0x00108000
 CONFIG_SYS_LOAD_ADDR=0x1000000
 CONFIG_TEGRA20=y
 CONFIG_TARGET_MEDCOM_WIDE=y
diff --git a/configs/meesc_dataflash_defconfig b/configs/meesc_dataflash_defconfig
index 5d79565..5a040cd 100644
--- a/configs/meesc_dataflash_defconfig
+++ b/configs/meesc_dataflash_defconfig
@@ -24,8 +24,8 @@
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
diff --git a/configs/meesc_defconfig b/configs/meesc_defconfig
index bab87e6..1ce98bd 100644
--- a/configs/meesc_defconfig
+++ b/configs/meesc_defconfig
@@ -24,8 +24,8 @@
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_NAND=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_IS_IN_NAND=y
diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig
index ca78b32..2e618d8 100644
--- a/configs/microblaze-generic_defconfig
+++ b/configs/microblaze-generic_defconfig
@@ -47,15 +47,14 @@
 CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_CACHE=y
-CONFIG_CMD_JFFS2=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_USE_HOSTNAME=y
 CONFIG_HOSTNAME="microblaze-generic"
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
 CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_XILINX_GPIO=y
 CONFIG_DM_I2C=y
diff --git a/configs/microchip_mpfs_icicle_defconfig b/configs/microchip_mpfs_icicle_defconfig
index a35721a..5ea6cc3 100644
--- a/configs/microchip_mpfs_icicle_defconfig
+++ b/configs/microchip_mpfs_icicle_defconfig
@@ -5,7 +5,6 @@
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="microchip/mpfs-icicle-kit"
-CONFIG_OF_UPSTREAM=y
 CONFIG_SYS_LOAD_ADDR=0x80200000
 CONFIG_SYS_MEM_TOP_HIDE=0x400000
 CONFIG_TARGET_MICROCHIP_ICICLE=y
@@ -18,6 +17,7 @@
 CONFIG_DISPLAY_CPUINFO=y
 CONFIG_DISPLAY_BOARDINFO=y
 CONFIG_SYS_PROMPT="RISC-V # "
+CONFIG_OF_UPSTREAM=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_BOOTP_SEND_HOSTNAME=y
 CONFIG_DM_MTD=y
diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig
index 48577c5..1eddb58 100644
--- a/configs/minnowmax_defconfig
+++ b/configs/minnowmax_defconfig
@@ -40,8 +40,8 @@
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig
index 5595352..420a8bd 100644
--- a/configs/miqi-rk3288_defconfig
+++ b/configs/miqi-rk3288_defconfig
@@ -9,7 +9,6 @@
 CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-miqi"
-CONFIG_SPL_TEXT_BASE=0xff704000
 CONFIG_DM_RESET=y
 CONFIG_SYS_MONITOR_LEN=614400
 CONFIG_ROCKCHIP_RK3288=y
@@ -17,6 +16,7 @@
 CONFIG_TARGET_MIQI_RK3288=y
 CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_SPL_STACK=0xff718000
+CONFIG_SPL_TEXT_BASE=0xff704000
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
 CONFIG_SYS_BOOTM_LEN=0x4000000
diff --git a/configs/mk808_defconfig b/configs/mk808_defconfig
index dc9b12e..12a3705 100644
--- a/configs/mk808_defconfig
+++ b/configs/mk808_defconfig
@@ -15,7 +15,6 @@
 CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_SIZE=0x8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3066a-mk808"
-CONFIG_SPL_TEXT_BASE=0x60000000
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3066=y
 # CONFIG_ROCKCHIP_STIMER is not set
@@ -24,6 +23,7 @@
 CONFIG_TARGET_MK808=y
 CONFIG_SPL_STACK_R_ADDR=0x70000000
 CONFIG_SPL_STACK=0x1008ffff
+CONFIG_SPL_TEXT_BASE=0x60000000
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000
 CONFIG_SYS_LOAD_ADDR=0x70800800
diff --git a/configs/msc_sm2s_imx8mp_defconfig b/configs/msc_sm2s_imx8mp_defconfig
index fc84485..def90d4 100644
--- a/configs/msc_sm2s_imx8mp_defconfig
+++ b/configs/msc_sm2s_imx8mp_defconfig
@@ -9,13 +9,13 @@
 CONFIG_ENV_OFFSET=0x200000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx8mp-msc-sm2s"
-CONFIG_SPL_TEXT_BASE=0x920000
 CONFIG_TARGET_MSC_SM2S_IMX8MP=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x960000
+CONFIG_SPL_TEXT_BASE=0x920000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x0098FC00
 CONFIG_SPL_BSS_MAX_SIZE=0x400
diff --git a/configs/mscc_jr2_defconfig b/configs/mscc_jr2_defconfig
index bc9d1c2..0577b12 100644
--- a/configs/mscc_jr2_defconfig
+++ b/configs/mscc_jr2_defconfig
@@ -41,8 +41,8 @@
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_SPI=y
-CONFIG_CMD_DHCP=y
 # CONFIG_NET_TFTP_VARS is not set
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
diff --git a/configs/mscc_luton_defconfig b/configs/mscc_luton_defconfig
index a857616..dfd6bc0 100644
--- a/configs/mscc_luton_defconfig
+++ b/configs/mscc_luton_defconfig
@@ -43,8 +43,8 @@
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_SPI=y
-CONFIG_CMD_DHCP=y
 # CONFIG_NET_TFTP_VARS is not set
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_MTDPARTS=y
diff --git a/configs/mscc_ocelot_defconfig b/configs/mscc_ocelot_defconfig
index 855e966..23aff7e 100644
--- a/configs/mscc_ocelot_defconfig
+++ b/configs/mscc_ocelot_defconfig
@@ -41,8 +41,8 @@
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_MTD=y
 CONFIG_CMD_SPI=y
-CONFIG_CMD_DHCP=y
 # CONFIG_NET_TFTP_VARS is not set
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
diff --git a/configs/mscc_serval_defconfig b/configs/mscc_serval_defconfig
index f8a43c4..6ddcbe1 100644
--- a/configs/mscc_serval_defconfig
+++ b/configs/mscc_serval_defconfig
@@ -38,8 +38,8 @@
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_SPI=y
-CONFIG_CMD_DHCP=y
 # CONFIG_NET_TFTP_VARS is not set
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
diff --git a/configs/mscc_servalt_defconfig b/configs/mscc_servalt_defconfig
index a3328c6..629b555 100644
--- a/configs/mscc_servalt_defconfig
+++ b/configs/mscc_servalt_defconfig
@@ -37,8 +37,8 @@
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_SPI=y
-CONFIG_CMD_DHCP=y
 # CONFIG_NET_TFTP_VARS is not set
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
diff --git a/configs/mt7622_rfb_defconfig b/configs/mt7622_rfb_defconfig
index 47106ca..08a88e1 100644
--- a/configs/mt7622_rfb_defconfig
+++ b/configs/mt7622_rfb_defconfig
@@ -26,11 +26,11 @@
 CONFIG_CMD_SMC=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_USE_IPADDR=y
 CONFIG_IPADDR="192.168.1.1"
 CONFIG_USE_SERVERIP=y
 CONFIG_SERVERIP="192.168.1.3"
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CLK=y
diff --git a/configs/mt7623a_unielec_u7623_02_defconfig b/configs/mt7623a_unielec_u7623_02_defconfig
index 376167d..cf89f43 100644
--- a/configs/mt7623a_unielec_u7623_02_defconfig
+++ b/configs/mt7623a_unielec_u7623_02_defconfig
@@ -33,11 +33,11 @@
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_USE_IPADDR=y
 CONFIG_IPADDR="192.168.1.1"
 CONFIG_USE_SERVERIP=y
 CONFIG_SERVERIP="192.168.1.2"
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CLK=y
diff --git a/configs/mt7623n_bpir2_defconfig b/configs/mt7623n_bpir2_defconfig
index 23b750f..42da25e 100644
--- a/configs/mt7623n_bpir2_defconfig
+++ b/configs/mt7623n_bpir2_defconfig
@@ -35,11 +35,11 @@
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_USE_IPADDR=y
 CONFIG_IPADDR="192.168.1.1"
 CONFIG_USE_SERVERIP=y
 CONFIG_SERVERIP="192.168.1.2"
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CLK=y
diff --git a/configs/mt7629_rfb_defconfig b/configs/mt7629_rfb_defconfig
index ef148a9..abdf3d0 100644
--- a/configs/mt7629_rfb_defconfig
+++ b/configs/mt7629_rfb_defconfig
@@ -10,12 +10,12 @@
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41fffef0
 CONFIG_ENV_SIZE=0x1000
 CONFIG_DEFAULT_DEVICE_TREE="mt7629-rfb"
-CONFIG_SPL_TEXT_BASE=0x201000
 CONFIG_TARGET_MT7629=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK_R_ADDR=0x40800000
 CONFIG_SPL_STACK=0x106000
+CONFIG_SPL_TEXT_BASE=0x201000
 CONFIG_SPL_STACK_R=y
 CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_SYS_LOAD_ADDR=0x42007f1c
@@ -55,11 +55,11 @@
 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-parents"
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_USE_IPADDR=y
 CONFIG_IPADDR="192.168.1.1"
 CONFIG_USE_SERVERIP=y
 CONFIG_SERVERIP="192.168.1.2"
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SPL_REGMAP=y
 CONFIG_SPL_SYSCON=y
diff --git a/configs/mt7988_rfb_defconfig b/configs/mt7988_rfb_defconfig
index 96c7368..4d7454d 100644
--- a/configs/mt7988_rfb_defconfig
+++ b/configs/mt7988_rfb_defconfig
@@ -36,7 +36,6 @@
 CONFIG_EFI_PARTITION=y
 CONFIG_PARTITION_TYPE_GUID=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_USE_IPADDR=y
 CONFIG_IPADDR="192.168.1.1"
 CONFIG_USE_NETMASK=y
@@ -44,6 +43,7 @@
 CONFIG_USE_SERVERIP=y
 CONFIG_SERVERIP="192.168.1.2"
 CONFIG_PROT_TCP=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CLK=y
diff --git a/configs/mt7988_sd_rfb_defconfig b/configs/mt7988_sd_rfb_defconfig
index 7d0a262..9946998 100644
--- a/configs/mt7988_sd_rfb_defconfig
+++ b/configs/mt7988_sd_rfb_defconfig
@@ -36,7 +36,6 @@
 CONFIG_EFI_PARTITION=y
 CONFIG_PARTITION_TYPE_GUID=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_USE_IPADDR=y
 CONFIG_IPADDR="192.168.1.1"
 CONFIG_USE_NETMASK=y
@@ -44,6 +43,7 @@
 CONFIG_USE_SERVERIP=y
 CONFIG_SERVERIP="192.168.1.2"
 CONFIG_PROT_TCP=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CLK=y
diff --git a/configs/mx23_olinuxino_defconfig b/configs/mx23_olinuxino_defconfig
index 3016f75..6bb3ced 100644
--- a/configs/mx23_olinuxino_defconfig
+++ b/configs/mx23_olinuxino_defconfig
@@ -9,9 +9,9 @@
 CONFIG_ENV_OFFSET=0x40000
 CONFIG_IMX_CONFIG=""
 CONFIG_DEFAULT_DEVICE_TREE="imx23-olinuxino"
-CONFIG_SPL_TEXT_BASE=0x00001000
 CONFIG_TARGET_MX23_OLINUXINO=y
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0x00001000
 CONFIG_SYS_LOAD_ADDR=0x42000000
 CONFIG_SPL=y
 CONFIG_BOOTDELAY=3
diff --git a/configs/mx23evk_defconfig b/configs/mx23evk_defconfig
index 6152d93..02cbc4b 100644
--- a/configs/mx23evk_defconfig
+++ b/configs/mx23evk_defconfig
@@ -11,9 +11,9 @@
 CONFIG_IMX_CONFIG=""
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx23-evk"
-CONFIG_SPL_TEXT_BASE=0x00001000
 CONFIG_TARGET_MX23EVK=y
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0x00001000
 CONFIG_SYS_LOAD_ADDR=0x42000000
 CONFIG_SPL=y
 CONFIG_USE_BOOTCOMMAND=y
diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig
index 951d506..fdab7ef 100644
--- a/configs/mx28evk_defconfig
+++ b/configs/mx28evk_defconfig
@@ -11,9 +11,9 @@
 CONFIG_IMX_CONFIG=""
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx28-evk"
-CONFIG_SPL_TEXT_BASE=0x00001000
 CONFIG_TARGET_MX28EVK=y
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0x00001000
 CONFIG_SYS_LOAD_ADDR=0x42000000
 CONFIG_SPL=y
 CONFIG_FIT=y
diff --git a/configs/myir_mys_6ulx_defconfig b/configs/myir_mys_6ulx_defconfig
index b165dd4..baee86a 100644
--- a/configs/myir_mys_6ulx_defconfig
+++ b/configs/myir_mys_6ulx_defconfig
@@ -9,10 +9,10 @@
 CONFIG_MX6ULL=y
 CONFIG_TARGET_MYS_6ULX=y
 CONFIG_DEFAULT_DEVICE_TREE="imx6ull-myir-mys-6ulx-eval"
-CONFIG_SPL_TEXT_BASE=0x908000
 CONFIG_SYS_MONITOR_LEN=409600
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0x908000
 CONFIG_SPL=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x90000000
diff --git a/configs/n2350_defconfig b/configs/n2350_defconfig
index 7851bc4..9fb84c3 100644
--- a/configs/n2350_defconfig
+++ b/configs/n2350_defconfig
@@ -17,9 +17,9 @@
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_DEFAULT_DEVICE_TREE="armada-385-thecus-n2350"
-CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK=0x4002c000
+CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x40023000
 CONFIG_SPL_BSS_MAX_SIZE=0x4000
@@ -62,8 +62,8 @@
 CONFIG_VERSION_VARIABLE=y
 CONFIG_ARP_TIMEOUT=200
 CONFIG_NET_RETRY_COUNT=50
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_AHCI_GENERIC=y
 CONFIG_LBA48=y
diff --git a/configs/nanopi-r2c-plus-rk3328_defconfig b/configs/nanopi-r2c-plus-rk3328_defconfig
index f83df37..bef1e22 100644
--- a/configs/nanopi-r2c-plus-rk3328_defconfig
+++ b/configs/nanopi-r2c-plus-rk3328_defconfig
@@ -92,7 +92,6 @@
 CONFIG_SYSRESET=y
 # CONFIG_TPL_SYSRESET is not set
 CONFIG_USB=y
-CONFIG_DM_USB_GADGET=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
diff --git a/configs/nanopi-r2c-rk3328_defconfig b/configs/nanopi-r2c-rk3328_defconfig
index 1e65091..4d66a76 100644
--- a/configs/nanopi-r2c-rk3328_defconfig
+++ b/configs/nanopi-r2c-rk3328_defconfig
@@ -92,7 +92,6 @@
 CONFIG_SYSRESET=y
 # CONFIG_TPL_SYSRESET is not set
 CONFIG_USB=y
-CONFIG_DM_USB_GADGET=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
diff --git a/configs/nanopi-r2s-plus-rk3328_defconfig b/configs/nanopi-r2s-plus-rk3328_defconfig
index 6e6785f..3a75566 100644
--- a/configs/nanopi-r2s-plus-rk3328_defconfig
+++ b/configs/nanopi-r2s-plus-rk3328_defconfig
@@ -44,7 +44,6 @@
 CONFIG_TPL_OF_PLATDATA=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SYS_MMC_ENV_DEV=0
 CONFIG_TPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_REGMAP=y
@@ -92,7 +91,6 @@
 CONFIG_SYSRESET=y
 # CONFIG_TPL_SYSRESET is not set
 CONFIG_USB=y
-CONFIG_DM_USB_GADGET=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig
index 90073a1..2b9193d 100644
--- a/configs/nanopi-r2s-rk3328_defconfig
+++ b/configs/nanopi-r2s-rk3328_defconfig
@@ -92,7 +92,6 @@
 CONFIG_SYSRESET=y
 # CONFIG_TPL_SYSRESET is not set
 CONFIG_USB=y
-CONFIG_DM_USB_GADGET=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
diff --git a/configs/nas220_defconfig b/configs/nas220_defconfig
index bf47ec6..783879d 100644
--- a/configs/nas220_defconfig
+++ b/configs/nas220_defconfig
@@ -27,8 +27,8 @@
 CONFIG_CMD_NAND=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_SYS_DISABLE_AUTOLOAD=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_EXT2=y
diff --git a/configs/net2big_v2_defconfig b/configs/net2big_v2_defconfig
index 2f1ea40..67b883d 100644
--- a/configs/net2big_v2_defconfig
+++ b/configs/net2big_v2_defconfig
@@ -37,8 +37,8 @@
 CONFIG_CMD_SATA=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_SYS_DISABLE_AUTOLOAD=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_EXT2=y
diff --git a/configs/netspace_lite_v2_defconfig b/configs/netspace_lite_v2_defconfig
index 97b528c..7c0e42c 100644
--- a/configs/netspace_lite_v2_defconfig
+++ b/configs/netspace_lite_v2_defconfig
@@ -37,8 +37,8 @@
 CONFIG_CMD_SATA=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_SYS_DISABLE_AUTOLOAD=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_EXT2=y
diff --git a/configs/netspace_max_v2_defconfig b/configs/netspace_max_v2_defconfig
index ce9d8d9..65cd79f 100644
--- a/configs/netspace_max_v2_defconfig
+++ b/configs/netspace_max_v2_defconfig
@@ -37,8 +37,8 @@
 CONFIG_CMD_SATA=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_SYS_DISABLE_AUTOLOAD=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_EXT2=y
diff --git a/configs/netspace_mini_v2_defconfig b/configs/netspace_mini_v2_defconfig
index b467619..1f82c2c 100644
--- a/configs/netspace_mini_v2_defconfig
+++ b/configs/netspace_mini_v2_defconfig
@@ -36,8 +36,8 @@
 CONFIG_CMD_I2C=y
 CONFIG_CMD_SATA=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_SYS_DISABLE_AUTOLOAD=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_EXT2=y
diff --git a/configs/netspace_v2_defconfig b/configs/netspace_v2_defconfig
index 562654c..f900d0c 100644
--- a/configs/netspace_v2_defconfig
+++ b/configs/netspace_v2_defconfig
@@ -37,8 +37,8 @@
 CONFIG_CMD_SATA=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_SYS_DISABLE_AUTOLOAD=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_EXT2=y
diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig
index f4e998e..f671835 100644
--- a/configs/nsa310s_defconfig
+++ b/configs/nsa310s_defconfig
@@ -39,9 +39,9 @@
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
 CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SATA_MV=y
 CONFIG_SYS_SATA_MAX_DEVICE=1
 CONFIG_LBA48=y
diff --git a/configs/nsa325_defconfig b/configs/nsa325_defconfig
index 607810c..c4235ee 100644
--- a/configs/nsa325_defconfig
+++ b/configs/nsa325_defconfig
@@ -52,8 +52,8 @@
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_VERSION_VARIABLE=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SATA_MV=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_LBA48=y
diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig
index 60db3fa..9054ec5 100644
--- a/configs/nyan-big_defconfig
+++ b/configs/nyan-big_defconfig
@@ -8,8 +8,8 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFE000
 CONFIG_DEFAULT_DEVICE_TREE="tegra124-nyan-big"
-CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SPL_STACK=0x800ffffc
+CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SYS_LOAD_ADDR=0x82408000
 CONFIG_TEGRA124=y
 CONFIG_TARGET_NYAN_BIG=y
diff --git a/configs/octeontx2_95xx_defconfig b/configs/octeontx2_95xx_defconfig
index 7909a33..92592ad 100644
--- a/configs/octeontx2_95xx_defconfig
+++ b/configs/octeontx2_95xx_defconfig
@@ -22,6 +22,7 @@
 CONFIG_DEBUG_UART=y
 CONFIG_SYS_MEMTEST_START=0x04000000
 CONFIG_SYS_MEMTEST_END=0x040f0000
+# CONFIG_BOOTEFI_HELLO_COMPILE is not set
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_SUPPORT_RAW_INITRD=y
@@ -38,7 +39,6 @@
 CONFIG_BOARD_EARLY_INIT_R=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Marvell> "
-# CONFIG_BOOTEFI_HELLO_COMPILE is not set
 CONFIG_CMD_MD5SUM=y
 CONFIG_MD5SUM_VERIFY=y
 CONFIG_CMD_MX_CYCLIC=y
@@ -54,18 +54,18 @@
 CONFIG_CMD_PCI=y
 CONFIG_CMD_SF_TEST=y
 CONFIG_CMD_WDT=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_TFTPSRV=y
 CONFIG_CMD_RARP=y
 CONFIG_SYS_DISABLE_AUTOLOAD=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
 CONFIG_CMD_CDP=y
 CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
 CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
 CONFIG_CMD_PXE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT2=y
@@ -78,8 +78,8 @@
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_VERSION_VARIABLE=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_TFTP_TSIZE=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM_I2C=y
 CONFIG_MISC=y
 CONFIG_SYS_MMC_MAX_BLK_COUNT=8192
diff --git a/configs/octeontx2_96xx_defconfig b/configs/octeontx2_96xx_defconfig
index cac337c..f77d515 100644
--- a/configs/octeontx2_96xx_defconfig
+++ b/configs/octeontx2_96xx_defconfig
@@ -22,6 +22,7 @@
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+# CONFIG_BOOTEFI_HELLO_COMPILE is not set
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_SUPPORT_RAW_INITRD=y
@@ -38,7 +39,6 @@
 CONFIG_BOARD_EARLY_INIT_R=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Marvell> "
-# CONFIG_BOOTEFI_HELLO_COMPILE is not set
 CONFIG_CMD_MD5SUM=y
 CONFIG_MD5SUM_VERIFY=y
 CONFIG_CMD_MX_CYCLIC=y
@@ -55,18 +55,18 @@
 CONFIG_CMD_SF_TEST=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_WDT=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_TFTPSRV=y
 CONFIG_CMD_RARP=y
 CONFIG_SYS_DISABLE_AUTOLOAD=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
 CONFIG_CMD_CDP=y
 CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
 CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
 CONFIG_CMD_PXE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT2=y
@@ -79,8 +79,8 @@
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_VERSION_VARIABLE=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_TFTP_TSIZE=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SCSI_AHCI=y
 CONFIG_AHCI_PCI=y
 CONFIG_DM_I2C=y
diff --git a/configs/octeontx_81xx_defconfig b/configs/octeontx_81xx_defconfig
index c935c4e..19a52bc 100644
--- a/configs/octeontx_81xx_defconfig
+++ b/configs/octeontx_81xx_defconfig
@@ -23,6 +23,7 @@
 CONFIG_AHCI=y
 CONFIG_SYS_MEMTEST_START=0x2800000
 CONFIG_SYS_MEMTEST_END=0x28f0000
+# CONFIG_BOOTEFI_HELLO_COMPILE is not set
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_SUPPORT_RAW_INITRD=y
@@ -39,7 +40,6 @@
 CONFIG_BOARD_EARLY_INIT_R=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Marvell> "
-# CONFIG_BOOTEFI_HELLO_COMPILE is not set
 CONFIG_CMD_MD5SUM=y
 CONFIG_MD5SUM_VERIFY=y
 CONFIG_CMD_MX_CYCLIC=y
@@ -56,17 +56,17 @@
 CONFIG_CMD_SF_TEST=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_WDT=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_TFTPSRV=y
 CONFIG_CMD_RARP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
 CONFIG_CMD_CDP=y
 CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
 CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
 CONFIG_CMD_PXE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT2=y
@@ -79,8 +79,8 @@
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_VERSION_VARIABLE=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_TFTP_TSIZE=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SCSI_AHCI=y
 CONFIG_AHCI_PCI=y
 CONFIG_LBA48=y
diff --git a/configs/octeontx_83xx_defconfig b/configs/octeontx_83xx_defconfig
index b214339..498a8b9 100644
--- a/configs/octeontx_83xx_defconfig
+++ b/configs/octeontx_83xx_defconfig
@@ -21,6 +21,7 @@
 CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
+# CONFIG_BOOTEFI_HELLO_COMPILE is not set
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_SUPPORT_RAW_INITRD=y
@@ -37,7 +38,6 @@
 CONFIG_BOARD_EARLY_INIT_R=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Marvell> "
-# CONFIG_BOOTEFI_HELLO_COMPILE is not set
 CONFIG_CMD_MD5SUM=y
 CONFIG_MD5SUM_VERIFY=y
 CONFIG_CMD_MX_CYCLIC=y
@@ -54,17 +54,17 @@
 CONFIG_CMD_SF_TEST=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_WDT=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_TFTPSRV=y
 CONFIG_CMD_RARP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
 CONFIG_CMD_CDP=y
 CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
 CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
 CONFIG_CMD_PXE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
@@ -76,8 +76,8 @@
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_VERSION_VARIABLE=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_TFTP_TSIZE=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SCSI_AHCI=y
 CONFIG_AHCI_PCI=y
 CONFIG_LBA48=y
diff --git a/configs/odroid-m1s-rk3566_defconfig b/configs/odroid-m1s-rk3566_defconfig
index 21f4fcb..39e815a 100644
--- a/configs/odroid-m1s-rk3566_defconfig
+++ b/configs/odroid-m1s-rk3566_defconfig
@@ -6,9 +6,9 @@
 CONFIG_ROCKCHIP_RK3568=y
 CONFIG_SPL_SERIAL=y
 CONFIG_TARGET_ODROID_M1S_RK3566=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
 CONFIG_DEBUG_UART_BASE=0xFE660000
 CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_SYS_LOAD_ADDR=0xc00800
 CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
diff --git a/configs/odroid-m2-rk3588s_defconfig b/configs/odroid-m2-rk3588s_defconfig
index d612ef3..4c3fa85 100644
--- a/configs/odroid-m2-rk3588s_defconfig
+++ b/configs/odroid-m2-rk3588s_defconfig
@@ -6,9 +6,9 @@
 CONFIG_ROCKCHIP_RK3588=y
 CONFIG_SPL_SERIAL=y
 CONFIG_TARGET_ODROID_M2_RK3588S=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
 CONFIG_DEBUG_UART_BASE=0xFEB50000
 CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_SYS_LOAD_ADDR=0xc00800
 CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig
index 51ed353..b9ea355 100644
--- a/configs/omapl138_lcdk_defconfig
+++ b/configs/omapl138_lcdk_defconfig
@@ -19,10 +19,10 @@
 CONFIG_ENV_OFFSET=0x0
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="da850-lcdk"
-CONFIG_SPL_TEXT_BASE=0x80000000
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK=0x8001ff00
+CONFIG_SPL_TEXT_BASE=0x80000000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0xc0000000
 CONFIG_SYS_LOAD_ADDR=0xc0700000
diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig
index ef26332..f7ed9e4 100644
--- a/configs/opos6uldev_defconfig
+++ b/configs/opos6uldev_defconfig
@@ -55,13 +55,13 @@
 CONFIG_CMD_PART=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_DHCP=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_SYS_DISABLE_AUTOLOAD=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_DNS=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT2=y
@@ -77,9 +77,9 @@
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SYS_MMC_ENV_PART=1
 CONFIG_VERSION_VARIABLE=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_USE_ROOTPATH=y
 CONFIG_ROOTPATH="/tftpboot/opos6ul-root"
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_BOUNCE_BUFFER=y
diff --git a/configs/orangepi-r1-plus-lts-rk3328_defconfig b/configs/orangepi-r1-plus-lts-rk3328_defconfig
index 23d3baa..6d5d8b9 100644
--- a/configs/orangepi-r1-plus-lts-rk3328_defconfig
+++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig
@@ -102,7 +102,6 @@
 CONFIG_SYSRESET=y
 # CONFIG_TPL_SYSRESET is not set
 CONFIG_USB=y
-CONFIG_DM_USB_GADGET=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
diff --git a/configs/orangepi-r1-plus-rk3328_defconfig b/configs/orangepi-r1-plus-rk3328_defconfig
index faadfa8..b382f9b 100644
--- a/configs/orangepi-r1-plus-rk3328_defconfig
+++ b/configs/orangepi-r1-plus-rk3328_defconfig
@@ -102,7 +102,6 @@
 CONFIG_SYSRESET=y
 # CONFIG_TPL_SYSRESET is not set
 CONFIG_USB=y
-CONFIG_DM_USB_GADGET=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
diff --git a/configs/origen_defconfig b/configs/origen_defconfig
index c6cc17a..bb69c02 100644
--- a/configs/origen_defconfig
+++ b/configs/origen_defconfig
@@ -14,8 +14,8 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x4200
 CONFIG_DEFAULT_DEVICE_TREE="exynos4210-origen"
-CONFIG_SPL_TEXT_BASE=0x02021410
 CONFIG_SYS_MONITOR_LEN=262144
+CONFIG_SPL_TEXT_BASE=0x02021410
 CONFIG_SYS_LOAD_ADDR=0x43e00000
 CONFIG_SPL=y
 CONFIG_IDENT_STRING=" for ORIGEN"
diff --git a/configs/paz00_defconfig b/configs/paz00_defconfig
index 57b4332..e93fa1c 100644
--- a/configs/paz00_defconfig
+++ b/configs/paz00_defconfig
@@ -6,8 +6,8 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFE000
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-paz00"
-CONFIG_SPL_TEXT_BASE=0x00108000
 CONFIG_SPL_STACK=0xffffc
+CONFIG_SPL_TEXT_BASE=0x00108000
 CONFIG_SYS_LOAD_ADDR=0x1000000
 CONFIG_TEGRA20=y
 CONFIG_TARGET_PAZ00=y
diff --git a/configs/pcm052_defconfig b/configs/pcm052_defconfig
index 8986f0c..d0d558a 100644
--- a/configs/pcm052_defconfig
+++ b/configs/pcm052_defconfig
@@ -31,8 +31,8 @@
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_NAND_TRIMFFS=y
-CONFIG_CMD_DHCP=y
 CONFIG_SYS_DISABLE_AUTOLOAD=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
diff --git a/configs/phycore-am335x-r2-regor_defconfig b/configs/phycore-am335x-r2-regor_defconfig
index 819482a..b40fb61 100644
--- a/configs/phycore-am335x-r2-regor_defconfig
+++ b/configs/phycore-am335x-r2-regor_defconfig
@@ -43,8 +43,8 @@
 CONFIG_CMD_PART=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_DNS2=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_CMD_MTDPARTS=y
diff --git a/configs/phycore-am335x-r2-wega_defconfig b/configs/phycore-am335x-r2-wega_defconfig
index 0d5373b..aaf7ff8 100644
--- a/configs/phycore-am335x-r2-wega_defconfig
+++ b/configs/phycore-am335x-r2-wega_defconfig
@@ -43,8 +43,8 @@
 CONFIG_CMD_PART=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_DNS2=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_CMD_MTDPARTS=y
diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig
index 48a0c0b..c245804 100644
--- a/configs/phycore-imx8mm_defconfig
+++ b/configs/phycore-imx8mm_defconfig
@@ -10,14 +10,15 @@
 CONFIG_ENV_OFFSET=0x3C0000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-phyboard-polis-rdk"
-CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_TARGET_PHYCORE_IMX8MM=y
+CONFIG_PHYTEC_SOM_DETECTION=y
 CONFIG_DM_RESET=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x920000
+CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x910000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig
index 1240c7f..2398182 100644
--- a/configs/phycore-imx8mp_defconfig
+++ b/configs/phycore-imx8mp_defconfig
@@ -13,7 +13,6 @@
 CONFIG_SYS_I2C_MXC_I2C1=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-phyboard-pollux-rdk"
-CONFIG_SPL_TEXT_BASE=0x920000
 CONFIG_TARGET_PHYCORE_IMX8MP=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_MONITOR_LEN=524288
@@ -21,6 +20,7 @@
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x960000
+CONFIG_SPL_TEXT_BASE=0x920000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x98fc00
 CONFIG_SPL_BSS_MAX_SIZE=0x400
diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig
index c7d5b73..0f8e999 100644
--- a/configs/phycore-rk3288_defconfig
+++ b/configs/phycore-rk3288_defconfig
@@ -9,13 +9,13 @@
 CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3288-phycore-rdk"
-CONFIG_SPL_TEXT_BASE=0xff704000
 CONFIG_SYS_MONITOR_LEN=614400
 CONFIG_ROCKCHIP_RK3288=y
 CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
 CONFIG_TARGET_PHYCORE_RK3288=y
 CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_SPL_STACK=0xff718000
+CONFIG_SPL_TEXT_BASE=0xff704000
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
 CONFIG_SYS_BOOTM_LEN=0x4000000
diff --git a/configs/phycore_am62x_a53_defconfig b/configs/phycore_am62x_a53_defconfig
index dfff586..0b0cf17 100644
--- a/configs/phycore_am62x_a53_defconfig
+++ b/configs/phycore_am62x_a53_defconfig
@@ -16,12 +16,12 @@
 CONFIG_ENV_OFFSET=0x680000
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am625-phyboard-lyra-rdk"
-CONFIG_SPL_TEXT_BASE=0x80080000
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_TEXT_BASE=0x80080000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x80c80000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
@@ -72,6 +72,7 @@
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_MULTI_DTB_FIT=y
+CONFIG_OF_OVERLAY_LIST="ti/k3-am6xx-phycore-disable-spi-nor ti/k3-am6xx-phycore-disable-rtc ti/k3-am6xx-phycore-disable-eth-phy ti/k3-am6xx-phycore-qspi-nor"
 CONFIG_SPL_MULTI_DTB_FIT=y
 CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
 CONFIG_ENV_OVERWRITE=y
diff --git a/configs/phycore_am62x_r5_defconfig b/configs/phycore_am62x_r5_defconfig
index 3ffb269..a856e69 100644
--- a/configs/phycore_am62x_r5_defconfig
+++ b/configs/phycore_am62x_r5_defconfig
@@ -16,13 +16,13 @@
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="k3-am625-r5-phycore-som-2gb"
-CONFIG_SPL_TEXT_BASE=0x43c00000
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x7000
+CONFIG_SPL_TEXT_BASE=0x43c00000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x43c3b000
 CONFIG_SPL_BSS_MAX_SIZE=0x3000
diff --git a/configs/phycore_am64x_a53_defconfig b/configs/phycore_am64x_a53_defconfig
index 662fc70..ac9731d 100644
--- a/configs/phycore_am64x_a53_defconfig
+++ b/configs/phycore_am64x_a53_defconfig
@@ -10,6 +10,7 @@
 CONFIG_SOC_K3_AM642=y
 CONFIG_K3_ATF_LOAD_ADDR=0x701c0000
 CONFIG_TARGET_PHYCORE_AM64X_A53=y
+CONFIG_PHYTEC_SOM_DETECTION=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
 CONFIG_ENV_SIZE=0x20000
@@ -17,13 +18,13 @@
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am642-phyboard-electra-rdk"
-CONFIG_SPL_TEXT_BASE=0x80080000
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_TEXT_BASE=0x80080000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x80a00000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
@@ -77,6 +78,7 @@
 CONFIG_CMD_SMC=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_OVERLAY_LIST="ti/k3-am6xx-phycore-disable-spi-nor ti/k3-am6xx-phycore-disable-rtc ti/k3-am6xx-phycore-disable-eth-phy ti/k3-am6xx-phycore-qspi-nor"
 CONFIG_MULTI_DTB_FIT=y
 CONFIG_SPL_MULTI_DTB_FIT=y
 CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
diff --git a/configs/phycore_am64x_r5_defconfig b/configs/phycore_am64x_r5_defconfig
index 269efdf..2d9ff95 100644
--- a/configs/phycore_am64x_r5_defconfig
+++ b/configs/phycore_am64x_r5_defconfig
@@ -16,12 +16,12 @@
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="k3-am642-r5-phycore-som-2gb"
-CONFIG_SPL_TEXT_BASE=0x70000000
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_TEXT_BASE=0x70000000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x7019b800
 CONFIG_SPL_BSS_MAX_SIZE=0x4000
diff --git a/configs/phycore_pcl063_defconfig b/configs/phycore_pcl063_defconfig
index 2f6b158..126caf5 100644
--- a/configs/phycore_pcl063_defconfig
+++ b/configs/phycore_pcl063_defconfig
@@ -9,10 +9,10 @@
 CONFIG_MX6UL=y
 CONFIG_TARGET_PCL063=y
 CONFIG_DEFAULT_DEVICE_TREE="imx6ul-phytec-segin-ff-rdk-nand"
-CONFIG_SPL_TEXT_BASE=0x00909000
 CONFIG_SYS_MONITOR_LEN=409600
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0x00909000
 CONFIG_SPL=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x90000000
diff --git a/configs/phycore_pcl063_ull_defconfig b/configs/phycore_pcl063_ull_defconfig
index b42a410..547d59a 100644
--- a/configs/phycore_pcl063_ull_defconfig
+++ b/configs/phycore_pcl063_ull_defconfig
@@ -9,10 +9,10 @@
 CONFIG_MX6ULL=y
 CONFIG_TARGET_PCL063_ULL=y
 CONFIG_DEFAULT_DEVICE_TREE="imx6ull-phytec-segin-ff-rdk-emmc"
-CONFIG_SPL_TEXT_BASE=0x908000
 CONFIG_SYS_MONITOR_LEN=409600
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0x908000
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/pico-imx8mq_defconfig b/configs/pico-imx8mq_defconfig
index 2960440..e9ba2a6 100644
--- a/configs/pico-imx8mq_defconfig
+++ b/configs/pico-imx8mq_defconfig
@@ -12,7 +12,6 @@
 CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx8mq-pico-pi"
-CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_TARGET_PICO_IMX8MQ=y
 CONFIG_DM_RESET=y
 CONFIG_SYS_MONITOR_LEN=524288
@@ -20,6 +19,7 @@
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x187ff0
+CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x180000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/plutux_defconfig b/configs/plutux_defconfig
index 8c43d9d..1f2889e 100644
--- a/configs/plutux_defconfig
+++ b/configs/plutux_defconfig
@@ -6,8 +6,8 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x1FFE0000
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-plutux"
-CONFIG_SPL_TEXT_BASE=0x00108000
 CONFIG_SPL_STACK=0xffffc
+CONFIG_SPL_TEXT_BASE=0x00108000
 CONFIG_SYS_LOAD_ADDR=0x1000000
 CONFIG_TEGRA20=y
 CONFIG_TARGET_PLUTUX=y
diff --git a/configs/pm9263_defconfig b/configs/pm9263_defconfig
index 811801b..cc37567 100644
--- a/configs/pm9263_defconfig
+++ b/configs/pm9263_defconfig
@@ -30,8 +30,8 @@
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_NAND=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_JFFS2=y
diff --git a/configs/pm9g45_defconfig b/configs/pm9g45_defconfig
index 20aa351..fa8b538 100644
--- a/configs/pm9g45_defconfig
+++ b/configs/pm9g45_defconfig
@@ -37,8 +37,8 @@
 CONFIG_CMD_NAND=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
diff --git a/configs/pogo_e02_defconfig b/configs/pogo_e02_defconfig
index d81bf59..50103f3 100644
--- a/configs/pogo_e02_defconfig
+++ b/configs/pogo_e02_defconfig
@@ -42,9 +42,9 @@
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
 CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
+CONFIG_NET_RANDOM_ETHADDR=y
 # CONFIG_MMC is not set
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
diff --git a/configs/pogo_v4_defconfig b/configs/pogo_v4_defconfig
index 66cfaae..fb8036a 100644
--- a/configs/pogo_v4_defconfig
+++ b/configs/pogo_v4_defconfig
@@ -51,9 +51,9 @@
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_VERSION_VARIABLE=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
 CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SATA_MV=y
 CONFIG_SYS_SATA_MAX_DEVICE=1
 CONFIG_LBA48=y
diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig
index fe16850..1b2fb4a 100644
--- a/configs/popmetal-rk3288_defconfig
+++ b/configs/popmetal-rk3288_defconfig
@@ -9,13 +9,13 @@
 CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-popmetal"
-CONFIG_SPL_TEXT_BASE=0xff704000
 CONFIG_SYS_MONITOR_LEN=614400
 CONFIG_ROCKCHIP_RK3288=y
 CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
 CONFIG_TARGET_POPMETAL_RK3288=y
 CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_SPL_STACK=0xff718000
+CONFIG_SPL_TEXT_BASE=0xff704000
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
 CONFIG_SYS_BOOTM_LEN=0x4000000
diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig
index 1211c5c..162b1f1 100644
--- a/configs/pxm2_defconfig
+++ b/configs/pxm2_defconfig
@@ -59,8 +59,8 @@
 CONFIG_CMD_NAND=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_DNS2=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
diff --git a/configs/qc750_defconfig b/configs/qc750_defconfig
index 58a3c83..2485e64 100644
--- a/configs/qc750_defconfig
+++ b/configs/qc750_defconfig
@@ -9,8 +9,8 @@
 CONFIG_ENV_SIZE=0x3000
 CONFIG_ENV_OFFSET=0xFFFFD000
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-wexler-qc750"
-CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SPL_STACK=0x800ffffc
+CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SYS_LOAD_ADDR=0x82000000
 CONFIG_TEGRA30=y
 CONFIG_TARGET_QC750=y
diff --git a/configs/qcm6490_defconfig b/configs/qcm6490_defconfig
index 5ddc5ab..ba26924 100644
--- a/configs/qcm6490_defconfig
+++ b/configs/qcm6490_defconfig
@@ -19,3 +19,9 @@
 CONFIG_REMAKE_ELF=y
 
 CONFIG_DEFAULT_DEVICE_TREE="qcom/qcs6490-rb3gen2"
+
+# Enable capsule updates
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_IGNORE_OSINDICATIONS=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig
index ea0dd3e..30f7b1c 100644
--- a/configs/qcom_defconfig
+++ b/configs/qcom_defconfig
@@ -21,12 +21,14 @@
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_CMD_BOOTMENU=y
+CONFIG_CMD_NVEDIT_EFI=y
 CONFIG_CMD_EEPROM=y
 CONFIG_SYS_I2C_EEPROM_BUS=2
 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
 CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5
 # CONFIG_CMD_BIND is not set
 CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -34,6 +36,7 @@
 CONFIG_CMD_USB=y
 CONFIG_CMD_CAT=y
 CONFIG_CMD_BMP=y
+CONFIG_CMD_EFIDEBUG=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_LOG=y
 CONFIG_OF_LIVE=y
@@ -52,6 +55,9 @@
 CONFIG_CLK_QCOM_SM8550=y
 CONFIG_CLK_QCOM_SM8650=y
 CONFIG_CLK_QCOM_SC7280=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_SCSI=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x200000
 CONFIG_MSM_GPIO=y
 CONFIG_QCOM_PMIC_GPIO=y
 CONFIG_DM_I2C=y
@@ -77,10 +83,12 @@
 CONFIG_DWC_ETH_QOS_QCOM=y
 CONFIG_RGMII=y
 CONFIG_PHY=y
+CONFIG_PHY_QCOM_QMP_UFS=y
 CONFIG_PHY_QCOM_QUSB2=y
 CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=y
 CONFIG_PHY_QCOM_SNPS_EUSB2=y
 CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
 CONFIG_PINCTRL_QCOM_APQ8016=y
 CONFIG_PINCTRL_QCOM_APQ8096=y
 CONFIG_PINCTRL_QCOM_QCM2290=y
@@ -114,6 +122,7 @@
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_FUNCTION_MASS_STORAGE=y
 CONFIG_UFS=y
+CONFIG_QCOM_UFS=y
 CONFIG_VIDEO=y
 # CONFIG_VIDEO_FONT_8X16 is not set
 CONFIG_VIDEO_FONT_16X32=y
diff --git a/configs/qemu-arm-sbsa_defconfig b/configs/qemu-arm-sbsa_defconfig
index 69195af..375e924 100644
--- a/configs/qemu-arm-sbsa_defconfig
+++ b/configs/qemu-arm-sbsa_defconfig
@@ -1,12 +1,12 @@
 CONFIG_ARM=y
 CONFIG_ARCH_QEMU=y
+CONFIG_BLOBLIST_SIZE_RELOC=0x20000
 CONFIG_TARGET_QEMU_ARM_SBSA=y
+CONFIG_EFI_VARIABLE_NO_STORE=y
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="bootflow scan"
+CONFIG_BLOBLIST_ALLOC=y
 CONFIG_EFI_PARTITION=y
 CONFIG_PARTITION_TYPE_GUID=y
 CONFIG_EFI_MEDIA=y
 CONFIG_FS_FAT=y
-CONFIG_EFI_VARIABLE_NO_STORE=y
-CONFIG_BLOBLIST_ALLOC=y
-CONFIG_BLOBLIST_SIZE_RELOC=0x20000
diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig
index de7267e..9f20b3f 100644
--- a/configs/qemu-ppce500_defconfig
+++ b/configs/qemu-ppce500_defconfig
@@ -39,8 +39,8 @@
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_USE_BOOTFILE=y
 CONFIG_BOOTFILE="uImage"
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_USE_ROOTPATH=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SIMPLE_BUS_CORRECT_RANGE=y
 CONFIG_LBA48=y
 CONFIG_CHIP_SELECTS_PER_CTRL=0
diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig
index 008eb46..812b206 100644
--- a/configs/qemu-x86_64_defconfig
+++ b/configs/qemu-x86_64_defconfig
@@ -6,8 +6,8 @@
 CONFIG_MAX_CPUS=2
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx"
-CONFIG_SPL_TEXT_BASE=0xfffd4000
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_TEXT_BASE=0xfffd4000
 CONFIG_DEBUG_UART_BASE=0x3f8
 CONFIG_DEBUG_UART_CLOCK=1843200
 CONFIG_X86_RUN_64BIT=y
diff --git a/configs/qemu_arm64_lwip_defconfig b/configs/qemu_arm64_lwip_defconfig
index d3d8ef1..754c770 100644
--- a/configs/qemu_arm64_lwip_defconfig
+++ b/configs/qemu_arm64_lwip_defconfig
@@ -7,3 +7,4 @@
 CONFIG_CMD_DNS=y
 CONFIG_CMD_WGET=y
 CONFIG_EFI_HTTP_BOOT=y
+CONFIG_WGET_HTTPS=y
diff --git a/configs/qemu_arm_defconfig b/configs/qemu_arm_defconfig
index d042aea..cc4f454 100644
--- a/configs/qemu_arm_defconfig
+++ b/configs/qemu_arm_defconfig
@@ -67,3 +67,4 @@
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_PCI=y
 CONFIG_TPM=y
+CONFIG_UNIT_TEST=y
diff --git a/configs/qnap-ts433-rk3568_defconfig b/configs/qnap-ts433-rk3568_defconfig
index 840da7f..ceef0d2 100644
--- a/configs/qnap-ts433-rk3568_defconfig
+++ b/configs/qnap-ts433-rk3568_defconfig
@@ -7,9 +7,9 @@
 CONFIG_ROCKCHIP_RK3568=y
 CONFIG_SPL_SERIAL=y
 CONFIG_TARGET_QNAP_TS433_RK3568=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
 CONFIG_DEBUG_UART_BASE=0xFE660000
 CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_SYS_LOAD_ADDR=0xc00800
 CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
@@ -32,8 +32,6 @@
 CONFIG_CMD_PCI=y
 CONFIG_CMD_SATA=y
 CONFIG_CMD_USB=y
-CONFIG_CMD_ROCKUSB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig
index e2ab518..bff65d1 100644
--- a/configs/rock2_defconfig
+++ b/configs/rock2_defconfig
@@ -9,13 +9,13 @@
 CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-rock2-square"
-CONFIG_SPL_TEXT_BASE=0xff704000
 CONFIG_SYS_MONITOR_LEN=614400
 CONFIG_ROCKCHIP_RK3288=y
 CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
 CONFIG_TARGET_ROCK2=y
 CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_SPL_STACK=0xff718000
+CONFIG_SPL_TEXT_BASE=0xff704000
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
 CONFIG_SYS_BOOTM_LEN=0x4000000
diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index c54e13e..47ee210 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -34,6 +34,7 @@
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
 CONFIG_SPL_ATF=y
+CONFIG_CMD_TCPM=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
@@ -94,6 +95,8 @@
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GENERIC=y
 CONFIG_SPL_USB_DWC3_GENERIC=y
+CONFIG_TYPEC_TCPM=y
+CONFIG_TYPEC_FUSB302=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_ASIX88179=y
@@ -106,6 +109,3 @@
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_FUNCTION_ROCKUSB=y
 CONFIG_ERRNO_STR=y
-CONFIG_TYPEC_TCPM=y
-CONFIG_TYPEC_FUSB302=y
-CONFIG_CMD_TCPM=y
diff --git a/configs/rock_defconfig b/configs/rock_defconfig
index e023425..d7f1131 100644
--- a/configs/rock_defconfig
+++ b/configs/rock_defconfig
@@ -12,12 +12,12 @@
 CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3188-radxarock"
-CONFIG_SPL_TEXT_BASE=0x10080800
 CONFIG_ROCKCHIP_RK3188=y
 # CONFIG_ROCKCHIP_STIMER is not set
 CONFIG_TARGET_ROCK=y
 CONFIG_SPL_STACK_R_ADDR=0x60080000
 CONFIG_SPL_STACK=0x10087fff
+CONFIG_SPL_TEXT_BASE=0x10080800
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
 CONFIG_SYS_LOAD_ADDR=0x60800800
diff --git a/configs/rut_defconfig b/configs/rut_defconfig
index b2f87f5..dd8df54 100644
--- a/configs/rut_defconfig
+++ b/configs/rut_defconfig
@@ -60,8 +60,8 @@
 CONFIG_CMD_NAND=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_DNS2=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
diff --git a/configs/sam9x60_curiosity_mmc1_defconfig b/configs/sam9x60_curiosity_mmc1_defconfig
index 7e7efa5..114589c 100644
--- a/configs/sam9x60_curiosity_mmc1_defconfig
+++ b/configs/sam9x60_curiosity_mmc1_defconfig
@@ -42,8 +42,8 @@
 CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
diff --git a/configs/sam9x60_curiosity_mmc_defconfig b/configs/sam9x60_curiosity_mmc_defconfig
index 5d5f5ec..f4e663f 100644
--- a/configs/sam9x60_curiosity_mmc_defconfig
+++ b/configs/sam9x60_curiosity_mmc_defconfig
@@ -42,8 +42,8 @@
 CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
diff --git a/configs/sam9x60ek_mmc_defconfig b/configs/sam9x60ek_mmc_defconfig
index 93bbe6c..1e542e2 100644
--- a/configs/sam9x60ek_mmc_defconfig
+++ b/configs/sam9x60ek_mmc_defconfig
@@ -44,8 +44,8 @@
 CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_SF_TEST=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
diff --git a/configs/sam9x60ek_nandflash_defconfig b/configs/sam9x60ek_nandflash_defconfig
index ddce526..c1754e8 100644
--- a/configs/sam9x60ek_nandflash_defconfig
+++ b/configs/sam9x60ek_nandflash_defconfig
@@ -44,8 +44,8 @@
 CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_SF_TEST=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
diff --git a/configs/sam9x60ek_qspiflash_defconfig b/configs/sam9x60ek_qspiflash_defconfig
index 7f09214..8696b08 100644
--- a/configs/sam9x60ek_qspiflash_defconfig
+++ b/configs/sam9x60ek_qspiflash_defconfig
@@ -43,8 +43,8 @@
 CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
diff --git a/configs/sama5d27_giantboard_defconfig b/configs/sama5d27_giantboard_defconfig
index 7cde865..70e3ea1 100644
--- a/configs/sama5d27_giantboard_defconfig
+++ b/configs/sama5d27_giantboard_defconfig
@@ -13,13 +13,13 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_giantboard"
-CONFIG_SPL_TEXT_BASE=0x200000
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x218000
+CONFIG_SPL_TEXT_BASE=0x200000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x20000000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
diff --git a/configs/sama5d27_som1_ek_mmc1_defconfig b/configs/sama5d27_som1_ek_mmc1_defconfig
index 2715437..9246ede 100644
--- a/configs/sama5d27_som1_ek_mmc1_defconfig
+++ b/configs/sama5d27_som1_ek_mmc1_defconfig
@@ -13,13 +13,13 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_som1_ek"
-CONFIG_SPL_TEXT_BASE=0x200000
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x218000
+CONFIG_SPL_TEXT_BASE=0x200000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x20000000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
@@ -54,8 +54,8 @@
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
 CONFIG_HASH_VERIFY=y
diff --git a/configs/sama5d27_som1_ek_mmc_defconfig b/configs/sama5d27_som1_ek_mmc_defconfig
index 25a0d6c..4be4245 100644
--- a/configs/sama5d27_som1_ek_mmc_defconfig
+++ b/configs/sama5d27_som1_ek_mmc_defconfig
@@ -14,13 +14,13 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_som1_ek"
-CONFIG_SPL_TEXT_BASE=0x200000
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x218000
+CONFIG_SPL_TEXT_BASE=0x200000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x20000000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
@@ -55,8 +55,8 @@
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
 CONFIG_HASH_VERIFY=y
diff --git a/configs/sama5d27_som1_ek_qspiflash_defconfig b/configs/sama5d27_som1_ek_qspiflash_defconfig
index f88a2e6..cdd1060 100644
--- a/configs/sama5d27_som1_ek_qspiflash_defconfig
+++ b/configs/sama5d27_som1_ek_qspiflash_defconfig
@@ -14,13 +14,13 @@
 CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_som1_ek"
-CONFIG_SPL_TEXT_BASE=0x200000
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x218000
+CONFIG_SPL_TEXT_BASE=0x200000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x20000000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
@@ -53,8 +53,8 @@
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
 CONFIG_HASH_VERIFY=y
diff --git a/configs/sama5d27_wlsom1_ek_mmc_defconfig b/configs/sama5d27_wlsom1_ek_mmc_defconfig
index 5edb634..cc69a41 100644
--- a/configs/sama5d27_wlsom1_ek_mmc_defconfig
+++ b/configs/sama5d27_wlsom1_ek_mmc_defconfig
@@ -12,13 +12,13 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_wlsom1_ek"
-CONFIG_SPL_TEXT_BASE=0x200000
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x218000
+CONFIG_SPL_TEXT_BASE=0x200000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x20000000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
@@ -58,8 +58,8 @@
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_MMC=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
diff --git a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig
index 9d5863e..beab5d0 100644
--- a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig
+++ b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig
@@ -13,12 +13,12 @@
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_wlsom1_ek"
-CONFIG_SPL_TEXT_BASE=0x200000
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x218000
+CONFIG_SPL_TEXT_BASE=0x200000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x20000000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
@@ -62,8 +62,8 @@
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
diff --git a/configs/sama5d2_icp_mmc_defconfig b/configs/sama5d2_icp_mmc_defconfig
index c1d1f20..5e8b9b9 100644
--- a/configs/sama5d2_icp_mmc_defconfig
+++ b/configs/sama5d2_icp_mmc_defconfig
@@ -63,8 +63,8 @@
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF_TEST=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
 CONFIG_HASH_VERIFY=y
diff --git a/configs/sama5d2_icp_qspiflash_defconfig b/configs/sama5d2_icp_qspiflash_defconfig
index c731c67..463951a 100644
--- a/configs/sama5d2_icp_qspiflash_defconfig
+++ b/configs/sama5d2_icp_qspiflash_defconfig
@@ -51,8 +51,8 @@
 CONFIG_CMD_SDRAM=y
 CONFIG_CMD_SF_TEST=y
 CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_GETTIME=y
 CONFIG_CMD_TIMER=y
diff --git a/configs/sama5d2_ptc_ek_mmc_defconfig b/configs/sama5d2_ptc_ek_mmc_defconfig
index ac96fe8..e62fd8c 100644
--- a/configs/sama5d2_ptc_ek_mmc_defconfig
+++ b/configs/sama5d2_ptc_ek_mmc_defconfig
@@ -38,8 +38,8 @@
 CONFIG_CMD_MMC=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
 CONFIG_HASH_VERIFY=y
diff --git a/configs/sama5d2_ptc_ek_nandflash_defconfig b/configs/sama5d2_ptc_ek_nandflash_defconfig
index e4d6a1d..0729cad 100644
--- a/configs/sama5d2_ptc_ek_nandflash_defconfig
+++ b/configs/sama5d2_ptc_ek_nandflash_defconfig
@@ -38,8 +38,8 @@
 CONFIG_CMD_MMC=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
 CONFIG_HASH_VERIFY=y
diff --git a/configs/sama5d2_xplained_emmc_defconfig b/configs/sama5d2_xplained_emmc_defconfig
index 23b53f1..736a6ee 100644
--- a/configs/sama5d2_xplained_emmc_defconfig
+++ b/configs/sama5d2_xplained_emmc_defconfig
@@ -13,13 +13,13 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained"
-CONFIG_SPL_TEXT_BASE=0x200000
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x218000
+CONFIG_SPL_TEXT_BASE=0x200000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x20000000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
@@ -54,8 +54,8 @@
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
 CONFIG_HASH_VERIFY=y
diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig
index f3b1b78..6fd1075 100644
--- a/configs/sama5d2_xplained_mmc_defconfig
+++ b/configs/sama5d2_xplained_mmc_defconfig
@@ -14,13 +14,13 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained"
-CONFIG_SPL_TEXT_BASE=0x200000
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x218000
+CONFIG_SPL_TEXT_BASE=0x200000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x20000000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
@@ -56,8 +56,8 @@
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
 CONFIG_HASH_VERIFY=y
diff --git a/configs/sama5d2_xplained_qspiflash_defconfig b/configs/sama5d2_xplained_qspiflash_defconfig
index f4b27fb..4c30e9d 100644
--- a/configs/sama5d2_xplained_qspiflash_defconfig
+++ b/configs/sama5d2_xplained_qspiflash_defconfig
@@ -14,13 +14,13 @@
 CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained"
-CONFIG_SPL_TEXT_BASE=0x200000
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x218000
+CONFIG_SPL_TEXT_BASE=0x200000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x20000000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
@@ -57,8 +57,8 @@
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
 CONFIG_HASH_VERIFY=y
diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig
index da386d2..9431ff1 100644
--- a/configs/sama5d2_xplained_spiflash_defconfig
+++ b/configs/sama5d2_xplained_spiflash_defconfig
@@ -17,12 +17,12 @@
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained"
-CONFIG_SPL_TEXT_BASE=0x200000
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x218000
+CONFIG_SPL_TEXT_BASE=0x200000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x20000000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
@@ -61,8 +61,8 @@
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
 CONFIG_HASH_VERIFY=y
diff --git a/configs/sama5d36ek_cmp_mmc_defconfig b/configs/sama5d36ek_cmp_mmc_defconfig
index a5d7be0..217632c 100644
--- a/configs/sama5d36ek_cmp_mmc_defconfig
+++ b/configs/sama5d36ek_cmp_mmc_defconfig
@@ -37,8 +37,8 @@
 CONFIG_CMD_MMC=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
diff --git a/configs/sama5d36ek_cmp_nandflash_defconfig b/configs/sama5d36ek_cmp_nandflash_defconfig
index caf843e..595cb9c 100644
--- a/configs/sama5d36ek_cmp_nandflash_defconfig
+++ b/configs/sama5d36ek_cmp_nandflash_defconfig
@@ -37,8 +37,8 @@
 CONFIG_CMD_MMC=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
diff --git a/configs/sama5d36ek_cmp_spiflash_defconfig b/configs/sama5d36ek_cmp_spiflash_defconfig
index 7db6bed..743959c 100644
--- a/configs/sama5d36ek_cmp_spiflash_defconfig
+++ b/configs/sama5d36ek_cmp_spiflash_defconfig
@@ -39,8 +39,8 @@
 CONFIG_CMD_MMC=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig
index ad02b09..0050d95 100644
--- a/configs/sama5d3_xplained_mmc_defconfig
+++ b/configs/sama5d3_xplained_mmc_defconfig
@@ -13,13 +13,13 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d3_xplained"
-CONFIG_SPL_TEXT_BASE=0x300000
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_MONITOR_LEN=1048576
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x318000
+CONFIG_SPL_TEXT_BASE=0x300000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x20000000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
@@ -53,8 +53,8 @@
 CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig
index 2eb9e1b..6a66637 100644
--- a/configs/sama5d3_xplained_nandflash_defconfig
+++ b/configs/sama5d3_xplained_nandflash_defconfig
@@ -12,12 +12,12 @@
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ef0
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d3_xplained"
-CONFIG_SPL_TEXT_BASE=0x300000
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_MONITOR_LEN=1048576
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x318000
+CONFIG_SPL_TEXT_BASE=0x300000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x20000000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
@@ -53,8 +53,8 @@
 CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig
index 27e5a1d..4c79146 100644
--- a/configs/sama5d3xek_mmc_defconfig
+++ b/configs/sama5d3xek_mmc_defconfig
@@ -14,12 +14,12 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek"
-CONFIG_SPL_TEXT_BASE=0x300000
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x318000
+CONFIG_SPL_TEXT_BASE=0x300000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x20000000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
@@ -57,8 +57,8 @@
 CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_EXT4=y
diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig
index 770b999..985a152 100644
--- a/configs/sama5d3xek_nandflash_defconfig
+++ b/configs/sama5d3xek_nandflash_defconfig
@@ -13,11 +13,11 @@
 CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek"
-CONFIG_SPL_TEXT_BASE=0x300000
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x318000
+CONFIG_SPL_TEXT_BASE=0x300000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x20000000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
@@ -57,8 +57,8 @@
 CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig
index 4bb0dbe..3f2bd73 100644
--- a/configs/sama5d3xek_spiflash_defconfig
+++ b/configs/sama5d3xek_spiflash_defconfig
@@ -17,11 +17,11 @@
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek"
-CONFIG_SPL_TEXT_BASE=0x300000
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x318000
+CONFIG_SPL_TEXT_BASE=0x300000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x20000000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
@@ -60,8 +60,8 @@
 CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig
index 2efe73f..f0c4356 100644
--- a/configs/sama5d4_xplained_mmc_defconfig
+++ b/configs/sama5d4_xplained_mmc_defconfig
@@ -14,13 +14,13 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained"
-CONFIG_SPL_TEXT_BASE=0x200000
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x218000
+CONFIG_SPL_TEXT_BASE=0x200000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x20000000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
@@ -54,8 +54,8 @@
 CONFIG_CMD_MMC=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
 CONFIG_HASH_VERIFY=y
diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig
index 0241318..4d6ca43 100644
--- a/configs/sama5d4_xplained_nandflash_defconfig
+++ b/configs/sama5d4_xplained_nandflash_defconfig
@@ -13,12 +13,12 @@
 CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained"
-CONFIG_SPL_TEXT_BASE=0x200000
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x218000
+CONFIG_SPL_TEXT_BASE=0x200000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x20000000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
@@ -54,8 +54,8 @@
 CONFIG_CMD_MMC=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
 CONFIG_HASH_VERIFY=y
diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig
index 28babe7..c0680fb 100644
--- a/configs/sama5d4_xplained_spiflash_defconfig
+++ b/configs/sama5d4_xplained_spiflash_defconfig
@@ -17,12 +17,12 @@
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained"
-CONFIG_SPL_TEXT_BASE=0x200000
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x218000
+CONFIG_SPL_TEXT_BASE=0x200000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x20000000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
@@ -59,8 +59,8 @@
 CONFIG_CMD_MMC=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_HASH=y
 CONFIG_HASH_VERIFY=y
diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig
index c839514..347ccb4 100644
--- a/configs/sama5d4ek_mmc_defconfig
+++ b/configs/sama5d4ek_mmc_defconfig
@@ -14,12 +14,12 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4ek"
-CONFIG_SPL_TEXT_BASE=0x200000
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x218000
+CONFIG_SPL_TEXT_BASE=0x200000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x20000000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
@@ -55,8 +55,8 @@
 CONFIG_CMD_MMC=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig
index fadefd9..b309b87 100644
--- a/configs/sama5d4ek_nandflash_defconfig
+++ b/configs/sama5d4ek_nandflash_defconfig
@@ -13,11 +13,11 @@
 CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4ek"
-CONFIG_SPL_TEXT_BASE=0x200000
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x218000
+CONFIG_SPL_TEXT_BASE=0x200000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x20000000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
@@ -55,8 +55,8 @@
 CONFIG_CMD_MMC=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig
index 35b6314..38edafc 100644
--- a/configs/sama5d4ek_spiflash_defconfig
+++ b/configs/sama5d4ek_spiflash_defconfig
@@ -17,11 +17,11 @@
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4ek"
-CONFIG_SPL_TEXT_BASE=0x200000
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x218000
+CONFIG_SPL_TEXT_BASE=0x200000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x20000000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
@@ -58,8 +58,8 @@
 CONFIG_CMD_MMC=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig
index b5f80b8..7960b2e 100644
--- a/configs/sandbox64_defconfig
+++ b/configs/sandbox64_defconfig
@@ -44,7 +44,6 @@
 CONFIG_CMD_NVEDIT_SELECT=y
 CONFIG_LOOPW=y
 CONFIG_CMD_MD5SUM=y
-CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_MX_CYCLIC=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_BCB=y
@@ -75,10 +74,10 @@
 CONFIG_CMD_RARP=y
 CONFIG_CMD_CDP=y
 CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
 CONFIG_CMD_LINK_LOCAL=y
 CONFIG_IPV6_ROUTER_DISCOVERY=y
 CONFIG_CMD_ETHSW=y
+CONFIG_CMD_DNS=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_EFIDEBUG=y
 CONFIG_CMD_RTC=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index d111858..8c244c8 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -50,6 +50,7 @@
 CONFIG_LOGF_FUNC=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_STACKPROTECTOR=y
+CONFIG_ANDROID_AB=y
 CONFIG_CMD_CPU=y
 CONFIG_CMD_LICENSE=y
 CONFIG_CMD_SMBIOS=y
@@ -71,7 +72,6 @@
 CONFIG_CMD_NVEDIT_SELECT=y
 CONFIG_LOOPW=y
 CONFIG_CMD_MD5SUM=y
-CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_MEM_SEARCH=y
 CONFIG_CMD_MX_CYCLIC=y
 CONFIG_CMD_MEMTEST=y
@@ -111,10 +111,10 @@
 CONFIG_CMD_RARP=y
 CONFIG_CMD_CDP=y
 CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
 CONFIG_CMD_LINK_LOCAL=y
 CONFIG_IPV6_ROUTER_DISCOVERY=y
 CONFIG_CMD_ETHSW=y
+CONFIG_CMD_DNS=y
 CONFIG_CMD_2048=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_BOOTCOUNT=y
diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig
index 0313fa0..563093d 100644
--- a/configs/sandbox_flattree_defconfig
+++ b/configs/sandbox_flattree_defconfig
@@ -41,7 +41,6 @@
 CONFIG_CMD_NVEDIT_SELECT=y
 CONFIG_LOOPW=y
 CONFIG_CMD_MD5SUM=y
-CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_MX_CYCLIC=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_CLK=y
@@ -64,9 +63,9 @@
 CONFIG_CMD_RARP=y
 CONFIG_CMD_CDP=y
 CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
 CONFIG_CMD_LINK_LOCAL=y
 CONFIG_IPV6_ROUTER_DISCOVERY=y
+CONFIG_CMD_DNS=y
 CONFIG_CMD_EFIDEBUG=y
 CONFIG_CMD_RTC=y
 CONFIG_CMD_TIME=y
diff --git a/configs/sandbox_nocmdline_defconfig b/configs/sandbox_nocmdline_defconfig
new file mode 100644
index 0000000..0317311
--- /dev/null
+++ b/configs/sandbox_nocmdline_defconfig
@@ -0,0 +1,2 @@
+#include "sandbox_defconfig"
+# CONFIG_CMDLINE is not set
diff --git a/configs/sandbox_noinst_defconfig b/configs/sandbox_noinst_defconfig
index a48ef1f..2a8e79a 100644
--- a/configs/sandbox_noinst_defconfig
+++ b/configs/sandbox_noinst_defconfig
@@ -78,7 +78,6 @@
 CONFIG_CMD_NVEDIT_SELECT=y
 CONFIG_LOOPW=y
 CONFIG_CMD_MD5SUM=y
-CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_MX_CYCLIC=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_CLK=y
@@ -100,8 +99,8 @@
 CONFIG_CMD_RARP=y
 CONFIG_CMD_CDP=y
 CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
 CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DNS=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_EFIDEBUG=y
 CONFIG_CMD_TIME=y
diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig
index f446962..91a09ba 100644
--- a/configs/sandbox_spl_defconfig
+++ b/configs/sandbox_spl_defconfig
@@ -57,7 +57,6 @@
 CONFIG_CMD_NVEDIT_SELECT=y
 CONFIG_LOOPW=y
 CONFIG_CMD_MD5SUM=y
-CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_MX_CYCLIC=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_CLK=y
@@ -78,8 +77,8 @@
 CONFIG_CMD_RARP=y
 CONFIG_CMD_CDP=y
 CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
 CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DNS=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_EFIDEBUG=y
 CONFIG_CMD_TIME=y
diff --git a/configs/sandbox_vpl_defconfig b/configs/sandbox_vpl_defconfig
index cda2526..84df2b8 100644
--- a/configs/sandbox_vpl_defconfig
+++ b/configs/sandbox_vpl_defconfig
@@ -4,7 +4,6 @@
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="sandbox"
-CONFIG_SPL_TEXT_BASE=0x100000
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
@@ -14,6 +13,7 @@
 CONFIG_TPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_TEXT_BASE=0x100000
 CONFIG_SYS_LOAD_ADDR=0x0
 CONFIG_SPL=y
 CONFIG_PCI=y
@@ -68,7 +68,6 @@
 CONFIG_CMD_NVEDIT_SELECT=y
 CONFIG_LOOPW=y
 CONFIG_CMD_MD5SUM=y
-CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_MX_CYCLIC=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_CLK=y
@@ -89,8 +88,8 @@
 CONFIG_CMD_RARP=y
 CONFIG_CMD_CDP=y
 CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
 CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DNS=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_EFIDEBUG=y
 CONFIG_CMD_TIME=y
diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig
index 84cec35..090dc04 100644
--- a/configs/seaboard_defconfig
+++ b/configs/seaboard_defconfig
@@ -6,8 +6,8 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFE000
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-seaboard"
-CONFIG_SPL_TEXT_BASE=0x00108000
 CONFIG_SPL_STACK=0xffffc
+CONFIG_SPL_TEXT_BASE=0x00108000
 CONFIG_SYS_LOAD_ADDR=0x1000000
 CONFIG_TEGRA20=y
 CONFIG_TARGET_SEABOARD=y
diff --git a/configs/seeed_npi_imx6ull_defconfig b/configs/seeed_npi_imx6ull_defconfig
index e755702..6211588 100644
--- a/configs/seeed_npi_imx6ull_defconfig
+++ b/configs/seeed_npi_imx6ull_defconfig
@@ -10,10 +10,10 @@
 CONFIG_MX6ULL=y
 CONFIG_TARGET_NPI_IMX6ULL=y
 CONFIG_DEFAULT_DEVICE_TREE="imx6ull-seeed-npi-imx6ull-dev-board"
-CONFIG_SPL_TEXT_BASE=0x908000
 CONFIG_SYS_MONITOR_LEN=409600
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0x908000
 CONFIG_SPL=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x90000000
@@ -44,9 +44,9 @@
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_USE_ETHPRIME=y
 CONFIG_ETHPRIME="eth0"
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_USE_NETMASK=y
 CONFIG_NETMASK="255.255.255.0"
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_FSL_USDHC=y
 CONFIG_MTD=y
 CONFIG_DM_MTD=y
diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig
index 9d59914..9ac40b9 100644
--- a/configs/sheevaplug_defconfig
+++ b/configs/sheevaplug_defconfig
@@ -51,9 +51,9 @@
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_NAND=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
 CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SATA_MV=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_LBA48=y
diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig
index 5e54e7f..aa8adf5 100644
--- a/configs/smartweb_defconfig
+++ b/configs/smartweb_defconfig
@@ -57,8 +57,8 @@
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_NAND=y
 # CONFIG_CMD_SOURCE is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_MTDPARTS=y
diff --git a/configs/smdkv310_defconfig b/configs/smdkv310_defconfig
index 2677ba7..b1c77c7 100644
--- a/configs/smdkv310_defconfig
+++ b/configs/smdkv310_defconfig
@@ -12,8 +12,8 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x4200
 CONFIG_DEFAULT_DEVICE_TREE="exynos4210-smdkv310"
-CONFIG_SPL_TEXT_BASE=0x02021410
 CONFIG_SYS_MONITOR_LEN=262144
+CONFIG_SPL_TEXT_BASE=0x02021410
 CONFIG_SYS_LOAD_ADDR=0x43e00000
 CONFIG_SPL=y
 CONFIG_IDENT_STRING=" for SMDKC210/V310"
diff --git a/configs/socfpga_agilex_atf_defconfig b/configs/socfpga_agilex_atf_defconfig
index bd6879c..8c4f707 100644
--- a/configs/socfpga_agilex_atf_defconfig
+++ b/configs/socfpga_agilex_atf_defconfig
@@ -12,9 +12,9 @@
 CONFIG_ENV_OFFSET=0x200
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk"
-CONFIG_SPL_TEXT_BASE=0xFFE00000
 CONFIG_DM_RESET=y
 CONFIG_SPL_STACK=0xffe3f000
+CONFIG_SPL_TEXT_BASE=0xFFE00000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x3ff00000
 CONFIG_SPL_BSS_MAX_SIZE=0x100000
diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig
index 29bb091..eaa2161 100644
--- a/configs/socfpga_agilex_defconfig
+++ b/configs/socfpga_agilex_defconfig
@@ -11,9 +11,9 @@
 CONFIG_ENV_OFFSET=0x200
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk"
-CONFIG_SPL_TEXT_BASE=0xFFE00000
 CONFIG_DM_RESET=y
 CONFIG_SPL_STACK=0xffe3f000
+CONFIG_SPL_TEXT_BASE=0xFFE00000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x3ff00000
 CONFIG_SPL_BSS_MAX_SIZE=0x100000
diff --git a/configs/socfpga_agilex_vab_defconfig b/configs/socfpga_agilex_vab_defconfig
index 983e3ac..2883480 100644
--- a/configs/socfpga_agilex_vab_defconfig
+++ b/configs/socfpga_agilex_vab_defconfig
@@ -12,9 +12,9 @@
 CONFIG_ENV_OFFSET=0x200
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk"
-CONFIG_SPL_TEXT_BASE=0xFFE00000
 CONFIG_DM_RESET=y
 CONFIG_SPL_STACK=0xffe3f000
+CONFIG_SPL_TEXT_BASE=0xFFE00000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x3ff00000
 CONFIG_SPL_BSS_MAX_SIZE=0x100000
diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig
index 6d27dee..7b3b022 100644
--- a/configs/socfpga_arria10_defconfig
+++ b/configs/socfpga_arria10_defconfig
@@ -8,9 +8,9 @@
 CONFIG_ENV_OFFSET=0x4400
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
-CONFIG_SPL_TEXT_BASE=0xFFE00000
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0xffe2b000
+CONFIG_SPL_TEXT_BASE=0xFFE00000
 CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
 CONFIG_IDENT_STRING="socfpga_arria10"
 CONFIG_SPL_FS_FAT=y
diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index b0c0906..9185af2 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -8,9 +8,9 @@
 CONFIG_ENV_OFFSET=0x4400
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk"
-CONFIG_SPL_TEXT_BASE=0xFFFF0000
 CONFIG_DM_RESET=y
 CONFIG_SPL_STACK=0x0
+CONFIG_SPL_TEXT_BASE=0xFFFF0000
 CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK=y
 CONFIG_TIMESTAMP=y
 CONFIG_FIT=y
diff --git a/configs/socfpga_chameleonv3_defconfig b/configs/socfpga_chameleonv3_defconfig
index a20b1b0..0b5c5a7 100644
--- a/configs/socfpga_chameleonv3_defconfig
+++ b/configs/socfpga_chameleonv3_defconfig
@@ -4,8 +4,8 @@
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x4400
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_chameleonv3_480_2"
-CONFIG_SPL_TEXT_BASE=0xFFE00000
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFFE00000
 CONFIG_SYS_BOOTM_LEN=0x2000000
 CONFIG_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM=y
 CONFIG_TARGET_SOCFPGA_CHAMELEONV3=y
diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
index 5ab48db..69a9909 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -8,9 +8,9 @@
 CONFIG_ENV_OFFSET=0x4400
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
-CONFIG_SPL_TEXT_BASE=0xFFFF0000
 CONFIG_DM_RESET=y
 CONFIG_SPL_STACK=0x0
+CONFIG_SPL_TEXT_BASE=0xFFFF0000
 CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y
 CONFIG_TIMESTAMP=y
 CONFIG_FIT=y
diff --git a/configs/socfpga_dbm_soc1_defconfig b/configs/socfpga_dbm_soc1_defconfig
index cf4e8eb..5b320e0 100644
--- a/configs/socfpga_dbm_soc1_defconfig
+++ b/configs/socfpga_dbm_soc1_defconfig
@@ -8,9 +8,9 @@
 CONFIG_ENV_OFFSET=0x4400
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_dbm_soc1"
-CONFIG_SPL_TEXT_BASE=0xFFFF0000
 CONFIG_DM_RESET=y
 CONFIG_SPL_STACK=0x0
+CONFIG_SPL_TEXT_BASE=0xFFFF0000
 CONFIG_TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1=y
 CONFIG_TIMESTAMP=y
 CONFIG_FIT=y
diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig
index c16004f..04b051c 100644
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ b/configs/socfpga_de0_nano_soc_defconfig
@@ -8,9 +8,9 @@
 CONFIG_ENV_OFFSET=0x4400
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de0_nano_soc"
-CONFIG_SPL_TEXT_BASE=0xFFFF0000
 CONFIG_DM_RESET=y
 CONFIG_SPL_STACK=0x0
+CONFIG_SPL_TEXT_BASE=0xFFFF0000
 CONFIG_TARGET_SOCFPGA_TERASIC_DE0_NANO=y
 CONFIG_TIMESTAMP=y
 CONFIG_FIT=y
diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig
index 005d575..703af3f 100644
--- a/configs/socfpga_de10_nano_defconfig
+++ b/configs/socfpga_de10_nano_defconfig
@@ -8,9 +8,9 @@
 CONFIG_ENV_OFFSET=0x4400
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de10_nano"
-CONFIG_SPL_TEXT_BASE=0xFFFF0000
 CONFIG_DM_RESET=y
 CONFIG_SPL_STACK=0x0
+CONFIG_SPL_TEXT_BASE=0xFFFF0000
 CONFIG_TARGET_SOCFPGA_TERASIC_DE10_NANO=y
 CONFIG_TIMESTAMP=y
 CONFIG_FIT=y
diff --git a/configs/socfpga_de10_standard_defconfig b/configs/socfpga_de10_standard_defconfig
index bf463f3..76c41b2 100644
--- a/configs/socfpga_de10_standard_defconfig
+++ b/configs/socfpga_de10_standard_defconfig
@@ -8,9 +8,9 @@
 CONFIG_ENV_OFFSET=0x4400
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de10_standard"
-CONFIG_SPL_TEXT_BASE=0xFFFF0000
 CONFIG_DM_RESET=y
 CONFIG_SPL_STACK=0x0
+CONFIG_SPL_TEXT_BASE=0xFFFF0000
 CONFIG_TARGET_SOCFPGA_TERASIC_DE10_STANDARD=y
 CONFIG_TIMESTAMP=y
 CONFIG_FIT=y
diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig
index c8985ed..8cb158a 100644
--- a/configs/socfpga_de1_soc_defconfig
+++ b/configs/socfpga_de1_soc_defconfig
@@ -8,9 +8,9 @@
 CONFIG_ENV_OFFSET=0x4400
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de1_soc"
-CONFIG_SPL_TEXT_BASE=0xFFFF0000
 CONFIG_DM_RESET=y
 CONFIG_SPL_STACK=0x0
+CONFIG_SPL_TEXT_BASE=0xFFFF0000
 CONFIG_TARGET_SOCFPGA_TERASIC_DE1_SOC=y
 # CONFIG_EFI_LOADER is not set
 CONFIG_TIMESTAMP=y
diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig
index 74994e3..231cf6b 100644
--- a/configs/socfpga_is1_defconfig
+++ b/configs/socfpga_is1_defconfig
@@ -9,10 +9,10 @@
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_is1"
-CONFIG_SPL_TEXT_BASE=0xFFFF0000
 CONFIG_DM_RESET=y
 CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
 CONFIG_SPL_STACK=0xfffffff8
+CONFIG_SPL_TEXT_BASE=0xFFFF0000
 CONFIG_TARGET_SOCFPGA_IS1=y
 # CONFIG_EFI_LOADER is not set
 CONFIG_TIMESTAMP=y
diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig
index fdf0775..7aa2db6 100644
--- a/configs/socfpga_mcvevk_defconfig
+++ b/configs/socfpga_mcvevk_defconfig
@@ -8,9 +8,9 @@
 CONFIG_ENV_OFFSET=0x4400
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_mcvevk"
-CONFIG_SPL_TEXT_BASE=0xFFFF0000
 CONFIG_DM_RESET=y
 CONFIG_SPL_STACK=0x0
+CONFIG_SPL_TEXT_BASE=0xFFFF0000
 CONFIG_TARGET_SOCFPGA_ARIES_MCVEVK=y
 CONFIG_TIMESTAMP=y
 CONFIG_FIT=y
diff --git a/configs/socfpga_n5x_atf_defconfig b/configs/socfpga_n5x_atf_defconfig
index 557adb4..5e92717 100644
--- a/configs/socfpga_n5x_atf_defconfig
+++ b/configs/socfpga_n5x_atf_defconfig
@@ -12,9 +12,9 @@
 CONFIG_ENV_OFFSET=0x200
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_n5x_socdk"
-CONFIG_SPL_TEXT_BASE=0xFFE00000
 CONFIG_DM_RESET=y
 CONFIG_SPL_STACK=0xffe3f000
+CONFIG_SPL_TEXT_BASE=0xFFE00000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x3ff00000
 CONFIG_SPL_BSS_MAX_SIZE=0x100000
diff --git a/configs/socfpga_n5x_defconfig b/configs/socfpga_n5x_defconfig
index 8615bb4..593325c 100644
--- a/configs/socfpga_n5x_defconfig
+++ b/configs/socfpga_n5x_defconfig
@@ -11,9 +11,9 @@
 CONFIG_ENV_OFFSET=0x200
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_n5x_socdk"
-CONFIG_SPL_TEXT_BASE=0xFFE00000
 CONFIG_DM_RESET=y
 CONFIG_SPL_STACK=0xffe3f000
+CONFIG_SPL_TEXT_BASE=0xFFE00000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x3ff00000
 CONFIG_SPL_BSS_MAX_SIZE=0x100000
diff --git a/configs/socfpga_n5x_vab_defconfig b/configs/socfpga_n5x_vab_defconfig
index dbd5470..e3d52fe 100644
--- a/configs/socfpga_n5x_vab_defconfig
+++ b/configs/socfpga_n5x_vab_defconfig
@@ -12,9 +12,9 @@
 CONFIG_ENV_OFFSET=0x200
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_n5x_socdk"
-CONFIG_SPL_TEXT_BASE=0xFFE00000
 CONFIG_DM_RESET=y
 CONFIG_SPL_STACK=0xffe3f000
+CONFIG_SPL_TEXT_BASE=0xFFE00000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x3ff00000
 CONFIG_SPL_BSS_MAX_SIZE=0x100000
diff --git a/configs/socfpga_secu1_defconfig b/configs/socfpga_secu1_defconfig
index 4665c09..dc6d66a 100644
--- a/configs/socfpga_secu1_defconfig
+++ b/configs/socfpga_secu1_defconfig
@@ -10,11 +10,11 @@
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_secu1"
-CONFIG_SPL_TEXT_BASE=0xFFFF0000
 CONFIG_DM_RESET=y
 # CONFIG_SPL_MMC is not set
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x0
+CONFIG_SPL_TEXT_BASE=0xFFFF0000
 CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_SYS_LOAD_ADDR=0x02000000
 CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index 2487f0a..869ba3d 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -8,9 +8,9 @@
 CONFIG_ENV_OFFSET=0x4400
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit"
-CONFIG_SPL_TEXT_BASE=0xFFFF0000
 CONFIG_DM_RESET=y
 CONFIG_SPL_STACK=0x0
+CONFIG_SPL_TEXT_BASE=0xFFFF0000
 CONFIG_TARGET_SOCFPGA_TERASIC_SOCKIT=y
 CONFIG_TIMESTAMP=y
 CONFIG_FIT=y
diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
index e8a9ade..31b4064 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -8,9 +8,9 @@
 CONFIG_ENV_OFFSET=0x4400
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
-CONFIG_SPL_TEXT_BASE=0xFFFF0000
 CONFIG_DM_RESET=y
 CONFIG_SPL_STACK=0x0
+CONFIG_SPL_TEXT_BASE=0xFFFF0000
 CONFIG_TARGET_SOCFPGA_EBV_SOCRATES=y
 CONFIG_FIT=y
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index c415248..cade0d4 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -10,10 +10,10 @@
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
-CONFIG_SPL_TEXT_BASE=0xFFFF0000
 CONFIG_DM_RESET=y
 CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
 CONFIG_SPL_STACK=0xfffffff8
+CONFIG_SPL_TEXT_BASE=0xFFFF0000
 CONFIG_TARGET_SOCFPGA_SR1500=y
 CONFIG_ENV_OFFSET_REDUND=0xF0000
 CONFIG_SYS_MEMTEST_START=0x00000000
diff --git a/configs/socfpga_stratix10_atf_defconfig b/configs/socfpga_stratix10_atf_defconfig
index 471b921..d3a358c 100644
--- a/configs/socfpga_stratix10_atf_defconfig
+++ b/configs/socfpga_stratix10_atf_defconfig
@@ -12,9 +12,9 @@
 CONFIG_ENV_OFFSET=0x200
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
-CONFIG_SPL_TEXT_BASE=0xFFE00000
 CONFIG_DM_RESET=y
 CONFIG_SPL_STACK=0xffe3f000
+CONFIG_SPL_TEXT_BASE=0xFFE00000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x3ff00000
 CONFIG_SPL_BSS_MAX_SIZE=0x100000
diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
index 99c33e6..3ea8259 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -11,9 +11,9 @@
 CONFIG_ENV_OFFSET=0x200
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
-CONFIG_SPL_TEXT_BASE=0xFFE00000
 CONFIG_DM_RESET=y
 CONFIG_SPL_STACK=0xffe3f000
+CONFIG_SPL_TEXT_BASE=0xFFE00000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x3ff00000
 CONFIG_SPL_BSS_MAX_SIZE=0x100000
diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig
index 094e918..df8391d 100644
--- a/configs/socfpga_vining_fpga_defconfig
+++ b/configs/socfpga_vining_fpga_defconfig
@@ -10,9 +10,9 @@
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_vining_fpga"
-CONFIG_SPL_TEXT_BASE=0xFFFF0000
 CONFIG_DM_RESET=y
 CONFIG_SPL_STACK=0x0
+CONFIG_SPL_TEXT_BASE=0xFFFF0000
 CONFIG_SYS_BOOTM_LEN=0x2000000
 CONFIG_TARGET_SOCFPGA_SOFTING_VINING_FPGA=y
 CONFIG_ENV_OFFSET_REDUND=0x110000
diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig
index e99d0a9..93d2736 100644
--- a/configs/socrates_defconfig
+++ b/configs/socrates_defconfig
@@ -55,11 +55,11 @@
 CONFIG_CMD_SDRAM=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
 # CONFIG_CMD_HASH is not set
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_MTDPARTS=y
diff --git a/configs/som-db5800-som-6867_defconfig b/configs/som-db5800-som-6867_defconfig
index c5de56a..473b04a 100644
--- a/configs/som-db5800-som-6867_defconfig
+++ b/configs/som-db5800-som-6867_defconfig
@@ -35,8 +35,8 @@
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig
index 11e1332..20f89ae 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -10,12 +10,12 @@
 CONFIG_ENV_OFFSET=0xf0000
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="jh7110-starfive-visionfive-2"
-CONFIG_SPL_TEXT_BASE=0x8000000
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x8180000
+CONFIG_SPL_TEXT_BASE=0x8000000
 CONFIG_SPL_BSS_START_ADDR=0x8040000
 CONFIG_SPL_BSS_MAX_SIZE=0x10000
 CONFIG_SYS_BOOTM_LEN=0x4000000
@@ -32,6 +32,7 @@
 CONFIG_RISCV_SMODE=y
 # CONFIG_OF_BOARD_FIXUP is not set
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
 CONFIG_FIT=y
 CONFIG_BOOTSTD_DEFAULTS=y
 CONFIG_BOOTSTAGE=y
@@ -55,10 +56,10 @@
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80000000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x400000
 CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2
-CONFIG_SPL_SYS_MALLOC_SIZE=0x400000
 CONFIG_SPL_I2C=y
 CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_DM_RESET=y
diff --git a/configs/stm32746g-eval_defconfig b/configs/stm32746g-eval_defconfig
index 21437d8..4346ecd 100644
--- a/configs/stm32746g-eval_defconfig
+++ b/configs/stm32746g-eval_defconfig
@@ -27,16 +27,16 @@
 CONFIG_CMD_MMC=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
 CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DNS=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIMER=y
 # CONFIG_ISO_PARTITION is not set
 CONFIG_OF_CONTROL=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_ARM_PL180_MMCI=y
 CONFIG_MTD=y
 CONFIG_DM_MTD=y
diff --git a/configs/stm32746g-eval_spl_defconfig b/configs/stm32746g-eval_spl_defconfig
index 26e430a..2756ad5 100644
--- a/configs/stm32746g-eval_spl_defconfig
+++ b/configs/stm32746g-eval_spl_defconfig
@@ -10,11 +10,11 @@
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20050000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="stm32746g-eval"
-CONFIG_SPL_TEXT_BASE=0x8000000
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0x8000000
 CONFIG_SYS_LOAD_ADDR=0x8009000
 CONFIG_SPL_SIZE_LIMIT=0x9000
 CONFIG_STM32F7=y
@@ -44,8 +44,8 @@
 CONFIG_CMD_MMC=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
 CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DNS=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIMER=y
@@ -53,8 +53,8 @@
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SPL_OF_TRANSLATE=y
diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig
index 2afe511..35a489c 100644
--- a/configs/stm32f746-disco_defconfig
+++ b/configs/stm32f746-disco_defconfig
@@ -27,16 +27,16 @@
 CONFIG_CMD_MMC=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
 CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DNS=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIMER=y
 # CONFIG_ISO_PARTITION is not set
 CONFIG_OF_CONTROL=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_ARM_PL180_MMCI=y
 CONFIG_MTD=y
 CONFIG_DM_MTD=y
diff --git a/configs/stm32f746-disco_spl_defconfig b/configs/stm32f746-disco_spl_defconfig
index 3ad86a0..6826b1c 100644
--- a/configs/stm32f746-disco_spl_defconfig
+++ b/configs/stm32f746-disco_spl_defconfig
@@ -10,11 +10,11 @@
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20050000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="stm32f746-disco"
-CONFIG_SPL_TEXT_BASE=0x8000000
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0x8000000
 CONFIG_SYS_LOAD_ADDR=0x8009000
 CONFIG_SPL_SIZE_LIMIT=0x9000
 CONFIG_STM32F7=y
@@ -44,8 +44,8 @@
 CONFIG_CMD_MMC=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
 CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DNS=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIMER=y
@@ -53,8 +53,8 @@
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SPL_OF_TRANSLATE=y
diff --git a/configs/stm32f769-disco_defconfig b/configs/stm32f769-disco_defconfig
index cb7c6d2..1e09c22 100644
--- a/configs/stm32f769-disco_defconfig
+++ b/configs/stm32f769-disco_defconfig
@@ -26,16 +26,16 @@
 CONFIG_CMD_MMC=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
 CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DNS=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIMER=y
 # CONFIG_ISO_PARTITION is not set
 CONFIG_OF_CONTROL=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_ARM_PL180_MMCI=y
 CONFIG_MTD=y
 CONFIG_DM_MTD=y
diff --git a/configs/stm32f769-disco_spl_defconfig b/configs/stm32f769-disco_spl_defconfig
index 9071904..787571d 100644
--- a/configs/stm32f769-disco_spl_defconfig
+++ b/configs/stm32f769-disco_spl_defconfig
@@ -10,11 +10,11 @@
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20050000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="stm32f769-disco"
-CONFIG_SPL_TEXT_BASE=0x8000000
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0x8000000
 CONFIG_SYS_LOAD_ADDR=0x8009000
 CONFIG_SPL_SIZE_LIMIT=0x9000
 CONFIG_STM32F7=y
@@ -43,8 +43,8 @@
 CONFIG_CMD_MMC=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
 CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_DNS=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIMER=y
@@ -52,8 +52,8 @@
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SPL_OF_TRANSLATE=y
diff --git a/configs/stm32mp13_dhcor_defconfig b/configs/stm32mp13_dhcor_defconfig
index 1ca057c..ff948b9 100644
--- a/configs/stm32mp13_dhcor_defconfig
+++ b/configs/stm32mp13_dhcor_defconfig
@@ -1,149 +1,46 @@
+#include <configs/stm32mp_dhsom.config>
+
 CONFIG_ARM=y
 CONFIG_ARCH_STM32MP=y
 CONFIG_TFABOOT=y
 CONFIG_SYS_MALLOC_F_LEN=0x1c0000
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0400000
-CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x3E0000
-CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp135f-dhcor-dhsbc"
-CONFIG_SYS_BOOTM_LEN=0x2000000
-CONFIG_SYS_LOAD_ADDR=0xc2000000
 CONFIG_STM32MP13X=y
 CONFIG_DDR_CACHEABLE_SIZE=0x8000000
-CONFIG_CMD_STM32KEY=y
 CONFIG_TARGET_ST_STM32MP13X=y
 CONFIG_ENV_OFFSET_REDUND=0x3F0000
-CONFIG_CMD_STM32PROG=y
 CONFIG_STM32MP15_PWR=y
 # CONFIG_ARMV7_NONSEC is not set
 CONFIG_SYS_MEMTEST_START=0xc0000000
 CONFIG_SYS_MEMTEST_END=0xc4000000
-# CONFIG_EFI_LOADER is not set
-CONFIG_FIT=y
-CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTSTAGE_RECORD_COUNT=100
 CONFIG_BOOTDELAY=3
-CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_PROMPT="STM32MP> "
-# CONFIG_CMD_ELF is not set
 CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_EXPORTENV is not set
 CONFIG_CMD_ERASEENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_UNZIP=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_FUSE=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
 CONFIG_CMD_LSBLK=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_CAT=y
 CONFIG_CMD_SETEXPR_FMT=y
 CONFIG_CMD_XXD=y
-CONFIG_CMD_DHCP6=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_SYS_DISABLE_AUTOLOAD=y
-CONFIG_CMD_WGET=y
-CONFIG_CMD_BOOTCOUNT=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
 CONFIG_CMD_RNG=y
-CONFIG_CMD_TIMER=y
-CONFIG_CMD_PMIC=y
-CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_BTRFS=y
-CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_LOG=y
 CONFIG_CMD_UBI=y
-# CONFIG_ISO_PARTITION is not set
-CONFIG_OF_LIVE=y
-CONFIG_OF_UPSTREAM=y
 CONFIG_ENV_IS_NOWHERE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_ENV_SPI_MAX_HZ=50000000
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_IP_DEFRAG=y
-CONFIG_TFTP_TSIZE=y
-CONFIG_PROT_TCP_SACK=y
-CONFIG_IPV6=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000
 CONFIG_CLK_SCMI=y
 CONFIG_SET_DFU_ALT_INFO=y
-CONFIG_GPIO_HOG=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_STM32F7=y
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_STM32_FMC2_EBI=y
-CONFIG_I2C_EEPROM=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x50
-CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_STM32_SDMMC2=y
-CONFIG_MTD=y
-CONFIG_DM_MTD=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SFDP_SUPPORT=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_SPI_FLASH_MTD=y
 CONFIG_PHY_REALTEK=y
-CONFIG_DWC_ETH_QOS=y
-CONFIG_PHY=y
-CONFIG_PHY_STM32_USBPHYC=y
-CONFIG_PINCONF=y
-CONFIG_DM_PMIC=y
-CONFIG_PMIC_STPMIC1=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_DM_REGULATOR_STPMIC1=y
 CONFIG_DM_REGULATOR_SCMI=y
 CONFIG_RESET_SCMI=y
 CONFIG_DM_RNG=y
 CONFIG_RNG_STM32=y
-CONFIG_DM_RTC=y
-CONFIG_RTC_STM32=y
-CONFIG_SERIAL_RX_BUFFER=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_STM32_QSPI=y
-CONFIG_STM32_SPI=y
 CONFIG_SYSRESET_PSCI=y
 CONFIG_TEE=y
 CONFIG_OPTEE=y
 # CONFIG_OPTEE_TA_AVB is not set
-CONFIG_USB=y
-CONFIG_DM_USB_GADGET=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_GENERIC=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_GENERIC=y
-CONFIG_USB_DWC2=y
 CONFIG_USB_ONBOARD_HUB=y
 CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=2000
-CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_ASIX=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="dh"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0483
-CONFIG_USB_GADGET_PRODUCT_NUM=0x5720
-CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_WDT=y
-CONFIG_WDT_STM32MP=y
-CONFIG_FAT_WRITE=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig b/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig
index 0b5ada7..4e17120 100644
--- a/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig
+++ b/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig
@@ -5,9 +5,9 @@
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000
 CONFIG_ENV_OFFSET=0x280000
 CONFIG_DEFAULT_DEVICE_TREE="stm32mp157a-icore-stm32mp1-ctouch2"
-CONFIG_SPL_TEXT_BASE=0x2FFC2500
 CONFIG_SPL_MMC=y
 CONFIG_SPL_STACK=0x30000000
+CONFIG_SPL_TEXT_BASE=0x2FFC2500
 CONFIG_SYS_BOOTM_LEN=0x2000000
 CONFIG_SYS_LOAD_ADDR=0xc2000000
 CONFIG_SPL=y
diff --git a/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig b/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig
index 7a5a75f..3f7eebd 100644
--- a/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig
+++ b/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig
@@ -5,9 +5,9 @@
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000
 CONFIG_ENV_OFFSET=0x280000
 CONFIG_DEFAULT_DEVICE_TREE="stm32mp157a-icore-stm32mp1-edimm2.2"
-CONFIG_SPL_TEXT_BASE=0x2FFC2500
 CONFIG_SPL_MMC=y
 CONFIG_SPL_STACK=0x30000000
+CONFIG_SPL_TEXT_BASE=0x2FFC2500
 CONFIG_SYS_BOOTM_LEN=0x2000000
 CONFIG_SYS_LOAD_ADDR=0xc2000000
 CONFIG_SPL=y
diff --git a/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig b/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig
index 38aa867..b32f71d 100644
--- a/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig
+++ b/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig
@@ -5,9 +5,9 @@
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000
 CONFIG_ENV_OFFSET=0x280000
 CONFIG_DEFAULT_DEVICE_TREE="stm32mp157a-microgea-stm32mp1-microdev2.0-of7"
-CONFIG_SPL_TEXT_BASE=0x2FFC2500
 CONFIG_SPL_MMC=y
 CONFIG_SPL_STACK=0x30000000
+CONFIG_SPL_TEXT_BASE=0x2FFC2500
 CONFIG_SYS_BOOTM_LEN=0x2000000
 CONFIG_SYS_LOAD_ADDR=0xc2000000
 CONFIG_SPL=y
diff --git a/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig b/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig
index b0c272b..8a16216 100644
--- a/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig
+++ b/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig
@@ -5,9 +5,9 @@
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000
 CONFIG_ENV_OFFSET=0x280000
 CONFIG_DEFAULT_DEVICE_TREE="stm32mp157a-microgea-stm32mp1-microdev2.0"
-CONFIG_SPL_TEXT_BASE=0x2FFC2500
 CONFIG_SPL_MMC=y
 CONFIG_SPL_STACK=0x30000000
+CONFIG_SPL_TEXT_BASE=0x2FFC2500
 CONFIG_SYS_BOOTM_LEN=0x2000000
 CONFIG_SYS_LOAD_ADDR=0xc2000000
 CONFIG_SPL=y
diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig
index 8914b64..1c0d0d0 100644
--- a/configs/stm32mp15_basic_defconfig
+++ b/configs/stm32mp15_basic_defconfig
@@ -7,9 +7,9 @@
 CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1"
-CONFIG_SPL_TEXT_BASE=0x2FFC2500
 CONFIG_SPL_MMC=y
 CONFIG_SPL_STACK=0x30000000
+CONFIG_SPL_TEXT_BASE=0x2FFC2500
 CONFIG_SYS_BOOTM_LEN=0x2000000
 CONFIG_SYS_LOAD_ADDR=0xc2000000
 CONFIG_SPL=y
diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig
index a92c615d..b730bf7 100644
--- a/configs/stm32mp15_dhcom_basic_defconfig
+++ b/configs/stm32mp15_dhcom_basic_defconfig
@@ -1,181 +1,11 @@
+#include <configs/stm32mp15_dhsom.config>
+
 CONFIG_ARM=y
 CONFIG_ARCH_STM32MP=y
-CONFIG_SYS_MALLOC_F_LEN=0x3000
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000
-CONFIG_SF_DEFAULT_SPEED=50000000
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_SECT_SIZE=0x1000
-CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp157c-dhcom-pdk2"
-CONFIG_SPL_TEXT_BASE=0x2FFC2500
-CONFIG_SPL_MMC=y
-CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0x5C00A14C
-CONFIG_SPL_STACK=0x30000000
-CONFIG_SYS_BOOTM_LEN=0x2000000
-CONFIG_SYS_LOAD_ADDR=0xc2000000
-CONFIG_SPL=y
-CONFIG_CMD_STM32KEY=y
-CONFIG_CMD_STBOARD=y
-CONFIG_TARGET_DH_STM32MP1_PDK2=y
-CONFIG_CMD_STM32PROG=y
-CONFIG_CMD_STM32PROG_OTP=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI=y
-# CONFIG_ARMV7_VIRT is not set
 CONFIG_SYS_MEMTEST_START=0xc0000000
 CONFIG_SYS_MEMTEST_END=0xc4000000
-CONFIG_HAS_BOARD_SIZE_LIMIT=y
-CONFIG_BOARD_SIZE_LIMIT=1441792
-# CONFIG_EFI_LOADER is not set
-CONFIG_FIT=y
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_LOAD_FIT_ADDRESS=0xc1000000
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTDELAY=1
-CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
-CONFIG_SYS_PBSIZE=1050
-CONFIG_CONSOLE_MUX=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_FOOTPRINT_LIMIT=y
-CONFIG_SPL_MAX_FOOTPRINT=0x3db00
-CONFIG_SPL_BOOTCOUNT_LIMIT=y
-CONFIG_SPL_LEGACY_IMAGE_FORMAT=y
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_SYS_MALLOC=y
-CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
-CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000
-CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C=y
-CONFIG_SPL_MTD=y
-CONFIG_SPL_DM_SPI_FLASH=y
-CONFIG_SPL_POWER=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_SPI_FLASH_MTD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
-CONFIG_SYS_PROMPT="STM32MP> "
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_EXPORTENV is not set
-CONFIG_CMD_EEPROM=y
 CONFIG_SYS_I2C_EEPROM_BUS=3
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_UNZIP=y
-CONFIG_CMD_ADC=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_FUSE=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_REMOTEPROC=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_DHCP6=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_SYS_DISABLE_AUTOLOAD=y
-CONFIG_CMD_WGET=y
-CONFIG_CMD_BOOTCOUNT=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_TIMER=y
-CONFIG_CMD_PMIC=y
-CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_BTRFS=y
-CONFIG_CMD_EXT4_WRITE=y
-# CONFIG_SPL_DOS_PARTITION is not set
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_SPL_PARTITION_UUIDS is not set
-CONFIG_OF_LIVE=y
-CONFIG_OF_UPSTREAM=y
 CONFIG_OF_LIST="st/stm32mp157c-dhcom-pdk2 st/stm32mp153c-dhcom-drc02 st/stm32mp157c-dhcom-picoitx"
 CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SPL_ENV_IS_NOWHERE=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_IP_DEFRAG=y
-CONFIG_TFTP_TSIZE=y
-CONFIG_USE_SERVERIP=y
-CONFIG_SERVERIP="192.168.1.1"
-CONFIG_PROT_TCP_SACK=y
-CONFIG_IPV6=y
-CONFIG_STM32_ADC=y
-CONFIG_SPL_BLOCK_CACHE=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000
-CONFIG_GPIO_HOG=y
-CONFIG_DM_HWSPINLOCK=y
-CONFIG_HWSPINLOCK_STM32=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_STM32F7=y
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_STM32_FMC2_EBI=y
-CONFIG_I2C_EEPROM=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x50
-CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_STM32_SDMMC2=y
-CONFIG_MTD=y
-CONFIG_DM_MTD=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SFDP_SUPPORT=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_SPI_FLASH_MTD=y
-CONFIG_PHY_ANEG_TIMEOUT=20000
-CONFIG_DWC_ETH_QOS=y
-CONFIG_KS8851_MLL=y
-CONFIG_PHY=y
-CONFIG_SPL_PHY=y
-CONFIG_PHY_STM32_USBPHYC=y
-CONFIG_PINCONF=y
-# CONFIG_SPL_PINCTRL_FULL is not set
-CONFIG_PINCTRL_STMFX=y
-CONFIG_DM_PMIC=y
-CONFIG_PMIC_STPMIC1=y
-CONFIG_DM_REGULATOR=y
-CONFIG_SPL_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_DM_REGULATOR_STM32_VREFBUF=y
-CONFIG_DM_REGULATOR_STPMIC1=y
-CONFIG_SPL_DM_REGULATOR_STPMIC1=y
-CONFIG_REMOTEPROC_STM32_COPRO=y
-CONFIG_DM_RTC=y
-CONFIG_RTC_STM32=y
-CONFIG_SERIAL_RX_BUFFER=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_STM32_QSPI=y
-CONFIG_STM32_SPI=y
-CONFIG_SYSRESET_SYSCON=y
-CONFIG_USB=y
-CONFIG_DM_USB_GADGET=y
-CONFIG_SPL_DM_USB_GADGET=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_GENERIC=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_GENERIC=y
-CONFIG_USB_DWC2=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_ASIX=y
-CONFIG_USB_GADGET=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="dh"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0483
-CONFIG_USB_GADGET_PRODUCT_NUM=0x5720
-CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_SPL_DFU=y
-CONFIG_WDT=y
-CONFIG_WDT_STM32MP=y
-CONFIG_FAT_WRITE=y
-# CONFIG_BINMAN_FDT is not set
diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig
index 4162eda..42a5965 100644
--- a/configs/stm32mp15_dhcor_basic_defconfig
+++ b/configs/stm32mp15_dhcor_basic_defconfig
@@ -1,181 +1,11 @@
+#include <configs/stm32mp15_dhsom.config>
+
 CONFIG_ARM=y
 CONFIG_ARCH_STM32MP=y
-CONFIG_SYS_MALLOC_F_LEN=0x3000
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000
-CONFIG_SF_DEFAULT_SPEED=50000000
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_SECT_SIZE=0x1000
-CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp157a-dhcor-avenger96"
-CONFIG_SPL_TEXT_BASE=0x2FFC2500
-CONFIG_SPL_MMC=y
-CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0x5C00A14C
-CONFIG_SPL_STACK=0x30000000
-CONFIG_SYS_BOOTM_LEN=0x2000000
-CONFIG_SYS_LOAD_ADDR=0xc2000000
-CONFIG_SPL=y
-CONFIG_CMD_STM32KEY=y
-CONFIG_CMD_STBOARD=y
-CONFIG_TARGET_DH_STM32MP1_PDK2=y
-CONFIG_CMD_STM32PROG=y
-CONFIG_CMD_STM32PROG_OTP=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI=y
-# CONFIG_ARMV7_VIRT is not set
-CONFIG_HAS_BOARD_SIZE_LIMIT=y
-CONFIG_BOARD_SIZE_LIMIT=1441792
-# CONFIG_EFI_LOADER is not set
-CONFIG_FIT=y
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_LOAD_FIT_ADDRESS=0xc1000000
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTDELAY=1
-CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
-CONFIG_SYS_PBSIZE=1050
-CONFIG_CONSOLE_MUX=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_FOOTPRINT_LIMIT=y
-CONFIG_SPL_MAX_FOOTPRINT=0x3db00
-CONFIG_SPL_BOOTCOUNT_LIMIT=y
-CONFIG_SPL_LEGACY_IMAGE_FORMAT=y
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_SYS_MALLOC=y
-CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
-CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000
-CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C=y
-CONFIG_SPL_MTD=y
-CONFIG_SPL_DM_SPI_FLASH=y
-CONFIG_SPL_POWER=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_SPI_FLASH_MTD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
-CONFIG_SYS_PROMPT="STM32MP> "
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_EXPORTENV is not set
-CONFIG_CMD_EEPROM=y
 CONFIG_SYS_I2C_EEPROM_BUS=2
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_UNZIP=y
-CONFIG_CMD_ADC=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_FUSE=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_REMOTEPROC=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_DHCP6=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_SYS_DISABLE_AUTOLOAD=y
-CONFIG_CMD_WGET=y
-CONFIG_CMD_BOOTCOUNT=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_TIMER=y
-CONFIG_CMD_PMIC=y
-CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_BTRFS=y
-CONFIG_CMD_EXT4_WRITE=y
-# CONFIG_SPL_DOS_PARTITION is not set
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_SPL_PARTITION_UUIDS is not set
-CONFIG_OF_LIVE=y
-CONFIG_OF_UPSTREAM=y
 CONFIG_OF_LIST="st/stm32mp157a-dhcor-avenger96 st/stm32mp151a-dhcor-testbench st/stm32mp153c-dhcor-drc-compact"
 CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SPL_ENV_IS_NOWHERE=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_IP_DEFRAG=y
-CONFIG_TFTP_TSIZE=y
-CONFIG_USE_SERVERIP=y
-CONFIG_SERVERIP="192.168.1.1"
-CONFIG_PROT_TCP_SACK=y
-CONFIG_IPV6=y
-CONFIG_STM32_ADC=y
-CONFIG_SPL_BLOCK_CACHE=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000
-CONFIG_GPIO_HOG=y
-CONFIG_DM_HWSPINLOCK=y
-CONFIG_HWSPINLOCK_STM32=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_STM32F7=y
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_STM32_FMC2_EBI=y
-CONFIG_I2C_EEPROM=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x53
-CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_STM32_SDMMC2=y
-CONFIG_MTD=y
-CONFIG_DM_MTD=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SFDP_SUPPORT=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_SPI_FLASH_MTD=y
-CONFIG_PHY_ANEG_TIMEOUT=20000
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_DWC_ETH_QOS=y
-CONFIG_KS8851_MLL=y
-CONFIG_PHY=y
-CONFIG_SPL_PHY=y
-CONFIG_PHY_STM32_USBPHYC=y
-CONFIG_PINCONF=y
-# CONFIG_SPL_PINCTRL_FULL is not set
-CONFIG_PINCTRL_STMFX=y
-CONFIG_DM_PMIC=y
-CONFIG_PMIC_STPMIC1=y
-CONFIG_DM_REGULATOR=y
-CONFIG_SPL_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_DM_REGULATOR_STM32_VREFBUF=y
-CONFIG_DM_REGULATOR_STPMIC1=y
-CONFIG_SPL_DM_REGULATOR_STPMIC1=y
-CONFIG_REMOTEPROC_STM32_COPRO=y
-CONFIG_DM_RTC=y
-CONFIG_RTC_STM32=y
-CONFIG_SERIAL_RX_BUFFER=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_STM32_QSPI=y
-CONFIG_STM32_SPI=y
-CONFIG_SYSRESET_SYSCON=y
-CONFIG_USB=y
-CONFIG_DM_USB_GADGET=y
-CONFIG_SPL_DM_USB_GADGET=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_GENERIC=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_GENERIC=y
-CONFIG_USB_DWC2=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_ASIX=y
-CONFIG_USB_GADGET=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="dh"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0483
-CONFIG_USB_GADGET_PRODUCT_NUM=0x5720
-CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_SPL_DFU=y
-CONFIG_WDT=y
-CONFIG_WDT_STM32MP=y
-CONFIG_FAT_WRITE=y
-# CONFIG_BINMAN_FDT is not set
diff --git a/configs/stm32mp15_dhsom.config b/configs/stm32mp15_dhsom.config
new file mode 100644
index 0000000..efc1495
--- /dev/null
+++ b/configs/stm32mp15_dhsom.config
@@ -0,0 +1,70 @@
+#include <configs/stm32mp_dhsom.config>
+
+# CONFIG_ARMV7_VIRT is not set
+# CONFIG_BINMAN_FDT is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_PARTITION_UUIDS is not set
+# CONFIG_SPL_PINCTRL_FULL is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_SIZE_LIMIT=1441792
+CONFIG_BOOTCOUNT_BOOTLIMIT=3
+CONFIG_BOOTDELAY=1
+CONFIG_CMD_ADC=y
+CONFIG_CMD_REMOTEPROC=y
+CONFIG_CMD_STBOARD=y
+CONFIG_CMD_STM32PROG_OTP=y
+CONFIG_CONSOLE_MUX=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000
+CONFIG_DM_HWSPINLOCK=y
+CONFIG_DM_REGULATOR_STM32_VREFBUF=y
+CONFIG_HAS_BOARD_SIZE_LIMIT=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_HWSPINLOCK_STM32=y
+CONFIG_KS8851_MLL=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
+CONFIG_PINCTRL_STMFX=y
+CONFIG_REMOTEPROC_STM32_COPRO=y
+CONFIG_SERVERIP="192.168.1.1"
+CONFIG_SF_DEFAULT_SPEED=50000000
+CONFIG_SPL=y
+CONFIG_SPL_BLOCK_CACHE=y
+CONFIG_SPL_BOOTCOUNT_LIMIT=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000
+CONFIG_SPL_DFU=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR_STPMIC1=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_SPL_ENV_IS_NOWHERE=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_FOOTPRINT_LIMIT=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_LEGACY_IMAGE_FORMAT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0xc1000000
+CONFIG_SPL_MAX_FOOTPRINT=0x3db00
+CONFIG_SPL_MMC=y
+CONFIG_SPL_MTD=y
+CONFIG_SPL_PHY=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_SPI=y
+CONFIG_SPL_SPI_FLASH_MTD=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_STACK=0x30000000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000
+CONFIG_SPL_TEXT_BASE=0x2FFC2500
+CONFIG_SPL_USB_GADGET=y
+CONFIG_STM32_ADC=y
+CONFIG_SYSRESET_SYSCON=y
+CONFIG_SYS_BOOTCOUNT_ADDR=0x5C00A14C
+CONFIG_SYS_MALLOC_F_LEN=0x3000
+CONFIG_SYS_PBSIZE=1050
+CONFIG_PREBOOT="run dh_preboot"
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
+CONFIG_TARGET_DH_STM32MP1_PDK2=y
+CONFIG_USE_SERVERIP=y
diff --git a/configs/stm32mp_dhsom.config b/configs/stm32mp_dhsom.config
new file mode 100644
index 0000000..01d65cf
--- /dev/null
+++ b/configs/stm32mp_dhsom.config
@@ -0,0 +1,105 @@
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_CMD_BOOTCOUNT=y
+CONFIG_CMD_BTRFS=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_DHCP6=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_STM32KEY=y
+CONFIG_CMD_STM32PROG=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_UNZIP=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_WGET=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MTD=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_REGULATOR_STPMIC1=y
+CONFIG_DM_RTC=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_FAT_WRITE=y
+CONFIG_FIT=y
+CONFIG_GPIO_HOG=y
+CONFIG_I2C_EEPROM=y
+CONFIG_IPV6=y
+CONFIG_IP_DEFRAG=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MTD=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_UPSTREAM=y
+CONFIG_PHY=y
+CONFIG_PHY_STM32_USBPHYC=y
+CONFIG_PINCONF=y
+CONFIG_PMIC_STPMIC1=y
+CONFIG_PROT_TCP_SACK=y
+CONFIG_RTC_STM32=y
+CONFIG_SERIAL_RX_BUFFER=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_STM32_FMC2_EBI=y
+CONFIG_STM32_QSPI=y
+CONFIG_STM32_SDMMC2=y
+CONFIG_STM32_SPI=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000
+CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_SYS_DISABLE_AUTOLOAD=y
+CONFIG_SYS_I2C_STM32F7=y
+CONFIG_SYS_LOAD_ADDR=0xc2000000
+CONFIG_SYS_PROMPT="STM32MP> "
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_TFTP_TSIZE=y
+CONFIG_USB=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_MANUFACTURER="dh"
+CONFIG_USB_GADGET_PRODUCT_NUM=0x5720
+CONFIG_USB_GADGET_VENDOR_NUM=0x0483
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_WDT=y
+CONFIG_WDT_STM32MP=y
diff --git a/configs/surface-rt_defconfig b/configs/surface-rt_defconfig
index c1fd4a5..b5c84b4 100644
--- a/configs/surface-rt_defconfig
+++ b/configs/surface-rt_defconfig
@@ -9,8 +9,8 @@
 CONFIG_ENV_SIZE=0x3000
 CONFIG_ENV_OFFSET=0xFFFFD000
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-microsoft-surface-rt"
-CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SPL_STACK=0x800ffffc
+CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SYS_LOAD_ADDR=0x82000000
 CONFIG_TEGRA30=y
 CONFIG_TARGET_SURFACE_RT=y
diff --git a/configs/tec-ng_defconfig b/configs/tec-ng_defconfig
index 26a37d2..5e840ff 100644
--- a/configs/tec-ng_defconfig
+++ b/configs/tec-ng_defconfig
@@ -7,8 +7,8 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFE000
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-tec-ng"
-CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SPL_STACK=0x800ffffc
+CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SYS_LOAD_ADDR=0x81000000
 CONFIG_TEGRA30=y
 CONFIG_TARGET_TEC_NG=y
diff --git a/configs/tec_defconfig b/configs/tec_defconfig
index 5fd214d..3d46c9e 100644
--- a/configs/tec_defconfig
+++ b/configs/tec_defconfig
@@ -6,8 +6,8 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x1FFE0000
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-tec"
-CONFIG_SPL_TEXT_BASE=0x00108000
 CONFIG_SPL_STACK=0xffffc
+CONFIG_SPL_TEXT_BASE=0x00108000
 CONFIG_SYS_LOAD_ADDR=0x1000000
 CONFIG_TEGRA20=y
 CONFIG_TARGET_TEC=y
diff --git a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig
index bd5dd98..fed54bc 100644
--- a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig
+++ b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig
@@ -35,8 +35,8 @@
 CONFIG_CMD_PART=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_TIME=y
diff --git a/configs/theadorable-x86-conga-qa3-e3845_defconfig b/configs/theadorable-x86-conga-qa3-e3845_defconfig
index e93178a..af81e78 100644
--- a/configs/theadorable-x86-conga-qa3-e3845_defconfig
+++ b/configs/theadorable-x86-conga-qa3-e3845_defconfig
@@ -34,8 +34,8 @@
 CONFIG_CMD_PART=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_TIME=y
diff --git a/configs/theadorable-x86-dfi-bt700_defconfig b/configs/theadorable-x86-dfi-bt700_defconfig
index 4905ba6..0c9e609 100644
--- a/configs/theadorable-x86-dfi-bt700_defconfig
+++ b/configs/theadorable-x86-dfi-bt700_defconfig
@@ -32,8 +32,8 @@
 CONFIG_CMD_PART=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_TIME=y
diff --git a/configs/theadorable_debug_defconfig b/configs/theadorable_debug_defconfig
index 5a075c5..f957167 100644
--- a/configs/theadorable_debug_defconfig
+++ b/configs/theadorable_debug_defconfig
@@ -13,9 +13,9 @@
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable"
-CONFIG_SPL_TEXT_BASE=0x40004030
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK=0x4002c000
+CONFIG_SPL_TEXT_BASE=0x40004030
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x40020000
 CONFIG_SPL_BSS_MAX_SIZE=0x4000
@@ -48,8 +48,8 @@
 CONFIG_CMD_PCI=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
 CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_BMP=y
diff --git a/configs/tools-only_defconfig b/configs/tools-only_defconfig
index cecd261..5e3a46b 100644
--- a/configs/tools-only_defconfig
+++ b/configs/tools-only_defconfig
@@ -4,27 +4,27 @@
 CONFIG_DEFAULT_DEVICE_TREE="sandbox"
 CONFIG_SYS_LOAD_ADDR=0x0
 CONFIG_PCI=y
-CONFIG_SANDBOX_SDL=n
-CONFIG_EFI_LOADER=n
+# CONFIG_SANDBOX_SDL is not set
+# CONFIG_EFI_LOADER is not set
 CONFIG_ANDROID_BOOT_IMAGE=y
 CONFIG_TIMESTAMP=y
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
-CONFIG_BOOTSTD_FULL=n
-CONFIG_BOOTMETH_CROS=n
-CONFIG_BOOTMETH_VBE=n
+# CONFIG_BOOTSTD_FULL is not set
+# CONFIG_BOOTMETH_CROS is not set
+# CONFIG_BOOTMETH_VBE is not set
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="run distro_bootcmd"
-CONFIG_CMD_BOOTD=n
-CONFIG_CMD_BOOTM=n
-CONFIG_CMD_BOOTI=n
-CONFIG_CMD_ELF=n
-CONFIG_CMD_EXTENSION=n
-CONFIG_CMD_DATE=n
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTM is not set
+# CONFIG_CMD_BOOTI is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_EXTENSION is not set
+# CONFIG_CMD_DATE is not set
 CONFIG_OF_CONTROL=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NO_NET=y
-CONFIG_ACPIGEN=n
+# CONFIG_ACPIGEN is not set
 CONFIG_AXI=y
 CONFIG_AXI_SANDBOX=y
 CONFIG_SANDBOX_GPIO=y
@@ -33,8 +33,8 @@
 CONFIG_SOUND=y
 CONFIG_SYSRESET=y
 CONFIG_TIMER=y
-CONFIG_VIRTIO_MMIO=n
-CONFIG_VIRTIO_PCI=n
-CONFIG_VIRTIO_SANDBOX=n
-CONFIG_GENERATE_ACPI_TABLE=n
+# CONFIG_VIRTIO_MMIO is not set
+# CONFIG_VIRTIO_PCI is not set
+# CONFIG_VIRTIO_SANDBOX is not set
+# CONFIG_GENERATE_ACPI_TABLE is not set
 CONFIG_TOOLS_MKEFICAPSULE=y
diff --git a/configs/total_compute_defconfig b/configs/total_compute_defconfig
index e0d6199..70bec3b 100644
--- a/configs/total_compute_defconfig
+++ b/configs/total_compute_defconfig
@@ -22,9 +22,6 @@
 CONFIG_SYS_PBSIZE=544
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_AVB_VERIFY=y
-CONFIG_AVB_BUF_ADDR=0x90000000
-CONFIG_AVB_BUF_SIZE=0x10000000
 CONFIG_SYS_PROMPT="TOTAL_COMPUTE# "
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_XIMG is not set
@@ -38,7 +35,6 @@
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_CACHE=y
 # CONFIG_CMD_SLEEP is not set
-CONFIG_CMD_AVB=y
 CONFIG_CMD_UBI=y
 # CONFIG_ISO_PARTITION is not set
 CONFIG_OF_CONTROL=y
@@ -59,4 +55,3 @@
 CONFIG_SYS_MAX_FLASH_SECT=256
 # CONFIG_RANDOM_UUID is not set
 CONFIG_LIBAVB=y
-CONFIG_ENV_SOURCE_FILE=total_compute
diff --git a/configs/transformer_t20_defconfig b/configs/transformer_t20_defconfig
index df993c3..b693665 100644
--- a/configs/transformer_t20_defconfig
+++ b/configs/transformer_t20_defconfig
@@ -9,8 +9,8 @@
 CONFIG_ENV_SIZE=0x3000
 CONFIG_ENV_OFFSET=0xFFFFD000
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-asus-tf101"
-CONFIG_SPL_TEXT_BASE=0x00108000
 CONFIG_SPL_STACK=0xffffc
+CONFIG_SPL_TEXT_BASE=0x00108000
 CONFIG_SYS_LOAD_ADDR=0x2000000
 CONFIG_TEGRA20=y
 CONFIG_TARGET_TRANSFORMER_T20=y
diff --git a/configs/transformer_t30_defconfig b/configs/transformer_t30_defconfig
index 9102dcc..c5f0bc2 100644
--- a/configs/transformer_t30_defconfig
+++ b/configs/transformer_t30_defconfig
@@ -9,8 +9,8 @@
 CONFIG_ENV_SIZE=0x3000
 CONFIG_ENV_OFFSET=0xFFFFD000
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf201"
-CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SPL_STACK=0x800ffffc
+CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SYS_LOAD_ADDR=0x82000000
 CONFIG_TEGRA30=y
 CONFIG_TARGET_TRANSFORMER_T30=y
diff --git a/configs/trimslice_defconfig b/configs/trimslice_defconfig
index c797275..c04fc1a 100644
--- a/configs/trimslice_defconfig
+++ b/configs/trimslice_defconfig
@@ -8,8 +8,8 @@
 CONFIG_ENV_OFFSET=0xFE000
 CONFIG_ENV_SECT_SIZE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-trimslice"
-CONFIG_SPL_TEXT_BASE=0x00108000
 CONFIG_SPL_STACK=0xffffc
+CONFIG_SPL_TEXT_BASE=0x00108000
 CONFIG_SYS_LOAD_ADDR=0x1000000
 CONFIG_TEGRA20=y
 CONFIG_TARGET_TRIMSLICE=y
diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig
index 3a32bc8..d1b7719 100644
--- a/configs/tuge1_defconfig
+++ b/configs/tuge1_defconfig
@@ -119,11 +119,10 @@
 CONFIG_CMD_I2C=y
 CONFIG_LOADS_ECHO=y
 CONFIG_SYS_LOADS_BAUD_CHANGE=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
-CONFIG_CMD_JFFS2=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=boot"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);"
diff --git a/configs/turris_1x_nor_defconfig b/configs/turris_1x_nor_defconfig
index 52819b1..a96fae1 100644
--- a/configs/turris_1x_nor_defconfig
+++ b/configs/turris_1x_nor_defconfig
@@ -46,8 +46,8 @@
 CONFIG_CMD_PCI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_WDT=y
-CONFIG_CMD_DHCP=y
 CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_BTRFS=y
 CONFIG_CMD_EXT2=y
diff --git a/configs/turris_1x_sdcard_defconfig b/configs/turris_1x_sdcard_defconfig
index ec4717e..719a394 100644
--- a/configs/turris_1x_sdcard_defconfig
+++ b/configs/turris_1x_sdcard_defconfig
@@ -6,10 +6,10 @@
 CONFIG_NR_DRAM_BANKS=5
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SYS_MONITOR_LEN=1048576
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SYS_LOAD_ADDR=0x1000000
 CONFIG_SPL=y
 CONFIG_DEBUG_UART_BASE=0xffe04500
diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig
index dd1a45b..bdcc740 100644
--- a/configs/turris_omnia_defconfig
+++ b/configs/turris_omnia_defconfig
@@ -19,9 +19,9 @@
 CONFIG_ENV_OFFSET=0xF0000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="armada-385-turris-omnia"
-CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK=0x4002c000
+CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x40023000
 CONFIG_SPL_BSS_MAX_SIZE=0x4000
diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig
index c12b8e9..1dc737e 100644
--- a/configs/tuxx1_defconfig
+++ b/configs/tuxx1_defconfig
@@ -133,11 +133,10 @@
 CONFIG_CMD_I2C=y
 CONFIG_LOADS_ECHO=y
 CONFIG_SYS_LOADS_BAUD_CHANGE=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
-CONFIG_CMD_JFFS2=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=boot"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);"
diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig
index 0aed619..a0fea87 100644
--- a/configs/uniphier_ld4_sld8_defconfig
+++ b/configs/uniphier_ld4_sld8_defconfig
@@ -6,11 +6,11 @@
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x84000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld4-ref"
-CONFIG_SPL_TEXT_BASE=0x00040000
 CONFIG_SYS_MONITOR_LEN=2097152
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK=0x100000
+CONFIG_SPL_TEXT_BASE=0x00040000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
 CONFIG_SYS_BOOTM_LEN=0x2000000
 CONFIG_SYS_LOAD_ADDR=0x85000000
@@ -50,7 +50,6 @@
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_USE_BOOTFILE=y
 CONFIG_BOOTFILE="zImage"
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_USE_GATEWAYIP=y
 CONFIG_GATEWAYIP="192.168.11.1"
 CONFIG_USE_IPADDR=y
@@ -61,6 +60,7 @@
 CONFIG_ROOTPATH="/nfs/root/path"
 CONFIG_USE_SERVERIP=y
 CONFIG_SERVERIP="192.168.11.1"
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_GPIO_UNIPHIER=y
 CONFIG_MISC=y
 CONFIG_I2C_EEPROM=y
diff --git a/configs/uniphier_v7_defconfig b/configs/uniphier_v7_defconfig
index 1939fa1..12647bb 100644
--- a/configs/uniphier_v7_defconfig
+++ b/configs/uniphier_v7_defconfig
@@ -6,11 +6,11 @@
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x84000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="uniphier-pxs2-vodka"
-CONFIG_SPL_TEXT_BASE=0x00100000
 CONFIG_SYS_MONITOR_LEN=2097152
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK=0x100000
+CONFIG_SPL_TEXT_BASE=0x00100000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
 CONFIG_SYS_BOOTM_LEN=0x2000000
 CONFIG_SYS_LOAD_ADDR=0x85000000
@@ -51,7 +51,6 @@
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_USE_BOOTFILE=y
 CONFIG_BOOTFILE="zImage"
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_USE_GATEWAYIP=y
 CONFIG_GATEWAYIP="192.168.11.1"
 CONFIG_USE_IPADDR=y
@@ -62,6 +61,7 @@
 CONFIG_ROOTPATH="/nfs/root/path"
 CONFIG_USE_SERVERIP=y
 CONFIG_SERVERIP="192.168.11.1"
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_GPIO_UNIPHIER=y
 CONFIG_MISC=y
 CONFIG_I2C_EEPROM=y
diff --git a/configs/uniphier_v8_defconfig b/configs/uniphier_v8_defconfig
index 5dfd428..e77d793 100644
--- a/configs/uniphier_v8_defconfig
+++ b/configs/uniphier_v8_defconfig
@@ -38,7 +38,6 @@
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_USE_BOOTFILE=y
 CONFIG_BOOTFILE="Image"
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_USE_GATEWAYIP=y
 CONFIG_GATEWAYIP="192.168.11.1"
 CONFIG_USE_IPADDR=y
@@ -49,6 +48,7 @@
 CONFIG_ROOTPATH="/nfs/root/path"
 CONFIG_USE_SERVERIP=y
 CONFIG_SERVERIP="192.168.11.1"
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_GPIO_UNIPHIER=y
 CONFIG_MISC=y
 CONFIG_I2C_EEPROM=y
diff --git a/configs/usb_a9263_dataflash_defconfig b/configs/usb_a9263_dataflash_defconfig
index b23e273..d7fb61c 100644
--- a/configs/usb_a9263_dataflash_defconfig
+++ b/configs/usb_a9263_dataflash_defconfig
@@ -29,8 +29,8 @@
 CONFIG_CMD_NAND=y
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_MTDPARTS_DEFAULT="mtdparts=atmel_nand:16m(kernel)ro,120m(root1),-(root2)"
 CONFIG_OF_CONTROL=y
diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig
index 821fa33..dfe821b 100644
--- a/configs/venice2_defconfig
+++ b/configs/venice2_defconfig
@@ -8,8 +8,8 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFE000
 CONFIG_DEFAULT_DEVICE_TREE="tegra124-venice2"
-CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SPL_STACK=0x800ffffc
+CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SYS_LOAD_ADDR=0x81000000
 CONFIG_TEGRA124=y
 CONFIG_TARGET_VENICE2=y
diff --git a/configs/ventana_defconfig b/configs/ventana_defconfig
index 77a8738..1357f5f 100644
--- a/configs/ventana_defconfig
+++ b/configs/ventana_defconfig
@@ -6,8 +6,8 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFE000
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-ventana"
-CONFIG_SPL_TEXT_BASE=0x00108000
 CONFIG_SPL_STACK=0xffffc
+CONFIG_SPL_TEXT_BASE=0x00108000
 CONFIG_SYS_LOAD_ADDR=0x1000000
 CONFIG_TEGRA20=y
 CONFIG_TARGET_VENTANA=y
diff --git a/configs/verdin-am62_a53_defconfig b/configs/verdin-am62_a53_defconfig
index ff2771e..49fb979 100644
--- a/configs/verdin-am62_a53_defconfig
+++ b/configs/verdin-am62_a53_defconfig
@@ -15,13 +15,13 @@
 CONFIG_ENV_OFFSET=0xFFFFDE00
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am625-verdin-wifi-dev"
-CONFIG_SPL_TEXT_BASE=0x80080000
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_TEXT_BASE=0x80080000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x80c80000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
@@ -102,8 +102,8 @@
 CONFIG_USE_ETHPRIME=y
 CONFIG_ETHPRIME="eth0"
 CONFIG_VERSION_VARIABLE=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_IP_DEFRAG=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_TFTP_BLOCKSIZE=4096
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
diff --git a/configs/verdin-am62_r5_defconfig b/configs/verdin-am62_r5_defconfig
index 4a7da1a..220469a 100644
--- a/configs/verdin-am62_r5_defconfig
+++ b/configs/verdin-am62_r5_defconfig
@@ -12,13 +12,13 @@
 CONFIG_ENV_SIZE=0x20000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="k3-am625-verdin-r5"
-CONFIG_SPL_TEXT_BASE=0x43c00000
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x7000
+CONFIG_SPL_TEXT_BASE=0x43c00000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x43c3b000
 CONFIG_SPL_BSS_MAX_SIZE=0x3000
diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig
index abb458d..b54028f 100644
--- a/configs/verdin-imx8mm_defconfig
+++ b/configs/verdin-imx8mm_defconfig
@@ -9,7 +9,6 @@
 CONFIG_ENV_OFFSET=0xFFFFDE00
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-verdin-wifi-dev"
-CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_TARGET_VERDIN_IMX8MM=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_MONITOR_LEN=524288
@@ -17,6 +16,7 @@
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x920000
+CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x910000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
@@ -29,7 +29,6 @@
 CONFIG_FIT_EXTERNAL_OFFSET=0x3000
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTDELAY=1
 CONFIG_OF_SYSTEM_SETUP=y
@@ -89,8 +88,8 @@
 CONFIG_USE_ETHPRIME=y
 CONFIG_ETHPRIME="eth0"
 CONFIG_VERSION_VARIABLE=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_IP_DEFRAG=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_TFTP_BLOCKSIZE=4096
 CONFIG_SPL_DM=y
 CONFIG_BOOTCOUNT_LIMIT=y
diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig
index 661761f..ec76cff 100644
--- a/configs/verdin-imx8mp_defconfig
+++ b/configs/verdin-imx8mp_defconfig
@@ -13,7 +13,6 @@
 CONFIG_SYS_I2C_MXC_I2C4=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-verdin-wifi-dev"
-CONFIG_SPL_TEXT_BASE=0x920000
 CONFIG_TARGET_VERDIN_IMX8MP=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
@@ -23,6 +22,7 @@
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x960000
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000
+CONFIG_SPL_TEXT_BASE=0x920000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x98fc00
 CONFIG_SPL_BSS_MAX_SIZE=0x400
@@ -38,7 +38,6 @@
 CONFIG_FIT_EXTERNAL_OFFSET=0x3000
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTDELAY=1
 CONFIG_OF_SYSTEM_SETUP=y
@@ -102,8 +101,8 @@
 CONFIG_USE_ETHPRIME=y
 CONFIG_ETHPRIME="eth0"
 CONFIG_VERSION_VARIABLE=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_IP_DEFRAG=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_TFTP_BLOCKSIZE=4096
 CONFIG_SPL_DM=y
 CONFIG_BOOTCOUNT_LIMIT=y
diff --git a/configs/vinco_defconfig b/configs/vinco_defconfig
index ea1d7c9..86087d4 100644
--- a/configs/vinco_defconfig
+++ b/configs/vinco_defconfig
@@ -33,8 +33,8 @@
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig
index 368b389..0b5ad85 100644
--- a/configs/work_92105_defconfig
+++ b/configs/work_92105_defconfig
@@ -16,10 +16,10 @@
 CONFIG_CMD_MAX6957=y
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_TEXT_BASE=0x00000000
 CONFIG_SYS_MONITOR_LEN=262144
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK=0xfff8
+CONFIG_SPL_TEXT_BASE=0x00000000
 CONFIG_SYS_LOAD_ADDR=0x80008000
 CONFIG_SPL=y
 CONFIG_ENV_OFFSET_REDUND=0x120000
diff --git a/configs/x3_t30_defconfig b/configs/x3_t30_defconfig
index 53b1fd9..c8da5b4 100644
--- a/configs/x3_t30_defconfig
+++ b/configs/x3_t30_defconfig
@@ -8,8 +8,8 @@
 CONFIG_ENV_SIZE=0x3000
 CONFIG_ENV_OFFSET=0xFFFFD000
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-lg-p880"
-CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SPL_STACK=0x800ffffc
+CONFIG_SPL_TEXT_BASE=0x80108000
 CONFIG_SYS_LOAD_ADDR=0x82000000
 CONFIG_TEGRA30=y
 CONFIG_TARGET_X3_T30=y
diff --git a/configs/x530_defconfig b/configs/x530_defconfig
index c1fb90d..89612be 100644
--- a/configs/x530_defconfig
+++ b/configs/x530_defconfig
@@ -13,9 +13,9 @@
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DEFAULT_DEVICE_TREE="armada-385-atl-x530"
-CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK=0x4002c000
+CONFIG_SPL_TEXT_BASE=0x40000030
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x40023000
 CONFIG_SPL_BSS_MAX_SIZE=0x4000
@@ -48,8 +48,8 @@
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
diff --git a/configs/xilinx_versal_mini_defconfig b/configs/xilinx_versal_mini_defconfig
index 7388a78..ac3815b 100644
--- a/configs/xilinx_versal_mini_defconfig
+++ b/configs/xilinx_versal_mini_defconfig
@@ -12,6 +12,7 @@
 CONFIG_ENV_SIZE=0x80
 CONFIG_DEFAULT_DEVICE_TREE="versal-mini"
 CONFIG_SYS_LOAD_ADDR=0x8000000
+CONFIG_XILINX_MINI=y
 CONFIG_SYS_MEM_RSVD_FOR_MMU=y
 # CONFIG_PSCI_RESET is not set
 CONFIG_SYS_MEMTEST_START=0x00000000
diff --git a/configs/xilinx_versal_mini_emmc0_defconfig b/configs/xilinx_versal_mini_emmc0_defconfig
index a36e40d..21f241e 100644
--- a/configs/xilinx_versal_mini_emmc0_defconfig
+++ b/configs/xilinx_versal_mini_emmc0_defconfig
@@ -12,6 +12,7 @@
 CONFIG_ENV_SIZE=0x80
 CONFIG_DEFAULT_DEVICE_TREE="versal-mini-emmc0"
 CONFIG_SYS_LOAD_ADDR=0x8000000
+CONFIG_XILINX_MINI=y
 # CONFIG_PSCI_RESET is not set
 # CONFIG_EXPERT is not set
 CONFIG_REMAKE_ELF=y
diff --git a/configs/xilinx_versal_mini_emmc1_defconfig b/configs/xilinx_versal_mini_emmc1_defconfig
index 3ae2115..6cb654c 100644
--- a/configs/xilinx_versal_mini_emmc1_defconfig
+++ b/configs/xilinx_versal_mini_emmc1_defconfig
@@ -12,6 +12,7 @@
 CONFIG_ENV_SIZE=0x80
 CONFIG_DEFAULT_DEVICE_TREE="versal-mini-emmc1"
 CONFIG_SYS_LOAD_ADDR=0x8000000
+CONFIG_XILINX_MINI=y
 # CONFIG_PSCI_RESET is not set
 # CONFIG_EXPERT is not set
 CONFIG_REMAKE_ELF=y
diff --git a/configs/xilinx_versal_mini_ospi_defconfig b/configs/xilinx_versal_mini_ospi_defconfig
index d0ea2b6..c2a5624 100644
--- a/configs/xilinx_versal_mini_ospi_defconfig
+++ b/configs/xilinx_versal_mini_ospi_defconfig
@@ -13,6 +13,7 @@
 # CONFIG_DM_GPIO is not set
 CONFIG_DEFAULT_DEVICE_TREE="versal-mini-ospi-single"
 CONFIG_SYS_LOAD_ADDR=0x8000000
+CONFIG_XILINX_MINI=y
 CONFIG_SYS_MEM_RSVD_FOR_MMU=y
 CONFIG_VERSAL_NO_DDR=y
 # CONFIG_PSCI_RESET is not set
diff --git a/configs/xilinx_versal_mini_qspi_defconfig b/configs/xilinx_versal_mini_qspi_defconfig
index ef6eec0..4d23b35 100644
--- a/configs/xilinx_versal_mini_qspi_defconfig
+++ b/configs/xilinx_versal_mini_qspi_defconfig
@@ -11,6 +11,7 @@
 CONFIG_ENV_SIZE=0x80
 CONFIG_DEFAULT_DEVICE_TREE="versal-mini-qspi-single"
 CONFIG_SYS_LOAD_ADDR=0x8000000
+CONFIG_XILINX_MINI=y
 CONFIG_SYS_MEM_RSVD_FOR_MMU=y
 CONFIG_VERSAL_NO_DDR=y
 # CONFIG_PSCI_RESET is not set
diff --git a/configs/xilinx_versal_net_mini_defconfig b/configs/xilinx_versal_net_mini_defconfig
index 1640dfa..e489f70 100644
--- a/configs/xilinx_versal_net_mini_defconfig
+++ b/configs/xilinx_versal_net_mini_defconfig
@@ -14,6 +14,7 @@
 CONFIG_ENV_SIZE=0x80
 CONFIG_DEFAULT_DEVICE_TREE="versal-net-mini"
 CONFIG_SYS_LOAD_ADDR=0xBBF00000
+CONFIG_XILINX_MINI=y
 CONFIG_SYS_MEM_RSVD_FOR_MMU=y
 # CONFIG_PSCI_RESET is not set
 CONFIG_SYS_MEMTEST_START=0x00000000
diff --git a/configs/xilinx_versal_net_mini_emmc_defconfig b/configs/xilinx_versal_net_mini_emmc_defconfig
index 4c6159a..ab20156 100644
--- a/configs/xilinx_versal_net_mini_emmc_defconfig
+++ b/configs/xilinx_versal_net_mini_emmc_defconfig
@@ -10,6 +10,7 @@
 CONFIG_ENV_SIZE=0x80
 CONFIG_DEFAULT_DEVICE_TREE="versal-net-mini-emmc"
 CONFIG_SYS_LOAD_ADDR=0x8000000
+CONFIG_XILINX_MINI=y
 # CONFIG_PSCI_RESET is not set
 # CONFIG_EXPERT is not set
 CONFIG_REMAKE_ELF=y
diff --git a/configs/xilinx_versal_net_mini_ospi_defconfig b/configs/xilinx_versal_net_mini_ospi_defconfig
index 071eeb8..f5864b5 100644
--- a/configs/xilinx_versal_net_mini_ospi_defconfig
+++ b/configs/xilinx_versal_net_mini_ospi_defconfig
@@ -13,6 +13,7 @@
 # CONFIG_DM_GPIO is not set
 CONFIG_DEFAULT_DEVICE_TREE="versal-net-mini-ospi-single"
 CONFIG_SYS_LOAD_ADDR=0xBBF80000
+CONFIG_XILINX_MINI=y
 CONFIG_SYS_MEM_RSVD_FOR_MMU=y
 # CONFIG_PSCI_RESET is not set
 CONFIG_LTO=y
diff --git a/configs/xilinx_versal_net_mini_qspi_defconfig b/configs/xilinx_versal_net_mini_qspi_defconfig
index 227c45d..8453be5 100644
--- a/configs/xilinx_versal_net_mini_qspi_defconfig
+++ b/configs/xilinx_versal_net_mini_qspi_defconfig
@@ -11,6 +11,7 @@
 CONFIG_ENV_SIZE=0x80
 CONFIG_DEFAULT_DEVICE_TREE="versal-net-mini-qspi-single"
 CONFIG_SYS_LOAD_ADDR=0xBBF80000
+CONFIG_XILINX_MINI=y
 CONFIG_SYS_MEM_RSVD_FOR_MMU=y
 # CONFIG_PSCI_RESET is not set
 CONFIG_LTO=y
diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig
index 899776e..30d79ab 100644
--- a/configs/xilinx_versal_net_virt_defconfig
+++ b/configs/xilinx_versal_net_virt_defconfig
@@ -69,10 +69,10 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
 CONFIG_IP_DEFRAG=y
 CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_TFTP_BLOCKSIZE=4096
 CONFIG_SIMPLE_PM_BUS=y
 CONFIG_CLK_VERSAL=y
@@ -128,12 +128,12 @@
 CONFIG_SOC_DEVICE=y
 CONFIG_SOC_XILINX_VERSAL_NET=y
 CONFIG_SPI=y
-CONFIG_SPI_ADVANCE=y
 CONFIG_DM_SPI=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_CADENCE_OSPI_VERSAL=y
 CONFIG_ZYNQ_SPI=y
 CONFIG_ZYNQMP_GQSPI=y
+CONFIG_SPI_STACKED_PARALLEL=y
 CONFIG_TPM2_TIS_SPI=y
 CONFIG_USB=y
 CONFIG_DM_USB_GADGET=y
diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig
index 32c6bcd..c8f166c 100644
--- a/configs/xilinx_versal_virt_defconfig
+++ b/configs/xilinx_versal_virt_defconfig
@@ -4,6 +4,7 @@
 CONFIG_SYS_INIT_SP_BSS_OFFSET=1572864
 CONFIG_ARCH_VERSAL=y
 CONFIG_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_LEN=0x4000000
 CONFIG_SYS_MALLOC_F_LEN=0x100000
 CONFIG_NR_DRAM_BANKS=36
 CONFIG_SF_DEFAULT_SPEED=30000000
@@ -18,6 +19,10 @@
 CONFIG_SYS_MEMTEST_START=0x00000000
 CONFIG_SYS_MEMTEST_END=0x00001000
 CONFIG_REMAKE_ELF=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_ON_DISK_EARLY=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
 CONFIG_EFI_HTTP_BOOT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -68,14 +73,15 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
 CONFIG_IP_DEFRAG=y
 CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_TFTP_BLOCKSIZE=4096
 CONFIG_SIMPLE_PM_BUS=y
 CONFIG_CLK_VERSAL=y
 CONFIG_DFU_TIMEOUT=y
+CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
 CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1800000
 CONFIG_ARM_FFA_TRANSPORT=y
@@ -99,11 +105,14 @@
 CONFIG_ZYNQ_SDHCI_MIN_FREQ=100000
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SOFT_RESET=y
+CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_ISSI=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
@@ -129,7 +138,6 @@
 CONFIG_XILINX_UARTLITE=y
 CONFIG_SOC_XILINX_VERSAL=y
 CONFIG_SPI=y
-CONFIG_SPI_ADVANCE=y
 CONFIG_DM_SPI=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_HAS_CQSPI_REF_CLK=y
@@ -137,6 +145,9 @@
 CONFIG_CADENCE_OSPI_VERSAL=y
 CONFIG_ZYNQ_SPI=y
 CONFIG_ZYNQMP_GQSPI=y
+CONFIG_SPI_STACKED_PARALLEL=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
 CONFIG_TPM2_TIS_SPI=y
 CONFIG_USB=y
 CONFIG_DM_USB_GADGET=y
diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig
index eaaf105..ed3d101 100644
--- a/configs/xilinx_zynq_virt_defconfig
+++ b/configs/xilinx_zynq_virt_defconfig
@@ -92,9 +92,9 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
 CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SIMPLE_PM_BUS=y
 CONFIG_DFU_TIMEOUT=y
@@ -144,9 +144,9 @@
 CONFIG_POWER_DOMAIN=y
 CONFIG_ARM_DCC=y
 CONFIG_ZYNQ_SERIAL=y
-CONFIG_SPI_ADVANCE=y
 CONFIG_ZYNQ_SPI=y
 CONFIG_ZYNQ_QSPI=y
+CONFIG_SPI_STACKED_PARALLEL=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_ULPI_VIEWPORT=y
diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig
index dd4df0b..e5ffc70 100644
--- a/configs/xilinx_zynqmp_kria_defconfig
+++ b/configs/xilinx_zynqmp_kria_defconfig
@@ -117,9 +117,9 @@
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_ENV_FAT_DEVICE_AND_PART=":auto"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
 CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SIMPLE_PM_BUS=y
 CONFIG_SATA=y
@@ -187,7 +187,6 @@
 CONFIG_PWM_CADENCE_TTC=y
 CONFIG_RESET_ZYNQMP=y
 CONFIG_DM_RTC=y
-CONFIG_RTC_EMULATION=y
 CONFIG_RTC_ZYNQMP=y
 CONFIG_SCSI=y
 CONFIG_ARM_DCC=y
diff --git a/configs/xilinx_zynqmp_mini_defconfig b/configs/xilinx_zynqmp_mini_defconfig
index 7aab69c..b58cf8a 100644
--- a/configs/xilinx_zynqmp_mini_defconfig
+++ b/configs/xilinx_zynqmp_mini_defconfig
@@ -9,6 +9,7 @@
 CONFIG_ENV_SIZE=0x80
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini"
 CONFIG_SYS_LOAD_ADDR=0x8000000
+CONFIG_XILINX_MINI=y
 CONFIG_SYS_MEM_RSVD_FOR_MMU=y
 CONFIG_SYS_MEMTEST_START=0x00000000
 CONFIG_SYS_MEMTEST_END=0x00001000
diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig
index c56b1e83..f47880b 100644
--- a/configs/xilinx_zynqmp_mini_emmc0_defconfig
+++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig
@@ -15,6 +15,7 @@
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
 CONFIG_SYS_LOAD_ADDR=0x8000000
 CONFIG_SPL=y
+CONFIG_XILINX_MINI=y
 CONFIG_REMAKE_ELF=y
 # CONFIG_MP is not set
 # CONFIG_EFI_LOADER is not set
diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig
index a8dbf00..fc0070a 100644
--- a/configs/xilinx_zynqmp_mini_emmc1_defconfig
+++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig
@@ -15,6 +15,7 @@
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
 CONFIG_SYS_LOAD_ADDR=0x8000000
 CONFIG_SPL=y
+CONFIG_XILINX_MINI=y
 CONFIG_REMAKE_ELF=y
 # CONFIG_MP is not set
 # CONFIG_EFI_LOADER is not set
diff --git a/configs/xilinx_zynqmp_mini_nand_defconfig b/configs/xilinx_zynqmp_mini_nand_defconfig
index ba8f02c..6a7541f 100644
--- a/configs/xilinx_zynqmp_mini_nand_defconfig
+++ b/configs/xilinx_zynqmp_mini_nand_defconfig
@@ -10,6 +10,7 @@
 CONFIG_ENV_SIZE=0x80
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand"
 CONFIG_SYS_LOAD_ADDR=0x8000000
+CONFIG_XILINX_MINI=y
 CONFIG_REMAKE_ELF=y
 # CONFIG_MP is not set
 # CONFIG_EFI_LOADER is not set
diff --git a/configs/xilinx_zynqmp_mini_nand_single_defconfig b/configs/xilinx_zynqmp_mini_nand_single_defconfig
index a8a0055..3643cae 100644
--- a/configs/xilinx_zynqmp_mini_nand_single_defconfig
+++ b/configs/xilinx_zynqmp_mini_nand_single_defconfig
@@ -10,6 +10,7 @@
 CONFIG_ENV_SIZE=0x80
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand"
 CONFIG_SYS_LOAD_ADDR=0x8000000
+CONFIG_XILINX_MINI=y
 CONFIG_REMAKE_ELF=y
 # CONFIG_MP is not set
 # CONFIG_EFI_LOADER is not set
diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig
index c08b10c..a60403d 100644
--- a/configs/xilinx_zynqmp_mini_qspi_defconfig
+++ b/configs/xilinx_zynqmp_mini_qspi_defconfig
@@ -15,6 +15,7 @@
 CONFIG_SPL=y
 # CONFIG_SPL_FS_FAT is not set
 # CONFIG_SPL_LIBDISK_SUPPORT is not set
+CONFIG_XILINX_MINI=y
 CONFIG_SYS_MEM_RSVD_FOR_MMU=y
 CONFIG_ZYNQMP_NO_DDR=y
 # CONFIG_PSCI_RESET is not set
diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig
index ff8ab34..310efdf 100644
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -118,9 +118,9 @@
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_ENV_FAT_DEVICE_AND_PART=":auto"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
 CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SIMPLE_PM_BUS=y
 CONFIG_SATA=y
@@ -208,9 +208,9 @@
 CONFIG_ZYNQ_SERIAL=y
 CONFIG_SOC_XILINX_ZYNQMP=y
 CONFIG_SPI=y
-CONFIG_SPI_ADVANCE=y
 CONFIG_ZYNQ_SPI=y
 CONFIG_ZYNQMP_GQSPI=y
+CONFIG_SPI_STACKED_PARALLEL=y
 CONFIG_SYSRESET=y
 CONFIG_SYSRESET_CMD_POWEROFF=y
 CONFIG_SYSRESET_PSCI=y
diff --git a/disk/part_efi.c b/disk/part_efi.c
index bdcfcba..932d058 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -292,6 +292,7 @@
 		 print_efiname(&gpt_pte[part - 1]));
 	strcpy((char *)info->type, "U-Boot");
 	info->bootable = get_bootable(&gpt_pte[part - 1]);
+	info->type_flags = gpt_pte[part - 1].attributes.fields.type_guid_specific;
 	if (CONFIG_IS_ENABLED(PARTITION_UUIDS)) {
 		uuid_bin_to_str(gpt_pte[part - 1].unique_partition_guid.b,
 				(char *)disk_partition_uuid(info),
diff --git a/doc/README.TPL b/doc/README.TPL
deleted file mode 100644
index 95b466e..0000000
--- a/doc/README.TPL
+++ /dev/null
@@ -1,49 +0,0 @@
-Generic TPL framework
-=====================
-
-Overview
---------
-
-TPL---Third Program Loader.
-
-Due to the SPL on some boards(powerpc mpc85xx) has a size limit and cannot
-be compatible with all the external device(e.g. DDR). So add a tertiary
-program loader (TPL) to enable a loader stub loaded by the code from the
-SPL. It loads the final uboot image into DDR, then jump to it to begin
-execution. Now, only the powerpc mpc85xx has this requirement and will
-implemente it.
-
-Keep consistent with SPL, with this framework almost all source files for a
-board can be reused. No code duplication or symlinking is necessary anymore.
-
-How it works
-------------
-
-There has been a directory $(srctree)/spl which contains only a Makefile. The
-Makefile is shared by SPL and TPL.
-
-The object files are built separately for SPL/TPL and placed in the
-directory spl/tpl. The final binaries which are generated are
-u-boot-{spl|tpl}, u-boot-{spl|tpl}.bin and u-boot-{spl|tpl}.map.
-
-During the TPL build a variable named CONFIG_TPL_BUILD is exported in the
-make environment and also appended to CPPFLAGS with -DCONFIG_TPL_BUILD.
-
-The SPL options are shared by SPL and TPL, the board config file should
-determine which SPL options to choose based on whether CONFIG_TPL_BUILD
-is set. Source files can be compiled for TPL with options chosen in the
-board config file.
-
-TPL use a small device tree (u-boot-tpl.dtb), containing only the nodes with
-the pre-relocation properties: 'bootph-all' and 'bootph-pre-sram'
-(see doc/develop/spl.rst for details).
-
-For example:
-
-spl/Makefile:
-LIBS-$(CONFIG_SPL_LIBCOMMON_SUPPORT) += common/libcommon.o
-
-CONFIG_SPL_LIBCOMMON_SUPPORT is defined in board config file:
-#ifdef CONFIG_TPL_BUILD
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#endif
diff --git a/doc/README.kconfig b/doc/README.kconfig
deleted file mode 100644
index 808cf56..0000000
--- a/doc/README.kconfig
+++ /dev/null
@@ -1,151 +0,0 @@
-Kconfig in U-Boot
-=================
-
-This document describes the configuration infrastructure of U-Boot.
-
-The conventional configuration was replaced by Kconfig at v2014.10-rc1 release.
-
-
-Language Specification
-----------------------
-
-Kconfig originates in Linux Kernel.
-See the file "Documentation/kbuild/kconfig*.txt" in your Linux Kernel
-source directory for a basic specification of Kconfig.
-
-
-Difference from Linux's Kconfig
--------------------------------
-
-Here are some worth-mentioning configuration targets.
-
-- silentoldconfig
-
-  This target updates .config, include/generated/autoconf.h and
-  include/configs/* as in Linux.  In U-Boot, it also does the following
-  for the compatibility with the old configuration system:
-
-   * create a symbolic link "arch/${ARCH}/include/asm/arch" pointing to
-     the SoC/CPU specific header directory
-   * create include/config.h
-   * create include/autoconf.mk
-   * create spl/include/autoconf.mk (SPL and TPL only)
-   * create tpl/include/autoconf.mk (TPL only)
-
-   If we could completely switch to Kconfig in a long run
-   (i.e. remove all the include/configs/*.h), those additional processings
-   above would be removed.
-
-- defconfig
-
-  In U-Boot, "make defconfig" is a shorthand of "make sandbox_defconfig"
-
-- <board>_defconfig
-
-  Now it works as in Linux.
-  The prefixes such as "+S:" in *_defconfig are deprecated.
-  You can simply remove the prefixes.  Do not add them for new boards.
-
-- <board>_config
-
-  This does not exist in Linux's Kconfig.
-  "make <board>_config" works the same as "make <board>_defconfig".
-  Prior to Kconfig, in U-Boot, "make <board>_config" was used for the
-  configuration.  It is still supported for backward compatibility, so
-  we do not need to update the distro recipes.
-
-
-The other configuration targets work as in Linux Kernel.
-
-
-Migration steps to Kconfig
---------------------------
-
-Prior to Kconfig, the C preprocessor based board configuration had been used
-in U-Boot.
-
-Although Kconfig was introduced and some configs have been moved to Kconfig,
-many of configs are still defined in C header files.  It will take a very
-long term to move all of them to Kconfig.  In the interim, the two different
-configuration infrastructures should coexist.
-The configuration files are generated by both Kconfig and the old preprocessor
-based configuration as follows:
-
-Configuration files for use in C sources
-  - include/generated/autoconf.h     (generated by Kconfig for Normal)
-  - include/configs/<board>.h        (exists for all boards)
-
-Configuration file for use in makefiles
-  - include/config/auto.conf         (generated by Kconfig)
-  - include/autoconf.mk              (generated by the old config for Normal)
-  - spl/include/autoconfig.mk        (generated by the old config for SPL)
-  - tpl/include/autoconfig.mk        (generated by the old config for TPL)
-
-When adding a new CONFIG macro, it is highly recommended to add it to Kconfig
-rather than to a header file.
-
-
-Conversion from boards.cfg to Kconfig
--------------------------------------
-
-Prior to Kconfig, boards.cfg was a primary database that contained Arch, CPU,
-SoC, etc. of all the supported boards.  It was deleted when switching to
-Kconfig.  Each field of boards.cfg was converted as follows:
-
- Status      ->  "S:" entry of MAINTAINERS
- Arch        ->  CONFIG_SYS_ARCH defined by Kconfig
- CPU         ->  CONFIG_SYS_CPU defined by Kconfig
- SoC         ->  CONFIG_SYS_SOC defined by Kconfig
- Vendor      ->  CONFIG_SYS_VENDOR defined by Kconfig
- Board       ->  CONFIG_SYS_BOARD defined by Kconfig
- Target      ->  File name of defconfig (configs/<target>_defconfig)
- Maintainers ->  "M:" entry of MAINTAINERS
-
-
-Tips to add/remove boards
--------------------------
-
-When adding a new board, the following steps are generally needed:
-
- [1] Add a header file include/configs/<target>.h
- [2] Make sure to define necessary CONFIG_SYS_* in Kconfig:
-       Define CONFIG_SYS_CPU="cpu" to compile arch/<arch>/cpu/<cpu>
-       Define CONFIG_SYS_SOC="soc" to compile arch/<arch>/cpu/<cpu>/<soc>
-       Define CONFIG_SYS_VENDOR="vendor" to compile board/<vendor>/common/*
-         and board/<vendor>/<board>/*
-       Define CONFIG_SYS_BOARD="board" to compile board/<board>/*
-         (or board/<vendor>/<board>/* if CONFIG_SYS_VENDOR is defined)
-       Define CONFIG_SYS_CONFIG_NAME="target" to include
-         include/configs/<target>.h
- [3] Add a new entry to the board select menu in Kconfig.
-     The board select menu is located in arch/<arch>/Kconfig or
-     arch/<arch>/*/Kconfig.
- [4] Add a MAINTAINERS file
-     It is generally placed at board/<board>/MAINTAINERS or
-     board/<vendor>/<board>/MAINTAINERS
- [5] Add configs/<target>_defconfig
-
-When removing an obsolete board, the following steps are generally needed:
-
- [1] Remove configs/<target>_defconfig
- [2] Remove include/configs/<target>.h if it is not used by any other boards
- [3] Remove board/<vendor>/<board>/* or board/<board>/* if it is not used
-     by any other boards
- [4] Update MAINTAINERS if necessary
- [5] Remove the unused entry from the board select menu in Kconfig
- [6] Add an entry to doc/README.scrapyard
-
-
-TODO
-----
-
-- In the pre-Kconfig, a single board had multiple entries in the boards.cfg
-  file with differences in the option fields.  The corresponding defconfig
-  files were auto-generated when switching to Kconfig.  Now we have too many
-  defconfig files compared with the number of the supported boards.  It is
-  recommended to have only one defconfig per board and allow users to select
-  the config options.
-
-- Move the config macros in header files to Kconfig.  When we move at least
-  macros used in makefiles, we can drop include/autoconfig.mk, which makes
-  the build scripts much simpler.
diff --git a/doc/board/phytec/imx93-phyboard-segin.rst b/doc/board/phytec/imx93-phycore.rst
similarity index 90%
rename from doc/board/phytec/imx93-phyboard-segin.rst
rename to doc/board/phytec/imx93-phycore.rst
index ce17fbe..bd110a3 100644
--- a/doc/board/phytec/imx93-phyboard-segin.rst
+++ b/doc/board/phytec/imx93-phycore.rst
@@ -1,9 +1,9 @@
 .. SPDX-License-Identifier: GPL-2.0+
 
-phyBOARD-Segin-i.MX93
-=====================
+phyCORE-i.MX 93
+===============
 
-U-Boot for the phyBOARD-Segin-i.MX93.
+U-Boot for the phyCORE-i.MX 93.
 
 Quick Start
 -----------
@@ -51,7 +51,7 @@
 
 .. code-block:: bash
 
-   $ make imx93-phyboard-segin_defconfig
+   $ make imx93-phycore_defconfig
    $ make
 
 Burn the flash.bin to MicroSD card offset 32KB:
diff --git a/doc/board/phytec/index.rst b/doc/board/phytec/index.rst
index 99848a9..fa30697 100644
--- a/doc/board/phytec/index.rst
+++ b/doc/board/phytec/index.rst
@@ -7,7 +7,7 @@
    :maxdepth: 2
 
    imx8mm-phygate-tauri-l
-   imx93-phyboard-segin
+   imx93-phycore
    phycore-am62x
    phycore-am64x
    phycore-imx8mm
diff --git a/doc/develop/index.rst b/doc/develop/index.rst
index 30f7fdb..d9f2a83 100644
--- a/doc/develop/index.rst
+++ b/doc/develop/index.rst
@@ -13,6 +13,7 @@
    codingstyle
    designprinciples
    docstyle
+   kconfig
    memory
    patman
    process
diff --git a/doc/develop/kconfig.rst b/doc/develop/kconfig.rst
new file mode 100644
index 0000000..227074d
--- /dev/null
+++ b/doc/develop/kconfig.rst
@@ -0,0 +1,157 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+
+Kconfig in U-Boot
+=================
+
+This document describes the configuration infrastructure of U-Boot.
+
+The conventional configuration was replaced by Kconfig at v2014.10-rc1 release.
+
+Language Specification
+----------------------
+
+The Kconfig configuration language originates in Linux kernel.
+See the Linux document
+`Kconfig Language <https://www.kernel.org/doc/html/latest/kbuild/kconfig-language.html>`_
+for a description of Kconfig.
+
+Difference from Linux's Kconfig
+-------------------------------
+
+Here are some worth-mentioning configuration targets.
+
+silentoldconfig
+  This target updates .config, include/generated/autoconf.h and
+  include/configs/* as in Linux.  In U-Boot, it also does the following
+  for the compatibility with the old configuration system:
+
+   * create a symbolic link "arch/${ARCH}/include/asm/arch" pointing to
+     the SoC/CPU specific header directory
+   * create include/config.h
+   * create include/autoconf.mk
+   * create spl/include/autoconf.mk (SPL and TPL only)
+   * create tpl/include/autoconf.mk (TPL only)
+
+   If we could completely switch to Kconfig in a long run
+   (i.e. remove all the include/configs/\*.h), those additional processings
+   above would be removed.
+
+defconfig
+  In U-Boot, "make defconfig" is a shorthand of "make sandbox_defconfig"
+
+<board>_defconfig
+  Now it works as in Linux.
+  The prefixes such as "+S:" in \*_defconfig are deprecated.
+  You can simply remove the prefixes.  Do not add them for new boards.
+
+<board>_config
+  This does not exist in Linux's Kconfig.
+  "make <board>_config" works the same as "make <board>_defconfig".
+  Prior to Kconfig, in U-Boot, "make <board>_config" was used for the
+  configuration.  It is still supported for backward compatibility, so
+  we do not need to update the distro recipes.
+
+The other configuration targets work as in Linux Kernel.
+
+Migration steps to Kconfig
+--------------------------
+
+Prior to Kconfig, the C preprocessor based board configuration had been used
+in U-Boot.
+
+Although Kconfig was introduced and some configs have been moved to Kconfig,
+many of configs are still defined in C header files.  It will take a very
+long term to move all of them to Kconfig.  In the interim, the two different
+configuration infrastructures should coexist.
+The configuration files are generated by both Kconfig and the old preprocessor
+based configuration as follows:
+
+Configuration files for use in C sources
+  - include/generated/autoconf.h     (generated by Kconfig for Normal)
+  - include/configs/<board>.h        (exists for all boards)
+
+Configuration file for use in makefiles
+  - include/config/auto.conf         (generated by Kconfig)
+  - include/autoconf.mk              (generated by the old config for Normal)
+  - spl/include/autoconfig.mk        (generated by the old config for SPL)
+  - tpl/include/autoconfig.mk        (generated by the old config for TPL)
+
+When adding a new CONFIG macro, it is highly recommended to add it to Kconfig
+rather than to a header file.
+
+Conversion from boards.cfg to Kconfig
+-------------------------------------
+
+Prior to Kconfig, boards.cfg was a primary database that contained Arch, CPU,
+SoC, etc. of all the supported boards. It was deleted when switching to
+Kconfig. Each field of boards.cfg was converted as follows:
+
+=========== ====================================================
+From        To
+=========== ====================================================
+Arch        CONFIG_SYS_ARCH defined by Kconfig
+Board       CONFIG_SYS_BOARD defined by Kconfig
+CPU         CONFIG_SYS_CPU defined by Kconfig
+Maintainers "M:" entry of MAINTAINERS
+SoC         CONFIG_SYS_SOC defined by Kconfig
+Status      "S:" entry of MAINTAINERS
+Target      File name of defconfig (configs/<target>\_defconfig)
+Vendor      CONFIG_SYS_VENDOR defined by Kconfig
+=========== ====================================================
+
+Tips to add/remove boards
+-------------------------
+
+When adding a new board, the following steps are generally needed:
+
+1. Add a header file include/configs/<target>.h
+
+2. Make sure to define necessary CONFIG_SYS_* in Kconfig:
+
+   * Define CONFIG_SYS_CPU="cpu" to compile arch/<arch>/cpu/<cpu>
+   * Define CONFIG_SYS_SOC="soc" to compile arch/<arch>/cpu/<cpu>/<soc>
+   * Define CONFIG_SYS_VENDOR="vendor" to compile board/<vendor>/common/\*
+     and board/<vendor>/<board>/\*
+   * Define CONFIG_SYS_BOARD="board" to compile board/<board>/\*
+     (or board/<vendor>/<board>/* if CONFIG_SYS_VENDOR is defined)
+     Define CONFIG_SYS_CONFIG_NAME="target" to include
+     include/configs/<target>.h
+
+3. Add a new entry to the board select menu in Kconfig.
+   The board select menu is located in arch/<arch>/Kconfig or
+   arch/<arch>/\*/Kconfig.
+
+4. Add a MAINTAINERS file
+   It is generally placed at board/<board>/MAINTAINERS or
+   board/<vendor>/<board>/MAINTAINERS
+
+5. Add configs/<target>_defconfig
+
+When removing an obsolete board, the following steps are generally needed:
+
+1. Remove configs/<target>_defconfig
+
+2. Remove include/configs/<target>.h if it is not used by any other boards
+
+3. Remove board/<vendor>/<board>/\* or board/<board>/\* if it is not used
+   by any other boards
+
+4. Update MAINTAINERS if necessary
+
+5. Remove the unused entry from the board select menu in Kconfig
+
+6. Add an entry to doc/README.scrapyard
+
+TODO
+----
+
+* In the pre-Kconfig, a single board had multiple entries in the boards.cfg
+  file with differences in the option fields. The corresponding defconfig
+  files were auto-generated when switching to Kconfig. Now we have too many
+  defconfig files compared with the number of the supported boards. It is
+  recommended to have only one defconfig per board and allow users to select
+  the config options.
+
+* Move the config macros in header files to Kconfig. When we move at least
+  macros used in makefiles, we can drop include/autoconfig.mk, which makes
+  the build scripts much simpler.
diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst
index 1548d26..c742c2f 100644
--- a/doc/develop/release_cycle.rst
+++ b/doc/develop/release_cycle.rst
@@ -71,7 +71,7 @@
 
 * U-Boot v2025.01-rc2 was released on Mon 11 November 2024.
 
-.. * U-Boot v2025.01-rc3 was released on Mon 25 November 2024.
+* U-Boot v2025.01-rc3 was released on Mon 25 November 2024.
 
 .. * U-Boot v2025.01-rc4 was released on Mon 09 December 2024.
 
diff --git a/doc/develop/uefi/uefi.rst b/doc/develop/uefi/uefi.rst
index 0760ca9..48d6110 100644
--- a/doc/develop/uefi/uefi.rst
+++ b/doc/develop/uefi/uefi.rst
@@ -681,8 +681,8 @@
 As of U-Boot v2020.10 UEFI variables cannot be set at runtime. The U-Boot
 command 'efidebug' can be used to set the variables.
 
-UEFI HTTP Boot
-~~~~~~~~~~~~~~
+UEFI HTTP Boot using the legacy TCP stack
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 HTTP Boot provides the capability for system deployment and configuration
 over the network. HTTP Boot can be activated by specifying::
@@ -715,6 +715,47 @@
 
     setenv httpserverip 192.168.1.1
 
+UEFI HTTP(s) Boot using lwIP
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Similar to the above U-Boot can do EFI HTTP boot using lwIP. If we combine this
+with Mbed TLS we can also download from https://
+
+HTTP(s) Boot can be activated by specifying::
+
+    CONFIG_EFI_HTTP_BOOT
+    CONFIG_NET_LWIP
+    CONFIG_WGET_HTTPS
+
+For QEMU targets there's a Kconfig that supports this by default::
+
+    make qemu_arm64_lwip_defconfig
+
+The commands and functionality are similar to the legacy stack, with the notable
+exception of not having to define an "httpserverip" if you are trying to resolve
+an IP. However, lwIP code doesn't yet support redirects::
+
+    => efidebug boot add -u 1 netinst https://cdimage.debian.org/cdimage/weekly-builds/arm64/iso-cd/debian-testing-arm64-netinst.iso
+    => dhcp
+    DHCP client bound to address 10.0.2.15 (3 ms)
+    => efidebug boot order 1
+    => bootefi bootmgr
+
+    HTTP server error 302
+    Loading Boot0001 'netinst' failed
+    EFI boot manager: Cannot load any image
+
+If the url you specified isn't a redirect::
+
+    => efidebug boot add -u 1 netinst https://download.rockylinux.org/pub/rocky/9/isos/aarch64/Rocky-9.4-aarch64-minimal.iso
+    => dhcp
+    => bootefi bootmgr
+    #######################################
+
+If the downloaded file extension is .iso or .img file, efibootmgr tries to
+mount the image and boot with the default file(e.g. EFI/BOOT/BOOTAA64.EFI).
+If the downloaded file is PE-COFF image, load the downloaded file and
+start it.
+
 Executing the built in hello world application
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
diff --git a/doc/usage/cmd/wget.rst b/doc/usage/cmd/wget.rst
index b8ca35b..48bedf1 100644
--- a/doc/usage/cmd/wget.rst
+++ b/doc/usage/cmd/wget.rst
@@ -11,29 +11,54 @@
 
 ::
 
-    wget address [[hostIPaddr:]path]
+    wget [address] [host:]path
+    wget [address] url          # lwIP only
+
 
 Description
 -----------
 
+The wget command is used to download a file from an HTTP(S) server.
+In order to use HTTPS you will need to compile wget with lwIP support.
+
-The wget command is used to download a file from an HTTP server.
+Legacy syntax
+~~~~~~~~~~~~~
 
-wget command will use HTTP over TCP to download files from an HTTP server.
+The legacy syntax is supported by the legacy network stack (CONFIG_NET=y)
+as well as by the lwIP base network stack (CONFIG_NET_LWIP=y). It supports HTTP
+only.
+
 By default the destination port is 80 and the source port is pseudo-random.
-The environment variable *httpdstp* can be used to set the destination port.
+On the legacy nework stack the environment variable *httpdstp* can be used to
+set the destination port
 
 address
     memory address for the data downloaded
 
-hostIPaddr
-    IP address of the HTTP server, defaults to the value of environment
-    variable *serverip*
+host
+    IP address (or host name if `CONFIG_CMD_DNS` is enabled) of the HTTP
+    server, defaults to the value of environment variable *serverip*.
 
 path
     path of the file to be downloaded.
 
+New syntax (lwIP only)
+~~~~~~~~~~~~~~~~~~~~~~
+
+In addition to the syntax described above, wget accepts URLs if the network
+stack is lwIP.
+
+address
+    memory address for the data downloaded
+
+url
+    HTTP or HTTPS URL, that is: http[s]://<host>[:<port>]/<path>.
+
+Examples
+--------
+
-Example
--------
+Example with the legacy network stack
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 In the example the following steps are executed:
 
@@ -52,13 +77,42 @@
     HTTP/1.0 302 Found
     Packets received 4, Transfer Successful
 
+Example with lwIP
+~~~~~~~~~~~~~~~~~
+
+In the example the following steps are executed:
+
+* setup client network address
+* download a file from the HTTPS server
+
+::
+
+   => dhcp
+   DHCP client bound to address 10.0.2.15 (3 ms)
+   => wget https://download.rockylinux.org/pub/rocky/9/isos/aarch64/Rocky-9.4-aarch64-minimal.iso
+   ##########################################################################
+   ##########################################################################
+   ##########################################################################
+   [...]
+   1694892032 bytes transferred in 492181 ms (3.3 MiB/s)
+   Bytes transferred = 1694892032 (65060000 hex)
+
 Configuration
 -------------
 
 The command is only available if CONFIG_CMD_WGET=y.
+To enable lwIP support set CONFIG_NET_LWIP=y.
+
+TCP Selective Acknowledgments in the legacy network stack can be enabled via
+CONFIG_PROT_TCP_SACK=y. This will improve the download speed. Selective
+Acknowledgments are enabled by default with lwIP.
+
+.. note::
 
-TCP Selective Acknowledgments can be enabled via CONFIG_PROT_TCP_SACK=y.
-This will improve the download speed.
+    U-Boot currently has no way to verify certificates for HTTPS.
+    A place to store the root CA certificates is needed, and then MBed TLS would
+    need to walk the entire chain. Therefore, man-in-the middle attacks are
+    possible and HTTPS should not be relied upon for payload authentication.
 
 Return value
 ------------
diff --git a/doc/usage/dfu.rst b/doc/usage/dfu.rst
index 8cc09c3..af80551 100644
--- a/doc/usage/dfu.rst
+++ b/doc/usage/dfu.rst
@@ -22,6 +22,7 @@
 Today the supported DFU backends are:
 
 - MMC (RAW or FAT / EXT2 / EXT3 / EXT4 file system / SKIP / SCRIPT)
+- SCSI (UFS, RAW partition, FAT / EXT2 / EXT3 / EXT4 file system / SKIP / SCRIPT)
 - NAND
 - RAM
 - SF (serial flash)
@@ -51,6 +52,7 @@
 * CONFIG_DFU_MTD
 * CONFIG_DFU_NAND
 * CONFIG_DFU_RAM
+* CONFIG_DFU_SCSI
 * CONFIG_DFU_SF
 * CONFIG_DFU_SF_PART
 * CONFIG_DFU_TIMEOUT
@@ -167,6 +169,36 @@
     Please note that this means the user will be able to execute any
     arbitrary commands just like in the u-boot's shell.
 
+scsi
+    for UFS storage::
+
+        dfu 0 scsi <dev>
+
+    each element in *dfu_alt_info* being
+
+    * <name> raw <offset> <size>     raw access to SCSI LUN
+    * <name> part <part_id>          raw access to partition
+    * <name> fat <part_id>           file in FAT partition
+    * <name> ext4 <part_id>          file in EXT4 partition
+    * <name> skip 0 0                ignore flashed data
+    * <name> script 0 0              execute commands in shell
+
+    with
+
+    size
+        is the size of the access area (hexadecimal without "0x")
+        or 0 which means whole device
+    partid
+        is the GPT or DOS partition index.
+    dev
+        is the SCSI LU (Logical Unit) index (decimal only)
+
+    A value of environment variable *dfu_alt_info* for UFS could be::
+
+        u-boot part 4;bl2 raw 0x1e 0x1d
+
+    See mmc section above for details on the skip and script types.
+
 nand
     raw slc nand device::
 
@@ -278,6 +310,7 @@
     mmc <dev>=<alt1>;....;<altN>
     nand <dev>=<alt1>;....;<altN>
     ram <dev>=<alt1>;....;<altN>
+    scsi <dev>=<alt1>;....;<altN>
     sf <dev>=<alt1>;....;<altN>
     mtd <dev>=<alt1>;....;<altN>
     virt <dev>=<alt1>;....;<altN>
diff --git a/drivers/bootcount/Kconfig b/drivers/bootcount/Kconfig
index fa6d8e7..0080d2a 100644
--- a/drivers/bootcount/Kconfig
+++ b/drivers/bootcount/Kconfig
@@ -164,6 +164,13 @@
 
 	  Accessing the backend is done using the regmap interface.
 
+config DM_BOOTCOUNT_ZYNQMP
+	bool "Support ZynqMP PMUFW as a backing store for bootcount"
+	depends on ARCH_ZYNQMP
+	help
+	  Enable support for the bootcount API by utilising the Persistent
+	  Global General Storage Register 2 of the PMU.
+
 endmenu
 
 endif
diff --git a/drivers/bootcount/Makefile b/drivers/bootcount/Makefile
index 245f879..0cf79e4 100644
--- a/drivers/bootcount/Makefile
+++ b/drivers/bootcount/Makefile
@@ -16,3 +16,4 @@
 obj-$(CONFIG_DM_BOOTCOUNT_I2C)	+= bootcount_dm_i2c.o
 obj-$(CONFIG_DM_BOOTCOUNT_SPI_FLASH)	+= spi-flash.o
 obj-$(CONFIG_DM_BOOTCOUNT_SYSCON) += bootcount_syscon.o
+obj-$(CONFIG_DM_BOOTCOUNT_ZYNQMP)	+= bootcount_zynqmp.o
diff --git a/drivers/bootcount/bootcount_zynqmp.c b/drivers/bootcount/bootcount_zynqmp.c
new file mode 100644
index 0000000..bc0984e
--- /dev/null
+++ b/drivers/bootcount/bootcount_zynqmp.c
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0+
+// SPDX-FileCopyrightText: 2024 CERN (home.cern)
+
+#include <bootcount.h>
+#include <dm.h>
+#include <stdio.h>
+#include <zynqmp_firmware.h>
+#include <asm/arch/hardware.h>
+#include <dm/platdata.h>
+
+static int bootcount_zynqmp_set(struct udevice *dev, const u32 val)
+{
+	int ret;
+
+	ret = zynqmp_mmio_write((ulong)&pmu_base->pers_gen_storage2, 0xFF, val);
+	if (ret)
+		pr_info("%s write fail\n", __func__);
+
+	return ret;
+}
+
+static int bootcount_zynqmp_get(struct udevice *dev, u32 *val)
+{
+	int ret;
+
+	*val = 0;
+	ret = zynqmp_mmio_read((ulong)&pmu_base->pers_gen_storage2, val);
+	if (ret)
+		pr_info("%s read fail\n", __func__);
+
+	return ret;
+}
+
+U_BOOT_DRVINFO(bootcount_zynqmp) = {
+	.name = "bootcount_zynqmp",
+};
+
+static const struct bootcount_ops bootcount_zynqmp_ops = {
+	.get = bootcount_zynqmp_get,
+	.set = bootcount_zynqmp_set,
+};
+
+U_BOOT_DRIVER(bootcount_zynqmp) = {
+	.name = "bootcount_zynqmp",
+	.id = UCLASS_BOOTCOUNT,
+	.ops = &bootcount_zynqmp_ops,
+};
diff --git a/drivers/core/root.c b/drivers/core/root.c
index 7a714f5..c7fb582 100644
--- a/drivers/core/root.c
+++ b/drivers/core/root.c
@@ -147,6 +147,13 @@
 
 	return 0;
 }
+
+void dm_remove_devices_active(void)
+{
+	/* Remove non-vital devices first */
+	device_remove(dm_root(), DM_REMOVE_ACTIVE_ALL | DM_REMOVE_NON_VITAL);
+	device_remove(dm_root(), DM_REMOVE_ACTIVE_ALL);
+}
 #endif
 
 int dm_scan_plat(bool pre_reloc_only)
diff --git a/drivers/dfu/Kconfig b/drivers/dfu/Kconfig
index 604386b..e33b005 100644
--- a/drivers/dfu/Kconfig
+++ b/drivers/dfu/Kconfig
@@ -89,6 +89,13 @@
 	  used at board level to manage specific behavior
 	  (OTP update for example).
 
+config DFU_SCSI
+	bool "SCSI flash back end for DFU"
+	help
+	  This option enables using DFU to read and write to SCSI devices
+	  used at board level to manage specific behavior
+	  (OTP update for example).
+
 config SET_DFU_ALT_INFO
 	bool "Dynamic set of DFU alternate information"
 	help
diff --git a/drivers/dfu/Makefile b/drivers/dfu/Makefile
index 05d7cc6..6e1ab1c 100644
--- a/drivers/dfu/Makefile
+++ b/drivers/dfu/Makefile
@@ -11,3 +11,4 @@
 obj-$(CONFIG_$(XPL_)DFU_SF) += dfu_sf.o
 obj-$(CONFIG_$(XPL_)DFU_WRITE_ALT) += dfu_alt.o
 obj-$(CONFIG_$(XPL_)DFU_VIRT) += dfu_virt.o
+obj-$(CONFIG_$(XPL_)DFU_SCSI) += dfu_scsi.o
diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c
index 7a4d7ba..7565692 100644
--- a/drivers/dfu/dfu.c
+++ b/drivers/dfu/dfu.c
@@ -564,6 +564,9 @@
 	} else if (strcmp(interface, "virt") == 0) {
 		if (dfu_fill_entity_virt(dfu, devstr, argv, argc))
 			return -1;
+	} else if (strcmp(interface, "scsi") == 0) {
+		if (dfu_fill_entity_scsi(dfu, devstr, argv, argc))
+			return -1;
 	} else {
 		printf("%s: Device %s not (yet) supported!\n",
 		       __func__,  interface);
@@ -660,7 +663,7 @@
 const char *dfu_get_dev_type(enum dfu_device_type t)
 {
 	const char *const dev_t[] = {NULL, "eMMC", "OneNAND", "NAND", "RAM",
-				     "SF", "MTD", "VIRT"};
+				     "SF", "MTD", "VIRT", "SCSI"};
 	return dev_t[t];
 }
 
diff --git a/drivers/dfu/dfu_scsi.c b/drivers/dfu/dfu_scsi.c
new file mode 100644
index 0000000..9f95194
--- /dev/null
+++ b/drivers/dfu/dfu_scsi.c
@@ -0,0 +1,435 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * DFU SCSI backend (based on MMC backend).
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *   author: Lukasz Majewski <l.majewski@samsung.com>
+ * Copyright (C) 2024 Linaro Ltd.
+ */
+
+#include <log.h>
+#include <malloc.h>
+#include <errno.h>
+#include <div64.h>
+#include <dfu.h>
+#include <ext4fs.h>
+#include <fat.h>
+#include <scsi.h>
+#include <part.h>
+#include <command.h>
+#include <linux/printk.h>
+
+static unsigned char *dfu_file_buf;
+static u64 dfu_file_buf_len;
+static u64 dfu_file_buf_offset;
+
+#define scsi_get_blk_desc(dev) ((struct blk_desc *)dev_get_uclass_plat(dev))
+
+#define find_scsi_device(dev_num, scsi) blk_get_device(UCLASS_SCSI, dev_num, scsi)
+
+static int scsi_block_op(enum dfu_op op, struct dfu_entity *dfu, u64 offset, void *buf, long *len)
+{
+	struct udevice *scsi;
+	u32 blk_start, blk_count, n = 0;
+	int ret;
+
+	ret = find_scsi_device(dfu->data.scsi.lun, &scsi);
+	if (ret < 0) {
+		pr_err("Device scsi %d - not found!", dfu->data.scsi.lun);
+		return -ENODEV;
+	}
+
+	/*
+	 * We must ensure that we work in lba_blk_size chunks, so ALIGN
+	 * this value.
+	 */
+	*len = ALIGN(*len, dfu->data.scsi.lba_blk_size);
+
+	blk_start = dfu->data.scsi.lba_start + (u32)lldiv(offset, dfu->data.scsi.lba_blk_size);
+	blk_count = *len / dfu->data.scsi.lba_blk_size;
+	if (blk_start + blk_count > dfu->data.scsi.lba_start + dfu->data.scsi.lba_size) {
+		puts("Request would exceed designated area!\n");
+		return -EINVAL;
+	}
+
+	debug("%s: %s dev: %d start: %d cnt: %d buf: 0x%p\n", __func__,
+	      op == DFU_OP_READ ? "scsi READ" : "scsi WRITE", dfu->data.scsi.lun, blk_start,
+	      blk_count, buf);
+	switch (op) {
+	case DFU_OP_READ:
+		n = blk_dread(scsi_get_blk_desc(scsi), blk_start, blk_count, buf);
+		break;
+	case DFU_OP_WRITE:
+		n = blk_dwrite(scsi_get_blk_desc(scsi), blk_start, blk_count, buf);
+		break;
+	default:
+		pr_err("Operation not supported\n");
+	}
+
+	if (n != blk_count) {
+		pr_err("scsi block operation failed");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int scsi_file_op(enum dfu_op op, struct dfu_entity *dfu, u64 offset, void *buf, u64 *len)
+{
+	char dev_part_str[8];
+	int ret;
+	int fstype;
+	loff_t size = 0;
+
+	switch (dfu->layout) {
+	case DFU_FS_FAT:
+		fstype = FS_TYPE_FAT;
+		break;
+	case DFU_FS_EXT4:
+		fstype = FS_TYPE_EXT;
+		break;
+	case DFU_SKIP:
+		return 0;
+	default:
+		printf("%s: Layout (%s) not (yet) supported!\n", __func__,
+		       dfu_get_layout(dfu->layout));
+		return -1;
+	}
+
+	snprintf(dev_part_str, sizeof(dev_part_str), "%d:%d", dfu->data.scsi.dev,
+		 dfu->data.scsi.part);
+
+	ret = fs_set_blk_dev("scsi", dev_part_str, fstype);
+	if (ret) {
+		puts("dfu: fs_set_blk_dev error!\n");
+		return ret;
+	}
+
+	switch (op) {
+	case DFU_OP_READ:
+		ret = fs_read(dfu->name, (size_t)buf, offset, *len, &size);
+		if (ret) {
+			puts("dfu: fs_read error!\n");
+			return ret;
+		}
+		*len = size;
+		break;
+	case DFU_OP_WRITE:
+		ret = fs_write(dfu->name, (size_t)buf, offset, *len, &size);
+		if (ret) {
+			puts("dfu: fs_write error!\n");
+			return ret;
+		}
+		break;
+	case DFU_OP_SIZE:
+		ret = fs_size(dfu->name, &size);
+		if (ret) {
+			puts("dfu: fs_size error!\n");
+			return ret;
+		}
+		*len = size;
+		break;
+	default:
+		return -1;
+	}
+
+	return ret;
+}
+
+static int scsi_file_buf_write(struct dfu_entity *dfu, u64 offset, void *buf, long *len)
+{
+	int ret = 0;
+
+	if (offset == 0) {
+		dfu_file_buf_len = 0;
+		dfu_file_buf_offset = 0;
+	}
+
+	/* Add to the current buffer. */
+	if (dfu_file_buf_len + *len > CONFIG_SYS_DFU_MAX_FILE_SIZE)
+		*len = CONFIG_SYS_DFU_MAX_FILE_SIZE - dfu_file_buf_len;
+	memcpy(dfu_file_buf + dfu_file_buf_len, buf, *len);
+	dfu_file_buf_len += *len;
+
+	if (dfu_file_buf_len == CONFIG_SYS_DFU_MAX_FILE_SIZE) {
+		ret = scsi_file_op(DFU_OP_WRITE, dfu, dfu_file_buf_offset, dfu_file_buf,
+				   &dfu_file_buf_len);
+		dfu_file_buf_offset += dfu_file_buf_len;
+		dfu_file_buf_len = 0;
+	}
+
+	return ret;
+}
+
+static int scsi_file_buf_write_finish(struct dfu_entity *dfu)
+{
+	int ret = scsi_file_op(DFU_OP_WRITE, dfu, dfu_file_buf_offset, dfu_file_buf,
+			       &dfu_file_buf_len);
+
+	/* Now that we're done */
+	dfu_file_buf_len = 0;
+	dfu_file_buf_offset = 0;
+
+	return ret;
+}
+
+int dfu_write_medium_scsi(struct dfu_entity *dfu, u64 offset, void *buf, long *len)
+{
+	int ret = -1;
+
+	switch (dfu->layout) {
+	case DFU_RAW_ADDR:
+		ret = scsi_block_op(DFU_OP_WRITE, dfu, offset, buf, len);
+		break;
+	case DFU_FS_FAT:
+	case DFU_FS_EXT4:
+		ret = scsi_file_buf_write(dfu, offset, buf, len);
+		break;
+	case DFU_SCRIPT:
+		ret = run_command_list(buf, *len, 0);
+		break;
+	case DFU_SKIP:
+		ret = 0;
+		break;
+	default:
+		printf("%s: Layout (%s) not (yet) supported!\n", __func__,
+		       dfu_get_layout(dfu->layout));
+	}
+
+	return ret;
+}
+
+int dfu_flush_medium_scsi(struct dfu_entity *dfu)
+{
+	int ret = 0;
+
+	switch (dfu->layout) {
+	case DFU_FS_FAT:
+	case DFU_FS_EXT4:
+		ret = scsi_file_buf_write_finish(dfu);
+		break;
+	case DFU_SCRIPT:
+		/* script may have changed the dfu_alt_info */
+		dfu_reinit_needed = true;
+		break;
+	case DFU_RAW_ADDR:
+	case DFU_SKIP:
+		break;
+	default:
+		printf("%s: Layout (%s) not (yet) supported!\n", __func__,
+		       dfu_get_layout(dfu->layout));
+	}
+
+	return ret;
+}
+
+int dfu_get_medium_size_scsi(struct dfu_entity *dfu, u64 *size)
+{
+	int ret;
+
+	switch (dfu->layout) {
+	case DFU_RAW_ADDR:
+		*size = dfu->data.scsi.lba_size * dfu->data.scsi.lba_blk_size;
+		return 0;
+	case DFU_FS_FAT:
+	case DFU_FS_EXT4:
+		ret = scsi_file_op(DFU_OP_SIZE, dfu, 0, NULL, size);
+		if (ret < 0)
+			return ret;
+		return 0;
+	case DFU_SCRIPT:
+	case DFU_SKIP:
+		return 0;
+	default:
+		printf("%s: Layout (%s) not (yet) supported!\n", __func__,
+		       dfu_get_layout(dfu->layout));
+		return -1;
+	}
+}
+
+static int scsi_file_buf_read(struct dfu_entity *dfu, u64 offset, void *buf, long *len)
+{
+	int ret;
+
+	if (offset == 0 || offset >= dfu_file_buf_offset + dfu_file_buf_len ||
+	    offset + *len < dfu_file_buf_offset) {
+		u64 file_len = CONFIG_SYS_DFU_MAX_FILE_SIZE;
+
+		ret = scsi_file_op(DFU_OP_READ, dfu, offset, dfu_file_buf, &file_len);
+		if (ret < 0)
+			return ret;
+		dfu_file_buf_len = file_len;
+		dfu_file_buf_offset = offset;
+	}
+	if (offset + *len > dfu_file_buf_offset + dfu_file_buf_len)
+		return -EINVAL;
+
+	/* Add to the current buffer. */
+	memcpy(buf, dfu_file_buf + offset - dfu_file_buf_offset, *len);
+
+	return 0;
+}
+
+int dfu_read_medium_scsi(struct dfu_entity *dfu, u64 offset, void *buf, long *len)
+{
+	int ret = -1;
+
+	switch (dfu->layout) {
+	case DFU_RAW_ADDR:
+		ret = scsi_block_op(DFU_OP_READ, dfu, offset, buf, len);
+		break;
+	case DFU_FS_FAT:
+	case DFU_FS_EXT4:
+		ret = scsi_file_buf_read(dfu, offset, buf, len);
+		break;
+	default:
+		printf("%s: Layout (%s) not (yet) supported!\n", __func__,
+		       dfu_get_layout(dfu->layout));
+	}
+
+	return ret;
+}
+
+void dfu_free_entity_scsi(struct dfu_entity *dfu)
+{
+	if (dfu_file_buf) {
+		free(dfu_file_buf);
+		dfu_file_buf = NULL;
+	}
+}
+
+/*
+ * @param s Parameter string containing space-separated arguments:
+ *	1st:
+ *		raw	(raw read/write)
+ *		fat	(files)
+ *		ext4	(^)
+ *		part	(partition image)
+ *	2nd and 3rd:
+ *		lba_start and lba_size, for raw write
+ *		scsi_dev and scsi_part, for filesystems and part
+ */
+int dfu_fill_entity_scsi(struct dfu_entity *dfu, char *devstr, char **argv, int argc)
+{
+	const char *entity_type;
+	ssize_t second_arg;
+	ssize_t third_arg = -1;
+	struct udevice *scsi;
+	struct blk_desc *blk_dev;
+	int ret;
+	char *s;
+
+	if (argc < 2) {
+		pr_err("Need at least one argument\n");
+		return -EINVAL;
+	}
+
+	dfu->data.scsi.lun = dectoul(devstr, &s);
+	if (*s)
+		return -EINVAL;
+
+	entity_type = argv[0];
+	/*
+	 * Base 0 means we'll accept (prefixed with 0x or 0) base 16, 8,
+	 * with default 10.
+	 */
+	second_arg = simple_strtol(argv[1], &s, 0);
+	if (*s)
+		return -EINVAL;
+	if (argc >= 3) {
+		third_arg = simple_strtoul(argv[2], &s, 0);
+		if (*s)
+			return -EINVAL;
+	}
+
+	if (scsi_scan(false)) {
+		pr_err("Couldn't init scsi device.\n");
+		return -ENODEV;
+	}
+
+	ret = find_scsi_device(dfu->data.scsi.lun, &scsi);
+	if (ret < 0) {
+		pr_err("Couldn't find scsi device no. %d.\n", dfu->data.scsi.lun);
+		return -ENODEV;
+	}
+
+	blk_dev = scsi_get_blk_desc(scsi);
+	if (!blk_dev) {
+		pr_err("Couldn't get block device for scsi device no. %d.\n", dfu->data.scsi.lun);
+		return -ENODEV;
+	}
+
+	/* if it's NOT a raw write */
+	if (strcmp(entity_type, "raw")) {
+		dfu->data.scsi.dev = (second_arg != -1) ? second_arg : dfu->data.scsi.lun;
+		dfu->data.scsi.part = third_arg;
+	}
+
+	if (!strcmp(entity_type, "raw")) {
+		dfu->layout = DFU_RAW_ADDR;
+		dfu->data.scsi.lba_start = second_arg;
+		if (third_arg < 0) {
+			pr_err("raw requires two arguments\n");
+			return -EINVAL;
+		}
+		dfu->data.scsi.lba_size = third_arg;
+		dfu->data.scsi.lba_blk_size = blk_dev->blksz;
+
+		/*
+		 * In case the size is zero (i.e. scsi raw 0x10 0),
+		 * assume the user intends to use whole device.
+		 */
+		if (third_arg == 0)
+			dfu->data.scsi.lba_size = blk_dev->lba;
+
+	} else if (!strcmp(entity_type, "part")) {
+		struct disk_partition partinfo;
+		int scsipart = second_arg;
+
+		if (third_arg >= 0) {
+			pr_err("part only accepts one argument\n");
+			return -EINVAL;
+		}
+
+		if (part_get_info(blk_dev, scsipart, &partinfo) != 0) {
+			pr_err("Couldn't find part #%d on scsi device #%d\n", scsipart,
+			       dfu->data.scsi.lun);
+			return -ENODEV;
+		}
+
+		dfu->layout = DFU_RAW_ADDR;
+		dfu->data.scsi.lba_start = partinfo.start;
+		dfu->data.scsi.lba_size = partinfo.size;
+		dfu->data.scsi.lba_blk_size = partinfo.blksz;
+	} else if (!strcmp(entity_type, "fat")) {
+		dfu->layout = DFU_FS_FAT;
+	} else if (!strcmp(entity_type, "ext4")) {
+		dfu->layout = DFU_FS_EXT4;
+	} else if (!strcmp(entity_type, "skip")) {
+		dfu->layout = DFU_SKIP;
+	} else if (!strcmp(entity_type, "script")) {
+		dfu->layout = DFU_SCRIPT;
+	} else {
+		pr_err("Memory layout (%s) not supported!\n", entity_type);
+		return -ENODEV;
+	}
+
+	dfu->dev_type = DFU_DEV_SCSI;
+	dfu->get_medium_size = dfu_get_medium_size_scsi;
+	dfu->read_medium = dfu_read_medium_scsi;
+	dfu->write_medium = dfu_write_medium_scsi;
+	dfu->flush_medium = dfu_flush_medium_scsi;
+	dfu->inited = 0;
+	dfu->free_entity = dfu_free_entity_scsi;
+
+	/* Check if file buffer is ready */
+	if (!dfu_file_buf) {
+		dfu_file_buf = memalign(CONFIG_SYS_CACHELINE_SIZE, CONFIG_SYS_DFU_MAX_FILE_SIZE);
+		if (!dfu_file_buf) {
+			pr_err("Could not memalign 0x%x bytes\n", CONFIG_SYS_DFU_MAX_FILE_SIZE);
+			return -ENOMEM;
+		}
+	}
+
+	return 0;
+}
diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c
index 50a6981..76fcd3f 100644
--- a/drivers/gpio/at91_gpio.c
+++ b/drivers/gpio/at91_gpio.c
@@ -219,6 +219,44 @@
 	val = readl(&at91_port->osr);
 	return val & mask;
 }
+
+static bool at91_is_port_gpio(struct at91_port *at91_port, int offset)
+{
+	u32 mask, val;
+
+	mask = 1 << offset;
+	val = readl(&at91_port->psr);
+	return !!(val & mask);
+}
+
+static void at91_set_port_multi_drive(struct at91_port *at91_port, int offset, int is_on)
+{
+	u32 mask;
+
+	mask = 1 << offset;
+	if (is_on)
+		writel(mask, &at91_port->mder);
+	else
+		writel(mask, &at91_port->mddr);
+}
+
+static bool at91_get_port_multi_drive(struct at91_port *at91_port, int offset)
+{
+	u32 mask, val;
+
+	mask = 1 << offset;
+	val = readl(&at91_port->mdsr);
+	return !!(val & mask);
+}
+
+static bool at91_get_port_pullup(struct at91_port *at91_port, int offset)
+{
+	u32 mask, val;
+
+	mask = 1 << offset;
+	val = readl(&at91_port->pusr);
+	return !(val & mask);
+}
 #endif
 
 static void at91_set_port_input(struct at91_port *at91_port, int offset,
@@ -549,13 +587,68 @@
 {
 	struct at91_port_priv *port = dev_get_priv(dev);
 
-	/* GPIOF_FUNC is not implemented yet */
+	if (!at91_is_port_gpio(port->regs, offset))
+		return GPIOF_FUNC;
+
 	if (at91_get_port_output(port->regs, offset))
 		return GPIOF_OUTPUT;
 	else
 		return GPIOF_INPUT;
 }
 
+static int at91_gpio_set_flags(struct udevice *dev, unsigned int offset,
+			       ulong flags)
+{
+	struct at91_port_priv *port = dev_get_priv(dev);
+	ulong supported_mask;
+
+	supported_mask = GPIOD_OPEN_DRAIN | GPIOD_MASK_DIR | GPIOD_PULL_UP;
+	if (flags & ~supported_mask)
+		return -ENOTSUPP;
+
+	if (flags & GPIOD_IS_OUT) {
+		if (flags & GPIOD_OPEN_DRAIN)
+			at91_set_port_multi_drive(port->regs, offset, true);
+		else
+			at91_set_port_multi_drive(port->regs, offset, false);
+
+		at91_set_port_output(port->regs, offset, flags & GPIOD_IS_OUT_ACTIVE);
+
+	} else if (flags & GPIOD_IS_IN) {
+		at91_set_port_input(port->regs, offset, false);
+	}
+	if (flags & GPIOD_PULL_UP)
+		at91_set_port_pullup(port->regs, offset, true);
+
+	return 0;
+}
+
+static int at91_gpio_get_flags(struct udevice *dev, unsigned int offset,
+			       ulong *flagsp)
+{
+	struct at91_port_priv *port = dev_get_priv(dev);
+	ulong dir_flags = 0;
+
+	if (at91_get_port_output(port->regs, offset)) {
+		dir_flags |= GPIOD_IS_OUT;
+
+		if (at91_get_port_multi_drive(port->regs, offset))
+			dir_flags |= GPIOD_OPEN_DRAIN;
+
+		if (at91_get_port_value(port->regs, offset))
+			dir_flags |= GPIOD_IS_OUT_ACTIVE;
+	} else {
+		dir_flags |= GPIOD_IS_IN;
+	}
+
+	if (at91_get_port_pullup(port->regs, offset))
+		dir_flags |= GPIOD_PULL_UP;
+
+	*flagsp = dir_flags;
+
+	return 0;
+}
+
 static const char *at91_get_bank_name(uint32_t base_addr)
 {
 	switch (base_addr) {
@@ -584,6 +677,8 @@
 	.get_value		= at91_gpio_get_value,
 	.set_value		= at91_gpio_set_value,
 	.get_function		= at91_gpio_get_function,
+	.set_flags		= at91_gpio_set_flags,
+	.get_flags		= at91_gpio_get_flags,
 };
 
 static int at91_gpio_probe(struct udevice *dev)
diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c
index f2ef4e5..cd9f392 100644
--- a/drivers/gpio/qcom_pmic_gpio.c
+++ b/drivers/gpio/qcom_pmic_gpio.c
@@ -69,6 +69,17 @@
 #define REG_EN_CTL             0x46
 #define REG_EN_CTL_ENABLE      (1 << 7)
 
+/**
+ * pmic_gpio_match_data - platform specific configuration
+ *
+ * @PMIC_MATCH_READONLY: treat all GPIOs as readonly, don't attempt to configure them.
+ * This is a workaround for an unknown bug on some platforms where trying to write the
+ * GPIO configuration registers causes the board to hang.
+ */
+enum pmic_gpio_quirks {
+	QCOM_PMIC_QUIRK_READONLY = (1 << 0),
+};
+
 struct qcom_pmic_gpio_data {
 	uint32_t pid; /* Peripheral ID on SPMI bus */
 	bool     lv_mv_type; /* If subtype is GPIO_LV(0x10) or GPIO_MV(0x11) */
@@ -117,8 +128,13 @@
 {
 	struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
 	uint32_t gpio_base = plat->pid + REG_OFFSET(offset);
+	ulong quirks = dev_get_driver_data(dev);
 	int ret = 0;
 
+	/* Some PMICs don't like their GPIOs being configured */
+	if (quirks & QCOM_PMIC_QUIRK_READONLY)
+		return 0;
+
 	/* Disable the GPIO */
 	ret = pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL,
 			      REG_EN_CTL_ENABLE, 0);
@@ -262,6 +278,7 @@
 {
 
 	struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
+	ulong quirks = dev_get_driver_data(dev);
 	struct udevice *child;
 	struct driver *drv;
 	int ret;
@@ -275,7 +292,7 @@
 	/* Bind the GPIO driver as a child of the PMIC. */
 	ret = device_bind_with_driver_data(dev, drv,
 					   dev->name,
-					   0, dev_ofnode(dev), &child);
+					   quirks, dev_ofnode(dev), &child);
 	if (ret)
 		return log_msg_ret("bind", ret);
 
@@ -348,7 +365,7 @@
 	{ .compatible = "qcom,pms405-gpio" },
 	{ .compatible = "qcom,pm6125-gpio" },
 	{ .compatible = "qcom,pm8150-gpio" },
-	{ .compatible = "qcom,pm8550-gpio" },
+	{ .compatible = "qcom,pm8550-gpio", .data = QCOM_PMIC_QUIRK_READONLY },
 	{ }
 };
 
diff --git a/drivers/iommu/apple_dart.c b/drivers/iommu/apple_dart.c
index 3e9e7819..bfd4ad2 100644
--- a/drivers/iommu/apple_dart.c
+++ b/drivers/iommu/apple_dart.c
@@ -322,5 +322,5 @@
 	.ops = &apple_dart_ops,
 	.probe = apple_dart_probe,
 	.remove = apple_dart_remove,
-	.flags	= DM_FLAG_OS_PREPARE
+	.flags	= DM_FLAG_OS_PREPARE | DM_FLAG_VITAL
 };
diff --git a/drivers/iommu/qcom-hyp-smmu.c b/drivers/iommu/qcom-hyp-smmu.c
index 1b5a09b..c1b95bc 100644
--- a/drivers/iommu/qcom-hyp-smmu.c
+++ b/drivers/iommu/qcom-hyp-smmu.c
@@ -91,6 +91,8 @@
 	phys_addr_t base;
 	struct list_head devices;
 	struct udevice *dev;
+	/* SMMU is not needed when running in EL2 */
+	bool disable;
 
 	/* Read-once config */
 	int num_cb;
@@ -134,7 +136,7 @@
 	int count = ofnode_parse_phandle_with_args(node, "iommus",
 						   "#iommu-cells", 0, 0, &args);
 
-	if (count < 0 || args.args[0] == 0) {
+	if (count < 0) {
 		printf("Error: %s: iommus property not found or wrong number of cells\n",
 		       __func__);
 		return -EINVAL;
@@ -277,6 +279,9 @@
 	if (WARN_ON(!priv))
 		return -EINVAL;
 
+	if (priv->disable)
+		return 0;
+
 	mdev = alloc_dev(dev);
 	if (IS_ERR(mdev) && PTR_ERR(mdev) != -EEXIST) {
 		printf("%s: %s Couldn't create mmu context\n", __func__,
@@ -348,6 +353,8 @@
 	priv->base = dev_read_addr(dev);
 	INIT_LIST_HEAD(&priv->devices);
 
+	priv->disable = current_el() > 1;
+
 	/* Read SMMU config */
 	val = gr0_readl(priv, ARM_SMMU_GR0_ID0);
 	priv->num_smr = FIELD_GET(ARM_SMMU_ID0_NUMSMRG, val);
diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c
index 591d71b..a40c8ba 100644
--- a/drivers/misc/imx8/scu_api.c
+++ b/drivers/misc/imx8/scu_api.c
@@ -951,6 +951,26 @@
 	return ret;
 }
 
+int sc_timer_control_siemens_pmic_wdog(sc_ipc_t ipc, u8 cmd)
+{
+	struct udevice *dev = gd->arch.scu_dev;
+	struct sc_rpc_msg_s msg;
+	int size = sizeof(struct sc_rpc_msg_s);
+	int ret;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = (u8)SC_RPC_SVC_TIMER;
+	RPC_FUNC(&msg) = (u8)TIMER_FUNC_CTRL_SIEMENS_PMIC_WDOG;
+	RPC_U8(&msg, 0U) = (u8)cmd;
+	RPC_SIZE(&msg) = 2U;
+
+	ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size);
+	if (ret)
+		printf("%s: res:%d\n", __func__, RPC_R8(&msg));
+
+	return ret;
+}
+
 int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd,
 			 sc_faddr_t addr)
 {
diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c
index 4e5c932..27bb705 100644
--- a/drivers/mmc/msm_sdhci.c
+++ b/drivers/mmc/msm_sdhci.c
@@ -15,6 +15,7 @@
 #include <asm/global_data.h>
 #include <asm/io.h>
 #include <linux/bitops.h>
+#include <power/regulator.h>
 
 /* Non-standard registers needed for SDHCI startup */
 #define SDCC_MCI_POWER   0x0
@@ -43,6 +44,7 @@
 	struct sdhci_host host;
 	void *base;
 	struct clk_bulk clks;
+	struct udevice *vqmmc;
 };
 
 struct msm_sdhc_variant_info {
@@ -163,6 +165,16 @@
 	if (ret)
 		return ret;
 
+	/* Get the vqmmc regulator and enable it if available */
+	device_get_supply_regulator(dev, "vqmmc-supply", &prv->vqmmc);
+	if (prv->vqmmc) {
+		ret = regulator_set_enable_if_allowed(prv->vqmmc, true);
+		if (ret) {
+			printf("Failed to enable the VQMMC regulator\n");
+			return ret;
+		}
+	}
+
 	var_info = (void *)dev_get_driver_data(dev);
 	if (!var_info->mci_removed) {
 		ret = msm_sdc_mci_init(prv);
diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c b/drivers/mtd/nand/raw/atmel/nand-controller.c
index 817fab4..25f187a 100644
--- a/drivers/mtd/nand/raw/atmel/nand-controller.c
+++ b/drivers/mtd/nand/raw/atmel/nand-controller.c
@@ -2205,7 +2205,6 @@
 static int atmel_nand_controller_probe(struct udevice *dev)
 {
 	const struct atmel_nand_controller_caps *caps;
-	struct udevice *pmecc_dev;
 
 	caps = (struct atmel_nand_controller_caps *)dev_get_driver_data(dev);
 	if (!caps) {
@@ -2213,12 +2212,6 @@
 		return -EINVAL;
 	}
 
-	/* Probe pmecc driver */
-	if (uclass_get_device(UCLASS_MTD, 1, &pmecc_dev)) {
-		printf("%s: get device fail\n", __func__);
-		return -EINVAL;
-	}
-
 	return caps->ops->probe(dev, caps);
 }
 
diff --git a/drivers/mtd/nand/raw/atmel/pmecc.c b/drivers/mtd/nand/raw/atmel/pmecc.c
index 51f6bd2..e500a0f 100644
--- a/drivers/mtd/nand/raw/atmel/pmecc.c
+++ b/drivers/mtd/nand/raw/atmel/pmecc.c
@@ -913,6 +913,7 @@
 	ret = ofnode_parse_phandle_with_args(userdev->node_,
 					     "ecc-engine",
 					     NULL, 0, 0, &args);
+	/* Probe pmecc driver */
 	ret = uclass_get_device_by_ofnode(UCLASS_MTD, args.node, &pdev);
 	if (ret)
 		return NULL;
diff --git a/drivers/mtd/ubispl/ubispl.c b/drivers/mtd/ubispl/ubispl.c
index 90a7c4c..9face5f 100644
--- a/drivers/mtd/ubispl/ubispl.c
+++ b/drivers/mtd/ubispl/ubispl.c
@@ -113,7 +113,7 @@
 
 		crc = crc32(UBI_CRC32_INIT, &vtbl[i], UBI_VTBL_RECORD_SIZE_CRC);
 		if (be32_to_cpu(vtbl[i].crc) != crc) {
-			ubi_err("bad CRC at record %u: %#08x, not %#08x",
+			ubi_err("bad CRC at record %u: #%08x, not #%08x",
 				i, crc, be32_to_cpu(vtbl[i].crc));
 			ubi_dump_vtbl_record(&vtbl[i], i);
 			return 1;
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index d6d5cb5..eca681b 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -160,7 +160,7 @@
 	}
 }
 
-static void fec_mii_setspeed(struct ethernet_regs *eth)
+static void fec_mii_setspeed(struct udevice *dev, struct ethernet_regs *eth)
 {
 	/*
 	 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
@@ -182,7 +182,7 @@
 	u32 hold;
 	int ret;
 
-	ret = fec_get_clk_rate(NULL, 0);
+	ret = fec_get_clk_rate(dev, 0);
 	if (ret < 0) {
 		printf("Can't find FEC0 clk rate: %d\n", ret);
 		return;
@@ -581,7 +581,7 @@
 	fec_reg_setup(fec);
 
 	if (fec->xcv_type != SEVENWIRE)
-		fec_mii_setspeed(fec->bus->priv);
+		fec_mii_setspeed(dev, fec->bus->priv);
 
 	/* Set Opcode/Pause Duration Register */
 	writel(0x00010020, &fec->eth->op_pause);	/* FIXME 0xffff0020; */
@@ -996,7 +996,7 @@
 	free(fec->tbd_base);
 }
 
-struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id)
+struct mii_dev *fec_get_miibus(struct udevice *dev, ulong base_addr, int dev_id)
 {
 	struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
 	struct mii_dev *bus;
@@ -1018,7 +1018,7 @@
 		free(bus);
 		return NULL;
 	}
-	fec_mii_setspeed(eth);
+	fec_mii_setspeed(dev, eth);
 	return bus;
 }
 
@@ -1354,10 +1354,10 @@
 	if (!bus) {
 		dm_mii_bus = false;
 #ifdef CONFIG_FEC_MXC_MDIO_BASE
-		bus = fec_get_miibus((ulong)CONFIG_FEC_MXC_MDIO_BASE,
+		bus = fec_get_miibus(dev, (ulong)CONFIG_FEC_MXC_MDIO_BASE,
 				     dev_seq(dev));
 #else
-		bus = fec_get_miibus((ulong)priv->eth, dev_seq(dev));
+		bus = fec_get_miibus(dev, (ulong)priv->eth, dev_seq(dev));
 #endif
 	}
 	if (!bus) {
diff --git a/drivers/phy/qcom/phy-qcom-qmp-ufs.c b/drivers/phy/qcom/phy-qcom-qmp-ufs.c
index 8908a34..5c90d60 100644
--- a/drivers/phy/qcom/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qcom/phy-qcom-qmp-ufs.c
@@ -84,12 +84,6 @@
 	QPHY_LAYOUT_SIZE
 };
 
-static const unsigned int ufsphy_v2_regs_layout[QPHY_LAYOUT_SIZE] = {
-	[QPHY_START_CTRL]		= QPHY_V2_PCS_UFS_PHY_START,
-	[QPHY_PCS_READY_STATUS]		= QPHY_V2_PCS_UFS_READY_STATUS,
-	[QPHY_PCS_POWER_DOWN_CONTROL]	= QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL,
-};
-
 static const unsigned int ufsphy_v3_regs_layout[QPHY_LAYOUT_SIZE] = {
 	[QPHY_START_CTRL]		= QPHY_V3_PCS_UFS_PHY_START,
 	[QPHY_PCS_READY_STATUS]		= QPHY_V3_PCS_UFS_READY_STATUS,
@@ -189,6 +183,29 @@
 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
 };
 
+static const struct qmp_ufs_init_tbl sm8150_ufsphy_hs_g4_tx[] = {
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x75),
+};
+
+static const struct qmp_ufs_init_tbl sm8150_ufsphy_hs_g4_rx[] = {
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x6c),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c),
+};
+
 static const struct qmp_ufs_init_tbl sm8150_ufsphy_serdes[] = {
 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
@@ -461,6 +478,112 @@
 	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
 };
 
+
+static const struct qmp_ufs_init_tbl sc7280_ufsphy_tx[] = {
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
+};
+
+static const struct qmp_ufs_init_tbl sc7280_ufsphy_rx[] = {
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x6d),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x6d),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xed),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3c),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
+};
+
+static const struct qmp_ufs_init_tbl sc7280_ufsphy_pcs[] = {
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_PLL_CNTL, 0x03),
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
+	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
+};
+
+static const struct qmp_ufs_init_tbl sc7280_ufsphy_hs_g4_rx[] = {
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x0f),
+};
+
 struct qmp_ufs_offsets {
 	u16 serdes;
 	u16 pcs;
@@ -623,6 +746,44 @@
 	.no_pcs_sw_reset	= true,
 };
 
+static const struct qmp_ufs_cfg sm8150_ufsphy_cfg = {
+	.lanes			= 2,
+
+	.offsets		= &qmp_ufs_offsets,
+
+	.tbls = {
+		.serdes		= sm8150_ufsphy_serdes,
+		.serdes_num	= ARRAY_SIZE(sm8150_ufsphy_serdes),
+		.tx		= sm8150_ufsphy_tx,
+		.tx_num		= ARRAY_SIZE(sm8150_ufsphy_tx),
+		.rx		= sm8150_ufsphy_rx,
+		.rx_num		= ARRAY_SIZE(sm8150_ufsphy_rx),
+		.pcs		= sm8150_ufsphy_pcs,
+		.pcs_num	= ARRAY_SIZE(sm8150_ufsphy_pcs),
+	},
+	.tbls_hs_b = {
+		.serdes		= sm8150_ufsphy_hs_b_serdes,
+		.serdes_num	= ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
+	},
+	.tbls_hs_g4 = {
+		.tx		= sm8150_ufsphy_hs_g4_tx,
+		.tx_num		= ARRAY_SIZE(sm8150_ufsphy_hs_g4_tx),
+		.rx		= sm8150_ufsphy_hs_g4_rx,
+		.rx_num		= ARRAY_SIZE(sm8150_ufsphy_hs_g4_rx),
+		.pcs		= sm8150_ufsphy_hs_g4_pcs,
+		.pcs_num	= ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
+	},
+	.clk_list		= sdm845_ufs_phy_clk_l,
+	.num_clks		= ARRAY_SIZE(sdm845_ufs_phy_clk_l),
+	.vreg_list		= qmp_ufs_vreg_l,
+	.num_vregs		= ARRAY_SIZE(qmp_ufs_vreg_l),
+	.reset_list		= qmp_ufs_reset_l,
+	.num_resets		= ARRAY_SIZE(qmp_ufs_reset_l),
+	.regs			= ufsphy_v4_regs_layout,
+
+	.no_pcs_sw_reset	= false,
+};
+
 static const struct qmp_ufs_cfg sm8250_ufsphy_cfg = {
 	.lanes			= 2,
 
@@ -713,6 +874,41 @@
 	.no_pcs_sw_reset	= false,
 };
 
+
+static const struct qmp_ufs_cfg sc7280_ufsphy_cfg = {
+	.lanes			= 2,
+
+	.offsets		= &qmp_ufs_offsets,
+
+	.tbls = {
+		.serdes		= sm8150_ufsphy_serdes,
+		.serdes_num	= ARRAY_SIZE(sm8150_ufsphy_serdes),
+		.tx		= sc7280_ufsphy_tx,
+		.tx_num		= ARRAY_SIZE(sc7280_ufsphy_tx),
+		.rx		= sc7280_ufsphy_rx,
+		.rx_num		= ARRAY_SIZE(sc7280_ufsphy_rx),
+		.pcs		= sc7280_ufsphy_pcs,
+		.pcs_num	= ARRAY_SIZE(sc7280_ufsphy_pcs),
+	},
+	.tbls_hs_b = {
+		.serdes		= sm8150_ufsphy_hs_b_serdes,
+		.serdes_num	= ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
+	},
+	.tbls_hs_g4		= {
+		.tx		= sm8250_ufsphy_hs_g4_tx,
+		.tx_num		= ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
+		.rx		= sc7280_ufsphy_hs_g4_rx,
+		.rx_num		= ARRAY_SIZE(sc7280_ufsphy_hs_g4_rx),
+		.pcs		= sm8150_ufsphy_hs_g4_pcs,
+		.pcs_num	= ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
+	},
+	.clk_list		= sdm845_ufs_phy_clk_l,
+	.num_clks		= ARRAY_SIZE(sdm845_ufs_phy_clk_l),
+	.vreg_list		= qmp_ufs_vreg_l,
+	.num_vregs		= ARRAY_SIZE(qmp_ufs_vreg_l),
+	.regs			= ufsphy_v4_regs_layout,
+};
+
 static void qmp_ufs_configure_lane(void __iomem *base,
 					const struct qmp_ufs_init_tbl tbl[],
 					int num,
@@ -1100,9 +1296,11 @@
 
 static const struct udevice_id qmp_ufs_ids[] = {
 	{ .compatible = "qcom,sdm845-qmp-ufs-phy", .data = (ulong)&sdm845_ufsphy_cfg },
+	{ .compatible = "qcom,sm8150-qmp-ufs-phy", .data = (ulong)&sm8150_ufsphy_cfg },
 	{ .compatible = "qcom,sm8250-qmp-ufs-phy", .data = (ulong)&sm8250_ufsphy_cfg },
 	{ .compatible = "qcom,sm8550-qmp-ufs-phy", .data = (ulong)&sm8550_ufsphy_cfg },
 	{ .compatible = "qcom,sm8650-qmp-ufs-phy", .data = (ulong)&sm8650_ufsphy_cfg },
+	{ .compatible = "qcom,sc7280-qmp-ufs-phy", .data = (ulong)&sc7280_ufsphy_cfg, },
 	{ }
 };
 
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 9c466f8..331a46d 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -251,13 +251,6 @@
 
 	priv->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, priv->ref_clk_hz);
 
-	/* Versal and Versal-NET use spi calibration to set read delay */
-	if (CONFIG_IS_ENABLED(ARCH_VERSAL) ||
-	    CONFIG_IS_ENABLED(ARCH_VERSAL_NET) ||
-	    CONFIG_IS_ENABLED(ARCH_VERSAL2))
-		if (priv->read_delay >= 0)
-			priv->read_delay = -1;
-
 	/* Reset ospi flash device */
 	return cadence_qspi_versal_flash_reset(bus);
 }
diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index 36b7d38..d604975 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -446,7 +446,7 @@
 	slave = dev_get_parent_priv(dev);
 	bus_data = dev_get_uclass_priv(bus);
 
-#if CONFIG_IS_ENABLED(SPI_ADVANCE)
+#if CONFIG_IS_ENABLED(SPI_STACKED_PARALLEL)
 	if ((dev_read_bool(dev, "parallel-memories")) && !slave->multi_cs_cap) {
 		dev_err(dev, "controller doesn't support multi CS\n");
 		return -EINVAL;
@@ -515,7 +515,7 @@
 	int mode = 0;
 	int value;
 
-#if CONFIG_IS_ENABLED(SPI_ADVANCE)
+#if CONFIG_IS_ENABLED(SPI_STACKED_PARALLEL)
 	int ret;
 
 	ret = dev_read_u32_array(dev, "reg", plat->cs, SPI_CS_CNT_MAX);
diff --git a/drivers/usb/eth/asix88179.c b/drivers/usb/eth/asix88179.c
index 4bd3b9d..69d3073 100644
--- a/drivers/usb/eth/asix88179.c
+++ b/drivers/usb/eth/asix88179.c
@@ -173,9 +173,10 @@
 #define USB_BULK_SEND_TIMEOUT 5000
 #define USB_BULK_RECV_TIMEOUT 5000
 
-#define AX_RX_URB_SIZE 1024 * 0x12
+#define AX_RX_URB_SIZE 1024 * 0x1a
 #define BLK_FRAME_SIZE 0x200
 #define PHY_CONNECT_TIMEOUT 5000
+#define PHY_RESET_TIMEOUT 500
 
 #define TIMEOUT_RESOLUTION 50	/* ms */
 
@@ -192,10 +193,10 @@
 static const struct {
 	unsigned char ctrl, timer_l, timer_h, size, ifg;
 } AX88179_BULKIN_SIZE[] =	{
-	{7, 0x4f, 0,	0x02, 0xff},
-	{7, 0x20, 3,	0x03, 0xff},
-	{7, 0xae, 7,	0x04, 0xff},
-	{7, 0xcc, 0x4c, 0x04, 8},
+	{7, 0x4f, 0,	0x12, 0xff},
+	{7, 0x20, 3,	0x16, 0xff},
+	{7, 0xae, 7,	0x18, 0xff},
+	{7, 0xcc, 0x4c, 0x18, 8},
 };
 
 /* driver private */
@@ -285,6 +286,26 @@
 	return ret;
 }
 
+static int asix_reset_phy(struct ueth_data *dev)
+{
+	u16 bmcr;
+	u32 t;
+
+	/* Reset the PHY */
+	bmcr = BMCR_RESET;
+	asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_BMCR, 2, &bmcr);
+
+	for (t = 0; t < PHY_RESET_TIMEOUT; t += TIMEOUT_RESOLUTION) {
+		asix_read_cmd(dev, AX_ACCESS_PHY, 0x03, MII_BMCR, 2, &bmcr);
+		if (!(bmcr & BMCR_RESET))
+			return 0;
+		mdelay(TIMEOUT_RESOLUTION);
+	}
+
+	debug("Reset PHY timeout\n");
+	return -ETIMEDOUT;
+}
+
 static int asix_basic_reset(struct ueth_data *dev,
 			struct asix_private *dev_priv)
 {
@@ -311,7 +332,7 @@
 	memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5);
 	asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp);
 
-	dev_priv->rx_urb_size = 128 * 20;
+	dev_priv->rx_urb_size = 1024 * 20;
 
 	/* Water Level configuration */
 	*tmp = 0x34;
@@ -344,14 +365,22 @@
 		 AX_MEDIUM_GIGAMODE | AX_MEDIUM_JUMBO_EN;
 	asix_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 2, 2, tmp16);
 
+	asix_reset_phy(dev);
+
 	u16 adv = 0;
-	adv = ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_LPACK |
-	      ADVERTISE_NPAGE | ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP;
+	adv = ADVERTISE_ALL | ADVERTISE_CSMA |
+	      ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP;
 	asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_ADVERTISE, 2, &adv);
 
 	adv = ADVERTISE_1000FULL;
 	asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_CTRL1000, 2, &adv);
 
+	/* Restart auto-negotiation */
+	u16 bmcr = 0;
+	asix_read_cmd(dev, AX_ACCESS_PHY, 0x03, MII_BMCR, 2, &bmcr);
+	bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
+	asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_BMCR, 2, &bmcr);
+
 	return 0;
 }
 
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 0e45f0a..b39b254 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -351,6 +351,13 @@
 	   In the single stage mode, when the timeout is reached, your system
 	   will be reset by WS1. The first signal (WS0) is ignored.
 
+config WDT_SIEMENS_PMIC
+	bool "Enable PMIC Watchdog Timer support for Siemens platforms"
+	depends on ARCH_IMX8 && WDT
+	help
+	  Select this to enable the PMIC watchdog driver controlled via
+	  IMX8 SCU API found on Siemens platforms.
+
 config WDT_SL28CPLD
 	bool "sl28cpld watchdog timer support"
 	depends on WDT && SL28CPLD
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 0b107c0..9b6b1a8 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -45,6 +45,7 @@
 obj-$(CONFIG_WDT_OMAP3) += omap_wdt.o
 obj-$(CONFIG_WDT_SBSA) += sbsa_gwdt.o
 obj-$(CONFIG_WDT_K3_RTI) += rti_wdt.o
+obj-$(CONFIG_WDT_SIEMENS_PMIC) += siemens_pmic_wdt.o
 obj-$(CONFIG_WDT_SL28CPLD) += sl28cpld-wdt.o
 obj-$(CONFIG_WDT_SP805) += sp805_wdt.o
 obj-$(CONFIG_WDT_STARFIVE) += starfive_wdt.o
diff --git a/drivers/watchdog/siemens_pmic_wdt.c b/drivers/watchdog/siemens_pmic_wdt.c
new file mode 100644
index 0000000..87e817b
--- /dev/null
+++ b/drivers/watchdog/siemens_pmic_wdt.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Driver for a PMIC watchdog timer controlled via Siemens SCU firmware
+ * extensions. Only useful on some Siemens i.MX8-based platforms as
+ * special NXP SCFW is needed which provides the needed SCU API.
+ *
+ * Copyright (C) 2024 Siemens AG
+ */
+
+#include <dm.h>
+#include <wdt.h>
+#include <firmware/imx/sci/sci.h>
+
+/* watchdog commands */
+#define CMD_START_WDT 0x55
+#define CMD_STOP_WDT  0x45
+#define CMD_PING_WDT  0x35
+
+static int scu_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
+{
+	/* start external watchdog via Timer API */
+	return sc_timer_control_siemens_pmic_wdog(-1, CMD_START_WDT);
+}
+
+static int scu_wdt_stop(struct udevice *dev)
+{
+	/* stop external watchdog via Timer API */
+	return sc_timer_control_siemens_pmic_wdog(-1, CMD_STOP_WDT);
+}
+
+static int scu_wdt_reset(struct udevice *dev)
+{
+	return sc_timer_control_siemens_pmic_wdog(-1, CMD_PING_WDT);
+}
+
+static int scu_wdt_probe(struct udevice *dev)
+{
+	debug("%s(dev=%p)\n", __func__, dev);
+	return 0;
+}
+
+static const struct wdt_ops scu_wdt_ops = {
+	.reset		= scu_wdt_reset,
+	.start		= scu_wdt_start,
+	.stop		= scu_wdt_stop,
+};
+
+static const struct udevice_id scu_wdt_ids[] = {
+	{ .compatible = "siemens,scu-wdt" },
+	{ }
+};
+
+U_BOOT_DRIVER(scu_wdt) = {
+	.name		= "scu_wdt",
+	.id		= UCLASS_WDT,
+	.of_match	= scu_wdt_ids,
+	.probe		= scu_wdt_probe,
+	.ops		= &scu_wdt_ops,
+};
diff --git a/dts/upstream/src/arm64/ti/k3-j7200-som-p0.dtsi b/dts/upstream/src/arm64/ti/k3-j7200-som-p0.dtsi
index 21fe194..014cf18 100644
--- a/dts/upstream/src/arm64/ti/k3-j7200-som-p0.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-j7200-som-p0.dtsi
@@ -124,6 +124,7 @@
 	};
 
 	mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
+		bootph-all;
 		pinctrl-single,pins = <
 			J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
 			J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
diff --git a/examples/api/Makefile b/examples/api/Makefile
index ca4eb1f..ec1643e 100644
--- a/examples/api/Makefile
+++ b/examples/api/Makefile
@@ -9,8 +9,12 @@
 LOAD_ADDR = 0x40000
 endif
 ifeq ($(ARCH),arm)
+ifdef CONFIG_64BIT
+LOAD_ADDR = 0x40400000
+else
 LOAD_ADDR = 0x1000000
 endif
+endif
 ifeq ($(ARCH),mips)
 ifdef CONFIG_64BIT
 LOAD_ADDR = 0xffffffff80200000
diff --git a/examples/api/crt0.S b/examples/api/crt0.S
index 06f6d1f..f1b88ed 100644
--- a/examples/api/crt0.S
+++ b/examples/api/crt0.S
@@ -24,7 +24,7 @@
 	mtctr	%r11
 	bctr
 
-#elif defined(CONFIG_ARM)
+#elif defined(CONFIG_ARM) && !defined(CONFIG_ARM64)
 
 	.text
 	.globl _start
@@ -33,26 +33,27 @@
 	str	sp, [ip]
 	b	main
 
-#elif defined(CONFIG_ARM64)
-
-              .text
-              .globl _start
-_start:
-              ldr           ip0, =search_hint
-              str           sp_el2, [ip0]
-              b             main
 
-
-              .globl syscall
+	.globl syscall
 syscall:
-              ldr           ip0, =syscall_ptr
-              ldr           pc_el2, [ip0]
+	ldr	ip, =syscall_ptr
+	ldr	pc, [ip]
 
+#elif defined(CONFIG_ARM64)
+
+	.text
+	.globl _start
+_start:
+	ldr	x17, =search_hint
+	mov	x16, sp
+	str	x16, [x17]
+	b	main
 
 	.globl syscall
 syscall:
-	ldr	ip, =syscall_ptr
-	ldr	pc, [ip]
+	ldr	x16, =syscall_ptr
+	ldr	x16, [x16]
+	br	x16
 
 #elif defined(CONFIG_MIPS)
 #include <asm/asm.h>
@@ -83,6 +84,8 @@
 #error No support for this arch!
 #endif
 
+.section .data
+
 	.globl syscall_ptr
 syscall_ptr:
 	.align	8
@@ -90,4 +93,4 @@
 
 	.globl search_hint
 search_hint:
-	.long   0
+	.long	0
diff --git a/examples/api/demo.c b/examples/api/demo.c
index 677d13b..9a55f76 100644
--- a/examples/api/demo.c
+++ b/examples/api/demo.c
@@ -43,12 +43,11 @@
 	if (sig->version > API_SIG_VERSION)
 		return -3;
 
-	printf("API signature found @%x\n", (unsigned int)sig);
+	printf("API signature found @%p\n", sig);
 	test_dump_sig(sig);
 
 	printf("\n*** Consumer API test ***\n");
-	printf("syscall ptr 0x%08x@%08x\n", (unsigned int)syscall_ptr,
-		(unsigned int)&syscall_ptr);
+	printf("syscall ptr 0x%p@%p\n", syscall_ptr, &syscall_ptr);
 
 	/* console activities */
 	ub_putc('B');
@@ -203,7 +202,7 @@
 	printf("signature:\n");
 	printf("  version\t= %d\n", sig->version);
 	printf("  checksum\t= 0x%08x\n", sig->checksum);
-	printf("  sc entry\t= 0x%08x\n", (unsigned int)sig->syscall);
+	printf("  sc entry\t= 0x%p\n", sig->syscall);
 }
 
 void test_dump_si(struct sys_info *si)
@@ -296,7 +295,7 @@
 	struct device_info *di = ub_dev_get(handle);
 
 	printf("device info (%d):\n", handle);
-	printf("  cookie\t= 0x%08x\n", (uint32_t)di->cookie);
+	printf("  cookie\t= 0x%p\n", di->cookie);
 	printf("  type\t\t= 0x%08x\n", di->type);
 
 	if (di->type == DEV_TYP_NET) {
diff --git a/examples/api/glue.c b/examples/api/glue.c
index 0aaa82b..478f7b6 100644
--- a/examples/api/glue.c
+++ b/examples/api/glue.c
@@ -41,8 +41,8 @@
 int api_search_sig(struct api_signature **sig)
 {
 	unsigned char *sp;
-	uint32_t search_start = 0;
-	uint32_t search_end = 0;
+	uintptr_t search_start = 0;
+	uintptr_t search_end = 0;
 
 	if (sig == NULL)
 		return 0;
diff --git a/fs/btrfs/btrfs.c b/fs/btrfs/btrfs.c
index 350cff0..f3087f6 100644
--- a/fs/btrfs/btrfs.c
+++ b/fs/btrfs/btrfs.c
@@ -193,7 +193,7 @@
 	ret = btrfs_lookup_path(fs_info->fs_root, BTRFS_FIRST_FREE_OBJECTID,
 				file, &root, &ino, &type, 40);
 	if (ret < 0) {
-		printf("Cannot lookup file %s\n", file);
+		debug("Cannot lookup file %s\n", file);
 		return ret;
 	}
 	if (type != BTRFS_FT_REG_FILE) {
diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c
index dfecfa0..1727da2 100644
--- a/fs/ext4/ext4fs.c
+++ b/fs/ext4/ext4fs.c
@@ -213,7 +213,7 @@
 	if (!dirs)
 		return -ENOMEM;
 	dirs->dirname = strdup(dirname);
-	if (!dirs) {
+	if (!dirs->dirname) {
 		free(dirs);
 		return -ENOMEM;
 	}
@@ -224,6 +224,8 @@
 		ret = 0;
 		*dirsp = (struct fs_dir_stream *)dirs;
 	} else {
+		free(dirs->dirname);
+		free(dirs);
 		ret = -ENOENT;
 	}
 
diff --git a/fs/fs.c b/fs/fs.c
index 1afa0fb..21a23ef 100644
--- a/fs/fs.c
+++ b/fs/fs.c
@@ -23,6 +23,7 @@
 #include <time.h>
 #include <ubifs_uboot.h>
 #include <btrfs.h>
+#include <asm/cache.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
 #include <div64.h>
@@ -1001,6 +1002,9 @@
 	char *buf;
 	int ret;
 
+	if (!align)
+		align = ARCH_DMA_MINALIGN;
+
 	buf = memalign(align, size + 1);
 	if (!buf)
 		return log_msg_ret("buf", -ENOMEM);
diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h
index 1f61b2b..4d95f3f 100644
--- a/include/configs/capricorn-common.h
+++ b/include/configs/capricorn-common.h
@@ -95,7 +95,9 @@
 #define CFG_SYS_SDRAM_BASE		0x80000000
 #define PHYS_SDRAM_1			0x80000000
 #define PHYS_SDRAM_2			0x880000000
-/* DDR3 board total DDR is 1 GB */
+/* Set default values to the smallest DDR we have in capricorn modules
+ * Use it in case the system controller would return an error
+ */
 #define PHYS_SDRAM_1_SIZE		0x40000000	/* 1 GB */
 #define PHYS_SDRAM_2_SIZE		0x00000000	/* 0 GB */
 
diff --git a/include/configs/deneb.h b/include/configs/deneb.h
deleted file mode 100644
index f155bb8..0000000
--- a/include/configs/deneb.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2019 Siemens AG
- *
- */
-
-#ifndef __DENEB_H
-#define __DENEB_H
-
-#include "capricorn-common.h"
-
-/* DDR3 board total DDR is 2 GB */
-#undef PHYS_SDRAM_1_SIZE
-#define PHYS_SDRAM_1_SIZE		0x80000000	/* 2 GB */
-
-#endif /* __DENEB_H */
diff --git a/include/configs/khadas-vim3_android.h b/include/configs/khadas-vim3_android.h
index 0e2953f..551ab51 100644
--- a/include/configs/khadas-vim3_android.h
+++ b/include/configs/khadas-vim3_android.h
@@ -41,10 +41,27 @@
 	"name=rootfs,size=-,uuid=" ROOT_UUID
 #endif
 
-#define EXTRA_ANDROID_ENV_SETTINGS \
-	"board=vim3\0" \
-	"board_name=vim3\0" \
+#define CFG_EXTRA_ENV_SETTINGS                                    \
+	"board=vim3\0"                                               \
+	"board_name=vim3\0"                                          \
+	"bootmeths=android\0"                                         \
+	"bootcmd=bootflow scan\0"                                     \
+	"adtb_idx=3\0"                                                \
+	"partitions=" PARTS_DEFAULT "\0"                              \
+	"mmcdev=2\0"                                                  \
+	"fastboot_raw_partition_bootloader=0x1 0xfff mmcpart 1\0"     \
+	"fastboot_raw_partition_bootenv=0x0 0xfff mmcpart 2\0"        \
+	"stdin=" STDIN_CFG "\0"                                       \
+	"stdout=" STDOUT_CFG "\0"                                     \
+	"stderr=" STDOUT_CFG "\0"                                     \
+	"dtboaddr=0x08200000\0"                                       \
+	"loadaddr=0x01080000\0"                                       \
+	"fdt_addr_r=0x01000000\0"                                     \
+	"scriptaddr=0x08000000\0"                                     \
+	"kernel_addr_r=0x01080000\0"                                  \
+	"pxefile_addr_r=0x01080000\0"                                 \
+	"ramdisk_addr_r=0x13000000\0"                                 \
 
-#include <configs/meson64_android.h>
+#include <configs/meson64.h>
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/khadas-vim3l_android.h b/include/configs/khadas-vim3l_android.h
index f39a378..1869249 100644
--- a/include/configs/khadas-vim3l_android.h
+++ b/include/configs/khadas-vim3l_android.h
@@ -41,10 +41,27 @@
 	"name=rootfs,size=-,uuid=" ROOT_UUID
 #endif
 
-#define EXTRA_ANDROID_ENV_SETTINGS \
-	"board=vim3l\0" \
-	"board_name=vim3l\0" \
+#define CFG_EXTRA_ENV_SETTINGS                                    \
+	"board=vim3l\0"                                               \
+	"board_name=vim3l\0"                                          \
+	"bootmeths=android\0"                                         \
+	"bootcmd=bootflow scan\0"                                     \
+	"adtb_idx=2\0"                                                \
+	"partitions=" PARTS_DEFAULT "\0"                              \
+	"mmcdev=2\0"                                                  \
+	"fastboot_raw_partition_bootloader=0x1 0xfff mmcpart 1\0"     \
+	"fastboot_raw_partition_bootenv=0x0 0xfff mmcpart 2\0"        \
+	"stdin=" STDIN_CFG "\0"                                       \
+	"stdout=" STDOUT_CFG "\0"                                     \
+	"stderr=" STDOUT_CFG "\0"                                     \
+	"dtboaddr=0x08200000\0"                                       \
+	"loadaddr=0x01080000\0"                                       \
+	"fdt_addr_r=0x01000000\0"                                     \
+	"scriptaddr=0x08000000\0"                                     \
+	"kernel_addr_r=0x01080000\0"                                  \
+	"pxefile_addr_r=0x01080000\0"                                 \
+	"ramdisk_addr_r=0x13000000\0"                                 \
 
-#include <configs/meson64_android.h>
+#include <configs/meson64.h>
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/meson64_android.h b/include/configs/meson64_android.h
index 77364bb..d6ef0a8 100644
--- a/include/configs/meson64_android.h
+++ b/include/configs/meson64_android.h
@@ -104,12 +104,6 @@
 	"elif test $board_name = sei610; then " \
 		"echo \"  Reading DTB for sei610...\"; " \
 		"setenv dtb_index 1;" \
-	"elif test $board_name = vim3l; then " \
-		"echo \"  Reading DTB for vim3l...\"; " \
-		"setenv dtb_index 2;" \
-	"elif test $board_name = vim3; then " \
-		"echo \"  Reading DTB for vim3...\"; " \
-		"setenv dtb_index 3;" \
 	"else " \
 		"echo Error: Android boot is not supported for $board_name; " \
 		"exit; " \
diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index 6740ab2..3bcc4c4 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -82,7 +82,7 @@
 	"nor0=flash-0\0"\
 	"mtdparts=mtdparts=flash-0:"\
 	"256k(u-boot),256k(env),3m(kernel),"\
-	"1m(romfs),1m(cramfs),-(jffs2)\0"\
+	"1m(romfs),1m(cramfs),-(fs)\0"\
 	"nc=setenv stdout nc;"\
 	"setenv stdin nc\0" \
 	"serial=setenv stdout serial;"\
diff --git a/include/configs/qcom.h b/include/configs/qcom.h
index 5b5ebbd..9b41ab9 100644
--- a/include/configs/qcom.h
+++ b/include/configs/qcom.h
@@ -11,4 +11,9 @@
 
 #define CFG_SYS_BAUDRATE_TABLE	{ 115200, 230400, 460800, 921600 }
 
+// 2a5aa852-b856-4d97-baa9-5c5f4421551f
+#define QUALCOMM_UBOOT_BOOT_IMAGE_GUID \
+	EFI_GUID(0x2a5aa852, 0xb856, 0x4d97, 0xba, 0xa9, \
+		0x5c, 0x5f, 0x44, 0x21, 0x55, 0x1f)
+
 #endif
diff --git a/include/configs/stm32mp15_dh_dhsom.h b/include/configs/stm32mp15_dh_dhsom.h
index 2797fc6..c004a8c 100644
--- a/include/configs/stm32mp15_dh_dhsom.h
+++ b/include/configs/stm32mp15_dh_dhsom.h
@@ -18,6 +18,8 @@
 #endif
 
 #define STM32MP_BOARD_EXTRA_ENV						\
+	"dh_preboot="							\
+		"run dh_testbench_backward_compat\0"			\
 	"dh_update_sd_to_emmc=" /* Install U-Boot from SD to eMMC */	\
 		"setexpr loadaddr1 ${loadaddr} + 0x1000000 && "		\
 		"load mmc 0:4 ${loadaddr1} boot/u-boot-spl.stm32 && "	\
@@ -61,7 +63,20 @@
 	"stdout=serial\0"						\
 	"stderr=serial\0"						\
 	"update_sf=run dh_update_sd_to_sf\0"				\
-	"usb_pgood_delay=1000\0"
+	"usb_pgood_delay=1000\0"					\
+	/* Old testbench-only backward compatibility environment */	\
+	"dh_testbench_backward_compat="					\
+		"test ${board_name} = \"dh,stm32mp15xx-dhcor-testbench\" && " \
+		"run load_bootenv importbootenv\0"			\
+	"importbootenv="						\
+		"echo Importing environment from DHupdate.ini...;"	\
+		"env import -t ${loadaddr} ${filesize}\0"		\
+	"load_bootenv="							\
+		"usb reset && "						\
+		"load usb ${usbdev}:${usbpart} ${loadaddr} DHupdate.ini && " \
+		"echo \"--> Update: found DHupdate.ini (${filesize} bytes)\"\0" \
+	"usbdev=0\0"							\
+	"usbpart=1\0"
 
 #include <configs/stm32mp15_common.h>
 
diff --git a/include/dfu.h b/include/dfu.h
index e25588c..12f9dfc 100644
--- a/include/dfu.h
+++ b/include/dfu.h
@@ -24,6 +24,7 @@
 	DFU_DEV_SF,
 	DFU_DEV_MTD,
 	DFU_DEV_VIRT,
+	DFU_DEV_SCSI,
 };
 
 enum dfu_layout {
@@ -99,6 +100,19 @@
 	int dev_num;
 };
 
+struct scsi_internal_data {
+	int lun;
+
+	/* RAW programming */
+	unsigned int lba_start;
+	unsigned int lba_size;
+	unsigned int lba_blk_size;
+
+	/* FAT/EXT */
+	unsigned int dev; // Always 0???
+	unsigned int part;
+};
+
 #if defined(CONFIG_DFU_NAME_MAX_SIZE)
 #define DFU_NAME_SIZE			CONFIG_DFU_NAME_MAX_SIZE
 #else
@@ -126,6 +140,7 @@
 		struct ram_internal_data ram;
 		struct sf_internal_data sf;
 		struct virt_internal_data virt;
+		struct scsi_internal_data scsi;
 	} data;
 
 	int (*get_medium_size)(struct dfu_entity *dfu, u64 *size);
@@ -516,6 +531,18 @@
 }
 #endif
 
+#if CONFIG_IS_ENABLED(DFU_SCSI)
+int dfu_fill_entity_scsi(struct dfu_entity *dfu, char *devstr,
+			 char **argv, int argc);
+#else
+static inline int dfu_fill_entity_scsi(struct dfu_entity *dfu, char *devstr,
+				       char **argv, int argc)
+{
+	puts("SCSI support not available!\n");
+	return -1;
+}
+#endif
+
 extern bool dfu_reinit_needed;
 extern bool dfu_alt_info_changed;
 
diff --git a/include/dm/root.h b/include/dm/root.h
index b2f30a8..5651b86 100644
--- a/include/dm/root.h
+++ b/include/dm/root.h
@@ -167,8 +167,18 @@
  * Return: 0 if OK, -ve on error
  */
 int dm_remove_devices_flags(uint flags);
+
+/**
+ * dm_remove_devices_active - Call remove function of all active drivers heeding
+ *                            device dependencies as far as know, i.e. removing
+ *                            devices marked with DM_FLAG_VITAL last.
+ *
+ * All active devices will be removed
+ */
+void dm_remove_devices_active(void);
 #else
 static inline int dm_remove_devices_flags(uint flags) { return 0; }
+static inline void dm_remove_devices_active(void) { }
 #endif
 
 /**
diff --git a/include/dt-bindings/clock/qcom,camcc-sdm845.h b/include/dt-bindings/clock/qcom,camcc-sdm845.h
deleted file mode 100644
index 4f7a2d2..0000000
--- a/include/dt-bindings/clock/qcom,camcc-sdm845.h
+++ /dev/null
@@ -1,116 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2018, The Linux Foundation. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H
-#define _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H
-
-/* CAM_CC clock registers */
-#define CAM_CC_BPS_AHB_CLK				0
-#define CAM_CC_BPS_AREG_CLK				1
-#define CAM_CC_BPS_AXI_CLK				2
-#define CAM_CC_BPS_CLK					3
-#define CAM_CC_BPS_CLK_SRC				4
-#define CAM_CC_CAMNOC_ATB_CLK				5
-#define CAM_CC_CAMNOC_AXI_CLK				6
-#define CAM_CC_CCI_CLK					7
-#define CAM_CC_CCI_CLK_SRC				8
-#define CAM_CC_CPAS_AHB_CLK				9
-#define CAM_CC_CPHY_RX_CLK_SRC				10
-#define CAM_CC_CSI0PHYTIMER_CLK				11
-#define CAM_CC_CSI0PHYTIMER_CLK_SRC			12
-#define CAM_CC_CSI1PHYTIMER_CLK				13
-#define CAM_CC_CSI1PHYTIMER_CLK_SRC			14
-#define CAM_CC_CSI2PHYTIMER_CLK				15
-#define CAM_CC_CSI2PHYTIMER_CLK_SRC			16
-#define CAM_CC_CSI3PHYTIMER_CLK				17
-#define CAM_CC_CSI3PHYTIMER_CLK_SRC			18
-#define CAM_CC_CSIPHY0_CLK				19
-#define CAM_CC_CSIPHY1_CLK				20
-#define CAM_CC_CSIPHY2_CLK				21
-#define CAM_CC_CSIPHY3_CLK				22
-#define CAM_CC_FAST_AHB_CLK_SRC				23
-#define CAM_CC_FD_CORE_CLK				24
-#define CAM_CC_FD_CORE_CLK_SRC				25
-#define CAM_CC_FD_CORE_UAR_CLK				26
-#define CAM_CC_ICP_APB_CLK				27
-#define CAM_CC_ICP_ATB_CLK				28
-#define CAM_CC_ICP_CLK					29
-#define CAM_CC_ICP_CLK_SRC				30
-#define CAM_CC_ICP_CTI_CLK				31
-#define CAM_CC_ICP_TS_CLK				32
-#define CAM_CC_IFE_0_AXI_CLK				33
-#define CAM_CC_IFE_0_CLK				34
-#define CAM_CC_IFE_0_CLK_SRC				35
-#define CAM_CC_IFE_0_CPHY_RX_CLK			36
-#define CAM_CC_IFE_0_CSID_CLK				37
-#define CAM_CC_IFE_0_CSID_CLK_SRC			38
-#define CAM_CC_IFE_0_DSP_CLK				39
-#define CAM_CC_IFE_1_AXI_CLK				40
-#define CAM_CC_IFE_1_CLK				41
-#define CAM_CC_IFE_1_CLK_SRC				42
-#define CAM_CC_IFE_1_CPHY_RX_CLK			43
-#define CAM_CC_IFE_1_CSID_CLK				44
-#define CAM_CC_IFE_1_CSID_CLK_SRC			45
-#define CAM_CC_IFE_1_DSP_CLK				46
-#define CAM_CC_IFE_LITE_CLK				47
-#define CAM_CC_IFE_LITE_CLK_SRC				48
-#define CAM_CC_IFE_LITE_CPHY_RX_CLK			49
-#define CAM_CC_IFE_LITE_CSID_CLK			50
-#define CAM_CC_IFE_LITE_CSID_CLK_SRC			51
-#define CAM_CC_IPE_0_AHB_CLK				52
-#define CAM_CC_IPE_0_AREG_CLK				53
-#define CAM_CC_IPE_0_AXI_CLK				54
-#define CAM_CC_IPE_0_CLK				55
-#define CAM_CC_IPE_0_CLK_SRC				56
-#define CAM_CC_IPE_1_AHB_CLK				57
-#define CAM_CC_IPE_1_AREG_CLK				58
-#define CAM_CC_IPE_1_AXI_CLK				59
-#define CAM_CC_IPE_1_CLK				60
-#define CAM_CC_IPE_1_CLK_SRC				61
-#define CAM_CC_JPEG_CLK					62
-#define CAM_CC_JPEG_CLK_SRC				63
-#define CAM_CC_LRME_CLK					64
-#define CAM_CC_LRME_CLK_SRC				65
-#define CAM_CC_MCLK0_CLK				66
-#define CAM_CC_MCLK0_CLK_SRC				67
-#define CAM_CC_MCLK1_CLK				68
-#define CAM_CC_MCLK1_CLK_SRC				69
-#define CAM_CC_MCLK2_CLK				70
-#define CAM_CC_MCLK2_CLK_SRC				71
-#define CAM_CC_MCLK3_CLK				72
-#define CAM_CC_MCLK3_CLK_SRC				73
-#define CAM_CC_PLL0					74
-#define CAM_CC_PLL0_OUT_EVEN				75
-#define CAM_CC_PLL1					76
-#define CAM_CC_PLL1_OUT_EVEN				77
-#define CAM_CC_PLL2					78
-#define CAM_CC_PLL2_OUT_EVEN				79
-#define CAM_CC_PLL3					80
-#define CAM_CC_PLL3_OUT_EVEN				81
-#define CAM_CC_SLOW_AHB_CLK_SRC				82
-#define CAM_CC_SOC_AHB_CLK				83
-#define CAM_CC_SYS_TMR_CLK				84
-
-/* CAM_CC Resets */
-#define TITAN_CAM_CC_CCI_BCR				0
-#define TITAN_CAM_CC_CPAS_BCR				1
-#define TITAN_CAM_CC_CSI0PHY_BCR			2
-#define TITAN_CAM_CC_CSI1PHY_BCR			3
-#define TITAN_CAM_CC_CSI2PHY_BCR			4
-#define TITAN_CAM_CC_MCLK0_BCR				5
-#define TITAN_CAM_CC_MCLK1_BCR				6
-#define TITAN_CAM_CC_MCLK2_BCR				7
-#define TITAN_CAM_CC_MCLK3_BCR				8
-#define TITAN_CAM_CC_TITAN_TOP_BCR			9
-
-/* CAM_CC GDSCRs */
-#define BPS_GDSC					0
-#define IPE_0_GDSC					1
-#define IPE_1_GDSC					2
-#define IFE_0_GDSC					3
-#define IFE_1_GDSC					4
-#define TITAN_TOP_GDSC					5
-
-#endif
diff --git a/include/dt-bindings/clock/qcom,dispcc-sdm845.h b/include/dt-bindings/clock/qcom,dispcc-sdm845.h
deleted file mode 100644
index 4016fd1..0000000
--- a/include/dt-bindings/clock/qcom,dispcc-sdm845.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H
-#define _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H
-
-/* DISP_CC clock registers */
-#define DISP_CC_MDSS_AHB_CLK					0
-#define DISP_CC_MDSS_AXI_CLK					1
-#define DISP_CC_MDSS_BYTE0_CLK					2
-#define DISP_CC_MDSS_BYTE0_CLK_SRC				3
-#define DISP_CC_MDSS_BYTE0_INTF_CLK				4
-#define DISP_CC_MDSS_BYTE1_CLK					5
-#define DISP_CC_MDSS_BYTE1_CLK_SRC				6
-#define DISP_CC_MDSS_BYTE1_INTF_CLK				7
-#define DISP_CC_MDSS_ESC0_CLK					8
-#define DISP_CC_MDSS_ESC0_CLK_SRC				9
-#define DISP_CC_MDSS_ESC1_CLK					10
-#define DISP_CC_MDSS_ESC1_CLK_SRC				11
-#define DISP_CC_MDSS_MDP_CLK					12
-#define DISP_CC_MDSS_MDP_CLK_SRC				13
-#define DISP_CC_MDSS_MDP_LUT_CLK				14
-#define DISP_CC_MDSS_PCLK0_CLK					15
-#define DISP_CC_MDSS_PCLK0_CLK_SRC				16
-#define DISP_CC_MDSS_PCLK1_CLK					17
-#define DISP_CC_MDSS_PCLK1_CLK_SRC				18
-#define DISP_CC_MDSS_ROT_CLK					19
-#define DISP_CC_MDSS_ROT_CLK_SRC				20
-#define DISP_CC_MDSS_RSCC_AHB_CLK				21
-#define DISP_CC_MDSS_RSCC_VSYNC_CLK				22
-#define DISP_CC_MDSS_VSYNC_CLK					23
-#define DISP_CC_MDSS_VSYNC_CLK_SRC				24
-#define DISP_CC_PLL0						25
-#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC				26
-#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC				27
-#define DISP_CC_MDSS_DP_AUX_CLK					28
-#define DISP_CC_MDSS_DP_AUX_CLK_SRC				29
-#define DISP_CC_MDSS_DP_CRYPTO_CLK				30
-#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC				31
-#define DISP_CC_MDSS_DP_LINK_CLK				32
-#define DISP_CC_MDSS_DP_LINK_CLK_SRC				33
-#define DISP_CC_MDSS_DP_LINK_INTF_CLK				34
-#define DISP_CC_MDSS_DP_PIXEL1_CLK				35
-#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC				36
-#define DISP_CC_MDSS_DP_PIXEL_CLK				37
-#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC				38
-
-/* DISP_CC Reset */
-#define DISP_CC_MDSS_RSCC_BCR					0
-
-/* DISP_CC GDSCR */
-#define MDSS_GDSC						0
-
-#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8916.h b/include/dt-bindings/clock/qcom,gcc-msm8916.h
deleted file mode 100644
index 5630344..0000000
--- a/include/dt-bindings/clock/qcom,gcc-msm8916.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright 2015 Linaro Limited
- */
-
-#ifndef _DT_BINDINGS_CLK_MSM_GCC_8916_H
-#define _DT_BINDINGS_CLK_MSM_GCC_8916_H
-
-#define GPLL0					0
-#define GPLL0_VOTE				1
-#define BIMC_PLL				2
-#define BIMC_PLL_VOTE				3
-#define GPLL1					4
-#define GPLL1_VOTE				5
-#define GPLL2					6
-#define GPLL2_VOTE				7
-#define PCNOC_BFDCD_CLK_SRC			8
-#define SYSTEM_NOC_BFDCD_CLK_SRC		9
-#define CAMSS_AHB_CLK_SRC			10
-#define APSS_AHB_CLK_SRC			11
-#define CSI0_CLK_SRC				12
-#define CSI1_CLK_SRC				13
-#define GFX3D_CLK_SRC				14
-#define VFE0_CLK_SRC				15
-#define BLSP1_QUP1_I2C_APPS_CLK_SRC		16
-#define BLSP1_QUP1_SPI_APPS_CLK_SRC		17
-#define BLSP1_QUP2_I2C_APPS_CLK_SRC		18
-#define BLSP1_QUP2_SPI_APPS_CLK_SRC		19
-#define BLSP1_QUP3_I2C_APPS_CLK_SRC		20
-#define BLSP1_QUP3_SPI_APPS_CLK_SRC		21
-#define BLSP1_QUP4_I2C_APPS_CLK_SRC		22
-#define BLSP1_QUP4_SPI_APPS_CLK_SRC		23
-#define BLSP1_QUP5_I2C_APPS_CLK_SRC		24
-#define BLSP1_QUP5_SPI_APPS_CLK_SRC		25
-#define BLSP1_QUP6_I2C_APPS_CLK_SRC		26
-#define BLSP1_QUP6_SPI_APPS_CLK_SRC		27
-#define BLSP1_UART1_APPS_CLK_SRC		28
-#define BLSP1_UART2_APPS_CLK_SRC		29
-#define CCI_CLK_SRC				30
-#define CAMSS_GP0_CLK_SRC			31
-#define CAMSS_GP1_CLK_SRC			32
-#define JPEG0_CLK_SRC				33
-#define MCLK0_CLK_SRC				34
-#define MCLK1_CLK_SRC				35
-#define CSI0PHYTIMER_CLK_SRC			36
-#define CSI1PHYTIMER_CLK_SRC			37
-#define CPP_CLK_SRC				38
-#define CRYPTO_CLK_SRC				39
-#define GP1_CLK_SRC				40
-#define GP2_CLK_SRC				41
-#define GP3_CLK_SRC				42
-#define BYTE0_CLK_SRC				43
-#define ESC0_CLK_SRC				44
-#define MDP_CLK_SRC				45
-#define PCLK0_CLK_SRC				46
-#define VSYNC_CLK_SRC				47
-#define PDM2_CLK_SRC				48
-#define SDCC1_APPS_CLK_SRC			49
-#define SDCC2_APPS_CLK_SRC			50
-#define APSS_TCU_CLK_SRC			51
-#define USB_HS_SYSTEM_CLK_SRC			52
-#define VCODEC0_CLK_SRC				53
-#define GCC_BLSP1_AHB_CLK			54
-#define GCC_BLSP1_SLEEP_CLK			55
-#define GCC_BLSP1_QUP1_I2C_APPS_CLK		56
-#define GCC_BLSP1_QUP1_SPI_APPS_CLK		57
-#define GCC_BLSP1_QUP2_I2C_APPS_CLK		58
-#define GCC_BLSP1_QUP2_SPI_APPS_CLK		59
-#define GCC_BLSP1_QUP3_I2C_APPS_CLK		60
-#define GCC_BLSP1_QUP3_SPI_APPS_CLK		61
-#define GCC_BLSP1_QUP4_I2C_APPS_CLK		62
-#define GCC_BLSP1_QUP4_SPI_APPS_CLK		63
-#define GCC_BLSP1_QUP5_I2C_APPS_CLK		64
-#define GCC_BLSP1_QUP5_SPI_APPS_CLK		65
-#define GCC_BLSP1_QUP6_I2C_APPS_CLK		66
-#define GCC_BLSP1_QUP6_SPI_APPS_CLK		67
-#define GCC_BLSP1_UART1_APPS_CLK		68
-#define GCC_BLSP1_UART2_APPS_CLK		69
-#define GCC_BOOT_ROM_AHB_CLK			70
-#define GCC_CAMSS_CCI_AHB_CLK			71
-#define GCC_CAMSS_CCI_CLK			72
-#define GCC_CAMSS_CSI0_AHB_CLK			73
-#define GCC_CAMSS_CSI0_CLK			74
-#define GCC_CAMSS_CSI0PHY_CLK			75
-#define GCC_CAMSS_CSI0PIX_CLK			76
-#define GCC_CAMSS_CSI0RDI_CLK			77
-#define GCC_CAMSS_CSI1_AHB_CLK			78
-#define GCC_CAMSS_CSI1_CLK			79
-#define GCC_CAMSS_CSI1PHY_CLK			80
-#define GCC_CAMSS_CSI1PIX_CLK			81
-#define GCC_CAMSS_CSI1RDI_CLK			82
-#define GCC_CAMSS_CSI_VFE0_CLK			83
-#define GCC_CAMSS_GP0_CLK			84
-#define GCC_CAMSS_GP1_CLK			85
-#define GCC_CAMSS_ISPIF_AHB_CLK			86
-#define GCC_CAMSS_JPEG0_CLK			87
-#define GCC_CAMSS_JPEG_AHB_CLK			88
-#define GCC_CAMSS_JPEG_AXI_CLK			89
-#define GCC_CAMSS_MCLK0_CLK			90
-#define GCC_CAMSS_MCLK1_CLK			91
-#define GCC_CAMSS_MICRO_AHB_CLK			92
-#define GCC_CAMSS_CSI0PHYTIMER_CLK		93
-#define GCC_CAMSS_CSI1PHYTIMER_CLK		94
-#define GCC_CAMSS_AHB_CLK			95
-#define GCC_CAMSS_TOP_AHB_CLK			96
-#define GCC_CAMSS_CPP_AHB_CLK			97
-#define GCC_CAMSS_CPP_CLK			98
-#define GCC_CAMSS_VFE0_CLK			99
-#define GCC_CAMSS_VFE_AHB_CLK			100
-#define GCC_CAMSS_VFE_AXI_CLK			101
-#define GCC_CRYPTO_AHB_CLK			102
-#define GCC_CRYPTO_AXI_CLK			103
-#define GCC_CRYPTO_CLK				104
-#define GCC_OXILI_GMEM_CLK			105
-#define GCC_GP1_CLK				106
-#define GCC_GP2_CLK				107
-#define GCC_GP3_CLK				108
-#define GCC_MDSS_AHB_CLK			109
-#define GCC_MDSS_AXI_CLK			110
-#define GCC_MDSS_BYTE0_CLK			111
-#define GCC_MDSS_ESC0_CLK			112
-#define GCC_MDSS_MDP_CLK			113
-#define GCC_MDSS_PCLK0_CLK			114
-#define GCC_MDSS_VSYNC_CLK			115
-#define GCC_MSS_CFG_AHB_CLK			116
-#define GCC_OXILI_AHB_CLK			117
-#define GCC_OXILI_GFX3D_CLK			118
-#define GCC_PDM2_CLK				119
-#define GCC_PDM_AHB_CLK				120
-#define GCC_PRNG_AHB_CLK			121
-#define GCC_SDCC1_AHB_CLK			122
-#define GCC_SDCC1_APPS_CLK			123
-#define GCC_SDCC2_AHB_CLK			124
-#define GCC_SDCC2_APPS_CLK			125
-#define GCC_GTCU_AHB_CLK			126
-#define GCC_JPEG_TBU_CLK			127
-#define GCC_MDP_TBU_CLK				128
-#define GCC_SMMU_CFG_CLK			129
-#define GCC_VENUS_TBU_CLK			130
-#define GCC_VFE_TBU_CLK				131
-#define GCC_USB2A_PHY_SLEEP_CLK			132
-#define GCC_USB_HS_AHB_CLK			133
-#define GCC_USB_HS_SYSTEM_CLK			134
-#define GCC_VENUS0_AHB_CLK			135
-#define GCC_VENUS0_AXI_CLK			136
-#define GCC_VENUS0_VCODEC0_CLK			137
-#define BIMC_DDR_CLK_SRC			138
-#define GCC_APSS_TCU_CLK			139
-#define GCC_GFX_TCU_CLK				140
-#define BIMC_GPU_CLK_SRC			141
-#define GCC_BIMC_GFX_CLK			142
-#define GCC_BIMC_GPU_CLK			143
-#define ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC		144
-#define ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC		145
-#define ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC		146
-#define ULTAUDIO_XO_CLK_SRC			147
-#define ULTAUDIO_AHBFABRIC_CLK_SRC		148
-#define CODEC_DIGCODEC_CLK_SRC			149
-#define GCC_ULTAUDIO_PCNOC_MPORT_CLK		150
-#define GCC_ULTAUDIO_PCNOC_SWAY_CLK		151
-#define GCC_ULTAUDIO_AVSYNC_XO_CLK		152
-#define GCC_ULTAUDIO_STC_XO_CLK			153
-#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK	154
-#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK	155
-#define GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK		156
-#define GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK		157
-#define GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK		158
-#define GCC_CODEC_DIGCODEC_CLK			159
-#define GCC_MSS_Q6_BIMC_AXI_CLK			160
-
-/* Indexes for GDSCs */
-#define BIMC_GDSC				0
-#define VENUS_GDSC				1
-#define MDSS_GDSC				2
-#define JPEG_GDSC				3
-#define VFE_GDSC				4
-#define OXILI_GDSC				5
-
-#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8996.h b/include/dt-bindings/clock/qcom,gcc-msm8996.h
deleted file mode 100644
index de5c36c..0000000
--- a/include/dt-bindings/clock/qcom,gcc-msm8996.h
+++ /dev/null
@@ -1,361 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2015, The Linux Foundation. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_CLK_MSM_GCC_8996_H
-#define _DT_BINDINGS_CLK_MSM_GCC_8996_H
-
-#define GPLL0_EARLY						0
-#define GPLL0							1
-#define GPLL1_EARLY						2
-#define GPLL1							3
-#define GPLL2_EARLY						4
-#define GPLL2							5
-#define GPLL3_EARLY						6
-#define GPLL3							7
-#define GPLL4_EARLY						8
-#define GPLL4							9
-#define SYSTEM_NOC_CLK_SRC					10
-/* U-Boot: KConfig check in CI erroneously picks this up, it's unused
- * anyway so comment it out for now
- */
-//#define CONFIG _NOC_CLK_SRC					11
-#define PERIPH_NOC_CLK_SRC					12
-#define MMSS_BIMC_GFX_CLK_SRC					13
-#define USB30_MASTER_CLK_SRC					14
-#define USB30_MOCK_UTMI_CLK_SRC					15
-#define USB3_PHY_AUX_CLK_SRC					16
-#define USB20_MASTER_CLK_SRC					17
-#define USB20_MOCK_UTMI_CLK_SRC					18
-#define SDCC1_APPS_CLK_SRC					19
-#define SDCC1_ICE_CORE_CLK_SRC					20
-#define SDCC2_APPS_CLK_SRC					21
-#define SDCC3_APPS_CLK_SRC					22
-#define SDCC4_APPS_CLK_SRC					23
-#define BLSP1_QUP1_SPI_APPS_CLK_SRC				24
-#define BLSP1_QUP1_I2C_APPS_CLK_SRC				25
-#define BLSP1_UART1_APPS_CLK_SRC				26
-#define BLSP1_QUP2_SPI_APPS_CLK_SRC				27
-#define BLSP1_QUP2_I2C_APPS_CLK_SRC				28
-#define BLSP1_UART2_APPS_CLK_SRC				29
-#define BLSP1_QUP3_SPI_APPS_CLK_SRC				30
-#define BLSP1_QUP3_I2C_APPS_CLK_SRC				31
-#define BLSP1_UART3_APPS_CLK_SRC				32
-#define BLSP1_QUP4_SPI_APPS_CLK_SRC				33
-#define BLSP1_QUP4_I2C_APPS_CLK_SRC				34
-#define BLSP1_UART4_APPS_CLK_SRC				35
-#define BLSP1_QUP5_SPI_APPS_CLK_SRC				36
-#define BLSP1_QUP5_I2C_APPS_CLK_SRC				37
-#define BLSP1_UART5_APPS_CLK_SRC				38
-#define BLSP1_QUP6_SPI_APPS_CLK_SRC				39
-#define BLSP1_QUP6_I2C_APPS_CLK_SRC				40
-#define BLSP1_UART6_APPS_CLK_SRC				41
-#define BLSP2_QUP1_SPI_APPS_CLK_SRC				42
-#define BLSP2_QUP1_I2C_APPS_CLK_SRC				43
-#define BLSP2_UART1_APPS_CLK_SRC				44
-#define BLSP2_QUP2_SPI_APPS_CLK_SRC				45
-#define BLSP2_QUP2_I2C_APPS_CLK_SRC				46
-#define BLSP2_UART2_APPS_CLK_SRC				47
-#define BLSP2_QUP3_SPI_APPS_CLK_SRC				48
-#define BLSP2_QUP3_I2C_APPS_CLK_SRC				49
-#define BLSP2_UART3_APPS_CLK_SRC				50
-#define BLSP2_QUP4_SPI_APPS_CLK_SRC				51
-#define BLSP2_QUP4_I2C_APPS_CLK_SRC				52
-#define BLSP2_UART4_APPS_CLK_SRC				53
-#define BLSP2_QUP5_SPI_APPS_CLK_SRC				54
-#define BLSP2_QUP5_I2C_APPS_CLK_SRC				55
-#define BLSP2_UART5_APPS_CLK_SRC				56
-#define BLSP2_QUP6_SPI_APPS_CLK_SRC				57
-#define BLSP2_QUP6_I2C_APPS_CLK_SRC				58
-#define BLSP2_UART6_APPS_CLK_SRC				59
-#define PDM2_CLK_SRC						60
-#define TSIF_REF_CLK_SRC					61
-#define CE1_CLK_SRC						62
-#define GCC_SLEEP_CLK_SRC					63
-#define BIMC_CLK_SRC						64
-#define HMSS_AHB_CLK_SRC					65
-#define BIMC_HMSS_AXI_CLK_SRC					66
-#define HMSS_RBCPR_CLK_SRC					67
-#define HMSS_GPLL0_CLK_SRC					68
-#define GP1_CLK_SRC						69
-#define GP2_CLK_SRC						70
-#define GP3_CLK_SRC						71
-#define PCIE_AUX_CLK_SRC					72
-#define UFS_AXI_CLK_SRC						73
-#define UFS_ICE_CORE_CLK_SRC					74
-#define QSPI_SER_CLK_SRC					75
-#define GCC_SYS_NOC_AXI_CLK					76
-#define GCC_SYS_NOC_HMSS_AHB_CLK				77
-#define GCC_SNOC_CNOC_AHB_CLK					78
-#define GCC_SNOC_PNOC_AHB_CLK					79
-#define GCC_SYS_NOC_AT_CLK					80
-#define GCC_SYS_NOC_USB3_AXI_CLK				81
-#define GCC_SYS_NOC_UFS_AXI_CLK					82
-#define GCC_CFG_NOC_AHB_CLK					83
-#define GCC_PERIPH_NOC_AHB_CLK					84
-#define GCC_PERIPH_NOC_USB20_AHB_CLK				85
-#define GCC_TIC_CLK						86
-#define GCC_IMEM_AXI_CLK					87
-#define GCC_MMSS_SYS_NOC_AXI_CLK				88
-#define GCC_MMSS_NOC_CFG_AHB_CLK				89
-#define GCC_MMSS_BIMC_GFX_CLK					90
-#define GCC_USB30_MASTER_CLK					91
-#define GCC_USB30_SLEEP_CLK					92
-#define GCC_USB30_MOCK_UTMI_CLK					93
-#define GCC_USB3_PHY_AUX_CLK					94
-#define GCC_USB3_PHY_PIPE_CLK					95
-#define GCC_USB20_MASTER_CLK					96
-#define GCC_USB20_SLEEP_CLK					97
-#define GCC_USB20_MOCK_UTMI_CLK					98
-#define GCC_USB_PHY_CFG_AHB2PHY_CLK				99
-#define GCC_SDCC1_APPS_CLK					100
-#define GCC_SDCC1_AHB_CLK					101
-#define GCC_SDCC1_ICE_CORE_CLK					102
-#define GCC_SDCC2_APPS_CLK					103
-#define GCC_SDCC2_AHB_CLK					104
-#define GCC_SDCC3_APPS_CLK					105
-#define GCC_SDCC3_AHB_CLK					106
-#define GCC_SDCC4_APPS_CLK					107
-#define GCC_SDCC4_AHB_CLK					108
-#define GCC_BLSP1_AHB_CLK					109
-#define GCC_BLSP1_SLEEP_CLK					110
-#define GCC_BLSP1_QUP1_SPI_APPS_CLK				111
-#define GCC_BLSP1_QUP1_I2C_APPS_CLK				112
-#define GCC_BLSP1_UART1_APPS_CLK				113
-#define GCC_BLSP1_QUP2_SPI_APPS_CLK				114
-#define GCC_BLSP1_QUP2_I2C_APPS_CLK				115
-#define GCC_BLSP1_UART2_APPS_CLK				116
-#define GCC_BLSP1_QUP3_SPI_APPS_CLK				117
-#define GCC_BLSP1_QUP3_I2C_APPS_CLK				118
-#define GCC_BLSP1_UART3_APPS_CLK				119
-#define GCC_BLSP1_QUP4_SPI_APPS_CLK				120
-#define GCC_BLSP1_QUP4_I2C_APPS_CLK				121
-#define GCC_BLSP1_UART4_APPS_CLK				122
-#define GCC_BLSP1_QUP5_SPI_APPS_CLK				123
-#define GCC_BLSP1_QUP5_I2C_APPS_CLK				124
-#define GCC_BLSP1_UART5_APPS_CLK				125
-#define GCC_BLSP1_QUP6_SPI_APPS_CLK				126
-#define GCC_BLSP1_QUP6_I2C_APPS_CLK				127
-#define GCC_BLSP1_UART6_APPS_CLK				128
-#define GCC_BLSP2_AHB_CLK					129
-#define GCC_BLSP2_SLEEP_CLK					130
-#define GCC_BLSP2_QUP1_SPI_APPS_CLK				131
-#define GCC_BLSP2_QUP1_I2C_APPS_CLK				132
-#define GCC_BLSP2_UART1_APPS_CLK				133
-#define GCC_BLSP2_QUP2_SPI_APPS_CLK				134
-#define GCC_BLSP2_QUP2_I2C_APPS_CLK				135
-#define GCC_BLSP2_UART2_APPS_CLK				136
-#define GCC_BLSP2_QUP3_SPI_APPS_CLK				137
-#define GCC_BLSP2_QUP3_I2C_APPS_CLK				138
-#define GCC_BLSP2_UART3_APPS_CLK				139
-#define GCC_BLSP2_QUP4_SPI_APPS_CLK				140
-#define GCC_BLSP2_QUP4_I2C_APPS_CLK				141
-#define GCC_BLSP2_UART4_APPS_CLK				142
-#define GCC_BLSP2_QUP5_SPI_APPS_CLK				143
-#define GCC_BLSP2_QUP5_I2C_APPS_CLK				144
-#define GCC_BLSP2_UART5_APPS_CLK				145
-#define GCC_BLSP2_QUP6_SPI_APPS_CLK				146
-#define GCC_BLSP2_QUP6_I2C_APPS_CLK				147
-#define GCC_BLSP2_UART6_APPS_CLK				148
-#define GCC_PDM_AHB_CLK						149
-#define GCC_PDM_XO4_CLK						150
-#define GCC_PDM2_CLK						151
-#define GCC_PRNG_AHB_CLK					152
-#define GCC_TSIF_AHB_CLK					153
-#define GCC_TSIF_REF_CLK					154
-#define GCC_TSIF_INACTIVITY_TIMERS_CLK				155
-#define GCC_TCSR_AHB_CLK					156
-#define GCC_BOOT_ROM_AHB_CLK					157
-#define GCC_MSG_RAM_AHB_CLK					158
-#define GCC_TLMM_AHB_CLK					159
-#define GCC_TLMM_CLK						160
-#define GCC_MPM_AHB_CLK						161
-#define GCC_SPMI_SER_CLK					162
-#define GCC_SPMI_CNOC_AHB_CLK					163
-#define GCC_CE1_CLK						164
-#define GCC_CE1_AXI_CLK						165
-#define GCC_CE1_AHB_CLK						166
-#define GCC_BIMC_HMSS_AXI_CLK					167
-#define GCC_BIMC_GFX_CLK					168
-#define GCC_HMSS_AHB_CLK					169
-#define GCC_HMSS_SLV_AXI_CLK					170
-#define GCC_HMSS_MSTR_AXI_CLK					171
-#define GCC_HMSS_RBCPR_CLK					172
-#define GCC_GP1_CLK						173
-#define GCC_GP2_CLK						174
-#define GCC_GP3_CLK						175
-#define GCC_PCIE_0_SLV_AXI_CLK					176
-#define GCC_PCIE_0_MSTR_AXI_CLK					177
-#define GCC_PCIE_0_CFG_AHB_CLK					178
-#define GCC_PCIE_0_AUX_CLK					179
-#define GCC_PCIE_0_PIPE_CLK					180
-#define GCC_PCIE_1_SLV_AXI_CLK					181
-#define GCC_PCIE_1_MSTR_AXI_CLK					182
-#define GCC_PCIE_1_CFG_AHB_CLK					183
-#define GCC_PCIE_1_AUX_CLK					184
-#define GCC_PCIE_1_PIPE_CLK					185
-#define GCC_PCIE_2_SLV_AXI_CLK					186
-#define GCC_PCIE_2_MSTR_AXI_CLK					187
-#define GCC_PCIE_2_CFG_AHB_CLK					188
-#define GCC_PCIE_2_AUX_CLK					189
-#define GCC_PCIE_2_PIPE_CLK					190
-#define GCC_PCIE_PHY_CFG_AHB_CLK				191
-#define GCC_PCIE_PHY_AUX_CLK					192
-#define GCC_UFS_AXI_CLK						193
-#define GCC_UFS_AHB_CLK						194
-#define GCC_UFS_TX_CFG_CLK					195
-#define GCC_UFS_RX_CFG_CLK					196
-#define GCC_UFS_TX_SYMBOL_0_CLK					197
-#define GCC_UFS_RX_SYMBOL_0_CLK					198
-#define GCC_UFS_RX_SYMBOL_1_CLK					199
-#define GCC_UFS_UNIPRO_CORE_CLK					200
-#define GCC_UFS_ICE_CORE_CLK					201
-#define GCC_UFS_SYS_CLK_CORE_CLK				202
-#define GCC_UFS_TX_SYMBOL_CLK_CORE_CLK				203
-#define GCC_AGGRE0_SNOC_AXI_CLK					204
-#define GCC_AGGRE0_CNOC_AHB_CLK					205
-#define GCC_SMMU_AGGRE0_AXI_CLK					206
-#define GCC_SMMU_AGGRE0_AHB_CLK					207
-#define GCC_AGGRE1_PNOC_AHB_CLK					208
-#define GCC_AGGRE2_UFS_AXI_CLK					209
-#define GCC_AGGRE2_USB3_AXI_CLK					210
-#define GCC_QSPI_AHB_CLK					211
-#define GCC_QSPI_SER_CLK					212
-#define GCC_USB3_CLKREF_CLK					213
-#define GCC_HDMI_CLKREF_CLK					214
-#define GCC_UFS_CLKREF_CLK					215
-#define GCC_PCIE_CLKREF_CLK					216
-#define GCC_RX2_USB2_CLKREF_CLK					217
-#define GCC_RX1_USB2_CLKREF_CLK					218
-#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK			219
-#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK			220
-#define GCC_EDP_CLKREF_CLK					221
-#define GCC_MSS_CFG_AHB_CLK					222
-#define GCC_MSS_Q6_BIMC_AXI_CLK					223
-#define GCC_MSS_SNOC_AXI_CLK					224
-#define GCC_MSS_MNOC_BIMC_AXI_CLK				225
-#define GCC_DCC_AHB_CLK						226
-#define GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK				227
-#define GCC_MMSS_GPLL0_DIV_CLK					228
-#define GCC_MSS_GPLL0_DIV_CLK					229
-
-#define GCC_SYSTEM_NOC_BCR					0
-#define GCC_CONFIG_NOC_BCR					1
-#define GCC_PERIPH_NOC_BCR					2
-#define GCC_IMEM_BCR						3
-#define GCC_MMSS_BCR						4
-#define GCC_PIMEM_BCR						5
-#define GCC_QDSS_BCR						6
-#define GCC_USB_30_BCR						7
-#define GCC_USB_20_BCR						8
-#define GCC_QUSB2PHY_PRIM_BCR					9
-#define GCC_QUSB2PHY_SEC_BCR					10
-#define GCC_USB_PHY_CFG_AHB2PHY_BCR				11
-#define GCC_SDCC1_BCR						12
-#define GCC_SDCC2_BCR						13
-#define GCC_SDCC3_BCR						14
-#define GCC_SDCC4_BCR						15
-#define GCC_BLSP1_BCR						16
-#define GCC_BLSP1_QUP1_BCR					17
-#define GCC_BLSP1_UART1_BCR					18
-#define GCC_BLSP1_QUP2_BCR					19
-#define GCC_BLSP1_UART2_BCR					20
-#define GCC_BLSP1_QUP3_BCR					21
-#define GCC_BLSP1_UART3_BCR					22
-#define GCC_BLSP1_QUP4_BCR					23
-#define GCC_BLSP1_UART4_BCR					24
-#define GCC_BLSP1_QUP5_BCR					25
-#define GCC_BLSP1_UART5_BCR					26
-#define GCC_BLSP1_QUP6_BCR					27
-#define GCC_BLSP1_UART6_BCR					28
-#define GCC_BLSP2_BCR						29
-#define GCC_BLSP2_QUP1_BCR					30
-#define GCC_BLSP2_UART1_BCR					31
-#define GCC_BLSP2_QUP2_BCR					32
-#define GCC_BLSP2_UART2_BCR					33
-#define GCC_BLSP2_QUP3_BCR					34
-#define GCC_BLSP2_UART3_BCR					35
-#define GCC_BLSP2_QUP4_BCR					36
-#define GCC_BLSP2_UART4_BCR					37
-#define GCC_BLSP2_QUP5_BCR					38
-#define GCC_BLSP2_UART5_BCR					39
-#define GCC_BLSP2_QUP6_BCR					40
-#define GCC_BLSP2_UART6_BCR					41
-#define GCC_PDM_BCR						42
-#define GCC_PRNG_BCR						43
-#define GCC_TSIF_BCR						44
-#define GCC_TCSR_BCR						45
-#define GCC_BOOT_ROM_BCR					46
-#define GCC_MSG_RAM_BCR						47
-#define GCC_TLMM_BCR						48
-#define GCC_MPM_BCR						49
-#define GCC_SEC_CTRL_BCR					50
-#define GCC_SPMI_BCR						51
-#define GCC_SPDM_BCR						52
-#define GCC_CE1_BCR						53
-#define GCC_BIMC_BCR						54
-#define GCC_SNOC_BUS_TIMEOUT0_BCR				55
-#define GCC_SNOC_BUS_TIMEOUT2_BCR				56
-#define GCC_SNOC_BUS_TIMEOUT1_BCR				57
-#define GCC_SNOC_BUS_TIMEOUT3_BCR				58
-#define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR				59
-#define GCC_PNOC_BUS_TIMEOUT0_BCR				60
-#define GCC_PNOC_BUS_TIMEOUT1_BCR				61
-#define GCC_PNOC_BUS_TIMEOUT2_BCR				62
-#define GCC_PNOC_BUS_TIMEOUT3_BCR				63
-#define GCC_PNOC_BUS_TIMEOUT4_BCR				64
-#define GCC_CNOC_BUS_TIMEOUT0_BCR				65
-#define GCC_CNOC_BUS_TIMEOUT1_BCR				66
-#define GCC_CNOC_BUS_TIMEOUT2_BCR				67
-#define GCC_CNOC_BUS_TIMEOUT3_BCR				68
-#define GCC_CNOC_BUS_TIMEOUT4_BCR				69
-#define GCC_CNOC_BUS_TIMEOUT5_BCR				70
-#define GCC_CNOC_BUS_TIMEOUT6_BCR				71
-#define GCC_CNOC_BUS_TIMEOUT7_BCR				72
-#define GCC_CNOC_BUS_TIMEOUT8_BCR				73
-#define GCC_CNOC_BUS_TIMEOUT9_BCR				74
-#define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR				75
-#define GCC_APB2JTAG_BCR					76
-#define GCC_RBCPR_CX_BCR					77
-#define GCC_RBCPR_MX_BCR					78
-#define GCC_PCIE_0_BCR						79
-#define GCC_PCIE_0_PHY_BCR					80
-#define GCC_PCIE_1_BCR						81
-#define GCC_PCIE_1_PHY_BCR					82
-#define GCC_PCIE_2_BCR						83
-#define GCC_PCIE_2_PHY_BCR					84
-#define GCC_PCIE_PHY_BCR					85
-#define GCC_DCD_BCR						86
-#define GCC_OBT_ODT_BCR						87
-#define GCC_UFS_BCR						88
-#define GCC_SSC_BCR						89
-#define GCC_VS_BCR						90
-#define GCC_AGGRE0_NOC_BCR					91
-#define GCC_AGGRE1_NOC_BCR					92
-#define GCC_AGGRE2_NOC_BCR					93
-#define GCC_DCC_BCR						94
-#define GCC_IPA_BCR						95
-#define GCC_QSPI_BCR						96
-#define GCC_SKL_BCR						97
-#define GCC_MSMPU_BCR						98
-#define GCC_MSS_Q6_BCR						99
-#define GCC_QREFS_VBG_CAL_BCR					100
-#define GCC_PCIE_PHY_COM_BCR					101
-#define GCC_PCIE_PHY_COM_NOCSR_BCR				102
-#define GCC_USB3_PHY_BCR					103
-#define GCC_USB3PHY_PHY_BCR					104
-#define GCC_MSS_RESTART						105
-
-/* Indexes for GDSCs */
-#define AGGRE0_NOC_GDSC			0
-#define HLOS1_VOTE_AGGRE0_NOC_GDSC	1
-#define HLOS1_VOTE_LPASS_ADSP_GDSC	2
-#define HLOS1_VOTE_LPASS_CORE_GDSC	3
-#define USB30_GDSC			4
-#define PCIE0_GDSC			5
-#define PCIE1_GDSC			6
-#define PCIE2_GDSC			7
-#define UFS_GDSC			8
-
-#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h
deleted file mode 100644
index bc30515..0000000
--- a/include/dt-bindings/clock/qcom,gcc-qcs404.h
+++ /dev/null
@@ -1,180 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2018, The Linux Foundation. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H
-#define _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H
-
-#define GCC_APSS_AHB_CLK_SRC				0
-#define GCC_BLSP1_QUP0_I2C_APPS_CLK_SRC			1
-#define GCC_BLSP1_QUP0_SPI_APPS_CLK_SRC			2
-#define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC			3
-#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC			4
-#define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC			5
-#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC			6
-#define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC			7
-#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC			8
-#define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC			9
-#define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC			10
-#define GCC_BLSP1_UART0_APPS_CLK_SRC			11
-#define GCC_BLSP1_UART1_APPS_CLK_SRC			12
-#define GCC_BLSP1_UART2_APPS_CLK_SRC			13
-#define GCC_BLSP1_UART3_APPS_CLK_SRC			14
-#define GCC_BLSP2_QUP0_I2C_APPS_CLK_SRC			15
-#define GCC_BLSP2_QUP0_SPI_APPS_CLK_SRC			16
-#define GCC_BLSP2_UART0_APPS_CLK_SRC			17
-#define GCC_BYTE0_CLK_SRC				18
-#define GCC_EMAC_CLK_SRC				19
-#define GCC_EMAC_PTP_CLK_SRC				20
-#define GCC_ESC0_CLK_SRC				21
-#define GCC_APSS_AHB_CLK				22
-#define GCC_APSS_AXI_CLK				23
-#define GCC_BIMC_APSS_AXI_CLK				24
-#define GCC_BIMC_GFX_CLK				25
-#define GCC_BIMC_MDSS_CLK				26
-#define GCC_BLSP1_AHB_CLK				27
-#define GCC_BLSP1_QUP0_I2C_APPS_CLK			28
-#define GCC_BLSP1_QUP0_SPI_APPS_CLK			29
-#define GCC_BLSP1_QUP1_I2C_APPS_CLK			30
-#define GCC_BLSP1_QUP1_SPI_APPS_CLK			31
-#define GCC_BLSP1_QUP2_I2C_APPS_CLK			32
-#define GCC_BLSP1_QUP2_SPI_APPS_CLK			33
-#define GCC_BLSP1_QUP3_I2C_APPS_CLK			34
-#define GCC_BLSP1_QUP3_SPI_APPS_CLK			35
-#define GCC_BLSP1_QUP4_I2C_APPS_CLK			36
-#define GCC_BLSP1_QUP4_SPI_APPS_CLK			37
-#define GCC_BLSP1_UART0_APPS_CLK			38
-#define GCC_BLSP1_UART1_APPS_CLK			39
-#define GCC_BLSP1_UART2_APPS_CLK			40
-#define GCC_BLSP1_UART3_APPS_CLK			41
-#define GCC_BLSP2_AHB_CLK				42
-#define GCC_BLSP2_QUP0_I2C_APPS_CLK			43
-#define GCC_BLSP2_QUP0_SPI_APPS_CLK			44
-#define GCC_BLSP2_UART0_APPS_CLK			45
-#define GCC_BOOT_ROM_AHB_CLK				46
-#define GCC_DCC_CLK					47
-#define GCC_GENI_IR_H_CLK				48
-#define GCC_ETH_AXI_CLK					49
-#define GCC_ETH_PTP_CLK					50
-#define GCC_ETH_RGMII_CLK				51
-#define GCC_ETH_SLAVE_AHB_CLK				52
-#define GCC_GENI_IR_S_CLK				53
-#define GCC_GP1_CLK					54
-#define GCC_GP2_CLK					55
-#define GCC_GP3_CLK					56
-#define GCC_MDSS_AHB_CLK				57
-#define GCC_MDSS_AXI_CLK				58
-#define GCC_MDSS_BYTE0_CLK				59
-#define GCC_MDSS_ESC0_CLK				60
-#define GCC_MDSS_HDMI_APP_CLK				61
-#define GCC_MDSS_HDMI_PCLK_CLK				62
-#define GCC_MDSS_MDP_CLK				63
-#define GCC_MDSS_PCLK0_CLK				64
-#define GCC_MDSS_VSYNC_CLK				65
-#define GCC_OXILI_AHB_CLK				66
-#define GCC_OXILI_GFX3D_CLK				67
-#define GCC_PCIE_0_AUX_CLK				68
-#define GCC_PCIE_0_CFG_AHB_CLK				69
-#define GCC_PCIE_0_MSTR_AXI_CLK				70
-#define GCC_PCIE_0_PIPE_CLK				71
-#define GCC_PCIE_0_SLV_AXI_CLK				72
-#define GCC_PCNOC_USB2_CLK				73
-#define GCC_PCNOC_USB3_CLK				74
-#define GCC_PDM2_CLK					75
-#define GCC_PDM_AHB_CLK					76
-#define GCC_VSYNC_CLK_SRC				77
-#define GCC_PRNG_AHB_CLK				78
-#define GCC_PWM0_XO512_CLK				79
-#define GCC_PWM1_XO512_CLK				80
-#define GCC_PWM2_XO512_CLK				81
-#define GCC_SDCC1_AHB_CLK				82
-#define GCC_SDCC1_APPS_CLK				83
-#define GCC_SDCC1_ICE_CORE_CLK				84
-#define GCC_SDCC2_AHB_CLK				85
-#define GCC_SDCC2_APPS_CLK				86
-#define GCC_SYS_NOC_USB3_CLK				87
-#define GCC_USB20_MOCK_UTMI_CLK				88
-#define GCC_USB2A_PHY_SLEEP_CLK				89
-#define GCC_USB30_MASTER_CLK				90
-#define GCC_USB30_MOCK_UTMI_CLK				91
-#define GCC_USB30_SLEEP_CLK				92
-#define GCC_USB3_PHY_AUX_CLK				93
-#define GCC_USB3_PHY_PIPE_CLK				94
-#define GCC_USB_HS_PHY_CFG_AHB_CLK			95
-#define GCC_USB_HS_SYSTEM_CLK				96
-#define GCC_GFX3D_CLK_SRC				97
-#define GCC_GP1_CLK_SRC					98
-#define GCC_GP2_CLK_SRC					99
-#define GCC_GP3_CLK_SRC					100
-#define GCC_GPLL0_OUT_MAIN				101
-#define GCC_GPLL1_OUT_MAIN				102
-#define GCC_GPLL3_OUT_MAIN				103
-#define GCC_GPLL4_OUT_MAIN				104
-#define GCC_HDMI_APP_CLK_SRC				105
-#define GCC_HDMI_PCLK_CLK_SRC				106
-#define GCC_MDP_CLK_SRC					107
-#define GCC_PCIE_0_AUX_CLK_SRC				108
-#define GCC_PCIE_0_PIPE_CLK_SRC				109
-#define GCC_PCLK0_CLK_SRC				110
-#define GCC_PDM2_CLK_SRC				111
-#define GCC_SDCC1_APPS_CLK_SRC				112
-#define GCC_SDCC1_ICE_CORE_CLK_SRC			113
-#define GCC_SDCC2_APPS_CLK_SRC				114
-#define GCC_USB20_MOCK_UTMI_CLK_SRC			115
-#define GCC_USB30_MASTER_CLK_SRC			116
-#define GCC_USB30_MOCK_UTMI_CLK_SRC			117
-#define GCC_USB3_PHY_AUX_CLK_SRC			118
-#define GCC_USB_HS_SYSTEM_CLK_SRC			119
-#define GCC_GPLL0_AO_CLK_SRC				120
-#define GCC_USB_HS_INACTIVITY_TIMERS_CLK		122
-#define GCC_GPLL0_AO_OUT_MAIN				123
-#define GCC_GPLL0_SLEEP_CLK_SRC				124
-#define GCC_GPLL6					125
-#define GCC_GPLL6_OUT_AUX				126
-#define GCC_MDSS_MDP_VOTE_CLK				127
-#define GCC_MDSS_ROTATOR_VOTE_CLK			128
-#define GCC_BIMC_GPU_CLK				129
-#define GCC_GTCU_AHB_CLK				130
-#define GCC_GFX_TCU_CLK					131
-#define GCC_GFX_TBU_CLK					132
-#define GCC_SMMU_CFG_CLK				133
-#define GCC_APSS_TCU_CLK				134
-#define GCC_CRYPTO_AHB_CLK				135
-#define GCC_CRYPTO_AXI_CLK				136
-#define GCC_CRYPTO_CLK					137
-#define GCC_MDP_TBU_CLK					138
-#define GCC_QDSS_DAP_CLK				139
-#define GCC_DCC_XO_CLK					140
-#define GCC_WCSS_Q6_AHB_CLK				141
-#define GCC_WCSS_Q6_AXIM_CLK				142
-#define GCC_CDSP_CFG_AHB_CLK				143
-#define GCC_BIMC_CDSP_CLK				144
-#define GCC_CDSP_TBU_CLK				145
-#define GCC_CDSP_BIMC_CLK_SRC				146
-
-#define GCC_GENI_IR_BCR					0
-#define GCC_USB_HS_BCR					1
-#define GCC_USB2_HS_PHY_ONLY_BCR			2
-#define GCC_QUSB2_PHY_BCR				3
-#define GCC_USB_HS_PHY_CFG_AHB_BCR			4
-#define GCC_USB2A_PHY_BCR				5
-#define GCC_USB3_PHY_BCR				6
-#define GCC_USB_30_BCR					7
-#define GCC_USB3PHY_PHY_BCR				8
-#define GCC_PCIE_0_BCR					9
-#define GCC_PCIE_0_PHY_BCR				10
-#define GCC_PCIE_0_LINK_DOWN_BCR			11
-#define GCC_PCIEPHY_0_PHY_BCR				12
-#define GCC_EMAC_BCR					13
-#define GCC_CDSP_RESTART				14
-#define GCC_PCIE_0_AXI_MASTER_STICKY_ARES		15
-#define GCC_PCIE_0_AHB_ARES				16
-#define GCC_PCIE_0_AXI_SLAVE_ARES			17
-#define GCC_PCIE_0_AXI_MASTER_ARES			18
-#define GCC_PCIE_0_CORE_STICKY_ARES			19
-#define GCC_PCIE_0_SLEEP_ARES				20
-#define GCC_PCIE_0_PIPE_ARES				21
-#define GCC_WDSP_RESTART				22
-
-#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-sdm845.h b/include/dt-bindings/clock/qcom,gcc-sdm845.h
deleted file mode 100644
index 968fa65..0000000
--- a/include/dt-bindings/clock/qcom,gcc-sdm845.h
+++ /dev/null
@@ -1,246 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2018, The Linux Foundation. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_CLK_SDM_GCC_SDM845_H
-#define _DT_BINDINGS_CLK_SDM_GCC_SDM845_H
-
-/* GCC clock registers */
-#define GCC_AGGRE_NOC_PCIE_TBU_CLK				0
-#define GCC_AGGRE_UFS_CARD_AXI_CLK				1
-#define GCC_AGGRE_UFS_PHY_AXI_CLK				2
-#define GCC_AGGRE_USB3_PRIM_AXI_CLK				3
-#define GCC_AGGRE_USB3_SEC_AXI_CLK				4
-#define GCC_BOOT_ROM_AHB_CLK					5
-#define GCC_CAMERA_AHB_CLK					6
-#define GCC_CAMERA_AXI_CLK					7
-#define GCC_CAMERA_XO_CLK					8
-#define GCC_CE1_AHB_CLK						9
-#define GCC_CE1_AXI_CLK						10
-#define GCC_CE1_CLK						11
-#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK				12
-#define GCC_CFG_NOC_USB3_SEC_AXI_CLK				13
-#define GCC_CPUSS_AHB_CLK					14
-#define GCC_CPUSS_AHB_CLK_SRC					15
-#define GCC_CPUSS_RBCPR_CLK					16
-#define GCC_CPUSS_RBCPR_CLK_SRC					17
-#define GCC_DDRSS_GPU_AXI_CLK					18
-#define GCC_DISP_AHB_CLK					19
-#define GCC_DISP_AXI_CLK					20
-#define GCC_DISP_GPLL0_CLK_SRC					21
-#define GCC_DISP_GPLL0_DIV_CLK_SRC				22
-#define GCC_DISP_XO_CLK						23
-#define GCC_GP1_CLK						24
-#define GCC_GP1_CLK_SRC						25
-#define GCC_GP2_CLK						26
-#define GCC_GP2_CLK_SRC						27
-#define GCC_GP3_CLK						28
-#define GCC_GP3_CLK_SRC						29
-#define GCC_GPU_CFG_AHB_CLK					30
-#define GCC_GPU_GPLL0_CLK_SRC					31
-#define GCC_GPU_GPLL0_DIV_CLK_SRC				32
-#define GCC_GPU_MEMNOC_GFX_CLK					33
-#define GCC_GPU_SNOC_DVM_GFX_CLK				34
-#define GCC_MSS_AXIS2_CLK					35
-#define GCC_MSS_CFG_AHB_CLK					36
-#define GCC_MSS_GPLL0_DIV_CLK_SRC				37
-#define GCC_MSS_MFAB_AXIS_CLK					38
-#define GCC_MSS_Q6_MEMNOC_AXI_CLK				39
-#define GCC_MSS_SNOC_AXI_CLK					40
-#define GCC_PCIE_0_AUX_CLK					41
-#define GCC_PCIE_0_AUX_CLK_SRC					42
-#define GCC_PCIE_0_CFG_AHB_CLK					43
-#define GCC_PCIE_0_CLKREF_CLK					44
-#define GCC_PCIE_0_MSTR_AXI_CLK					45
-#define GCC_PCIE_0_PIPE_CLK					46
-#define GCC_PCIE_0_SLV_AXI_CLK					47
-#define GCC_PCIE_0_SLV_Q2A_AXI_CLK				48
-#define GCC_PCIE_1_AUX_CLK					49
-#define GCC_PCIE_1_AUX_CLK_SRC					50
-#define GCC_PCIE_1_CFG_AHB_CLK					51
-#define GCC_PCIE_1_CLKREF_CLK					52
-#define GCC_PCIE_1_MSTR_AXI_CLK					53
-#define GCC_PCIE_1_PIPE_CLK					54
-#define GCC_PCIE_1_SLV_AXI_CLK					55
-#define GCC_PCIE_1_SLV_Q2A_AXI_CLK				56
-#define GCC_PCIE_PHY_AUX_CLK					57
-#define GCC_PCIE_PHY_REFGEN_CLK					58
-#define GCC_PCIE_PHY_REFGEN_CLK_SRC				59
-#define GCC_PDM2_CLK						60
-#define GCC_PDM2_CLK_SRC					61
-#define GCC_PDM_AHB_CLK						62
-#define GCC_PDM_XO4_CLK						63
-#define GCC_PRNG_AHB_CLK					64
-#define GCC_QMIP_CAMERA_AHB_CLK					65
-#define GCC_QMIP_DISP_AHB_CLK					66
-#define GCC_QMIP_VIDEO_AHB_CLK					67
-#define GCC_QUPV3_WRAP0_S0_CLK					68
-#define GCC_QUPV3_WRAP0_S0_CLK_SRC				69
-#define GCC_QUPV3_WRAP0_S1_CLK					70
-#define GCC_QUPV3_WRAP0_S1_CLK_SRC				71
-#define GCC_QUPV3_WRAP0_S2_CLK					72
-#define GCC_QUPV3_WRAP0_S2_CLK_SRC				73
-#define GCC_QUPV3_WRAP0_S3_CLK					74
-#define GCC_QUPV3_WRAP0_S3_CLK_SRC				75
-#define GCC_QUPV3_WRAP0_S4_CLK					76
-#define GCC_QUPV3_WRAP0_S4_CLK_SRC				77
-#define GCC_QUPV3_WRAP0_S5_CLK					78
-#define GCC_QUPV3_WRAP0_S5_CLK_SRC				79
-#define GCC_QUPV3_WRAP0_S6_CLK					80
-#define GCC_QUPV3_WRAP0_S6_CLK_SRC				81
-#define GCC_QUPV3_WRAP0_S7_CLK					82
-#define GCC_QUPV3_WRAP0_S7_CLK_SRC				83
-#define GCC_QUPV3_WRAP1_S0_CLK					84
-#define GCC_QUPV3_WRAP1_S0_CLK_SRC				85
-#define GCC_QUPV3_WRAP1_S1_CLK					86
-#define GCC_QUPV3_WRAP1_S1_CLK_SRC				87
-#define GCC_QUPV3_WRAP1_S2_CLK					88
-#define GCC_QUPV3_WRAP1_S2_CLK_SRC				89
-#define GCC_QUPV3_WRAP1_S3_CLK					90
-#define GCC_QUPV3_WRAP1_S3_CLK_SRC				91
-#define GCC_QUPV3_WRAP1_S4_CLK					92
-#define GCC_QUPV3_WRAP1_S4_CLK_SRC				93
-#define GCC_QUPV3_WRAP1_S5_CLK					94
-#define GCC_QUPV3_WRAP1_S5_CLK_SRC				95
-#define GCC_QUPV3_WRAP1_S6_CLK					96
-#define GCC_QUPV3_WRAP1_S6_CLK_SRC				97
-#define GCC_QUPV3_WRAP1_S7_CLK					98
-#define GCC_QUPV3_WRAP1_S7_CLK_SRC				99
-#define GCC_QUPV3_WRAP_0_M_AHB_CLK				100
-#define GCC_QUPV3_WRAP_0_S_AHB_CLK				101
-#define GCC_QUPV3_WRAP_1_M_AHB_CLK				102
-#define GCC_QUPV3_WRAP_1_S_AHB_CLK				103
-#define GCC_SDCC2_AHB_CLK					104
-#define GCC_SDCC2_APPS_CLK					105
-#define GCC_SDCC2_APPS_CLK_SRC					106
-#define GCC_SDCC4_AHB_CLK					107
-#define GCC_SDCC4_APPS_CLK					108
-#define GCC_SDCC4_APPS_CLK_SRC					109
-#define GCC_SYS_NOC_CPUSS_AHB_CLK				110
-#define GCC_TSIF_AHB_CLK					111
-#define GCC_TSIF_INACTIVITY_TIMERS_CLK				112
-#define GCC_TSIF_REF_CLK					113
-#define GCC_TSIF_REF_CLK_SRC					114
-#define GCC_UFS_CARD_AHB_CLK					115
-#define GCC_UFS_CARD_AXI_CLK					116
-#define GCC_UFS_CARD_AXI_CLK_SRC				117
-#define GCC_UFS_CARD_CLKREF_CLK					118
-#define GCC_UFS_CARD_ICE_CORE_CLK				119
-#define GCC_UFS_CARD_ICE_CORE_CLK_SRC				120
-#define GCC_UFS_CARD_PHY_AUX_CLK				121
-#define GCC_UFS_CARD_PHY_AUX_CLK_SRC				122
-#define GCC_UFS_CARD_RX_SYMBOL_0_CLK				123
-#define GCC_UFS_CARD_RX_SYMBOL_1_CLK				124
-#define GCC_UFS_CARD_TX_SYMBOL_0_CLK				125
-#define GCC_UFS_CARD_UNIPRO_CORE_CLK				126
-#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC			127
-#define GCC_UFS_MEM_CLKREF_CLK					128
-#define GCC_UFS_PHY_AHB_CLK					129
-#define GCC_UFS_PHY_AXI_CLK					130
-#define GCC_UFS_PHY_AXI_CLK_SRC					131
-#define GCC_UFS_PHY_ICE_CORE_CLK				132
-#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				133
-#define GCC_UFS_PHY_PHY_AUX_CLK					134
-#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				135
-#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				136
-#define GCC_UFS_PHY_RX_SYMBOL_1_CLK				137
-#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				138
-#define GCC_UFS_PHY_UNIPRO_CORE_CLK				139
-#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				140
-#define GCC_USB30_PRIM_MASTER_CLK				141
-#define GCC_USB30_PRIM_MASTER_CLK_SRC				142
-#define GCC_USB30_PRIM_MOCK_UTMI_CLK				143
-#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			144
-#define GCC_USB30_PRIM_SLEEP_CLK				145
-#define GCC_USB30_SEC_MASTER_CLK				146
-#define GCC_USB30_SEC_MASTER_CLK_SRC				147
-#define GCC_USB30_SEC_MOCK_UTMI_CLK				148
-#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC				149
-#define GCC_USB30_SEC_SLEEP_CLK					150
-#define GCC_USB3_PRIM_CLKREF_CLK				151
-#define GCC_USB3_PRIM_PHY_AUX_CLK				152
-#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				153
-#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				154
-#define GCC_USB3_PRIM_PHY_PIPE_CLK				155
-#define GCC_USB3_SEC_CLKREF_CLK					156
-#define GCC_USB3_SEC_PHY_AUX_CLK				157
-#define GCC_USB3_SEC_PHY_AUX_CLK_SRC				158
-#define GCC_USB3_SEC_PHY_PIPE_CLK				159
-#define GCC_USB3_SEC_PHY_COM_AUX_CLK				160
-#define GCC_USB_PHY_CFG_AHB2PHY_CLK				161
-#define GCC_VIDEO_AHB_CLK					162
-#define GCC_VIDEO_AXI_CLK					163
-#define GCC_VIDEO_XO_CLK					164
-#define GPLL0							165
-#define GPLL0_OUT_EVEN						166
-#define GPLL0_OUT_MAIN						167
-#define GCC_GPU_IREF_CLK					168
-#define GCC_SDCC1_AHB_CLK					169
-#define GCC_SDCC1_APPS_CLK					170
-#define GCC_SDCC1_ICE_CORE_CLK					171
-#define GCC_SDCC1_APPS_CLK_SRC					172
-#define GCC_SDCC1_ICE_CORE_CLK_SRC				173
-#define GCC_APC_VS_CLK						174
-#define GCC_GPU_VS_CLK						175
-#define GCC_MSS_VS_CLK						176
-#define GCC_VDDA_VS_CLK						177
-#define GCC_VDDCX_VS_CLK					178
-#define GCC_VDDMX_VS_CLK					179
-#define GCC_VS_CTRL_AHB_CLK					180
-#define GCC_VS_CTRL_CLK						181
-#define GCC_VS_CTRL_CLK_SRC					182
-#define GCC_VSENSOR_CLK_SRC					183
-#define GPLL4							184
-#define GCC_CPUSS_DVM_BUS_CLK					185
-#define GCC_CPUSS_GNOC_CLK					186
-#define GCC_QSPI_CORE_CLK_SRC					187
-#define GCC_QSPI_CORE_CLK					188
-#define GCC_QSPI_CNOC_PERIPH_AHB_CLK				189
-#define GCC_LPASS_Q6_AXI_CLK					190
-#define GCC_LPASS_SWAY_CLK					191
-
-/* GCC Resets */
-#define GCC_MMSS_BCR						0
-#define GCC_PCIE_0_BCR						1
-#define GCC_PCIE_1_BCR						2
-#define GCC_PCIE_PHY_BCR					3
-#define GCC_PDM_BCR						4
-#define GCC_PRNG_BCR						5
-#define GCC_QUPV3_WRAPPER_0_BCR					6
-#define GCC_QUPV3_WRAPPER_1_BCR					7
-#define GCC_QUSB2PHY_PRIM_BCR					8
-#define GCC_QUSB2PHY_SEC_BCR					9
-#define GCC_SDCC2_BCR						10
-#define GCC_SDCC4_BCR						11
-#define GCC_TSIF_BCR						12
-#define GCC_UFS_CARD_BCR					13
-#define GCC_UFS_PHY_BCR						14
-#define GCC_USB30_PRIM_BCR					15
-#define GCC_USB30_SEC_BCR					16
-#define GCC_USB3_PHY_PRIM_BCR					17
-#define GCC_USB3PHY_PHY_PRIM_BCR				18
-#define GCC_USB3_DP_PHY_PRIM_BCR				19
-#define GCC_USB3_PHY_SEC_BCR					20
-#define GCC_USB3PHY_PHY_SEC_BCR					21
-#define GCC_USB3_DP_PHY_SEC_BCR					22
-#define GCC_USB_PHY_CFG_AHB2PHY_BCR				23
-#define GCC_PCIE_0_PHY_BCR					24
-#define GCC_PCIE_1_PHY_BCR					25
-
-/* GCC GDSCRs */
-#define PCIE_0_GDSC						0
-#define PCIE_1_GDSC						1
-#define UFS_CARD_GDSC						2
-#define UFS_PHY_GDSC						3
-#define USB30_PRIM_GDSC						4
-#define USB30_SEC_GDSC						5
-#define HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC			6
-#define HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC			7
-#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC			8
-#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC			9
-#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC			10
-#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC			11
-#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC			12
-
-#endif
diff --git a/include/dt-bindings/clock/qcom,gpucc-sdm845.h b/include/dt-bindings/clock/qcom,gpucc-sdm845.h
deleted file mode 100644
index 9690d90..0000000
--- a/include/dt-bindings/clock/qcom,gpucc-sdm845.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2018, The Linux Foundation. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_CLK_SDM_GPU_CC_SDM845_H
-#define _DT_BINDINGS_CLK_SDM_GPU_CC_SDM845_H
-
-/* GPU_CC clock registers */
-#define GPU_CC_CX_GMU_CLK			0
-#define GPU_CC_CXO_CLK				1
-#define GPU_CC_GMU_CLK_SRC			2
-#define GPU_CC_PLL1				3
-
-/* GPU_CC Resets */
-#define GPUCC_GPU_CC_CX_BCR			0
-#define GPUCC_GPU_CC_GMU_BCR			1
-#define GPUCC_GPU_CC_XO_BCR			2
-
-/* GPU_CC GDSCRs */
-#define GPU_CX_GDSC				0
-#define GPU_GX_GDSC				1
-
-#endif
diff --git a/include/dt-bindings/clock/qcom,lpass-sdm845.h b/include/dt-bindings/clock/qcom,lpass-sdm845.h
deleted file mode 100644
index 6590508..0000000
--- a/include/dt-bindings/clock/qcom,lpass-sdm845.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2018, The Linux Foundation. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_CLK_SDM_LPASS_SDM845_H
-#define _DT_BINDINGS_CLK_SDM_LPASS_SDM845_H
-
-#define LPASS_Q6SS_AHBM_AON_CLK				0
-#define LPASS_Q6SS_AHBS_AON_CLK				1
-#define LPASS_QDSP6SS_XO_CLK				2
-#define LPASS_QDSP6SS_SLEEP_CLK				3
-#define LPASS_QDSP6SS_CORE_CLK				4
-
-#endif
diff --git a/include/dt-bindings/clock/qcom,mmcc-msm8996.h b/include/dt-bindings/clock/qcom,mmcc-msm8996.h
deleted file mode 100644
index d51f9ac..0000000
--- a/include/dt-bindings/clock/qcom,mmcc-msm8996.h
+++ /dev/null
@@ -1,295 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2015, The Linux Foundation. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8996_H
-#define _DT_BINDINGS_CLK_MSM_MMCC_8996_H
-
-#define MMPLL0_EARLY					0
-#define MMPLL0_PLL					1
-#define MMPLL1_EARLY					2
-#define MMPLL1_PLL					3
-#define MMPLL2_EARLY					4
-#define MMPLL2_PLL					5
-#define MMPLL3_EARLY					6
-#define MMPLL3_PLL					7
-#define MMPLL4_EARLY					8
-#define MMPLL4_PLL					9
-#define MMPLL5_EARLY					10
-#define MMPLL5_PLL					11
-#define MMPLL8_EARLY					12
-#define MMPLL8_PLL					13
-#define MMPLL9_EARLY					14
-#define MMPLL9_PLL					15
-#define AHB_CLK_SRC					16
-#define AXI_CLK_SRC					17
-#define MAXI_CLK_SRC					18
-#define DSA_CORE_CLK_SRC				19
-#define GFX3D_CLK_SRC					20
-#define RBBMTIMER_CLK_SRC				21
-#define ISENSE_CLK_SRC					22
-#define RBCPR_CLK_SRC					23
-#define VIDEO_CORE_CLK_SRC				24
-#define VIDEO_SUBCORE0_CLK_SRC				25
-#define VIDEO_SUBCORE1_CLK_SRC				26
-#define PCLK0_CLK_SRC					27
-#define PCLK1_CLK_SRC					28
-#define MDP_CLK_SRC					29
-#define EXTPCLK_CLK_SRC					30
-#define VSYNC_CLK_SRC					31
-#define HDMI_CLK_SRC					32
-#define BYTE0_CLK_SRC					33
-#define BYTE1_CLK_SRC					34
-#define ESC0_CLK_SRC					35
-#define ESC1_CLK_SRC					36
-#define CAMSS_GP0_CLK_SRC				37
-#define CAMSS_GP1_CLK_SRC				38
-#define MCLK0_CLK_SRC					39
-#define MCLK1_CLK_SRC					40
-#define MCLK2_CLK_SRC					41
-#define MCLK3_CLK_SRC					42
-#define CCI_CLK_SRC					43
-#define CSI0PHYTIMER_CLK_SRC				44
-#define CSI1PHYTIMER_CLK_SRC				45
-#define CSI2PHYTIMER_CLK_SRC				46
-#define CSIPHY0_3P_CLK_SRC				47
-#define CSIPHY1_3P_CLK_SRC				48
-#define CSIPHY2_3P_CLK_SRC				49
-#define JPEG0_CLK_SRC					50
-#define JPEG2_CLK_SRC					51
-#define JPEG_DMA_CLK_SRC				52
-#define VFE0_CLK_SRC					53
-#define VFE1_CLK_SRC					54
-#define CPP_CLK_SRC					55
-#define CSI0_CLK_SRC					56
-#define CSI1_CLK_SRC					57
-#define CSI2_CLK_SRC					58
-#define CSI3_CLK_SRC					59
-#define FD_CORE_CLK_SRC					60
-#define MMSS_CXO_CLK					61
-#define MMSS_SLEEPCLK_CLK				62
-#define MMSS_MMAGIC_AHB_CLK				63
-#define MMSS_MMAGIC_CFG_AHB_CLK				64
-#define MMSS_MISC_AHB_CLK				65
-#define MMSS_MISC_CXO_CLK				66
-#define MMSS_BTO_AHB_CLK				67
-#define MMSS_MMAGIC_AXI_CLK				68
-#define MMSS_S0_AXI_CLK					69
-#define MMSS_MMAGIC_MAXI_CLK				70
-#define DSA_CORE_CLK					71
-#define DSA_NOC_CFG_AHB_CLK				72
-#define MMAGIC_CAMSS_AXI_CLK				73
-#define MMAGIC_CAMSS_NOC_CFG_AHB_CLK			74
-#define THROTTLE_CAMSS_CXO_CLK				75
-#define THROTTLE_CAMSS_AHB_CLK				76
-#define THROTTLE_CAMSS_AXI_CLK				77
-#define SMMU_VFE_AHB_CLK				78
-#define SMMU_VFE_AXI_CLK				79
-#define SMMU_CPP_AHB_CLK				80
-#define SMMU_CPP_AXI_CLK				81
-#define SMMU_JPEG_AHB_CLK				82
-#define SMMU_JPEG_AXI_CLK				83
-#define MMAGIC_MDSS_AXI_CLK				84
-#define MMAGIC_MDSS_NOC_CFG_AHB_CLK			85
-#define THROTTLE_MDSS_CXO_CLK				86
-#define THROTTLE_MDSS_AHB_CLK				87
-#define THROTTLE_MDSS_AXI_CLK				88
-#define SMMU_ROT_AHB_CLK				89
-#define SMMU_ROT_AXI_CLK				90
-#define SMMU_MDP_AHB_CLK				91
-#define SMMU_MDP_AXI_CLK				92
-#define MMAGIC_VIDEO_AXI_CLK				93
-#define MMAGIC_VIDEO_NOC_CFG_AHB_CLK			94
-#define THROTTLE_VIDEO_CXO_CLK				95
-#define THROTTLE_VIDEO_AHB_CLK				96
-#define THROTTLE_VIDEO_AXI_CLK				97
-#define SMMU_VIDEO_AHB_CLK				98
-#define SMMU_VIDEO_AXI_CLK				99
-#define MMAGIC_BIMC_AXI_CLK				100
-#define MMAGIC_BIMC_NOC_CFG_AHB_CLK			101
-#define GPU_GX_GFX3D_CLK				102
-#define GPU_GX_RBBMTIMER_CLK				103
-#define GPU_AHB_CLK					104
-#define GPU_AON_ISENSE_CLK				105
-#define VMEM_MAXI_CLK					106
-#define VMEM_AHB_CLK					107
-#define MMSS_RBCPR_CLK					108
-#define MMSS_RBCPR_AHB_CLK				109
-#define VIDEO_CORE_CLK					110
-#define VIDEO_AXI_CLK					111
-#define VIDEO_MAXI_CLK					112
-#define VIDEO_AHB_CLK					113
-#define VIDEO_SUBCORE0_CLK				114
-#define VIDEO_SUBCORE1_CLK				115
-#define MDSS_AHB_CLK					116
-#define MDSS_HDMI_AHB_CLK				117
-#define MDSS_AXI_CLK					118
-#define MDSS_PCLK0_CLK					119
-#define MDSS_PCLK1_CLK					120
-#define MDSS_MDP_CLK					121
-#define MDSS_EXTPCLK_CLK				122
-#define MDSS_VSYNC_CLK					123
-#define MDSS_HDMI_CLK					124
-#define MDSS_BYTE0_CLK					125
-#define MDSS_BYTE1_CLK					126
-#define MDSS_ESC0_CLK					127
-#define MDSS_ESC1_CLK					128
-#define CAMSS_TOP_AHB_CLK				129
-#define CAMSS_AHB_CLK					130
-#define CAMSS_MICRO_AHB_CLK				131
-#define CAMSS_GP0_CLK					132
-#define CAMSS_GP1_CLK					133
-#define CAMSS_MCLK0_CLK					134
-#define CAMSS_MCLK1_CLK					135
-#define CAMSS_MCLK2_CLK					136
-#define CAMSS_MCLK3_CLK					137
-#define CAMSS_CCI_CLK					138
-#define CAMSS_CCI_AHB_CLK				139
-#define CAMSS_CSI0PHYTIMER_CLK				140
-#define CAMSS_CSI1PHYTIMER_CLK				141
-#define CAMSS_CSI2PHYTIMER_CLK				142
-#define CAMSS_CSIPHY0_3P_CLK				143
-#define CAMSS_CSIPHY1_3P_CLK				144
-#define CAMSS_CSIPHY2_3P_CLK				145
-#define CAMSS_JPEG0_CLK					146
-#define CAMSS_JPEG2_CLK					147
-#define CAMSS_JPEG_DMA_CLK				148
-#define CAMSS_JPEG_AHB_CLK				149
-#define CAMSS_JPEG_AXI_CLK				150
-#define CAMSS_VFE_AHB_CLK				151
-#define CAMSS_VFE_AXI_CLK				152
-#define CAMSS_VFE0_CLK					153
-#define CAMSS_VFE0_STREAM_CLK				154
-#define CAMSS_VFE0_AHB_CLK				155
-#define CAMSS_VFE1_CLK					156
-#define CAMSS_VFE1_STREAM_CLK				157
-#define CAMSS_VFE1_AHB_CLK				158
-#define CAMSS_CSI_VFE0_CLK				159
-#define CAMSS_CSI_VFE1_CLK				160
-#define CAMSS_CPP_VBIF_AHB_CLK				161
-#define CAMSS_CPP_AXI_CLK				162
-#define CAMSS_CPP_CLK					163
-#define CAMSS_CPP_AHB_CLK				164
-#define CAMSS_CSI0_CLK					165
-#define CAMSS_CSI0_AHB_CLK				166
-#define CAMSS_CSI0PHY_CLK				167
-#define CAMSS_CSI0RDI_CLK				168
-#define CAMSS_CSI0PIX_CLK				169
-#define CAMSS_CSI1_CLK					170
-#define CAMSS_CSI1_AHB_CLK				171
-#define CAMSS_CSI1PHY_CLK				172
-#define CAMSS_CSI1RDI_CLK				173
-#define CAMSS_CSI1PIX_CLK				174
-#define CAMSS_CSI2_CLK					175
-#define CAMSS_CSI2_AHB_CLK				176
-#define CAMSS_CSI2PHY_CLK				177
-#define CAMSS_CSI2RDI_CLK				178
-#define CAMSS_CSI2PIX_CLK				179
-#define CAMSS_CSI3_CLK					180
-#define CAMSS_CSI3_AHB_CLK				181
-#define CAMSS_CSI3PHY_CLK				182
-#define CAMSS_CSI3RDI_CLK				183
-#define CAMSS_CSI3PIX_CLK				184
-#define CAMSS_ISPIF_AHB_CLK				185
-#define FD_CORE_CLK					186
-#define FD_CORE_UAR_CLK					187
-#define FD_AHB_CLK					188
-#define MMSS_SPDM_CSI0_CLK				189
-#define MMSS_SPDM_JPEG_DMA_CLK				190
-#define MMSS_SPDM_CPP_CLK				191
-#define MMSS_SPDM_PCLK0_CLK				192
-#define MMSS_SPDM_AHB_CLK				193
-#define MMSS_SPDM_GFX3D_CLK				194
-#define MMSS_SPDM_PCLK1_CLK				195
-#define MMSS_SPDM_JPEG2_CLK				196
-#define MMSS_SPDM_DEBUG_CLK				197
-#define MMSS_SPDM_VFE1_CLK				198
-#define MMSS_SPDM_VFE0_CLK				199
-#define MMSS_SPDM_VIDEO_CORE_CLK			200
-#define MMSS_SPDM_AXI_CLK				201
-#define MMSS_SPDM_MDP_CLK				202
-#define MMSS_SPDM_JPEG0_CLK				203
-#define MMSS_SPDM_RM_AXI_CLK				204
-#define MMSS_SPDM_RM_MAXI_CLK				205
-
-#define MMAGICAHB_BCR					0
-#define MMAGIC_CFG_BCR					1
-#define MISC_BCR					2
-#define BTO_BCR						3
-#define MMAGICAXI_BCR					4
-#define MMAGICMAXI_BCR					5
-#define DSA_BCR						6
-#define MMAGIC_CAMSS_BCR				7
-#define THROTTLE_CAMSS_BCR				8
-#define SMMU_VFE_BCR					9
-#define SMMU_CPP_BCR					10
-#define SMMU_JPEG_BCR					11
-#define MMAGIC_MDSS_BCR					12
-#define THROTTLE_MDSS_BCR				13
-#define SMMU_ROT_BCR					14
-#define SMMU_MDP_BCR					15
-#define MMAGIC_VIDEO_BCR				16
-#define THROTTLE_VIDEO_BCR				17
-#define SMMU_VIDEO_BCR					18
-#define MMAGIC_BIMC_BCR					19
-#define GPU_GX_BCR					20
-#define GPU_BCR						21
-#define GPU_AON_BCR					22
-#define VMEM_BCR					23
-#define MMSS_RBCPR_BCR					24
-#define VIDEO_BCR					25
-#define MDSS_BCR					26
-#define CAMSS_TOP_BCR					27
-#define CAMSS_AHB_BCR					28
-#define CAMSS_MICRO_BCR					29
-#define CAMSS_CCI_BCR					30
-#define CAMSS_PHY0_BCR					31
-#define CAMSS_PHY1_BCR					32
-#define CAMSS_PHY2_BCR					33
-#define CAMSS_CSIPHY0_3P_BCR				34
-#define CAMSS_CSIPHY1_3P_BCR				35
-#define CAMSS_CSIPHY2_3P_BCR				36
-#define CAMSS_JPEG_BCR					37
-#define CAMSS_VFE_BCR					38
-#define CAMSS_VFE0_BCR					39
-#define CAMSS_VFE1_BCR					40
-#define CAMSS_CSI_VFE0_BCR				41
-#define CAMSS_CSI_VFE1_BCR				42
-#define CAMSS_CPP_TOP_BCR				43
-#define CAMSS_CPP_BCR					44
-#define CAMSS_CSI0_BCR					45
-#define CAMSS_CSI0RDI_BCR				46
-#define CAMSS_CSI0PIX_BCR				47
-#define CAMSS_CSI1_BCR					48
-#define CAMSS_CSI1RDI_BCR				49
-#define CAMSS_CSI1PIX_BCR				50
-#define CAMSS_CSI2_BCR					51
-#define CAMSS_CSI2RDI_BCR				52
-#define CAMSS_CSI2PIX_BCR				53
-#define CAMSS_CSI3_BCR					54
-#define CAMSS_CSI3RDI_BCR				55
-#define CAMSS_CSI3PIX_BCR				56
-#define CAMSS_ISPIF_BCR					57
-#define FD_BCR						58
-#define MMSS_SPDM_RM_BCR				59
-
-/* Indexes for GDSCs */
-#define MMAGIC_VIDEO_GDSC	0
-#define MMAGIC_MDSS_GDSC	1
-#define MMAGIC_CAMSS_GDSC	2
-#define GPU_GDSC		3
-#define VENUS_GDSC		4
-#define VENUS_CORE0_GDSC	5
-#define VENUS_CORE1_GDSC	6
-#define CAMSS_GDSC		7
-#define VFE0_GDSC		8
-#define VFE1_GDSC		9
-#define JPEG_GDSC		10
-#define CPP_GDSC		11
-#define FD_GDSC			12
-#define MDSS_GDSC		13
-#define GPU_GX_GDSC		14
-#define MMAGIC_BIMC_GDSC	15
-
-#endif
diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h
deleted file mode 100644
index 46309c9..0000000
--- a/include/dt-bindings/clock/qcom,rpmcc.h
+++ /dev/null
@@ -1,174 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright 2015 Linaro Limited
- */
-
-#ifndef _DT_BINDINGS_CLK_MSM_RPMCC_H
-#define _DT_BINDINGS_CLK_MSM_RPMCC_H
-
-/* RPM clocks */
-#define RPM_PXO_CLK				0
-#define RPM_PXO_A_CLK				1
-#define RPM_CXO_CLK				2
-#define RPM_CXO_A_CLK				3
-#define RPM_APPS_FABRIC_CLK			4
-#define RPM_APPS_FABRIC_A_CLK			5
-#define RPM_CFPB_CLK				6
-#define RPM_CFPB_A_CLK				7
-#define RPM_QDSS_CLK				8
-#define RPM_QDSS_A_CLK				9
-#define RPM_DAYTONA_FABRIC_CLK			10
-#define RPM_DAYTONA_FABRIC_A_CLK		11
-#define RPM_EBI1_CLK				12
-#define RPM_EBI1_A_CLK				13
-#define RPM_MM_FABRIC_CLK			14
-#define RPM_MM_FABRIC_A_CLK			15
-#define RPM_MMFPB_CLK				16
-#define RPM_MMFPB_A_CLK				17
-#define RPM_SYS_FABRIC_CLK			18
-#define RPM_SYS_FABRIC_A_CLK			19
-#define RPM_SFPB_CLK				20
-#define RPM_SFPB_A_CLK				21
-#define RPM_SMI_CLK				22
-#define RPM_SMI_A_CLK				23
-#define RPM_PLL4_CLK				24
-#define RPM_XO_D0				25
-#define RPM_XO_D1				26
-#define RPM_XO_A0				27
-#define RPM_XO_A1				28
-#define RPM_XO_A2				29
-#define RPM_NSS_FABRIC_0_CLK			30
-#define RPM_NSS_FABRIC_0_A_CLK			31
-#define RPM_NSS_FABRIC_1_CLK			32
-#define RPM_NSS_FABRIC_1_A_CLK			33
-
-/* SMD RPM clocks */
-#define RPM_SMD_XO_CLK_SRC				0
-#define RPM_SMD_XO_A_CLK_SRC			1
-#define RPM_SMD_PCNOC_CLK				2
-#define RPM_SMD_PCNOC_A_CLK				3
-#define RPM_SMD_SNOC_CLK				4
-#define RPM_SMD_SNOC_A_CLK				5
-#define RPM_SMD_BIMC_CLK				6
-#define RPM_SMD_BIMC_A_CLK				7
-#define RPM_SMD_QDSS_CLK				8
-#define RPM_SMD_QDSS_A_CLK				9
-#define RPM_SMD_BB_CLK1				10
-#define RPM_SMD_BB_CLK1_A				11
-#define RPM_SMD_BB_CLK2				12
-#define RPM_SMD_BB_CLK2_A				13
-#define RPM_SMD_RF_CLK1				14
-#define RPM_SMD_RF_CLK1_A				15
-#define RPM_SMD_RF_CLK2				16
-#define RPM_SMD_RF_CLK2_A				17
-#define RPM_SMD_BB_CLK1_PIN				18
-#define RPM_SMD_BB_CLK1_A_PIN			19
-#define RPM_SMD_BB_CLK2_PIN				20
-#define RPM_SMD_BB_CLK2_A_PIN			21
-#define RPM_SMD_RF_CLK1_PIN				22
-#define RPM_SMD_RF_CLK1_A_PIN			23
-#define RPM_SMD_RF_CLK2_PIN				24
-#define RPM_SMD_RF_CLK2_A_PIN			25
-#define RPM_SMD_PNOC_CLK			26
-#define RPM_SMD_PNOC_A_CLK			27
-#define RPM_SMD_CNOC_CLK			28
-#define RPM_SMD_CNOC_A_CLK			29
-#define RPM_SMD_MMSSNOC_AHB_CLK			30
-#define RPM_SMD_MMSSNOC_AHB_A_CLK		31
-#define RPM_SMD_GFX3D_CLK_SRC			32
-#define RPM_SMD_GFX3D_A_CLK_SRC			33
-#define RPM_SMD_OCMEMGX_CLK			34
-#define RPM_SMD_OCMEMGX_A_CLK			35
-#define RPM_SMD_CXO_D0				36
-#define RPM_SMD_CXO_D0_A			37
-#define RPM_SMD_CXO_D1				38
-#define RPM_SMD_CXO_D1_A			39
-#define RPM_SMD_CXO_A0				40
-#define RPM_SMD_CXO_A0_A			41
-#define RPM_SMD_CXO_A1				42
-#define RPM_SMD_CXO_A1_A			43
-#define RPM_SMD_CXO_A2				44
-#define RPM_SMD_CXO_A2_A			45
-#define RPM_SMD_DIV_CLK1			46
-#define RPM_SMD_DIV_A_CLK1			47
-#define RPM_SMD_DIV_CLK2			48
-#define RPM_SMD_DIV_A_CLK2			49
-#define RPM_SMD_DIFF_CLK			50
-#define RPM_SMD_DIFF_A_CLK			51
-#define RPM_SMD_CXO_D0_PIN			52
-#define RPM_SMD_CXO_D0_A_PIN			53
-#define RPM_SMD_CXO_D1_PIN			54
-#define RPM_SMD_CXO_D1_A_PIN			55
-#define RPM_SMD_CXO_A0_PIN			56
-#define RPM_SMD_CXO_A0_A_PIN			57
-#define RPM_SMD_CXO_A1_PIN			58
-#define RPM_SMD_CXO_A1_A_PIN			59
-#define RPM_SMD_CXO_A2_PIN			60
-#define RPM_SMD_CXO_A2_A_PIN			61
-#define RPM_SMD_AGGR1_NOC_CLK			62
-#define RPM_SMD_AGGR1_NOC_A_CLK			63
-#define RPM_SMD_AGGR2_NOC_CLK			64
-#define RPM_SMD_AGGR2_NOC_A_CLK			65
-#define RPM_SMD_MMAXI_CLK			66
-#define RPM_SMD_MMAXI_A_CLK			67
-#define RPM_SMD_IPA_CLK				68
-#define RPM_SMD_IPA_A_CLK			69
-#define RPM_SMD_CE1_CLK				70
-#define RPM_SMD_CE1_A_CLK			71
-#define RPM_SMD_DIV_CLK3			72
-#define RPM_SMD_DIV_A_CLK3			73
-#define RPM_SMD_LN_BB_CLK			74
-#define RPM_SMD_LN_BB_A_CLK			75
-#define RPM_SMD_BIMC_GPU_CLK			76
-#define RPM_SMD_BIMC_GPU_A_CLK			77
-#define RPM_SMD_QPIC_CLK			78
-#define RPM_SMD_QPIC_CLK_A			79
-#define RPM_SMD_LN_BB_CLK1			80
-#define RPM_SMD_LN_BB_CLK1_A			81
-#define RPM_SMD_LN_BB_CLK2			82
-#define RPM_SMD_LN_BB_CLK2_A			83
-#define RPM_SMD_LN_BB_CLK3_PIN			84
-#define RPM_SMD_LN_BB_CLK3_A_PIN		85
-#define RPM_SMD_RF_CLK3				86
-#define RPM_SMD_RF_CLK3_A			87
-#define RPM_SMD_RF_CLK3_PIN			88
-#define RPM_SMD_RF_CLK3_A_PIN			89
-#define RPM_SMD_MMSSNOC_AXI_CLK			90
-#define RPM_SMD_MMSSNOC_AXI_CLK_A		91
-#define RPM_SMD_CNOC_PERIPH_CLK			92
-#define RPM_SMD_CNOC_PERIPH_A_CLK		93
-#define RPM_SMD_LN_BB_CLK3			94
-#define RPM_SMD_LN_BB_CLK3_A			95
-#define RPM_SMD_LN_BB_CLK1_PIN			96
-#define RPM_SMD_LN_BB_CLK1_A_PIN		97
-#define RPM_SMD_LN_BB_CLK2_PIN			98
-#define RPM_SMD_LN_BB_CLK2_A_PIN		99
-#define RPM_SMD_SYSMMNOC_CLK			100
-#define RPM_SMD_SYSMMNOC_A_CLK			101
-#define RPM_SMD_CE2_CLK				102
-#define RPM_SMD_CE2_A_CLK			103
-#define RPM_SMD_CE3_CLK				104
-#define RPM_SMD_CE3_A_CLK			105
-#define RPM_SMD_QUP_CLK				106
-#define RPM_SMD_QUP_A_CLK			107
-#define RPM_SMD_MMRT_CLK			108
-#define RPM_SMD_MMRT_A_CLK			109
-#define RPM_SMD_MMNRT_CLK			110
-#define RPM_SMD_MMNRT_A_CLK			111
-#define RPM_SMD_SNOC_PERIPH_CLK			112
-#define RPM_SMD_SNOC_PERIPH_A_CLK		113
-#define RPM_SMD_SNOC_LPASS_CLK			114
-#define RPM_SMD_SNOC_LPASS_A_CLK		115
-#define RPM_SMD_HWKM_CLK			116
-#define RPM_SMD_HWKM_A_CLK			117
-#define RPM_SMD_PKA_CLK				118
-#define RPM_SMD_PKA_A_CLK			119
-#define RPM_SMD_CPUSS_GNOC_CLK			120
-#define RPM_SMD_CPUSS_GNOC_A_CLK		121
-#define RPM_SMD_MSS_CFG_AHB_CLK		122
-#define RPM_SMD_MSS_CFG_AHB_A_CLK		123
-#define RPM_SMD_BIMC_FREQ_LOG			124
-#define RPM_SMD_LN_BB_CLK_PIN			125
-#define RPM_SMD_LN_BB_A_CLK_PIN			126
-
-#endif
diff --git a/include/dt-bindings/clock/qcom,rpmh.h b/include/dt-bindings/clock/qcom,rpmh.h
deleted file mode 100644
index bf5b59b..0000000
--- a/include/dt-bindings/clock/qcom,rpmh.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved. */
-
-#ifndef _DT_BINDINGS_CLK_MSM_RPMH_H
-#define _DT_BINDINGS_CLK_MSM_RPMH_H
-
-/* RPMh controlled clocks */
-#define RPMH_CXO_CLK				0
-#define RPMH_CXO_CLK_A				1
-#define RPMH_LN_BB_CLK2				2
-#define RPMH_LN_BB_CLK2_A			3
-#define RPMH_LN_BB_CLK3				4
-#define RPMH_LN_BB_CLK3_A			5
-#define RPMH_RF_CLK1				6
-#define RPMH_RF_CLK1_A				7
-#define RPMH_RF_CLK2				8
-#define RPMH_RF_CLK2_A				9
-#define RPMH_RF_CLK3				10
-#define RPMH_RF_CLK3_A				11
-#define RPMH_IPA_CLK				12
-#define RPMH_LN_BB_CLK1				13
-#define RPMH_LN_BB_CLK1_A			14
-#define RPMH_CE_CLK				15
-#define RPMH_QPIC_CLK				16
-#define RPMH_DIV_CLK1				17
-#define RPMH_DIV_CLK1_A				18
-#define RPMH_RF_CLK4				19
-#define RPMH_RF_CLK4_A				20
-#define RPMH_RF_CLK5				21
-#define RPMH_RF_CLK5_A				22
-#define RPMH_PKA_CLK				23
-#define RPMH_HWKM_CLK				24
-#define RPMH_QLINK_CLK				25
-#define RPMH_QLINK_CLK_A			26
-
-#endif
diff --git a/include/dt-bindings/clock/qcom,turingcc-qcs404.h b/include/dt-bindings/clock/qcom,turingcc-qcs404.h
deleted file mode 100644
index 838faef..0000000
--- a/include/dt-bindings/clock/qcom,turingcc-qcs404.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2019, Linaro Ltd
- */
-
-#ifndef _DT_BINDINGS_CLK_TURING_QCS404_H
-#define _DT_BINDINGS_CLK_TURING_QCS404_H
-
-#define TURING_Q6SS_Q6_AXIM_CLK		0
-#define TURING_Q6SS_AHBM_AON_CLK	1
-#define TURING_WRAPPER_AON_CLK		2
-#define TURING_Q6SS_AHBS_AON_CLK	3
-#define TURING_WRAPPER_QOS_AHBS_AON_CLK	4
-
-#endif
diff --git a/include/dt-bindings/clock/qcom,videocc-sdm845.h b/include/dt-bindings/clock/qcom,videocc-sdm845.h
deleted file mode 100644
index 1b86816..0000000
--- a/include/dt-bindings/clock/qcom,videocc-sdm845.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2018, The Linux Foundation. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H
-#define _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H
-
-/* VIDEO_CC clock registers */
-#define VIDEO_CC_APB_CLK		0
-#define VIDEO_CC_AT_CLK			1
-#define VIDEO_CC_QDSS_TRIG_CLK		2
-#define VIDEO_CC_QDSS_TSCTR_DIV8_CLK	3
-#define VIDEO_CC_VCODEC0_AXI_CLK	4
-#define VIDEO_CC_VCODEC0_CORE_CLK	5
-#define VIDEO_CC_VCODEC1_AXI_CLK	6
-#define VIDEO_CC_VCODEC1_CORE_CLK	7
-#define VIDEO_CC_VENUS_AHB_CLK		8
-#define VIDEO_CC_VENUS_CLK_SRC		9
-#define VIDEO_CC_VENUS_CTL_AXI_CLK	10
-#define VIDEO_CC_VENUS_CTL_CORE_CLK	11
-#define VIDEO_PLL0			12
-
-/* VIDEO_CC Resets */
-#define VIDEO_CC_VENUS_BCR		0
-#define VIDEO_CC_VCODEC0_BCR		1
-#define VIDEO_CC_VCODEC1_BCR		2
-#define VIDEO_CC_INTERFACE_BCR		3
-
-/* VIDEO_CC GDSCRs */
-#define VENUS_GDSC			0
-#define VCODEC0_GDSC			1
-#define VCODEC1_GDSC			2
-
-#endif
diff --git a/include/dt-bindings/dma/qcom-gpi.h b/include/dt-bindings/dma/qcom-gpi.h
deleted file mode 100644
index ebda2a3..0000000
--- a/include/dt-bindings/dma/qcom-gpi.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
-/* Copyright (c) 2020, Linaro Ltd.  */
-
-#ifndef __DT_BINDINGS_DMA_QCOM_GPI_H__
-#define __DT_BINDINGS_DMA_QCOM_GPI_H__
-
-#define QCOM_GPI_SPI		1
-#define QCOM_GPI_UART		2
-#define QCOM_GPI_I2C		3
-
-#endif /* __DT_BINDINGS_DMA_QCOM_GPI_H__ */
diff --git a/include/dt-bindings/firmware/qcom,scm.h b/include/dt-bindings/firmware/qcom,scm.h
deleted file mode 100644
index 6de8b08..0000000
--- a/include/dt-bindings/firmware/qcom,scm.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
-/*
- * Copyright (c) 2010-2015, 2018-2019 The Linux Foundation. All rights reserved.
- * Copyright (C) 2015 Linaro Ltd.
- * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_FIRMWARE_QCOM_SCM_H
-#define _DT_BINDINGS_FIRMWARE_QCOM_SCM_H
-
-#define QCOM_SCM_VMID_TZ		0x1
-#define QCOM_SCM_VMID_HLOS		0x3
-#define QCOM_SCM_VMID_SSC_Q6		0x5
-#define QCOM_SCM_VMID_ADSP_Q6		0x6
-#define QCOM_SCM_VMID_CP_TOUCH		0x8
-#define QCOM_SCM_VMID_CP_BITSTREAM	0x9
-#define QCOM_SCM_VMID_CP_PIXEL		0xA
-#define QCOM_SCM_VMID_CP_NON_PIXEL	0xB
-#define QCOM_SCM_VMID_CP_CAMERA		0xD
-#define QCOM_SCM_VMID_HLOS_FREE		0xE
-#define QCOM_SCM_VMID_MSS_MSA		0xF
-#define QCOM_SCM_VMID_MSS_NONMSA	0x10
-#define QCOM_SCM_VMID_CP_SEC_DISPLAY	0x11
-#define QCOM_SCM_VMID_CP_APP		0x12
-#define QCOM_SCM_VMID_LPASS		0x16
-#define QCOM_SCM_VMID_WLAN		0x18
-#define QCOM_SCM_VMID_WLAN_CE		0x19
-#define QCOM_SCM_VMID_CP_SPSS_SP	0x1A
-#define QCOM_SCM_VMID_CP_CAMERA_PREVIEW 0x1D
-#define QCOM_SCM_VMID_CDSP		0x1E
-#define QCOM_SCM_VMID_CP_SPSS_SP_SHARED 0x22
-#define QCOM_SCM_VMID_CP_SPSS_HLOS_SHARED 0x24
-#define QCOM_SCM_VMID_ADSP_HEAP		0x25
-#define QCOM_SCM_VMID_CP_CDSP		0x2A
-#define QCOM_SCM_VMID_NAV		0x2B
-#define QCOM_SCM_VMID_TVM		0x2D
-#define QCOM_SCM_VMID_OEMVM		0x31
-
-#endif
diff --git a/include/dt-bindings/iio/qcom,spmi-vadc.h b/include/dt-bindings/iio/qcom,spmi-vadc.h
deleted file mode 100644
index 08adfe2..0000000
--- a/include/dt-bindings/iio/qcom,spmi-vadc.h
+++ /dev/null
@@ -1,300 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H
-#define _DT_BINDINGS_QCOM_SPMI_VADC_H
-
-/* Voltage ADC channels */
-#define VADC_USBIN				0x00
-#define VADC_DCIN				0x01
-#define VADC_VCHG_SNS				0x02
-#define VADC_SPARE1_03				0x03
-#define VADC_USB_ID_MV				0x04
-#define VADC_VCOIN				0x05
-#define VADC_VBAT_SNS				0x06
-#define VADC_VSYS				0x07
-#define VADC_DIE_TEMP				0x08
-#define VADC_REF_625MV				0x09
-#define VADC_REF_1250MV				0x0a
-#define VADC_CHG_TEMP				0x0b
-#define VADC_SPARE1				0x0c
-#define VADC_SPARE2				0x0d
-#define VADC_GND_REF				0x0e
-#define VADC_VDD_VADC				0x0f
-
-#define VADC_P_MUX1_1_1				0x10
-#define VADC_P_MUX2_1_1				0x11
-#define VADC_P_MUX3_1_1				0x12
-#define VADC_P_MUX4_1_1				0x13
-#define VADC_P_MUX5_1_1				0x14
-#define VADC_P_MUX6_1_1				0x15
-#define VADC_P_MUX7_1_1				0x16
-#define VADC_P_MUX8_1_1				0x17
-#define VADC_P_MUX9_1_1				0x18
-#define VADC_P_MUX10_1_1			0x19
-#define VADC_P_MUX11_1_1			0x1a
-#define VADC_P_MUX12_1_1			0x1b
-#define VADC_P_MUX13_1_1			0x1c
-#define VADC_P_MUX14_1_1			0x1d
-#define VADC_P_MUX15_1_1			0x1e
-#define VADC_P_MUX16_1_1			0x1f
-
-#define VADC_P_MUX1_1_3				0x20
-#define VADC_P_MUX2_1_3				0x21
-#define VADC_P_MUX3_1_3				0x22
-#define VADC_P_MUX4_1_3				0x23
-#define VADC_P_MUX5_1_3				0x24
-#define VADC_P_MUX6_1_3				0x25
-#define VADC_P_MUX7_1_3				0x26
-#define VADC_P_MUX8_1_3				0x27
-#define VADC_P_MUX9_1_3				0x28
-#define VADC_P_MUX10_1_3			0x29
-#define VADC_P_MUX11_1_3			0x2a
-#define VADC_P_MUX12_1_3			0x2b
-#define VADC_P_MUX13_1_3			0x2c
-#define VADC_P_MUX14_1_3			0x2d
-#define VADC_P_MUX15_1_3			0x2e
-#define VADC_P_MUX16_1_3			0x2f
-
-#define VADC_LR_MUX1_BAT_THERM			0x30
-#define VADC_LR_MUX2_BAT_ID			0x31
-#define VADC_LR_MUX3_XO_THERM			0x32
-#define VADC_LR_MUX4_AMUX_THM1			0x33
-#define VADC_LR_MUX5_AMUX_THM2			0x34
-#define VADC_LR_MUX6_AMUX_THM3			0x35
-#define VADC_LR_MUX7_HW_ID			0x36
-#define VADC_LR_MUX8_AMUX_THM4			0x37
-#define VADC_LR_MUX9_AMUX_THM5			0x38
-#define VADC_LR_MUX10_USB_ID			0x39
-#define VADC_AMUX_PU1				0x3a
-#define VADC_AMUX_PU2				0x3b
-#define VADC_LR_MUX3_BUF_XO_THERM		0x3c
-
-#define VADC_LR_MUX1_PU1_BAT_THERM		0x70
-#define VADC_LR_MUX2_PU1_BAT_ID			0x71
-#define VADC_LR_MUX3_PU1_XO_THERM		0x72
-#define VADC_LR_MUX4_PU1_AMUX_THM1		0x73
-#define VADC_LR_MUX5_PU1_AMUX_THM2		0x74
-#define VADC_LR_MUX6_PU1_AMUX_THM3		0x75
-#define VADC_LR_MUX7_PU1_AMUX_HW_ID		0x76
-#define VADC_LR_MUX8_PU1_AMUX_THM4		0x77
-#define VADC_LR_MUX9_PU1_AMUX_THM5		0x78
-#define VADC_LR_MUX10_PU1_AMUX_USB_ID		0x79
-#define VADC_LR_MUX3_BUF_PU1_XO_THERM		0x7c
-
-#define VADC_LR_MUX1_PU2_BAT_THERM		0xb0
-#define VADC_LR_MUX2_PU2_BAT_ID			0xb1
-#define VADC_LR_MUX3_PU2_XO_THERM		0xb2
-#define VADC_LR_MUX4_PU2_AMUX_THM1		0xb3
-#define VADC_LR_MUX5_PU2_AMUX_THM2		0xb4
-#define VADC_LR_MUX6_PU2_AMUX_THM3		0xb5
-#define VADC_LR_MUX7_PU2_AMUX_HW_ID		0xb6
-#define VADC_LR_MUX8_PU2_AMUX_THM4		0xb7
-#define VADC_LR_MUX9_PU2_AMUX_THM5		0xb8
-#define VADC_LR_MUX10_PU2_AMUX_USB_ID		0xb9
-#define VADC_LR_MUX3_BUF_PU2_XO_THERM		0xbc
-
-#define VADC_LR_MUX1_PU1_PU2_BAT_THERM		0xf0
-#define VADC_LR_MUX2_PU1_PU2_BAT_ID		0xf1
-#define VADC_LR_MUX3_PU1_PU2_XO_THERM		0xf2
-#define VADC_LR_MUX4_PU1_PU2_AMUX_THM1		0xf3
-#define VADC_LR_MUX5_PU1_PU2_AMUX_THM2		0xf4
-#define VADC_LR_MUX6_PU1_PU2_AMUX_THM3		0xf5
-#define VADC_LR_MUX7_PU1_PU2_AMUX_HW_ID		0xf6
-#define VADC_LR_MUX8_PU1_PU2_AMUX_THM4		0xf7
-#define VADC_LR_MUX9_PU1_PU2_AMUX_THM5		0xf8
-#define VADC_LR_MUX10_PU1_PU2_AMUX_USB_ID	0xf9
-#define VADC_LR_MUX3_BUF_PU1_PU2_XO_THERM	0xfc
-
-/* ADC channels for SPMI PMIC5 */
-
-#define ADC5_REF_GND				0x00
-#define ADC5_1P25VREF				0x01
-#define ADC5_VREF_VADC				0x02
-#define ADC5_VREF_VADC5_DIV_3			0x82
-#define ADC5_VPH_PWR				0x83
-#define ADC5_VBAT_SNS				0x84
-#define ADC5_VCOIN				0x85
-#define ADC5_DIE_TEMP				0x06
-#define ADC5_USB_IN_I				0x07
-#define ADC5_USB_IN_V_16			0x08
-#define ADC5_CHG_TEMP				0x09
-#define ADC5_BAT_THERM				0x0a
-#define ADC5_BAT_ID				0x0b
-#define ADC5_XO_THERM				0x0c
-#define ADC5_AMUX_THM1				0x0d
-#define ADC5_AMUX_THM2				0x0e
-#define ADC5_AMUX_THM3				0x0f
-#define ADC5_AMUX_THM4				0x10
-#define ADC5_AMUX_THM5				0x11
-#define ADC5_GPIO1				0x12
-#define ADC5_GPIO2				0x13
-#define ADC5_GPIO3				0x14
-#define ADC5_GPIO4				0x15
-#define ADC5_GPIO5				0x16
-#define ADC5_GPIO6				0x17
-#define ADC5_GPIO7				0x18
-#define ADC5_SBUx				0x99
-#define ADC5_MID_CHG_DIV6			0x1e
-#define ADC5_OFF				0xff
-
-/* 30k pull-up1 */
-#define ADC5_BAT_THERM_30K_PU			0x2a
-#define ADC5_BAT_ID_30K_PU			0x2b
-#define ADC5_XO_THERM_30K_PU			0x2c
-#define ADC5_AMUX_THM1_30K_PU			0x2d
-#define ADC5_AMUX_THM2_30K_PU			0x2e
-#define ADC5_AMUX_THM3_30K_PU			0x2f
-#define ADC5_AMUX_THM4_30K_PU			0x30
-#define ADC5_AMUX_THM5_30K_PU			0x31
-#define ADC5_GPIO1_30K_PU			0x32
-#define ADC5_GPIO2_30K_PU			0x33
-#define ADC5_GPIO3_30K_PU			0x34
-#define ADC5_GPIO4_30K_PU			0x35
-#define ADC5_GPIO5_30K_PU			0x36
-#define ADC5_GPIO6_30K_PU			0x37
-#define ADC5_GPIO7_30K_PU			0x38
-#define ADC5_SBUx_30K_PU			0x39
-
-/* 100k pull-up2 */
-#define ADC5_BAT_THERM_100K_PU			0x4a
-#define ADC5_BAT_ID_100K_PU			0x4b
-#define ADC5_XO_THERM_100K_PU			0x4c
-#define ADC5_AMUX_THM1_100K_PU			0x4d
-#define ADC5_AMUX_THM2_100K_PU			0x4e
-#define ADC5_AMUX_THM3_100K_PU			0x4f
-#define ADC5_AMUX_THM4_100K_PU			0x50
-#define ADC5_AMUX_THM5_100K_PU			0x51
-#define ADC5_GPIO1_100K_PU			0x52
-#define ADC5_GPIO2_100K_PU			0x53
-#define ADC5_GPIO3_100K_PU			0x54
-#define ADC5_GPIO4_100K_PU			0x55
-#define ADC5_GPIO5_100K_PU			0x56
-#define ADC5_GPIO6_100K_PU			0x57
-#define ADC5_GPIO7_100K_PU			0x58
-#define ADC5_SBUx_100K_PU			0x59
-
-/* 400k pull-up3 */
-#define ADC5_BAT_THERM_400K_PU			0x6a
-#define ADC5_BAT_ID_400K_PU			0x6b
-#define ADC5_XO_THERM_400K_PU			0x6c
-#define ADC5_AMUX_THM1_400K_PU			0x6d
-#define ADC5_AMUX_THM2_400K_PU			0x6e
-#define ADC5_AMUX_THM3_400K_PU			0x6f
-#define ADC5_AMUX_THM4_400K_PU			0x70
-#define ADC5_AMUX_THM5_400K_PU			0x71
-#define ADC5_GPIO1_400K_PU			0x72
-#define ADC5_GPIO2_400K_PU			0x73
-#define ADC5_GPIO3_400K_PU			0x74
-#define ADC5_GPIO4_400K_PU			0x75
-#define ADC5_GPIO5_400K_PU			0x76
-#define ADC5_GPIO6_400K_PU			0x77
-#define ADC5_GPIO7_400K_PU			0x78
-#define ADC5_SBUx_400K_PU			0x79
-
-/* 1/3 Divider */
-#define ADC5_GPIO1_DIV3				0x92
-#define ADC5_GPIO2_DIV3				0x93
-#define ADC5_GPIO3_DIV3				0x94
-#define ADC5_GPIO4_DIV3				0x95
-#define ADC5_GPIO5_DIV3				0x96
-#define ADC5_GPIO6_DIV3				0x97
-#define ADC5_GPIO7_DIV3				0x98
-#define ADC5_SBUx_DIV3				0x99
-
-/* Current and combined current/voltage channels */
-#define ADC5_INT_EXT_ISENSE			0xa1
-#define ADC5_PARALLEL_ISENSE			0xa5
-#define ADC5_CUR_REPLICA_VDS			0xa7
-#define ADC5_CUR_SENS_BATFET_VDS_OFFSET		0xa9
-#define ADC5_CUR_SENS_REPLICA_VDS_OFFSET	0xab
-#define ADC5_EXT_SENS_OFFSET			0xad
-
-#define ADC5_INT_EXT_ISENSE_VBAT_VDATA		0xb0
-#define ADC5_INT_EXT_ISENSE_VBAT_IDATA		0xb1
-#define ADC5_EXT_ISENSE_VBAT_VDATA		0xb2
-#define ADC5_EXT_ISENSE_VBAT_IDATA		0xb3
-#define ADC5_PARALLEL_ISENSE_VBAT_VDATA		0xb4
-#define ADC5_PARALLEL_ISENSE_VBAT_IDATA		0xb5
-
-#define ADC5_MAX_CHANNEL			0xc0
-
-/* ADC channels for ADC for PMIC7 */
-
-#define ADC7_REF_GND				0x00
-#define ADC7_1P25VREF				0x01
-#define ADC7_VREF_VADC				0x02
-#define ADC7_DIE_TEMP				0x03
-
-#define ADC7_AMUX_THM1				0x04
-#define ADC7_AMUX_THM2				0x05
-#define ADC7_AMUX_THM3				0x06
-#define ADC7_AMUX_THM4				0x07
-#define ADC7_AMUX_THM5				0x08
-#define ADC7_AMUX_THM6				0x09
-#define ADC7_GPIO1				0x0a
-#define ADC7_GPIO2				0x0b
-#define ADC7_GPIO3				0x0c
-#define ADC7_GPIO4				0x0d
-
-#define ADC7_CHG_TEMP				0x10
-#define ADC7_USB_IN_V_16			0x11
-#define ADC7_VDC_16				0x12
-#define ADC7_CC1_ID				0x13
-#define ADC7_VREF_BAT_THERM			0x15
-#define ADC7_IIN_FB				0x17
-
-/* 30k pull-up1 */
-#define ADC7_AMUX_THM1_30K_PU			0x24
-#define ADC7_AMUX_THM2_30K_PU			0x25
-#define ADC7_AMUX_THM3_30K_PU			0x26
-#define ADC7_AMUX_THM4_30K_PU			0x27
-#define ADC7_AMUX_THM5_30K_PU			0x28
-#define ADC7_AMUX_THM6_30K_PU			0x29
-#define ADC7_GPIO1_30K_PU			0x2a
-#define ADC7_GPIO2_30K_PU			0x2b
-#define ADC7_GPIO3_30K_PU			0x2c
-#define ADC7_GPIO4_30K_PU			0x2d
-#define ADC7_CC1_ID_30K_PU			0x33
-
-/* 100k pull-up2 */
-#define ADC7_AMUX_THM1_100K_PU			0x44
-#define ADC7_AMUX_THM2_100K_PU			0x45
-#define ADC7_AMUX_THM3_100K_PU			0x46
-#define ADC7_AMUX_THM4_100K_PU			0x47
-#define ADC7_AMUX_THM5_100K_PU			0x48
-#define ADC7_AMUX_THM6_100K_PU			0x49
-#define ADC7_GPIO1_100K_PU			0x4a
-#define ADC7_GPIO2_100K_PU			0x4b
-#define ADC7_GPIO3_100K_PU			0x4c
-#define ADC7_GPIO4_100K_PU			0x4d
-#define ADC7_CC1_ID_100K_PU			0x53
-
-/* 400k pull-up3 */
-#define ADC7_AMUX_THM1_400K_PU			0x64
-#define ADC7_AMUX_THM2_400K_PU			0x65
-#define ADC7_AMUX_THM3_400K_PU			0x66
-#define ADC7_AMUX_THM4_400K_PU			0x67
-#define ADC7_AMUX_THM5_400K_PU			0x68
-#define ADC7_AMUX_THM6_400K_PU			0x69
-#define ADC7_GPIO1_400K_PU			0x6a
-#define ADC7_GPIO2_400K_PU			0x6b
-#define ADC7_GPIO3_400K_PU			0x6c
-#define ADC7_GPIO4_400K_PU			0x6d
-#define ADC7_CC1_ID_400K_PU			0x73
-
-/* 1/3 Divider */
-#define ADC7_GPIO1_DIV3				0x8a
-#define ADC7_GPIO2_DIV3				0x8b
-#define ADC7_GPIO3_DIV3				0x8c
-#define ADC7_GPIO4_DIV3				0x8d
-
-#define ADC7_VPH_PWR				0x8e
-#define ADC7_VBAT_SNS				0x8f
-
-#define ADC7_SBUx				0x94
-#define ADC7_VBAT_2S_MID			0x96
-
-#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */
diff --git a/include/dt-bindings/interconnect/qcom,msm8916.h b/include/dt-bindings/interconnect/qcom,msm8916.h
deleted file mode 100644
index 359a75f..0000000
--- a/include/dt-bindings/interconnect/qcom,msm8916.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Qualcomm interconnect IDs
- *
- * Copyright (c) 2019, Linaro Ltd.
- * Author: Georgi Djakov <georgi.djakov@linaro.org>
- */
-
-#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8916_H
-#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8916_H
-
-#define BIMC_SNOC_SLV			0
-#define MASTER_JPEG			1
-#define MASTER_MDP_PORT0		2
-#define MASTER_QDSS_BAM			3
-#define MASTER_QDSS_ETR			4
-#define MASTER_SNOC_CFG			5
-#define MASTER_VFE			6
-#define MASTER_VIDEO_P0			7
-#define SNOC_MM_INT_0			8
-#define SNOC_MM_INT_1			9
-#define SNOC_MM_INT_2			10
-#define SNOC_MM_INT_BIMC		11
-#define PCNOC_SNOC_SLV			12
-#define SLAVE_APSS			13
-#define SLAVE_CATS_128			14
-#define SLAVE_OCMEM_64			15
-#define SLAVE_IMEM			16
-#define SLAVE_QDSS_STM			17
-#define SLAVE_SRVC_SNOC			18
-#define SNOC_BIMC_0_MAS			19
-#define SNOC_BIMC_1_MAS			20
-#define SNOC_INT_0			21
-#define SNOC_INT_1			22
-#define SNOC_INT_BIMC			23
-#define SNOC_PCNOC_MAS			24
-#define SNOC_QDSS_INT			25
-
-#define BIMC_SNOC_MAS			0
-#define MASTER_AMPSS_M0			1
-#define MASTER_GRAPHICS_3D		2
-#define MASTER_TCU0			3
-#define MASTER_TCU1			4
-#define SLAVE_AMPSS_L2			5
-#define SLAVE_EBI_CH0			6
-#define SNOC_BIMC_0_SLV			7
-#define SNOC_BIMC_1_SLV			8
-
-#define MASTER_BLSP_1			0
-#define MASTER_DEHR			1
-#define MASTER_LPASS			2
-#define MASTER_CRYPTO_CORE0		3
-#define MASTER_SDCC_1			4
-#define MASTER_SDCC_2			5
-#define MASTER_SPDM			6
-#define MASTER_USB_HS			7
-#define PCNOC_INT_0			8
-#define PCNOC_INT_1			9
-#define PCNOC_MAS_0			10
-#define PCNOC_MAS_1			11
-#define PCNOC_SLV_0			12
-#define PCNOC_SLV_1			13
-#define PCNOC_SLV_2			14
-#define PCNOC_SLV_3			15
-#define PCNOC_SLV_4			16
-#define PCNOC_SLV_8			17
-#define PCNOC_SLV_9			18
-#define PCNOC_SNOC_MAS			19
-#define SLAVE_BIMC_CFG			20
-#define SLAVE_BLSP_1			21
-#define SLAVE_BOOT_ROM			22
-#define SLAVE_CAMERA_CFG		23
-#define SLAVE_CLK_CTL			24
-#define SLAVE_CRYPTO_0_CFG		25
-#define SLAVE_DEHR_CFG			26
-#define SLAVE_DISPLAY_CFG		27
-#define SLAVE_GRAPHICS_3D_CFG		28
-#define SLAVE_IMEM_CFG			29
-#define SLAVE_LPASS			30
-#define SLAVE_MPM			31
-#define SLAVE_MSG_RAM			32
-#define SLAVE_MSS			33
-#define SLAVE_PDM			34
-#define SLAVE_PMIC_ARB			35
-#define SLAVE_PCNOC_CFG			36
-#define SLAVE_PRNG			37
-#define SLAVE_QDSS_CFG			38
-#define SLAVE_RBCPR_CFG			39
-#define SLAVE_SDCC_1			40
-#define SLAVE_SDCC_2			41
-#define SLAVE_SECURITY			42
-#define SLAVE_SNOC_CFG			43
-#define SLAVE_SPDM			44
-#define SLAVE_TCSR			45
-#define SLAVE_TLMM			46
-#define SLAVE_USB_HS			47
-#define SLAVE_VENUS_CFG			48
-#define SNOC_PCNOC_SLV			49
-
-#endif
diff --git a/include/dt-bindings/interconnect/qcom,msm8996-cbf.h b/include/dt-bindings/interconnect/qcom,msm8996-cbf.h
deleted file mode 100644
index aac5e69..0000000
--- a/include/dt-bindings/interconnect/qcom,msm8996-cbf.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-/*
- * Copyright (C) 2023 Linaro Ltd. All rights reserved.
- */
-
-#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8996_CBF_H
-#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8996_CBF_H
-
-#define MASTER_CBF_M4M		0
-#define SLAVE_CBF_M4M		1
-
-#endif
diff --git a/include/dt-bindings/interconnect/qcom,msm8996.h b/include/dt-bindings/interconnect/qcom,msm8996.h
deleted file mode 100644
index a0b7c0e..0000000
--- a/include/dt-bindings/interconnect/qcom,msm8996.h
+++ /dev/null
@@ -1,163 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
-/*
- * Qualcomm MSM8996 interconnect IDs
- *
- * Copyright (c) 2021 Yassine Oudjana <y.oudjana@protonmail.com>
- */
-
-#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8996_H
-#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8996_H
-
-/* A0NOC */
-#define MASTER_PCIE_0			0
-#define MASTER_PCIE_1			1
-#define MASTER_PCIE_2			2
-
-/* A1NOC */
-#define MASTER_CNOC_A1NOC		0
-#define MASTER_CRYPTO_CORE0		1
-#define MASTER_PNOC_A1NOC		2
-
-/* A2NOC */
-#define MASTER_USB3			0
-#define MASTER_IPA			1
-#define MASTER_UFS			2
-
-/* BIMC */
-#define MASTER_AMPSS_M0			0
-#define MASTER_GRAPHICS_3D		1
-#define MASTER_MNOC_BIMC		2
-#define MASTER_SNOC_BIMC		3
-#define SLAVE_EBI_CH0			4
-#define SLAVE_HMSS_L3			5
-#define SLAVE_BIMC_SNOC_0		6
-#define SLAVE_BIMC_SNOC_1		7
-
-/* CNOC */
-#define MASTER_SNOC_CNOC		0
-#define MASTER_QDSS_DAP			1
-#define SLAVE_CNOC_A1NOC		2
-#define SLAVE_CLK_CTL			3
-#define SLAVE_TCSR			4
-#define SLAVE_TLMM			5
-#define SLAVE_CRYPTO_0_CFG		6
-#define SLAVE_MPM			7
-#define SLAVE_PIMEM_CFG			8
-#define SLAVE_IMEM_CFG			9
-#define SLAVE_MESSAGE_RAM		10
-#define SLAVE_BIMC_CFG			11
-#define SLAVE_PMIC_ARB			12
-#define SLAVE_PRNG			13
-#define SLAVE_DCC_CFG			14
-#define SLAVE_RBCPR_MX			15
-#define SLAVE_QDSS_CFG			16
-#define SLAVE_RBCPR_CX			17
-#define SLAVE_QDSS_RBCPR_APU		18
-#define SLAVE_CNOC_MNOC_CFG		19
-#define SLAVE_SNOC_CFG			20
-#define SLAVE_SNOC_MPU_CFG		21
-#define SLAVE_EBI1_PHY_CFG		22
-#define SLAVE_A0NOC_CFG			23
-#define SLAVE_PCIE_1_CFG		24
-#define SLAVE_PCIE_2_CFG		25
-#define SLAVE_PCIE_0_CFG		26
-#define SLAVE_PCIE20_AHB2PHY		27
-#define SLAVE_A0NOC_MPU_CFG		28
-#define SLAVE_UFS_CFG			29
-#define SLAVE_A1NOC_CFG			30
-#define SLAVE_A1NOC_MPU_CFG		31
-#define SLAVE_A2NOC_CFG			32
-#define SLAVE_A2NOC_MPU_CFG		33
-#define SLAVE_SSC_CFG			34
-#define SLAVE_A0NOC_SMMU_CFG		35
-#define SLAVE_A1NOC_SMMU_CFG		36
-#define SLAVE_A2NOC_SMMU_CFG		37
-#define SLAVE_LPASS_SMMU_CFG		38
-#define SLAVE_CNOC_MNOC_MMSS_CFG	39
-
-/* MNOC */
-#define MASTER_CNOC_MNOC_CFG		0
-#define MASTER_CPP			1
-#define MASTER_JPEG			2
-#define MASTER_MDP_PORT0		3
-#define MASTER_MDP_PORT1		4
-#define MASTER_ROTATOR			5
-#define MASTER_VIDEO_P0			6
-#define MASTER_VFE			7
-#define MASTER_SNOC_VMEM		8
-#define MASTER_VIDEO_P0_OCMEM		9
-#define MASTER_CNOC_MNOC_MMSS_CFG	10
-#define SLAVE_MNOC_BIMC			11
-#define SLAVE_VMEM			12
-#define SLAVE_SERVICE_MNOC		13
-#define SLAVE_MMAGIC_CFG		14
-#define SLAVE_CPR_CFG			15
-#define SLAVE_MISC_CFG			16
-#define SLAVE_VENUS_THROTTLE_CFG	17
-#define SLAVE_VENUS_CFG			18
-#define SLAVE_VMEM_CFG			19
-#define SLAVE_DSA_CFG			20
-#define SLAVE_MMSS_CLK_CFG		21
-#define SLAVE_DSA_MPU_CFG		22
-#define SLAVE_MNOC_MPU_CFG		23
-#define SLAVE_DISPLAY_CFG		24
-#define SLAVE_DISPLAY_THROTTLE_CFG	25
-#define SLAVE_CAMERA_CFG		26
-#define SLAVE_CAMERA_THROTTLE_CFG	27
-#define SLAVE_GRAPHICS_3D_CFG		28
-#define SLAVE_SMMU_MDP_CFG		29
-#define SLAVE_SMMU_ROT_CFG		30
-#define SLAVE_SMMU_VENUS_CFG		31
-#define SLAVE_SMMU_CPP_CFG		32
-#define SLAVE_SMMU_JPEG_CFG		33
-#define SLAVE_SMMU_VFE_CFG		34
-
-/* PNOC */
-#define MASTER_SNOC_PNOC		0
-#define MASTER_SDCC_1			1
-#define MASTER_SDCC_2			2
-#define MASTER_SDCC_4			3
-#define MASTER_USB_HS			4
-#define MASTER_BLSP_1			5
-#define MASTER_BLSP_2			6
-#define MASTER_TSIF			7
-#define SLAVE_PNOC_A1NOC		8
-#define SLAVE_USB_HS			9
-#define SLAVE_SDCC_2			10
-#define SLAVE_SDCC_4			11
-#define SLAVE_TSIF			12
-#define SLAVE_BLSP_2			13
-#define SLAVE_SDCC_1			14
-#define SLAVE_BLSP_1			15
-#define SLAVE_PDM			16
-#define SLAVE_AHB2PHY			17
-
-/* SNOC */
-#define MASTER_HMSS			0
-#define MASTER_QDSS_BAM			1
-#define MASTER_SNOC_CFG			2
-#define MASTER_BIMC_SNOC_0		3
-#define MASTER_BIMC_SNOC_1		4
-#define MASTER_A0NOC_SNOC		5
-#define MASTER_A1NOC_SNOC		6
-#define MASTER_A2NOC_SNOC		7
-#define MASTER_QDSS_ETR			8
-#define SLAVE_A0NOC_SNOC		9
-#define SLAVE_A1NOC_SNOC		10
-#define SLAVE_A2NOC_SNOC		11
-#define SLAVE_HMSS			12
-#define SLAVE_LPASS			13
-#define SLAVE_USB3			14
-#define SLAVE_SNOC_BIMC			15
-#define SLAVE_SNOC_CNOC			16
-#define SLAVE_IMEM			17
-#define SLAVE_PIMEM			18
-#define SLAVE_SNOC_VMEM			19
-#define SLAVE_SNOC_PNOC			20
-#define SLAVE_QDSS_STM			21
-#define SLAVE_PCIE_0			22
-#define SLAVE_PCIE_1			23
-#define SLAVE_PCIE_2			24
-#define SLAVE_SERVICE_SNOC		25
-
-#endif
diff --git a/include/dt-bindings/interconnect/qcom,osm-l3.h b/include/dt-bindings/interconnect/qcom,osm-l3.h
deleted file mode 100644
index 61ef649..0000000
--- a/include/dt-bindings/interconnect/qcom,osm-l3.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2019 The Linux Foundation. All rights reserved.
- */
-
-#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H
-#define __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H
-
-#define MASTER_OSM_L3_APPS	0
-#define SLAVE_OSM_L3		1
-
-#define MASTER_EPSS_L3_APPS	0
-#define SLAVE_EPSS_L3_SHARED	1
-
-#endif
diff --git a/include/dt-bindings/interconnect/qcom,sdm845.h b/include/dt-bindings/interconnect/qcom,sdm845.h
deleted file mode 100644
index 67b500e..0000000
--- a/include/dt-bindings/interconnect/qcom,sdm845.h
+++ /dev/null
@@ -1,150 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Qualcomm SDM845 interconnect IDs
- *
- * Copyright (c) 2018, Linaro Ltd.
- * Author: Georgi Djakov <georgi.djakov@linaro.org>
- */
-
-#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDM845_H
-#define __DT_BINDINGS_INTERCONNECT_QCOM_SDM845_H
-
-#define MASTER_A1NOC_CFG		0
-#define MASTER_TSIF			1
-#define MASTER_SDCC_2			2
-#define MASTER_SDCC_4			3
-#define MASTER_UFS_CARD			4
-#define MASTER_UFS_MEM			5
-#define MASTER_PCIE_0			6
-#define SLAVE_A1NOC_SNOC		7
-#define SLAVE_SERVICE_A1NOC		8
-#define SLAVE_ANOC_PCIE_A1NOC_SNOC	9
-#define MASTER_QUP_1			10
-
-#define MASTER_A2NOC_CFG		0
-#define MASTER_QDSS_BAM			1
-#define MASTER_CNOC_A2NOC		2
-#define MASTER_CRYPTO			3
-#define MASTER_IPA			4
-#define MASTER_PCIE_1			5
-#define MASTER_QDSS_ETR			6
-#define MASTER_USB3_0			7
-#define MASTER_USB3_1			8
-#define SLAVE_A2NOC_SNOC		9
-#define SLAVE_ANOC_PCIE_SNOC		10
-#define SLAVE_SERVICE_A2NOC		11
-#define MASTER_QUP_2			12
-
-#define MASTER_SPDM			0
-#define MASTER_TIC			1
-#define MASTER_SNOC_CNOC		2
-#define MASTER_QDSS_DAP			3
-#define SLAVE_A1NOC_CFG			4
-#define SLAVE_A2NOC_CFG			5
-#define SLAVE_AOP			6
-#define SLAVE_AOSS			7
-#define SLAVE_CAMERA_CFG		8
-#define SLAVE_CLK_CTL			9
-#define SLAVE_CDSP_CFG			10
-#define SLAVE_RBCPR_CX_CFG		11
-#define SLAVE_CRYPTO_0_CFG		12
-#define SLAVE_DCC_CFG			13
-#define SLAVE_CNOC_DDRSS		14
-#define SLAVE_DISPLAY_CFG		15
-#define SLAVE_GLM			16
-#define SLAVE_GFX3D_CFG			17
-#define SLAVE_IMEM_CFG			18
-#define SLAVE_IPA_CFG			19
-#define SLAVE_CNOC_MNOC_CFG		20
-#define SLAVE_PCIE_0_CFG		21
-#define SLAVE_PCIE_1_CFG		22
-#define SLAVE_PDM			23
-#define SLAVE_SOUTH_PHY_CFG		24
-#define SLAVE_PIMEM_CFG			25
-#define SLAVE_PRNG			26
-#define SLAVE_QDSS_CFG			27
-#define SLAVE_BLSP_2			28
-#define SLAVE_BLSP_1			29
-#define SLAVE_SDCC_2			30
-#define SLAVE_SDCC_4			31
-#define SLAVE_SNOC_CFG			32
-#define SLAVE_SPDM_WRAPPER		33
-#define SLAVE_SPSS_CFG			34
-#define SLAVE_TCSR			35
-#define SLAVE_TLMM_NORTH		36
-#define SLAVE_TLMM_SOUTH		37
-#define SLAVE_TSIF			38
-#define SLAVE_UFS_CARD_CFG		39
-#define SLAVE_UFS_MEM_CFG		40
-#define SLAVE_USB3_0			41
-#define SLAVE_USB3_1			42
-#define SLAVE_VENUS_CFG			43
-#define SLAVE_VSENSE_CTRL_CFG		44
-#define SLAVE_CNOC_A2NOC		45
-#define SLAVE_SERVICE_CNOC		46
-
-#define MASTER_CNOC_DC_NOC		0
-#define SLAVE_LLCC_CFG			1
-#define SLAVE_MEM_NOC_CFG		2
-
-#define MASTER_APPSS_PROC		0
-#define MASTER_GNOC_CFG			1
-#define SLAVE_GNOC_SNOC			2
-#define SLAVE_GNOC_MEM_NOC		3
-#define SLAVE_SERVICE_GNOC		4
-
-#define MASTER_TCU_0			0
-#define MASTER_MEM_NOC_CFG		1
-#define MASTER_GNOC_MEM_NOC		2
-#define MASTER_MNOC_HF_MEM_NOC		3
-#define MASTER_MNOC_SF_MEM_NOC		4
-#define MASTER_SNOC_GC_MEM_NOC		5
-#define MASTER_SNOC_SF_MEM_NOC		6
-#define MASTER_GFX3D			7
-#define SLAVE_MSS_PROC_MS_MPU_CFG	8
-#define SLAVE_MEM_NOC_GNOC		9
-#define SLAVE_LLCC			10
-#define SLAVE_MEM_NOC_SNOC		11
-#define SLAVE_SERVICE_MEM_NOC		12
-#define MASTER_LLCC			13
-#define SLAVE_EBI1			14
-
-#define MASTER_CNOC_MNOC_CFG		0
-#define MASTER_CAMNOC_HF0		1
-#define MASTER_CAMNOC_HF1		2
-#define MASTER_CAMNOC_SF		3
-#define MASTER_MDP0			4
-#define MASTER_MDP1			5
-#define MASTER_ROTATOR			6
-#define MASTER_VIDEO_P0			7
-#define MASTER_VIDEO_P1			8
-#define MASTER_VIDEO_PROC		9
-#define SLAVE_MNOC_SF_MEM_NOC		10
-#define SLAVE_MNOC_HF_MEM_NOC		11
-#define SLAVE_SERVICE_MNOC		12
-#define MASTER_CAMNOC_HF0_UNCOMP	13
-#define MASTER_CAMNOC_HF1_UNCOMP	14
-#define MASTER_CAMNOC_SF_UNCOMP		15
-#define SLAVE_CAMNOC_UNCOMP		16
-
-#define MASTER_SNOC_CFG			0
-#define MASTER_A1NOC_SNOC		1
-#define MASTER_A2NOC_SNOC		2
-#define MASTER_GNOC_SNOC		3
-#define MASTER_MEM_NOC_SNOC		4
-#define MASTER_ANOC_PCIE_SNOC		5
-#define MASTER_PIMEM			6
-#define MASTER_GIC			7
-#define SLAVE_APPSS			8
-#define SLAVE_SNOC_CNOC			9
-#define SLAVE_SNOC_MEM_NOC_GC		10
-#define SLAVE_SNOC_MEM_NOC_SF		11
-#define SLAVE_IMEM			12
-#define SLAVE_PCIE_0			13
-#define SLAVE_PCIE_1			14
-#define SLAVE_PIMEM			15
-#define SLAVE_SERVICE_SNOC		16
-#define SLAVE_QDSS_STM			17
-#define SLAVE_TCU			18
-
-#endif
diff --git a/include/dt-bindings/phy/phy-qcom-qmp.h b/include/dt-bindings/phy/phy-qcom-qmp.h
deleted file mode 100644
index 4edec4c..0000000
--- a/include/dt-bindings/phy/phy-qcom-qmp.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
-/*
- * Qualcomm QMP PHY constants
- *
- * Copyright (C) 2022 Linaro Limited
- */
-
-#ifndef _DT_BINDINGS_PHY_QMP
-#define _DT_BINDINGS_PHY_QMP
-
-/* QMP USB4-USB3-DP clocks */
-#define QMP_USB43DP_USB3_PIPE_CLK	0
-#define QMP_USB43DP_DP_LINK_CLK		1
-#define QMP_USB43DP_DP_VCO_DIV_CLK	2
-
-/* QMP USB4-USB3-DP PHYs */
-#define QMP_USB43DP_USB3_PHY		0
-#define QMP_USB43DP_DP_PHY		1
-
-#endif /* _DT_BINDINGS_PHY_QMP */
diff --git a/include/dt-bindings/phy/phy-qcom-qusb2.h b/include/dt-bindings/phy/phy-qcom-qusb2.h
deleted file mode 100644
index 5c5e4d8..0000000
--- a/include/dt-bindings/phy/phy-qcom-qusb2.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2018, The Linux Foundation. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_QCOM_PHY_QUSB2_H_
-#define _DT_BINDINGS_QCOM_PHY_QUSB2_H_
-
-/* PHY HSTX TRIM bit values (24mA to 15mA) */
-#define QUSB2_V2_HSTX_TRIM_24_0_MA		0x0
-#define QUSB2_V2_HSTX_TRIM_23_4_MA		0x1
-#define QUSB2_V2_HSTX_TRIM_22_8_MA		0x2
-#define QUSB2_V2_HSTX_TRIM_22_2_MA		0x3
-#define QUSB2_V2_HSTX_TRIM_21_6_MA		0x4
-#define QUSB2_V2_HSTX_TRIM_21_0_MA		0x5
-#define QUSB2_V2_HSTX_TRIM_20_4_MA		0x6
-#define QUSB2_V2_HSTX_TRIM_19_8_MA		0x7
-#define QUSB2_V2_HSTX_TRIM_19_2_MA		0x8
-#define QUSB2_V2_HSTX_TRIM_18_6_MA		0x9
-#define QUSB2_V2_HSTX_TRIM_18_0_MA		0xa
-#define QUSB2_V2_HSTX_TRIM_17_4_MA		0xb
-#define QUSB2_V2_HSTX_TRIM_16_8_MA		0xc
-#define QUSB2_V2_HSTX_TRIM_16_2_MA		0xd
-#define QUSB2_V2_HSTX_TRIM_15_6_MA		0xe
-#define QUSB2_V2_HSTX_TRIM_15_0_MA		0xf
-
-/* PHY PREEMPHASIS bit values */
-#define QUSB2_V2_PREEMPHASIS_NONE		0
-#define QUSB2_V2_PREEMPHASIS_5_PERCENT		1
-#define QUSB2_V2_PREEMPHASIS_10_PERCENT		2
-#define QUSB2_V2_PREEMPHASIS_15_PERCENT		3
-
-/* PHY PREEMPHASIS-WIDTH bit values */
-#define QUSB2_V2_PREEMPHASIS_WIDTH_FULL_BIT	0
-#define QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT	1
-
-#endif
diff --git a/include/dt-bindings/pinctrl/qcom,pmic-gpio.h b/include/dt-bindings/pinctrl/qcom,pmic-gpio.h
deleted file mode 100644
index e5df5ce..0000000
--- a/include/dt-bindings/pinctrl/qcom,pmic-gpio.h
+++ /dev/null
@@ -1,164 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * This header provides constants for the Qualcomm PMIC GPIO binding.
- */
-
-#ifndef _DT_BINDINGS_PINCTRL_QCOM_PMIC_GPIO_H
-#define _DT_BINDINGS_PINCTRL_QCOM_PMIC_GPIO_H
-
-#define PMIC_GPIO_PULL_UP_30		0
-#define PMIC_GPIO_PULL_UP_1P5		1
-#define PMIC_GPIO_PULL_UP_31P5		2
-#define PMIC_GPIO_PULL_UP_1P5_30	3
-
-#define PMIC_GPIO_STRENGTH_NO		0
-#define PMIC_GPIO_STRENGTH_HIGH		1
-#define PMIC_GPIO_STRENGTH_MED		2
-#define PMIC_GPIO_STRENGTH_LOW		3
-
-/*
- * Note: PM8018 GPIO3 and GPIO4 are supporting
- * only S3 and L2 options (1.8V)
- */
-#define PM8018_GPIO_L6			0
-#define PM8018_GPIO_L5			1
-#define PM8018_GPIO_S3			2
-#define PM8018_GPIO_L14			3
-#define PM8018_GPIO_L2			4
-#define PM8018_GPIO_L4			5
-#define PM8018_GPIO_VDD			6
-
-/*
- * Note: PM8038 GPIO7 and GPIO8 are supporting
- * only L11 and L4 options (1.8V)
- */
-#define PM8038_GPIO_VPH			0
-#define PM8038_GPIO_BB			1
-#define PM8038_GPIO_L11			2
-#define PM8038_GPIO_L15			3
-#define PM8038_GPIO_L4			4
-#define PM8038_GPIO_L3			5
-#define PM8038_GPIO_L17			6
-
-#define PM8058_GPIO_VPH			0
-#define PM8058_GPIO_BB			1
-#define PM8058_GPIO_S3			2
-#define PM8058_GPIO_L3			3
-#define PM8058_GPIO_L7			4
-#define PM8058_GPIO_L6			5
-#define PM8058_GPIO_L5			6
-#define PM8058_GPIO_L2			7
-
-/*
- * Note: PM8916 GPIO1 and GPIO2 are supporting
- * only L2(1.15V) and L5(1.8V) options
- */
-#define PM8916_GPIO_VPH			0
-#define PM8916_GPIO_L2			2
-#define PM8916_GPIO_L5			3
-
-#define PM8917_GPIO_VPH			0
-#define PM8917_GPIO_S4			2
-#define PM8917_GPIO_L15			3
-#define PM8917_GPIO_L4			4
-#define PM8917_GPIO_L3			5
-#define PM8917_GPIO_L17			6
-
-#define PM8921_GPIO_VPH			0
-#define PM8921_GPIO_BB			1
-#define PM8921_GPIO_S4			2
-#define PM8921_GPIO_L15			3
-#define PM8921_GPIO_L4			4
-#define PM8921_GPIO_L3			5
-#define PM8921_GPIO_L17			6
-
-/*
- * Note: PM8941 gpios from 15 to 18 are supporting
- * only S3 and L6 options (1.8V)
- */
-#define PM8941_GPIO_VPH			0
-#define PM8941_GPIO_L1			1
-#define PM8941_GPIO_S3			2
-#define PM8941_GPIO_L6			3
-
-/*
- * Note: PMA8084 gpios from 15 to 18 are supporting
- * only S4 and L6 options (1.8V)
- */
-#define PMA8084_GPIO_VPH		0
-#define PMA8084_GPIO_L1			1
-#define PMA8084_GPIO_S4			2
-#define PMA8084_GPIO_L6			3
-
-#define PM8994_GPIO_VPH			0
-#define PM8994_GPIO_S4			2
-#define PM8994_GPIO_L12			3
-
-/* To be used with "function" */
-#define PMIC_GPIO_FUNC_NORMAL		"normal"
-#define PMIC_GPIO_FUNC_PAIRED		"paired"
-#define PMIC_GPIO_FUNC_FUNC1		"func1"
-#define PMIC_GPIO_FUNC_FUNC2		"func2"
-#define PMIC_GPIO_FUNC_FUNC3		"func3"
-#define PMIC_GPIO_FUNC_FUNC4		"func4"
-#define PMIC_GPIO_FUNC_DTEST1		"dtest1"
-#define PMIC_GPIO_FUNC_DTEST2		"dtest2"
-#define PMIC_GPIO_FUNC_DTEST3		"dtest3"
-#define PMIC_GPIO_FUNC_DTEST4		"dtest4"
-
-#define PM8038_GPIO1_2_LPG_DRV		PMIC_GPIO_FUNC_FUNC1
-#define PM8038_GPIO3_5V_BOOST_EN	PMIC_GPIO_FUNC_FUNC1
-#define PM8038_GPIO4_SSBI_ALT_CLK	PMIC_GPIO_FUNC_FUNC1
-#define PM8038_GPIO5_6_EXT_REG_EN	PMIC_GPIO_FUNC_FUNC1
-#define PM8038_GPIO10_11_EXT_REG_EN	PMIC_GPIO_FUNC_FUNC1
-#define PM8038_GPIO6_7_CLK		PMIC_GPIO_FUNC_FUNC1
-#define PM8038_GPIO9_BAT_ALRM_OUT	PMIC_GPIO_FUNC_FUNC1
-#define PM8038_GPIO6_12_KYPD_DRV	PMIC_GPIO_FUNC_FUNC2
-
-#define PM8058_GPIO7_8_MP3_CLK		PMIC_GPIO_FUNC_FUNC1
-#define PM8058_GPIO7_8_BCLK_19P2MHZ	PMIC_GPIO_FUNC_FUNC2
-#define PM8058_GPIO9_26_KYPD_DRV	PMIC_GPIO_FUNC_FUNC1
-#define PM8058_GPIO21_23_UART_TX	PMIC_GPIO_FUNC_FUNC2
-#define PM8058_GPIO24_26_LPG_DRV	PMIC_GPIO_FUNC_FUNC2
-#define PM8058_GPIO33_BCLK_19P2MHZ	PMIC_GPIO_FUNC_FUNC1
-#define PM8058_GPIO34_35_MP3_CLK	PMIC_GPIO_FUNC_FUNC1
-#define PM8058_GPIO36_BCLK_19P2MHZ	PMIC_GPIO_FUNC_FUNC1
-#define PM8058_GPIO37_UPL_OUT		PMIC_GPIO_FUNC_FUNC1
-#define PM8058_GPIO37_UART_M_RX		PMIC_GPIO_FUNC_FUNC2
-#define PM8058_GPIO38_XO_SLEEP_CLK	PMIC_GPIO_FUNC_FUNC1
-#define PM8058_GPIO38_39_CLK_32KHZ	PMIC_GPIO_FUNC_FUNC2
-#define PM8058_GPIO39_MP3_CLK		PMIC_GPIO_FUNC_FUNC1
-#define PM8058_GPIO40_EXT_BB_EN		PMIC_GPIO_FUNC_FUNC1
-
-#define PM8916_GPIO1_BAT_ALRM_OUT	PMIC_GPIO_FUNC_FUNC1
-#define PM8916_GPIO1_KEYP_DRV		PMIC_GPIO_FUNC_FUNC2
-#define PM8916_GPIO2_DIV_CLK		PMIC_GPIO_FUNC_FUNC1
-#define PM8916_GPIO2_SLEEP_CLK		PMIC_GPIO_FUNC_FUNC2
-#define PM8916_GPIO3_KEYP_DRV		PMIC_GPIO_FUNC_FUNC1
-#define PM8916_GPIO4_KEYP_DRV		PMIC_GPIO_FUNC_FUNC2
-
-#define PM8917_GPIO9_18_KEYP_DRV	PMIC_GPIO_FUNC_FUNC1
-#define PM8917_GPIO20_BAT_ALRM_OUT	PMIC_GPIO_FUNC_FUNC1
-#define PM8917_GPIO21_23_UART_TX	PMIC_GPIO_FUNC_FUNC2
-#define PM8917_GPIO25_26_EXT_REG_EN	PMIC_GPIO_FUNC_FUNC1
-#define PM8917_GPIO37_38_XO_SLEEP_CLK	PMIC_GPIO_FUNC_FUNC1
-#define PM8917_GPIO37_38_MP3_CLK	PMIC_GPIO_FUNC_FUNC2
-
-#define PM8941_GPIO9_14_KYPD_DRV	PMIC_GPIO_FUNC_FUNC1
-#define PM8941_GPIO15_18_DIV_CLK	PMIC_GPIO_FUNC_FUNC1
-#define PM8941_GPIO15_18_SLEEP_CLK	PMIC_GPIO_FUNC_FUNC2
-#define PM8941_GPIO23_26_KYPD_DRV	PMIC_GPIO_FUNC_FUNC1
-#define PM8941_GPIO23_26_LPG_DRV_HI	PMIC_GPIO_FUNC_FUNC2
-#define PM8941_GPIO31_BAT_ALRM_OUT	PMIC_GPIO_FUNC_FUNC1
-#define PM8941_GPIO33_36_LPG_DRV_3D	PMIC_GPIO_FUNC_FUNC1
-#define PM8941_GPIO33_36_LPG_DRV_HI	PMIC_GPIO_FUNC_FUNC2
-
-#define PMA8084_GPIO4_5_LPG_DRV		PMIC_GPIO_FUNC_FUNC1
-#define PMA8084_GPIO7_10_LPG_DRV	PMIC_GPIO_FUNC_FUNC1
-#define PMA8084_GPIO5_14_KEYP_DRV	PMIC_GPIO_FUNC_FUNC2
-#define PMA8084_GPIO19_21_KEYP_DRV	PMIC_GPIO_FUNC_FUNC2
-#define PMA8084_GPIO15_18_DIV_CLK	PMIC_GPIO_FUNC_FUNC1
-#define PMA8084_GPIO15_18_SLEEP_CLK	PMIC_GPIO_FUNC_FUNC2
-#define PMA8084_GPIO22_BAT_ALRM_OUT	PMIC_GPIO_FUNC_FUNC1
-
-#endif
diff --git a/include/dt-bindings/pinctrl/qcom,pmic-mpp.h b/include/dt-bindings/pinctrl/qcom,pmic-mpp.h
deleted file mode 100644
index 32e66ee..0000000
--- a/include/dt-bindings/pinctrl/qcom,pmic-mpp.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * This header provides constants for the Qualcomm PMIC's
- * Multi-Purpose Pin binding.
- */
-
-#ifndef _DT_BINDINGS_PINCTRL_QCOM_PMIC_MPP_H
-#define _DT_BINDINGS_PINCTRL_QCOM_PMIC_MPP_H
-
-/* power-source */
-
-/* Digital Input/Output: level [PM8058] */
-#define PM8058_MPP_VPH			0
-#define PM8058_MPP_S3			1
-#define PM8058_MPP_L2			2
-#define PM8058_MPP_L3			3
-
-/* Digital Input/Output: level [PM8901] */
-#define PM8901_MPP_MSMIO		0
-#define PM8901_MPP_DIG			1
-#define PM8901_MPP_L5			2
-#define PM8901_MPP_S4			3
-#define PM8901_MPP_VPH			4
-
-/* Digital Input/Output: level [PM8921] */
-#define PM8921_MPP_S4			1
-#define PM8921_MPP_L15			3
-#define PM8921_MPP_L17			4
-#define PM8921_MPP_VPH			7
-
-/* Digital Input/Output: level [PM8821] */
-#define PM8821_MPP_1P8			0
-#define PM8821_MPP_VPH			7
-
-/* Digital Input/Output: level [PM8018] */
-#define PM8018_MPP_L4			0
-#define PM8018_MPP_L14			1
-#define PM8018_MPP_S3			2
-#define PM8018_MPP_L6			3
-#define PM8018_MPP_L2			4
-#define PM8018_MPP_L5			5
-#define PM8018_MPP_VPH			7
-
-/* Digital Input/Output: level [PM8038] */
-#define PM8038_MPP_L20			0
-#define PM8038_MPP_L11			1
-#define PM8038_MPP_L5			2
-#define PM8038_MPP_L15			3
-#define PM8038_MPP_L17			4
-#define PM8038_MPP_VPH			7
-
-#define PM8841_MPP_VPH			0
-#define PM8841_MPP_S3			2
-
-#define PM8916_MPP_VPH			0
-#define PM8916_MPP_L2			2
-#define PM8916_MPP_L5			3
-
-#define PM8941_MPP_VPH			0
-#define PM8941_MPP_L1			1
-#define PM8941_MPP_S3			2
-#define PM8941_MPP_L6			3
-
-#define PMA8084_MPP_VPH			0
-#define PMA8084_MPP_L1			1
-#define PMA8084_MPP_S4			2
-#define PMA8084_MPP_L6			3
-
-#define PM8994_MPP_VPH			0
-/* Only supported for MPP_05-MPP_08 */
-#define PM8994_MPP_L19			1
-#define PM8994_MPP_S4			2
-#define PM8994_MPP_L12			3
-
-/*
- * Analog Input - Set the source for analog input.
- * To be used with "qcom,amux-route" property
- */
-#define PMIC_MPP_AMUX_ROUTE_CH5		0
-#define PMIC_MPP_AMUX_ROUTE_CH6		1
-#define PMIC_MPP_AMUX_ROUTE_CH7		2
-#define PMIC_MPP_AMUX_ROUTE_CH8		3
-#define PMIC_MPP_AMUX_ROUTE_ABUS1	4
-#define PMIC_MPP_AMUX_ROUTE_ABUS2	5
-#define PMIC_MPP_AMUX_ROUTE_ABUS3	6
-#define PMIC_MPP_AMUX_ROUTE_ABUS4	7
-
-/* Analog Output: level */
-#define PMIC_MPP_AOUT_LVL_1V25		0
-#define PMIC_MPP_AOUT_LVL_1V25_2	1
-#define PMIC_MPP_AOUT_LVL_0V625		2
-#define PMIC_MPP_AOUT_LVL_0V3125	3
-#define PMIC_MPP_AOUT_LVL_MPP		4
-#define PMIC_MPP_AOUT_LVL_ABUS1		5
-#define PMIC_MPP_AOUT_LVL_ABUS2		6
-#define PMIC_MPP_AOUT_LVL_ABUS3		7
-
-/* To be used with "function" */
-#define PMIC_MPP_FUNC_NORMAL		"normal"
-#define PMIC_MPP_FUNC_PAIRED		"paired"
-#define PMIC_MPP_FUNC_DTEST1		"dtest1"
-#define PMIC_MPP_FUNC_DTEST2		"dtest2"
-#define PMIC_MPP_FUNC_DTEST3		"dtest3"
-#define PMIC_MPP_FUNC_DTEST4		"dtest4"
-
-#endif
diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h
deleted file mode 100644
index 7f4e298..0000000
--- a/include/dt-bindings/power/qcom-rpmpd.h
+++ /dev/null
@@ -1,412 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */
-
-#ifndef _DT_BINDINGS_POWER_QCOM_RPMPD_H
-#define _DT_BINDINGS_POWER_QCOM_RPMPD_H
-
-/* SA8775P Power Domain Indexes */
-#define SA8775P_CX	0
-#define SA8775P_CX_AO	1
-#define SA8775P_DDR	2
-#define SA8775P_EBI	3
-#define SA8775P_GFX	4
-#define SA8775P_LCX	5
-#define SA8775P_LMX	6
-#define SA8775P_MMCX	7
-#define SA8775P_MMCX_AO	8
-#define SA8775P_MSS	9
-#define SA8775P_MX	10
-#define SA8775P_MX_AO	11
-#define SA8775P_MXC	12
-#define SA8775P_MXC_AO	13
-#define SA8775P_NSP0	14
-#define SA8775P_NSP1	15
-#define SA8775P_XO	16
-
-/* SDM670 Power Domain Indexes */
-#define SDM670_MX	0
-#define SDM670_MX_AO	1
-#define SDM670_CX	2
-#define SDM670_CX_AO	3
-#define SDM670_LMX	4
-#define SDM670_LCX	5
-#define SDM670_GFX	6
-#define SDM670_MSS	7
-
-/* SDM845 Power Domain Indexes */
-#define SDM845_EBI	0
-#define SDM845_MX	1
-#define SDM845_MX_AO	2
-#define SDM845_CX	3
-#define SDM845_CX_AO	4
-#define SDM845_LMX	5
-#define SDM845_LCX	6
-#define SDM845_GFX	7
-#define SDM845_MSS	8
-
-/* SDX55 Power Domain Indexes */
-#define SDX55_MSS	0
-#define SDX55_MX	1
-#define SDX55_CX	2
-
-/* SDX65 Power Domain Indexes */
-#define SDX65_MSS	0
-#define SDX65_MX	1
-#define SDX65_MX_AO	2
-#define SDX65_CX	3
-#define SDX65_CX_AO	4
-#define SDX65_MXC	5
-
-/* SM6350 Power Domain Indexes */
-#define SM6350_CX	0
-#define SM6350_GFX	1
-#define SM6350_LCX	2
-#define SM6350_LMX	3
-#define SM6350_MSS	4
-#define SM6350_MX	5
-
-/* SM6350 Power Domain Indexes */
-#define SM6375_VDDCX		0
-#define SM6375_VDDCX_AO	1
-#define SM6375_VDDCX_VFL	2
-#define SM6375_VDDMX		3
-#define SM6375_VDDMX_AO	4
-#define SM6375_VDDMX_VFL	5
-#define SM6375_VDDGX		6
-#define SM6375_VDDGX_AO	7
-#define SM6375_VDD_LPI_CX	8
-#define SM6375_VDD_LPI_MX	9
-
-/* SM8150 Power Domain Indexes */
-#define SM8150_MSS	0
-#define SM8150_EBI	1
-#define SM8150_LMX	2
-#define SM8150_LCX	3
-#define SM8150_GFX	4
-#define SM8150_MX	5
-#define SM8150_MX_AO	6
-#define SM8150_CX	7
-#define SM8150_CX_AO	8
-#define SM8150_MMCX	9
-#define SM8150_MMCX_AO	10
-
-/* SA8155P is a special case, kept for backwards compatibility */
-#define SA8155P_CX	SM8150_CX
-#define SA8155P_CX_AO	SM8150_CX_AO
-#define SA8155P_EBI	SM8150_EBI
-#define SA8155P_GFX	SM8150_GFX
-#define SA8155P_MSS	SM8150_MSS
-#define SA8155P_MX	SM8150_MX
-#define SA8155P_MX_AO	SM8150_MX_AO
-
-/* SM8250 Power Domain Indexes */
-#define SM8250_CX	0
-#define SM8250_CX_AO	1
-#define SM8250_EBI	2
-#define SM8250_GFX	3
-#define SM8250_LCX	4
-#define SM8250_LMX	5
-#define SM8250_MMCX	6
-#define SM8250_MMCX_AO	7
-#define SM8250_MX	8
-#define SM8250_MX_AO	9
-
-/* SM8350 Power Domain Indexes */
-#define SM8350_CX	0
-#define SM8350_CX_AO	1
-#define SM8350_EBI	2
-#define SM8350_GFX	3
-#define SM8350_LCX	4
-#define SM8350_LMX	5
-#define SM8350_MMCX	6
-#define SM8350_MMCX_AO	7
-#define SM8350_MX	8
-#define SM8350_MX_AO	9
-#define SM8350_MXC	10
-#define SM8350_MXC_AO	11
-#define SM8350_MSS	12
-
-/* SM8450 Power Domain Indexes */
-#define SM8450_CX	0
-#define SM8450_CX_AO	1
-#define SM8450_EBI	2
-#define SM8450_GFX	3
-#define SM8450_LCX	4
-#define SM8450_LMX	5
-#define SM8450_MMCX	6
-#define SM8450_MMCX_AO	7
-#define SM8450_MX	8
-#define SM8450_MX_AO	9
-#define SM8450_MXC	10
-#define SM8450_MXC_AO	11
-#define SM8450_MSS	12
-
-/* SM8550 Power Domain Indexes */
-#define SM8550_CX	0
-#define SM8550_CX_AO	1
-#define SM8550_EBI	2
-#define SM8550_GFX	3
-#define SM8550_LCX	4
-#define SM8550_LMX	5
-#define SM8550_MMCX	6
-#define SM8550_MMCX_AO	7
-#define SM8550_MX	8
-#define SM8550_MX_AO	9
-#define SM8550_MXC	10
-#define SM8550_MXC_AO	11
-#define SM8550_MSS	12
-#define SM8550_NSP	13
-
-/* QDU1000/QRU1000 Power Domain Indexes */
-#define QDU1000_EBI	0
-#define QDU1000_MSS	1
-#define QDU1000_CX	2
-#define QDU1000_MX	3
-
-/* SC7180 Power Domain Indexes */
-#define SC7180_CX	0
-#define SC7180_CX_AO	1
-#define SC7180_GFX	2
-#define SC7180_MX	3
-#define SC7180_MX_AO	4
-#define SC7180_LMX	5
-#define SC7180_LCX	6
-#define SC7180_MSS	7
-
-/* SC7280 Power Domain Indexes */
-#define SC7280_CX	0
-#define SC7280_CX_AO	1
-#define SC7280_EBI	2
-#define SC7280_GFX	3
-#define SC7280_MX	4
-#define SC7280_MX_AO	5
-#define SC7280_LMX	6
-#define SC7280_LCX	7
-#define SC7280_MSS	8
-
-/* SC8180X Power Domain Indexes */
-#define SC8180X_CX	0
-#define SC8180X_CX_AO	1
-#define SC8180X_EBI	2
-#define SC8180X_GFX	3
-#define SC8180X_LCX	4
-#define SC8180X_LMX	5
-#define SC8180X_MMCX	6
-#define SC8180X_MMCX_AO	7
-#define SC8180X_MSS	8
-#define SC8180X_MX	9
-#define SC8180X_MX_AO	10
-
-/* SC8280XP Power Domain Indexes */
-#define SC8280XP_CX		0
-#define SC8280XP_CX_AO		1
-#define SC8280XP_DDR		2
-#define SC8280XP_EBI		3
-#define SC8280XP_GFX		4
-#define SC8280XP_LCX		5
-#define SC8280XP_LMX		6
-#define SC8280XP_MMCX		7
-#define SC8280XP_MMCX_AO	8
-#define SC8280XP_MSS		9
-#define SC8280XP_MX		10
-#define SC8280XP_MXC		12
-#define SC8280XP_MX_AO		11
-#define SC8280XP_NSP		13
-#define SC8280XP_QPHY		14
-#define SC8280XP_XO		15
-
-/* SDM845 Power Domain performance levels */
-#define RPMH_REGULATOR_LEVEL_RETENTION		16
-#define RPMH_REGULATOR_LEVEL_MIN_SVS		48
-#define RPMH_REGULATOR_LEVEL_LOW_SVS_D2		52
-#define RPMH_REGULATOR_LEVEL_LOW_SVS_D1		56
-#define RPMH_REGULATOR_LEVEL_LOW_SVS_D0		60
-#define RPMH_REGULATOR_LEVEL_LOW_SVS		64
-#define RPMH_REGULATOR_LEVEL_LOW_SVS_P1		72
-#define RPMH_REGULATOR_LEVEL_LOW_SVS_L1		80
-#define RPMH_REGULATOR_LEVEL_LOW_SVS_L2		96
-#define RPMH_REGULATOR_LEVEL_SVS		128
-#define RPMH_REGULATOR_LEVEL_SVS_L0		144
-#define RPMH_REGULATOR_LEVEL_SVS_L1		192
-#define RPMH_REGULATOR_LEVEL_SVS_L2		224
-#define RPMH_REGULATOR_LEVEL_NOM		256
-#define RPMH_REGULATOR_LEVEL_NOM_L0		288
-#define RPMH_REGULATOR_LEVEL_NOM_L1		320
-#define RPMH_REGULATOR_LEVEL_NOM_L2		336
-#define RPMH_REGULATOR_LEVEL_TURBO		384
-#define RPMH_REGULATOR_LEVEL_TURBO_L0		400
-#define RPMH_REGULATOR_LEVEL_TURBO_L1		416
-#define RPMH_REGULATOR_LEVEL_TURBO_L2		432
-#define RPMH_REGULATOR_LEVEL_TURBO_L3		448
-#define RPMH_REGULATOR_LEVEL_SUPER_TURBO 	464
-#define RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR	480
-
-/* MDM9607 Power Domains */
-#define MDM9607_VDDCX		0
-#define MDM9607_VDDCX_AO	1
-#define MDM9607_VDDCX_VFL	2
-#define MDM9607_VDDMX		3
-#define MDM9607_VDDMX_AO	4
-#define MDM9607_VDDMX_VFL	5
-
-/* MSM8226 Power Domain Indexes */
-#define MSM8226_VDDCX		0
-#define MSM8226_VDDCX_AO	1
-#define MSM8226_VDDCX_VFC	2
-
-/* MSM8939 Power Domains */
-#define MSM8939_VDDMDCX		0
-#define MSM8939_VDDMDCX_AO	1
-#define MSM8939_VDDMDCX_VFC	2
-#define MSM8939_VDDCX		3
-#define MSM8939_VDDCX_AO	4
-#define MSM8939_VDDCX_VFC	5
-#define MSM8939_VDDMX		6
-#define MSM8939_VDDMX_AO	7
-
-/* MSM8916 Power Domain Indexes */
-#define MSM8916_VDDCX		0
-#define MSM8916_VDDCX_AO	1
-#define MSM8916_VDDCX_VFC	2
-#define MSM8916_VDDMX		3
-#define MSM8916_VDDMX_AO	4
-
-/* MSM8909 Power Domain Indexes */
-#define MSM8909_VDDCX		MSM8916_VDDCX
-#define MSM8909_VDDCX_AO	MSM8916_VDDCX_AO
-#define MSM8909_VDDCX_VFC	MSM8916_VDDCX_VFC
-#define MSM8909_VDDMX		MSM8916_VDDMX
-#define MSM8909_VDDMX_AO	MSM8916_VDDMX_AO
-
-/* MSM8917 Power Domain Indexes */
-#define MSM8917_VDDCX		0
-#define MSM8917_VDDCX_AO	1
-#define MSM8917_VDDCX_VFL	2
-#define MSM8917_VDDMX		3
-#define MSM8917_VDDMX_AO	4
-
-/* MSM8937 Power Domain Indexes */
-#define MSM8937_VDDCX		MSM8917_VDDCX
-#define MSM8937_VDDCX_AO	MSM8917_VDDCX_AO
-#define MSM8937_VDDCX_VFL	MSM8917_VDDCX_VFL
-#define MSM8937_VDDMX		MSM8917_VDDMX
-#define MSM8937_VDDMX_AO	MSM8917_VDDMX_AO
-
-/* QM215 Power Domain Indexes */
-#define QM215_VDDCX		MSM8917_VDDCX
-#define QM215_VDDCX_AO		MSM8917_VDDCX_AO
-#define QM215_VDDCX_VFL		MSM8917_VDDCX_VFL
-#define QM215_VDDMX		MSM8917_VDDMX
-#define QM215_VDDMX_AO		MSM8917_VDDMX_AO
-
-/* MSM8953 Power Domain Indexes */
-#define MSM8953_VDDMD		0
-#define MSM8953_VDDMD_AO	1
-#define MSM8953_VDDCX		2
-#define MSM8953_VDDCX_AO	3
-#define MSM8953_VDDCX_VFL	4
-#define MSM8953_VDDMX		5
-#define MSM8953_VDDMX_AO	6
-
-/* MSM8976 Power Domain Indexes */
-#define MSM8976_VDDCX		0
-#define MSM8976_VDDCX_AO	1
-#define MSM8976_VDDCX_VFL	2
-#define MSM8976_VDDMX		3
-#define MSM8976_VDDMX_AO	4
-#define MSM8976_VDDMX_VFL	5
-
-/* MSM8994 Power Domain Indexes */
-#define MSM8994_VDDCX		0
-#define MSM8994_VDDCX_AO	1
-#define MSM8994_VDDCX_VFC	2
-#define MSM8994_VDDMX		3
-#define MSM8994_VDDMX_AO	4
-#define MSM8994_VDDGFX		5
-#define MSM8994_VDDGFX_VFC	6
-
-/* MSM8996 Power Domain Indexes */
-#define MSM8996_VDDCX		0
-#define MSM8996_VDDCX_AO	1
-#define MSM8996_VDDCX_VFC	2
-#define MSM8996_VDDMX		3
-#define MSM8996_VDDMX_AO	4
-#define MSM8996_VDDSSCX		5
-#define MSM8996_VDDSSCX_VFC	6
-
-/* MSM8998 Power Domain Indexes */
-#define MSM8998_VDDCX		0
-#define MSM8998_VDDCX_AO	1
-#define MSM8998_VDDCX_VFL	2
-#define MSM8998_VDDMX		3
-#define MSM8998_VDDMX_AO	4
-#define MSM8998_VDDMX_VFL	5
-#define MSM8998_SSCCX		6
-#define MSM8998_SSCCX_VFL	7
-#define MSM8998_SSCMX		8
-#define MSM8998_SSCMX_VFL	9
-
-/* QCS404 Power Domains */
-#define QCS404_VDDMX		0
-#define QCS404_VDDMX_AO		1
-#define QCS404_VDDMX_VFL	2
-#define QCS404_LPICX		3
-#define QCS404_LPICX_VFL	4
-#define QCS404_LPIMX		5
-#define QCS404_LPIMX_VFL	6
-
-/* SDM660 Power Domains */
-#define SDM660_VDDCX		0
-#define SDM660_VDDCX_AO		1
-#define SDM660_VDDCX_VFL	2
-#define SDM660_VDDMX		3
-#define SDM660_VDDMX_AO		4
-#define SDM660_VDDMX_VFL	5
-#define SDM660_SSCCX		6
-#define SDM660_SSCCX_VFL	7
-#define SDM660_SSCMX		8
-#define SDM660_SSCMX_VFL	9
-
-/* SM6115 Power Domains */
-#define SM6115_VDDCX		0
-#define SM6115_VDDCX_AO		1
-#define SM6115_VDDCX_VFL	2
-#define SM6115_VDDMX		3
-#define SM6115_VDDMX_AO		4
-#define SM6115_VDDMX_VFL	5
-#define SM6115_VDD_LPI_CX	6
-#define SM6115_VDD_LPI_MX	7
-
-/* SM6125 Power Domains */
-#define SM6125_VDDCX		0
-#define SM6125_VDDCX_AO		1
-#define SM6125_VDDCX_VFL	2
-#define SM6125_VDDMX		3
-#define SM6125_VDDMX_AO		4
-#define SM6125_VDDMX_VFL	5
-
-/* QCM2290 Power Domains */
-#define QCM2290_VDDCX		0
-#define QCM2290_VDDCX_AO	1
-#define QCM2290_VDDCX_VFL	2
-#define QCM2290_VDDMX		3
-#define QCM2290_VDDMX_AO	4
-#define QCM2290_VDDMX_VFL	5
-#define QCM2290_VDD_LPI_CX	6
-#define QCM2290_VDD_LPI_MX	7
-
-/* RPM SMD Power Domain performance levels */
-#define RPM_SMD_LEVEL_RETENTION       16
-#define RPM_SMD_LEVEL_RETENTION_PLUS  32
-#define RPM_SMD_LEVEL_MIN_SVS         48
-#define RPM_SMD_LEVEL_LOW_SVS         64
-#define RPM_SMD_LEVEL_SVS             128
-#define RPM_SMD_LEVEL_SVS_PLUS        192
-#define RPM_SMD_LEVEL_NOM             256
-#define RPM_SMD_LEVEL_NOM_PLUS        320
-#define RPM_SMD_LEVEL_TURBO           384
-#define RPM_SMD_LEVEL_TURBO_NO_CPR    416
-#define RPM_SMD_LEVEL_TURBO_HIGH      448
-#define RPM_SMD_LEVEL_BINNING         512
-
-#endif
diff --git a/include/dt-bindings/regulator/qcom,rpmh-regulator.h b/include/dt-bindings/regulator/qcom,rpmh-regulator.h
deleted file mode 100644
index 86713dc..0000000
--- a/include/dt-bindings/regulator/qcom,rpmh-regulator.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */
-
-#ifndef __QCOM_RPMH_REGULATOR_H
-#define __QCOM_RPMH_REGULATOR_H
-
-/*
- * These mode constants may be used to specify modes for various RPMh regulator
- * device tree properties (e.g. regulator-initial-mode).  Each type of regulator
- * supports a subset of the possible modes.
- *
- * %RPMH_REGULATOR_MODE_RET:	Retention mode in which only an extremely small
- *				load current is allowed.  This mode is supported
- *				by LDO and SMPS type regulators.
- * %RPMH_REGULATOR_MODE_LPM:	Low power mode in which a small load current is
- *				allowed.  This mode corresponds to PFM for SMPS
- *				and BOB type regulators.  This mode is supported
- *				by LDO, HFSMPS, BOB, and PMIC4 FTSMPS type
- *				regulators.
- * %RPMH_REGULATOR_MODE_AUTO:	Auto mode in which the regulator hardware
- *				automatically switches between LPM and HPM based
- *				upon the real-time load current.  This mode is
- *				supported by HFSMPS, BOB, and PMIC4 FTSMPS type
- *				regulators.
- * %RPMH_REGULATOR_MODE_HPM:	High power mode in which the full rated current
- *				of the regulator is allowed.  This mode
- *				corresponds to PWM for SMPS and BOB type
- *				regulators.  This mode is supported by all types
- *				of regulators.
- */
-#define RPMH_REGULATOR_MODE_RET		0
-#define RPMH_REGULATOR_MODE_LPM		1
-#define RPMH_REGULATOR_MODE_AUTO	2
-#define RPMH_REGULATOR_MODE_HPM		3
-
-#endif
diff --git a/include/dt-bindings/reset/qcom,gcc-msm8916.h b/include/dt-bindings/reset/qcom,gcc-msm8916.h
deleted file mode 100644
index 1f9be10..0000000
--- a/include/dt-bindings/reset/qcom,gcc-msm8916.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright 2015 Linaro Limited
- */
-
-#ifndef _DT_BINDINGS_RESET_MSM_GCC_8916_H
-#define _DT_BINDINGS_RESET_MSM_GCC_8916_H
-
-#define GCC_BLSP1_BCR			0
-#define GCC_BLSP1_QUP1_BCR		1
-#define GCC_BLSP1_UART1_BCR		2
-#define GCC_BLSP1_QUP2_BCR		3
-#define GCC_BLSP1_UART2_BCR		4
-#define GCC_BLSP1_QUP3_BCR		5
-#define GCC_BLSP1_QUP4_BCR		6
-#define GCC_BLSP1_QUP5_BCR		7
-#define GCC_BLSP1_QUP6_BCR		8
-#define GCC_IMEM_BCR			9
-#define GCC_SMMU_BCR			10
-#define GCC_APSS_TCU_BCR		11
-#define GCC_SMMU_XPU_BCR		12
-#define GCC_PCNOC_TBU_BCR		13
-#define GCC_PRNG_BCR			14
-#define GCC_BOOT_ROM_BCR		15
-#define GCC_CRYPTO_BCR			16
-#define GCC_SEC_CTRL_BCR		17
-#define GCC_AUDIO_CORE_BCR		18
-#define GCC_ULT_AUDIO_BCR		19
-#define GCC_DEHR_BCR			20
-#define GCC_SYSTEM_NOC_BCR		21
-#define GCC_PCNOC_BCR			22
-#define GCC_TCSR_BCR			23
-#define GCC_QDSS_BCR			24
-#define GCC_DCD_BCR			25
-#define GCC_MSG_RAM_BCR			26
-#define GCC_MPM_BCR			27
-#define GCC_SPMI_BCR			28
-#define GCC_SPDM_BCR			29
-#define GCC_MM_SPDM_BCR			30
-#define GCC_BIMC_BCR			31
-#define GCC_RBCPR_BCR			32
-#define GCC_TLMM_BCR			33
-#define GCC_USB_HS_BCR			34
-#define GCC_USB2A_PHY_BCR		35
-#define GCC_SDCC1_BCR			36
-#define GCC_SDCC2_BCR			37
-#define GCC_PDM_BCR			38
-#define GCC_SNOC_BUS_TIMEOUT0_BCR	39
-#define GCC_PCNOC_BUS_TIMEOUT0_BCR	40
-#define GCC_PCNOC_BUS_TIMEOUT1_BCR	41
-#define GCC_PCNOC_BUS_TIMEOUT2_BCR	42
-#define GCC_PCNOC_BUS_TIMEOUT3_BCR	43
-#define GCC_PCNOC_BUS_TIMEOUT4_BCR	44
-#define GCC_PCNOC_BUS_TIMEOUT5_BCR	45
-#define GCC_PCNOC_BUS_TIMEOUT6_BCR	46
-#define GCC_PCNOC_BUS_TIMEOUT7_BCR	47
-#define GCC_PCNOC_BUS_TIMEOUT8_BCR	48
-#define GCC_PCNOC_BUS_TIMEOUT9_BCR	49
-#define GCC_MMSS_BCR			50
-#define GCC_VENUS0_BCR			51
-#define GCC_MDSS_BCR			52
-#define GCC_CAMSS_PHY0_BCR		53
-#define GCC_CAMSS_CSI0_BCR		54
-#define GCC_CAMSS_CSI0PHY_BCR		55
-#define GCC_CAMSS_CSI0RDI_BCR		56
-#define GCC_CAMSS_CSI0PIX_BCR		57
-#define GCC_CAMSS_PHY1_BCR		58
-#define GCC_CAMSS_CSI1_BCR		59
-#define GCC_CAMSS_CSI1PHY_BCR		60
-#define GCC_CAMSS_CSI1RDI_BCR		61
-#define GCC_CAMSS_CSI1PIX_BCR		62
-#define GCC_CAMSS_ISPIF_BCR		63
-#define GCC_CAMSS_CCI_BCR		64
-#define GCC_CAMSS_MCLK0_BCR		65
-#define GCC_CAMSS_MCLK1_BCR		66
-#define GCC_CAMSS_GP0_BCR		67
-#define GCC_CAMSS_GP1_BCR		68
-#define GCC_CAMSS_TOP_BCR		69
-#define GCC_CAMSS_MICRO_BCR		70
-#define GCC_CAMSS_JPEG_BCR		71
-#define GCC_CAMSS_VFE_BCR		72
-#define GCC_CAMSS_CSI_VFE0_BCR		73
-#define GCC_OXILI_BCR			74
-#define GCC_GMEM_BCR			75
-#define GCC_CAMSS_AHB_BCR		76
-#define GCC_MDP_TBU_BCR			77
-#define GCC_GFX_TBU_BCR			78
-#define GCC_GFX_TCU_BCR			79
-#define GCC_MSS_TBU_AXI_BCR		80
-#define GCC_MSS_TBU_GSS_AXI_BCR		81
-#define GCC_MSS_TBU_Q6_AXI_BCR		82
-#define GCC_GTCU_AHB_BCR		83
-#define GCC_SMMU_CFG_BCR		84
-#define GCC_VFE_TBU_BCR			85
-#define GCC_VENUS_TBU_BCR		86
-#define GCC_JPEG_TBU_BCR		87
-#define GCC_PRONTO_TBU_BCR		88
-#define GCC_SMMU_CATS_BCR		89
-
-#endif
diff --git a/include/dt-bindings/reset/qcom,sdm845-aoss.h b/include/dt-bindings/reset/qcom,sdm845-aoss.h
deleted file mode 100644
index 476c5fc..0000000
--- a/include/dt-bindings/reset/qcom,sdm845-aoss.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2018 The Linux Foundation. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_RESET_AOSS_SDM_845_H
-#define _DT_BINDINGS_RESET_AOSS_SDM_845_H
-
-#define AOSS_CC_MSS_RESTART	0
-#define AOSS_CC_CAMSS_RESTART	1
-#define AOSS_CC_VENUS_RESTART	2
-#define AOSS_CC_GPU_RESTART	3
-#define AOSS_CC_DISPSS_RESTART	4
-#define AOSS_CC_WCSS_RESTART	5
-#define AOSS_CC_LPASS_RESTART	6
-
-#endif
diff --git a/include/dt-bindings/reset/qcom,sdm845-pdc.h b/include/dt-bindings/reset/qcom,sdm845-pdc.h
deleted file mode 100644
index 03a0c0e..0000000
--- a/include/dt-bindings/reset/qcom,sdm845-pdc.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2018 The Linux Foundation. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_RESET_PDC_SDM_845_H
-#define _DT_BINDINGS_RESET_PDC_SDM_845_H
-
-#define PDC_APPS_SYNC_RESET	0
-#define PDC_SP_SYNC_RESET	1
-#define PDC_AUDIO_SYNC_RESET	2
-#define PDC_SENSORS_SYNC_RESET	3
-#define PDC_AOP_SYNC_RESET	4
-#define PDC_DEBUG_SYNC_RESET	5
-#define PDC_GPU_SYNC_RESET	6
-#define PDC_DISPLAY_SYNC_RESET	7
-#define PDC_COMPUTE_SYNC_RESET	8
-#define PDC_MODEM_SYNC_RESET	9
-#define PDC_WLAN_RF_SYNC_RESET	10
-#define PDC_WPSS_SYNC_RESET	11
-
-#endif
diff --git a/include/dt-bindings/soc/qcom,apr.h b/include/dt-bindings/soc/qcom,apr.h
deleted file mode 100644
index 0063624..0000000
--- a/include/dt-bindings/soc/qcom,apr.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __DT_BINDINGS_QCOM_APR_H
-#define __DT_BINDINGS_QCOM_APR_H
-
-/* Domain IDs */
-#define APR_DOMAIN_SIM		0x1
-#define APR_DOMAIN_PC		0x2
-#define APR_DOMAIN_MODEM	0x3
-#define APR_DOMAIN_ADSP		0x4
-#define APR_DOMAIN_APPS		0x5
-#define APR_DOMAIN_MAX		0x6
-
-/* ADSP service IDs */
-#define APR_SVC_ADSP_CORE	0x3
-#define APR_SVC_AFE		0x4
-#define APR_SVC_VSM		0x5
-#define APR_SVC_VPM		0x6
-#define APR_SVC_ASM		0x7
-#define APR_SVC_ADM		0x8
-#define APR_SVC_ADSP_MVM	0x09
-#define APR_SVC_ADSP_CVS	0x0A
-#define APR_SVC_ADSP_CVP	0x0B
-#define APR_SVC_USM		0x0C
-#define APR_SVC_LSM		0x0D
-#define APR_SVC_VIDC		0x16
-#define APR_SVC_MAX		0x17
-
-#endif /* __DT_BINDINGS_QCOM_APR_H */
diff --git a/include/dt-bindings/soc/qcom,rpmh-rsc.h b/include/dt-bindings/soc/qcom,rpmh-rsc.h
deleted file mode 100644
index 868f998..0000000
--- a/include/dt-bindings/soc/qcom,rpmh-rsc.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
- */
-
-#ifndef __DT_QCOM_RPMH_RSC_H__
-#define __DT_QCOM_RPMH_RSC_H__
-
-#define SLEEP_TCS	0
-#define WAKE_TCS	1
-#define ACTIVE_TCS	2
-#define CONTROL_TCS	3
-
-#endif /* __DT_QCOM_RPMH_RSC_H__ */
diff --git a/include/dt-bindings/sound/qcom,lpass.h b/include/dt-bindings/sound/qcom,lpass.h
deleted file mode 100644
index a9404c3..0000000
--- a/include/dt-bindings/sound/qcom,lpass.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __DT_QCOM_LPASS_H
-#define __DT_QCOM_LPASS_H
-
-#define MI2S_PRIMARY	0
-#define MI2S_SECONDARY	1
-#define MI2S_TERTIARY	2
-#define MI2S_QUATERNARY	3
-#define MI2S_QUINARY	4
-
-#define LPASS_DP_RX	5
-
-#define LPASS_CDC_DMA_RX0 6
-#define LPASS_CDC_DMA_RX1 7
-#define LPASS_CDC_DMA_RX2 8
-#define LPASS_CDC_DMA_RX3 9
-#define LPASS_CDC_DMA_RX4 10
-#define LPASS_CDC_DMA_RX5 11
-#define LPASS_CDC_DMA_RX6 12
-#define LPASS_CDC_DMA_RX7 13
-#define LPASS_CDC_DMA_RX8 14
-#define LPASS_CDC_DMA_RX9 15
-
-#define LPASS_CDC_DMA_TX0 16
-#define LPASS_CDC_DMA_TX1 17
-#define LPASS_CDC_DMA_TX2 18
-#define LPASS_CDC_DMA_TX3 19
-#define LPASS_CDC_DMA_TX4 20
-#define LPASS_CDC_DMA_TX5 21
-#define LPASS_CDC_DMA_TX6 22
-#define LPASS_CDC_DMA_TX7 23
-#define LPASS_CDC_DMA_TX8 24
-
-#define LPASS_CDC_DMA_VA_TX0 25
-#define LPASS_CDC_DMA_VA_TX1 26
-#define LPASS_CDC_DMA_VA_TX2 27
-#define LPASS_CDC_DMA_VA_TX3 28
-#define LPASS_CDC_DMA_VA_TX4 29
-#define LPASS_CDC_DMA_VA_TX5 30
-#define LPASS_CDC_DMA_VA_TX6 31
-#define LPASS_CDC_DMA_VA_TX7 32
-#define LPASS_CDC_DMA_VA_TX8 33
-
-#define LPASS_MCLK0	0
-
-#endif /* __DT_QCOM_LPASS_H */
diff --git a/include/dt-bindings/sound/qcom,q6afe.h b/include/dt-bindings/sound/qcom,q6afe.h
deleted file mode 100644
index 9d5d89c..0000000
--- a/include/dt-bindings/sound/qcom,q6afe.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __DT_BINDINGS_Q6_AFE_H__
-#define __DT_BINDINGS_Q6_AFE_H__
-
-/* This file exists due to backward compatibility reasons, Please do not DELETE! */
-
-#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
-
-#endif /* __DT_BINDINGS_Q6_AFE_H__ */
diff --git a/include/dt-bindings/sound/qcom,q6asm.h b/include/dt-bindings/sound/qcom,q6asm.h
deleted file mode 100644
index f59d74f..0000000
--- a/include/dt-bindings/sound/qcom,q6asm.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __DT_BINDINGS_Q6_ASM_H__
-#define __DT_BINDINGS_Q6_ASM_H__
-
-#define	MSM_FRONTEND_DAI_MULTIMEDIA1	0
-#define	MSM_FRONTEND_DAI_MULTIMEDIA2	1
-#define	MSM_FRONTEND_DAI_MULTIMEDIA3	2
-#define	MSM_FRONTEND_DAI_MULTIMEDIA4	3
-#define	MSM_FRONTEND_DAI_MULTIMEDIA5	4
-#define	MSM_FRONTEND_DAI_MULTIMEDIA6	5
-#define	MSM_FRONTEND_DAI_MULTIMEDIA7	6
-#define	MSM_FRONTEND_DAI_MULTIMEDIA8	7
-#define	MSM_FRONTEND_DAI_MULTIMEDIA9	8
-#define	MSM_FRONTEND_DAI_MULTIMEDIA10	9
-#define	MSM_FRONTEND_DAI_MULTIMEDIA11	10
-#define	MSM_FRONTEND_DAI_MULTIMEDIA12	11
-#define	MSM_FRONTEND_DAI_MULTIMEDIA13	12
-#define	MSM_FRONTEND_DAI_MULTIMEDIA14	13
-#define	MSM_FRONTEND_DAI_MULTIMEDIA15	14
-#define	MSM_FRONTEND_DAI_MULTIMEDIA16	15
-
-#define Q6ASM_DAI_TX_RX	0
-#define Q6ASM_DAI_TX	1
-#define Q6ASM_DAI_RX	2
-
-#endif /* __DT_BINDINGS_Q6_ASM_H__ */
diff --git a/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h b/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h
deleted file mode 100644
index 39f2032..0000000
--- a/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h
+++ /dev/null
@@ -1,234 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __DT_BINDINGS_Q6_AUDIO_PORTS_H__
-#define __DT_BINDINGS_Q6_AUDIO_PORTS_H__
-
-/* LPASS Audio virtual ports IDs */
-#define HDMI_RX		1
-#define SLIMBUS_0_RX    2
-#define SLIMBUS_0_TX    3
-#define SLIMBUS_1_RX    4
-#define SLIMBUS_1_TX    5
-#define SLIMBUS_2_RX    6
-#define SLIMBUS_2_TX    7
-#define SLIMBUS_3_RX    8
-#define SLIMBUS_3_TX    9
-#define SLIMBUS_4_RX    10
-#define SLIMBUS_4_TX    11
-#define SLIMBUS_5_RX    12
-#define SLIMBUS_5_TX    13
-#define SLIMBUS_6_RX    14
-#define SLIMBUS_6_TX    15
-#define PRIMARY_MI2S_RX		16
-#define PRIMARY_MI2S_TX		17
-#define SECONDARY_MI2S_RX	18
-#define SECONDARY_MI2S_TX	19
-#define TERTIARY_MI2S_RX	20
-#define TERTIARY_MI2S_TX	21
-#define QUATERNARY_MI2S_RX	22
-#define QUATERNARY_MI2S_TX	23
-#define PRIMARY_TDM_RX_0	24
-#define PRIMARY_TDM_TX_0	25
-#define PRIMARY_TDM_RX_1	26
-#define PRIMARY_TDM_TX_1	27
-#define PRIMARY_TDM_RX_2	28
-#define PRIMARY_TDM_TX_2	29
-#define PRIMARY_TDM_RX_3	30
-#define PRIMARY_TDM_TX_3	31
-#define PRIMARY_TDM_RX_4	32
-#define PRIMARY_TDM_TX_4	33
-#define PRIMARY_TDM_RX_5	34
-#define PRIMARY_TDM_TX_5	35
-#define PRIMARY_TDM_RX_6	36
-#define PRIMARY_TDM_TX_6	37
-#define PRIMARY_TDM_RX_7	38
-#define PRIMARY_TDM_TX_7	39
-#define SECONDARY_TDM_RX_0	40
-#define SECONDARY_TDM_TX_0	41
-#define SECONDARY_TDM_RX_1	42
-#define SECONDARY_TDM_TX_1	43
-#define SECONDARY_TDM_RX_2	44
-#define SECONDARY_TDM_TX_2	45
-#define SECONDARY_TDM_RX_3	46
-#define SECONDARY_TDM_TX_3	47
-#define SECONDARY_TDM_RX_4	48
-#define SECONDARY_TDM_TX_4	49
-#define SECONDARY_TDM_RX_5	50
-#define SECONDARY_TDM_TX_5	51
-#define SECONDARY_TDM_RX_6	52
-#define SECONDARY_TDM_TX_6	53
-#define SECONDARY_TDM_RX_7	54
-#define SECONDARY_TDM_TX_7	55
-#define TERTIARY_TDM_RX_0	56
-#define TERTIARY_TDM_TX_0	57
-#define TERTIARY_TDM_RX_1	58
-#define TERTIARY_TDM_TX_1	59
-#define TERTIARY_TDM_RX_2	60
-#define TERTIARY_TDM_TX_2	61
-#define TERTIARY_TDM_RX_3	62
-#define TERTIARY_TDM_TX_3	63
-#define TERTIARY_TDM_RX_4	64
-#define TERTIARY_TDM_TX_4	65
-#define TERTIARY_TDM_RX_5	66
-#define TERTIARY_TDM_TX_5	67
-#define TERTIARY_TDM_RX_6	68
-#define TERTIARY_TDM_TX_6	69
-#define TERTIARY_TDM_RX_7	70
-#define TERTIARY_TDM_TX_7	71
-#define QUATERNARY_TDM_RX_0	72
-#define QUATERNARY_TDM_TX_0	73
-#define QUATERNARY_TDM_RX_1	74
-#define QUATERNARY_TDM_TX_1	75
-#define QUATERNARY_TDM_RX_2	76
-#define QUATERNARY_TDM_TX_2	77
-#define QUATERNARY_TDM_RX_3	78
-#define QUATERNARY_TDM_TX_3	79
-#define QUATERNARY_TDM_RX_4	80
-#define QUATERNARY_TDM_TX_4	81
-#define QUATERNARY_TDM_RX_5	82
-#define QUATERNARY_TDM_TX_5	83
-#define QUATERNARY_TDM_RX_6	84
-#define QUATERNARY_TDM_TX_6	85
-#define QUATERNARY_TDM_RX_7	86
-#define QUATERNARY_TDM_TX_7	87
-#define QUINARY_TDM_RX_0	88
-#define QUINARY_TDM_TX_0	89
-#define QUINARY_TDM_RX_1	90
-#define QUINARY_TDM_TX_1	91
-#define QUINARY_TDM_RX_2	92
-#define QUINARY_TDM_TX_2	93
-#define QUINARY_TDM_RX_3	94
-#define QUINARY_TDM_TX_3	95
-#define QUINARY_TDM_RX_4	96
-#define QUINARY_TDM_TX_4	97
-#define QUINARY_TDM_RX_5	98
-#define QUINARY_TDM_TX_5	99
-#define QUINARY_TDM_RX_6	100
-#define QUINARY_TDM_TX_6	101
-#define QUINARY_TDM_RX_7	102
-#define QUINARY_TDM_TX_7	103
-#define DISPLAY_PORT_RX		104
-#define WSA_CODEC_DMA_RX_0	105
-#define WSA_CODEC_DMA_TX_0	106
-#define WSA_CODEC_DMA_RX_1	107
-#define WSA_CODEC_DMA_TX_1	108
-#define WSA_CODEC_DMA_TX_2	109
-#define VA_CODEC_DMA_TX_0	110
-#define VA_CODEC_DMA_TX_1	111
-#define VA_CODEC_DMA_TX_2	112
-#define RX_CODEC_DMA_RX_0	113
-#define TX_CODEC_DMA_TX_0	114
-#define RX_CODEC_DMA_RX_1	115
-#define TX_CODEC_DMA_TX_1	116
-#define RX_CODEC_DMA_RX_2	117
-#define TX_CODEC_DMA_TX_2	118
-#define RX_CODEC_DMA_RX_3	119
-#define TX_CODEC_DMA_TX_3	120
-#define RX_CODEC_DMA_RX_4	121
-#define TX_CODEC_DMA_TX_4	122
-#define RX_CODEC_DMA_RX_5	123
-#define TX_CODEC_DMA_TX_5	124
-#define RX_CODEC_DMA_RX_6	125
-#define RX_CODEC_DMA_RX_7	126
-#define QUINARY_MI2S_RX		127
-#define QUINARY_MI2S_TX		128
-#define DISPLAY_PORT_RX_0	DISPLAY_PORT_RX
-#define DISPLAY_PORT_RX_1	129
-#define DISPLAY_PORT_RX_2	130
-#define DISPLAY_PORT_RX_3	131
-#define DISPLAY_PORT_RX_4	132
-#define DISPLAY_PORT_RX_5	133
-#define DISPLAY_PORT_RX_6	134
-#define DISPLAY_PORT_RX_7	135
-
-#define LPASS_CLK_ID_PRI_MI2S_IBIT	1
-#define LPASS_CLK_ID_PRI_MI2S_EBIT	2
-#define LPASS_CLK_ID_SEC_MI2S_IBIT	3
-#define LPASS_CLK_ID_SEC_MI2S_EBIT	4
-#define LPASS_CLK_ID_TER_MI2S_IBIT	5
-#define LPASS_CLK_ID_TER_MI2S_EBIT	6
-#define LPASS_CLK_ID_QUAD_MI2S_IBIT	7
-#define LPASS_CLK_ID_QUAD_MI2S_EBIT	8
-#define LPASS_CLK_ID_SPEAKER_I2S_IBIT	9
-#define LPASS_CLK_ID_SPEAKER_I2S_EBIT	10
-#define LPASS_CLK_ID_SPEAKER_I2S_OSR	11
-#define LPASS_CLK_ID_QUI_MI2S_IBIT	12
-#define LPASS_CLK_ID_QUI_MI2S_EBIT	13
-#define LPASS_CLK_ID_SEN_MI2S_IBIT	14
-#define LPASS_CLK_ID_SEN_MI2S_EBIT	15
-#define LPASS_CLK_ID_INT0_MI2S_IBIT	16
-#define LPASS_CLK_ID_INT1_MI2S_IBIT	17
-#define LPASS_CLK_ID_INT2_MI2S_IBIT	18
-#define LPASS_CLK_ID_INT3_MI2S_IBIT	19
-#define LPASS_CLK_ID_INT4_MI2S_IBIT	20
-#define LPASS_CLK_ID_INT5_MI2S_IBIT	21
-#define LPASS_CLK_ID_INT6_MI2S_IBIT	22
-#define LPASS_CLK_ID_QUI_MI2S_OSR	23
-#define LPASS_CLK_ID_PRI_PCM_IBIT	24
-#define LPASS_CLK_ID_PRI_PCM_EBIT	25
-#define LPASS_CLK_ID_SEC_PCM_IBIT	26
-#define LPASS_CLK_ID_SEC_PCM_EBIT	27
-#define LPASS_CLK_ID_TER_PCM_IBIT	28
-#define LPASS_CLK_ID_TER_PCM_EBIT	29
-#define LPASS_CLK_ID_QUAD_PCM_IBIT	30
-#define LPASS_CLK_ID_QUAD_PCM_EBIT	31
-#define LPASS_CLK_ID_QUIN_PCM_IBIT	32
-#define LPASS_CLK_ID_QUIN_PCM_EBIT	33
-#define LPASS_CLK_ID_QUI_PCM_OSR	34
-#define LPASS_CLK_ID_PRI_TDM_IBIT	35
-#define LPASS_CLK_ID_PRI_TDM_EBIT	36
-#define LPASS_CLK_ID_SEC_TDM_IBIT	37
-#define LPASS_CLK_ID_SEC_TDM_EBIT	38
-#define LPASS_CLK_ID_TER_TDM_IBIT	39
-#define LPASS_CLK_ID_TER_TDM_EBIT	40
-#define LPASS_CLK_ID_QUAD_TDM_IBIT	41
-#define LPASS_CLK_ID_QUAD_TDM_EBIT	42
-#define LPASS_CLK_ID_QUIN_TDM_IBIT	43
-#define LPASS_CLK_ID_QUIN_TDM_EBIT	44
-#define LPASS_CLK_ID_QUIN_TDM_OSR	45
-#define LPASS_CLK_ID_MCLK_1		46
-#define LPASS_CLK_ID_MCLK_2		47
-#define LPASS_CLK_ID_MCLK_3		48
-#define LPASS_CLK_ID_MCLK_4		49
-#define LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE	50
-#define LPASS_CLK_ID_INT_MCLK_0		51
-#define LPASS_CLK_ID_INT_MCLK_1		52
-#define LPASS_CLK_ID_MCLK_5		53
-#define LPASS_CLK_ID_WSA_CORE_MCLK	54
-#define LPASS_CLK_ID_WSA_CORE_NPL_MCLK	55
-#define LPASS_CLK_ID_VA_CORE_MCLK	56
-#define LPASS_CLK_ID_TX_CORE_MCLK	57
-#define LPASS_CLK_ID_TX_CORE_NPL_MCLK	58
-#define LPASS_CLK_ID_RX_CORE_MCLK	59
-#define LPASS_CLK_ID_RX_CORE_NPL_MCLK	60
-#define LPASS_CLK_ID_VA_CORE_2X_MCLK	61
-/* Clock ID for MCLK for WSA2 core */
-#define LPASS_CLK_ID_WSA2_CORE_MCLK	62
-/* Clock ID for NPL MCLK for WSA2 core */
-#define LPASS_CLK_ID_WSA2_CORE_2X_MCLK	63
-/* Clock ID for RX Core TX MCLK */
-#define LPASS_CLK_ID_RX_CORE_TX_MCLK	64
-/* Clock ID for RX CORE TX 2X MCLK */
-#define LPASS_CLK_ID_RX_CORE_TX_2X_MCLK	65
-/* Clock ID for WSA core TX MCLK */
-#define LPASS_CLK_ID_WSA_CORE_TX_MCLK	66
-/* Clock ID for WSA core TX 2X MCLK */
-#define LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK	67
-/* Clock ID for WSA2 core TX MCLK */
-#define LPASS_CLK_ID_WSA2_CORE_TX_MCLK	68
-/* Clock ID for WSA2 core TX 2X MCLK */
-#define LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK	69
-/* Clock ID for RX CORE MCLK2 2X  MCLK */
-#define LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK	70
-
-#define LPASS_HW_AVTIMER_VOTE		101
-#define LPASS_HW_MACRO_VOTE		102
-#define LPASS_HW_DCODEC_VOTE		103
-
-#define Q6AFE_MAX_CLK_ID			104
-
-#define LPASS_CLK_ATTRIBUTE_INVALID		0x0
-#define LPASS_CLK_ATTRIBUTE_COUPLE_NO		0x1
-#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND	0x2
-#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR	0x3
-
-#endif /* __DT_BINDINGS_Q6_AUDIO_PORTS_H__ */
diff --git a/include/dt-bindings/sound/qcom,wcd9335.h b/include/dt-bindings/sound/qcom,wcd9335.h
deleted file mode 100644
index f5e9f1d..0000000
--- a/include/dt-bindings/sound/qcom,wcd9335.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-
-#ifndef __DT_SOUND_QCOM_WCD9335_H
-#define __DT_SOUND_QCOM_WCD9335_H
-
-#define AIF1_PB                 0
-#define AIF1_CAP                1
-#define AIF2_PB                 2
-#define AIF2_CAP                3
-#define AIF3_PB                 4
-#define AIF3_CAP                5
-#define AIF4_PB                 6
-#define NUM_CODEC_DAIS          7
-
-#endif
diff --git a/include/firmware/imx/sci/rpc.h b/include/firmware/imx/sci/rpc.h
index 28adec2..04acc7f 100644
--- a/include/firmware/imx/sci/rpc.h
+++ b/include/firmware/imx/sci/rpc.h
@@ -231,4 +231,7 @@
 #define TIMER_FUNC_SET_SYSCTR_PERIODIC_ALARM 17U /* Index for sc_timer_set_sysctr_periodic_alarm() RPC call */
 #define TIMER_FUNC_CANCEL_SYSCTR_ALARM 18U /* Index for sc_timer_cancel_sysctr_alarm() RPC call */
 
+/* Siemens specific API extension */
+#define TIMER_FUNC_CTRL_SIEMENS_PMIC_WDOG 20U  /*!< Index for sc_timer_ctrl_pmic_wdog() RPC call */
+
 #endif /* SC_RPC_H */
diff --git a/include/firmware/imx/sci/sci.h b/include/firmware/imx/sci/sci.h
index 7d8499f..588f367 100644
--- a/include/firmware/imx/sci/sci.h
+++ b/include/firmware/imx/sci/sci.h
@@ -123,6 +123,7 @@
 
 /* Timer API */
 int sc_timer_set_wdog_window(sc_ipc_t ipc, sc_timer_wdog_time_t window);
+int sc_timer_control_siemens_pmic_wdog(sc_ipc_t ipc, u8 cmd);
 
 /* SECO API */
 int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd,
diff --git a/include/fs.h b/include/fs.h
index 6372756..2474880 100644
--- a/include/fs.h
+++ b/include/fs.h
@@ -325,7 +325,7 @@
  *
  * @fname: Filename to read
  * @size: Size of file to read (must be correct!)
- * @align: Alignment to use for memory allocation (0 for default)
+ * @align: Alignment to use for memory allocation (0 for default: ARCH_DMA_MINALIGN)
  * @bufp: On success, returns the allocated buffer with the nul-terminated file
  *	in it
  * Return: 0 if OK, -ENOMEM if out of memory, -EIO if read failed
diff --git a/include/image.h b/include/image.h
index c52fced..9be5acd 100644
--- a/include/image.h
+++ b/include/image.h
@@ -1802,6 +1802,30 @@
 struct andr_image_data;
 
 /**
+ * android_image_get_bootimg_size() - Extract size of Android boot image
+ *
+ * This is used to extract the size of an Android boot image
+ * from boot image header.
+ *
+ * @hdr: Pointer to boot image header
+ * @boot_img_size: On exit returns the size in bytes of the boot image
+ * Return: true if succeeded, false otherwise
+ */
+bool android_image_get_bootimg_size(const void *hdr, u32 *boot_img_size);
+
+/**
+ * android_image_get_vendor_bootimg_size() - Extract size of Android vendor-boot image
+ *
+ * This is used to extract the size of an Android vendor-boot image
+ * from vendor-boot image header.
+ *
+ * @hdr: Pointer to vendor-boot image header
+ * @vendor_boot_img_size: On exit returns the size in bytes of the vendor-boot image
+ * Return: true if succeeded, false otherwise
+ */
+bool android_image_get_vendor_bootimg_size(const void *hdr, u32 *vendor_boot_img_size);
+
+/**
  * android_image_get_data() - Parse Android boot images
  *
  * This is used to parse boot and vendor-boot header into
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index 6751fb5..3ffcd40 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -339,7 +339,7 @@
 	dev_set_ofnode(mtd->dev, node);
 }
 
-static inline const ofnode mtd_get_ofnode(struct mtd_info *mtd)
+static inline ofnode mtd_get_ofnode(struct mtd_info *mtd)
 {
 	return dev_ofnode(mtd->dev);
 }
diff --git a/include/memtop.h b/include/memtop.h
new file mode 100644
index 0000000..28f62e2
--- /dev/null
+++ b/include/memtop.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2024, Linaro Limited
+ */
+
+/**
+ * get_mem_top() - Compute the value of ram_top
+ * @ram_start:	Start of RAM
+ * @ram_size:	RAM size
+ * @size:	Minimum RAM size requested
+ * @fdt:	FDT blob
+ *
+ * The function computes the top address of RAM memory that can be
+ * used by U-Boot. This is being done by going through the list of
+ * reserved memory regions specified in the devicetree blob passed
+ * to the function. The logic used here is derived from the lmb
+ * allocation function.
+ *
+ * Return: address of ram top on success, 0 on failure
+ */
+phys_addr_t get_mem_top(phys_addr_t ram_start, phys_size_t ram_size,
+			phys_size_t size, void *fdt);
diff --git a/include/net-common.h b/include/net-common.h
index b7a519e..c5e314b 100644
--- a/include/net-common.h
+++ b/include/net-common.h
@@ -69,7 +69,7 @@
 	u16		udp_dst;	/* UDP destination port		*/
 	u16		udp_len;	/* Length of UDP packet		*/
 	u16		udp_xsum;	/* Checksum			*/
-} __attribute__((packed));
+} __packed;
 
 #define IP_UDP_HDR_SIZE		(sizeof(struct ip_udp_hdr))
 #define UDP_HDR_SIZE		(IP_UDP_HDR_SIZE - IP_HDR_SIZE)
@@ -85,13 +85,13 @@
  */
 #define ARP_HLEN_ASCII (ARP_HLEN * 2) + (ARP_HLEN - 1)
 
-#define ARP_HDR_SIZE	(8+20)		/* Size assuming ethernet	*/
+#define ARP_HDR_SIZE	(8 + 20)	/* Size assuming ethernet	*/
 
 #   define ARP_ETHER	    1		/* Ethernet  hardware address	*/
 
 /*
  * Maximum packet size; used to allocate packet storage. Use
- * the maxium Ethernet frame size as specified by the Ethernet
+ * the maximum Ethernet frame size as specified by the Ethernet
  * standard including the 802.1Q tag (VLAN tagging).
  * maximum packet size =  1522
  * maximum packet size and multiple of 32 bytes =  1536
@@ -130,7 +130,7 @@
  * @nbytes:	Number of bytes to check (normally a multiple of 2)
  * Return: 16-bit IP checksum
  */
-unsigned compute_ip_checksum(const void *addr, unsigned nbytes);
+unsigned compute_ip_checksum(const void *addr, unsigned int nbytes);
 
 /**
  * ip_checksum_ok() - check if a checksum is correct
@@ -141,7 +141,7 @@
  * @nbytes:	Number of bytes to check (normally a multiple of 2)
  * Return: true if the checksum matches, false if not
  */
-int ip_checksum_ok(const void *addr, unsigned nbytes);
+int ip_checksum_ok(const void *addr, unsigned int nbytes);
 
 /**
  * add_ip_checksums() - add two IP checksums
@@ -151,7 +151,7 @@
  * @new_sum:	New checksum to add
  * Return: updated 16-bit IP checksum
  */
-unsigned add_ip_checksums(unsigned offset, unsigned sum, unsigned new_sum);
+unsigned add_ip_checksums(unsigned offset, unsigned sum, unsigned int new_sum);
 
 /*
  * The devname can be either an exact name given by the driver or device tree
@@ -186,7 +186,7 @@
  * Return: 0 if OK, other value on error
  */
 int eth_env_set_enetaddr_by_index(const char *base_name, int index,
-				 uchar *enetaddr);
+				  uchar *enetaddr);
 
 /*
  * Initialize USB ethernet device with CONFIG_DM_ETH
@@ -232,7 +232,7 @@
 	if (DEBUG_NET_PKT_TRACE)
 		print_hex_dump_bytes("tx: ", DUMP_PREFIX_OFFSET, pkt, len);
 	/* Currently no way to return errors from eth_send() */
-	(void) eth_send(pkt, len);
+	(void)eth_send(pkt, len);
 }
 
 enum eth_recv_flags {
@@ -328,7 +328,7 @@
 	u8		et_dest[ARP_HLEN];	/* Destination node	*/
 	u8		et_src[ARP_HLEN];	/* Source node		*/
 	u16		et_protlen;		/* Protocol or length	*/
-} __attribute__((packed));
+} __packed;
 
 /* Ethernet header size */
 #define ETHER_HDR_SIZE	(sizeof(struct ethernet_hdr))
@@ -456,10 +456,10 @@
 int update_tftp(ulong addr, char *interface, char *devstring);
 
 /**
- * env_get_ip() - Convert an environment value to to an ip address
+ * env_get_ip() - Convert an environment value to an ip address
  *
  * @var: Environment variable to convert. The value of this variable must be
- *	in the format format a.b.c.d, where each value is a decimal number from
+ *	in the format a.b.c.d, where each value is a decimal number from
  *	0 to 255
  * Return: IP address, or 0 if invalid
  */
diff --git a/include/net-legacy.h b/include/net-legacy.h
index ca1efd1..1f62ebf 100644
--- a/include/net-legacy.h
+++ b/include/net-legacy.h
@@ -43,9 +43,9 @@
  * @param sport  source UDP port
  * @param len    packet length
  */
-typedef void rxhand_f(uchar *pkt, unsigned dport,
-		      struct in_addr sip, unsigned sport,
-		      unsigned len);
+typedef void rxhand_f(uchar *pkt, unsigned int dport,
+		      struct in_addr sip, unsigned int sport,
+		      unsigned int len);
 
 /**
  * An incoming ICMP packet handler.
@@ -57,8 +57,9 @@
  * @param pkt	pointer to the ICMP packet data
  * @param len	packet length
  */
-typedef void rxhand_icmp_f(unsigned type, unsigned code, unsigned dport,
-		struct in_addr sip, unsigned sport, uchar *pkt, unsigned len);
+typedef void rxhand_icmp_f(unsigned type, unsigned int code, unsigned int dport,
+			   struct in_addr sip, unsigned int sport, uchar *pkt,
+			   unsigned int len);
 
 /*
  *	A timeout handler.  Called after time interval has expired.
@@ -87,7 +88,7 @@
  * Return: 0 if OK, other value on error
  */
 int eth_env_set_enetaddr_by_index(const char *base_name, int index,
-				 uchar *enetaddr);
+				  uchar *enetaddr);
 
 /*
  * Get the hardware address for an ethernet interface .
@@ -99,7 +100,7 @@
  *	Return true if the address is valid.
  */
 int eth_env_get_enetaddr_by_index(const char *base_name, int index,
-				 uchar *enetaddr);
+				  uchar *enetaddr);
 
 int eth_send(void *packet, int length);	   /* Send a packet */
 
@@ -127,7 +128,7 @@
 	u8		et_snap2;
 	u8		et_snap3;
 	u16		et_prot;		/* 802 protocol		*/
-} __attribute__((packed));
+} __packed;
 
 /* 802 + SNAP + ethernet header size */
 #define E802_HDR_SIZE	(sizeof(struct e802_hdr))
@@ -141,7 +142,7 @@
 	u16		vet_vlan_type;		/* PROT_VLAN		*/
 	u16		vet_tag;		/* TAG of VLAN		*/
 	u16		vet_type;		/* protocol type	*/
-} __attribute__((packed));
+} __packed;
 
 /* VLAN Ethernet header size */
 #define VLAN_ETHER_HDR_SIZE	(sizeof(struct vlan_ethernet_hdr))
@@ -160,7 +161,7 @@
 	u16		ip_sum;		/* checksum			*/
 	struct in_addr	ip_src;		/* Source IP address		*/
 	struct in_addr	ip_dst;		/* Destination IP address	*/
-} __attribute__((packed));
+} __packed;
 
 #define IP_OFFS		0x1fff /* ip offset *= 8 */
 #define IP_FLAGS	0xe000 /* first 3 bits */
@@ -205,8 +206,7 @@
 	u8		ar_tha[];	/* Target hardware address	*/
 	u8		ar_tpa[];	/* Target protocol address	*/
 #endif /* 0 */
-} __attribute__((packed));
-
+} __packed;
 
 /*
  * ICMP stuff (just enough to handle (host) redirect messages)
@@ -239,14 +239,14 @@
 		} frag;
 		u8 data[0];
 	} un;
-} __attribute__((packed));
+} __packed;
 
 #define ICMP_HDR_SIZE		(sizeof(struct icmp_hdr))
 #define IP_ICMP_HDR_SIZE	(IP_HDR_SIZE + ICMP_HDR_SIZE)
 
 /*
  * Maximum packet size; used to allocate packet storage. Use
- * the maxium Ethernet frame size as specified by the Ethernet
+ * the maximum Ethernet frame size as specified by the Ethernet
  * standard including the 802.1Q tag (VLAN tagging).
  * maximum packet size =  1522
  * maximum packet size and multiple of 32 bytes =  1536
@@ -307,6 +307,7 @@
 	NETCONS, SNTP, TFTPSRV, TFTPPUT, LINKLOCAL, FASTBOOT_UDP, FASTBOOT_TCP,
 	WOL, UDP, NCSI, WGET, RS
 };
+
 /* Indicates whether the file name was specified on the command line */
 extern bool	net_boot_file_name_explicit;
 /* The actual transferred size of the bootfile (in bytes) */
@@ -360,16 +361,16 @@
 void net_set_ip_header(uchar *pkt, struct in_addr dest, struct in_addr source,
 		       u16 pkt_len, u8 proto);
 void net_set_udp_header(uchar *pkt, struct in_addr dest, int dport,
-				int sport, int len);
+			int sport, int len);
 
 /* Callbacks */
 rxhand_f *net_get_udp_handler(void);	/* Get UDP RX packet handler */
-void net_set_udp_handler(rxhand_f *);	/* Set UDP RX packet handler */
+void net_set_udp_handler(rxhand_f *f);	/* Set UDP RX packet handler */
 rxhand_f *net_get_arp_handler(void);	/* Get ARP RX packet handler */
-void net_set_arp_handler(rxhand_f *);	/* Set ARP RX packet handler */
+void net_set_arp_handler(rxhand_f *f);	/* Set ARP RX packet handler */
 bool arp_is_waiting(void);		/* Waiting for ARP reply? */
 void net_set_icmp_handler(rxhand_icmp_f *f); /* Set ICMP RX handler */
-void net_set_timeout_handler(ulong, thand_f *);/* Set timeout handler */
+void net_set_timeout_handler(ulong t, thand_f *f);/* Set timeout handler */
 
 /* Network loop state */
 enum net_loop_state {
@@ -378,6 +379,7 @@
 	NETLOOP_SUCCESS,
 	NETLOOP_FAIL
 };
+
 extern enum net_loop_state net_state;
 
 static inline void net_set_state(enum net_loop_state state)
@@ -429,8 +431,8 @@
 
 #if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_XPL_BUILD)
 void nc_start(void);
-int nc_input_packet(uchar *pkt, struct in_addr src_ip, unsigned dest_port,
-	unsigned src_port, unsigned len);
+int nc_input_packet(uchar *pkt, struct in_addr src_ip, unsigned int dest_port,
+		    unsigned int src_port, unsigned int len);
 #endif
 
 static __always_inline int eth_is_on_demand_init(void)
@@ -522,7 +524,7 @@
 ushort string_to_vlan(const char *s);
 
 /* read a VLAN id from an environment variable */
-ushort env_get_vlan(char *);
+ushort env_get_vlan(char *var);
 
 /* check if serverip is specified in filename from the command line */
 int is_serverip_in_cmd(void);
diff --git a/include/netdev.h b/include/netdev.h
index 2a06d9a..949245e 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -117,7 +117,7 @@
 	return num;
 }
 
-struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id);
+struct mii_dev *fec_get_miibus(struct udevice *dev, ulong base_addr, int dev_id);
 
 #ifdef CONFIG_PHYLIB
 struct phy_device;
diff --git a/include/part.h b/include/part.h
index 9266267..fcb3c13 100644
--- a/include/part.h
+++ b/include/part.h
@@ -74,6 +74,7 @@
 	 * PART_EFI_SYSTEM_PARTITION	the partition is an EFI system partition
 	 */
 	int	bootable;
+	u16	type_flags;	/* top 16 bits of GPT partition attributes	*/
 #if CONFIG_IS_ENABLED(PARTITION_UUIDS)
 	char	uuid[UUID_STR_LEN + 1];	/* filesystem UUID as string, if exists	*/
 #endif
diff --git a/include/test/compression.h b/include/test/compression.h
deleted file mode 100644
index 02fcfa4..0000000
--- a/include/test/compression.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2017 Google, Inc
- * Written by Simon Glass <sjg@chromium.org>
- */
-
-#ifndef __TEST_COMPRESSION_H__
-#define __TEST_COMPRESSION_H__
-
-#include <test/test.h>
-
-/* Declare a new compression test */
-#define COMPRESSION_TEST(_name, _flags) \
-		UNIT_TEST(_name, _flags, compression_test)
-
-#endif /* __TEST_ENV_H__ */
diff --git a/include/vsprintf.h b/include/vsprintf.h
index fe95147..9da6ce7 100644
--- a/include/vsprintf.h
+++ b/include/vsprintf.h
@@ -45,6 +45,19 @@
 unsigned long hextoul(const char *cp, char **endp);
 
 /**
+ * hex_strtoull - convert a string in hex to an unsigned long long
+ *
+ * @cp: The string to be converted
+ * @endp: Updated to point to the first character not converted
+ * Return: value decoded from string (0 if invalid)
+ *
+ * Converts a hex string to an unsigned long long. If there are invalid
+ * characters at the end these are ignored. In the worst case, if all characters
+ * are invalid, 0 is returned
+ */
+unsigned long long hextoull(const char *cp, char **endp);
+
+/**
  * dec_strtoul - convert a string in decimal to an unsigned long
  *
  * @cp: The string to be converted
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index 58d4978..d93f28b 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -481,7 +481,6 @@
 menu "Misc options"
 config EFI_LOADER_BOUNCE_BUFFER
 	bool "EFI Applications use bounce buffers for DMA operations"
-	depends on ARM64
 	help
 	  Some hardware does not support DMA to full 64bit addresses. For this
 	  hardware we can create a bounce buffer so that payloads don't have to
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index 4f52284..080e7f7 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -2234,7 +2234,7 @@
 		if (IS_ENABLED(CONFIG_USB_DEVICE))
 			udc_disconnect();
 		board_quiesce_devices();
-		dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL);
+		dm_remove_devices_active();
 	}
 
 	/* Patch out unsupported runtime function */
diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
index d2f5d56..e493934 100644
--- a/lib/efi_loader/efi_memory.c
+++ b/lib/efi_loader/efi_memory.c
@@ -451,7 +451,7 @@
 				enum efi_memory_type memory_type,
 				efi_uintn_t pages, uint64_t *memory)
 {
-	u64 len;
+	u64 efi_addr, len;
 	uint flags;
 	efi_status_t ret;
 	phys_addr_t addr;
@@ -499,14 +499,17 @@
 		return EFI_INVALID_PARAMETER;
 	}
 
-	addr = (u64)(uintptr_t)map_sysmem(addr, 0);
+	efi_addr = (u64)(uintptr_t)map_sysmem(addr, 0);
 	/* Reserve that map in our memory maps */
-	ret = efi_add_memory_map_pg(addr, pages, memory_type, true);
-	if (ret != EFI_SUCCESS)
+	ret = efi_add_memory_map_pg(efi_addr, pages, memory_type, true);
+	if (ret != EFI_SUCCESS) {
 		/* Map would overlap, bail out */
+		lmb_free_flags(addr, (u64)pages << EFI_PAGE_SHIFT, flags);
+		unmap_sysmem((void *)(uintptr_t)efi_addr);
 		return  EFI_OUT_OF_RESOURCES;
+	}
 
-	*memory = addr;
+	*memory = efi_addr;
 
 	return EFI_SUCCESS;
 }
@@ -546,6 +549,8 @@
 	if (status)
 		return EFI_NOT_FOUND;
 
+	unmap_sysmem((void *)(uintptr_t)memory);
+
 	return ret;
 }
 
diff --git a/lib/efi_loader/efi_tcg2.c b/lib/efi_loader/efi_tcg2.c
index 866a529..572c6b5 100644
--- a/lib/efi_loader/efi_tcg2.c
+++ b/lib/efi_loader/efi_tcg2.c
@@ -607,12 +607,9 @@
 	 * Format"
 	 */
 	if (flags & PE_COFF_IMAGE) {
-		IMAGE_NT_HEADERS32 *nt;
-
 		ret = efi_check_pe((void *)(uintptr_t)data_to_hash,
-				   data_to_hash_len, (void **)&nt);
+				   data_to_hash_len, NULL);
 		if (ret != EFI_SUCCESS) {
-			log_err("Not a valid PE-COFF file\n");
 			ret = EFI_UNSUPPORTED;
 			goto out;
 		}
diff --git a/lib/lmb.c b/lib/lmb.c
index 74ffa9f..14b9b84 100644
--- a/lib/lmb.c
+++ b/lib/lmb.c
@@ -481,16 +481,22 @@
 
 static void lmb_print_region_flags(enum lmb_flags flags)
 {
-	u64 bitpos;
 	const char *flag_str[] = { "none", "no-map", "no-overwrite", "no-notify" };
+	unsigned int pflags = flags &
+			      (LMB_NOMAP | LMB_NOOVERWRITE | LMB_NONOTIFY);
+
+	if (flags != pflags) {
+		printf("invalid %#x\n", flags);
+		return;
+	}
 
 	do {
-		bitpos = flags ? fls(flags) - 1 : 0;
-		assert_noisy(bitpos < ARRAY_SIZE(flag_str));
+		int bitpos = pflags ? fls(pflags) - 1 : 0;
+
 		printf("%s", flag_str[bitpos]);
-		flags &= ~(1ull << bitpos);
-		puts(flags ? ", " : "\n");
-	} while (flags);
+		pflags &= ~(1u << bitpos);
+		puts(pflags ? ", " : "\n");
+	} while (pflags);
 }
 
 static void lmb_dump_region(struct alist *lmb_rgn_lst, char *name)
@@ -500,7 +506,7 @@
 	enum lmb_flags flags;
 	int i;
 
-	printf(" %s.count = 0x%x\n", name, lmb_rgn_lst->count);
+	printf(" %s.count = %#x\n", name, lmb_rgn_lst->count);
 
 	for (i = 0; i < lmb_rgn_lst->count; i++) {
 		base = rgn[i].base;
@@ -508,7 +514,7 @@
 		end = base + size - 1;
 		flags = rgn[i].flags;
 
-		printf(" %s[%d]\t[0x%llx-0x%llx], 0x%08llx bytes flags: ",
+		printf(" %s[%d]\t[%#llx-%#llx], %#llx bytes, flags: ",
 		       name, i, base, end, size);
 		lmb_print_region_flags(flags);
 	}
diff --git a/lib/lwip/Makefile b/lib/lwip/Makefile
index dfcd700..19e5c68 100644
--- a/lib/lwip/Makefile
+++ b/lib/lwip/Makefile
@@ -53,3 +53,6 @@
 	lwip/src/core/timeouts.o \
 	lwip/src/core/udp.o \
 	lwip/src/netif/ethernet.o
+
+obj-$(CONFIG_MBEDTLS_LIB_TLS) += lwip/src/apps/altcp_tls/altcp_tls_mbedtls.o \
+	lwip/src/apps/altcp_tls/altcp_tls_mbedtls_mem.o
diff --git a/lib/lwip/lwip/src/apps/altcp_tls/altcp_tls_mbedtls.c b/lib/lwip/lwip/src/apps/altcp_tls/altcp_tls_mbedtls.c
index a8c2fc2..6643b05 100644
--- a/lib/lwip/lwip/src/apps/altcp_tls/altcp_tls_mbedtls.c
+++ b/lib/lwip/lwip/src/apps/altcp_tls/altcp_tls_mbedtls.c
@@ -70,7 +70,6 @@
 /* @todo: which includes are really needed? */
 #include "mbedtls/entropy.h"
 #include "mbedtls/ctr_drbg.h"
-#include "mbedtls/certs.h"
 #include "mbedtls/x509.h"
 #include "mbedtls/ssl.h"
 #include "mbedtls/net_sockets.h"
@@ -81,8 +80,6 @@
 #include "mbedtls/ssl_cache.h"
 #include "mbedtls/ssl_ticket.h"
 
-#include "mbedtls/ssl_internal.h" /* to call mbedtls_flush_output after ERR_MEM */
-
 #include <string.h>
 
 #ifndef ALTCP_MBEDTLS_ENTROPY_PTR
@@ -109,6 +106,7 @@
   u8_t pkey_count;
   u8_t pkey_max;
   mbedtls_x509_crt *ca;
+  char host[256];
 #if defined(MBEDTLS_SSL_CACHE_C) && ALTCP_MBEDTLS_USE_SESSION_CACHE
   /** Inter-connection cache for fast connection startup */
   struct mbedtls_ssl_cache_context cache;
@@ -132,6 +130,16 @@
 static err_t altcp_mbedtls_handle_rx_appldata(struct altcp_pcb *conn, altcp_mbedtls_state_t *state);
 static int altcp_mbedtls_bio_send(void *ctx, const unsigned char *dataptr, size_t size);
 
+static void
+altcp_mbedtls_flush_output(altcp_mbedtls_state_t *state)
+{
+  if (state->ssl_context.MBEDTLS_PRIVATE(out_left) != 0) {
+    int flushed = mbedtls_ssl_send_alert_message(&state->ssl_context, 0, 0);
+    if (flushed) {
+      LWIP_DEBUGF(ALTCP_MBEDTLS_DEBUG, ("mbedtls_ssl_send_alert_message failed: %d\n", flushed));
+    }
+  }
+}
 
 /* callback functions from inner/lower connection: */
 
@@ -524,14 +532,14 @@
     LWIP_ASSERT("state", state != NULL);
     LWIP_ASSERT("pcb mismatch", conn->inner_conn == inner_conn);
     /* calculate TLS overhead part to not send it to application */
-    overhead = state->overhead_bytes_adjust + state->ssl_context.out_left;
+    overhead = state->overhead_bytes_adjust + state->ssl_context.MBEDTLS_PRIVATE(out_left);
     if ((unsigned)overhead > len) {
       overhead = len;
     }
     /* remove ACKed bytes from overhead adjust counter */
     state->overhead_bytes_adjust -= len;
     /* try to send more if we failed before (may increase overhead adjust counter) */
-    mbedtls_ssl_flush_output(&state->ssl_context);
+    altcp_mbedtls_flush_output(state);
     /* remove calculated overhead from ACKed bytes len */
     app_len = len - (u16_t)overhead;
     /* update application write counter and inform application */
@@ -559,7 +567,7 @@
     if (conn->state) {
       altcp_mbedtls_state_t *state = (altcp_mbedtls_state_t *)conn->state;
       /* try to send more if we failed before */
-      mbedtls_ssl_flush_output(&state->ssl_context);
+      altcp_mbedtls_flush_output(state);
       if (altcp_mbedtls_handle_rx_appldata(conn, state) == ERR_ABRT) {
         return ERR_ABRT;
       }
@@ -635,6 +643,7 @@
   /* tell mbedtls about our I/O functions */
   mbedtls_ssl_set_bio(&state->ssl_context, conn, altcp_mbedtls_bio_send, altcp_mbedtls_bio_recv, NULL);
 
+  mbedtls_ssl_set_hostname(&state->ssl_context, config->host);
   altcp_mbedtls_setup_callbacks(conn, inner_conn);
   conn->inner_conn = inner_conn;
   conn->fns = &altcp_mbedtls_functions;
@@ -683,7 +692,7 @@
   if (session && conn && conn->state) {
     altcp_mbedtls_state_t *state = (altcp_mbedtls_state_t *)conn->state;
     int ret = -1;
-    if (session->data.start)
+    if (session->data.MBEDTLS_PRIVATE(start))
       ret = mbedtls_ssl_set_session(&state->ssl_context, &session->data);
     return ret < 0 ? ERR_VAL : ERR_OK;
   }
@@ -776,7 +785,7 @@
   struct altcp_tls_config *conf;
   mbedtls_x509_crt *mem;
 
-  if (TCP_WND < MBEDTLS_SSL_MAX_CONTENT_LEN) {
+  if (TCP_WND < MBEDTLS_SSL_IN_CONTENT_LEN || TCP_WND < MBEDTLS_SSL_OUT_CONTENT_LEN) {
     LWIP_DEBUGF(ALTCP_MBEDTLS_DEBUG|LWIP_DBG_LEVEL_SERIOUS,
       ("altcp_tls: TCP_WND is smaller than the RX decrypion buffer, connection RX might stall!\n"));
   }
@@ -900,7 +909,7 @@
     return ERR_VAL;
   }
 
-  ret = mbedtls_pk_parse_key(pkey, (const unsigned char *) privkey, privkey_len, privkey_pass, privkey_pass_len);
+  ret = mbedtls_pk_parse_key(pkey, (const unsigned char *) privkey, privkey_len, privkey_pass, privkey_pass_len, mbedtls_ctr_drbg_random, &altcp_tls_entropy_rng->ctr_drbg);
   if (ret != 0) {
     LWIP_DEBUGF(ALTCP_MBEDTLS_DEBUG, ("mbedtls_pk_parse_public_key failed: %d\n", ret));
     mbedtls_x509_crt_free(srvcert);
@@ -944,7 +953,7 @@
 }
 
 static struct altcp_tls_config *
-altcp_tls_create_config_client_common(const u8_t *ca, size_t ca_len, int is_2wayauth)
+altcp_tls_create_config_client_common(const u8_t *ca, size_t ca_len, int is_2wayauth, char *host)
 {
   int ret;
   struct altcp_tls_config *conf = altcp_tls_create_config(0, (is_2wayauth) ? 1 : 0, (is_2wayauth) ? 1 : 0, ca != NULL);
@@ -966,13 +975,15 @@
 
     mbedtls_ssl_conf_ca_chain(&conf->conf, conf->ca, NULL);
   }
+  strlcpy(conf->host, host, sizeof(conf->host));
+
   return conf;
 }
 
 struct altcp_tls_config *
-altcp_tls_create_config_client(const u8_t *ca, size_t ca_len)
+altcp_tls_create_config_client(const u8_t *ca, size_t ca_len, char *host)
 {
-  return altcp_tls_create_config_client_common(ca, ca_len, 0);
+  return altcp_tls_create_config_client_common(ca, ca_len, 0, host);
 }
 
 struct altcp_tls_config *
@@ -988,7 +999,7 @@
     return NULL;
   }
 
-  conf = altcp_tls_create_config_client_common(ca, ca_len, 1);
+  conf = altcp_tls_create_config_client_common(ca, ca_len, 1, NULL);
   if (conf == NULL) {
     return NULL;
   }
@@ -1003,7 +1014,7 @@
   }
 
   mbedtls_pk_init(conf->pkey);
-  ret = mbedtls_pk_parse_key(conf->pkey, privkey, privkey_len, privkey_pass, privkey_pass_len);
+  ret = mbedtls_pk_parse_key(conf->pkey, privkey, privkey_len, privkey_pass, privkey_pass_len, mbedtls_ctr_drbg_random, &altcp_tls_entropy_rng->ctr_drbg);
   if (ret != 0) {
     LWIP_DEBUGF(ALTCP_MBEDTLS_DEBUG, ("mbedtls_pk_parse_key failed: %d 0x%x\n", ret, -1*ret));
     altcp_tls_free_config(conf);
@@ -1189,7 +1200,7 @@
           size_t ret;
 #if defined(MBEDTLS_SSL_MAX_FRAGMENT_LENGTH)
           /* @todo: adjust ssl_added to real value related to negotiated cipher */
-          size_t max_frag_len = mbedtls_ssl_get_max_frag_len(&state->ssl_context);
+          size_t max_frag_len = mbedtls_ssl_get_max_in_record_payload(&state->ssl_context);
           max_len = LWIP_MIN(max_frag_len, max_len);
 #endif
           /* Adjust sndbuf of inner_conn with what added by SSL */
@@ -1232,9 +1243,9 @@
   /* HACK: if there is something left to send, try to flush it and only
      allow sending more if this succeeded (this is a hack because neither
      returning 0 nor MBEDTLS_ERR_SSL_WANT_WRITE worked for me) */
-  if (state->ssl_context.out_left) {
-    mbedtls_ssl_flush_output(&state->ssl_context);
-    if (state->ssl_context.out_left) {
+  if (state->ssl_context.MBEDTLS_PRIVATE(out_left)) {
+    altcp_mbedtls_flush_output(state);
+    if (state->ssl_context.MBEDTLS_PRIVATE(out_left)) {
       return ERR_MEM;
     }
   }
@@ -1284,6 +1295,8 @@
   while (size_left) {
     u16_t write_len = (u16_t)LWIP_MIN(size_left, 0xFFFF);
     err_t err = altcp_write(conn->inner_conn, (const void *)dataptr, write_len, apiflags);
+    /* try to send data... */
+    altcp_output(conn->inner_conn);
     if (err == ERR_OK) {
       written += write_len;
       size_left -= write_len;
diff --git a/lib/lwip/lwip/src/core/tcp_out.c b/lib/lwip/lwip/src/core/tcp_out.c
index 64579ee5..6dbc5f9 100644
--- a/lib/lwip/lwip/src/core/tcp_out.c
+++ b/lib/lwip/lwip/src/core/tcp_out.c
@@ -1255,14 +1255,6 @@
   LWIP_ASSERT("don't call tcp_output for listen-pcbs",
               pcb->state != LISTEN);
 
-  /* First, check if we are invoked by the TCP input processing
-     code. If so, we do not output anything. Instead, we rely on the
-     input processing code to call us when input processing is done
-     with. */
-  if (tcp_input_pcb == pcb) {
-    return ERR_OK;
-  }
-
   wnd = LWIP_MIN(pcb->snd_wnd, pcb->cwnd);
 
   seg = pcb->unsent;
diff --git a/lib/lwip/lwip/src/include/lwip/altcp_tls.h b/lib/lwip/lwip/src/include/lwip/altcp_tls.h
index fcb784d..fb06182 100644
--- a/lib/lwip/lwip/src/include/lwip/altcp_tls.h
+++ b/lib/lwip/lwip/src/include/lwip/altcp_tls.h
@@ -92,7 +92,7 @@
 /** @ingroup altcp_tls
  * Create an ALTCP_TLS client configuration handle
  */
-struct altcp_tls_config *altcp_tls_create_config_client(const u8_t *cert, size_t cert_len);
+struct altcp_tls_config *altcp_tls_create_config_client(const u8_t *cert, size_t cert_len, char *host);
 
 /** @ingroup altcp_tls
  * Create an ALTCP_TLS client configuration handle with two-way server/client authentication
diff --git a/lib/lwip/u-boot/arch/cc.h b/lib/lwip/u-boot/arch/cc.h
index 563d3bf..de13884 100644
--- a/lib/lwip/u-boot/arch/cc.h
+++ b/lib/lwip/u-boot/arch/cc.h
@@ -29,8 +29,9 @@
 
 #define LWIP_DONT_PROVIDE_BYTEORDER_FUNCTIONS
 
-#define LWIP_PLATFORM_ASSERT(x) do {printf("Assertion \"%s\" failed at line %d in %s\n", \
-				    x, __LINE__, __FILE__); } while (0)
+#define LWIP_PLATFORM_ASSERT(x) do { \
+	printf("Assertion \"%s\" failed at line %d in %s\n", \
+	       x, __LINE__, __FILE__); } while (0)
 
 #define atoi(str) (int)dectoul(str, NULL)
 #define lwip_strnstr(a, b, c)  strstr(a, b)
diff --git a/lib/lwip/u-boot/lwipopts.h b/lib/lwip/u-boot/lwipopts.h
index 9d61862..88d6faf 100644
--- a/lib/lwip/u-boot/lwipopts.h
+++ b/lib/lwip/u-boot/lwipopts.h
@@ -154,4 +154,10 @@
 #define MEMP_MEM_INIT			1
 #define MEM_LIBC_MALLOC			1
 
+#if defined(CONFIG_MBEDTLS_LIB_TLS)
+#define LWIP_ALTCP                      1
+#define LWIP_ALTCP_TLS                  1
+#define LWIP_ALTCP_TLS_MBEDTLS          1
+#endif
+
 #endif /* LWIP_UBOOT_LWIPOPTS_H */
diff --git a/lib/mbedtls/Kconfig b/lib/mbedtls/Kconfig
index d71adc3..78167ff 100644
--- a/lib/mbedtls/Kconfig
+++ b/lib/mbedtls/Kconfig
@@ -430,4 +430,16 @@
 
 endif # MBEDTLS_LIB_X509
 
+config MBEDTLS_LIB_TLS
+	bool "MbedTLS TLS library"
+	depends on RSA_PUBLIC_KEY_PARSER_MBEDTLS
+	depends on X509_CERTIFICATE_PARSER_MBEDTLS
+	depends on ASYMMETRIC_PUBLIC_KEY_MBEDTLS
+	depends on ASN1_DECODER_MBEDTLS
+	depends on ASYMMETRIC_PUBLIC_KEY_MBEDTLS
+	depends on MBEDTLS_LIB_CRYPTO
+	help
+	  Enable MbedTLS TLS library. Required for HTTPs support
+	  in wget
+
 endif # MBEDTLS_LIB
diff --git a/lib/mbedtls/Makefile b/lib/mbedtls/Makefile
index 83cb3c2..ce0a61e 100644
--- a/lib/mbedtls/Makefile
+++ b/lib/mbedtls/Makefile
@@ -26,6 +26,7 @@
 	$(MBEDTLS_LIB_DIR)/platform_util.o \
 	$(MBEDTLS_LIB_DIR)/constant_time.o \
 	$(MBEDTLS_LIB_DIR)/md.o
+
 mbedtls_lib_crypto-$(CONFIG_$(SPL_)MD5_MBEDTLS) += $(MBEDTLS_LIB_DIR)/md5.o
 mbedtls_lib_crypto-$(CONFIG_$(SPL_)SHA1_MBEDTLS) += $(MBEDTLS_LIB_DIR)/sha1.o
 mbedtls_lib_crypto-$(CONFIG_$(SPL_)SHA256_MBEDTLS) += \
@@ -54,3 +55,33 @@
 	$(MBEDTLS_LIB_DIR)/x509_crt.o
 mbedtls_lib_x509-$(CONFIG_$(SPL_)PKCS7_MESSAGE_PARSER_MBEDTLS) += \
 	$(MBEDTLS_LIB_DIR)/pkcs7.o
+
+#mbedTLS TLS support
+obj-$(CONFIG_MBEDTLS_LIB_TLS) += mbedtls_lib_tls.o
+mbedtls_lib_tls-y := \
+	$(MBEDTLS_LIB_DIR)/mps_reader.o \
+	$(MBEDTLS_LIB_DIR)/mps_trace.o \
+	$(MBEDTLS_LIB_DIR)/net_sockets.o \
+	$(MBEDTLS_LIB_DIR)/pk_ecc.o \
+	$(MBEDTLS_LIB_DIR)/ssl_cache.o \
+	$(MBEDTLS_LIB_DIR)/ssl_ciphersuites.o \
+	$(MBEDTLS_LIB_DIR)/ssl_client.o \
+	$(MBEDTLS_LIB_DIR)/ssl_cookie.o \
+	$(MBEDTLS_LIB_DIR)/ssl_debug_helpers_generated.o \
+	$(MBEDTLS_LIB_DIR)/ssl_msg.o \
+	$(MBEDTLS_LIB_DIR)/ssl_ticket.o \
+	$(MBEDTLS_LIB_DIR)/ssl_tls.o \
+	$(MBEDTLS_LIB_DIR)/ssl_tls12_client.o \
+	$(MBEDTLS_LIB_DIR)/hmac_drbg.o \
+	$(MBEDTLS_LIB_DIR)/ctr_drbg.o \
+	$(MBEDTLS_LIB_DIR)/entropy.o \
+	$(MBEDTLS_LIB_DIR)/entropy_poll.o \
+	$(MBEDTLS_LIB_DIR)/aes.o \
+	$(MBEDTLS_LIB_DIR)/cipher.o \
+	$(MBEDTLS_LIB_DIR)/cipher_wrap.o \
+	$(MBEDTLS_LIB_DIR)/ecdh.o \
+	$(MBEDTLS_LIB_DIR)/ecdsa.o \
+	$(MBEDTLS_LIB_DIR)/ecp.o \
+	$(MBEDTLS_LIB_DIR)/ecp_curves.o \
+	$(MBEDTLS_LIB_DIR)/ecp_curves_new.o \
+	$(MBEDTLS_LIB_DIR)/gcm.o \
diff --git a/lib/mbedtls/mbedtls_def_config.h b/lib/mbedtls/mbedtls_def_config.h
index 1af911c..d27f017 100644
--- a/lib/mbedtls/mbedtls_def_config.h
+++ b/lib/mbedtls/mbedtls_def_config.h
@@ -87,4 +87,56 @@
 
 #endif /* #if defined CONFIG_MBEDTLS_LIB_X509 */
 
+#if IS_ENABLED(CONFIG_MBEDTLS_LIB_TLS)
+#include "rtc.h"
+
+/* Generic options */
+#define MBEDTLS_ENTROPY_HARDWARE_ALT
+#define MBEDTLS_HAVE_TIME
+#define MBEDTLS_PLATFORM_MS_TIME_ALT
+#define MBEDTLS_PLATFORM_TIME_MACRO rtc_mktime
+#define MBEDTLS_PLATFORM_C
+#define MBEDTLS_SSL_CLI_C
+#define MBEDTLS_SSL_TLS_C
+#define MBEDTLS_CIPHER_C
+#define MBEDTLS_MD_C
+#define MBEDTLS_CTR_DRBG_C
+#define MBEDTLS_AES_C
+#define MBEDTLS_ENTROPY_C
+#define MBEDTLS_NO_PLATFORM_ENTROPY
+#define MBEDTLS_SSL_PROTO_TLS1_2
+#define MBEDTLS_SSL_SERVER_NAME_INDICATION
+#define MBEDTLS_KEY_EXCHANGE_PSK_ENABLED
+
+/* RSA */
+#define MBEDTLS_KEY_EXCHANGE_RSA_ENABLED
+#define MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED
+#define MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED
+#define MBEDTLS_GCM_C
+
+/* ECDSA */
+#define MBEDTLS_ECDSA_C
+#define MBEDTLS_ECDH_C
+#define MBEDTLS_ECDSA_DETERMINISTIC
+#define MBEDTLS_HMAC_DRBG_C
+#define MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED
+#define MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED
+#define MBEDTLS_CAN_ECDH
+#define MBEDTLS_PK_CAN_ECDSA_SIGN
+#define MBEDTLS_ECP_C
+#define MBEDTLS_ECP_DP_SECP256K1_ENABLED
+#define MBEDTLS_ECP_DP_SECP192R1_ENABLED
+#define MBEDTLS_ECP_DP_SECP224R1_ENABLED
+#define MBEDTLS_ECP_DP_SECP256R1_ENABLED
+#define MBEDTLS_ECP_DP_SECP384R1_ENABLED
+#define MBEDTLS_ECP_DP_SECP521R1_ENABLED
+#define MBEDTLS_ECP_DP_SECP192K1_ENABLED
+#define MBEDTLS_ECP_DP_SECP224K1_ENABLED
+#define MBEDTLS_ECP_DP_SECP256K1_ENABLED
+#define MBEDTLS_ECP_DP_BP256R1_ENABLED
+#define MBEDTLS_ECP_DP_BP384R1_ENABLED
+#define MBEDTLS_ECP_DP_BP512R1_ENABLED
+
+#endif /* #if defined CONFIG_MBEDTLS_LIB_TLS */
+
 #endif /* #if defined CONFIG_MBEDTLS_LIB */
diff --git a/lib/rsa/rsa-sign.c b/lib/rsa/rsa-sign.c
index 2304030..fa9e143 100644
--- a/lib/rsa/rsa-sign.c
+++ b/lib/rsa/rsa-sign.c
@@ -428,6 +428,15 @@
 			ret = rsa_err("Signer padding setup failed");
 			goto err_sign;
 		}
+
+		/* Per RFC 3447 (and convention) the Typical salt length is the
+		 * length of the output of the digest algorithm.
+		 */
+		if (EVP_PKEY_CTX_set_rsa_pss_saltlen(ckey,
+						     checksum_algo->checksum_len) <= 0) {
+			ret = rsa_err("Signer salt length setup failed");
+			goto err_sign;
+		}
 	}
 
 	for (i = 0; i < region_count; i++) {
diff --git a/lib/strto.c b/lib/strto.c
index f83ac67..206d1e9 100644
--- a/lib/strto.c
+++ b/lib/strto.c
@@ -78,6 +78,11 @@
 	return simple_strtoul(cp, endp, 16);
 }
 
+unsigned long long hextoull(const char *cp, char **endp)
+{
+	return simple_strtoull(cp, endp, 16);
+}
+
 ulong dectoul(const char *cp, char **endp)
 {
 	return simple_strtoul(cp, endp, 10);
diff --git a/lib/tiny-printf.c b/lib/tiny-printf.c
index cc1dfe6..0503c17 100644
--- a/lib/tiny-printf.c
+++ b/lib/tiny-printf.c
@@ -312,7 +312,7 @@
 
 			*info->bf = 0;
 			info->bf = p;
-			while (*info->bf++ && width > 0)
+			while (width > 0 && info->bf && *info->bf++)
 				width--;
 			while (width-- > 0)
 				info->putc(info, lz ? '0' : ' ');
diff --git a/lib/tpm-v2.c b/lib/tpm-v2.c
index 59e6cba..ad2b5ab 100644
--- a/lib/tpm-v2.c
+++ b/lib/tpm-v2.c
@@ -821,7 +821,7 @@
 	if (*recv_size < 12)
 		return -ENODATA;
 	*recv_size -= 12;
-	memcpy(recvbuf, recvbuf + 12, *recv_size);
+	memmove(recvbuf, recvbuf + 12, *recv_size);
 
 	return 0;
 }
diff --git a/lib/uuid.c b/lib/uuid.c
index c6a27b7..538a1ba 100644
--- a/lib/uuid.c
+++ b/lib/uuid.c
@@ -35,6 +35,7 @@
 #ifdef USE_HOSTCC
 /* polyfill hextoul to avoid pulling in strto.c */
 #define hextoul(cp, endp) strtoul(cp, endp, 16)
+#define hextoull(cp, endp) strtoull(cp, endp, 16)
 #endif
 
 int uuid_str_valid(const char *uuid)
@@ -312,7 +313,7 @@
 	tmp16 = cpu_to_be16(hextoul(uuid_str + 19, NULL));
 	memcpy(uuid_bin + 8, &tmp16, 2);
 
-	tmp64 = cpu_to_be64(hextoul(uuid_str + 24, NULL));
+	tmp64 = cpu_to_be64(hextoull(uuid_str + 24, NULL));
 	memcpy(uuid_bin + 10, (char *)&tmp64 + 2, 6);
 
 	return 0;
@@ -339,7 +340,7 @@
 	tmp16 = cpu_to_le16(hextoul(uuid_str + 19, NULL));
 	memcpy(uuid_bin + 8, &tmp16, 2);
 
-	tmp64 = cpu_to_le64(hextoul(uuid_str + 24, NULL));
+	tmp64 = cpu_to_le64(hextoull(uuid_str + 24, NULL));
 	memcpy(uuid_bin + 10, &tmp64, 6);
 
 	return 0;
diff --git a/lib/vsprintf.c b/lib/vsprintf.c
index e580286..c7340a0 100644
--- a/lib/vsprintf.c
+++ b/lib/vsprintf.c
@@ -308,7 +308,7 @@
 	return buf;
 }
 
-#if CONFIG_IS_ENABLED(EFI_DEVICE_PATH_TO_TEXT)
+#if CONFIG_IS_ENABLED(EFI_DEVICE_PATH_TO_TEXT) && !defined(API_BUILD)
 static char *device_path_string(char *buf, char *end, void *dp, int field_width,
 				int precision, int flags)
 {
diff --git a/net/lwip/Kconfig b/net/lwip/Kconfig
index 8a67de4..40345ce 100644
--- a/net/lwip/Kconfig
+++ b/net/lwip/Kconfig
@@ -6,9 +6,16 @@
 
 config LWIP_DEBUG
 	bool "Enable debug traces in the lwIP library"
+	help
+	  Prints messages to the console regarding network packets that go in
+          and out of the lwIP library.
 
 config LWIP_ASSERT
 	bool "Enable assertions in the lwIP library"
+	help
+	  Compiles additional error checking code into the lwIP library. These
+	  checks are related to conditions that should not happen in typical
+	  use, but may be helpful to debug new features.
 
 config PROT_DHCP_LWIP
 	bool
@@ -37,7 +44,7 @@
 
 config LWIP_TCP_WND
 	int "Value of TCP_WND"
-	default 8000 if ARCH_QEMU
+	default 32768 if ARCH_QEMU
 	default 3000000
 	help
 	  Default value for TCP_WND in the lwIP configuration
diff --git a/net/lwip/dhcp.c b/net/lwip/dhcp.c
index 23b5622..9b882cf 100644
--- a/net/lwip/dhcp.c
+++ b/net/lwip/dhcp.c
@@ -27,9 +27,9 @@
 
 static int dhcp_loop(struct udevice *udev)
 {
-	char *ipstr = "ipaddr\0\0";
-	char *maskstr = "netmask\0\0";
-	char *gwstr = "gatewayip\0\0";
+	char ipstr[] = "ipaddr\0\0";
+	char maskstr[] = "netmask\0\0";
+	char gwstr[] = "gatewayip\0\0";
 	unsigned long start;
 	struct netif *netif;
 	struct dhcp *dhcp;
@@ -111,9 +111,21 @@
 
 int do_dhcp(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 {
+	int ret;
+
 	eth_set_current();
 
+	ret = dhcp_loop(eth_get_dev());
+	if (ret)
+		return ret;
+
+	if (argc > 1) {
+		struct cmd_tbl cmdtp = {};
+
-	return dhcp_loop(eth_get_dev());
+		return do_tftpb(&cmdtp, 0, argc, argv);
+	}
+
+	return CMD_RET_SUCCESS;
 }
 
 int dhcp_run(ulong addr, const char *fname, bool autoload)
diff --git a/net/lwip/eth_internal.h b/net/lwip/eth_internal.h
index 0b829a8..87561d5 100644
--- a/net/lwip/eth_internal.h
+++ b/net/lwip/eth_internal.h
@@ -25,7 +25,7 @@
  * Return: 0 if OK, other value on error
  */
 int eth_env_set_enetaddr_by_index(const char *base_name, int index,
-				 uchar *enetaddr);
+				  uchar *enetaddr);
 
 int eth_mac_skip(int index);
 void eth_current_changed(void);
diff --git a/net/lwip/net-lwip.c b/net/lwip/net-lwip.c
index 5c2bb2e..b863047 100644
--- a/net/lwip/net-lwip.c
+++ b/net/lwip/net-lwip.c
@@ -91,9 +91,9 @@
 static int get_udev_ipv4_info(struct udevice *dev, ip4_addr_t *ip,
 			      ip4_addr_t *mask, ip4_addr_t *gw)
 {
-	char *ipstr = "ipaddr\0\0";
-	char *maskstr = "netmask\0\0";
-	char *gwstr = "gatewayip\0\0";
+	char ipstr[] = "ipaddr\0\0";
+	char maskstr[] = "netmask\0\0";
+	char gwstr[] = "gatewayip\0\0";
 	int idx = dev_seq(dev);
 	char *env;
 
@@ -203,7 +203,6 @@
 
 struct netif *net_lwip_new_netif_noip(struct udevice *udev)
 {
-
 	return new_netif(udev, false);
 }
 
@@ -224,24 +223,24 @@
 
 static struct pbuf *alloc_pbuf_and_copy(uchar *data, int len)
 {
-        struct pbuf *p, *q;
+	struct pbuf *p, *q;
 
-        /* We allocate a pbuf chain of pbufs from the pool. */
-        p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
-        if (!p) {
-                LINK_STATS_INC(link.memerr);
-                LINK_STATS_INC(link.drop);
-                return NULL;
-        }
+	/* We allocate a pbuf chain of pbufs from the pool. */
+	p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
+	if (!p) {
+		LINK_STATS_INC(link.memerr);
+		LINK_STATS_INC(link.drop);
+		return NULL;
+	}
 
-        for (q = p; q != NULL; q = q->next) {
-                memcpy(q->payload, data, q->len);
-                data += q->len;
-        }
+	for (q = p; q != NULL; q = q->next) {
+		memcpy(q->payload, data, q->len);
+		data += q->len;
+	}
 
-        LINK_STATS_INC(link.recv);
+	LINK_STATS_INC(link.recv);
 
-        return p;
+	return p;
 }
 
 int net_lwip_rx(struct udevice *udev, struct netif *netif)
diff --git a/net/lwip/ping.c b/net/lwip/ping.c
index 8dafa25..aa61753 100644
--- a/net/lwip/ping.c
+++ b/net/lwip/ping.c
@@ -39,8 +39,8 @@
 	    pbuf_remove_header(p, IP_HLEN) == 0) {
 		iecho = (struct icmp_echo_hdr *)p->payload;
 
-		if ((iecho->id == PING_ID) &&
-		    (iecho->seqno == lwip_htons(ctx->seq_num))) {
+		if (iecho->id == PING_ID &&
+		    iecho->seqno == lwip_htons(ctx->seq_num)) {
 			ctx->alive = true;
 			printf("host %s is alive\n", ipaddr_ntoa(addr));
 			pbuf_free(p);
@@ -93,7 +93,7 @@
 	if (!p)
 		return;
 
-	if ((p->len == p->tot_len) && !p->next) {
+	if (p->len == p->tot_len && !p->next) {
 		ctx->iecho = (struct icmp_echo_hdr *)p->payload;
 		ping_prepare_echo(ctx);
 		raw_sendto(ctx->pcb, p, &ctx->target);
@@ -113,7 +113,7 @@
 	}
 }
 
-static int ping_loop(struct udevice *udev, const ip_addr_t* addr)
+static int ping_loop(struct udevice *udev, const ip_addr_t *addr)
 {
 	struct ping_ctx ctx = {};
 	struct netif *netif;
diff --git a/net/lwip/tftp.c b/net/lwip/tftp.c
index f4d0a6a..fc4aff5 100644
--- a/net/lwip/tftp.c
+++ b/net/lwip/tftp.c
@@ -71,7 +71,7 @@
 	struct tftp_ctx *ctx = handle;
 	struct pbuf *q;
 
-	for (q = p; q != NULL; q = q->next) {
+	for (q = p; q; q = q->next) {
 		memcpy((void *)ctx->daddr, q->payload, q->len);
 		ctx->daddr += q->len;
 		ctx->size += q->len;
@@ -130,7 +130,7 @@
 
 	printf("Using %s device\n", udev->name);
 	printf("TFTP from server %s; our IP address is %s\n",
-		 ip4addr_ntoa(&srvip), env_get("ipaddr"));
+	       ip4addr_ntoa(&srvip), env_get("ipaddr"));
 	printf("Filename '%s'.\n", fname);
 	printf("Load address: 0x%lx\n", ctx.daddr);
 	printf("Loading: ");
@@ -187,7 +187,7 @@
 	char *server_port = NULL;
 	char *end;
 	ip_addr_t srvip;
-	uint16_t port = TFTP_PORT;
+	u16 port = TFTP_PORT;
 	ulong laddr;
 	ulong addr;
 	int i;
@@ -228,7 +228,7 @@
 	if (arg) {
 		/* Parse [ip:[port:]]fname */
 		i = 0;
-		while ((*(words + i) = strsep(&arg,":")))
+		while ((*(words + i) = strsep(&arg, ":")))
 			i++;
 
 		switch (i) {
diff --git a/net/lwip/wget.c b/net/lwip/wget.c
index 53c3b16..46858cb 100644
--- a/net/lwip/wget.c
+++ b/net/lwip/wget.c
@@ -7,19 +7,23 @@
 #include <efi_loader.h>
 #include <image.h>
 #include <lwip/apps/http_client.h>
+#include "lwip/altcp_tls.h"
 #include <lwip/timeouts.h>
+#include <rng.h>
 #include <mapmem.h>
 #include <net.h>
 #include <time.h>
+#include <dm/uclass.h>
 
-#define SERVER_NAME_SIZE 200
+#define SERVER_NAME_SIZE 254
 #define HTTP_PORT_DEFAULT 80
+#define HTTPS_PORT_DEFAULT 443
 #define PROGRESS_PRINT_STEP_BYTES (100 * 1024)
 
 enum done_state {
-        NOT_DONE = 0,
-        SUCCESS = 1,
-        FAILURE = 2
+	NOT_DONE = 0,
+	SUCCESS = 1,
+	FAILURE = 2
 };
 
 struct wget_ctx {
@@ -46,18 +50,54 @@
 	wget_info->file_size = (ulong)rx_content_len;
 }
 
-static int parse_url(char *url, char *host, u16 *port, char **path)
+bool wget_validate_uri(char *uri);
+
+int mbedtls_hardware_poll(void *data, unsigned char *output, size_t len,
+			  size_t *olen)
+{
+	struct udevice *dev;
+	int ret;
+
+	*olen = 0;
+
+	ret = uclass_get_device(UCLASS_RNG, 0, &dev);
+	if (ret) {
+		log_err("Failed to get an rng: %d\n", ret);
+		return ret;
+	}
+	ret = dm_rng_read(dev, output, len);
+	if (ret)
+		return ret;
+
+	*olen = len;
+
+	return 0;
+}
+
+static int parse_url(char *url, char *host, u16 *port, char **path,
+		     bool *is_https)
 {
 	char *p, *pp;
 	long lport;
+	size_t prefix_len = 0;
 
+	if (!wget_validate_uri(url)) {
+		log_err("Invalid URL. Use http(s)://\n");
+		return -EINVAL;
+	}
+
+	*is_https = false;
+	*port = HTTP_PORT_DEFAULT;
+	prefix_len = strlen("http://");
 	p = strstr(url, "http://");
 	if (!p) {
-		log_err("only http:// is supported\n");
-		return -EINVAL;
+		p = strstr(url, "https://");
+		prefix_len = strlen("https://");
+		*port = HTTPS_PORT_DEFAULT;
+		*is_https = true;
 	}
 
-	p += strlen("http://");
+	p += prefix_len;
 
 	/* Parse hostname */
 	pp = strchr(p, ':');
@@ -81,9 +121,8 @@
 		if (lport > 65535)
 			return -EINVAL;
 		*port = (u16)lport;
-	} else {
-		*port = HTTP_PORT_DEFAULT;
 	}
+
 	if (*pp != '/')
 		return -EINVAL;
 	*path = pp;
@@ -136,7 +175,7 @@
 
 	if (rem < n)
 		return -1;
-	strncpy(p, server, n);
+	strlcpy(p, server, n);
 	p += n;
 	rem -= n;
 	if (rem < 1)
@@ -147,7 +186,7 @@
 	n = strlen(path);
 	if (rem < n)
 		return -1;
-	strncpy(p, path, n);
+	strlcpy(p, path, n);
 	p += n;
 	rem -= n;
 	if (rem < 1)
@@ -244,11 +283,17 @@
 
 static int wget_loop(struct udevice *udev, ulong dst_addr, char *uri)
 {
+	char server_name[SERVER_NAME_SIZE];
+#if defined CONFIG_WGET_HTTPS
+	altcp_allocator_t tls_allocator;
+#endif
 	httpc_connection_t conn;
 	httpc_state_t *state;
 	struct netif *netif;
 	struct wget_ctx ctx;
 	char *path;
+	u16 port;
+	bool is_https;
 
 	ctx.daddr = dst_addr;
 	ctx.saved_daddr = dst_addr;
@@ -257,7 +302,7 @@
 	ctx.prevsize = 0;
 	ctx.start_time = 0;
 
-	if (parse_url(uri, ctx.server_name, &ctx.port, &path))
+	if (parse_url(uri, server_name, &port, &path, &is_https))
 		return CMD_RET_USAGE;
 
 	netif = net_lwip_new_netif(udev);
@@ -265,6 +310,22 @@
 		return -1;
 
 	memset(&conn, 0, sizeof(conn));
+#if defined CONFIG_WGET_HTTPS
+	if (is_https) {
+		tls_allocator.alloc = &altcp_tls_alloc;
+		tls_allocator.arg =
+			altcp_tls_create_config_client(NULL, 0, server_name);
+
+		if (!tls_allocator.arg) {
+			log_err("error: Cannot create a TLS connection\n");
+			net_lwip_remove_netif(netif);
+			return -1;
+		}
+
+		conn.altcp_allocator = &tls_allocator;
+	}
+#endif
+
 	conn.result_fn = httpc_result_cb;
 	conn.headers_done_fn = httpc_headers_done_cb;
 	ctx.path = path;
@@ -310,7 +371,7 @@
 		return CMD_RET_USAGE;
 
 	dst_addr = hextoul(argv[1], &end);
-        if (end == (argv[1] + strlen(argv[1]))) {
+	if (end == (argv[1] + strlen(argv[1]))) {
 		if (argc < 3)
 			return CMD_RET_USAGE;
 		url = argv[2];
@@ -320,7 +381,7 @@
 	}
 
 	if (parse_legacy_arg(url, nurl, sizeof(nurl)))
-	    return CMD_RET_FAILURE;
+		return CMD_RET_FAILURE;
 
 	wget_info = &default_wget_info;
 	if (wget_with_dns(dst_addr, nurl))
@@ -354,6 +415,7 @@
 	char c;
 	bool ret = true;
 	char *str_copy, *s, *authority;
+	size_t prefix_len = 0;
 
 	for (c = 0x1; c < 0x21; c++) {
 		if (strchr(uri, c)) {
@@ -361,15 +423,21 @@
 			return false;
 		}
 	}
+
 	if (strchr(uri, 0x7f)) {
 		log_err("invalid character is used\n");
 		return false;
 	}
 
-	if (strncmp(uri, "http://", 7)) {
-		log_err("only http:// is supported\n");
+	if (!strncmp(uri, "http://", strlen("http://"))) {
+		prefix_len = strlen("http://");
+	} else if (!strncmp(uri, "https://", strlen("https://"))) {
+		prefix_len = strlen("https://");
+	} else {
+		log_err("only http(s):// is supported\n");
 		return false;
 	}
+
 	str_copy = strdup(uri);
 	if (!str_copy)
 		return false;
diff --git a/test/Makefile b/test/Makefile
index 145c952..47a07d6 100644
--- a/test/Makefile
+++ b/test/Makefile
@@ -4,14 +4,8 @@
 
 obj-y += test-main.o
 
-ifneq ($(CONFIG_$(XPL_)BLOBLIST),)
-obj-$(CONFIG_$(XPL_)CMDLINE) += bloblist.o
-obj-$(CONFIG_$(XPL_)CMDLINE) += bootm.o
-endif
 obj-$(CONFIG_$(XPL_)CMDLINE) += cmd/
 obj-$(CONFIG_$(XPL_)CMDLINE) += cmd_ut.o
-obj-$(CONFIG_$(XPL_)CMDLINE) += command_ut.o
-obj-$(CONFIG_$(XPL_)UT_COMPRESSION) += compression.o
 obj-y += dm/
 obj-$(CONFIG_FUZZ) += fuzz/
 ifndef CONFIG_SANDBOX_VPL
@@ -20,16 +14,12 @@
 ifneq ($(CONFIG_HUSH_PARSER),)
 obj-$(CONFIG_$(XPL_)CMDLINE) += hush/
 endif
-obj-$(CONFIG_$(XPL_)CMDLINE) += print_ut.o
-obj-$(CONFIG_$(XPL_)CMDLINE) += str_ut.o
-obj-$(CONFIG_UT_TIME) += time_ut.o
 obj-y += ut.o
 
 ifeq ($(CONFIG_XPL_BUILD),)
 obj-y += boot/
 obj-$(CONFIG_UNIT_TEST) += common/
 obj-y += log/
-obj-$(CONFIG_$(XPL_)UT_UNICODE) += unicode_ut.o
 else
 obj-$(CONFIG_SPL_UT_LOAD) += image/
 endif
diff --git a/test/boot/Makefile b/test/boot/Makefile
index d8eded2..63487e8 100644
--- a/test/boot/Makefile
+++ b/test/boot/Makefile
@@ -10,6 +10,9 @@
 obj-$(CONFIG_CEDIT) += cedit.o
 endif
 
+ifdef CONFIG_SANDBOX
+obj-$(CONFIG_$(XPL_)CMDLINE) += bootm.o
+endif
 obj-$(CONFIG_MEASURED_BOOT) += measurement.o
 
 ifdef CONFIG_OF_LIVE
diff --git a/test/boot/bootflow.c b/test/boot/bootflow.c
index 9397328..e33b08a 100644
--- a/test/boot/bootflow.c
+++ b/test/boot/bootflow.c
@@ -1197,10 +1197,10 @@
 
 	return 0;
 }
-BOOTSTD_TEST(bootflow_cros, UTF_CONSOLE);
+BOOTSTD_TEST(bootflow_cros, UTF_CONSOLE | UTF_DM | UTF_SCAN_FDT);
 
-/* Test Android bootmeth  */
-static int bootflow_android(struct unit_test_state *uts)
+/* Test Android bootmeth  with boot image version 4 */
+static int bootflow_android_image_v4(struct unit_test_state *uts)
 {
 	if (!IS_ENABLED(CONFIG_BOOTMETH_ANDROID))
 		return -EAGAIN;
@@ -1220,7 +1220,30 @@
 
 	return 0;
 }
-BOOTSTD_TEST(bootflow_android, UTF_CONSOLE);
+BOOTSTD_TEST(bootflow_android_image_v4, UTF_CONSOLE | UTF_DM | UTF_SCAN_FDT);
+
+/* Test Android bootmeth with boot image version 2 */
+static int bootflow_android_image_v2(struct unit_test_state *uts)
+{
+	if (!IS_ENABLED(CONFIG_BOOTMETH_ANDROID))
+		return -EAGAIN;
+
+	ut_assertok(scan_mmc_android_bootdev(uts, "mmc8"));
+	ut_assertok(run_command("bootflow list", 0));
+
+	ut_assert_nextlinen("Showing all");
+	ut_assert_nextlinen("Seq");
+	ut_assert_nextlinen("---");
+	ut_assert_nextlinen("  0  extlinux");
+	ut_assert_nextlinen("  1  android      ready   mmc          0  mmc8.bootdev.whole        ");
+	ut_assert_nextlinen("---");
+	ut_assert_skip_to_line("(2 bootflows, 2 valid)");
+
+	ut_assert_console_end();
+
+	return 0;
+}
+BOOTSTD_TEST(bootflow_android_image_v2, UTF_CONSOLE | UTF_DM | UTF_SCAN_FDT);
 
 /* Test EFI bootmeth */
 static int bootflow_efi(struct unit_test_state *uts)
diff --git a/test/bootm.c b/test/boot/bootm.c
similarity index 100%
rename from test/bootm.c
rename to test/boot/bootm.c
diff --git a/test/cmd/Makefile b/test/cmd/Makefile
index 0055330..583e7c2 100644
--- a/test/cmd/Makefile
+++ b/test/cmd/Makefile
@@ -5,6 +5,7 @@
 
 obj-y += cmd_ut_cmd.o
 
+obj-$(CONFIG_$(XPL_)CMDLINE) += command.o
 ifdef CONFIG_HUSH_PARSER
 obj-$(CONFIG_CONSOLE_RECORD) += test_echo.o
 endif
@@ -18,6 +19,7 @@
 obj-$(CONFIG_COREBOOT_SYSINFO) += coreboot.o
 obj-$(CONFIG_CMD_FDT) += fdt.o
 obj-$(CONFIG_CONSOLE_TRUETYPE) += font.o
+obj-$(CONFIG_CMD_HASH) += hash.o
 obj-$(CONFIG_CMD_HISTORY) += history.o
 obj-$(CONFIG_CMD_LOADM) += loadm.o
 obj-$(CONFIG_CMD_MEMINFO) += meminfo.o
diff --git a/test/cmd/bdinfo.c b/test/cmd/bdinfo.c
index 770b3bf..bb419ab 100644
--- a/test/cmd/bdinfo.c
+++ b/test/cmd/bdinfo.c
@@ -107,7 +107,7 @@
 	enum lmb_flags flags;
 	int i;
 
-	ut_assert_nextline(" %s.count = 0x%hx", name, lmb_rgn_lst->count);
+	ut_assert_nextline(" %s.count = %#x", name, lmb_rgn_lst->count);
 
 	for (i = 0; i < lmb_rgn_lst->count; i++) {
 		base = rgn[i].base;
@@ -119,7 +119,7 @@
 			ut_assert_nextlinen(" %s[%d]\t[", name, i);
 			continue;
 		}
-		ut_assert_nextlinen(" %s[%d]\t[0x%llx-0x%llx], 0x%08llx bytes flags: ",
+		ut_assert_nextlinen(" %s[%d]\t[%#llx-%#llx], %#llx bytes, flags: ",
 				    name, i, base, end, size);
 	}
 
diff --git a/test/cmd/command.c b/test/cmd/command.c
new file mode 100644
index 0000000..5ec93d4
--- /dev/null
+++ b/test/cmd/command.c
@@ -0,0 +1,108 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2012, The Chromium Authors
+ */
+
+#define DEBUG
+
+#include <command.h>
+#include <env.h>
+#include <log.h>
+#include <string.h>
+#include <linux/errno.h>
+#include <test/cmd.h>
+#include <test/ut.h>
+
+static const char test_cmd[] = "setenv list 1\n setenv list ${list}2; "
+		"setenv list ${list}3\0"
+		"setenv list ${list}4";
+
+static int command_test(struct unit_test_state *uts)
+{
+	char long_str[CONFIG_SYS_CBSIZE + 42];
+
+	printf("%s: Testing commands\n", __func__);
+	run_command("env default -f -a", 0);
+
+	/* commands separated by \n */
+	run_command_list("setenv list 1\n setenv list ${list}1", -1, 0);
+	ut_assert(!strcmp("11", env_get("list")));
+
+	/* command followed by \n and nothing else */
+	run_command_list("setenv list 1${list}\n", -1, 0);
+	ut_assert(!strcmp("111", env_get("list")));
+
+	/* a command string with \0 in it. Stuff after \0 should be ignored */
+	run_command("setenv list", 0);
+	run_command_list(test_cmd, sizeof(test_cmd), 0);
+	ut_assert(!strcmp("123", env_get("list")));
+
+	/*
+	 * a command list where we limit execution to only the first command
+	 * using the length parameter.
+	 */
+	run_command_list("setenv list 1\n setenv list ${list}2; "
+		"setenv list ${list}3", strlen("setenv list 1"), 0);
+	ut_assert(!strcmp("1", env_get("list")));
+
+	ut_asserteq(1, run_command("false", 0));
+	ut_assertok(run_command("echo", 0));
+	ut_asserteq(1, run_command_list("false", -1, 0));
+	ut_assertok(run_command_list("echo", -1, 0));
+
+#ifdef CONFIG_HUSH_PARSER
+	run_command("setenv foo 'setenv black 1\nsetenv adder 2'", 0);
+	run_command("run foo", 0);
+	ut_assertnonnull(env_get("black"));
+	ut_asserteq(0, strcmp("1", env_get("black")));
+	ut_assertnonnull(env_get("adder"));
+	ut_asserteq(0, strcmp("2", env_get("adder")));
+#endif
+
+	ut_assertok(run_command("", 0));
+	ut_assertok(run_command(" ", 0));
+
+	ut_asserteq(1, run_command("'", 0));
+
+	/* Variadic function test-cases */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wformat-zero-length"
+	ut_assertok(run_commandf(""));
+#pragma GCC diagnostic pop
+	ut_assertok(run_commandf(" "));
+	ut_asserteq(1, run_commandf("'"));
+
+	ut_assertok(run_commandf("env %s %s", "delete -f", "list"));
+	/*
+	 * Expected: "## Error: "list" not defined"
+	 * (disabled to avoid pytest bailing out)
+	 *
+	 * ut_asserteq(1, run_commandf("printenv list"));
+	 */
+
+	memset(long_str, 'x', sizeof(long_str));
+	ut_asserteq(-ENOSPC, run_commandf("Truncation case: %s", long_str));
+
+	if (IS_ENABLED(CONFIG_HUSH_PARSER)) {
+		ut_assertok(run_commandf("env %s %s %s %s", "delete -f",
+					 "adder", "black", "foo"));
+		ut_assertok(run_commandf(
+			"setenv foo 'setenv %s 1\nsetenv %s 2'",
+			"black", "adder"));
+		ut_assertok(run_command("run foo", 0));
+		ut_assertnonnull(env_get("black"));
+		ut_asserteq(0, strcmp("1", env_get("black")));
+		ut_assertnonnull(env_get("adder"));
+		ut_asserteq(0, strcmp("2", env_get("adder")));
+	}
+
+	/* Clean up before exit */
+	ut_assertok(run_command("env default -f -a", 0));
+
+	/* put back the FDT environment */
+	ut_assertok(env_set("from_fdt", "yes"));
+
+	printf("%s: Everything went swimmingly\n", __func__);
+	return 0;
+}
+CMD_TEST(command_test, 0);
diff --git a/test/cmd/hash.c b/test/cmd/hash.c
new file mode 100644
index 0000000..296dd76
--- /dev/null
+++ b/test/cmd/hash.c
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Tests for hash command
+ *
+ * Copyright 2024, Heinrich Schuchardt <heinrich.schuchardt@canoncal.com>
+ */
+
+#include <command.h>
+#include <dm.h>
+#include <dm/test.h>
+#include <test/test.h>
+#include <test/ut.h>
+
+static int dm_test_cmd_hash_md5(struct unit_test_state *uts)
+{
+	if (!CONFIG_IS_ENABLED(MD5)) {
+		ut_assert(run_command("hash md5 $loadaddr 0", 0));
+
+		return 0;
+	}
+
+	ut_assertok(run_command("hash md5 $loadaddr 0", 0));
+	console_record_readline(uts->actual_str, sizeof(uts->actual_str));
+	ut_asserteq_ptr(uts->actual_str,
+			strstr(uts->actual_str, "md5 for "));
+	ut_assert(strstr(uts->actual_str,
+			 "d41d8cd98f00b204e9800998ecf8427e"));
+	ut_assert_console_end();
+
+	ut_assertok(run_command("hash md5 $loadaddr 0 foo; echo $foo", 0));
+	console_record_readline(uts->actual_str, sizeof(uts->actual_str));
+	ut_asserteq_ptr(uts->actual_str,
+			strstr(uts->actual_str, "md5 for "));
+	ut_assert(strstr(uts->actual_str,
+			 "d41d8cd98f00b204e9800998ecf8427e"));
+	ut_assertok(ut_check_console_line(uts,
+					  "d41d8cd98f00b204e9800998ecf8427e"));
+
+	if (!CONFIG_IS_ENABLED(HASH_VERIFY)) {
+		ut_assert(run_command("hash -v sha256 $loadaddr 0 foo", 0));
+		ut_assertok(ut_check_console_line(
+				uts, "hash - compute hash message digest"));
+
+		return 0;
+	}
+
+	ut_assertok(run_command("hash -v md5 $loadaddr 0 foo", 0));
+	ut_assert_console_end();
+
+	env_set("foo", "ffffffffffffffffffffffffffffffff");
+	ut_assert(run_command("hash -v md5 $loadaddr 0 foo", 0));
+	console_record_readline(uts->actual_str, sizeof(uts->actual_str));
+	ut_assert(strstr(uts->actual_str, "!="));
+	ut_assert_console_end();
+
+	return 0;
+}
+DM_TEST(dm_test_cmd_hash_md5, UTF_CONSOLE);
+
+static int dm_test_cmd_hash_sha256(struct unit_test_state *uts)
+{
+	if (!CONFIG_IS_ENABLED(SHA256)) {
+		ut_assert(run_command("hash sha256 $loadaddr 0", 0));
+
+		return 0;
+	}
+
+	ut_assertok(run_command("hash sha256 $loadaddr 0", 0));
+	console_record_readline(uts->actual_str, sizeof(uts->actual_str));
+	ut_asserteq_ptr(uts->actual_str,
+			strstr(uts->actual_str, "sha256 for "));
+	ut_assert(strstr(uts->actual_str,
+			 "e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855"));
+	ut_assert_console_end();
+
+	ut_assertok(run_command("hash sha256 $loadaddr 0 foo; echo $foo", 0));
+	console_record_readline(uts->actual_str, sizeof(uts->actual_str));
+	ut_asserteq_ptr(uts->actual_str,
+			strstr(uts->actual_str, "sha256 for "));
+	ut_assert(strstr(uts->actual_str,
+			 "e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855"));
+	ut_assertok(ut_check_console_line(
+			uts, "e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855"));
+
+	if (!CONFIG_IS_ENABLED(HASH_VERIFY)) {
+		ut_assert(run_command("hash -v sha256 $loadaddr 0 foo", 0));
+		ut_assertok(ut_check_console_line(
+				uts, "hash - compute hash message digest"));
+
+		return 0;
+	}
+
+	ut_assertok(run_command("hash -v sha256 $loadaddr 0 foo", 0));
+	ut_assert_console_end();
+
+	env_set("foo", "ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff");
+	ut_assert(run_command("hash -v sha256 $loadaddr 0 foo", 0));
+	console_record_readline(uts->actual_str, sizeof(uts->actual_str));
+	ut_assert(strstr(uts->actual_str, "!="));
+	ut_assert_console_end();
+
+	return 0;
+}
+DM_TEST(dm_test_cmd_hash_sha256, UTF_CONSOLE);
diff --git a/test/cmd/mbr.c b/test/cmd/mbr.c
index b14137e..d137378 100644
--- a/test/cmd/mbr.c
+++ b/test/cmd/mbr.c
@@ -257,8 +257,8 @@
 		strlen(mbr_parts_p3) +
 		max(strlen(mbr_parts_p4), strlen(mbr_parts_p5)) +
 		strlen(mbr_parts_tail);
-	ut_assertf(sizeof(mbr_parts_buf) >= mbr_parts_max, "Buffer avail: %ld; buffer req: %ld\n",
-		sizeof(mbr_parts_buf), mbr_parts_max);
+	ut_assertf(sizeof(mbr_parts_buf) >= mbr_parts_max, "Buffer avail: %zd; buffer req: %ld\n",
+		   sizeof(mbr_parts_buf), mbr_parts_max);
 
 	mbr_wbuf = map_sysmem(mbr_wa, BLKSZ);
 	ebr_wbuf = map_sysmem(ebr_wa, BLKSZ);
@@ -277,7 +277,7 @@
 				 (ulong)0xbffe00 / BLKSZ));
 
 	/* Test one MBR partition */
-	init_write_buffers(mbr_wbuf, sizeof(mbr_wbuf), ebr_wbuf, sizeof(ebr_wbuf), __LINE__);
+	init_write_buffers(mbr_wbuf, BLKSZ, ebr_wbuf, BLKSZ, __LINE__);
 	ut_assertok(build_mbr_parts(mbr_parts_buf, sizeof(mbr_parts_buf), 1));
 	ut_assertok(run_commandf("write mmc 6:0 %lx 0 1", mbr_wa));
 	memset(rbuf, '\0', BLKSZ);
diff --git a/test/cmd_ut.c b/test/cmd_ut.c
index 53fddeb..195b7ea 100644
--- a/test/cmd_ut.c
+++ b/test/cmd_ut.c
@@ -99,25 +99,15 @@
 	U_BOOT_CMD_MKENT(setexpr, CONFIG_SYS_MAXARGS, 1, do_ut_setexpr, "",
 			 ""),
 #endif
-	U_BOOT_CMD_MKENT(print, CONFIG_SYS_MAXARGS, 1, do_ut_print, "", ""),
-#ifdef CONFIG_UT_TIME
-	U_BOOT_CMD_MKENT(time, CONFIG_SYS_MAXARGS, 1, do_ut_time, "", ""),
-#endif
-#if CONFIG_IS_ENABLED(UT_UNICODE) && !defined(API_BUILD)
-	U_BOOT_CMD_MKENT(unicode, CONFIG_SYS_MAXARGS, 1, do_ut_unicode, "", ""),
-#endif
 #ifdef CONFIG_MEASURED_BOOT
 	U_BOOT_CMD_MKENT(measurement, CONFIG_SYS_MAXARGS, 1, do_ut_measurement,
 			 "", ""),
 #endif
 #ifdef CONFIG_SANDBOX
-	U_BOOT_CMD_MKENT(compression, CONFIG_SYS_MAXARGS, 1, do_ut_compression,
-			 "", ""),
 	U_BOOT_CMD_MKENT(bloblist, CONFIG_SYS_MAXARGS, 1, do_ut_bloblist,
 			 "", ""),
 	U_BOOT_CMD_MKENT(bootm, CONFIG_SYS_MAXARGS, 1, do_ut_bootm, "", ""),
 #endif
-	U_BOOT_CMD_MKENT(str, CONFIG_SYS_MAXARGS, 1, do_ut_str, "", ""),
 #ifdef CONFIG_CMD_ADDRMAP
 	U_BOOT_CMD_MKENT(addrmap, CONFIG_SYS_MAXARGS, 1, do_ut_addrmap, "", ""),
 #endif
@@ -207,9 +197,7 @@
 #ifdef CONFIG_CMDLINE
 	"\ncmd - test various commands"
 #endif
-#ifdef CONFIG_SANDBOX
-	"\ncompression - compressors and bootm decompression"
-#endif
+	"\ncommon   - tests for common/ directory"
 #ifdef CONFIG_UT_DM
 	"\ndm - driver model"
 #endif
@@ -244,21 +232,10 @@
 #ifdef CONFIG_CMD_PCI_MPS
 	"\npci_mps - PCI Express Maximum Payload Size"
 #endif
-	"\nprint  - printing things to the console"
 	"\nsetexpr - setexpr command"
-#ifdef CONFIG_SANDBOX
-	"\nstr - basic test of string functions"
-#endif
 #ifdef CONFIG_CMD_SEAMA
 	"\nseama - seama command parameters loading and decoding"
 #endif
-#ifdef CONFIG_UT_TIME
-	"\ntime - very basic test of time functions"
-#endif
-#if defined(CONFIG_UT_UNICODE) && \
-	!defined(CONFIG_XPL_BUILD) && !defined(API_BUILD)
-	"\nunicode - Unicode functions"
-#endif
 	);
 
 U_BOOT_CMD(
diff --git a/test/command_ut.c b/test/command_ut.c
deleted file mode 100644
index 2b8d28d..0000000
--- a/test/command_ut.c
+++ /dev/null
@@ -1,104 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2012, The Chromium Authors
- */
-
-#define DEBUG
-
-#include <command.h>
-#include <env.h>
-#include <log.h>
-#include <string.h>
-#include <linux/errno.h>
-
-static const char test_cmd[] = "setenv list 1\n setenv list ${list}2; "
-		"setenv list ${list}3\0"
-		"setenv list ${list}4";
-
-static int do_ut_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
-		     char *const argv[])
-{
-	char long_str[CONFIG_SYS_CBSIZE + 42];
-
-	printf("%s: Testing commands\n", __func__);
-	run_command("env default -f -a", 0);
-
-	/* commands separated by \n */
-	run_command_list("setenv list 1\n setenv list ${list}1", -1, 0);
-	assert(!strcmp("11", env_get("list")));
-
-	/* command followed by \n and nothing else */
-	run_command_list("setenv list 1${list}\n", -1, 0);
-	assert(!strcmp("111", env_get("list")));
-
-	/* a command string with \0 in it. Stuff after \0 should be ignored */
-	run_command("setenv list", 0);
-	run_command_list(test_cmd, sizeof(test_cmd), 0);
-	assert(!strcmp("123", env_get("list")));
-
-	/*
-	 * a command list where we limit execution to only the first command
-	 * using the length parameter.
-	 */
-	run_command_list("setenv list 1\n setenv list ${list}2; "
-		"setenv list ${list}3", strlen("setenv list 1"), 0);
-	assert(!strcmp("1", env_get("list")));
-
-	assert(run_command("false", 0) == 1);
-	assert(run_command("echo", 0) == 0);
-	assert(run_command_list("false", -1, 0) == 1);
-	assert(run_command_list("echo", -1, 0) == 0);
-
-#ifdef CONFIG_HUSH_PARSER
-	run_command("setenv foo 'setenv black 1\nsetenv adder 2'", 0);
-	run_command("run foo", 0);
-	assert(env_get("black") != NULL);
-	assert(!strcmp("1", env_get("black")));
-	assert(env_get("adder") != NULL);
-	assert(!strcmp("2", env_get("adder")));
-#endif
-
-	assert(run_command("", 0) == 0);
-	assert(run_command(" ", 0) == 0);
-
-	assert(run_command("'", 0) == 1);
-
-	/* Variadic function test-cases */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wformat-zero-length"
-	assert(run_commandf("") == 0);
-#pragma GCC diagnostic pop
-	assert(run_commandf(" ") == 0);
-	assert(run_commandf("'") == 1);
-
-	assert(run_commandf("env %s %s", "delete -f", "list") == 0);
-	/* Expected: "Error: "list" not defined" */
-	assert(run_commandf("printenv list") == 1);
-
-	memset(long_str, 'x', sizeof(long_str));
-	assert(run_commandf("Truncation case: %s", long_str) == -ENOSPC);
-
-	if (IS_ENABLED(CONFIG_HUSH_PARSER)) {
-		assert(run_commandf("env %s %s %s %s", "delete -f", "adder",
-				    "black", "foo") == 0);
-		assert(run_commandf("setenv foo 'setenv %s 1\nsetenv %s 2'",
-				    "black", "adder") == 0);
-		run_command("run foo", 0);
-		assert(env_get("black"));
-		assert(!strcmp("1", env_get("black")));
-		assert(env_get("adder"));
-		assert(!strcmp("2", env_get("adder")));
-	}
-
-	/* Clean up before exit */
-	run_command("env default -f -a", 0);
-
-	printf("%s: Everything went swimmingly\n", __func__);
-	return 0;
-}
-
-U_BOOT_CMD(
-	ut_cmd,	5,	1,	do_ut_cmd,
-	"Very basic test of command parsers",
-	""
-);
diff --git a/test/common.sh b/test/common.sh
deleted file mode 100644
index 904d579..0000000
--- a/test/common.sh
+++ /dev/null
@@ -1,20 +0,0 @@
-#!/bin/sh
-
-OUTPUT_DIR=sandbox
-
-fail() {
-	echo "Test failed: $1"
-	if [ -n ${tmp} ]; then
-		rm ${tmp}
-	fi
-	exit 1
-}
-
-build_uboot() {
-	echo "Build sandbox"
-	OPTS="O=${OUTPUT_DIR} $1"
-	NUM_CPUS=$(nproc)
-	echo ${OPTS}
-	make ${OPTS} sandbox_config
-	make ${OPTS} -s -j${NUM_CPUS}
-}
diff --git a/test/common/Makefile b/test/common/Makefile
index 12c65f8..53c4f16 100644
--- a/test/common/Makefile
+++ b/test/common/Makefile
@@ -1,6 +1,10 @@
 # SPDX-License-Identifier: GPL-2.0+
 obj-y += cmd_ut_common.o
 obj-$(CONFIG_AUTOBOOT) += test_autoboot.o
+ifneq ($(CONFIG_$(XPL_)BLOBLIST),)
+obj-$(CONFIG_$(XPL_)CMDLINE) += bloblist.o
+endif
 obj-$(CONFIG_CYCLIC) += cyclic.o
 obj-$(CONFIG_EVENT_DYNAMIC) += event.o
 obj-y += cread.o
+obj-$(CONFIG_$(XPL_)CMDLINE) += print.o
diff --git a/test/bloblist.c b/test/common/bloblist.c
similarity index 99%
rename from test/bloblist.c
rename to test/common/bloblist.c
index e0ad94e..4bca621 100644
--- a/test/bloblist.c
+++ b/test/common/bloblist.c
@@ -6,13 +6,10 @@
 #include <bloblist.h>
 #include <log.h>
 #include <mapmem.h>
-#include <asm/global_data.h>
 #include <test/suites.h>
 #include <test/test.h>
 #include <test/ut.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
 /* Declare a new bloblist test */
 #define BLOBLIST_TEST(_name, _flags) \
 		UNIT_TEST(_name, _flags, bloblist_test)
diff --git a/test/print_ut.c b/test/common/print.c
similarity index 93%
rename from test/print_ut.c
rename to test/common/print.c
index f5e607b..464e425 100644
--- a/test/print_ut.c
+++ b/test/common/print.c
@@ -11,7 +11,7 @@
 #include <version_string.h>
 #include <stdio.h>
 #include <vsprintf.h>
-#include <test/suites.h>
+#include <test/common.h>
 #include <test/test.h>
 #include <test/ut.h>
 
@@ -20,9 +20,6 @@
 #define FAKE_BUILD_TAG	"jenkins-u-boot-denx_uboot_dm-master-build-aarch64" \
 			"and a lot more text to come"
 
-/* Declare a new print test */
-#define PRINT_TEST(_name, _flags)	UNIT_TEST(_name, _flags, print_test)
-
 #if CONFIG_IS_ENABLED(LIB_UUID)
 /* Test printing GUIDs */
 static int print_guid(struct unit_test_state *uts)
@@ -59,7 +56,7 @@
 
 	return 0;
 }
-PRINT_TEST(print_guid, 0);
+COMMON_TEST(print_guid, 0);
 #endif
 
 #if CONFIG_IS_ENABLED(EFI_LOADER) && !defined(API_BUILD)
@@ -95,7 +92,7 @@
 
 	return 0;
 }
-PRINT_TEST(print_efi_ut, 0);
+COMMON_TEST(print_efi_ut, 0);
 #endif
 
 static int print_printf(struct unit_test_state *uts)
@@ -118,8 +115,10 @@
 	snprintf(str, 0, "testing none");
 	ut_asserteq('x', *str);
 
-	sprintf(big_str, "_%ls_", u"foo");
-	ut_assertok(strcmp("_foo_", big_str));
+	if (CONFIG_IS_ENABLED(EFI_LOADER) || IS_ENABLED(CONFIG_EFI_APP)) {
+		sprintf(big_str, "_%ls_", u"foo");
+		ut_assertok(strcmp("_foo_", big_str));
+	}
 
 	/* Test the banner function */
 	s = display_options_get_banner(true, str, sizeof(str));
@@ -163,7 +162,7 @@
 
 	return 0;
 }
-PRINT_TEST(print_printf, 0);
+COMMON_TEST(print_printf, 0);
 
 static int print_display_buffer(struct unit_test_state *uts)
 {
@@ -238,7 +237,7 @@
 
 	return 0;
 }
-PRINT_TEST(print_display_buffer, UTF_CONSOLE);
+COMMON_TEST(print_display_buffer, UTF_CONSOLE);
 
 static int print_hexdump_line(struct unit_test_state *uts)
 {
@@ -264,7 +263,7 @@
 
 	return 0;
 }
-PRINT_TEST(print_hexdump_line, UTF_CONSOLE);
+COMMON_TEST(print_hexdump_line, UTF_CONSOLE);
 
 static int print_do_hex_dump(struct unit_test_state *uts)
 {
@@ -350,7 +349,7 @@
 
 	return 0;
 }
-PRINT_TEST(print_do_hex_dump, UTF_CONSOLE);
+COMMON_TEST(print_do_hex_dump, UTF_CONSOLE);
 
 static int snprint(struct unit_test_state *uts)
 {
@@ -376,12 +375,4 @@
 	ut_asserteq(8, ret);
 	return 0;
 }
-PRINT_TEST(snprint, 0);
-
-int do_ut_print(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
-	struct unit_test *tests = UNIT_TEST_SUITE_START(print_test);
-	const int n_ents = UNIT_TEST_SUITE_COUNT(print_test);
-
-	return cmd_ut_category("print", "print_", tests, n_ents, argc, argv);
-}
+COMMON_TEST(snprint, 0);
diff --git a/test/dm/core.c b/test/dm/core.c
index 7371d3f..c59ffc6 100644
--- a/test/dm/core.c
+++ b/test/dm/core.c
@@ -999,6 +999,56 @@
 }
 DM_TEST(dm_test_remove_vital, 0);
 
+/* Test removal of 'active' devices */
+static int dm_test_remove_active(struct unit_test_state *uts)
+{
+	struct udevice *normal, *dma, *vital, *dma_vital;
+
+	/* Skip the behaviour in test_post_probe() */
+	uts->skip_post_probe = 1;
+
+	ut_assertok(device_bind_by_name(uts->root, false, &driver_info_manual,
+					&normal));
+	ut_assertnonnull(normal);
+
+	ut_assertok(device_bind_by_name(uts->root, false, &driver_info_act_dma,
+					&dma));
+	ut_assertnonnull(dma);
+
+	ut_assertok(device_bind_by_name(uts->root, false,
+					&driver_info_vital_clk, &vital));
+	ut_assertnonnull(vital);
+
+	ut_assertok(device_bind_by_name(uts->root, false,
+					&driver_info_act_dma_vital_clk,
+					&dma_vital));
+	ut_assertnonnull(dma_vital);
+
+	/* Probe the devices */
+	ut_assertok(device_probe(normal));
+	ut_assertok(device_probe(dma));
+	ut_assertok(device_probe(vital));
+	ut_assertok(device_probe(dma_vital));
+
+	/* Check that devices are active right now */
+	ut_asserteq(true, device_active(normal));
+	ut_asserteq(true, device_active(dma));
+	ut_asserteq(true, device_active(vital));
+	ut_asserteq(true, device_active(dma_vital));
+
+	/* Remove active devices in an ordered way */
+	dm_remove_devices_active();
+
+	/* Check that all devices are inactive right now */
+	ut_asserteq(true, device_active(normal));
+	ut_asserteq(false, device_active(dma));
+	ut_asserteq(true, device_active(vital));
+	ut_asserteq(false, device_active(dma_vital));
+
+	return 0;
+}
+DM_TEST(dm_test_remove_active, 0);
+
 static int dm_test_uclass_before_ready(struct unit_test_state *uts)
 {
 	struct uclass *uc;
diff --git a/test/lib/Makefile b/test/lib/Makefile
index a54387a..f516d00 100644
--- a/test/lib/Makefile
+++ b/test/lib/Makefile
@@ -2,6 +2,9 @@
 #
 # (C) Copyright 2018
 # Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+
+obj-$(CONFIG_$(XPL_)UT_COMPRESSION) += compression.o
+
 ifeq ($(CONFIG_XPL_BUILD),)
 obj-y += cmd_ut_lib.o
 obj-y += abuf.o
@@ -11,9 +14,10 @@
 obj-y += hexdump.o
 obj-$(CONFIG_SANDBOX) += kconfig.o
 obj-y += lmb.o
-obj-y += longjmp.o
+obj-$(CONFIG_HAVE_SETJMP) += longjmp.o
 obj-$(CONFIG_CONSOLE_RECORD) += test_print.o
 obj-$(CONFIG_SSCANF) += sscanf.o
+obj-$(CONFIG_$(XPL_)CMDLINE) += str.o
 obj-y += string.o
 obj-y += strlcat.o
 obj-$(CONFIG_ERRNO_STR) += test_errno_str.o
@@ -23,6 +27,8 @@
 obj-$(CONFIG_GETOPT) += getopt.o
 obj-$(CONFIG_CRC8) += test_crc8.o
 obj-$(CONFIG_UT_LIB_CRYPT) += test_crypt.o
+obj-$(CONFIG_UT_TIME) += time.o
+obj-$(CONFIG_$(XPL_)UT_UNICODE) += unicode.o
 obj-$(CONFIG_LIB_UUID) += uuid.o
 else
 obj-$(CONFIG_SANDBOX) += kconfig_spl.o
diff --git a/test/compression.c b/test/lib/compression.c
similarity index 94%
rename from test/compression.c
rename to test/lib/compression.c
index 618a193..31b6e5b 100644
--- a/test/compression.c
+++ b/test/lib/compression.c
@@ -23,8 +23,7 @@
 
 #include <linux/lzo.h>
 #include <linux/zstd.h>
-#include <test/compression.h>
-#include <test/suites.h>
+#include <test/lib.h>
 #include <test/ut.h>
 
 static const char plain[] =
@@ -471,40 +470,40 @@
 	return run_test(uts, "gzip", compress_using_gzip,
 			uncompress_using_gzip);
 }
-COMPRESSION_TEST(compression_test_gzip, 0);
+LIB_TEST(compression_test_gzip, 0);
 
 static int compression_test_bzip2(struct unit_test_state *uts)
 {
 	return run_test(uts, "bzip2", compress_using_bzip2,
 			uncompress_using_bzip2);
 }
-COMPRESSION_TEST(compression_test_bzip2, 0);
+LIB_TEST(compression_test_bzip2, 0);
 
 static int compression_test_lzma(struct unit_test_state *uts)
 {
 	return run_test(uts, "lzma", compress_using_lzma,
 			uncompress_using_lzma);
 }
-COMPRESSION_TEST(compression_test_lzma, 0);
+LIB_TEST(compression_test_lzma, 0);
 
 static int compression_test_lzo(struct unit_test_state *uts)
 {
 	return run_test(uts, "lzo", compress_using_lzo, uncompress_using_lzo);
 }
-COMPRESSION_TEST(compression_test_lzo, 0);
+LIB_TEST(compression_test_lzo, 0);
 
 static int compression_test_lz4(struct unit_test_state *uts)
 {
 	return run_test(uts, "lz4", compress_using_lz4, uncompress_using_lz4);
 }
-COMPRESSION_TEST(compression_test_lz4, 0);
+LIB_TEST(compression_test_lz4, 0);
 
 static int compression_test_zstd(struct unit_test_state *uts)
 {
 	return run_test(uts, "zstd", compress_using_zstd,
 			uncompress_using_zstd);
 }
-COMPRESSION_TEST(compression_test_zstd, 0);
+LIB_TEST(compression_test_zstd, 0);
 
 static int compress_using_none(struct unit_test_state *uts,
 			       void *in, unsigned long in_size,
@@ -570,50 +569,40 @@
 {
 	return run_bootm_test(uts, IH_COMP_GZIP, compress_using_gzip);
 }
-COMPRESSION_TEST(compression_test_bootm_gzip, 0);
+LIB_TEST(compression_test_bootm_gzip, 0);
 
 static int compression_test_bootm_bzip2(struct unit_test_state *uts)
 {
 	return run_bootm_test(uts, IH_COMP_BZIP2, compress_using_bzip2);
 }
-COMPRESSION_TEST(compression_test_bootm_bzip2, 0);
+LIB_TEST(compression_test_bootm_bzip2, 0);
 
 static int compression_test_bootm_lzma(struct unit_test_state *uts)
 {
 	return run_bootm_test(uts, IH_COMP_LZMA, compress_using_lzma);
 }
-COMPRESSION_TEST(compression_test_bootm_lzma, 0);
+LIB_TEST(compression_test_bootm_lzma, 0);
 
 static int compression_test_bootm_lzo(struct unit_test_state *uts)
 {
 	return run_bootm_test(uts, IH_COMP_LZO, compress_using_lzo);
 }
-COMPRESSION_TEST(compression_test_bootm_lzo, 0);
+LIB_TEST(compression_test_bootm_lzo, 0);
 
 static int compression_test_bootm_lz4(struct unit_test_state *uts)
 {
 	return run_bootm_test(uts, IH_COMP_LZ4, compress_using_lz4);
 }
-COMPRESSION_TEST(compression_test_bootm_lz4, 0);
+LIB_TEST(compression_test_bootm_lz4, 0);
 
 static int compression_test_bootm_zstd(struct unit_test_state *uts)
 {
 	return run_bootm_test(uts, IH_COMP_ZSTD, compress_using_zstd);
 }
-COMPRESSION_TEST(compression_test_bootm_zstd, 0);
+LIB_TEST(compression_test_bootm_zstd, 0);
 
 static int compression_test_bootm_none(struct unit_test_state *uts)
 {
 	return run_bootm_test(uts, IH_COMP_NONE, compress_using_none);
 }
-COMPRESSION_TEST(compression_test_bootm_none, 0);
-
-int do_ut_compression(struct cmd_tbl *cmdtp, int flag, int argc,
-		      char *const argv[])
-{
-	struct unit_test *tests = UNIT_TEST_SUITE_START(compression_test);
-	const int n_ents = UNIT_TEST_SUITE_COUNT(compression_test);
-
-	return cmd_ut_category("compression", "compression_test_",
-			       tests, n_ents, argc, argv);
-}
+LIB_TEST(compression_test_bootm_none, 0);
diff --git a/test/str_ut.c b/test/lib/str.c
similarity index 90%
rename from test/str_ut.c
rename to test/lib/str.c
index 96e0489..e620453 100644
--- a/test/str_ut.c
+++ b/test/lib/str.c
@@ -4,7 +4,7 @@
  */
 
 #include <vsprintf.h>
-#include <test/suites.h>
+#include <test/lib.h>
 #include <test/test.h>
 #include <test/ut.h>
 
@@ -18,9 +18,8 @@
 static const char str5[] = "0x9876543210the last time I was deloused";
 static const char str6[] = "0778octal is seldom used";
 static const char str7[] = "707it is a piece of computing history";
-
-/* Declare a new str test */
-#define STR_TEST(_name, _flags)		UNIT_TEST(_name, _flags, str_test)
+static const char str8[] = "0x887e2561352d80fa";
+static const char str9[] = "614FF7EAA63009DA";
 
 static int str_upper(struct unit_test_state *uts)
 {
@@ -58,7 +57,7 @@
 
 	return 0;
 }
-STR_TEST(str_upper, 0);
+LIB_TEST(str_upper, 0);
 
 static int run_strtoul(struct unit_test_state *uts, const char *str, int base,
 		       ulong expect_val, int expect_endp_offset, bool upper)
@@ -112,7 +111,7 @@
 
 	return 0;
 }
-STR_TEST(str_simple_strtoul, 0);
+LIB_TEST(str_simple_strtoul, 0);
 
 static int run_strtoull(struct unit_test_state *uts, const char *str, int base,
 			unsigned long long expect_val, int expect_endp_offset,
@@ -175,7 +174,7 @@
 
 	return 0;
 }
-STR_TEST(str_simple_strtoull, 0);
+LIB_TEST(str_simple_strtoull, 0);
 
 static int str_hextoul(struct unit_test_state *uts)
 {
@@ -187,7 +186,23 @@
 
 	return 0;
 }
+LIB_TEST(str_hextoul, 0);
+
+static int str_hextoull(struct unit_test_state *uts)
+{
+	char *endp;
+
+	/* Just a simple test, since we know this uses simple_strtoull() */
+	ut_asserteq_64(0x887e2561352d80faULL, hextoull(str8, &endp));
+	ut_asserteq_64(0x12, endp - str8);
+	ut_asserteq_64(0x614ff7eaa63009daULL, hextoull(str9, &endp));
+	ut_asserteq_64(0x10, endp - str9);
+	ut_asserteq_64(0x887e2561352d80faULL, hextoull(str8, NULL));
+	ut_asserteq_64(0x614ff7eaa63009daULL, hextoull(str9, NULL));
+
+	return 0;
+}
-STR_TEST(str_hextoul, 0);
+LIB_TEST(str_hextoull, 0);
 
 static int str_dectoul(struct unit_test_state *uts)
 {
@@ -199,7 +214,7 @@
 
 	return 0;
 }
-STR_TEST(str_dectoul, 0);
+LIB_TEST(str_dectoul, 0);
 
 static int str_itoa(struct unit_test_state *uts)
 {
@@ -219,7 +234,7 @@
 
 	return 0;
 }
-STR_TEST(str_itoa, 0);
+LIB_TEST(str_itoa, 0);
 
 static int str_xtoa(struct unit_test_state *uts)
 {
@@ -239,7 +254,7 @@
 
 	return 0;
 }
-STR_TEST(str_xtoa, 0);
+LIB_TEST(str_xtoa, 0);
 
 static int str_trailing(struct unit_test_state *uts)
 {
@@ -271,7 +286,7 @@
 
 	return 0;
 }
-STR_TEST(str_trailing, 0);
+LIB_TEST(str_trailing, 0);
 
 static int test_str_to_list(struct unit_test_state *uts)
 {
@@ -351,12 +366,4 @@
 
 	return 0;
 }
-STR_TEST(test_str_to_list, 0);
-
-int do_ut_str(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
-	struct unit_test *tests = UNIT_TEST_SUITE_START(str_test);
-	const int n_ents = UNIT_TEST_SUITE_COUNT(str_test);
-
-	return cmd_ut_category("str", "str_", tests, n_ents, argc, argv);
-}
+LIB_TEST(test_str_to_list, 0);
diff --git a/test/time_ut.c b/test/lib/time.c
similarity index 82%
rename from test/time_ut.c
rename to test/lib/time.c
index 149c4b5..2095bef 100644
--- a/test/time_ut.c
+++ b/test/lib/time.c
@@ -4,12 +4,13 @@
  * Written by Simon Glass <sjg@chromium.org>
  */
 
-#include <command.h>
 #include <errno.h>
 #include <time.h>
 #include <linux/delay.h>
+#include <test/lib.h>
+#include <test/ut.h>
 
-static int test_get_timer(void)
+static int test_get_timer(struct unit_test_state *uts)
 {
 	ulong base, start, next, diff;
 	int iter;
@@ -42,8 +43,9 @@
 
 	return 0;
 }
+LIB_TEST(test_get_timer, 0);
 
-static int test_timer_get_us(void)
+static int test_timer_get_us(struct unit_test_state *uts)
 {
 	ulong prev, next, min = 1000000;
 	long delta;
@@ -76,8 +78,9 @@
 
 	return 0;
 }
+LIB_TEST(test_timer_get_us, 0);
 
-static int test_time_comparison(void)
+static int test_time_comparison(struct unit_test_state *uts)
 {
 	ulong start_us, end_us, delta_us;
 	long error;
@@ -97,8 +100,9 @@
 
 	return 0;
 }
+LIB_TEST(test_time_comparison, 0);
 
-static int test_udelay(void)
+static int test_udelay(struct unit_test_state *uts)
 {
 	long error;
 	ulong start, delta;
@@ -116,17 +120,4 @@
 
 	return 0;
 }
-
-int do_ut_time(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
-	int ret = 0;
-
-	ret |= test_get_timer();
-	ret |= test_timer_get_us();
-	ret |= test_time_comparison();
-	ret |= test_udelay();
-
-	printf("Test %s\n", ret ? "failed" : "passed");
-
-	return ret ? CMD_RET_FAILURE : CMD_RET_SUCCESS;
-}
+LIB_TEST(test_udelay, 0);
diff --git a/test/unicode_ut.c b/test/lib/unicode.c
similarity index 92%
rename from test/unicode_ut.c
rename to test/lib/unicode.c
index 13e29c9..673470c 100644
--- a/test/unicode_ut.c
+++ b/test/lib/unicode.c
@@ -11,13 +11,10 @@
 #include <errno.h>
 #include <log.h>
 #include <malloc.h>
+#include <test/lib.h>
 #include <test/test.h>
-#include <test/suites.h>
 #include <test/ut.h>
 
-/* Linker list entry for a Unicode test */
-#define UNICODE_TEST(_name) UNIT_TEST(_name, 0, unicode_test)
-
 /* Constants c1-c4 and d1-d4 encode the same letters */
 
 /* Six characters translating to one utf-8 byte each. */
@@ -64,7 +61,7 @@
 	ut_asserteq(6, u16_strlen(c4));
 	return 0;
 }
-UNICODE_TEST(unicode_test_u16_strlen);
+LIB_TEST(unicode_test_u16_strlen, 0);
 
 static int unicode_test_u16_strnlen(struct unit_test_state *uts)
 {
@@ -75,7 +72,7 @@
 
 	return 0;
 }
-UNICODE_TEST(unicode_test_u16_strnlen);
+LIB_TEST(unicode_test_u16_strnlen, 0);
 
 static int unicode_test_u16_strdup(struct unit_test_state *uts)
 {
@@ -87,7 +84,7 @@
 
 	return 0;
 }
-UNICODE_TEST(unicode_test_u16_strdup);
+LIB_TEST(unicode_test_u16_strdup, 0);
 
 static int unicode_test_u16_strcpy(struct unit_test_state *uts)
 {
@@ -100,7 +97,7 @@
 
 	return 0;
 }
-UNICODE_TEST(unicode_test_u16_strcpy);
+LIB_TEST(unicode_test_u16_strcpy, 0);
 
 /* U-Boot uses UTF-16 strings in the EFI context only. */
 #if CONFIG_IS_ENABLED(EFI_LOADER) && !defined(API_BUILD)
@@ -173,7 +170,7 @@
 
 	return 0;
 }
-UNICODE_TEST(unicode_test_string16);
+LIB_TEST(unicode_test_string16, 0);
 #endif
 
 static int unicode_test_utf8_get(struct unit_test_state *uts)
@@ -218,7 +215,7 @@
 
 	return 0;
 }
-UNICODE_TEST(unicode_test_utf8_get);
+LIB_TEST(unicode_test_utf8_get, 0);
 
 static int unicode_test_utf8_put(struct unit_test_state *uts)
 {
@@ -256,7 +253,7 @@
 
 	return 0;
 }
-UNICODE_TEST(unicode_test_utf8_put);
+LIB_TEST(unicode_test_utf8_put, 0);
 
 static int unicode_test_utf8_utf16_strlen(struct unit_test_state *uts)
 {
@@ -272,7 +269,7 @@
 
 	return 0;
 }
-UNICODE_TEST(unicode_test_utf8_utf16_strlen);
+LIB_TEST(unicode_test_utf8_utf16_strlen, 0);
 
 static int unicode_test_utf8_utf16_strnlen(struct unit_test_state *uts)
 {
@@ -290,7 +287,7 @@
 
 	return 0;
 }
-UNICODE_TEST(unicode_test_utf8_utf16_strnlen);
+LIB_TEST(unicode_test_utf8_utf16_strnlen, 0);
 
 /**
  * ut_u16_strcmp() - Compare to u16 strings.
@@ -354,7 +351,7 @@
 
 	return 0;
 }
-UNICODE_TEST(unicode_test_utf8_utf16_strcpy);
+LIB_TEST(unicode_test_utf8_utf16_strcpy, 0);
 
 static int unicode_test_utf8_utf16_strncpy(struct unit_test_state *uts)
 {
@@ -398,7 +395,7 @@
 
 	return 0;
 }
-UNICODE_TEST(unicode_test_utf8_utf16_strncpy);
+LIB_TEST(unicode_test_utf8_utf16_strncpy, 0);
 
 static int unicode_test_utf16_get(struct unit_test_state *uts)
 {
@@ -424,7 +421,7 @@
 
 	return 0;
 }
-UNICODE_TEST(unicode_test_utf16_get);
+LIB_TEST(unicode_test_utf16_get, 0);
 
 static int unicode_test_utf16_put(struct unit_test_state *uts)
 {
@@ -452,7 +449,7 @@
 
 	return 0;
 }
-UNICODE_TEST(unicode_test_utf16_put);
+LIB_TEST(unicode_test_utf16_put, 0);
 
 static int unicode_test_utf16_strnlen(struct unit_test_state *uts)
 {
@@ -470,7 +467,7 @@
 
 	return 0;
 }
-UNICODE_TEST(unicode_test_utf16_strnlen);
+LIB_TEST(unicode_test_utf16_strnlen, 0);
 
 static int unicode_test_utf16_utf8_strlen(struct unit_test_state *uts)
 {
@@ -486,7 +483,7 @@
 
 	return 0;
 }
-UNICODE_TEST(unicode_test_utf16_utf8_strlen);
+LIB_TEST(unicode_test_utf16_utf8_strlen, 0);
 
 static int unicode_test_utf16_utf8_strnlen(struct unit_test_state *uts)
 {
@@ -498,7 +495,7 @@
 	ut_asserteq(12, utf16_utf8_strnlen(c4, 3));
 	return 0;
 }
-UNICODE_TEST(unicode_test_utf16_utf8_strnlen);
+LIB_TEST(unicode_test_utf16_utf8_strnlen, 0);
 
 static int unicode_test_utf16_utf8_strcpy(struct unit_test_state *uts)
 {
@@ -543,7 +540,7 @@
 
 	return 0;
 }
-UNICODE_TEST(unicode_test_utf16_utf8_strcpy);
+LIB_TEST(unicode_test_utf16_utf8_strcpy, 0);
 
 static int unicode_test_utf16_utf8_strncpy(struct unit_test_state *uts)
 {
@@ -587,7 +584,7 @@
 
 	return 0;
 }
-UNICODE_TEST(unicode_test_utf16_utf8_strncpy);
+LIB_TEST(unicode_test_utf16_utf8_strncpy, 0);
 
 static int unicode_test_utf_to_lower(struct unit_test_state *uts)
 {
@@ -604,7 +601,7 @@
 #endif
 	return 0;
 }
-UNICODE_TEST(unicode_test_utf_to_lower);
+LIB_TEST(unicode_test_utf_to_lower, 0);
 
 static int unicode_test_utf_to_upper(struct unit_test_state *uts)
 {
@@ -621,7 +618,7 @@
 #endif
 	return 0;
 }
-UNICODE_TEST(unicode_test_utf_to_upper);
+LIB_TEST(unicode_test_utf_to_upper, 0);
 
 static int unicode_test_u16_strcasecmp(struct unit_test_state *uts)
 {
@@ -646,7 +643,7 @@
 
 	return 0;
 }
-UNICODE_TEST(unicode_test_u16_strcasecmp);
+LIB_TEST(unicode_test_u16_strcasecmp, 0);
 
 static int unicode_test_u16_strncmp(struct unit_test_state *uts)
 {
@@ -659,7 +656,7 @@
 	ut_assert(u16_strcmp(u"deghi", u"abcdef") > 0);
 	return 0;
 }
-UNICODE_TEST(unicode_test_u16_strncmp);
+LIB_TEST(unicode_test_u16_strncmp, 0);
 
 static int unicode_test_u16_strsize(struct unit_test_state *uts)
 {
@@ -669,7 +666,7 @@
 	ut_asserteq_64(u16_strsize(c4), 14);
 	return 0;
 }
-UNICODE_TEST(unicode_test_u16_strsize);
+LIB_TEST(unicode_test_u16_strsize, 0);
 
 static int unicode_test_utf_to_cp(struct unit_test_state *uts)
 {
@@ -698,7 +695,7 @@
 
 	return 0;
 }
-UNICODE_TEST(unicode_test_utf_to_cp);
+LIB_TEST(unicode_test_utf_to_cp, 0);
 
 static void utf8_to_cp437_stream_helper(const char *in, char *out)
 {
@@ -729,7 +726,7 @@
 
 	return 0;
 }
-UNICODE_TEST(unicode_test_utf8_to_cp437_stream);
+LIB_TEST(unicode_test_utf8_to_cp437_stream, 0);
 
 static void utf8_to_utf32_stream_helper(const char *in, s32 *out)
 {
@@ -778,7 +775,7 @@
 
 	return 0;
 }
-UNICODE_TEST(unicode_test_utf8_to_utf32_stream);
+LIB_TEST(unicode_test_utf8_to_utf32_stream, 0);
 
 #ifdef CONFIG_EFI_LOADER
 static int unicode_test_efi_create_indexed_name(struct unit_test_state *uts)
@@ -795,7 +792,7 @@
 
 	return 0;
 }
-UNICODE_TEST(unicode_test_efi_create_indexed_name);
+LIB_TEST(unicode_test_efi_create_indexed_name, 0);
 #endif
 
 static int unicode_test_u16_strlcat(struct unit_test_state *uts)
@@ -846,13 +843,4 @@
 
 	return 0;
 }
-UNICODE_TEST(unicode_test_u16_strlcat);
-
-int do_ut_unicode(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
-	struct unit_test *tests = UNIT_TEST_SUITE_START(unicode_test);
-	const int n_ents = UNIT_TEST_SUITE_COUNT(unicode_test);
-
-	return cmd_ut_category("Unicode", "unicode_test_",
-			       tests, n_ents, argc, argv);
-}
+LIB_TEST(unicode_test_u16_strlcat, 0);
diff --git a/test/py/conftest.py b/test/py/conftest.py
index 46a410c..d9f074f 100644
--- a/test/py/conftest.py
+++ b/test/py/conftest.py
@@ -23,6 +23,7 @@
 import pytest
 import re
 from _pytest.runner import runtestprotocol
+import subprocess
 import sys
 from u_boot_spawn import BootFail, Timeout, Unexpected, handle_exception
 
@@ -65,12 +66,16 @@
 
     parser.addoption('--build-dir', default=None,
         help='U-Boot build directory (O=)')
+    parser.addoption('--build-dir-extra', default=None,
+        help='U-Boot build directory for extra build (O=)')
     parser.addoption('--result-dir', default=None,
         help='U-Boot test result/tmp directory')
     parser.addoption('--persistent-data-dir', default=None,
         help='U-Boot test persistent generated data directory')
     parser.addoption('--board-type', '--bd', '-B', default='sandbox',
         help='U-Boot board type')
+    parser.addoption('--board-type-extra', '--bde', default='sandbox',
+        help='U-Boot extra board type')
     parser.addoption('--board-identity', '--id', default='na',
         help='U-Boot board identity/instance')
     parser.addoption('--build', default=False, action='store_true',
@@ -80,6 +85,9 @@
     parser.addoption('--gdbserver', default=None,
         help='Run sandbox under gdbserver. The argument is the channel '+
         'over which gdbserver should communicate, e.g. localhost:1234')
+    parser.addoption('--role', help='U-Boot board role (for Labgrid-sjg)')
+    parser.addoption('--use-running-system', default=False, action='store_true',
+        help="Assume that U-Boot is ready and don't wait for a prompt")
 
 def run_build(config, source_dir, build_dir, board_type, log):
     """run_build: Build U-Boot
@@ -125,26 +133,71 @@
     Returns:
         tuple:
             str: Board type (U-Boot build name)
+            str: Extra board type (where two U-Boot builds are needed)
             str: Identity for the lab board
             str: Build directory
+            str: Extra build directory (where two U-Boot builds are needed)
             str: Source directory
     """
-    board_type = config.getoption('board_type')
-    board_identity = config.getoption('board_identity')
+    role = config.getoption('role')
+
+    # Get a few provided parameters
     build_dir = config.getoption('build_dir')
+    build_dir_extra = config.getoption('build_dir_extra')
+    if role:
+        # When using a role, build_dir and build_dir_extra are normally not set,
+        # since they are picked up from Labgrid-sjg via the u-boot-test-getrole
+        # script
+        board_identity = role
+        cmd = ['u-boot-test-getrole', role, '--configure']
+        env = os.environ.copy()
+        if build_dir:
+            env['U_BOOT_BUILD_DIR'] = build_dir
+        if build_dir_extra:
+            env['U_BOOT_BUILD_DIR_EXTRA'] = build_dir_extra
+        proc = subprocess.run(cmd, capture_output=True, encoding='utf-8',
+                              env=env)
+        if proc.returncode:
+            raise ValueError(proc.stderr)
+        # For debugging
+        # print('conftest: lab:', proc.stdout)
+        vals = {}
+        for line in proc.stdout.splitlines():
+            item, value = line.split(' ', maxsplit=1)
+            k = item.split(':')[-1]
+            vals[k] = value
+        # For debugging
+        # print('conftest: lab info:', vals)
+
+        # Read the build directories here, in case none were provided in the
+        # command-line arguments
+        (board_type, board_type_extra, default_build_dir,
+         default_build_dir_extra, source_dir) = (vals['board'],
+            vals['board_extra'], vals['build_dir'], vals['build_dir_extra'],
+            vals['source_dir'])
+    else:
+        board_type = config.getoption('board_type')
+        board_type_extra = config.getoption('board_type_extra')
+        board_identity = config.getoption('board_identity')
+
+        source_dir = os.path.dirname(os.path.dirname(TEST_PY_DIR))
+        default_build_dir = source_dir + '/build-' + board_type
+        default_build_dir_extra = source_dir + '/build-' + board_type_extra
 
-    source_dir = os.path.dirname(os.path.dirname(TEST_PY_DIR))
-    default_build_dir = source_dir + '/build-' + board_type
+    # Use the provided command-line arguments if present, else fall back to
     if not build_dir:
         build_dir = default_build_dir
+    if not build_dir_extra:
+        build_dir_extra = default_build_dir_extra
 
-    return board_type, board_identity, build_dir, source_dir
+    return (board_type, board_type_extra, board_identity, build_dir,
+            build_dir_extra, source_dir)
 
 def pytest_xdist_setupnodes(config, specs):
     """Clear out any 'done' file from a previous build"""
     global build_done_file
 
-    build_dir = get_details(config)[2]
+    build_dir = get_details(config)[3]
 
     build_done_file = Path(build_dir) / 'build.done'
     if build_done_file.exists():
@@ -184,7 +237,8 @@
     global console
     global ubconfig
 
-    board_type, board_identity, build_dir, source_dir = get_details(config)
+    (board_type, board_type_extra, board_identity, build_dir, build_dir_extra,
+     source_dir) = get_details(config)
 
     board_type_filename = board_type.replace('-', '_')
     board_identity_filename = board_identity.replace('-', '_')
@@ -249,20 +303,25 @@
     ubconfig.test_py_dir = TEST_PY_DIR
     ubconfig.source_dir = source_dir
     ubconfig.build_dir = build_dir
+    ubconfig.build_dir_extra = build_dir_extra
     ubconfig.result_dir = result_dir
     ubconfig.persistent_data_dir = persistent_data_dir
     ubconfig.board_type = board_type
+    ubconfig.board_type_extra = board_type_extra
     ubconfig.board_identity = board_identity
     ubconfig.gdbserver = gdbserver
+    ubconfig.use_running_system = config.getoption('use_running_system')
     ubconfig.dtb = build_dir + '/arch/sandbox/dts/test.dtb'
     ubconfig.connection_ok = True
 
     env_vars = (
         'board_type',
+        'board_type_extra',
         'board_identity',
         'source_dir',
         'test_py_dir',
         'build_dir',
+        'build_dir_extra',
         'result_dir',
         'persistent_data_dir',
     )
diff --git a/test/py/tests/test_spi.py b/test/py/tests/test_spi.py
index caca930..0abdfa7 100644
--- a/test/py/tests/test_spi.py
+++ b/test/py/tests/test_spi.py
@@ -75,7 +75,7 @@
     ''' Get SPI device test parameters from boardenv file '''
     f = u_boot_console.config.env.get('env__spi_device_test', None)
     if not f:
-        pytest.skip('No env file to read for SPI family device test')
+        pytest.skip('No SPI test device configured')
 
     bus = f.get('bus', 0)
     cs = f.get('chip_select', 0)
@@ -84,7 +84,7 @@
     timeout = f.get('timeout', None)
 
     if not part_name:
-        pytest.skip('No env file to read SPI family flash part name')
+        pytest.skip('No SPI test device configured')
 
     return bus, cs, mode, part_name, timeout
 
@@ -92,7 +92,7 @@
     '''Find out minimum and maximum frequnecies that SPI device can operate'''
     f = u_boot_console.config.env.get('env__spi_device_test', None)
     if not f:
-        pytest.skip('No env file to read for SPI family device test')
+        pytest.skip('No SPI test device configured')
 
     min_f = f.get('min_freq', None)
     max_f = f.get('max_freq', None)
@@ -116,21 +116,21 @@
         pytest.fail('No SPI device available')
 
     if not part_name in output:
-        pytest.fail('SPI flash part name not recognized')
+        pytest.fail('Not recognized the SPI flash part name')
 
     m = re.search('page size (.+?) Bytes', output)
     if m:
         try:
             page_size = int(m.group(1))
         except ValueError:
-            pytest.fail('SPI page size not recognized')
+            pytest.fail('Not recognized the SPI page size')
 
     m = re.search('erase size (.+?) KiB', output)
     if m:
         try:
             erase_size = int(m.group(1))
         except ValueError:
-            pytest.fail('SPI erase size not recognized')
+            pytest.fail('Not recognized the SPI erase size')
 
         erase_size *= 1024
 
@@ -139,7 +139,7 @@
         try:
             total_size = int(m.group(1))
         except ValueError:
-            pytest.fail('SPI total size not recognized')
+            pytest.fail('Not recognized the SPI total size')
 
         total_size *= 1024 * 1024
 
@@ -149,7 +149,7 @@
             flash_part = m.group(1)
             assert flash_part == part_name
         except ValueError:
-            pytest.fail('SPI flash part not recognized')
+            pytest.fail('Not recognized the SPI flash part')
 
     global SPI_DATA
     SPI_DATA = {
@@ -574,7 +574,7 @@
     min_f, max_f, loop = spi_find_freq_range(u_boot_console)
     flashes = u_boot_console.config.env.get('env__spi_lock_unlock', False)
     if not flashes:
-        pytest.skip('No supported flash list for lock/unlock provided')
+        pytest.skip('No SPI test device configured for lock/unlock')
 
     i = 0
     while i < loop:
@@ -695,7 +695,7 @@
 
         # Read to relocation address
         output = u_boot_console.run_command('bdinfo')
-        m = re.search('relocaddr\s*= (.+)', output)
+        m = re.search(r'relocaddr\s*= (.+)', output)
         res_area = int(m.group(1), 16)
 
         start = 0
diff --git a/test/py/tests/test_ut.py b/test/py/tests/test_ut.py
index 9b6b6b2..10ec7e5 100644
--- a/test/py/tests/test_ut.py
+++ b/test/py/tests/test_ut.py
@@ -442,6 +442,55 @@
 
     print(f'wrote to {fname}')
 
+    mmc_dev = 8
+    fname = os.path.join(cons.config.source_dir, f'mmc{mmc_dev}.img')
+    u_boot_utils.run_and_log(cons, f'qemu-img create {fname} 20M')
+    u_boot_utils.run_and_log(cons, f'cgpt create {fname}')
+
+    ptr = 40
+
+    # Number of sectors in 1MB
+    sect_size = 512
+    sect_1mb = (1 << 20) // sect_size
+
+    required_parts = [
+        {'num': 1, 'label':'misc', 'size': '1M'},
+        {'num': 2, 'label':'boot_a', 'size': '4M'},
+        {'num': 3, 'label':'boot_b', 'size': '4M'},
+    ]
+
+    for part in required_parts:
+        size_str = part['size']
+        if 'M' in size_str:
+            size = int(size_str[:-1]) * sect_1mb
+        else:
+            size = int(size_str)
+        u_boot_utils.run_and_log(
+            cons,
+            f"cgpt add -i {part['num']} -b {ptr} -s {size} -l {part['label']} -t basicdata {fname}")
+        ptr += size
+
+    u_boot_utils.run_and_log(cons, f'cgpt boot -p {fname}')
+    out = u_boot_utils.run_and_log(cons, f'cgpt show -q {fname}')
+
+    # Create a dict (indexed by partition number) containing the above info
+    for line in out.splitlines():
+        start, size, num, name = line.split(maxsplit=3)
+        parts[int(num)] = Partition(int(start), int(size), name)
+
+    with open(fname, 'rb') as inf:
+        disk_data = inf.read()
+
+    test_abootimg.AbootimgTestDiskImage(cons, 'boot.img', test_abootimg.img_hex)
+    boot_img = os.path.join(cons.config.result_dir, 'boot.img')
+    with open(boot_img, 'rb') as inf:
+        set_part_data(2, inf.read())
+
+    with open(fname, 'wb') as outf:
+        outf.write(disk_data)
+
+    print(f'wrote to {fname}')
+
     return fname
 
 def setup_cedit_file(cons):
diff --git a/test/py/u_boot_console_base.py b/test/py/u_boot_console_base.py
index d8d0bdf..fa9cd57 100644
--- a/test/py/u_boot_console_base.py
+++ b/test/py/u_boot_console_base.py
@@ -23,12 +23,22 @@
 pattern_unknown_command = re.compile('Unknown command \'.*\' - try \'help\'')
 pattern_error_notification = re.compile('## Error: ')
 pattern_error_please_reset = re.compile('### ERROR ### Please RESET the board ###')
+pattern_ready_prompt = re.compile('{lab ready in (.*)s: (.*)}')
+pattern_lab_mode = re.compile('{lab mode.*}')
 
 PAT_ID = 0
 PAT_RE = 1
 
 # Timeout before expecting the console to be ready (in milliseconds)
-TIMEOUT_MS = 30000
+TIMEOUT_MS = 30000                  # Standard timeout
+TIMEOUT_CMD_MS = 10000              # Command-echo timeout
+
+# Timeout for board preparation in lab mode. This needs to be enough to build
+# U-Boot, write it to the board and then boot the board. Since this process is
+# under the control of another program (e.g. Labgrid), it will failure sooner
+# if something goes way. So use a very long timeout here to cover all possible
+# situations.
+TIMEOUT_PREPARE_MS = 3 * 60 * 1000
 
 bad_pattern_defs = (
     ('spl_signon', pattern_u_boot_spl_signon),
@@ -142,6 +152,7 @@
 
         self.at_prompt = False
         self.at_prompt_logevt = None
+        self.lab_mode = False
 
     def get_spawn(self):
         # This is not called, ssubclass must define this.
@@ -172,43 +183,75 @@
         """
 
         if self.p:
-            self.p.close()
+            self.log.start_section('Stopping U-Boot')
+            close_type = self.p.close()
+            self.log.info(f'Close type: {close_type}')
+            self.log.end_section('Stopping U-Boot')
         self.logstream.close()
 
+    def set_lab_mode(self):
+        """Select lab mode
+
+        This tells us that we will get a 'lab ready' message when the board is
+        ready for use. We don't need to look for signon messages.
+        """
+        self.log.info(f'test.py: Lab mode is active')
+        self.p.timeout = TIMEOUT_PREPARE_MS
+        self.lab_mode = True
+
     def wait_for_boot_prompt(self, loop_num = 1):
         """Wait for the boot up until command prompt. This is for internal use only.
         """
         try:
+            self.log.info('Waiting for U-Boot to be ready')
             bcfg = self.config.buildconfig
             config_spl_serial = bcfg.get('config_spl_serial', 'n') == 'y'
             env_spl_skipped = self.config.env.get('env__spl_skipped', False)
             env_spl_banner_times = self.config.env.get('env__spl_banner_times', 1)
 
-            while loop_num > 0:
+            while not self.lab_mode and loop_num > 0:
                 loop_num -= 1
                 while config_spl_serial and not env_spl_skipped and env_spl_banner_times > 0:
-                    m = self.p.expect([pattern_u_boot_spl_signon] +
-                                      self.bad_patterns)
-                    if m != 0:
+                    m = self.p.expect([pattern_u_boot_spl_signon,
+                                       pattern_lab_mode] + self.bad_patterns)
+                    if m == 1:
+                        self.set_lab_mode()
+                        break
+                    elif m != 0:
                         raise BootFail('Bad pattern found on SPL console: ' +
-                                        self.bad_pattern_ids[m - 1])
+                                       self.bad_pattern_ids[m - 1])
                     env_spl_banner_times -= 1
 
-                m = self.p.expect([pattern_u_boot_main_signon] + self.bad_patterns)
-                if m != 0:
-                    raise BootFail('Bad pattern found on console: ' +
-                                    self.bad_pattern_ids[m - 1])
-            self.u_boot_version_string = self.p.after
+                if not self.lab_mode:
+                    m = self.p.expect([pattern_u_boot_main_signon,
+                                       pattern_lab_mode] + self.bad_patterns)
+                    if m == 1:
+                        self.set_lab_mode()
+                    elif m != 0:
+                        raise BootFail('Bad pattern found on console: ' +
+                                       self.bad_pattern_ids[m - 1])
+            if not self.lab_mode:
+                self.u_boot_version_string = self.p.after
             while True:
-                m = self.p.expect([self.prompt_compiled,
+                m = self.p.expect([self.prompt_compiled, pattern_ready_prompt,
                     pattern_stop_autoboot_prompt] + self.bad_patterns)
                 if m == 0:
+                    self.log.info(f'Found ready prompt {m}')
                     break
-                if m == 1:
+                elif m == 1:
+                    m = pattern_ready_prompt.search(self.p.after)
+                    self.u_boot_version_string = m.group(2)
+                    self.log.info(f'Lab: Board is ready')
+                    self.p.timeout = TIMEOUT_MS
+                    break
+                if m == 2:
+                    self.log.info(f'Found autoboot prompt {m}')
                     self.p.send(' ')
                     continue
-                raise BootFail('Bad pattern found on console: ' +
-                                self.bad_pattern_ids[m - 2])
+                if not self.lab_mode:
+                    raise BootFail('Missing prompt / ready message on console: ' +
+                                   self.bad_pattern_ids[m - 3])
+            self.log.info(f'U-Boot is ready')
 
         finally:
             self.log.timestamp()
@@ -261,22 +304,28 @@
 
         try:
             self.at_prompt = False
+            if not self.p:
+                raise BootFail(
+                    f"Lab failure: Connection lost when sending command '{cmd}'")
+
             if send_nl:
                 cmd += '\n'
-            while cmd:
-                # Limit max outstanding data, so UART FIFOs don't overflow
-                chunk = cmd[:self.max_fifo_fill]
-                cmd = cmd[self.max_fifo_fill:]
-                self.p.send(chunk)
-                if not wait_for_echo:
-                    continue
-                chunk = re.escape(chunk)
-                chunk = chunk.replace('\\\n', '[\r\n]')
-                m = self.p.expect([chunk] + self.bad_patterns)
-                if m != 0:
-                    self.at_prompt = False
-                    raise BootFail('Bad pattern found on console: ' +
-                                    self.bad_pattern_ids[m - 1])
+            rem = cmd  # Remaining to be sent
+            with self.temporary_timeout(TIMEOUT_CMD_MS):
+                while rem:
+                    # Limit max outstanding data, so UART FIFOs don't overflow
+                    chunk = rem[:self.max_fifo_fill]
+                    rem = rem[self.max_fifo_fill:]
+                    self.p.send(chunk)
+                    if not wait_for_echo:
+                        continue
+                    chunk = re.escape(chunk)
+                    chunk = chunk.replace('\\\n', '[\r\n]')
+                    m = self.p.expect([chunk] + self.bad_patterns)
+                    if m != 0:
+                        self.at_prompt = False
+                        raise BootFail(f"Failed to get echo on console (cmd '{cmd}':rem '{rem}'): " +
+                                        self.bad_pattern_ids[m - 1])
             if not wait_for_prompt:
                 return
             if wait_for_reboot:
@@ -440,11 +489,17 @@
             if not self.config.gdbserver:
                 self.p.timeout = TIMEOUT_MS
             self.p.logfile_read = self.logstream
-            if expect_reset:
-                loop_num = 2
+            if self.config.use_running_system:
+                # Send an empty command to set up the 'expect' logic. This has
+                # the side effect of ensuring that there was no partial command
+                # line entered
+                self.run_command(' ')
             else:
-                loop_num = 1
-            self.wait_for_boot_prompt(loop_num = loop_num)
+                if expect_reset:
+                    loop_num = 2
+                else:
+                    loop_num = 1
+                self.wait_for_boot_prompt(loop_num = loop_num)
             self.at_prompt = True
             self.at_prompt_logevt = self.logstream.logfile.cur_evt
         except Exception as ex:
diff --git a/test/py/u_boot_console_exec_attach.py b/test/py/u_boot_console_exec_attach.py
index 8dd8cc1..8b253b4 100644
--- a/test/py/u_boot_console_exec_attach.py
+++ b/test/py/u_boot_console_exec_attach.py
@@ -59,14 +59,27 @@
         args = [self.config.board_type, self.config.board_identity]
         s = Spawn(['u-boot-test-console'] + args)
 
-        try:
-            self.log.action('Resetting board')
-            cmd = ['u-boot-test-reset'] + args
-            runner = self.log.get_runner(cmd[0], sys.stdout)
-            runner.run(cmd)
-            runner.close()
-        except:
-            s.close()
-            raise
+        if self.config.use_running_system:
+            self.log.action('Connecting to board without reset')
+        else:
+            try:
+                self.log.action('Resetting board')
+                cmd = ['u-boot-test-reset'] + args
+                runner = self.log.get_runner(cmd[0], sys.stdout)
+                runner.run(cmd)
+                runner.close()
+            except:
+                s.close()
+                raise
 
         return s
+
+    def close(self):
+        super().close()
+
+        self.log.action('Releasing board')
+        args = [self.config.board_type, self.config.board_identity]
+        cmd = ['u-boot-test-release'] + args
+        runner = self.log.get_runner(cmd[0], sys.stdout)
+        runner.run(cmd)
+        runner.close()
diff --git a/test/py/u_boot_spawn.py b/test/py/u_boot_spawn.py
index 24d3690..c703454 100644
--- a/test/py/u_boot_spawn.py
+++ b/test/py/u_boot_spawn.py
@@ -5,15 +5,21 @@
 Logic to spawn a sub-process and interact with its stdio.
 """
 
+import io
 import os
 import re
 import pty
 import pytest
 import signal
 import select
+import sys
+import termios
 import time
 import traceback
 
+# Character to send (twice) to exit the terminal
+EXIT_CHAR = 0x1d    # FS (Ctrl + ])
+
 class Timeout(Exception):
     """An exception sub-class that indicates that a timeout occurred."""
 
@@ -115,11 +121,30 @@
             finally:
                 os._exit(255)
 
+        old = None
         try:
+            isatty = False
+            try:
+                isatty = os.isatty(sys.stdout.fileno())
+
+            # with --capture=tee-sys we cannot call fileno()
+            except io.UnsupportedOperation as exc:
+                pass
+            if isatty:
+                new = termios.tcgetattr(self.fd)
+                old = new
+                new[3] = new[3] & ~(termios.ICANON | termios.ISIG)
+                new[3] = new[3] & ~termios.ECHO
+                new[6][termios.VMIN] = 0
+                new[6][termios.VTIME] = 0
+                termios.tcsetattr(self.fd, termios.TCSANOW, new)
+
             self.poll = select.poll()
             self.poll.register(self.fd, select.POLLIN | select.POLLPRI | select.POLLERR |
                                select.POLLHUP | select.POLLNVAL)
         except:
+            if old:
+                termios.tcsetattr(self.fd, termios.TCSANOW, old)
             self.close()
             raise
 
@@ -289,15 +314,28 @@
             None.
 
         Returns:
-            Nothing.
+            str: Type of closure completed
         """
+        # For Labgrid-sjg, ask it is exit gracefully, so it can transition the
+        # board to the final state (like 'off') before exiting.
+        if os.environ.get('USE_LABGRID_SJG'):
+            self.send(chr(EXIT_CHAR) * 2)
 
+            # Wait about 10 seconds for Labgrid to close and power off the board
+            for _ in range(100):
+                if not self.isalive():
+                    return 'normal'
+                time.sleep(0.1)
+
+        # That didn't work, so try closing the PTY
         os.close(self.fd)
         for _ in range(100):
             if not self.isalive():
-                break
+                return 'break'
             time.sleep(0.1)
 
+        return 'timeout'
+
     def get_expect_output(self):
         """Return the output read by expect()
 
diff --git a/test/test-main.c b/test/test-main.c
index 7a1f74a..8d76489 100644
--- a/test/test-main.c
+++ b/test/test-main.c
@@ -617,14 +617,14 @@
 			 */
 			len = strlen(test_name);
 			if (len < 6 || strcmp(test_name + len - 6, "_norun")) {
-				printf("Test %s is manual so must have a name ending in _norun\n",
+				printf("Test '%s' is manual so must have a name ending in _norun\n",
 				       test_name);
 				uts->fail_count++;
 				return -EBADF;
 			}
 			if (!uts->force_run) {
 				if (select_name) {
-					printf("Test %s skipped as it is manual (use -f to run it)\n",
+					printf("Test '%s' skipped as it is manual (use -f to run it)\n",
 					       test_name);
 				}
 				continue;
@@ -635,7 +635,7 @@
 		if (one && upto == pos) {
 			ret = ut_run_test_live_flat(uts, one);
 			if (uts->fail_count != old_fail_count) {
-				printf("Test %s failed %d times (position %d)\n",
+				printf("Test '%s' failed %d times (position %d)\n",
 				       one->name,
 				       uts->fail_count - old_fail_count, pos);
 			}
@@ -645,7 +645,7 @@
 		for (i = 0; i < uts->runs_per_test; i++)
 			ret = ut_run_test_live_flat(uts, test);
 		if (uts->fail_count != old_fail_count) {
-			printf("Test %s failed %d times\n", select_name,
+			printf("Test '%s' failed %d times\n", test_name,
 			       uts->fail_count - old_fail_count);
 		}
 		found++;
diff --git a/test/trace/test-trace.sh b/test/trace/test-trace.sh
deleted file mode 100755
index 5130b2b..0000000
--- a/test/trace/test-trace.sh
+++ /dev/null
@@ -1,64 +0,0 @@
-#!/bin/bash
-# SPDX-License-Identifier: GPL-2.0+
-# Copyright (c) 2013 The Chromium OS Authors.
-#
-
-# Simple test script for tracing with sandbox
-
-TRACE_OPT="FTRACE=1"
-
-BASE="$(dirname $0)/.."
-. $BASE/common.sh
-
-run_trace() {
-	echo "Run trace"
-	./${OUTPUT_DIR}/u-boot <<END
-trace stats
-hash sha256 0 10000
-trace pause
-trace stats
-hash sha256 0 10000
-trace stats
-trace resume
-hash sha256 0 10000
-trace pause
-trace stats
-reset
-END
-}
-
-check_results() {
-	echo "Check results"
-
-	# Expect sha256 to run 3 times, so we see the string 6 times
-	if [ $(grep -c sha256 ${tmp}) -ne 6 ]; then
-		fail "sha256 error"
-	fi
-
-	# 4 sets of results (output of 'trace stats')
-	if [ $(grep -c "traced function calls" ${tmp}) -ne 4 ]; then
-		fail "trace output error"
-	fi
-
-	# Check trace counts. We expect to see an increase in the number of
-	# traced function calls between each 'trace stats' command, except
-	# between calls 2 and 3, where tracing is paused.
-	# This code gets the sign of the difference between each number and
-	# its predecessor.
-	counts="$(tr -d ',\r' <${tmp} | awk \
-		'/traced function calls/ { diff = $1 - upto; upto = $1; \
-		printf "%d ", diff < 0 ? -1 : (diff > 0 ? 1 : 0)}')"
-
-	if [ "${counts}" != "1 1 0 1 " ]; then
-		fail "trace collection error: ${counts}"
-	fi
-}
-
-echo "Simple trace test / sanity check using sandbox"
-echo
-tmp="$(tempfile)"
-build_uboot "${TRACE_OPT}"
-run_trace >${tmp}
-check_results ${tmp}
-rm ${tmp}
-echo "Test passed"
diff --git a/tools/imx8image.c b/tools/imx8image.c
index 96ece28..15510d3 100644
--- a/tools/imx8image.c
+++ b/tools/imx8image.c
@@ -93,6 +93,7 @@
 	case CMD_DCD_SKIP:
 		if (!strncmp("true", token, 4))
 			dcd_skip = true;
+		break;
 	case CMD_FUSE_VERSION:
 		fuse_version = (uint8_t)(strtoll(token, NULL, 0) & 0xFF);
 		break;
@@ -733,7 +734,7 @@
 			fclose(fd);
 
 			if (header.tag != IVT_HEADER_TAG_B0) {
-				fprintf(stderr, "header tag mismatched \n");
+				fprintf(stderr, "header tag mismatched file %s\n", img_sp->filename);
 				exit(EXIT_FAILURE);
 			} else {
 				file_off +=
diff --git a/tools/imx_cntr_image.sh b/tools/imx_cntr_image.sh
index 972b95c..07acd38 100755
--- a/tools/imx_cntr_image.sh
+++ b/tools/imx_cntr_image.sh
@@ -14,6 +14,10 @@
 		continue
 	fi
 
+	if [ $f = "spl/u-boot-spl.bin" ]; then
+		continue
+	fi
+
 	if [ -f $f ]; then
 		continue
 	fi