| commit | d9672d7ae58a8ee663c8fac007ed086975d536d4 | [log] [tgz] |
|---|---|---|
| author | Svyatoslav Ryhel <clamor95@gmail.com> | Fri Nov 29 08:14:21 2024 +0200 |
| committer | Svyatoslav Ryhel <clamor95@gmail.com> | Wed Feb 12 10:35:17 2025 +0200 |
| tree | e90cff7578cb1d07beee18e6a0b9529f40305e35 | |
| parent | 007d4973328694abceaa8f3d22bc7402d594c4c3 [diff] |
ARM: tegra210: clock: implement PLLD2 support PLLD2 is a simple clock (controlled by 2 registers) and appears starting from T30. Primary use of PLLD2 is as main HDMI clock parent. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>