Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86
- verdin-imx8mm board reST documentation update
- Intel Edison board ACPI table I2C/USB minor updates
- Fix a regression of ns16550 serial driver that breaks Intel Edison
diff --git a/Kconfig b/Kconfig
index b4864cd..f698e0a 100644
--- a/Kconfig
+++ b/Kconfig
@@ -299,6 +299,11 @@
pointer values - up to 'MAX_ERRNO' bytes below this value must be
unused/invalid addresses.
+config PLATFORM_ELFENTRY
+ string
+ default "__start" if MIPS
+ default "_start"
+
endmenu # General setup
menu "Boot images"
diff --git a/Makefile b/Makefile
index 7fae3c2..0db44d4 100644
--- a/Makefile
+++ b/Makefile
@@ -1647,18 +1647,17 @@
u-boot-img-spl-at-end.bin: u-boot.img spl/u-boot-spl.bin FORCE
$(call if_changed,pad_cat)
-# Create a new ELF from a raw binary file.
-ifndef PLATFORM_ELFENTRY
- PLATFORM_ELFENTRY = "_start"
-endif
quiet_cmd_u-boot-elf ?= LD $@
cmd_u-boot-elf ?= $(LD) u-boot-elf.o -o $@ \
- --defsym=$(PLATFORM_ELFENTRY)=$(CONFIG_SYS_TEXT_BASE) \
+ -T u-boot-elf.lds --defsym=$(CONFIG_PLATFORM_ELFENTRY)=$(CONFIG_SYS_TEXT_BASE) \
-Ttext=$(CONFIG_SYS_TEXT_BASE)
-u-boot.elf: u-boot.bin
+u-boot.elf: u-boot.bin u-boot-elf.lds
$(Q)$(OBJCOPY) -I binary $(PLATFORM_ELFFLAGS) $< u-boot-elf.o
$(call if_changed,u-boot-elf)
+u-boot-elf.lds: arch/u-boot-elf.lds prepare FORCE
+ $(call if_changed_dep,cpp_lds)
+
# MediaTek's ARM-based u-boot needs a header to contains its load address
# which is parsed by the BootROM.
# If the SPL build is enabled, the header will be added to the spl binary,
diff --git a/arch/arm/cpu/armv8/cpu.c b/arch/arm/cpu/armv8/cpu.c
index 2467e0b..3575203 100644
--- a/arch/arm/cpu/armv8/cpu.c
+++ b/arch/arm/cpu/armv8/cpu.c
@@ -32,6 +32,8 @@
"b.ne 1b" : "=r" (loops) : "0"(loops) : "cc");
}
+void __weak board_cleanup_before_linux(void){}
+
int cleanup_before_linux(void)
{
/*
@@ -40,6 +42,9 @@
*
* disable interrupt and turn off caches etc ...
*/
+
+ board_cleanup_before_linux();
+
disable_interrupts();
/*
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9c593b2..820ee97 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -180,7 +180,8 @@
tegra210-e2220-1170.dtb \
tegra210-p2371-0000.dtb \
tegra210-p2371-2180.dtb \
- tegra210-p2571.dtb
+ tegra210-p2571.dtb \
+ tegra210-p3450-0000.dtb
dtb-$(CONFIG_ARCH_MVEBU) += \
armada-3720-db.dtb \
diff --git a/arch/arm/dts/tegra210-p2371-2180.dts b/arch/arm/dts/tegra210-p2371-2180.dts
index c2f497c..649c163 100644
--- a/arch/arm/dts/tegra210-p2371-2180.dts
+++ b/arch/arm/dts/tegra210-p2371-2180.dts
@@ -12,6 +12,8 @@
aliases {
i2c0 = "/i2c@7000d000";
+ i2c2 = "/i2c@7000c400";
+ i2c3 = "/i2c@7000c500";
mmc0 = "/sdhci@700b0600";
mmc1 = "/sdhci@700b0000";
usb0 = "/usb@7d000000";
@@ -85,6 +87,16 @@
non-removable;
};
+ i2c@7000c400 {
+ status = "okay";
+ clock-frequency = <400000>;
+ };
+
+ i2c@7000c500 {
+ status = "okay";
+ clock-frequency = <400000>;
+ };
+
i2c@7000d000 {
status = "okay";
clock-frequency = <400000>;
diff --git a/arch/arm/dts/tegra210-p3450-0000.dts b/arch/arm/dts/tegra210-p3450-0000.dts
new file mode 100644
index 0000000..9ef744a
--- /dev/null
+++ b/arch/arm/dts/tegra210-p3450-0000.dts
@@ -0,0 +1,147 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019-2020 NVIDIA Corporation <www.nvidia.com>
+ */
+/dts-v1/;
+
+#include "tegra210.dtsi"
+
+/ {
+ model = "NVIDIA Jetson Nano Developer Kit";
+ compatible = "nvidia,p3450-0000", "nvidia,tegra210";
+
+ chosen {
+ stdout-path = &uarta;
+ };
+
+ aliases {
+ ethernet = "/pcie@1003000/pci@2,0/ethernet@0,0";
+ i2c0 = "/i2c@7000d000";
+ i2c2 = "/i2c@7000c400";
+ i2c3 = "/i2c@7000c500";
+ i2c4 = "/i2c@7000c700";
+ mmc0 = "/sdhci@700b0600";
+ mmc1 = "/sdhci@700b0000";
+ spi0 = "/spi@70410000";
+ usb0 = "/usb@7d000000";
+ };
+
+ memory {
+ reg = <0x0 0x80000000 0x0 0xc0000000>;
+ };
+
+ pcie@1003000 {
+ status = "okay";
+
+ pci@1,0 {
+ status = "okay";
+ };
+
+ pci@2,0 {
+ status = "okay";
+
+ ethernet@0,0 {
+ reg = <0x000000 0 0 0 0>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ };
+ };
+ };
+
+ serial@70006000 {
+ status = "okay";
+ };
+
+ padctl@7009f000 {
+ pinctrl-0 = <&padctl_default>;
+ pinctrl-names = "default";
+
+ padctl_default: pinmux {
+ xusb {
+ nvidia,lanes = "otg-1", "otg-2";
+ nvidia,function = "xusb";
+ nvidia,iddq = <0>;
+ };
+
+ usb3 {
+ nvidia,lanes = "pcie-5", "pcie-6";
+ nvidia,function = "usb3";
+ nvidia,iddq = <0>;
+ };
+
+ pcie-x1 {
+ nvidia,lanes = "pcie-0";
+ nvidia,function = "pcie-x1";
+ nvidia,iddq = <0>;
+ };
+
+ pcie-x4 {
+ nvidia,lanes = "pcie-1", "pcie-2",
+ "pcie-3", "pcie-4";
+ nvidia,function = "pcie-x4";
+ nvidia,iddq = <0>;
+ };
+
+ sata {
+ nvidia,lanes = "sata-0";
+ nvidia,function = "sata";
+ nvidia,iddq = <0>;
+ };
+ };
+ };
+
+ sdhci@700b0000 {
+ status = "okay";
+ cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
+ power-gpios = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
+ bus-width = <4>;
+ };
+
+ sdhci@700b0600 {
+ status = "okay";
+ bus-width = <8>;
+ non-removable;
+ };
+
+ i2c@7000c400 {
+ status = "okay";
+ clock-frequency = <400000>;
+ };
+
+ i2c@7000c500 {
+ status = "okay";
+ clock-frequency = <400000>;
+ };
+
+ i2c@7000c700 {
+ status = "okay";
+ clock-frequency = <400000>;
+ };
+
+ i2c@7000d000 {
+ status = "okay";
+ clock-frequency = <400000>;
+ };
+
+ spi@70410000 {
+ status = "okay";
+ spi-max-frequency = <80000000>;
+ };
+
+ usb@7d000000 {
+ status = "okay";
+ dr_mode = "peripheral";
+ };
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clk32k_in: clock@0 {
+ compatible = "fixed-clock";
+ reg = <0>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+};
diff --git a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h
index 8398249..872a158 100644
--- a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h
@@ -85,8 +85,18 @@
LB_RGB_1280X8 = 0x5
};
+#if defined(CONFIG_ROCKCHIP_RK3399)
enum vop_modes {
VOP_MODE_EDP = 0,
+ VOP_MODE_MIPI,
+ VOP_MODE_HDMI,
+ VOP_MODE_MIPI1,
+ VOP_MODE_DP,
+ VOP_MODE_NONE,
+};
+#else
+enum vop_modes {
+ VOP_MODE_EDP = 0,
VOP_MODE_HDMI,
VOP_MODE_LVDS,
VOP_MODE_MIPI,
@@ -94,6 +104,7 @@
VOP_MODE_AUTO_DETECT,
VOP_MODE_UNKNOWN,
};
+#endif
/* VOP_VERSION_INFO */
#define M_FPGA_VERSION (0xffff << 16)
diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
index a2b6f63..70dcf4a 100644
--- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h
+++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
@@ -2,7 +2,7 @@
/*
* (C) Copyright 2009 SAMSUNG Electronics
* Minkyu Kang <mk7.kang@samsung.com>
- * Portions Copyright (C) 2011-2012 NVIDIA Corporation
+ * Portions Copyright (C) 2011-2012,2019 NVIDIA Corporation
*/
#ifndef __TEGRA_MMC_H_
@@ -52,7 +52,7 @@
unsigned char admaerr; /* offset 54h */
unsigned char res4[3]; /* RESERVED, offset 55h-57h */
unsigned long admaaddr; /* offset 58h-5Fh */
- unsigned char res5[0xa0]; /* RESERVED, offset 60h-FBh */
+ unsigned char res5[0x9c]; /* RESERVED, offset 60h-FBh */
unsigned short slotintstatus; /* offset FCh */
unsigned short hcver; /* HOST Version */
unsigned int venclkctl; /* _VENDOR_CLOCK_CNTRL_0, 100h */
@@ -127,11 +127,23 @@
#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE (1 << 1)
-/* SDMMC1/3 settings from section 24.6 of T30 TRM */
+/* SDMMC1/3 settings from SDMMCx Initialization Sequence of TRM */
#define MEMCOMP_PADCTRL_VREF 7
-#define AUTO_CAL_ENABLED (1 << 29)
+#define AUTO_CAL_ENABLE (1 << 29)
+#define AUTO_CAL_ACTIVE (1 << 31)
+#define AUTO_CAL_START (1 << 31)
+#if defined(CONFIG_TEGRA210)
+#define AUTO_CAL_PD_OFFSET (0x7D << 8)
+#define AUTO_CAL_PU_OFFSET (0 << 0)
+#define IO_TRIM_BYPASS_MASK (1 << 2)
+#define TRIM_VAL_SHIFT 24
+#define TRIM_VAL_MASK (0x1F << TRIM_VAL_SHIFT)
+#define TAP_VAL_SHIFT 16
+#define TAP_VAL_MASK (0xFF << TAP_VAL_SHIFT)
+#else
#define AUTO_CAL_PD_OFFSET (0x70 << 8)
#define AUTO_CAL_PU_OFFSET (0x62 << 0)
+#endif
#endif /* __ASSEMBLY__ */
#endif /* __TEGRA_MMC_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/xusb-padctl.h b/arch/arm/include/asm/arch-tegra/xusb-padctl.h
index deccdf4..7e14d81 100644
--- a/arch/arm/include/asm/arch-tegra/xusb-padctl.h
+++ b/arch/arm/include/asm/arch-tegra/xusb-padctl.h
@@ -16,6 +16,7 @@
struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type);
void tegra_xusb_padctl_init(void);
+void tegra_xusb_padctl_exit(void);
int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy);
int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy);
int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy);
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index ed7514a..0cb1f23 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -229,6 +229,7 @@
select DM_PMIC
select DM_REGULATOR_FIXED
select BOARD_LATE_INIT
+ imply PRE_CONSOLE_BUFFER
imply ROCKCHIP_COMMON_BOARD
imply ROCKCHIP_SDRAM_COMMON
imply SPL_ROCKCHIP_COMMON_BOARD
diff --git a/arch/arm/mach-snapdragon/misc.c b/arch/arm/mach-snapdragon/misc.c
index f6c8786..aaa561c 100644
--- a/arch/arm/mach-snapdragon/misc.c
+++ b/arch/arm/mach-snapdragon/misc.c
@@ -41,7 +41,7 @@
int i;
char sn[9];
- snprintf(sn, 8, "%08x", msm_board_serial());
+ snprintf(sn, 9, "%08x", msm_board_serial());
/* fill in the mac with serialno, use locally adminstrated pool */
mac[0] = 0x02;
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index d3497a2..224efc9 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -181,6 +181,12 @@
return nvidia_board_init();
}
+void board_cleanup_before_linux(void)
+{
+ /* power down UPHY PLL */
+ tegra_xusb_padctl_exit();
+}
+
#ifdef CONFIG_BOARD_EARLY_INIT_F
static void __gpio_early_init(void)
{
@@ -211,6 +217,31 @@
arch_timer_init();
#endif
+#if defined(CONFIG_DISABLE_SDMMC1_EARLY)
+ /*
+ * Turn off (reset/disable) SDMMC1 on Nano here, before GPIO INIT.
+ * We do this because earlier bootloaders have enabled power to
+ * SDMMC1 on Nano, and toggling power-gpio (PZ3) in pinmux_init()
+ * results in power being back-driven into the SD-card and SDMMC1
+ * HW, which is 'bad' as per the HW team.
+ *
+ * From the HW team: "LDO2 from the PMIC has already been set to 3.3v in
+ * nvtboot/CBoot on Nano (for SD-card boot). So when U-Boot's GPIO_INIT
+ * table sets PZ3 to OUT0 as per the pinmux spreadsheet, it turns off
+ * the loadswitch. When PZ3 is 0 and not driving, essentially the SDCard
+ * voltage turns off. Since the SDCard voltage is no longer there, the
+ * SDMMC CLK/DAT lines are backdriving into what essentially is a
+ * powered-off SDCard, that's why the voltage drops from 3.3V to ~1.6V"
+ *
+ * Note that this can probably be removed when we change over to storing
+ * all BL components on QSPI on Nano, and U-Boot then becomes the first
+ * one to turn on SDMMC1 power. Another fix would be to have CBoot
+ * disable power/gate SDMMC1 off before handing off to U-Boot/kernel.
+ */
+ reset_set_enable(PERIPH_ID_SDMMC1, 1);
+ clock_set_enable(PERIPH_ID_SDMMC1, 0);
+#endif /* CONFIG_DISABLE_SDMMC1_EARLY */
+
pinmux_init();
board_init_uart_f();
diff --git a/arch/arm/mach-tegra/tegra210/Kconfig b/arch/arm/mach-tegra/tegra210/Kconfig
index 3637473..97ed8e0 100644
--- a/arch/arm/mach-tegra/tegra210/Kconfig
+++ b/arch/arm/mach-tegra/tegra210/Kconfig
@@ -35,6 +35,12 @@
help
P2571 is a P2530 married to a P1963 I/O board
+config TARGET_P3450_0000
+ bool "NVIDIA Jetson Nano Developer Kit"
+ select BOARD_LATE_INIT
+ help
+ P3450-0000 is a P3448 CPU board married to a P3449 I/O board.
+
endchoice
config SYS_SOC
@@ -44,5 +50,6 @@
source "board/nvidia/p2371-0000/Kconfig"
source "board/nvidia/p2371-2180/Kconfig"
source "board/nvidia/p2571/Kconfig"
+source "board/nvidia/p3450-0000/Kconfig"
endif
diff --git a/arch/arm/mach-tegra/tegra210/Makefile b/arch/arm/mach-tegra/tegra210/Makefile
index b6012fc..cfcba5b 100644
--- a/arch/arm/mach-tegra/tegra210/Makefile
+++ b/arch/arm/mach-tegra/tegra210/Makefile
@@ -1,5 +1,5 @@
#
-# (C) Copyright 2013-2015
+# (C) Copyright 2013-2020
# NVIDIA Corporation <www.nvidia.com>
#
# SPDX-License-Identifier: GPL-2.0+
@@ -7,6 +7,5 @@
obj-y += clock.o
obj-y += funcmux.o
-obj-y += pinmux.o
obj-y += xusb-padctl.o
obj-y += ../xusb-padctl-common.o
diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c
index b240860..00c65c2 100644
--- a/arch/arm/mach-tegra/tegra210/clock.c
+++ b/arch/arm/mach-tegra/tegra210/clock.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * (C) Copyright 2013-2015
+ * (C) Copyright 2013-2020
* NVIDIA Corporation <www.nvidia.com>
*/
@@ -333,7 +333,7 @@
TYPE(PERIPHC_DMIC3, CLOCK_TYPE_NONE),
TYPE(PERIPHC_APE, CLOCK_TYPE_NONE),
TYPE(PERIPHC_QSPI, CLOCK_TYPE_PC01C00_C42C41TC40),
- TYPE(PERIPHC_VI_I2C, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_VI_I2C, CLOCK_TYPE_PC2CC3M_T16),
TYPE(PERIPHC_USB2_HSIC_TRK, CLOCK_TYPE_NONE),
TYPE(PERIPHC_PEX_SATA_USB_RX_BYP, CLOCK_TYPE_NONE),
@@ -739,7 +739,7 @@
if (!clock_periph_id_isvalid(periph_id))
return -1;
- internal_id = periph_id_to_internal_id[periph_id];
+ internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]);
if (!periphc_internal_id_isvalid(internal_id))
return -1;
@@ -765,7 +765,7 @@
if (!clock_periph_id_isvalid(periph_id))
return CLOCK_ID_NONE;
- internal_id = periph_id_to_internal_id[periph_id];
+ internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]);
if (!periphc_internal_id_isvalid(internal_id))
return CLOCK_ID_NONE;
@@ -1235,25 +1235,6 @@
value &= ~PLLE_SS_CNTL_INTERP_RESET;
writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
- /* 7. Enable HW power sequencer for PLLE */
-
- value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
- value &= ~PLLE_MISC_IDDQ_SWCTL;
- writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
-
- value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX);
- value &= ~PLLE_AUX_SS_SWCTL;
- value &= ~PLLE_AUX_ENABLE_SWCTL;
- value |= PLLE_AUX_SS_SEQ_INCLUDE;
- value |= PLLE_AUX_USE_LOCKDET;
- writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX);
-
- /* 8. Wait 1 us */
-
- udelay(1);
- value |= PLLE_AUX_SEQ_ENABLE;
- writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX);
-
return 0;
}
diff --git a/arch/arm/mach-tegra/tegra210/pinmux.c b/arch/arm/mach-tegra/tegra210/pinmux.c
deleted file mode 100644
index 6158099..0000000
--- a/arch/arm/mach-tegra/tegra210/pinmux.c
+++ /dev/null
@@ -1,194 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/pinmux.h>
-
-#define PIN(pin, f0, f1, f2, f3) \
- { \
- .funcs = { \
- PMUX_FUNC_##f0, \
- PMUX_FUNC_##f1, \
- PMUX_FUNC_##f2, \
- PMUX_FUNC_##f3, \
- }, \
- }
-
-#define PIN_RESERVED {}
-
-static const struct pmux_pingrp_desc tegra210_pingroups[] = {
- /* pin, f0, f1, f2, f3 */
- /* Offset 0x3000 */
- PIN(SDMMC1_CLK_PM0, SDMMC1, RSVD1, RSVD2, RSVD3),
- PIN(SDMMC1_CMD_PM1, SDMMC1, SPI3, RSVD2, RSVD3),
- PIN(SDMMC1_DAT3_PM2, SDMMC1, SPI3, RSVD2, RSVD3),
- PIN(SDMMC1_DAT2_PM3, SDMMC1, SPI3, RSVD2, RSVD3),
- PIN(SDMMC1_DAT1_PM4, SDMMC1, SPI3, RSVD2, RSVD3),
- PIN(SDMMC1_DAT0_PM5, SDMMC1, RSVD1, RSVD2, RSVD3),
- PIN_RESERVED,
- /* Offset 0x301c */
- PIN(SDMMC3_CLK_PP0, SDMMC3, RSVD1, RSVD2, RSVD3),
- PIN(SDMMC3_CMD_PP1, SDMMC3, RSVD1, RSVD2, RSVD3),
- PIN(SDMMC3_DAT0_PP5, SDMMC3, RSVD1, RSVD2, RSVD3),
- PIN(SDMMC3_DAT1_PP4, SDMMC3, RSVD1, RSVD2, RSVD3),
- PIN(SDMMC3_DAT2_PP3, SDMMC3, RSVD1, RSVD2, RSVD3),
- PIN(SDMMC3_DAT3_PP2, SDMMC3, RSVD1, RSVD2, RSVD3),
- PIN_RESERVED,
- /* Offset 0x3038 */
- PIN(PEX_L0_RST_N_PA0, PE0, RSVD1, RSVD2, RSVD3),
- PIN(PEX_L0_CLKREQ_N_PA1, PE0, RSVD1, RSVD2, RSVD3),
- PIN(PEX_WAKE_N_PA2, PE, RSVD1, RSVD2, RSVD3),
- PIN(PEX_L1_RST_N_PA3, PE1, RSVD1, RSVD2, RSVD3),
- PIN(PEX_L1_CLKREQ_N_PA4, PE1, RSVD1, RSVD2, RSVD3),
- PIN(SATA_LED_ACTIVE_PA5, SATA, RSVD1, RSVD2, RSVD3),
- PIN(SPI1_MOSI_PC0, SPI1, RSVD1, RSVD2, RSVD3),
- PIN(SPI1_MISO_PC1, SPI1, RSVD1, RSVD2, RSVD3),
- PIN(SPI1_SCK_PC2, SPI1, RSVD1, RSVD2, RSVD3),
- PIN(SPI1_CS0_PC3, SPI1, RSVD1, RSVD2, RSVD3),
- PIN(SPI1_CS1_PC4, SPI1, RSVD1, RSVD2, RSVD3),
- PIN(SPI2_MOSI_PB4, SPI2, DTV, RSVD2, RSVD3),
- PIN(SPI2_MISO_PB5, SPI2, DTV, RSVD2, RSVD3),
- PIN(SPI2_SCK_PB6, SPI2, DTV, RSVD2, RSVD3),
- PIN(SPI2_CS0_PB7, SPI2, DTV, RSVD2, RSVD3),
- PIN(SPI2_CS1_PDD0, SPI2, RSVD1, RSVD2, RSVD3),
- PIN(SPI4_MOSI_PC7, SPI4, RSVD1, RSVD2, RSVD3),
- PIN(SPI4_MISO_PD0, SPI4, RSVD1, RSVD2, RSVD3),
- PIN(SPI4_SCK_PC5, SPI4, RSVD1, RSVD2, RSVD3),
- PIN(SPI4_CS0_PC6, SPI4, RSVD1, RSVD2, RSVD3),
- PIN(QSPI_SCK_PEE0, QSPI, RSVD1, RSVD2, RSVD3),
- PIN(QSPI_CS_N_PEE1, QSPI, RSVD1, RSVD2, RSVD3),
- PIN(QSPI_IO0_PEE2, QSPI, RSVD1, RSVD2, RSVD3),
- PIN(QSPI_IO1_PEE3, QSPI, RSVD1, RSVD2, RSVD3),
- PIN(QSPI_IO2_PEE4, QSPI, RSVD1, RSVD2, RSVD3),
- PIN(QSPI_IO3_PEE5, QSPI, RSVD1, RSVD2, RSVD3),
- PIN_RESERVED,
- /* Offset 0x30a4 */
- PIN(DMIC1_CLK_PE0, DMIC1, I2S3, RSVD2, RSVD3),
- PIN(DMIC1_DAT_PE1, DMIC1, I2S3, RSVD2, RSVD3),
- PIN(DMIC2_CLK_PE2, DMIC2, I2S3, RSVD2, RSVD3),
- PIN(DMIC2_DAT_PE3, DMIC2, I2S3, RSVD2, RSVD3),
- PIN(DMIC3_CLK_PE4, DMIC3, I2S5A, RSVD2, RSVD3),
- PIN(DMIC3_DAT_PE5, DMIC3, I2S5A, RSVD2, RSVD3),
- PIN(GEN1_I2C_SCL_PJ1, I2C1, RSVD1, RSVD2, RSVD3),
- PIN(GEN1_I2C_SDA_PJ0, I2C1, RSVD1, RSVD2, RSVD3),
- PIN(GEN2_I2C_SCL_PJ2, I2C2, RSVD1, RSVD2, RSVD3),
- PIN(GEN2_I2C_SDA_PJ3, I2C2, RSVD1, RSVD2, RSVD3),
- PIN(GEN3_I2C_SCL_PF0, I2C3, RSVD1, RSVD2, RSVD3),
- PIN(GEN3_I2C_SDA_PF1, I2C3, RSVD1, RSVD2, RSVD3),
- PIN(CAM_I2C_SCL_PS2, I2C3, I2CVI, RSVD2, RSVD3),
- PIN(CAM_I2C_SDA_PS3, I2C3, I2CVI, RSVD2, RSVD3),
- PIN(PWR_I2C_SCL_PY3, I2CPMU, RSVD1, RSVD2, RSVD3),
- PIN(PWR_I2C_SDA_PY4, I2CPMU, RSVD1, RSVD2, RSVD3),
- PIN(UART1_TX_PU0, UARTA, RSVD1, RSVD2, RSVD3),
- PIN(UART1_RX_PU1, UARTA, RSVD1, RSVD2, RSVD3),
- PIN(UART1_RTS_PU2, UARTA, RSVD1, RSVD2, RSVD3),
- PIN(UART1_CTS_PU3, UARTA, RSVD1, RSVD2, RSVD3),
- PIN(UART2_TX_PG0, UARTB, I2S4A, SPDIF, UART),
- PIN(UART2_RX_PG1, UARTB, I2S4A, SPDIF, UART),
- PIN(UART2_RTS_PG2, UARTB, I2S4A, RSVD2, UART),
- PIN(UART2_CTS_PG3, UARTB, I2S4A, RSVD2, UART),
- PIN(UART3_TX_PD1, UARTC, SPI4, RSVD2, RSVD3),
- PIN(UART3_RX_PD2, UARTC, SPI4, RSVD2, RSVD3),
- PIN(UART3_RTS_PD3, UARTC, SPI4, RSVD2, RSVD3),
- PIN(UART3_CTS_PD4, UARTC, SPI4, RSVD2, RSVD3),
- PIN(UART4_TX_PI4, UARTD, UART, RSVD2, RSVD3),
- PIN(UART4_RX_PI5, UARTD, UART, RSVD2, RSVD3),
- PIN(UART4_RTS_PI6, UARTD, UART, RSVD2, RSVD3),
- PIN(UART4_CTS_PI7, UARTD, UART, RSVD2, RSVD3),
- PIN(DAP1_FS_PB0, I2S1, RSVD1, RSVD2, RSVD3),
- PIN(DAP1_DIN_PB1, I2S1, RSVD1, RSVD2, RSVD3),
- PIN(DAP1_DOUT_PB2, I2S1, RSVD1, RSVD2, RSVD3),
- PIN(DAP1_SCLK_PB3, I2S1, RSVD1, RSVD2, RSVD3),
- PIN(DAP2_FS_PAA0, I2S2, RSVD1, RSVD2, RSVD3),
- PIN(DAP2_DIN_PAA2, I2S2, RSVD1, RSVD2, RSVD3),
- PIN(DAP2_DOUT_PAA3, I2S2, RSVD1, RSVD2, RSVD3),
- PIN(DAP2_SCLK_PAA1, I2S2, RSVD1, RSVD2, RSVD3),
- PIN(DAP4_FS_PJ4, I2S4B, RSVD1, RSVD2, RSVD3),
- PIN(DAP4_DIN_PJ5, I2S4B, RSVD1, RSVD2, RSVD3),
- PIN(DAP4_DOUT_PJ6, I2S4B, RSVD1, RSVD2, RSVD3),
- PIN(DAP4_SCLK_PJ7, I2S4B, RSVD1, RSVD2, RSVD3),
- PIN(CAM1_MCLK_PS0, EXTPERIPH3, RSVD1, RSVD2, RSVD3),
- PIN(CAM2_MCLK_PS1, EXTPERIPH3, RSVD1, RSVD2, RSVD3),
- PIN(JTAG_RTCK, JTAG, RSVD1, RSVD2, RSVD3),
- PIN(CLK_32K_IN, CLK, RSVD1, RSVD2, RSVD3),
- PIN(CLK_32K_OUT_PY5, SOC, BLINK, RSVD2, RSVD3),
- PIN(BATT_BCL, BCL, RSVD1, RSVD2, RSVD3),
- PIN(CLK_REQ, SYS, RSVD1, RSVD2, RSVD3),
- PIN(CPU_PWR_REQ, CPU, RSVD1, RSVD2, RSVD3),
- PIN(PWR_INT_N, PMI, RSVD1, RSVD2, RSVD3),
- PIN(SHUTDOWN, SHUTDOWN, RSVD1, RSVD2, RSVD3),
- PIN(CORE_PWR_REQ, CORE, RSVD1, RSVD2, RSVD3),
- PIN(AUD_MCLK_PBB0, AUD, RSVD1, RSVD2, RSVD3),
- PIN(DVFS_PWM_PBB1, RSVD0, CLDVFS, SPI3, RSVD3),
- PIN(DVFS_CLK_PBB2, RSVD0, CLDVFS, SPI3, RSVD3),
- PIN(GPIO_X1_AUD_PBB3, RSVD0, RSVD1, SPI3, RSVD3),
- PIN(GPIO_X3_AUD_PBB4, RSVD0, RSVD1, SPI3, RSVD3),
- PIN(PCC7, RSVD0, RSVD1, RSVD2, RSVD3),
- PIN(HDMI_CEC_PCC0, CEC, RSVD1, RSVD2, RSVD3),
- PIN(HDMI_INT_DP_HPD_PCC1, DP, RSVD1, RSVD2, RSVD3),
- PIN(SPDIF_OUT_PCC2, SPDIF, RSVD1, RSVD2, RSVD3),
- PIN(SPDIF_IN_PCC3, SPDIF, RSVD1, RSVD2, RSVD3),
- PIN(USB_VBUS_EN0_PCC4, USB, RSVD1, RSVD2, RSVD3),
- PIN(USB_VBUS_EN1_PCC5, USB, RSVD1, RSVD2, RSVD3),
- PIN(DP_HPD0_PCC6, DP, RSVD1, RSVD2, RSVD3),
- PIN(WIFI_EN_PH0, RSVD0, RSVD1, RSVD2, RSVD3),
- PIN(WIFI_RST_PH1, RSVD0, RSVD1, RSVD2, RSVD3),
- PIN(WIFI_WAKE_AP_PH2, RSVD0, RSVD1, RSVD2, RSVD3),
- PIN(AP_WAKE_BT_PH3, RSVD0, UARTB, SPDIF, RSVD3),
- PIN(BT_RST_PH4, RSVD0, UARTB, SPDIF, RSVD3),
- PIN(BT_WAKE_AP_PH5, RSVD0, RSVD1, RSVD2, RSVD3),
- PIN(AP_WAKE_NFC_PH7, RSVD0, RSVD1, RSVD2, RSVD3),
- PIN(NFC_EN_PI0, RSVD0, RSVD1, RSVD2, RSVD3),
- PIN(NFC_INT_PI1, RSVD0, RSVD1, RSVD2, RSVD3),
- PIN(GPS_EN_PI2, RSVD0, RSVD1, RSVD2, RSVD3),
- PIN(GPS_RST_PI3, RSVD0, RSVD1, RSVD2, RSVD3),
- PIN(CAM_RST_PS4, VGP1, RSVD1, RSVD2, RSVD3),
- PIN(CAM_AF_EN_PS5, VIMCLK, VGP2, RSVD2, RSVD3),
- PIN(CAM_FLASH_EN_PS6, VIMCLK, VGP3, RSVD2, RSVD3),
- PIN(CAM1_PWDN_PS7, VGP4, RSVD1, RSVD2, RSVD3),
- PIN(CAM2_PWDN_PT0, VGP5, RSVD1, RSVD2, RSVD3),
- PIN(CAM1_STROBE_PT1, VGP6, RSVD1, RSVD2, RSVD3),
- PIN(LCD_TE_PY2, DISPLAYA, RSVD1, RSVD2, RSVD3),
- PIN(LCD_BL_PWM_PV0, DISPLAYA, PWM0, SOR0, RSVD3),
- PIN(LCD_BL_EN_PV1, RSVD0, RSVD1, RSVD2, RSVD3),
- PIN(LCD_RST_PV2, RSVD0, RSVD1, RSVD2, RSVD3),
- PIN(LCD_GPIO1_PV3, DISPLAYB, RSVD1, RSVD2, RSVD3),
- PIN(LCD_GPIO2_PV4, DISPLAYB, PWM1, RSVD2, SOR1),
- PIN(AP_READY_PV5, RSVD0, RSVD1, RSVD2, RSVD3),
- PIN(TOUCH_RST_PV6, RSVD0, RSVD1, RSVD2, RSVD3),
- PIN(TOUCH_CLK_PV7, TOUCH, RSVD1, RSVD2, RSVD3),
- PIN(MODEM_WAKE_AP_PX0, RSVD0, RSVD1, RSVD2, RSVD3),
- PIN(TOUCH_INT_PX1, RSVD0, RSVD1, RSVD2, RSVD3),
- PIN(MOTION_INT_PX2, RSVD0, RSVD1, RSVD2, RSVD3),
- PIN(ALS_PROX_INT_PX3, RSVD0, RSVD1, RSVD2, RSVD3),
- PIN(TEMP_ALERT_PX4, RSVD0, RSVD1, RSVD2, RSVD3),
- PIN(BUTTON_POWER_ON_PX5, RSVD0, RSVD1, RSVD2, RSVD3),
- PIN(BUTTON_VOL_UP_PX6, RSVD0, RSVD1, RSVD2, RSVD3),
- PIN(BUTTON_VOL_DOWN_PX7, RSVD0, RSVD1, RSVD2, RSVD3),
- PIN(BUTTON_SLIDE_SW_PY0, RSVD0, RSVD1, RSVD2, RSVD3),
- PIN(BUTTON_HOME_PY1, RSVD0, RSVD1, RSVD2, RSVD3),
- PIN(PA6, SATA, RSVD1, RSVD2, RSVD3),
- PIN(PE6, RSVD0, I2S5A, PWM2, RSVD3),
- PIN(PE7, RSVD0, I2S5A, PWM3, RSVD3),
- PIN(PH6, RSVD0, RSVD1, RSVD2, RSVD3),
- PIN(PK0, IQC0, I2S5B, RSVD2, RSVD3),
- PIN(PK1, IQC0, I2S5B, RSVD2, RSVD3),
- PIN(PK2, IQC0, I2S5B, RSVD2, RSVD3),
- PIN(PK3, IQC0, I2S5B, RSVD2, RSVD3),
- PIN(PK4, IQC1, RSVD1, RSVD2, RSVD3),
- PIN(PK5, IQC1, RSVD1, RSVD2, RSVD3),
- PIN(PK6, IQC1, RSVD1, RSVD2, RSVD3),
- PIN(PK7, IQC1, RSVD1, RSVD2, RSVD3),
- PIN(PL0, RSVD0, RSVD1, RSVD2, RSVD3),
- PIN(PL1, SOC, RSVD1, RSVD2, RSVD3),
- PIN(PZ0, VIMCLK2, RSVD1, RSVD2, RSVD3),
- PIN(PZ1, VIMCLK2, SDMMC1, RSVD2, RSVD3),
- PIN(PZ2, SDMMC3, CCLA, RSVD2, RSVD3),
- PIN(PZ3, SDMMC3, RSVD1, RSVD2, RSVD3),
- PIN(PZ4, SDMMC1, RSVD1, RSVD2, RSVD3),
- PIN(PZ5, SOC, RSVD1, RSVD2, RSVD3),
-};
-const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra210_pingroups;
diff --git a/arch/arm/mach-tegra/tegra210/xusb-padctl.c b/arch/arm/mach-tegra/tegra210/xusb-padctl.c
index ab6684f..64dc297 100644
--- a/arch/arm/mach-tegra/tegra210/xusb-padctl.c
+++ b/arch/arm/mach-tegra/tegra210/xusb-padctl.c
@@ -170,6 +170,17 @@
return tegra_xusb_padctl_disable(phy->padctl);
}
+#define XUSB_PADCTL_USB3_PAD_MUX 0x28
+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE (1 << 0)
+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0 (1 << 1)
+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1 (1 << 2)
+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2 (1 << 3)
+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK3 (1 << 4)
+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK4 (1 << 5)
+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK5 (1 << 6)
+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK6 (1 << 7)
+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0 (1 << 8)
+
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK (0xff << 20)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(x) (((x) & 0xff) << 20)
@@ -366,31 +377,6 @@
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
- value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
- value &= ~CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL;
- value &= ~CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL;
- value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET;
- value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ;
- writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
-
- value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
- value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD;
- padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
-
- value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
- value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD;
- padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
-
- value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
- value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD;
- padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
-
- udelay(1);
-
- value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
- value |= CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE;
- writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
-
debug("< %s()\n", __func__);
return 0;
}
@@ -454,3 +440,35 @@
ret = tegra_xusb_process_nodes(nodes, count, &tegra210_socdata);
debug("%s: done, ret=%d\n", __func__, ret);
}
+
+void tegra_xusb_padctl_exit(void)
+{
+ u32 value;
+
+ debug("> %s\n", __func__);
+
+ value = padctl_readl(&padctl, XUSB_PADCTL_USB3_PAD_MUX);
+ value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE;
+ value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0;
+ value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1;
+ value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2;
+ value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK3;
+ value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK4;
+ value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK5;
+ value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK6;
+ value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0;
+ padctl_writel(&padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
+
+ value = padctl_readl(&padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
+ value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ;
+ value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK;
+ value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP(3);
+ value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE;
+ padctl_writel(&padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
+
+ reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 1);
+ while (padctl.enable)
+ tegra_xusb_padctl_disable(&padctl);
+
+ debug("< %s()\n", __func__);
+}
diff --git a/arch/arm/mach-tegra/xusb-padctl-dummy.c b/arch/arm/mach-tegra/xusb-padctl-dummy.c
index 3ec27a2..f2d9030 100644
--- a/arch/arm/mach-tegra/xusb-padctl-dummy.c
+++ b/arch/arm/mach-tegra/xusb-padctl-dummy.c
@@ -36,3 +36,7 @@
void __weak tegra_xusb_padctl_init(void)
{
}
+
+void __weak tegra_xusb_padctl_exit(void)
+{
+}
diff --git a/arch/mips/config.mk b/arch/mips/config.mk
index 9d3a845..527fd6a 100644
--- a/arch/mips/config.mk
+++ b/arch/mips/config.mk
@@ -36,7 +36,6 @@
endif
PLATFORM_CPPFLAGS += -D__MIPS__
-PLATFORM_ELFENTRY = "__start"
PLATFORM_ELFFLAGS += -B mips $(OBJCOPYFLAGS)
#
diff --git a/arch/u-boot-elf.lds b/arch/u-boot-elf.lds
new file mode 100644
index 0000000..1666027
--- /dev/null
+++ b/arch/u-boot-elf.lds
@@ -0,0 +1,9 @@
+ENTRY(CONFIG_PLATFORM_ELFENTRY)
+SECTIONS
+{
+ . = CONFIG_PLATFORM_ELFENTRY;
+
+ .data : {
+ *(.data*)
+ }
+}
diff --git a/board/nvidia/e2220-1170/e2220-1170.c b/board/nvidia/e2220-1170/e2220-1170.c
index 8baaf2c..5aac040 100644
--- a/board/nvidia/e2220-1170/e2220-1170.c
+++ b/board/nvidia/e2220-1170/e2220-1170.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * (C) Copyright 2013-2015
+ * (C) Copyright 2013-2019
* NVIDIA Corporation <www.nvidia.com>
*/
@@ -9,7 +9,6 @@
#include <asm/arch/gpio.h>
#include <asm/arch/pinmux.h>
#include "../p2571/max77620_init.h"
-#include "pinmux-config-e2220-1170.h"
void pin_mux_mmc(void)
{
@@ -30,21 +29,3 @@
if (ret)
printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret);
}
-
-/*
- * Routine: pinmux_init
- * Description: Do individual peripheral pinmux configs
- */
-void pinmux_init(void)
-{
- pinmux_clear_tristate_input_clamping();
-
- gpio_config_table(e2220_1170_gpio_inits,
- ARRAY_SIZE(e2220_1170_gpio_inits));
-
- pinmux_config_pingrp_table(e2220_1170_pingrps,
- ARRAY_SIZE(e2220_1170_pingrps));
-
- pinmux_config_drvgrp_table(e2220_1170_drvgrps,
- ARRAY_SIZE(e2220_1170_drvgrps));
-}
diff --git a/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h b/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h
deleted file mode 100644
index 14bbfbf..0000000
--- a/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h
+++ /dev/null
@@ -1,276 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
- */
-
-/*
- * THIS FILE IS AUTO-GENERATED - DO NOT EDIT!
- *
- * To generate this file, use the tegra-pinmux-scripts tool available from
- * https://github.com/NVIDIA/tegra-pinmux-scripts
- * Run "board-to-uboot.py e2220-1170".
- */
-
-#ifndef _PINMUX_CONFIG_E2220_1170_H_
-#define _PINMUX_CONFIG_E2220_1170_H_
-
-#define GPIO_INIT(_port, _gpio, _init) \
- { \
- .gpio = TEGRA_GPIO(_port, _gpio), \
- .init = TEGRA_GPIO_INIT_##_init, \
- }
-
-static const struct tegra_gpio_config e2220_1170_gpio_inits[] = {
- /* port, pin, init_val */
- GPIO_INIT(A, 5, IN),
- GPIO_INIT(A, 6, IN),
- GPIO_INIT(B, 4, IN),
- GPIO_INIT(E, 6, IN),
- GPIO_INIT(G, 2, OUT0),
- GPIO_INIT(G, 3, OUT0),
- GPIO_INIT(H, 0, OUT0),
- GPIO_INIT(H, 1, OUT0),
- GPIO_INIT(H, 2, IN),
- GPIO_INIT(H, 3, OUT0),
- GPIO_INIT(H, 4, OUT0),
- GPIO_INIT(H, 5, IN),
- GPIO_INIT(H, 6, OUT0),
- GPIO_INIT(H, 7, OUT0),
- GPIO_INIT(I, 0, OUT0),
- GPIO_INIT(I, 1, IN),
- GPIO_INIT(I, 2, OUT0),
- GPIO_INIT(I, 3, OUT0),
- GPIO_INIT(K, 0, IN),
- GPIO_INIT(K, 1, OUT0),
- GPIO_INIT(K, 2, OUT0),
- GPIO_INIT(K, 3, OUT0),
- GPIO_INIT(K, 4, IN),
- GPIO_INIT(K, 5, OUT0),
- GPIO_INIT(K, 6, IN),
- GPIO_INIT(K, 7, OUT0),
- GPIO_INIT(L, 0, OUT0),
- GPIO_INIT(S, 4, OUT0),
- GPIO_INIT(S, 5, OUT0),
- GPIO_INIT(S, 6, OUT0),
- GPIO_INIT(S, 7, OUT0),
- GPIO_INIT(T, 0, OUT0),
- GPIO_INIT(T, 1, OUT0),
- GPIO_INIT(V, 1, OUT0),
- GPIO_INIT(V, 2, OUT0),
- GPIO_INIT(V, 3, IN),
- GPIO_INIT(V, 5, OUT0),
- GPIO_INIT(V, 6, OUT0),
- GPIO_INIT(X, 0, IN),
- GPIO_INIT(X, 1, IN),
- GPIO_INIT(X, 2, IN),
- GPIO_INIT(X, 3, IN),
- GPIO_INIT(X, 4, IN),
- GPIO_INIT(X, 5, IN),
- GPIO_INIT(X, 6, IN),
- GPIO_INIT(X, 7, IN),
- GPIO_INIT(Y, 0, IN),
- GPIO_INIT(Y, 1, IN),
- GPIO_INIT(Z, 0, IN),
- GPIO_INIT(Z, 4, OUT0),
- GPIO_INIT(BB, 2, OUT0),
- GPIO_INIT(BB, 3, OUT0),
- GPIO_INIT(BB, 4, IN),
- GPIO_INIT(CC, 1, IN),
- GPIO_INIT(CC, 5, OUT0),
- GPIO_INIT(CC, 6, IN),
- GPIO_INIT(CC, 7, OUT0),
-};
-
-#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \
- { \
- .pingrp = PMUX_PINGRP_##_pingrp, \
- .func = PMUX_FUNC_##_mux, \
- .pull = PMUX_PULL_##_pull, \
- .tristate = PMUX_TRI_##_tri, \
- .io = PMUX_PIN_##_io, \
- .od = PMUX_PIN_OD_##_od, \
- .e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \
- .lock = PMUX_PIN_LOCK_DEFAULT, \
- }
-
-static const struct pmux_pingrp_config e2220_1170_pingrps[] = {
- /* pingrp, mux, pull, tri, e_input, od, e_io_hv */
- PINCFG(PEX_L0_RST_N_PA0, PE0, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL),
- PINCFG(PEX_L0_CLKREQ_N_PA1, PE0, UP, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(PEX_WAKE_N_PA2, PE, UP, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(PEX_L1_RST_N_PA3, PE1, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL),
- PINCFG(PEX_L1_CLKREQ_N_PA4, PE1, UP, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PA6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DAP1_FS_PB0, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DAP1_DIN_PB1, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DAP1_DOUT_PB2, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DAP1_SCLK_PB3, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SPI2_MOSI_PB4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SPI2_MISO_PB5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(SPI2_SCK_PB6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(SPI2_CS0_PB7, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(SPI1_MOSI_PC0, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(SPI1_MISO_PC1, SPI1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SPI1_SCK_PC2, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(SPI1_CS0_PC3, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(SPI1_CS1_PC4, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(SPI4_SCK_PC5, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(SPI4_CS0_PC6, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(SPI4_MOSI_PC7, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(SPI4_MISO_PD0, SPI4, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(UART3_TX_PD1, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART3_RX_PD2, UARTC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(UART3_RTS_PD3, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART3_CTS_PD4, UARTC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DMIC1_CLK_PE0, DMIC1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(DMIC1_DAT_PE1, DMIC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DMIC2_CLK_PE2, DMIC2, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(DMIC2_DAT_PE3, DMIC2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DMIC3_CLK_PE4, DMIC3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(DMIC3_DAT_PE5, DMIC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PE6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(UART2_TX_PG0, UART, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART2_RX_PG1, UART, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(UART2_RTS_PG2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART2_CTS_PG3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(WIFI_RST_PH1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PH6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(AP_WAKE_NFC_PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(NFC_INT_PI1, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(GPS_EN_PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(GPS_RST_PI3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART4_CTS_PI7, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(DAP4_FS_PJ4, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DAP4_DIN_PJ5, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DAP4_DOUT_PJ6, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DAP4_SCLK_PJ7, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PK0, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(PK2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(PK3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(PK4, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PK5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(PK6, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PK7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(PL0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(PL1, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(CAM1_MCLK_PS0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(CAM2_MCLK_PS1, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(CAM_RST_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(CAM_AF_EN_PS5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(CAM_FLASH_EN_PS6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(CAM1_PWDN_PS7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(CAM2_PWDN_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(CAM1_STROBE_PT1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART1_RX_PU1, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(UART1_RTS_PU2, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART1_CTS_PU3, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(LCD_BL_PWM_PV0, PWM0, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(LCD_RST_PV2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(LCD_GPIO1_PV3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(AP_READY_PV5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(TOUCH_RST_PV6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(TOUCH_CLK_PV7, TOUCH, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(MODEM_WAKE_AP_PX0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(TOUCH_INT_PX1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(MOTION_INT_PX2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(ALS_PROX_INT_PX3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(BUTTON_POWER_ON_PX5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(BUTTON_VOL_DOWN_PX7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(BUTTON_SLIDE_SW_PY0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(LCD_TE_PY2, DISPLAYA, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(CLK_32K_OUT_PY5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PZ2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PZ3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PZ4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(AUD_MCLK_PBB0, AUD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(DVFS_CLK_PBB2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(GPIO_X1_AUD_PBB3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(GPIO_X3_AUD_PBB4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
- PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(SPDIF_OUT_PCC2, SPDIF, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(SPDIF_IN_PCC3, SPDIF, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(USB_VBUS_EN0_PCC4, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
- PINCFG(USB_VBUS_EN1_PCC5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL),
- PINCFG(DP_HPD0_PCC6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PCC7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL),
- PINCFG(SPI2_CS1_PDD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_SCK_PEE0, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_CS_N_PEE1, QSPI, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_IO0_PEE2, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_IO1_PEE3, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_IO2_PEE4, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_IO3_PEE5, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(CLK_REQ, SYS, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
-};
-
-#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
- { \
- .drvgrp = PMUX_DRVGRP_##_drvgrp, \
- .slwf = _slwf, \
- .slwr = _slwr, \
- .drvup = _drvup, \
- .drvdn = _drvdn, \
- .lpmd = PMUX_LPMD_##_lpmd, \
- .schmt = PMUX_SCHMT_##_schmt, \
- .hsm = PMUX_HSM_##_hsm, \
- }
-
-static const struct pmux_drvgrp_config e2220_1170_drvgrps[] = {
-};
-
-#endif /* PINMUX_CONFIG_E2220_1170_H */
diff --git a/board/nvidia/p2371-0000/p2371-0000.c b/board/nvidia/p2371-0000/p2371-0000.c
index e0c907b..5aac040 100644
--- a/board/nvidia/p2371-0000/p2371-0000.c
+++ b/board/nvidia/p2371-0000/p2371-0000.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * (C) Copyright 2013-2015
+ * (C) Copyright 2013-2019
* NVIDIA Corporation <www.nvidia.com>
*/
@@ -9,7 +9,6 @@
#include <asm/arch/gpio.h>
#include <asm/arch/pinmux.h>
#include "../p2571/max77620_init.h"
-#include "pinmux-config-p2371-0000.h"
void pin_mux_mmc(void)
{
@@ -30,21 +29,3 @@
if (ret)
printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret);
}
-
-/*
- * Routine: pinmux_init
- * Description: Do individual peripheral pinmux configs
- */
-void pinmux_init(void)
-{
- pinmux_clear_tristate_input_clamping();
-
- gpio_config_table(p2371_0000_gpio_inits,
- ARRAY_SIZE(p2371_0000_gpio_inits));
-
- pinmux_config_pingrp_table(p2371_0000_pingrps,
- ARRAY_SIZE(p2371_0000_pingrps));
-
- pinmux_config_drvgrp_table(p2371_0000_drvgrps,
- ARRAY_SIZE(p2371_0000_drvgrps));
-}
diff --git a/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h b/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h
deleted file mode 100644
index aa5d7f9..0000000
--- a/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h
+++ /dev/null
@@ -1,267 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
- */
-
-/*
- * THIS FILE IS AUTO-GENERATED - DO NOT EDIT!
- *
- * To generate this file, use the tegra-pinmux-scripts tool available from
- * https://github.com/NVIDIA/tegra-pinmux-scripts
- * Run "board-to-uboot.py p2371-0000".
- */
-
-#ifndef _PINMUX_CONFIG_P2371_0000_H_
-#define _PINMUX_CONFIG_P2371_0000_H_
-
-#define GPIO_INIT(_port, _gpio, _init) \
- { \
- .gpio = TEGRA_GPIO(_port, _gpio), \
- .init = TEGRA_GPIO_INIT_##_init, \
- }
-
-static const struct tegra_gpio_config p2371_0000_gpio_inits[] = {
- /* port, pin, init_val */
- GPIO_INIT(A, 5, IN),
- GPIO_INIT(E, 4, OUT0),
- GPIO_INIT(E, 6, IN),
- GPIO_INIT(G, 0, IN),
- GPIO_INIT(G, 3, OUT0),
- GPIO_INIT(H, 0, OUT0),
- GPIO_INIT(H, 2, IN),
- GPIO_INIT(H, 3, OUT0),
- GPIO_INIT(H, 4, OUT0),
- GPIO_INIT(H, 5, IN),
- GPIO_INIT(H, 6, OUT0),
- GPIO_INIT(H, 7, OUT0),
- GPIO_INIT(I, 0, OUT0),
- GPIO_INIT(I, 1, IN),
- GPIO_INIT(I, 2, OUT0),
- GPIO_INIT(I, 3, OUT0),
- GPIO_INIT(K, 4, IN),
- GPIO_INIT(K, 5, OUT0),
- GPIO_INIT(K, 6, IN),
- GPIO_INIT(K, 7, OUT0),
- GPIO_INIT(L, 0, OUT0),
- GPIO_INIT(S, 4, OUT0),
- GPIO_INIT(S, 5, OUT0),
- GPIO_INIT(S, 6, OUT0),
- GPIO_INIT(S, 7, OUT0),
- GPIO_INIT(T, 0, OUT0),
- GPIO_INIT(T, 1, OUT0),
- GPIO_INIT(V, 1, OUT0),
- GPIO_INIT(V, 2, OUT0),
- GPIO_INIT(V, 5, OUT0),
- GPIO_INIT(V, 6, OUT0),
- GPIO_INIT(V, 7, OUT1),
- GPIO_INIT(X, 0, IN),
- GPIO_INIT(X, 1, IN),
- GPIO_INIT(X, 2, IN),
- GPIO_INIT(X, 3, IN),
- GPIO_INIT(X, 4, IN),
- GPIO_INIT(X, 5, IN),
- GPIO_INIT(X, 6, IN),
- GPIO_INIT(X, 7, IN),
- GPIO_INIT(Y, 1, IN),
- GPIO_INIT(Z, 0, IN),
- GPIO_INIT(Z, 4, OUT0),
- GPIO_INIT(BB, 2, OUT0),
- GPIO_INIT(BB, 3, OUT0),
- GPIO_INIT(CC, 1, IN),
- GPIO_INIT(CC, 6, IN),
- GPIO_INIT(CC, 7, OUT0),
-};
-
-#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \
- { \
- .pingrp = PMUX_PINGRP_##_pingrp, \
- .func = PMUX_FUNC_##_mux, \
- .pull = PMUX_PULL_##_pull, \
- .tristate = PMUX_TRI_##_tri, \
- .io = PMUX_PIN_##_io, \
- .od = PMUX_PIN_OD_##_od, \
- .e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \
- .lock = PMUX_PIN_LOCK_DEFAULT, \
- }
-
-static const struct pmux_pingrp_config p2371_0000_pingrps[] = {
- /* pingrp, mux, pull, tri, e_input, od, e_io_hv */
- PINCFG(PEX_L0_RST_N_PA0, PE0, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH),
- PINCFG(PEX_L0_CLKREQ_N_PA1, PE0, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
- PINCFG(PEX_WAKE_N_PA2, PE, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
- PINCFG(PEX_L1_RST_N_PA3, PE1, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH),
- PINCFG(PEX_L1_CLKREQ_N_PA4, PE1, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
- PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PA6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(DAP1_FS_PB0, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DAP1_DIN_PB1, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DAP1_DOUT_PB2, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DAP1_SCLK_PB3, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SPI2_MOSI_PB4, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(SPI2_MISO_PB5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(SPI2_SCK_PB6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(SPI2_CS0_PB7, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(SPI1_MOSI_PC0, SPI1, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SPI1_MISO_PC1, SPI1, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SPI1_SCK_PC2, SPI1, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SPI1_CS0_PC3, SPI1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SPI1_CS1_PC4, SPI1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SPI4_SCK_PC5, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(SPI4_CS0_PC6, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(SPI4_MOSI_PC7, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(SPI4_MISO_PD0, SPI4, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(UART3_TX_PD1, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART3_RX_PD2, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(UART3_RTS_PD3, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART3_CTS_PD4, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DMIC1_CLK_PE0, DMIC1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(DMIC1_DAT_PE1, DMIC1, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DMIC2_CLK_PE2, DMIC2, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(DMIC2_DAT_PE3, DMIC2, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DMIC3_CLK_PE4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(DMIC3_DAT_PE5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(PE6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(UART2_TX_PG0, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(UART2_RX_PG1, UARTB, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART2_RTS_PG2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART2_CTS_PG3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(WIFI_RST_PH1, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PH6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(AP_WAKE_NFC_PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(NFC_INT_PI1, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(GPS_EN_PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(GPS_RST_PI3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART4_CTS_PI7, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
- PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
- PINCFG(DAP4_FS_PJ4, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DAP4_DIN_PJ5, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DAP4_DOUT_PJ6, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DAP4_SCLK_PJ7, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PK0, I2S5B, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PK1, I2S5B, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PK2, I2S5B, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PK3, I2S5B, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PK4, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PK5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(PK6, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PK7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(PL0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(PL1, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(CAM1_MCLK_PS0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(CAM2_MCLK_PS1, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(CAM_RST_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(CAM_AF_EN_PS5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(CAM_FLASH_EN_PS6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(CAM1_PWDN_PS7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(CAM2_PWDN_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(CAM1_STROBE_PT1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART1_RX_PU1, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(UART1_RTS_PU2, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART1_CTS_PU3, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(LCD_BL_PWM_PV0, PWM0, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(LCD_RST_PV2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(LCD_GPIO1_PV3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(AP_READY_PV5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(TOUCH_RST_PV6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(TOUCH_CLK_PV7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(MODEM_WAKE_AP_PX0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(TOUCH_INT_PX1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(MOTION_INT_PX2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(ALS_PROX_INT_PX3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(BUTTON_POWER_ON_PX5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(BUTTON_VOL_DOWN_PX7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(BUTTON_SLIDE_SW_PY0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(LCD_TE_PY2, DISPLAYA, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(CLK_32K_OUT_PY5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PZ2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(PZ3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(PZ4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(AUD_MCLK_PBB0, AUD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(DVFS_CLK_PBB2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(GPIO_X1_AUD_PBB3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(GPIO_X3_AUD_PBB4, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
- PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(SPDIF_OUT_PCC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(SPDIF_IN_PCC3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(USB_VBUS_EN0_PCC4, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
- PINCFG(USB_VBUS_EN1_PCC5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
- PINCFG(DP_HPD0_PCC6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PCC7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL),
- PINCFG(SPI2_CS1_PDD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_SCK_PEE0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_CS_N_PEE1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_IO0_PEE2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_IO1_PEE3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_IO2_PEE4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_IO3_PEE5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(CLK_REQ, SYS, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
-};
-
-#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
- { \
- .drvgrp = PMUX_DRVGRP_##_drvgrp, \
- .slwf = _slwf, \
- .slwr = _slwr, \
- .drvup = _drvup, \
- .drvdn = _drvdn, \
- .lpmd = PMUX_LPMD_##_lpmd, \
- .schmt = PMUX_SCHMT_##_schmt, \
- .hsm = PMUX_HSM_##_hsm, \
- }
-
-static const struct pmux_drvgrp_config p2371_0000_drvgrps[] = {
-};
-
-#endif /* PINMUX_CONFIG_P2371_0000_H */
diff --git a/board/nvidia/p2371-2180/p2371-2180.c b/board/nvidia/p2371-2180/p2371-2180.c
index fa5288b..1756bbc 100644
--- a/board/nvidia/p2371-2180/p2371-2180.c
+++ b/board/nvidia/p2371-2180/p2371-2180.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * (C) Copyright 2013-2015
+ * (C) Copyright 2013-2019
* NVIDIA Corporation <www.nvidia.com>
*/
@@ -13,7 +13,6 @@
#include <asm/arch/pinmux.h>
#include <asm/arch-tegra/cboot.h>
#include "../p2571/max77620_init.h"
-#include "pinmux-config-p2371-2180.h"
void pin_mux_mmc(void)
{
@@ -57,24 +56,6 @@
}
}
-/*
- * Routine: pinmux_init
- * Description: Do individual peripheral pinmux configs
- */
-void pinmux_init(void)
-{
- pinmux_clear_tristate_input_clamping();
-
- gpio_config_table(p2371_2180_gpio_inits,
- ARRAY_SIZE(p2371_2180_gpio_inits));
-
- pinmux_config_pingrp_table(p2371_2180_pingrps,
- ARRAY_SIZE(p2371_2180_pingrps));
-
- pinmux_config_drvgrp_table(p2371_2180_drvgrps,
- ARRAY_SIZE(p2371_2180_drvgrps));
-}
-
#ifdef CONFIG_PCI_TEGRA
int tegra_pcie_board_init(void)
{
diff --git a/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h b/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h
deleted file mode 100644
index d9abfa7..0000000
--- a/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h
+++ /dev/null
@@ -1,278 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
- */
-
-/*
- * THIS FILE IS AUTO-GENERATED - DO NOT EDIT!
- *
- * To generate this file, use the tegra-pinmux-scripts tool available from
- * https://github.com/NVIDIA/tegra-pinmux-scripts
- * Run "board-to-uboot.py p2371-2180".
- */
-
-#ifndef _PINMUX_CONFIG_P2371_2180_H_
-#define _PINMUX_CONFIG_P2371_2180_H_
-
-#define GPIO_INIT(_port, _gpio, _init) \
- { \
- .gpio = TEGRA_GPIO(_port, _gpio), \
- .init = TEGRA_GPIO_INIT_##_init, \
- }
-
-static const struct tegra_gpio_config p2371_2180_gpio_inits[] = {
- /* port, pin, init_val */
- GPIO_INIT(A, 5, IN),
- GPIO_INIT(B, 0, IN),
- GPIO_INIT(B, 1, IN),
- GPIO_INIT(B, 2, IN),
- GPIO_INIT(B, 3, IN),
- GPIO_INIT(C, 0, IN),
- GPIO_INIT(C, 1, IN),
- GPIO_INIT(C, 2, IN),
- GPIO_INIT(C, 3, IN),
- GPIO_INIT(C, 4, IN),
- GPIO_INIT(E, 4, IN),
- GPIO_INIT(E, 5, IN),
- GPIO_INIT(E, 6, IN),
- GPIO_INIT(H, 0, OUT0),
- GPIO_INIT(H, 1, OUT0),
- GPIO_INIT(H, 2, IN),
- GPIO_INIT(H, 3, OUT0),
- GPIO_INIT(H, 4, OUT0),
- GPIO_INIT(H, 5, IN),
- GPIO_INIT(H, 6, IN),
- GPIO_INIT(H, 7, IN),
- GPIO_INIT(I, 0, OUT0),
- GPIO_INIT(I, 1, IN),
- GPIO_INIT(I, 2, OUT0),
- GPIO_INIT(K, 4, IN),
- GPIO_INIT(K, 5, OUT0),
- GPIO_INIT(K, 6, IN),
- GPIO_INIT(K, 7, IN),
- GPIO_INIT(L, 1, IN),
- GPIO_INIT(S, 4, OUT0),
- GPIO_INIT(S, 5, OUT0),
- GPIO_INIT(S, 6, OUT0),
- GPIO_INIT(S, 7, OUT0),
- GPIO_INIT(T, 0, OUT0),
- GPIO_INIT(T, 1, OUT0),
- GPIO_INIT(U, 2, IN),
- GPIO_INIT(U, 3, IN),
- GPIO_INIT(V, 1, OUT0),
- GPIO_INIT(V, 2, OUT0),
- GPIO_INIT(V, 3, IN),
- GPIO_INIT(V, 5, OUT0),
- GPIO_INIT(V, 6, OUT0),
- GPIO_INIT(X, 0, IN),
- GPIO_INIT(X, 1, IN),
- GPIO_INIT(X, 2, IN),
- GPIO_INIT(X, 3, IN),
- GPIO_INIT(X, 4, IN),
- GPIO_INIT(X, 5, IN),
- GPIO_INIT(X, 6, IN),
- GPIO_INIT(X, 7, IN),
- GPIO_INIT(Y, 0, IN),
- GPIO_INIT(Y, 1, IN),
- GPIO_INIT(Z, 0, IN),
- GPIO_INIT(Z, 2, IN),
- GPIO_INIT(Z, 3, OUT0),
- GPIO_INIT(BB, 0, IN),
- GPIO_INIT(BB, 2, OUT0),
- GPIO_INIT(BB, 3, IN),
- GPIO_INIT(CC, 1, IN),
-};
-
-#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \
- { \
- .pingrp = PMUX_PINGRP_##_pingrp, \
- .func = PMUX_FUNC_##_mux, \
- .pull = PMUX_PULL_##_pull, \
- .tristate = PMUX_TRI_##_tri, \
- .io = PMUX_PIN_##_io, \
- .od = PMUX_PIN_OD_##_od, \
- .e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \
- .lock = PMUX_PIN_LOCK_DEFAULT, \
- }
-
-static const struct pmux_pingrp_config p2371_2180_pingrps[] = {
- /* pingrp, mux, pull, tri, e_input, od, e_io_hv */
- PINCFG(PEX_L0_RST_N_PA0, PE0, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH),
- PINCFG(PEX_L0_CLKREQ_N_PA1, PE0, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
- PINCFG(PEX_WAKE_N_PA2, PE, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
- PINCFG(PEX_L1_RST_N_PA3, PE1, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH),
- PINCFG(PEX_L1_CLKREQ_N_PA4, PE1, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
- PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PA6, SATA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(DAP1_FS_PB0, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DAP1_DIN_PB1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DAP1_DOUT_PB2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DAP1_SCLK_PB3, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SPI2_MOSI_PB4, SPI2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SPI2_MISO_PB5, SPI2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SPI2_SCK_PB6, SPI2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SPI2_CS0_PB7, SPI2, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SPI1_MOSI_PC0, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SPI1_MISO_PC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SPI1_SCK_PC2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SPI1_CS0_PC3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SPI1_CS1_PC4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SPI4_SCK_PC5, SPI4, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SPI4_CS0_PC6, SPI4, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SPI4_MOSI_PC7, SPI4, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SPI4_MISO_PD0, SPI4, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(UART3_TX_PD1, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART3_RX_PD2, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(UART3_RTS_PD3, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART3_CTS_PD4, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DMIC1_CLK_PE0, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DMIC1_DAT_PE1, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DMIC2_CLK_PE2, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DMIC2_DAT_PE3, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DMIC3_CLK_PE4, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DMIC3_DAT_PE5, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PE6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(UART2_TX_PG0, UARTB, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART2_RX_PG1, UARTB, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(UART2_RTS_PG2, UARTB, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART2_CTS_PG3, UARTB, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(WIFI_RST_PH1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PH6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(AP_WAKE_NFC_PH7, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(NFC_INT_PI1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(GPS_EN_PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(GPS_RST_PI3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART4_CTS_PI7, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
- PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
- PINCFG(DAP4_FS_PJ4, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DAP4_DIN_PJ5, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DAP4_DOUT_PJ6, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DAP4_SCLK_PJ7, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PK0, I2S5B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PK1, I2S5B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PK2, I2S5B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PK3, I2S5B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PK4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PK5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(PK6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PK7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PL0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(PL1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(CAM1_MCLK_PS0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(CAM2_MCLK_PS1, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(CAM_RST_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(CAM_AF_EN_PS5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(CAM_FLASH_EN_PS6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(CAM1_PWDN_PS7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(CAM2_PWDN_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(CAM1_STROBE_PT1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART1_RX_PU1, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(UART1_RTS_PU2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(UART1_CTS_PU3, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(LCD_BL_PWM_PV0, PWM0, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(LCD_RST_PV2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(LCD_GPIO1_PV3, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(AP_READY_PV5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(TOUCH_RST_PV6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(TOUCH_CLK_PV7, TOUCH, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(MODEM_WAKE_AP_PX0, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(TOUCH_INT_PX1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(MOTION_INT_PX2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(ALS_PROX_INT_PX3, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(BUTTON_POWER_ON_PX5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(BUTTON_VOL_DOWN_PX7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(BUTTON_SLIDE_SW_PY0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(LCD_TE_PY2, DISPLAYA, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(CLK_32K_OUT_PY5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PZ2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PZ3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(PZ4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(AUD_MCLK_PBB0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(DVFS_CLK_PBB2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(GPIO_X1_AUD_PBB3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(GPIO_X3_AUD_PBB4, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
- PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(SPDIF_OUT_PCC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(SPDIF_IN_PCC3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(USB_VBUS_EN0_PCC4, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
- PINCFG(USB_VBUS_EN1_PCC5, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
- PINCFG(DP_HPD0_PCC6, DP, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PCC7, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
- PINCFG(SPI2_CS1_PDD0, SPI2, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_SCK_PEE0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_CS_N_PEE1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_IO0_PEE2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_IO1_PEE3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_IO2_PEE4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_IO3_PEE5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(CLK_REQ, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
-};
-
-#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
- { \
- .drvgrp = PMUX_DRVGRP_##_drvgrp, \
- .slwf = _slwf, \
- .slwr = _slwr, \
- .drvup = _drvup, \
- .drvdn = _drvdn, \
- .lpmd = PMUX_LPMD_##_lpmd, \
- .schmt = PMUX_SCHMT_##_schmt, \
- .hsm = PMUX_HSM_##_hsm, \
- }
-
-static const struct pmux_drvgrp_config p2371_2180_drvgrps[] = {
-};
-
-#endif /* PINMUX_CONFIG_P2371_2180_H */
diff --git a/board/nvidia/p2571/p2571.c b/board/nvidia/p2571/p2571.c
index dba3579a..a9e4d21 100644
--- a/board/nvidia/p2571/p2571.c
+++ b/board/nvidia/p2571/p2571.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * (C) Copyright 2013-2015
+ * (C) Copyright 2013-2019
* NVIDIA Corporation <www.nvidia.com>
*/
@@ -10,7 +10,6 @@
#include <asm/arch/pinmux.h>
#include <asm/gpio.h>
#include "max77620_init.h"
-#include "pinmux-config-p2571.h"
void pin_mux_mmc(void)
{
@@ -33,24 +32,6 @@
}
/*
- * Routine: pinmux_init
- * Description: Do individual peripheral pinmux configs
- */
-void pinmux_init(void)
-{
- pinmux_clear_tristate_input_clamping();
-
- gpio_config_table(p2571_gpio_inits,
- ARRAY_SIZE(p2571_gpio_inits));
-
- pinmux_config_pingrp_table(p2571_pingrps,
- ARRAY_SIZE(p2571_pingrps));
-
- pinmux_config_drvgrp_table(p2571_drvgrps,
- ARRAY_SIZE(p2571_drvgrps));
-}
-
-/*
* Routine: start_cpu_fan
* Description: Enable/start PWM CPU fan on P2571
*/
diff --git a/board/nvidia/p2571/pinmux-config-p2571.h b/board/nvidia/p2571/pinmux-config-p2571.h
deleted file mode 100644
index 04bb6ce..0000000
--- a/board/nvidia/p2571/pinmux-config-p2571.h
+++ /dev/null
@@ -1,242 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
- */
-
-/*
- * THIS FILE IS AUTO-GENERATED - DO NOT EDIT!
- *
- * To generate this file, use the tegra-pinmux-scripts tool available from
- * https://github.com/NVIDIA/tegra-pinmux-scripts
- * Run "board-to-uboot.py p2571".
- */
-
-#ifndef _PINMUX_CONFIG_P2571_H_
-#define _PINMUX_CONFIG_P2571_H_
-
-#define GPIO_INIT(_port, _gpio, _init) \
- { \
- .gpio = TEGRA_GPIO(_port, _gpio), \
- .init = TEGRA_GPIO_INIT_##_init, \
- }
-
-static const struct tegra_gpio_config p2571_gpio_inits[] = {
- /* port, pin, init_val */
- GPIO_INIT(A, 0, IN),
- GPIO_INIT(A, 5, IN),
- GPIO_INIT(D, 4, IN),
- GPIO_INIT(E, 4, OUT0),
- GPIO_INIT(G, 0, IN),
- GPIO_INIT(H, 0, OUT0),
- GPIO_INIT(H, 2, IN),
- GPIO_INIT(H, 3, OUT0),
- GPIO_INIT(H, 4, OUT0),
- GPIO_INIT(H, 5, IN),
- GPIO_INIT(I, 0, OUT0),
- GPIO_INIT(I, 1, IN),
- GPIO_INIT(V, 1, OUT0),
- GPIO_INIT(V, 6, OUT1),
- GPIO_INIT(X, 4, IN),
- GPIO_INIT(X, 6, IN),
- GPIO_INIT(X, 7, IN),
- GPIO_INIT(Y, 1, IN),
- GPIO_INIT(Z, 0, IN),
- GPIO_INIT(Z, 4, OUT0),
- GPIO_INIT(BB, 2, OUT0),
- GPIO_INIT(CC, 1, IN),
- GPIO_INIT(CC, 3, IN),
-};
-
-#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \
- { \
- .pingrp = PMUX_PINGRP_##_pingrp, \
- .func = PMUX_FUNC_##_mux, \
- .pull = PMUX_PULL_##_pull, \
- .tristate = PMUX_TRI_##_tri, \
- .io = PMUX_PIN_##_io, \
- .od = PMUX_PIN_OD_##_od, \
- .e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \
- .lock = PMUX_PIN_LOCK_DEFAULT, \
- }
-
-static const struct pmux_pingrp_config p2571_pingrps[] = {
- /* pingrp, mux, pull, tri, e_input, od, e_io_hv */
- PINCFG(PEX_L0_RST_N_PA0, DEFAULT, UP, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(PEX_L0_CLKREQ_N_PA1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
- PINCFG(PEX_WAKE_N_PA2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
- PINCFG(PEX_L1_RST_N_PA3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
- PINCFG(PEX_L1_CLKREQ_N_PA4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
- PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PA6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(DAP1_FS_PB0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(DAP1_DIN_PB1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(DAP1_DOUT_PB2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(DAP1_SCLK_PB3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(SPI2_MOSI_PB4, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(SPI2_MISO_PB5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(SPI2_SCK_PB6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(SPI2_CS0_PB7, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(SPI1_MOSI_PC0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(SPI1_MISO_PC1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(SPI1_SCK_PC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(SPI1_CS0_PC3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(SPI1_CS1_PC4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(SPI4_SCK_PC5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(SPI4_CS0_PC6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(SPI4_MOSI_PC7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(SPI4_MISO_PD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART3_TX_PD1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART3_RX_PD2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART3_RTS_PD3, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART3_CTS_PD4, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DMIC1_CLK_PE0, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DMIC1_DAT_PE1, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DMIC2_CLK_PE2, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DMIC2_DAT_PE3, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DMIC3_CLK_PE4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(DMIC3_DAT_PE5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(PE6, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(UART2_TX_PG0, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(UART2_RX_PG1, UARTB, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART2_RTS_PG2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART2_CTS_PG3, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(WIFI_RST_PH1, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PH6, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(AP_WAKE_NFC_PH7, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(NFC_INT_PI1, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(GPS_EN_PI2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(GPS_RST_PI3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART4_CTS_PI7, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
- PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
- PINCFG(DAP4_FS_PJ4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(DAP4_DIN_PJ5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(DAP4_DOUT_PJ6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(DAP4_SCLK_PJ7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(PK0, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(PK1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(PK2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(PK3, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(PK4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(PK5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(PK6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(PK7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(PL0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(PL1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(CAM1_MCLK_PS0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(CAM2_MCLK_PS1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(CAM_RST_PS4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(CAM_AF_EN_PS5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(CAM_FLASH_EN_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(CAM1_PWDN_PS7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(CAM2_PWDN_PT0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(CAM1_STROBE_PT1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART1_RX_PU1, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(UART1_RTS_PU2, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART1_CTS_PU3, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(LCD_BL_PWM_PV0, PWM0, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(LCD_RST_PV2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(LCD_GPIO1_PV3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(AP_READY_PV5, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(TOUCH_RST_PV6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(TOUCH_CLK_PV7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(MODEM_WAKE_AP_PX0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(TOUCH_INT_PX1, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(MOTION_INT_PX2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(ALS_PROX_INT_PX3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(BUTTON_POWER_ON_PX5, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(BUTTON_VOL_DOWN_PX7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(BUTTON_SLIDE_SW_PY0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(LCD_TE_PY2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(CLK_32K_OUT_PY5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(PZ2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(PZ3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(PZ4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(AUD_MCLK_PBB0, AUD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(DVFS_CLK_PBB2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(GPIO_X1_AUD_PBB3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(GPIO_X3_AUD_PBB4, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
- PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, NORMAL),
- PINCFG(SPDIF_OUT_PCC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(SPDIF_IN_PCC3, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(USB_VBUS_EN0_PCC4, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
- PINCFG(USB_VBUS_EN1_PCC5, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
- PINCFG(DP_HPD0_PCC6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(PCC7, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
- PINCFG(SPI2_CS1_PDD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_SCK_PEE0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_CS_N_PEE1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_IO0_PEE2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_IO1_PEE3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_IO2_PEE4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_IO3_PEE5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(CLK_REQ, SYS, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
-};
-
-#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
- { \
- .drvgrp = PMUX_DRVGRP_##_drvgrp, \
- .slwf = _slwf, \
- .slwr = _slwr, \
- .drvup = _drvup, \
- .drvdn = _drvdn, \
- .lpmd = PMUX_LPMD_##_lpmd, \
- .schmt = PMUX_SCHMT_##_schmt, \
- .hsm = PMUX_HSM_##_hsm, \
- }
-
-static const struct pmux_drvgrp_config p2571_drvgrps[] = {
-};
-
-#endif /* PINMUX_CONFIG_P2571_H */
diff --git a/board/nvidia/p3450-0000/Kconfig b/board/nvidia/p3450-0000/Kconfig
new file mode 100644
index 0000000..7a08cd8
--- /dev/null
+++ b/board/nvidia/p3450-0000/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_P3450_0000
+
+config SYS_BOARD
+ default "p3450-0000"
+
+config SYS_VENDOR
+ default "nvidia"
+
+config SYS_CONFIG_NAME
+ default "p3450-0000"
+
+endif
diff --git a/board/nvidia/p3450-0000/MAINTAINERS b/board/nvidia/p3450-0000/MAINTAINERS
new file mode 100644
index 0000000..4070006
--- /dev/null
+++ b/board/nvidia/p3450-0000/MAINTAINERS
@@ -0,0 +1,6 @@
+P3450-0000 BOARD
+M: Tom Warren <twarren@nvidia.com>
+S: Maintained
+F: board/nvidia/p3450-0000/
+F: include/configs/p3450-0000.h
+F: configs/p3450-0000_defconfig
diff --git a/board/nvidia/p3450-0000/Makefile b/board/nvidia/p3450-0000/Makefile
new file mode 100644
index 0000000..993c506
--- /dev/null
+++ b/board/nvidia/p3450-0000/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2018
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += p3450-0000.o
diff --git a/board/nvidia/p3450-0000/p3450-0000.c b/board/nvidia/p3450-0000/p3450-0000.c
new file mode 100644
index 0000000..f4212ab
--- /dev/null
+++ b/board/nvidia/p3450-0000/p3450-0000.c
@@ -0,0 +1,178 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018-2019
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <i2c.h>
+#include <linux/libfdt.h>
+#include <pca953x.h>
+#include <asm/arch-tegra/cboot.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux.h>
+#include "../p2571/max77620_init.h"
+
+void pin_mux_mmc(void)
+{
+ struct udevice *dev;
+ uchar val;
+ int ret;
+
+ /* Turn on MAX77620 LDO2 to 3.3V for SD card power */
+ debug("%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n", __func__);
+ ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev);
+ if (ret) {
+ printf("%s: Cannot find MAX77620 I2C chip\n", __func__);
+ return;
+ }
+ /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
+ val = 0xF2;
+ ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1);
+ if (ret)
+ printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret);
+
+ /* Disable LDO4 discharge */
+ ret = dm_i2c_read(dev, MAX77620_CNFG2_L4_REG, &val, 1);
+ if (ret) {
+ printf("i2c_read 0 0x3c 0x2c failed: %d\n", ret);
+ } else {
+ val &= ~BIT(1); /* ADE */
+ ret = dm_i2c_write(dev, MAX77620_CNFG2_L4_REG, &val, 1);
+ if (ret)
+ printf("i2c_write 0 0x3c 0x2c failed: %d\n", ret);
+ }
+
+ /* Set MBLPD */
+ ret = dm_i2c_read(dev, MAX77620_CNFGGLBL1_REG, &val, 1);
+ if (ret) {
+ printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret);
+ } else {
+ val |= BIT(6); /* MBLPD */
+ ret = dm_i2c_write(dev, MAX77620_CNFGGLBL1_REG, &val, 1);
+ if (ret)
+ printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret);
+ }
+}
+
+#ifdef CONFIG_PCI_TEGRA
+int tegra_pcie_board_init(void)
+{
+ struct udevice *dev;
+ uchar val;
+ int ret;
+
+ /* Turn on MAX77620 LDO1 to 1.05V for PEX power */
+ debug("%s: Set LDO1 for PEX power to 1.05V\n", __func__);
+ ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev);
+ if (ret) {
+ printf("%s: Cannot find MAX77620 I2C chip\n", __func__);
+ return -1;
+ }
+ /* 0xCA for 1.05v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
+ val = 0xCA;
+ ret = dm_i2c_write(dev, MAX77620_CNFG1_L1_REG, &val, 1);
+ if (ret)
+ printf("i2c_write 0 0x3c 0x25 failed: %d\n", ret);
+
+ return 0;
+}
+#endif /* PCI */
+
+static void ft_mac_address_setup(void *fdt)
+{
+ const void *cboot_fdt = (const void *)cboot_boot_x0;
+ uint8_t mac[ETH_ALEN], local_mac[ETH_ALEN];
+ const char *path;
+ int offset, err;
+
+ err = cboot_get_ethaddr(cboot_fdt, local_mac);
+ if (err < 0)
+ memset(local_mac, 0, ETH_ALEN);
+
+ path = fdt_get_alias(fdt, "ethernet");
+ if (!path)
+ return;
+
+ debug("ethernet alias found: %s\n", path);
+
+ offset = fdt_path_offset(fdt, path);
+ if (offset < 0) {
+ printf("ethernet alias points to absent node %s\n", path);
+ return;
+ }
+
+ if (is_valid_ethaddr(local_mac)) {
+ err = fdt_setprop(fdt, offset, "local-mac-address", local_mac,
+ ETH_ALEN);
+ if (!err)
+ debug("Local MAC address set: %pM\n", local_mac);
+ }
+
+ if (eth_env_get_enetaddr("ethaddr", mac)) {
+ if (memcmp(local_mac, mac, ETH_ALEN) != 0) {
+ err = fdt_setprop(fdt, offset, "mac-address", mac,
+ ETH_ALEN);
+ if (!err)
+ debug("MAC address set: %pM\n", mac);
+ }
+ }
+}
+
+static int ft_copy_carveout(void *dst, const void *src, const char *node)
+{
+ struct fdt_memory fb;
+ int err;
+
+ err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb);
+ if (err < 0) {
+ if (err != -FDT_ERR_NOTFOUND)
+ printf("failed to get carveout for %s: %d\n", node,
+ err);
+
+ return err;
+ }
+
+ err = fdtdec_set_carveout(dst, node, "memory-region", 0, "framebuffer",
+ &fb);
+ if (err < 0) {
+ printf("failed to set carveout for %s: %d\n", node, err);
+ return err;
+ }
+
+ return 0;
+}
+
+static void ft_carveout_setup(void *fdt)
+{
+ const void *cboot_fdt = (const void *)cboot_boot_x0;
+ static const char * const nodes[] = {
+ "/host1x@50000000/dc@54200000",
+ "/host1x@50000000/dc@54240000",
+ };
+ unsigned int i;
+ int err;
+
+ for (i = 0; i < ARRAY_SIZE(nodes); i++) {
+ printf("copying carveout for %s...\n", nodes[i]);
+
+ err = ft_copy_carveout(fdt, cboot_fdt, nodes[i]);
+ if (err < 0) {
+ if (err != -FDT_ERR_NOTFOUND)
+ printf("failed to copy carveout for %s: %d\n",
+ nodes[i], err);
+
+ continue;
+ }
+ }
+}
+
+int ft_board_setup(void *fdt, bd_t *bd)
+{
+ ft_mac_address_setup(fdt);
+ ft_carveout_setup(fdt);
+
+ return 0;
+}
diff --git a/common/Kconfig b/common/Kconfig
index 46e4193..bd35de3 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -568,6 +568,7 @@
default 0x2f000000 if ARCH_SUNXI && MACH_SUN9I
default 0x4f000000 if ARCH_SUNXI && !MACH_SUN9I
default 0x0f000000 if ROCKCHIP_RK3288
+ default 0x0f200000 if ROCKCHIP_RK3399
help
This sets the start address of the pre-console buffer. This must
be in available memory and is accessed before relocation and
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index aef1dbd..69dabd2 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -646,10 +646,6 @@
if (!spl_fit_image_get_os(fit, node, &os_type))
debug("Loadable is %s\n", genimg_get_os_name(os_type));
-#if CONFIG_IS_ENABLED(FIT_IMAGE_TINY)
- else
- os_type = IH_OS_U_BOOT;
-#endif
if (os_type == IH_OS_U_BOOT) {
spl_fit_append_fdt(&image_info, info, sector,
diff --git a/configs/e2220-1170_defconfig b/configs/e2220-1170_defconfig
index 1639040..951ed1d 100644
--- a/configs/e2220-1170_defconfig
+++ b/configs/e2220-1170_defconfig
@@ -43,3 +43,4 @@
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
+CONFIG_BOOTP_PREFER_SERVERIP=y
diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig
index 9ea9b11..607a00d 100644
--- a/configs/nanopc-t4-rk3399_defconfig
+++ b/configs/nanopc-t4-rk3399_defconfig
@@ -52,5 +52,12 @@
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_USB_KEYBOARD=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_BPP16=y
+CONFIG_VIDEO_BPP32=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_DISPLAY_ROCKCHIP_HDMI=y
diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig
index ad0e808..3fcb7ac 100644
--- a/configs/nanopi-m4-rk3399_defconfig
+++ b/configs/nanopi-m4-rk3399_defconfig
@@ -52,5 +52,12 @@
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_USB_KEYBOARD=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_BPP16=y
+CONFIG_VIDEO_BPP32=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_DISPLAY_ROCKCHIP_HDMI=y
diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig
index d038a8c..b9ea535 100644
--- a/configs/nanopi-neo4-rk3399_defconfig
+++ b/configs/nanopi-neo4-rk3399_defconfig
@@ -52,5 +52,12 @@
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_USB_KEYBOARD=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_BPP16=y
+CONFIG_VIDEO_BPP32=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_DISPLAY_ROCKCHIP_HDMI=y
diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig
index 2070199..7081719 100644
--- a/configs/p2371-0000_defconfig
+++ b/configs/p2371-0000_defconfig
@@ -44,3 +44,4 @@
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
+CONFIG_BOOTP_PREFER_SERVERIP=y
diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig
index 8c808ae..c70217c 100644
--- a/configs/p2371-2180_defconfig
+++ b/configs/p2371-2180_defconfig
@@ -52,3 +52,4 @@
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
+CONFIG_BOOTP_PREFER_SERVERIP=y
diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig
index 721c5c5..43c24b8 100644
--- a/configs/p2571_defconfig
+++ b/configs/p2571_defconfig
@@ -44,3 +44,4 @@
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
+CONFIG_BOOTP_PREFER_SERVERIP=y
diff --git a/configs/p2771-0000-000_defconfig b/configs/p2771-0000-000_defconfig
index 06f12e2..8bf8419 100644
--- a/configs/p2771-0000-000_defconfig
+++ b/configs/p2771-0000-000_defconfig
@@ -36,3 +36,5 @@
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_BOOTP_PREFER_SERVERIP=y
diff --git a/configs/p2771-0000-500_defconfig b/configs/p2771-0000-500_defconfig
index 1a14a92..1f40333 100644
--- a/configs/p2771-0000-500_defconfig
+++ b/configs/p2771-0000-500_defconfig
@@ -36,3 +36,5 @@
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_BOOTP_PREFER_SERVERIP=y
diff --git a/configs/p3450-0000_defconfig b/configs/p3450-0000_defconfig
new file mode 100644
index 0000000..f78e1d3
--- /dev/null
+++ b/configs/p3450-0000_defconfig
@@ -0,0 +1,64 @@
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_SYS_TEXT_BASE=0x80080000
+CONFIG_TEGRA210=y
+CONFIG_TARGET_P3450_0000=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_STDIO_DEREGISTER=y
+CONFIG_SYS_PROMPT="Tegra210 (P3450-0000) # "
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_LIVE=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra210-p3450-0000"
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_SYS_I2C_TEGRA=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_USE_4K_SECTORS=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=24000000
+CONFIG_RTL8169=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCI_TEGRA=y
+CONFIG_SYS_NS16550=y
+CONFIG_TEGRA114_SPI=y
+CONFIG_TEGRA210_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="NVIDIA"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0955
+CONFIG_USB_GADGET_PRODUCT_NUM=0x701a
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+# CONFIG_ENV_IS_IN_MMC is not set
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_ENV_OFFSET=0xFFFFE000
+CONFIG_BOOTP_PREFER_SERVERIP=y
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_DISABLE_SDMMC1_EARLY=y
diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig
index d540a17..be76524 100644
--- a/configs/roc-pc-rk3399_defconfig
+++ b/configs/roc-pc-rk3399_defconfig
@@ -59,3 +59,9 @@
CONFIG_USB_KEYBOARD=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_BPP16=y
+CONFIG_VIDEO_BPP32=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_DISPLAY_ROCKCHIP_HDMI=y
diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig
index ba4226e..c4e9547 100644
--- a/configs/rock960-rk3399_defconfig
+++ b/configs/rock960-rk3399_defconfig
@@ -58,5 +58,12 @@
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_USB_KEYBOARD=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_BPP16=y
+CONFIG_VIDEO_BPP32=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_DISPLAY_ROCKCHIP_HDMI=y
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 865b80c..1f62376 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -994,6 +994,13 @@
case DCLK_VOP1:
ret = rk3399_vop_set_clk(priv->cru, clk->id, rate);
break;
+ case ACLK_VOP1:
+ case HCLK_VOP1:
+ /**
+ * assigned-clocks handling won't require for vopl, so
+ * return 0 to satisfy clk_set_defaults during device probe.
+ */
+ return 0;
case SCLK_DDRCLK:
ret = rk3399_ddr_set_clk(priv->cru, rate);
break;
diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c
index f022e93..2b04156 100644
--- a/drivers/mmc/tegra_mmc.c
+++ b/drivers/mmc/tegra_mmc.c
@@ -3,7 +3,7 @@
* (C) Copyright 2009 SAMSUNG Electronics
* Minkyu Kang <mk7.kang@samsung.com>
* Jaehoon Chung <jh80.chung@samsung.com>
- * Portions Copyright 2011-2016 NVIDIA Corporation
+ * Portions Copyright 2011-2019 NVIDIA Corporation
*/
#include <bouncebuf.h>
@@ -15,6 +15,9 @@
#include <asm/io.h>
#include <asm/arch-tegra/tegra_mmc.h>
#include <linux/err.h>
+#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA210)
+#include <asm/arch/clock.h>
+#endif
struct tegra_mmc_plat {
struct mmc_config cfg;
@@ -30,6 +33,7 @@
struct gpio_desc wp_gpio; /* Write Protect GPIO */
unsigned int version; /* SDHCI spec. version */
unsigned int clock; /* Current clock (MHz) */
+ int mmc_id; /* peripheral id */
};
static void tegra_mmc_set_power(struct tegra_mmc_priv *priv,
@@ -372,6 +376,25 @@
rate = clk_set_rate(&priv->clk, clock);
div = (rate + clock - 1) / clock;
+
+#if defined(CONFIG_TEGRA210)
+ if (priv->mmc_id == PERIPH_ID_SDMMC1 && clock <= 400000) {
+ /* clock_adjust_periph_pll_div() chooses a 'bad' clock
+ * on SDMMC1 T210, so skip it here and force a clock
+ * that's been spec'd in the table in the TRM for
+ * card-detect (400KHz).
+ */
+ uint effective_rate = clock_adjust_periph_pll_div(priv->mmc_id,
+ CLOCK_ID_PERIPH, 24727273, NULL);
+ div = 62;
+
+ debug("%s: WAR: Using SDMMC1 clock of %u, div %d to achieve %dHz card clock ...\n",
+ __func__, effective_rate, div, clock);
+ } else {
+ clock_adjust_periph_pll_div(priv->mmc_id, CLOCK_ID_PERIPH,
+ clock, &div);
+ }
+#endif
debug("div = %d\n", div);
writew(0, &priv->reg->clkcon);
@@ -446,16 +469,19 @@
static void tegra_mmc_pad_init(struct tegra_mmc_priv *priv)
{
-#if defined(CONFIG_TEGRA30)
+#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA210)
u32 val;
+ u16 clk_con;
+ int timeout;
+ int id = priv->mmc_id;
- debug("%s: sdmmc address = %08x\n", __func__, (unsigned int)priv->reg);
+ debug("%s: sdmmc address = %p, id = %d\n", __func__,
+ priv->reg, id);
/* Set the pad drive strength for SDMMC1 or 3 only */
- if (priv->reg != (void *)0x78000000 &&
- priv->reg != (void *)0x78000400) {
+ if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) {
debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
- __func__);
+ __func__);
return;
}
@@ -464,11 +490,65 @@
val |= MEMCOMP_PADCTRL_VREF;
writel(val, &priv->reg->sdmemcmppadctl);
+ /* Disable SD Clock Enable before running auto-cal as per TRM */
+ clk_con = readw(&priv->reg->clkcon);
+ debug("%s: CLOCK_CONTROL = 0x%04X\n", __func__, clk_con);
+ clk_con &= ~TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
+ writew(clk_con, &priv->reg->clkcon);
+
val = readl(&priv->reg->autocalcfg);
val &= 0xFFFF0000;
- val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED;
+ val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET;
writel(val, &priv->reg->autocalcfg);
-#endif
+ val |= AUTO_CAL_START | AUTO_CAL_ENABLE;
+ writel(val, &priv->reg->autocalcfg);
+ debug("%s: AUTO_CAL_CFG = 0x%08X\n", __func__, val);
+ udelay(1);
+ timeout = 100; /* 10 mSec max (100*100uS) */
+ do {
+ val = readl(&priv->reg->autocalsts);
+ udelay(100);
+ } while ((val & AUTO_CAL_ACTIVE) && --timeout);
+ val = readl(&priv->reg->autocalsts);
+ debug("%s: Final AUTO_CAL_STATUS = 0x%08X, timeout = %d\n",
+ __func__, val, timeout);
+
+ /* Re-enable SD Clock Enable when auto-cal is done */
+ clk_con |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
+ writew(clk_con, &priv->reg->clkcon);
+ clk_con = readw(&priv->reg->clkcon);
+ debug("%s: final CLOCK_CONTROL = 0x%04X\n", __func__, clk_con);
+
+ if (timeout == 0) {
+ printf("%s: Warning: Autocal timed out!\n", __func__);
+ /* TBD: Set CFG2TMC_SDMMC1_PAD_CAL_DRV* regs here */
+ }
+
+#if defined(CONFIG_TEGRA210)
+ u32 tap_value, trim_value;
+
+ /* Set tap/trim values for SDMMC1/3 @ <48MHz here */
+ val = readl(&priv->reg->venspictl); /* aka VENDOR_SYS_SW_CNTL */
+ val &= IO_TRIM_BYPASS_MASK;
+ if (id == PERIPH_ID_SDMMC1) {
+ tap_value = 4; /* default */
+ if (val)
+ tap_value = 3;
+ trim_value = 2;
+ } else { /* SDMMC3 */
+ tap_value = 3;
+ trim_value = 3;
+ }
+
+ val = readl(&priv->reg->venclkctl);
+ val &= ~TRIM_VAL_MASK;
+ val |= (trim_value << TRIM_VAL_SHIFT);
+ val &= ~TAP_VAL_MASK;
+ val |= (tap_value << TAP_VAL_SHIFT);
+ writel(val, &priv->reg->venclkctl);
+ debug("%s: VENDOR_CLOCK_CNTRL = 0x%08X\n", __func__, val);
+#endif /* T210 */
+#endif /* T30/T210 */
}
static void tegra_mmc_reset(struct tegra_mmc_priv *priv, struct mmc *mmc)
@@ -514,6 +594,13 @@
unsigned int mask;
debug(" tegra_mmc_init called\n");
+#if defined(CONFIG_TEGRA210)
+ priv->mmc_id = clock_decode_periph_id(dev);
+ if (priv->mmc_id == PERIPH_ID_NONE) {
+ printf("%s: Missing/invalid peripheral ID\n", __func__);
+ return -EINVAL;
+ }
+#endif
tegra_mmc_reset(priv, mmc);
#if defined(CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 973b6f8..abdf560 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -147,6 +147,7 @@
{ INFO("mx25l6405d", 0xc22017, 0, 64 * 1024, 128, SECT_4K) },
{ INFO("mx25u2033e", 0xc22532, 0, 64 * 1024, 4, SECT_4K) },
{ INFO("mx25u1635e", 0xc22535, 0, 64 * 1024, 32, SECT_4K) },
+ { INFO("mx25u3235f", 0xc22536, 0, 4 * 1024, 1024, SECT_4K) },
{ INFO("mx25u6435f", 0xc22537, 0, 64 * 1024, 128, SECT_4K) },
{ INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, 0) },
{ INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) },
diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c
index a09bf88..a6c3939 100644
--- a/drivers/spi/atmel-quadspi.c
+++ b/drivers/spi/atmel-quadspi.c
@@ -146,7 +146,9 @@
struct atmel_qspi {
void __iomem *regs;
void __iomem *mem;
+ resource_size_t mmap_size;
const struct atmel_qspi_caps *caps;
+ struct udevice *dev;
ulong bus_clk_rate;
u32 mr;
};
@@ -168,6 +170,81 @@
{ 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD },
};
+#ifdef VERBOSE_DEBUG
+static const char *atmel_qspi_reg_name(u32 offset, char *tmp, size_t sz)
+{
+ switch (offset) {
+ case QSPI_CR:
+ return "CR";
+ case QSPI_MR:
+ return "MR";
+ case QSPI_RD:
+ return "MR";
+ case QSPI_TD:
+ return "TD";
+ case QSPI_SR:
+ return "SR";
+ case QSPI_IER:
+ return "IER";
+ case QSPI_IDR:
+ return "IDR";
+ case QSPI_IMR:
+ return "IMR";
+ case QSPI_SCR:
+ return "SCR";
+ case QSPI_IAR:
+ return "IAR";
+ case QSPI_ICR:
+ return "ICR/WICR";
+ case QSPI_IFR:
+ return "IFR";
+ case QSPI_RICR:
+ return "RICR";
+ case QSPI_SMR:
+ return "SMR";
+ case QSPI_SKR:
+ return "SKR";
+ case QSPI_WPMR:
+ return "WPMR";
+ case QSPI_WPSR:
+ return "WPSR";
+ case QSPI_VERSION:
+ return "VERSION";
+ default:
+ snprintf(tmp, sz, "0x%02x", offset);
+ break;
+ }
+
+ return tmp;
+}
+#endif /* VERBOSE_DEBUG */
+
+static u32 atmel_qspi_read(struct atmel_qspi *aq, u32 offset)
+{
+ u32 value = readl(aq->regs + offset);
+
+#ifdef VERBOSE_DEBUG
+ char tmp[16];
+
+ dev_vdbg(aq->dev, "read 0x%08x from %s\n", value,
+ atmel_qspi_reg_name(offset, tmp, sizeof(tmp)));
+#endif /* VERBOSE_DEBUG */
+
+ return value;
+}
+
+static void atmel_qspi_write(u32 value, struct atmel_qspi *aq, u32 offset)
+{
+#ifdef VERBOSE_DEBUG
+ char tmp[16];
+
+ dev_vdbg(aq->dev, "write 0x%08x into %s\n", value,
+ atmel_qspi_reg_name(offset, tmp, sizeof(tmp)));
+#endif /* VERBOSE_DEBUG */
+
+ writel(value, aq->regs + offset);
+}
+
static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op,
const struct atmel_qspi_mode *mode)
{
@@ -288,32 +365,32 @@
* Serial Memory Mode (SMM).
*/
if (aq->mr != QSPI_MR_SMM) {
- writel(QSPI_MR_SMM, aq->regs + QSPI_MR);
+ atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
aq->mr = QSPI_MR_SMM;
}
/* Clear pending interrupts */
- (void)readl(aq->regs + QSPI_SR);
+ (void)atmel_qspi_read(aq, QSPI_SR);
if (aq->caps->has_ricr) {
if (!op->addr.nbytes && op->data.dir == SPI_MEM_DATA_IN)
ifr |= QSPI_IFR_APBTFRTYP_READ;
/* Set QSPI Instruction Frame registers */
- writel(iar, aq->regs + QSPI_IAR);
+ atmel_qspi_write(iar, aq, QSPI_IAR);
if (op->data.dir == SPI_MEM_DATA_IN)
- writel(icr, aq->regs + QSPI_RICR);
+ atmel_qspi_write(icr, aq, QSPI_RICR);
else
- writel(icr, aq->regs + QSPI_WICR);
- writel(ifr, aq->regs + QSPI_IFR);
+ atmel_qspi_write(icr, aq, QSPI_WICR);
+ atmel_qspi_write(ifr, aq, QSPI_IFR);
} else {
if (op->data.dir == SPI_MEM_DATA_OUT)
ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR;
/* Set QSPI Instruction Frame registers */
- writel(iar, aq->regs + QSPI_IAR);
- writel(icr, aq->regs + QSPI_ICR);
- writel(ifr, aq->regs + QSPI_IFR);
+ atmel_qspi_write(iar, aq, QSPI_IAR);
+ atmel_qspi_write(icr, aq, QSPI_ICR);
+ atmel_qspi_write(ifr, aq, QSPI_IFR);
}
return 0;
@@ -326,6 +403,14 @@
u32 sr, imr, offset;
int err;
+ /*
+ * Check if the address exceeds the MMIO window size. An improvement
+ * would be to add support for regular SPI mode and fall back to it
+ * when the flash memories overrun the controller's memory space.
+ */
+ if (op->addr.val + op->data.nbytes > aq->mmap_size)
+ return -ENOTSUPP;
+
err = atmel_qspi_set_cfg(aq, op, &offset);
if (err)
return err;
@@ -333,7 +418,7 @@
/* Skip to the final steps if there is no data */
if (op->data.nbytes) {
/* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
- (void)readl(aq->regs + QSPI_IFR);
+ (void)atmel_qspi_read(aq, QSPI_IFR);
/* Send/Receive data */
if (op->data.dir == SPI_MEM_DATA_IN)
@@ -344,7 +429,7 @@
op->data.nbytes);
/* Release the chip-select */
- writel(QSPI_CR_LASTXFER, aq->regs + QSPI_CR);
+ atmel_qspi_write(QSPI_CR_LASTXFER, aq, QSPI_CR);
}
/* Poll INSTruction End and Chip Select Rise flags. */
@@ -366,12 +451,12 @@
new_value = QSPI_SCR_SCBR(scbr);
mask = QSPI_SCR_SCBR_MASK;
- scr = readl(aq->regs + QSPI_SCR);
+ scr = atmel_qspi_read(aq, QSPI_SCR);
if ((scr & mask) == new_value)
return 0;
scr = (scr & ~mask) | new_value;
- writel(scr, aq->regs + QSPI_SCR);
+ atmel_qspi_write(scr, aq, QSPI_SCR);
return 0;
}
@@ -388,12 +473,12 @@
mask = QSPI_SCR_CPOL | QSPI_SCR_CPHA;
- scr = readl(aq->regs + QSPI_SCR);
+ scr = atmel_qspi_read(aq, QSPI_SCR);
if ((scr & mask) == new_value)
return 0;
scr = (scr & ~mask) | new_value;
- writel(scr, aq->regs + QSPI_SCR);
+ atmel_qspi_write(scr, aq, QSPI_SCR);
return 0;
}
@@ -446,14 +531,14 @@
static void atmel_qspi_init(struct atmel_qspi *aq)
{
/* Reset the QSPI controller */
- writel(QSPI_CR_SWRST, aq->regs + QSPI_CR);
+ atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR);
/* Set the QSPI controller by default in Serial Memory Mode */
- writel(QSPI_MR_SMM, aq->regs + QSPI_MR);
+ atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
aq->mr = QSPI_MR_SMM;
/* Enable the QSPI controller */
- writel(QSPI_CR_QSPIEN, aq->regs + QSPI_CR);
+ atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR);
}
static int atmel_qspi_probe(struct udevice *dev)
@@ -490,10 +575,14 @@
if (IS_ERR(aq->mem))
return PTR_ERR(aq->mem);
+ aq->mmap_size = resource_size(&res);
+
ret = atmel_qspi_enable_clk(dev);
if (ret)
return ret;
+ aq->dev = dev;
+
atmel_qspi_init(aq);
return 0;
diff --git a/drivers/spi/tegra210_qspi.c b/drivers/spi/tegra210_qspi.c
index d82ecaa..6e540e9 100644
--- a/drivers/spi/tegra210_qspi.c
+++ b/drivers/spi/tegra210_qspi.c
@@ -2,7 +2,8 @@
/*
* NVIDIA Tegra210 QSPI controller driver
*
- * (C) Copyright 2015 NVIDIA Corporation <www.nvidia.com>
+ * (C) Copyright 2015-2020 NVIDIA Corporation <www.nvidia.com>
+ *
*/
#include <common.h>
@@ -41,10 +42,10 @@
#define QSPI_CMD1_BITLEN_SHIFT 0
/* COMMAND2 */
-#define QSPI_CMD2_TX_CLK_TAP_DELAY BIT(6)
-#define QSPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(11,6)
-#define QSPI_CMD2_RX_CLK_TAP_DELAY BIT(0)
-#define QSPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(5,0)
+#define QSPI_CMD2_TX_CLK_TAP_DELAY_SHIFT 10
+#define QSPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(14,10)
+#define QSPI_CMD2_RX_CLK_TAP_DELAY_SHIFT 0
+#define QSPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(7,0)
/* TRANSFER STATUS */
#define QSPI_XFER_STS_RDY BIT(30)
@@ -96,10 +97,8 @@
static int tegra210_qspi_ofdata_to_platdata(struct udevice *bus)
{
struct tegra_spi_platdata *plat = bus->platdata;
- const void *blob = gd->fdt_blob;
- int node = dev_of_offset(bus);
- plat->base = devfdt_get_addr(bus);
+ plat->base = dev_read_addr(bus);
plat->periph_id = clock_decode_periph_id(bus);
if (plat->periph_id == PERIPH_ID_NONE) {
@@ -109,10 +108,11 @@
}
/* Use 500KHz as a suitable default */
- plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
- 500000);
- plat->deactivate_delay_us = fdtdec_get_int(blob, node,
- "spi-deactivate-delay", 0);
+ plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
+ 500000);
+ plat->deactivate_delay_us = dev_read_u32_default(bus,
+ "spi-deactivate-delay",
+ 0);
debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
__func__, plat->base, plat->periph_id, plat->frequency,
plat->deactivate_delay_us);
@@ -126,25 +126,32 @@
struct tegra210_qspi_priv *priv = dev_get_priv(bus);
priv->regs = (struct qspi_regs *)plat->base;
+ struct qspi_regs *regs = priv->regs;
priv->last_transaction_us = timer_get_us();
priv->freq = plat->frequency;
priv->periph_id = plat->periph_id;
+ debug("%s: Freq = %u, id = %d\n", __func__, priv->freq,
+ priv->periph_id);
/* Change SPI clock to correct frequency, PLLP_OUT0 source */
clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq);
+ /* Set tap delays here, clock change above resets QSPI controller */
+ u32 reg = (0x09 << QSPI_CMD2_TX_CLK_TAP_DELAY_SHIFT) |
+ (0x0C << QSPI_CMD2_RX_CLK_TAP_DELAY_SHIFT);
+ writel(reg, ®s->command2);
+ debug("%s: COMMAND2 = %08x\n", __func__, readl(®s->command2));
+
return 0;
}
-static int tegra210_qspi_claim_bus(struct udevice *bus)
+static int tegra210_qspi_claim_bus(struct udevice *dev)
{
+ struct udevice *bus = dev->parent;
struct tegra210_qspi_priv *priv = dev_get_priv(bus);
struct qspi_regs *regs = priv->regs;
- /* Change SPI clock to correct frequency, PLLP_OUT0 source */
- clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq);
-
debug("%s: FIFO STATUS = %08x\n", __func__, readl(®s->fifo_status));
/* Set master mode and sw controlled CS */
diff --git a/drivers/video/rockchip/Kconfig b/drivers/video/rockchip/Kconfig
index 10182d0..cfd774e 100644
--- a/drivers/video/rockchip/Kconfig
+++ b/drivers/video/rockchip/Kconfig
@@ -22,6 +22,7 @@
config VIDEO_ROCKCHIP_MAX_XRES
int "Maximum horizontal resolution (for memory allocation purposes)"
depends on VIDEO_ROCKCHIP
+ default 3480 if ROCKCHIP_RK3399 && DISPLAY_ROCKCHIP_HDMI
default 1920
help
The maximum horizontal resolution to support for the framebuffer.
@@ -31,6 +32,7 @@
config VIDEO_ROCKCHIP_MAX_YRES
int "Maximum vertical resolution (for memory allocation purposes)"
depends on VIDEO_ROCKCHIP
+ default 2160 if ROCKCHIP_RK3399 && DISPLAY_ROCKCHIP_HDMI
default 1080
help
The maximum vertical resolution to support for the framebuffer.
diff --git a/drivers/video/rockchip/rk3399_vop.c b/drivers/video/rockchip/rk3399_vop.c
index 81c122d..1d5b393 100644
--- a/drivers/video/rockchip/rk3399_vop.c
+++ b/drivers/video/rockchip/rk3399_vop.c
@@ -45,8 +45,6 @@
V_RK3399_DSP_MIPI_POL(polarity));
break;
- case VOP_MODE_LVDS:
- /* The RK3399 has neither parallel RGB nor LVDS output. */
default:
debug("%s: unsupported output mode %x\n", __func__, mode);
}
diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index e91d4df..e1bd656 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -118,10 +118,12 @@
V_EDP_OUT_EN(1));
break;
+#if defined(CONFIG_ROCKCHIP_RK3288)
case VOP_MODE_LVDS:
clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN,
V_RGB_OUT_EN(1));
break;
+#endif
case VOP_MODE_MIPI:
clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN,
@@ -313,7 +315,9 @@
/* Set bitwidth for vop display according to vop mode */
switch (vop_id) {
case VOP_MODE_EDP:
+#if defined(CONFIG_ROCKCHIP_RK3288)
case VOP_MODE_LVDS:
+#endif
l2bpp = VIDEO_BPP16;
break;
case VOP_MODE_HDMI:
diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h
index 4127f2d..8ca571b 100644
--- a/include/configs/apalis-tk1.h
+++ b/include/configs/apalis-tk1.h
@@ -46,6 +46,14 @@
"zImage fat 0 1 mmcpart 0; " \
"tegra124-apalis-eval.dtb fat 0 1 mmcpart 0"
+#define UBOOT_UPDATE \
+ "uboot_hwpart=1\0" \
+ "uboot_blk=0\0" \
+ "set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff && " \
+ "setexpr blkcnt ${blkcnt} / 0x200\0" \
+ "update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && " \
+ "mmc write ${loadaddr} ${uboot_blk} ${blkcnt}\0" \
+
#define EMMC_BOOTCMD \
"set_emmcargs=setenv emmcargs ip=off root=PARTUUID=${uuid} " \
"ro rootfstype=ext4 rootwait\0" \
@@ -104,6 +112,7 @@
"fdt_module=" FDT_MODULE "\0" \
NFS_BOOTCMD \
SD_BOOTCMD \
+ UBOOT_UPDATE \
"setethupdate=if env exists ethaddr; then; else setenv ethaddr " \
"00:14:2d:00:00:00; fi; pci enum && tftpboot ${loadaddr} " \
"flash_eth.img && source ${loadaddr}\0" \
diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h
index 821162a..701b34a 100644
--- a/include/configs/apalis_t30.h
+++ b/include/configs/apalis_t30.h
@@ -40,6 +40,17 @@
#undef CONFIG_SYS_MAXARGS
#define CONFIG_SYS_MAXARGS 32
+#define UBOOT_UPDATE \
+ "uboot_hwpart=1\0" \
+ "uboot_blk=0\0" \
+ "set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff && " \
+ "setexpr blkcnt ${blkcnt} / 0x200\0" \
+ "update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && " \
+ "mmc write ${loadaddr} ${uboot_blk} ${blkcnt}\0" \
+
+#define BOARD_EXTRA_ENV_SETTINGS \
+ UBOOT_UPDATE
+
#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h
index 122294d..94e17bb 100644
--- a/include/configs/colibri_t20.h
+++ b/include/configs/colibri_t20.h
@@ -27,10 +27,14 @@
#define CONFIG_TEGRA_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-/* Environment in NAND, 64K is a bit excessive but erase block is 512K anyway */
+#define UBOOT_UPDATE \
+ "update_uboot=nand erase.part u-boot && " \
+ "nand write ${loadaddr} u-boot ${filesize}\0" \
+/* Environment in NAND, 64K is a bit excessive but erase block is 512K anyway */
#define BOARD_EXTRA_ENV_SETTINGS \
- "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"
+ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+ UBOOT_UPDATE
/* Increase console I/O buffer size */
#undef CONFIG_SYS_CBSIZE
diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h
index 5aecf14..4e5e89b 100644
--- a/include/configs/colibri_t30.h
+++ b/include/configs/colibri_t30.h
@@ -39,6 +39,17 @@
#undef CONFIG_SYS_MAXARGS
#define CONFIG_SYS_MAXARGS 32
+#define UBOOT_UPDATE \
+ "uboot_hwpart=1\0" \
+ "uboot_blk=0\0" \
+ "set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff && " \
+ "setexpr blkcnt ${blkcnt} / 0x200\0" \
+ "update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && " \
+ "mmc write ${loadaddr} ${uboot_blk} ${blkcnt}\0" \
+
+#define BOARD_EXTRA_ENV_SETTINGS \
+ UBOOT_UPDATE
+
#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
diff --git a/include/configs/evb_rk3399.h b/include/configs/evb_rk3399.h
index c0b0358..2d3db22 100644
--- a/include/configs/evb_rk3399.h
+++ b/include/configs/evb_rk3399.h
@@ -6,6 +6,11 @@
#ifndef __EVB_RK3399_H
#define __EVB_RK3399_H
+#define ROCKCHIP_DEVICE_SETTINGS \
+ "stdin=serial,usbkbd\0" \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
+
#include <configs/rk3399_common.h>
#if defined(CONFIG_ENV_IS_IN_MMC)
diff --git a/include/configs/p3450-0000.h b/include/configs/p3450-0000.h
new file mode 100644
index 0000000..7f05beb
--- /dev/null
+++ b/include/configs/p3450-0000.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2018-2019 NVIDIA Corporation.
+ */
+
+#ifndef _P3450_0000_H
+#define _P3450_0000_H
+
+#include <linux/sizes.h>
+
+#include "tegra210-common.h"
+
+/* High-level configuration options */
+#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P3450-0000"
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTA
+
+/* Only MMC/PXE/DHCP for now, add USB back in later when supported */
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 0) \
+ func(PXE, pxe, na) \
+ func(DHCP, dhcp, na)
+
+/* Environment at end of QSPI, in the VER partition */
+#define CONFIG_ENV_SPI_MAX_HZ 48000000
+#define CONFIG_ENV_SPI_MODE SPI_MODE_0
+#define CONFIG_SPI_FLASH_SIZE (4 << 20)
+
+#define CONFIG_PREBOOT
+
+#define BOARD_EXTRA_ENV_SETTINGS \
+ "preboot=if test -e mmc 1:1 /u-boot-preboot.scr; then " \
+ "load mmc 1:1 ${scriptaddr} /u-boot-preboot.scr; " \
+ "source ${scriptaddr}; " \
+ "fi\0"
+
+/* General networking support */
+#include "tegra-common-usb-gadget.h"
+#include "tegra-common-post.h"
+
+/* Crystal is 38.4MHz. clk_m runs at half that rate */
+#define COUNTER_FREQUENCY 19200000
+
+#endif /* _P3450_0000_H */
diff --git a/include/configs/rock960_rk3399.h b/include/configs/rock960_rk3399.h
index 746d24c..304ad2b 100644
--- a/include/configs/rock960_rk3399.h
+++ b/include/configs/rock960_rk3399.h
@@ -6,6 +6,11 @@
#ifndef __ROCK960_RK3399_H
#define __ROCK960_RK3399_H
+#define ROCKCHIP_DEVICE_SETTINGS \
+ "stdin=serial,usbkbd\0" \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
+
#include <configs/rk3399_common.h>
#define CONFIG_SYS_MMC_ENV_DEV 1
diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h
index 1c53311..1b8e94b 100644
--- a/include/configs/tegra210-common.h
+++ b/include/configs/tegra210-common.h
@@ -46,8 +46,8 @@
"scriptaddr=0x90000000\0" \
"pxefile_addr_r=0x90100000\0" \
"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "fdt_addr_r=0x82000000\0" \
- "ramdisk_addr_r=0x82100000\0"
+ "fdt_addr_r=0x83000000\0" \
+ "ramdisk_addr_r=0x83200000\0"
/* For USB EHCI controller */
#define CONFIG_EHCI_IS_TDI