Merge https://source.denx.de/u-boot/custodians/u-boot-spi
- Fix mtd erase with mtdpart (Marek Behún)
- NXP fspi driver fixes (Kuldeep Singh)
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index 53f86f5..b3794a9 100644
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -2,7 +2,7 @@
windows_vm: vs2017-win2016
ubuntu_vm: ubuntu-18.04
macos_vm: macOS-10.15
- ci_runner_image: trini/u-boot-gitlab-ci-runner:focal-20210827-30Sep2021
+ ci_runner_image: trini/u-boot-gitlab-ci-runner:focal-20210921-05Oct2021
# Add '-u 0' options for Azure pipelines, otherwise we get "permission
# denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
# since our $(ci_runner_image) user is not root.
@@ -169,8 +169,7 @@
options: $(container_option)
steps:
- script: |
- ./tools/buildman/buildman --fetch-arch arm
- export PATH=~/.buildman-toolchains/gcc-9.2.0-nolibc/arm-linux-gnueabi/bin/:$PATH
+ export PATH=/opt/gcc-11.1.0-nolibc/arm-linux-gnueabi/bin:$PATH
test/nokia_rx51_test.sh
- job: test_py
@@ -183,7 +182,7 @@
TEST_PY_BD: "sandbox"
sandbox_clang:
TEST_PY_BD: "sandbox"
- OVERRIDE: "-O clang-12"
+ OVERRIDE: "-O clang-13"
sandbox_spl:
TEST_PY_BD: "sandbox_spl"
TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 5a3e2f0..e7c65eb 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -2,7 +2,7 @@
# Grab our configured image. The source for this is found at:
# https://source.denx.de/u-boot/gitlab-ci-runner
-image: trini/u-boot-gitlab-ci-runner:focal-20210827-30Sep2021
+image: trini/u-boot-gitlab-ci-runner:focal-20210921-05Oct2021
# We run some tests in different order, to catch some failures quicker.
stages:
@@ -177,8 +177,7 @@
Run tests for Nokia RX-51 (aka N900):
stage: testsuites
script:
- - ./tools/buildman/buildman --fetch-arch arm;
- export PATH=~/.buildman-toolchains/gcc-9.2.0-nolibc/arm-linux-gnueabi/bin/:$PATH;
+ - export PATH=/opt/gcc-11.1.0-nolibc/arm-linux-gnueabi/bin:$PATH;
test/nokia_rx51_test.sh
# Test sandbox with test.py
@@ -190,7 +189,7 @@
sandbox with clang test.py:
variables:
TEST_PY_BD: "sandbox"
- OVERRIDE: "-O clang-12"
+ OVERRIDE: "-O clang-13"
<<: *buildman_and_testpy_dfn
sandbox_spl test.py:
diff --git a/MAINTAINERS b/MAINTAINERS
index 71f468c..5069f18 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -693,6 +693,13 @@
F: include/dm/
F: test/dm/
+EFI APP
+M: Simon Glass <sjg@chromium.org>
+M: Heinrich Schuchardt <xypron.glpk@gmx.de>
+S: Maintained
+W: https://u-boot.readthedocs.io/en/latest/develop/uefi/u-boot_on_efi.html
+F: lib/efi/efi_app.c
+
EFI PAYLOAD
M: Heinrich Schuchardt <xypron.glpk@gmx.de>
R: Alexander Graf <agraf@csgraf.de>
@@ -756,6 +763,7 @@
F: include/linux/libfdt*
F: cmd/fdt.c
F: common/fdt_support.c
+F: scripts/dtc-version.sh
FREEBSD
M: Rafal Jaworowski <raj@semihalf.com>
diff --git a/Makefile b/Makefile
index f911f70..5194e4d 100644
--- a/Makefile
+++ b/Makefile
@@ -299,9 +299,7 @@
# have older compilers as their default, so we make it explicit for
# these that our host tools are GNU11 (i.e. C11 w/ GNU extensions).
CSTD_FLAG := -std=gnu11
-ifeq ($(HOSTOS),linux)
KBUILD_HOSTCFLAGS += $(CSTD_FLAG)
-endif
ifeq ($(HOSTOS),cygwin)
KBUILD_HOSTCFLAGS += -ansi
@@ -415,7 +413,13 @@
PYTHON ?= python
PYTHON2 = python2
PYTHON3 ?= python3
-DTC ?= $(objtree)/scripts/dtc/dtc
+
+# The devicetree compiler and pylibfdt are automatically built unless DTC is
+# provided. If DTC is provided, it is assumed the pylibfdt is available too.
+DTC_INTREE := $(objtree)/scripts/dtc/dtc
+DTC ?= $(DTC_INTREE)
+DTC_MIN_VERSION := 010406
+
CHECK = sparse
CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \
@@ -1335,9 +1339,6 @@
else
ifneq ($(CONFIG_USE_SPL_FIT_GENERATOR),)
U_BOOT_ITS := u-boot.its
-ifeq ($(CONFIG_SPL_FIT_GENERATOR),"arch/arm/mach-imx/mkimage_fit_atf.sh")
-U_BOOT_ITS_DEPS += u-boot-nodtb.bin
-endif
ifeq ($(CONFIG_SPL_FIT_GENERATOR),"arch/arm/mach-rockchip/make_fit_atf.py")
U_BOOT_ITS_DEPS += u-boot
endif
@@ -1954,9 +1955,29 @@
endif
+# Check dtc and pylibfdt, if DTC is provided, else build them
PHONY += scripts_dtc
scripts_dtc: scripts_basic
- $(Q)$(MAKE) $(build)=scripts/dtc
+ $(Q)if test "$(DTC)" = "$(DTC_INTREE)"; then \
+ $(MAKE) $(build)=scripts/dtc; \
+ else \
+ if ! $(DTC) -v >/dev/null; then \
+ echo '*** Failed to check dtc version: $(DTC)'; \
+ false; \
+ else \
+ if test "$(call dtc-version)" -lt $(DTC_MIN_VERSION); then \
+ echo '*** Your dtc is too old, please upgrade to dtc $(DTC_MIN_VERSION) or newer'; \
+ false; \
+ else \
+ if [ -n "$(CONFIG_PYLIBFDT)" ]; then \
+ if ! echo "import libfdt" | $(PYTHON3) 2>/dev/null; then \
+ echo '*** pylibfdt does not seem to be available with $(PYTHON3)'; \
+ false; \
+ fi; \
+ fi; \
+ fi; \
+ fi; \
+ fi
# ---------------------------------------------------------------------------
quiet_cmd_cpp_lds = LDS $@
diff --git a/arch/arc/lib/bootm.c b/arch/arc/lib/bootm.c
index 41408c2..ed6c5df 100644
--- a/arch/arc/lib/bootm.c
+++ b/arch/arc/lib/bootm.c
@@ -63,7 +63,7 @@
"(fake run for tracing)" : "");
bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
- if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
+ if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) {
r0 = 2;
r2 = (unsigned int)images->ft_addr;
} else {
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ebb1927..504abca 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -636,7 +636,6 @@
select DM
select GPIO_EXTRA_HEADER
select OF_CONTROL
- select OF_PRIOR_STAGE
imply CMD_DM
help
This enables support for Broadcom ARM-based set-top box
@@ -1028,6 +1027,7 @@
select DM
select DM_ETH
select DM_GPIO
+ select DM_I2C if I2C
select DM_KEYBOARD
select DM_MMC if MMC
select DM_SCSI if SCSI
diff --git a/arch/arm/cpu/armv7/stv0991/timer.c b/arch/arm/cpu/armv7/stv0991/timer.c
index 07033ac..67764cc 100644
--- a/arch/arm/cpu/armv7/stv0991/timer.c
+++ b/arch/arm/cpu/armv7/stv0991/timer.c
@@ -18,7 +18,7 @@
(struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
#define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING)
-#define GPT_RESOLUTION (CONFIG_STV0991_HZ_CLOCK / CONFIG_STV0991_HZ)
+#define GPT_RESOLUTION (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
DECLARE_GLOBAL_DATA_PTR;
@@ -67,7 +67,7 @@
{
ulong tmo;
ulong start = get_timer_masked();
- ulong tenudelcnt = CONFIG_STV0991_HZ_CLOCK / (1000 * 100);
+ ulong tenudelcnt = CONFIG_SYS_HZ_CLOCK / (1000 * 100);
ulong rndoff;
rndoff = (usec % 10) ? 1 : 0;
@@ -110,5 +110,5 @@
*/
ulong get_tbclk(void)
{
- return CONFIG_STV0991_HZ;
+ return CONFIG_SYS_HZ;
}
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 41f3e95..9820d32 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -54,7 +54,8 @@
lpi_base.start = addr;
lpi_base.end = addr + size - 1;
- ret = fdtdec_add_reserved_memory(blob, "lpi_rd_table", &lpi_base, NULL, false);
+ ret = fdtdec_add_reserved_memory(blob, "lpi_rd_table", &lpi_base, NULL,
+ 0, NULL, 0);
if (ret) {
debug("%s: failed to add reserved memory\n", __func__);
return ret;
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b8a382d..b549f3c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -638,6 +638,7 @@
sun50i-h5-libretech-all-h5-cc.dtb \
sun50i-h5-nanopi-neo2.dtb \
sun50i-h5-nanopi-neo-plus2.dtb \
+ sun50i-h5-nanopi-r1s-h5.dtb \
sun50i-h5-orangepi-zero-plus.dtb \
sun50i-h5-orangepi-pc2.dtb \
sun50i-h5-orangepi-prime.dtb \
@@ -821,7 +822,9 @@
imx6ul-liteboard.dtb \
imx6ul-phytec-segin-ff-rdk-nand.dtb \
imx6ul-pico-hobbit.dtb \
- imx6ul-pico-pi.dtb
+ imx6ul-pico-pi.dtb \
+ imx6ul-kontron-n631x-s.dtb \
+ imx6ull-kontron-n641x-s.dtb
dtb-$(CONFIG_MX6ULL) += \
imx6ull-14x14-evk.dtb \
@@ -876,6 +879,8 @@
imx8mm-evk.dtb \
imx8mm-icore-mx8mm-ctouch2.dtb \
imx8mm-icore-mx8mm-edimm2.2.dtb \
+ imx8mm-kontron-n801x-s.dtb \
+ imx8mm-kontron-n801x-s-lvds.dtb \
imx8mm-venice.dtb \
imx8mm-venice-gw71xx-0x.dtb \
imx8mm-venice-gw72xx-0x.dtb \
@@ -1143,6 +1148,8 @@
dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) += imx8mm-cl-iot-gate.dtb
+dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE_OPTEE) += imx8mm-cl-iot-gate-optee.dtb
+
dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) += lpc3250-ea3250.dtb
targets += $(dtb-y)
diff --git a/arch/arm/dts/am33xx-clocks.dtsi b/arch/arm/dts/am33xx-clocks.dtsi
index 9221824..44b6268 100644
--- a/arch/arm/dts/am33xx-clocks.dtsi
+++ b/arch/arm/dts/am33xx-clocks.dtsi
@@ -167,7 +167,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-core-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x0490>, <0x045c>, <0x0468>;
+ reg = <0x0490>, <0x045c>, <0x0468>, <0x0460>, <0x0464>;
};
dpll_core_x2_ck: dpll_core_x2_ck {
@@ -207,7 +207,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x0488>, <0x0420>, <0x042c>;
+ reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>;
};
dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 {
@@ -223,7 +223,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-no-gate-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x0494>, <0x0434>, <0x0440>;
+ reg = <0x0494>, <0x0434>, <0x0440>, <0x0438>, <0x043c>;
};
dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 {
@@ -247,7 +247,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-no-gate-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x0498>, <0x0448>, <0x0454>;
+ reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>;
};
dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 {
@@ -264,7 +264,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-no-gate-j-type-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x048c>, <0x0470>, <0x049c>;
+ reg = <0x048c>, <0x0470>, <0x049c>, <0x0474>, <0x0478>;
};
dpll_per_m2_ck: dpll_per_m2_ck@4ac {
diff --git a/arch/arm/dts/am43xx-clocks.dtsi b/arch/arm/dts/am43xx-clocks.dtsi
index d0c0dfa..b1127b5 100644
--- a/arch/arm/dts/am43xx-clocks.dtsi
+++ b/arch/arm/dts/am43xx-clocks.dtsi
@@ -199,7 +199,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-core-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x2d20>, <0x2d24>, <0x2d2c>;
+ reg = <0x2d20>, <0x2d24>, <0x2d2c>, <0x2d48>, <0x2d4c>;
};
dpll_core_x2_ck: dpll_core_x2_ck {
@@ -245,7 +245,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x2d60>, <0x2d64>, <0x2d6c>;
+ reg = <0x2d60>, <0x2d64>, <0x2d6c>, <0x2d88>, <0x2d8c>;
};
dpll_mpu_m2_ck: dpll_mpu_m2_ck {
@@ -263,7 +263,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x2da0>, <0x2da4>, <0x2dac>;
+ reg = <0x2da0>, <0x2da4>, <0x2dac>, <0x2dc8>, <0x2dcc>;
};
dpll_ddr_m2_ck: dpll_ddr_m2_ck {
@@ -281,7 +281,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x2e20>, <0x2e24>, <0x2e2c>;
+ reg = <0x2e20>, <0x2e24>, <0x2e2c>, <0x2e48>, <0x2e4c>;
};
dpll_disp_m2_ck: dpll_disp_m2_ck {
@@ -300,7 +300,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-j-type-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x2de0>, <0x2de4>, <0x2dec>;
+ reg = <0x2de0>, <0x2de4>, <0x2dec>, <0x2e08>, <0x2e0c>;
};
dpll_per_m2_ck: dpll_per_m2_ck {
@@ -583,7 +583,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x2e60>, <0x2e64>, <0x2e6c>;
+ reg = <0x2e60>, <0x2e64>, <0x2e6c>, <0x2e88>, <0x2e8c>;
};
dpll_extdev_m2_ck: dpll_extdev_m2_ck {
diff --git a/arch/arm/dts/armada-37xx.dtsi b/arch/arm/dts/armada-37xx.dtsi
index 2615b8c..fec3460 100644
--- a/arch/arm/dts/armada-37xx.dtsi
+++ b/arch/arm/dts/armada-37xx.dtsi
@@ -335,14 +335,14 @@
/*
* The 128 MiB address range [0xe8000000-0xf0000000] is
* dedicated for PCIe and can be assigned to 8 windows
- * with size a power of two. Use one 64 KiB window for
+ * with size a power of two. Use one 1 MiB window for
* IO at the end and the remaining seven windows
* (totaling 127 MiB) for MEM.
*/
ranges = <0x82000000 0 0xe8000000
0 0xe8000000 0 0x7f00000 /* Port 0 MEM */
- 0x81000000 0 0xefff0000
- 0 0xefff0000 0 0x10000>; /* Port 0 IO*/
+ 0x81000000 0 0xeff00000
+ 0 0xeff00000 0 0x100000>; /* Port 0 IO*/
};
};
};
diff --git a/arch/arm/dts/armada-8040-puzzle-m801.dts b/arch/arm/dts/armada-8040-puzzle-m801.dts
index 510fb84..9e714c3 100644
--- a/arch/arm/dts/armada-8040-puzzle-m801.dts
+++ b/arch/arm/dts/armada-8040-puzzle-m801.dts
@@ -243,6 +243,9 @@
&cp1_mdio {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_smi_pins>;
+
cp1_ge_phy0: ethernet-phy@3 {
reg = <1>;
};
@@ -292,33 +295,24 @@
/*
* MPP Bus:
* [0-5] TDM
- * [6,7] CP1_UART 0
- * [8] CP1 10G SFP LOS
- * [9] CP1 10G PHY RESET
- * [10] CP1 10G SFP TX Disable
- * [11] CP1 10G SFP Mode
- * [12] SPI1 CS1n
- * [13] SPI1 MISO (TDM and SPI ROM shared)
- * [14] SPI1 CS0n
- * [15] SPI1 MOSI (TDM and SPI ROM shared)
- * [16] SPI1 CLK (TDM and SPI ROM shared)
- * [24] CP1 2.5G SFP TX Disable
- * [26] CP0 10G SFP TX Fault
- * [27] CP0 10G SFP Mode
- * [28] CP0 10G SFP LOS
- * [29] CP0 10G SFP TX Disable
- * [30] USB Over current indication
- * [31] 10G Port 0 phy reset
+ * [27-28] SMI
+ * [29-30] CP1 MSS I2C
+ * [6-26, 31] GPIO
* [32-62] = 0xff: Keep default CP1_shared_pins:
*/
/* 0 1 2 3 4 5 6 7 8 9 */
- pin-func = < 0x4 0x4 0x4 0x4 0x4 0x4 0x8 0x8 0x0 0x0
- 0x0 0x0 0x3 0x3 0x3 0x3 0x3 0xff 0xff 0xff
- 0xff 0xff 0xff 0xff 0x0 0xff 0x0 0x0 0x0 0x0
- 0x0 0x0 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+ pin-func = < 0x4 0x4 0x4 0x4 0x4 0x4 0x0 0x0 0x0 0x0
+ 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
+ 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x8 0x8 0x8
+ 0x8 0x0 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
0xff 0xff 0xff>;
+
+ cp1_smi_pins: cp1-smi-pins {
+ marvell,pins = < 27 28 >;
+ marvell,function = <8>;
+ };
};
&ap_spi0 {
diff --git a/arch/arm/dts/imx53-m53menlo-u-boot.dtsi b/arch/arm/dts/imx53-m53menlo-u-boot.dtsi
index bc4b348..869adb9 100644
--- a/arch/arm/dts/imx53-m53menlo-u-boot.dtsi
+++ b/arch/arm/dts/imx53-m53menlo-u-boot.dtsi
@@ -7,7 +7,7 @@
soc {
u-boot,dm-pre-reloc;
- aips@50000000 {
+ bus@50000000 {
u-boot,dm-pre-reloc;
};
};
diff --git a/arch/arm/dts/imx53-usbarmory.dts b/arch/arm/dts/imx53-usbarmory.dts
index f34993a..433b62e 100644
--- a/arch/arm/dts/imx53-usbarmory.dts
+++ b/arch/arm/dts/imx53-usbarmory.dts
@@ -91,6 +91,7 @@
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1>;
+ broken-cd;
status = "okay";
};
diff --git a/arch/arm/dts/imx53.dtsi b/arch/arm/dts/imx53.dtsi
index ed341cf..8536f59 100644
--- a/arch/arm/dts/imx53.dtsi
+++ b/arch/arm/dts/imx53.dtsi
@@ -222,7 +222,7 @@
clock-names = "core_clk", "mem_iface_clk";
};
- aips@50000000 { /* AIPS1 */
+ bus@50000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -654,7 +654,7 @@
};
};
- aips@60000000 { /* AIPS2 */
+ bus@60000000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/dts/imx6-apalis-u-boot.dtsi b/arch/arm/dts/imx6-apalis-u-boot.dtsi
new file mode 100644
index 0000000..95e7e02
--- /dev/null
+++ b/arch/arm/dts/imx6-apalis-u-boot.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Copyright 2020 Foundries.IO
+ */
+
+#include "imx6qdl-u-boot.dtsi"
+
+&wdog1 {
+ status = "okay";
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx6dl.dtsi b/arch/arm/dts/imx6dl.dtsi
index f0607eb..ae5aad6 100644
--- a/arch/arm/dts/imx6dl.dtsi
+++ b/arch/arm/dts/imx6dl.dtsi
@@ -84,7 +84,7 @@
clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
- aips1: aips-bus@2000000 {
+ aips1: bus@2000000 {
iomuxc: iomuxc@20e0000 {
compatible = "fsl,imx6dl-iomuxc";
};
@@ -100,7 +100,7 @@
};
};
- aips2: aips-bus@2100000 {
+ aips2: bus@2100000 {
i2c4: i2c@21f8000 {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/dts/imx6q-display5-u-boot.dtsi b/arch/arm/dts/imx6q-display5-u-boot.dtsi
index aa660b5..ced4dac 100644
--- a/arch/arm/dts/imx6q-display5-u-boot.dtsi
+++ b/arch/arm/dts/imx6q-display5-u-boot.dtsi
@@ -23,7 +23,7 @@
soc {
u-boot,dm-pre-reloc;
- aips-bus@2100000 {
+ bus@2100000 {
u-boot,dm-pre-reloc;
};
};
diff --git a/arch/arm/dts/imx6q.dtsi b/arch/arm/dts/imx6q.dtsi
index 71543a4..c37484d 100644
--- a/arch/arm/dts/imx6q.dtsi
+++ b/arch/arm/dts/imx6q.dtsi
@@ -162,7 +162,7 @@
clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
- aips-bus@2000000 { /* AIPS1 */
+ bus@2000000 { /* AIPS1 */
spba-bus@2000000 {
ecspi5: spi@2018000 {
#address-cells = <1>;
diff --git a/arch/arm/dts/imx6qdl-gw53xx.dtsi b/arch/arm/dts/imx6qdl-gw53xx.dtsi
index 904b228..77ac103 100644
--- a/arch/arm/dts/imx6qdl-gw53xx.dtsi
+++ b/arch/arm/dts/imx6qdl-gw53xx.dtsi
@@ -137,7 +137,8 @@
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- regulator-always-on;
+ gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
@@ -550,6 +551,8 @@
&usbh1 {
vbus-supply = <®_usb_h1_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh1>;
status = "okay";
};
@@ -720,6 +723,12 @@
>;
};
+ pinctrl_usbh1: usbh1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
+ >;
+ };
+
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
diff --git a/arch/arm/dts/imx6qdl-gw54xx.dtsi b/arch/arm/dts/imx6qdl-gw54xx.dtsi
index ffed4fb..98c81e9 100644
--- a/arch/arm/dts/imx6qdl-gw54xx.dtsi
+++ b/arch/arm/dts/imx6qdl-gw54xx.dtsi
@@ -146,7 +146,8 @@
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- regulator-always-on;
+ gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
};
reg_usb_otg_vbus: regulator@3 {
@@ -620,6 +621,8 @@
&usbh1 {
vbus-supply = <®_usb_h1_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh1>;
status = "okay";
};
@@ -815,6 +818,12 @@
>;
};
+ pinctrl_usbh1: usbh1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
+ >;
+ };
+
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
diff --git a/arch/arm/dts/imx6qdl-gw552x.dtsi b/arch/arm/dts/imx6qdl-gw552x.dtsi
index f6742e5..b853399 100644
--- a/arch/arm/dts/imx6qdl-gw552x.dtsi
+++ b/arch/arm/dts/imx6qdl-gw552x.dtsi
@@ -121,6 +121,15 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
+
+ reg_usb_h1_vbus: regulator-usbh1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_h1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
};
&gpmi {
@@ -390,9 +399,13 @@
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
- status = "okay"; };
+ status = "okay";
+};
&usbh1 {
+ vbus-supply = <®_usb_h1_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh1>;
status = "okay";
};
@@ -507,6 +520,12 @@
>;
};
+ pinctrl_usbh1: usbh1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
+ >;
+ };
+
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x13059
diff --git a/arch/arm/dts/imx6qdl-gw560x.dtsi b/arch/arm/dts/imx6qdl-gw560x.dtsi
index 5da1975..1e95267 100644
--- a/arch/arm/dts/imx6qdl-gw560x.dtsi
+++ b/arch/arm/dts/imx6qdl-gw560x.dtsi
@@ -221,7 +221,8 @@
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- regulator-always-on;
+ gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
diff --git a/arch/arm/dts/imx6qdl-gw5904.dtsi b/arch/arm/dts/imx6qdl-gw5904.dtsi
index b5ed2d8..286c7a9 100644
--- a/arch/arm/dts/imx6qdl-gw5904.dtsi
+++ b/arch/arm/dts/imx6qdl-gw5904.dtsi
@@ -176,7 +176,8 @@
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- regulator-always-on;
+ gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
@@ -593,6 +594,8 @@
&usbh1 {
vbus-supply = <®_usb_h1_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
status = "okay";
};
@@ -753,6 +756,12 @@
>;
};
+ pinctrl_usbh1: usbh1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
+ >;
+ };
+
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
diff --git a/arch/arm/dts/imx6qdl-gw5912.dtsi b/arch/arm/dts/imx6qdl-gw5912.dtsi
index 2537288..8fd8fdb 100644
--- a/arch/arm/dts/imx6qdl-gw5912.dtsi
+++ b/arch/arm/dts/imx6qdl-gw5912.dtsi
@@ -120,7 +120,8 @@
regulator-name = "usb_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- regulator-always-on;
+ gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
};
};
@@ -380,6 +381,8 @@
&usbh1 {
vbus-supply = <®_usb_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh1>;
status = "okay";
};
@@ -560,6 +563,12 @@
>;
};
+ pinctrl_usbh1: usbh1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
+ >;
+ };
+
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
diff --git a/arch/arm/dts/imx6qdl-u-boot.dtsi b/arch/arm/dts/imx6qdl-u-boot.dtsi
index 1279cc2..f74af6c 100644
--- a/arch/arm/dts/imx6qdl-u-boot.dtsi
+++ b/arch/arm/dts/imx6qdl-u-boot.dtsi
@@ -13,14 +13,14 @@
u-boot,dm-spl;
u-boot,dm-pre-reloc;
- aips-bus@2000000 {
+ bus@2000000 {
u-boot,dm-spl;
spba-bus@2000000 {
u-boot,dm-spl;
};
};
- aips-bus@2100000 {
+ bus@2100000 {
u-boot,dm-spl;
};
};
diff --git a/arch/arm/dts/imx6qdl.dtsi b/arch/arm/dts/imx6qdl.dtsi
index e4daf15..1cdb498 100644
--- a/arch/arm/dts/imx6qdl.dtsi
+++ b/arch/arm/dts/imx6qdl.dtsi
@@ -283,7 +283,7 @@
status = "disabled";
};
- aips-bus@2000000 { /* AIPS1 */
+ bus@2000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -913,7 +913,7 @@
};
};
- aips-bus@2100000 { /* AIPS2 */
+ bus@2100000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/dts/imx6qp.dtsi b/arch/arm/dts/imx6qp.dtsi
index 5f51f8e..93b89dc 100644
--- a/arch/arm/dts/imx6qp.dtsi
+++ b/arch/arm/dts/imx6qp.dtsi
@@ -18,7 +18,7 @@
clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
- aips-bus@2100000 {
+ bus@2100000 {
pre1: pre@21c8000 {
compatible = "fsl,imx6qp-pre";
reg = <0x021c8000 0x1000>;
diff --git a/arch/arm/dts/imx6sl.dtsi b/arch/arm/dts/imx6sl.dtsi
index cc9572e..37e341c 100644
--- a/arch/arm/dts/imx6sl.dtsi
+++ b/arch/arm/dts/imx6sl.dtsi
@@ -130,7 +130,7 @@
interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
};
- aips1: aips-bus@02000000 {
+ aips1: bus@02000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -751,7 +751,7 @@
};
};
- aips2: aips-bus@02100000 {
+ aips2: bus@02100000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/dts/imx6sll.dtsi b/arch/arm/dts/imx6sll.dtsi
index 349c47a..ebc6d9d 100644
--- a/arch/arm/dts/imx6sll.dtsi
+++ b/arch/arm/dts/imx6sll.dtsi
@@ -176,7 +176,7 @@
arm,data-latency = <4 2 3>;
};
- aips1: aips-bus@02000000 {
+ aips1: bus@02000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -682,7 +682,7 @@
};
};
- aips2: aips-bus@02100000 {
+ aips2: bus@02100000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/dts/imx6sx.dtsi b/arch/arm/dts/imx6sx.dtsi
index 531a52c..8d2d396 100644
--- a/arch/arm/dts/imx6sx.dtsi
+++ b/arch/arm/dts/imx6sx.dtsi
@@ -235,7 +235,7 @@
status = "disabled";
};
- aips1: aips-bus@2000000 {
+ aips1: bus@2000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -830,7 +830,7 @@
};
};
- aips2: aips-bus@2100000 {
+ aips2: bus@2100000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -1188,7 +1188,7 @@
};
};
- aips3: aips-bus@2200000 {
+ aips3: bus@2200000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/dts/imx6ul-kontron-n631x-s-u-boot.dtsi b/arch/arm/dts/imx6ul-kontron-n631x-s-u-boot.dtsi
new file mode 100644
index 0000000..d3f013c
--- /dev/null
+++ b/arch/arm/dts/imx6ul-kontron-n631x-s-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ */
+
+#include "imx6ul-kontron-n6x1x-s-u-boot.dtsi"
diff --git a/arch/arm/dts/imx6ul-kontron-n631x-s.dts b/arch/arm/dts/imx6ul-kontron-n631x-s.dts
new file mode 100644
index 0000000..407d2b1
--- /dev/null
+++ b/arch/arm/dts/imx6ul-kontron-n631x-s.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
+ */
+
+/dts-v1/;
+
+#include "imx6ul-kontron-n631x-som.dtsi"
+#include "imx6ul-kontron-n6x1x-s.dtsi"
+
+/ {
+ model = "Kontron N631X S";
+ compatible = "kontron,imx6ul-n631x-s", "kontron,imx6ul-n631x-som",
+ "fsl,imx6ul";
+};
diff --git a/arch/arm/dts/imx6ul-kontron-n631x-som.dtsi b/arch/arm/dts/imx6ul-kontron-n631x-som.dtsi
new file mode 100644
index 0000000..9a11798
--- /dev/null
+++ b/arch/arm/dts/imx6ul-kontron-n631x-som.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
+ */
+
+#include "imx6ul.dtsi"
+#include "imx6ul-kontron-n6x1x-som-common.dtsi"
+
+/ {
+ model = "Kontron N631X SOM";
+ compatible = "kontron,imx6ul-n631x-som", "fsl,imx6ul";
+};
diff --git a/arch/arm/dts/imx6ul-kontron-n6x1x-s-u-boot.dtsi b/arch/arm/dts/imx6ul-kontron-n6x1x-s-u-boot.dtsi
new file mode 100644
index 0000000..39cc6d0
--- /dev/null
+++ b/arch/arm/dts/imx6ul-kontron-n6x1x-s-u-boot.dtsi
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ */
+
+#if defined(CONFIG_FIT)
+
+/ {
+ binman: binman {
+ filename = "flash.bin";
+ pad-byte = <0x00>;
+
+ spl: blob-ext@1 {
+ offset = <0x0>;
+ filename = "SPL";
+ };
+
+ uboot: blob-ext@2 {
+ offset = <0x11000>;
+ filename = "u-boot.img";
+ };
+ };
+};
+
+#endif /* CONFIG_FIT */
+
+/*
+ * To make the PHYs work, we need to set the reset pin once. Afterwards
+ * in Linux we can't assign the shared reset GPIO to the PHYs, as this
+ * would cause Linux to reset both PHYs every time one of them gets
+ * reinitialized.
+ *
+ * Also we disable the second ethernet as it currently doesn't work with
+ * the devicetree setup in U-Boot.
+ */
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>;
+ phy-mode = "rmii";
+ phy-handle = <ðphy1>;
+ phy-reset-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@1 {
+ reg = <1>;
+ micrel,led-mode = <0>;
+ clocks = <&clks IMX6UL_CLK_ENET_REF>;
+ clock-names = "rmii-ref";
+ };
+ };
+};
+
+&fec2 {
+ status = "disabled";
+ /delete-property/ phy-handle;
+ /delete-node/ mdio;
+};
diff --git a/arch/arm/dts/imx6ul-kontron-n6x1x-s.dts b/arch/arm/dts/imx6ul-kontron-n6x1x-s.dts
new file mode 100644
index 0000000..84d8a71
--- /dev/null
+++ b/arch/arm/dts/imx6ul-kontron-n6x1x-s.dts
@@ -0,0 +1,423 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include "imx6ul-kontron-n6x1x-som.dtsi"
+
+/ {
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led1 {
+ label = "debug-led1";
+ gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ linux,default-trigger = "heartbeat";
+ };
+
+ led2 {
+ label = "debug-led2";
+ gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led3 {
+ label = "debug-led3";
+ gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ };
+
+ pwm-beeper {
+ compatible = "pwm-beeper";
+ pwms = <&pwm8 0 5000>;
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_vref_adc: regulator-vref-adc {
+ compatible = "regulator-fixed";
+ regulator-name = "vref-adc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&adc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc1>;
+ num-channels = <3>;
+ vref-supply = <®_vref_adc>;
+ status = "okay";
+};
+
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ status = "okay";
+};
+
+&ecspi1 {
+ cs-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ status = "okay";
+
+ eeprom@0 {
+ compatible = "anvo,anv32e61w", "atmel,at25";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ spi-cpha;
+ spi-cpol;
+ pagesize = <1>;
+ size = <8192>;
+ address-width = <16>;
+ };
+};
+
+&fec1 {
+ pinctrl-0 = <&pinctrl_enet1>;
+ /delete-node/ mdio;
+};
+
+&fec2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
+ phy-mode = "rmii";
+ phy-handle = <ðphy2>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@1 {
+ reg = <1>;
+ micrel,led-mode = <0>;
+ clocks = <&clks IMX6UL_CLK_ENET_REF>;
+ clock-names = "rmii-ref";
+ };
+
+ ethphy2: ethernet-phy@2 {
+ reg = <2>;
+ micrel,led-mode = <0>;
+ clocks = <&clks IMX6UL_CLK_ENET2_REF>;
+ clock-names = "rmii-ref";
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+};
+
+&i2c4 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+
+ rtc@32 {
+ compatible = "epson,rx8900";
+ reg = <0x32>;
+ };
+};
+
+&pwm8 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm8>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ linux,rs485-enabled-at-boot-time;
+ rs485-rx-during-tx;
+ rs485-rts-active-low;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ fsl,uart-has-rtscts;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&usbotg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1>;
+ dr_mode = "otg";
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+ over-current-active-low;
+ vbus-supply = <®_usb_otg1_vbus>;
+ status = "okay";
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ disable-over-current;
+ vbus-supply = <®_5v>;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+ keep-power-in-suspend;
+ wakeup-source;
+ vmmc-supply = <®_3v3>;
+ voltage-ranges = <3300 3300>;
+ bus-width = <4>;
+ no-1-8-v;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+ non-removable;
+ keep-power-in-suspend;
+ wakeup-source;
+ vmmc-supply = <®_3v3>;
+ voltage-ranges = <3300 3300>;
+ bus-width = <4>;
+ no-1-8-v;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>;
+
+ pinctrl_adc1: adc1grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
+ MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
+ MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1
+ MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1
+ MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1
+ MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */
+ >;
+ };
+
+ pinctrl_enet2: enet2grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
+ MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009
+ >;
+ };
+
+ pinctrl_enet2_mdio: enet2mdiogrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
+ MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp{
+ fsl,pins = <
+ MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
+ MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
+ >;
+ };
+
+ pinctrl_gpio: gpiogrp {
+ fsl,pins = <
+ MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */
+ MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */
+ MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */
+ MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
+ MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */
+ MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */
+ MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
+ MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0
+ MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0
+ >;
+ };
+
+ pinctrl_pwm8: pwm8grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1
+ MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1
+ MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1
+ /*
+ * mux unused RTS to make sure it doesn't cause
+ * any interrupts when it is undefined
+ */
+ MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
+ MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1
+ MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg1: usbotg1 {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x30b0
+ >;
+ };
+};
diff --git a/arch/arm/dts/imx6ul-kontron-n6x1x-s.dtsi b/arch/arm/dts/imx6ul-kontron-n6x1x-s.dtsi
new file mode 100644
index 0000000..4682a79
--- /dev/null
+++ b/arch/arm/dts/imx6ul-kontron-n6x1x-s.dtsi
@@ -0,0 +1,420 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led1 {
+ label = "debug-led1";
+ gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ linux,default-trigger = "heartbeat";
+ };
+
+ led2 {
+ label = "debug-led2";
+ gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led3 {
+ label = "debug-led3";
+ gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ };
+
+ pwm-beeper {
+ compatible = "pwm-beeper";
+ pwms = <&pwm8 0 5000>;
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_vref_adc: regulator-vref-adc {
+ compatible = "regulator-fixed";
+ regulator-name = "vref-adc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&adc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc1>;
+ num-channels = <3>;
+ vref-supply = <®_vref_adc>;
+ status = "okay";
+};
+
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ status = "okay";
+};
+
+&ecspi1 {
+ cs-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ status = "okay";
+
+ eeprom@0 {
+ compatible = "anvo,anv32e61w", "atmel,at25";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ spi-cpha;
+ spi-cpol;
+ pagesize = <1>;
+ size = <8192>;
+ address-width = <16>;
+ };
+};
+
+&fec1 {
+ pinctrl-0 = <&pinctrl_enet1>;
+ /delete-node/ mdio;
+};
+
+&fec2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
+ phy-mode = "rmii";
+ phy-handle = <ðphy2>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@1 {
+ reg = <1>;
+ micrel,led-mode = <0>;
+ clocks = <&clks IMX6UL_CLK_ENET_REF>;
+ clock-names = "rmii-ref";
+ };
+
+ ethphy2: ethernet-phy@2 {
+ reg = <2>;
+ micrel,led-mode = <0>;
+ clocks = <&clks IMX6UL_CLK_ENET2_REF>;
+ clock-names = "rmii-ref";
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+};
+
+&i2c4 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+
+ rtc@32 {
+ compatible = "epson,rx8900";
+ reg = <0x32>;
+ };
+};
+
+&pwm8 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm8>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ linux,rs485-enabled-at-boot-time;
+ rs485-rx-during-tx;
+ rs485-rts-active-low;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ fsl,uart-has-rtscts;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&usbotg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1>;
+ dr_mode = "otg";
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+ over-current-active-low;
+ vbus-supply = <®_usb_otg1_vbus>;
+ status = "okay";
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ disable-over-current;
+ vbus-supply = <®_5v>;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+ keep-power-in-suspend;
+ wakeup-source;
+ vmmc-supply = <®_3v3>;
+ voltage-ranges = <3300 3300>;
+ bus-width = <4>;
+ no-1-8-v;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+ non-removable;
+ keep-power-in-suspend;
+ wakeup-source;
+ vmmc-supply = <®_3v3>;
+ voltage-ranges = <3300 3300>;
+ bus-width = <4>;
+ no-1-8-v;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>;
+
+ pinctrl_adc1: adc1grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
+ MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
+ MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1
+ MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1
+ MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1
+ MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */
+ >;
+ };
+
+ pinctrl_enet2: enet2grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
+ MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009
+ >;
+ };
+
+ pinctrl_enet2_mdio: enet2mdiogrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
+ MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp{
+ fsl,pins = <
+ MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
+ MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
+ >;
+ };
+
+ pinctrl_gpio: gpiogrp {
+ fsl,pins = <
+ MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */
+ MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */
+ MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */
+ MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
+ MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */
+ MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */
+ MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
+ MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0
+ MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0
+ >;
+ };
+
+ pinctrl_pwm8: pwm8grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1
+ MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1
+ MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1
+ /*
+ * mux unused RTS to make sure it doesn't cause
+ * any interrupts when it is undefined
+ */
+ MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
+ MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1
+ MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg1: usbotg1 {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x30b0
+ >;
+ };
+};
diff --git a/arch/arm/dts/imx6ul-kontron-n6x1x-som-common.dtsi b/arch/arm/dts/imx6ul-kontron-n6x1x-som-common.dtsi
new file mode 100644
index 0000000..e9ec6b7
--- /dev/null
+++ b/arch/arm/dts/imx6ul-kontron-n6x1x-som-common.dtsi
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ chosen {
+ stdout-path = &uart4;
+ };
+
+ memory@80000000 {
+ reg = <0x80000000 0x10000000>;
+ device_type = "memory";
+ };
+};
+
+&ecspi2 {
+ cs-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ status = "okay";
+
+ spi-flash@0 {
+ compatible = "mxicy,mx25v8035f", "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>;
+ phy-mode = "rmii";
+ phy-handle = <ðphy1>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@1 {
+ reg = <1>;
+ micrel,led-mode = <0>;
+ clocks = <&clks IMX6UL_CLK_ENET_REF>;
+ clock-names = "rmii-ref";
+ };
+ };
+};
+
+&fec2 {
+ phy-mode = "rmii";
+ status = "disabled";
+};
+
+&qspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi>;
+ status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ spi-max-frequency = <104000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ reg = <0>;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reset_out>;
+
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x100b1
+ MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x100b1
+ MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x100b1
+ MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x100b1
+ >;
+ };
+
+ pinctrl_enet1: enet1grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009
+ >;
+ };
+
+ pinctrl_enet1_mdio: enet1mdiogrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
+ MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
+ >;
+ };
+
+ pinctrl_qspi: qspigrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
+ MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
+ MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
+ MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
+ MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
+ MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
+ >;
+ };
+
+ pinctrl_reset_out: rstoutgrp {
+ fsl,pins = <
+ MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0
+ >;
+ };
+};
diff --git a/arch/arm/dts/imx6ul.dtsi b/arch/arm/dts/imx6ul.dtsi
index 5644b0f..ad9cb37 100644
--- a/arch/arm/dts/imx6ul.dtsi
+++ b/arch/arm/dts/imx6ul.dtsi
@@ -206,7 +206,7 @@
status = "disabled";
};
- aips1: aips-bus@2000000 {
+ aips1: bus@2000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -763,7 +763,7 @@
};
};
- aips2: aips-bus@2100000 {
+ aips2: bus@2100000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/dts/imx6ull-kontron-n641x-s-u-boot.dtsi b/arch/arm/dts/imx6ull-kontron-n641x-s-u-boot.dtsi
new file mode 100644
index 0000000..d3f013c
--- /dev/null
+++ b/arch/arm/dts/imx6ull-kontron-n641x-s-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ */
+
+#include "imx6ul-kontron-n6x1x-s-u-boot.dtsi"
diff --git a/arch/arm/dts/imx6ull-kontron-n641x-s.dts b/arch/arm/dts/imx6ull-kontron-n641x-s.dts
new file mode 100644
index 0000000..01aeea4
--- /dev/null
+++ b/arch/arm/dts/imx6ull-kontron-n641x-s.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ */
+
+/dts-v1/;
+
+#include "imx6ull-kontron-n641x-som.dtsi"
+#include "imx6ul-kontron-n6x1x-s.dtsi"
+
+/ {
+ model = "Kontron N641X S";
+ compatible = "kontron,imx6ull-n641x-s", "kontron,imx6ull-n641x-som",
+ "fsl,imx6ull";
+};
diff --git a/arch/arm/dts/imx6ull-kontron-n641x-som.dtsi b/arch/arm/dts/imx6ull-kontron-n641x-som.dtsi
new file mode 100644
index 0000000..8a64aa9
--- /dev/null
+++ b/arch/arm/dts/imx6ull-kontron-n641x-som.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ */
+
+#include "imx6ull.dtsi"
+#include "imx6ul-kontron-n6x1x-som-common.dtsi"
+
+/ {
+ model = "Kontron N641X SOM";
+ compatible = "kontron,imx6ull-n641x-som", "fsl,imx6ull";
+};
diff --git a/arch/arm/dts/imx6ull.dtsi b/arch/arm/dts/imx6ull.dtsi
index 22e4a30..f224e20 100644
--- a/arch/arm/dts/imx6ull.dtsi
+++ b/arch/arm/dts/imx6ull.dtsi
@@ -44,7 +44,7 @@
/ {
soc {
- aips3: aips-bus@2200000 {
+ aips3: bus@2200000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/dts/imx7s.dtsi b/arch/arm/dts/imx7s.dtsi
index 967023f..483824f 100644
--- a/arch/arm/dts/imx7s.dtsi
+++ b/arch/arm/dts/imx7s.dtsi
@@ -340,7 +340,7 @@
<0x31006000 0x2000>;
};
- aips1: aips-bus@30000000 {
+ aips1: bus@30000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -647,7 +647,7 @@
};
};
- aips2: aips-bus@30400000 {
+ aips2: bus@30400000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -739,7 +739,7 @@
};
};
- aips3: aips-bus@30800000 {
+ aips3: bus@30800000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-optee-u-boot.dtsi b/arch/arm/dts/imx8mm-cl-iot-gate-optee-u-boot.dtsi
new file mode 100644
index 0000000..1206593
--- /dev/null
+++ b/arch/arm/dts/imx8mm-cl-iot-gate-optee-u-boot.dtsi
@@ -0,0 +1,255 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ u-boot,dm-spl;
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+};
+
+&{/soc@0} {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+&clk {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+};
+
+&osc_24m {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&aips1 {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&aips2 {
+ u-boot,dm-spl;
+};
+
+&aips3 {
+ u-boot,dm-spl;
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+};
+
+&pinctrl_uart3 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_gpio {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&uart3 {
+ u-boot,dm-spl;
+};
+
+&usdhc1 {
+ u-boot,dm-spl;
+};
+
+&usdhc2 {
+ u-boot,dm-spl;
+};
+
+&usdhc3 {
+ u-boot,dm-spl;
+};
+
+&i2c1 {
+ u-boot,dm-spl;
+};
+
+&i2c2 {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b/regulators} {
+ u-boot,dm-spl;
+};
+
+&pinctrl_i2c2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_pmic {
+ u-boot,dm-spl;
+};
+
+&fec1 {
+ phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+};
+
+&wdog1 {
+ u-boot,dm-spl;
+};
+
+&binman {
+ u-boot-spl-ddr {
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+ align-size = <4>;
+ align = <4>;
+
+ u-boot-spl {
+ align-end = <4>;
+ };
+
+ blob_1: blob-ext@1 {
+ filename = "lpddr4_pmu_train_1d_imem.bin";
+ size = <0x8000>;
+ };
+
+ blob_2: blob-ext@2 {
+ filename = "lpddr4_pmu_train_1d_dmem.bin";
+ size = <0x4000>;
+ };
+
+ blob_3: blob-ext@3 {
+ filename = "lpddr4_pmu_train_2d_imem.bin";
+ size = <0x8000>;
+ };
+
+ blob_4: blob-ext@4 {
+ filename = "lpddr4_pmu_train_2d_dmem.bin";
+ size = <0x4000>;
+ };
+ };
+
+ flash {
+ mkimage {
+ args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000";
+
+ blob {
+ filename = "u-boot-spl-ddr.bin";
+ };
+ };
+ };
+
+ itb {
+ filename = "u-boot.itb";
+
+ fit {
+ description = "Configuration to load ATF before U-Boot";
+ #address-cells = <1>;
+ fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
+
+ images {
+ uboot {
+ description = "U-Boot (64-bit)";
+ type = "standalone";
+ arch = "arm64";
+ compression = "none";
+ load = <CONFIG_SYS_TEXT_BASE>;
+
+ uboot_blob: blob-ext {
+ filename = "u-boot-nodtb.bin";
+ };
+ };
+
+ atf {
+ description = "ARM Trusted Firmware";
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <0x920000>;
+ entry = <0x920000>;
+
+ atf_blob: blob-ext {
+ filename = "bl2.bin";
+ };
+ };
+
+ fip {
+ description = "Trusted Firmware FIP";
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <0x40310000>;
+
+ fip_blob: blob-ext{
+ filename = "fip.bin";
+ };
+ };
+
+ fdt {
+ description = "NAME";
+ type = "flat_dt";
+ compression = "none";
+
+ uboot_fdt_blob: blob-ext {
+ filename = "u-boot.dtb";
+ };
+ };
+ };
+
+ configurations {
+ default = "conf";
+
+ conf {
+ description = "NAME";
+ firmware = "uboot";
+ loadables = "atf", "fip";
+ fdt = "fdt";
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-optee.dts b/arch/arm/dts/imx8mm-cl-iot-gate-optee.dts
new file mode 100644
index 0000000..4d0ef46
--- /dev/null
+++ b/arch/arm/dts/imx8mm-cl-iot-gate-optee.dts
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ */
+
+#include "imx8mm-cl-iot-gate.dts"
diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi b/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi
index 3226a24..00927c1 100644
--- a/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi
@@ -217,18 +217,6 @@
};
};
- fip {
- description = "Trusted Firmware FIP";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- load = <0x40310000>;
-
- fip_blob: blob-ext{
- filename = "fip.bin";
- };
- };
-
fdt {
description = "NAME";
type = "flat_dt";
@@ -246,7 +234,7 @@
conf {
description = "NAME";
firmware = "uboot";
- loadables = "atf", "fip";
+ loadables = "atf";
fdt = "fdt";
};
};
diff --git a/arch/arm/dts/imx8mm-kontron-n801x-s-lvds.dts b/arch/arm/dts/imx8mm-kontron-n801x-s-lvds.dts
new file mode 100644
index 0000000..dd1adde
--- /dev/null
+++ b/arch/arm/dts/imx8mm-kontron-n801x-s-lvds.dts
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ */
+
+#include "imx8mm-kontron-n801x-s.dts"
+
+/ {
+ model = "Kontron i.MX8MM N801X S LVDS";
+ compatible = "kontron,imx8mm-n801x-s-lvds", "fsl,imx8mm";
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 50000>; /* period = 5000000 ns => f = 200 Hz */
+ power-supply = <®_vdd_24v>;
+ brightness-levels = <0 100>;
+ num-interpolated-steps = <100>;
+ default-brightness-level = <100>;
+ status = "okay";
+ };
+
+ reg_panel_pwr: regpanel-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "reg_panel_pwr";
+ regulator-always-on;
+ gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_panel_rst: regpanel-rst {
+ compatible = "regulator-fixed";
+ regulator-name = "reg_panel_rst";
+ regulator-always-on;
+ gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_panel_stby: regpanel-stby {
+ compatible = "regulator-fixed";
+ regulator-name = "reg_panel_stby";
+ regulator-always-on;
+ gpio = <&gpio3 21 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_panel_hinv: regpanel-hinv {
+ compatible = "regulator-fixed";
+ regulator-name = "reg_panel_hinv";
+ regulator-always-on;
+ gpio = <&gpio3 24 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_panel_vinv: regpanel-vinv {
+ compatible = "regulator-fixed";
+ regulator-name = "reg_panel_vinv";
+ gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_vdd_24v: regulator-24v {
+ compatible = "regulator-fixed";
+ regulator-name = "reg-vdd-24v";
+ regulator-min-microvolt = <24000000>;
+ regulator-max-microvolt = <24000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ status = "okay";
+ };
+};
+
+&i2c2 {
+ status = "okay";
+
+ gt911@5d {
+ compatible = "goodix,gt928";
+ reg = <0x5d>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_touch>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <22 8>;
+ reset-gpios = <&gpio3 23 0>;
+ irq-gpios = <&gpio3 22 0>;
+ };
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_panel: panelgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x19 /* TFT-PWR - family */
+ MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 /* RESET family */
+ MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 /* STBY family */
+ MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x19 /* HINV panel */
+ MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 /* VINV panel */
+ >;
+ };
+
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x6
+ >;
+ };
+
+ pinctrl_touch: touchgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 /* Touch Interrupt */
+ MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19 /* Touch Reset */
+ >;
+ };
+};
diff --git a/arch/arm/dts/imx8mm-kontron-n801x-s-u-boot.dtsi b/arch/arm/dts/imx8mm-kontron-n801x-s-u-boot.dtsi
new file mode 100644
index 0000000..5e368a6
--- /dev/null
+++ b/arch/arm/dts/imx8mm-kontron-n801x-s-u-boot.dtsi
@@ -0,0 +1,274 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ */
+
+#include "imx8mm-u-boot.dtsi"
+
+/ {
+ aliases {
+ usb0 = &usbotg1;
+ usb1 = &usbotg2;
+ };
+
+ binman: binman {
+ multiple-images;
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ u-boot,dm-spl;
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+};
+
+&fec1 {
+ phy-mode = "rgmii-rxid";
+};
+
+&i2c1 {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&i2c2 {
+ status = "okay";
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_ecspi1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_i2c1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_pmic {
+ u-boot,dm-spl;
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141
+ /* Disable Pullup for SD_VSEL */
+ MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x41
+ >;
+};
+
+&pinctrl_uart3 {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_usdhc1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1_100mhz {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1_200mhz {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+ u-boot,dm-spl;
+};
+
+&pca9450 {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
+ u-boot,dm-spl;
+};
+
+&ecspi1 {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&uart3 {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&usdhc1 {
+ u-boot,dm-spl;
+};
+
+&usdhc2 {
+ u-boot,dm-spl;
+};
+
+&wdog1 {
+ u-boot,dm-spl;
+};
+
+&binman {
+ u-boot-spl-ddr {
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+ align-size = <4>;
+ align = <4>;
+
+ u-boot-spl {
+ align-end = <4>;
+ };
+
+ blob_1: blob-ext@1 {
+ filename = "lpddr4_pmu_train_1d_imem.bin";
+ size = <0x8000>;
+ };
+
+ blob_2: blob-ext@2 {
+ filename = "lpddr4_pmu_train_1d_dmem.bin";
+ size = <0x4000>;
+ };
+
+ blob_3: blob-ext@3 {
+ filename = "lpddr4_pmu_train_2d_imem.bin";
+ size = <0x8000>;
+ };
+
+ blob_4: blob-ext@4 {
+ filename = "lpddr4_pmu_train_2d_dmem.bin";
+ size = <0x4000>;
+ };
+ };
+
+ spl {
+ filename = "spl.bin";
+
+ mkimage {
+ args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000";
+
+ blob {
+ filename = "u-boot-spl-ddr.bin";
+ };
+ };
+ };
+
+ itb {
+ filename = "u-boot.itb";
+
+ fit {
+ description = "Configuration to load ATF before U-Boot";
+ #address-cells = <1>;
+ fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
+
+ images {
+ uboot {
+ description = "U-Boot (64-bit)";
+ type = "standalone";
+ arch = "arm64";
+ compression = "none";
+ load = <CONFIG_SYS_TEXT_BASE>;
+
+ uboot_blob: blob-ext {
+ filename = "u-boot-nodtb.bin";
+ };
+ };
+
+ atf {
+ description = "ARM Trusted Firmware";
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <0x920000>;
+ entry = <0x920000>;
+
+ atf_blob: blob-ext {
+ filename = "bl31.bin";
+ };
+ };
+
+ fdt {
+ description = "NAME";
+ type = "flat_dt";
+ compression = "none";
+
+ uboot_fdt_blob: blob-ext {
+ filename = "u-boot.dtb";
+ };
+ };
+ };
+
+ configurations {
+ default = "conf";
+
+ conf {
+ description = "NAME";
+ firmware = "uboot";
+ loadables = "atf";
+ fdt = "fdt";
+ };
+ };
+ };
+ };
+
+ imx-boot {
+ filename = "flash.bin";
+ pad-byte = <0x00>;
+
+ spl: blob-ext@1 {
+ offset = <0x0>;
+ filename = "spl.bin";
+ };
+
+ uboot: blob-ext@2 {
+ offset = <0x57c00>;
+ filename = "u-boot.itb";
+ };
+ };
+
+ u-boot-update {
+ filename = "firmware-update.itb";
+
+ fit {
+ description = "Configuration for firmware update file";
+
+ images {
+ flash-bin {
+ description = "U-Boot flash image";
+ type = "firmware";
+ os = "u-boot";
+ arch = "arm";
+ compress = "none";
+ load = <0>; /* unused */
+
+ blob {
+ filename = "flash.bin";
+ };
+
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/imx8mm-kontron-n801x-s.dts b/arch/arm/dts/imx8mm-kontron-n801x-s.dts
new file mode 100644
index 0000000..c796d14
--- /dev/null
+++ b/arch/arm/dts/imx8mm-kontron-n801x-s.dts
@@ -0,0 +1,388 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ */
+
+/dts-v1/;
+
+#include "imx8mm-kontron-n801x-som.dtsi"
+#include <dt-bindings/net/mscc-phy-vsc8531.h>
+
+/ {
+ model = "Kontron i.MX8MM N801X S";
+ compatible = "kontron,imx8mm-n801x-s", "kontron,imx8mm-n801x-som", "fsl,imx8mm";
+
+ aliases {
+ ethernet1 = &usbnet;
+ };
+
+ /* fixed crystal dedicated to mcp2515 */
+ osc_can: clock-osc-can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <16000000>;
+ clock-output-names = "osc-can";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_led>;
+
+ led1 {
+ label = "led1";
+ gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led2 {
+ label = "led2";
+ gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
+ };
+
+ led3 {
+ label = "led3";
+ gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
+ };
+
+ led4 {
+ label = "led4";
+ gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
+ };
+
+ led5 {
+ label = "led5";
+ gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
+ };
+
+ led6 {
+ label = "led6";
+ gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ pwm-beeper {
+ compatible = "pwm-beeper";
+ pwms = <&pwm2 0 5000 0>;
+ };
+
+ reg_rst_eth2: regulator-rst-eth2 {
+ compatible = "regulator-fixed";
+ regulator-name = "rst-usb-eth2";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_eth2>;
+ gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ reg_vdd_5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+};
+
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ can0: can@0 {
+ compatible = "microchip,mcp2515";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can>;
+ clocks = <&osc_can>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
+ spi-max-frequency = <10000000>;
+ vdd-supply = <®_vdd_3v3>;
+ xceiver-supply = <®_vdd_5v>;
+ };
+};
+
+&ecspi3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi3>;
+ cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-connection-type = "rgmii-rxid";
+ phy-handle = <ðphy>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy: ethernet-phy@0 {
+ compatible = "ethernet-phy-id0007.0570";
+ reg = <0>;
+ reset-assert-us = <100>;
+ reset-deassert-us = <100>;
+ reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
+ vsc8531,led-0-mode = <VSC8531_LINK_100_1000_ACTIVITY>;
+ vsc8531,led-1-mode = <VSC8531_LINK_ACTIVITY>;
+ vsc8531,led-0-combine-disable;
+ };
+ };
+};
+
+&gpio4 {
+ dsi_mux_sel: dsi_mux_sel {
+ gpio-hog;
+ gpios = <14 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "dsi-mux-sel";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_dsi_sel>;
+ };
+
+ dsi_mux_oe {
+ gpio-hog;
+ gpios = <15 GPIO_ACTIVE_LOW>;
+ output-high;
+ line-name = "dsi-mux-oe";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_dsi_oe>;
+ };
+};
+
+&i2c4 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+
+ rtc@32 {
+ compatible = "epson,rx8900";
+ reg = <0x32>;
+ };
+};
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ linux,rs485-enabled-at-boot-time;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&usbotg1 {
+ dr_mode = "otg";
+ over-current-active-low;
+ status = "okay";
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ disable-over-current;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ usb1@1 {
+ compatible = "usb424,9514";
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usbnet: usbether@1 {
+ compatible = "usb424,ec00";
+ reg = <1>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ };
+ };
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+ vmmc-supply = <®_vdd_3v3>;
+ vqmmc-supply = <®_nvcc_sd>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio>;
+
+ pinctrl_can: cangrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19
+ >;
+ };
+
+ pinctrl_dsi_sel: dsiselgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19
+ >;
+ };
+
+ pinctrl_dsi_oe: dsioegrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19
+ >;
+ };
+
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
+ MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
+ MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
+ MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19
+ >;
+ };
+
+ pinctrl_ecspi3: ecspi3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82
+ MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82
+ MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82
+ MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19
+ >;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
+ MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 /* PHY RST */
+ MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* ETH IRQ */
+ >;
+ };
+
+ pinctrl_gpio_led: gpioledgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
+ MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x19
+ MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x19
+ MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x19
+ MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19
+ MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19
+ MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19
+ >;
+ };
+
+ pinctrl_gpio: gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19
+ MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
+ MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
+ MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19
+ MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
+ MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19
+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19
+ MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140
+ MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140
+ MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140
+ MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140
+ MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140
+ MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140
+ >;
+ };
+
+ pinctrl_usb_eth2: usbeth2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
+ >;
+ };
+};
diff --git a/arch/arm/dts/imx8mm-kontron-n801x-som.dtsi b/arch/arm/dts/imx8mm-kontron-n801x-som.dtsi
new file mode 100644
index 0000000..c3418d2
--- /dev/null
+++ b/arch/arm/dts/imx8mm-kontron-n801x-som.dtsi
@@ -0,0 +1,299 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ */
+
+#include "imx8mm.dtsi"
+
+/ {
+ model = "Kontron i.MX8MM N801X SoM";
+ compatible = "kontron,imx8mm-n801x-som", "fsl,imx8mm";
+
+ memory@40000000 {
+ device_type = "memory";
+ /*
+ * There are multiple SoM flavors with different DDR sizes.
+ * The smallest is 1GB. For larger sizes the bootloader will
+ * update the reg property.
+ */
+ reg = <0x0 0x40000000 0 0x80000000>;
+ };
+
+ chosen {
+ stdout-path = &uart3;
+ };
+};
+
+&A53_0 {
+ cpu-supply = <®_vdd_arm>;
+};
+
+&A53_1 {
+ cpu-supply = <®_vdd_arm>;
+};
+
+&A53_2 {
+ cpu-supply = <®_vdd_arm>;
+};
+
+&A53_3 {
+ cpu-supply = <®_vdd_arm>;
+};
+
+&ddrc {
+ operating-points-v2 = <&ddrc_opp_table>;
+
+ ddrc_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-25M {
+ opp-hz = /bits/ 64 <25000000>;
+ };
+
+ opp-100M {
+ opp-hz = /bits/ 64 <100000000>;
+ };
+
+ opp-750M {
+ opp-hz = /bits/ 64 <750000000>;
+ };
+ };
+};
+
+&ecspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ spi-flash@0 {
+ compatible = "mxicy,mx25r1635f", "jedec,spi-nor";
+ spi-max-frequency = <80000000>;
+ reg = <0>;
+ };
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ pca9450: pmic@25 {
+ compatible = "nxp,pca9450a";
+ reg = <0x25>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+
+ regulators {
+ reg_vdd_soc: BUCK1 {
+ regulator-name = "buck1";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ nxp,dvs-run-voltage = <850000>;
+ nxp,dvs-standby-voltage = <800000>;
+ };
+
+ reg_vdd_arm: BUCK2 {
+ regulator-name = "buck2";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <950000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ nxp,dvs-run-voltage = <950000>;
+ nxp,dvs-standby-voltage = <850000>;
+ };
+
+ reg_vdd_dram: BUCK3 {
+ regulator-name = "buck3";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <950000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_vdd_3v3: BUCK4 {
+ regulator-name = "buck4";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_vdd_1v8: BUCK5 {
+ regulator-name = "buck5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_nvcc_dram: BUCK6 {
+ regulator-name = "buck6";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_nvcc_snvs: LDO1 {
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_vdd_snvs: LDO2 {
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_vdda: LDO3 {
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_vdd_phy: LDO4 {
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_nvcc_sd: LDO5 {
+ regulator-name = "ldo5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+ };
+};
+
+&uart3 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ vmmc-supply = <®_vdd_3v3>;
+ vqmmc-supply = <®_vdd_1v8>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
+ MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
+ MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
+ MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_pmic: pmicgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141
+ MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x141
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
+ MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
+ MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0
+ MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0
+ MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0
+ MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0
+ MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
+ MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
+ MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4
+ MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4
+ MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4
+ MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4
+ MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
+ MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
+ MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6
+ MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6
+ MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6
+ MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6
+ MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
+ MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+ >;
+ };
+};
diff --git a/arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi
index 1a15d6a..7670243 100644
--- a/arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi
@@ -3,59 +3,7 @@
* Copyright 2021 Gateworks Corporation
*/
-#include "imx8mm-u-boot.dtsi"
-
-&gpio1 {
- u-boot,dm-spl;
-};
-
-&gpio2 {
- u-boot,dm-spl;
-};
-
-&gpio3 {
- u-boot,dm-spl;
-};
-
-&gpio4 {
- u-boot,dm-spl;
-};
-
-&gpio5 {
- u-boot,dm-spl;
-};
-
-&uart2 {
- u-boot,dm-spl;
-};
-
-&pinctrl_uart2 {
- u-boot,dm-spl;
-};
-
-&usdhc3 {
- u-boot,dm-spl;
-};
-
-&pinctrl_usdhc3 {
- u-boot,dm-spl;
-};
-
-&i2c1 {
- u-boot,dm-spl;
-};
-
-&pinctrl_i2c1 {
- u-boot,dm-spl;
-};
-
-&i2c2 {
- u-boot,dm-spl;
-};
-
-&pinctrl_i2c2 {
- u-boot,dm-spl;
-};
+#include "imx8mm-venice-u-boot.dtsi"
&fec1 {
phy-reset-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
@@ -63,6 +11,10 @@
phy-reset-post-delay = <1>;
};
+&pinctrl_fec1 {
+ u-boot,dm-spl;
+};
+
&{/soc@0/bus@30800000/i2c@30a20000/pmic@69} {
u-boot,dm-spl;
};
@@ -70,3 +22,7 @@
&{/soc@0/bus@30800000/i2c@30a20000/pmic@69/regulators} {
u-boot,dm-spl;
};
+
+&pinctrl_pmic {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mm-venice-gw700x.dtsi b/arch/arm/dts/imx8mm-venice-gw700x.dtsi
index cc850e7..f182a81 100644
--- a/arch/arm/dts/imx8mm-venice-gw700x.dtsi
+++ b/arch/arm/dts/imx8mm-venice-gw700x.dtsi
@@ -282,65 +282,83 @@
reg = <0x69>;
regulators {
+ /* vdd_0p95: DRAM/GPU/VPU */
buck1 {
- regulator-name = "vdd_0p95";
- regulator-min-microvolt = <805000>;
+ regulator-name = "buck1";
+ regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1000000>;
- regulator-max-microamp = <2500000>;
+ regulator-min-microamp = <3800000>;
+ regulator-max-microamp = <6800000>;
regulator-boot-on;
+ regulator-always-on;
};
+ /* vdd_soc */
buck2 {
- regulator-name = "vdd_soc";
- regulator-min-microvolt = <805000>;
+ regulator-name = "buck2";
+ regulator-min-microvolt = <800000>;
regulator-max-microvolt = <900000>;
- regulator-max-microamp = <1000000>;
+ regulator-min-microamp = <2200000>;
+ regulator-max-microamp = <5200000>;
regulator-boot-on;
+ regulator-always-on;
};
+ /* vdd_arm */
buck3_reg: buck3 {
- regulator-name = "vdd_arm";
- regulator-min-microvolt = <805000>;
+ regulator-name = "buck3";
+ regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1000000>;
- regulator-max-microamp = <2200000>;
- regulator-boot-on;
+ regulator-min-microamp = <3800000>;
+ regulator-max-microamp = <6800000>;
+ regulator-always-on;
};
+ /* vdd_1p8 */
buck4 {
- regulator-name = "vdd_1p8";
+ regulator-name = "buck4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
- regulator-max-microamp = <500000>;
+ regulator-min-microamp = <2200000>;
+ regulator-max-microamp = <5200000>;
regulator-boot-on;
+ regulator-always-on;
};
+ /* nvcc_snvs_1p8 */
ldo1 {
- regulator-name = "nvcc_snvs_1p8";
+ regulator-name = "ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
- regulator-max-microamp = <300000>;
regulator-boot-on;
+ regulator-always-on;
};
+ /* vdd_snvs_0p8 */
ldo2 {
- regulator-name = "vdd_snvs_0p8";
+ regulator-name = "ldo2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-boot-on;
+ regulator-always-on;
};
+ /* vdd_0p9 */
ldo3 {
- regulator-name = "vdd_0p95";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <800000>;
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
regulator-boot-on;
+ regulator-always-on;
};
+ /* vdd_1p8 */
ldo4 {
- regulator-name = "vdd_1p8";
+ regulator-name = "ldo4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
+ regulator-always-on;
};
};
};
diff --git a/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi
index a5adf27..a801ee1 100644
--- a/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi
@@ -3,67 +3,7 @@
* Copyright 2020 Gateworks Corporation
*/
-#include "imx8mm-u-boot.dtsi"
-
-&gpio1 {
- u-boot,dm-spl;
-};
-
-&gpio2 {
- u-boot,dm-spl;
-};
-
-&gpio3 {
- u-boot,dm-spl;
-};
-
-&gpio4 {
- u-boot,dm-spl;
-};
-
-&gpio5 {
- u-boot,dm-spl;
-};
-
-&uart2 {
- u-boot,dm-spl;
-};
-
-&pinctrl_uart2 {
- u-boot,dm-spl;
-};
-
-&usdhc2 {
- u-boot,dm-spl;
-};
-
-&pinctrl_usdhc2 {
- u-boot,dm-spl;
-};
-
-&usdhc3 {
- u-boot,dm-spl;
-};
-
-&pinctrl_usdhc3 {
- u-boot,dm-spl;
-};
-
-&i2c1 {
- u-boot,dm-spl;
-};
-
-&pinctrl_i2c1 {
- u-boot,dm-spl;
-};
-
-&i2c2 {
- u-boot,dm-spl;
-};
-
-&pinctrl_i2c2 {
- u-boot,dm-spl;
-};
+#include "imx8mm-venice-u-boot.dtsi"
&fec1 {
phy-reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
@@ -71,6 +11,10 @@
phy-reset-post-delay = <1>;
};
+&pinctrl_fec1 {
+ u-boot,dm-spl;
+};
+
&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mm-venice-gw7901.dts b/arch/arm/dts/imx8mm-venice-gw7901.dts
index 124e1e4..d5cdbb7 100644
--- a/arch/arm/dts/imx8mm-venice-gw7901.dts
+++ b/arch/arm/dts/imx8mm-venice-gw7901.dts
@@ -1041,15 +1041,3 @@
>;
};
};
-
-&cpu_alert0 {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "passive";
-};
-
-&cpu_crit0 {
- temperature = <105000>;
- hysteresis = <2000>;
- type = "critical";
-};
diff --git a/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi
index 361ddaa..d0e5d6c 100644
--- a/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi
@@ -3,59 +3,7 @@
* Copyright 2021 Gateworks Corporation
*/
-#include "imx8mm-u-boot.dtsi"
-
-&gpio1 {
- u-boot,dm-spl;
-};
-
-&gpio2 {
- u-boot,dm-spl;
-};
-
-&gpio3 {
- u-boot,dm-spl;
-};
-
-&gpio4 {
- u-boot,dm-spl;
-};
-
-&gpio5 {
- u-boot,dm-spl;
-};
-
-&uart2 {
- u-boot,dm-spl;
-};
-
-&pinctrl_uart2 {
- u-boot,dm-spl;
-};
-
-&usdhc3 {
- u-boot,dm-spl;
-};
-
-&pinctrl_usdhc3 {
- u-boot,dm-spl;
-};
-
-&i2c1 {
- u-boot,dm-spl;
-};
-
-&pinctrl_i2c1 {
- u-boot,dm-spl;
-};
-
-&i2c2 {
- u-boot,dm-spl;
-};
-
-&pinctrl_i2c2 {
- u-boot,dm-spl;
-};
+#include "imx8mm-venice-u-boot.dtsi"
&fec1 {
phy-reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/dts/imx8mm-venice-gw7902.dts b/arch/arm/dts/imx8mm-venice-gw7902.dts
index 2948821..07e436b 100644
--- a/arch/arm/dts/imx8mm-venice-gw7902.dts
+++ b/arch/arm/dts/imx8mm-venice-gw7902.dts
@@ -913,15 +913,3 @@
>;
};
};
-
-&cpu_alert0 {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "passive";
-};
-
-&cpu_crit0 {
- temperature = <105000>;
- hysteresis = <2000>;
- type = "critical";
-};
diff --git a/arch/arm/dts/imx8mm-verdin.dts b/arch/arm/dts/imx8mm-verdin.dts
index fb0756d..ac2a4b6 100644
--- a/arch/arm/dts/imx8mm-verdin.dts
+++ b/arch/arm/dts/imx8mm-verdin.dts
@@ -160,7 +160,7 @@
&fec1 {
fsl,magic-packet;
phy-handle = <ðphy0>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
phy-supply = <®_ethphy>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_fec1>;
diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi
index d61346d..afb3995 100644
--- a/arch/arm/dts/imx8mp-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-u-boot.dtsi
@@ -79,7 +79,9 @@
};
};
- flash {
+ spl {
+ filename = "spl.bin";
+
mkimage {
args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x920000";
@@ -146,4 +148,19 @@
};
};
};
+
+ imx-boot {
+ filename = "flash.bin";
+ pad-byte = <0x00>;
+
+ spl: blob-ext@1 {
+ filename = "spl.bin";
+ offset = <0x0>;
+ };
+
+ uboot: blob-ext@2 {
+ filename = "u-boot.itb";
+ offset = <0x58000>;
+ };
+ };
};
diff --git a/arch/arm/dts/k3-am65-iot2050-common-pg2-u-boot.dtsi b/arch/arm/dts/k3-am65-iot2050-common-pg2-u-boot.dtsi
new file mode 100644
index 0000000..64dddce
--- /dev/null
+++ b/arch/arm/dts/k3-am65-iot2050-common-pg2-u-boot.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) Siemens AG, 2018-2021
+ *
+ * Authors:
+ * Chao Zeng <chao.zeng@siemens.com>
+ *
+ * U-Boot bits of the IOT2050 Advanced PG2 variants
+ * (downgrade of usb0 to USB 2.0 mode)
+ */
+
+&serdes0 {
+ status = "disabled";
+};
+
+&dwc3_0 {
+ assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
+ <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
+ /delete-property/ phys;
+ /delete-property/ phy-names;
+};
+
+&usb0 {
+ maximum-speed = "high-speed";
+ /delete-property/ snps,dis-u1-entry-quirk;
+ /delete-property/ snps,dis-u2-entry-quirk;
+};
diff --git a/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi b/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi
index c25bce7..e7e0ca4 100644
--- a/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi
+++ b/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi
@@ -44,8 +44,10 @@
phy-names = "usb3-phy";
};
-&usb0_phy {
+&usb0 {
maximum-speed = "super-speed";
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
};
+
+#include "k3-am65-iot2050-common-pg2-u-boot.dtsi"
diff --git a/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi b/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi
index 88c36fc..286e25f 100644
--- a/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi
+++ b/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi
@@ -35,7 +35,7 @@
&cbass_main {
u-boot,dm-spl;
- main-navss {
+ main_navss: bus@30800000 {
u-boot,dm-spl;
};
};
diff --git a/arch/arm/dts/px30.dtsi b/arch/arm/dts/px30.dtsi
index aaa8ae2..ef70648 100644
--- a/arch/arm/dts/px30.dtsi
+++ b/arch/arm/dts/px30.dtsi
@@ -967,7 +967,7 @@
clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
clock-names = "clk_sfc", "hclk_sfc";
pinctrl-names = "default";
- pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus4>;
+ pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
power-domains = <&power PX30_PD_MMC_NAND>;
status = "disabled";
};
@@ -1953,7 +1953,7 @@
<1 RK_PA1 3 &pcfg_pull_none>;
};
- sfc_cs: sfc-cs {
+ sfc_cs0: sfc-cs0 {
rockchip,pins =
<1 RK_PA4 3 &pcfg_pull_none>;
};
diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
index 741e8dd..bffaa3e 100644
--- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
+++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
@@ -18,8 +18,18 @@
};
};
+/* U-Boot clk driver for px30 cannot set GPU_CLK */
&cru {
u-boot,dm-pre-reloc;
+ assigned-clocks = <&cru PLL_NPLL>,
+ <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
+ <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
+ <&cru PCLK_BUS_PRE>, <&cru PLL_CPLL>;
+
+ assigned-clock-rates = <1188000000>,
+ <200000000>, <200000000>,
+ <150000000>, <150000000>,
+ <100000000>, <17000000>;
};
&dmc {
@@ -70,7 +80,7 @@
u-boot,dm-pre-reloc;
};
-&spi_flash {
+&{/sfc@ff3a0000/flash@0} {
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/rk3326-odroid-go2.dts b/arch/arm/dts/rk3326-odroid-go2.dts
index 6f91f50..4e3dcee 100644
--- a/arch/arm/dts/rk3326-odroid-go2.dts
+++ b/arch/arm/dts/rk3326-odroid-go2.dts
@@ -618,18 +618,18 @@
};
&sfc {
+ pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>;
+ pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus2>;
status = "okay";
- spi_flash: xt25f128b@0 {
+ flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <108000000>;
spi-rx-bus-width = <2>;
- spi-tx-bus-width = <2>;
+ spi-tx-bus-width = <1>;
};
};
diff --git a/arch/arm/dts/sama5d2.dtsi b/arch/arm/dts/sama5d2.dtsi
index d8a125b..038cd73 100644
--- a/arch/arm/dts/sama5d2.dtsi
+++ b/arch/arm/dts/sama5d2.dtsi
@@ -671,6 +671,14 @@
status = "disabled";
};
+ pwm0: pwm@f802c000 {
+ compatible = "atmel,sama5d2-pwm";
+ reg = <0xf802c000 0x4000>;
+ clocks = <&pwm_clk>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
rstc@f8048000 {
compatible = "atmel,sama5d3-rstc";
reg = <0xf8048000 0x10>;
diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
index ba9b3cd..78facde 100644
--- a/arch/arm/dts/stm32f746.dtsi
+++ b/arch/arm/dts/stm32f746.dtsi
@@ -313,6 +313,7 @@
clocks = <&rcc 1 CLK_I2C1>;
#address-cells = <1>;
#size-cells = <0>;
+ i2c-analog-filter;
status = "disabled";
};
@@ -325,6 +326,7 @@
clocks = <&rcc 1 CLK_I2C2>;
#address-cells = <1>;
#size-cells = <0>;
+ i2c-analog-filter;
status = "disabled";
};
@@ -337,6 +339,7 @@
clocks = <&rcc 1 CLK_I2C3>;
#address-cells = <1>;
#size-cells = <0>;
+ i2c-analog-filter;
status = "disabled";
};
@@ -349,6 +352,7 @@
clocks = <&rcc 1 CLK_I2C4>;
#address-cells = <1>;
#size-cells = <0>;
+ i2c-analog-filter;
status = "disabled";
};
diff --git a/arch/arm/dts/stm32h743.dtsi b/arch/arm/dts/stm32h743.dtsi
index ed68575..dbfebf0 100644
--- a/arch/arm/dts/stm32h743.dtsi
+++ b/arch/arm/dts/stm32h743.dtsi
@@ -124,6 +124,7 @@
<32>;
resets = <&rcc STM32H7_APB1L_RESET(I2C1)>;
clocks = <&rcc I2C1_CK>;
+ i2c-analog-filter;
status = "disabled";
};
@@ -136,6 +137,7 @@
<34>;
resets = <&rcc STM32H7_APB1L_RESET(I2C2)>;
clocks = <&rcc I2C2_CK>;
+ i2c-analog-filter;
status = "disabled";
};
@@ -148,6 +150,7 @@
<73>;
resets = <&rcc STM32H7_APB1L_RESET(I2C3)>;
clocks = <&rcc I2C3_CK>;
+ i2c-analog-filter;
status = "disabled";
};
@@ -395,6 +398,7 @@
<96>;
resets = <&rcc STM32H7_APB4_RESET(I2C4)>;
clocks = <&rcc I2C4_CK>;
+ i2c-analog-filter;
status = "disabled";
};
diff --git a/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts b/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts
new file mode 100644
index 0000000..55bcdf8
--- /dev/null
+++ b/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts
@@ -0,0 +1,195 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2021 Chukun Pan <amadeus@jmu.edu.cn>
+ *
+ * Based on sun50i-h5-nanopi-neo-plus2.dts, which is:
+ * Copyright (C) 2017 Antony Antony <antony@phenome.org>
+ * Copyright (C) 2016 ARM Ltd.
+ */
+
+/dts-v1/;
+#include "sun50i-h5.dtsi"
+#include "sun50i-h5-cpu-opp.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "FriendlyARM NanoPi R1S H5";
+ compatible = "friendlyarm,nanopi-r1s-h5", "allwinner,sun50i-h5";
+
+ aliases {
+ ethernet0 = &emac;
+ ethernet1 = &rtl8189etv;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ function = LED_FUNCTION_LAN;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-1 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led-2 {
+ function = LED_FUNCTION_WAN;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ r-gpio-keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_usb0_vbus: usb0-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
+ status = "okay";
+ };
+
+ vdd_cpux: gpio-regulator {
+ compatible = "regulator-gpio";
+ regulator-name = "vdd-cpux";
+ regulator-type = "voltage";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-ramp-delay = <50>; /* 4ms */
+ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0x1>;
+ states = <1100000 0x0>, <1300000 0x1>;
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
+ post-power-on-delay-ms = <200>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpux>;
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <®_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+};
+
+&external_mdio {
+ ext_rgmii_phy: ethernet-phy@7 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+
+ eeprom@51 {
+ compatible = "microchip,24c02";
+ reg = <0x51>;
+ pagesize = <16>;
+ };
+};
+
+&mmc0 {
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <®_vcc3v3>;
+ vqmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ rtl8189etv: sdio_wifi@1 {
+ reg = <1>;
+ };
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pa_pins>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy {
+ /* USB Type-A port's VBUS is always on */
+ usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
+ usb0_vbus-supply = <®_usb0_vbus>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/vf.dtsi b/arch/arm/dts/vf.dtsi
index 5f69d0f..5ba13dc 100644
--- a/arch/arm/dts/vf.dtsi
+++ b/arch/arm/dts/vf.dtsi
@@ -34,7 +34,7 @@
compatible = "simple-bus";
ranges;
- aips0: aips-bus@40000000 {
+ aips0: bus@40000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -158,7 +158,7 @@
};
};
- aips1: aips-bus@40080000 {
+ aips1: bus@40080000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h
index 5d77590..79e3b8c 100644
--- a/arch/arm/include/asm/arch-am33xx/clock.h
+++ b/arch/arm/include/asm/arch-am33xx/clock.h
@@ -78,6 +78,18 @@
#define CM_CLKSEL_DPLL_N_SHIFT 0
#define CM_CLKSEL_DPLL_N_MASK 0x7F
+/* CM_SSC_DELTAM_DPLL */
+#define CM_SSC_DELTAM_DPLL_FRAC_SHIFT 0
+#define CM_SSC_DELTAM_DPLL_FRAC_MASK GENMASK(17, 0)
+#define CM_SSC_DELTAM_DPLL_INT_SHIFT 18
+#define CM_SSC_DELTAM_DPLL_INT_MASK GENMASK(19, 18)
+
+/* CM_SSC_MODFREQ_DPLL */
+#define CM_SSC_MODFREQ_DPLL_MANT_SHIFT 0
+#define CM_SSC_MODFREQ_DPLL_MANT_MASK GENMASK(6, 0)
+#define CM_SSC_MODFREQ_DPLL_EXP_SHIFT 7
+#define CM_SSC_MODFREQ_DPLL_EXP_MASK GENMASK(10, 8)
+
struct dpll_params {
u32 m;
u32 n;
diff --git a/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h b/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h
index ea2f113..df392a2 100644
--- a/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h
+++ b/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h
@@ -11,7 +11,7 @@
#include <asm/arch/sys_proto.h>
-/* CONFIG_REG_0 */
+/* CFG REG_0 */
#define CFG_REG_0_OFFSET 0xC
#define CFG_REG_ROM_READ_SHIFT 1
#define CFG_REG_ROM_READ_MASK (1 << 1)
@@ -22,18 +22,18 @@
#define CFG_REG_ROM_READ_START (1 << 1)
#define CFG_REG_ROM_READ_END (0 << 1)
-/* CONFIG_REG_2 */
+/* CFG REG_2 */
#define CFG_REG_2_OFFSET 0x14
#define CFG_REG_REFCLK_PERIOD_SHIFT 0
#define CFG_REG_REFCLK_PERIOD_MASK (0xFFFF << 0)
#define CFG_REG_REFCLK_PERIOD 0x2EF
-/* CONFIG_REG_8 */
+/* CFG REG_8 */
#define CFG_REG_8_OFFSET 0x2C
#define CFG_IODELAY_UNLOCK_KEY 0x0000AAAA
#define CFG_IODELAY_LOCK_KEY 0x0000AAAB
-/* CONFIG_REG_3/4 */
+/* CFG REG_3/4 */
#define CFG_REG_3_OFFSET 0x18
#define CFG_REG_4_OFFSET 0x1C
#define CFG_REG_DLY_CNT_SHIFT 16
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h
index 6c59033..399f19a 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h
@@ -14,7 +14,7 @@
#define APLL_HZ (816 * MHz)
#define GPLL_HZ (1188 * MHz)
#define CPLL_HZ (1000 * MHz)
-#define PPLL_HZ (100 * MHz)
+#define PPLL_HZ (200 * MHz)
/* RK3568 pll id */
enum rk3568_pll_id {
diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h
index cd27472..f1d5667 100644
--- a/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h
+++ b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h
@@ -36,7 +36,7 @@
#define GPT_FREE_RUNNING 0xFFFF
/* Timer, HZ specific defines */
-#define CONFIG_STV0991_HZ 1000
-#define CONFIG_STV0991_HZ_CLOCK (27*1000*1000)/GPT_PRESCALER_128
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_HZ_CLOCK ((27 * 1000 * 1000) / GPT_PRESCALER_128)
#endif
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index 2969a53..f3ab1ae 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -93,20 +93,10 @@
#define GPIO_PULL_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1)
/* GPIO bank sizes */
-#define SUNXI_GPIO_A_NR 32
-#define SUNXI_GPIO_B_NR 32
-#define SUNXI_GPIO_C_NR 32
-#define SUNXI_GPIO_D_NR 32
-#define SUNXI_GPIO_E_NR 32
-#define SUNXI_GPIO_F_NR 32
-#define SUNXI_GPIO_G_NR 32
-#define SUNXI_GPIO_H_NR 32
-#define SUNXI_GPIO_I_NR 32
-#define SUNXI_GPIO_L_NR 32
-#define SUNXI_GPIO_M_NR 32
+#define SUNXI_GPIOS_PER_BANK 32
#define SUNXI_GPIO_NEXT(__gpio) \
- ((__gpio##_START) + (__gpio##_NR) + 0)
+ ((__gpio##_START) + SUNXI_GPIOS_PER_BANK)
enum sunxi_gpio_number {
SUNXI_GPIO_A_START = 0,
@@ -148,8 +138,6 @@
#define SUNXI_GPA_EMAC 2
#define SUN6I_GPA_GMAC 2
#define SUN7I_GPA_GMAC 5
-#define SUN6I_GPA_SDC2 5
-#define SUN6I_GPA_SDC3 4
#define SUN8I_H3_GPA_UART0 2
#define SUN4I_GPB_PWM 2
@@ -173,12 +161,10 @@
#define SUN6I_GPC_SDC3 4
#define SUN50I_GPC_SPI0 4
-#define SUN8I_GPD_SDC1 3
#define SUNXI_GPD_LCD0 2
#define SUNXI_GPD_LVDS0 3
#define SUNXI_GPD_PWM 2
-#define SUN5I_GPE_SDC2 3
#define SUN8I_GPE_TWI2 3
#define SUN50I_GPE_TWI2 3
@@ -242,9 +228,7 @@
int sunxi_gpio_get_cfgpin(u32 pin);
int sunxi_gpio_set_drv(u32 pin, u32 val);
int sunxi_gpio_set_pull(u32 pin, u32 val);
-int sunxi_name_to_gpio_bank(const char *name);
int sunxi_name_to_gpio(const char *name);
-#define name_to_gpio(name) sunxi_name_to_gpio(name)
#if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO
int axp_gpio_init(void);
diff --git a/arch/arm/include/asm/arch-tegra/board.h b/arch/arm/include/asm/arch-tegra/board.h
index 24d0db8..cd4d0ee 100644
--- a/arch/arm/include/asm/arch-tegra/board.h
+++ b/arch/arm/include/asm/arch-tegra/board.h
@@ -30,4 +30,14 @@
void pin_mux_mmc(void); /* overridable mmc pinmux setup */
void pin_mux_display(void); /* overridable DISPLAY pinmux setup */
+/*
+ * Helpers for various standard DT update mechanisms.
+ */
+
+#if defined(CONFIG_ARM64)
+void ft_mac_address_setup(void *fdt);
+void ft_carveout_setup(void *fdt, const char *const *nodes,
+ unsigned int count);
+#endif
+
#endif
diff --git a/arch/arm/include/asm/mach-imx/iomux-v3.h b/arch/arm/include/asm/mach-imx/iomux-v3.h
index 1de7093..9330a32 100644
--- a/arch/arm/include/asm/mach-imx/iomux-v3.h
+++ b/arch/arm/include/asm/mach-imx/iomux-v3.h
@@ -87,15 +87,6 @@
#define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \
MUX_MODE_SHIFT)
#ifdef CONFIG_IMX8M
-#define PAD_CTL_DSE0 (0x0 << 0)
-#define PAD_CTL_DSE1 (0x1 << 0)
-#define PAD_CTL_DSE2 (0x2 << 0)
-#define PAD_CTL_DSE3 (0x3 << 0)
-#define PAD_CTL_DSE4 (0x4 << 0)
-#define PAD_CTL_DSE5 (0x5 << 0)
-#define PAD_CTL_DSE6 (0x6 << 0)
-#define PAD_CTL_DSE7 (0x7 << 0)
-
#define PAD_CTL_FSEL0 (0x0 << 3)
#define PAD_CTL_FSEL1 (0x1 << 3)
#define PAD_CTL_FSEL2 (0x2 << 3)
@@ -105,8 +96,20 @@
#define PAD_CTL_PUE (0x1 << 6)
#define PAD_CTL_HYS (0x1 << 7)
#if defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
+#define PAD_CTL_DSE1 (0x0 << 1)
+#define PAD_CTL_DSE2 (0x2 << 1)
+#define PAD_CTL_DSE4 (0x1 << 1)
+#define PAD_CTL_DSE6 (0x3 << 1)
#define PAD_CTL_PE (0x1 << 8)
#else
+#define PAD_CTL_DSE0 (0x0 << 0)
+#define PAD_CTL_DSE1 (0x1 << 0)
+#define PAD_CTL_DSE2 (0x2 << 0)
+#define PAD_CTL_DSE3 (0x3 << 0)
+#define PAD_CTL_DSE4 (0x4 << 0)
+#define PAD_CTL_DSE5 (0x5 << 0)
+#define PAD_CTL_DSE6 (0x6 << 0)
+#define PAD_CTL_DSE7 (0x7 << 0)
#define PAD_CTL_LVTTL (0x1 << 8)
#endif
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index dd6a693..a59a5e6 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -199,7 +199,7 @@
{
char *commandline = env_get("bootargs");
- if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
+ if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) {
#ifdef CONFIG_OF_LIBFDT
debug("using: FDT\n");
if (image_setup_linux(images)) {
@@ -356,7 +356,7 @@
bootstage_mark(BOOTSTAGE_ID_RUN_OS);
announce_and_cleanup(fake);
- if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len)
+ if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len)
r2 = (unsigned long)images->ft_addr;
else
r2 = gd->bd->bi_boot_params;
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index dd4f027..9aa1d84 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -48,7 +48,7 @@
config IMX_HAB
bool "Support i.MX HAB features"
- depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5 || ARCH_IMX8M
+ depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5 || ARCH_IMX8M || ARCH_MX7ULP
select FSL_CAAM if HAS_CAAM
imply CMD_DEKBLOB if HAS_CAAM
help
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 63e28c6..bfff79f 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -114,8 +114,7 @@
DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o u-boot-dtb.cfgout $(srctree)/$(IMX_CONFIG); if [ -f u-boot-dtb.cfgout ]; then $(CNTR_DEPFILES) u-boot-dtb.cfgout; echo $$?; fi)
else ifeq ($(CONFIG_ARCH_IMX8M), y)
IMAGE_TYPE := imx8mimage
-IMX8M_DEPFILES := $(srctree)/tools/imx8m_image.sh
-DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o spl/u-boot-spl.cfgout $(srctree)/$(IMX_CONFIG);if [ -f spl/u-boot-spl.cfgout ]; then $(IMX8M_DEPFILES) spl/u-boot-spl.cfgout 0; echo $$?; fi)
+DEPFILE_EXISTS := 0
else
IMAGE_TYPE := imximage
DEPFILE_EXISTS := 0
@@ -150,16 +149,18 @@
ifdef CONFIG_ARM64
ifeq ($(CONFIG_ARCH_IMX8M), y)
-SPL:
+
+SPL: spl/u-boot-spl.bin spl/u-boot-spl.cfgout FORCE
MKIMAGEFLAGS_flash.bin = -n spl/u-boot-spl.cfgout \
-T $(IMAGE_TYPE) -e $(CONFIG_SPL_TEXT_BASE)
flash.bin: MKIMAGEOUTPUT = flash.log
+spl/u-boot-spl.cfgout: $(IMX_CONFIG) FORCE
+ $(Q)mkdir -p $(dir $@)
+ $(call if_changed_dep,cpp_cfg)
+
spl/u-boot-spl-ddr.bin: spl/u-boot-spl.bin spl/u-boot-spl.cfgout FORCE
-ifeq ($(DEPFILE_EXISTS),0)
- $(IMX8M_DEPFILES) spl/u-boot-spl.cfgout 1
-endif
flash.bin: spl/u-boot-spl-ddr.bin u-boot.itb FORCE
$(call if_changed,mkimage)
diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c
index cc39e6b..55317ab 100644
--- a/arch/arm/mach-imx/hab.c
+++ b/arch/arm/mach-imx/hab.c
@@ -591,7 +591,7 @@
return (image_get_image_size((image_header_t *)img_addr)
+ 0x1000 - 1) & ~(0x1000 - 1);
#endif
-#if IMAGE_ENABLE_FIT
+#if CONFIG_IS_ENABLED(FIT)
case IMAGE_FORMAT_FIT:
return (fit_get_size(buf) + 0x1000 - 1) & ~(0x1000 - 1);
#endif
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index ccaf106..41088a2 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -75,6 +75,13 @@
select SUPPORT_SPL
select IMX8M_LPDDR4
+config TARGET_KONTRON_MX8MM
+ bool "Kontron Electronics N80xx"
+ select BINMAN
+ select IMX8MM
+ select SUPPORT_SPL
+ select IMX8M_LPDDR4
+
config TARGET_IMX8MN_EVK
bool "imx8mn LPDDR4 EVK board"
select BINMAN
@@ -138,6 +145,13 @@
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
+
+config TARGET_IMX8MM_CL_IOT_GATE_OPTEE
+ bool "CompuLab iot-gate-imx8 with optee support"
+ select BINMAN
+ select IMX8MM
+ select SUPPORT_SPL
+ select IMX8M_LPDDR4
endchoice
source "board/beacon/imx8mm/Kconfig"
@@ -150,6 +164,7 @@
source "board/freescale/imx8mp_evk/Kconfig"
source "board/gateworks/venice/Kconfig"
source "board/google/imx8mq_phanbell/Kconfig"
+source "board/kontron/sl-mx8mm/Kconfig"
source "board/phytec/phycore_imx8mm/Kconfig"
source "board/phytec/phycore_imx8mp/Kconfig"
source "board/ronetix/imx8mq-cm/Kconfig"
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index f2ddc83..8635087 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -298,16 +298,26 @@
ulong board_get_usable_ram_top(ulong total_size)
{
+ ulong top_addr = PHYS_SDRAM + gd->ram_size;
+
/*
* Some IPs have their accessible address space restricted by
* the interconnect. Let's make sure U-Boot only ever uses the
* space below the 4G address boundary (which is 3GiB big),
* even when the effective available memory is bigger.
*/
+ if (top_addr > 0x80000000)
+ top_addr = 0x80000000;
+
+ /*
+ * rom_pointer[0] stores the TEE memory start address.
+ * rom_pointer[1] stores the size TEE uses.
+ * We need to reserve the memory region for TEE.
+ */
- if (PHYS_SDRAM + gd->ram_size > 0x80000000)
- return 0x80000000;
+ if (rom_pointer[0] && rom_pointer[1] && top_addr > rom_pointer[0])
+ top_addr = rom_pointer[0];
- return PHYS_SDRAM + gd->ram_size;
+ return top_addr;
}
static u32 get_cpu_variant_type(u32 type)
diff --git a/arch/arm/mach-imx/mkimage_fit_atf.sh b/arch/arm/mach-imx/mkimage_fit_atf.sh
deleted file mode 100755
index 2a17968..0000000
--- a/arch/arm/mach-imx/mkimage_fit_atf.sh
+++ /dev/null
@@ -1,143 +0,0 @@
-#!/bin/sh
-# SPDX-License-Identifier: GPL-2.0+
-#
-# script to generate FIT image source for i.MX8MQ boards with
-# ARM Trusted Firmware and multiple device trees (given on the command line)
-#
-# usage: $0 <dt_name> [<dt_name> [<dt_name] ...]
-
-[ -z "$BL31" ] && BL31="bl31.bin"
-[ -z "$TEE_LOAD_ADDR" ] && TEE_LOAD_ADDR="0xfe000000"
-[ -z "$ATF_LOAD_ADDR" ] && ATF_LOAD_ADDR="0x00910000"
-[ -z "$BL33_LOAD_ADDR" ] && BL33_LOAD_ADDR="0x40200000"
-
-if [ ! -f $BL31 ]; then
- echo "ERROR: BL31 file $BL31 NOT found" >&2
- exit 0
-else
- echo "$BL31 size: " >&2
- stat -c %s $BL31 >&2
-fi
-
-BL32="tee.bin"
-
-if [ ! -f $BL32 ]; then
- BL32=/dev/null
-else
- echo "Building with TEE support, make sure your $BL31 is compiled with spd. If you do not want tee, please delete $BL31" >&2
- echo "$BL32 size: " >&2
- stat -c %s $BL32 >&2
-fi
-
-BL33="u-boot-nodtb.bin"
-
-if [ ! -f $BL33 ]; then
- echo "ERROR: $BL33 file NOT found" >&2
- exit 0
-else
- echo "u-boot-nodtb.bin size: " >&2
- stat -c %s u-boot-nodtb.bin >&2
-fi
-
-for dtname in $*
-do
- echo "$dtname size: " >&2
- stat -c %s $dtname >&2
-done
-
-
-cat << __HEADER_EOF
-/dts-v1/;
-
-/ {
- description = "Configuration to load ATF before U-Boot";
-
- images {
- uboot@1 {
- description = "U-Boot (64-bit)";
- os = "u-boot";
- data = /incbin/("$BL33");
- type = "standalone";
- arch = "arm64";
- compression = "none";
- load = <$BL33_LOAD_ADDR>;
- };
-__HEADER_EOF
-
-cnt=1
-for dtname in $*
-do
- cat << __FDT_IMAGE_EOF
- fdt@$cnt {
- description = "$(basename $dtname .dtb)";
- data = /incbin/("$dtname");
- type = "flat_dt";
- compression = "none";
- };
-__FDT_IMAGE_EOF
-cnt=$((cnt+1))
-done
-
-cat << __HEADER_EOF
- atf@1 {
- description = "ARM Trusted Firmware";
- os = "arm-trusted-firmware";
- data = /incbin/("$BL31");
- type = "firmware";
- arch = "arm64";
- compression = "none";
- load = <$ATF_LOAD_ADDR>;
- entry = <$ATF_LOAD_ADDR>;
- };
-__HEADER_EOF
-
-if [ -f $BL32 ]; then
-cat << __HEADER_EOF
- tee@1 {
- description = "TEE firmware";
- data = /incbin/("$BL32");
- type = "firmware";
- arch = "arm64";
- compression = "none";
- load = <$TEE_LOAD_ADDR>;
- entry = <$TEE_LOAD_ADDR>;
- };
-__HEADER_EOF
-fi
-
-cat << __CONF_HEADER_EOF
- };
- configurations {
- default = "config@1";
-
-__CONF_HEADER_EOF
-
-cnt=1
-for dtname in $*
-do
-if [ -f $BL32 ]; then
-cat << __CONF_SECTION_EOF
- config@$cnt {
- description = "$(basename $dtname .dtb)";
- firmware = "uboot@1";
- loadables = "atf@1", "tee@1";
- fdt = "fdt@$cnt";
- };
-__CONF_SECTION_EOF
-else
-cat << __CONF_SECTION1_EOF
- config@$cnt {
- description = "$(basename $dtname .dtb)";
- firmware = "uboot@1";
- loadables = "atf@1";
- fdt = "fdt@$cnt";
- };
-__CONF_SECTION1_EOF
-fi
-cnt=$((cnt+1))
-done
-
-cat << __ITS_EOF
- };
-};
-__ITS_EOF
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index ee73006..b4c8511 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -230,6 +230,15 @@
imply CMD_SATA
imply CMD_SPL
+config TARGET_KONTRON_MX6UL
+ bool "Kontron Electronics SL/BL i.MX6UL/ULL (N63xx/N64xx)"
+ depends on MX6UL
+ select BINMAN
+ select DM
+ select DM_THERMAL
+ select SUPPORT_SPL
+ imply CMD_DM
+
config TARGET_KOSAGI_NOVENA
bool "Kosagi Novena"
select BOARD_LATE_INIT
@@ -668,6 +677,7 @@
source "board/phytec/pcm058/Kconfig"
source "board/phytec/pcl063/Kconfig"
source "board/gateworks/gw_ventana/Kconfig"
+source "board/kontron/sl-mx6ul/Kconfig"
source "board/kosagi/novena/Kconfig"
source "board/softing/vining_2000/Kconfig"
source "board/liebherr/display5/Kconfig"
diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c
index 320f24d..7f097d6 100644
--- a/arch/arm/mach-imx/mx7ulp/soc.c
+++ b/arch/arm/mach-imx/mx7ulp/soc.c
@@ -93,14 +93,31 @@
static void disable_wdog(u32 wdog_base)
{
- writel(UNLOCK_WORD0, (wdog_base + 0x04));
- writel(UNLOCK_WORD1, (wdog_base + 0x04));
- writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */
- writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */
- writel(0x120, (wdog_base + 0x00)); /* Disable it and set update */
+ u32 val_cs = readl(wdog_base + 0x00);
+
+ if (!(val_cs & 0x80))
+ return;
+
+ dmb();
+ __raw_writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */
+ __raw_writel(REFRESH_WORD1, (wdog_base + 0x04));
+ dmb();
+
+ if (!(val_cs & 800)) {
+ dmb();
+ __raw_writel(UNLOCK_WORD0, (wdog_base + 0x04));
+ __raw_writel(UNLOCK_WORD1, (wdog_base + 0x04));
+ dmb();
+
+ while (!(readl(wdog_base + 0x00) & 0x800));
+ }
+ dmb();
+ __raw_writel(0x0, wdog_base + 0x0C); /* Set WIN to 0 */
+ __raw_writel(0x400, wdog_base + 0x08); /* Set timeout to default 0x400 */
+ __raw_writel(0x120, wdog_base + 0x00); /* Disable it and set update */
+ dmb();
- writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */
- writel(REFRESH_WORD1, (wdog_base + 0x04));
+ while (!(readl(wdog_base + 0x00) & 0x400));
}
void init_wdog(void)
diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index c284524..427b7f7 100644
--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c
@@ -334,6 +334,20 @@
}
#endif
+void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len)
+{
+ int align_len = ARCH_DMA_MINALIGN - 1;
+
+ /* Some devices like SDP, NOR, NAND, SPI are using bl_len =1, so their fit address
+ * is different with SD/MMC, this cause mismatch with signed address. Thus, adjust
+ * the bl_len to align with SD/MMC.
+ */
+ if (bl_len < 512)
+ bl_len = 512;
+
+ return (void *)((CONFIG_SYS_TEXT_BASE - fit_size - bl_len -
+ align_len) & ~align_len);
+}
#endif
#if defined(CONFIG_MX6) && defined(CONFIG_SPL_OS_BOOT)
@@ -345,3 +359,36 @@
return 0;
}
#endif
+
+/*
+ * read the address where the IVT header must sit
+ * from IVT image header, loaded from SPL into
+ * an malloced buffer and copy the IVT header
+ * to this address
+ */
+void *spl_load_simple_fit_fix_load(const void *fit)
+{
+ struct ivt *ivt;
+ unsigned long new;
+ unsigned long offset;
+ unsigned long size;
+ u8 *tmp = (u8 *)fit;
+
+ offset = ALIGN(fdt_totalsize(fit), 0x1000);
+ size = ALIGN(fdt_totalsize(fit), 4);
+ size = board_spl_fit_size_align(size);
+ tmp += offset;
+ ivt = (struct ivt *)tmp;
+ if (ivt->hdr.magic != IVT_HEADER_MAGIC) {
+ debug("no IVT header found\n");
+ return (void *)fit;
+ }
+ debug("%s: ivt: %p offset: %lx size: %lx\n", __func__, ivt, offset, size);
+ debug("%s: ivt self: %x\n", __func__, ivt->self);
+ new = ivt->self;
+ new -= offset;
+ debug("%s: new %lx\n", __func__, new);
+ memcpy((void *)new, fit, size);
+
+ return (void *)new;
+}
diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h
index 9002e26..cf6b1b9 100644
--- a/arch/arm/mach-kirkwood/include/mach/config.h
+++ b/arch/arm/mach-kirkwood/include/mach/config.h
@@ -63,13 +63,6 @@
#endif /* CONFIG_CMD_NET */
/*
- * USB/EHCI
- */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_EHCI_IS_TDI
-#endif /* CONFIG_CMD_USB */
-
-/*
* IDE Support on SATA ports
*/
#ifdef CONFIG_IDE
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 0876437..d23cc0c 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -11,6 +11,7 @@
select SPL_DM if SPL
select SPL_DM_SEQ_ALIAS if SPL
select SPL_OF_CONTROL if SPL
+ select SPL_SKIP_LOWLEVEL_INIT if SPL
select SPL_SIMPLE_BUS if SPL
select SUPPORT_SPL
select TRANSLATION_OFFSET
@@ -126,7 +127,9 @@
select DM_I2C
select I2C_MUX
select I2C_MUX_PCA954x
+ select SPL_DRIVERS_MISC
select SPL_I2C_MUX
+ select SPL_SYS_MALLOC_SIMPLE
select SYS_I2C_MVTWSI
select ATSHA204A
diff --git a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c
index adef333..55c3f9c 100644
--- a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c
+++ b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c
@@ -21,35 +21,12 @@
int hws_pex_config(const struct serdes_map *serdes_map, u8 count)
{
- u32 pex_idx, tmp, next_busno, first_busno, temp_pex_reg,
- temp_reg, addr, dev_id, ctrl_mode;
enum serdes_type serdes_type;
- u32 idx;
+ u32 idx, tmp;
DEBUG_INIT_FULL_S("\n### hws_pex_config ###\n");
- for (idx = 0; idx < count; idx++) {
- serdes_type = serdes_map[idx].serdes_type;
- /* configuration for PEX only */
- if ((serdes_type != PEX0) && (serdes_type != PEX1) &&
- (serdes_type != PEX2) && (serdes_type != PEX3))
- continue;
-
- if ((serdes_type != PEX0) &&
- ((serdes_map[idx].serdes_mode == PEX_ROOT_COMPLEX_X4) ||
- (serdes_map[idx].serdes_mode == PEX_END_POINT_X4))) {
- /* for PEX by4 - relevant for the first port only */
- continue;
- }
-
- pex_idx = serdes_type - PEX0;
- tmp = reg_read(PEX_CAPABILITIES_REG(pex_idx));
- tmp &= ~(0xf << 20);
- tmp |= (0x4 << 20);
- reg_write(PEX_CAPABILITIES_REG(pex_idx), tmp);
- }
-
- tmp = reg_read(SOC_CTRL_REG);
+ tmp = reg_read(SOC_CONTROL_REG1);
tmp &= ~0x03;
for (idx = 0; idx < count; idx++) {
@@ -79,277 +56,9 @@
}
}
- reg_write(SOC_CTRL_REG, tmp);
-
- /* Support gen1/gen2 */
- DEBUG_INIT_FULL_S("Support gen1/gen2\n");
+ reg_write(SOC_CONTROL_REG1, tmp);
board_pex_config();
- next_busno = 0;
- mdelay(150);
-
- for (idx = 0; idx < count; idx++) {
- serdes_type = serdes_map[idx].serdes_type;
- DEBUG_INIT_FULL_S(" serdes_type=0x");
- DEBUG_INIT_FULL_D(serdes_type, 8);
- DEBUG_INIT_FULL_S("\n");
- DEBUG_INIT_FULL_S(" idx=0x");
- DEBUG_INIT_FULL_D(idx, 8);
- DEBUG_INIT_FULL_S("\n");
-
- /* Configuration for PEX only */
- if ((serdes_type != PEX0) && (serdes_type != PEX1) &&
- (serdes_type != PEX2) && (serdes_type != PEX3))
- continue;
-
- if ((serdes_type != PEX0) &&
- ((serdes_map[idx].serdes_mode == PEX_ROOT_COMPLEX_X4) ||
- (serdes_map[idx].serdes_mode == PEX_END_POINT_X4))) {
- /* for PEX by4 - relevant for the first port only */
- continue;
- }
-
- pex_idx = serdes_type - PEX0;
- tmp = reg_read(PEX_DBG_STATUS_REG(pex_idx));
-
- first_busno = next_busno;
- if ((tmp & 0x7f) != 0x7e) {
- DEBUG_INIT_S("PCIe, Idx ");
- DEBUG_INIT_D(pex_idx, 1);
- DEBUG_INIT_S(": detected no link\n");
- continue;
- }
-
- next_busno++;
- temp_pex_reg = reg_read((PEX_CFG_DIRECT_ACCESS
- (pex_idx, PEX_LINK_CAPABILITY_REG)));
- temp_pex_reg &= 0xf;
- if (temp_pex_reg != 0x2)
- continue;
-
- temp_reg = (reg_read(PEX_CFG_DIRECT_ACCESS(
- pex_idx,
- PEX_LINK_CTRL_STAT_REG)) &
- 0xf0000) >> 16;
-
- /* Check if the link established is GEN1 */
- DEBUG_INIT_FULL_S
- ("Checking if the link established is gen1\n");
- if (temp_reg != 0x1)
- continue;
-
- pex_local_bus_num_set(pex_idx, first_busno);
- pex_local_dev_num_set(pex_idx, 1);
- DEBUG_INIT_FULL_S("PCIe, Idx ");
- DEBUG_INIT_FULL_D(pex_idx, 1);
-
- DEBUG_INIT_S(":** Link is Gen1, check the EP capability\n");
- /* link is Gen1, check the EP capability */
- addr = pex_config_read(pex_idx, first_busno, 0, 0, 0x34) & 0xff;
- DEBUG_INIT_FULL_C("pex_config_read: return addr=0x%x", addr, 4);
- if (addr == 0xff) {
- DEBUG_INIT_FULL_C
- ("pex_config_read: return 0xff -->PCIe (%d): Detected No Link.",
- pex_idx, 1);
- continue;
- }
-
- while ((pex_config_read(pex_idx, first_busno, 0, 0, addr)
- & 0xff) != 0x10) {
- addr = (pex_config_read(pex_idx, first_busno, 0,
- 0, addr) & 0xff00) >> 8;
- }
-
- /* Check for Gen2 and above */
- if ((pex_config_read(pex_idx, first_busno, 0, 0,
- addr + 0xc) & 0xf) < 0x2) {
- DEBUG_INIT_S("PCIe, Idx ");
- DEBUG_INIT_D(pex_idx, 1);
- DEBUG_INIT_S(": remains Gen1\n");
- continue;
- }
-
- tmp = reg_read(PEX_LINK_CTRL_STATUS2_REG(pex_idx));
- DEBUG_RD_REG(PEX_LINK_CTRL_STATUS2_REG(pex_idx), tmp);
- tmp &= ~(BIT(0) | BIT(1));
- tmp |= BIT(1);
- tmp |= BIT(6); /* Select Deemphasize (-3.5d_b) */
- reg_write(PEX_LINK_CTRL_STATUS2_REG(pex_idx), tmp);
- DEBUG_WR_REG(PEX_LINK_CTRL_STATUS2_REG(pex_idx), tmp);
-
- tmp = reg_read(PEX_CTRL_REG(pex_idx));
- DEBUG_RD_REG(PEX_CTRL_REG(pex_idx), tmp);
- tmp |= BIT(10);
- reg_write(PEX_CTRL_REG(pex_idx), tmp);
- DEBUG_WR_REG(PEX_CTRL_REG(pex_idx), tmp);
-
- /*
- * We need to wait 10ms before reading the PEX_DBG_STATUS_REG
- * in order not to read the status of the former state
- */
- mdelay(10);
-
- DEBUG_INIT_S("PCIe, Idx ");
- DEBUG_INIT_D(pex_idx, 1);
- DEBUG_INIT_S
- (": Link upgraded to Gen2 based on client capabilities\n");
- }
-
- /* Update pex DEVICE ID */
- ctrl_mode = sys_env_model_get();
-
- for (idx = 0; idx < count; idx++) {
- serdes_type = serdes_map[idx].serdes_type;
- /* configuration for PEX only */
- if ((serdes_type != PEX0) && (serdes_type != PEX1) &&
- (serdes_type != PEX2) && (serdes_type != PEX3))
- continue;
-
- if ((serdes_type != PEX0) &&
- ((serdes_map[idx].serdes_mode == PEX_ROOT_COMPLEX_X4) ||
- (serdes_map[idx].serdes_mode == PEX_END_POINT_X4))) {
- /* for PEX by4 - relevant for the first port only */
- continue;
- }
-
- pex_idx = serdes_type - PEX0;
- dev_id = reg_read(PEX_CFG_DIRECT_ACCESS
- (pex_idx, PEX_DEVICE_AND_VENDOR_ID));
- dev_id &= 0xffff;
- dev_id |= ((ctrl_mode << 16) & 0xffff0000);
- reg_write(PEX_CFG_DIRECT_ACCESS
- (pex_idx, PEX_DEVICE_AND_VENDOR_ID), dev_id);
- }
- DEBUG_INIT_FULL_C("Update PEX Device ID ", ctrl_mode, 4);
-
return MV_OK;
}
-
-int pex_local_bus_num_set(u32 pex_if, u32 bus_num)
-{
- u32 pex_status;
-
- DEBUG_INIT_FULL_S("\n### pex_local_bus_num_set ###\n");
-
- if (bus_num >= MAX_PEX_BUSSES) {
- DEBUG_INIT_C("pex_local_bus_num_set: Illegal bus number %d\n",
- bus_num, 4);
- return MV_BAD_PARAM;
- }
-
- pex_status = reg_read(PEX_STATUS_REG(pex_if));
- pex_status &= ~PXSR_PEX_BUS_NUM_MASK;
- pex_status |=
- (bus_num << PXSR_PEX_BUS_NUM_OFFS) & PXSR_PEX_BUS_NUM_MASK;
- reg_write(PEX_STATUS_REG(pex_if), pex_status);
-
- return MV_OK;
-}
-
-int pex_local_dev_num_set(u32 pex_if, u32 dev_num)
-{
- u32 pex_status;
-
- DEBUG_INIT_FULL_S("\n### pex_local_dev_num_set ###\n");
-
- pex_status = reg_read(PEX_STATUS_REG(pex_if));
- pex_status &= ~PXSR_PEX_DEV_NUM_MASK;
- pex_status |=
- (dev_num << PXSR_PEX_DEV_NUM_OFFS) & PXSR_PEX_DEV_NUM_MASK;
- reg_write(PEX_STATUS_REG(pex_if), pex_status);
-
- return MV_OK;
-}
-
-/*
- * pex_config_read - Read from configuration space
- *
- * DESCRIPTION:
- * This function performs a 32 bit read from PEX configuration space.
- * It supports both type 0 and type 1 of Configuration Transactions
- * (local and over bridge). In order to read from local bus segment, use
- * bus number retrieved from pex_local_bus_num_get(). Other bus numbers
- * will result configuration transaction of type 1 (over bridge).
- *
- * INPUT:
- * pex_if - PEX interface number.
- * bus - PEX segment bus number.
- * dev - PEX device number.
- * func - Function number.
- * reg_offs - Register offset.
- *
- * OUTPUT:
- * None.
- *
- * RETURN:
- * 32bit register data, 0xffffffff on error
- */
-u32 pex_config_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 reg_off)
-{
- u32 pex_data = 0;
- u32 local_dev, local_bus;
- u32 pex_status;
-
- pex_status = reg_read(PEX_STATUS_REG(pex_if));
- local_dev =
- ((pex_status & PXSR_PEX_DEV_NUM_MASK) >> PXSR_PEX_DEV_NUM_OFFS);
- local_bus =
- ((pex_status & PXSR_PEX_BUS_NUM_MASK) >> PXSR_PEX_BUS_NUM_OFFS);
-
- /*
- * In PCI Express we have only one device number
- * and this number is the first number we encounter
- * else that the local_dev
- * spec pex define return on config read/write on any device
- */
- if (bus == local_bus) {
- if (local_dev == 0) {
- /*
- * if local dev is 0 then the first number we encounter
- * after 0 is 1
- */
- if ((dev != 1) && (dev != local_dev))
- return MV_ERROR;
- } else {
- /*
- * if local dev is not 0 then the first number we
- * encounter is 0
- */
- if ((dev != 0) && (dev != local_dev))
- return MV_ERROR;
- }
- }
-
- /* Creating PEX address to be passed */
- pex_data = (bus << PXCAR_BUS_NUM_OFFS);
- pex_data |= (dev << PXCAR_DEVICE_NUM_OFFS);
- pex_data |= (func << PXCAR_FUNC_NUM_OFFS);
- /* Legacy register space */
- pex_data |= (reg_off & PXCAR_REG_NUM_MASK);
- /* Extended register space */
- pex_data |= (((reg_off & PXCAR_REAL_EXT_REG_NUM_MASK) >>
- PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS);
- pex_data |= PXCAR_CONFIG_EN;
-
- /* Write the address to the PEX configuration address register */
- reg_write(PEX_CFG_ADDR_REG(pex_if), pex_data);
-
- /*
- * In order to let the PEX controller absorbed the address
- * of the read transaction we perform a validity check that
- * the address was written
- */
- if (pex_data != reg_read(PEX_CFG_ADDR_REG(pex_if)))
- return MV_ERROR;
-
- /* Cleaning Master Abort */
- reg_bit_set(PEX_CFG_DIRECT_ACCESS(pex_if, PEX_STATUS_AND_COMMAND),
- PXSAC_MABORT);
- /* Read the Data returned in the PEX Data register */
- pex_data = reg_read(PEX_CFG_DATA_REG(pex_if));
-
- DEBUG_INIT_FULL_C(" --> ", pex_data, 4);
-
- return pex_data;
-}
diff --git a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h
index 3f30b6b..64193d5 100644
--- a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h
+++ b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h
@@ -6,35 +6,13 @@
#ifndef _CTRL_PEX_H
#define _CTRL_PEX_H
+#include <pci.h>
#include "high_speed_env_spec.h"
-/* Sample at Reset */
-#define MPP_SAMPLE_AT_RESET(id) (0xe4200 + (id * 4))
+/* Direct access to PEX0 Root Port's PCIe Capability structure */
+#define PEX0_RP_PCIE_CFG_OFFSET (0x00080000 + 0x60)
-/* PCI Express Control and Status Registers */
-#define MAX_PEX_BUSSES 256
-
-#define MISC_REGS_OFFSET 0x18200
-#define MV_MISC_REGS_BASE MISC_REGS_OFFSET
-#define SOC_CTRL_REG (MV_MISC_REGS_BASE + 0x4)
-
-#define PEX_IF_REGS_OFFSET(if) ((if) > 0 ? \
- (0x40000 + ((if) - 1) * 0x4000) : \
- 0x80000)
-#define PEX_IF_REGS_BASE(if) (PEX_IF_REGS_OFFSET(if))
-#define PEX_CAPABILITIES_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x60)
-#define PEX_LINK_CTRL_STATUS2_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x90)
-#define PEX_CTRL_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x1a00)
-#define PEX_STATUS_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x1a04)
-#define PEX_DBG_STATUS_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x1a64)
-#define PEX_LINK_CAPABILITY_REG 0x6c
-#define PEX_LINK_CTRL_STAT_REG 0x70
-#define PXSR_PEX_DEV_NUM_OFFS 16 /* Device Number Indication */
-#define PXSR_PEX_DEV_NUM_MASK (0x1f << PXSR_PEX_DEV_NUM_OFFS)
-#define PXSR_PEX_BUS_NUM_OFFS 8 /* Bus Number Indication */
-#define PXSR_PEX_BUS_NUM_MASK (0xff << PXSR_PEX_BUS_NUM_OFFS)
-
-/* PEX_CAPABILITIES_REG fields */
+/* SOC_CONTROL_REG1 fields */
#define PCIE0_ENABLE_OFFS 0
#define PCIE0_ENABLE_MASK (0x1 << PCIE0_ENABLE_OFFS)
#define PCIE1_ENABLE_OFFS 1
@@ -44,45 +22,7 @@
#define PCIE3_ENABLE_OFFS 3
#define PCIE4_ENABLE_MASK (0x1 << PCIE3_ENABLE_OFFS)
-/* Controller revision info */
-#define PEX_DEVICE_AND_VENDOR_ID 0x000
-#define PEX_CFG_DIRECT_ACCESS(if, reg) (PEX_IF_REGS_BASE(if) + (reg))
-
-/* PCI Express Configuration Address Register */
-#define PXCAR_REG_NUM_OFFS 2
-#define PXCAR_REG_NUM_MAX 0x3f
-#define PXCAR_REG_NUM_MASK (PXCAR_REG_NUM_MAX << \
- PXCAR_REG_NUM_OFFS)
-#define PXCAR_FUNC_NUM_OFFS 8
-#define PXCAR_FUNC_NUM_MAX 0x7
-#define PXCAR_FUNC_NUM_MASK (PXCAR_FUNC_NUM_MAX << \
- PXCAR_FUNC_NUM_OFFS)
-#define PXCAR_DEVICE_NUM_OFFS 11
-#define PXCAR_DEVICE_NUM_MAX 0x1f
-#define PXCAR_DEVICE_NUM_MASK (PXCAR_DEVICE_NUM_MAX << \
- PXCAR_DEVICE_NUM_OFFS)
-#define PXCAR_BUS_NUM_OFFS 16
-#define PXCAR_BUS_NUM_MAX 0xff
-#define PXCAR_BUS_NUM_MASK (PXCAR_BUS_NUM_MAX << \
- PXCAR_BUS_NUM_OFFS)
-#define PXCAR_EXT_REG_NUM_OFFS 24
-#define PXCAR_EXT_REG_NUM_MAX 0xf
-
-#define PEX_CFG_ADDR_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x18f8)
-#define PEX_CFG_DATA_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x18fc)
-
-#define PXCAR_REAL_EXT_REG_NUM_OFFS 8
-#define PXCAR_REAL_EXT_REG_NUM_MASK (0xf << PXCAR_REAL_EXT_REG_NUM_OFFS)
-
-#define PXCAR_CONFIG_EN BIT(31)
-#define PEX_STATUS_AND_COMMAND 0x004
-#define PXSAC_MABORT BIT(29) /* Recieved Master Abort */
-
int hws_pex_config(const struct serdes_map *serdes_map, u8 count);
-int pex_local_bus_num_set(u32 pex_if, u32 bus_num);
-int pex_local_dev_num_set(u32 pex_if, u32 dev_num);
-u32 pex_config_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 reg_off);
-
void board_pex_config(void);
#endif
diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
index bb7d24b..d2bc3ab 100644
--- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
+++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
@@ -1712,7 +1712,7 @@
(serdes_mode == PEX_END_POINT_X1);
pex_idx = serdes_type - PEX0;
- if ((is_pex_by1 == 1) || (serdes_type == PEX0)) {
+ if (serdes_type == PEX0) {
/* For PEX by 4, init only the PEX 0 */
reg_data = reg_read(SOC_CONTROL_REG1);
if (is_pex_by1 == 1)
@@ -1721,32 +1721,20 @@
reg_data &= ~0x4000;
reg_write(SOC_CONTROL_REG1, reg_data);
- reg_data =
- reg_read(((PEX_IF_REGS_BASE(pex_idx)) +
- 0x6c));
- reg_data &= ~0x3f0;
- if (is_pex_by1 == 1)
- reg_data |= 0x10;
- else
- reg_data |= 0x40;
- reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x6c),
- reg_data);
-
- reg_data =
- reg_read(((PEX_IF_REGS_BASE(pex_idx)) +
- 0x6c));
- reg_data &= ~0xf;
- reg_data |= 0x2;
- reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x6c),
- reg_data);
-
- reg_data =
- reg_read(((PEX_IF_REGS_BASE(pex_idx)) +
- 0x70));
- reg_data &= ~0x40;
- reg_data |= 0x40;
- reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x70),
- reg_data);
+ /*
+ * Set Maximum Link Width to X1 or X4 in Root
+ * Port's PCIe Link Capability register.
+ * This register is read-only but if is not set
+ * correctly then access to PCI config space of
+ * endpoint card behind this Root Port does not
+ * work.
+ */
+ reg_data = reg_read(PEX0_RP_PCIE_CFG_OFFSET +
+ PCI_EXP_LNKCAP);
+ reg_data &= ~PCI_EXP_LNKCAP_MLW;
+ reg_data |= (is_pex_by1 ? 1 : 4) << 4;
+ reg_write(PEX0_RP_PCIE_CFG_OFFSET +
+ PCI_EXP_LNKCAP, reg_data);
}
CHECK_STATUS(mv_seq_exec(serdes_num, PEX_POWER_UP_SEQ));
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 1d4a4fd..2c18cf0 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -88,17 +88,6 @@
feature.
endif
-config SUN6I_P2WI
- bool "Allwinner sun6i internal P2WI controller"
- help
- If you say yes to this option, support will be included for the
- P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
- SOCs.
- The P2WI looks like an SMBus controller (which supports only byte
- accesses), except that it only supports one slave device.
- This interface is used to connect to specific PMIC devices (like the
- AXP221).
-
config SUN6I_PRCM
bool
help
@@ -106,19 +95,13 @@
in A31 SoC.
config AXP_PMIC_BUS
- bool "Sunxi AXP PMIC bus access helpers"
+ bool
+ select DM_PMIC if DM_I2C
+ select PMIC_AXP if DM_I2C
help
Select this PMIC bus access helpers for Sunxi platform PRCM or other
AXP family PMIC devices.
-config SUN8I_RSB
- bool "Allwinner sunXi Reduced Serial Bus Driver"
- help
- Say y here to enable support for Allwinner's Reduced Serial Bus
- (RSB) support. This controller is responsible for communicating
- with various RSB based devices, such as AXP223, AXP8XX PMICs,
- and AC100/AC200 ICs.
-
config SUNXI_SRAM_ADDRESS
hex
default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
@@ -182,7 +165,6 @@
config MACH_SUNXI_H3_H5
bool
- select DM_I2C
select PHY_SUN4I_USB
select SUNXI_DE2
select SUNXI_DRAM_DW
@@ -232,10 +214,11 @@
select ARCH_SUPPORT_PSCI
select DRAM_SUN6I
select PHY_SUN4I_USB
- select SUN6I_P2WI
+ select SPL_I2C
select SUN6I_PRCM
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
+ select SYS_I2C_SUN6I_P2WI
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
config MACH_SUN7I
@@ -260,8 +243,10 @@
select ARCH_SUPPORT_PSCI
select DRAM_SUN8I_A23
select PHY_SUN4I_USB
+ select SPL_I2C
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
+ select SYS_I2C_SUN8I_RSB
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
imply CONS_INDEX_5 if !DM_SERIAL
@@ -273,8 +258,10 @@
select ARCH_SUPPORT_PSCI
select DRAM_SUN8I_A33
select PHY_SUN4I_USB
+ select SPL_I2C
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
+ select SYS_I2C_SUN8I_RSB
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
imply CONS_INDEX_5 if !DM_SERIAL
@@ -283,10 +270,12 @@
select CPU_V7A
select DRAM_SUN8I_A83T
select PHY_SUN4I_USB
+ select SPL_I2C
select SUNXI_GEN_SUN6I
select MMC_SUNXI_HAS_NEW_MODE
select MMC_SUNXI_HAS_MODE_SWITCH
select SUPPORT_SPL
+ select SYS_I2C_SUN8I_RSB
config MACH_SUN8I_H3
bool "sun8i (Allwinner H3)"
@@ -327,16 +316,15 @@
bool "sun9i (Allwinner A80)"
select CPU_V7A
select DRAM_SUN9I
+ select SPL_I2C
select SUN6I_PRCM
select SUNXI_GEN_SUN6I
- select SUN8I_RSB
select SUPPORT_SPL
config MACH_SUN50I
bool "sun50i (Allwinner A64)"
select ARM64
select SPI
- select DM_I2C
select DM_SPI if SPI
select DM_SPI_FLASH
select PHY_SUN4I_USB
@@ -377,7 +365,6 @@
# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
config MACH_SUN8I
bool
- select SUN8I_RSB
select SUN6I_PRCM
default y if MACH_SUN8I_A23
default y if MACH_SUN8I_A33
@@ -677,24 +664,11 @@
---help---
See MMC0_CD_PIN help text.
-config MMC1_PINS
- string "Pins for mmc1"
- default ""
+config MMC1_PINS_PH
+ bool "Pins for mmc1 are on Port H"
+ depends on MACH_SUN4I || MACH_SUN7I || MACH_SUN8I_R40
---help---
- Set the pins used for mmc1, when applicable. This takes a string in the
- format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
-
-config MMC2_PINS
- string "Pins for mmc2"
- default ""
- ---help---
- See MMC1_PINS help text.
-
-config MMC3_PINS
- string "Pins for mmc3"
- default ""
- ---help---
- See MMC1_PINS help text.
+ Select this option for boards where mmc1 uses the Port H pinmux.
config MMC_SUNXI_SLOT_EXTRA
int "mmc extra slot number"
@@ -807,6 +781,7 @@
config AXP_GPIO
bool "Enable support for gpio-s on axp PMICs"
+ depends on AXP_PMIC_BUS
---help---
Say Y here to enable support for the gpio pins of the axp PMIC ICs.
@@ -932,27 +907,17 @@
config VIDEO_LCD_PANEL_I2C
bool "LCD panel needs to be configured via i2c"
depends on VIDEO_SUNXI
- select CMD_I2C
+ select DM_I2C_GPIO
---help---
Say y here if the LCD panel needs to be configured via i2c. This
will add a bitbang i2c controller using gpios to talk to the LCD.
-config VIDEO_LCD_PANEL_I2C_SDA
- string "LCD panel i2c interface SDA pin"
+config VIDEO_LCD_PANEL_I2C_NAME
+ string "LCD panel i2c interface node name"
depends on VIDEO_LCD_PANEL_I2C
- default "PG12"
+ default "i2c@0"
---help---
- Set the SDA pin for the LCD i2c interface. This takes a string in the
- format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
-
-config VIDEO_LCD_PANEL_I2C_SCL
- string "LCD panel i2c interface SCL pin"
- depends on VIDEO_LCD_PANEL_I2C
- default "PG10"
- ---help---
- Set the SCL pin for the LCD i2c interface. This takes a string in the
- format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
-
+ Set the device tree node name for the LCD i2c interface.
# Note only one of these may be selected at a time! But hidden choices are
# not supported by Kconfig
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index 3f081d9..5d3fd70 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -11,10 +11,8 @@
obj-y += cpu_info.o
obj-y += dram_helpers.o
obj-y += pinmux.o
-obj-$(CONFIG_SUN6I_P2WI) += p2wi.o
obj-$(CONFIG_SUN6I_PRCM) += prcm.o
obj-$(CONFIG_AXP_PMIC_BUS) += pmic_bus.o
-obj-$(CONFIG_SUN8I_RSB) += rsb.o
obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index d9b04f7..b4ba2a7 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -21,7 +21,6 @@
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/spl.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/timer.h>
@@ -339,7 +338,7 @@
spl_init();
preloader_console_init();
-#ifdef CONFIG_SPL_I2C
+#if CONFIG_IS_ENABLED(I2C) && CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
/* Needed early by sunxi_board_init if PMU is enabled */
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
diff --git a/arch/arm/mach-sunxi/clock.c b/arch/arm/mach-sunxi/clock.c
index f591aff..de7e875 100644
--- a/arch/arm/mach-sunxi/clock.c
+++ b/arch/arm/mach-sunxi/clock.c
@@ -10,7 +10,6 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/prcm.h>
#include <asm/arch/gtbus.h>
#include <asm/arch/sys_proto.h>
diff --git a/arch/arm/mach-sunxi/clock_sun4i.c b/arch/arm/mach-sunxi/clock_sun4i.c
index 57ee018..4716097 100644
--- a/arch/arm/mach-sunxi/clock_sun4i.c
+++ b/arch/arm/mach-sunxi/clock_sun4i.c
@@ -12,7 +12,6 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/sys_proto.h>
#ifdef CONFIG_SPL_BUILD
diff --git a/arch/arm/mach-sunxi/p2wi.c b/arch/arm/mach-sunxi/p2wi.c
deleted file mode 100644
index 7c5c122..0000000
--- a/arch/arm/mach-sunxi/p2wi.c
+++ /dev/null
@@ -1,117 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Sunxi A31 Power Management Unit
- *
- * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
- * http://linux-sunxi.org
- *
- * Based on sun6i sources and earlier U-Boot Allwinner A10 SPL work
- *
- * (C) Copyright 2006-2013
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- * Berg Xing <bergxing@allwinnertech.com>
- * Tom Cubie <tangliang@allwinnertech.com>
- */
-
-#include <common.h>
-#include <errno.h>
-#include <time.h>
-#include <asm/io.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/p2wi.h>
-#include <asm/arch/prcm.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-
-void p2wi_init(void)
-{
- struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
-
- /* Enable p2wi and PIO clk, and de-assert their resets */
- prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI);
-
- sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN6I_GPL0_R_P2WI_SCK);
- sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN6I_GPL1_R_P2WI_SDA);
-
- /* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */
- writel(P2WI_CTRL_RESET, &p2wi->ctrl);
- sdelay(0x100);
- writel(P2WI_CC_SDA_OUT_DELAY(1) | P2WI_CC_CLK_DIV(8),
- &p2wi->cc);
-}
-
-int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data)
-{
- struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
- unsigned long tmo = timer_get_us() + 1000000;
-
- writel(P2WI_PM_DEV_ADDR(slave_addr) |
- P2WI_PM_CTRL_ADDR(ctrl_reg) |
- P2WI_PM_INIT_DATA(init_data) |
- P2WI_PM_INIT_SEND,
- &p2wi->pm);
-
- while ((readl(&p2wi->pm) & P2WI_PM_INIT_SEND)) {
- if (timer_get_us() > tmo)
- return -ETIME;
- }
-
- return 0;
-}
-
-static int p2wi_await_trans(void)
-{
- struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
- unsigned long tmo = timer_get_us() + 1000000;
- int ret;
- u8 reg;
-
- while (1) {
- reg = readl(&p2wi->status);
- if (reg & P2WI_STAT_TRANS_ERR) {
- ret = -EIO;
- break;
- }
- if (reg & P2WI_STAT_TRANS_DONE) {
- ret = 0;
- break;
- }
- if (timer_get_us() > tmo) {
- ret = -ETIME;
- break;
- }
- }
- writel(reg, &p2wi->status); /* Clear status bits */
- return ret;
-}
-
-int p2wi_read(const u8 addr, u8 *data)
-{
- struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
- int ret;
-
- writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
- writel(P2WI_DATA_NUM_BYTES(1) |
- P2WI_DATA_NUM_BYTES_READ, &p2wi->numbytes);
- writel(P2WI_STAT_TRANS_DONE, &p2wi->status);
- writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl);
-
- ret = p2wi_await_trans();
-
- *data = readl(&p2wi->data0) & P2WI_DATA_BYTE_1_MASK;
- return ret;
-}
-
-int p2wi_write(const u8 addr, u8 data)
-{
- struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
-
- writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
- writel(P2WI_DATA_BYTE_1(data), &p2wi->data0);
- writel(P2WI_DATA_NUM_BYTES(1), &p2wi->numbytes);
- writel(P2WI_STAT_TRANS_DONE, &p2wi->status);
- writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl);
-
- return p2wi_await_trans();
-}
diff --git a/arch/arm/mach-sunxi/pmic_bus.c b/arch/arm/mach-sunxi/pmic_bus.c
index 0394ce8..c090840 100644
--- a/arch/arm/mach-sunxi/pmic_bus.c
+++ b/arch/arm/mach-sunxi/pmic_bus.c
@@ -8,10 +8,13 @@
* axp223 uses the rsb bus, these functions abstract this.
*/
+#include <axp_pmic.h>
#include <common.h>
+#include <dm.h>
#include <asm/arch/p2wi.h>
#include <asm/arch/rsb.h>
#include <i2c.h>
+#include <power/pmic.h>
#include <asm/arch/pmic_bus.h>
#define AXP152_I2C_ADDR 0x30
@@ -21,80 +24,80 @@
#define AXP305_I2C_ADDR 0x36
#define AXP221_CHIP_ADDR 0x68
-#define AXP221_CTRL_ADDR 0x3e
-#define AXP221_INIT_DATA 0x3e
-/* AXP818 device and runtime addresses are same as AXP223 */
-#define AXP223_DEVICE_ADDR 0x3a3
-#define AXP223_RUNTIME_ADDR 0x2d
+#if CONFIG_IS_ENABLED(PMIC_AXP)
+static struct udevice *pmic;
+#else
+static int pmic_i2c_address(void)
+{
+ if (IS_ENABLED(CONFIG_AXP152_POWER))
+ return AXP152_I2C_ADDR;
+ if (IS_ENABLED(CONFIG_AXP305_POWER))
+ return AXP305_I2C_ADDR;
+
+ /* Other AXP2xx and AXP8xx variants */
+ return AXP209_I2C_ADDR;
+}
+#endif
int pmic_bus_init(void)
{
/* This cannot be 0 because it is used in SPL before BSS is ready */
static int needs_init = 1;
- __maybe_unused int ret;
+ int ret = 0;
if (!needs_init)
return 0;
-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
-# ifdef CONFIG_MACH_SUN6I
- p2wi_init();
- ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR,
- AXP221_INIT_DATA);
-# elif defined CONFIG_MACH_SUN8I_R40
- /* Nothing. R40 uses the AXP221s in I2C mode */
- ret = 0;
-# else
- ret = rsb_init();
- if (ret)
- return ret;
+#if CONFIG_IS_ENABLED(PMIC_AXP)
+ ret = uclass_get_device_by_driver(UCLASS_PMIC, DM_DRIVER_GET(axp_pmic),
+ &pmic);
+#else
+ if (IS_ENABLED(CONFIG_SYS_I2C_SUN6I_P2WI)) {
+ p2wi_init();
+ ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR,
+ AXP_PMIC_MODE_REG,
+ AXP_PMIC_MODE_P2WI);
+ } else if (IS_ENABLED(CONFIG_SYS_I2C_SUN8I_RSB)) {
+ ret = rsb_init();
+ if (ret)
+ return ret;
- ret = rsb_set_device_address(AXP223_DEVICE_ADDR, AXP223_RUNTIME_ADDR);
-# endif
- if (ret)
- return ret;
+ ret = rsb_set_device_address(AXP_PMIC_PRI_DEVICE_ADDR,
+ AXP_PMIC_PRI_RUNTIME_ADDR);
+ }
#endif
- needs_init = 0;
- return 0;
+ needs_init = ret;
+
+ return ret;
}
int pmic_bus_read(u8 reg, u8 *data)
{
-#ifdef CONFIG_AXP152_POWER
- return i2c_read(AXP152_I2C_ADDR, reg, 1, data, 1);
-#elif defined CONFIG_AXP209_POWER
- return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1);
-#elif defined CONFIG_AXP305_POWER
- return i2c_read(AXP305_I2C_ADDR, reg, 1, data, 1);
-#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
-# ifdef CONFIG_MACH_SUN6I
- return p2wi_read(reg, data);
-# elif defined CONFIG_MACH_SUN8I_R40
- return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1);
-# else
- return rsb_read(AXP223_RUNTIME_ADDR, reg, data);
-# endif
+#if CONFIG_IS_ENABLED(PMIC_AXP)
+ return pmic_read(pmic, reg, data, 1);
+#else
+ if (IS_ENABLED(CONFIG_SYS_I2C_SUN6I_P2WI))
+ return p2wi_read(reg, data);
+ if (IS_ENABLED(CONFIG_SYS_I2C_SUN8I_RSB))
+ return rsb_read(AXP_PMIC_PRI_RUNTIME_ADDR, reg, data);
+
+ return i2c_read(pmic_i2c_address(), reg, 1, data, 1);
#endif
}
int pmic_bus_write(u8 reg, u8 data)
{
-#ifdef CONFIG_AXP152_POWER
- return i2c_write(AXP152_I2C_ADDR, reg, 1, &data, 1);
-#elif defined CONFIG_AXP209_POWER
- return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1);
-#elif defined CONFIG_AXP305_POWER
- return i2c_write(AXP305_I2C_ADDR, reg, 1, &data, 1);
-#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
-# ifdef CONFIG_MACH_SUN6I
- return p2wi_write(reg, data);
-# elif defined CONFIG_MACH_SUN8I_R40
- return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1);
-# else
- return rsb_write(AXP223_RUNTIME_ADDR, reg, data);
-# endif
+#if CONFIG_IS_ENABLED(PMIC_AXP)
+ return pmic_write(pmic, reg, &data, 1);
+#else
+ if (IS_ENABLED(CONFIG_SYS_I2C_SUN6I_P2WI))
+ return p2wi_write(reg, data);
+ if (IS_ENABLED(CONFIG_SYS_I2C_SUN8I_RSB))
+ return rsb_write(AXP_PMIC_PRI_RUNTIME_ADDR, reg, data);
+
+ return i2c_write(pmic_i2c_address(), reg, 1, &data, 1);
#endif
}
diff --git a/arch/arm/mach-sunxi/rsb.c b/arch/arm/mach-sunxi/rsb.c
deleted file mode 100644
index 01bb09b..0000000
--- a/arch/arm/mach-sunxi/rsb.c
+++ /dev/null
@@ -1,175 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
- *
- * Based on allwinner u-boot sources rsb code which is:
- * (C) Copyright 2007-2013
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- * lixiang <lixiang@allwinnertech.com>
- */
-
-#include <common.h>
-#include <errno.h>
-#include <time.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/prcm.h>
-#include <asm/arch/rsb.h>
-
-static int rsb_set_device_mode(void);
-
-static void rsb_cfg_io(void)
-{
-#ifdef CONFIG_MACH_SUN8I
- sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB);
- sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB);
- sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
- sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
- sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
- sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
-#elif defined CONFIG_MACH_SUN9I
- sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB);
- sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB);
- sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
- sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
- sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
- sunxi_gpio_set_drv(SUNXI_GPN(1), 2);
-#else
-#error unsupported MACH_SUNXI
-#endif
-}
-
-static void rsb_set_clk(void)
-{
- struct sunxi_rsb_reg * const rsb =
- (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
- u32 div = 0;
- u32 cd_odly = 0;
-
- /* Source is Hosc24M, set RSB clk to 3Mhz */
- div = 24000000 / 3000000 / 2 - 1;
- cd_odly = div >> 1;
- if (!cd_odly)
- cd_odly = 1;
-
- writel((cd_odly << 8) | div, &rsb->ccr);
-}
-
-int rsb_init(void)
-{
- struct sunxi_rsb_reg * const rsb =
- (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
-
- /* Enable RSB and PIO clk, and de-assert their resets */
- prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB);
-
- /* Setup external pins */
- rsb_cfg_io();
-
- writel(RSB_CTRL_SOFT_RST, &rsb->ctrl);
- rsb_set_clk();
-
- return rsb_set_device_mode();
-}
-
-static int rsb_await_trans(void)
-{
- struct sunxi_rsb_reg * const rsb =
- (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
- unsigned long tmo = timer_get_us() + 1000000;
- u32 stat;
- int ret;
-
- while (1) {
- stat = readl(&rsb->stat);
- if (stat & RSB_STAT_LBSY_INT) {
- ret = -EBUSY;
- break;
- }
- if (stat & RSB_STAT_TERR_INT) {
- ret = -EIO;
- break;
- }
- if (stat & RSB_STAT_TOVER_INT) {
- ret = 0;
- break;
- }
- if (timer_get_us() > tmo) {
- ret = -ETIME;
- break;
- }
- }
- writel(stat, &rsb->stat); /* Clear status bits */
-
- return ret;
-}
-
-static int rsb_set_device_mode(void)
-{
- struct sunxi_rsb_reg * const rsb =
- (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
- unsigned long tmo = timer_get_us() + 1000000;
-
- writel(RSB_DMCR_DEVICE_MODE_START | RSB_DMCR_DEVICE_MODE_DATA,
- &rsb->dmcr);
-
- while (readl(&rsb->dmcr) & RSB_DMCR_DEVICE_MODE_START) {
- if (timer_get_us() > tmo)
- return -ETIME;
- }
-
- return rsb_await_trans();
-}
-
-static int rsb_do_trans(void)
-{
- struct sunxi_rsb_reg * const rsb =
- (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
-
- setbits_le32(&rsb->ctrl, RSB_CTRL_START_TRANS);
- return rsb_await_trans();
-}
-
-int rsb_set_device_address(u16 device_addr, u16 runtime_addr)
-{
- struct sunxi_rsb_reg * const rsb =
- (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
-
- writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr) |
- RSB_DEVADDR_DEVICE_ADDR(device_addr), &rsb->devaddr);
- writel(RSB_CMD_SET_RTSADDR, &rsb->cmd);
-
- return rsb_do_trans();
-}
-
-int rsb_write(const u16 runtime_device_addr, const u8 reg_addr, u8 data)
-{
- struct sunxi_rsb_reg * const rsb =
- (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
-
- writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_device_addr), &rsb->devaddr);
- writel(reg_addr, &rsb->addr);
- writel(data, &rsb->data);
- writel(RSB_CMD_BYTE_WRITE, &rsb->cmd);
-
- return rsb_do_trans();
-}
-
-int rsb_read(const u16 runtime_device_addr, const u8 reg_addr, u8 *data)
-{
- struct sunxi_rsb_reg * const rsb =
- (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
- int ret;
-
- writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_device_addr), &rsb->devaddr);
- writel(reg_addr, &rsb->addr);
- writel(RSB_CMD_BYTE_READ, &rsb->cmd);
-
- ret = rsb_do_trans();
- if (ret)
- return ret;
-
- *data = readl(&rsb->data) & 0xff;
-
- return 0;
-}
diff --git a/arch/arm/mach-tegra/dt-setup.c b/arch/arm/mach-tegra/dt-setup.c
index 602b20e..c114947 100644
--- a/arch/arm/mach-tegra/dt-setup.c
+++ b/arch/arm/mach-tegra/dt-setup.c
@@ -4,6 +4,9 @@
*/
#include <common.h>
+#include <fdtdec.h>
+#include <stdlib.h>
+#include <asm/arch-tegra/cboot.h>
#include <asm/arch-tegra/gpu.h>
/*
@@ -31,3 +34,147 @@
return 0;
}
+
+#if defined(CONFIG_ARM64)
+void ft_mac_address_setup(void *fdt)
+{
+ const void *cboot_fdt = (const void *)cboot_boot_x0;
+ uint8_t mac[ETH_ALEN], local_mac[ETH_ALEN];
+ const char *path;
+ int offset, err;
+
+ err = cboot_get_ethaddr(cboot_fdt, local_mac);
+ if (err < 0)
+ memset(local_mac, 0, ETH_ALEN);
+
+ path = fdt_get_alias(fdt, "ethernet");
+ if (!path)
+ return;
+
+ debug("ethernet alias found: %s\n", path);
+
+ offset = fdt_path_offset(fdt, path);
+ if (offset < 0) {
+ printf("ethernet alias points to absent node %s\n", path);
+ return;
+ }
+
+ if (is_valid_ethaddr(local_mac)) {
+ err = fdt_setprop(fdt, offset, "local-mac-address", local_mac,
+ ETH_ALEN);
+ if (!err)
+ debug("Local MAC address set: %pM\n", local_mac);
+ }
+
+ if (eth_env_get_enetaddr("ethaddr", mac)) {
+ if (memcmp(local_mac, mac, ETH_ALEN) != 0) {
+ err = fdt_setprop(fdt, offset, "mac-address", mac,
+ ETH_ALEN);
+ if (!err)
+ debug("MAC address set: %pM\n", mac);
+ }
+ }
+}
+
+static int ft_copy_carveout(void *dst, const void *src, const char *node)
+{
+ const char *names = "memory-region-names";
+ struct fdt_memory carveout;
+ unsigned int index = 0;
+ int err, offset, len;
+ const void *prop;
+
+ while (true) {
+ const char **compatibles = NULL;
+ unsigned int num_compatibles;
+ unsigned long flags;
+ char *copy = NULL;
+ const char *name;
+
+ err = fdtdec_get_carveout(src, node, "memory-region", index,
+ &carveout, &name, &compatibles,
+ &num_compatibles, &flags);
+ if (err < 0) {
+ if (err != -FDT_ERR_NOTFOUND)
+ printf("failed to get carveout for %s: %d\n",
+ node, err);
+ else
+ break;
+
+ return err;
+ }
+
+ if (name) {
+ const char *ptr = strchr(name, '@');
+
+ if (ptr) {
+ copy = strndup(name, ptr - name);
+ name = copy;
+ }
+ } else {
+ name = "carveout";
+ }
+
+ err = fdtdec_set_carveout(dst, node, "memory-region", index,
+ &carveout, name, compatibles,
+ num_compatibles, flags);
+ if (err < 0) {
+ printf("failed to set carveout for %s: %d\n", node,
+ err);
+ return err;
+ }
+
+ if (copy)
+ free(copy);
+
+ index++;
+ }
+
+ offset = fdt_path_offset(src, node);
+ if (offset < 0) {
+ debug("failed to find source offset for %s: %s\n", node,
+ fdt_strerror(err));
+ return err;
+ }
+
+ prop = fdt_getprop(src, offset, names, &len);
+ if (prop) {
+ offset = fdt_path_offset(dst, node);
+ if (offset < 0) {
+ debug("failed to find destination offset for %s: %s\n",
+ node, fdt_strerror(err));
+ return err;
+ }
+
+ err = fdt_setprop(dst, offset, "memory-region-names", prop,
+ len);
+ if (err < 0) {
+ debug("failed to copy \"%s\" property: %s\n", names,
+ fdt_strerror(err));
+ return err;
+ }
+ }
+
+ return 0;
+}
+
+void ft_carveout_setup(void *fdt, const char * const *nodes, unsigned int count)
+{
+ const void *cboot_fdt = (const void *)cboot_boot_x0;
+ unsigned int i;
+ int err;
+
+ for (i = 0; i < count; i++) {
+ printf("copying carveout for %s...\n", nodes[i]);
+
+ err = ft_copy_carveout(fdt, cboot_fdt, nodes[i]);
+ if (err < 0) {
+ if (err != -FDT_ERR_NOTFOUND)
+ printf("failed to copy carveout for %s: %d\n",
+ nodes[i], err);
+
+ continue;
+ }
+ }
+}
+#endif
diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c
index 3a6da6e..12ea324 100644
--- a/arch/microblaze/lib/bootm.c
+++ b/arch/microblaze/lib/bootm.c
@@ -75,7 +75,7 @@
static void boot_prep_linux(bootm_headers_t *images)
{
- if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
+ if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) {
debug("using: FDT\n");
if (image_setup_linux(images)) {
printf("FDT creation failed! hanging...");
diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig
index bdb23b5..cd85d1b 100644
--- a/arch/mips/mach-ath79/Kconfig
+++ b/arch/mips/mach-ath79/Kconfig
@@ -20,6 +20,7 @@
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
+ select USB_EHCI_IS_TDI if USB_EHCI_HCD
help
This supports QCA/Atheros ar934x family SOCs.
diff --git a/arch/nds32/lib/bootm.c b/arch/nds32/lib/bootm.c
index 1c7f785..71ebfb4 100644
--- a/arch/nds32/lib/bootm.c
+++ b/arch/nds32/lib/bootm.c
@@ -69,7 +69,7 @@
debug("## Transferring control to Linux (at address %08lx) ...\n",
(ulong)theKernel);
- if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
+ if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) {
#ifdef CONFIG_OF_LIBFDT
debug("using: FDT\n");
if (image_setup_linux(images)) {
@@ -110,7 +110,7 @@
#endif
}
cleanup_before_linux();
- if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len)
+ if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len)
theKernel(0, machid, (unsigned long)images->ft_addr);
else
theKernel(0, machid, bd->bi_boot_params);
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index 8e49b6d..8d90c5e 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -17,9 +17,6 @@
* The variables here must be stored in the data section since they are used
* before the bss section is available.
*/
-#ifdef CONFIG_OF_PRIOR_STAGE
-phys_addr_t prior_stage_fdt_address __section(".data");
-#endif
#ifndef CONFIG_XIP
u32 hart_lottery __section(".data") = 0;
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 308b0a9..76850ec 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -142,11 +142,6 @@
bnez tp, secondary_hart_loop
#endif
-#ifdef CONFIG_OF_PRIOR_STAGE
- la t0, prior_stage_fdt_address
- SREG s1, 0(t0)
-#endif
-
jal board_init_f_init_reserve
SREG s1, GD_FIRMWARE_FDT_ADDR(gp)
diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi
index d26cfdb..5757ef6 100644
--- a/arch/riscv/dts/binman.dtsi
+++ b/arch/riscv/dts/binman.dtsi
@@ -48,7 +48,7 @@
};
};
-#ifndef CONFIG_OF_PRIOR_STAGE
+#ifndef CONFIG_OF_BOARD
@fdt-SEQ {
description = "NAME";
type = "flat_dt";
@@ -60,7 +60,7 @@
configurations {
default = "conf-1";
-#ifndef CONFIG_OF_PRIOR_STAGE
+#ifndef CONFIG_OF_BOARD
@conf-SEQ {
#else
conf-1 {
@@ -68,7 +68,7 @@
description = "NAME";
firmware = "opensbi";
loadables = "uboot";
-#ifndef CONFIG_OF_PRIOR_STAGE
+#ifndef CONFIG_OF_BOARD
fdt = "fdt-SEQ";
#endif
};
diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
index acf5a96..3540773 100644
--- a/arch/riscv/include/asm/io.h
+++ b/arch/riscv/include/asm/io.h
@@ -44,15 +44,15 @@
* read/writes. We define __arch_*[bl] here, and leave __arch_*w
* to the architecture specific code.
*/
-#define __arch_getb(a) (*(unsigned char *)(a))
-#define __arch_getw(a) (*(unsigned short *)(a))
-#define __arch_getl(a) (*(unsigned int *)(a))
-#define __arch_getq(a) (*(unsigned long long *)(a))
+#define __arch_getb(a) (*(volatile unsigned char *)(a))
+#define __arch_getw(a) (*(volatile unsigned short *)(a))
+#define __arch_getl(a) (*(volatile unsigned int *)(a))
+#define __arch_getq(a) (*(volatile unsigned long long *)(a))
-#define __arch_putb(v, a) (*(unsigned char *)(a) = (v))
-#define __arch_putw(v, a) (*(unsigned short *)(a) = (v))
-#define __arch_putl(v, a) (*(unsigned int *)(a) = (v))
-#define __arch_putq(v, a) (*(unsigned long long *)(a) = (v))
+#define __arch_putb(v, a) (*(volatile unsigned char *)(a) = (v))
+#define __arch_putw(v, a) (*(volatile unsigned short *)(a) = (v))
+#define __arch_putl(v, a) (*(volatile unsigned int *)(a) = (v))
+#define __arch_putq(v, a) (*(volatile unsigned long long *)(a) = (v))
#define __raw_writeb(v, a) __arch_putb(v, a)
#define __raw_writew(v, a) __arch_putw(v, a)
diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c
index ff1bdf7..2e1e286 100644
--- a/arch/riscv/lib/bootm.c
+++ b/arch/riscv/lib/bootm.c
@@ -64,7 +64,7 @@
static void boot_prep_linux(bootm_headers_t *images)
{
- if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
+ if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) {
#ifdef CONFIG_OF_LIBFDT
debug("using: FDT\n");
if (image_setup_linux(images)) {
@@ -96,7 +96,7 @@
announce_and_cleanup(fake);
if (!fake) {
- if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
+ if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) {
#ifdef CONFIG_SMP
ret = smp_call_function(images->ep,
(ulong)images->ft_addr, 0, 0);
diff --git a/arch/riscv/lib/fdt_fixup.c b/arch/riscv/lib/fdt_fixup.c
index 61cf893..36c16e9 100644
--- a/arch/riscv/lib/fdt_fixup.c
+++ b/arch/riscv/lib/fdt_fixup.c
@@ -75,7 +75,7 @@
pmp_mem.start = addr;
pmp_mem.end = addr + size - 1;
err = fdtdec_add_reserved_memory(dst, basename, &pmp_mem,
- &phandle, false);
+ NULL, 0, &phandle, 0);
if (err < 0 && err != -FDT_ERR_EXISTS) {
log_err("failed to add reserved memory: %d\n", err);
return err;
diff --git a/arch/sandbox/lib/Makefile b/arch/sandbox/lib/Makefile
index b4ff717..a2bc5a7 100644
--- a/arch/sandbox/lib/Makefile
+++ b/arch/sandbox/lib/Makefile
@@ -5,7 +5,7 @@
# (C) Copyright 2002-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-obj-y += interrupts.o sections.o
+obj-y += fdt_fixup.o interrupts.o sections.o
obj-$(CONFIG_PCI) += pci_io.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-$(CONFIG_CMD_BOOTZ) += bootm.o
diff --git a/arch/sandbox/lib/fdt_fixup.c b/arch/sandbox/lib/fdt_fixup.c
new file mode 100644
index 0000000..a646f20
--- /dev/null
+++ b/arch/sandbox/lib/fdt_fixup.c
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#define LOG_CATEGORY LOGC_ARCH
+
+#include <common.h>
+#include <fdt_support.h>
+#include <log.h>
+
+#if defined(__riscv)
+int arch_fixup_fdt(void *blob)
+{
+ int ret;
+
+ ret = fdt_find_or_add_subnode(blob, 0, "chosen");;
+ if (ret < 0)
+ goto err;
+ ret = fdt_setprop_u32(blob, ret, "boot-hartid", 1);
+ if (ret < 0)
+ goto err;
+ return 0;
+err:
+ log_err("Setting /chosen/boot-hartid failed: %s\n", fdt_strerror(ret));
+ return ret;
+}
+#endif
diff --git a/arch/x86/config.mk b/arch/x86/config.mk
index 7a82425..589f2ae 100644
--- a/arch/x86/config.mk
+++ b/arch/x86/config.mk
@@ -37,7 +37,7 @@
LDFLAGS_EFI_PAYLOAD := -Bsymbolic -Bsymbolic-functions -shared --no-undefined -s
OBJCOPYFLAGS_EFI := -j .text -j .sdata -j .data -j .dynamic -j .dynsym \
- -j .rel -j .rela -j .reloc
+ -j .rel -j .rela -j .reloc --strip-all
# Compiler flags to be added when building UEFI applications
CFLAGS_EFI := -fpic -fshort-wchar
@@ -65,7 +65,7 @@
ifeq ($(CONFIG_EFI_APP),y)
PLATFORM_CPPFLAGS += $(CFLAGS_EFI)
-LDFLAGS_FINAL += -znocombreloc -shared -s
+LDFLAGS_FINAL += -znocombreloc -shared
LDSCRIPT := $(LDSCRIPT_EFI)
else
diff --git a/arch/x86/cpu/efi/payload.c b/arch/x86/cpu/efi/payload.c
index 9a73b76..3a9f7d7 100644
--- a/arch/x86/cpu/efi/payload.c
+++ b/arch/x86/cpu/efi/payload.c
@@ -280,15 +280,24 @@
}
efi_info->efi_memdesc_size = map->desc_size;
efi_info->efi_memdesc_version = map->version;
- efi_info->efi_memmap = (u32)(map->desc);
+ efi_info->efi_memmap = (ulong)(map->desc);
efi_info->efi_memmap_size = size - sizeof(struct efi_entry_memmap);
#ifdef CONFIG_EFI_STUB_64BIT
efi_info->efi_systab_hi = table->sys_table >> 32;
- efi_info->efi_memmap_hi = (u64)(u32)(map->desc) >> 32;
+ efi_info->efi_memmap_hi = (u64)(ulong)map->desc >> 32;
signature = EFI64_LOADER_SIGNATURE;
#else
signature = EFI32_LOADER_SIGNATURE;
#endif
memcpy(&efi_info->efi_loader_signature, signature, 4);
}
+
+void efi_show_bdinfo(void)
+{
+ struct efi_entry_systable *table = NULL;
+ int size, ret;
+
+ ret = efi_info_get(EFIET_SYS_TABLE, (void **)&table, &size);
+ bdinfo_print_num_l("efi_table", (ulong)table);
+}
diff --git a/arch/x86/include/asm/efi.h b/arch/x86/include/asm/efi.h
new file mode 100644
index 0000000..dfd858b
--- /dev/null
+++ b/arch/x86/include/asm/efi.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright Google LLC
+ */
+
+#ifndef _ASM_EFI_H_
+#define _ASM_EFI_H_
+
+struct efi_info;
+struct screen_info;
+
+/**
+ * setup_video() - Set up the screen info in the x86 setup
+ *
+ * This is needed so Linux can use the display (when U-Boot is an EFI payload)
+ *
+ * @efi_info: Pointer to place to put the screen info in the x86 setup base
+ */
+void setup_video(struct screen_info *screen_info);
+
+/**
+ * setup_efi_info() - Set up the EFI info needed by Linux to boot
+ *
+ * This writes a suitable signature, table pointers, memory-map pointer, etc.
+ * These are needed for Linux to boot from U-Boot (when U-Boot is an EFI
+ * payload).
+ *
+ * @efi_info: Pointer to place to put the EFI info in the x86 setup base
+ */
+void setup_efi_info(struct efi_info *efi_info);
+
+/**
+ * efi_show_bdinfo() - Show information about EFI for the 'bdinfo' command
+ *
+ * This looks up the EFI table pointer and shows related info
+ */
+void efi_show_bdinfo(void);
+
+#endif
diff --git a/arch/x86/include/asm/zimage.h b/arch/x86/include/asm/zimage.h
index 6679767..fa6e7f7 100644
--- a/arch/x86/include/asm/zimage.h
+++ b/arch/x86/include/asm/zimage.h
@@ -72,7 +72,4 @@
*/
void zimage_dump(struct boot_params *base_ptr);
-void setup_video(struct screen_info *screen_info);
-void setup_efi_info(struct efi_info *efi_info);
-
#endif
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index 65d9b3b..18757b2 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -3,6 +3,7 @@
# (C) Copyright 2002-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+obj-y += bdinfo.o
ifndef CONFIG_X86_64
ifndef CONFIG_TPL_BUILD
obj-y += bios.o
diff --git a/arch/x86/lib/bdinfo.c b/arch/x86/lib/bdinfo.c
new file mode 100644
index 0000000..0cb79b0
--- /dev/null
+++ b/arch/x86/lib/bdinfo.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * x86-specific information for the 'bd' command
+ *
+ * Copyright 2021 Google LLC
+ */
+
+#include <common.h>
+#include <efi.h>
+#include <init.h>
+#include <asm/efi.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void arch_print_bdinfo(void)
+{
+ bdinfo_print_num_l("prev table", gd->arch.table);
+
+ if (IS_ENABLED(CONFIG_EFI_STUB))
+ efi_show_bdinfo();
+}
diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c
index 9938c80..7ce0222 100644
--- a/arch/x86/lib/zimage.c
+++ b/arch/x86/lib/zimage.c
@@ -29,6 +29,7 @@
#include <asm/byteorder.h>
#include <asm/bootm.h>
#include <asm/bootparam.h>
+#include <asm/efi.h>
#include <asm/global_data.h>
#ifdef CONFIG_SYS_COREBOOT
#include <asm/arch/timestamp.h>
diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c b/board/AndesTech/ax25-ae350/ax25-ae350.c
index 15da58a..b28894e 100644
--- a/board/AndesTech/ax25-ae350/ax25-ae350.c
+++ b/board/AndesTech/ax25-ae350/ax25-ae350.c
@@ -21,7 +21,6 @@
DECLARE_GLOBAL_DATA_PTR;
-extern phys_addr_t prior_stage_fdt_address;
/*
* Miscellaneous platform dependent initializations
*/
@@ -57,7 +56,13 @@
void *board_fdt_blob_setup(void)
{
+#if CONFIG_IS_ENABLED(OF_BOARD)
+ return (void *)(ulong)gd->arch.firmware_fdt_addr;
+#elif CONFIG_IS_ENABLED(OF_SEPARATE)
return (void *)CONFIG_SYS_FDT_BASE;
+#else
+ return NULL;
+#endif
}
int smc_init(void)
diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c
index 428cd23..2202eb8 100644
--- a/board/CZ.NIC/turris_mox/turris_mox.c
+++ b/board/CZ.NIC/turris_mox/turris_mox.c
@@ -359,20 +359,22 @@
int misc_init_r(void)
{
- int ret;
- u8 mac1[6], mac2[6];
+ u8 mac[2][6];
+ int i, ret;
- ret = mbox_sp_get_board_info(NULL, mac1, mac2, NULL, NULL);
+ ret = mbox_sp_get_board_info(NULL, mac[0], mac[1], NULL, NULL);
if (ret < 0) {
printf("Cannot read data from OTP!\n");
return 0;
}
- if (is_valid_ethaddr(mac1) && !env_get("ethaddr"))
- eth_env_set_enetaddr("ethaddr", mac1);
+ for (i = 0; i < 2; ++i) {
+ u8 oldmac[6];
- if (is_valid_ethaddr(mac2) && !env_get("eth1addr"))
- eth_env_set_enetaddr("eth1addr", mac2);
+ if (is_valid_ethaddr(mac[i]) &&
+ !eth_env_get_enetaddr_by_index("eth", i, oldmac))
+ eth_env_set_enetaddr_by_index("eth", i, mac[i]);
+ }
return 0;
}
@@ -485,44 +487,34 @@
}
}
-static void mox_print_info(void)
+int show_board_info(void)
{
- int ret, board_version, ram_size;
- u64 serial_number;
+ int i, ret, board_version, ram_size, is_sd;
const char *pub_key;
+ const u8 *topology;
+ u64 serial_number;
+
+ printf("Model: CZ.NIC Turris Mox Board\n");
ret = mbox_sp_get_board_info(&serial_number, NULL, NULL, &board_version,
&ram_size);
- if (ret < 0)
- return;
-
- printf("Turris Mox:\n");
- printf(" Board version: %i\n", board_version);
- printf(" RAM size: %i MiB\n", ram_size);
- printf(" Serial Number: %016llX\n", serial_number);
+ if (ret < 0) {
+ printf(" Cannot read board info: %i\n", ret);
+ } else {
+ printf(" Board version: %i\n", board_version);
+ printf(" RAM size: %i MiB\n", ram_size);
+ printf(" Serial Number: %016llX\n", serial_number);
+ }
pub_key = mox_sp_get_ecdsa_public_key();
if (pub_key)
printf(" ECDSA Public Key: %s\n", pub_key);
else
- printf("Cannot read ECDSA Public Key\n");
-}
-
-int last_stage_init(void)
-{
- int ret, i;
- const u8 *topology;
- int is_sd;
- struct mii_dev *bus;
- struct gpio_desc reset_gpio = {};
-
- mox_print_info();
+ printf(" Cannot read ECDSA Public Key\n");
ret = mox_get_topology(&topology, &module_count, &is_sd);
- if (ret) {
+ if (ret)
printf("Cannot read module topology!\n");
- return 0;
- }
printf(" SD/eMMC version: %s\n", is_sd ? "SD" : "eMMC");
@@ -554,8 +546,7 @@
}
}
- /* now check if modules are connected in supported mode */
-
+ /* check if modules are connected in supported mode */
for (i = 0; i < module_count; ++i) {
switch (topology[i]) {
case MOX_MODULE_SFP:
@@ -616,10 +607,19 @@
}
}
- /* now configure modules */
+ if (module_count)
+ printf("\n");
+
+ return 0;
+}
+
+int last_stage_init(void)
+{
+ struct gpio_desc reset_gpio = {};
+ /* configure modules */
if (get_reset_gpio(&reset_gpio) < 0)
- return 0;
+ goto handle_reset_btn;
if (peridot > 0) {
if (configure_peridots(&reset_gpio) < 0) {
@@ -633,16 +633,19 @@
mdelay(50);
}
+ /*
+ * check if the addresses are set by reading Scratch & Misc register
+ * 0x70 of Peridot (and potentially Topaz) modules
+ */
if (peridot || topaz) {
- /*
- * now check if the addresses are set by reading Scratch & Misc
- * register 0x70 of Peridot (and potentially Topaz) modules
- */
+ struct mii_dev *bus;
bus = miiphy_get_dev_by_name("neta@30000");
if (!bus) {
printf("Cannot get MDIO bus device!\n");
} else {
+ int i;
+
for (i = 0; i < peridot; ++i)
check_switch_address(bus, 0x10 + i);
@@ -653,8 +656,7 @@
}
}
- printf("\n");
-
+handle_reset_btn:
handle_reset_button();
return 0;
diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c
index a48e1f5..39051a8 100644
--- a/board/CZ.NIC/turris_omnia/turris_omnia.c
+++ b/board/CZ.NIC/turris_omnia/turris_omnia.c
@@ -468,7 +468,7 @@
return dev;
}
-int checkboard(void)
+int show_board_info(void)
{
u32 version_num, serial_num;
int err = 1;
@@ -496,7 +496,7 @@
}
out:
- printf("Turris Omnia:\n");
+ printf("Model: Turris Omnia\n");
printf(" RAM size: %i MiB\n", omnia_get_ram_size_gb() * 1024);
if (err)
printf(" Serial Number: unknown\n");
@@ -518,6 +518,15 @@
}
}
+static void set_mac_if_invalid(int i, u8 *mac)
+{
+ u8 oldmac[6];
+
+ if (is_valid_ethaddr(mac) &&
+ !eth_env_get_enetaddr_by_index("eth", i, oldmac))
+ eth_env_set_enetaddr_by_index("eth", i, mac);
+}
+
int misc_init_r(void)
{
int err;
@@ -550,18 +559,11 @@
mac[4] = mac1[2];
mac[5] = mac1[3];
- if (is_valid_ethaddr(mac))
- eth_env_set_enetaddr("eth1addr", mac);
-
+ set_mac_if_invalid(1, mac);
increment_mac(mac);
-
- if (is_valid_ethaddr(mac))
- eth_env_set_enetaddr("eth2addr", mac);
-
+ set_mac_if_invalid(2, mac);
increment_mac(mac);
-
- if (is_valid_ethaddr(mac))
- eth_env_set_enetaddr("ethaddr", mac);
+ set_mac_if_invalid(0, mac);
out:
return 0;
diff --git a/board/Marvell/mvebu_armada-8k/board.c b/board/Marvell/mvebu_armada-8k/board.c
index 7da5d9f..77c7dd7 100644
--- a/board/Marvell/mvebu_armada-8k/board.c
+++ b/board/Marvell/mvebu_armada-8k/board.c
@@ -35,17 +35,6 @@
#define I2C_IO_REG_CL ((1 << I2C_IO_REG_0_USB_H0_CL) | \
(1 << I2C_IO_REG_0_USB_H1_CL))
-/*
- * Information specific to the iEi Puzzle-M801 board.
- */
-
-/* Internal configuration registers */
-#define CP1_CONF_REG_BASE 0xf4440000
-#define CONF_REG_MPP0 0x0
-#define CONF_REG_MPP1 0x4
-#define CONF_REG_MPP2 0x8
-#define CONF_REG_MPP3 0xC
-
static int usb_enabled = 0;
/* Board specific xHCI dis-/enable code */
@@ -153,14 +142,7 @@
int board_early_init_f(void)
{
- /* Initialize some platform specific memory locations */
- if (of_machine_is_compatible("marvell,armada8040-puzzle-m801")) {
- /* MPP setup */
- writel(0x00444444, CP1_CONF_REG_BASE + CONF_REG_MPP0);
- writel(0x00000000, CP1_CONF_REG_BASE + CONF_REG_MPP1);
- writel(0x00000000, CP1_CONF_REG_BASE + CONF_REG_MPP2);
- writel(0x08888000, CP1_CONF_REG_BASE + CONF_REG_MPP3);
- }
+ /* Nothing to do yet */
return 0;
}
diff --git a/board/alliedtelesis/x530/kwbimage.cfg b/board/alliedtelesis/x530/kwbimage.cfg
deleted file mode 100644
index f58d388..0000000
--- a/board/alliedtelesis/x530/kwbimage.cfg
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Copyright (C) 2017 Allied Telesis Labs
-#
-
-# Armada XP uses version 1 image format
-VERSION 1
-
-# Boot Media configurations
-BOOT_FROM spi
-
-# Binary Header (bin_hdr) with DDR3 training code
-BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
diff --git a/board/armltd/total_compute/total_compute.c b/board/armltd/total_compute/total_compute.c
index b7eaab0..b7772f7 100644
--- a/board/armltd/total_compute/total_compute.c
+++ b/board/armltd/total_compute/total_compute.c
@@ -59,6 +59,9 @@
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+
return 0;
}
diff --git a/board/broadcom/bcmstb/bcmstb.c b/board/broadcom/bcmstb/bcmstb.c
index 276e59b..723ebda 100644
--- a/board/broadcom/bcmstb/bcmstb.c
+++ b/board/broadcom/bcmstb/bcmstb.c
@@ -130,3 +130,9 @@
return 0;
}
+
+void *board_fdt_blob_setup(void)
+{
+ /* Stored the DTB address there during our init */
+ return (void *)prior_stage_fdt_address;
+}
diff --git a/board/compulab/imx8mm-cl-iot-gate/Kconfig b/board/compulab/imx8mm-cl-iot-gate/Kconfig
index 30760cb..e6ceb91 100644
--- a/board/compulab/imx8mm-cl-iot-gate/Kconfig
+++ b/board/compulab/imx8mm-cl-iot-gate/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_IMX8MM_CL_IOT_GATE
+if TARGET_IMX8MM_CL_IOT_GATE || TARGET_IMX8MM_CL_IOT_GATE_OPTEE
config SYS_BOARD
default "imx8mm-cl-iot-gate"
diff --git a/board/compulab/imx8mm-cl-iot-gate/MAINTAINERS b/board/compulab/imx8mm-cl-iot-gate/MAINTAINERS
index 9c6b170..9db1fb6 100644
--- a/board/compulab/imx8mm-cl-iot-gate/MAINTAINERS
+++ b/board/compulab/imx8mm-cl-iot-gate/MAINTAINERS
@@ -4,3 +4,4 @@
F: board/compulab/imx8mm-cl-iot-gate/
F: include/configs/imx8mm-cl-iot-gate.h
F: configs/imx8mm-cl-iot-gate_defconfig
+F: configs/imx8mm-cl-iot-gate-optee_defconfig
diff --git a/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c b/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c
index eabcc84..cd15410 100644
--- a/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c
+++ b/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <env.h>
+#include <hang.h>
#include <init.h>
#include <miiphy.h>
#include <netdev.h>
@@ -14,8 +15,32 @@
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
+#include "ddr/ddr.h"
+
DECLARE_GLOBAL_DATA_PTR;
+int board_phys_sdram_size(phys_size_t *size)
+{
+ struct lpddr4_tcm_desc *lpddr4_tcm_desc =
+ (struct lpddr4_tcm_desc *)TCM_DATA_CFG;
+
+ switch (lpddr4_tcm_desc->size) {
+ case 4096:
+ case 2048:
+ case 1024:
+ *size = (1L << 20) * lpddr4_tcm_desc->size;
+ break;
+ default:
+ printf("%s: DRAM size %uM is not supported\n",
+ __func__,
+ lpddr4_tcm_desc->size);
+ hang();
+ break;
+ };
+
+ return 0;
+}
+
static int setup_fec(void)
{
if (IS_ENABLED(CONFIG_FEC_MXC)) {
diff --git a/board/congatec/cgtqmx8/spl.c b/board/congatec/cgtqmx8/spl.c
index 2a5d4c1..37b7221 100644
--- a/board/congatec/cgtqmx8/spl.c
+++ b/board/congatec/cgtqmx8/spl.c
@@ -32,7 +32,7 @@
offset = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "nxp,imx8-pd");
while (offset != -FDT_ERR_NOTFOUND) {
lists_bind_fdt(gd->dm_root, offset_to_ofnode(offset),
- NULL, true);
+ NULL, NULL, true);
offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset,
"nxp,imx8-pd");
}
diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c
index 4b3167f..a8402e2 100644
--- a/board/dhelectronics/dh_stm32mp1/board.c
+++ b/board/dhelectronics/dh_stm32mp1/board.c
@@ -591,12 +591,6 @@
/* board dependent setup after realloc */
int board_init(void)
{
- /* address of boot parameters */
- gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
-
- if (CONFIG_IS_ENABLED(DM_GPIO_HOG))
- gpio_hog_probe_all();
-
board_key_check();
#ifdef CONFIG_DM_REGULATOR
diff --git a/board/emulation/qemu-riscv/qemu-riscv.c b/board/emulation/qemu-riscv/qemu-riscv.c
index dcfd3f2..2a26e26 100644
--- a/board/emulation/qemu-riscv/qemu-riscv.c
+++ b/board/emulation/qemu-riscv/qemu-riscv.c
@@ -14,6 +14,8 @@
#include <virtio_types.h>
#include <virtio.h>
+DECLARE_GLOBAL_DATA_PTR;
+
int board_init(void)
{
/*
@@ -69,3 +71,9 @@
return 0;
}
#endif
+
+void *board_fdt_blob_setup(void)
+{
+ /* Stored the DTB address there during our init */
+ return (void *)(ulong)gd->arch.firmware_fdt_addr;
+}
diff --git a/board/engicam/stm32mp1/stm32mp1.c b/board/engicam/stm32mp1/stm32mp1.c
index 8bf9c9c..20d8603 100644
--- a/board/engicam/stm32mp1/stm32mp1.c
+++ b/board/engicam/stm32mp1/stm32mp1.c
@@ -40,9 +40,6 @@
/* board dependent setup after realloc */
int board_init(void)
{
- /* address of boot parameters */
- gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
-
if (IS_ENABLED(CONFIG_DM_REGULATOR))
regulators_enable_boot_on(_DEBUG);
diff --git a/board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg b/board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg
index b2920b4..4c3ecf5 100644
--- a/board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg
+++ b/board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg
@@ -7,4 +7,4 @@
ROM_VERSION v2
BOOT_FROM sd
-LOADER mkimage.flash.mkimage 0x920000
+LOADER u-boot-spl-ddr.bin 0x920000
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c
index 7962982..8cf7914 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -39,41 +39,6 @@
struct ventana_board_info ventana_info;
static int board_type;
-#ifdef CONFIG_USB_EHCI_MX6
-/* toggle USB_HUB_RST# for boards that have it; it is not defined in dt */
-int board_ehci_hcd_init(int port)
-{
- int gpio;
-
- /* USB HUB is always on P1 */
- if (port == 0)
- return 0;
-
- /* Reset USB HUB */
- switch (board_type) {
- case GW53xx:
- case GW552x:
- case GW5906:
- gpio = (IMX_GPIO_NR(1, 9));
- break;
- case GW54proto:
- case GW54xx:
- gpio = (IMX_GPIO_NR(1, 16));
- break;
- default:
- return 0;
- }
-
- /* request and toggle hub rst */
- gpio_request(gpio, "usb_hub_rst#");
- gpio_direction_output(gpio, 0);
- mdelay(2);
- gpio_set_value(gpio, 1);
-
- return 0;
-}
-#endif /* CONFIG_USB_EHCI_MX6 */
-
/* configure eth0 PHY board-specific LED behavior */
int board_phy_config(struct phy_device *phydev)
{
@@ -158,25 +123,54 @@
imx_enable_hdmi_phy();
}
-static int detect_i2c(struct display_info_t const *dev)
+static int detect_lvds(struct display_info_t const *dev)
{
+ /* only the following boards support LVDS connectors */
+ switch (board_type) {
+ case GW52xx:
+ case GW53xx:
+ case GW54xx:
+ case GW560x:
+ case GW5905:
+ case GW5909:
+ break;
+ default:
+ return 0;
+ }
+
return i2c_set_bus_num(dev->bus) == 0 &&
i2c_probe(dev->addr) == 0;
}
static void enable_lvds(struct display_info_t const *dev)
{
- struct iomuxc *iomux = (struct iomuxc *)
- IOMUXC_BASE_ADDR;
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
u32 reg = readl(&iomux->gpr[2]);
reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
writel(reg, &iomux->gpr[2]);
- /* Enable Backlight */
- gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
- gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
+ /* Configure GPIO */
+ switch (board_type) {
+ case GW52xx:
+ case GW53xx:
+ case GW54xx:
+ if (!strncmp(dev->mode.name, "Hannstar", 8)) {
+ SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
+ gpio_request(IMX_GPIO_NR(1, 10), "cabc");
+ gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
+ } else if (!strncmp(dev->mode.name, "DLC", 3)) {
+ SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
+ gpio_request(IMX_GPIO_NR(1, 10), "touch_rst#");
+ gpio_direction_output(IMX_GPIO_NR(1, 10), 1);
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Configure backlight */
gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
@@ -208,7 +202,7 @@
.bus = 2,
.addr = 0x4,
.pixfmt = IPU_PIX_FMT_LVDS666,
- .detect = detect_i2c,
+ .detect = detect_lvds,
.enable = enable_lvds,
.mode = {
.name = "Hannstar-XGA",
@@ -228,7 +222,7 @@
/* DLC700JMG-T-4 */
.bus = 2,
.addr = 0x38,
- .detect = NULL,
+ .detect = detect_lvds,
.enable = enable_lvds,
.pixfmt = IPU_PIX_FMT_LVDS666,
.mode = {
@@ -247,9 +241,9 @@
.vmode = FB_VMODE_NONINTERLACED
} }, {
/* DLC0700XDP21LF-C-1 */
- .bus = 0,
- .addr = 0,
- .detect = NULL,
+ .bus = 2,
+ .addr = 0x38,
+ .detect = detect_lvds,
.enable = enable_lvds,
.pixfmt = IPU_PIX_FMT_LVDS666,
.mode = {
@@ -270,7 +264,7 @@
/* DLC800FIG-T-3 */
.bus = 2,
.addr = 0x14,
- .detect = NULL,
+ .detect = detect_lvds,
.enable = enable_lvds,
.pixfmt = IPU_PIX_FMT_LVDS666,
.mode = {
@@ -290,7 +284,7 @@
} }, {
.bus = 2,
.addr = 0x5d,
- .detect = detect_i2c,
+ .detect = detect_lvds,
.enable = enable_lvds,
.pixfmt = IPU_PIX_FMT_LVDS666,
.mode = {
@@ -358,10 +352,6 @@
| (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
writel(reg, &iomux->gpr[3]);
-
- /* LVDS Backlight GPIO on LVDS connector - output low */
- SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
- gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
}
#endif /* CONFIG_VIDEO_IPUV3 */
@@ -1048,6 +1038,14 @@
#endif
/*
+ * remove reset gpio control as we configure the PHY registers
+ * for internal delay, LED config, and clock config in the bootloader
+ */
+ i = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-fec");
+ if (i)
+ fdt_delprop(blob, i, "phy-reset-gpios");
+
+ /*
* Peripheral Config:
* remove nodes by alias path if EEPROM config tells us the
* peripheral is not loaded on the board.
diff --git a/board/gateworks/venice/gsc.c b/board/gateworks/venice/gsc.c
index 7d6acd7..065d1fb 100644
--- a/board/gateworks/venice/gsc.c
+++ b/board/gateworks/venice/gsc.c
@@ -527,6 +527,9 @@
printf("%d\n", buf[0] | buf[1] << 8 | buf[2] << 16 | buf[3] << 24);
}
+ /* Display hwmon */
+ gsc_hwmon();
+
return 0;
}
diff --git a/board/gateworks/venice/imx8mm_venice.c b/board/gateworks/venice/imx8mm_venice.c
index 2a97d55..4e05802 100644
--- a/board/gateworks/venice/imx8mm_venice.c
+++ b/board/gateworks/venice/imx8mm_venice.c
@@ -114,7 +114,8 @@
led_default_state();
/* Set board serial/model */
- env_set_ulong("serial#", gsc_get_serial());
+ if (!env_get("serial#"))
+ env_set_ulong("serial#", gsc_get_serial());
env_set("model", gsc_get_model());
/* Set fdt_file vars */
@@ -155,8 +156,26 @@
int ft_board_setup(void *blob, struct bd_info *bd)
{
+ int off;
+
/* set board model dt prop */
fdt_setprop_string(blob, 0, "board", gsc_get_model());
+ /* update temp thresholds */
+ off = fdt_path_offset(blob, "/thermal-zones/cpu-thermal/trips");
+ if (off >= 0) {
+ int minc, maxc, prop;
+
+ get_cpu_temp_grade(&minc, &maxc);
+ fdt_for_each_subnode(prop, blob, off) {
+ const char *type = fdt_getprop(blob, prop, "type", NULL);
+
+ if (type && (!strcmp("critical", type)))
+ fdt_setprop_u32(blob, prop, "temperature", maxc * 1000);
+ else if (type && (!strcmp("passive", type)))
+ fdt_setprop_u32(blob, prop, "temperature", (maxc - 10) * 1000);
+ }
+ }
+
return 0;
}
diff --git a/board/keymile/km83xx/MAINTAINERS b/board/keymile/km83xx/MAINTAINERS
index 9268719..9fd5a85 100644
--- a/board/keymile/km83xx/MAINTAINERS
+++ b/board/keymile/km83xx/MAINTAINERS
@@ -1,5 +1,5 @@
KM83XX BOARD
-M: Holger Brunck <holger.brunck@hitachi-powergrids.com>
+M: Holger Brunck <holger.brunck@hitachienergy.com>
M: Heiko Schocher <hs@denx.de>
S: Maintained
F: board/keymile/km83xx/
diff --git a/board/keymile/km_arm/MAINTAINERS b/board/keymile/km_arm/MAINTAINERS
index 8da58da..bc6858b 100644
--- a/board/keymile/km_arm/MAINTAINERS
+++ b/board/keymile/km_arm/MAINTAINERS
@@ -1,5 +1,5 @@
KM_ARM BOARD
-M: Valentin Longchamp <valentin.longchamp@hitachi-powergrids.com>
+M: Holger Brunck <holger.brunck@hitachienergy.com>
S: Maintained
F: board/keymile/km_arm/
F: include/configs/km_kirkwood.h
diff --git a/board/keymile/pg-wcom-ls102xa/MAINTAINERS b/board/keymile/pg-wcom-ls102xa/MAINTAINERS
index 26b2023..966c88b 100644
--- a/board/keymile/pg-wcom-ls102xa/MAINTAINERS
+++ b/board/keymile/pg-wcom-ls102xa/MAINTAINERS
@@ -1,7 +1,6 @@
Hitachi Power Grids LS102XA BOARD
-M: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
-M: Rainer Boschung <rainer.boschung@hitachi-powergrids.com>
-M: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com>
+M: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
+M: Rainer Boschung <rainer.boschung@hitachienergy.com>
S: Maintained
F: board/keymile/pg-wcom-ls102xa/
F: include/configs/km/pg-wcom-ls102xa.h
diff --git a/board/keymile/secu1/MAINTAINERS b/board/keymile/secu1/MAINTAINERS
index 3e40eef..833b3fd 100644
--- a/board/keymile/secu1/MAINTAINERS
+++ b/board/keymile/secu1/MAINTAINERS
@@ -1,5 +1,5 @@
Hitachi Power Grids SECU1 BOARD
-M: Holger Brunck <holger.brunck@hitachi-powergrids.com>
+M: Holger Brunck <holger.brunck@hitachienergy.com>
S: Maintained
F: include/configs/socfpga_arria5_secu1.h
F: configs/socfpga_secu1_defconfig
diff --git a/board/kontron/sl-mx6ul/Kconfig b/board/kontron/sl-mx6ul/Kconfig
new file mode 100644
index 0000000..4e58de2
--- /dev/null
+++ b/board/kontron/sl-mx6ul/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_KONTRON_MX6UL
+
+config SYS_BOARD
+ string
+ default "sl-mx6ul"
+
+config SYS_VENDOR
+ string
+ default "kontron"
+
+config SYS_CONFIG_NAME
+ string
+ default "kontron-sl-mx6ul"
+
+endif
diff --git a/board/kontron/sl-mx6ul/MAINTAINERS b/board/kontron/sl-mx6ul/MAINTAINERS
new file mode 100644
index 0000000..0f8b551
--- /dev/null
+++ b/board/kontron/sl-mx6ul/MAINTAINERS
@@ -0,0 +1,9 @@
+Kontron SL/BL i.MX6UL/ULL Boards (N63xx/N64xx)
+M: Frieder Schrempf <frieder.schrempf@kontron.de>
+S: Maintained
+F: arch/arm/dts/imx6ul-kontron-n6*
+F: arch/arm/dts/imx6ull-kontron-n6*
+F: board/kontron/sl-mx6ul
+F: configs/kontron-sl-mx6ul_defconfig
+F: doc/board/kontron/sl-mx6ul.rst
+F: include/configs/kontron-sl-mx6ul.h
diff --git a/board/kontron/sl-mx6ul/Makefile b/board/kontron/sl-mx6ul/Makefile
new file mode 100644
index 0000000..cae273c
--- /dev/null
+++ b/board/kontron/sl-mx6ul/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2018 Kontron Electronics GmbH
+
+ifdef CONFIG_SPL_BUILD
+obj-y := spl.o
+else
+obj-y := sl-mx6ul.o
+endif
diff --git a/board/kontron/sl-mx6ul/sl-mx6ul.c b/board/kontron/sl-mx6ul/sl-mx6ul.c
new file mode 100644
index 0000000..79d4d87
--- /dev/null
+++ b/board/kontron/sl-mx6ul/sl-mx6ul.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <fdt_support.h>
+#include <phy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+
+ return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ /*
+ * Overwrite the memory size in the devicetree that is
+ * passed to the kernel with the actual size detected.
+ */
+ return fdt_fixup_memory(blob, PHYS_SDRAM, gd->ram_size);
+}
+
+static int setup_fec(void)
+{
+ struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ int ret;
+
+ /*
+ * Use 50M anatop loopback REF_CLK1 for ENET1,
+ * clear gpr1[13], set gpr1[17].
+ */
+ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
+ IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
+
+ /*
+ * Use 50M anatop loopback REF_CLK2 for ENET2,
+ * clear gpr1[14], set gpr1[18].
+ */
+ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
+ IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
+
+ ret = enable_fec_anatop_clock(0, ENET_50MHZ);
+ if (ret)
+ return ret;
+
+ ret = enable_fec_anatop_clock(1, ENET_50MHZ);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ enable_qspi_clk(0);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ setup_fec();
+
+ return 0;
+}
diff --git a/board/kontron/sl-mx6ul/spl.c b/board/kontron/sl-mx6ul/spl.c
new file mode 100644
index 0000000..12b0352
--- /dev/null
+++ b/board/kontron/sl-mx6ul/spl.c
@@ -0,0 +1,377 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <fsl_esdhc_imx.h>
+#include <init.h>
+#include <linux/delay.h>
+#include <linux/sizes.h>
+#include <linux/errno.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+ BOARD_TYPE_KTN_N631X = 1,
+ BOARD_TYPE_KTN_N641X,
+ BOARD_TYPE_MAX
+};
+
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#include <spl.h>
+#include <asm/arch/mx6-ddr.h>
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+ MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ /* CD */
+ MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(USDHC_CD_PAD_CTRL),
+};
+
+#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ /* RST */
+ MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10)
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+ {USDHC1_BASE_ADDR, 0, 4},
+ {USDHC2_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC1_BASE_ADDR:
+ ret = !gpio_get_value(USDHC1_CD_GPIO);
+ break;
+ case USDHC2_BASE_ADDR:
+ // This SDHC interface does not use a CD pin
+ ret = 1;
+ break;
+ }
+
+ return ret;
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+ int i, ret;
+
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-boot device node) (Physical Port)
+ * mmc0 USDHC1
+ * mmc1 USDHC2
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+ gpio_direction_input(USDHC1_CD_GPIO);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ gpio_direction_output(USDHC2_PWR_GPIO, 0);
+ udelay(500);
+ gpio_direction_output(USDHC2_PWR_GPIO, 1);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n",
+ i + 1);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret) {
+ printf("Warning: failed to initialize mmc dev %d\n", i);
+ return ret;
+ }
+ }
+ return 0;
+}
+
+iomux_v3_cfg_t const ecspi2_pads[] = {
+ MX6_PAD_CSI_DATA00__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_CSI_DATA02__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_CSI_DATA03__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_CSI_DATA01__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+int board_spi_cs_gpio(unsigned int bus, unsigned int cs)
+{
+ return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
+ ? (IMX_GPIO_NR(4, 22)) : -1;
+}
+
+static void setup_spi(void)
+{
+ gpio_request(IMX_GPIO_NR(4, 22), "spi2_cs0");
+ gpio_direction_output(IMX_GPIO_NR(4, 22), 1);
+ imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads));
+
+ enable_spi_clk(true, 1);
+}
+
+static iomux_v3_cfg_t const uart4_pads[] = {
+ MX6_PAD_UART4_TX_DATA__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_UART4_RX_DATA__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
+}
+
+// DDR 256MB (Hynix H5TQ2G63DFR)
+static struct mx6_ddr3_cfg mem_256M_ddr = {
+ .mem_speed = 800,
+ .density = 2,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 14,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1350,
+ .trcmin = 4950,
+ .trasmin = 3600,
+};
+
+static struct mx6_mmdc_calibration mx6_mmcd_256M_calib = {
+ .p0_mpwldectrl0 = 0x00000000,
+ .p0_mpdgctrl0 = 0x01340134,
+ .p0_mprddlctl = 0x40405052,
+ .p0_mpwrdlctl = 0x40404E48,
+};
+
+// DDR 512MB (Hynix H5TQ4G63DFR)
+static struct mx6_ddr3_cfg mem_512M_ddr = {
+ .mem_speed = 800,
+ .density = 4,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 15,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1350,
+ .trcmin = 4950,
+ .trasmin = 3600,
+};
+
+static struct mx6_mmdc_calibration mx6_mmcd_512M_calib = {
+ .p0_mpwldectrl0 = 0x00000000,
+ .p0_mpdgctrl0 = 0X01440144,
+ .p0_mprddlctl = 0x40405454,
+ .p0_mpwrdlctl = 0x40404E4C,
+};
+
+// Common DDR parameters (256MB and 512MB)
+static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
+ .grp_addds = 0x00000028,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_b0ds = 0x00000028,
+ .grp_ctlds = 0x00000028,
+ .grp_b1ds = 0x00000028,
+ .grp_ddrpke = 0x00000000,
+ .grp_ddrmode = 0x00020000,
+ .grp_ddr_type = 0x000c0000,
+};
+
+static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
+ .dram_dqm0 = 0x00000028,
+ .dram_dqm1 = 0x00000028,
+ .dram_ras = 0x00000028,
+ .dram_cas = 0x00000028,
+ .dram_odt0 = 0x00000028,
+ .dram_odt1 = 0x00000028,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdclk_0 = 0x00000028,
+ .dram_sdqs0 = 0x00000028,
+ .dram_sdqs1 = 0x00000028,
+ .dram_reset = 0x00000028,
+};
+
+struct mx6_ddr_sysinfo ddr_sysinfo = {
+ .dsize = 0,
+ .cs_density = 20,
+ .ncs = 1,
+ .cs1_mirror = 0,
+ .rtt_wr = 2,
+ .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
+ .walat = 1, /* Write additional latency */
+ .ralat = 5, /* Read additional latency */
+ .mif3_mode = 3, /* Command prediction working mode */
+ .bi_on = 1, /* Bank interleaving enabled */
+ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
+ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+ .ddr_type = DDR_TYPE_DDR3,
+ .refsel = 0, /* Refresh cycles at 64KHz */
+ .refr = 1, /* 2 refresh commands per refresh cycle */
+};
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0xFFFFFFFF, &ccm->CCGR0);
+ writel(0xFFFFFFFF, &ccm->CCGR1);
+ writel(0xFFFFFFFF, &ccm->CCGR2);
+ writel(0xFFFFFFFF, &ccm->CCGR3);
+ writel(0xFFFFFFFF, &ccm->CCGR4);
+ writel(0xFFFFFFFF, &ccm->CCGR5);
+ writel(0xFFFFFFFF, &ccm->CCGR6);
+ writel(0xFFFFFFFF, &ccm->CCGR7);
+}
+
+static void spl_dram_init(void)
+{
+ unsigned int size;
+
+ // DDR RAM connection is always 16 bit wide. Init IOs.
+ mx6ul_dram_iocfg(16, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+
+ // Try to detect the 512MB RAM chip first.
+ mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_512M_calib, &mem_512M_ddr);
+
+ // Get the available RAM size
+ size = get_ram_size((void *)PHYS_SDRAM, SZ_512M);
+
+ gd->ram_size = size;
+
+ if (size == SZ_512M) {
+ // 512MB RAM was detected
+ return;
+ } else if (size == SZ_256M) {
+ // 256MB RAM was detected, use correct config and calibration
+ mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_256M_calib, &mem_256M_ddr);
+ } else {
+ printf("Invalid DDR RAM size detected: %x\n", size);
+ }
+}
+
+static int do_board_detect(void)
+{
+ if (is_mx6ul())
+ gd->board_type = BOARD_TYPE_KTN_N631X;
+ else if (is_mx6ull())
+ gd->board_type = BOARD_TYPE_KTN_N641X;
+
+ printf("Kontron SL i.MX6UL%s (N6%s1x) module, %lu MB RAM detected\n",
+ is_mx6ull() ? "L" : "", is_mx6ull() ? "4" : "3", gd->ram_size / SZ_1M);
+
+ return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+ ccgr_init();
+
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ /* iomux and setup of UART and SPI */
+ board_early_init_f();
+
+ /* setup GP timer */
+ timer_init();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* Detect the board type */
+ do_board_detect();
+
+ /* load/boot image from boot device */
+ board_init_r(NULL, 0);
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+ u32 bootdev = spl_boot_device();
+
+ /*
+ * The default boot fuse settings use the SD card (MMC1) as primary
+ * boot device, but allow SPI NOR as a fallback boot device.
+ * We can't detect the fallback case and spl_boot_device() will return
+ * BOOT_DEVICE_MMC1 despite the actual boot device being SPI NOR.
+ * Therefore we try to load U-Boot proper vom SPI NOR after loading
+ * from MMC has failed.
+ */
+ spl_boot_list[0] = bootdev;
+
+ switch (bootdev) {
+ case BOOT_DEVICE_MMC1:
+ case BOOT_DEVICE_MMC2:
+ spl_boot_list[1] = BOOT_DEVICE_SPI;
+ break;
+ }
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+ setup_spi();
+
+ return 0;
+}
+
+int board_fit_config_name_match(const char *name)
+{
+ if (gd->board_type == BOARD_TYPE_KTN_N631X && is_mx6ul() &&
+ !strcmp(name, "imx6ul-kontron-n631x-s"))
+ return 0;
+
+ if (gd->board_type == BOARD_TYPE_KTN_N641X && is_mx6ull() &&
+ !strcmp(name, "imx6ull-kontron-n641x-s"))
+ return 0;
+
+ return -1;
+}
diff --git a/board/kontron/sl-mx8mm/Kconfig b/board/kontron/sl-mx8mm/Kconfig
new file mode 100644
index 0000000..9dcf407
--- /dev/null
+++ b/board/kontron/sl-mx8mm/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_KONTRON_MX8MM
+
+config SYS_BOARD
+ string
+ default "sl-mx8mm"
+
+config SYS_VENDOR
+ string
+ default "kontron"
+
+config SYS_CONFIG_NAME
+ string
+ default "kontron-sl-mx8mm"
+
+endif
diff --git a/board/kontron/sl-mx8mm/MAINTAINERS b/board/kontron/sl-mx8mm/MAINTAINERS
new file mode 100644
index 0000000..5e68ae0
--- /dev/null
+++ b/board/kontron/sl-mx8mm/MAINTAINERS
@@ -0,0 +1,8 @@
+Kontron SL/BL i.MX8M Mini Boards (N801x)
+M: Frieder Schrempf <frieder.schrempf@kontron.de>
+S: Maintained
+F: arch/arm/dts/imx8mm-kontron-n801x-*
+F: board/kontron/sl-mx8mm
+F: configs/kontron-sl-mx8mm_defconfig
+F: doc/board/kontron/sl-mx8mm.rst
+F: include/configs/kontron-sl-mx8mm.h
diff --git a/board/kontron/sl-mx8mm/Makefile b/board/kontron/sl-mx8mm/Makefile
new file mode 100644
index 0000000..fceed68
--- /dev/null
+++ b/board/kontron/sl-mx8mm/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2019 Kontron Electronics GmbH
+
+obj-y := sl-mx8mm.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+endif
diff --git a/board/kontron/sl-mx8mm/imximage.cfg b/board/kontron/sl-mx8mm/imximage.cfg
new file mode 100644
index 0000000..f101f3d
--- /dev/null
+++ b/board/kontron/sl-mx8mm/imximage.cfg
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ */
+
+#define __ASSEMBLY__
+
+BOOT_FROM sd
+LOADER u-boot-spl-ddr.bin 0x7E1000
diff --git a/board/kontron/sl-mx8mm/lpddr4_timing.c b/board/kontron/sl-mx8mm/lpddr4_timing.c
new file mode 100644
index 0000000..0eabb16
--- /dev/null
+++ b/board/kontron/sl-mx8mm/lpddr4_timing.c
@@ -0,0 +1,1844 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ */
+
+#include <linux/kernel.h>
+#include <common.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /** Initialize DDRC registers **/
+ {0x3d400304, 0x1},
+ {0x3d400030, 0x1},
+ {0x3d400000, 0xa3080020},
+ {0x3d400020, 0x223},
+ {0x3d400024, 0x3a980},
+ {0x3d400064, 0x5b0087},
+ {0x3d4000d0, 0xc00305ba},
+ {0x3d4000d4, 0x940000},
+ {0x3d4000dc, 0xd4002d},
+ {0x3d4000e0, 0x310000},
+ {0x3d4000e8, 0x66004d},
+ {0x3d4000ec, 0x16004d},
+ {0x3d400100, 0x191e1920},
+ {0x3d400104, 0x60630},
+ {0x3d40010c, 0xb0b000},
+ {0x3d400110, 0xe04080e},
+ {0x3d400114, 0x2040c0c},
+ {0x3d400118, 0x1010007},
+ {0x3d40011c, 0x401},
+ {0x3d400130, 0x20600},
+ {0x3d400134, 0xc100002},
+ {0x3d400138, 0xd8},
+ {0x3d400144, 0x96004b},
+ {0x3d400180, 0x2ee0017},
+ {0x3d400184, 0x2605b8e},
+ {0x3d400188, 0x0},
+ {0x3d400190, 0x497820a},
+ {0x3d400194, 0x80303},
+ {0x3d4001b4, 0x170a},
+ {0x3d4001a0, 0xe0400018},
+ {0x3d4001a4, 0xdf00e4},
+ {0x3d4001a8, 0x80000000},
+ {0x3d4001b0, 0x11},
+ {0x3d4001c0, 0x1},
+ {0x3d4001c4, 0x1},
+ {0x3d4000f4, 0xc99},
+ {0x3d400108, 0x70e1617},
+ {0x3d400200, 0x17},
+ {0x3d40020c, 0x0},
+ {0x3d400210, 0x1f1f},
+ {0x3d400204, 0x80808},
+ {0x3d400214, 0x7070707},
+ {0x3d400218, 0x7070707},
+ {0x3d400250, 0x29001701},
+ {0x3d400254, 0x2c},
+ {0x3d40025c, 0x4000030},
+ {0x3d400264, 0x900093e7},
+ {0x3d40026c, 0x2005574},
+ {0x3d400400, 0x111},
+ {0x3d400408, 0x72ff},
+ {0x3d400494, 0x2100e07},
+ {0x3d400498, 0x620096},
+ {0x3d40049c, 0x1100e07},
+ {0x3d4004a0, 0xc8012c},
+ {0x3d402020, 0x21},
+ {0x3d402024, 0x7d00},
+ {0x3d402050, 0x20d040},
+ {0x3d402064, 0xc001c},
+ {0x3d4020dc, 0x840000},
+ {0x3d4020e0, 0x310000},
+ {0x3d4020e8, 0x66004d},
+ {0x3d4020ec, 0x16004d},
+ {0x3d402100, 0xa040305},
+ {0x3d402104, 0x30407},
+ {0x3d402108, 0x203060b},
+ {0x3d40210c, 0x505000},
+ {0x3d402110, 0x2040202},
+ {0x3d402114, 0x2030202},
+ {0x3d402118, 0x1010004},
+ {0x3d40211c, 0x301},
+ {0x3d402130, 0x20300},
+ {0x3d402134, 0xa100002},
+ {0x3d402138, 0x1d},
+ {0x3d402144, 0x14000a},
+ {0x3d402180, 0x640004},
+ {0x3d402190, 0x3818200},
+ {0x3d402194, 0x80303},
+ {0x3d4021b4, 0x100},
+ {0x3d403020, 0x21},
+ {0x3d403024, 0x1f40},
+ {0x3d403050, 0x20d040},
+ {0x3d403064, 0x30007},
+ {0x3d4030dc, 0x840000},
+ {0x3d4030e0, 0x310000},
+ {0x3d4030e8, 0x66004d},
+ {0x3d4030ec, 0x16004d},
+ {0x3d403100, 0xa010102},
+ {0x3d403104, 0x30404},
+ {0x3d403108, 0x203060b},
+ {0x3d40310c, 0x505000},
+ {0x3d403110, 0x2040202},
+ {0x3d403114, 0x2030202},
+ {0x3d403118, 0x1010004},
+ {0x3d40311c, 0x301},
+ {0x3d403130, 0x20300},
+ {0x3d403134, 0xa100002},
+ {0x3d403138, 0x8},
+ {0x3d403144, 0x50003},
+ {0x3d403180, 0x190004},
+ {0x3d403190, 0x3818200},
+ {0x3d403194, 0x80303},
+ {0x3d4031b4, 0x100},
+ {0x3d400028, 0x0},
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ {0x100a0, 0x0},
+ {0x100a1, 0x1},
+ {0x100a2, 0x2},
+ {0x100a3, 0x3},
+ {0x100a4, 0x4},
+ {0x100a5, 0x5},
+ {0x100a6, 0x6},
+ {0x100a7, 0x7},
+ {0x110a0, 0x0},
+ {0x110a1, 0x1},
+ {0x110a2, 0x3},
+ {0x110a3, 0x4},
+ {0x110a4, 0x5},
+ {0x110a5, 0x2},
+ {0x110a6, 0x7},
+ {0x110a7, 0x6},
+ {0x120a0, 0x0},
+ {0x120a1, 0x1},
+ {0x120a2, 0x3},
+ {0x120a3, 0x2},
+ {0x120a4, 0x5},
+ {0x120a5, 0x4},
+ {0x120a6, 0x7},
+ {0x120a7, 0x6},
+ {0x130a0, 0x0},
+ {0x130a1, 0x1},
+ {0x130a2, 0x2},
+ {0x130a3, 0x3},
+ {0x130a4, 0x4},
+ {0x130a5, 0x5},
+ {0x130a6, 0x6},
+ {0x130a7, 0x7},
+ {0x1005f, 0x1ff},
+ {0x1015f, 0x1ff},
+ {0x1105f, 0x1ff},
+ {0x1115f, 0x1ff},
+ {0x1205f, 0x1ff},
+ {0x1215f, 0x1ff},
+ {0x1305f, 0x1ff},
+ {0x1315f, 0x1ff},
+ {0x11005f, 0x1ff},
+ {0x11015f, 0x1ff},
+ {0x11105f, 0x1ff},
+ {0x11115f, 0x1ff},
+ {0x11205f, 0x1ff},
+ {0x11215f, 0x1ff},
+ {0x11305f, 0x1ff},
+ {0x11315f, 0x1ff},
+ {0x21005f, 0x1ff},
+ {0x21015f, 0x1ff},
+ {0x21105f, 0x1ff},
+ {0x21115f, 0x1ff},
+ {0x21205f, 0x1ff},
+ {0x21215f, 0x1ff},
+ {0x21305f, 0x1ff},
+ {0x21315f, 0x1ff},
+ {0x55, 0x1ff},
+ {0x1055, 0x1ff},
+ {0x2055, 0x1ff},
+ {0x3055, 0x1ff},
+ {0x4055, 0x1ff},
+ {0x5055, 0x1ff},
+ {0x6055, 0x1ff},
+ {0x7055, 0x1ff},
+ {0x8055, 0x1ff},
+ {0x9055, 0x1ff},
+ {0x200c5, 0x19},
+ {0x1200c5, 0x7},
+ {0x2200c5, 0x7},
+ {0x2002e, 0x2},
+ {0x12002e, 0x2},
+ {0x22002e, 0x2},
+ {0x90204, 0x0},
+ {0x190204, 0x0},
+ {0x290204, 0x0},
+ {0x20024, 0x1ab},
+ {0x2003a, 0x0},
+ {0x120024, 0x1ab},
+ {0x2003a, 0x0},
+ {0x220024, 0x1ab},
+ {0x2003a, 0x0},
+ {0x20056, 0x3},
+ {0x120056, 0x3},
+ {0x220056, 0x3},
+ {0x1004d, 0xe00},
+ {0x1014d, 0xe00},
+ {0x1104d, 0xe00},
+ {0x1114d, 0xe00},
+ {0x1204d, 0xe00},
+ {0x1214d, 0xe00},
+ {0x1304d, 0xe00},
+ {0x1314d, 0xe00},
+ {0x11004d, 0xe00},
+ {0x11014d, 0xe00},
+ {0x11104d, 0xe00},
+ {0x11114d, 0xe00},
+ {0x11204d, 0xe00},
+ {0x11214d, 0xe00},
+ {0x11304d, 0xe00},
+ {0x11314d, 0xe00},
+ {0x21004d, 0xe00},
+ {0x21014d, 0xe00},
+ {0x21104d, 0xe00},
+ {0x21114d, 0xe00},
+ {0x21204d, 0xe00},
+ {0x21214d, 0xe00},
+ {0x21304d, 0xe00},
+ {0x21314d, 0xe00},
+ {0x10049, 0xeba},
+ {0x10149, 0xeba},
+ {0x11049, 0xeba},
+ {0x11149, 0xeba},
+ {0x12049, 0xeba},
+ {0x12149, 0xeba},
+ {0x13049, 0xeba},
+ {0x13149, 0xeba},
+ {0x110049, 0xeba},
+ {0x110149, 0xeba},
+ {0x111049, 0xeba},
+ {0x111149, 0xeba},
+ {0x112049, 0xeba},
+ {0x112149, 0xeba},
+ {0x113049, 0xeba},
+ {0x113149, 0xeba},
+ {0x210049, 0xeba},
+ {0x210149, 0xeba},
+ {0x211049, 0xeba},
+ {0x211149, 0xeba},
+ {0x212049, 0xeba},
+ {0x212149, 0xeba},
+ {0x213049, 0xeba},
+ {0x213149, 0xeba},
+ {0x43, 0x63},
+ {0x1043, 0x63},
+ {0x2043, 0x63},
+ {0x3043, 0x63},
+ {0x4043, 0x63},
+ {0x5043, 0x63},
+ {0x6043, 0x63},
+ {0x7043, 0x63},
+ {0x8043, 0x63},
+ {0x9043, 0x63},
+ {0x20018, 0x3},
+ {0x20075, 0x4},
+ {0x20050, 0x0},
+ {0x20008, 0x2ee},
+ {0x120008, 0x64},
+ {0x220008, 0x19},
+ {0x20088, 0x9},
+ {0x200b2, 0xdc},
+ {0x10043, 0x5a1},
+ {0x10143, 0x5a1},
+ {0x11043, 0x5a1},
+ {0x11143, 0x5a1},
+ {0x12043, 0x5a1},
+ {0x12143, 0x5a1},
+ {0x13043, 0x5a1},
+ {0x13143, 0x5a1},
+ {0x1200b2, 0xdc},
+ {0x110043, 0x5a1},
+ {0x110143, 0x5a1},
+ {0x111043, 0x5a1},
+ {0x111143, 0x5a1},
+ {0x112043, 0x5a1},
+ {0x112143, 0x5a1},
+ {0x113043, 0x5a1},
+ {0x113143, 0x5a1},
+ {0x2200b2, 0xdc},
+ {0x210043, 0x5a1},
+ {0x210143, 0x5a1},
+ {0x211043, 0x5a1},
+ {0x211143, 0x5a1},
+ {0x212043, 0x5a1},
+ {0x212143, 0x5a1},
+ {0x213043, 0x5a1},
+ {0x213143, 0x5a1},
+ {0x200fa, 0x1},
+ {0x1200fa, 0x1},
+ {0x2200fa, 0x1},
+ {0x20019, 0x1},
+ {0x120019, 0x1},
+ {0x220019, 0x1},
+ {0x200f0, 0x660},
+ {0x200f1, 0x0},
+ {0x200f2, 0x4444},
+ {0x200f3, 0x8888},
+ {0x200f4, 0x5665},
+ {0x200f5, 0x0},
+ {0x200f6, 0x0},
+ {0x200f7, 0xf000},
+ {0x20025, 0x0},
+ {0x2002d, 0x0},
+ {0x12002d, 0x0},
+ {0x22002d, 0x0},
+ {0x200c7, 0x21},
+ {0x1200c7, 0x21},
+ {0x2200c7, 0x21},
+ {0x200ca, 0x24},
+ {0x1200ca, 0x24},
+ {0x2200ca, 0x24},
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ { 0x200b2, 0x0 },
+ { 0x1200b2, 0x0 },
+ { 0x2200b2, 0x0 },
+ { 0x200cb, 0x0 },
+ { 0x10043, 0x0 },
+ { 0x110043, 0x0 },
+ { 0x210043, 0x0 },
+ { 0x10143, 0x0 },
+ { 0x110143, 0x0 },
+ { 0x210143, 0x0 },
+ { 0x11043, 0x0 },
+ { 0x111043, 0x0 },
+ { 0x211043, 0x0 },
+ { 0x11143, 0x0 },
+ { 0x111143, 0x0 },
+ { 0x211143, 0x0 },
+ { 0x12043, 0x0 },
+ { 0x112043, 0x0 },
+ { 0x212043, 0x0 },
+ { 0x12143, 0x0 },
+ { 0x112143, 0x0 },
+ { 0x212143, 0x0 },
+ { 0x13043, 0x0 },
+ { 0x113043, 0x0 },
+ { 0x213043, 0x0 },
+ { 0x13143, 0x0 },
+ { 0x113143, 0x0 },
+ { 0x213143, 0x0 },
+ { 0x80, 0x0 },
+ { 0x100080, 0x0 },
+ { 0x200080, 0x0 },
+ { 0x1080, 0x0 },
+ { 0x101080, 0x0 },
+ { 0x201080, 0x0 },
+ { 0x2080, 0x0 },
+ { 0x102080, 0x0 },
+ { 0x202080, 0x0 },
+ { 0x3080, 0x0 },
+ { 0x103080, 0x0 },
+ { 0x203080, 0x0 },
+ { 0x4080, 0x0 },
+ { 0x104080, 0x0 },
+ { 0x204080, 0x0 },
+ { 0x5080, 0x0 },
+ { 0x105080, 0x0 },
+ { 0x205080, 0x0 },
+ { 0x6080, 0x0 },
+ { 0x106080, 0x0 },
+ { 0x206080, 0x0 },
+ { 0x7080, 0x0 },
+ { 0x107080, 0x0 },
+ { 0x207080, 0x0 },
+ { 0x8080, 0x0 },
+ { 0x108080, 0x0 },
+ { 0x208080, 0x0 },
+ { 0x9080, 0x0 },
+ { 0x109080, 0x0 },
+ { 0x209080, 0x0 },
+ { 0x10080, 0x0 },
+ { 0x110080, 0x0 },
+ { 0x210080, 0x0 },
+ { 0x10180, 0x0 },
+ { 0x110180, 0x0 },
+ { 0x210180, 0x0 },
+ { 0x11080, 0x0 },
+ { 0x111080, 0x0 },
+ { 0x211080, 0x0 },
+ { 0x11180, 0x0 },
+ { 0x111180, 0x0 },
+ { 0x211180, 0x0 },
+ { 0x12080, 0x0 },
+ { 0x112080, 0x0 },
+ { 0x212080, 0x0 },
+ { 0x12180, 0x0 },
+ { 0x112180, 0x0 },
+ { 0x212180, 0x0 },
+ { 0x13080, 0x0 },
+ { 0x113080, 0x0 },
+ { 0x213080, 0x0 },
+ { 0x13180, 0x0 },
+ { 0x113180, 0x0 },
+ { 0x213180, 0x0 },
+ { 0x10081, 0x0 },
+ { 0x110081, 0x0 },
+ { 0x210081, 0x0 },
+ { 0x10181, 0x0 },
+ { 0x110181, 0x0 },
+ { 0x210181, 0x0 },
+ { 0x11081, 0x0 },
+ { 0x111081, 0x0 },
+ { 0x211081, 0x0 },
+ { 0x11181, 0x0 },
+ { 0x111181, 0x0 },
+ { 0x211181, 0x0 },
+ { 0x12081, 0x0 },
+ { 0x112081, 0x0 },
+ { 0x212081, 0x0 },
+ { 0x12181, 0x0 },
+ { 0x112181, 0x0 },
+ { 0x212181, 0x0 },
+ { 0x13081, 0x0 },
+ { 0x113081, 0x0 },
+ { 0x213081, 0x0 },
+ { 0x13181, 0x0 },
+ { 0x113181, 0x0 },
+ { 0x213181, 0x0 },
+ { 0x100d0, 0x0 },
+ { 0x1100d0, 0x0 },
+ { 0x2100d0, 0x0 },
+ { 0x101d0, 0x0 },
+ { 0x1101d0, 0x0 },
+ { 0x2101d0, 0x0 },
+ { 0x110d0, 0x0 },
+ { 0x1110d0, 0x0 },
+ { 0x2110d0, 0x0 },
+ { 0x111d0, 0x0 },
+ { 0x1111d0, 0x0 },
+ { 0x2111d0, 0x0 },
+ { 0x120d0, 0x0 },
+ { 0x1120d0, 0x0 },
+ { 0x2120d0, 0x0 },
+ { 0x121d0, 0x0 },
+ { 0x1121d0, 0x0 },
+ { 0x2121d0, 0x0 },
+ { 0x130d0, 0x0 },
+ { 0x1130d0, 0x0 },
+ { 0x2130d0, 0x0 },
+ { 0x131d0, 0x0 },
+ { 0x1131d0, 0x0 },
+ { 0x2131d0, 0x0 },
+ { 0x100d1, 0x0 },
+ { 0x1100d1, 0x0 },
+ { 0x2100d1, 0x0 },
+ { 0x101d1, 0x0 },
+ { 0x1101d1, 0x0 },
+ { 0x2101d1, 0x0 },
+ { 0x110d1, 0x0 },
+ { 0x1110d1, 0x0 },
+ { 0x2110d1, 0x0 },
+ { 0x111d1, 0x0 },
+ { 0x1111d1, 0x0 },
+ { 0x2111d1, 0x0 },
+ { 0x120d1, 0x0 },
+ { 0x1120d1, 0x0 },
+ { 0x2120d1, 0x0 },
+ { 0x121d1, 0x0 },
+ { 0x1121d1, 0x0 },
+ { 0x2121d1, 0x0 },
+ { 0x130d1, 0x0 },
+ { 0x1130d1, 0x0 },
+ { 0x2130d1, 0x0 },
+ { 0x131d1, 0x0 },
+ { 0x1131d1, 0x0 },
+ { 0x2131d1, 0x0 },
+ { 0x10068, 0x0 },
+ { 0x10168, 0x0 },
+ { 0x10268, 0x0 },
+ { 0x10368, 0x0 },
+ { 0x10468, 0x0 },
+ { 0x10568, 0x0 },
+ { 0x10668, 0x0 },
+ { 0x10768, 0x0 },
+ { 0x10868, 0x0 },
+ { 0x11068, 0x0 },
+ { 0x11168, 0x0 },
+ { 0x11268, 0x0 },
+ { 0x11368, 0x0 },
+ { 0x11468, 0x0 },
+ { 0x11568, 0x0 },
+ { 0x11668, 0x0 },
+ { 0x11768, 0x0 },
+ { 0x11868, 0x0 },
+ { 0x12068, 0x0 },
+ { 0x12168, 0x0 },
+ { 0x12268, 0x0 },
+ { 0x12368, 0x0 },
+ { 0x12468, 0x0 },
+ { 0x12568, 0x0 },
+ { 0x12668, 0x0 },
+ { 0x12768, 0x0 },
+ { 0x12868, 0x0 },
+ { 0x13068, 0x0 },
+ { 0x13168, 0x0 },
+ { 0x13268, 0x0 },
+ { 0x13368, 0x0 },
+ { 0x13468, 0x0 },
+ { 0x13568, 0x0 },
+ { 0x13668, 0x0 },
+ { 0x13768, 0x0 },
+ { 0x13868, 0x0 },
+ { 0x10069, 0x0 },
+ { 0x10169, 0x0 },
+ { 0x10269, 0x0 },
+ { 0x10369, 0x0 },
+ { 0x10469, 0x0 },
+ { 0x10569, 0x0 },
+ { 0x10669, 0x0 },
+ { 0x10769, 0x0 },
+ { 0x10869, 0x0 },
+ { 0x11069, 0x0 },
+ { 0x11169, 0x0 },
+ { 0x11269, 0x0 },
+ { 0x11369, 0x0 },
+ { 0x11469, 0x0 },
+ { 0x11569, 0x0 },
+ { 0x11669, 0x0 },
+ { 0x11769, 0x0 },
+ { 0x11869, 0x0 },
+ { 0x12069, 0x0 },
+ { 0x12169, 0x0 },
+ { 0x12269, 0x0 },
+ { 0x12369, 0x0 },
+ { 0x12469, 0x0 },
+ { 0x12569, 0x0 },
+ { 0x12669, 0x0 },
+ { 0x12769, 0x0 },
+ { 0x12869, 0x0 },
+ { 0x13069, 0x0 },
+ { 0x13169, 0x0 },
+ { 0x13269, 0x0 },
+ { 0x13369, 0x0 },
+ { 0x13469, 0x0 },
+ { 0x13569, 0x0 },
+ { 0x13669, 0x0 },
+ { 0x13769, 0x0 },
+ { 0x13869, 0x0 },
+ { 0x1008c, 0x0 },
+ { 0x11008c, 0x0 },
+ { 0x21008c, 0x0 },
+ { 0x1018c, 0x0 },
+ { 0x11018c, 0x0 },
+ { 0x21018c, 0x0 },
+ { 0x1108c, 0x0 },
+ { 0x11108c, 0x0 },
+ { 0x21108c, 0x0 },
+ { 0x1118c, 0x0 },
+ { 0x11118c, 0x0 },
+ { 0x21118c, 0x0 },
+ { 0x1208c, 0x0 },
+ { 0x11208c, 0x0 },
+ { 0x21208c, 0x0 },
+ { 0x1218c, 0x0 },
+ { 0x11218c, 0x0 },
+ { 0x21218c, 0x0 },
+ { 0x1308c, 0x0 },
+ { 0x11308c, 0x0 },
+ { 0x21308c, 0x0 },
+ { 0x1318c, 0x0 },
+ { 0x11318c, 0x0 },
+ { 0x21318c, 0x0 },
+ { 0x1008d, 0x0 },
+ { 0x11008d, 0x0 },
+ { 0x21008d, 0x0 },
+ { 0x1018d, 0x0 },
+ { 0x11018d, 0x0 },
+ { 0x21018d, 0x0 },
+ { 0x1108d, 0x0 },
+ { 0x11108d, 0x0 },
+ { 0x21108d, 0x0 },
+ { 0x1118d, 0x0 },
+ { 0x11118d, 0x0 },
+ { 0x21118d, 0x0 },
+ { 0x1208d, 0x0 },
+ { 0x11208d, 0x0 },
+ { 0x21208d, 0x0 },
+ { 0x1218d, 0x0 },
+ { 0x11218d, 0x0 },
+ { 0x21218d, 0x0 },
+ { 0x1308d, 0x0 },
+ { 0x11308d, 0x0 },
+ { 0x21308d, 0x0 },
+ { 0x1318d, 0x0 },
+ { 0x11318d, 0x0 },
+ { 0x21318d, 0x0 },
+ { 0x100c0, 0x0 },
+ { 0x1100c0, 0x0 },
+ { 0x2100c0, 0x0 },
+ { 0x101c0, 0x0 },
+ { 0x1101c0, 0x0 },
+ { 0x2101c0, 0x0 },
+ { 0x102c0, 0x0 },
+ { 0x1102c0, 0x0 },
+ { 0x2102c0, 0x0 },
+ { 0x103c0, 0x0 },
+ { 0x1103c0, 0x0 },
+ { 0x2103c0, 0x0 },
+ { 0x104c0, 0x0 },
+ { 0x1104c0, 0x0 },
+ { 0x2104c0, 0x0 },
+ { 0x105c0, 0x0 },
+ { 0x1105c0, 0x0 },
+ { 0x2105c0, 0x0 },
+ { 0x106c0, 0x0 },
+ { 0x1106c0, 0x0 },
+ { 0x2106c0, 0x0 },
+ { 0x107c0, 0x0 },
+ { 0x1107c0, 0x0 },
+ { 0x2107c0, 0x0 },
+ { 0x108c0, 0x0 },
+ { 0x1108c0, 0x0 },
+ { 0x2108c0, 0x0 },
+ { 0x110c0, 0x0 },
+ { 0x1110c0, 0x0 },
+ { 0x2110c0, 0x0 },
+ { 0x111c0, 0x0 },
+ { 0x1111c0, 0x0 },
+ { 0x2111c0, 0x0 },
+ { 0x112c0, 0x0 },
+ { 0x1112c0, 0x0 },
+ { 0x2112c0, 0x0 },
+ { 0x113c0, 0x0 },
+ { 0x1113c0, 0x0 },
+ { 0x2113c0, 0x0 },
+ { 0x114c0, 0x0 },
+ { 0x1114c0, 0x0 },
+ { 0x2114c0, 0x0 },
+ { 0x115c0, 0x0 },
+ { 0x1115c0, 0x0 },
+ { 0x2115c0, 0x0 },
+ { 0x116c0, 0x0 },
+ { 0x1116c0, 0x0 },
+ { 0x2116c0, 0x0 },
+ { 0x117c0, 0x0 },
+ { 0x1117c0, 0x0 },
+ { 0x2117c0, 0x0 },
+ { 0x118c0, 0x0 },
+ { 0x1118c0, 0x0 },
+ { 0x2118c0, 0x0 },
+ { 0x120c0, 0x0 },
+ { 0x1120c0, 0x0 },
+ { 0x2120c0, 0x0 },
+ { 0x121c0, 0x0 },
+ { 0x1121c0, 0x0 },
+ { 0x2121c0, 0x0 },
+ { 0x122c0, 0x0 },
+ { 0x1122c0, 0x0 },
+ { 0x2122c0, 0x0 },
+ { 0x123c0, 0x0 },
+ { 0x1123c0, 0x0 },
+ { 0x2123c0, 0x0 },
+ { 0x124c0, 0x0 },
+ { 0x1124c0, 0x0 },
+ { 0x2124c0, 0x0 },
+ { 0x125c0, 0x0 },
+ { 0x1125c0, 0x0 },
+ { 0x2125c0, 0x0 },
+ { 0x126c0, 0x0 },
+ { 0x1126c0, 0x0 },
+ { 0x2126c0, 0x0 },
+ { 0x127c0, 0x0 },
+ { 0x1127c0, 0x0 },
+ { 0x2127c0, 0x0 },
+ { 0x128c0, 0x0 },
+ { 0x1128c0, 0x0 },
+ { 0x2128c0, 0x0 },
+ { 0x130c0, 0x0 },
+ { 0x1130c0, 0x0 },
+ { 0x2130c0, 0x0 },
+ { 0x131c0, 0x0 },
+ { 0x1131c0, 0x0 },
+ { 0x2131c0, 0x0 },
+ { 0x132c0, 0x0 },
+ { 0x1132c0, 0x0 },
+ { 0x2132c0, 0x0 },
+ { 0x133c0, 0x0 },
+ { 0x1133c0, 0x0 },
+ { 0x2133c0, 0x0 },
+ { 0x134c0, 0x0 },
+ { 0x1134c0, 0x0 },
+ { 0x2134c0, 0x0 },
+ { 0x135c0, 0x0 },
+ { 0x1135c0, 0x0 },
+ { 0x2135c0, 0x0 },
+ { 0x136c0, 0x0 },
+ { 0x1136c0, 0x0 },
+ { 0x2136c0, 0x0 },
+ { 0x137c0, 0x0 },
+ { 0x1137c0, 0x0 },
+ { 0x2137c0, 0x0 },
+ { 0x138c0, 0x0 },
+ { 0x1138c0, 0x0 },
+ { 0x2138c0, 0x0 },
+ { 0x100c1, 0x0 },
+ { 0x1100c1, 0x0 },
+ { 0x2100c1, 0x0 },
+ { 0x101c1, 0x0 },
+ { 0x1101c1, 0x0 },
+ { 0x2101c1, 0x0 },
+ { 0x102c1, 0x0 },
+ { 0x1102c1, 0x0 },
+ { 0x2102c1, 0x0 },
+ { 0x103c1, 0x0 },
+ { 0x1103c1, 0x0 },
+ { 0x2103c1, 0x0 },
+ { 0x104c1, 0x0 },
+ { 0x1104c1, 0x0 },
+ { 0x2104c1, 0x0 },
+ { 0x105c1, 0x0 },
+ { 0x1105c1, 0x0 },
+ { 0x2105c1, 0x0 },
+ { 0x106c1, 0x0 },
+ { 0x1106c1, 0x0 },
+ { 0x2106c1, 0x0 },
+ { 0x107c1, 0x0 },
+ { 0x1107c1, 0x0 },
+ { 0x2107c1, 0x0 },
+ { 0x108c1, 0x0 },
+ { 0x1108c1, 0x0 },
+ { 0x2108c1, 0x0 },
+ { 0x110c1, 0x0 },
+ { 0x1110c1, 0x0 },
+ { 0x2110c1, 0x0 },
+ { 0x111c1, 0x0 },
+ { 0x1111c1, 0x0 },
+ { 0x2111c1, 0x0 },
+ { 0x112c1, 0x0 },
+ { 0x1112c1, 0x0 },
+ { 0x2112c1, 0x0 },
+ { 0x113c1, 0x0 },
+ { 0x1113c1, 0x0 },
+ { 0x2113c1, 0x0 },
+ { 0x114c1, 0x0 },
+ { 0x1114c1, 0x0 },
+ { 0x2114c1, 0x0 },
+ { 0x115c1, 0x0 },
+ { 0x1115c1, 0x0 },
+ { 0x2115c1, 0x0 },
+ { 0x116c1, 0x0 },
+ { 0x1116c1, 0x0 },
+ { 0x2116c1, 0x0 },
+ { 0x117c1, 0x0 },
+ { 0x1117c1, 0x0 },
+ { 0x2117c1, 0x0 },
+ { 0x118c1, 0x0 },
+ { 0x1118c1, 0x0 },
+ { 0x2118c1, 0x0 },
+ { 0x120c1, 0x0 },
+ { 0x1120c1, 0x0 },
+ { 0x2120c1, 0x0 },
+ { 0x121c1, 0x0 },
+ { 0x1121c1, 0x0 },
+ { 0x2121c1, 0x0 },
+ { 0x122c1, 0x0 },
+ { 0x1122c1, 0x0 },
+ { 0x2122c1, 0x0 },
+ { 0x123c1, 0x0 },
+ { 0x1123c1, 0x0 },
+ { 0x2123c1, 0x0 },
+ { 0x124c1, 0x0 },
+ { 0x1124c1, 0x0 },
+ { 0x2124c1, 0x0 },
+ { 0x125c1, 0x0 },
+ { 0x1125c1, 0x0 },
+ { 0x2125c1, 0x0 },
+ { 0x126c1, 0x0 },
+ { 0x1126c1, 0x0 },
+ { 0x2126c1, 0x0 },
+ { 0x127c1, 0x0 },
+ { 0x1127c1, 0x0 },
+ { 0x2127c1, 0x0 },
+ { 0x128c1, 0x0 },
+ { 0x1128c1, 0x0 },
+ { 0x2128c1, 0x0 },
+ { 0x130c1, 0x0 },
+ { 0x1130c1, 0x0 },
+ { 0x2130c1, 0x0 },
+ { 0x131c1, 0x0 },
+ { 0x1131c1, 0x0 },
+ { 0x2131c1, 0x0 },
+ { 0x132c1, 0x0 },
+ { 0x1132c1, 0x0 },
+ { 0x2132c1, 0x0 },
+ { 0x133c1, 0x0 },
+ { 0x1133c1, 0x0 },
+ { 0x2133c1, 0x0 },
+ { 0x134c1, 0x0 },
+ { 0x1134c1, 0x0 },
+ { 0x2134c1, 0x0 },
+ { 0x135c1, 0x0 },
+ { 0x1135c1, 0x0 },
+ { 0x2135c1, 0x0 },
+ { 0x136c1, 0x0 },
+ { 0x1136c1, 0x0 },
+ { 0x2136c1, 0x0 },
+ { 0x137c1, 0x0 },
+ { 0x1137c1, 0x0 },
+ { 0x2137c1, 0x0 },
+ { 0x138c1, 0x0 },
+ { 0x1138c1, 0x0 },
+ { 0x2138c1, 0x0 },
+ { 0x10020, 0x0 },
+ { 0x110020, 0x0 },
+ { 0x210020, 0x0 },
+ { 0x11020, 0x0 },
+ { 0x111020, 0x0 },
+ { 0x211020, 0x0 },
+ { 0x12020, 0x0 },
+ { 0x112020, 0x0 },
+ { 0x212020, 0x0 },
+ { 0x13020, 0x0 },
+ { 0x113020, 0x0 },
+ { 0x213020, 0x0 },
+ { 0x20072, 0x0 },
+ { 0x20073, 0x0 },
+ { 0x20074, 0x0 },
+ { 0x100aa, 0x0 },
+ { 0x110aa, 0x0 },
+ { 0x120aa, 0x0 },
+ { 0x130aa, 0x0 },
+ { 0x20010, 0x0 },
+ { 0x120010, 0x0 },
+ { 0x220010, 0x0 },
+ { 0x20011, 0x0 },
+ { 0x120011, 0x0 },
+ { 0x220011, 0x0 },
+ { 0x100ae, 0x0 },
+ { 0x1100ae, 0x0 },
+ { 0x2100ae, 0x0 },
+ { 0x100af, 0x0 },
+ { 0x1100af, 0x0 },
+ { 0x2100af, 0x0 },
+ { 0x110ae, 0x0 },
+ { 0x1110ae, 0x0 },
+ { 0x2110ae, 0x0 },
+ { 0x110af, 0x0 },
+ { 0x1110af, 0x0 },
+ { 0x2110af, 0x0 },
+ { 0x120ae, 0x0 },
+ { 0x1120ae, 0x0 },
+ { 0x2120ae, 0x0 },
+ { 0x120af, 0x0 },
+ { 0x1120af, 0x0 },
+ { 0x2120af, 0x0 },
+ { 0x130ae, 0x0 },
+ { 0x1130ae, 0x0 },
+ { 0x2130ae, 0x0 },
+ { 0x130af, 0x0 },
+ { 0x1130af, 0x0 },
+ { 0x2130af, 0x0 },
+ { 0x20020, 0x0 },
+ { 0x120020, 0x0 },
+ { 0x220020, 0x0 },
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x0 },
+ { 0x100a2, 0x0 },
+ { 0x100a3, 0x0 },
+ { 0x100a4, 0x0 },
+ { 0x100a5, 0x0 },
+ { 0x100a6, 0x0 },
+ { 0x100a7, 0x0 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x0 },
+ { 0x110a2, 0x0 },
+ { 0x110a3, 0x0 },
+ { 0x110a4, 0x0 },
+ { 0x110a5, 0x0 },
+ { 0x110a6, 0x0 },
+ { 0x110a7, 0x0 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x0 },
+ { 0x120a2, 0x0 },
+ { 0x120a3, 0x0 },
+ { 0x120a4, 0x0 },
+ { 0x120a5, 0x0 },
+ { 0x120a6, 0x0 },
+ { 0x120a7, 0x0 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x0 },
+ { 0x130a2, 0x0 },
+ { 0x130a3, 0x0 },
+ { 0x130a4, 0x0 },
+ { 0x130a5, 0x0 },
+ { 0x130a6, 0x0 },
+ { 0x130a7, 0x0 },
+ { 0x2007c, 0x0 },
+ { 0x12007c, 0x0 },
+ { 0x22007c, 0x0 },
+ { 0x2007d, 0x0 },
+ { 0x12007d, 0x0 },
+ { 0x22007d, 0x0 },
+ { 0x400fd, 0x0 },
+ { 0x400c0, 0x0 },
+ { 0x90201, 0x0 },
+ { 0x190201, 0x0 },
+ { 0x290201, 0x0 },
+ { 0x90202, 0x0 },
+ { 0x190202, 0x0 },
+ { 0x290202, 0x0 },
+ { 0x90203, 0x0 },
+ { 0x190203, 0x0 },
+ { 0x290203, 0x0 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x90205, 0x0 },
+ { 0x190205, 0x0 },
+ { 0x290205, 0x0 },
+ { 0x90206, 0x0 },
+ { 0x190206, 0x0 },
+ { 0x290206, 0x0 },
+ { 0x90207, 0x0 },
+ { 0x190207, 0x0 },
+ { 0x290207, 0x0 },
+ { 0x90208, 0x0 },
+ { 0x190208, 0x0 },
+ { 0x290208, 0x0 },
+ { 0x10062, 0x0 },
+ { 0x10162, 0x0 },
+ { 0x10262, 0x0 },
+ { 0x10362, 0x0 },
+ { 0x10462, 0x0 },
+ { 0x10562, 0x0 },
+ { 0x10662, 0x0 },
+ { 0x10762, 0x0 },
+ { 0x10862, 0x0 },
+ { 0x11062, 0x0 },
+ { 0x11162, 0x0 },
+ { 0x11262, 0x0 },
+ { 0x11362, 0x0 },
+ { 0x11462, 0x0 },
+ { 0x11562, 0x0 },
+ { 0x11662, 0x0 },
+ { 0x11762, 0x0 },
+ { 0x11862, 0x0 },
+ { 0x12062, 0x0 },
+ { 0x12162, 0x0 },
+ { 0x12262, 0x0 },
+ { 0x12362, 0x0 },
+ { 0x12462, 0x0 },
+ { 0x12562, 0x0 },
+ { 0x12662, 0x0 },
+ { 0x12762, 0x0 },
+ { 0x12862, 0x0 },
+ { 0x13062, 0x0 },
+ { 0x13162, 0x0 },
+ { 0x13262, 0x0 },
+ { 0x13362, 0x0 },
+ { 0x13462, 0x0 },
+ { 0x13562, 0x0 },
+ { 0x13662, 0x0 },
+ { 0x13762, 0x0 },
+ { 0x13862, 0x0 },
+ { 0x20077, 0x0 },
+ { 0x10001, 0x0 },
+ { 0x11001, 0x0 },
+ { 0x12001, 0x0 },
+ { 0x13001, 0x0 },
+ { 0x10040, 0x0 },
+ { 0x10140, 0x0 },
+ { 0x10240, 0x0 },
+ { 0x10340, 0x0 },
+ { 0x10440, 0x0 },
+ { 0x10540, 0x0 },
+ { 0x10640, 0x0 },
+ { 0x10740, 0x0 },
+ { 0x10840, 0x0 },
+ { 0x10030, 0x0 },
+ { 0x10130, 0x0 },
+ { 0x10230, 0x0 },
+ { 0x10330, 0x0 },
+ { 0x10430, 0x0 },
+ { 0x10530, 0x0 },
+ { 0x10630, 0x0 },
+ { 0x10730, 0x0 },
+ { 0x10830, 0x0 },
+ { 0x11040, 0x0 },
+ { 0x11140, 0x0 },
+ { 0x11240, 0x0 },
+ { 0x11340, 0x0 },
+ { 0x11440, 0x0 },
+ { 0x11540, 0x0 },
+ { 0x11640, 0x0 },
+ { 0x11740, 0x0 },
+ { 0x11840, 0x0 },
+ { 0x11030, 0x0 },
+ { 0x11130, 0x0 },
+ { 0x11230, 0x0 },
+ { 0x11330, 0x0 },
+ { 0x11430, 0x0 },
+ { 0x11530, 0x0 },
+ { 0x11630, 0x0 },
+ { 0x11730, 0x0 },
+ { 0x11830, 0x0 },
+ { 0x12040, 0x0 },
+ { 0x12140, 0x0 },
+ { 0x12240, 0x0 },
+ { 0x12340, 0x0 },
+ { 0x12440, 0x0 },
+ { 0x12540, 0x0 },
+ { 0x12640, 0x0 },
+ { 0x12740, 0x0 },
+ { 0x12840, 0x0 },
+ { 0x12030, 0x0 },
+ { 0x12130, 0x0 },
+ { 0x12230, 0x0 },
+ { 0x12330, 0x0 },
+ { 0x12430, 0x0 },
+ { 0x12530, 0x0 },
+ { 0x12630, 0x0 },
+ { 0x12730, 0x0 },
+ { 0x12830, 0x0 },
+ { 0x13040, 0x0 },
+ { 0x13140, 0x0 },
+ { 0x13240, 0x0 },
+ { 0x13340, 0x0 },
+ { 0x13440, 0x0 },
+ { 0x13540, 0x0 },
+ { 0x13640, 0x0 },
+ { 0x13740, 0x0 },
+ { 0x13840, 0x0 },
+ { 0x13030, 0x0 },
+ { 0x13130, 0x0 },
+ { 0x13230, 0x0 },
+ { 0x13330, 0x0 },
+ { 0x13430, 0x0 },
+ { 0x13530, 0x0 },
+ { 0x13630, 0x0 },
+ { 0x13730, 0x0 },
+ { 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54003, 0xbb8},
+ {0x54004, 0x2},
+ {0x54005, 0x2228},
+ {0x54006, 0x11},
+ {0x54008, 0x131f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x2},
+ {0x5400d, 0x100},
+ {0x54012, 0x310},
+ {0x54019, 0x2dd4},
+ {0x5401a, 0x31},
+ {0x5401b, 0x4d66},
+ {0x5401c, 0x4d00},
+ {0x5401e, 0x16},
+ {0x5401f, 0x2dd4},
+ {0x54020, 0x31},
+ {0x54021, 0x4d66},
+ {0x54022, 0x4d00},
+ {0x54024, 0x16},
+ {0x5402b, 0x1000},
+ {0x5402c, 0x3},
+ {0x54032, 0xd400},
+ {0x54033, 0x312d},
+ {0x54034, 0x6600},
+ {0x54035, 0x4d},
+ {0x54036, 0x4d},
+ {0x54037, 0x1600},
+ {0x54038, 0xd400},
+ {0x54039, 0x312d},
+ {0x5403a, 0x6600},
+ {0x5403b, 0x4d},
+ {0x5403c, 0x4d},
+ {0x5403d, 0x1600},
+ {0xd0000, 0x1},
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54002, 0x101},
+ {0x54003, 0x190},
+ {0x54004, 0x2},
+ {0x54005, 0x2228},
+ {0x54006, 0x11},
+ {0x54008, 0x121f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x2},
+ {0x5400d, 0x100},
+ {0x54012, 0x310},
+ {0x54019, 0x84},
+ {0x5401a, 0x31},
+ {0x5401b, 0x4d66},
+ {0x5401c, 0x4d00},
+ {0x5401e, 0x16},
+ {0x5401f, 0x84},
+ {0x54020, 0x31},
+ {0x54021, 0x4d66},
+ {0x54022, 0x4d00},
+ {0x54024, 0x16},
+ {0x5402b, 0x1000},
+ {0x5402c, 0x3},
+ {0x54032, 0x8400},
+ {0x54033, 0x3100},
+ {0x54034, 0x6600},
+ {0x54035, 0x4d},
+ {0x54036, 0x4d},
+ {0x54037, 0x1600},
+ {0x54038, 0x8400},
+ {0x54039, 0x3100},
+ {0x5403a, 0x6600},
+ {0x5403b, 0x4d},
+ {0x5403c, 0x4d},
+ {0x5403d, 0x1600},
+ {0xd0000, 0x1},
+};
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54002, 0x102},
+ {0x54003, 0x64},
+ {0x54004, 0x2},
+ {0x54005, 0x2228},
+ {0x54006, 0x11},
+ {0x54008, 0x121f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x2},
+ {0x5400d, 0x100},
+ {0x54012, 0x310},
+ {0x54019, 0x84},
+ {0x5401a, 0x31},
+ {0x5401b, 0x4d66},
+ {0x5401c, 0x4d00},
+ {0x5401e, 0x16},
+ {0x5401f, 0x84},
+ {0x54020, 0x31},
+ {0x54021, 0x4d66},
+ {0x54022, 0x4d00},
+ {0x54024, 0x16},
+ {0x5402b, 0x1000},
+ {0x5402c, 0x3},
+ {0x54032, 0x8400},
+ {0x54033, 0x3100},
+ {0x54034, 0x6600},
+ {0x54035, 0x4d},
+ {0x54036, 0x4d},
+ {0x54037, 0x1600},
+ {0x54038, 0x8400},
+ {0x54039, 0x3100},
+ {0x5403a, 0x6600},
+ {0x5403b, 0x4d},
+ {0x5403c, 0x4d},
+ {0x5403d, 0x1600},
+ {0xd0000, 0x1},
+};
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54003, 0xbb8},
+ {0x54004, 0x2},
+ {0x54005, 0x2228},
+ {0x54006, 0x11},
+ {0x54008, 0x61},
+ {0x54009, 0xc8},
+ {0x5400b, 0x2},
+ {0x5400f, 0x100},
+ {0x54010, 0x1f7f},
+ {0x54012, 0x310},
+ {0x54019, 0x2dd4},
+ {0x5401a, 0x31},
+ {0x5401b, 0x4d66},
+ {0x5401c, 0x4d00},
+ {0x5401e, 0x16},
+ {0x5401f, 0x2dd4},
+ {0x54020, 0x31},
+ {0x54021, 0x4d66},
+ {0x54022, 0x4d00},
+ {0x54024, 0x16},
+ {0x5402b, 0x1000},
+ {0x5402c, 0x3},
+ {0x54032, 0xd400},
+ {0x54033, 0x312d},
+ {0x54034, 0x6600},
+ {0x54035, 0x4d},
+ {0x54036, 0x4d},
+ {0x54037, 0x1600},
+ {0x54038, 0xd400},
+ {0x54039, 0x312d},
+ {0x5403a, 0x6600},
+ {0x5403b, 0x4d},
+ {0x5403c, 0x4d},
+ {0x5403d, 0x1600},
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+ {0xd0000, 0x0},
+ {0x90000, 0x10},
+ {0x90001, 0x400},
+ {0x90002, 0x10e},
+ {0x90003, 0x0},
+ {0x90004, 0x0},
+ {0x90005, 0x8},
+ {0x90029, 0xb},
+ {0x9002a, 0x480},
+ {0x9002b, 0x109},
+ {0x9002c, 0x8},
+ {0x9002d, 0x448},
+ {0x9002e, 0x139},
+ {0x9002f, 0x8},
+ {0x90030, 0x478},
+ {0x90031, 0x109},
+ {0x90032, 0x0},
+ {0x90033, 0xe8},
+ {0x90034, 0x109},
+ {0x90035, 0x2},
+ {0x90036, 0x10},
+ {0x90037, 0x139},
+ {0x90038, 0xf},
+ {0x90039, 0x7c0},
+ {0x9003a, 0x139},
+ {0x9003b, 0x44},
+ {0x9003c, 0x630},
+ {0x9003d, 0x159},
+ {0x9003e, 0x14f},
+ {0x9003f, 0x630},
+ {0x90040, 0x159},
+ {0x90041, 0x47},
+ {0x90042, 0x630},
+ {0x90043, 0x149},
+ {0x90044, 0x4f},
+ {0x90045, 0x630},
+ {0x90046, 0x179},
+ {0x90047, 0x8},
+ {0x90048, 0xe0},
+ {0x90049, 0x109},
+ {0x9004a, 0x0},
+ {0x9004b, 0x7c8},
+ {0x9004c, 0x109},
+ {0x9004d, 0x0},
+ {0x9004e, 0x1},
+ {0x9004f, 0x8},
+ {0x90050, 0x0},
+ {0x90051, 0x45a},
+ {0x90052, 0x9},
+ {0x90053, 0x0},
+ {0x90054, 0x448},
+ {0x90055, 0x109},
+ {0x90056, 0x40},
+ {0x90057, 0x630},
+ {0x90058, 0x179},
+ {0x90059, 0x1},
+ {0x9005a, 0x618},
+ {0x9005b, 0x109},
+ {0x9005c, 0x40c0},
+ {0x9005d, 0x630},
+ {0x9005e, 0x149},
+ {0x9005f, 0x8},
+ {0x90060, 0x4},
+ {0x90061, 0x48},
+ {0x90062, 0x4040},
+ {0x90063, 0x630},
+ {0x90064, 0x149},
+ {0x90065, 0x0},
+ {0x90066, 0x4},
+ {0x90067, 0x48},
+ {0x90068, 0x40},
+ {0x90069, 0x630},
+ {0x9006a, 0x149},
+ {0x9006b, 0x10},
+ {0x9006c, 0x4},
+ {0x9006d, 0x18},
+ {0x9006e, 0x0},
+ {0x9006f, 0x4},
+ {0x90070, 0x78},
+ {0x90071, 0x549},
+ {0x90072, 0x630},
+ {0x90073, 0x159},
+ {0x90074, 0xd49},
+ {0x90075, 0x630},
+ {0x90076, 0x159},
+ {0x90077, 0x94a},
+ {0x90078, 0x630},
+ {0x90079, 0x159},
+ {0x9007a, 0x441},
+ {0x9007b, 0x630},
+ {0x9007c, 0x149},
+ {0x9007d, 0x42},
+ {0x9007e, 0x630},
+ {0x9007f, 0x149},
+ {0x90080, 0x1},
+ {0x90081, 0x630},
+ {0x90082, 0x149},
+ {0x90083, 0x0},
+ {0x90084, 0xe0},
+ {0x90085, 0x109},
+ {0x90086, 0xa},
+ {0x90087, 0x10},
+ {0x90088, 0x109},
+ {0x90089, 0x9},
+ {0x9008a, 0x3c0},
+ {0x9008b, 0x149},
+ {0x9008c, 0x9},
+ {0x9008d, 0x3c0},
+ {0x9008e, 0x159},
+ {0x9008f, 0x18},
+ {0x90090, 0x10},
+ {0x90091, 0x109},
+ {0x90092, 0x0},
+ {0x90093, 0x3c0},
+ {0x90094, 0x109},
+ {0x90095, 0x18},
+ {0x90096, 0x4},
+ {0x90097, 0x48},
+ {0x90098, 0x18},
+ {0x90099, 0x4},
+ {0x9009a, 0x58},
+ {0x9009b, 0xa},
+ {0x9009c, 0x10},
+ {0x9009d, 0x109},
+ {0x9009e, 0x2},
+ {0x9009f, 0x10},
+ {0x900a0, 0x109},
+ {0x900a1, 0x5},
+ {0x900a2, 0x7c0},
+ {0x900a3, 0x109},
+ {0x900a4, 0x10},
+ {0x900a5, 0x10},
+ {0x900a6, 0x109},
+ {0x40000, 0x811},
+ {0x40020, 0x880},
+ {0x40040, 0x0},
+ {0x40060, 0x0},
+ {0x40001, 0x4008},
+ {0x40021, 0x83},
+ {0x40041, 0x4f},
+ {0x40061, 0x0},
+ {0x40002, 0x4040},
+ {0x40022, 0x83},
+ {0x40042, 0x51},
+ {0x40062, 0x0},
+ {0x40003, 0x811},
+ {0x40023, 0x880},
+ {0x40043, 0x0},
+ {0x40063, 0x0},
+ {0x40004, 0x720},
+ {0x40024, 0xf},
+ {0x40044, 0x1740},
+ {0x40064, 0x0},
+ {0x40005, 0x16},
+ {0x40025, 0x83},
+ {0x40045, 0x4b},
+ {0x40065, 0x0},
+ {0x40006, 0x716},
+ {0x40026, 0xf},
+ {0x40046, 0x2001},
+ {0x40066, 0x0},
+ {0x40007, 0x716},
+ {0x40027, 0xf},
+ {0x40047, 0x2800},
+ {0x40067, 0x0},
+ {0x40008, 0x716},
+ {0x40028, 0xf},
+ {0x40048, 0xf00},
+ {0x40068, 0x0},
+ {0x40009, 0x720},
+ {0x40029, 0xf},
+ {0x40049, 0x1400},
+ {0x40069, 0x0},
+ {0x4000a, 0xe08},
+ {0x4002a, 0xc15},
+ {0x4004a, 0x0},
+ {0x4006a, 0x0},
+ {0x4000b, 0x623},
+ {0x4002b, 0x15},
+ {0x4004b, 0x0},
+ {0x4006b, 0x0},
+ {0x4000c, 0x4028},
+ {0x4002c, 0x80},
+ {0x4004c, 0x0},
+ {0x4006c, 0x0},
+ {0x4000d, 0xe08},
+ {0x4002d, 0xc1a},
+ {0x4004d, 0x0},
+ {0x4006d, 0x0},
+ {0x4000e, 0x623},
+ {0x4002e, 0x1a},
+ {0x4004e, 0x0},
+ {0x4006e, 0x0},
+ {0x4000f, 0x4040},
+ {0x4002f, 0x80},
+ {0x4004f, 0x0},
+ {0x4006f, 0x0},
+ {0x40010, 0x2604},
+ {0x40030, 0x15},
+ {0x40050, 0x0},
+ {0x40070, 0x0},
+ {0x40011, 0x708},
+ {0x40031, 0x5},
+ {0x40051, 0x0},
+ {0x40071, 0x2002},
+ {0x40012, 0x8},
+ {0x40032, 0x80},
+ {0x40052, 0x0},
+ {0x40072, 0x0},
+ {0x40013, 0x2604},
+ {0x40033, 0x1a},
+ {0x40053, 0x0},
+ {0x40073, 0x0},
+ {0x40014, 0x708},
+ {0x40034, 0xa},
+ {0x40054, 0x0},
+ {0x40074, 0x2002},
+ {0x40015, 0x4040},
+ {0x40035, 0x80},
+ {0x40055, 0x0},
+ {0x40075, 0x0},
+ {0x40016, 0x60a},
+ {0x40036, 0x15},
+ {0x40056, 0x1200},
+ {0x40076, 0x0},
+ {0x40017, 0x61a},
+ {0x40037, 0x15},
+ {0x40057, 0x1300},
+ {0x40077, 0x0},
+ {0x40018, 0x60a},
+ {0x40038, 0x1a},
+ {0x40058, 0x1200},
+ {0x40078, 0x0},
+ {0x40019, 0x642},
+ {0x40039, 0x1a},
+ {0x40059, 0x1300},
+ {0x40079, 0x0},
+ {0x4001a, 0x4808},
+ {0x4003a, 0x880},
+ {0x4005a, 0x0},
+ {0x4007a, 0x0},
+ {0x900a7, 0x0},
+ {0x900a8, 0x790},
+ {0x900a9, 0x11a},
+ {0x900aa, 0x8},
+ {0x900ab, 0x7aa},
+ {0x900ac, 0x2a},
+ {0x900ad, 0x10},
+ {0x900ae, 0x7b2},
+ {0x900af, 0x2a},
+ {0x900b0, 0x0},
+ {0x900b1, 0x7c8},
+ {0x900b2, 0x109},
+ {0x900b3, 0x10},
+ {0x900b4, 0x2a8},
+ {0x900b5, 0x129},
+ {0x900b6, 0x8},
+ {0x900b7, 0x370},
+ {0x900b8, 0x129},
+ {0x900b9, 0xa},
+ {0x900ba, 0x3c8},
+ {0x900bb, 0x1a9},
+ {0x900bc, 0xc},
+ {0x900bd, 0x408},
+ {0x900be, 0x199},
+ {0x900bf, 0x14},
+ {0x900c0, 0x790},
+ {0x900c1, 0x11a},
+ {0x900c2, 0x8},
+ {0x900c3, 0x4},
+ {0x900c4, 0x18},
+ {0x900c5, 0xe},
+ {0x900c6, 0x408},
+ {0x900c7, 0x199},
+ {0x900c8, 0x8},
+ {0x900c9, 0x8568},
+ {0x900ca, 0x108},
+ {0x900cb, 0x18},
+ {0x900cc, 0x790},
+ {0x900cd, 0x16a},
+ {0x900ce, 0x8},
+ {0x900cf, 0x1d8},
+ {0x900d0, 0x169},
+ {0x900d1, 0x10},
+ {0x900d2, 0x8558},
+ {0x900d3, 0x168},
+ {0x900d4, 0x70},
+ {0x900d5, 0x788},
+ {0x900d6, 0x16a},
+ {0x900d7, 0x1ff8},
+ {0x900d8, 0x85a8},
+ {0x900d9, 0x1e8},
+ {0x900da, 0x50},
+ {0x900db, 0x798},
+ {0x900dc, 0x16a},
+ {0x900dd, 0x60},
+ {0x900de, 0x7a0},
+ {0x900df, 0x16a},
+ {0x900e0, 0x8},
+ {0x900e1, 0x8310},
+ {0x900e2, 0x168},
+ {0x900e3, 0x8},
+ {0x900e4, 0xa310},
+ {0x900e5, 0x168},
+ {0x900e6, 0xa},
+ {0x900e7, 0x408},
+ {0x900e8, 0x169},
+ {0x900e9, 0x6e},
+ {0x900ea, 0x0},
+ {0x900eb, 0x68},
+ {0x900ec, 0x0},
+ {0x900ed, 0x408},
+ {0x900ee, 0x169},
+ {0x900ef, 0x0},
+ {0x900f0, 0x8310},
+ {0x900f1, 0x168},
+ {0x900f2, 0x0},
+ {0x900f3, 0xa310},
+ {0x900f4, 0x168},
+ {0x900f5, 0x1ff8},
+ {0x900f6, 0x85a8},
+ {0x900f7, 0x1e8},
+ {0x900f8, 0x68},
+ {0x900f9, 0x798},
+ {0x900fa, 0x16a},
+ {0x900fb, 0x78},
+ {0x900fc, 0x7a0},
+ {0x900fd, 0x16a},
+ {0x900fe, 0x68},
+ {0x900ff, 0x790},
+ {0x90100, 0x16a},
+ {0x90101, 0x8},
+ {0x90102, 0x8b10},
+ {0x90103, 0x168},
+ {0x90104, 0x8},
+ {0x90105, 0xab10},
+ {0x90106, 0x168},
+ {0x90107, 0xa},
+ {0x90108, 0x408},
+ {0x90109, 0x169},
+ {0x9010a, 0x58},
+ {0x9010b, 0x0},
+ {0x9010c, 0x68},
+ {0x9010d, 0x0},
+ {0x9010e, 0x408},
+ {0x9010f, 0x169},
+ {0x90110, 0x0},
+ {0x90111, 0x8b10},
+ {0x90112, 0x168},
+ {0x90113, 0x0},
+ {0x90114, 0xab10},
+ {0x90115, 0x168},
+ {0x90116, 0x0},
+ {0x90117, 0x1d8},
+ {0x90118, 0x169},
+ {0x90119, 0x80},
+ {0x9011a, 0x790},
+ {0x9011b, 0x16a},
+ {0x9011c, 0x18},
+ {0x9011d, 0x7aa},
+ {0x9011e, 0x6a},
+ {0x9011f, 0xa},
+ {0x90120, 0x0},
+ {0x90121, 0x1e9},
+ {0x90122, 0x8},
+ {0x90123, 0x8080},
+ {0x90124, 0x108},
+ {0x90125, 0xf},
+ {0x90126, 0x408},
+ {0x90127, 0x169},
+ {0x90128, 0xc},
+ {0x90129, 0x0},
+ {0x9012a, 0x68},
+ {0x9012b, 0x9},
+ {0x9012c, 0x0},
+ {0x9012d, 0x1a9},
+ {0x9012e, 0x0},
+ {0x9012f, 0x408},
+ {0x90130, 0x169},
+ {0x90131, 0x0},
+ {0x90132, 0x8080},
+ {0x90133, 0x108},
+ {0x90134, 0x8},
+ {0x90135, 0x7aa},
+ {0x90136, 0x6a},
+ {0x90137, 0x0},
+ {0x90138, 0x8568},
+ {0x90139, 0x108},
+ {0x9013a, 0xb7},
+ {0x9013b, 0x790},
+ {0x9013c, 0x16a},
+ {0x9013d, 0x1f},
+ {0x9013e, 0x0},
+ {0x9013f, 0x68},
+ {0x90140, 0x8},
+ {0x90141, 0x8558},
+ {0x90142, 0x168},
+ {0x90143, 0xf},
+ {0x90144, 0x408},
+ {0x90145, 0x169},
+ {0x90146, 0xc},
+ {0x90147, 0x0},
+ {0x90148, 0x68},
+ {0x90149, 0x0},
+ {0x9014a, 0x408},
+ {0x9014b, 0x169},
+ {0x9014c, 0x0},
+ {0x9014d, 0x8558},
+ {0x9014e, 0x168},
+ {0x9014f, 0x8},
+ {0x90150, 0x3c8},
+ {0x90151, 0x1a9},
+ {0x90152, 0x3},
+ {0x90153, 0x370},
+ {0x90154, 0x129},
+ {0x90155, 0x20},
+ {0x90156, 0x2aa},
+ {0x90157, 0x9},
+ {0x90158, 0x0},
+ {0x90159, 0x400},
+ {0x9015a, 0x10e},
+ {0x9015b, 0x8},
+ {0x9015c, 0xe8},
+ {0x9015d, 0x109},
+ {0x9015e, 0x0},
+ {0x9015f, 0x8140},
+ {0x90160, 0x10c},
+ {0x90161, 0x10},
+ {0x90162, 0x8138},
+ {0x90163, 0x10c},
+ {0x90164, 0x8},
+ {0x90165, 0x7c8},
+ {0x90166, 0x101},
+ {0x90167, 0x8},
+ {0x90168, 0x0},
+ {0x90169, 0x8},
+ {0x9016a, 0x8},
+ {0x9016b, 0x448},
+ {0x9016c, 0x109},
+ {0x9016d, 0xf},
+ {0x9016e, 0x7c0},
+ {0x9016f, 0x109},
+ {0x90170, 0x0},
+ {0x90171, 0xe8},
+ {0x90172, 0x109},
+ {0x90173, 0x47},
+ {0x90174, 0x630},
+ {0x90175, 0x109},
+ {0x90176, 0x8},
+ {0x90177, 0x618},
+ {0x90178, 0x109},
+ {0x90179, 0x8},
+ {0x9017a, 0xe0},
+ {0x9017b, 0x109},
+ {0x9017c, 0x0},
+ {0x9017d, 0x7c8},
+ {0x9017e, 0x109},
+ {0x9017f, 0x8},
+ {0x90180, 0x8140},
+ {0x90181, 0x10c},
+ {0x90182, 0x0},
+ {0x90183, 0x1},
+ {0x90184, 0x8},
+ {0x90185, 0x8},
+ {0x90186, 0x4},
+ {0x90187, 0x8},
+ {0x90188, 0x8},
+ {0x90189, 0x7c8},
+ {0x9018a, 0x101},
+ {0x90006, 0x0},
+ {0x90007, 0x0},
+ {0x90008, 0x8},
+ {0x90009, 0x0},
+ {0x9000a, 0x0},
+ {0x9000b, 0x0},
+ {0xd00e7, 0x400},
+ {0x90017, 0x0},
+ {0x9001f, 0x2a},
+ {0x90026, 0x6a},
+ {0x400d0, 0x0},
+ {0x400d1, 0x101},
+ {0x400d2, 0x105},
+ {0x400d3, 0x107},
+ {0x400d4, 0x10f},
+ {0x400d5, 0x202},
+ {0x400d6, 0x20a},
+ {0x400d7, 0x20b},
+ {0x2003a, 0x2},
+ {0x2000b, 0x5d},
+ {0x2000c, 0xbb},
+ {0x2000d, 0x753},
+ {0x2000e, 0x2c},
+ {0x12000b, 0xc},
+ {0x12000c, 0x19},
+ {0x12000d, 0xfa},
+ {0x12000e, 0x10},
+ {0x22000b, 0x3},
+ {0x22000c, 0x6},
+ {0x22000d, 0x3e},
+ {0x22000e, 0x10},
+ {0x9000c, 0x0},
+ {0x9000d, 0x173},
+ {0x9000e, 0x60},
+ {0x9000f, 0x6110},
+ {0x90010, 0x2152},
+ {0x90011, 0xdfbd},
+ {0x90012, 0x60},
+ {0x90013, 0x6152},
+ {0x20010, 0x5a},
+ {0x20011, 0x3},
+ {0x120010, 0x5a},
+ {0x120011, 0x3},
+ {0x220010, 0x5a},
+ {0x220011, 0x3},
+ {0x40080, 0xe0},
+ {0x40081, 0x12},
+ {0x40082, 0xe0},
+ {0x40083, 0x12},
+ {0x40084, 0xe0},
+ {0x40085, 0x12},
+ {0x140080, 0xe0},
+ {0x140081, 0x12},
+ {0x140082, 0xe0},
+ {0x140083, 0x12},
+ {0x140084, 0xe0},
+ {0x140085, 0x12},
+ {0x240080, 0xe0},
+ {0x240081, 0x12},
+ {0x240082, 0xe0},
+ {0x240083, 0x12},
+ {0x240084, 0xe0},
+ {0x240085, 0x12},
+ {0x400fd, 0xf},
+ {0x10011, 0x1},
+ {0x10012, 0x1},
+ {0x10013, 0x180},
+ {0x10018, 0x1},
+ {0x10002, 0x6209},
+ {0x100b2, 0x1},
+ {0x101b4, 0x1},
+ {0x102b4, 0x1},
+ {0x103b4, 0x1},
+ {0x104b4, 0x1},
+ {0x105b4, 0x1},
+ {0x106b4, 0x1},
+ {0x107b4, 0x1},
+ {0x108b4, 0x1},
+ {0x11011, 0x1},
+ {0x11012, 0x1},
+ {0x11013, 0x180},
+ {0x11018, 0x1},
+ {0x11002, 0x6209},
+ {0x110b2, 0x1},
+ {0x111b4, 0x1},
+ {0x112b4, 0x1},
+ {0x113b4, 0x1},
+ {0x114b4, 0x1},
+ {0x115b4, 0x1},
+ {0x116b4, 0x1},
+ {0x117b4, 0x1},
+ {0x118b4, 0x1},
+ {0x12011, 0x1},
+ {0x12012, 0x1},
+ {0x12013, 0x180},
+ {0x12018, 0x1},
+ {0x12002, 0x6209},
+ {0x120b2, 0x1},
+ {0x121b4, 0x1},
+ {0x122b4, 0x1},
+ {0x123b4, 0x1},
+ {0x124b4, 0x1},
+ {0x125b4, 0x1},
+ {0x126b4, 0x1},
+ {0x127b4, 0x1},
+ {0x128b4, 0x1},
+ {0x13011, 0x1},
+ {0x13012, 0x1},
+ {0x13013, 0x180},
+ {0x13018, 0x1},
+ {0x13002, 0x6209},
+ {0x130b2, 0x1},
+ {0x131b4, 0x1},
+ {0x132b4, 0x1},
+ {0x133b4, 0x1},
+ {0x134b4, 0x1},
+ {0x135b4, 0x1},
+ {0x136b4, 0x1},
+ {0x137b4, 0x1},
+ {0x138b4, 0x1},
+ {0x2003a, 0x2},
+ {0xc0080, 0x2},
+ {0xd0000, 0x1}
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 3000mts 1D */
+ .drate = 3000,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+ },
+ {
+ /* P0 3000mts 2D */
+ .drate = 3000,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 3000, 400, 100, },
+};
diff --git a/board/kontron/sl-mx8mm/sl-mx8mm.c b/board/kontron/sl-mx8mm/sl-mx8mm.c
new file mode 100644
index 0000000..48376cb
--- /dev/null
+++ b/board/kontron/sl-mx8mm/sl-mx8mm.c
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ */
+
+#include <asm/arch/imx-regs.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <fdt_support.h>
+#include <linux/errno.h>
+#include <net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_phys_sdram_size(phys_size_t *size)
+{
+ u32 ddr_size = readl(M4_BOOTROM_BASE_ADDR);
+
+ if (ddr_size == 4) {
+ *size = 0x100000000;
+ } else if (ddr_size == 3) {
+ *size = 0xc0000000;
+ } else if (ddr_size == 2) {
+ *size = 0x80000000;
+ } else if (ddr_size == 1) {
+ *size = 0x40000000;
+ } else {
+ printf("Unknown DDR type!!!\n");
+ *size = 0x40000000;
+ }
+
+ return 0;
+}
+
+/*
+ * If the SoM is mounted on a baseboard with a USB ethernet controller,
+ * there might be an additional MAC address programmed to the MAC OTP fuses.
+ * Although the i.MX8MM has only one MAC, the MAC0, MAC1 and MAC2 registers
+ * in the OTP fuses can still be used to store two separate addresses.
+ * Try to read the secondary address from MAC1 and MAC2 and adjust the
+ * devicetree so Linux can pick up the MAC address.
+ */
+int fdt_set_usb_eth_addr(void *blob)
+{
+ u32 value = readl(OCOTP_BASE_ADDR + 0x660);
+ unsigned char mac[6];
+ int node, ret;
+
+ mac[0] = value >> 24;
+ mac[1] = value >> 16;
+ mac[2] = value >> 8;
+ mac[3] = value;
+
+ value = readl(OCOTP_BASE_ADDR + 0x650);
+ mac[4] = value >> 24;
+ mac[5] = value >> 16;
+
+ node = fdt_path_offset(blob, fdt_get_alias(blob, "ethernet1"));
+ if (node < 0) {
+ /*
+ * There is no node for the USB ethernet in the devicetree. Just skip.
+ */
+ return 0;
+ }
+
+ if (is_zero_ethaddr(mac)) {
+ printf("\nNo MAC address for USB ethernet set in OTP fuses!\n");
+ return 0;
+ }
+
+ if (!is_valid_ethaddr(mac)) {
+ printf("\nInvalid MAC address for USB ethernet set in OTP fuses!\n");
+ return -EINVAL;
+ }
+
+ ret = fdt_setprop(blob, node, "local-mac-address", &mac, 6);
+ if (ret)
+ ret = fdt_setprop(blob, node, "mac-address", &mac, 6);
+
+ if (ret)
+ printf("\nMissing mac-address or local-mac-address property in dt, skip setting MAC address for USB ethernet\n");
+
+ return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ int ret = fdt_set_usb_eth_addr(blob);
+
+ if (ret)
+ return ret;
+
+ return fdt_fixup_memory(blob, PHYS_SDRAM, gd->ram_size);
+}
+
+int board_init(void)
+{
+ return 0;
+}
diff --git a/board/kontron/sl-mx8mm/spl.c b/board/kontron/sl-mx8mm/spl.c
new file mode 100644
index 0000000..4ef03c8
--- /dev/null
+++ b/board/kontron/sl-mx8mm/spl.c
@@ -0,0 +1,321 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ */
+
+#include <asm/arch/imx8mm_pins.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <dm/uclass.h>
+#include <hang.h>
+#include <i2c.h>
+#include <init.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <power/pca9450.h>
+#include <power/pmic.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+ BOARD_TYPE_KTN_N801X,
+ BOARD_TYPE_KTN_N801X_LVDS,
+ BOARD_TYPE_MAX
+};
+
+#define GPIO_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+#define TOUCH_RESET_GPIO IMX_GPIO_NR(3, 23)
+
+static iomux_v3_cfg_t const i2c1_pads[] = {
+ IMX8MM_PAD_I2C1_SCL_I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL) | MUX_MODE_SION,
+ IMX8MM_PAD_I2C1_SDA_I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL) | MUX_MODE_SION
+};
+
+static iomux_v3_cfg_t const i2c2_pads[] = {
+ IMX8MM_PAD_I2C2_SCL_I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL) | MUX_MODE_SION,
+ IMX8MM_PAD_I2C2_SDA_I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL) | MUX_MODE_SION
+};
+
+static iomux_v3_cfg_t const touch_gpio[] = {
+ IMX8MM_PAD_SAI5_RXD2_GPIO3_IO23 | MUX_PAD_CTRL(GPIO_PAD_CTRL)
+};
+
+static iomux_v3_cfg_t const uart_pads[] = {
+ IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+ IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+ switch (boot_dev_spl) {
+ case USB_BOOT:
+ return BOOT_DEVICE_BOARD;
+ case SPI_NOR_BOOT:
+ return BOOT_DEVICE_SPI;
+ case SD1_BOOT:
+ case MMC1_BOOT:
+ return BOOT_DEVICE_MMC1;
+ case SD2_BOOT:
+ case MMC2_BOOT:
+ return BOOT_DEVICE_MMC2;
+ default:
+ return BOOT_DEVICE_NONE;
+ }
+}
+
+bool check_ram_available(long size)
+{
+ long sz = get_ram_size((long *)PHYS_SDRAM, size);
+
+ if (sz == size)
+ return true;
+
+ return false;
+}
+
+static void spl_dram_init(void)
+{
+ u32 size = 0;
+
+ /*
+ * Try the default DDR settings in lpddr4_timing.c to
+ * comply with the Micron 4GB DDR.
+ */
+ if (!ddr_init(&dram_timing) && check_ram_available(SZ_4G)) {
+ size = 4;
+ } else {
+ /*
+ * Overwrite some values to comply with the Micron 1GB/2GB DDRs.
+ */
+ dram_timing.ddrc_cfg[2].val = 0xa1080020;
+ dram_timing.ddrc_cfg[37].val = 0x1f;
+
+ dram_timing.fsp_msg[0].fsp_cfg[9].val = 0x110;
+ dram_timing.fsp_msg[0].fsp_cfg[21].val = 0x1;
+ dram_timing.fsp_msg[1].fsp_cfg[10].val = 0x110;
+ dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x1;
+ dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x110;
+ dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x1;
+ dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x110;
+ dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x1;
+
+ if (!ddr_init(&dram_timing)) {
+ if (check_ram_available(SZ_2G))
+ size = 2;
+ else if (check_ram_available(SZ_1G))
+ size = 1;
+ }
+ }
+
+ if (size == 0) {
+ printf("Failed to initialize DDR RAM!\n");
+ size = 1;
+ }
+
+ printf("Kontron SL i.MX8MM (N801X) module, %u GB RAM detected\n", size);
+ writel(size, M4_BOOTROM_BASE_ADDR);
+}
+
+static void touch_reset(void)
+{
+ /*
+ * Toggle the reset of the touch panel.
+ */
+ imx_iomux_v3_setup_multiple_pads(touch_gpio, ARRAY_SIZE(touch_gpio));
+
+ gpio_request(TOUCH_RESET_GPIO, "touch_reset");
+ gpio_direction_output(TOUCH_RESET_GPIO, 0);
+ mdelay(20);
+ gpio_direction_output(TOUCH_RESET_GPIO, 1);
+ mdelay(20);
+}
+
+static int i2c_detect(u8 bus, u16 addr)
+{
+ struct udevice *udev;
+ int ret;
+
+ /*
+ * Try to probe the touch controller to check if an LVDS panel is
+ * connected.
+ */
+ ret = i2c_get_chip_for_busnum(bus, addr, 0, &udev);
+ if (ret == 0)
+ return 0;
+
+ return 1;
+}
+
+int do_board_detect(void)
+{
+ bool lvds = false;
+
+ /*
+ * Check the I2C touch controller to detect a LVDS panel.
+ */
+ imx_iomux_v3_setup_multiple_pads(i2c2_pads, ARRAY_SIZE(i2c2_pads));
+ touch_reset();
+
+ if (i2c_detect(1, 0x5d) == 0) {
+ printf("Touch controller detected, assuming LVDS panel...\n");
+ lvds = true;
+ }
+
+ /*
+ * Check the I2C PMIC to detect the deprecated SoM with DA9063.
+ */
+ imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
+
+ if (i2c_detect(0, 0x58) == 0) {
+ printf("### ATTENTION: DEPRECATED SOM REVISION (N8010 Rev0) DETECTED! ###\n");
+ printf("### THIS HW IS NOT SUPPRTED AND BOOTING WILL PROBABLY FAIL ###\n");
+ printf("### PLEASE UPGRADE TO LATEST MODULE ###\n");
+ }
+
+ if (lvds)
+ gd->board_type = BOARD_TYPE_KTN_N801X_LVDS;
+ else
+ gd->board_type = BOARD_TYPE_KTN_N801X;
+
+ return 0;
+}
+
+int board_fit_config_name_match(const char *name)
+{
+ if (gd->board_type == BOARD_TYPE_KTN_N801X_LVDS && is_imx8mm() &&
+ !strncmp(name, "imx8mm-kontron-n801x-s-lvds", 27))
+ return 0;
+
+ if (gd->board_type == BOARD_TYPE_KTN_N801X && is_imx8mm() &&
+ !strncmp(name, "imx8mm-kontron-n801x-s", 22))
+ return 0;
+
+ return -1;
+}
+
+void spl_board_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ puts("Normal Boot\n");
+
+ ret = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@30380000",
+ &dev);
+ if (ret < 0)
+ printf("Failed to find clock node. Check device tree\n");
+}
+
+int board_early_init_f(void)
+{
+ struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+ imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+ set_wdog_reset(wdog);
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+ return 0;
+}
+
+static int power_init_board(void)
+{
+ struct udevice *dev;
+ int ret = pmic_get("pmic@25", &dev);
+
+ if (ret == -ENODEV)
+ puts("No pmic found\n");
+
+ if (ret)
+ return ret;
+
+ /* BUCKxOUT_DVS0/1 control BUCK123 output, clear PRESET_EN */
+ pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
+
+ /* increase VDD_DRAM to 0.95V for 1.5GHz DDR */
+ pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1c);
+
+ /* set VDD_SNVS_0V8 from default 0.85V to 0.8V */
+ pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0);
+
+ /* set WDOG_B_CFG to cold reset */
+ pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
+
+ return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+ int ret;
+
+ arch_cpu_init();
+
+ init_uart_clk(2);
+
+ board_early_init_f();
+
+ timer_init();
+
+ preloader_console_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ ret = spl_init();
+ if (ret) {
+ debug("spl_init() failed: %d\n", ret);
+ hang();
+ }
+
+ enable_tzc380();
+
+ /* PMIC initialization */
+ power_init_board();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* Detect the board type */
+ do_board_detect();
+
+ board_init_r(NULL, 0);
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+ u32 bootdev = spl_boot_device();
+
+ /*
+ * The default boot fuse settings use the SD card (MMC2) as primary
+ * boot device, but allow SPI NOR as a fallback boot device.
+ * We can't detect the fallback case and spl_boot_device() will return
+ * BOOT_DEVICE_MMC2 despite the actual boot device being SPI NOR.
+ * Therefore we try to load U-Boot proper vom SPI NOR after loading
+ * from MMC has failed.
+ */
+ spl_boot_list[0] = bootdev;
+
+ switch (bootdev) {
+ case BOOT_DEVICE_MMC1:
+ case BOOT_DEVICE_MMC2:
+ spl_boot_list[1] = BOOT_DEVICE_SPI;
+ break;
+ }
+}
diff --git a/board/logicpd/omap3som/omap3logic.h b/board/logicpd/omap3som/omap3logic.h
index 0de1f2a..3a6f6c1 100644
--- a/board/logicpd/omap3som/omap3logic.h
+++ b/board/logicpd/omap3som/omap3logic.h
@@ -45,209 +45,209 @@
*/
void set_muxconf_regs(void)
{
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /*SDRC_D1*/
- MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /*SDRC_D2*/
- MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /*SDRC_D3*/
- MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /*SDRC_D4*/
- MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /*SDRC_D5*/
- MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /*SDRC_D6*/
- MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /*SDRC_D7*/
- MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /*SDRC_D8*/
- MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /*SDRC_D9*/
- MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /*SDRC_D10*/
- MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /*SDRC_D11*/
- MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /*SDRC_D12*/
- MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /*SDRC_D13*/
- MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /*SDRC_D14*/
- MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /*SDRC_D15*/
- MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /*SDRC_D16*/
- MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /*SDRC_D17*/
- MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /*SDRC_D18*/
- MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /*SDRC_D19*/
- MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /*SDRC_D20*/
- MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /*SDRC_D21*/
- MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /*SDRC_D22*/
- MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /*SDRC_D23*/
- MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /*SDRC_D24*/
- MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /*SDRC_D25*/
- MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /*SDRC_D26*/
- MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /*SDRC_D27*/
- MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /*SDRC_D28*/
- MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /*SDRC_D29*/
- MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /*SDRC_D30*/
- MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /*SDRC_D31*/
- MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /*SDRC_CLK*/
- MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /*SDRC_DQS0*/
- MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /*SDRC_DQS1*/
- MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /*SDRC_DQS2*/
- MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /*SDRC_DQS3*/
- MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/
- MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | DIS | M0)); /*SDRC_CKE1*/
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*SDRC_CKE0*/
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | DIS | M0)) /*SDRC_CKE1*/
- MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/
- MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/
- MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/
- MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/
- MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/
- MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/
- MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/
- MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/
- MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/
- MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); /*GPMC_A10*/
- MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/
- MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); /*GPMC_D1*/
- MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); /*GPMC_D2*/
- MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); /*GPMC_D3*/
- MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); /*GPMC_D4*/
- MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); /*GPMC_D5*/
- MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); /*GPMC_D6*/
- MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); /*GPMC_D7*/
- MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); /*GPMC_D8*/
- MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); /*GPMC_D9*/
- MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); /*GPMC_D10*/
- MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); /*GPMC_D11*/
- MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); /*GPMC_D12*/
- MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); /*GPMC_D13*/
- MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); /*GPMC_D14*/
- MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); /*GPMC_D15*/
- MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /*GPMC_nCS0*/
- MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)); /*GPMC_nCS1*/
- MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)); /*GPMC_nCS2*/
- MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)); /*GPMC_nCS3*/
- MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/
- MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)); /*GPMC_nCS5*/
- MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M0)); /*GPMC_nCS6*/
- MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)); /*GPMC_nCS7*/
- MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)); /*GPMC_CLK*/
- MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*GPMC_nADV_ALE*/
- MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*GPMC_nOE*/
- MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /*GPMC_nWE*/
- MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); /*GPMC_nBE0_CLE*/
- MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)); /*GPMC_nBE1*/
- MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /*GPMC_nWP*/
- MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /*GPMC_WAIT0*/
- MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)); /*GPMC_WAIT1*/
- MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)); /*GPIO_64*/
- MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)); /*GPMC_WAIT3*/
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) /*GPMC_A8*/
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) /*GPMC_A9*/
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) /*GPMC_A10*/
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/
+ MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)) /*GPMC_nCS4*/
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/
+ MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M0)) /*GPMC_nCS6*/
+ MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) /*GPMC_nCS7*/
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) /*GPMC_CLK*/
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) /*GPMC_nBE0_CLE*/
+ MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) /*GPMC_nBE1*/
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/
- MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /*MMC1_CLK*/
- MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /*MMC1_CMD*/
- MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /*MMC1_DAT0*/
- MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/
- MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/
- MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/
- MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)); /*UART1_TX*/
- MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)); /*UART1_RTS*/
- MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)); /*UART1_CTS*/
- MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)); /*UART1_RX*/
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/
+ MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/
- MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/
- MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/
- MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/
- MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)); /*JTAG_EMU0*/
- MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)); /*JTAG_EMU1*/
+ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/
+ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/
+ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/
+ MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/
+ MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/
- MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)); /*ETK_CLK*/
- MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)); /*ETK_CTL*/
- MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)); /*ETK_D0*/
- MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)); /*ETK_D1*/
- MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)); /*ETK_D2*/
- MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)); /*ETK_D3*/
- MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)); /*ETK_D4*/
- MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)); /*ETK_D5*/
- MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)); /*ETK_D6*/
- MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)); /*ETK_D7*/
- MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)); /*ETK_D8*/
- MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)); /*ETK_D9*/
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)) /*ETK_CLK*/
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)) /*ETK_CTL*/
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)) /*ETK_D0*/
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)) /*ETK_D1*/
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)) /*ETK_D2*/
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)) /*ETK_D3*/
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)) /*ETK_D4*/
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)) /*ETK_D5*/
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)) /*ETK_D6*/
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)) /*ETK_D7*/
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)) /*ETK_D8*/
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)) /*ETK_D9*/
#ifndef CONFIG_USB_EHCI_OMAP /* Torpedo does not use EHCI_OMAP */
- MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)); /*ETK_D10*/
- MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)); /*ETK_D11*/
- MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)); /*ETK_D12*/
- MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)); /*ETK_D13*/
- MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)); /*ETK_D14*/
- MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)); /*ETK_D15*/
+ MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)) /*ETK_D10*/
+ MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)) /*ETK_D11*/
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)) /*ETK_D12*/
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)) /*ETK_D13*/
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)) /*ETK_D14*/
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)) /*ETK_D15*/
#endif
- MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)); /*d2d_mcad1*/
- MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)); /*d2d_mcad2*/
- MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)); /*d2d_mcad3*/
- MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)); /*d2d_mcad4*/
- MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)); /*d2d_mcad5*/
- MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)); /*d2d_mcad6*/
- MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)); /*d2d_mcad7*/
- MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)); /*d2d_mcad8*/
- MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)); /*d2d_mcad9*/
- MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)); /*d2d_mcad10*/
- MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)); /*d2d_mcad11*/
- MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)); /*d2d_mcad12*/
- MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)); /*d2d_mcad13*/
- MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)); /*d2d_mcad14*/
- MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)); /*d2d_mcad15*/
- MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)); /*d2d_mcad16*/
- MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)); /*d2d_mcad17*/
- MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)); /*d2d_mcad18*/
- MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)); /*d2d_mcad19*/
- MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)); /*d2d_mcad20*/
- MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)); /*d2d_mcad21*/
- MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)); /*d2d_mcad22*/
- MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)); /*d2d_mcad23*/
- MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)); /*d2d_mcad24*/
- MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)); /*d2d_mcad25*/
- MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)); /*d2d_mcad26*/
- MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)); /*d2d_mcad27*/
- MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)); /*d2d_mcad28*/
- MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)); /*d2d_mcad29*/
- MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)); /*d2d_mcad30*/
- MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)); /*d2d_mcad31*/
- MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)); /*d2d_mcad32*/
- MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)); /*d2d_mcad33*/
- MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)); /*d2d_mcad34*/
- MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)); /*d2d_mcad35*/
- MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)); /*d2d_mcad36*/
- MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)); /*d2d_clk26mi*/
- MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)); /*d2d_nrespwron*/
- MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)); /*d2d_nreswarm */
- MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)); /*d2d_arm9nirq */
- MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)); /*d2d_uma2p6fiq*/
- MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)); /*d2d_spint*/
- MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)); /*d2d_frint*/
- MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)); /*d2d_dmareq0*/
- MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)); /*d2d_dmareq1*/
- MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)); /*d2d_dmareq2*/
- MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)); /*d2d_dmareq3*/
- MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)); /*d2d_n3gtrst*/
- MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)); /*d2d_n3gtdi*/
- MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)); /*d2d_n3gtdo*/
- MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)); /*d2d_n3gtms*/
- MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)); /*d2d_n3gtck*/
- MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)); /*d2d_n3grtck*/
- MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)); /*d2d_mstdby*/
- MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)); /*d2d_swakeup*/
- MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)); /*d2d_idlereq*/
- MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)); /*d2d_idleack*/
- MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)); /*d2d_mwrite*/
- MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)); /*d2d_swrite*/
- MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)); /*d2d_mread*/
- MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)); /*d2d_sread*/
- MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)); /*d2d_mbusflag*/
- MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)); /*d2d_sbusflag*/
+ MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/
+ MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/
+ MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/
+ MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/
+ MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/
+ MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/
+ MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/
+ MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/
+ MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/
+ MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/
+ MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/
+ MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/
+ MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/
+ MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/
+ MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/
+ MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/
+ MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/
+ MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/
+ MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/
+ MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/
+ MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/
+ MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/
+ MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/
+ MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/
+ MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/
+ MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/
+ MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/
+ MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/
+ MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/
+ MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/
+ MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/
+ MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/
+ MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/
+ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/
+ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/
+ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/
+ MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/
+ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/
+ MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */
+ MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */
+ MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/
+ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/
+ MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/
+ MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/
+ MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/
+ MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/
+ MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/
+ MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/
+ MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/
+ MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/
+ MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/
+ MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/
+ MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/
+ MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/
+ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/
+ MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/
+ MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/
+ MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/
+ MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/
+ MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/
+ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/
+ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/
+ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/
#ifdef CONFIG_USB_EHCI_OMAP /* SOM-LV Uses EHCI-OMAP */
- MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M3)); /*HSUSB2_DATA0*/
- MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M3)); /*HSUSB2_DATA1*/
- MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)); /*HSUSB2_DATA2*/
- MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)); /*HSUSB2_DATA3*/
- MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)); /*HSUSB2_DATA4*/
- MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)); /*HSUSB2_DATA5*/
- MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)); /*HSUSB2_DATA6*/
- MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)); /*HSUSB2_DATA7*/
- MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */
- MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_CLK*/
- MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/
- MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)); /*HSUSB2_DIR*/
- MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)); /*HSUSB2_NXT*/
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA0*/
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA1*/
+ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)) /*HSUSB2_DATA2*/
+ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) /*HSUSB2_DATA3*/
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) /*HSUSB2_DATA4*/
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /*HSUSB2_DATA5*/
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)) /*HSUSB2_DATA6*/
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) /*HSUSB2_DATA7*/
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */
+ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_CLK*/
+ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_STP*/
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DIR*/
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_NXT*/
#endif
}
diff --git a/board/menlo/m53menlo/m53menlo.c b/board/menlo/m53menlo/m53menlo.c
index 2b331b3..9545e63 100644
--- a/board/menlo/m53menlo/m53menlo.c
+++ b/board/menlo/m53menlo/m53menlo.c
@@ -17,6 +17,7 @@
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux-mx53.h>
+#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/mx5_video.h>
#include <asm/mach-imx/video.h>
#include <asm/gpio.h>
@@ -334,6 +335,10 @@
int board_late_init(void)
{
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(NULL);
+#endif
+
#if defined(CONFIG_VIDEO_IPUV3)
struct udevice *dev;
int xpos, ypos, ret;
diff --git a/board/nvidia/p2371-2180/p2371-2180.c b/board/nvidia/p2371-2180/p2371-2180.c
index 7423a97..816c7be 100644
--- a/board/nvidia/p2371-2180/p2371-2180.c
+++ b/board/nvidia/p2371-2180/p2371-2180.c
@@ -10,11 +10,12 @@
#include <i2c.h>
#include <log.h>
#include <net.h>
+#include <stdlib.h>
#include <linux/bitops.h>
#include <linux/libfdt.h>
#include <asm/arch/gpio.h>
#include <asm/arch/pinmux.h>
-#include <asm/arch-tegra/cboot.h>
+#include <asm/arch-tegra/board.h>
#include "../p2571/max77620_init.h"
void pin_mux_mmc(void)
@@ -83,95 +84,16 @@
}
#endif /* PCI */
-static void ft_mac_address_setup(void *fdt)
-{
- const void *cboot_fdt = (const void *)cboot_boot_x0;
- uint8_t mac[ETH_ALEN], local_mac[ETH_ALEN];
- const char *path;
- int offset, err;
-
- err = cboot_get_ethaddr(cboot_fdt, local_mac);
- if (err < 0)
- memset(local_mac, 0, ETH_ALEN);
-
- path = fdt_get_alias(fdt, "ethernet");
- if (!path)
- return;
-
- debug("ethernet alias found: %s\n", path);
-
- offset = fdt_path_offset(fdt, path);
- if (offset < 0) {
- printf("ethernet alias points to absent node %s\n", path);
- return;
- }
-
- if (is_valid_ethaddr(local_mac)) {
- err = fdt_setprop(fdt, offset, "local-mac-address", local_mac,
- ETH_ALEN);
- if (!err)
- debug("Local MAC address set: %pM\n", local_mac);
- }
-
- if (eth_env_get_enetaddr("ethaddr", mac)) {
- if (memcmp(local_mac, mac, ETH_ALEN) != 0) {
- err = fdt_setprop(fdt, offset, "mac-address", mac,
- ETH_ALEN);
- if (!err)
- debug("MAC address set: %pM\n", mac);
- }
- }
-}
-
-static int ft_copy_carveout(void *dst, const void *src, const char *node)
-{
- struct fdt_memory fb;
- int err;
-
- err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb);
- if (err < 0) {
- if (err != -FDT_ERR_NOTFOUND)
- printf("failed to get carveout for %s: %d\n", node,
- err);
-
- return err;
- }
-
- err = fdtdec_set_carveout(dst, node, "memory-region", 0, "framebuffer",
- &fb);
- if (err < 0) {
- printf("failed to set carveout for %s: %d\n", node, err);
- return err;
- }
-
- return 0;
-}
-
-static void ft_carveout_setup(void *fdt)
-{
- const void *cboot_fdt = (const void *)cboot_boot_x0;
- static const char * const nodes[] = {
- "/host1x@50000000/dc@54200000",
- "/host1x@50000000/dc@54240000",
- };
- unsigned int i;
- int err;
-
- for (i = 0; i < ARRAY_SIZE(nodes); i++) {
- err = ft_copy_carveout(fdt, cboot_fdt, nodes[i]);
- if (err < 0) {
- if (err != -FDT_ERR_NOTFOUND)
- printf("failed to copy carveout for %s: %d\n",
- nodes[i], err);
- continue;
- }
- }
-}
+static const char * const nodes[] = {
+ "/host1x@50000000/dc@54200000",
+ "/host1x@50000000/dc@54240000",
+ "/external-memory-controller@7001b000",
+};
int ft_board_setup(void *fdt, struct bd_info *bd)
{
ft_mac_address_setup(fdt);
- ft_carveout_setup(fdt);
+ ft_carveout_setup(fdt, nodes, ARRAY_SIZE(nodes));
return 0;
}
diff --git a/board/nvidia/p2771-0000/p2771-0000.c b/board/nvidia/p2771-0000/p2771-0000.c
index 508c4d2..5ff89c4 100644
--- a/board/nvidia/p2771-0000/p2771-0000.c
+++ b/board/nvidia/p2771-0000/p2771-0000.c
@@ -9,8 +9,9 @@
#include <i2c.h>
#include <log.h>
#include <net.h>
+#include <stdlib.h>
#include <linux/libfdt.h>
-#include <asm/arch-tegra/cboot.h>
+#include <asm/arch-tegra/board.h>
#include "../p2571/max77620_init.h"
void pin_mux_mmc(void)
@@ -59,99 +60,16 @@
}
#endif
-static void ft_mac_address_setup(void *fdt)
-{
- const void *cboot_fdt = (const void *)cboot_boot_x0;
- uint8_t mac[ETH_ALEN], local_mac[ETH_ALEN];
- const char *path;
- int offset, err;
-
- err = cboot_get_ethaddr(cboot_fdt, local_mac);
- if (err < 0)
- memset(local_mac, 0, ETH_ALEN);
-
- path = fdt_get_alias(fdt, "ethernet");
- if (!path)
- return;
-
- debug("ethernet alias found: %s\n", path);
-
- offset = fdt_path_offset(fdt, path);
- if (offset < 0) {
- printf("ethernet alias points to absent node %s\n", path);
- return;
- }
-
- if (is_valid_ethaddr(local_mac)) {
- err = fdt_setprop(fdt, offset, "local-mac-address", local_mac,
- ETH_ALEN);
- if (!err)
- debug("Local MAC address set: %pM\n", local_mac);
- }
-
- if (eth_env_get_enetaddr("ethaddr", mac)) {
- if (memcmp(local_mac, mac, ETH_ALEN) != 0) {
- err = fdt_setprop(fdt, offset, "mac-address", mac,
- ETH_ALEN);
- if (!err)
- debug("MAC address set: %pM\n", mac);
- }
- }
-}
-
-static int ft_copy_carveout(void *dst, const void *src, const char *node)
-{
- struct fdt_memory fb;
- int err;
-
- err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb);
- if (err < 0) {
- if (err != -FDT_ERR_NOTFOUND)
- printf("failed to get carveout for %s: %d\n", node,
- err);
-
- return err;
- }
-
- err = fdtdec_set_carveout(dst, node, "memory-region", 0, "framebuffer",
- &fb);
- if (err < 0) {
- printf("failed to set carveout for %s: %d\n", node, err);
- return err;
- }
-
- return 0;
-}
-
-static void ft_carveout_setup(void *fdt)
-{
- const void *cboot_fdt = (const void *)cboot_boot_x0;
- static const char * const nodes[] = {
- "/host1x@13e00000/display-hub@15200000/display@15200000",
- "/host1x@13e00000/display-hub@15200000/display@15210000",
- "/host1x@13e00000/display-hub@15200000/display@15220000",
- };
- unsigned int i;
- int err;
-
- for (i = 0; i < ARRAY_SIZE(nodes); i++) {
- printf("copying carveout for %s...\n", nodes[i]);
-
- err = ft_copy_carveout(fdt, cboot_fdt, nodes[i]);
- if (err < 0) {
- if (err != -FDT_ERR_NOTFOUND)
- printf("failed to copy carveout for %s: %d\n",
- nodes[i], err);
-
- continue;
- }
- }
-}
+static const char * const nodes[] = {
+ "/host1x@13e00000/display-hub@15200000/display@15200000",
+ "/host1x@13e00000/display-hub@15200000/display@15210000",
+ "/host1x@13e00000/display-hub@15200000/display@15220000",
+};
int ft_board_setup(void *fdt, struct bd_info *bd)
{
ft_mac_address_setup(fdt);
- ft_carveout_setup(fdt);
+ ft_carveout_setup(fdt, nodes, ARRAY_SIZE(nodes));
return 0;
}
diff --git a/board/nvidia/p3450-0000/p3450-0000.c b/board/nvidia/p3450-0000/p3450-0000.c
index e6b6696..fb1a224 100644
--- a/board/nvidia/p3450-0000/p3450-0000.c
+++ b/board/nvidia/p3450-0000/p3450-0000.c
@@ -11,9 +11,9 @@
#include <linux/bitops.h>
#include <linux/libfdt.h>
#include <pca953x.h>
-#include <asm/arch-tegra/cboot.h>
#include <asm/arch/gpio.h>
#include <asm/arch/pinmux.h>
+#include <asm/arch-tegra/board.h>
#include "../p2571/max77620_init.h"
void pin_mux_mmc(void)
@@ -82,98 +82,16 @@
}
#endif /* PCI */
-static void ft_mac_address_setup(void *fdt)
-{
- const void *cboot_fdt = (const void *)cboot_boot_x0;
- uint8_t mac[ETH_ALEN], local_mac[ETH_ALEN];
- const char *path;
- int offset, err;
-
- err = cboot_get_ethaddr(cboot_fdt, local_mac);
- if (err < 0)
- memset(local_mac, 0, ETH_ALEN);
-
- path = fdt_get_alias(fdt, "ethernet");
- if (!path)
- return;
-
- debug("ethernet alias found: %s\n", path);
-
- offset = fdt_path_offset(fdt, path);
- if (offset < 0) {
- printf("ethernet alias points to absent node %s\n", path);
- return;
- }
-
- if (is_valid_ethaddr(local_mac)) {
- err = fdt_setprop(fdt, offset, "local-mac-address", local_mac,
- ETH_ALEN);
- if (!err)
- debug("Local MAC address set: %pM\n", local_mac);
- }
-
- if (eth_env_get_enetaddr("ethaddr", mac)) {
- if (memcmp(local_mac, mac, ETH_ALEN) != 0) {
- err = fdt_setprop(fdt, offset, "mac-address", mac,
- ETH_ALEN);
- if (!err)
- debug("MAC address set: %pM\n", mac);
- }
- }
-}
-
-static int ft_copy_carveout(void *dst, const void *src, const char *node)
-{
- struct fdt_memory fb;
- int err;
-
- err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb);
- if (err < 0) {
- if (err != -FDT_ERR_NOTFOUND)
- printf("failed to get carveout for %s: %d\n", node,
- err);
-
- return err;
- }
-
- err = fdtdec_set_carveout(dst, node, "memory-region", 0, "framebuffer",
- &fb);
- if (err < 0) {
- printf("failed to set carveout for %s: %d\n", node, err);
- return err;
- }
-
- return 0;
-}
-
-static void ft_carveout_setup(void *fdt)
-{
- const void *cboot_fdt = (const void *)cboot_boot_x0;
- static const char * const nodes[] = {
- "/host1x@50000000/dc@54200000",
- "/host1x@50000000/dc@54240000",
- };
- unsigned int i;
- int err;
-
- for (i = 0; i < ARRAY_SIZE(nodes); i++) {
- printf("copying carveout for %s...\n", nodes[i]);
-
- err = ft_copy_carveout(fdt, cboot_fdt, nodes[i]);
- if (err < 0) {
- if (err != -FDT_ERR_NOTFOUND)
- printf("failed to copy carveout for %s: %d\n",
- nodes[i], err);
-
- continue;
- }
- }
-}
+static const char * const nodes[] = {
+ "/host1x@50000000/dc@54200000",
+ "/host1x@50000000/dc@54240000",
+ "/external-memory-controller@7001b000",
+};
int ft_board_setup(void *fdt, struct bd_info *bd)
{
ft_mac_address_setup(fdt);
- ft_carveout_setup(fdt);
+ ft_carveout_setup(fdt, nodes, ARRAY_SIZE(nodes));
return 0;
}
diff --git a/board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg b/board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg
index b2920b4..4c3ecf5 100644
--- a/board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg
+++ b/board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg
@@ -7,4 +7,4 @@
ROM_VERSION v2
BOOT_FROM sd
-LOADER mkimage.flash.mkimage 0x920000
+LOADER u-boot-spl-ddr.bin 0x920000
diff --git a/board/sifive/unleashed/unleashed.c b/board/sifive/unleashed/unleashed.c
index 8cd514d..e7d2332 100644
--- a/board/sifive/unleashed/unleashed.c
+++ b/board/sifive/unleashed/unleashed.c
@@ -118,10 +118,10 @@
{
if (IS_ENABLED(CONFIG_OF_SEPARATE)) {
if (gd->arch.firmware_fdt_addr)
- return (ulong *)gd->arch.firmware_fdt_addr;
- else
- return (ulong *)&_end;
+ return (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr;
}
+
+ return (ulong *)&_end;
}
int board_init(void)
diff --git a/board/sifive/unmatched/unmatched.c b/board/sifive/unmatched/unmatched.c
index d90b252..93c452c 100644
--- a/board/sifive/unmatched/unmatched.c
+++ b/board/sifive/unmatched/unmatched.c
@@ -15,10 +15,10 @@
{
if (IS_ENABLED(CONFIG_OF_SEPARATE)) {
if (gd->arch.firmware_fdt_addr)
- return (ulong *)gd->arch.firmware_fdt_addr;
- else
- return (ulong *)&_end;
+ return (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr;
}
+
+ return (ulong *)&_end;
}
int board_init(void)
diff --git a/board/st/stm32f429-discovery/stm32f429-discovery.c b/board/st/stm32f429-discovery/stm32f429-discovery.c
index 34f9d6b..55e464c 100644
--- a/board/st/stm32f429-discovery/stm32f429-discovery.c
+++ b/board/st/stm32f429-discovery/stm32f429-discovery.c
@@ -48,8 +48,6 @@
int board_init(void)
{
- gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
-
return 0;
}
diff --git a/board/st/stm32f429-evaluation/stm32f429-evaluation.c b/board/st/stm32f429-evaluation/stm32f429-evaluation.c
index c170314..25472f0 100644
--- a/board/st/stm32f429-evaluation/stm32f429-evaluation.c
+++ b/board/st/stm32f429-evaluation/stm32f429-evaluation.c
@@ -42,8 +42,6 @@
int board_init(void)
{
- gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
-
return 0;
}
diff --git a/board/st/stm32f469-discovery/stm32f469-discovery.c b/board/st/stm32f469-discovery/stm32f469-discovery.c
index 122273a..9ed6c1e 100644
--- a/board/st/stm32f469-discovery/stm32f469-discovery.c
+++ b/board/st/stm32f469-discovery/stm32f469-discovery.c
@@ -42,8 +42,6 @@
int board_init(void)
{
- gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
-
return 0;
}
diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c
index 376bc06..08c2102 100644
--- a/board/st/stm32f746-disco/stm32f746-disco.c
+++ b/board/st/stm32f746-disco/stm32f746-disco.c
@@ -117,8 +117,6 @@
int board_init(void)
{
- gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
-
#ifdef CONFIG_ETH_DESIGNWARE
const char *phy_mode;
int node;
diff --git a/board/st/stm32h743-disco/stm32h743-disco.c b/board/st/stm32h743-disco/stm32h743-disco.c
index cc87230..4ca5e84 100644
--- a/board/st/stm32h743-disco/stm32h743-disco.c
+++ b/board/st/stm32h743-disco/stm32h743-disco.c
@@ -38,6 +38,5 @@
int board_init(void)
{
- gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
return 0;
}
diff --git a/board/st/stm32h743-eval/stm32h743-eval.c b/board/st/stm32h743-eval/stm32h743-eval.c
index cc87230..4ca5e84 100644
--- a/board/st/stm32h743-eval/stm32h743-eval.c
+++ b/board/st/stm32h743-eval/stm32h743-eval.c
@@ -38,6 +38,5 @@
int board_init(void)
{
- gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
return 0;
}
diff --git a/board/st/stm32h750-art-pi/stm32h750-art-pi.c b/board/st/stm32h750-art-pi/stm32h750-art-pi.c
index 0ece8e7..0d39ce8 100644
--- a/board/st/stm32h750-art-pi/stm32h750-art-pi.c
+++ b/board/st/stm32h750-art-pi/stm32h750-art-pi.c
@@ -48,6 +48,5 @@
int board_init(void)
{
- gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
return 0;
}
diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
index 1d4d7b4..2c2faad 100644
--- a/board/st/stm32mp1/stm32mp1.c
+++ b/board/st/stm32mp1/stm32mp1.c
@@ -647,12 +647,6 @@
/* board dependent setup after realloc */
int board_init(void)
{
- /* address of boot parameters */
- gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
-
- if (CONFIG_IS_ENABLED(DM_GPIO_HOG))
- gpio_hog_probe_all();
-
board_key_check();
if (board_is_ev1())
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index 4fc2607..56a0ee3 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -358,6 +358,11 @@
S: Maintained
F: configs/nanopi_neo_air_defconfig
+NANOPI-R1S-H5 BOARD
+M: Chukun Pan <amadeus@jmu.edu.cn>
+S: Maintained
+F: configs/nanopi_r1s_h5_defconfig
+
NANOPI-A64 BOARD
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
@@ -471,6 +476,11 @@
S: Maintained
F: configs/pinephone_defconfig
+PINETAB BOARD
+M: Arnaud Ferraris <arnaud.ferraris@collabora.com>
+S: Maintained
+F: configs/pinetab_defconfig
+
R16 EVB PARROT BOARD
M: Quentin Schulz <quentin.schulz@free-electrons.com>
S: Maintained
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 2b7d655..4f5747c 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -25,7 +25,6 @@
#include <asm/arch/cpu.h>
#include <asm/arch/display.h>
#include <asm/arch/dram.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
#include <asm/arch/prcm.h>
#include <asm/arch/spl.h>
@@ -46,47 +45,7 @@
#include <spl.h>
#include <sy8106a.h>
#include <asm/setup.h>
-
-#if defined(CONFIG_VIDEO_LCD_PANEL_I2C)
-/* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
-int soft_i2c_gpio_sda;
-int soft_i2c_gpio_scl;
-
-static int soft_i2c_board_init(void)
-{
- int ret;
-
- soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
- if (soft_i2c_gpio_sda < 0) {
- printf("Error invalid soft i2c sda pin: '%s', err %d\n",
- CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
- return soft_i2c_gpio_sda;
- }
- ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
- if (ret) {
- printf("Error requesting soft i2c sda pin: '%s', err %d\n",
- CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
- return ret;
- }
-
- soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
- if (soft_i2c_gpio_scl < 0) {
- printf("Error invalid soft i2c scl pin: '%s', err %d\n",
- CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
- return soft_i2c_gpio_scl;
- }
- ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
- if (ret) {
- printf("Error requesting soft i2c scl pin: '%s', err %d\n",
- CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
- return ret;
- }
-
- return 0;
-}
-#else
-static int soft_i2c_board_init(void) { return 0; }
-#endif
+#include <status_led.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -312,8 +271,7 @@
#endif
#endif /* CONFIG_DM_MMC */
- /* Uses dm gpio code so do this here and not in i2c_init_board() */
- return soft_i2c_board_init();
+ return 0;
}
/*
@@ -413,7 +371,6 @@
static void mmc_pinmux_setup(int sdc)
{
unsigned int pin;
- __maybe_unused int pins;
switch (sdc) {
case 0:
@@ -426,11 +383,9 @@
break;
case 1:
- pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
-
#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
defined(CONFIG_MACH_SUN8I_R40)
- if (pins == SUNXI_GPIO_H) {
+ if (IS_ENABLED(CONFIG_MMC1_PINS_PH)) {
/* SDC1: PH22-PH-27 */
for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
@@ -460,27 +415,16 @@
sunxi_gpio_set_drv(pin, 2);
}
#elif defined(CONFIG_MACH_SUN8I)
- if (pins == SUNXI_GPIO_D) {
- /* SDC1: PD2-PD7 */
- for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
- sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
- sunxi_gpio_set_drv(pin, 2);
- }
- } else {
- /* SDC1: PG0-PG5 */
- for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
- sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
- sunxi_gpio_set_drv(pin, 2);
- }
+ /* SDC1: PG0-PG5 */
+ for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
}
#endif
break;
case 2:
- pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
-
#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
/* SDC2: PC6-PC11 */
for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
@@ -489,41 +433,23 @@
sunxi_gpio_set_drv(pin, 2);
}
#elif defined(CONFIG_MACH_SUN5I)
- if (pins == SUNXI_GPIO_E) {
- /* SDC2: PE4-PE9 */
- for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
- sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
- sunxi_gpio_set_drv(pin, 2);
- }
- } else {
- /* SDC2: PC6-PC15 */
- for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
- sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
- sunxi_gpio_set_drv(pin, 2);
- }
+ /* SDC2: PC6-PC15 */
+ for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
}
#elif defined(CONFIG_MACH_SUN6I)
- if (pins == SUNXI_GPIO_A) {
- /* SDC2: PA9-PA14 */
- for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
- sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
- sunxi_gpio_set_drv(pin, 2);
- }
- } else {
- /* SDC2: PC6-PC15, PC24 */
- for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
- sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
- sunxi_gpio_set_drv(pin, 2);
- }
-
- sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
- sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
- sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
+ /* SDC2: PC6-PC15, PC24 */
+ for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
}
+
+ sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
+ sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
#elif defined(CONFIG_MACH_SUN8I_R40)
/* SDC2: PC6-PC15, PC24 */
for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
@@ -579,8 +505,6 @@
break;
case 3:
- pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
-
#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
defined(CONFIG_MACH_SUN8I_R40)
/* SDC3: PI4-PI9 */
@@ -590,25 +514,16 @@
sunxi_gpio_set_drv(pin, 2);
}
#elif defined(CONFIG_MACH_SUN6I)
- if (pins == SUNXI_GPIO_A) {
- /* SDC3: PA9-PA14 */
- for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
- sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
- sunxi_gpio_set_drv(pin, 2);
- }
- } else {
- /* SDC3: PC6-PC15, PC24 */
- for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
- sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
- sunxi_gpio_set_drv(pin, 2);
- }
-
- sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
- sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
- sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
+ /* SDC3: PC6-PC15, PC24 */
+ for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
}
+
+ sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
+ sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
#endif
break;
@@ -672,6 +587,11 @@
{
int power_failed = 0;
+#ifdef CONFIG_LED_STATUS
+ if (IS_ENABLED(CONFIG_SPL_DRIVERS_MISC))
+ status_led_init();
+#endif
+
#ifdef CONFIG_SY8106A_POWER
power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
#endif
diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c
index d8fdf772..1fa54ed 100644
--- a/board/sunxi/gmac.c
+++ b/board/sunxi/gmac.c
@@ -4,7 +4,6 @@
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
void eth_init_board(void)
{
diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c
index 892b94b..226fbba 100644
--- a/board/synopsys/hsdk/hsdk.c
+++ b/board/synopsys/hsdk/hsdk.c
@@ -871,7 +871,7 @@
if (env_common.core_mask.val == ALL_CPU_MASK)
return 0;
- if (!IMAGE_ENABLE_OF_LIBFDT || !images->ft_len) {
+ if (!CONFIG_IS_ENABLED(OF_LIBFDT) || !images->ft_len) {
pr_err("WARN: core_mask setup will work properly only with external DTB!\n");
return 0;
}
diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c
index f4cd28d..25a4cd9 100644
--- a/board/toradex/apalis_imx6/apalis_imx6.c
+++ b/board/toradex/apalis_imx6/apalis_imx6.c
@@ -1076,6 +1076,24 @@
writel(table[2 * i + 1], table[2 * i]);
}
+/* Perform DDR DRAM calibration */
+static void spl_dram_perform_cal(void)
+{
+#ifdef CONFIG_MX6_DDRCAL
+ int err;
+ struct mx6_ddr_sysinfo ddr_sysinfo = {
+ .dsize = 2,
+ };
+
+ err = mmdc_do_write_level_calibration(&ddr_sysinfo);
+ if (err)
+ printf("error %d from write level calibration\n", err);
+ err = mmdc_do_dqs_calibration(&ddr_sysinfo);
+ if (err)
+ printf("error %d from dqs calibration\n", err);
+#endif
+}
+
static void spl_dram_init(void)
{
int minc, maxc;
@@ -1094,6 +1112,7 @@
break;
};
udelay(100);
+ spl_dram_perform_cal();
}
void board_init_f(ulong dummy)
diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c
index 3b55f6c..38ff637 100644
--- a/board/toradex/colibri_imx6/colibri_imx6.c
+++ b/board/toradex/colibri_imx6/colibri_imx6.c
@@ -997,9 +997,28 @@
writel(table[2 * i + 1], table[2 * i]);
}
+/* Perform DDR DRAM calibration */
+static void spl_dram_perform_cal(u8 dsize)
+{
+#ifdef CONFIG_MX6_DDRCAL
+ int err;
+ struct mx6_ddr_sysinfo ddr_sysinfo = {
+ .dsize = dsize,
+ };
+
+ err = mmdc_do_write_level_calibration(&ddr_sysinfo);
+ if (err)
+ printf("error %d from write level calibration\n", err);
+ err = mmdc_do_dqs_calibration(&ddr_sysinfo);
+ if (err)
+ printf("error %d from dqs calibration\n", err);
+#endif
+}
+
static void spl_dram_init(void)
{
int minc, maxc;
+ u8 dsize = 2;
switch (get_cpu_temp_grade(&minc, &maxc)) {
case TEMP_COMMERCIAL:
@@ -1009,6 +1028,7 @@
ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
} else {
puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n");
+ dsize = 1;
ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
}
break;
@@ -1020,11 +1040,13 @@
ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
} else {
puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n");
+ dsize = 1;
ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
}
break;
};
udelay(100);
+ spl_dram_perform_cal(dsize);
}
static iomux_v3_cfg_t const gpio_reset_pad[] = {
diff --git a/cmd/bind.c b/cmd/bind.c
index 07c629e..4d1b788 100644
--- a/cmd/bind.c
+++ b/cmd/bind.c
@@ -152,7 +152,7 @@
}
ofnode = ofnode_path(path);
- ret = lists_bind_fdt(parent, ofnode, &dev, false);
+ ret = lists_bind_fdt(parent, ofnode, &dev, drv, false);
if (!dev || ret) {
printf("Unable to bind. err:%d\n", ret);
diff --git a/cmd/efidebug.c b/cmd/efidebug.c
index 67ab06a..a977ca9 100644
--- a/cmd/efidebug.c
+++ b/cmd/efidebug.c
@@ -1143,10 +1143,7 @@
{
struct efi_device_path *initrd_path = NULL;
struct efi_load_option lo;
- u16 *dp_str;
efi_status_t ret;
- efi_uintn_t initrd_dp_size;
- const efi_guid_t lf2_initrd_guid = EFI_INITRD_MEDIA_GUID;
ret = efi_deserialize_load_option(&lo, data, size);
if (ret != EFI_SUCCESS) {
@@ -1165,15 +1162,11 @@
lo.attributes);
printf(" label: %ls\n", lo.label);
- dp_str = efi_dp_str(lo.file_path);
- printf(" file_path: %ls\n", dp_str);
- efi_free_pool(dp_str);
+ printf(" file_path: %pD\n", lo.file_path);
- initrd_path = efi_dp_from_lo(&lo, &initrd_dp_size, lf2_initrd_guid);
+ initrd_path = efi_dp_from_lo(&lo, &efi_lf2_initrd_guid);
if (initrd_path) {
- dp_str = efi_dp_str(initrd_path);
- printf(" initrd_path: %ls\n", dp_str);
- efi_free_pool(dp_str);
+ printf(" initrd_path: %pD\n", initrd_path);
efi_free_pool(initrd_path);
}
diff --git a/cmd/nvedit.c b/cmd/nvedit.c
index ddc715b..3bb6e76 100644
--- a/cmd/nvedit.c
+++ b/cmd/nvedit.c
@@ -30,7 +30,6 @@
#include <env.h>
#include <env_internal.h>
#include <log.h>
-#include <net.h>
#include <search.h>
#include <errno.h>
#include <malloc.h>
@@ -38,7 +37,6 @@
#include <asm/global_data.h>
#include <linux/bitops.h>
#include <u-boot/crc.h>
-#include <watchdog.h>
#include <linux/stddef.h>
#include <asm/byteorder.h>
#include <asm/io.h>
@@ -320,69 +318,6 @@
return _do_env_set(0, 3, (char * const *)argv, H_PROGRAMMATIC);
}
-/**
- * Set an environment variable to an integer value
- *
- * @param varname Environment variable to set
- * @param value Value to set it to
- * @return 0 if ok, 1 on error
- */
-int env_set_ulong(const char *varname, ulong value)
-{
- /* TODO: this should be unsigned */
- char *str = simple_itoa(value);
-
- return env_set(varname, str);
-}
-
-/**
- * Set an environment variable to an value in hex
- *
- * @param varname Environment variable to set
- * @param value Value to set it to
- * @return 0 if ok, 1 on error
- */
-int env_set_hex(const char *varname, ulong value)
-{
- char str[17];
-
- sprintf(str, "%lx", value);
- return env_set(varname, str);
-}
-
-ulong env_get_hex(const char *varname, ulong default_val)
-{
- const char *s;
- ulong value;
- char *endp;
-
- s = env_get(varname);
- if (s)
- value = hextoul(s, &endp);
- if (!s || endp == s)
- return default_val;
-
- return value;
-}
-
-int eth_env_get_enetaddr(const char *name, uint8_t *enetaddr)
-{
- string_to_enetaddr(env_get(name), enetaddr);
- return is_valid_ethaddr(enetaddr);
-}
-
-int eth_env_set_enetaddr(const char *name, const uint8_t *enetaddr)
-{
- char buf[ARP_HLEN_ASCII + 1];
-
- if (eth_env_get_enetaddr(name, (uint8_t *)buf))
- return -EEXIST;
-
- sprintf(buf, "%pM", enetaddr);
-
- return env_set(name, buf);
-}
-
#ifndef CONFIG_SPL_BUILD
static int do_env_set(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
@@ -661,115 +596,7 @@
}
}
#endif /* CONFIG_CMD_EDITENV */
-#endif /* CONFIG_SPL_BUILD */
-
-/*
- * Look up variable from environment,
- * return address of storage for that variable,
- * or NULL if not found
- */
-char *env_get(const char *name)
-{
- if (gd->flags & GD_FLG_ENV_READY) { /* after import into hashtable */
- struct env_entry e, *ep;
-
- WATCHDOG_RESET();
-
- e.key = name;
- e.data = NULL;
- hsearch_r(e, ENV_FIND, &ep, &env_htab, 0);
-
- return ep ? ep->data : NULL;
- }
-
- /* restricted capabilities before import */
- if (env_get_f(name, (char *)(gd->env_buf), sizeof(gd->env_buf)) > 0)
- return (char *)(gd->env_buf);
-
- return NULL;
-}
-/*
- * Like env_get, but prints an error if envvar isn't defined in the
- * environment. It always returns what env_get does, so it can be used in
- * place of env_get without changing error handling otherwise.
- */
-char *from_env(const char *envvar)
-{
- char *ret;
-
- ret = env_get(envvar);
-
- if (!ret)
- printf("missing environment variable: %s\n", envvar);
-
- return ret;
-}
-
-/*
- * Look up variable from environment for restricted C runtime env.
- */
-int env_get_f(const char *name, char *buf, unsigned len)
-{
- int i, nxt, c;
-
- for (i = 0; env_get_char(i) != '\0'; i = nxt + 1) {
- int val, n;
-
- for (nxt = i; (c = env_get_char(nxt)) != '\0'; ++nxt) {
- if (c < 0)
- return c;
- if (nxt >= CONFIG_ENV_SIZE)
- return -1;
- }
-
- val = env_match((uchar *)name, i);
- if (val < 0)
- continue;
-
- /* found; copy out */
- for (n = 0; n < len; ++n, ++buf) {
- c = env_get_char(val++);
- if (c < 0)
- return c;
- *buf = c;
- if (*buf == '\0')
- return n;
- }
-
- if (n)
- *--buf = '\0';
-
- printf("env_buf [%u bytes] too small for value of \"%s\"\n",
- len, name);
-
- return n;
- }
-
- return -1;
-}
-
-/**
- * Decode the integer value of an environment variable and return it.
- *
- * @param name Name of environment variable
- * @param base Number base to use (normally 10, or 16 for hex)
- * @param default_val Default value to return if the variable is not
- * found
- * @return the decoded value, or default_val if not found
- */
-ulong env_get_ulong(const char *name, int base, ulong default_val)
-{
- /*
- * We can use env_get() here, even before relocation, since the
- * environment variable value is an integer and thus short.
- */
- const char *str = env_get(name);
-
- return str ? simple_strtoul(str, NULL, base) : default_val;
-}
-
-#ifndef CONFIG_SPL_BUILD
#if defined(CONFIG_CMD_SAVEENV) && defined(ENV_IS_IN_DEVICE)
static int do_env_save(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
@@ -816,21 +643,6 @@
#endif /* CONFIG_SPL_BUILD */
-int env_match(uchar *s1, int i2)
-{
- if (s1 == NULL)
- return -1;
-
- while (*s1 == env_get_char(i2++))
- if (*s1++ == '=')
- return i2;
-
- if (*s1 == '\0' && env_get_char(i2-1) == '=')
- return i2;
-
- return -1;
-}
-
#ifndef CONFIG_SPL_BUILD
static int do_env_default(struct cmd_tbl *cmdtp, int flag,
int argc, char *const argv[])
diff --git a/cmd/pci.c b/cmd/pci.c
index cfabdc0..3b1863f 100644
--- a/cmd/pci.c
+++ b/cmd/pci.c
@@ -71,10 +71,15 @@
int prefetchable;
dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
+ header_type &= 0x7f;
if (header_type == PCI_HEADER_TYPE_CARDBUS) {
printf("CardBus doesn't support BARs\n");
return -ENOSYS;
+ } else if (header_type != PCI_HEADER_TYPE_NORMAL &&
+ header_type != PCI_HEADER_TYPE_BRIDGE) {
+ printf("unknown header type\n");
+ return -ENOSYS;
}
bar_cnt = (header_type == PCI_HEADER_TYPE_NORMAL) ? 6 : 2;
@@ -234,7 +239,7 @@
pci_class_str(class));
pci_show_regs(dev, regs_rest);
- switch (header_type & 0x03) {
+ switch (header_type & 0x7f) {
case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */
pci_show_regs(dev, regs_normal);
break;
diff --git a/cmd/tlv_eeprom.c b/cmd/tlv_eeprom.c
index 2b643f9..bf8d453 100644
--- a/cmd/tlv_eeprom.c
+++ b/cmd/tlv_eeprom.c
@@ -169,6 +169,9 @@
{
int tlv_end;
int curr_tlv;
+#ifdef DEBUG
+ int i;
+#endif
struct tlvinfo_header *eeprom_hdr = to_header(eeprom);
struct tlvinfo_tlv *eeprom_tlv;
diff --git a/cmd/unlz4.c b/cmd/unlz4.c
index 323ab46..5f20838 100644
--- a/cmd/unlz4.c
+++ b/cmd/unlz4.c
@@ -7,7 +7,7 @@
#include <common.h>
#include <command.h>
#include <env.h>
-#include <lz4.h>
+#include <u-boot/lz4.h>
static int do_unlz4(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
diff --git a/common/Kconfig b/common/Kconfig
index 0543b83..d6f77ab 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -182,8 +182,8 @@
default y if CONSOLE_MUX
help
This allows multiple input/output devices to be set at boot time.
- For example, if stdout is set to "serial,video" then output will
- be sent to both the serial and video devices on boot. The
+ For example, if stdout is set to "serial,vidconsole" then output
+ will be sent to both the serial and video devices on boot. The
environment variables can be updated after boot to change the
input/output devices.
diff --git a/common/Kconfig.boot b/common/Kconfig.boot
index f23b998..9b84a8d 100644
--- a/common/Kconfig.boot
+++ b/common/Kconfig.boot
@@ -165,6 +165,16 @@
select SPL_IMAGE_SIGN_INFO
select SPL_FIT_FULL_CHECK
+config SPL_FIT_SIGNATURE_MAX_SIZE
+ hex "Max size of signed FIT structures in SPL"
+ depends on SPL_FIT_SIGNATURE
+ default 0x10000000
+ help
+ This option sets a max size in bytes for verified FIT uImages.
+ A sane value of 256MB protects corrupted DTB structures from overlapping
+ device memory. Assure this size does not extend past expected storage
+ space.
+
config SPL_LOAD_FIT
bool "Enable SPL loading U-Boot as a FIT (basic fitImage features)"
select SPL_FIT
diff --git a/common/Makefile b/common/Makefile
index fb8173a..e783902 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -101,7 +101,7 @@
endif
endif
-obj-y += image.o
+obj-y += image.o image-board.o
obj-$(CONFIG_$(SPL_TPL_)HASH) += hash.o
obj-$(CONFIG_ANDROID_AB) += android_ab.o
obj-$(CONFIG_ANDROID_BOOT_IMAGE) += image-android.o image-android-dt.o
diff --git a/common/bootm.c b/common/bootm.c
index ea71522..4482f84 100644
--- a/common/bootm.c
+++ b/common/bootm.c
@@ -115,7 +115,7 @@
images.os.arch = image_get_arch(os_hdr);
break;
#endif
-#if IMAGE_ENABLE_FIT
+#if CONFIG_IS_ENABLED(FIT)
case IMAGE_FORMAT_FIT:
if (fit_image_get_type(images.fit_hdr_os,
images.fit_noffset_os,
@@ -187,7 +187,7 @@
/* Kernel entry point is the setup.bin */
} else if (images.legacy_hdr_valid) {
images.ep = image_get_ep(&images.legacy_hdr_os_copy);
-#if IMAGE_ENABLE_FIT
+#if CONFIG_IS_ENABLED(FIT)
} else if (images.fit_uname_os) {
int ret;
@@ -271,7 +271,7 @@
return 1;
}
-#if IMAGE_ENABLE_OF_LIBFDT
+#if CONFIG_IS_ENABLED(OF_LIBFDT)
/* find flattened device tree */
ret = boot_get_fdt(flag, argc, argv, IH_ARCH_DEFAULT, &images,
&images.ft_addr, &images.ft_len);
@@ -295,16 +295,16 @@
set_working_fdt_addr(map_to_sysmem(images.ft_addr));
#endif
-#if IMAGE_ENABLE_FIT
-#if defined(CONFIG_FPGA)
- /* find bitstreams */
- ret = boot_get_fpga(argc, argv, &images, IH_ARCH_DEFAULT,
- NULL, NULL);
- if (ret) {
- printf("FPGA image is corrupted or invalid\n");
- return 1;
+#if CONFIG_IS_ENABLED(FIT)
+ if (IS_ENABLED(CONFIG_FPGA)) {
+ /* find bitstreams */
+ ret = boot_get_fpga(argc, argv, &images, IH_ARCH_DEFAULT,
+ NULL, NULL);
+ if (ret) {
+ printf("FPGA image is corrupted or invalid\n");
+ return 1;
+ }
}
-#endif
/* find all of the loadables */
ret = boot_get_loadable(argc, argv, &images, IH_ARCH_DEFAULT,
@@ -706,7 +706,7 @@
}
}
#endif
-#if IMAGE_ENABLE_OF_LIBFDT && defined(CONFIG_LMB)
+#if CONFIG_IS_ENABLED(OF_LIBFDT) && defined(CONFIG_LMB)
if (!ret && (states & BOOTM_STATE_FDT)) {
boot_fdt_add_mem_rsv_regions(&images->lmb, images->ft_addr);
ret = boot_relocate_fdt(&images->lmb, &images->ft_addr,
@@ -858,7 +858,7 @@
const void *buf;
const char *fit_uname_config = NULL;
const char *fit_uname_kernel = NULL;
-#if IMAGE_ENABLE_FIT
+#if CONFIG_IS_ENABLED(FIT)
int os_noffset;
#endif
@@ -916,7 +916,7 @@
bootstage_mark(BOOTSTAGE_ID_DECOMP_IMAGE);
break;
#endif
-#if IMAGE_ENABLE_FIT
+#if CONFIG_IS_ENABLED(FIT)
case IMAGE_FORMAT_FIT:
os_noffset = fit_image_load(images, img_addr,
&fit_uname_kernel, &fit_uname_config,
diff --git a/common/bootm_os.c b/common/bootm_os.c
index d635037..39623f9 100644
--- a/common/bootm_os.c
+++ b/common/bootm_os.c
@@ -58,6 +58,14 @@
}
#endif
+static void __maybe_unused fit_unsupported_reset(const char *msg)
+{
+ if (CONFIG_IS_ENABLED(FIT_VERBOSE)) {
+ printf("! FIT images not supported for '%s' - must reset board to recover!\n",
+ msg);
+ }
+}
+
#ifdef CONFIG_BOOTM_NETBSD
static int do_bootm_netbsd(int flag, int argc, char *const argv[],
bootm_headers_t *images)
diff --git a/common/hash.c b/common/hash.c
index 3884298..79202e1 100644
--- a/common/hash.c
+++ b/common/hash.c
@@ -24,7 +24,9 @@
#include <u-boot/crc.h>
#else
#include "mkimage.h"
+#include <linux/compiler_attributes.h>
#include <time.h>
+#include <linux/kconfig.h>
#endif /* !USE_HOSTCC*/
#include <hash.h>
@@ -41,8 +43,7 @@
static void reloc_update(void);
-#if defined(CONFIG_SHA1) && !defined(CONFIG_SHA_PROG_HW_ACCEL)
-static int hash_init_sha1(struct hash_algo *algo, void **ctxp)
+static int __maybe_unused hash_init_sha1(struct hash_algo *algo, void **ctxp)
{
sha1_context *ctx = malloc(sizeof(sha1_context));
sha1_starts(ctx);
@@ -50,15 +51,16 @@
return 0;
}
-static int hash_update_sha1(struct hash_algo *algo, void *ctx, const void *buf,
- unsigned int size, int is_last)
+static int __maybe_unused hash_update_sha1(struct hash_algo *algo, void *ctx,
+ const void *buf, unsigned int size,
+ int is_last)
{
sha1_update((sha1_context *)ctx, buf, size);
return 0;
}
-static int hash_finish_sha1(struct hash_algo *algo, void *ctx, void *dest_buf,
- int size)
+static int __maybe_unused hash_finish_sha1(struct hash_algo *algo, void *ctx,
+ void *dest_buf, int size)
{
if (size < algo->digest_size)
return -1;
@@ -67,10 +69,8 @@
free(ctx);
return 0;
}
-#endif
-#if defined(CONFIG_SHA256) && !defined(CONFIG_SHA_PROG_HW_ACCEL)
-static int hash_init_sha256(struct hash_algo *algo, void **ctxp)
+static int __maybe_unused hash_init_sha256(struct hash_algo *algo, void **ctxp)
{
sha256_context *ctx = malloc(sizeof(sha256_context));
sha256_starts(ctx);
@@ -78,15 +78,16 @@
return 0;
}
-static int hash_update_sha256(struct hash_algo *algo, void *ctx,
- const void *buf, unsigned int size, int is_last)
+static int __maybe_unused hash_update_sha256(struct hash_algo *algo, void *ctx,
+ const void *buf, uint size,
+ int is_last)
{
sha256_update((sha256_context *)ctx, buf, size);
return 0;
}
-static int hash_finish_sha256(struct hash_algo *algo, void *ctx, void
- *dest_buf, int size)
+static int __maybe_unused hash_finish_sha256(struct hash_algo *algo, void *ctx,
+ void *dest_buf, int size)
{
if (size < algo->digest_size)
return -1;
@@ -95,10 +96,8 @@
free(ctx);
return 0;
}
-#endif
-#if defined(CONFIG_SHA384) && !defined(CONFIG_SHA_PROG_HW_ACCEL)
-static int hash_init_sha384(struct hash_algo *algo, void **ctxp)
+static int __maybe_unused hash_init_sha384(struct hash_algo *algo, void **ctxp)
{
sha512_context *ctx = malloc(sizeof(sha512_context));
sha384_starts(ctx);
@@ -106,15 +105,16 @@
return 0;
}
-static int hash_update_sha384(struct hash_algo *algo, void *ctx,
- const void *buf, unsigned int size, int is_last)
+static int __maybe_unused hash_update_sha384(struct hash_algo *algo, void *ctx,
+ const void *buf, uint size,
+ int is_last)
{
sha384_update((sha512_context *)ctx, buf, size);
return 0;
}
-static int hash_finish_sha384(struct hash_algo *algo, void *ctx, void
- *dest_buf, int size)
+static int __maybe_unused hash_finish_sha384(struct hash_algo *algo, void *ctx,
+ void *dest_buf, int size)
{
if (size < algo->digest_size)
return -1;
@@ -123,10 +123,8 @@
free(ctx);
return 0;
}
-#endif
-#if defined(CONFIG_SHA512) && !defined(CONFIG_SHA_PROG_HW_ACCEL)
-static int hash_init_sha512(struct hash_algo *algo, void **ctxp)
+static int __maybe_unused hash_init_sha512(struct hash_algo *algo, void **ctxp)
{
sha512_context *ctx = malloc(sizeof(sha512_context));
sha512_starts(ctx);
@@ -134,15 +132,16 @@
return 0;
}
-static int hash_update_sha512(struct hash_algo *algo, void *ctx,
- const void *buf, unsigned int size, int is_last)
+static int __maybe_unused hash_update_sha512(struct hash_algo *algo, void *ctx,
+ const void *buf, uint size,
+ int is_last)
{
sha512_update((sha512_context *)ctx, buf, size);
return 0;
}
-static int hash_finish_sha512(struct hash_algo *algo, void *ctx, void
- *dest_buf, int size)
+static int __maybe_unused hash_finish_sha512(struct hash_algo *algo, void *ctx,
+ void *dest_buf, int size)
{
if (size < algo->digest_size)
return -1;
@@ -151,8 +150,6 @@
free(ctx);
return 0;
}
-#endif
-
static int hash_init_crc16_ccitt(struct hash_algo *algo, void **ctxp)
{
@@ -181,7 +178,7 @@
return 0;
}
-static int hash_init_crc32(struct hash_algo *algo, void **ctxp)
+static int __maybe_unused hash_init_crc32(struct hash_algo *algo, void **ctxp)
{
uint32_t *ctx = malloc(sizeof(uint32_t));
*ctx = 0;
@@ -189,15 +186,16 @@
return 0;
}
-static int hash_update_crc32(struct hash_algo *algo, void *ctx,
- const void *buf, unsigned int size, int is_last)
+static int __maybe_unused hash_update_crc32(struct hash_algo *algo, void *ctx,
+ const void *buf, unsigned int size,
+ int is_last)
{
*((uint32_t *)ctx) = crc32(*((uint32_t *)ctx), buf, size);
return 0;
}
-static int hash_finish_crc32(struct hash_algo *algo, void *ctx, void *dest_buf,
- int size)
+static int __maybe_unused hash_finish_crc32(struct hash_algo *algo, void *ctx,
+ void *dest_buf, int size)
{
if (size < algo->digest_size)
return -1;
@@ -207,18 +205,13 @@
return 0;
}
-#ifdef USE_HOSTCC
-# define I_WANT_MD5 1
-#else
-# define I_WANT_MD5 CONFIG_IS_ENABLED(MD5)
-#endif
/*
* These are the hash algorithms we support. If we have hardware acceleration
* is enable we will use that, otherwise a software version of the algorithm.
* Note that algorithm names must be in lower case.
*/
static struct hash_algo hash_algo[] = {
-#if I_WANT_MD5
+#if CONFIG_IS_ENABLED(MD5)
{
.name = "md5",
.digest_size = MD5_SUM_LEN,
@@ -226,17 +219,17 @@
.hash_func_ws = md5_wd,
},
#endif
-#ifdef CONFIG_SHA1
+#if CONFIG_IS_ENABLED(SHA1)
{
.name = "sha1",
.digest_size = SHA1_SUM_LEN,
.chunk_size = CHUNKSZ_SHA1,
-#ifdef CONFIG_SHA_HW_ACCEL
+#if CONFIG_IS_ENABLED(SHA_HW_ACCEL)
.hash_func_ws = hw_sha1,
#else
.hash_func_ws = sha1_csum_wd,
#endif
-#ifdef CONFIG_SHA_PROG_HW_ACCEL
+#if CONFIG_IS_ENABLED(SHA_PROG_HW_ACCEL)
.hash_init = hw_sha_init,
.hash_update = hw_sha_update,
.hash_finish = hw_sha_finish,
@@ -247,17 +240,17 @@
#endif
},
#endif
-#ifdef CONFIG_SHA256
+#if CONFIG_IS_ENABLED(SHA256)
{
.name = "sha256",
.digest_size = SHA256_SUM_LEN,
.chunk_size = CHUNKSZ_SHA256,
-#ifdef CONFIG_SHA_HW_ACCEL
+#if CONFIG_IS_ENABLED(SHA_HW_ACCEL)
.hash_func_ws = hw_sha256,
#else
.hash_func_ws = sha256_csum_wd,
#endif
-#ifdef CONFIG_SHA_PROG_HW_ACCEL
+#if CONFIG_IS_ENABLED(SHA_PROG_HW_ACCEL)
.hash_init = hw_sha_init,
.hash_update = hw_sha_update,
.hash_finish = hw_sha_finish,
@@ -268,17 +261,17 @@
#endif
},
#endif
-#ifdef CONFIG_SHA384
+#if CONFIG_IS_ENABLED(SHA384)
{
.name = "sha384",
.digest_size = SHA384_SUM_LEN,
.chunk_size = CHUNKSZ_SHA384,
-#ifdef CONFIG_SHA512_HW_ACCEL
+#if CONFIG_IS_ENABLED(SHA512_HW_ACCEL)
.hash_func_ws = hw_sha384,
#else
.hash_func_ws = sha384_csum_wd,
#endif
-#if defined(CONFIG_SHA512_HW_ACCEL) && defined(CONFIG_SHA_PROG_HW_ACCEL)
+#if CONFIG_IS_ENABLED(SHA512_HW_ACCEL) && CONFIG_IS_ENABLED(SHA_PROG_HW_ACCEL)
.hash_init = hw_sha_init,
.hash_update = hw_sha_update,
.hash_finish = hw_sha_finish,
@@ -289,17 +282,17 @@
#endif
},
#endif
-#ifdef CONFIG_SHA512
+#if CONFIG_IS_ENABLED(SHA512)
{
.name = "sha512",
.digest_size = SHA512_SUM_LEN,
.chunk_size = CHUNKSZ_SHA512,
-#ifdef CONFIG_SHA512_HW_ACCEL
+#if CONFIG_IS_ENABLED(SHA512_HW_ACCEL)
.hash_func_ws = hw_sha512,
#else
.hash_func_ws = sha512_csum_wd,
#endif
-#if defined(CONFIG_SHA512_HW_ACCEL) && defined(CONFIG_SHA_PROG_HW_ACCEL)
+#if CONFIG_IS_ENABLED(SHA512_HW_ACCEL) && CONFIG_IS_ENABLED(SHA_PROG_HW_ACCEL)
.hash_init = hw_sha_init,
.hash_update = hw_sha_update,
.hash_finish = hw_sha_finish,
@@ -319,6 +312,7 @@
.hash_update = hash_update_crc16_ccitt,
.hash_finish = hash_finish_crc16_ccitt,
},
+#if CONFIG_IS_ENABLED(CRC32)
{
.name = "crc32",
.digest_size = 4,
@@ -328,12 +322,13 @@
.hash_update = hash_update_crc32,
.hash_finish = hash_finish_crc32,
},
+#endif
};
/* Try to minimize code size for boards that don't want much hashing */
-#if defined(CONFIG_SHA256) || defined(CONFIG_CMD_SHA1SUM) || \
- defined(CONFIG_CRC32_VERIFY) || defined(CONFIG_CMD_HASH) || \
- defined(CONFIG_SHA384) || defined(CONFIG_SHA512)
+#if CONFIG_IS_ENABLED(SHA256) || CONFIG_IS_ENABLED(CMD_SHA1SUM) || \
+ CONFIG_IS_ENABLED(CRC32_VERIFY) || CONFIG_IS_ENABLED(CMD_HASH) || \
+ CONFIG_IS_ENABLED(SHA384) || CONFIG_IS_ENABLED(SHA512)
#define multi_hash() 1
#else
#define multi_hash() 0
@@ -438,7 +433,8 @@
return 0;
}
-#if defined(CONFIG_CMD_HASH) || defined(CONFIG_CMD_SHA1SUM) || defined(CONFIG_CMD_CRC32)
+#if !defined(CONFIG_SPL_BUILD) && (defined(CONFIG_CMD_HASH) || \
+ defined(CONFIG_CMD_SHA1SUM) || defined(CONFIG_CMD_CRC32))
/**
* store_result: Store the resulting sum to an address or variable
*
diff --git a/common/image-board.c b/common/image-board.c
new file mode 100644
index 0000000..e766035
--- /dev/null
+++ b/common/image-board.c
@@ -0,0 +1,956 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Image code used by boards (and not host tools)
+ *
+ * (C) Copyright 2008 Semihalf
+ *
+ * (C) Copyright 2000-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <bootstage.h>
+#include <cpu_func.h>
+#include <env.h>
+#include <fpga.h>
+#include <image.h>
+#include <mapmem.h>
+#include <rtc.h>
+#include <watchdog.h>
+#include <asm/cache.h>
+#include <asm/global_data.h>
+
+#ifndef CONFIG_SYS_BARGSIZE
+#define CONFIG_SYS_BARGSIZE 512
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * image_get_ramdisk - get and verify ramdisk image
+ * @rd_addr: ramdisk image start address
+ * @arch: expected ramdisk architecture
+ * @verify: checksum verification flag
+ *
+ * image_get_ramdisk() returns a pointer to the verified ramdisk image
+ * header. Routine receives image start address and expected architecture
+ * flag. Verification done covers data and header integrity and os/type/arch
+ * fields checking.
+ *
+ * returns:
+ * pointer to a ramdisk image header, if image was found and valid
+ * otherwise, return NULL
+ */
+static const image_header_t *image_get_ramdisk(ulong rd_addr, u8 arch,
+ int verify)
+{
+ const image_header_t *rd_hdr = (const image_header_t *)rd_addr;
+
+ if (!image_check_magic(rd_hdr)) {
+ puts("Bad Magic Number\n");
+ bootstage_error(BOOTSTAGE_ID_RD_MAGIC);
+ return NULL;
+ }
+
+ if (!image_check_hcrc(rd_hdr)) {
+ puts("Bad Header Checksum\n");
+ bootstage_error(BOOTSTAGE_ID_RD_HDR_CHECKSUM);
+ return NULL;
+ }
+
+ bootstage_mark(BOOTSTAGE_ID_RD_MAGIC);
+ image_print_contents(rd_hdr);
+
+ if (verify) {
+ puts(" Verifying Checksum ... ");
+ if (!image_check_dcrc(rd_hdr)) {
+ puts("Bad Data CRC\n");
+ bootstage_error(BOOTSTAGE_ID_RD_CHECKSUM);
+ return NULL;
+ }
+ puts("OK\n");
+ }
+
+ bootstage_mark(BOOTSTAGE_ID_RD_HDR_CHECKSUM);
+
+ if (!image_check_os(rd_hdr, IH_OS_LINUX) ||
+ !image_check_arch(rd_hdr, arch) ||
+ !image_check_type(rd_hdr, IH_TYPE_RAMDISK)) {
+ printf("No Linux %s Ramdisk Image\n",
+ genimg_get_arch_name(arch));
+ bootstage_error(BOOTSTAGE_ID_RAMDISK);
+ return NULL;
+ }
+
+ return rd_hdr;
+}
+
+/*****************************************************************************/
+/* Shared dual-format routines */
+/*****************************************************************************/
+ulong image_load_addr = CONFIG_SYS_LOAD_ADDR; /* Default Load Address */
+ulong image_save_addr; /* Default Save Address */
+ulong image_save_size; /* Default Save Size (in bytes) */
+
+static int on_loadaddr(const char *name, const char *value, enum env_op op,
+ int flags)
+{
+ switch (op) {
+ case env_op_create:
+ case env_op_overwrite:
+ image_load_addr = hextoul(value, NULL);
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+U_BOOT_ENV_CALLBACK(loadaddr, on_loadaddr);
+
+ulong env_get_bootm_low(void)
+{
+ char *s = env_get("bootm_low");
+
+ if (s) {
+ ulong tmp = hextoul(s, NULL);
+ return tmp;
+ }
+
+#if defined(CONFIG_SYS_SDRAM_BASE)
+ return CONFIG_SYS_SDRAM_BASE;
+#elif defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE) || defined(CONFIG_RISCV)
+ return gd->bd->bi_dram[0].start;
+#else
+ return 0;
+#endif
+}
+
+phys_size_t env_get_bootm_size(void)
+{
+ phys_size_t tmp, size;
+ phys_addr_t start;
+ char *s = env_get("bootm_size");
+
+ if (s) {
+ tmp = (phys_size_t)simple_strtoull(s, NULL, 16);
+ return tmp;
+ }
+
+ start = gd->ram_base;
+ size = gd->ram_size;
+
+ if (start + size > gd->ram_top)
+ size = gd->ram_top - start;
+
+ s = env_get("bootm_low");
+ if (s)
+ tmp = (phys_size_t)simple_strtoull(s, NULL, 16);
+ else
+ tmp = start;
+
+ return size - (tmp - start);
+}
+
+phys_size_t env_get_bootm_mapsize(void)
+{
+ phys_size_t tmp;
+ char *s = env_get("bootm_mapsize");
+
+ if (s) {
+ tmp = (phys_size_t)simple_strtoull(s, NULL, 16);
+ return tmp;
+ }
+
+#if defined(CONFIG_SYS_BOOTMAPSZ)
+ return CONFIG_SYS_BOOTMAPSZ;
+#else
+ return env_get_bootm_size();
+#endif
+}
+
+void memmove_wd(void *to, void *from, size_t len, ulong chunksz)
+{
+ if (to == from)
+ return;
+
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+ if (to > from) {
+ from += len;
+ to += len;
+ }
+ while (len > 0) {
+ size_t tail = (len > chunksz) ? chunksz : len;
+
+ WATCHDOG_RESET();
+ if (to > from) {
+ to -= tail;
+ from -= tail;
+ }
+ memmove(to, from, tail);
+ if (to < from) {
+ to += tail;
+ from += tail;
+ }
+ len -= tail;
+ }
+#else /* !(CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG) */
+ memmove(to, from, len);
+#endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */
+}
+
+/**
+ * genimg_get_kernel_addr_fit - get the real kernel address and return 2
+ * FIT strings
+ * @img_addr: a string might contain real image address
+ * @fit_uname_config: double pointer to a char, will hold pointer to a
+ * configuration unit name
+ * @fit_uname_kernel: double pointer to a char, will hold pointer to a subimage
+ * name
+ *
+ * genimg_get_kernel_addr_fit get the real kernel start address from a string
+ * which is normally the first argv of bootm/bootz
+ *
+ * returns:
+ * kernel start address
+ */
+ulong genimg_get_kernel_addr_fit(char * const img_addr,
+ const char **fit_uname_config,
+ const char **fit_uname_kernel)
+{
+ ulong kernel_addr;
+
+ /* find out kernel image address */
+ if (!img_addr) {
+ kernel_addr = image_load_addr;
+ debug("* kernel: default image load address = 0x%08lx\n",
+ image_load_addr);
+ } else if (CONFIG_IS_ENABLED(FIT) &&
+ fit_parse_conf(img_addr, image_load_addr, &kernel_addr,
+ fit_uname_config)) {
+ debug("* kernel: config '%s' from image at 0x%08lx\n",
+ *fit_uname_config, kernel_addr);
+ } else if (CONFIG_IS_ENABLED(FIT) &&
+ fit_parse_subimage(img_addr, image_load_addr, &kernel_addr,
+ fit_uname_kernel)) {
+ debug("* kernel: subimage '%s' from image at 0x%08lx\n",
+ *fit_uname_kernel, kernel_addr);
+ } else {
+ kernel_addr = hextoul(img_addr, NULL);
+ debug("* kernel: cmdline image address = 0x%08lx\n",
+ kernel_addr);
+ }
+
+ return kernel_addr;
+}
+
+/**
+ * genimg_get_kernel_addr() is the simple version of
+ * genimg_get_kernel_addr_fit(). It ignores those return FIT strings
+ */
+ulong genimg_get_kernel_addr(char * const img_addr)
+{
+ const char *fit_uname_config = NULL;
+ const char *fit_uname_kernel = NULL;
+
+ return genimg_get_kernel_addr_fit(img_addr, &fit_uname_config,
+ &fit_uname_kernel);
+}
+
+/**
+ * genimg_get_format - get image format type
+ * @img_addr: image start address
+ *
+ * genimg_get_format() checks whether provided address points to a valid
+ * legacy or FIT image.
+ *
+ * New uImage format and FDT blob are based on a libfdt. FDT blob
+ * may be passed directly or embedded in a FIT image. In both situations
+ * genimg_get_format() must be able to dectect libfdt header.
+ *
+ * returns:
+ * image format type or IMAGE_FORMAT_INVALID if no image is present
+ */
+int genimg_get_format(const void *img_addr)
+{
+ if (CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)) {
+ const image_header_t *hdr;
+
+ hdr = (const image_header_t *)img_addr;
+ if (image_check_magic(hdr))
+ return IMAGE_FORMAT_LEGACY;
+ }
+ if (CONFIG_IS_ENABLED(FIT) || CONFIG_IS_ENABLED(OF_LIBFDT)) {
+ if (!fdt_check_header(img_addr))
+ return IMAGE_FORMAT_FIT;
+ }
+ if (IS_ENABLED(CONFIG_ANDROID_BOOT_IMAGE) &&
+ !android_image_check_header(img_addr))
+ return IMAGE_FORMAT_ANDROID;
+
+ return IMAGE_FORMAT_INVALID;
+}
+
+/**
+ * fit_has_config - check if there is a valid FIT configuration
+ * @images: pointer to the bootm command headers structure
+ *
+ * fit_has_config() checks if there is a FIT configuration in use
+ * (if FTI support is present).
+ *
+ * returns:
+ * 0, no FIT support or no configuration found
+ * 1, configuration found
+ */
+int genimg_has_config(bootm_headers_t *images)
+{
+ if (CONFIG_IS_ENABLED(FIT) && images->fit_uname_cfg)
+ return 1;
+
+ return 0;
+}
+
+/**
+ * select_ramdisk() - Select and locate the ramdisk to use
+ *
+ * @images: pointer to the bootm images structure
+ * @select: name of ramdisk to select, or NULL for any
+ * @arch: expected ramdisk architecture
+ * @rd_datap: pointer to a ulong variable, will hold ramdisk pointer
+ * @rd_lenp: pointer to a ulong variable, will hold ramdisk length
+ * @return 0 if OK, -ENOPKG if no ramdisk (but an error should not be reported),
+ * other -ve value on other error
+ */
+static int select_ramdisk(bootm_headers_t *images, const char *select, u8 arch,
+ ulong *rd_datap, ulong *rd_lenp)
+{
+ ulong rd_addr = 0;
+ char *buf;
+ const char *fit_uname_config = images->fit_uname_cfg;
+ const char *fit_uname_ramdisk = NULL;
+ bool processed;
+ int rd_noffset;
+
+ if (select) {
+ ulong default_addr;
+ bool done = true;
+
+ if (CONFIG_IS_ENABLED(FIT)) {
+ /*
+ * If the init ramdisk comes from the FIT image and
+ * the FIT image address is omitted in the command
+ * line argument, try to use os FIT image address or
+ * default load address.
+ */
+ if (images->fit_uname_os)
+ default_addr = (ulong)images->fit_hdr_os;
+ else
+ default_addr = image_load_addr;
+
+ if (fit_parse_conf(select, default_addr, &rd_addr,
+ &fit_uname_config)) {
+ debug("* ramdisk: config '%s' from image at 0x%08lx\n",
+ fit_uname_config, rd_addr);
+ } else if (fit_parse_subimage(select, default_addr,
+ &rd_addr,
+ &fit_uname_ramdisk)) {
+ debug("* ramdisk: subimage '%s' from image at 0x%08lx\n",
+ fit_uname_ramdisk, rd_addr);
+ } else {
+ done = false;
+ }
+ }
+ if (!done) {
+ rd_addr = hextoul(select, NULL);
+ debug("* ramdisk: cmdline image address = 0x%08lx\n",
+ rd_addr);
+ }
+ } else if (CONFIG_IS_ENABLED(FIT)) {
+ /* use FIT configuration provided in first bootm
+ * command argument. If the property is not defined,
+ * quit silently (with -ENOPKG )
+ */
+ rd_addr = map_to_sysmem(images->fit_hdr_os);
+ rd_noffset = fit_get_node_from_config(images, FIT_RAMDISK_PROP,
+ rd_addr);
+ if (rd_noffset == -ENOENT)
+ return -ENOPKG;
+ else if (rd_noffset < 0)
+ return rd_noffset;
+ }
+
+ /*
+ * Check if there is an initrd image at the
+ * address provided in the second bootm argument
+ * check image type, for FIT images get FIT node.
+ */
+ buf = map_sysmem(rd_addr, 0);
+ processed = false;
+ switch (genimg_get_format(buf)) {
+ case IMAGE_FORMAT_LEGACY:
+ if (CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)) {
+ const image_header_t *rd_hdr;
+
+ printf("## Loading init Ramdisk from Legacy Image at %08lx ...\n",
+ rd_addr);
+
+ bootstage_mark(BOOTSTAGE_ID_CHECK_RAMDISK);
+ rd_hdr = image_get_ramdisk(rd_addr, arch, images->verify);
+ if (!rd_hdr)
+ return -ENOENT;
+
+ *rd_datap = image_get_data(rd_hdr);
+ *rd_lenp = image_get_data_size(rd_hdr);
+ processed = true;
+ }
+ break;
+ case IMAGE_FORMAT_FIT:
+ if (CONFIG_IS_ENABLED(FIT)) {
+ rd_noffset = fit_image_load(images, rd_addr,
+ &fit_uname_ramdisk,
+ &fit_uname_config, arch,
+ IH_TYPE_RAMDISK,
+ BOOTSTAGE_ID_FIT_RD_START,
+ FIT_LOAD_OPTIONAL_NON_ZERO,
+ rd_datap, rd_lenp);
+ if (rd_noffset < 0)
+ return rd_noffset;
+
+ images->fit_hdr_rd = map_sysmem(rd_addr, 0);
+ images->fit_uname_rd = fit_uname_ramdisk;
+ images->fit_noffset_rd = rd_noffset;
+ processed = true;
+ }
+ break;
+ case IMAGE_FORMAT_ANDROID:
+ if (IS_ENABLED(CONFIG_ANDROID_BOOT_IMAGE)) {
+ android_image_get_ramdisk((void *)images->os.start,
+ rd_datap, rd_lenp);
+ processed = true;
+ }
+ break;
+ }
+
+ if (!processed) {
+ if (IS_ENABLED(CONFIG_SUPPORT_RAW_INITRD)) {
+ char *end = NULL;
+
+ if (select)
+ end = strchr(select, ':');
+ if (end) {
+ *rd_lenp = hextoul(++end, NULL);
+ *rd_datap = rd_addr;
+ processed = true;
+ }
+ }
+
+ if (!processed) {
+ puts("Wrong Ramdisk Image Format\n");
+ return -EINVAL;
+ }
+ }
+
+ return 0;
+}
+
+/**
+ * boot_get_ramdisk - main ramdisk handling routine
+ * @argc: command argument count
+ * @argv: command argument list
+ * @images: pointer to the bootm images structure
+ * @arch: expected ramdisk architecture
+ * @rd_start: pointer to a ulong variable, will hold ramdisk start address
+ * @rd_end: pointer to a ulong variable, will hold ramdisk end
+ *
+ * boot_get_ramdisk() is responsible for finding a valid ramdisk image.
+ * Currently supported are the following ramdisk sources:
+ * - multicomponent kernel/ramdisk image,
+ * - commandline provided address of decicated ramdisk image.
+ *
+ * returns:
+ * 0, if ramdisk image was found and valid, or skiped
+ * rd_start and rd_end are set to ramdisk start/end addresses if
+ * ramdisk image is found and valid
+ *
+ * 1, if ramdisk image is found but corrupted, or invalid
+ * rd_start and rd_end are set to 0 if no ramdisk exists
+ */
+int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images,
+ u8 arch, ulong *rd_start, ulong *rd_end)
+{
+ ulong rd_data, rd_len;
+ const char *select = NULL;
+
+ *rd_start = 0;
+ *rd_end = 0;
+
+ if (IS_ENABLED(CONFIG_ANDROID_BOOT_IMAGE)) {
+ char *buf;
+
+ /* Look for an Android boot image */
+ buf = map_sysmem(images->os.start, 0);
+ if (buf && genimg_get_format(buf) == IMAGE_FORMAT_ANDROID)
+ select = (argc == 0) ? env_get("loadaddr") : argv[0];
+ }
+
+ if (argc >= 2)
+ select = argv[1];
+
+ /*
+ * Look for a '-' which indicates to ignore the
+ * ramdisk argument
+ */
+ if (select && strcmp(select, "-") == 0) {
+ debug("## Skipping init Ramdisk\n");
+ rd_len = 0;
+ rd_data = 0;
+ } else if (select || genimg_has_config(images)) {
+ int ret;
+
+ ret = select_ramdisk(images, select, arch, &rd_data, &rd_len);
+ if (ret == -ENOPKG)
+ return 0;
+ else if (ret)
+ return ret;
+ } else if (images->legacy_hdr_valid &&
+ image_check_type(&images->legacy_hdr_os_copy,
+ IH_TYPE_MULTI)) {
+ /*
+ * Now check if we have a legacy mult-component image,
+ * get second entry data start address and len.
+ */
+ bootstage_mark(BOOTSTAGE_ID_RAMDISK);
+ printf("## Loading init Ramdisk from multi component Legacy Image at %08lx ...\n",
+ (ulong)images->legacy_hdr_os);
+
+ image_multi_getimg(images->legacy_hdr_os, 1, &rd_data, &rd_len);
+ } else {
+ /*
+ * no initrd image
+ */
+ bootstage_mark(BOOTSTAGE_ID_NO_RAMDISK);
+ rd_len = 0;
+ rd_data = 0;
+ }
+
+ if (!rd_data) {
+ debug("## No init Ramdisk\n");
+ } else {
+ *rd_start = rd_data;
+ *rd_end = rd_data + rd_len;
+ }
+ debug(" ramdisk start = 0x%08lx, ramdisk end = 0x%08lx\n",
+ *rd_start, *rd_end);
+
+ return 0;
+}
+
+/**
+ * boot_ramdisk_high - relocate init ramdisk
+ * @lmb: pointer to lmb handle, will be used for memory mgmt
+ * @rd_data: ramdisk data start address
+ * @rd_len: ramdisk data length
+ * @initrd_start: pointer to a ulong variable, will hold final init ramdisk
+ * start address (after possible relocation)
+ * @initrd_end: pointer to a ulong variable, will hold final init ramdisk
+ * end address (after possible relocation)
+ *
+ * boot_ramdisk_high() takes a relocation hint from "initrd_high" environment
+ * variable and if requested ramdisk data is moved to a specified location.
+ *
+ * Initrd_start and initrd_end are set to final (after relocation) ramdisk
+ * start/end addresses if ramdisk image start and len were provided,
+ * otherwise set initrd_start and initrd_end set to zeros.
+ *
+ * returns:
+ * 0 - success
+ * -1 - failure
+ */
+int boot_ramdisk_high(struct lmb *lmb, ulong rd_data, ulong rd_len,
+ ulong *initrd_start, ulong *initrd_end)
+{
+ char *s;
+ ulong initrd_high;
+ int initrd_copy_to_ram = 1;
+
+ s = env_get("initrd_high");
+ if (s) {
+ /* a value of "no" or a similar string will act like 0,
+ * turning the "load high" feature off. This is intentional.
+ */
+ initrd_high = hextoul(s, NULL);
+ if (initrd_high == ~0)
+ initrd_copy_to_ram = 0;
+ } else {
+ initrd_high = env_get_bootm_mapsize() + env_get_bootm_low();
+ }
+
+ debug("## initrd_high = 0x%08lx, copy_to_ram = %d\n",
+ initrd_high, initrd_copy_to_ram);
+
+ if (rd_data) {
+ if (!initrd_copy_to_ram) { /* zero-copy ramdisk support */
+ debug(" in-place initrd\n");
+ *initrd_start = rd_data;
+ *initrd_end = rd_data + rd_len;
+ lmb_reserve(lmb, rd_data, rd_len);
+ } else {
+ if (initrd_high)
+ *initrd_start = (ulong)lmb_alloc_base(lmb,
+ rd_len, 0x1000, initrd_high);
+ else
+ *initrd_start = (ulong)lmb_alloc(lmb, rd_len,
+ 0x1000);
+
+ if (*initrd_start == 0) {
+ puts("ramdisk - allocation error\n");
+ goto error;
+ }
+ bootstage_mark(BOOTSTAGE_ID_COPY_RAMDISK);
+
+ *initrd_end = *initrd_start + rd_len;
+ printf(" Loading Ramdisk to %08lx, end %08lx ... ",
+ *initrd_start, *initrd_end);
+
+ memmove_wd((void *)*initrd_start,
+ (void *)rd_data, rd_len, CHUNKSZ);
+
+ /*
+ * Ensure the image is flushed to memory to handle
+ * AMP boot scenarios in which we might not be
+ * HW cache coherent
+ */
+ if (IS_ENABLED(CONFIG_MP)) {
+ flush_cache((unsigned long)*initrd_start,
+ ALIGN(rd_len, ARCH_DMA_MINALIGN));
+ }
+ puts("OK\n");
+ }
+ } else {
+ *initrd_start = 0;
+ *initrd_end = 0;
+ }
+ debug(" ramdisk load start = 0x%08lx, ramdisk load end = 0x%08lx\n",
+ *initrd_start, *initrd_end);
+
+ return 0;
+
+error:
+ return -1;
+}
+
+int boot_get_setup(bootm_headers_t *images, u8 arch,
+ ulong *setup_start, ulong *setup_len)
+{
+ if (!CONFIG_IS_ENABLED(FIT))
+ return -ENOENT;
+
+ return boot_get_setup_fit(images, arch, setup_start, setup_len);
+}
+
+int boot_get_fpga(int argc, char *const argv[], bootm_headers_t *images,
+ u8 arch, const ulong *ld_start, ulong * const ld_len)
+{
+ ulong tmp_img_addr, img_data, img_len;
+ void *buf;
+ int conf_noffset;
+ int fit_img_result;
+ const char *uname, *name;
+ int err;
+ int devnum = 0; /* TODO support multi fpga platforms */
+
+ if (!IS_ENABLED(CONFIG_FPGA))
+ return -ENOSYS;
+
+ /* Check to see if the images struct has a FIT configuration */
+ if (!genimg_has_config(images)) {
+ debug("## FIT configuration was not specified\n");
+ return 0;
+ }
+
+ /*
+ * Obtain the os FIT header from the images struct
+ */
+ tmp_img_addr = map_to_sysmem(images->fit_hdr_os);
+ buf = map_sysmem(tmp_img_addr, 0);
+ /*
+ * Check image type. For FIT images get FIT node
+ * and attempt to locate a generic binary.
+ */
+ switch (genimg_get_format(buf)) {
+ case IMAGE_FORMAT_FIT:
+ conf_noffset = fit_conf_get_node(buf, images->fit_uname_cfg);
+
+ uname = fdt_stringlist_get(buf, conf_noffset, FIT_FPGA_PROP, 0,
+ NULL);
+ if (!uname) {
+ debug("## FPGA image is not specified\n");
+ return 0;
+ }
+ fit_img_result = fit_image_load(images,
+ tmp_img_addr,
+ (const char **)&uname,
+ &images->fit_uname_cfg,
+ arch,
+ IH_TYPE_FPGA,
+ BOOTSTAGE_ID_FPGA_INIT,
+ FIT_LOAD_OPTIONAL_NON_ZERO,
+ &img_data, &img_len);
+
+ debug("FPGA image (%s) loaded to 0x%lx/size 0x%lx\n",
+ uname, img_data, img_len);
+
+ if (fit_img_result < 0) {
+ /* Something went wrong! */
+ return fit_img_result;
+ }
+
+ if (!fpga_is_partial_data(devnum, img_len)) {
+ name = "full";
+ err = fpga_loadbitstream(devnum, (char *)img_data,
+ img_len, BIT_FULL);
+ if (err)
+ err = fpga_load(devnum, (const void *)img_data,
+ img_len, BIT_FULL);
+ } else {
+ name = "partial";
+ err = fpga_loadbitstream(devnum, (char *)img_data,
+ img_len, BIT_PARTIAL);
+ if (err)
+ err = fpga_load(devnum, (const void *)img_data,
+ img_len, BIT_PARTIAL);
+ }
+
+ if (err)
+ return err;
+
+ printf(" Programming %s bitstream... OK\n", name);
+ break;
+ default:
+ printf("The given image format is not supported (corrupt?)\n");
+ return 1;
+ }
+
+ return 0;
+}
+
+static void fit_loadable_process(u8 img_type,
+ ulong img_data,
+ ulong img_len)
+{
+ int i;
+ const unsigned int count =
+ ll_entry_count(struct fit_loadable_tbl, fit_loadable);
+ struct fit_loadable_tbl *fit_loadable_handler =
+ ll_entry_start(struct fit_loadable_tbl, fit_loadable);
+ /* For each loadable handler */
+ for (i = 0; i < count; i++, fit_loadable_handler++)
+ /* matching this type */
+ if (fit_loadable_handler->type == img_type)
+ /* call that handler with this image data */
+ fit_loadable_handler->handler(img_data, img_len);
+}
+
+int boot_get_loadable(int argc, char *const argv[], bootm_headers_t *images,
+ u8 arch, const ulong *ld_start, ulong * const ld_len)
+{
+ /*
+ * These variables are used to hold the current image location
+ * in system memory.
+ */
+ ulong tmp_img_addr;
+ /*
+ * These two variables are requirements for fit_image_load, but
+ * their values are not used
+ */
+ ulong img_data, img_len;
+ void *buf;
+ int loadables_index;
+ int conf_noffset;
+ int fit_img_result;
+ const char *uname;
+ u8 img_type;
+
+ /* Check to see if the images struct has a FIT configuration */
+ if (!genimg_has_config(images)) {
+ debug("## FIT configuration was not specified\n");
+ return 0;
+ }
+
+ /*
+ * Obtain the os FIT header from the images struct
+ */
+ tmp_img_addr = map_to_sysmem(images->fit_hdr_os);
+ buf = map_sysmem(tmp_img_addr, 0);
+ /*
+ * Check image type. For FIT images get FIT node
+ * and attempt to locate a generic binary.
+ */
+ switch (genimg_get_format(buf)) {
+ case IMAGE_FORMAT_FIT:
+ conf_noffset = fit_conf_get_node(buf, images->fit_uname_cfg);
+
+ for (loadables_index = 0;
+ uname = fdt_stringlist_get(buf, conf_noffset,
+ FIT_LOADABLE_PROP,
+ loadables_index, NULL), uname;
+ loadables_index++) {
+ fit_img_result = fit_image_load(images, tmp_img_addr,
+ &uname,
+ &images->fit_uname_cfg,
+ arch, IH_TYPE_LOADABLE,
+ BOOTSTAGE_ID_FIT_LOADABLE_START,
+ FIT_LOAD_OPTIONAL_NON_ZERO,
+ &img_data, &img_len);
+ if (fit_img_result < 0) {
+ /* Something went wrong! */
+ return fit_img_result;
+ }
+
+ fit_img_result = fit_image_get_node(buf, uname);
+ if (fit_img_result < 0) {
+ /* Something went wrong! */
+ return fit_img_result;
+ }
+ fit_img_result = fit_image_get_type(buf,
+ fit_img_result,
+ &img_type);
+ if (fit_img_result < 0) {
+ /* Something went wrong! */
+ return fit_img_result;
+ }
+
+ fit_loadable_process(img_type, img_data, img_len);
+ }
+ break;
+ default:
+ printf("The given image format is not supported (corrupt?)\n");
+ return 1;
+ }
+
+ return 0;
+}
+
+/**
+ * boot_get_cmdline - allocate and initialize kernel cmdline
+ * @lmb: pointer to lmb handle, will be used for memory mgmt
+ * @cmd_start: pointer to a ulong variable, will hold cmdline start
+ * @cmd_end: pointer to a ulong variable, will hold cmdline end
+ *
+ * boot_get_cmdline() allocates space for kernel command line below
+ * BOOTMAPSZ + env_get_bootm_low() address. If "bootargs" U-Boot environment
+ * variable is present its contents is copied to allocated kernel
+ * command line.
+ *
+ * returns:
+ * 0 - success
+ * -1 - failure
+ */
+int boot_get_cmdline(struct lmb *lmb, ulong *cmd_start, ulong *cmd_end)
+{
+ char *cmdline;
+ char *s;
+
+ cmdline = (char *)(ulong)lmb_alloc_base(lmb, CONFIG_SYS_BARGSIZE, 0xf,
+ env_get_bootm_mapsize() + env_get_bootm_low());
+ if (!cmdline)
+ return -1;
+
+ s = env_get("bootargs");
+ if (!s)
+ s = "";
+
+ strcpy(cmdline, s);
+
+ *cmd_start = (ulong)cmdline;
+ *cmd_end = *cmd_start + strlen(cmdline);
+
+ debug("## cmdline at 0x%08lx ... 0x%08lx\n", *cmd_start, *cmd_end);
+
+ return 0;
+}
+
+/**
+ * boot_get_kbd - allocate and initialize kernel copy of board info
+ * @lmb: pointer to lmb handle, will be used for memory mgmt
+ * @kbd: double pointer to board info data
+ *
+ * boot_get_kbd() allocates space for kernel copy of board info data below
+ * BOOTMAPSZ + env_get_bootm_low() address and kernel board info is initialized
+ * with the current u-boot board info data.
+ *
+ * returns:
+ * 0 - success
+ * -1 - failure
+ */
+int boot_get_kbd(struct lmb *lmb, struct bd_info **kbd)
+{
+ *kbd = (struct bd_info *)(ulong)lmb_alloc_base(lmb,
+ sizeof(struct bd_info),
+ 0xf,
+ env_get_bootm_mapsize() +
+ env_get_bootm_low());
+ if (!*kbd)
+ return -1;
+
+ **kbd = *gd->bd;
+
+ debug("## kernel board info at 0x%08lx\n", (ulong)*kbd);
+
+#if defined(DEBUG)
+ if (IS_ENABLED(CONFIG_CMD_BDI)
+ do_bdinfo(NULL, 0, 0, NULL);
+#endif
+
+ return 0;
+}
+
+int image_setup_linux(bootm_headers_t *images)
+{
+ ulong of_size = images->ft_len;
+ char **of_flat_tree = &images->ft_addr;
+ struct lmb *lmb = &images->lmb;
+ int ret;
+
+ if (CONFIG_IS_ENABLED(OF_LIBFDT))
+ boot_fdt_add_mem_rsv_regions(lmb, *of_flat_tree);
+
+ if (IS_ENABLED(CONFIG_SYS_BOOT_GET_CMDLINE)) {
+ ret = boot_get_cmdline(lmb, &images->cmdline_start,
+ &images->cmdline_end);
+ if (ret) {
+ puts("ERROR with allocation of cmdline\n");
+ return ret;
+ }
+ }
+
+ if (CONFIG_IS_ENABLED(OF_LIBFDT)) {
+ ret = boot_relocate_fdt(lmb, of_flat_tree, &of_size);
+ if (ret)
+ return ret;
+ }
+
+ if (CONFIG_IS_ENABLED(OF_LIBFDT) && of_size) {
+ ret = image_setup_libfdt(images, *of_flat_tree, of_size, lmb);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+void genimg_print_size(uint32_t size)
+{
+ printf("%d Bytes = ", size);
+ print_size(size, "\n");
+}
+
+void genimg_print_time(time_t timestamp)
+{
+ struct rtc_time tm;
+
+ rtc_to_tm(timestamp, &tm);
+ printf("%4d-%02d-%02d %2d:%02d:%02d UTC\n",
+ tm.tm_year, tm.tm_mon, tm.tm_mday,
+ tm.tm_hour, tm.tm_min, tm.tm_sec);
+}
diff --git a/common/image-fdt.c b/common/image-fdt.c
index b698e96..7aad6d5 100644
--- a/common/image-fdt.c
+++ b/common/image-fdt.c
@@ -252,59 +252,29 @@
}
/**
- * boot_get_fdt - main fdt handling routine
- * @argc: command argument count
- * @argv: command argument list
- * @arch: architecture (IH_ARCH_...)
- * @images: pointer to the bootm images structure
- * @of_flat_tree: pointer to a char* variable, will hold fdt start address
- * @of_size: pointer to a ulong variable, will hold fdt length
+ * select_fdt() - Select and locate the FDT to use
*
- * boot_get_fdt() is responsible for finding a valid flat device tree image.
- * Curently supported are the following ramdisk sources:
- * - multicomponent kernel/ramdisk image,
- * - commandline provided address of decicated ramdisk image.
- *
- * returns:
- * 0, if fdt image was found and valid, or skipped
- * of_flat_tree and of_size are set to fdt start address and length if
- * fdt image is found and valid
- *
- * 1, if fdt image is found but corrupted
- * of_flat_tree and of_size are set to 0 if no fdt exists
+ * @images: pointer to the bootm images structure
+ * @select: name of FDT to select, or NULL for any
+ * @arch: expected FDT architecture
+ * @fdt_addrp: pointer to a ulong variable, will hold FDT pointer
+ * @return 0 if OK, -ENOPKG if no FDT (but an error should not be reported),
+ * other -ve value on other error
*/
-int boot_get_fdt(int flag, int argc, char *const argv[], uint8_t arch,
- bootm_headers_t *images, char **of_flat_tree, ulong *of_size)
-{
-#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
- const image_header_t *fdt_hdr;
- ulong load, load_end;
- ulong image_start, image_data, image_end;
-#endif
- ulong img_addr;
- ulong fdt_addr;
- char *fdt_blob = NULL;
- void *buf;
-#if CONFIG_IS_ENABLED(FIT)
- const char *fit_uname_config = images->fit_uname_cfg;
- const char *fit_uname_fdt = NULL;
- ulong default_addr;
- int fdt_noffset;
-#endif
- const char *select = NULL;
-
- *of_flat_tree = NULL;
- *of_size = 0;
- img_addr = (argc == 0) ? image_load_addr :
- hextoul(argv[0], NULL);
- buf = map_sysmem(img_addr, 0);
+static int select_fdt(bootm_headers_t *images, const char *select, u8 arch,
+ ulong *fdt_addrp)
+{
+ const char *buf;
+ ulong fdt_addr;
- if (argc > 2)
- select = argv[2];
- if (select || genimg_has_config(images)) {
#if CONFIG_IS_ENABLED(FIT)
- if (select) {
+ const char *fit_uname_config = images->fit_uname_cfg;
+ const char *fit_uname_fdt = NULL;
+ ulong default_addr;
+ int fdt_noffset;
+
+ if (select) {
/*
* If the FDT blob comes from the FIT image and the
* FIT image address is omitted in the command line
@@ -318,54 +288,57 @@
else
default_addr = image_load_addr;
- if (fit_parse_conf(select, default_addr,
- &fdt_addr, &fit_uname_config)) {
+ if (fit_parse_conf(select, default_addr, &fdt_addr,
+ &fit_uname_config)) {
debug("* fdt: config '%s' from image at 0x%08lx\n",
fit_uname_config, fdt_addr);
- } else if (fit_parse_subimage(select, default_addr,
- &fdt_addr, &fit_uname_fdt)) {
+ } else if (fit_parse_subimage(select, default_addr, &fdt_addr,
+ &fit_uname_fdt)) {
debug("* fdt: subimage '%s' from image at 0x%08lx\n",
fit_uname_fdt, fdt_addr);
} else
#endif
- {
- fdt_addr = hextoul(select, NULL);
- debug("* fdt: cmdline image address = 0x%08lx\n",
- fdt_addr);
- }
-#if CONFIG_IS_ENABLED(FIT)
- } else {
- /* use FIT configuration provided in first bootm
- * command argument
- */
- fdt_addr = map_to_sysmem(images->fit_hdr_os);
- fdt_noffset = fit_get_node_from_config(images,
- FIT_FDT_PROP,
- fdt_addr);
- if (fdt_noffset == -ENOENT)
- return 0;
- else if (fdt_noffset < 0)
- return 1;
+ {
+ fdt_addr = hextoul(select, NULL);
+ debug("* fdt: cmdline image address = 0x%08lx\n",
+ fdt_addr);
}
+#if CONFIG_IS_ENABLED(FIT)
+ } else {
+ /* use FIT configuration provided in first bootm
+ * command argument
+ */
+ fdt_addr = map_to_sysmem(images->fit_hdr_os);
+ fdt_noffset = fit_get_node_from_config(images, FIT_FDT_PROP,
+ fdt_addr);
+ if (fdt_noffset == -ENOENT)
+ return -ENOPKG;
+ else if (fdt_noffset < 0)
+ return fdt_noffset;
+ }
#endif
- debug("## Checking for 'FDT'/'FDT Image' at %08lx\n",
- fdt_addr);
+ debug("## Checking for 'FDT'/'FDT Image' at %08lx\n",
+ fdt_addr);
- /*
- * Check if there is an FDT image at the
- * address provided in the second bootm argument
- * check image type, for FIT images get a FIT node.
- */
- buf = map_sysmem(fdt_addr, 0);
- switch (genimg_get_format(buf)) {
+ /*
+ * Check if there is an FDT image at the
+ * address provided in the second bootm argument
+ * check image type, for FIT images get a FIT node.
+ */
+ buf = map_sysmem(fdt_addr, 0);
+ switch (genimg_get_format(buf)) {
#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
- case IMAGE_FORMAT_LEGACY:
+ case IMAGE_FORMAT_LEGACY: {
+ const image_header_t *fdt_hdr;
+ ulong load, load_end;
+ ulong image_start, image_data, image_end;
+
/* verify fdt_addr points to a valid image header */
printf("## Flattened Device Tree from Legacy Image at %08lx\n",
fdt_addr);
fdt_hdr = image_get_fdt(fdt_addr);
if (!fdt_hdr)
- goto no_fdt;
+ return -ENOPKG;
/*
* move image data to the load address,
@@ -386,7 +359,7 @@
if ((load < image_end) && (load_end > image_start)) {
fdt_error("fdt overwritten");
- goto error;
+ return -EFAULT;
}
debug(" Loading FDT from 0x%08lx to 0x%08lx\n",
@@ -398,25 +371,26 @@
fdt_addr = load;
break;
+ }
#endif
- case IMAGE_FORMAT_FIT:
- /*
- * This case will catch both: new uImage format
- * (libfdt based) and raw FDT blob (also libfdt
- * based).
- */
+ case IMAGE_FORMAT_FIT:
+ /*
+ * This case will catch both: new uImage format
+ * (libfdt based) and raw FDT blob (also libfdt
+ * based).
+ */
#if CONFIG_IS_ENABLED(FIT)
/* check FDT blob vs FIT blob */
if (!fit_check_format(buf, IMAGE_SIZE_INVAL)) {
ulong load, len;
- fdt_noffset = boot_get_fdt_fit(images,
- fdt_addr, &fit_uname_fdt,
- &fit_uname_config,
- arch, &load, &len);
+ fdt_noffset = boot_get_fdt_fit(images, fdt_addr,
+ &fit_uname_fdt,
+ &fit_uname_config,
+ arch, &load, &len);
if (fdt_noffset < 0)
- goto error;
+ return -ENOENT;
images->fit_hdr_fdt = map_sysmem(fdt_addr, 0);
images->fit_uname_fdt = fit_uname_fdt;
@@ -424,22 +398,73 @@
fdt_addr = load;
break;
- } else
+ } else
#endif
- {
- /*
- * FDT blob
- */
- debug("* fdt: raw FDT blob\n");
- printf("## Flattened Device Tree blob at %08lx\n",
- (long)fdt_addr);
- }
- break;
- default:
- puts("ERROR: Did not find a cmdline Flattened Device Tree\n");
- goto error;
+ {
+ /*
+ * FDT blob
+ */
+ debug("* fdt: raw FDT blob\n");
+ printf("## Flattened Device Tree blob at %08lx\n",
+ (long)fdt_addr);
}
+ break;
+ default:
+ puts("ERROR: Did not find a cmdline Flattened Device Tree\n");
+ return -ENOENT;
+ }
+ *fdt_addrp = fdt_addr;
+ return 0;
+}
+
+/**
+ * boot_get_fdt - main fdt handling routine
+ * @argc: command argument count
+ * @argv: command argument list
+ * @arch: architecture (IH_ARCH_...)
+ * @images: pointer to the bootm images structure
+ * @of_flat_tree: pointer to a char* variable, will hold fdt start address
+ * @of_size: pointer to a ulong variable, will hold fdt length
+ *
+ * boot_get_fdt() is responsible for finding a valid flat device tree image.
+ * Currently supported are the following ramdisk sources:
+ * - multicomponent kernel/ramdisk image,
+ * - commandline provided address of decicated ramdisk image.
+ *
+ * returns:
+ * 0, if fdt image was found and valid, or skipped
+ * of_flat_tree and of_size are set to fdt start address and length if
+ * fdt image is found and valid
+ *
+ * 1, if fdt image is found but corrupted
+ * of_flat_tree and of_size are set to 0 if no fdt exists
+ */
+int boot_get_fdt(int flag, int argc, char *const argv[], uint8_t arch,
+ bootm_headers_t *images, char **of_flat_tree, ulong *of_size)
+{
+ ulong img_addr;
+ ulong fdt_addr;
+ char *fdt_blob = NULL;
+ void *buf;
+ const char *select = NULL;
+
+ *of_flat_tree = NULL;
+ *of_size = 0;
+
+ img_addr = (argc == 0) ? image_load_addr : hextoul(argv[0], NULL);
+ buf = map_sysmem(img_addr, 0);
+
+ if (argc > 2)
+ select = argv[2];
+ if (select || genimg_has_config(images)) {
+ int ret;
+
+ ret = select_fdt(images, select, arch, &fdt_addr);
+ if (ret == -ENOPKG)
+ goto no_fdt;
+ else if (ret)
+ return 1;
printf(" Booting using the fdt blob at %#08lx\n", fdt_addr);
fdt_blob = map_sysmem(fdt_addr, 0);
} else if (images->legacy_hdr_valid &&
@@ -582,7 +607,7 @@
/* Append PStore configuration */
fdt_fixup_pstore(blob);
#endif
- if (IMAGE_OF_BOARD_SETUP) {
+ if (IS_ENABLED(CONFIG_OF_BOARD_SETUP)) {
const char *skip_board_fixup;
skip_board_fixup = env_get("skip_board_fixup");
@@ -597,7 +622,7 @@
}
}
}
- if (IMAGE_OF_SYSTEM_SETUP) {
+ if (IS_ENABLED(CONFIG_OF_SYSTEM_SETUP)) {
fdt_ret = ft_system_setup(blob, gd->bd);
if (fdt_ret) {
printf("ERROR: system-specific fdt fixup failed: %s\n",
@@ -629,7 +654,7 @@
goto err;
#if defined(CONFIG_ARCH_KEYSTONE)
- if (IMAGE_OF_BOARD_SETUP)
+ if (IS_ENABLED(CONFIG_OF_BOARD_SETUP))
ft_board_setup_ex(blob, gd->bd);
#endif
diff --git a/common/image-fit-sig.c b/common/image-fit-sig.c
index b979cd2..4edebbf 100644
--- a/common/image-fit-sig.c
+++ b/common/image-fit-sig.c
@@ -49,10 +49,8 @@
* Use malloc() except in SPL (to save code size). In SPL the caller
* must allocate the array.
*/
-#ifndef CONFIG_SPL_BUILD
- if (!region)
+ if (!IS_ENABLED(CONFIG_SPL_BUILD) && !region)
region = calloc(sizeof(*region), count);
-#endif
if (!region)
return NULL;
for (i = 0; i < count; i++) {
@@ -72,11 +70,10 @@
char *algo_name;
const char *padding_name;
- if (fdt_totalsize(fit) > CONFIG_FIT_SIGNATURE_MAX_SIZE) {
+ if (fdt_totalsize(fit) > CONFIG_VAL(FIT_SIGNATURE_MAX_SIZE)) {
*err_msgp = "Total size too large";
return 1;
}
-
if (fit_image_hash_get_algo(fit, noffset, &algo_name)) {
*err_msgp = "Can't get hash algo property";
return -1;
diff --git a/common/image-fit.c b/common/image-fit.c
index 5a0a0cc..33b4a46 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -170,7 +170,6 @@
return count;
}
-#if CONFIG_IS_ENABLED(FIT_PRINT) || CONFIG_IS_ENABLED(SPL_FIT_PRINT)
/**
* fit_image_print_data() - prints out the hash node details
* @fit: pointer to the FIT format image header
@@ -380,6 +379,9 @@
const char *p;
time_t timestamp;
+ if (!CONFIG_IS_ENABLED(FIT_PRINT))
+ return;
+
/* Indent string is defined in header image.h */
p = IMAGE_INDENT_STRING;
@@ -482,6 +484,9 @@
int ndepth;
int ret;
+ if (!CONFIG_IS_ENABLED(FIT_PRINT))
+ return;
+
/* Mandatory properties */
ret = fit_get_desc(fit, image_noffset, &desc);
printf("%s Description: ", p);
@@ -509,7 +514,7 @@
ret = fit_image_get_data_and_size(fit, image_noffset, &data, &size);
- if (!host_build()) {
+ if (!tools_build()) {
printf("%s Data Start: ", p);
if (ret) {
printf("unavailable\n");
@@ -575,10 +580,6 @@
}
}
}
-#else
-void fit_print_contents(const void *fit) { }
-void fit_image_print(const void *fit, int image_noffset, const char *p) { }
-#endif /* CONFIG_IS_ENABLED(FIR_PRINT) || CONFIG_IS_ENABLED(SPL_FIT_PRINT) */
/**
* fit_get_desc - get node description property
@@ -1277,7 +1278,7 @@
}
printf("%s", algo);
- if (IMAGE_ENABLE_IGNORE) {
+ if (!tools_build()) {
fit_image_hash_get_ignore(fit, noffset, &ignore);
if (ignore) {
printf("-skipped ");
@@ -1845,7 +1846,7 @@
if (conf_uname == NULL) {
/* get configuration unit name from the default property */
debug("No configuration specified, trying default...\n");
- if (!host_build() && IS_ENABLED(CONFIG_MULTI_DTB_FIT)) {
+ if (!tools_build() && IS_ENABLED(CONFIG_MULTI_DTB_FIT)) {
noffset = fit_find_config_node(fit);
if (noffset < 0)
return noffset;
@@ -2008,9 +2009,6 @@
int type_ok, os_ok;
ulong load, load_end, data, len;
uint8_t os, comp;
-#ifndef USE_HOSTCC
- uint8_t os_arch;
-#endif
const char *prop_name;
int ret;
@@ -2093,7 +2091,7 @@
}
bootstage_mark(bootstage_id + BOOTSTAGE_SUB_CHECK_ARCH);
- if (!host_build() && IS_ENABLED(CONFIG_SANDBOX)) {
+ if (!tools_build() && IS_ENABLED(CONFIG_SANDBOX)) {
if (!fit_image_check_target_arch(fit, noffset)) {
puts("Unsupported Architecture\n");
bootstage_error(bootstage_id + BOOTSTAGE_SUB_CHECK_ARCH);
@@ -2102,8 +2100,12 @@
}
#ifndef USE_HOSTCC
+ {
+ uint8_t os_arch;
+
fit_image_get_arch(fit, noffset, &os_arch);
images->os.arch = os_arch;
+ }
#endif
bootstage_mark(bootstage_id + BOOTSTAGE_SUB_CHECK_ALL);
@@ -2158,7 +2160,7 @@
}
/* perform any post-processing on the image data */
- if (!host_build() && IS_ENABLED(CONFIG_FIT_IMAGE_POST_PROCESS))
+ if (!tools_build() && IS_ENABLED(CONFIG_FIT_IMAGE_POST_PROCESS))
board_fit_image_post_process(fit, noffset, &buf, &size);
len = (ulong)size;
diff --git a/common/image-host.c b/common/image-host.c
new file mode 100644
index 0000000..20a9521
--- /dev/null
+++ b/common/image-host.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Image code used by host tools (and not boards)
+ *
+ * (C) Copyright 2008 Semihalf
+ *
+ * (C) Copyright 2000-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <time.h>
+
+void memmove_wd(void *to, void *from, size_t len, ulong chunksz)
+{
+ memmove(to, from, len);
+}
+
+void genimg_print_size(uint32_t size)
+{
+ printf("%d Bytes = %.2f KiB = %.2f MiB\n", size, (double)size / 1.024e3,
+ (double)size / 1.048576e6);
+}
+
+void genimg_print_time(time_t timestamp)
+{
+ printf("%s", ctime(×tamp));
+}
diff --git a/common/image-sig.c b/common/image-sig.c
index fa9407b..1aa0b58 100644
--- a/common/image-sig.c
+++ b/common/image-sig.c
@@ -9,6 +9,7 @@
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#include <image.h>
+#include <relocate.h>
#include <u-boot/ecdsa.h>
#include <u-boot/rsa.h>
#include <u-boot/hash-checksum.h>
@@ -56,17 +57,19 @@
int i;
const char *name;
-#if defined(CONFIG_NEEDS_MANUAL_RELOC)
- static bool done;
+ if (IS_ENABLED(CONFIG_NEEDS_MANUAL_RELOC)) {
+ static bool done;
- if (!done) {
- done = true;
- for (i = 0; i < ARRAY_SIZE(checksum_algos); i++) {
- checksum_algos[i].name += gd->reloc_off;
- checksum_algos[i].calculate += gd->reloc_off;
+ if (!done) {
+ done = true;
+ for (i = 0; i < ARRAY_SIZE(checksum_algos); i++) {
+ struct checksum_algo *algo = &checksum_algos[i];
+
+ MANUAL_RELOC(algo->name);
+ MANUAL_RELOC(algo->calculate);
+ }
}
}
-#endif
for (i = 0; i < ARRAY_SIZE(checksum_algos); i++) {
name = checksum_algos[i].name;
@@ -84,18 +87,19 @@
struct crypto_algo *crypto, *end;
const char *name;
-#if defined(CONFIG_NEEDS_MANUAL_RELOC)
- static bool done;
+ if (IS_ENABLED(CONFIG_NEEDS_MANUAL_RELOC)) {
+ static bool done;
- if (!done) {
- crypto = ll_entry_start(struct crypto_algo, cryptos);
- end = ll_entry_end(struct crypto_algo, cryptos);
- for (; crypto < end; crypto++) {
- crypto->name += gd->reloc_off;
- crypto->verify += gd->reloc_off;
+ if (!done) {
+ done = true;
+ crypto = ll_entry_start(struct crypto_algo, cryptos);
+ end = ll_entry_end(struct crypto_algo, cryptos);
+ for (; crypto < end; crypto++) {
+ MANUAL_RELOC(crypto->name);
+ MANUAL_RELOC(crypto->verify);
+ }
}
}
-#endif
/* Move name to after the comma */
name = strchr(full_name, ',');
diff --git a/common/image.c b/common/image.c
index 8ac5708..3fa60b5 100644
--- a/common/image.c
+++ b/common/image.c
@@ -8,32 +8,19 @@
#ifndef USE_HOSTCC
#include <common.h>
-#include <bootstage.h>
-#include <cpu_func.h>
#include <env.h>
#include <lmb.h>
#include <log.h>
#include <malloc.h>
-#include <asm/cache.h>
#include <u-boot/crc.h>
-#include <watchdog.h>
#ifdef CONFIG_SHOW_BOOT_PROGRESS
#include <status_led.h>
#endif
-#include <rtc.h>
-
-#include <gzip.h>
-#include <image.h>
-#include <lz4.h>
-#include <mapmem.h>
-
-#if IMAGE_ENABLE_FIT || IMAGE_ENABLE_OF_LIBFDT
+#if CONFIG_IS_ENABLED(FIT) || CONFIG_IS_ENABLED(OF_LIBFDT)
#include <linux/libfdt.h>
#include <fdt_support.h>
-#include <fpga.h>
-#include <xilinx.h>
#endif
#include <asm/global_data.h>
@@ -42,13 +29,6 @@
#include <linux/errno.h>
#include <asm/io.h>
-#include <bzlib.h>
-#include <linux/lzo.h>
-#include <lzma/LzmaTypes.h>
-#include <lzma/LzmaDec.h>
-#include <lzma/LzmaTools.h>
-#include <linux/zstd.h>
-
#ifdef CONFIG_CMD_BDI
extern int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[]);
@@ -56,27 +36,41 @@
DECLARE_GLOBAL_DATA_PTR;
-#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
-static const image_header_t *image_get_ramdisk(ulong rd_addr, uint8_t arch,
- int verify);
-#endif
+/* Set this if we have less than 4 MB of malloc() space */
+#if CONFIG_SYS_MALLOC_LEN < (4096 * 1024)
+#define CONSERVE_MEMORY true
#else
+#define CONSERVE_MEMORY false
+#endif
+
+#else /* USE_HOSTCC */
#include "mkimage.h"
#include <u-boot/md5.h>
#include <time.h>
-#include <image.h>
#ifndef __maybe_unused
# define __maybe_unused /* unimplemented */
#endif
+
+#define CONSERVE_MEMORY false
+
#endif /* !USE_HOSTCC*/
-#include <u-boot/crc.h>
+#include <abuf.h>
+#include <bzlib.h>
+#include <display_options.h>
+#include <gzip.h>
+#include <image.h>
#include <imximage.h>
-
-#ifndef CONFIG_SYS_BARGSIZE
-#define CONFIG_SYS_BARGSIZE 512
-#endif
+#include <relocate.h>
+#include <linux/lzo.h>
+#include <linux/zstd.h>
+#include <linux/kconfig.h>
+#include <lzma/LzmaTypes.h>
+#include <lzma/LzmaDec.h>
+#include <lzma/LzmaTools.h>
+#include <u-boot/crc.h>
+#include <u-boot/lz4.h>
static const table_entry_t uimage_arch[] = {
{ IH_ARCH_INVALID, "invalid", "Invalid ARCH", },
@@ -445,7 +439,7 @@
void *load_buf, void *image_buf, ulong image_len,
uint unc_len, ulong *load_end)
{
- int ret = 0;
+ int ret = -ENOSYS;
*load_end = load;
print_decomp_msg(comp, type, load == image_start);
@@ -457,6 +451,7 @@
*/
switch (comp) {
case IH_COMP_NONE:
+ ret = 0;
if (load == image_start)
break;
if (image_len <= unc_len)
@@ -464,337 +459,75 @@
else
ret = -ENOSPC;
break;
-#ifndef USE_HOSTCC
-#if CONFIG_IS_ENABLED(GZIP)
- case IH_COMP_GZIP: {
- ret = gunzip(load_buf, unc_len, image_buf, &image_len);
- break;
- }
-#endif /* CONFIG_GZIP */
-#endif
-#ifndef USE_HOSTCC
-#if CONFIG_IS_ENABLED(BZIP2)
- case IH_COMP_BZIP2: {
- uint size = unc_len;
-
- /*
- * If we've got less than 4 MB of malloc() space,
- * use slower decompression algorithm which requires
- * at most 2300 KB of memory.
- */
- ret = BZ2_bzBuffToBuffDecompress(load_buf, &size,
- image_buf, image_len,
- CONFIG_SYS_MALLOC_LEN < (4096 * 1024), 0);
- image_len = size;
+ case IH_COMP_GZIP:
+ if (!tools_build() && CONFIG_IS_ENABLED(GZIP))
+ ret = gunzip(load_buf, unc_len, image_buf, &image_len);
break;
- }
-#endif /* CONFIG_BZIP2 */
-#endif
-#ifndef USE_HOSTCC
-#if CONFIG_IS_ENABLED(LZMA)
- case IH_COMP_LZMA: {
- SizeT lzma_len = unc_len;
+ case IH_COMP_BZIP2:
+ if (!tools_build() && CONFIG_IS_ENABLED(BZIP2)) {
+ uint size = unc_len;
- ret = lzmaBuffToBuffDecompress(load_buf, &lzma_len,
- image_buf, image_len);
- image_len = lzma_len;
- break;
- }
-#endif /* CONFIG_LZMA */
-#endif
-#ifndef USE_HOSTCC
-#if CONFIG_IS_ENABLED(LZO)
- case IH_COMP_LZO: {
- size_t size = unc_len;
-
- ret = lzop_decompress(image_buf, image_len, load_buf, &size);
- image_len = size;
+ /*
+ * If we've got less than 4 MB of malloc() space,
+ * use slower decompression algorithm which requires
+ * at most 2300 KB of memory.
+ */
+ ret = BZ2_bzBuffToBuffDecompress(load_buf, &size,
+ image_buf, image_len, CONSERVE_MEMORY, 0);
+ image_len = size;
+ }
break;
- }
-#endif /* CONFIG_LZO */
-#endif
-#ifndef USE_HOSTCC
-#if CONFIG_IS_ENABLED(LZ4)
- case IH_COMP_LZ4: {
- size_t size = unc_len;
+ case IH_COMP_LZMA:
+ if (!tools_build() && CONFIG_IS_ENABLED(LZMA)) {
+ SizeT lzma_len = unc_len;
- ret = ulz4fn(image_buf, image_len, load_buf, &size);
- image_len = size;
+ ret = lzmaBuffToBuffDecompress(load_buf, &lzma_len,
+ image_buf, image_len);
+ image_len = lzma_len;
+ }
break;
- }
-#endif /* CONFIG_LZ4 */
-#endif
-#ifndef USE_HOSTCC
-#if CONFIG_IS_ENABLED(ZSTD)
- case IH_COMP_ZSTD: {
- size_t size = unc_len;
- ZSTD_DStream *dstream;
- ZSTD_inBuffer in_buf;
- ZSTD_outBuffer out_buf;
- void *workspace;
- size_t wsize;
+ case IH_COMP_LZO:
+ if (!tools_build() && CONFIG_IS_ENABLED(LZO)) {
+ size_t size = unc_len;
- wsize = ZSTD_DStreamWorkspaceBound(image_len);
- workspace = malloc(wsize);
- if (!workspace) {
- debug("%s: cannot allocate workspace of size %zu\n", __func__,
- wsize);
- return -1;
+ ret = lzop_decompress(image_buf, image_len, load_buf, &size);
+ image_len = size;
}
+ break;
+ case IH_COMP_LZ4:
+ if (!tools_build() && CONFIG_IS_ENABLED(LZ4)) {
+ size_t size = unc_len;
- dstream = ZSTD_initDStream(image_len, workspace, wsize);
- if (!dstream) {
- printf("%s: ZSTD_initDStream failed\n", __func__);
- return ZSTD_getErrorCode(ret);
+ ret = ulz4fn(image_buf, image_len, load_buf, &size);
+ image_len = size;
}
-
- in_buf.src = image_buf;
- in_buf.pos = 0;
- in_buf.size = image_len;
-
- out_buf.dst = load_buf;
- out_buf.pos = 0;
- out_buf.size = size;
-
- while (1) {
- size_t ret;
+ break;
+ case IH_COMP_ZSTD:
+ if (!tools_build() && CONFIG_IS_ENABLED(ZSTD)) {
+ struct abuf in, out;
- ret = ZSTD_decompressStream(dstream, &out_buf, &in_buf);
- if (ZSTD_isError(ret)) {
- printf("%s: ZSTD_decompressStream error %d\n", __func__,
- ZSTD_getErrorCode(ret));
- return ZSTD_getErrorCode(ret);
+ abuf_init_set(&in, image_buf, image_len);
+ abuf_init_set(&in, load_buf, unc_len);
+ ret = zstd_decompress(&in, &out);
+ if (ret >= 0) {
+ image_len = ret;
+ ret = 0;
}
-
- if (in_buf.pos >= image_len || !ret)
- break;
}
-
- image_len = out_buf.pos;
-
break;
}
-#endif /* CONFIG_ZSTD */
-#endif
- default:
+ if (ret == -ENOSYS) {
printf("Unimplemented compression type %d\n", comp);
- return -ENOSYS;
+ return ret;
}
+ if (ret)
+ return ret;
*load_end = load + image_len;
- return ret;
-}
-
-
-#ifndef USE_HOSTCC
-#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
-/**
- * image_get_ramdisk - get and verify ramdisk image
- * @rd_addr: ramdisk image start address
- * @arch: expected ramdisk architecture
- * @verify: checksum verification flag
- *
- * image_get_ramdisk() returns a pointer to the verified ramdisk image
- * header. Routine receives image start address and expected architecture
- * flag. Verification done covers data and header integrity and os/type/arch
- * fields checking.
- *
- * returns:
- * pointer to a ramdisk image header, if image was found and valid
- * otherwise, return NULL
- */
-static const image_header_t *image_get_ramdisk(ulong rd_addr, uint8_t arch,
- int verify)
-{
- const image_header_t *rd_hdr = (const image_header_t *)rd_addr;
-
- if (!image_check_magic(rd_hdr)) {
- puts("Bad Magic Number\n");
- bootstage_error(BOOTSTAGE_ID_RD_MAGIC);
- return NULL;
- }
-
- if (!image_check_hcrc(rd_hdr)) {
- puts("Bad Header Checksum\n");
- bootstage_error(BOOTSTAGE_ID_RD_HDR_CHECKSUM);
- return NULL;
- }
-
- bootstage_mark(BOOTSTAGE_ID_RD_MAGIC);
- image_print_contents(rd_hdr);
-
- if (verify) {
- puts(" Verifying Checksum ... ");
- if (!image_check_dcrc(rd_hdr)) {
- puts("Bad Data CRC\n");
- bootstage_error(BOOTSTAGE_ID_RD_CHECKSUM);
- return NULL;
- }
- puts("OK\n");
- }
-
- bootstage_mark(BOOTSTAGE_ID_RD_HDR_CHECKSUM);
-
- if (!image_check_os(rd_hdr, IH_OS_LINUX) ||
- !image_check_arch(rd_hdr, arch) ||
- !image_check_type(rd_hdr, IH_TYPE_RAMDISK)) {
- printf("No Linux %s Ramdisk Image\n",
- genimg_get_arch_name(arch));
- bootstage_error(BOOTSTAGE_ID_RAMDISK);
- return NULL;
- }
-
- return rd_hdr;
-}
-#endif
-#endif /* !USE_HOSTCC */
-
-/*****************************************************************************/
-/* Shared dual-format routines */
-/*****************************************************************************/
-#ifndef USE_HOSTCC
-ulong image_load_addr = CONFIG_SYS_LOAD_ADDR; /* Default Load Address */
-ulong image_save_addr; /* Default Save Address */
-ulong image_save_size; /* Default Save Size (in bytes) */
-
-static int on_loadaddr(const char *name, const char *value, enum env_op op,
- int flags)
-{
- switch (op) {
- case env_op_create:
- case env_op_overwrite:
- image_load_addr = hextoul(value, NULL);
- break;
- default:
- break;
- }
-
- return 0;
-}
-U_BOOT_ENV_CALLBACK(loadaddr, on_loadaddr);
-
-ulong env_get_bootm_low(void)
-{
- char *s = env_get("bootm_low");
- if (s) {
- ulong tmp = hextoul(s, NULL);
- return tmp;
- }
-
-#if defined(CONFIG_SYS_SDRAM_BASE)
- return CONFIG_SYS_SDRAM_BASE;
-#elif defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE) || defined(CONFIG_RISCV)
- return gd->bd->bi_dram[0].start;
-#else
return 0;
-#endif
-}
-
-phys_size_t env_get_bootm_size(void)
-{
- phys_size_t tmp, size;
- phys_addr_t start;
- char *s = env_get("bootm_size");
- if (s) {
- tmp = (phys_size_t)simple_strtoull(s, NULL, 16);
- return tmp;
- }
-
- start = gd->ram_base;
- size = gd->ram_size;
-
- if (start + size > gd->ram_top)
- size = gd->ram_top - start;
-
- s = env_get("bootm_low");
- if (s)
- tmp = (phys_size_t)simple_strtoull(s, NULL, 16);
- else
- tmp = start;
-
- return size - (tmp - start);
}
-phys_size_t env_get_bootm_mapsize(void)
-{
- phys_size_t tmp;
- char *s = env_get("bootm_mapsize");
- if (s) {
- tmp = (phys_size_t)simple_strtoull(s, NULL, 16);
- return tmp;
- }
-
-#if defined(CONFIG_SYS_BOOTMAPSZ)
- return CONFIG_SYS_BOOTMAPSZ;
-#else
- return env_get_bootm_size();
-#endif
-}
-
-void memmove_wd(void *to, void *from, size_t len, ulong chunksz)
-{
- if (to == from)
- return;
-
-#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
- if (to > from) {
- from += len;
- to += len;
- }
- while (len > 0) {
- size_t tail = (len > chunksz) ? chunksz : len;
- WATCHDOG_RESET();
- if (to > from) {
- to -= tail;
- from -= tail;
- }
- memmove(to, from, tail);
- if (to < from) {
- to += tail;
- from += tail;
- }
- len -= tail;
- }
-#else /* !(CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG) */
- memmove(to, from, len);
-#endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */
-}
-#else /* USE_HOSTCC */
-void memmove_wd(void *to, void *from, size_t len, ulong chunksz)
-{
- memmove(to, from, len);
-}
-#endif /* !USE_HOSTCC */
-
-void genimg_print_size(uint32_t size)
-{
-#ifndef USE_HOSTCC
- printf("%d Bytes = ", size);
- print_size(size, "\n");
-#else
- printf("%d Bytes = %.2f KiB = %.2f MiB\n",
- size, (double)size / 1.024e3,
- (double)size / 1.048576e6);
-#endif
-}
-
-#if IMAGE_ENABLE_TIMESTAMP
-void genimg_print_time(time_t timestamp)
-{
-#ifndef USE_HOSTCC
- struct rtc_time tm;
-
- rtc_to_tm(timestamp, &tm);
- printf("%4d-%02d-%02d %2d:%02d:%02d UTC\n",
- tm.tm_year, tm.tm_mon, tm.tm_mday,
- tm.tm_hour, tm.tm_min, tm.tm_sec);
-#else
- printf("%s", ctime(×tamp));
-#endif
-}
-#endif
-
const table_entry_t *get_table_entry(const table_entry_t *table, int id)
{
for (; table->id >= 0; ++table) {
@@ -833,11 +566,7 @@
entry = get_table_entry(table_info[category].table, id);
if (!entry)
return unknown_msg(category);
-#if defined(USE_HOSTCC) || !defined(CONFIG_NEEDS_MANUAL_RELOC)
- return entry->lname;
-#else
- return entry->lname + gd->reloc_off;
-#endif
+ return manual_reloc(entry->lname);
}
/**
@@ -857,11 +586,7 @@
entry = get_table_entry(table_info[category].table, id);
if (!entry)
return unknown_msg(category);
-#if defined(USE_HOSTCC) || !defined(CONFIG_NEEDS_MANUAL_RELOC)
- return entry->sname;
-#else
- return entry->sname + gd->reloc_off;
-#endif
+ return manual_reloc(entry->sname);
}
int genimg_get_cat_count(enum ih_category category)
@@ -911,11 +636,7 @@
table = get_table_entry(table, id);
if (!table)
return msg;
-#if defined(USE_HOSTCC) || !defined(CONFIG_NEEDS_MANUAL_RELOC)
- return table->lname;
-#else
- return table->lname + gd->reloc_off;
-#endif
+ return manual_reloc(table->lname);
}
const char *genimg_get_os_name(uint8_t os)
@@ -945,11 +666,7 @@
table = get_table_entry(table, val);
if (!table)
return "unknown";
-#if defined(USE_HOSTCC) || !defined(CONFIG_NEEDS_MANUAL_RELOC)
- return table->sname;
-#else
- return table->sname + gd->reloc_off;
-#endif
+ return manual_reloc(table->sname);
}
const char *genimg_get_type_short_name(uint8_t type)
@@ -992,12 +709,8 @@
const table_entry_t *t;
for (t = table; t->id >= 0; ++t) {
-#ifdef CONFIG_NEEDS_MANUAL_RELOC
- if (t->sname && strcasecmp(t->sname + gd->reloc_off, name) == 0)
-#else
- if (t->sname && strcasecmp(t->sname, name) == 0)
-#endif
- return (t->id);
+ if (t->sname && !strcasecmp(manual_reloc(t->sname), name))
+ return t->id;
}
debug("Invalid %s Type: %s\n", table_name, name);
@@ -1023,733 +736,3 @@
{
return (get_table_entry_id(uimage_comp, "Compression", name));
}
-
-#ifndef USE_HOSTCC
-/**
- * genimg_get_kernel_addr_fit - get the real kernel address and return 2
- * FIT strings
- * @img_addr: a string might contain real image address
- * @fit_uname_config: double pointer to a char, will hold pointer to a
- * configuration unit name
- * @fit_uname_kernel: double pointer to a char, will hold pointer to a subimage
- * name
- *
- * genimg_get_kernel_addr_fit get the real kernel start address from a string
- * which is normally the first argv of bootm/bootz
- *
- * returns:
- * kernel start address
- */
-ulong genimg_get_kernel_addr_fit(char * const img_addr,
- const char **fit_uname_config,
- const char **fit_uname_kernel)
-{
- ulong kernel_addr;
-
- /* find out kernel image address */
- if (!img_addr) {
- kernel_addr = image_load_addr;
- debug("* kernel: default image load address = 0x%08lx\n",
- image_load_addr);
-#if CONFIG_IS_ENABLED(FIT)
- } else if (fit_parse_conf(img_addr, image_load_addr, &kernel_addr,
- fit_uname_config)) {
- debug("* kernel: config '%s' from image at 0x%08lx\n",
- *fit_uname_config, kernel_addr);
- } else if (fit_parse_subimage(img_addr, image_load_addr, &kernel_addr,
- fit_uname_kernel)) {
- debug("* kernel: subimage '%s' from image at 0x%08lx\n",
- *fit_uname_kernel, kernel_addr);
-#endif
- } else {
- kernel_addr = hextoul(img_addr, NULL);
- debug("* kernel: cmdline image address = 0x%08lx\n",
- kernel_addr);
- }
-
- return kernel_addr;
-}
-
-/**
- * genimg_get_kernel_addr() is the simple version of
- * genimg_get_kernel_addr_fit(). It ignores those return FIT strings
- */
-ulong genimg_get_kernel_addr(char * const img_addr)
-{
- const char *fit_uname_config = NULL;
- const char *fit_uname_kernel = NULL;
-
- return genimg_get_kernel_addr_fit(img_addr, &fit_uname_config,
- &fit_uname_kernel);
-}
-
-/**
- * genimg_get_format - get image format type
- * @img_addr: image start address
- *
- * genimg_get_format() checks whether provided address points to a valid
- * legacy or FIT image.
- *
- * New uImage format and FDT blob are based on a libfdt. FDT blob
- * may be passed directly or embedded in a FIT image. In both situations
- * genimg_get_format() must be able to dectect libfdt header.
- *
- * returns:
- * image format type or IMAGE_FORMAT_INVALID if no image is present
- */
-int genimg_get_format(const void *img_addr)
-{
-#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
- const image_header_t *hdr;
-
- hdr = (const image_header_t *)img_addr;
- if (image_check_magic(hdr))
- return IMAGE_FORMAT_LEGACY;
-#endif
-#if IMAGE_ENABLE_FIT || IMAGE_ENABLE_OF_LIBFDT
- if (fdt_check_header(img_addr) == 0)
- return IMAGE_FORMAT_FIT;
-#endif
-#ifdef CONFIG_ANDROID_BOOT_IMAGE
- if (android_image_check_header(img_addr) == 0)
- return IMAGE_FORMAT_ANDROID;
-#endif
-
- return IMAGE_FORMAT_INVALID;
-}
-
-/**
- * fit_has_config - check if there is a valid FIT configuration
- * @images: pointer to the bootm command headers structure
- *
- * fit_has_config() checks if there is a FIT configuration in use
- * (if FTI support is present).
- *
- * returns:
- * 0, no FIT support or no configuration found
- * 1, configuration found
- */
-int genimg_has_config(bootm_headers_t *images)
-{
-#if IMAGE_ENABLE_FIT
- if (images->fit_uname_cfg)
- return 1;
-#endif
- return 0;
-}
-
-/**
- * boot_get_ramdisk - main ramdisk handling routine
- * @argc: command argument count
- * @argv: command argument list
- * @images: pointer to the bootm images structure
- * @arch: expected ramdisk architecture
- * @rd_start: pointer to a ulong variable, will hold ramdisk start address
- * @rd_end: pointer to a ulong variable, will hold ramdisk end
- *
- * boot_get_ramdisk() is responsible for finding a valid ramdisk image.
- * Curently supported are the following ramdisk sources:
- * - multicomponent kernel/ramdisk image,
- * - commandline provided address of decicated ramdisk image.
- *
- * returns:
- * 0, if ramdisk image was found and valid, or skiped
- * rd_start and rd_end are set to ramdisk start/end addresses if
- * ramdisk image is found and valid
- *
- * 1, if ramdisk image is found but corrupted, or invalid
- * rd_start and rd_end are set to 0 if no ramdisk exists
- */
-int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images,
- uint8_t arch, ulong *rd_start, ulong *rd_end)
-{
- ulong rd_addr, rd_load;
- ulong rd_data, rd_len;
-#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
- const image_header_t *rd_hdr;
-#endif
- void *buf;
-#ifdef CONFIG_SUPPORT_RAW_INITRD
- char *end;
-#endif
-#if IMAGE_ENABLE_FIT
- const char *fit_uname_config = images->fit_uname_cfg;
- const char *fit_uname_ramdisk = NULL;
- ulong default_addr;
- int rd_noffset;
-#endif
- const char *select = NULL;
-
- *rd_start = 0;
- *rd_end = 0;
-
-#ifdef CONFIG_ANDROID_BOOT_IMAGE
- /*
- * Look for an Android boot image.
- */
- buf = map_sysmem(images->os.start, 0);
- if (buf && genimg_get_format(buf) == IMAGE_FORMAT_ANDROID)
- select = (argc == 0) ? env_get("loadaddr") : argv[0];
-#endif
-
- if (argc >= 2)
- select = argv[1];
-
- /*
- * Look for a '-' which indicates to ignore the
- * ramdisk argument
- */
- if (select && strcmp(select, "-") == 0) {
- debug("## Skipping init Ramdisk\n");
- rd_len = rd_data = 0;
- } else if (select || genimg_has_config(images)) {
-#if IMAGE_ENABLE_FIT
- if (select) {
- /*
- * If the init ramdisk comes from the FIT image and
- * the FIT image address is omitted in the command
- * line argument, try to use os FIT image address or
- * default load address.
- */
- if (images->fit_uname_os)
- default_addr = (ulong)images->fit_hdr_os;
- else
- default_addr = image_load_addr;
-
- if (fit_parse_conf(select, default_addr,
- &rd_addr, &fit_uname_config)) {
- debug("* ramdisk: config '%s' from image at "
- "0x%08lx\n",
- fit_uname_config, rd_addr);
- } else if (fit_parse_subimage(select, default_addr,
- &rd_addr, &fit_uname_ramdisk)) {
- debug("* ramdisk: subimage '%s' from image at "
- "0x%08lx\n",
- fit_uname_ramdisk, rd_addr);
- } else
-#endif
- {
- rd_addr = hextoul(select, NULL);
- debug("* ramdisk: cmdline image address = "
- "0x%08lx\n",
- rd_addr);
- }
-#if IMAGE_ENABLE_FIT
- } else {
- /* use FIT configuration provided in first bootm
- * command argument. If the property is not defined,
- * quit silently.
- */
- rd_addr = map_to_sysmem(images->fit_hdr_os);
- rd_noffset = fit_get_node_from_config(images,
- FIT_RAMDISK_PROP, rd_addr);
- if (rd_noffset == -ENOENT)
- return 0;
- else if (rd_noffset < 0)
- return 1;
- }
-#endif
-
- /*
- * Check if there is an initrd image at the
- * address provided in the second bootm argument
- * check image type, for FIT images get FIT node.
- */
- buf = map_sysmem(rd_addr, 0);
- switch (genimg_get_format(buf)) {
-#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
- case IMAGE_FORMAT_LEGACY:
- printf("## Loading init Ramdisk from Legacy "
- "Image at %08lx ...\n", rd_addr);
-
- bootstage_mark(BOOTSTAGE_ID_CHECK_RAMDISK);
- rd_hdr = image_get_ramdisk(rd_addr, arch,
- images->verify);
-
- if (rd_hdr == NULL)
- return 1;
-
- rd_data = image_get_data(rd_hdr);
- rd_len = image_get_data_size(rd_hdr);
- rd_load = image_get_load(rd_hdr);
- break;
-#endif
-#if IMAGE_ENABLE_FIT
- case IMAGE_FORMAT_FIT:
- rd_noffset = fit_image_load(images,
- rd_addr, &fit_uname_ramdisk,
- &fit_uname_config, arch,
- IH_TYPE_RAMDISK,
- BOOTSTAGE_ID_FIT_RD_START,
- FIT_LOAD_OPTIONAL_NON_ZERO,
- &rd_data, &rd_len);
- if (rd_noffset < 0)
- return 1;
-
- images->fit_hdr_rd = map_sysmem(rd_addr, 0);
- images->fit_uname_rd = fit_uname_ramdisk;
- images->fit_noffset_rd = rd_noffset;
- break;
-#endif
-#ifdef CONFIG_ANDROID_BOOT_IMAGE
- case IMAGE_FORMAT_ANDROID:
- android_image_get_ramdisk((void *)images->os.start,
- &rd_data, &rd_len);
- break;
-#endif
- default:
-#ifdef CONFIG_SUPPORT_RAW_INITRD
- end = NULL;
- if (select)
- end = strchr(select, ':');
- if (end) {
- rd_len = hextoul(++end, NULL);
- rd_data = rd_addr;
- } else
-#endif
- {
- puts("Wrong Ramdisk Image Format\n");
- rd_data = rd_len = rd_load = 0;
- return 1;
- }
- }
- } else if (images->legacy_hdr_valid &&
- image_check_type(&images->legacy_hdr_os_copy,
- IH_TYPE_MULTI)) {
-
- /*
- * Now check if we have a legacy mult-component image,
- * get second entry data start address and len.
- */
- bootstage_mark(BOOTSTAGE_ID_RAMDISK);
- printf("## Loading init Ramdisk from multi component "
- "Legacy Image at %08lx ...\n",
- (ulong)images->legacy_hdr_os);
-
- image_multi_getimg(images->legacy_hdr_os, 1, &rd_data, &rd_len);
- } else {
- /*
- * no initrd image
- */
- bootstage_mark(BOOTSTAGE_ID_NO_RAMDISK);
- rd_len = rd_data = 0;
- }
-
- if (!rd_data) {
- debug("## No init Ramdisk\n");
- } else {
- *rd_start = rd_data;
- *rd_end = rd_data + rd_len;
- }
- debug(" ramdisk start = 0x%08lx, ramdisk end = 0x%08lx\n",
- *rd_start, *rd_end);
-
- return 0;
-}
-
-#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH
-/**
- * boot_ramdisk_high - relocate init ramdisk
- * @lmb: pointer to lmb handle, will be used for memory mgmt
- * @rd_data: ramdisk data start address
- * @rd_len: ramdisk data length
- * @initrd_start: pointer to a ulong variable, will hold final init ramdisk
- * start address (after possible relocation)
- * @initrd_end: pointer to a ulong variable, will hold final init ramdisk
- * end address (after possible relocation)
- *
- * boot_ramdisk_high() takes a relocation hint from "initrd_high" environment
- * variable and if requested ramdisk data is moved to a specified location.
- *
- * Initrd_start and initrd_end are set to final (after relocation) ramdisk
- * start/end addresses if ramdisk image start and len were provided,
- * otherwise set initrd_start and initrd_end set to zeros.
- *
- * returns:
- * 0 - success
- * -1 - failure
- */
-int boot_ramdisk_high(struct lmb *lmb, ulong rd_data, ulong rd_len,
- ulong *initrd_start, ulong *initrd_end)
-{
- char *s;
- ulong initrd_high;
- int initrd_copy_to_ram = 1;
-
- s = env_get("initrd_high");
- if (s) {
- /* a value of "no" or a similar string will act like 0,
- * turning the "load high" feature off. This is intentional.
- */
- initrd_high = hextoul(s, NULL);
- if (initrd_high == ~0)
- initrd_copy_to_ram = 0;
- } else {
- initrd_high = env_get_bootm_mapsize() + env_get_bootm_low();
- }
-
-
- debug("## initrd_high = 0x%08lx, copy_to_ram = %d\n",
- initrd_high, initrd_copy_to_ram);
-
- if (rd_data) {
- if (!initrd_copy_to_ram) { /* zero-copy ramdisk support */
- debug(" in-place initrd\n");
- *initrd_start = rd_data;
- *initrd_end = rd_data + rd_len;
- lmb_reserve(lmb, rd_data, rd_len);
- } else {
- if (initrd_high)
- *initrd_start = (ulong)lmb_alloc_base(lmb,
- rd_len, 0x1000, initrd_high);
- else
- *initrd_start = (ulong)lmb_alloc(lmb, rd_len,
- 0x1000);
-
- if (*initrd_start == 0) {
- puts("ramdisk - allocation error\n");
- goto error;
- }
- bootstage_mark(BOOTSTAGE_ID_COPY_RAMDISK);
-
- *initrd_end = *initrd_start + rd_len;
- printf(" Loading Ramdisk to %08lx, end %08lx ... ",
- *initrd_start, *initrd_end);
-
- memmove_wd((void *)*initrd_start,
- (void *)rd_data, rd_len, CHUNKSZ);
-
-#ifdef CONFIG_MP
- /*
- * Ensure the image is flushed to memory to handle
- * AMP boot scenarios in which we might not be
- * HW cache coherent
- */
- flush_cache((unsigned long)*initrd_start,
- ALIGN(rd_len, ARCH_DMA_MINALIGN));
-#endif
- puts("OK\n");
- }
- } else {
- *initrd_start = 0;
- *initrd_end = 0;
- }
- debug(" ramdisk load start = 0x%08lx, ramdisk load end = 0x%08lx\n",
- *initrd_start, *initrd_end);
-
- return 0;
-
-error:
- return -1;
-}
-#endif /* CONFIG_SYS_BOOT_RAMDISK_HIGH */
-
-int boot_get_setup(bootm_headers_t *images, uint8_t arch,
- ulong *setup_start, ulong *setup_len)
-{
-#if IMAGE_ENABLE_FIT
- return boot_get_setup_fit(images, arch, setup_start, setup_len);
-#else
- return -ENOENT;
-#endif
-}
-
-#if IMAGE_ENABLE_FIT
-#if defined(CONFIG_FPGA)
-int boot_get_fpga(int argc, char *const argv[], bootm_headers_t *images,
- uint8_t arch, const ulong *ld_start, ulong * const ld_len)
-{
- ulong tmp_img_addr, img_data, img_len;
- void *buf;
- int conf_noffset;
- int fit_img_result;
- const char *uname, *name;
- int err;
- int devnum = 0; /* TODO support multi fpga platforms */
-
- /* Check to see if the images struct has a FIT configuration */
- if (!genimg_has_config(images)) {
- debug("## FIT configuration was not specified\n");
- return 0;
- }
-
- /*
- * Obtain the os FIT header from the images struct
- */
- tmp_img_addr = map_to_sysmem(images->fit_hdr_os);
- buf = map_sysmem(tmp_img_addr, 0);
- /*
- * Check image type. For FIT images get FIT node
- * and attempt to locate a generic binary.
- */
- switch (genimg_get_format(buf)) {
- case IMAGE_FORMAT_FIT:
- conf_noffset = fit_conf_get_node(buf, images->fit_uname_cfg);
-
- uname = fdt_stringlist_get(buf, conf_noffset, FIT_FPGA_PROP, 0,
- NULL);
- if (!uname) {
- debug("## FPGA image is not specified\n");
- return 0;
- }
- fit_img_result = fit_image_load(images,
- tmp_img_addr,
- (const char **)&uname,
- &(images->fit_uname_cfg),
- arch,
- IH_TYPE_FPGA,
- BOOTSTAGE_ID_FPGA_INIT,
- FIT_LOAD_OPTIONAL_NON_ZERO,
- &img_data, &img_len);
-
- debug("FPGA image (%s) loaded to 0x%lx/size 0x%lx\n",
- uname, img_data, img_len);
-
- if (fit_img_result < 0) {
- /* Something went wrong! */
- return fit_img_result;
- }
-
- if (!fpga_is_partial_data(devnum, img_len)) {
- name = "full";
- err = fpga_loadbitstream(devnum, (char *)img_data,
- img_len, BIT_FULL);
- if (err)
- err = fpga_load(devnum, (const void *)img_data,
- img_len, BIT_FULL);
- } else {
- name = "partial";
- err = fpga_loadbitstream(devnum, (char *)img_data,
- img_len, BIT_PARTIAL);
- if (err)
- err = fpga_load(devnum, (const void *)img_data,
- img_len, BIT_PARTIAL);
- }
-
- if (err)
- return err;
-
- printf(" Programming %s bitstream... OK\n", name);
- break;
- default:
- printf("The given image format is not supported (corrupt?)\n");
- return 1;
- }
-
- return 0;
-}
-#endif
-
-static void fit_loadable_process(uint8_t img_type,
- ulong img_data,
- ulong img_len)
-{
- int i;
- const unsigned int count =
- ll_entry_count(struct fit_loadable_tbl, fit_loadable);
- struct fit_loadable_tbl *fit_loadable_handler =
- ll_entry_start(struct fit_loadable_tbl, fit_loadable);
- /* For each loadable handler */
- for (i = 0; i < count; i++, fit_loadable_handler++)
- /* matching this type */
- if (fit_loadable_handler->type == img_type)
- /* call that handler with this image data */
- fit_loadable_handler->handler(img_data, img_len);
-}
-
-int boot_get_loadable(int argc, char *const argv[], bootm_headers_t *images,
- uint8_t arch, const ulong *ld_start, ulong * const ld_len)
-{
- /*
- * These variables are used to hold the current image location
- * in system memory.
- */
- ulong tmp_img_addr;
- /*
- * These two variables are requirements for fit_image_load, but
- * their values are not used
- */
- ulong img_data, img_len;
- void *buf;
- int loadables_index;
- int conf_noffset;
- int fit_img_result;
- const char *uname;
- uint8_t img_type;
-
- /* Check to see if the images struct has a FIT configuration */
- if (!genimg_has_config(images)) {
- debug("## FIT configuration was not specified\n");
- return 0;
- }
-
- /*
- * Obtain the os FIT header from the images struct
- */
- tmp_img_addr = map_to_sysmem(images->fit_hdr_os);
- buf = map_sysmem(tmp_img_addr, 0);
- /*
- * Check image type. For FIT images get FIT node
- * and attempt to locate a generic binary.
- */
- switch (genimg_get_format(buf)) {
- case IMAGE_FORMAT_FIT:
- conf_noffset = fit_conf_get_node(buf, images->fit_uname_cfg);
-
- for (loadables_index = 0;
- uname = fdt_stringlist_get(buf, conf_noffset,
- FIT_LOADABLE_PROP, loadables_index,
- NULL), uname;
- loadables_index++)
- {
- fit_img_result = fit_image_load(images,
- tmp_img_addr,
- &uname,
- &(images->fit_uname_cfg), arch,
- IH_TYPE_LOADABLE,
- BOOTSTAGE_ID_FIT_LOADABLE_START,
- FIT_LOAD_OPTIONAL_NON_ZERO,
- &img_data, &img_len);
- if (fit_img_result < 0) {
- /* Something went wrong! */
- return fit_img_result;
- }
-
- fit_img_result = fit_image_get_node(buf, uname);
- if (fit_img_result < 0) {
- /* Something went wrong! */
- return fit_img_result;
- }
- fit_img_result = fit_image_get_type(buf,
- fit_img_result,
- &img_type);
- if (fit_img_result < 0) {
- /* Something went wrong! */
- return fit_img_result;
- }
-
- fit_loadable_process(img_type, img_data, img_len);
- }
- break;
- default:
- printf("The given image format is not supported (corrupt?)\n");
- return 1;
- }
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_SYS_BOOT_GET_CMDLINE
-/**
- * boot_get_cmdline - allocate and initialize kernel cmdline
- * @lmb: pointer to lmb handle, will be used for memory mgmt
- * @cmd_start: pointer to a ulong variable, will hold cmdline start
- * @cmd_end: pointer to a ulong variable, will hold cmdline end
- *
- * boot_get_cmdline() allocates space for kernel command line below
- * BOOTMAPSZ + env_get_bootm_low() address. If "bootargs" U-Boot environment
- * variable is present its contents is copied to allocated kernel
- * command line.
- *
- * returns:
- * 0 - success
- * -1 - failure
- */
-int boot_get_cmdline(struct lmb *lmb, ulong *cmd_start, ulong *cmd_end)
-{
- char *cmdline;
- char *s;
-
- cmdline = (char *)(ulong)lmb_alloc_base(lmb, CONFIG_SYS_BARGSIZE, 0xf,
- env_get_bootm_mapsize() + env_get_bootm_low());
-
- if (cmdline == NULL)
- return -1;
-
- s = env_get("bootargs");
- if (!s)
- s = "";
-
- strcpy(cmdline, s);
-
- *cmd_start = (ulong) & cmdline[0];
- *cmd_end = *cmd_start + strlen(cmdline);
-
- debug("## cmdline at 0x%08lx ... 0x%08lx\n", *cmd_start, *cmd_end);
-
- return 0;
-}
-#endif /* CONFIG_SYS_BOOT_GET_CMDLINE */
-
-#ifdef CONFIG_SYS_BOOT_GET_KBD
-/**
- * boot_get_kbd - allocate and initialize kernel copy of board info
- * @lmb: pointer to lmb handle, will be used for memory mgmt
- * @kbd: double pointer to board info data
- *
- * boot_get_kbd() allocates space for kernel copy of board info data below
- * BOOTMAPSZ + env_get_bootm_low() address and kernel board info is initialized
- * with the current u-boot board info data.
- *
- * returns:
- * 0 - success
- * -1 - failure
- */
-int boot_get_kbd(struct lmb *lmb, struct bd_info **kbd)
-{
- *kbd = (struct bd_info *)(ulong)lmb_alloc_base(lmb,
- sizeof(struct bd_info),
- 0xf,
- env_get_bootm_mapsize() + env_get_bootm_low());
- if (*kbd == NULL)
- return -1;
-
- **kbd = *(gd->bd);
-
- debug("## kernel board info at 0x%08lx\n", (ulong)*kbd);
-
-#if defined(DEBUG) && defined(CONFIG_CMD_BDI)
- do_bdinfo(NULL, 0, 0, NULL);
-#endif
-
- return 0;
-}
-#endif /* CONFIG_SYS_BOOT_GET_KBD */
-
-#ifdef CONFIG_LMB
-int image_setup_linux(bootm_headers_t *images)
-{
- ulong of_size = images->ft_len;
- char **of_flat_tree = &images->ft_addr;
- struct lmb *lmb = &images->lmb;
- int ret;
-
- if (IMAGE_ENABLE_OF_LIBFDT)
- boot_fdt_add_mem_rsv_regions(lmb, *of_flat_tree);
-
- if (IMAGE_BOOT_GET_CMDLINE) {
- ret = boot_get_cmdline(lmb, &images->cmdline_start,
- &images->cmdline_end);
- if (ret) {
- puts("ERROR with allocation of cmdline\n");
- return ret;
- }
- }
-
- if (IMAGE_ENABLE_OF_LIBFDT) {
- ret = boot_relocate_fdt(lmb, of_flat_tree, &of_size);
- if (ret)
- return ret;
- }
-
- if (IMAGE_ENABLE_OF_LIBFDT && of_size) {
- ret = image_setup_libfdt(images, *of_flat_tree, of_size, lmb);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-#endif /* CONFIG_LMB */
-#endif /* !USE_HOSTCC */
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 8a8a971..17ce2f6 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -419,7 +419,8 @@
config SPL_CRC32
bool "Support CRC32"
- default y if SPL_LEGACY_IMAGE_SUPPORT
+ default y if SPL_LEGACY_IMAGE_SUPPORT || SPL_EFI_PARTITION
+ default y if SPL_ENV_SUPPORT || TPL_BLOBLIST
help
Enable this to support CRC32 in uImages or FIT images within SPL.
This is a 32-bit checksum value that can be used to verify images.
@@ -1419,6 +1420,16 @@
BOOT_DEVICE_BOOTROM (or fall-through to the next boot device in the
boot device list, if not implemented for a given board)
+config TPL_CRC32
+ bool "Support CRC32 in TPL"
+ default y if TPL_ENV_SUPPORT || TPL_BLOBLIST
+ help
+ Enable this to support CRC32 in uImages or FIT images within SPL.
+ This is a 32-bit checksum value that can be used to verify images.
+ For FIT images, this is the least secure type of checksum, suitable
+ for detected accidental image corruption. For secure applications you
+ should consider SHA1 or SHA256.
+
config TPL_DRIVERS_MISC
bool "Support misc drivers in TPL"
help
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index f41abca..5fe0273 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -538,6 +538,11 @@
return buf;
}
+__weak void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len)
+{
+ return spl_get_fit_load_buffer(sectors * bl_len);
+}
+
/*
* Weak default function to allow customizing SPL fit loading for load-only
* use cases by allowing to skip the parsing/processing of the FIT contents
@@ -548,6 +553,15 @@
return false;
}
+/*
+ * Weak default function to allow fixes after fit header
+ * is loaded.
+ */
+__weak void *spl_load_simple_fit_fix_load(const void *fit)
+{
+ return (void *)fit;
+}
+
static void warn_deprecated(const char *msg)
{
printf("DEPRECATED: %s\n", msg);
@@ -631,7 +645,7 @@
* For FIT with external data, data is not loaded in this step.
*/
sectors = get_aligned_image_size(info, size, 0);
- buf = spl_get_fit_load_buffer(sectors * info->bl_len);
+ buf = board_spl_fit_buffer_addr(size, sectors, info->bl_len);
count = info->read(info, sector, sectors, buf);
ctx->fit = buf;
@@ -685,6 +699,8 @@
if (spl_load_simple_fit_skip_processing())
return 0;
+ ctx.fit = spl_load_simple_fit_fix_load(ctx.fit);
+
ret = spl_simple_fit_parse(&ctx);
if (ret < 0)
return ret;
diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig
index ececdac..075d999 100644
--- a/configs/A20-Olimex-SOM-EVB_defconfig
+++ b/configs/A20-Olimex-SOM-EVB_defconfig
@@ -6,7 +6,6 @@
CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_MMC3_CD_PIN="PH0"
-CONFIG_MMC3_PINS="PH"
CONFIG_MMC_SUNXI_SLOT_EXTRA=3
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_USB0_VBUS_DET="PH5"
diff --git a/configs/Bananapi_M2_Ultra_defconfig b/configs/Bananapi_M2_Ultra_defconfig
index a24c600..8917af3 100644
--- a/configs/Bananapi_M2_Ultra_defconfig
+++ b/configs/Bananapi_M2_Ultra_defconfig
@@ -13,7 +13,6 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
-CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000
diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig
index 31541f8..270bd7d 100644
--- a/configs/Colombus_defconfig
+++ b/configs/Colombus_defconfig
@@ -13,15 +13,9 @@
CONFIG_VIDEO_LCD_POWER="PH27"
CONFIG_VIDEO_LCD_BL_EN="PM1"
CONFIG_VIDEO_LCD_BL_PWM="PH13"
-CONFIG_VIDEO_LCD_PANEL_I2C_SDA="PA23"
-CONFIG_VIDEO_LCD_PANEL_I2C_SCL="PA24"
CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_I2C_LEGACY=y
CONFIG_SPL_SYS_I2C_LEGACY=y
-CONFIG_SYS_I2C_SOFT=y
-CONFIG_SYS_I2C_SOFT_SPEED=50000
-CONFIG_SYS_I2C_SOFT_SLAVE=0x00
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000
diff --git a/configs/Cubieboard4_defconfig b/configs/Cubieboard4_defconfig
index c66f29e..04ed79a 100644
--- a/configs/Cubieboard4_defconfig
+++ b/configs/Cubieboard4_defconfig
@@ -12,4 +12,5 @@
CONFIG_USB1_VBUS_PIN="PH14"
CONFIG_USB3_VBUS_PIN="PH15"
CONFIG_AXP_GPIO=y
+CONFIG_SYS_I2C_SUN8I_RSB=y
CONFIG_AXP809_POWER=y
diff --git a/configs/Cubietruck_plus_defconfig b/configs/Cubietruck_plus_defconfig
index a4f8869..13f9589 100644
--- a/configs/Cubietruck_plus_defconfig
+++ b/configs/Cubietruck_plus_defconfig
@@ -16,7 +16,6 @@
CONFIG_AXP_GPIO=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
-CONFIG_SYS_I2C_LEGACY=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/Merrii_A80_Optimus_defconfig b/configs/Merrii_A80_Optimus_defconfig
index 0944e64..c5d1f40 100644
--- a/configs/Merrii_A80_Optimus_defconfig
+++ b/configs/Merrii_A80_Optimus_defconfig
@@ -12,4 +12,5 @@
CONFIG_USB1_VBUS_PIN="PH4"
CONFIG_USB3_VBUS_PIN="PH5"
CONFIG_AXP_GPIO=y
+CONFIG_SYS_I2C_SUN8I_RSB=y
CONFIG_AXP809_POWER=y
diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig
index 628880a..acd841a 100644
--- a/configs/P1010RDB-PA_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig
@@ -71,7 +71,6 @@
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x4000
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig
index 59c7569..32d5e38 100644
--- a/configs/P1010RDB-PA_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig
@@ -50,7 +50,6 @@
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
index e8df2c3..9254c40 100644
--- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
@@ -62,7 +62,6 @@
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
index 7d2ccc7..4d8f5d8 100644
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
@@ -64,7 +64,6 @@
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig
index caac1e5..24421a6 100644
--- a/configs/P1010RDB-PA_NAND_defconfig
+++ b/configs/P1010RDB-PA_NAND_defconfig
@@ -70,7 +70,6 @@
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x4000
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig
index abeb433..09b4120 100644
--- a/configs/P1010RDB-PA_NOR_defconfig
+++ b/configs/P1010RDB-PA_NOR_defconfig
@@ -49,7 +49,6 @@
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig
index a29ff27..9db5a98 100644
--- a/configs/P1010RDB-PA_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_SDCARD_defconfig
@@ -61,7 +61,6 @@
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig
index 5192377..d3e73b6 100644
--- a/configs/P1010RDB-PA_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_SPIFLASH_defconfig
@@ -63,7 +63,6 @@
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig
index 99dbf2c..f618707 100644
--- a/configs/P1010RDB-PB_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig
@@ -74,7 +74,6 @@
CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig
index 44ba09c..16cb143 100644
--- a/configs/P1010RDB-PB_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig
@@ -52,7 +52,6 @@
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
index a895c61..cf9203e 100644
--- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
@@ -64,7 +64,6 @@
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
index ce175e8..9868c99 100644
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
@@ -66,7 +66,6 @@
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig
index 76a81b6..421025e 100644
--- a/configs/P1010RDB-PB_NAND_defconfig
+++ b/configs/P1010RDB-PB_NAND_defconfig
@@ -73,7 +73,6 @@
CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig
index 46fbed2..555cce9 100644
--- a/configs/P1010RDB-PB_NOR_defconfig
+++ b/configs/P1010RDB-PB_NOR_defconfig
@@ -51,7 +51,6 @@
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig
index db47f4f..724d692 100644
--- a/configs/P1010RDB-PB_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_SDCARD_defconfig
@@ -63,7 +63,6 @@
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig
index 5c549cc..b79e3b8 100644
--- a/configs/P1010RDB-PB_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_SPIFLASH_defconfig
@@ -65,7 +65,6 @@
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig
index 3abcb71..52e6ee4 100644
--- a/configs/P1020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig
@@ -71,7 +71,6 @@
CONFIG_NAND_FSL_ELBC=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x4000
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
index 9941c14..7f6ff42 100644
--- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
@@ -63,7 +63,6 @@
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
index 6152ef9..4cac391 100644
--- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -65,7 +65,6 @@
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig
index d7cc4db..c1dcb42 100644
--- a/configs/P1020RDB-PC_36BIT_defconfig
+++ b/configs/P1020RDB-PC_36BIT_defconfig
@@ -52,7 +52,6 @@
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig
index cd573cb..66ab208 100644
--- a/configs/P1020RDB-PC_NAND_defconfig
+++ b/configs/P1020RDB-PC_NAND_defconfig
@@ -70,7 +70,6 @@
CONFIG_NAND_FSL_ELBC=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x4000
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig
index 5d668ca..4ee631e 100644
--- a/configs/P1020RDB-PC_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_SDCARD_defconfig
@@ -62,7 +62,6 @@
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig
index bc5f577..e41c372 100644
--- a/configs/P1020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_SPIFLASH_defconfig
@@ -64,7 +64,6 @@
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig
index 0778dc6..10f39a9 100644
--- a/configs/P1020RDB-PC_defconfig
+++ b/configs/P1020RDB-PC_defconfig
@@ -51,7 +51,6 @@
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig
index 3b5a14b..b4e2322 100644
--- a/configs/P1020RDB-PD_NAND_defconfig
+++ b/configs/P1020RDB-PD_NAND_defconfig
@@ -74,7 +74,6 @@
CONFIG_NAND_FSL_ELBC=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig
index 4f4e5f5..dee35ee 100644
--- a/configs/P1020RDB-PD_SDCARD_defconfig
+++ b/configs/P1020RDB-PD_SDCARD_defconfig
@@ -66,7 +66,6 @@
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig
index 205ca03..cc354f0 100644
--- a/configs/P1020RDB-PD_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PD_SPIFLASH_defconfig
@@ -68,7 +68,6 @@
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig
index c7ba60c..400ab1e 100644
--- a/configs/P1020RDB-PD_defconfig
+++ b/configs/P1020RDB-PD_defconfig
@@ -55,7 +55,6 @@
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig
index 3d72d46..47a87ac 100644
--- a/configs/P2020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig
@@ -76,7 +76,6 @@
CONFIG_NAND_FSL_ELBC=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x4000
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
index 282ed31..e3496c4 100644
--- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
@@ -68,7 +68,6 @@
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
index fe2bf1a..9397105 100644
--- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -70,7 +70,6 @@
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig
index 9252151..c3bc4d1 100644
--- a/configs/P2020RDB-PC_36BIT_defconfig
+++ b/configs/P2020RDB-PC_36BIT_defconfig
@@ -57,7 +57,6 @@
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig
index c700ee4..1ca7844 100644
--- a/configs/P2020RDB-PC_NAND_defconfig
+++ b/configs/P2020RDB-PC_NAND_defconfig
@@ -75,7 +75,6 @@
CONFIG_NAND_FSL_ELBC=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x4000
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig
index 32e509d..34e9557 100644
--- a/configs/P2020RDB-PC_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_SDCARD_defconfig
@@ -67,7 +67,6 @@
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig
index bfee816..1fb8449 100644
--- a/configs/P2020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_SPIFLASH_defconfig
@@ -69,7 +69,6 @@
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig
index dbd2d87..4b4bad5 100644
--- a/configs/P2020RDB-PC_defconfig
+++ b/configs/P2020RDB-PC_defconfig
@@ -56,7 +56,6 @@
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig
index 5e6f3be..1018275 100644
--- a/configs/P2041RDB_NAND_defconfig
+++ b/configs/P2041RDB_NAND_defconfig
@@ -51,7 +51,6 @@
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_ELBC=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig
index 67c4f40..767b8a7 100644
--- a/configs/P2041RDB_SDCARD_defconfig
+++ b/configs/P2041RDB_SDCARD_defconfig
@@ -50,7 +50,6 @@
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig
index 6e0b99a..06aad47 100644
--- a/configs/P2041RDB_SPIFLASH_defconfig
+++ b/configs/P2041RDB_SPIFLASH_defconfig
@@ -51,7 +51,6 @@
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig
index 49e485d..7d95064 100644
--- a/configs/P2041RDB_defconfig
+++ b/configs/P2041RDB_defconfig
@@ -46,7 +46,6 @@
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig
index 6d1f346..fbaa5be 100644
--- a/configs/P3041DS_NAND_defconfig
+++ b/configs/P3041DS_NAND_defconfig
@@ -51,7 +51,6 @@
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_ELBC=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig
index 43d0d31..3277be6 100644
--- a/configs/P3041DS_SDCARD_defconfig
+++ b/configs/P3041DS_SDCARD_defconfig
@@ -50,7 +50,6 @@
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig
index f905a5a..a1f0da6 100644
--- a/configs/P3041DS_SPIFLASH_defconfig
+++ b/configs/P3041DS_SPIFLASH_defconfig
@@ -51,7 +51,6 @@
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig
index 7406b1e..d659d68 100644
--- a/configs/P3041DS_defconfig
+++ b/configs/P3041DS_defconfig
@@ -46,7 +46,6 @@
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig
index ed46a1b..ce95b17 100644
--- a/configs/P4080DS_SDCARD_defconfig
+++ b/configs/P4080DS_SDCARD_defconfig
@@ -49,7 +49,6 @@
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig
index ae46fd4..cd4a914 100644
--- a/configs/P4080DS_SPIFLASH_defconfig
+++ b/configs/P4080DS_SPIFLASH_defconfig
@@ -50,7 +50,6 @@
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig
index d9094b9..4960ef0 100644
--- a/configs/P4080DS_defconfig
+++ b/configs/P4080DS_defconfig
@@ -45,7 +45,6 @@
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig
index 87e88d4..ef6a2b9 100644
--- a/configs/P5040DS_NAND_defconfig
+++ b/configs/P5040DS_NAND_defconfig
@@ -52,7 +52,6 @@
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_ELBC=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig
index a1b4cf3..80c2c68 100644
--- a/configs/P5040DS_SDCARD_defconfig
+++ b/configs/P5040DS_SDCARD_defconfig
@@ -50,7 +50,6 @@
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig
index 27b009c..211a683 100644
--- a/configs/P5040DS_SPIFLASH_defconfig
+++ b/configs/P5040DS_SPIFLASH_defconfig
@@ -51,7 +51,6 @@
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig
index 89924b4..5ebc4c3 100644
--- a/configs/P5040DS_defconfig
+++ b/configs/P5040DS_defconfig
@@ -46,7 +46,6 @@
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
diff --git a/configs/Sinlinx_SinA31s_defconfig b/configs/Sinlinx_SinA31s_defconfig
index 8fa8246..238b007 100644
--- a/configs/Sinlinx_SinA31s_defconfig
+++ b/configs/Sinlinx_SinA31s_defconfig
@@ -6,7 +6,6 @@
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=251
CONFIG_MMC0_CD_PIN="PA4"
-CONFIG_MMC3_PINS="PC"
CONFIG_MMC_SUNXI_SLOT_EXTRA=3
CONFIG_USB1_VBUS_PIN=""
CONFIG_USB2_VBUS_PIN=""
diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig
index 9330f71..21e6986 100644
--- a/configs/T1024RDB_NAND_defconfig
+++ b/configs/T1024RDB_NAND_defconfig
@@ -84,7 +84,6 @@
CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig
index 82848a7..47cac6b 100644
--- a/configs/T1024RDB_SDCARD_defconfig
+++ b/configs/T1024RDB_SDCARD_defconfig
@@ -79,7 +79,6 @@
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig
index a9424fa..ef38ace 100644
--- a/configs/T1024RDB_SPIFLASH_defconfig
+++ b/configs/T1024RDB_SPIFLASH_defconfig
@@ -81,7 +81,6 @@
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig
index 8b07e21..8da4802 100644
--- a/configs/T1024RDB_defconfig
+++ b/configs/T1024RDB_defconfig
@@ -64,7 +64,6 @@
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig
index b4a5ff7..ce9c6b8 100644
--- a/configs/T1042D4RDB_NAND_defconfig
+++ b/configs/T1042D4RDB_NAND_defconfig
@@ -78,7 +78,6 @@
CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig
index 6d9f777..7b0289f 100644
--- a/configs/T1042D4RDB_SDCARD_defconfig
+++ b/configs/T1042D4RDB_SDCARD_defconfig
@@ -73,7 +73,6 @@
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig
index b818e63..71a39c2 100644
--- a/configs/T1042D4RDB_SPIFLASH_defconfig
+++ b/configs/T1042D4RDB_SPIFLASH_defconfig
@@ -75,7 +75,6 @@
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig
index 2fdf470..12f1349 100644
--- a/configs/T1042D4RDB_defconfig
+++ b/configs/T1042D4RDB_defconfig
@@ -58,7 +58,6 @@
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig
index 5f3ec9c..e4cbcf2 100644
--- a/configs/T2080QDS_NAND_defconfig
+++ b/configs/T2080QDS_NAND_defconfig
@@ -76,7 +76,6 @@
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig
index 0046c71..6fc5f01 100644
--- a/configs/T2080QDS_SDCARD_defconfig
+++ b/configs/T2080QDS_SDCARD_defconfig
@@ -71,7 +71,6 @@
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig
index dc3e985..c303433 100644
--- a/configs/T2080QDS_SECURE_BOOT_defconfig
+++ b/configs/T2080QDS_SECURE_BOOT_defconfig
@@ -55,7 +55,6 @@
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig
index 9c1912e..cb459ec 100644
--- a/configs/T2080QDS_SPIFLASH_defconfig
+++ b/configs/T2080QDS_SPIFLASH_defconfig
@@ -73,7 +73,6 @@
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
index 344e2cb..1dc5cf8 100644
--- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
@@ -48,7 +48,6 @@
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig
index 1679ef1..00cd009 100644
--- a/configs/T2080QDS_defconfig
+++ b/configs/T2080QDS_defconfig
@@ -56,7 +56,6 @@
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig
index 72e3d50..7ebe8e3 100644
--- a/configs/T2080RDB_NAND_defconfig
+++ b/configs/T2080RDB_NAND_defconfig
@@ -82,7 +82,6 @@
CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig
index 68989d7..b8656ef 100644
--- a/configs/T2080RDB_SDCARD_defconfig
+++ b/configs/T2080RDB_SDCARD_defconfig
@@ -77,7 +77,6 @@
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig
index 6a9752a..b0d5e25 100644
--- a/configs/T2080RDB_SPIFLASH_defconfig
+++ b/configs/T2080RDB_SPIFLASH_defconfig
@@ -79,7 +79,6 @@
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig
index db0c09b..610f706 100644
--- a/configs/T2080RDB_defconfig
+++ b/configs/T2080RDB_defconfig
@@ -62,7 +62,6 @@
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
diff --git a/configs/T2080RDB_revD_NAND_defconfig b/configs/T2080RDB_revD_NAND_defconfig
index c7482d6..b56314b 100644
--- a/configs/T2080RDB_revD_NAND_defconfig
+++ b/configs/T2080RDB_revD_NAND_defconfig
@@ -83,7 +83,6 @@
CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
diff --git a/configs/T2080RDB_revD_SDCARD_defconfig b/configs/T2080RDB_revD_SDCARD_defconfig
index f7f37e8..1c42f54 100644
--- a/configs/T2080RDB_revD_SDCARD_defconfig
+++ b/configs/T2080RDB_revD_SDCARD_defconfig
@@ -78,7 +78,6 @@
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
diff --git a/configs/T2080RDB_revD_SPIFLASH_defconfig b/configs/T2080RDB_revD_SPIFLASH_defconfig
index f91e7a8..a03b211 100644
--- a/configs/T2080RDB_revD_SPIFLASH_defconfig
+++ b/configs/T2080RDB_revD_SPIFLASH_defconfig
@@ -80,7 +80,6 @@
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
diff --git a/configs/T2080RDB_revD_defconfig b/configs/T2080RDB_revD_defconfig
index d20b576..569efe9 100644
--- a/configs/T2080RDB_revD_defconfig
+++ b/configs/T2080RDB_revD_defconfig
@@ -63,7 +63,6 @@
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig
index 6d66736..ea71242 100644
--- a/configs/T4240RDB_SDCARD_defconfig
+++ b/configs/T4240RDB_SDCARD_defconfig
@@ -63,7 +63,6 @@
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig
index a3ae720..3a28c2a 100644
--- a/configs/T4240RDB_defconfig
+++ b/configs/T4240RDB_defconfig
@@ -48,7 +48,6 @@
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
diff --git a/configs/UTOO_P66_defconfig b/configs/UTOO_P66_defconfig
index b572807..b021b0a 100644
--- a/configs/UTOO_P66_defconfig
+++ b/configs/UTOO_P66_defconfig
@@ -21,9 +21,6 @@
CONFIG_VIDEO_LCD_TL059WV5C0=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
-CONFIG_SYS_I2C_SOFT=y
-CONFIG_SYS_I2C_SOFT_SPEED=50000
-CONFIG_SYS_I2C_SOFT_SLAVE=0x00
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000
diff --git a/configs/Yones_Toptech_BD1078_defconfig b/configs/Yones_Toptech_BD1078_defconfig
index 1b88cfa..f1ceb8b 100644
--- a/configs/Yones_Toptech_BD1078_defconfig
+++ b/configs/Yones_Toptech_BD1078_defconfig
@@ -6,7 +6,7 @@
CONFIG_DRAM_CLK=408
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_MMC1_CD_PIN="PH2"
-CONFIG_MMC1_PINS="PH"
+CONFIG_MMC1_PINS_PH=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=1
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig
index dab35f9..2ee5bf1 100644
--- a/configs/ae350_rv32_defconfig
+++ b/configs/ae350_rv32_defconfig
@@ -17,7 +17,7 @@
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTP_PREFER_SERVERIP=y
CONFIG_CMD_CACHE=y
-CONFIG_OF_PRIOR_STAGE=y
+CONFIG_OF_BOARD=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig
index 11063e9..7093569 100644
--- a/configs/ae350_rv32_spl_defconfig
+++ b/configs/ae350_rv32_spl_defconfig
@@ -21,7 +21,7 @@
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTP_PREFER_SERVERIP=y
CONFIG_CMD_CACHE=y
-CONFIG_OF_PRIOR_STAGE=y
+CONFIG_OF_BOARD=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTP_SEND_HOSTNAME=y
diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig
index d2d0e31..4b98531 100644
--- a/configs/ae350_rv64_defconfig
+++ b/configs/ae350_rv64_defconfig
@@ -18,7 +18,7 @@
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTP_PREFER_SERVERIP=y
CONFIG_CMD_CACHE=y
-CONFIG_OF_PRIOR_STAGE=y
+CONFIG_OF_BOARD=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig
index 90511ae..3c072aa 100644
--- a/configs/ae350_rv64_spl_defconfig
+++ b/configs/ae350_rv64_spl_defconfig
@@ -22,7 +22,7 @@
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTP_PREFER_SERVERIP=y
CONFIG_CMD_CACHE=y
-CONFIG_OF_PRIOR_STAGE=y
+CONFIG_OF_BOARD=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTP_SEND_HOSTNAME=y
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index 0f938e7..4dc5d0f 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -48,6 +48,7 @@
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_CLK=y
CONFIG_CLK_CDCE9XX=y
+CONFIG_CLK_TI_CTRL=y
CONFIG_DFU_TFTP=y
CONFIG_DFU_MMC=y
CONFIG_DFU_NAND=y
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index 9a038a6..f747cff 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -84,7 +84,6 @@
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=76800000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_MICREL=y
diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index 0a99df4..0533dbd 100644
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -80,7 +80,6 @@
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=76800000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_MICREL=y
diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig
index dbbe18d..7be951b 100644
--- a/configs/am57xx_hs_evm_usb_defconfig
+++ b/configs/am57xx_hs_evm_usb_defconfig
@@ -87,7 +87,6 @@
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=76800000
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig
index 859306d..d157403 100644
--- a/configs/am64x_evm_a53_defconfig
+++ b/configs/am64x_evm_a53_defconfig
@@ -94,7 +94,6 @@
CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_AM654=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_TI_DP83867=y
diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig
index 1659760..5b04f18 100644
--- a/configs/am64x_evm_r5_defconfig
+++ b/configs/am64x_evm_r5_defconfig
@@ -95,7 +95,6 @@
CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_AM654=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PINCTRL=y
diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig
index 52f2539..329f38d 100644
--- a/configs/apalis_imx6_defconfig
+++ b/configs/apalis_imx6_defconfig
@@ -10,6 +10,7 @@
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
CONFIG_MX6Q=y
+CONFIG_MX6_DDRCAL=y
CONFIG_TARGET_APALIS_IMX6=y
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
diff --git a/configs/aristainetos2c_defconfig b/configs/aristainetos2c_defconfig
index 0a4c48f..ad4e835 100644
--- a/configs/aristainetos2c_defconfig
+++ b/configs/aristainetos2c_defconfig
@@ -78,7 +78,6 @@
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_MTD=y
@@ -93,7 +92,6 @@
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
-# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_DM_PMIC_DA9063=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_DA9063=y
diff --git a/configs/aristainetos2ccslb_defconfig b/configs/aristainetos2ccslb_defconfig
index 342e4e9..e4ecd81 100644
--- a/configs/aristainetos2ccslb_defconfig
+++ b/configs/aristainetos2ccslb_defconfig
@@ -78,7 +78,6 @@
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_MTD=y
@@ -93,7 +92,6 @@
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
-# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_DM_PMIC_DA9063=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_DA9063=y
diff --git a/configs/bananapi_m2_berry_defconfig b/configs/bananapi_m2_berry_defconfig
index 8b7f376..2d65d0f 100644
--- a/configs/bananapi_m2_berry_defconfig
+++ b/configs/bananapi_m2_berry_defconfig
@@ -10,7 +10,6 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
-CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000
diff --git a/configs/bcm7260_defconfig b/configs/bcm7260_defconfig
index ec58dd2..3afb909 100644
--- a/configs/bcm7260_defconfig
+++ b/configs/bcm7260_defconfig
@@ -25,7 +25,7 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_PRIOR_STAGE=y
+CONFIG_OF_BOARD=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
diff --git a/configs/bcm7445_defconfig b/configs/bcm7445_defconfig
index d5dd4b7..3726abd 100644
--- a/configs/bcm7445_defconfig
+++ b/configs/bcm7445_defconfig
@@ -26,7 +26,7 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_PRIOR_STAGE=y
+CONFIG_OF_BOARD=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
diff --git a/configs/beaver_defconfig b/configs/beaver_defconfig
index ec45269..df6a56e 100644
--- a/configs/beaver_defconfig
+++ b/configs/beaver_defconfig
@@ -39,7 +39,6 @@
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000
CONFIG_SYS_I2C_TEGRA=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_RTL8169=y
diff --git a/configs/cardhu_defconfig b/configs/cardhu_defconfig
index 6fb808d..47995ea 100644
--- a/configs/cardhu_defconfig
+++ b/configs/cardhu_defconfig
@@ -30,7 +30,6 @@
CONFIG_SYS_MMC_ENV_PART=2
CONFIG_SPL_DM=y
CONFIG_SYS_I2C_TEGRA=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_RTL8169=y
diff --git a/configs/cei-tk1-som_defconfig b/configs/cei-tk1-som_defconfig
index 8923fd0..0acde45 100644
--- a/configs/cei-tk1-som_defconfig
+++ b/configs/cei-tk1-som_defconfig
@@ -39,7 +39,6 @@
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000
CONFIG_SYS_I2C_TEGRA=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_RTL8169=y
diff --git a/configs/cl-som-imx7_defconfig b/configs/cl-som-imx7_defconfig
index 99c4685..0e71364 100644
--- a/configs/cl-som-imx7_defconfig
+++ b/configs/cl-som-imx7_defconfig
@@ -69,7 +69,6 @@
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_EON=y
diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig
index f613107..718ac7c 100644
--- a/configs/clearfog_defconfig
+++ b/configs/clearfog_defconfig
@@ -1,5 +1,4 @@
CONFIG_ARM=y
-CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_MVEBU=y
diff --git a/configs/clearfog_gt_8k_defconfig b/configs/clearfog_gt_8k_defconfig
index 89b978d..082ced9 100644
--- a/configs/clearfog_gt_8k_defconfig
+++ b/configs/clearfog_gt_8k_defconfig
@@ -48,7 +48,6 @@
CONFIG_MISC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_XENON=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig
index c0bc620..1c8bde3 100644
--- a/configs/cm_fx6_defconfig
+++ b/configs/cm_fx6_defconfig
@@ -80,7 +80,6 @@
CONFIG_NAND_MXS=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_EON=y
diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig
index 0af56f4..edb21c8 100644
--- a/configs/colibri-imx6ull_defconfig
+++ b/configs/colibri-imx6ull_defconfig
@@ -96,6 +96,7 @@
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_DM_VIDEO=y
CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MXS=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_VIDEO_BMP_RLE8=y
diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig
index 62a207f..e9c11d7 100644
--- a/configs/colibri_imx6_defconfig
+++ b/configs/colibri_imx6_defconfig
@@ -10,6 +10,7 @@
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
CONFIG_MX6DL=y
+CONFIG_MX6_DDRCAL=y
CONFIG_TARGET_COLIBRI_IMX6=y
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig
index 88d6994..fae8fce 100644
--- a/configs/colibri_imx7_defconfig
+++ b/configs/colibri_imx7_defconfig
@@ -92,6 +92,7 @@
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_DM_VIDEO=y
CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MXS=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_VIDEO_BMP_RLE8=y
diff --git a/configs/controlcenterdc_defconfig b/configs/controlcenterdc_defconfig
index bf0581a..5cfd61f 100644
--- a/configs/controlcenterdc_defconfig
+++ b/configs/controlcenterdc_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
-CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig
index 8c5ac9d..de7879e 100644
--- a/configs/dalmore_defconfig
+++ b/configs/dalmore_defconfig
@@ -38,7 +38,6 @@
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000
CONFIG_SYS_I2C_TEGRA=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
diff --git a/configs/db-88f6720_defconfig b/configs/db-88f6720_defconfig
index 632a22f..0e9299d 100644
--- a/configs/db-88f6720_defconfig
+++ b/configs/db-88f6720_defconfig
@@ -1,5 +1,4 @@
CONFIG_ARM=y
-CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
diff --git a/configs/db-88f6820-amc_defconfig b/configs/db-88f6820-amc_defconfig
index 0bb0d59..fd5e648 100644
--- a/configs/db-88f6820-amc_defconfig
+++ b/configs/db-88f6820-amc_defconfig
@@ -1,5 +1,4 @@
CONFIG_ARM=y
-CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig
index 2e0f938..da18e7d 100644
--- a/configs/db-88f6820-gp_defconfig
+++ b/configs/db-88f6820-gp_defconfig
@@ -1,5 +1,4 @@
CONFIG_ARM=y
-CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig
index eb588b6..b113d0d 100644
--- a/configs/dh_imx6_defconfig
+++ b/configs/dh_imx6_defconfig
@@ -71,7 +71,6 @@
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
@@ -97,6 +96,8 @@
CONFIG_SYSRESET=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_USB=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="dh"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
diff --git a/configs/display5_defconfig b/configs/display5_defconfig
index a49bf33..b02f6f1 100644
--- a/configs/display5_defconfig
+++ b/configs/display5_defconfig
@@ -98,7 +98,6 @@
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig
index 5a2e478..df84ee5 100644
--- a/configs/display5_factory_defconfig
+++ b/configs/display5_factory_defconfig
@@ -102,7 +102,6 @@
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 19f5563..9bc6b79 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -101,7 +101,6 @@
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x140000
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=76800000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_TI_DP83867=y
diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
index d6a752c..9e7b6fe 100644
--- a/configs/dra7xx_hs_evm_defconfig
+++ b/configs/dra7xx_hs_evm_defconfig
@@ -102,7 +102,6 @@
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x140000
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=76800000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_TI_DP83867=y
diff --git a/configs/dra7xx_hs_evm_usb_defconfig b/configs/dra7xx_hs_evm_usb_defconfig
index 09aa073..f1aac20 100644
--- a/configs/dra7xx_hs_evm_usb_defconfig
+++ b/configs/dra7xx_hs_evm_usb_defconfig
@@ -91,7 +91,6 @@
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=76800000
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig
index 7265ac4..057aa53 100644
--- a/configs/evb-px30_defconfig
+++ b/configs/evb-px30_defconfig
@@ -31,7 +31,6 @@
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
# CONFIG_TPL_BANNER_PRINT is not set
-CONFIG_SPL_CRC32=y
CONFIG_SPL_ATF=y
# CONFIG_TPL_FRAMEWORK is not set
# CONFIG_CMD_BOOTD is not set
diff --git a/configs/firefly-px30_defconfig b/configs/firefly-px30_defconfig
index 363fa63..0fb27e9 100644
--- a/configs/firefly-px30_defconfig
+++ b/configs/firefly-px30_defconfig
@@ -32,7 +32,6 @@
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
# CONFIG_TPL_BANNER_PRINT is not set
-CONFIG_SPL_CRC32=y
CONFIG_SPL_ATF=y
# CONFIG_TPL_FRAMEWORK is not set
# CONFIG_CMD_BOOTD is not set
diff --git a/configs/gardena-smart-gateway-at91sam_defconfig b/configs/gardena-smart-gateway-at91sam_defconfig
index 9c1b6b3..3273672 100644
--- a/configs/gardena-smart-gateway-at91sam_defconfig
+++ b/configs/gardena-smart-gateway-at91sam_defconfig
@@ -86,13 +86,13 @@
CONFIG_MTD=y
CONFIG_NAND_ATMEL=y
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
-CONFIG_MTD_UBI_FASTMAP=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
+CONFIG_MTD_UBI_FASTMAP=y
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
diff --git a/configs/ge_b1x5v2_defconfig b/configs/ge_b1x5v2_defconfig
index ef32a4b..4642ced 100644
--- a/configs/ge_b1x5v2_defconfig
+++ b/configs/ge_b1x5v2_defconfig
@@ -86,7 +86,6 @@
CONFIG_LED_GPIO=y
CONFIG_FSL_USDHC=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
@@ -100,7 +99,6 @@
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
-# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig
index 690fa11..29df308 100644
--- a/configs/ge_bx50v3_defconfig
+++ b/configs/ge_bx50v3_defconfig
@@ -59,7 +59,6 @@
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig
index 000bdb5..9763fc1 100644
--- a/configs/gwventana_emmc_defconfig
+++ b/configs/gwventana_emmc_defconfig
@@ -44,7 +44,6 @@
CONFIG_SPL_I2C=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_POWER=y
-CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Ventana > "
CONFIG_CMD_BOOTZ=y
@@ -54,12 +53,15 @@
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_WDT=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
@@ -113,12 +115,19 @@
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MXC_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_LAN75XX=y
+CONFIG_USB_ETHER_LAN78XX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Gateworks"
@@ -137,4 +146,8 @@
CONFIG_SYS_WHITE_ON_BLACK=y
# CONFIG_PANEL is not set
CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
+CONFIG_IMX_WATCHDOG=y
CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig
index 87851f3..5d9db22 100644
--- a/configs/gwventana_gw5904_defconfig
+++ b/configs/gwventana_gw5904_defconfig
@@ -44,7 +44,6 @@
CONFIG_SPL_I2C=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_POWER=y
-CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Ventana > "
CONFIG_CMD_BOOTZ=y
@@ -54,12 +53,15 @@
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_WDT=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
@@ -117,12 +119,19 @@
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MXC_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_LAN75XX=y
+CONFIG_USB_ETHER_LAN78XX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Gateworks"
@@ -141,4 +150,8 @@
CONFIG_SYS_WHITE_ON_BLACK=y
# CONFIG_PANEL is not set
CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
+CONFIG_IMX_WATCHDOG=y
CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig
index 8ff8ab4..8e30eea 100644
--- a/configs/gwventana_nand_defconfig
+++ b/configs/gwventana_nand_defconfig
@@ -45,7 +45,6 @@
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_POWER=y
-CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Ventana > "
CONFIG_CMD_BOOTZ=y
@@ -57,12 +56,15 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_PART=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_WDT=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
@@ -121,12 +123,19 @@
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MXC_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_LAN75XX=y
+CONFIG_USB_ETHER_LAN78XX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Gateworks"
@@ -145,4 +154,8 @@
CONFIG_SYS_WHITE_ON_BLACK=y
# CONFIG_PANEL is not set
CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
+CONFIG_IMX_WATCHDOG=y
CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/helios4_defconfig b/configs/helios4_defconfig
index c121a3c..2071aa9 100644
--- a/configs/helios4_defconfig
+++ b/configs/helios4_defconfig
@@ -1,5 +1,4 @@
CONFIG_ARM=y
-CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_MVEBU=y
diff --git a/configs/imx8mm-cl-iot-gate-optee_defconfig b/configs/imx8mm-cl-iot-gate-optee_defconfig
new file mode 100644
index 0000000..d987328
--- /dev/null
+++ b/configs/imx8mm-cl-iot-gate-optee_defconfig
@@ -0,0 +1,148 @@
+CONFIG_ARM=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x4400
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-cl-iot-gate-optee"
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_IMX8MM_CL_IOT_GATE_OPTEE=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_IMX_CONFIG="board/compulab/imx8mm-cl-iot-gate/imximage-8mm-lpddr4.cfg"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_CMD_BOOTEFI_SELFTEST=y
+CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_SHA1SUM=y
+CONFIG_CMD_BIND=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_TPM=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MM=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x44000000
+CONFIG_FASTBOOT_BUF_SIZE=0x5000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=2
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_KEYBOARD=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_ESDHC_IMX=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PCI_ENDPOINT=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_BD71837=y
+CONFIG_SPL_DM_PMIC_BD71837=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_BD71837=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_ABX80X=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_DM_THERMAL=y
+CONFIG_TPM2_TIS_SPI=y
+CONFIG_TPM2_FTPM_TEE=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_TPM=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
+CONFIG_EFI_SECURE_BOOT=y
diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig
index cb37442..70bf747 100644
--- a/configs/imx8mn_beacon_2g_defconfig
+++ b/configs/imx8mn_beacon_2g_defconfig
@@ -89,7 +89,6 @@
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig
index 59cae55..d2ff02f 100644
--- a/configs/imx8mn_beacon_defconfig
+++ b/configs/imx8mn_beacon_defconfig
@@ -91,7 +91,6 @@
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/imx8ulp_evk_defconfig b/configs/imx8ulp_evk_defconfig
index f156100..23afbbb 100644
--- a/configs/imx8ulp_evk_defconfig
+++ b/configs/imx8ulp_evk_defconfig
@@ -52,7 +52,6 @@
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_FSL_USDHC=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_PHYLIB=y
diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig
index 94363cf..92c398e 100644
--- a/configs/imxrt1050-evk_defconfig
+++ b/configs/imxrt1050-evk_defconfig
@@ -74,6 +74,7 @@
CONFIG_DM_VIDEO=y
CONFIG_BACKLIGHT_GPIO=y
CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MXS=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_VIDEO_BMP_RLE8=y
diff --git a/configs/iot2050_defconfig b/configs/iot2050_defconfig
index 72ee5c8..84e387a 100644
--- a/configs/iot2050_defconfig
+++ b/configs/iot2050_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_K3=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -10,15 +11,16 @@
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x680000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am6528-iot2050-basic"
CONFIG_SPL_TEXT_BASE=0x80080000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_ENV_OFFSET_REDUND=0x6a0000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig
index 50e85be..33b850f 100644
--- a/configs/jetson-tk1_defconfig
+++ b/configs/jetson-tk1_defconfig
@@ -39,7 +39,6 @@
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000
CONFIG_SYS_I2C_TEGRA=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_RTL8169=y
diff --git a/configs/kontron-sl-mx6ul_defconfig b/configs/kontron-sl-mx6ul_defconfig
new file mode 100644
index 0000000..28b5d0d
--- /dev/null
+++ b/configs/kontron-sl-mx6ul_defconfig
@@ -0,0 +1,109 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x90000000
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0xF0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_MX6UL=y
+CONFIG_TARGET_KONTRON_MX6UL=y
+CONFIG_SYS_MALLOC_LEN=0x4000000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ul-kontron-n631x-s"
+CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_BOOTCOUNT_BOOTLIMIT=3
+CONFIG_SPL=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_IMX_CONFIG="arch/arm/mach-imx/spl_sd.cfg"
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_TYPES=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_RAW_IMAGE_SUPPORT=y
+CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y
+CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8A
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400
+CONFIG_SPL_USB_HOST=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_SDP=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FS_UUID=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nor0=spi1.0,spi-nand0=spi4.0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=spi1.0:128k(spl),832k(u-boot),64k(env);spi4.0:-(UBI)"
+CONFIG_CMD_UBI=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIST="imx6ul-kontron-n631x-s imx6ull-kontron-n641x-s"
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USE_ENV_SPI_BUS=y
+CONFIG_ENV_SPI_BUS=2
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTCOUNT_ENV=y
+CONFIG_DM_I2C=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=10000000
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_CONS_INDEX=4
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_MXC_SPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/kontron-sl-mx8mm_defconfig b/configs/kontron-sl-mx8mm_defconfig
new file mode 100644
index 0000000..0289781
--- /dev/null
+++ b/configs/kontron-sl-mx8mm_defconfig
@@ -0,0 +1,142 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x1f0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x4000000
+CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-kontron-n801x-s"
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_KONTRON_MX8MM=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_BOOTCOUNT_BOOTLIMIT=3
+CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_IMX_CONFIG="board/kontron/sl-mx8mm/imximage.cfg"
+CONFIG_BOARD_TYPES=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+# CONFIG_SPL_FIT_IMAGE_TINY is not set
+CONFIG_SPL_I2C=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x58000
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SPL_ATF=y
+CONFIG_CMD_NVEDIT_EFI=y
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNZIP is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIST="imx8mm-kontron-n801x-s imx8mm-kontron-n801x-s-lvds"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USE_ENV_SPI_BUS=y
+CONFIG_ENV_SPI_BUS=0
+CONFIG_USE_ENV_SPI_MAX_HZ=y
+CONFIG_ENV_SPI_MAX_HZ=80000000
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTCOUNT_ENV=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MM=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_DFU_SF=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_ESDHC_IMX=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=80000000
+CONFIG_SPI_FLASH_MACRONIX=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MSCC=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PCA9450=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_RV8803=y
+CONFIG_CONS_INDEX=2
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+# CONFIG_WATCHDOG_AUTOSTART is not set
+CONFIG_IMX_WATCHDOG=y
+# CONFIG_HEXDUMP is not set
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_IGNORE_OSINDICATIONS=y
+CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
diff --git a/configs/kp_imx53_defconfig b/configs/kp_imx53_defconfig
index b8f6d8a..b611cee 100644
--- a/configs/kp_imx53_defconfig
+++ b/configs/kp_imx53_defconfig
@@ -49,7 +49,6 @@
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX5=y
-# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_DM_PMIC_MC34708=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
diff --git a/configs/kp_imx6q_tpc_defconfig b/configs/kp_imx6q_tpc_defconfig
index 85fdfad..bcaa82a 100644
--- a/configs/kp_imx6q_tpc_defconfig
+++ b/configs/kp_imx6q_tpc_defconfig
@@ -76,5 +76,7 @@
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
# CONFIG_SPL_DM_USB is not set
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
CONFIG_IMX_WATCHDOG=y
diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig
index e214cf5..7f62811 100644
--- a/configs/lion-rk3368_defconfig
+++ b/configs/lion-rk3368_defconfig
@@ -96,7 +96,6 @@
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC2=y
-CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_SPL_TINY_MEMSET=y
diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig
index 0903650..376bcf5 100644
--- a/configs/ls1012aqds_qspi_defconfig
+++ b/configs/ls1012aqds_qspi_defconfig
@@ -63,7 +63,6 @@
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
index 02eecf0..939ca2c 100644
--- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
@@ -52,7 +52,6 @@
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig
index fad0c1c..8ded692 100644
--- a/configs/ls1012aqds_tfa_defconfig
+++ b/configs/ls1012aqds_tfa_defconfig
@@ -64,7 +64,6 @@
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig
index 5500d8e..2c065c6 100644
--- a/configs/m53menlo_defconfig
+++ b/configs/m53menlo_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_MX5=y
CONFIG_SYS_TEXT_BASE=0x71000000
CONFIG_SPL_GPIO=y
@@ -22,7 +23,6 @@
CONFIG_SPL=y
CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
CONFIG_ENV_OFFSET_REDUND=0x180000
-# CONFIG_CMD_BMODE is not set
CONFIG_SYS_LOAD_ADDR=0x70800000
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig
index 8e0aa04..33be803 100644
--- a/configs/marsboard_defconfig
+++ b/configs/marsboard_defconfig
@@ -38,7 +38,6 @@
CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
diff --git a/configs/mccmon6_nor_defconfig b/configs/mccmon6_nor_defconfig
index 9fabc29..c8b8df3 100644
--- a/configs/mccmon6_nor_defconfig
+++ b/configs/mccmon6_nor_defconfig
@@ -62,7 +62,6 @@
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
@@ -74,7 +73,6 @@
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
-# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PFUZE100=y
diff --git a/configs/mccmon6_sd_defconfig b/configs/mccmon6_sd_defconfig
index f9d586a..bf32c71 100644
--- a/configs/mccmon6_sd_defconfig
+++ b/configs/mccmon6_sd_defconfig
@@ -60,7 +60,6 @@
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
@@ -72,7 +71,6 @@
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
-# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PFUZE100=y
diff --git a/configs/mvebu_crb_cn9130_defconfig b/configs/mvebu_crb_cn9130_defconfig
index f0f50a9..334d7f2 100644
--- a/configs/mvebu_crb_cn9130_defconfig
+++ b/configs/mvebu_crb_cn9130_defconfig
@@ -51,7 +51,6 @@
CONFIG_MMC_SDHCI_XENON=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig
index d401f47..931ca9c 100644
--- a/configs/mvebu_db-88f3720_defconfig
+++ b/configs/mvebu_db-88f3720_defconfig
@@ -45,12 +45,12 @@
CONFIG_CLK_MVEBU=y
# CONFIG_MVEBU_GPIO is not set
CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MV=y
CONFIG_MISC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_XENON=y
CONFIG_MTD=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/mvebu_db_armada8k_defconfig b/configs/mvebu_db_armada8k_defconfig
index 4ad6d4d..d9a5759 100644
--- a/configs/mvebu_db_armada8k_defconfig
+++ b/configs/mvebu_db_armada8k_defconfig
@@ -44,7 +44,6 @@
CONFIG_MISC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_XENON=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/mvebu_db_cn9130_defconfig b/configs/mvebu_db_cn9130_defconfig
index e0470ce..c8dffe0 100644
--- a/configs/mvebu_db_cn9130_defconfig
+++ b/configs/mvebu_db_cn9130_defconfig
@@ -56,7 +56,6 @@
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_PXA3XX=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig
index 01cf24a..3a69954 100644
--- a/configs/mvebu_espressobin-88f3720_defconfig
+++ b/configs/mvebu_espressobin-88f3720_defconfig
@@ -54,13 +54,13 @@
CONFIG_CLK=y
CONFIG_CLK_MVEBU=y
CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MV=y
CONFIG_MISC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_XENON=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_ISSI=y
diff --git a/configs/mvebu_mcbin-88f8040_defconfig b/configs/mvebu_mcbin-88f8040_defconfig
index 44f16b6..61cc260 100644
--- a/configs/mvebu_mcbin-88f8040_defconfig
+++ b/configs/mvebu_mcbin-88f8040_defconfig
@@ -48,7 +48,6 @@
CONFIG_MISC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_XENON=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/mvebu_puzzle-m801-88f8040_defconfig b/configs/mvebu_puzzle-m801-88f8040_defconfig
index c521f2c..da73dd1 100644
--- a/configs/mvebu_puzzle-m801-88f8040_defconfig
+++ b/configs/mvebu_puzzle-m801-88f8040_defconfig
@@ -54,7 +54,6 @@
CONFIG_MISC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_XENON=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_PHY_MARVELL=y
diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig
index 081707f..5f39df8 100644
--- a/configs/mx53ppd_defconfig
+++ b/configs/mx53ppd_defconfig
@@ -70,6 +70,10 @@
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_USB=y
CONFIG_USB_EHCI_MX5=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_DM_VIDEO=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_VIDEO_IPUV3=y
diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig
index 419626a..da1f030 100644
--- a/configs/mx6qsabrelite_defconfig
+++ b/configs/mx6qsabrelite_defconfig
@@ -58,7 +58,6 @@
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig
index 5819fe6..5fd0dee 100644
--- a/configs/mx6sabreauto_defconfig
+++ b/configs/mx6sabreauto_defconfig
@@ -80,7 +80,6 @@
CONFIG_NAND_MXS=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig
index 5216bca..676e8a9 100644
--- a/configs/mx6sabresd_defconfig
+++ b/configs/mx6sabresd_defconfig
@@ -87,7 +87,6 @@
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig
index c041cb7..a75a632 100644
--- a/configs/mx6slevk_defconfig
+++ b/configs/mx6slevk_defconfig
@@ -42,7 +42,6 @@
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
diff --git a/configs/mx6slevk_spinor_defconfig b/configs/mx6slevk_spinor_defconfig
index 1e6aae6..94692c2 100644
--- a/configs/mx6slevk_spinor_defconfig
+++ b/configs/mx6slevk_spinor_defconfig
@@ -42,7 +42,6 @@
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig
index 7c445e6..ce1d518 100644
--- a/configs/mx6slevk_spl_defconfig
+++ b/configs/mx6slevk_spl_defconfig
@@ -55,7 +55,6 @@
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig
index 957dc45..5bb481b 100644
--- a/configs/mx6sxsabreauto_defconfig
+++ b/configs/mx6sxsabreauto_defconfig
@@ -44,7 +44,6 @@
CONFIG_NAND_MXS=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig
index b80dc94..751aa53 100644
--- a/configs/mx6sxsabresd_defconfig
+++ b/configs/mx6sxsabresd_defconfig
@@ -45,7 +45,6 @@
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig
index c9760df..dd3847e 100644
--- a/configs/mx6ul_14x14_evk_defconfig
+++ b/configs/mx6ul_14x14_evk_defconfig
@@ -64,7 +64,6 @@
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
@@ -94,6 +93,7 @@
CONFIG_CI_UDC=y
CONFIG_DM_VIDEO=y
CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MXS=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_VIDEO_BMP_RLE8=y
diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig
index a373e20..65bc15c 100644
--- a/configs/mx6ul_9x9_evk_defconfig
+++ b/configs/mx6ul_9x9_evk_defconfig
@@ -57,7 +57,6 @@
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
@@ -84,6 +83,7 @@
CONFIG_USB_STORAGE=y
CONFIG_DM_VIDEO=y
CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MXS=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_VIDEO_BMP_RLE8=y
diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig
index 8ecb496..1b70100 100644
--- a/configs/mx6ull_14x14_evk_defconfig
+++ b/configs/mx6ull_14x14_evk_defconfig
@@ -40,7 +40,6 @@
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig b/configs/mx6ull_14x14_evk_plugin_defconfig
index 64719b1..aaac371 100644
--- a/configs/mx6ull_14x14_evk_plugin_defconfig
+++ b/configs/mx6ull_14x14_evk_plugin_defconfig
@@ -41,7 +41,6 @@
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
diff --git a/configs/mx6ulz_14x14_evk_defconfig b/configs/mx6ulz_14x14_evk_defconfig
index e233931..28bc8db 100644
--- a/configs/mx6ulz_14x14_evk_defconfig
+++ b/configs/mx6ulz_14x14_evk_defconfig
@@ -39,7 +39,6 @@
CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PINCTRL=y
diff --git a/configs/mx7dsabresd_qspi_defconfig b/configs/mx7dsabresd_qspi_defconfig
index 0da33c4..c5613b3 100644
--- a/configs/mx7dsabresd_qspi_defconfig
+++ b/configs/mx7dsabresd_qspi_defconfig
@@ -52,7 +52,6 @@
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_MACRONIX=y
diff --git a/configs/mx7ulp_com_defconfig b/configs/mx7ulp_com_defconfig
index 6e6b821..bab5d6d 100644
--- a/configs/mx7ulp_com_defconfig
+++ b/configs/mx7ulp_com_defconfig
@@ -9,6 +9,8 @@
CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-com"
CONFIG_LDO_ENABLED_MODE=y
CONFIG_TARGET_MX7ULP_COM=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="if run loadimage; then run mmcboot; fi"
CONFIG_SYS_LOAD_ADDR=0x60800000
CONFIG_DEFAULT_FDT_FILE="imx7ulp-com"
CONFIG_BOARD_EARLY_INIT_F=y
@@ -34,7 +36,6 @@
CONFIG_SYS_I2C_IMX_LPI2C=y
CONFIG_FSL_USDHC=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_PINCTRL=y
diff --git a/configs/myir_mys_6ulx_defconfig b/configs/myir_mys_6ulx_defconfig
index 022f9ff..5f140a5 100644
--- a/configs/myir_mys_6ulx_defconfig
+++ b/configs/myir_mys_6ulx_defconfig
@@ -60,7 +60,6 @@
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
-# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_MXC_UART=y
diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig
index d86faf1..f31668c 100644
--- a/configs/nanopc-t4-rk3399_defconfig
+++ b/configs/nanopc-t4-rk3399_defconfig
@@ -53,7 +53,6 @@
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC3=y
-CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/nanopi_r1s_h5_defconfig b/configs/nanopi_r1s_h5_defconfig
new file mode 100644
index 0000000..27cf172
--- /dev/null
+++ b/configs/nanopi_r1s_h5_defconfig
@@ -0,0 +1,14 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-r1s-h5"
+CONFIG_SPL=y
+CONFIG_MACH_SUN50I_H5=y
+CONFIG_DRAM_CLK=672
+CONFIG_DRAM_ZQ=3881977
+# CONFIG_DRAM_ODT_EN is not set
+CONFIG_MACPWR="PD6"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig
index a56cb2c..f0d6dd1 100644
--- a/configs/nitrogen6dl2g_defconfig
+++ b/configs/nitrogen6dl2g_defconfig
@@ -61,7 +61,6 @@
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig
index 68d286c..54e5a4d 100644
--- a/configs/nitrogen6dl_defconfig
+++ b/configs/nitrogen6dl_defconfig
@@ -61,7 +61,6 @@
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig
index cbe9ced..c19284c 100644
--- a/configs/nitrogen6q2g_defconfig
+++ b/configs/nitrogen6q2g_defconfig
@@ -63,7 +63,6 @@
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig
index 95e60f9..ef23d61 100644
--- a/configs/nitrogen6q_defconfig
+++ b/configs/nitrogen6q_defconfig
@@ -63,7 +63,6 @@
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig
index 43c0787..31fb783 100644
--- a/configs/nitrogen6s1g_defconfig
+++ b/configs/nitrogen6s1g_defconfig
@@ -61,7 +61,6 @@
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig
index a8428dc..78d4b7b 100644
--- a/configs/nitrogen6s_defconfig
+++ b/configs/nitrogen6s_defconfig
@@ -61,7 +61,6 @@
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig
index 9d7d54e..daf0114 100644
--- a/configs/nyan-big_defconfig
+++ b/configs/nyan-big_defconfig
@@ -59,7 +59,6 @@
CONFIG_CROS_EC_KEYB=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_PMIC=y
diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig
index df64307..70ebcd3 100644
--- a/configs/odroid-go2_defconfig
+++ b/configs/odroid-go2_defconfig
@@ -35,7 +35,6 @@
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
# CONFIG_TPL_BANNER_PRINT is not set
-CONFIG_SPL_CRC32=y
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_ATF=y
@@ -98,7 +97,6 @@
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_SOUND=y
CONFIG_SYSRESET=y
-CONFIG_OPTEE_LIB=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
@@ -112,3 +110,4 @@
CONFIG_TPL_TINY_MEMSET=y
CONFIG_LZO=y
CONFIG_ERRNO_STR=y
+CONFIG_OPTEE_LIB=y
diff --git a/configs/odroid-hc4_defconfig b/configs/odroid-hc4_defconfig
index 917d95c..2fe761e 100644
--- a/configs/odroid-hc4_defconfig
+++ b/configs/odroid-hc4_defconfig
@@ -11,8 +11,8 @@
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" odroid-hc4"
CONFIG_DEBUG_UART=y
-CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_AHCI=y
+CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MISC_INIT_R=y
diff --git a/configs/omap35_logic_defconfig b/configs/omap35_logic_defconfig
index 9d8ac94..db38d78 100644
--- a/configs/omap35_logic_defconfig
+++ b/configs/omap35_logic_defconfig
@@ -12,6 +12,7 @@
CONFIG_TARGET_OMAP3_LOGIC=y
# CONFIG_SPL_OMAP3_ID_NAND is not set
CONFIG_SPL=y
+CONFIG_LTO=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ANDROID_BOOT_IMAGE=y
# CONFIG_USE_BOOTCOMMAND is not set
diff --git a/configs/omap35_logic_somlv_defconfig b/configs/omap35_logic_somlv_defconfig
index ee0c58a..9abfe95 100644
--- a/configs/omap35_logic_somlv_defconfig
+++ b/configs/omap35_logic_somlv_defconfig
@@ -12,6 +12,7 @@
CONFIG_TARGET_OMAP3_LOGIC=y
# CONFIG_SPL_OMAP3_ID_NAND is not set
CONFIG_SPL=y
+CONFIG_LTO=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ANDROID_BOOT_IMAGE=y
# CONFIG_USE_BOOTCOMMAND is not set
diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig
index ece92fe..fb1ee3a 100644
--- a/configs/omap3_logic_somlv_defconfig
+++ b/configs/omap3_logic_somlv_defconfig
@@ -12,6 +12,7 @@
CONFIG_TARGET_OMAP3_LOGIC=y
# CONFIG_SPL_OMAP3_ID_NAND is not set
CONFIG_SPL=y
+CONFIG_LTO=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ANDROID_BOOT_IMAGE=y
# CONFIG_USE_BOOTCOMMAND is not set
diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig
index 32adb5d..0bc1c6c 100644
--- a/configs/opos6uldev_defconfig
+++ b/configs/opos6uldev_defconfig
@@ -106,6 +106,7 @@
# CONFIG_VIDEO_BPP8 is not set
# CONFIG_VIDEO_BPP32 is not set
CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MXS=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_SPLASH_SOURCE=y
diff --git a/configs/orangepi_zero2_defconfig b/configs/orangepi_zero2_defconfig
index edb765f..22563c8 100644
--- a/configs/orangepi_zero2_defconfig
+++ b/configs/orangepi_zero2_defconfig
@@ -11,7 +11,6 @@
CONFIG_R_I2C_ENABLE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
-CONFIG_SYS_I2C_LEGACY=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig
index 43d9095..940c496 100644
--- a/configs/p2371-0000_defconfig
+++ b/configs/p2371-0000_defconfig
@@ -33,7 +33,6 @@
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000
CONFIG_SYS_I2C_TEGRA=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig
index c9498b3..27a19d2 100644
--- a/configs/p2371-2180_defconfig
+++ b/configs/p2371-2180_defconfig
@@ -37,7 +37,6 @@
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000
CONFIG_SYS_I2C_TEGRA=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_RTL8169=y
diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig
index 27cc68e..1251039 100644
--- a/configs/p2571_defconfig
+++ b/configs/p2571_defconfig
@@ -34,7 +34,6 @@
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000
CONFIG_SYS_I2C_TEGRA=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
diff --git a/configs/p3450-0000_defconfig b/configs/p3450-0000_defconfig
index 0587ca9..dc487ff 100644
--- a/configs/p3450-0000_defconfig
+++ b/configs/p3450-0000_defconfig
@@ -38,7 +38,6 @@
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000
CONFIG_SYS_I2C_TEGRA=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_RTL8169=y
diff --git a/configs/parrot_r16_defconfig b/configs/parrot_r16_defconfig
index de340e2..d56c450 100644
--- a/configs/parrot_r16_defconfig
+++ b/configs/parrot_r16_defconfig
@@ -6,7 +6,6 @@
CONFIG_DRAM_CLK=600
CONFIG_DRAM_ZQ=15291
CONFIG_MMC0_CD_PIN="PD14"
-CONFIG_MMC2_PINS="PC"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB0_ID_DET="PD10"
CONFIG_USB1_VBUS_PIN="PD12"
diff --git a/configs/pcm058_defconfig b/configs/pcm058_defconfig
index aefd91a..c290875 100644
--- a/configs/pcm058_defconfig
+++ b/configs/pcm058_defconfig
@@ -70,7 +70,6 @@
CONFIG_NAND_MXS_DT=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig
index 173ed4e..1458441 100644
--- a/configs/peach-pi_defconfig
+++ b/configs/peach-pi_defconfig
@@ -53,7 +53,6 @@
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_S5P=y
CONFIG_MTD=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_WINBOND=y
diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig
index af4865f..db18bec 100644
--- a/configs/peach-pit_defconfig
+++ b/configs/peach-pit_defconfig
@@ -52,7 +52,6 @@
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_S5P=y
CONFIG_MTD=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_WINBOND=y
diff --git a/configs/phycore_pcl063_defconfig b/configs/phycore_pcl063_defconfig
index 03d3e6f..0897aee 100644
--- a/configs/phycore_pcl063_defconfig
+++ b/configs/phycore_pcl063_defconfig
@@ -55,7 +55,6 @@
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
-# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_MXC_UART=y
diff --git a/configs/phycore_pcl063_ull_defconfig b/configs/phycore_pcl063_ull_defconfig
index 6524349..d8ce8d2 100644
--- a/configs/phycore_pcl063_ull_defconfig
+++ b/configs/phycore_pcl063_ull_defconfig
@@ -44,7 +44,6 @@
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
-# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_MXC_UART=y
diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig
index d7c3821..e55c0b7 100644
--- a/configs/pico-imx6ul_defconfig
+++ b/configs/pico-imx6ul_defconfig
@@ -78,5 +78,6 @@
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_MXS=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
diff --git a/configs/pico-imx7d_bl33_defconfig b/configs/pico-imx7d_bl33_defconfig
index df81717..2da6e9c 100644
--- a/configs/pico-imx7d_bl33_defconfig
+++ b/configs/pico-imx7d_bl33_defconfig
@@ -82,6 +82,7 @@
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_DM_VIDEO=y
CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MXS=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_VIDEO_BMP_RLE8=y
diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig
index 7d53562..34c0648 100644
--- a/configs/pico-imx7d_defconfig
+++ b/configs/pico-imx7d_defconfig
@@ -86,6 +86,7 @@
CONFIG_CI_UDC=y
CONFIG_DM_VIDEO=y
CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MXS=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_VIDEO_BMP_RLE8=y
diff --git a/configs/pinecube_defconfig b/configs/pinecube_defconfig
index 742da36..0c71d59 100644
--- a/configs/pinecube_defconfig
+++ b/configs/pinecube_defconfig
@@ -8,7 +8,6 @@
CONFIG_DRAM_ODT_EN=y
CONFIG_I2C0_ENABLE=y
CONFIG_SPL_I2C=y
-CONFIG_SYS_I2C_LEGACY=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/pinephone_defconfig b/configs/pinephone_defconfig
index 64e13d3..9d39204 100644
--- a/configs/pinephone_defconfig
+++ b/configs/pinephone_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pinephone-1.2"
+CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MACH_SUN50I=y
CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
@@ -10,3 +11,8 @@
CONFIG_PINEPHONE_DT_SELECTION=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_OF_LIST="sun50i-a64-pinephone-1.1 sun50i-a64-pinephone-1.2"
+CONFIG_LED_STATUS=y
+CONFIG_LED_STATUS_GPIO=y
+CONFIG_LED_STATUS0=y
+CONFIG_LED_STATUS_BIT=114
+CONFIG_LED_STATUS_STATE=2
diff --git a/configs/pinetab_defconfig b/configs/pinetab_defconfig
new file mode 100644
index 0000000..0cc2414
--- /dev/null
+++ b/configs/pinetab_defconfig
@@ -0,0 +1,10 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pinetab"
+CONFIG_SPL=y
+CONFIG_MACH_SUN50I=y
+CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
+CONFIG_DRAM_CLK=552
+CONFIG_DRAM_ZQ=3881949
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/px30-core-ctouch2-px30_defconfig b/configs/px30-core-ctouch2-px30_defconfig
index 9146191..0bba43c 100644
--- a/configs/px30-core-ctouch2-px30_defconfig
+++ b/configs/px30-core-ctouch2-px30_defconfig
@@ -32,7 +32,6 @@
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
# CONFIG_TPL_BANNER_PRINT is not set
-CONFIG_SPL_CRC32=y
CONFIG_SPL_ATF=y
# CONFIG_TPL_FRAMEWORK is not set
# CONFIG_CMD_BOOTD is not set
diff --git a/configs/px30-core-edimm2.2-px30_defconfig b/configs/px30-core-edimm2.2-px30_defconfig
index 46077fa..f8db3d1 100644
--- a/configs/px30-core-edimm2.2-px30_defconfig
+++ b/configs/px30-core-edimm2.2-px30_defconfig
@@ -32,7 +32,6 @@
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
# CONFIG_TPL_BANNER_PRINT is not set
-CONFIG_SPL_CRC32=y
CONFIG_SPL_ATF=y
# CONFIG_TPL_FRAMEWORK is not set
# CONFIG_CMD_BOOTD is not set
diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig
index f49d49e..e77e3ed 100644
--- a/configs/qemu-riscv32_defconfig
+++ b/configs/qemu-riscv32_defconfig
@@ -11,6 +11,6 @@
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_NVEDIT_EFI=y
# CONFIG_CMD_MII is not set
-CONFIG_OF_PRIOR_STAGE=y
+CONFIG_OF_BOARD=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig
index a009f62..0378741 100644
--- a/configs/qemu-riscv32_smode_defconfig
+++ b/configs/qemu-riscv32_smode_defconfig
@@ -12,7 +12,7 @@
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_NVEDIT_EFI=y
# CONFIG_CMD_MII is not set
-CONFIG_OF_PRIOR_STAGE=y
+CONFIG_OF_BOARD=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
CONFIG_SYSRESET_SBI=y
diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig
index aac6f389..b0e655b 100644
--- a/configs/qemu-riscv32_spl_defconfig
+++ b/configs/qemu-riscv32_spl_defconfig
@@ -14,7 +14,7 @@
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_CMD_SBI=y
# CONFIG_CMD_MII is not set
-CONFIG_OF_PRIOR_STAGE=y
+CONFIG_OF_BOARD=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
CONFIG_SYSRESET_SBI=y
diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig
index 506ac43..1f8dc2d 100644
--- a/configs/qemu-riscv64_defconfig
+++ b/configs/qemu-riscv64_defconfig
@@ -12,6 +12,6 @@
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_NVEDIT_EFI=y
# CONFIG_CMD_MII is not set
-CONFIG_OF_PRIOR_STAGE=y
+CONFIG_OF_BOARD=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig
index db2f21d..bdcec1f 100644
--- a/configs/qemu-riscv64_smode_defconfig
+++ b/configs/qemu-riscv64_smode_defconfig
@@ -15,7 +15,7 @@
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_NVEDIT_EFI=y
# CONFIG_CMD_MII is not set
-CONFIG_OF_PRIOR_STAGE=y
+CONFIG_OF_BOARD=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
CONFIG_SYSRESET_SBI=y
diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig
index cf33870..9745c1a 100644
--- a/configs/qemu-riscv64_spl_defconfig
+++ b/configs/qemu-riscv64_spl_defconfig
@@ -15,7 +15,7 @@
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_CMD_SBI=y
# CONFIG_CMD_MII is not set
-CONFIG_OF_PRIOR_STAGE=y
+CONFIG_OF_BOARD=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
CONFIG_SYSRESET_SBI=y
diff --git a/configs/radxa-zero_defconfig b/configs/radxa-zero_defconfig
index 91457f5..a9afb64 100644
--- a/configs/radxa-zero_defconfig
+++ b/configs/radxa-zero_defconfig
@@ -22,10 +22,10 @@
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig
index 1fb7084..5fdbc56 100644
--- a/configs/riotboard_defconfig
+++ b/configs/riotboard_defconfig
@@ -50,7 +50,6 @@
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig
index 199624f..ca2fb9e 100644
--- a/configs/roc-pc-mezzanine-rk3399_defconfig
+++ b/configs/roc-pc-mezzanine-rk3399_defconfig
@@ -71,7 +71,6 @@
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
-CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig
index bc124c8..de35a62 100644
--- a/configs/roc-pc-rk3399_defconfig
+++ b/configs/roc-pc-rk3399_defconfig
@@ -68,7 +68,6 @@
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
-CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/rock-pi-n10-rk3399pro_defconfig b/configs/rock-pi-n10-rk3399pro_defconfig
index 0b89ae9..bd8b120 100644
--- a/configs/rock-pi-n10-rk3399pro_defconfig
+++ b/configs/rock-pi-n10-rk3399pro_defconfig
@@ -62,7 +62,6 @@
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
-CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_KEYBOARD=y
# CONFIG_USB_KEYBOARD_FN_KEYS is not set
CONFIG_USB_GADGET=y
diff --git a/configs/sama5d2_icp_qspiflash_defconfig b/configs/sama5d2_icp_qspiflash_defconfig
index bf442bf..e88a47a 100644
--- a/configs/sama5d2_icp_qspiflash_defconfig
+++ b/configs/sama5d2_icp_qspiflash_defconfig
@@ -14,9 +14,9 @@
CONFIG_DEBUG_UART_CLOCK=83000000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_SYS_BOOT_GET_CMDLINE=y
CONFIG_SYS_BOOT_GET_KBD=y
+CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2"
CONFIG_QSPI_BOOT=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index f1067b9..9a462cb 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -56,6 +56,7 @@
CONFIG_CMD_MEM_SEARCH=y
CONFIG_CMD_MX_CYCLIC=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_UNZIP=y
CONFIG_CMD_BIND=y
CONFIG_CMD_DEMO=y
CONFIG_CMD_GPIO=y
@@ -268,6 +269,10 @@
CONFIG_USB=y
CONFIG_USB_EMUL=y
CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_ETHER=y
+CONFIG_USB_ETH_CDC=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_COPY=y
CONFIG_CONSOLE_ROTATION=y
diff --git a/configs/seeed_npi_imx6ull_defconfig b/configs/seeed_npi_imx6ull_defconfig
index caff2a6..97158c6 100644
--- a/configs/seeed_npi_imx6ull_defconfig
+++ b/configs/seeed_npi_imx6ull_defconfig
@@ -62,7 +62,6 @@
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
-# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig
index 5564655..555b191 100644
--- a/configs/sifive_unmatched_defconfig
+++ b/configs/sifive_unmatched_defconfig
@@ -1,4 +1,5 @@
CONFIG_RISCV=y
+# CONFIG_SPL_USE_ARCH_MEMMOVE is not set
CONFIG_SPL_GPIO=y
CONFIG_SYS_MALLOC_F_LEN=0x3000
CONFIG_NR_DRAM_BANKS=1
@@ -12,7 +13,6 @@
CONFIG_TARGET_SIFIVE_UNMATCHED=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
-# CONFIG_SPL_USE_ARCH_MEMMOVE is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_FIT=y
diff --git a/configs/smdk5250_defconfig b/configs/smdk5250_defconfig
index f1d38ee..0da76e5 100644
--- a/configs/smdk5250_defconfig
+++ b/configs/smdk5250_defconfig
@@ -48,7 +48,6 @@
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_S5P=y
CONFIG_MTD=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_WINBOND=y
diff --git a/configs/smdk5420_defconfig b/configs/smdk5420_defconfig
index fa0c2ea..6c5d4b0 100644
--- a/configs/smdk5420_defconfig
+++ b/configs/smdk5420_defconfig
@@ -43,7 +43,6 @@
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_S5P=y
CONFIG_MTD=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_WINBOND=y
diff --git a/configs/smegw01_defconfig b/configs/smegw01_defconfig
index 7a779f3..1469c46 100644
--- a/configs/smegw01_defconfig
+++ b/configs/smegw01_defconfig
@@ -4,15 +4,17 @@
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0xa0000000
CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_OFFSET=0x100000
CONFIG_SYS_MALLOC_LEN=0x2300000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7d-smegw01"
CONFIG_TARGET_SMEGW01=y
+CONFIG_ENV_OFFSET_REDUND=0x110000
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
# CONFIG_ARMV7_VIRT is not set
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
+CONFIG_IMX_HAB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_HUSH_PARSER=y
@@ -35,6 +37,7 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_BOUNCE_BUFFER=y
diff --git a/configs/snow_defconfig b/configs/snow_defconfig
index 407777c0..55ee7c6 100644
--- a/configs/snow_defconfig
+++ b/configs/snow_defconfig
@@ -58,7 +58,6 @@
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_S5P=y
CONFIG_MTD=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_WINBOND=y
diff --git a/configs/spring_defconfig b/configs/spring_defconfig
index a9062b2..a286467 100644
--- a/configs/spring_defconfig
+++ b/configs/spring_defconfig
@@ -58,7 +58,6 @@
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_S5P=y
CONFIG_MTD=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_WINBOND=y
diff --git a/configs/stih410-b2260_defconfig b/configs/stih410-b2260_defconfig
index d5ec00e..a7ad277 100644
--- a/configs/stih410-b2260_defconfig
+++ b/configs/stih410-b2260_defconfig
@@ -53,6 +53,10 @@
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics"
CONFIG_USB_GADGET_VENDOR_NUM=0x483
diff --git a/configs/stm32f429-discovery_defconfig b/configs/stm32f429-discovery_defconfig
index b6388cf..ed96c37 100644
--- a/configs/stm32f429-discovery_defconfig
+++ b/configs/stm32f429-discovery_defconfig
@@ -28,3 +28,4 @@
# CONFIG_NET is not set
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
+CONFIG_STM32_FLASH=y
diff --git a/configs/stm32f429-evaluation_defconfig b/configs/stm32f429-evaluation_defconfig
index a75c269..9cbd56c 100644
--- a/configs/stm32f429-evaluation_defconfig
+++ b/configs/stm32f429-evaluation_defconfig
@@ -28,3 +28,4 @@
# CONFIG_NET is not set
CONFIG_ARM_PL180_MMCI=y
CONFIG_MTD_NOR_FLASH=y
+CONFIG_STM32_FLASH=y
diff --git a/configs/stm32f469-discovery_defconfig b/configs/stm32f469-discovery_defconfig
index ecca110..85639e2 100644
--- a/configs/stm32f469-discovery_defconfig
+++ b/configs/stm32f469-discovery_defconfig
@@ -30,6 +30,7 @@
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_NOR_FLASH=y
+CONFIG_STM32_FLASH=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_PINCTRL_FULL is not set
diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig
index 2694a32..e5e7ef7 100644
--- a/configs/stm32f746-disco_defconfig
+++ b/configs/stm32f746-disco_defconfig
@@ -45,6 +45,7 @@
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_NOR_FLASH=y
+CONFIG_STM32_FLASH=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/stm32f769-disco_defconfig b/configs/stm32f769-disco_defconfig
index 10af638..bb122d6 100644
--- a/configs/stm32f769-disco_defconfig
+++ b/configs/stm32f769-disco_defconfig
@@ -44,6 +44,7 @@
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_NOR_FLASH=y
+CONFIG_STM32_FLASH=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig
index b6ec831e..e066640 100644
--- a/configs/stv0991_defconfig
+++ b/configs/stv0991_defconfig
@@ -12,7 +12,6 @@
CONFIG_SYS_MALLOC_LEN=0x14000
CONFIG_DEFAULT_DEVICE_TREE="stv0991"
CONFIG_SYS_LOAD_ADDR=0x0
-CONFIG_SYS_EXTRA_OPTIONS="STV0991"
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
diff --git a/configs/synquacer_developerbox_defconfig b/configs/synquacer_developerbox_defconfig
index a88856b..72d6c8c 100644
--- a/configs/synquacer_developerbox_defconfig
+++ b/configs/synquacer_developerbox_defconfig
@@ -93,4 +93,3 @@
CONFIG_EFI_CAPSULE_ON_DISK=y
CONFIG_EFI_IGNORE_OSINDICATIONS=y
CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
-CONFIG_EFI_SECURE_BOOT=y
diff --git a/configs/tec-ng_defconfig b/configs/tec-ng_defconfig
index 760e516..df9c242 100644
--- a/configs/tec-ng_defconfig
+++ b/configs/tec-ng_defconfig
@@ -30,7 +30,6 @@
CONFIG_SYS_MMC_ENV_PART=2
CONFIG_SPL_DM=y
CONFIG_SYS_I2C_TEGRA=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
diff --git a/configs/tools-only_defconfig b/configs/tools-only_defconfig
index 64a015b..d0e34cb 100644
--- a/configs/tools-only_defconfig
+++ b/configs/tools-only_defconfig
@@ -7,6 +7,8 @@
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_MISC_INIT_F=y
+CONFIG_AVB_BUF_ADDR=0x0
+CONFIG_AVB_BUF_SIZE=0x8192
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_BOOTM is not set
# CONFIG_CMD_ELF is not set
@@ -31,4 +33,7 @@
# CONFIG_VIRTIO_MMIO is not set
# CONFIG_VIRTIO_PCI is not set
# CONFIG_VIRTIO_SANDBOX is not set
-# CONFIG_EFI_LOADER is not set
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_CAPSULE_AUTHENTICATE=y
diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig
index b43e546..f8ba64d 100644
--- a/configs/topic_miami_defconfig
+++ b/configs/topic_miami_defconfig
@@ -46,7 +46,6 @@
CONFIG_SYS_I2C_CADENCE=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=108000000
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig
index a8a0ff2..94d7afd 100644
--- a/configs/topic_miamilite_defconfig
+++ b/configs/topic_miamilite_defconfig
@@ -46,7 +46,6 @@
CONFIG_SYS_I2C_CADENCE=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=108000000
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig
index 7f8cb4b..dc03caa 100644
--- a/configs/topic_miamiplus_defconfig
+++ b/configs/topic_miamiplus_defconfig
@@ -45,7 +45,6 @@
CONFIG_SYS_I2C_CADENCE=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=108000000
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
diff --git a/configs/tqma6dl_mba6_mmc_defconfig b/configs/tqma6dl_mba6_mmc_defconfig
index 8ca32b1..9f3e8f6 100644
--- a/configs/tqma6dl_mba6_mmc_defconfig
+++ b/configs/tqma6dl_mba6_mmc_defconfig
@@ -39,7 +39,6 @@
CONFIG_SYS_I2C_MXC=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_FSL_USDHC=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/tqma6dl_mba6_spi_defconfig b/configs/tqma6dl_mba6_spi_defconfig
index 75b034a..a7a9776 100644
--- a/configs/tqma6dl_mba6_spi_defconfig
+++ b/configs/tqma6dl_mba6_spi_defconfig
@@ -43,7 +43,6 @@
CONFIG_SYS_I2C_MXC=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_FSL_USDHC=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/tqma6q_mba6_mmc_defconfig b/configs/tqma6q_mba6_mmc_defconfig
index f2ba649..955877b 100644
--- a/configs/tqma6q_mba6_mmc_defconfig
+++ b/configs/tqma6q_mba6_mmc_defconfig
@@ -39,7 +39,6 @@
CONFIG_SYS_I2C_MXC=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_FSL_USDHC=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/tqma6q_mba6_spi_defconfig b/configs/tqma6q_mba6_spi_defconfig
index 65c52aa..d1f3f2b 100644
--- a/configs/tqma6q_mba6_spi_defconfig
+++ b/configs/tqma6q_mba6_spi_defconfig
@@ -43,7 +43,6 @@
CONFIG_SYS_I2C_MXC=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_FSL_USDHC=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/tqma6s_mba6_mmc_defconfig b/configs/tqma6s_mba6_mmc_defconfig
index fce236e..c46c7e2 100644
--- a/configs/tqma6s_mba6_mmc_defconfig
+++ b/configs/tqma6s_mba6_mmc_defconfig
@@ -39,7 +39,6 @@
CONFIG_SYS_I2C_MXC=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_FSL_USDHC=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/tqma6s_mba6_spi_defconfig b/configs/tqma6s_mba6_spi_defconfig
index 23aa030..feb98a6 100644
--- a/configs/tqma6s_mba6_spi_defconfig
+++ b/configs/tqma6s_mba6_spi_defconfig
@@ -43,7 +43,6 @@
CONFIG_SYS_I2C_MXC=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_FSL_USDHC=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/trimslice_defconfig b/configs/trimslice_defconfig
index 8881645..50b08cb 100644
--- a/configs/trimslice_defconfig
+++ b/configs/trimslice_defconfig
@@ -33,7 +33,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM=y
CONFIG_SYS_I2C_TEGRA=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_RTL8169=y
CONFIG_PCI=y
diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig
index 82ad68b..3cae32f 100644
--- a/configs/turris_mox_defconfig
+++ b/configs/turris_mox_defconfig
@@ -24,7 +24,9 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_ARCH_EARLY_INIT_R=y
+CONFIG_LAST_STAGE_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_CMD_SHA1SUM=y
CONFIG_CMD_CLK=y
@@ -59,6 +61,7 @@
CONFIG_CLK_MVEBU=y
# CONFIG_MVEBU_GPIO is not set
CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MV=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_MISC=y
@@ -67,7 +70,6 @@
CONFIG_MMC_SDHCI_XENON=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig
index 4d080ba..9cad1e1 100644
--- a/configs/turris_omnia_defconfig
+++ b/configs/turris_omnia_defconfig
@@ -1,5 +1,4 @@
CONFIG_ARM=y
-CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_SPL_SYS_THUMB_BUILD=y
CONFIG_ARCH_MVEBU=y
diff --git a/configs/uDPU_defconfig b/configs/uDPU_defconfig
index a06a253..fa2293b 100644
--- a/configs/uDPU_defconfig
+++ b/configs/uDPU_defconfig
@@ -54,13 +54,13 @@
CONFIG_CLK_MVEBU=y
CONFIG_DM_I2C=y
CONFIG_DM_I2C_GPIO=y
+CONFIG_SYS_I2C_MV=y
CONFIG_MISC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_XENON=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/usbarmory_defconfig b/configs/usbarmory_defconfig
index f259554..a4cdcca 100644
--- a/configs/usbarmory_defconfig
+++ b/configs/usbarmory_defconfig
@@ -39,3 +39,4 @@
CONFIG_MXC_UART=y
CONFIG_USB=y
CONFIG_USB_EHCI_MX5=y
+CONFIG_DM_ETH=y
diff --git a/configs/variscite_dart6ul_defconfig b/configs/variscite_dart6ul_defconfig
index e93ce8e..d15886c 100644
--- a/configs/variscite_dart6ul_defconfig
+++ b/configs/variscite_dart6ul_defconfig
@@ -47,7 +47,6 @@
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
-# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_MXC_UART=y
diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig
index dba47c9..d005bbf 100644
--- a/configs/venice2_defconfig
+++ b/configs/venice2_defconfig
@@ -37,7 +37,6 @@
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000
CONFIG_SYS_I2C_TEGRA=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
diff --git a/configs/vinco_defconfig b/configs/vinco_defconfig
index 5297c54..e90e362 100644
--- a/configs/vinco_defconfig
+++ b/configs/vinco_defconfig
@@ -35,7 +35,6 @@
CONFIG_AT91_GPIO=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_PHY_SMSC=y
CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/warp7_bl33_defconfig b/configs/warp7_bl33_defconfig
index 246a1ec..9b4650f 100644
--- a/configs/warp7_bl33_defconfig
+++ b/configs/warp7_bl33_defconfig
@@ -53,7 +53,6 @@
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
-CONFIG_OPTEE=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
@@ -68,4 +67,3 @@
CONFIG_USB_ETH_CDC=y
CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00"
CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_OPTEE_TZDRAM_SIZE=0x02000000
diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig
index db8d4f6..4d1a781 100644
--- a/configs/warp7_defconfig
+++ b/configs/warp7_defconfig
@@ -8,6 +8,7 @@
CONFIG_SYS_MALLOC_LEN=0x2300000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7s-warp"
+CONFIG_OPTEE_TZDRAM_SIZE=0x3000000
CONFIG_TARGET_WARP7=y
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
# CONFIG_ARMV7_VIRT is not set
@@ -59,7 +60,6 @@
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
-CONFIG_OPTEE=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
@@ -73,5 +73,4 @@
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00"
-CONFIG_OPTEE_TZDRAM_SIZE=0x3000000
CONFIG_BOOTM_OPTEE=y
diff --git a/configs/x530_defconfig b/configs/x530_defconfig
index 0f94b54..6ba7ee2 100644
--- a/configs/x530_defconfig
+++ b/configs/x530_defconfig
@@ -1,5 +1,4 @@
CONFIG_ARM=y
-CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig
index 78ebff7..ff5c8dc 100644
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -210,4 +210,3 @@
CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
CONFIG_EFI_CAPSULE_ON_DISK=y
CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
-CONFIG_EFI_SECURE_BOOT=y
diff --git a/doc/README.440-DDR-performance b/doc/README.440-DDR-performance
deleted file mode 100644
index 66b97bc..0000000
--- a/doc/README.440-DDR-performance
+++ /dev/null
@@ -1,90 +0,0 @@
-AMCC suggested to set the PMU bit to 0 for best performace on the
-PPC440 DDR controller. The 440er common DDR setup files (sdram.c &
-spd_sdram.c) are changed accordingly. So all 440er boards using
-these setup routines will automatically receive this performance
-increase.
-
-Please see below some benchmarks done by AMCC to demonstrate this
-performance changes:
-
-
-----------------------------------------
-SDRAM0_CFG0[PMU] = 1 (U-Boot default for Bamboo, Yosemite and Yellowstone)
-----------------------------------------
-Stream benchmark results
--------------------------------------------------------------
-This system uses 8 bytes per DOUBLE PRECISION word.
--------------------------------------------------------------
-Array size = 2000000, Offset = 0
-Total memory required = 45.8 MB.
-Each test is run 10 times, but only
-the *best* time for each is used.
--------------------------------------------------------------
-Your clock granularity/precision appears to be 1 microseconds.
-Each test below will take on the order of 112345 microseconds.
- (= 112345 clock ticks)
-Increase the size of the arrays if this shows that you are not getting
-at least 20 clock ticks per test.
--------------------------------------------------------------
-WARNING -- The above is only a rough guideline.
-For best results, please be sure you know the precision of your system
-timer.
--------------------------------------------------------------
-Function Rate (MB/s) RMS time Min time Max time
-Copy: 256.7683 0.1248 0.1246 0.1250
-Scale: 246.0157 0.1302 0.1301 0.1302
-Add: 255.0316 0.1883 0.1882 0.1885
-Triad: 253.1245 0.1897 0.1896 0.1899
-
-
-TTCP Benchmark Results
-ttcp-t: socket
-ttcp-t: connect
-ttcp-t: buflen=8192, nbuf=2048, align=16384/0, port=5000 tcp ->
-localhost
-ttcp-t: 16777216 bytes in 0.28 real seconds = 454.29 Mbit/sec +++
-ttcp-t: 2048 I/O calls, msec/call = 0.14, calls/sec = 7268.57
-ttcp-t: 0.0user 0.1sys 0:00real 60% 0i+0d 0maxrss 0+2pf 3+1506csw
-
-----------------------------------------
-SDRAM0_CFG0[PMU] = 0 (Suggested modification)
-Setting PMU = 0 provides a noticeable performance improvement *2% to
-5% improvement in memory performance.
-*Improves the Mbit/sec for TTCP benchmark by almost 76%.
-----------------------------------------
-Stream benchmark results
--------------------------------------------------------------
-This system uses 8 bytes per DOUBLE PRECISION word.
--------------------------------------------------------------
-Array size = 2000000, Offset = 0
-Total memory required = 45.8 MB.
-Each test is run 10 times, but only
-the *best* time for each is used.
--------------------------------------------------------------
-Your clock granularity/precision appears to be 1 microseconds.
-Each test below will take on the order of 120066 microseconds.
- (= 120066 clock ticks)
-Increase the size of the arrays if this shows that you are not getting
-at least 20 clock ticks per test.
--------------------------------------------------------------
-WARNING -- The above is only a rough guideline.
-For best results, please be sure you know the precision of your system
-timer.
--------------------------------------------------------------
-Function Rate (MB/s) RMS time Min time Max time
-Copy: 262.5167 0.1221 0.1219 0.1223
-Scale: 258.4856 0.1238 0.1238 0.1240
-Add: 262.5404 0.1829 0.1828 0.1831
-Triad: 266.8594 0.1800 0.1799 0.1802
-
-TTCP Benchmark Results
-ttcp-t: socket
-ttcp-t: connect
-ttcp-t: buflen=8192, nbuf=2048, align=16384/0, port=5000 tcp ->
-localhost
-ttcp-t: 16777216 bytes in 0.16 real seconds = 804.06 Mbit/sec +++
-ttcp-t: 2048 I/O calls, msec/call = 0.08, calls/sec = 12864.89
-ttcp-t: 0.0user 0.0sys 0:00real 46% 0i+0d 0maxrss 0+2pf 120+1csw
-
-
-2006-07-28, Stefan Roese <sr@denx.de>
diff --git a/doc/api/index.rst b/doc/api/index.rst
index ea02aa5..281d1dc 100644
--- a/doc/api/index.rst
+++ b/doc/api/index.rst
@@ -15,5 +15,6 @@
rng
sandbox
serial
+ sysreset
timer
unicode
diff --git a/doc/api/sysreset.rst b/doc/api/sysreset.rst
new file mode 100644
index 0000000..a51b06c
--- /dev/null
+++ b/doc/api/sysreset.rst
@@ -0,0 +1,7 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+System reset
+============
+
+.. kernel-doc:: include/sysreset.h
+ :internal:
diff --git a/doc/board/kontron/index.rst b/doc/board/kontron/index.rst
index 543b22e..7dfe3d9 100644
--- a/doc/board/kontron/index.rst
+++ b/doc/board/kontron/index.rst
@@ -7,3 +7,5 @@
:maxdepth: 2
sl28
+ sl-mx6ul
+ sl-mx8mm
diff --git a/doc/board/kontron/sl-mx6ul.rst b/doc/board/kontron/sl-mx6ul.rst
new file mode 100644
index 0000000..b0b0f44
--- /dev/null
+++ b/doc/board/kontron/sl-mx6ul.rst
@@ -0,0 +1,43 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Kontron Electronics SL i.MX6UL/ULL SoM
+======================================
+
+The Kontron SoM-Line i.MX6UL/ULL (N6x1x) by Kontron Electronics GmbH is a SoM module
+with either an i.MX6UL or i.MX6ULL SoC, 256/512 MB DDR3 RAM, SPI NOR, SPI NAND and Ethernet PHY.
+
+The matching evaluation boards (Board-Line) have two Ethernet ports, USB 2.0,
+RGB, SD card, CAN, RS485, RS232 and much more.
+
+Quick Start
+-----------
+
+- Build U-Boot
+- Boot
+
+Build U-Boot
+^^^^^^^^^^^^
+
+.. code-block:: bash
+
+ $ make kontron-sl-mx6ul_defconfig
+ $ make
+
+Burn the flash.bin to SD card at an offset of 1 KiB:
+
+.. code-block:: bash
+
+ $ dd if=flash.bin of=/dev/sd[x] bs=1K seek=1 conv=notrunc
+
+Boot
+^^^^
+
+Put the SD card in the slot on the board and apply power.
+
+Further Information
+-------------------
+
+The bootloader configuration is setup to be used with kernel FIT images. Legacy
+images might not be working out of the box.
+
+Please see https://docs.kontron-electronics.de for further vendor documentation.
diff --git a/doc/board/kontron/sl-mx8mm.rst b/doc/board/kontron/sl-mx8mm.rst
new file mode 100644
index 0000000..74ff228
--- /dev/null
+++ b/doc/board/kontron/sl-mx8mm.rst
@@ -0,0 +1,85 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Kontron Electronics SL i.MX8MM SoM
+==================================
+
+The Kontron SoM-Line i.MX8MM (N801x) by Kontron Electronics GmbH is a SoM module
+with an i.MX8M-Mini SoC, 1/2/4 GB LPDDR4 RAM, SPI NOR, eMMC and PMIC.
+
+The matching evaluation boards (Board-Line) have two Ethernet ports, USB 2.0,
+HDMI/LVDS, SD card, CAN, RS485, RS232 and much more.
+
+Quick Start
+-----------
+
+- Get and Build the Trusted Firmware-A (TF-A)
+- Get the DDR firmware
+- Build U-Boot
+- Boot
+
+Get and Build the Trusted Firmware-A (TF-A)
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Note: builddir is U-Boot build directory (source directory for in-tree builds)
+
+There are two sources for the TF-A. Mainline and NXP. Get the one you prefer
+(support and features might differ).
+
+**NXP's imx-atf**
+
+1. Get TF-A from: https://source.codeaurora.org/external/imx/imx-atf, branch: imx_5.4.70_2.3.0
+2. Apply the patch to select the correct UART for the console, otherwise the TF-A will lock up during boot.
+3. Build
+
+ .. code-block:: bash
+
+ $ make PLAT=imx8mm bl31
+ $ cp build/imx8mm/release/bl31.bin $(builddir)
+
+**Mainline TF-A**
+
+1. Get TF-A from: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/, tag: v2.4
+2. Build
+
+ .. code-block:: bash
+
+ $ make PLAT=imx8mm CROSS_COMPILE=aarch64-linux-gnu- IMX_BOOT_UART_BASE="0x30880000" bl31
+ $ cp build/imx8mm/release/bl31.bin $(builddir)
+
+Get the DDR firmware
+^^^^^^^^^^^^^^^^^^^^
+
+.. code-block:: bash
+
+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
+ $ chmod +x firmware-imx-8.9.bin
+ $ ./firmware-imx-8.9.bin
+ $ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin $(builddir)
+
+Build U-Boot
+^^^^^^^^^^^^
+
+.. code-block:: bash
+
+ $ make kontron-sl-mx8mm_defconfig
+ $ export ATF_LOAD_ADDR=0x920000
+ $ make
+
+Burn the flash.bin to SD card at an offset of 33 KiB:
+
+.. code-block:: bash
+
+ $ dd if=flash.bin of=/dev/sd[x] bs=1K seek=33 conv=notrunc
+
+Boot
+^^^^
+
+Put the SD card in the slot on the board and apply power.
+
+Further Information
+-------------------
+
+The bootloader configuration is setup to be used with kernel FIT images. Legacy
+images might not be working out of the box.
+
+Please see https://docs.kontron-electronics.de for further vendor documentation.
diff --git a/doc/board/nxp/imx8mp_evk.rst b/doc/board/nxp/imx8mp_evk.rst
index 609a29f..b996ae0 100644
--- a/doc/board/nxp/imx8mp_evk.rst
+++ b/doc/board/nxp/imx8mp_evk.rst
@@ -52,7 +52,6 @@
.. code-block:: bash
$sudo dd if=build/flash.bin of=/dev/sd[x] bs=1K seek=32 conv=notrunc; sync
- $sudo dd if=build/u-boot.itb of=/dev/sd[x] bs=1K seek=384 conv=notrunc; sync
Boot
----
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index fbb9983..144cb98 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -16,16 +16,18 @@
Rockchip is SoC solutions provider for tablets & PCs, streaming media
TV boxes, AI audio & vision, IoT hardware.
-A wide range of Rockchip SoCs with associated boardsare supported in
+A wide range of Rockchip SoCs with associated boards are supported in
mainline U-Boot.
-List of mainline supported rockchip boards:
+List of mainline supported Rockchip boards:
* rk3036
- Rockchip Evb-RK3036 (evb-rk3036)
- Kylin (kylin_rk3036)
* rk3128
- Rockchip Evb-RK3128 (evb-rk3128)
+* rk3188
+ - Radxa Rock (rock)
* rk3229
- Rockchip Evb-RK3229 (evb-rk3229)
* rk3288
@@ -75,8 +77,6 @@
* rv1108
- Rockchip Evb-rv1108 (evb-rv1108)
- Elgin-R1 (elgin-rv1108)
-* rv3188
- - Radxa Rock (rock)
Building
--------
@@ -93,7 +93,7 @@
make realclean
make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399
-Specify the PLAT= with desired rockchip platform to build TF-A for.
+Specify the PLAT= with desired Rockchip platform to build TF-A for.
U-Boot
^^^^^^
@@ -130,7 +130,7 @@
SD Card
^^^^^^^
-All rockchip platforms, except rk3128 (which doesn't use SPL) are now
+All Rockchip platforms, except rk3128 (which doesn't use SPL) are now
supporting single boot image using binman and pad_cat.
To write an image that boots from an SD card (assumed to be /dev/sda)::
@@ -141,7 +141,7 @@
eMMC
^^^^
-eMMC flash would probe on mmc0 in most of the rockchip platforms.
+eMMC flash would probe on mmc0 in most of the Rockchip platforms.
Create GPT partition layout as defined in configurations::
@@ -164,7 +164,7 @@
sudo fastboot -i 0x2207 flash loader1 idbloader.img
sudo fastboot -i 0x2207 flash loader2 u-boot.itb
-Note: for rockchip 32-bit platforms the U-Boot proper image
+Note: for Rockchip 32-bit platforms the U-Boot proper image
is u-boot-dtb.img
SPI
@@ -227,8 +227,8 @@
TODO
----
-- Add rockchip idbloader image building
-- Add rockchip TPL image building
+- Add Rockchip idbloader image building
+- Add Rockchip TPL image building
- Document SPI flash boot
- Add missing SoC's with it boards list
diff --git a/doc/build/gcc.rst b/doc/build/gcc.rst
index 0cdc307..cdd7970 100644
--- a/doc/build/gcc.rst
+++ b/doc/build/gcc.rst
@@ -27,9 +27,9 @@
device-tree-compiler dfu-util efitools flex gdisk graphviz imagemagick \
liblz4-tool libguestfs-tools libncurses-dev libpython3-dev libsdl2-dev \
libssl-dev lz4 lzma lzma-alone openssl pkg-config python3 \
- python3-coverage python3-pycryptodome python3-pyelftools python3-pytest \
- python3-sphinxcontrib.apidoc python3-sphinx-rtd-theme python3-virtualenv \
- swig
+ python3-coverage python3-pkg-resources python3-pycryptodome \
+ python3-pyelftools python3-pytest python3-sphinxcontrib.apidoc \
+ python3-sphinx-rtd-theme python3-virtualenv swig
SUSE based
~~~~~~~~~~
@@ -120,6 +120,27 @@
* O=<dir> - generate all output files in directory <dir>, including .config
* V=1 - verbose build
+Devicetree compiler
+~~~~~~~~~~~~~~~~~~~
+
+Boards that use `CONFIG_OF_CONTROL` (i.e. almost all of them) need the
+devicetree compiler (dtc). Those with `CONFIG_PYLIBFDT` need pylibfdt, a Python
+library for accessing devicetree data. Suitable versions of these are included
+in the U-Boot tree in `scripts/dtc` and built automatically as needed.
+
+To use the system versions of these, use the DTC parameter, for example
+
+.. code-block:: bash
+
+ DTC=/usr/bin/dtc make
+
+In this case, dtc and pylibfdt are not built. The build checks that the version
+of dtc is new enough. It also makes sure that pylibfdt is present, if needed
+(see `scripts_dtc` in the Makefile).
+
+Note that the :doc:`tools` are always built with the included version of libfdt
+so it is not possible to build U-Boot tools with a system libfdt, at present.
+
Other build targets
~~~~~~~~~~~~~~~~~~~
diff --git a/doc/develop/py_testing.rst b/doc/develop/py_testing.rst
index 4f1e1f6..06f9196 100644
--- a/doc/develop/py_testing.rst
+++ b/doc/develop/py_testing.rst
@@ -103,6 +103,21 @@
browser, but may be read directly as plain text, perhaps with the aid of the
`html2text` utility.
+If sandbox crashes (e.g. with a segfault) you will see message like this::
+
+
+ test/py/u_boot_spawn.py:171: in expect
+ c = os.read(self.fd, 1024).decode(errors='replace')
+ E ValueError: U-Boot exited with signal 11 (Signals.SIGSEGV)
+
+
+Controlling output
+~~~~~~~~~~~~~~~~~~
+
+By default a short backtrace is reported. If you would like a longer one,
+pass ``--tb=long`` when running the test. See the pytest documentation for
+more options.
+
Running tests in parallel
~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/doc/device-tree-bindings/gpio/gpio-max7320.txt b/doc/device-tree-bindings/gpio/gpio-max7320.txt
new file mode 100644
index 0000000..87b703b
--- /dev/null
+++ b/doc/device-tree-bindings/gpio/gpio-max7320.txt
@@ -0,0 +1,36 @@
+* MAX7320 I/O expanders
+
+The original maxim 7320 i/o expander offers 8 bit push/pull outputs.
+There exists some clones which offers 16 bit.
+
+Required Properties:
+
+ - compatible: should be one of the following.
+ - "maxim,max7320"
+
+ - reg: I2C slave address.
+
+ - gpio-controller: Marks the device node as a gpio controller.
+ - #gpio-cells: Should be 2. The first cell is the GPIO number and the second
+ cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. Only the
+ GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.
+
+Optional Properties:
+
+ - ngpios: tell the driver how many gpios the device offers.
+ if the property is omitted, 8bit (original maxim) is assumed.
+
+Please refer to gpio.txt in this directory for details of the common GPIO
+bindings used by client devices.
+
+Example: MAX7320 I/O expander node
+
+ ledgpio: max7320@5d {
+ status = "okay";
+ compatible = "maxim,max7320";
+ reg = <0x5d>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ ngpios = <16>;
+ };
+
diff --git a/doc/device-tree-bindings/pwm/pwm-at91.txt b/doc/device-tree-bindings/pwm/pwm-at91.txt
new file mode 100644
index 0000000..a03da40
--- /dev/null
+++ b/doc/device-tree-bindings/pwm/pwm-at91.txt
@@ -0,0 +1,16 @@
+Microchip AT91 PWM controller for SAMA5D2
+
+Required properties:
+ - compatible: Should be "atmel,sama5d2-pwm"
+ - reg: Physical base address and length of the controller's registers.
+ - clocks: Should contain a clock identifier for the PWM's parent clock.
+ - #pwm-cells: Should be 3.
+
+Example:
+
+pwm0: pwm@f802c000 {
+ compatible = "atmel,sama5d2-pwm";
+ reg = <0xf802c000 0x4000>;
+ clocks = <&pwm_clk>;
+ #pwm-cells = <3>;
+};
diff --git a/doc/sphinx/requirements.txt b/doc/sphinx/requirements.txt
index af79d2c..4555a94 100644
--- a/doc/sphinx/requirements.txt
+++ b/doc/sphinx/requirements.txt
@@ -1,4 +1,4 @@
docutils==0.16
-Sphinx==2.4.4
+Sphinx==3.4.3
sphinx_rtd_theme
six
diff --git a/drivers/cache/cache-sifive-ccache.c b/drivers/cache/cache-sifive-ccache.c
index 76c0ab2..c8766f6 100644
--- a/drivers/cache/cache-sifive-ccache.c
+++ b/drivers/cache/cache-sifive-ccache.c
@@ -38,7 +38,7 @@
{
struct sifive_ccache *priv = dev_get_priv(dev);
- info->base = (phys_addr_t)priv->base;
+ info->base = (uintptr_t)priv->base;
return 0;
}
diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c
index e0dc4ab..c5a2a42 100644
--- a/drivers/clk/clk_fixed_rate.c
+++ b/drivers/clk/clk_fixed_rate.c
@@ -26,6 +26,7 @@
const struct clk_ops clk_fixed_rate_ops = {
.get_rate = clk_fixed_rate_get_rate,
.enable = dummy_enable,
+ .disable = dummy_enable,
};
void clk_fixed_rate_ofdata_to_plat_(struct udevice *dev,
diff --git a/drivers/clk/rockchip/clk_px30.c b/drivers/clk/rockchip/clk_px30.c
index 617ce0d..ea874e3 100644
--- a/drivers/clk/rockchip/clk_px30.c
+++ b/drivers/clk/rockchip/clk_px30.c
@@ -1291,6 +1291,9 @@
case PLL_NPLL:
ret = px30_clk_set_pll_rate(priv, NPLL, rate);
break;
+ case PLL_CPLL:
+ ret = px30_clk_set_pll_rate(priv, CPLL, rate);
+ break;
case ARMCLK:
ret = px30_armclk_set_clk(priv, rate);
break;
diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c
index 553c6c0..d5e45e7 100644
--- a/drivers/clk/rockchip/clk_rk3568.c
+++ b/drivers/clk/rockchip/clk_rk3568.c
@@ -1441,6 +1441,7 @@
switch (rate) {
case OSC_HZ:
+ case 26 * MHz:
src_clk = CLK_SDMMC_SEL_24M;
break;
case 400 * MHz:
@@ -1507,7 +1508,7 @@
case SCLK_SFC_SEL_125M:
return 125 * MHz;
case SCLK_SFC_SEL_150M:
- return 150 * KHz;
+ return 150 * MHz;
default:
return -ENOENT;
}
@@ -1534,7 +1535,7 @@
case 125 * MHz:
src_clk = SCLK_SFC_SEL_125M;
break;
- case 150 * KHz:
+ case 150 * MHz:
src_clk = SCLK_SFC_SEL_150M;
break;
default:
@@ -2406,6 +2407,9 @@
case BCLK_EMMC:
rate = rk3568_emmc_get_bclk(priv);
break;
+ case TCLK_EMMC:
+ rate = OSC_HZ;
+ break;
#ifndef CONFIG_SPL_BUILD
case ACLK_VOP:
rate = rk3568_aclk_vop_get_clk(priv);
@@ -2582,6 +2586,9 @@
case BCLK_EMMC:
ret = rk3568_emmc_set_bclk(priv, rate);
break;
+ case TCLK_EMMC:
+ ret = OSC_HZ;
+ break;
#ifndef CONFIG_SPL_BUILD
case ACLK_VOP:
ret = rk3568_aclk_vop_set_clk(priv, rate);
diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c
index cd1acb9..52ae268 100644
--- a/drivers/clk/sifive/sifive-prci.c
+++ b/drivers/clk/sifive/sifive-prci.c
@@ -653,9 +653,9 @@
struct prci_clk_desc *data =
(struct prci_clk_desc *)dev_get_driver_data(dev);
- pd->va = (void *)dev_read_addr(dev);
- if (IS_ERR(pd->va))
- return PTR_ERR(pd->va);
+ pd->va = dev_read_addr_ptr(dev);
+ if (!pd->va)
+ return -EINVAL;
err = clk_get_by_index(dev, 0, &pd->parent_hfclk);
if (err)
diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig
index bf084fa..f89c7ff 100644
--- a/drivers/clk/sunxi/Kconfig
+++ b/drivers/clk/sunxi/Kconfig
@@ -30,6 +30,13 @@
This enables common clock driver support for platforms based
on Allwinner A31/A31s SoC.
+config CLK_SUN6I_A31_R
+ bool "Clock driver for Allwinner A31 generation PRCM"
+ default SUNXI_GEN_SUN6I
+ help
+ This enables common clock driver support for the PRCM
+ in Allwinner A31/A31s/A23/A33/A83T/H3/A64/H5 SoCs.
+
config CLK_SUN8I_A23
bool "Clock driver for Allwinner A23/A33"
default MACH_SUN8I_A23 || MACH_SUN8I_A33
@@ -79,6 +86,13 @@
This enables common clock driver support for platforms based
on Allwinner H6 SoC.
+config CLK_SUN50I_H6_R
+ bool "Clock driver for Allwinner H6 generation PRCM"
+ default SUN50I_GEN_H6
+ help
+ This enables common clock driver support for the PRCM
+ in Allwinner H6/H616 SoCs.
+
config CLK_SUN50I_H616
bool "Clock driver for Allwinner H616"
default MACH_SUN50I_H616
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 4f9282a..48a48a2 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -11,6 +11,7 @@
obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o
obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o
obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o
+obj-$(CONFIG_CLK_SUN6I_A31_R) += clk_a31_r.o
obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o
obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o
obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o
@@ -18,5 +19,6 @@
obj-$(CONFIG_CLK_SUN9I_A80) += clk_a80.o
obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
obj-$(CONFIG_CLK_SUN50I_H6) += clk_h6.o
+obj-$(CONFIG_CLK_SUN50I_H6_R) += clk_h6_r.o
obj-$(CONFIG_CLK_SUN50I_H616) += clk_h616.o
obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o
diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c
index 1b5de86..90b929d 100644
--- a/drivers/clk/sunxi/clk_a10.c
+++ b/drivers/clk/sunxi/clk_a10.c
@@ -8,7 +8,7 @@
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
#include <dt-bindings/clock/sun4i-a10-ccu.h>
#include <dt-bindings/reset/sun4i-a10-ccu.h>
#include <linux/bitops.h>
@@ -31,6 +31,11 @@
[CLK_AHB_GMAC] = GATE(0x064, BIT(17)),
+ [CLK_APB1_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_APB1_I2C1] = GATE(0x06c, BIT(1)),
+ [CLK_APB1_I2C2] = GATE(0x06c, BIT(2)),
+ [CLK_APB1_I2C3] = GATE(0x06c, BIT(3)),
+ [CLK_APB1_I2C4] = GATE(0x06c, BIT(15)),
[CLK_APB1_UART0] = GATE(0x06c, BIT(16)),
[CLK_APB1_UART1] = GATE(0x06c, BIT(17)),
[CLK_APB1_UART2] = GATE(0x06c, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c
index 184f61a..addf4f4 100644
--- a/drivers/clk/sunxi/clk_a10s.c
+++ b/drivers/clk/sunxi/clk_a10s.c
@@ -8,7 +8,7 @@
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
#include <dt-bindings/clock/sun5i-ccu.h>
#include <dt-bindings/reset/sun5i-ccu.h>
#include <linux/bitops.h>
@@ -25,6 +25,9 @@
[CLK_AHB_SPI1] = GATE(0x060, BIT(21)),
[CLK_AHB_SPI2] = GATE(0x060, BIT(22)),
+ [CLK_APB1_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_APB1_I2C1] = GATE(0x06c, BIT(1)),
+ [CLK_APB1_I2C2] = GATE(0x06c, BIT(2)),
[CLK_APB1_UART0] = GATE(0x06c, BIT(16)),
[CLK_APB1_UART1] = GATE(0x06c, BIT(17)),
[CLK_APB1_UART2] = GATE(0x06c, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c
index 5750514..c45d2c3 100644
--- a/drivers/clk/sunxi/clk_a23.c
+++ b/drivers/clk/sunxi/clk_a23.c
@@ -8,7 +8,7 @@
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
#include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
#include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
#include <linux/bitops.h>
@@ -23,6 +23,9 @@
[CLK_BUS_EHCI] = GATE(0x060, BIT(26)),
[CLK_BUS_OHCI] = GATE(0x060, BIT(29)),
+ [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
[CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
[CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
[CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
@@ -53,6 +56,9 @@
[RST_BUS_EHCI] = RESET(0x2c0, BIT(26)),
[RST_BUS_OHCI] = RESET(0x2c0, BIT(29)),
+ [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
+ [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
+ [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
[RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
[RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c
index 9226112..251fc3b 100644
--- a/drivers/clk/sunxi/clk_a31.c
+++ b/drivers/clk/sunxi/clk_a31.c
@@ -8,7 +8,7 @@
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
#include <dt-bindings/clock/sun6i-a31-ccu.h>
#include <dt-bindings/reset/sun6i-a31-ccu.h>
#include <linux/bitops.h>
@@ -30,6 +30,10 @@
[CLK_AHB1_OHCI1] = GATE(0x060, BIT(30)),
[CLK_AHB1_OHCI2] = GATE(0x060, BIT(31)),
+ [CLK_APB2_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_APB2_I2C1] = GATE(0x06c, BIT(1)),
+ [CLK_APB2_I2C2] = GATE(0x06c, BIT(2)),
+ [CLK_APB2_I2C3] = GATE(0x06c, BIT(3)),
[CLK_APB2_UART0] = GATE(0x06c, BIT(16)),
[CLK_APB2_UART1] = GATE(0x06c, BIT(17)),
[CLK_APB2_UART2] = GATE(0x06c, BIT(18)),
@@ -71,6 +75,10 @@
[RST_AHB1_OHCI1] = RESET(0x2c0, BIT(30)),
[RST_AHB1_OHCI2] = RESET(0x2c0, BIT(31)),
+ [RST_APB2_I2C0] = RESET(0x2d8, BIT(0)),
+ [RST_APB2_I2C1] = RESET(0x2d8, BIT(1)),
+ [RST_APB2_I2C2] = RESET(0x2d8, BIT(2)),
+ [RST_APB2_I2C3] = RESET(0x2d8, BIT(3)),
[RST_APB2_UART0] = RESET(0x2d8, BIT(16)),
[RST_APB2_UART1] = RESET(0x2d8, BIT(17)),
[RST_APB2_UART2] = RESET(0x2d8, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_a31_r.c b/drivers/clk/sunxi/clk_a31_r.c
new file mode 100644
index 0000000..1f08ea9
--- /dev/null
+++ b/drivers/clk/sunxi/clk_a31_r.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) Samuel Holland <samuel@sholland.org>
+ */
+
+#include <clk-uclass.h>
+#include <dm.h>
+#include <clk/sunxi.h>
+#include <dt-bindings/clock/sun8i-r-ccu.h>
+#include <dt-bindings/reset/sun8i-r-ccu.h>
+#include <linux/bitops.h>
+
+static struct ccu_clk_gate a31_r_gates[] = {
+ [CLK_APB0_PIO] = GATE(0x028, BIT(0)),
+ [CLK_APB0_IR] = GATE(0x028, BIT(1)),
+ [CLK_APB0_TIMER] = GATE(0x028, BIT(2)),
+ [CLK_APB0_RSB] = GATE(0x028, BIT(3)),
+ [CLK_APB0_UART] = GATE(0x028, BIT(4)),
+ [CLK_APB0_I2C] = GATE(0x028, BIT(6)),
+ [CLK_APB0_TWD] = GATE(0x028, BIT(7)),
+};
+
+static struct ccu_reset a31_r_resets[] = {
+ [RST_APB0_IR] = RESET(0x0b0, BIT(1)),
+ [RST_APB0_TIMER] = RESET(0x0b0, BIT(2)),
+ [RST_APB0_RSB] = RESET(0x0b0, BIT(3)),
+ [RST_APB0_UART] = RESET(0x0b0, BIT(4)),
+ [RST_APB0_I2C] = RESET(0x0b0, BIT(6)),
+};
+
+static const struct ccu_desc a31_r_ccu_desc = {
+ .gates = a31_r_gates,
+ .resets = a31_r_resets,
+};
+
+static int a31_r_clk_bind(struct udevice *dev)
+{
+ return sunxi_reset_bind(dev, ARRAY_SIZE(a31_r_resets));
+}
+
+static const struct udevice_id a31_r_clk_ids[] = {
+ { .compatible = "allwinner,sun8i-a83t-r-ccu",
+ .data = (ulong)&a31_r_ccu_desc },
+ { .compatible = "allwinner,sun8i-h3-r-ccu",
+ .data = (ulong)&a31_r_ccu_desc },
+ { .compatible = "allwinner,sun50i-a64-r-ccu",
+ .data = (ulong)&a31_r_ccu_desc },
+ { }
+};
+
+U_BOOT_DRIVER(clk_sun6i_a31_r) = {
+ .name = "sun6i_a31_r_ccu",
+ .id = UCLASS_CLK,
+ .of_match = a31_r_clk_ids,
+ .priv_auto = sizeof(struct ccu_priv),
+ .ops = &sunxi_clk_ops,
+ .probe = sunxi_clk_probe,
+ .bind = a31_r_clk_bind,
+};
diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c
index 0553ffa..1004a79 100644
--- a/drivers/clk/sunxi/clk_a64.c
+++ b/drivers/clk/sunxi/clk_a64.c
@@ -8,7 +8,7 @@
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
#include <dt-bindings/clock/sun50i-a64-ccu.h>
#include <dt-bindings/reset/sun50i-a64-ccu.h>
#include <linux/bitops.h>
@@ -26,6 +26,9 @@
[CLK_BUS_OHCI0] = GATE(0x060, BIT(28)),
[CLK_BUS_OHCI1] = GATE(0x060, BIT(29)),
+ [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
[CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
[CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
[CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
@@ -60,6 +63,9 @@
[RST_BUS_OHCI0] = RESET(0x2c0, BIT(28)),
[RST_BUS_OHCI1] = RESET(0x2c0, BIT(29)),
+ [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
+ [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
+ [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
[RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
[RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c
index 68973d5..8a0834d 100644
--- a/drivers/clk/sunxi/clk_a80.c
+++ b/drivers/clk/sunxi/clk_a80.c
@@ -8,7 +8,7 @@
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
#include <dt-bindings/clock/sun9i-a80-ccu.h>
#include <dt-bindings/reset/sun9i-a80-ccu.h>
#include <linux/bitops.h>
@@ -25,6 +25,11 @@
[CLK_BUS_SPI2] = GATE(0x580, BIT(22)),
[CLK_BUS_SPI3] = GATE(0x580, BIT(23)),
+ [CLK_BUS_I2C0] = GATE(0x594, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x594, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x594, BIT(2)),
+ [CLK_BUS_I2C3] = GATE(0x594, BIT(3)),
+ [CLK_BUS_I2C4] = GATE(0x594, BIT(4)),
[CLK_BUS_UART0] = GATE(0x594, BIT(16)),
[CLK_BUS_UART1] = GATE(0x594, BIT(17)),
[CLK_BUS_UART2] = GATE(0x594, BIT(18)),
@@ -40,6 +45,11 @@
[RST_BUS_SPI2] = RESET(0x5a0, BIT(22)),
[RST_BUS_SPI3] = RESET(0x5a0, BIT(23)),
+ [RST_BUS_I2C0] = RESET(0x5b4, BIT(0)),
+ [RST_BUS_I2C1] = RESET(0x5b4, BIT(1)),
+ [RST_BUS_I2C2] = RESET(0x5b4, BIT(2)),
+ [RST_BUS_I2C3] = RESET(0x5b4, BIT(3)),
+ [RST_BUS_I2C4] = RESET(0x5b4, BIT(4)),
[RST_BUS_UART0] = RESET(0x5b4, BIT(16)),
[RST_BUS_UART1] = RESET(0x5b4, BIT(17)),
[RST_BUS_UART2] = RESET(0x5b4, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c
index 880c7d7..8c6043f 100644
--- a/drivers/clk/sunxi/clk_a83t.c
+++ b/drivers/clk/sunxi/clk_a83t.c
@@ -8,7 +8,7 @@
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
#include <dt-bindings/clock/sun8i-a83t-ccu.h>
#include <dt-bindings/reset/sun8i-a83t-ccu.h>
#include <linux/bitops.h>
@@ -25,6 +25,9 @@
[CLK_BUS_EHCI1] = GATE(0x060, BIT(27)),
[CLK_BUS_OHCI0] = GATE(0x060, BIT(29)),
+ [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
[CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
[CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
[CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
@@ -57,6 +60,9 @@
[RST_BUS_EHCI1] = RESET(0x2c0, BIT(27)),
[RST_BUS_OHCI0] = RESET(0x2c0, BIT(29)),
+ [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
+ [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
+ [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
[RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
[RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c
index f81633b..59afba5 100644
--- a/drivers/clk/sunxi/clk_h3.c
+++ b/drivers/clk/sunxi/clk_h3.c
@@ -8,7 +8,7 @@
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
#include <dt-bindings/clock/sun8i-h3-ccu.h>
#include <dt-bindings/reset/sun8i-h3-ccu.h>
#include <linux/bitops.h>
@@ -30,6 +30,9 @@
[CLK_BUS_OHCI2] = GATE(0x060, BIT(30)),
[CLK_BUS_OHCI3] = GATE(0x060, BIT(31)),
+ [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
[CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
[CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
[CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
@@ -74,6 +77,9 @@
[RST_BUS_EPHY] = RESET(0x2c8, BIT(2)),
+ [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
+ [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
+ [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
[RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
[RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c
index df93d96..4a53788 100644
--- a/drivers/clk/sunxi/clk_h6.c
+++ b/drivers/clk/sunxi/clk_h6.c
@@ -8,7 +8,7 @@
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
#include <dt-bindings/clock/sun50i-h6-ccu.h>
#include <dt-bindings/reset/sun50i-h6-ccu.h>
#include <linux/bitops.h>
@@ -22,6 +22,11 @@
[CLK_BUS_UART2] = GATE(0x90c, BIT(2)),
[CLK_BUS_UART3] = GATE(0x90c, BIT(3)),
+ [CLK_BUS_I2C0] = GATE(0x91c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x91c, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x91c, BIT(2)),
+ [CLK_BUS_I2C3] = GATE(0x91c, BIT(3)),
+
[CLK_SPI0] = GATE(0x940, BIT(31)),
[CLK_SPI1] = GATE(0x944, BIT(31)),
@@ -57,6 +62,11 @@
[RST_BUS_UART2] = RESET(0x90c, BIT(18)),
[RST_BUS_UART3] = RESET(0x90c, BIT(19)),
+ [RST_BUS_I2C0] = RESET(0x91c, BIT(16)),
+ [RST_BUS_I2C1] = RESET(0x91c, BIT(17)),
+ [RST_BUS_I2C2] = RESET(0x91c, BIT(18)),
+ [RST_BUS_I2C3] = RESET(0x91c, BIT(19)),
+
[RST_BUS_SPI0] = RESET(0x96c, BIT(16)),
[RST_BUS_SPI1] = RESET(0x96c, BIT(17)),
diff --git a/drivers/clk/sunxi/clk_h616.c b/drivers/clk/sunxi/clk_h616.c
index 553d7c6..af97d3b 100644
--- a/drivers/clk/sunxi/clk_h616.c
+++ b/drivers/clk/sunxi/clk_h616.c
@@ -7,7 +7,7 @@
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
#include <dt-bindings/clock/sun50i-h616-ccu.h>
#include <dt-bindings/reset/sun50i-h616-ccu.h>
#include <linux/bitops.h>
@@ -24,6 +24,12 @@
[CLK_BUS_UART4] = GATE(0x90c, BIT(4)),
[CLK_BUS_UART5] = GATE(0x90c, BIT(5)),
+ [CLK_BUS_I2C0] = GATE(0x91c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x91c, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x91c, BIT(2)),
+ [CLK_BUS_I2C3] = GATE(0x91c, BIT(3)),
+ [CLK_BUS_I2C4] = GATE(0x91c, BIT(4)),
+
[CLK_SPI0] = GATE(0x940, BIT(31)),
[CLK_SPI1] = GATE(0x944, BIT(31)),
@@ -68,6 +74,12 @@
[RST_BUS_UART4] = RESET(0x90c, BIT(20)),
[RST_BUS_UART5] = RESET(0x90c, BIT(21)),
+ [RST_BUS_I2C0] = RESET(0x91c, BIT(16)),
+ [RST_BUS_I2C1] = RESET(0x91c, BIT(17)),
+ [RST_BUS_I2C2] = RESET(0x91c, BIT(18)),
+ [RST_BUS_I2C3] = RESET(0x91c, BIT(19)),
+ [RST_BUS_I2C4] = RESET(0x91c, BIT(20)),
+
[RST_BUS_SPI0] = RESET(0x96c, BIT(16)),
[RST_BUS_SPI1] = RESET(0x96c, BIT(17)),
diff --git a/drivers/clk/sunxi/clk_h6_r.c b/drivers/clk/sunxi/clk_h6_r.c
new file mode 100644
index 0000000..b9e527e
--- /dev/null
+++ b/drivers/clk/sunxi/clk_h6_r.c
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) Samuel Holland <samuel@sholland.org>
+ */
+
+#include <clk-uclass.h>
+#include <dm.h>
+#include <clk/sunxi.h>
+#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
+#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
+#include <linux/bitops.h>
+
+static struct ccu_clk_gate h6_r_gates[] = {
+ [CLK_R_APB1_TIMER] = GATE(0x11c, BIT(0)),
+ [CLK_R_APB1_TWD] = GATE(0x12c, BIT(0)),
+ [CLK_R_APB1_PWM] = GATE(0x13c, BIT(0)),
+ [CLK_R_APB2_UART] = GATE(0x18c, BIT(0)),
+ [CLK_R_APB2_I2C] = GATE(0x19c, BIT(0)),
+ [CLK_R_APB2_RSB] = GATE(0x1bc, BIT(0)),
+ [CLK_R_APB1_IR] = GATE(0x1cc, BIT(0)),
+ [CLK_R_APB1_W1] = GATE(0x1ec, BIT(0)),
+};
+
+static struct ccu_reset h6_r_resets[] = {
+ [RST_R_APB1_TIMER] = RESET(0x11c, BIT(16)),
+ [RST_R_APB1_TWD] = RESET(0x12c, BIT(16)),
+ [RST_R_APB1_PWM] = RESET(0x13c, BIT(16)),
+ [RST_R_APB2_UART] = RESET(0x18c, BIT(16)),
+ [RST_R_APB2_I2C] = RESET(0x19c, BIT(16)),
+ [RST_R_APB2_RSB] = RESET(0x1bc, BIT(16)),
+ [RST_R_APB1_IR] = RESET(0x1cc, BIT(16)),
+ [RST_R_APB1_W1] = RESET(0x1ec, BIT(16)),
+};
+
+static const struct ccu_desc h6_r_ccu_desc = {
+ .gates = h6_r_gates,
+ .resets = h6_r_resets,
+};
+
+static int h6_r_clk_bind(struct udevice *dev)
+{
+ return sunxi_reset_bind(dev, ARRAY_SIZE(h6_r_resets));
+}
+
+static const struct udevice_id h6_r_clk_ids[] = {
+ { .compatible = "allwinner,sun50i-h6-r-ccu",
+ .data = (ulong)&h6_r_ccu_desc },
+ { .compatible = "allwinner,sun50i-h616-r-ccu",
+ .data = (ulong)&h6_r_ccu_desc },
+ { }
+};
+
+U_BOOT_DRIVER(clk_sun6i_h6_r) = {
+ .name = "sun6i_h6_r_ccu",
+ .id = UCLASS_CLK,
+ .of_match = h6_r_clk_ids,
+ .priv_auto = sizeof(struct ccu_priv),
+ .ops = &sunxi_clk_ops,
+ .probe = sunxi_clk_probe,
+ .bind = h6_r_clk_bind,
+};
diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c
index ee1e86d..4d5b69a 100644
--- a/drivers/clk/sunxi/clk_r40.c
+++ b/drivers/clk/sunxi/clk_r40.c
@@ -8,7 +8,7 @@
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
#include <dt-bindings/clock/sun8i-r40-ccu.h>
#include <dt-bindings/reset/sun8i-r40-ccu.h>
#include <linux/bitops.h>
@@ -32,6 +32,11 @@
[CLK_BUS_GMAC] = GATE(0x064, BIT(17)),
+ [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
+ [CLK_BUS_I2C3] = GATE(0x06c, BIT(3)),
+ [CLK_BUS_I2C4] = GATE(0x06c, BIT(15)),
[CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
[CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
[CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
@@ -77,6 +82,11 @@
[RST_BUS_GMAC] = RESET(0x2c4, BIT(17)),
+ [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
+ [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
+ [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
+ [RST_BUS_I2C3] = RESET(0x2d8, BIT(3)),
+ [RST_BUS_I2C4] = RESET(0x2d8, BIT(15)),
[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
[RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
[RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_sunxi.c b/drivers/clk/sunxi/clk_sunxi.c
index 41934cd..9673b58 100644
--- a/drivers/clk/sunxi/clk_sunxi.c
+++ b/drivers/clk/sunxi/clk_sunxi.c
@@ -11,7 +11,7 @@
#include <log.h>
#include <reset.h>
#include <asm/io.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
#include <linux/bitops.h>
#include <linux/log2.h>
diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c
index 2962219..cce5c65 100644
--- a/drivers/clk/sunxi/clk_v3s.c
+++ b/drivers/clk/sunxi/clk_v3s.c
@@ -8,7 +8,7 @@
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
#include <dt-bindings/clock/sun8i-v3s-ccu.h>
#include <dt-bindings/reset/sun8i-v3s-ccu.h>
#include <linux/bitops.h>
@@ -20,6 +20,8 @@
[CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
[CLK_BUS_OTG] = GATE(0x060, BIT(24)),
+ [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
[CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
[CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
[CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
@@ -38,6 +40,8 @@
[RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
[RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
+ [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
+ [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
[RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
[RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
diff --git a/drivers/clk/ti/clk-am3-dpll.c b/drivers/clk/ti/clk-am3-dpll.c
index 916d308..398a011 100644
--- a/drivers/clk/ti/clk-am3-dpll.c
+++ b/drivers/clk/ti/clk-am3-dpll.c
@@ -27,11 +27,17 @@
struct clk_ti_reg clkmode_reg;
struct clk_ti_reg idlest_reg;
struct clk_ti_reg clksel_reg;
+ struct clk_ti_reg ssc_deltam_reg;
+ struct clk_ti_reg ssc_modfreq_reg;
struct clk clk_bypass;
struct clk clk_ref;
u16 last_rounded_mult;
u8 last_rounded_div;
+ u8 min_div;
ulong max_rate;
+ u32 ssc_modfreq;
+ u32 ssc_deltam;
+ bool ssc_downspread;
};
static ulong clk_ti_am3_dpll_round_rate(struct clk *clk, ulong rate)
@@ -51,7 +57,7 @@
err = rate;
err_min = rate;
ref_rate = clk_get_rate(&priv->clk_ref);
- for (d = 1; err_min && d <= 128; d++) {
+ for (d = priv->min_div; err_min && d <= 128; d++) {
for (m = 2; m <= 2047; m++) {
r = (ref_rate * m) / d;
err = abs(r - rate);
@@ -71,8 +77,8 @@
priv->last_rounded_mult = mult;
priv->last_rounded_div = div;
- dev_dbg(clk->dev, "rate=%ld, best_rate=%ld, mult=%d, div=%d\n", rate,
- ret, mult, div);
+ dev_dbg(clk->dev, "rate=%ld, min-div: %d, best_rate=%ld, mult=%d, div=%d\n",
+ rate, priv->min_div, ret, mult, div);
return ret;
}
@@ -107,6 +113,96 @@
return 0;
}
+/**
+ * clk_ti_am3_dpll_ssc_program - set spread-spectrum clocking registers
+ * @clk: struct clk * of DPLL to set
+ *
+ * Enable the DPLL spread spectrum clocking if frequency modulation and
+ * frequency spreading have been set, otherwise disable it.
+ */
+static void clk_ti_am3_dpll_ssc_program(struct clk *clk)
+{
+ struct clk_ti_am3_dpll_priv *priv = dev_get_priv(clk->dev);
+ unsigned long ref_rate;
+ u32 v, ctrl, mod_freq_divider, exponent, mantissa;
+ u32 deltam_step, deltam_ceil;
+
+ ctrl = clk_ti_readl(&priv->clkmode_reg);
+
+ if (priv->ssc_modfreq && priv->ssc_deltam) {
+ ctrl |= CM_CLKMODE_DPLL_SSC_EN_MASK;
+
+ if (priv->ssc_downspread)
+ ctrl |= CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK;
+ else
+ ctrl &= ~CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK;
+
+ ref_rate = clk_get_rate(&priv->clk_ref);
+ mod_freq_divider =
+ (ref_rate / priv->last_rounded_div) / (4 * priv->ssc_modfreq);
+ if (priv->ssc_modfreq > (ref_rate / 70))
+ dev_warn(clk->dev,
+ "clock: SSC modulation frequency of DPLL %s greater than %ld\n",
+ clk->dev->name, ref_rate / 70);
+
+ exponent = 0;
+ mantissa = mod_freq_divider;
+ while ((mantissa > 127) && (exponent < 7)) {
+ exponent++;
+ mantissa /= 2;
+ }
+ if (mantissa > 127)
+ mantissa = 127;
+
+ v = clk_ti_readl(&priv->ssc_modfreq_reg);
+ v &= ~(CM_SSC_MODFREQ_DPLL_MANT_MASK | CM_SSC_MODFREQ_DPLL_EXP_MASK);
+ v |= mantissa << __ffs(CM_SSC_MODFREQ_DPLL_MANT_MASK);
+ v |= exponent << __ffs(CM_SSC_MODFREQ_DPLL_EXP_MASK);
+ clk_ti_writel(v, &priv->ssc_modfreq_reg);
+ dev_dbg(clk->dev,
+ "mod_freq_divider: %u, exponent: %u, mantissa: %u, modfreq_reg: 0x%x\n",
+ mod_freq_divider, exponent, mantissa, v);
+
+ deltam_step = priv->last_rounded_mult * priv->ssc_deltam;
+ deltam_step /= 10;
+ if (priv->ssc_downspread)
+ deltam_step /= 2;
+
+ deltam_step <<= __ffs(CM_SSC_DELTAM_DPLL_INT_MASK);
+ deltam_step /= 100;
+ deltam_step /= mod_freq_divider;
+ if (deltam_step > 0xFFFFF)
+ deltam_step = 0xFFFFF;
+
+ deltam_ceil = (deltam_step & CM_SSC_DELTAM_DPLL_INT_MASK) >>
+ __ffs(CM_SSC_DELTAM_DPLL_INT_MASK);
+ if (deltam_step & CM_SSC_DELTAM_DPLL_FRAC_MASK)
+ deltam_ceil++;
+
+ if ((priv->ssc_downspread &&
+ ((priv->last_rounded_mult - (2 * deltam_ceil)) < 20 ||
+ priv->last_rounded_mult > 2045)) ||
+ ((priv->last_rounded_mult - deltam_ceil) < 20 ||
+ (priv->last_rounded_mult + deltam_ceil) > 2045))
+ dev_warn(clk->dev,
+ "clock: SSC multiplier of DPLL %s is out of range\n",
+ clk->dev->name);
+
+ v = clk_ti_readl(&priv->ssc_deltam_reg);
+ v &= ~(CM_SSC_DELTAM_DPLL_INT_MASK | CM_SSC_DELTAM_DPLL_FRAC_MASK);
+ v |= deltam_step << __ffs(CM_SSC_DELTAM_DPLL_INT_MASK |
+ CM_SSC_DELTAM_DPLL_FRAC_MASK);
+ clk_ti_writel(v, &priv->ssc_deltam_reg);
+ dev_dbg(clk->dev,
+ "deltam_step: %u, deltam_ceil: %u, deltam_reg: 0x%x\n",
+ deltam_step, deltam_ceil, v);
+ } else {
+ ctrl &= ~CM_CLKMODE_DPLL_SSC_EN_MASK;
+ }
+
+ clk_ti_writel(ctrl, &priv->clkmode_reg);
+}
+
static ulong clk_ti_am3_dpll_set_rate(struct clk *clk, ulong rate)
{
struct clk_ti_am3_dpll_priv *priv = dev_get_priv(clk->dev);
@@ -136,6 +232,8 @@
clk_ti_writel(v, &priv->clksel_reg);
+ clk_ti_am3_dpll_ssc_program(clk);
+
/* lock dpll */
clk_ti_am3_dpll_clken(priv, DPLL_EN_LOCK);
@@ -229,6 +327,7 @@
struct clk_ti_am3_dpll_priv *priv = dev_get_priv(dev);
struct clk_ti_am3_dpll_drv_data *data =
(struct clk_ti_am3_dpll_drv_data *)dev_get_driver_data(dev);
+ u32 min_div;
int err;
priv->max_rate = data->max_rate;
@@ -251,6 +350,32 @@
return err;
}
+ err = clk_ti_get_reg_addr(dev, 3, &priv->ssc_deltam_reg);
+ if (err) {
+ dev_err(dev, "failed to get SSC deltam register\n");
+ return err;
+ }
+
+ err = clk_ti_get_reg_addr(dev, 4, &priv->ssc_modfreq_reg);
+ if (err) {
+ dev_err(dev, "failed to get SSC modfreq register\n");
+ return err;
+ }
+
+ if (dev_read_u32(dev, "ti,ssc-modfreq-hz", &priv->ssc_modfreq))
+ priv->ssc_modfreq = 0;
+
+ if (dev_read_u32(dev, "ti,ssc-deltam", &priv->ssc_deltam))
+ priv->ssc_deltam = 0;
+
+ priv->ssc_downspread = dev_read_bool(dev, "ti,ssc-downspread");
+
+ if (dev_read_u32(dev, "ti,min-div", &min_div) || min_div == 0 ||
+ min_div > 128)
+ priv->min_div = 1;
+ else
+ priv->min_div = min_div;
+
return 0;
}
diff --git a/drivers/core/device.c b/drivers/core/device.c
index 42ba2dc..d7a778a 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -1135,7 +1135,7 @@
if (ret)
return ret;
- return lists_bind_fdt(parent, node, NULL, false);
+ return lists_bind_fdt(parent, node, NULL, NULL, false);
}
#endif
diff --git a/drivers/core/fdtaddr.c b/drivers/core/fdtaddr.c
index 6dfda20..c3a50a2 100644
--- a/drivers/core/fdtaddr.c
+++ b/drivers/core/fdtaddr.c
@@ -93,6 +93,13 @@
#endif
}
+void *devfdt_get_addr_index_ptr(const struct udevice *dev, int index)
+{
+ fdt_addr_t addr = devfdt_get_addr_index(dev, index);
+
+ return (addr == FDT_ADDR_T_NONE) ? NULL : (void *)(uintptr_t)addr;
+}
+
fdt_addr_t devfdt_get_addr_size_index(const struct udevice *dev, int index,
fdt_size_t *size)
{
@@ -155,9 +162,7 @@
void *devfdt_get_addr_ptr(const struct udevice *dev)
{
- fdt_addr_t addr = devfdt_get_addr_index(dev, 0);
-
- return (addr == FDT_ADDR_T_NONE) ? NULL : (void *)(uintptr_t)addr;
+ return devfdt_get_addr_index_ptr(dev, 0);
}
void *devfdt_remap_addr_index(const struct udevice *dev, int index)
diff --git a/drivers/core/lists.c b/drivers/core/lists.c
index 350b9d3..5d4f2ea 100644
--- a/drivers/core/lists.c
+++ b/drivers/core/lists.c
@@ -182,7 +182,7 @@
}
int lists_bind_fdt(struct udevice *parent, ofnode node, struct udevice **devp,
- bool pre_reloc_only)
+ struct driver *drv, bool pre_reloc_only)
{
struct driver *driver = ll_entry_start(struct driver, driver);
const int n_ents = ll_entry_count(struct driver, driver);
@@ -225,6 +225,8 @@
for (entry = driver; entry != driver + n_ents; entry++) {
ret = driver_check_compatible(entry->of_match, &id,
compat);
+ if ((drv) && (drv == entry))
+ break;
if (!ret)
break;
}
diff --git a/drivers/core/root.c b/drivers/core/root.c
index fecdcb5..26b8195 100644
--- a/drivers/core/root.c
+++ b/drivers/core/root.c
@@ -276,7 +276,7 @@
pr_debug(" - ignoring disabled device\n");
continue;
}
- err = lists_bind_fdt(parent, node, NULL, pre_reloc_only);
+ err = lists_bind_fdt(parent, node, NULL, NULL, pre_reloc_only);
if (err && !ret) {
ret = err;
debug("%s: ret=%d\n", node_name, ret);
diff --git a/drivers/fastboot/fb_mmc.c b/drivers/fastboot/fb_mmc.c
index cbb3f7b..2738dc8 100644
--- a/drivers/fastboot/fb_mmc.c
+++ b/drivers/fastboot/fb_mmc.c
@@ -40,7 +40,7 @@
/* check for raw partition descriptor */
strcpy(env_desc_name, "fastboot_raw_partition_");
- strlcat(env_desc_name, name, PART_NAME_LEN);
+ strlcat(env_desc_name, name, sizeof(env_desc_name));
raw_part_desc = strdup(env_get(env_desc_name));
if (raw_part_desc == NULL)
return -ENODEV;
@@ -114,7 +114,7 @@
/* check for alias */
strcpy(env_alias_name, "fastboot_partition_alias_");
- strlcat(env_alias_name, name, PART_NAME_LEN);
+ strlcat(env_alias_name, name, sizeof(env_alias_name));
aliased_part_name = env_get(env_alias_name);
if (aliased_part_name != NULL)
ret = do_get_part_info(dev_desc, aliased_part_name,
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index f0439e2..40abc33 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -183,6 +183,14 @@
help
Support for the LPC32XX GPIO driver.
+config MAX7320_GPIO
+ bool "MAX7320 I2C GPIO Expander driver"
+ depends on DM_GPIO && DM_I2C
+ help
+ Support for MAX7320 I2C 8/16-bit GPIO expander.
+ original maxim device has 8 push/pull outputs,
+ some clones offers 16bit.
+
config MCP230XX_GPIO
bool "MCP230XX GPIO driver"
depends on DM
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index a9dc546..3c851b3 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -68,3 +68,4 @@
obj-$(CONFIG_NX_GPIO) += nx_gpio.o
obj-$(CONFIG_SIFIVE_GPIO) += sifive-gpio.o
obj-$(CONFIG_NOMADIK_GPIO) += nmk_gpio.o
+obj-$(CONFIG_MAX7320_GPIO) += max7320_gpio.o
diff --git a/drivers/gpio/axp_gpio.c b/drivers/gpio/axp_gpio.c
index 73058cf..35585dc 100644
--- a/drivers/gpio/axp_gpio.c
+++ b/drivers/gpio/axp_gpio.c
@@ -6,7 +6,6 @@
*/
#include <common.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/pmic_bus.h>
#include <asm/gpio.h>
#include <axp_pmic.h>
diff --git a/drivers/gpio/max7320_gpio.c b/drivers/gpio/max7320_gpio.c
new file mode 100644
index 0000000..647aed9
--- /dev/null
+++ b/drivers/gpio/max7320_gpio.c
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * max7320 I2C GPIO EXPANDER DRIVER
+ *
+ * Copyright (C) 2021 Hannes Schmelzer <oe5hpm@oevsv.at>
+ * B&R Industrial Automation GmbH - http://www.br-automation.com
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <i2c.h>
+#include <asm-generic/gpio.h>
+#include <linux/bitops.h>
+
+struct max7320_chip {
+ u32 outreg;
+};
+
+static int max7320_direction_output(struct udevice *dev,
+ unsigned int offset, int value)
+{
+ struct max7320_chip *plat = dev_get_plat(dev);
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct dm_i2c_chip *chip = dev_get_parent_plat(dev);
+
+ int ret;
+
+ if (value)
+ plat->outreg |= BIT(offset);
+ else
+ plat->outreg &= ~BIT(offset);
+
+ ret = dm_i2c_write(dev,
+ plat->outreg & 0xff,
+ (uint8_t *)&plat->outreg + 1,
+ uc_priv->gpio_count > 8 ? 1 : 0);
+ if (ret)
+ printf("%s i2c write failed to addr %x\n", __func__,
+ chip->chip_addr);
+
+ return ret;
+}
+
+static int max7320_get_value(struct udevice *dev, unsigned int offset)
+{
+ struct max7320_chip *plat = dev_get_plat(dev);
+
+ return (plat->outreg >> offset) & 0x1;
+}
+
+static int max7320_set_value(struct udevice *dev, unsigned int offset,
+ int value)
+{
+ return max7320_direction_output(dev, offset, value);
+}
+
+static int max7320_get_function(struct udevice *dev, unsigned int offset)
+{
+ return GPIOF_OUTPUT;
+}
+
+static int max7320_ofdata_plat(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ uc_priv->gpio_count = dev_read_u32_default(dev, "ngpios", 8);
+ if (uc_priv->gpio_count > 16) {
+ printf("%s: max7320 doesn't support more than 16 gpios!",
+ __func__);
+ return -EINVAL;
+ }
+
+ uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
+ "gpio-bank-name", NULL);
+ if (!uc_priv->bank_name)
+ uc_priv->bank_name = fdt_get_name(gd->fdt_blob,
+ dev_of_offset(dev), NULL);
+
+ return 0;
+}
+
+static int max7320_gpio_probe(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ debug("%s GPIO controller with %d gpios probed\n",
+ uc_priv->bank_name, uc_priv->gpio_count);
+
+ return 0;
+}
+
+static const struct dm_gpio_ops max7320_gpio_ops = {
+ .direction_output = max7320_direction_output,
+ .set_value = max7320_set_value,
+ .get_value = max7320_get_value,
+ .get_function = max7320_get_function,
+};
+
+static const struct udevice_id max7320_gpio_ids[] = {
+ { .compatible = "maxim,max7320" },
+ { }
+};
+
+U_BOOT_DRIVER(gpio_max7320) = {
+ .name = "gpio_max7320",
+ .id = UCLASS_GPIO,
+ .ops = &max7320_gpio_ops,
+ .of_match = max7320_gpio_ids,
+ .of_to_plat = max7320_ofdata_plat,
+ .probe = max7320_gpio_probe,
+ .plat_auto = sizeof(struct max7320_chip),
+};
diff --git a/drivers/gpio/sifive-gpio.c b/drivers/gpio/sifive-gpio.c
index abd1f62..151f484 100644
--- a/drivers/gpio/sifive-gpio.c
+++ b/drivers/gpio/sifive-gpio.c
@@ -157,13 +157,11 @@
static int sifive_gpio_of_to_plat(struct udevice *dev)
{
struct sifive_gpio_plat *plat = dev_get_plat(dev);
- fdt_addr_t addr;
- addr = dev_read_addr(dev);
- if (addr == FDT_ADDR_T_NONE)
+ plat->base = dev_read_addr_ptr(dev);
+ if (!plat->base)
return -EINVAL;
- plat->base = (void *)addr;
return 0;
}
diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
index 24cb604..cdbc40d 100644
--- a/drivers/gpio/sunxi_gpio.c
+++ b/drivers/gpio/sunxi_gpio.c
@@ -14,14 +14,11 @@
#include <errno.h>
#include <fdtdec.h>
#include <malloc.h>
-#include <asm/arch/gpio.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <dm/device-internal.h>
#include <dt-bindings/gpio/gpio.h>
-#define SUNXI_GPIOS_PER_BANK SUNXI_GPIO_A_NR
-
struct sunxi_gpio_plat {
struct sunxi_gpio *regs;
const char *bank_name; /* Name of bank, e.g. "B" */
@@ -118,20 +115,6 @@
}
#endif /* DM_GPIO */
-int sunxi_name_to_gpio_bank(const char *name)
-{
- int group = 0;
-
- if (*name == 'P' || *name == 'p')
- name++;
- if (*name >= 'A') {
- group = *name - (*name > 'a' ? 'a' : 'A');
- return group;
- }
-
- return -1;
-}
-
#if CONFIG_IS_ENABLED(DM_GPIO)
/* TODO(sjg@chromium.org): Remove this function and use device tree */
int sunxi_name_to_gpio(const char *name)
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 57cac44..7c447a8 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -575,6 +575,22 @@
_ Optional clock stretching
_ Software reset
+config SYS_I2C_SUN6I_P2WI
+ bool "Allwinner sun6i P2WI controller"
+ depends on ARCH_SUNXI
+ help
+ Support for the P2WI (Push/Pull 2 Wire Interface) controller embedded
+ in the Allwinner A31 and A31s SOCs. This interface is used to connect
+ to specific devices like the X-Powers AXP221 PMIC.
+
+config SYS_I2C_SUN8I_RSB
+ bool "Allwinner sun8i Reduced Serial Bus controller"
+ depends on ARCH_SUNXI
+ help
+ Support for Allwinner's Reduced Serial Bus (RSB) controller. This
+ controller is responsible for communicating with various RSB based
+ devices, such as X-Powers AXPxxx PMICs and AC100/AC200 CODEC ICs.
+
config SYS_I2C_SYNQUACER
bool "Socionext SynQuacer I2C controller"
depends on ARCH_SYNQUACER && DM_I2C
@@ -611,6 +627,12 @@
Add support for the Arm Ltd Versatile Express I2C driver. The I2C host
controller is present in the development boards manufactured by Arm Ltd.
+config SYS_I2C_MV
+ bool "Marvell PXA (Armada 3720) I2C driver"
+ help
+ Support for PXA based I2C controller used on Armada 3720 SoC.
+ In Linux, this driver is called i2c-pxa.
+
config SYS_I2C_MVTWSI
bool "Marvell I2C driver"
help
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 67841bf..fca6b15 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -10,7 +10,6 @@
obj-$(CONFIG_$(SPL_)I2C_CROS_EC_TUNNEL) += cros_ec_tunnel.o
obj-$(CONFIG_$(SPL_)I2C_CROS_EC_LDO) += cros_ec_ldo.o
-obj-$(CONFIG_I2C_MV) += mv_i2c.o
obj-$(CONFIG_$(SPL_)SYS_I2C_LEGACY) += i2c_core.o
obj-$(CONFIG_SYS_I2C_ASPEED) += ast_i2c.o
obj-$(CONFIG_SYS_I2C_AT91) += at91_i2c.o
@@ -29,6 +28,7 @@
obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o
obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o
obj-$(CONFIG_SYS_I2C_MESON) += meson_i2c.o
+obj-$(CONFIG_SYS_I2C_MV) += mv_i2c.o
obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o
obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
obj-$(CONFIG_SYS_I2C_NEXELL) += nx_i2c.o
@@ -43,6 +43,8 @@
obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
obj-$(CONFIG_SYS_I2C_STM32F7) += stm32f7_i2c.o
+obj-$(CONFIG_SYS_I2C_SUN6I_P2WI) += sun6i_p2wi.o
+obj-$(CONFIG_SYS_I2C_SUN8I_RSB) += sun8i_rsb.o
obj-$(CONFIG_SYS_I2C_SYNQUACER) += synquacer_i2c.o
obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o
diff --git a/drivers/i2c/ocores_i2c.c b/drivers/i2c/ocores_i2c.c
index f129ec3..3b19ba7 100644
--- a/drivers/i2c/ocores_i2c.c
+++ b/drivers/i2c/ocores_i2c.c
@@ -516,7 +516,7 @@
u32 clock_frequency_khz;
int ret;
- bus->base = (void __iomem *)devfdt_get_addr(dev);
+ bus->base = dev_read_addr_ptr(dev);
if (dev_read_u32(dev, "reg-shift", &bus->reg_shift)) {
/* no 'reg-shift', check for deprecated 'regstep' */
diff --git a/drivers/i2c/stm32f7_i2c.c b/drivers/i2c/stm32f7_i2c.c
index 7b04a09..c6ae65b 100644
--- a/drivers/i2c/stm32f7_i2c.c
+++ b/drivers/i2c/stm32f7_i2c.c
@@ -45,6 +45,8 @@
/* STM32 I2C control 1 */
#define STM32_I2C_CR1_ANFOFF BIT(12)
+#define STM32_I2C_CR1_DNF_MASK GENMASK(11, 8)
+#define STM32_I2C_CR1_DNF(n) (((n) & 0xf) << 8)
#define STM32_I2C_CR1_ERRIE BIT(7)
#define STM32_I2C_CR1_TCIE BIT(6)
#define STM32_I2C_CR1_STOPIE BIT(5)
@@ -105,10 +107,8 @@
#define STM32_I2C_MAX_LEN 0xff
-#define STM32_I2C_DNF_DEFAULT 0
-#define STM32_I2C_DNF_MAX 16
+#define STM32_I2C_DNF_MAX 15
-#define STM32_I2C_ANALOG_FILTER_ENABLE 1
#define STM32_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */
#define STM32_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */
@@ -156,9 +156,8 @@
* @clock_src: I2C clock source frequency (Hz)
* @rise_time: Rise time (ns)
* @fall_time: Fall time (ns)
- * @dnf: Digital filter coefficient (0-16)
+ * @dnf: value of digital filter to apply
* @analog_filter: Analog filter delay (On/Off)
- * @fmp_clr_offset: Fast Mode Plus clear register offset from set register
*/
struct stm32_i2c_setup {
u32 speed_freq;
@@ -167,6 +166,13 @@
u32 fall_time;
u8 dnf;
bool analog_filter;
+};
+
+/**
+ * struct stm32_i2c_data - driver data for I2C configuration by compatible
+ * @fmp_clr_offset: Fast Mode Plus clear register offset from set register
+ */
+struct stm32_i2c_data {
u32 fmp_clr_offset;
};
@@ -197,16 +203,18 @@
* @regmap_sreg: register address for setting Fast Mode Plus bits
* @regmap_creg: register address for clearing Fast Mode Plus bits
* @regmap_mask: mask for Fast Mode Plus bits
+ * @dnf_dt: value of digital filter requested via dt
*/
struct stm32_i2c_priv {
struct stm32_i2c_regs *regs;
struct clk clk;
- struct stm32_i2c_setup *setup;
+ struct stm32_i2c_setup setup;
u32 speed;
struct regmap *regmap;
u32 regmap_sreg;
u32 regmap_creg;
u32 regmap_mask;
+ u32 dnf_dt;
};
static const struct stm32_i2c_spec i2c_specs[] = {
@@ -251,18 +259,11 @@
},
};
-static const struct stm32_i2c_setup stm32f7_setup = {
- .rise_time = STM32_I2C_RISE_TIME_DEFAULT,
- .fall_time = STM32_I2C_FALL_TIME_DEFAULT,
- .dnf = STM32_I2C_DNF_DEFAULT,
- .analog_filter = STM32_I2C_ANALOG_FILTER_ENABLE,
+static const struct stm32_i2c_data stm32f7_data = {
+ .fmp_clr_offset = 0x00,
};
-static const struct stm32_i2c_setup stm32mp15_setup = {
- .rise_time = STM32_I2C_RISE_TIME_DEFAULT,
- .fall_time = STM32_I2C_FALL_TIME_DEFAULT,
- .dnf = STM32_I2C_DNF_DEFAULT,
- .analog_filter = STM32_I2C_ANALOG_FILTER_ENABLE,
+static const struct stm32_i2c_data stm32mp15_data = {
.fmp_clr_offset = 0x40,
};
@@ -506,14 +507,13 @@
return 0;
}
-static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup,
+static int stm32_i2c_compute_solutions(u32 i2cclk,
+ struct stm32_i2c_setup *setup,
const struct stm32_i2c_spec *specs,
struct list_head *solutions)
{
struct stm32_i2c_timings *v;
u32 p_prev = STM32_PRESC_MAX;
- u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
- setup->clock_src);
u32 af_delay_min, af_delay_max;
u16 p, l, a;
int sdadel_min, sdadel_max, scldel_min;
@@ -581,7 +581,8 @@
return ret;
}
-static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup,
+static int stm32_i2c_choose_solution(u32 i2cclk,
+ struct stm32_i2c_setup *setup,
const struct stm32_i2c_spec *specs,
struct list_head *solutions,
struct stm32_i2c_timings *s)
@@ -590,8 +591,6 @@
u32 i2cbus = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
setup->speed_freq);
u32 clk_error_prev = i2cbus;
- u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
- setup->clock_src);
u32 clk_min, clk_max;
u32 af_delay_min;
u32 dnf_delay;
@@ -678,12 +677,13 @@
}
static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv,
- struct stm32_i2c_setup *setup,
struct stm32_i2c_timings *output)
{
+ struct stm32_i2c_setup *setup = &i2c_priv->setup;
const struct stm32_i2c_spec *specs;
struct stm32_i2c_timings *v, *_v;
struct list_head solutions;
+ u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC, setup->clock_src);
int ret;
specs = get_specs(setup->speed_freq);
@@ -701,6 +701,8 @@
return -EINVAL;
}
+ /* Analog and Digital Filters */
+ setup->dnf = DIV_ROUND_CLOSEST(i2c_priv->dnf_dt, i2cclk);
if (setup->dnf > STM32_I2C_DNF_MAX) {
log_err("DNF out of bound %d/%d\n",
setup->dnf, STM32_I2C_DNF_MAX);
@@ -708,11 +710,11 @@
}
INIT_LIST_HEAD(&solutions);
- ret = stm32_i2c_compute_solutions(setup, specs, &solutions);
+ ret = stm32_i2c_compute_solutions(i2cclk, setup, specs, &solutions);
if (ret)
goto exit;
- ret = stm32_i2c_choose_solution(setup, specs, &solutions, output);
+ ret = stm32_i2c_choose_solution(i2cclk, setup, specs, &solutions, output);
if (ret)
goto exit;
@@ -745,7 +747,7 @@
static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv,
struct stm32_i2c_timings *timing)
{
- struct stm32_i2c_setup *setup = i2c_priv->setup;
+ struct stm32_i2c_setup *setup = &i2c_priv->setup;
int ret = 0;
setup->speed_freq = i2c_priv->speed;
@@ -757,7 +759,7 @@
}
do {
- ret = stm32_i2c_compute_timing(i2c_priv, setup, timing);
+ ret = stm32_i2c_compute_timing(i2c_priv, timing);
if (ret) {
log_debug("failed to compute I2C timings.\n");
if (setup->speed_freq > I2C_SPEED_STANDARD_RATE) {
@@ -839,10 +841,15 @@
writel(timing, ®s->timingr);
/* Enable I2C */
- if (i2c_priv->setup->analog_filter)
+ if (i2c_priv->setup.analog_filter)
clrbits_le32(®s->cr1, STM32_I2C_CR1_ANFOFF);
else
setbits_le32(®s->cr1, STM32_I2C_CR1_ANFOFF);
+
+ /* Program the Digital Filter */
+ clrsetbits_le32(®s->cr1, STM32_I2C_CR1_DNF_MASK,
+ STM32_I2C_CR1_DNF(i2c_priv->setup.dnf));
+
setbits_le32(®s->cr1, STM32_I2C_CR1_PE);
return 0;
@@ -903,21 +910,26 @@
static int stm32_of_to_plat(struct udevice *dev)
{
+ const struct stm32_i2c_data *data;
struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
u32 rise_time, fall_time;
int ret;
- i2c_priv->setup = (struct stm32_i2c_setup *)dev_get_driver_data(dev);
- if (!i2c_priv->setup)
+ data = (const struct stm32_i2c_data *)dev_get_driver_data(dev);
+ if (!data)
return -EINVAL;
- rise_time = dev_read_u32_default(dev, "i2c-scl-rising-time-ns", 0);
- if (rise_time)
- i2c_priv->setup->rise_time = rise_time;
+ rise_time = dev_read_u32_default(dev, "i2c-scl-rising-time-ns",
+ STM32_I2C_RISE_TIME_DEFAULT);
- fall_time = dev_read_u32_default(dev, "i2c-scl-falling-time-ns", 0);
- if (fall_time)
- i2c_priv->setup->fall_time = fall_time;
+ fall_time = dev_read_u32_default(dev, "i2c-scl-falling-time-ns",
+ STM32_I2C_FALL_TIME_DEFAULT);
+
+ i2c_priv->dnf_dt = dev_read_u32_default(dev, "i2c-digital-filter-width-ns", 0);
+ if (!dev_read_bool(dev, "i2c-digital-filter"))
+ i2c_priv->dnf_dt = 0;
+
+ i2c_priv->setup.analog_filter = dev_read_bool(dev, "i2c-analog-filter");
/* Optional */
i2c_priv->regmap = syscon_regmap_lookup_by_phandle(dev,
@@ -930,8 +942,7 @@
return ret;
i2c_priv->regmap_sreg = fmp[1];
- i2c_priv->regmap_creg = fmp[1] +
- i2c_priv->setup->fmp_clr_offset;
+ i2c_priv->regmap_creg = fmp[1] + data->fmp_clr_offset;
i2c_priv->regmap_mask = fmp[2];
}
@@ -944,8 +955,8 @@
};
static const struct udevice_id stm32_i2c_of_match[] = {
- { .compatible = "st,stm32f7-i2c", .data = (ulong)&stm32f7_setup },
- { .compatible = "st,stm32mp15-i2c", .data = (ulong)&stm32mp15_setup },
+ { .compatible = "st,stm32f7-i2c", .data = (ulong)&stm32f7_data },
+ { .compatible = "st,stm32mp15-i2c", .data = (ulong)&stm32mp15_data },
{}
};
diff --git a/drivers/i2c/sun6i_p2wi.c b/drivers/i2c/sun6i_p2wi.c
new file mode 100644
index 0000000..c9e1b3f
--- /dev/null
+++ b/drivers/i2c/sun6i_p2wi.c
@@ -0,0 +1,220 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Sunxi A31 Power Management Unit
+ *
+ * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
+ * http://linux-sunxi.org
+ *
+ * Based on sun6i sources and earlier U-Boot Allwinner A10 SPL work
+ *
+ * (C) Copyright 2006-2013
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Berg Xing <bergxing@allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ */
+
+#include <axp_pmic.h>
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <i2c.h>
+#include <time.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/p2wi.h>
+#include <asm/arch/prcm.h>
+#include <asm/arch/sys_proto.h>
+
+static int sun6i_p2wi_await_trans(struct sunxi_p2wi_reg *base)
+{
+ unsigned long tmo = timer_get_us() + 1000000;
+ int ret;
+ u8 reg;
+
+ while (1) {
+ reg = readl(&base->status);
+ if (reg & P2WI_STAT_TRANS_ERR) {
+ ret = -EIO;
+ break;
+ }
+ if (reg & P2WI_STAT_TRANS_DONE) {
+ ret = 0;
+ break;
+ }
+ if (timer_get_us() > tmo) {
+ ret = -ETIME;
+ break;
+ }
+ }
+ writel(reg, &base->status); /* Clear status bits */
+
+ return ret;
+}
+
+static int sun6i_p2wi_read(struct sunxi_p2wi_reg *base, const u8 addr, u8 *data)
+{
+ int ret;
+
+ writel(P2WI_DATADDR_BYTE_1(addr), &base->dataddr0);
+ writel(P2WI_DATA_NUM_BYTES(1) |
+ P2WI_DATA_NUM_BYTES_READ, &base->numbytes);
+ writel(P2WI_STAT_TRANS_DONE, &base->status);
+ writel(P2WI_CTRL_TRANS_START, &base->ctrl);
+
+ ret = sun6i_p2wi_await_trans(base);
+
+ *data = readl(&base->data0) & P2WI_DATA_BYTE_1_MASK;
+
+ return ret;
+}
+
+static int sun6i_p2wi_write(struct sunxi_p2wi_reg *base, const u8 addr, u8 data)
+{
+ writel(P2WI_DATADDR_BYTE_1(addr), &base->dataddr0);
+ writel(P2WI_DATA_BYTE_1(data), &base->data0);
+ writel(P2WI_DATA_NUM_BYTES(1), &base->numbytes);
+ writel(P2WI_STAT_TRANS_DONE, &base->status);
+ writel(P2WI_CTRL_TRANS_START, &base->ctrl);
+
+ return sun6i_p2wi_await_trans(base);
+}
+
+static int sun6i_p2wi_change_to_p2wi_mode(struct sunxi_p2wi_reg *base,
+ u8 slave_addr, u8 ctrl_reg,
+ u8 init_data)
+{
+ unsigned long tmo = timer_get_us() + 1000000;
+
+ writel(P2WI_PM_DEV_ADDR(slave_addr) |
+ P2WI_PM_CTRL_ADDR(ctrl_reg) |
+ P2WI_PM_INIT_DATA(init_data) |
+ P2WI_PM_INIT_SEND,
+ &base->pm);
+
+ while ((readl(&base->pm) & P2WI_PM_INIT_SEND)) {
+ if (timer_get_us() > tmo)
+ return -ETIME;
+ }
+
+ return 0;
+}
+
+static void sun6i_p2wi_init(struct sunxi_p2wi_reg *base)
+{
+ /* Enable p2wi and PIO clk, and de-assert their resets */
+ prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI);
+
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN6I_GPL0_R_P2WI_SCK);
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN6I_GPL1_R_P2WI_SDA);
+
+ /* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */
+ writel(P2WI_CTRL_RESET, &base->ctrl);
+ sdelay(0x100);
+ writel(P2WI_CC_SDA_OUT_DELAY(1) | P2WI_CC_CLK_DIV(8),
+ &base->cc);
+}
+
+#if IS_ENABLED(CONFIG_AXP_PMIC_BUS)
+int p2wi_read(const u8 addr, u8 *data)
+{
+ struct sunxi_p2wi_reg *base = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
+
+ return sun6i_p2wi_read(base, addr, data);
+}
+
+int p2wi_write(const u8 addr, u8 data)
+{
+ struct sunxi_p2wi_reg *base = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
+
+ return sun6i_p2wi_write(base, addr, data);
+}
+
+int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data)
+{
+ struct sunxi_p2wi_reg *base = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
+
+ return sun6i_p2wi_change_to_p2wi_mode(base, slave_addr, ctrl_reg,
+ init_data);
+}
+
+void p2wi_init(void)
+{
+ struct sunxi_p2wi_reg *base = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
+
+ sun6i_p2wi_init(base);
+}
+#endif
+
+#if CONFIG_IS_ENABLED(DM_I2C)
+struct sun6i_p2wi_priv {
+ struct sunxi_p2wi_reg *base;
+};
+
+static int sun6i_p2wi_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
+{
+ struct sun6i_p2wi_priv *priv = dev_get_priv(bus);
+
+ /* The hardware only supports SMBus-style transfers. */
+ if (nmsgs == 2 && msg[1].flags == I2C_M_RD && msg[1].len == 1)
+ return sun6i_p2wi_read(priv->base,
+ msg[0].buf[0], &msg[1].buf[0]);
+
+ if (nmsgs == 1 && msg[0].len == 2)
+ return sun6i_p2wi_write(priv->base,
+ msg[0].buf[0], msg[0].buf[1]);
+
+ return -EINVAL;
+}
+
+static int sun6i_p2wi_probe_chip(struct udevice *bus, uint chip_addr,
+ uint chip_flags)
+{
+ struct sun6i_p2wi_priv *priv = dev_get_priv(bus);
+
+ return sun6i_p2wi_change_to_p2wi_mode(priv->base, chip_addr,
+ AXP_PMIC_MODE_REG,
+ AXP_PMIC_MODE_P2WI);
+}
+
+static int sun6i_p2wi_probe(struct udevice *bus)
+{
+ struct sun6i_p2wi_priv *priv = dev_get_priv(bus);
+
+ priv->base = dev_read_addr_ptr(bus);
+
+ sun6i_p2wi_init(priv->base);
+
+ return 0;
+}
+
+static int sun6i_p2wi_child_pre_probe(struct udevice *child)
+{
+ struct dm_i2c_chip *chip = dev_get_parent_plat(child);
+
+ /* Ensure each transfer is for a single register. */
+ chip->flags |= DM_I2C_CHIP_RD_ADDRESS | DM_I2C_CHIP_WR_ADDRESS;
+
+ return 0;
+}
+
+static const struct dm_i2c_ops sun6i_p2wi_ops = {
+ .xfer = sun6i_p2wi_xfer,
+ .probe_chip = sun6i_p2wi_probe_chip,
+};
+
+static const struct udevice_id sun6i_p2wi_ids[] = {
+ { .compatible = "allwinner,sun6i-a31-p2wi" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(sun6i_p2wi) = {
+ .name = "sun6i_p2wi",
+ .id = UCLASS_I2C,
+ .of_match = sun6i_p2wi_ids,
+ .probe = sun6i_p2wi_probe,
+ .child_pre_probe = sun6i_p2wi_child_pre_probe,
+ .priv_auto = sizeof(struct sun6i_p2wi_priv),
+ .ops = &sun6i_p2wi_ops,
+};
+#endif /* CONFIG_IS_ENABLED(DM_I2C) */
diff --git a/drivers/i2c/sun8i_rsb.c b/drivers/i2c/sun8i_rsb.c
new file mode 100644
index 0000000..716b245
--- /dev/null
+++ b/drivers/i2c/sun8i_rsb.c
@@ -0,0 +1,281 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Based on allwinner u-boot sources rsb code which is:
+ * (C) Copyright 2007-2013
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * lixiang <lixiang@allwinnertech.com>
+ */
+
+#include <axp_pmic.h>
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <i2c.h>
+#include <time.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/prcm.h>
+#include <asm/arch/rsb.h>
+
+static int sun8i_rsb_await_trans(struct sunxi_rsb_reg *base)
+{
+ unsigned long tmo = timer_get_us() + 1000000;
+ u32 stat;
+ int ret;
+
+ while (1) {
+ stat = readl(&base->stat);
+ if (stat & RSB_STAT_LBSY_INT) {
+ ret = -EBUSY;
+ break;
+ }
+ if (stat & RSB_STAT_TERR_INT) {
+ ret = -EIO;
+ break;
+ }
+ if (stat & RSB_STAT_TOVER_INT) {
+ ret = 0;
+ break;
+ }
+ if (timer_get_us() > tmo) {
+ ret = -ETIME;
+ break;
+ }
+ }
+ writel(stat, &base->stat); /* Clear status bits */
+
+ return ret;
+}
+
+static int sun8i_rsb_do_trans(struct sunxi_rsb_reg *base)
+{
+ setbits_le32(&base->ctrl, RSB_CTRL_START_TRANS);
+
+ return sun8i_rsb_await_trans(base);
+}
+
+static int sun8i_rsb_read(struct sunxi_rsb_reg *base, u16 runtime_addr,
+ u8 reg_addr, u8 *data)
+{
+ int ret;
+
+ writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr), &base->devaddr);
+ writel(reg_addr, &base->addr);
+ writel(RSB_CMD_BYTE_READ, &base->cmd);
+
+ ret = sun8i_rsb_do_trans(base);
+ if (ret)
+ return ret;
+
+ *data = readl(&base->data) & 0xff;
+
+ return 0;
+}
+
+static int sun8i_rsb_write(struct sunxi_rsb_reg *base, u16 runtime_addr,
+ u8 reg_addr, u8 data)
+{
+ writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr), &base->devaddr);
+ writel(reg_addr, &base->addr);
+ writel(data, &base->data);
+ writel(RSB_CMD_BYTE_WRITE, &base->cmd);
+
+ return sun8i_rsb_do_trans(base);
+}
+
+static int sun8i_rsb_set_device_address(struct sunxi_rsb_reg *base,
+ u16 device_addr, u16 runtime_addr)
+{
+ writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr) |
+ RSB_DEVADDR_DEVICE_ADDR(device_addr), &base->devaddr);
+ writel(RSB_CMD_SET_RTSADDR, &base->cmd);
+
+ return sun8i_rsb_do_trans(base);
+}
+
+static void sun8i_rsb_cfg_io(void)
+{
+#ifdef CONFIG_MACH_SUN8I
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB);
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB);
+ sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
+ sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
+ sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
+ sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
+#elif defined CONFIG_MACH_SUN9I
+ sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB);
+ sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB);
+ sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
+ sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
+ sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
+ sunxi_gpio_set_drv(SUNXI_GPN(1), 2);
+#else
+#error unsupported MACH_SUNXI
+#endif
+}
+
+static void sun8i_rsb_set_clk(struct sunxi_rsb_reg *base)
+{
+ u32 div = 0;
+ u32 cd_odly = 0;
+
+ /* Source is Hosc24M, set RSB clk to 3Mhz */
+ div = 24000000 / 3000000 / 2 - 1;
+ cd_odly = div >> 1;
+ if (!cd_odly)
+ cd_odly = 1;
+
+ writel((cd_odly << 8) | div, &base->ccr);
+}
+
+static int sun8i_rsb_set_device_mode(struct sunxi_rsb_reg *base)
+{
+ unsigned long tmo = timer_get_us() + 1000000;
+
+ writel(RSB_DMCR_DEVICE_MODE_START | RSB_DMCR_DEVICE_MODE_DATA,
+ &base->dmcr);
+
+ while (readl(&base->dmcr) & RSB_DMCR_DEVICE_MODE_START) {
+ if (timer_get_us() > tmo)
+ return -ETIME;
+ }
+
+ return sun8i_rsb_await_trans(base);
+}
+
+static int sun8i_rsb_init(struct sunxi_rsb_reg *base)
+{
+ /* Enable RSB and PIO clk, and de-assert their resets */
+ prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB);
+
+ /* Setup external pins */
+ sun8i_rsb_cfg_io();
+
+ writel(RSB_CTRL_SOFT_RST, &base->ctrl);
+ sun8i_rsb_set_clk(base);
+
+ return sun8i_rsb_set_device_mode(base);
+}
+
+#if IS_ENABLED(CONFIG_AXP_PMIC_BUS)
+int rsb_read(const u16 runtime_addr, const u8 reg_addr, u8 *data)
+{
+ struct sunxi_rsb_reg *base = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+
+ return sun8i_rsb_read(base, runtime_addr, reg_addr, data);
+}
+
+int rsb_write(const u16 runtime_addr, const u8 reg_addr, u8 data)
+{
+ struct sunxi_rsb_reg *base = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+
+ return sun8i_rsb_write(base, runtime_addr, reg_addr, data);
+}
+
+int rsb_set_device_address(u16 device_addr, u16 runtime_addr)
+{
+ struct sunxi_rsb_reg *base = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+
+ return sun8i_rsb_set_device_address(base, device_addr, runtime_addr);
+}
+
+int rsb_init(void)
+{
+ struct sunxi_rsb_reg *base = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+
+ return sun8i_rsb_init(base);
+}
+#endif
+
+#if CONFIG_IS_ENABLED(DM_I2C)
+struct sun8i_rsb_priv {
+ struct sunxi_rsb_reg *base;
+};
+
+/*
+ * The mapping from hardware address to runtime address is fixed, and shared
+ * among all RSB drivers. See the comment in drivers/bus/sunxi-rsb.c in Linux.
+ */
+static int sun8i_rsb_get_runtime_address(u16 device_addr)
+{
+ if (device_addr == AXP_PMIC_PRI_DEVICE_ADDR)
+ return AXP_PMIC_PRI_RUNTIME_ADDR;
+ if (device_addr == AXP_PMIC_SEC_DEVICE_ADDR)
+ return AXP_PMIC_SEC_RUNTIME_ADDR;
+
+ return -ENXIO;
+}
+
+static int sun8i_rsb_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
+{
+ int runtime_addr = sun8i_rsb_get_runtime_address(msg->addr);
+ struct sun8i_rsb_priv *priv = dev_get_priv(bus);
+
+ if (runtime_addr < 0)
+ return runtime_addr;
+
+ /* The hardware only supports SMBus-style transfers. */
+ if (nmsgs == 2 && msg[1].flags == I2C_M_RD && msg[1].len == 1)
+ return sun8i_rsb_read(priv->base, runtime_addr,
+ msg[0].buf[0], &msg[1].buf[0]);
+
+ if (nmsgs == 1 && msg[0].len == 2)
+ return sun8i_rsb_write(priv->base, runtime_addr,
+ msg[0].buf[0], msg[0].buf[1]);
+
+ return -EINVAL;
+}
+
+static int sun8i_rsb_probe_chip(struct udevice *bus, uint chip_addr,
+ uint chip_flags)
+{
+ int runtime_addr = sun8i_rsb_get_runtime_address(chip_addr);
+ struct sun8i_rsb_priv *priv = dev_get_priv(bus);
+
+ if (runtime_addr < 0)
+ return runtime_addr;
+
+ return sun8i_rsb_set_device_address(priv->base, chip_addr, runtime_addr);
+}
+
+static int sun8i_rsb_probe(struct udevice *bus)
+{
+ struct sun8i_rsb_priv *priv = dev_get_priv(bus);
+
+ priv->base = dev_read_addr_ptr(bus);
+
+ return sun8i_rsb_init(priv->base);
+}
+
+static int sun8i_rsb_child_pre_probe(struct udevice *child)
+{
+ struct dm_i2c_chip *chip = dev_get_parent_plat(child);
+
+ /* Ensure each transfer is for a single register. */
+ chip->flags |= DM_I2C_CHIP_RD_ADDRESS | DM_I2C_CHIP_WR_ADDRESS;
+
+ return 0;
+}
+
+static const struct dm_i2c_ops sun8i_rsb_ops = {
+ .xfer = sun8i_rsb_xfer,
+ .probe_chip = sun8i_rsb_probe_chip,
+};
+
+static const struct udevice_id sun8i_rsb_ids[] = {
+ { .compatible = "allwinner,sun8i-a23-rsb" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(sun8i_rsb) = {
+ .name = "sun8i_rsb",
+ .id = UCLASS_I2C,
+ .of_match = sun8i_rsb_ids,
+ .probe = sun8i_rsb_probe,
+ .child_pre_probe = sun8i_rsb_child_pre_probe,
+ .priv_auto = sizeof(struct sun8i_rsb_priv),
+ .ops = &sun8i_rsb_ops,
+};
+#endif /* CONFIG_IS_ENABLED(DM_I2C) */
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 099ff29..3bae072 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -233,6 +233,15 @@
Programmable memory pages that are stored on the some
Freescale i.MX processors.
+config SPL_MXC_OCOTP
+ bool "Enable MXC OCOTP driver in SPL"
+ depends on SPL && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610)
+ default y
+ help
+ If you say Y here, you will get support for the One Time
+ Programmable memory pages, that are stored on some
+ Freescale i.MX processors, in SPL.
+
config NUVOTON_NCT6102D
bool "Enable Nuvoton NCT6102D Super I/O driver"
help
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index c16a77c..f9826d2 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -50,7 +50,7 @@
obj-$(CONFIG_LED_STATUS) += status_led.o
obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o
obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o
-obj-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o
+obj-$(CONFIG_$(SPL_)MXC_OCOTP) += mxc_ocotp.o
obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o
obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o
obj-$(CONFIG_P2SB) += p2sb-uclass.o
diff --git a/drivers/misc/imx8/scu.c b/drivers/misc/imx8/scu.c
index 035a600..4ab5cb4 100644
--- a/drivers/misc/imx8/scu.c
+++ b/drivers/misc/imx8/scu.c
@@ -219,7 +219,7 @@
debug("%s(dev=%p)\n", __func__, dev);
ofnode_for_each_subnode(node, dev_ofnode(dev)) {
- ret = lists_bind_fdt(dev, node, &child, true);
+ ret = lists_bind_fdt(dev, node, &child, NULL, true);
if (ret)
return ret;
debug("bind child dev %s\n", child->name);
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 5dfd484..4c06361 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -727,17 +727,20 @@
if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
esdhc_write32(®s->strobe_dllctrl, ESDHC_STROBE_DLL_CTRL_RESET);
+ /* clear the reset bit on strobe dll before any setting */
+ esdhc_write32(®s->strobe_dllctrl, 0);
/*
* enable strobe dll ctrl and adjust the delay target
* for the uSDHC loopback read clock
*/
val = ESDHC_STROBE_DLL_CTRL_ENABLE |
+ ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT |
(priv->strobe_dll_delay_target <<
ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
esdhc_write32(®s->strobe_dllctrl, val);
- /* wait 1us to make sure strobe dll status register stable */
- mdelay(1);
+ /* wait 5us to make sure strobe dll status register stable */
+ mdelay(5);
val = esdhc_read32(®s->strobe_dllstat);
if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK))
pr_warn("HS400 strobe DLL status REF not lock!\n");
@@ -971,7 +974,6 @@
if (priv->clock != clock)
set_sysctl(priv, mmc, clock);
-#ifdef MMC_SUPPORTS_TUNING
if (mmc->clk_disable) {
#ifdef CONFIG_FSL_USDHC
esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
@@ -987,6 +989,7 @@
#endif
}
+#ifdef MMC_SUPPORTS_TUNING
/*
* For HS400/HS400ES mode, make sure set the strobe dll in the
* target clock rate. So call esdhc_set_strobe_dll() after the
@@ -1707,6 +1710,12 @@
| ESDHC_FLAG_HS400,
};
+static struct esdhc_soc_data usdhc_imx7ulp_data = {
+ .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
+ | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
+ | ESDHC_FLAG_HS400,
+};
+
static struct esdhc_soc_data usdhc_imx8qm_data = {
.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING |
ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 |
@@ -1721,7 +1730,7 @@
{ .compatible = "fsl,imx6sl-usdhc", },
{ .compatible = "fsl,imx6q-usdhc", },
{ .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,},
- { .compatible = "fsl,imx7ulp-usdhc", },
+ { .compatible = "fsl,imx7ulp-usdhc", .data = (ulong)&usdhc_imx7ulp_data,},
{ .compatible = "fsl,imx8qm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
{ .compatible = "fsl,imx8mm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
{ .compatible = "fsl,imx8mn-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index 1ac0058..2784738 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -143,6 +143,9 @@
writel(RK_CLRSETBITS(3 << 12, freqsel << 12), &phy->emmcphy_con[0]);
writel(RK_CLRSETBITS(1 << 1, 1 << 1), &phy->emmcphy_con[6]);
+ /* REN Enable on STRB Line for HS400 */
+ writel(RK_CLRSETBITS(0, 1 << 9), &phy->emmcphy_con[2]);
+
read_poll_timeout(readl, &phy->emmcphy_status, dllrdy,
PHYCTRL_DLL_LOCK_WO_TMOUT(dllrdy), 1, 5000);
}
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index aaab0cf..c170c16 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -15,12 +15,11 @@
#include <mmc.h>
#include <clk.h>
#include <reset.h>
+#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/cpu.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
-#include <asm-generic/gpio.h>
#include <linux/delay.h>
#ifndef CCM_MMC_CTRL_MODE_SEL_NEW
diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
index 83c055a..a9c8c48 100644
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -109,6 +109,13 @@
This is the driver for HyperBus controller on TI's AM65x and
other SoCs
+config STM32_FLASH
+ bool "STM32 MCU Flash driver"
+ depends on ARCH_STM32
+ help
+ This is the driver of embedded flash for some STMicroelectronics
+ STM32 MCU.
+
source "drivers/mtd/nand/Kconfig"
config SYS_NAND_MAX_CHIPS
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index 790ee34..cb0c0a1 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -369,7 +369,7 @@
imply CMD_NAND
help
This enables the NAND driver for the NAND flash controller on the
- i.MX27 / i.MX31 / i.MX5 rocessors.
+ i.MX27 / i.MX31 / i.MX5 processors.
config NAND_MXS
bool "MXS NAND support"
@@ -398,6 +398,12 @@
endif
+config NAND_MXIC
+ bool "Macronix raw NAND controller"
+ select SYS_NAND_SELF_INIT
+ help
+ This selects the Macronix raw NAND controller driver.
+
config NAND_ZYNQ
bool "Support for Zynq Nand controller"
select SYS_NAND_SELF_INIT
diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
index a5ed2c5..6ec3581 100644
--- a/drivers/mtd/nand/raw/Makefile
+++ b/drivers/mtd/nand/raw/Makefile
@@ -67,6 +67,7 @@
obj-$(CONFIG_NAND_OMAP_ELM) += omap_elm.o
obj-$(CONFIG_NAND_PLAT) += nand_plat.o
obj-$(CONFIG_NAND_SUNXI) += sunxi_nand.o
+obj-$(CONFIG_NAND_MXIC) += mxic_nand.o
obj-$(CONFIG_NAND_ZYNQ) += zynq_nand.o
obj-$(CONFIG_NAND_STM32_FMC2) += stm32_fmc2_nand.o
obj-$(CONFIG_CORTINA_NAND) += cortina_nand.o
diff --git a/drivers/mtd/nand/raw/mxic_nand.c b/drivers/mtd/nand/raw/mxic_nand.c
new file mode 100644
index 0000000..e54df46
--- /dev/null
+++ b/drivers/mtd/nand/raw/mxic_nand.c
@@ -0,0 +1,603 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Macronix International Co., Ltd.
+ *
+ * Author:
+ * Zhengxun Li <zhengxunli@mxic.com.tw>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <malloc.h>
+#include <nand.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <dm/device_compat.h>
+#include <linux/bug.h>
+#include <linux/errno.h>
+#include <linux/iopoll.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/rawnand.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/delay.h>
+
+#define HC_CFG 0x0
+#define HC_CFG_IF_CFG(x) ((x) << 27)
+#define HC_CFG_DUAL_SLAVE BIT(31)
+#define HC_CFG_INDIVIDUAL BIT(30)
+#define HC_CFG_NIO(x) (((x) / 4) << 27)
+#define HC_CFG_TYPE(s, t) ((t) << (23 + ((s) * 2)))
+#define HC_CFG_TYPE_SPI_NOR 0
+#define HC_CFG_TYPE_SPI_NAND 1
+#define HC_CFG_TYPE_SPI_RAM 2
+#define HC_CFG_TYPE_RAW_NAND 3
+#define HC_CFG_SLV_ACT(x) ((x) << 21)
+#define HC_CFG_CLK_PH_EN BIT(20)
+#define HC_CFG_CLK_POL_INV BIT(19)
+#define HC_CFG_BIG_ENDIAN BIT(18)
+#define HC_CFG_DATA_PASS BIT(17)
+#define HC_CFG_IDLE_SIO_LVL(x) ((x) << 16)
+#define HC_CFG_MAN_START_EN BIT(3)
+#define HC_CFG_MAN_START BIT(2)
+#define HC_CFG_MAN_CS_EN BIT(1)
+#define HC_CFG_MAN_CS_ASSERT BIT(0)
+
+#define INT_STS 0x4
+#define INT_STS_EN 0x8
+#define INT_SIG_EN 0xc
+#define INT_STS_ALL GENMASK(31, 0)
+#define INT_RDY_PIN BIT(26)
+#define INT_RDY_SR BIT(25)
+#define INT_LNR_SUSP BIT(24)
+#define INT_ECC_ERR BIT(17)
+#define INT_CRC_ERR BIT(16)
+#define INT_LWR_DIS BIT(12)
+#define INT_LRD_DIS BIT(11)
+#define INT_SDMA_INT BIT(10)
+#define INT_DMA_FINISH BIT(9)
+#define INT_RX_NOT_FULL BIT(3)
+#define INT_RX_NOT_EMPTY BIT(2)
+#define INT_TX_NOT_FULL BIT(1)
+#define INT_TX_EMPTY BIT(0)
+
+#define HC_EN 0x10
+#define HC_EN_BIT BIT(0)
+
+#define TXD(x) (0x14 + ((x) * 4))
+#define RXD 0x24
+
+#define SS_CTRL(s) (0x30 + ((s) * 4))
+#define LRD_CFG 0x44
+#define LWR_CFG 0x80
+#define RWW_CFG 0x70
+#define OP_READ BIT(23)
+#define OP_DUMMY_CYC(x) ((x) << 17)
+#define OP_ADDR_BYTES(x) ((x) << 14)
+#define OP_CMD_BYTES(x) (((x) - 1) << 13)
+#define OP_OCTA_CRC_EN BIT(12)
+#define OP_DQS_EN BIT(11)
+#define OP_ENHC_EN BIT(10)
+#define OP_PREAMBLE_EN BIT(9)
+#define OP_DATA_DDR BIT(8)
+#define OP_DATA_BUSW(x) ((x) << 6)
+#define OP_ADDR_DDR BIT(5)
+#define OP_ADDR_BUSW(x) ((x) << 3)
+#define OP_CMD_DDR BIT(2)
+#define OP_CMD_BUSW(x) (x)
+#define OP_BUSW_1 0
+#define OP_BUSW_2 1
+#define OP_BUSW_4 2
+#define OP_BUSW_8 3
+
+#define OCTA_CRC 0x38
+#define OCTA_CRC_IN_EN(s) BIT(3 + ((s) * 16))
+#define OCTA_CRC_CHUNK(s, x) ((fls((x) / 32)) << (1 + ((s) * 16)))
+#define OCTA_CRC_OUT_EN(s) BIT(0 + ((s) * 16))
+
+#define ONFI_DIN_CNT(s) (0x3c + (s))
+
+#define LRD_CTRL 0x48
+#define RWW_CTRL 0x74
+#define LWR_CTRL 0x84
+#define LMODE_EN BIT(31)
+#define LMODE_SLV_ACT(x) ((x) << 21)
+#define LMODE_CMD1(x) ((x) << 8)
+#define LMODE_CMD0(x) (x)
+
+#define LRD_ADDR 0x4c
+#define LWR_ADDR 0x88
+#define LRD_RANGE 0x50
+#define LWR_RANGE 0x8c
+
+#define AXI_SLV_ADDR 0x54
+
+#define DMAC_RD_CFG 0x58
+#define DMAC_WR_CFG 0x94
+#define DMAC_CFG_PERIPH_EN BIT(31)
+#define DMAC_CFG_ALLFLUSH_EN BIT(30)
+#define DMAC_CFG_LASTFLUSH_EN BIT(29)
+#define DMAC_CFG_QE(x) (((x) + 1) << 16)
+#define DMAC_CFG_BURST_LEN(x) (((x) + 1) << 12)
+#define DMAC_CFG_BURST_SZ(x) ((x) << 8)
+#define DMAC_CFG_DIR_READ BIT(1)
+#define DMAC_CFG_START BIT(0)
+
+#define DMAC_RD_CNT 0x5c
+#define DMAC_WR_CNT 0x98
+
+#define SDMA_ADDR 0x60
+
+#define DMAM_CFG 0x64
+#define DMAM_CFG_START BIT(31)
+#define DMAM_CFG_CONT BIT(30)
+#define DMAM_CFG_SDMA_GAP(x) (fls((x) / 8192) << 2)
+#define DMAM_CFG_DIR_READ BIT(1)
+#define DMAM_CFG_EN BIT(0)
+
+#define DMAM_CNT 0x68
+
+#define LNR_TIMER_TH 0x6c
+
+#define RDM_CFG0 0x78
+#define RDM_CFG0_POLY(x) (x)
+
+#define RDM_CFG1 0x7c
+#define RDM_CFG1_RDM_EN BIT(31)
+#define RDM_CFG1_SEED(x) (x)
+
+#define LWR_SUSP_CTRL 0x90
+#define LWR_SUSP_CTRL_EN BIT(31)
+
+#define DMAS_CTRL 0x9c
+#define DMAS_CTRL_EN BIT(31)
+#define DMAS_CTRL_DIR_READ BIT(30)
+
+#define DATA_STROB 0xa0
+#define DATA_STROB_EDO_EN BIT(2)
+#define DATA_STROB_INV_POL BIT(1)
+#define DATA_STROB_DELAY_2CYC BIT(0)
+
+#define IDLY_CODE(x) (0xa4 + ((x) * 4))
+#define IDLY_CODE_VAL(x, v) ((v) << (((x) % 4) * 8))
+
+#define GPIO 0xc4
+#define GPIO_PT(x) BIT(3 + ((x) * 16))
+#define GPIO_RESET(x) BIT(2 + ((x) * 16))
+#define GPIO_HOLDB(x) BIT(1 + ((x) * 16))
+#define GPIO_WPB(x) BIT((x) * 16)
+
+#define HC_VER 0xd0
+
+#define HW_TEST(x) (0xe0 + ((x) * 4))
+
+#define MXIC_NFC_MAX_CLK_HZ 50000000
+#define IRQ_TIMEOUT 1000
+
+struct mxic_nand_ctrl {
+ struct clk *send_clk;
+ struct clk *send_dly_clk;
+ void __iomem *regs;
+ struct nand_chip nand_chip;
+};
+
+/*
+ * struct mxic_nfc_command_format - Defines NAND flash command format
+ * @start_cmd: First cycle command (Start command)
+ * @end_cmd: Second cycle command (Last command)
+ * @addr_len: Number of address cycles required to send the address
+ * @read: Direction of command
+ */
+
+struct mxic_nfc_command_format {
+ int start_cmd;
+ int end_cmd;
+ u8 addr_len;
+ bool read;
+};
+
+/* The NAND flash operations command format */
+static const struct mxic_nfc_command_format mxic_nand_commands[] = {
+ {NAND_CMD_READ0, NAND_CMD_READSTART, 5, 1 },
+ {NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART, 2, 1 },
+ {NAND_CMD_READID, NAND_CMD_NONE, 1, 1 },
+ {NAND_CMD_STATUS, NAND_CMD_NONE, 0, 1 },
+ {NAND_CMD_SEQIN, NAND_CMD_NONE, 5, 0 },
+ {NAND_CMD_PAGEPROG, NAND_CMD_NONE, 0, 0 },
+ {NAND_CMD_CACHEDPROG, NAND_CMD_NONE, 0, 0 },
+ {NAND_CMD_RNDIN, NAND_CMD_NONE, 2, 0 },
+ {NAND_CMD_ERASE1, NAND_CMD_NONE, 3, 0 },
+ {NAND_CMD_ERASE2, NAND_CMD_NONE, 0, 0 },
+ {NAND_CMD_RESET, NAND_CMD_NONE, 0, 0 },
+ {NAND_CMD_PARAM, NAND_CMD_NONE, 1, 1 },
+ {NAND_CMD_GET_FEATURES, NAND_CMD_NONE, 1, 1 },
+ {NAND_CMD_SET_FEATURES, NAND_CMD_NONE, 1, 0 },
+ {NAND_CMD_NONE, NAND_CMD_NONE, 0, 0 },
+};
+
+static int mxic_nfc_clk_enable(struct mxic_nand_ctrl *nfc)
+{
+ int ret;
+
+ ret = clk_prepare_enable(nfc->send_clk);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(nfc->send_dly_clk);
+ if (ret)
+ goto err_send_dly_clk;
+
+ return ret;
+
+err_send_dly_clk:
+ clk_disable_unprepare(nfc->send_clk);
+
+ return ret;
+}
+
+static void mxic_nfc_clk_disable(struct mxic_nand_ctrl *nfc)
+{
+ clk_disable_unprepare(nfc->send_clk);
+ clk_disable_unprepare(nfc->send_dly_clk);
+}
+
+static void mxic_nfc_set_input_delay(struct mxic_nand_ctrl *nfc, u8 idly_code)
+{
+ writel(IDLY_CODE_VAL(0, idly_code) |
+ IDLY_CODE_VAL(1, idly_code) |
+ IDLY_CODE_VAL(2, idly_code) |
+ IDLY_CODE_VAL(3, idly_code),
+ nfc->regs + IDLY_CODE(0));
+ writel(IDLY_CODE_VAL(4, idly_code) |
+ IDLY_CODE_VAL(5, idly_code) |
+ IDLY_CODE_VAL(6, idly_code) |
+ IDLY_CODE_VAL(7, idly_code),
+ nfc->regs + IDLY_CODE(1));
+}
+
+static int mxic_nfc_clk_setup(struct mxic_nand_ctrl *nfc, unsigned long freq)
+{
+ int ret;
+
+ ret = clk_set_rate(nfc->send_clk, freq);
+ if (ret)
+ return ret;
+
+ ret = clk_set_rate(nfc->send_dly_clk, freq);
+ if (ret)
+ return ret;
+
+ /*
+ * A constant delay range from 0x0 ~ 0x1F for input delay,
+ * the unit is 78 ps, the max input delay is 2.418 ns.
+ */
+ mxic_nfc_set_input_delay(nfc, 0xf);
+
+ return 0;
+}
+
+static int mxic_nfc_set_freq(struct mxic_nand_ctrl *nfc, unsigned long freq)
+{
+ int ret;
+
+ if (freq > MXIC_NFC_MAX_CLK_HZ)
+ freq = MXIC_NFC_MAX_CLK_HZ;
+
+ mxic_nfc_clk_disable(nfc);
+ ret = mxic_nfc_clk_setup(nfc, freq);
+ if (ret)
+ return ret;
+
+ ret = mxic_nfc_clk_enable(nfc);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static void mxic_nfc_hw_init(struct mxic_nand_ctrl *nfc)
+{
+ writel(HC_CFG_NIO(8) | HC_CFG_TYPE(1, HC_CFG_TYPE_RAW_NAND) |
+ HC_CFG_SLV_ACT(0) | HC_CFG_MAN_CS_EN |
+ HC_CFG_IDLE_SIO_LVL(1), nfc->regs + HC_CFG);
+ writel(INT_STS_ALL, nfc->regs + INT_STS_EN);
+ writel(INT_RDY_PIN, nfc->regs + INT_SIG_EN);
+ writel(0x0, nfc->regs + ONFI_DIN_CNT(0));
+ writel(0, nfc->regs + LRD_CFG);
+ writel(0, nfc->regs + LRD_CTRL);
+ writel(0x0, nfc->regs + HC_EN);
+}
+
+static void mxic_nfc_cs_enable(struct mxic_nand_ctrl *nfc)
+{
+ writel(readl(nfc->regs + HC_CFG) | HC_CFG_MAN_CS_EN,
+ nfc->regs + HC_CFG);
+ writel(HC_CFG_MAN_CS_ASSERT | readl(nfc->regs + HC_CFG),
+ nfc->regs + HC_CFG);
+}
+
+static void mxic_nfc_cs_disable(struct mxic_nand_ctrl *nfc)
+{
+ writel(~HC_CFG_MAN_CS_ASSERT & readl(nfc->regs + HC_CFG),
+ nfc->regs + HC_CFG);
+}
+
+static int mxic_nfc_data_xfer(struct mxic_nand_ctrl *nfc, const void *txbuf,
+ void *rxbuf, unsigned int len)
+{
+ unsigned int pos = 0;
+
+ while (pos < len) {
+ unsigned int nbytes = len - pos;
+ u32 data = 0xffffffff;
+ u32 sts;
+ int ret;
+
+ if (nbytes > 4)
+ nbytes = 4;
+
+ if (txbuf)
+ memcpy(&data, txbuf + pos, nbytes);
+
+ ret = readl_poll_timeout(nfc->regs + INT_STS, sts,
+ sts & INT_TX_EMPTY, 1000000);
+ if (ret)
+ return ret;
+
+ writel(data, nfc->regs + TXD(nbytes % 4));
+
+ ret = readl_poll_timeout(nfc->regs + INT_STS, sts,
+ sts & INT_TX_EMPTY, 1000000);
+ if (ret)
+ return ret;
+
+ ret = readl_poll_timeout(nfc->regs + INT_STS, sts,
+ sts & INT_RX_NOT_EMPTY, 1000000);
+ if (ret)
+ return ret;
+
+ data = readl(nfc->regs + RXD);
+ if (rxbuf) {
+ data >>= (8 * (4 - nbytes));
+ memcpy(rxbuf + pos, &data, nbytes);
+ }
+
+ WARN_ON(readl(nfc->regs + INT_STS) & INT_RX_NOT_EMPTY);
+
+ pos += nbytes;
+ }
+
+ return 0;
+}
+
+static uint8_t mxic_nfc_read_byte(struct mtd_info *mtd)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct mxic_nand_ctrl *nfc = nand_get_controller_data(chip);
+ u8 data;
+
+ writel(0x0, nfc->regs + ONFI_DIN_CNT(0));
+ writel(OP_DATA_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) |
+ OP_READ, nfc->regs + SS_CTRL(0));
+
+ mxic_nfc_data_xfer(nfc, NULL, &data, 1);
+
+ return data;
+}
+
+static void mxic_nfc_read_buf(struct mtd_info *mtd, uint8_t *rxbuf, int rlen)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct mxic_nand_ctrl *nfc = nand_get_controller_data(chip);
+
+ writel(0x0, nfc->regs + ONFI_DIN_CNT(0));
+ writel(OP_DATA_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) |
+ OP_READ, nfc->regs + SS_CTRL(0));
+
+ mxic_nfc_data_xfer(nfc, NULL, rxbuf, rlen);
+}
+
+static void mxic_nfc_write_buf(struct mtd_info *mtd, const uint8_t *txbuf,
+ int wlen)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct mxic_nand_ctrl *nfc = nand_get_controller_data(chip);
+
+ writel(wlen, nfc->regs + ONFI_DIN_CNT(0));
+ writel(OP_DATA_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F),
+ nfc->regs + SS_CTRL(0));
+
+ mxic_nfc_data_xfer(nfc, txbuf, NULL, wlen);
+}
+
+static void mxic_nfc_cmd_function(struct mtd_info *mtd, unsigned int command,
+ int column, int page_addr)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct mxic_nand_ctrl *nfc = nand_get_controller_data(chip);
+ const struct mxic_nfc_command_format *cmd = NULL;
+ u32 sts;
+ u8 index, addr[5];
+
+ /* Emulate NAND_CMD_READOOB */
+ if (command == NAND_CMD_READOOB) {
+ column += mtd->writesize;
+ command = NAND_CMD_READ0;
+ }
+
+ /* Get the command format */
+ for (index = 0; index < ARRAY_SIZE(mxic_nand_commands); index++)
+ if (command == mxic_nand_commands[index].start_cmd)
+ break;
+
+ cmd = &mxic_nand_commands[index];
+
+ if (!(command == NAND_CMD_PAGEPROG ||
+ command == NAND_CMD_CACHEDPROG ||
+ command == NAND_CMD_ERASE2))
+ mxic_nfc_cs_disable(nfc);
+
+ mxic_nfc_cs_enable(nfc);
+
+ if (column != -1) {
+ addr[0] = column;
+ addr[1] = column >> 8;
+
+ if (page_addr != -1) {
+ addr[2] = page_addr;
+ addr[3] = page_addr >> 8;
+ addr[4] = page_addr >> 16;
+ }
+ } else if (page_addr != -1) {
+ addr[0] = page_addr;
+ addr[1] = page_addr >> 8;
+ addr[2] = page_addr >> 16;
+ }
+
+ writel(0, nfc->regs + HC_EN);
+ writel(HC_EN_BIT, nfc->regs + HC_EN);
+ writel(OP_CMD_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) | OP_CMD_BYTES(0),
+ nfc->regs + SS_CTRL(0));
+
+ mxic_nfc_data_xfer(nfc, &cmd->start_cmd, NULL, 1);
+
+ if (cmd->addr_len) {
+ writel(OP_ADDR_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) |
+ OP_ADDR_BYTES(cmd->addr_len), nfc->regs + SS_CTRL(0));
+
+ mxic_nfc_data_xfer(nfc, &addr, NULL, cmd->addr_len);
+ }
+
+ if (cmd->end_cmd != NAND_CMD_NONE) {
+ writel(0, nfc->regs + HC_EN);
+ writel(HC_EN_BIT, nfc->regs + HC_EN);
+ writel(OP_CMD_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) |
+ OP_CMD_BYTES(0), nfc->regs + SS_CTRL(0));
+
+ mxic_nfc_data_xfer(nfc, &cmd->end_cmd, NULL, 1);
+ }
+
+ readl_poll_timeout(nfc->regs + INT_STS, sts, sts & INT_RDY_PIN,
+ 1000000);
+
+ if (command == NAND_CMD_PAGEPROG ||
+ command == NAND_CMD_CACHEDPROG ||
+ command == NAND_CMD_ERASE2 ||
+ command == NAND_CMD_RESET) {
+ mxic_nfc_cs_disable(nfc);
+ }
+}
+
+static int mxic_nfc_setup_data_interface(struct mtd_info *mtd, int chipnr,
+ const struct nand_data_interface *conf)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct mxic_nand_ctrl *nfc = nand_get_controller_data(chip);
+ const struct nand_sdr_timings *sdr;
+ unsigned long freq;
+ int ret;
+
+ sdr = nand_get_sdr_timings(conf);
+ if (IS_ERR(sdr))
+ return PTR_ERR(sdr);
+
+ if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
+ return 0;
+
+ freq = 1000000000 / (sdr->tRC_min / 1000);
+
+ ret = mxic_nfc_set_freq(nfc, freq);
+ if (ret)
+ WARN_ON("Set freq failed\n");
+
+ if (sdr->tRC_min < 30000)
+ writel(DATA_STROB_EDO_EN, nfc->regs + DATA_STROB);
+
+ return 0;
+}
+
+/* Dummy implementation: we don't support multiple chips */
+static void mxic_nfc_select_chip(struct mtd_info *mtd, int chipnr)
+{
+ switch (chipnr) {
+ case -1:
+ case 0:
+ break;
+
+ default:
+ BUG();
+ }
+}
+
+static int mxic_nfc_probe(struct udevice *dev)
+{
+ struct mxic_nand_ctrl *nfc = dev_get_priv(dev);
+ struct nand_chip *nand_chip = &nfc->nand_chip;
+ struct mtd_info *mtd;
+ ofnode child;
+ int err;
+
+ nfc->regs = (void *)dev_read_addr(dev);
+
+ nfc->send_clk = devm_clk_get(dev, "send");
+ if (IS_ERR(nfc->send_clk))
+ return PTR_ERR(nfc->send_clk);
+
+ nfc->send_dly_clk = devm_clk_get(dev, "send_dly");
+ if (IS_ERR(nfc->send_dly_clk))
+ return PTR_ERR(nfc->send_dly_clk);
+
+ mtd = nand_to_mtd(nand_chip);
+
+ ofnode_for_each_subnode(child, dev_ofnode(dev))
+ nand_set_flash_node(nand_chip, child);
+
+ nand_set_controller_data(nand_chip, nfc);
+
+ nand_chip->select_chip = mxic_nfc_select_chip;
+ nand_chip->setup_data_interface = mxic_nfc_setup_data_interface;
+ nand_chip->cmdfunc = mxic_nfc_cmd_function;
+ nand_chip->read_byte = mxic_nfc_read_byte;
+ nand_chip->read_buf = mxic_nfc_read_buf;
+ nand_chip->write_buf = mxic_nfc_write_buf;
+
+ mxic_nfc_hw_init(nfc);
+
+ err = nand_scan(mtd, 1);
+ if (err)
+ return err;
+
+ err = nand_register(0, mtd);
+ if (err) {
+ dev_err(dev, "Failed to register MTD: %d\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id mxic_nfc_of_ids[] = {
+ { .compatible = "mxic,multi-itfc-v009-nand-controller" },
+ { /* Sentinel */ }
+};
+
+U_BOOT_DRIVER(mxic_nfc) = {
+ .name = "mxic_nfc",
+ .id = UCLASS_MTD,
+ .of_match = mxic_nfc_of_ids,
+ .probe = mxic_nfc_probe,
+ .priv_auto = sizeof(struct mxic_nand_ctrl),
+};
+
+void board_nand_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MTD,
+ DM_DRIVER_GET(mxic_nfc), &dev);
+ if (ret && ret != -ENODEV)
+ pr_err("Failed to initialize %s. (error %d)\n", dev->name,
+ ret);
+}
diff --git a/drivers/mtd/nand/raw/mxs_nand_spl.c b/drivers/mtd/nand/raw/mxs_nand_spl.c
index 6b70d68..9e0b8afb 100644
--- a/drivers/mtd/nand/raw/mxs_nand_spl.c
+++ b/drivers/mtd/nand/raw/mxs_nand_spl.c
@@ -296,3 +296,9 @@
void nand_deselect(void)
{
}
+
+u32 nand_spl_adjust_offset(u32 sector, u32 offs)
+{
+ /* Handle the offset adjust in nand_spl_load_image,*/
+ return offs;
+}
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 8151104..8c6461e 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -574,14 +574,9 @@
#ifdef CONFIG_DM_ETH
static int macb_sifive_clk_init(struct udevice *dev, ulong rate)
{
- fdt_addr_t addr;
void *gemgxl_regs;
- addr = dev_read_addr_index(dev, 1);
- if (addr == FDT_ADDR_T_NONE)
- return -ENODEV;
-
- gemgxl_regs = (void __iomem *)addr;
+ gemgxl_regs = dev_read_addr_index_ptr(dev, 1);
if (!gemgxl_regs)
return -ENODEV;
@@ -1383,7 +1378,7 @@
macb->phy_addr = ofnode_read_u32_default(phandle_args.node,
"reg", -1);
- macb->regs = (void *)pdata->iobase;
+ macb->regs = (void *)(uintptr_t)pdata->iobase;
macb->is_big_endian = (cpu_to_be32(0x12345678) == 0x12345678);
@@ -1444,7 +1439,7 @@
{
struct eth_pdata *pdata = dev_get_plat(dev);
- pdata->iobase = (phys_addr_t)dev_remap_addr(dev);
+ pdata->iobase = (uintptr_t)dev_remap_addr(dev);
if (!pdata->iobase)
return -EINVAL;
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index a6eb82b..2e24d12 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -14,9 +14,9 @@
#include <log.h>
#include <asm/cache.h>
#include <asm/global_data.h>
+#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
#include <common.h>
#include <clk.h>
#include <dm.h>
@@ -31,9 +31,6 @@
#include <reset.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
#include <wait_bit.h>
-#if CONFIG_IS_ENABLED(DM_GPIO)
-#include <asm-generic/gpio.h>
-#endif
#define MDIO_CMD_MII_BUSY BIT(0)
#define MDIO_CMD_MII_WRITE BIT(1)
diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
index f6465ea..3c529a2 100644
--- a/drivers/nvme/nvme.c
+++ b/drivers/nvme/nvme.c
@@ -743,6 +743,7 @@
u64 prp2;
u64 total_len = blkcnt << desc->log2blksz;
u64 temp_len = total_len;
+ uintptr_t temp_buffer = (uintptr_t)buffer;
u64 slba = blknr;
u16 lbas = 1 << (dev->max_transfer_shift - ns->lba_shift);
@@ -770,19 +771,19 @@
}
if (nvme_setup_prps(dev, &prp2,
- lbas << ns->lba_shift, (ulong)buffer))
+ lbas << ns->lba_shift, temp_buffer))
return -EIO;
c.rw.slba = cpu_to_le64(slba);
slba += lbas;
c.rw.length = cpu_to_le16(lbas - 1);
- c.rw.prp1 = cpu_to_le64((ulong)buffer);
+ c.rw.prp1 = cpu_to_le64(temp_buffer);
c.rw.prp2 = cpu_to_le64(prp2);
status = nvme_submit_sync_cmd(dev->queues[NVME_IO_Q],
&c, NULL, IO_TIMEOUT);
if (status)
break;
temp_len -= (u32)lbas << ns->lba_shift;
- buffer += lbas << ns->lba_shift;
+ temp_buffer += lbas << ns->lba_shift;
}
if (read)
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
index cf6e30f..9e623b6 100644
--- a/drivers/pci/pci-aardvark.c
+++ b/drivers/pci/pci-aardvark.c
@@ -39,6 +39,9 @@
#define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0)
#define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1)
#define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2)
+#define PCIE_CORE_DEV_REV_REG 0x8
+#define PCIE_CORE_EXP_ROM_BAR_REG 0x30
+#define PCIE_CORE_PCIEXP_CAP_OFF 0xc0
#define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
#define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
#define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
@@ -145,6 +148,7 @@
#define LTSSM_SHIFT 24
#define LTSSM_MASK 0x3f
#define LTSSM_L0 0x10
+#define LTSSM_DISABLED 0x20
#define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44)
/* PCIe core controller registers */
@@ -162,7 +166,7 @@
#define PCIE_CONFIG_WR_TYPE1 0xb
/* PCI_BDF shifts 8bit, so we need extra 4bit shift */
-#define PCIE_BDF(dev) (dev << 4)
+#define PCIE_BDF(b, d, f) (PCI_BDF(b, d, f) << 4)
#define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20)
#define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15)
#define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12)
@@ -182,18 +186,24 @@
/**
* struct pcie_advk - Advk PCIe controller state
*
- * @reg_base: The base address of the register space.
- * @first_busno: This driver supports multiple PCIe controllers.
- * first_busno stores the bus number of the PCIe root-port
- * number which may vary depending on the PCIe setup
- * (PEX switches etc).
- * @device: The pointer to PCI uclass device.
+ * @base: The base address of the register space.
+ * @first_busno: Bus number of the PCIe root-port.
+ * This may vary depending on the PCIe setup.
+ * @sec_busno: Bus number for the device behind the PCIe root-port.
+ * @dev: The pointer to PCI uclass device.
+ * @reset_gpio: GPIO descriptor for PERST.
+ * @cfgcache: Buffer for emulation of PCIe Root Port's PCI Bridge registers
+ * that are not available on Aardvark.
+ * @cfgcrssve: For CRSSVE emulation.
*/
struct pcie_advk {
- void *base;
- int first_busno;
- struct udevice *dev;
- struct gpio_desc reset_gpio;
+ void *base;
+ int first_busno;
+ int sec_busno;
+ struct udevice *dev;
+ struct gpio_desc reset_gpio;
+ u32 cfgcache[0x34 - 0x10];
+ bool cfgcrssve;
};
static inline void advk_writel(struct pcie_advk *pcie, uint val, uint reg)
@@ -209,22 +219,30 @@
/**
* pcie_advk_addr_valid() - Check for valid bus address
*
+ * @pcie: Pointer to the PCI bus
+ * @busno: Bus number of PCI device
+ * @dev: Device number of PCI device
+ * @func: Function number of PCI device
* @bdf: The PCI device to access
- * @first_busno: Bus number of the PCIe controller root complex
*
- * Return: 1 on valid, 0 on invalid
+ * Return: true on valid, false on invalid
*/
-static int pcie_advk_addr_valid(pci_dev_t bdf, int first_busno)
+static bool pcie_advk_addr_valid(struct pcie_advk *pcie,
+ int busno, u8 dev, u8 func)
{
+ /* On the primary (local) bus there is only one PCI Bridge */
+ if (busno == pcie->first_busno && (dev != 0 || func != 0))
+ return false;
+
/*
- * In PCIE-E only a single device (0) can exist
- * on the local bus. Beyound the local bus, there might be
- * a Switch and everything is possible.
+ * In PCI-E only a single device (0) can exist on the secondary bus.
+ * Beyond the secondary bus, there might be a Switch and anything is
+ * possible.
*/
- if ((PCI_BUS(bdf) == first_busno) && (PCI_DEV(bdf) > 0))
- return 0;
+ if (busno == pcie->sec_busno && dev != 0)
+ return false;
- return 1;
+ return true;
}
/**
@@ -354,32 +372,80 @@
enum pci_size_t size)
{
struct pcie_advk *pcie = dev_get_priv(bus);
+ int busno = PCI_BUS(bdf) - dev_seq(bus);
int retry_count;
bool allow_crs;
+ ulong data;
uint reg;
int ret;
dev_dbg(pcie->dev, "PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
- if (!pcie_advk_addr_valid(bdf, pcie->first_busno)) {
+ if (!pcie_advk_addr_valid(pcie, busno, PCI_DEV(bdf), PCI_FUNC(bdf))) {
dev_dbg(pcie->dev, "- out of range\n");
*valuep = pci_get_ff(size);
return 0;
}
/*
+ * The configuration space of the PCI Bridge on primary (local) bus is
+ * not accessible via PIO transfers like all other PCIe devices. PCI
+ * Bridge config registers are available directly in Aardvark memory
+ * space starting at offset zero. Moreover PCI Bridge registers in the
+ * range 0x10 - 0x34 are not available and register 0x38 (Expansion ROM
+ * Base Address) is at offset 0x30.
+ * We therefore read configuration space content of the primary PCI
+ * Bridge from our virtual cache.
+ */
+ if (busno == pcie->first_busno) {
+ if (offset >= 0x10 && offset < 0x34)
+ data = pcie->cfgcache[(offset - 0x10) / 4];
+ else if ((offset & ~3) == PCI_ROM_ADDRESS1)
+ data = advk_readl(pcie, PCIE_CORE_EXP_ROM_BAR_REG);
+ else
+ data = advk_readl(pcie, offset & ~3);
+
+ if ((offset & ~3) == (PCI_HEADER_TYPE & ~3)) {
+ /*
+ * Change Header Type of PCI Bridge device to Type 1
+ * (0x01, used by PCI Bridges) because hardwired value
+ * is Type 0 (0x00, used by Endpoint devices).
+ */
+ data &= ~0x007f0000;
+ data |= PCI_HEADER_TYPE_BRIDGE << 16;
+ }
+
+ if ((offset & ~3) == PCIE_CORE_PCIEXP_CAP_OFF + PCI_EXP_RTCTL) {
+ /* CRSSVE bit is stored only in cache */
+ if (pcie->cfgcrssve)
+ data |= PCI_EXP_RTCTL_CRSSVE;
+ }
+
+ if ((offset & ~3) == PCIE_CORE_PCIEXP_CAP_OFF +
+ (PCI_EXP_RTCAP & ~3)) {
+ /* CRS is emulated below, so set CRSVIS capability */
+ data |= PCI_EXP_RTCAP_CRSVIS << 16;
+ }
+
+ *valuep = pci_conv_32_to_size(data, offset, size);
+
+ return 0;
+ }
+
+ /*
* Returning fabricated CRS value (0xFFFF0001) by PCIe Root Complex to
* OS is allowed only for 4-byte PCI_VENDOR_ID config read request and
* only when CRSSVE bit in Root Port PCIe device is enabled. In all
* other error PCIe Root Complex must return all-ones.
- * Aardvark HW does not have Root Port PCIe device and U-Boot does not
- * implement emulation of this device.
+ *
* U-Boot currently does not support handling of CRS return value for
* PCI_VENDOR_ID config read request and also does not set CRSSVE bit.
- * Therefore disable returning CRS response for now.
+ * So it means that pcie->cfgcrssve is false. But the code is prepared
+ * for returning CRS, so that if U-Boot does support CRS in the future,
+ * it will work for Aardvark.
*/
- allow_crs = false;
+ allow_crs = (offset == PCI_VENDOR_ID) && (size == PCI_SIZE_32) && pcie->cfgcrssve;
if (advk_readl(pcie, PIO_START)) {
dev_err(pcie->dev,
@@ -395,14 +461,14 @@
/* Program the control register */
reg = advk_readl(pcie, PIO_CTRL);
reg &= ~PIO_CTRL_TYPE_MASK;
- if (PCI_BUS(bdf) == pcie->first_busno)
+ if (busno == pcie->sec_busno)
reg |= PCIE_CONFIG_RD_TYPE0;
else
reg |= PCIE_CONFIG_RD_TYPE1;
advk_writel(pcie, reg, PIO_CTRL);
/* Program the address registers */
- reg = PCIE_BDF(bdf) | PCIE_CONF_REG(offset);
+ reg = PCIE_BDF(busno, PCI_DEV(bdf), PCI_FUNC(bdf)) | PCIE_CONF_REG(offset);
advk_writel(pcie, reg, PIO_ADDR_LS);
advk_writel(pcie, 0, PIO_ADDR_MS);
@@ -490,7 +556,9 @@
enum pci_size_t size)
{
struct pcie_advk *pcie = dev_get_priv(bus);
+ int busno = PCI_BUS(bdf) - dev_seq(bus);
int retry_count;
+ ulong data;
uint reg;
int ret;
@@ -499,11 +567,48 @@
dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08lx)\n",
offset, size, value);
- if (!pcie_advk_addr_valid(bdf, pcie->first_busno)) {
+ if (!pcie_advk_addr_valid(pcie, busno, PCI_DEV(bdf), PCI_FUNC(bdf))) {
dev_dbg(pcie->dev, "- out of range\n");
return 0;
}
+ /*
+ * As explained in pcie_advk_read_config(), for the configuration
+ * space of the primary PCI Bridge, we write the content into virtual
+ * cache.
+ */
+ if (busno == pcie->first_busno) {
+ if (offset >= 0x10 && offset < 0x34) {
+ data = pcie->cfgcache[(offset - 0x10) / 4];
+ data = pci_conv_size_to_32(data, value, offset, size);
+ /* This PCI bridge does not have configurable bars */
+ if ((offset & ~3) == PCI_BASE_ADDRESS_0 ||
+ (offset & ~3) == PCI_BASE_ADDRESS_1)
+ data = 0x0;
+ pcie->cfgcache[(offset - 0x10) / 4] = data;
+ } else if ((offset & ~3) == PCI_ROM_ADDRESS1) {
+ data = advk_readl(pcie, PCIE_CORE_EXP_ROM_BAR_REG);
+ data = pci_conv_size_to_32(data, value, offset, size);
+ advk_writel(pcie, data, PCIE_CORE_EXP_ROM_BAR_REG);
+ } else {
+ data = advk_readl(pcie, offset & ~3);
+ data = pci_conv_size_to_32(data, value, offset, size);
+ advk_writel(pcie, data, offset & ~3);
+ }
+
+ if (offset == PCI_PRIMARY_BUS)
+ pcie->first_busno = data & 0xff;
+
+ if (offset == PCI_SECONDARY_BUS ||
+ (offset == PCI_PRIMARY_BUS && size != PCI_SIZE_8))
+ pcie->sec_busno = (data >> 8) & 0xff;
+
+ if ((offset & ~3) == PCIE_CORE_PCIEXP_CAP_OFF + PCI_EXP_RTCTL)
+ pcie->cfgcrssve = data & PCI_EXP_RTCTL_CRSSVE;
+
+ return 0;
+ }
+
if (advk_readl(pcie, PIO_START)) {
dev_err(pcie->dev,
"Previous PIO read/write transfer is still running\n");
@@ -513,14 +618,14 @@
/* Program the control register */
reg = advk_readl(pcie, PIO_CTRL);
reg &= ~PIO_CTRL_TYPE_MASK;
- if (PCI_BUS(bdf) == pcie->first_busno)
+ if (busno == pcie->sec_busno)
reg |= PCIE_CONFIG_WR_TYPE0;
else
reg |= PCIE_CONFIG_WR_TYPE1;
advk_writel(pcie, reg, PIO_CTRL);
/* Program the address registers */
- reg = PCIE_BDF(bdf) | PCIE_CONF_REG(offset);
+ reg = PCIE_BDF(busno, PCI_DEV(bdf), PCI_FUNC(bdf)) | PCIE_CONF_REG(offset);
advk_writel(pcie, reg, PIO_ADDR_LS);
advk_writel(pcie, 0, PIO_ADDR_MS);
dev_dbg(pcie->dev, "\tPIO req. - addr = 0x%08x\n", reg);
@@ -569,7 +674,7 @@
val = advk_readl(pcie, CFG_REG);
ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK;
- return ltssm_state >= LTSSM_L0;
+ return ltssm_state >= LTSSM_L0 && ltssm_state < LTSSM_DISABLED;
}
/**
@@ -589,14 +694,14 @@
/* check if the link is up or not */
for (retries = 0; retries < LINK_MAX_RETRIES; retries++) {
if (pcie_advk_link_up(pcie)) {
- printf("PCIE-%d: Link up\n", pcie->first_busno);
+ printf("PCIe: Link up\n");
return 0;
}
udelay(LINK_WAIT_TIMEOUT);
}
- printf("PCIE-%d: Link down\n", pcie->first_busno);
+ printf("PCIe: Link down\n");
return -ETIMEDOUT;
}
@@ -715,6 +820,25 @@
*/
advk_writel(pcie, 0x11ab11ab, VENDOR_ID_REG);
+ /*
+ * Change Class Code of PCI Bridge device to PCI Bridge (0x600400),
+ * because default value is Mass Storage Controller (0x010400), causing
+ * U-Boot to fail to recognize it as P2P Bridge.
+ *
+ * Note that this Aardvark PCI Bridge does not have a compliant Type 1
+ * Configuration Space and it even cannot be accessed via Aardvark's
+ * PCI config space access method. Something like config space is
+ * available in internal Aardvark registers starting at offset 0x0
+ * and is reported as Type 0. In range 0x10 - 0x34 it has totally
+ * different registers. So our driver reports Header Type as Type 1 and
+ * for the above mentioned range redirects access to the virtual
+ * cfgcache[] buffer, which avoids changing internal Aardvark registers.
+ */
+ reg = advk_readl(pcie, PCIE_CORE_DEV_REV_REG);
+ reg &= ~0xffffff00;
+ reg |= (PCI_CLASS_BRIDGE_PCI << 8) << 8;
+ advk_writel(pcie, reg, PCIE_CORE_DEV_REV_REG);
+
/* Set Advanced Error Capabilities and Control PF0 register */
reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |
PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
@@ -809,12 +933,6 @@
if (pcie_advk_wait_for_link(pcie))
return -ENXIO;
- reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
- reg |= PCIE_CORE_CMD_MEM_ACCESS_EN |
- PCIE_CORE_CMD_IO_ACCESS_EN |
- PCIE_CORE_CMD_MEM_IO_REQ_EN;
- advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
-
return 0;
}
@@ -856,9 +974,14 @@
dev_warn(dev, "PCIE Reset on GPIO support is missing\n");
}
- pcie->first_busno = dev_seq(dev);
pcie->dev = pci_get_controller(dev);
+ /* PCI Bridge support 32-bit I/O and 64-bit prefetch mem addressing */
+ pcie->cfgcache[(PCI_IO_BASE - 0x10) / 4] =
+ PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8);
+ pcie->cfgcache[(PCI_PREF_MEMORY_BASE - 0x10) / 4] =
+ PCI_PREF_RANGE_TYPE_64 | (PCI_PREF_RANGE_TYPE_64 << 16);
+
return pcie_advk_setup_hw(pcie);
}
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 044babe..5da3515 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -627,6 +627,7 @@
int dm_pci_hose_probe_bus(struct udevice *bus)
{
+ u8 header_type;
int sub_bus;
int ret;
int ea_pos;
@@ -634,6 +635,14 @@
debug("%s\n", __func__);
+ dm_pci_read_config8(bus, PCI_HEADER_TYPE, &header_type);
+ header_type &= 0x7f;
+ if (header_type != PCI_HEADER_TYPE_BRIDGE) {
+ debug("%s: Skipping PCI device %d with Non-Bridge Header Type 0x%x\n",
+ __func__, PCI_DEV(dm_pci_get_bdf(bus)), header_type);
+ return log_msg_ret("probe", -EINVAL);
+ }
+
ea_pos = dm_pci_find_capability(bus, PCI_CAP_ID_EA);
if (ea_pos) {
dm_pci_read_config8(bus, ea_pos + sizeof(u32) + sizeof(u8),
diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
index 0808246..5af4ee6 100644
--- a/drivers/pci/pci_auto.c
+++ b/drivers/pci/pci_auto.c
@@ -19,7 +19,7 @@
#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
#endif
-static void dm_pciauto_setup_device(struct udevice *dev, int bars_num,
+static void dm_pciauto_setup_device(struct udevice *dev,
struct pci_region *mem,
struct pci_region *prefetch,
struct pci_region *io)
@@ -28,6 +28,7 @@
pci_size_t bar_size;
u16 cmdstat = 0;
int bar, bar_nr = 0;
+ int bars_num;
u8 header_type;
int rom_addr;
pci_addr_t bar_value;
@@ -39,6 +40,26 @@
cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) |
PCI_COMMAND_MASTER;
+ dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
+ header_type &= 0x7f;
+
+ switch (header_type) {
+ case PCI_HEADER_TYPE_NORMAL:
+ bars_num = 6;
+ break;
+ case PCI_HEADER_TYPE_BRIDGE:
+ bars_num = 2;
+ break;
+ case PCI_HEADER_TYPE_CARDBUS:
+ /* CardBus header does not have any BAR */
+ bars_num = 0;
+ break;
+ default:
+ /* Skip configuring BARs for unknown header types */
+ bars_num = 0;
+ break;
+ }
+
for (bar = PCI_BASE_ADDRESS_0;
bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
int ret = 0;
@@ -129,9 +150,8 @@
}
/* Configure the expansion ROM address */
- dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
- header_type &= 0x7f;
- if (header_type != PCI_HEADER_TYPE_CARDBUS) {
+ if (header_type == PCI_HEADER_TYPE_NORMAL ||
+ header_type == PCI_HEADER_TYPE_BRIDGE) {
rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
dm_pci_write_config32(dev, rom_addr, 0xfffffffe);
@@ -342,7 +362,7 @@
debug("PCI Autoconfig: Found P2P bridge, device %d\n",
PCI_DEV(dm_pci_get_bdf(dev)));
- dm_pciauto_setup_device(dev, 2, pci_mem, pci_prefetch, pci_io);
+ dm_pciauto_setup_device(dev, pci_mem, pci_prefetch, pci_io);
ret = dm_pci_hose_probe_bus(dev);
if (ret < 0)
@@ -355,7 +375,7 @@
* just do a minimal setup of the bridge,
* let the OS take care of the rest
*/
- dm_pciauto_setup_device(dev, 0, pci_mem, pci_prefetch, pci_io);
+ dm_pciauto_setup_device(dev, pci_mem, pci_prefetch, pci_io);
debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
PCI_DEV(dm_pci_get_bdf(dev)));
@@ -387,7 +407,7 @@
/* fall through */
default:
- dm_pciauto_setup_device(dev, 6, pci_mem, pci_prefetch, pci_io);
+ dm_pciauto_setup_device(dev, pci_mem, pci_prefetch, pci_io);
break;
}
diff --git a/drivers/pci/pci_auto_common.c b/drivers/pci/pci_auto_common.c
index c0a53dc..2f4aff0 100644
--- a/drivers/pci/pci_auto_common.c
+++ b/drivers/pci/pci_auto_common.c
@@ -74,7 +74,7 @@
{
pciauto_region_init(region);
debug("PCI Autoconfig: Bus %s region: [%llx-%llx],\n"
- "\t\tPhysical Memory [%llx-%llxx]\n", name,
+ "\t\tPhysical Memory [%llx-%llx]\n", name,
(unsigned long long)region->bus_start,
(unsigned long long)(region->bus_start + region->size - 1),
(unsigned long long)region->phys_start,
diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c
index 06822d1..047c8bb 100644
--- a/drivers/phy/marvell/comphy_a3700.c
+++ b/drivers/phy/marvell/comphy_a3700.c
@@ -200,7 +200,7 @@
* 6. Enable the output of 100M/125M/500M clock
*/
reg_set16(phy_addr(PCIE, MISC_REG0),
- 0xA00D | rb_clk500m_en | rb_clk100m_125m_en, 0xFFFF);
+ 0xA00D | rb_clk500m_en | rb_txdclk_2x_sel | rb_clk100m_125m_en, 0xFFFF);
/*
* 7. Enable TX
@@ -230,9 +230,13 @@
*/
if (invert & COMPHY_POLARITY_TXD_INVERT)
reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_txd_inv, 0);
+ else
+ reg_set16(phy_addr(PCIE, SYNC_PATTERN), 0, phy_txd_inv);
if (invert & COMPHY_POLARITY_RXD_INVERT)
reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_rxd_inv, 0);
+ else
+ reg_set16(phy_addr(PCIE, SYNC_PATTERN), 0, phy_rxd_inv);
/*
* 11. Release SW reset
@@ -467,9 +471,13 @@
*/
if (invert & COMPHY_POLARITY_TXD_INVERT)
usb3_reg_set16(SYNC_PATTERN, phy_txd_inv, 0, lane);
+ else
+ usb3_reg_set16(SYNC_PATTERN, 0, phy_txd_inv, lane);
if (invert & COMPHY_POLARITY_RXD_INVERT)
usb3_reg_set16(SYNC_PATTERN, phy_rxd_inv, 0, lane);
+ else
+ usb3_reg_set16(SYNC_PATTERN, 0, phy_rxd_inv, lane);
/*
* 10. Set max speed generation to USB3.0 5Gbps
@@ -586,24 +594,30 @@
rb_usb2phy_pllcal_done, /* value */
rb_usb2phy_pllcal_done, /* mask */
POLL_32B_REG); /* 32bit */
- if (!ret)
+ if (!ret) {
printf("Failed to end USB2 PLL calibration\n");
+ goto out;
+ }
/* Assert impedance calibration done */
ret = comphy_poll_reg(USB2_PHY_CAL_CTRL_ADDR(usb32),
rb_usb2phy_impcal_done, /* value */
rb_usb2phy_impcal_done, /* mask */
POLL_32B_REG); /* 32bit */
- if (!ret)
+ if (!ret) {
printf("Failed to end USB2 impedance calibration\n");
+ goto out;
+ }
/* Assert squetch calibration done */
ret = comphy_poll_reg(USB2_PHY_RX_CHAN_CTRL1_ADDR(usb32),
rb_usb2phy_sqcal_done, /* value */
rb_usb2phy_sqcal_done, /* mask */
POLL_32B_REG); /* 32bit */
- if (!ret)
+ if (!ret) {
printf("Failed to end USB2 unknown calibration\n");
+ goto out;
+ }
/* Assert PLL is ready */
ret = comphy_poll_reg(USB2_PHY_PLL_CTRL0_ADDR(usb32),
@@ -611,9 +625,12 @@
rb_usb2phy_pll_ready, /* mask */
POLL_32B_REG); /* 32bit */
- if (!ret)
+ if (!ret) {
printf("Failed to lock USB2 PLL\n");
+ goto out;
+ }
+out:
debug_exit();
return ret;
@@ -839,9 +856,13 @@
*/
if (invert & COMPHY_POLARITY_TXD_INVERT)
reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_txd_inv, 0);
+ else
+ reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), 0, phy_txd_inv);
if (invert & COMPHY_POLARITY_RXD_INVERT)
reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_rxd_inv, 0);
+ else
+ reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), 0, phy_rxd_inv);
/*
* 19. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1
@@ -861,8 +882,10 @@
rb_pll_ready_tx | rb_pll_ready_rx, /* value */
rb_pll_ready_tx | rb_pll_ready_rx, /* mask */
POLL_32B_REG); /* 32bit */
- if (!ret)
+ if (!ret) {
printf("Failed to lock PLL for SGMII PHY %d\n", lane);
+ goto out;
+ }
/*
* 21. Set COMPHY input port PIN_TX_IDLE=0
@@ -883,14 +906,17 @@
rb_rx_init_done, /* value */
rb_rx_init_done, /* mask */
POLL_32B_REG); /* 32bit */
- if (!ret)
+ if (!ret) {
printf("Failed to init RX of SGMII PHY %d\n", lane);
+ goto out;
+ }
/*
* Restore saved selector.
*/
reg_set(COMPHY_SEL_ADDR, saved_selector, 0xFFFFFFFF);
+out:
debug_exit();
return ret;
diff --git a/drivers/phy/marvell/comphy_a3700.h b/drivers/phy/marvell/comphy_a3700.h
index 8748c6c..23c8ffb 100644
--- a/drivers/phy/marvell/comphy_a3700.h
+++ b/drivers/phy/marvell/comphy_a3700.h
@@ -120,6 +120,7 @@
#define MISC_REG0 0x4f
#define rb_clk100m_125m_en BIT(4)
+#define rb_txdclk_2x_sel BIT(6)
#define rb_clk500m_en BIT(7)
#define rb_ref_clk_sel BIT(10)
diff --git a/drivers/phy/phy-stm32-usbphyc.c b/drivers/phy/phy-stm32-usbphyc.c
index 02d859a..9c1dcfa 100644
--- a/drivers/phy/phy-stm32-usbphyc.c
+++ b/drivers/phy/phy-stm32-usbphyc.c
@@ -339,8 +339,8 @@
{
struct stm32_usbphyc *usbphyc = dev_get_priv(dev);
struct reset_ctl reset;
- ofnode node;
- int i, ret;
+ ofnode node, connector;
+ int ret;
usbphyc->base = dev_read_addr(dev);
if (usbphyc->base == FDT_ADDR_T_NONE)
@@ -378,14 +378,18 @@
return ret;
}
- /*
- * parse all PHY subnodes in order to populate regulator associated
- * to each PHY port
- */
- node = dev_read_first_subnode(dev);
- for (i = 0; i < MAX_PHYS; i++) {
- struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + i;
+ /* parse all PHY subnodes to populate regulator associated to each PHY port */
+ dev_for_each_subnode(node, dev) {
+ fdt_addr_t phy_id;
+ struct stm32_usbphyc_phy *usbphyc_phy;
+ phy_id = ofnode_read_u32_default(node, "reg", FDT_ADDR_T_NONE);
+ if (phy_id >= MAX_PHYS) {
+ dev_err(dev, "invalid reg value %lx for %s\n",
+ phy_id, ofnode_get_name(node));
+ return -ENOENT;
+ }
+ usbphyc_phy = usbphyc->phys + phy_id;
usbphyc_phy->init = false;
usbphyc_phy->powered = false;
ret = stm32_usbphyc_get_regulator(node, "phy-supply",
@@ -395,12 +399,12 @@
return ret;
}
- ret = stm32_usbphyc_get_regulator(node, "vbus-supply",
- &usbphyc_phy->vbus);
- if (ret)
- usbphyc_phy->vbus = NULL;
-
- node = dev_read_next_subnode(node);
+ usbphyc_phy->vbus = NULL;
+ connector = ofnode_find_subnode(node, "connector");
+ if (ofnode_valid(connector)) {
+ ret = stm32_usbphyc_get_regulator(connector, "vbus-supply",
+ &usbphyc_phy->vbus);
+ }
}
/* Check if second port has to be used for host controller */
diff --git a/drivers/power/axp809.c b/drivers/power/axp809.c
index 6323492..0396502 100644
--- a/drivers/power/axp809.c
+++ b/drivers/power/axp809.c
@@ -13,7 +13,6 @@
#include <common.h>
#include <command.h>
#include <errno.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/pmic_bus.h>
#include <axp_pmic.h>
diff --git a/drivers/power/axp818.c b/drivers/power/axp818.c
index 0531707..2dc7364 100644
--- a/drivers/power/axp818.c
+++ b/drivers/power/axp818.c
@@ -13,7 +13,6 @@
#include <common.h>
#include <command.h>
#include <errno.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/pmic_bus.h>
#include <axp_pmic.h>
diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index cf2a9b2..92e2ace 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -10,10 +10,12 @@
- 'drivers/power/pmic/pmic-uclass.c'
- 'include/power/pmic.h'
+if DM_PMIC
+
config SPL_DM_PMIC
bool "Enable Driver Model for PMIC drivers (UCLASS_PMIC) in SPL"
depends on SPL_DM
- default y if DM_PMIC
+ default y
---help---
This config enables the driver-model PMIC support in SPL.
UCLASS_PMIC - designed to provide an I/O interface for PMIC devices.
@@ -25,7 +27,6 @@
config PMIC_CHILDREN
bool "Allow child devices for PMICs"
- depends on DM_PMIC
default y
---help---
This allows PMICs to support child devices (such as regulators) in
@@ -35,7 +36,7 @@
config SPL_PMIC_CHILDREN
bool "Allow child devices for PMICs in SPL"
- depends on DM_PMIC
+ depends on SPL_DM_PMIC
default y
---help---
This allows PMICs to support child devices (such as regulators) in
@@ -46,7 +47,6 @@
config PMIC_AB8500
bool "Enable driver for ST-Ericsson AB8500 PMIC via PRCMU"
- depends on DM_PMIC
select REGMAP
select SYSCON
help
@@ -56,23 +56,36 @@
config PMIC_ACT8846
bool "Enable support for the active-semi 8846 PMIC"
- depends on DM_PMIC && DM_I2C
+ depends on DM_I2C
---help---
This PMIC includes 4 DC/DC step-down buck regulators and 8 low-dropout
regulators (LDOs). It also provides some GPIO, reset and battery
functions. It uses an I2C interface and is designed for use with
tablets and smartphones.
+config PMIC_AXP
+ bool "Enable Driver Model for X-Powers AXP PMICs"
+ depends on DM_I2C
+ help
+ This config enables driver-model PMIC uclass features for
+ X-Powers AXP152, AXP2xx, and AXP8xx PMICs.
+
+config SPL_PMIC_AXP
+ bool "Enable Driver Model for X-Powers AXP PMICs in SPL"
+ depends on SPL_DM_I2C && SPL_DM_PMIC
+ help
+ This config enables driver-model PMIC uclass features in the SPL for
+ X-Powers AXP152, AXP2xx, and AXP8xx PMICs.
+
config DM_PMIC_DA9063
bool "Enable Driver Model for the Dialog DA9063 PMIC"
- depends on DM_PMIC
help
This config enables implementation of driver-model pmic uclass features
for PMIC DA9063. The driver implements read/write operations.
config SPL_DM_PMIC_DA9063
bool "Enable Driver Model for the Dialog DA9063 PMIC in SPL"
- depends on DM_PMIC && SPL
+ depends on SPL_DM_PMIC
help
This config enables implementation of driver-model pmic uclass features
for PMIC DA9063. The driver implements read/write operations.
@@ -87,14 +100,13 @@
config DM_PMIC_BD71837
bool "Enable Driver Model for PMIC BD71837"
- depends on DM_PMIC
help
This config enables implementation of driver-model pmic uclass features
for PMIC BD71837. The driver implements read/write operations.
config SPL_DM_PMIC_BD71837
bool "Enable Driver Model for PMIC BD71837 in SPL stage"
- depends on DM_PMIC
+ depends on SPL_DM_PMIC
help
This config enables implementation of driver-model pmic uclass
features for PMIC BD71837. The driver implements read/write
@@ -102,7 +114,7 @@
config DM_PMIC_FAN53555
bool "Enable support for OnSemi FAN53555"
- depends on DM_PMIC && DM_REGULATOR && DM_I2C
+ depends on DM_REGULATOR && DM_I2C
select DM_REGULATOR_FAN53555
help
This config enables implementation of driver-model PMIC
@@ -116,14 +128,13 @@
config DM_PMIC_MP5416
bool "Enable Driver Model for PMIC MP5416"
- depends on DM_PMIC
help
This config enables implementation of driver-model pmic uclass features
for PMIC MP5416. The driver implements read/write operations.
config SPL_DM_PMIC_MP5416
bool "Enable Driver Model for PMIC MP5416 in SPL stage"
- depends on DM_PMIC
+ depends on SPL_DM_PMIC
help
This config enables implementation of driver-model pmic uclass
features for PMIC MP5416. The driver implements read/write
@@ -131,56 +142,50 @@
config DM_PMIC_PCA9450
bool "Enable Driver Model for PMIC PCA9450"
- depends on DM_PMIC
help
This config enables implementation of driver-model pmic uclass features
for PMIC PCA9450. The driver implements read/write operations.
config SPL_DM_PMIC_PCA9450
bool "Enable Driver Model for PMIC PCA9450"
- depends on DM_PMIC
+ depends on SPL_DM_PMIC
help
This config enables implementation of driver-model pmic uclass features
for PMIC PCA9450 in SPL. The driver implements read/write operations.
config DM_PMIC_PFUZE100
bool "Enable Driver Model for PMIC PFUZE100"
- depends on DM_PMIC
---help---
This config enables implementation of driver-model pmic uclass features
for PMIC PFUZE100. The driver implements read/write operations.
config SPL_DM_PMIC_PFUZE100
bool "Enable Driver Model for PMIC PFUZE100 in SPL"
- depends on DM_PMIC
+ depends on SPL_DM_PMIC
---help---
This config enables implementation of driver-model pmic uclass features
for PMIC PFUZE100 in SPL. The driver implements read/write operations.
config DM_PMIC_MAX77686
bool "Enable Driver Model for PMIC MAX77686"
- depends on DM_PMIC
---help---
This config enables implementation of driver-model pmic uclass features
for PMIC MAX77686. The driver implements read/write operations.
config DM_PMIC_MAX8998
bool "Enable Driver Model for PMIC MAX8998"
- depends on DM_PMIC
---help---
This config enables implementation of driver-model pmic uclass features
for PMIC MAX8998. The driver implements read/write operations.
config DM_PMIC_MC34708
bool "Enable Driver Model for PMIC MC34708"
- depends on DM_PMIC
help
This config enables implementation of driver-model pmic uclass features
for PMIC MC34708. The driver implements read/write operations.
config PMIC_MAX8997
bool "Enable Driver Model for PMIC MAX8997"
- depends on DM_PMIC
---help---
This config enables implementation of driver-model pmic uclass features
for PMIC MAX8997. The driver implements read/write operations.
@@ -195,7 +200,6 @@
config PMIC_PM8916
bool "Enable Driver Model for Qualcomm PM8916 PMIC"
- depends on DM_PMIC
---help---
The PM8916 is a PMIC connected to one (or several) processors
with SPMI bus. It has 2 slaves with several peripherals:
@@ -211,7 +215,6 @@
config PMIC_RK8XX
bool "Enable support for Rockchip PMIC RK8XX"
- depends on DM_PMIC
---help---
The Rockchip RK808 PMIC provides four buck DC-DC convertors, 8 LDOs,
an RTC and two low Rds (resistance (drain to source)) switches. It is
@@ -220,7 +223,7 @@
config SPL_PMIC_RK8XX
bool "Enable support for Rockchip PMIC RK8XX"
- depends on DM_PMIC
+ depends on SPL_DM_PMIC
---help---
The Rockchip RK808 PMIC provides four buck DC-DC convertors, 8 LDOs,
an RTC and two low Rds (resistance (drain to source)) switches. It is
@@ -229,7 +232,6 @@
config PMIC_S2MPS11
bool "Enable Driver Model for PMIC Samsung S2MPS11"
- depends on DM_PMIC
---help---
The Samsung S2MPS11 PMIC provides:
- 38 adjustable LDO regulators
@@ -243,7 +245,6 @@
config DM_PMIC_SANDBOX
bool "Enable Driver Model for emulated Sandbox PMIC"
- depends on DM_PMIC
---help---
Enable the driver for Sandbox PMIC emulation. The emulated PMIC device
depends on two drivers:
@@ -268,7 +269,6 @@
config PMIC_S5M8767
bool "Enable Driver Model for the Samsung S5M8767 PMIC"
- depends on DM_PMIC
---help---
The S5M8767 PMIC provides a large array of LDOs and BUCKs for use
as a SoC power controller. It also provides 32KHz clock outputs. This
@@ -277,7 +277,6 @@
config PMIC_RN5T567
bool "Enable driver for Ricoh RN5T567 PMIC"
- depends on DM_PMIC
---help---
The RN5T567 is a PMIC with 4 step-down DC/DC converters, 5 LDO
regulators Real-Time Clock and 4 GPIOs. This driver provides
@@ -285,7 +284,6 @@
config PMIC_TPS65090
bool "Enable driver for Texas Instruments TPS65090 PMIC"
- depends on DM_PMIC
---help---
The TPS65090 is a PMIC containing several LDOs, DC to DC convertors,
FETs and a battery charger. This driver provides register access
@@ -294,35 +292,24 @@
config PMIC_PALMAS
bool "Enable driver for Texas Instruments PALMAS PMIC"
- depends on DM_PMIC
---help---
The PALMAS is a PMIC containing several LDOs, SMPS.
This driver binds the pmic children.
config PMIC_LP873X
bool "Enable driver for Texas Instruments LP873X PMIC"
- depends on DM_PMIC
---help---
The LP873X is a PMIC containing couple of LDOs and couple of SMPS.
This driver binds the pmic children.
config PMIC_LP87565
bool "Enable driver for Texas Instruments LP87565 PMIC"
- depends on DM_PMIC
---help---
The LP87565 is a PMIC containing a bunch of SMPS.
This driver binds the pmic children.
-config POWER_MC34VR500
- bool "Enable driver for Freescale MC34VR500 PMIC"
- ---help---
- The MC34VR500 is used in conjunction with the FSL T1 and LS1 series
- SoC. It provides 4 buck DC-DC convertors and 5 LDOs, and it is accessed
- via an I2C interface.
-
config DM_PMIC_TPS65910
bool "Enable driver for Texas Instruments TPS65910 PMIC"
- depends on DM_PMIC
---help---
The TPS65910 is a PMIC containing 3 buck DC-DC converters, one boost
DC-DC converter, 8 LDOs and a RTC. This driver binds the SMPS and LDO
@@ -330,7 +317,7 @@
config PMIC_STPMIC1
bool "Enable support for STMicroelectronics STPMIC1 PMIC"
- depends on DM_PMIC && DM_I2C
+ depends on DM_I2C
select SYSRESET_CMD_POWEROFF if CMD_POWEROFF && !ARM_PSCI_FW
---help---
The STPMIC1 PMIC provides 4 BUCKs, 6 LDOs, 1 VREF and 2 power switches.
@@ -339,28 +326,37 @@
config SPL_PMIC_PALMAS
bool "Enable driver for Texas Instruments PALMAS PMIC"
- depends on DM_PMIC
+ depends on SPL_DM_PMIC
help
The PALMAS is a PMIC containing several LDOs, SMPS.
This driver binds the pmic children in SPL.
config SPL_PMIC_LP873X
bool "Enable driver for Texas Instruments LP873X PMIC"
- depends on DM_PMIC
+ depends on SPL_DM_PMIC
help
The LP873X is a PMIC containing couple of LDOs and couple of SMPS.
This driver binds the pmic children in SPL.
config SPL_PMIC_LP87565
bool "Enable driver for Texas Instruments LP87565 PMIC"
- depends on DM_PMIC
+ depends on SPL_DM_PMIC
help
The LP87565 is a PMIC containing a bunch of SMPS.
This driver binds the pmic children in SPL.
config PMIC_TPS65941
bool "Enable driver for Texas Instruments TPS65941 PMIC"
- depends on DM_PMIC
help
The TPS65941 is a PMIC containing a bunch of SMPS & LDOs.
This driver binds the pmic children.
+
+endif
+
+config POWER_MC34VR500
+ bool "Enable driver for Freescale MC34VR500 PMIC"
+ depends on !DM_PMIC
+ ---help---
+ The MC34VR500 is used in conjunction with the FSL T1 and LS1 series
+ SoC. It provides 4 buck DC-DC convertors and 5 LDOs, and it is accessed
+ via an I2C interface.
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index 5250eac..e1922df 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -18,6 +18,7 @@
obj-$(CONFIG_PMIC_AB8500) += ab8500.o
obj-$(CONFIG_PMIC_ACT8846) += act8846.o
obj-$(CONFIG_PMIC_AS3722) += as3722.o as3722_gpio.o
+obj-$(CONFIG_$(SPL_)PMIC_AXP) += axp.o
obj-$(CONFIG_PMIC_MAX8997) += max8997.o
obj-$(CONFIG_PMIC_PM8916) += pm8916.o
obj-$(CONFIG_$(SPL_TPL_)PMIC_RK8XX) += rk8xx.o
diff --git a/drivers/power/pmic/axp.c b/drivers/power/pmic/axp.c
new file mode 100644
index 0000000..74c94bd
--- /dev/null
+++ b/drivers/power/pmic/axp.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <dm.h>
+#include <i2c.h>
+#include <power/pmic.h>
+
+static int axp_pmic_reg_count(struct udevice *dev)
+{
+ /* TODO: Get the specific value from driver data. */
+ return 0x100;
+}
+
+static struct dm_pmic_ops axp_pmic_ops = {
+ .reg_count = axp_pmic_reg_count,
+ .read = dm_i2c_read,
+ .write = dm_i2c_write,
+};
+
+static const struct udevice_id axp_pmic_ids[] = {
+ { .compatible = "x-powers,axp152" },
+ { .compatible = "x-powers,axp202" },
+ { .compatible = "x-powers,axp209" },
+ { .compatible = "x-powers,axp221" },
+ { .compatible = "x-powers,axp223" },
+ { .compatible = "x-powers,axp803" },
+ { .compatible = "x-powers,axp806" },
+ { .compatible = "x-powers,axp809" },
+ { .compatible = "x-powers,axp813" },
+ { }
+};
+
+U_BOOT_DRIVER(axp_pmic) = {
+ .name = "axp_pmic",
+ .id = UCLASS_PMIC,
+ .of_match = axp_pmic_ids,
+ .bind = dm_scan_fdt_dev,
+ .ops = &axp_pmic_ops,
+};
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index cf7f4c6..669d3fa 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -9,6 +9,12 @@
frequency/period can be controlled along with the proportion of that
time that the signal is high.
+config PWM_AT91
+ bool "Enable support for PWM found on AT91 SoC's"
+ depends on DM_PWM && ARCH_AT91
+ help
+ Support for PWM hardware on AT91 based SoC.
+
config PWM_CROS_EC
bool "Enable support for the Chrome OS EC PWM"
depends on DM_PWM
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 10d244b..55f2bc0 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -10,6 +10,7 @@
obj-$(CONFIG_DM_PWM) += pwm-uclass.o
+obj-$(CONFIG_PWM_AT91) += pwm-at91.o
obj-$(CONFIG_PWM_CROS_EC) += cros_ec_pwm.o
obj-$(CONFIG_PWM_EXYNOS) += exynos_pwm.o
obj-$(CONFIG_PWM_IMX) += pwm-imx.o pwm-imx-util.o
diff --git a/drivers/pwm/pwm-at91.c b/drivers/pwm/pwm-at91.c
new file mode 100644
index 0000000..95597aee
--- /dev/null
+++ b/drivers/pwm/pwm-at91.c
@@ -0,0 +1,207 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * PWM support for Microchip AT91 architectures.
+ *
+ * Copyright (C) 2021 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Dan Sneddon <daniel.sneddon@microchip.com>
+ *
+ * Based on drivers/pwm/pwm-atmel.c from Linux.
+ */
+#include <clk.h>
+#include <common.h>
+#include <div64.h>
+#include <dm.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <pwm.h>
+
+#define PERIOD_BITS 16
+#define PWM_MAX_PRES 10
+#define NSEC_PER_SEC 1000000000L
+
+#define PWM_ENA 0x04
+#define PWM_CHANNEL_OFFSET 0x20
+#define PWM_CMR 0x200
+#define PWM_CMR_CPRE_MSK GENMASK(3, 0)
+#define PWM_CMR_CPOL BIT(9)
+#define PWM_CDTY 0x204
+#define PWM_CPRD 0x20C
+
+struct at91_pwm_priv {
+ void __iomem *base;
+ struct clk pclk;
+ u32 clkrate;
+};
+
+static int at91_pwm_calculate_cprd_and_pres(struct udevice *dev,
+ unsigned long clkrate,
+ uint period_ns, uint duty_ns,
+ unsigned long *cprd, u32 *pres)
+{
+ u64 cycles = period_ns;
+ int shift;
+
+ /* Calculate the period cycles and prescale value */
+ cycles *= clkrate;
+ do_div(cycles, NSEC_PER_SEC);
+
+ /*
+ * The register for the period length is period_bits bits wide.
+ * So for each bit the number of clock cycles is wider divide the input
+ * clock frequency by two using pres and shift cprd accordingly.
+ */
+ shift = fls(cycles) - PERIOD_BITS;
+
+ if (shift > PWM_MAX_PRES) {
+ return -EINVAL;
+ } else if (shift > 0) {
+ *pres = shift;
+ cycles >>= *pres;
+ } else {
+ *pres = 0;
+ }
+
+ *cprd = cycles;
+
+ return 0;
+}
+
+static void at91_pwm_calculate_cdty(uint period_ns, uint duty_ns,
+ unsigned long clkrate, unsigned long cprd,
+ u32 pres, unsigned long *cdty)
+{
+ u64 cycles = duty_ns;
+
+ cycles *= clkrate;
+ do_div(cycles, NSEC_PER_SEC);
+ cycles >>= pres;
+ *cdty = cprd - cycles;
+}
+
+/**
+ * Returns: channel status after set operation
+ */
+static bool at91_pwm_set(void __iomem *base, uint channel, bool enable)
+{
+ u32 val, cur_status;
+
+ val = ioread32(base + PWM_ENA);
+ cur_status = !!(val & BIT(channel));
+
+ /* if channel is already in that state, do nothing */
+ if (!(enable ^ cur_status))
+ return cur_status;
+
+ if (enable)
+ val |= BIT(channel);
+ else
+ val &= ~(BIT(channel));
+
+ iowrite32(val, base + PWM_ENA);
+
+ return cur_status;
+}
+
+static int at91_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
+{
+ struct at91_pwm_priv *priv = dev_get_priv(dev);
+
+ at91_pwm_set(priv->base, channel, enable);
+
+ return 0;
+}
+
+static int at91_pwm_set_config(struct udevice *dev, uint channel,
+ uint period_ns, uint duty_ns)
+{
+ struct at91_pwm_priv *priv = dev_get_priv(dev);
+ unsigned long cprd, cdty;
+ u32 pres, val;
+ int channel_enabled;
+ int ret;
+
+ ret = at91_pwm_calculate_cprd_and_pres(dev, priv->clkrate, period_ns,
+ duty_ns, &cprd, &pres);
+ if (ret)
+ return ret;
+
+ at91_pwm_calculate_cdty(period_ns, duty_ns, priv->clkrate, cprd, pres, &cdty);
+
+ /* disable the channel */
+ channel_enabled = at91_pwm_set(priv->base, channel, false);
+
+ /* It is necessary to preserve CPOL, inside CMR */
+ val = ioread32(priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CMR);
+ val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK);
+ iowrite32(val, priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CMR);
+
+ iowrite32(cprd, priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CPRD);
+
+ iowrite32(cdty, priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CDTY);
+
+ /* renable the channel if needed */
+ if (channel_enabled)
+ at91_pwm_set(priv->base, channel, true);
+
+ return 0;
+}
+
+static int at91_pwm_set_invert(struct udevice *dev, uint channel,
+ bool polarity)
+{
+ struct at91_pwm_priv *priv = dev_get_priv(dev);
+ u32 val;
+
+ val = ioread32(priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CMR);
+ if (polarity)
+ val |= PWM_CMR_CPOL;
+ else
+ val &= ~PWM_CMR_CPOL;
+ iowrite32(val, priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CMR);
+
+ return 0;
+}
+
+static int at91_pwm_probe(struct udevice *dev)
+{
+ struct at91_pwm_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ priv->base = dev_read_addr_ptr(dev);
+ if (!priv->base)
+ return -EINVAL;
+
+ ret = clk_get_by_index(dev, 0, &priv->pclk);
+ if (ret)
+ return ret;
+
+ /* clocks aren't ref-counted so just enabled them once here */
+ ret = clk_enable(&priv->pclk);
+ if (ret)
+ return ret;
+
+ priv->clkrate = clk_get_rate(&priv->pclk);
+
+ return ret;
+}
+
+static const struct pwm_ops at91_pwm_ops = {
+ .set_config = at91_pwm_set_config,
+ .set_enable = at91_pwm_set_enable,
+ .set_invert = at91_pwm_set_invert,
+};
+
+static const struct udevice_id at91_pwm_of_match[] = {
+ { .compatible = "atmel,sama5d2-pwm" },
+ { }
+};
+
+U_BOOT_DRIVER(at91_pwm) = {
+ .name = "at91_pwm",
+ .id = UCLASS_PWM,
+ .of_match = at91_pwm_of_match,
+ .probe = at91_pwm_probe,
+ .priv_auto = sizeof(struct at91_pwm_priv),
+ .ops = &at91_pwm_ops,
+};
diff --git a/drivers/ram/sifive/sifive_ddr.c b/drivers/ram/sifive/sifive_ddr.c
index ba18466..4bd69a6 100644
--- a/drivers/ram/sifive/sifive_ddr.c
+++ b/drivers/ram/sifive/sifive_ddr.c
@@ -313,7 +313,7 @@
sifive_ddr_phy_fixup(denali_phy);
/* check size */
- priv->info.size = get_ram_size((long *)priv->info.base,
+ priv->info.size = get_ram_size((long *)(uintptr_t)priv->info.base,
ddr_size);
debug("%s : %lx\n", __func__, (uintptr_t)priv->info.size);
@@ -369,9 +369,9 @@
return ret;
}
- priv->ctl = (struct sifive_ddrctl *)dev_read_addr_index(dev, 0);
- priv->phy = (struct sifive_ddrphy *)dev_read_addr_index(dev, 1);
- priv->physical_filter_ctrl = (u32 *)dev_read_addr_index(dev, 2);
+ priv->ctl = (struct sifive_ddrctl *)dev_read_addr_index_ptr(dev, 0);
+ priv->phy = (struct sifive_ddrphy *)dev_read_addr_index_ptr(dev, 1);
+ priv->physical_filter_ctrl = (u32 *)dev_read_addr_index_ptr(dev, 2);
return sifive_ddr_setup(dev);
#endif
diff --git a/drivers/reset/reset-sunxi.c b/drivers/reset/reset-sunxi.c
index 264337e..8b95938 100644
--- a/drivers/reset/reset-sunxi.c
+++ b/drivers/reset/reset-sunxi.c
@@ -11,11 +11,11 @@
#include <malloc.h>
#include <reset-uclass.h>
#include <asm/io.h>
+#include <clk/sunxi.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <linux/bitops.h>
#include <linux/log2.h>
-#include <asm/arch/ccu.h>
struct sunxi_reset_priv {
void *base;
diff --git a/drivers/rtc/ds1307.c b/drivers/rtc/ds1307.c
index 3be97c9..1963565 100644
--- a/drivers/rtc/ds1307.c
+++ b/drivers/rtc/ds1307.c
@@ -41,6 +41,12 @@
#define RTC_YR_REG_ADDR 0x06
#define RTC_CTL_REG_ADDR 0x07
+#define DS1337_CTL_REG_ADDR 0x0e
+#define DS1337_STAT_REG_ADDR 0x0f
+#define DS1340_STAT_REG_ADDR 0x09
+
+#define RTC_STAT_BIT_OSF 0x80
+
#define RTC_SEC_BIT_CH 0x80 /* Clock Halt (in Register 0) */
/* DS1307-specific bits */
@@ -248,6 +254,11 @@
if (ret < 0)
return ret;
+ if (type == ds_1337) {
+ /* Ensure oscillator is enabled */
+ dm_i2c_reg_write(dev, DS1337_CTL_REG_ADDR, 0);
+ }
+
return 0;
}
@@ -257,62 +268,19 @@
uchar buf[7];
enum ds_type type = dev_get_driver_data(dev);
-read_rtc:
ret = dm_i2c_read(dev, 0, buf, sizeof(buf));
if (ret < 0)
return ret;
- if (type == ds_1307) {
- if (buf[RTC_SEC_REG_ADDR] & RTC_SEC_BIT_CH) {
- printf("### Warning: RTC oscillator has stopped\n");
- /* clear the CH flag */
- buf[RTC_SEC_REG_ADDR] &= ~RTC_SEC_BIT_CH;
- dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR,
- buf[RTC_SEC_REG_ADDR]);
- return -1;
- }
- } else if (type == ds_1337) {
- if (buf[RTC_CTL_REG_ADDR] & DS1337_CTL_BIT_EOSC) {
- printf("### Warning: RTC oscillator has stopped\n");
- /* clear the not oscillator enable (~EOSC) flag */
- buf[RTC_CTL_REG_ADDR] &= ~DS1337_CTL_BIT_EOSC;
- dm_i2c_reg_write(dev, RTC_CTL_REG_ADDR,
- buf[RTC_CTL_REG_ADDR]);
- return -1;
- }
- } else if (type == ds_1340) {
- if (buf[RTC_SEC_REG_ADDR] & DS1340_SEC_BIT_EOSC) {
- printf("### Warning: RTC oscillator has stopped\n");
- /* clear the not oscillator enable (~EOSC) flag */
- buf[RTC_SEC_REG_ADDR] &= ~DS1340_SEC_BIT_EOSC;
- dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR,
- buf[RTC_SEC_REG_ADDR]);
- return -1;
- }
- } else if (type == m41t11) {
- /* clock halted? turn it on, so clock can tick. */
- if (buf[RTC_SEC_REG_ADDR] & RTC_SEC_BIT_CH) {
- buf[RTC_SEC_REG_ADDR] &= ~RTC_SEC_BIT_CH;
- dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR,
- MCP7941X_BIT_ST);
- dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR,
- buf[RTC_SEC_REG_ADDR]);
- goto read_rtc;
- }
- } else if (type == mcp794xx) {
- /* make sure that the backup battery is enabled */
- if (!(buf[RTC_DAY_REG_ADDR] & MCP7941X_BIT_VBATEN)) {
- dm_i2c_reg_write(dev, RTC_DAY_REG_ADDR,
- buf[RTC_DAY_REG_ADDR] |
- MCP7941X_BIT_VBATEN);
- }
+ if (type == ds_1337 || type == ds_1340) {
+ uint reg = (type == ds_1337) ? DS1337_STAT_REG_ADDR :
+ DS1340_STAT_REG_ADDR;
+ int status = dm_i2c_reg_read(dev, reg);
- /* clock halted? turn it on, so clock can tick. */
- if (!(buf[RTC_SEC_REG_ADDR] & MCP7941X_BIT_ST)) {
- dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR,
- MCP7941X_BIT_ST);
- printf("Started RTC\n");
- goto read_rtc;
+ if (status >= 0 && (status & RTC_STAT_BIT_OSF)) {
+ printf("### Warning: RTC oscillator has stopped\n");
+ /* clear the OSF flag */
+ dm_i2c_reg_write(dev, reg, status & ~RTC_STAT_BIT_OSF);
}
}
@@ -361,7 +329,7 @@
/* Write control register in order to enable oscillator output
* (not EOSC) and set a default rate of 32.768kHz (RS2|RS1).
*/
- ret = dm_i2c_reg_write(dev, RTC_CTL_REG_ADDR,
+ ret = dm_i2c_reg_write(dev, DS1337_CTL_REG_ADDR,
DS1337_CTL_BIT_RS2 | DS1337_CTL_BIT_RS1);
} else if (type == ds_1340 || type == mcp794xx || type == m41t11) {
/* Reset clock calibration, frequency test and output level. */
diff --git a/drivers/rtc/rv8803.c b/drivers/rtc/rv8803.c
index acd50c6..5bae39d 100644
--- a/drivers/rtc/rv8803.c
+++ b/drivers/rtc/rv8803.c
@@ -157,6 +157,8 @@
static const struct udevice_id rv8803_rtc_ids[] = {
{ .compatible = "microcrystal,rv8803", },
+ { .compatible = "epson,rx8803" },
+ { .compatible = "epson,rx8900" },
{ }
};
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index 57a7848..30d4421 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -65,7 +65,7 @@
* anyway.
*/
if (node > 0 && !lists_bind_fdt(gd->dm_root, offset_to_ofnode(node),
- devp, false)) {
+ devp, NULL, false)) {
if (!device_probe(*devp))
return 0;
}
diff --git a/drivers/spi/rockchip_sfc.c b/drivers/spi/rockchip_sfc.c
index 4e2b861..e098add 100644
--- a/drivers/spi/rockchip_sfc.c
+++ b/drivers/spi/rockchip_sfc.c
@@ -116,6 +116,7 @@
/* Master trigger */
#define SFC_DMA_TRIGGER 0x80
+#define SFC_DMA_TRIGGER_START 1
/* Src or Dst addr for master */
#define SFC_DMA_ADDR 0x84
@@ -163,14 +164,12 @@
#define SFC_DMA_TRANS_THRETHOLD (0x40)
/* Maximum clock values from datasheet suggest keeping clock value under
- * 150MHz. No minimum or average value is suggested, but the U-boot BSP driver
- * has a minimum of 10MHz and a default of 80MHz which seems reasonable.
+ * 150MHz. No minimum or average value is suggested.
*/
-#define SFC_MIN_SPEED_HZ (10 * 1000 * 1000)
-#define SFC_DEFAULT_SPEED_HZ (80 * 1000 * 1000)
-#define SFC_MAX_SPEED_HZ (150 * 1000 * 1000)
+#define SFC_MAX_SPEED (150 * 1000 * 1000)
struct rockchip_sfc {
+ struct udevice *dev;
void __iomem *regbase;
struct clk hclk;
struct clk clk;
@@ -197,8 +196,6 @@
/* Still need to clear the masked interrupt from RISR */
writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR);
- debug("reset\n");
-
return err;
}
@@ -261,15 +258,11 @@
#if CONFIG_IS_ENABLED(CLK)
ret = clk_enable(&sfc->hclk);
if (ret)
- debug("Enable ahb clock fail %s: %d\n", bus->name, ret);
+ dev_dbg(sfc->dev, "sfc Enable ahb clock fail %s: %d\n", bus->name, ret);
ret = clk_enable(&sfc->clk);
if (ret)
- debug("Enable clock fail for %s: %d\n", bus->name, ret);
-
- ret = clk_set_rate(&sfc->clk, SFC_DEFAULT_SPEED_HZ);
- if (ret)
- debug("Could not set sfc clock for %s: %d\n", bus->name, ret);
+ dev_dbg(sfc->dev, "sfc Enable clock fail for %s: %d\n", bus->name, ret);
#endif
ret = rockchip_sfc_init(sfc);
@@ -278,7 +271,8 @@
sfc->max_iosize = rockchip_sfc_get_max_iosize(sfc);
sfc->version = rockchip_sfc_get_version(sfc);
- sfc->speed = SFC_DEFAULT_SPEED_HZ;
+ sfc->max_freq = SFC_MAX_SPEED;
+ sfc->dev = bus;
return 0;
@@ -291,33 +285,38 @@
return ret;
}
-static inline int rockchip_sfc_get_fifo_level(struct rockchip_sfc *sfc, int wr)
+static int rockchip_sfc_wait_txfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us)
{
- u32 fsr = readl(sfc->regbase + SFC_FSR);
- int level;
+ int ret = 0;
+ u32 status;
- if (wr)
- level = (fsr & SFC_FSR_TXLV_MASK) >> SFC_FSR_TXLV_SHIFT;
- else
- level = (fsr & SFC_FSR_RXLV_MASK) >> SFC_FSR_RXLV_SHIFT;
+ ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status,
+ status & SFC_FSR_TXLV_MASK,
+ timeout_us);
+ if (ret) {
+ dev_dbg(sfc->dev, "sfc wait tx fifo timeout\n");
+
+ return -ETIMEDOUT;
+ }
- return level;
+ return (status & SFC_FSR_TXLV_MASK) >> SFC_FSR_TXLV_SHIFT;
}
-static int rockchip_sfc_wait_fifo_ready(struct rockchip_sfc *sfc, int wr, u32 timeout)
+static int rockchip_sfc_wait_rxfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us)
{
- unsigned long tbase = get_timer(0);
- int level;
+ int ret = 0;
+ u32 status;
- while (!(level = rockchip_sfc_get_fifo_level(sfc, wr))) {
- if (get_timer(tbase) > timeout) {
- debug("%s fifo timeout\n", wr ? "write" : "read");
- return -ETIMEDOUT;
- }
- udelay(1);
+ ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status,
+ status & SFC_FSR_RXLV_MASK,
+ timeout_us);
+ if (ret) {
+ dev_dbg(sfc->dev, "sfc wait rx fifo timeout\n");
+
+ return -ETIMEDOUT;
}
- return level;
+ return (status & SFC_FSR_RXLV_MASK) >> SFC_FSR_RXLV_SHIFT;
}
static void rockchip_sfc_adjust_op_work(struct spi_mem_op *op)
@@ -411,11 +410,11 @@
ctrl |= SFC_CTRL_PHASE_SEL_NEGETIVE;
cmd |= plat->cs << SFC_CMD_CS_SHIFT;
- debug("addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n",
- op->addr.nbytes, op->addr.buswidth,
- op->dummy.nbytes, op->dummy.buswidth);
- debug("ctrl=%x cmd=%x addr=%llx len=%x\n",
- ctrl, cmd, op->addr.val, len);
+ dev_dbg(sfc->dev, "sfc addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n",
+ op->addr.nbytes, op->addr.buswidth,
+ op->dummy.nbytes, op->dummy.buswidth);
+ dev_dbg(sfc->dev, "sfc ctrl=%x cmd=%x addr=%llx len=%x\n",
+ ctrl, cmd, op->addr.val, len);
writel(ctrl, sfc->regbase + SFC_CTRL);
writel(cmd, sfc->regbase + SFC_CMD);
@@ -435,7 +434,7 @@
dwords = len >> 2;
while (dwords) {
- tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_WR, 1000);
+ tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000);
if (tx_level < 0)
return tx_level;
write_words = min_t(u32, tx_level, dwords);
@@ -446,7 +445,7 @@
/* write the rest non word aligned bytes */
if (bytes) {
- tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_WR, 1000);
+ tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000);
if (tx_level < 0)
return tx_level;
memcpy(&tmp, buf, bytes);
@@ -467,7 +466,7 @@
/* word aligned access only */
dwords = len >> 2;
while (dwords) {
- rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_RD, 1000);
+ rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000);
if (rx_level < 0)
return rx_level;
read_words = min_t(u32, rx_level, dwords);
@@ -478,7 +477,7 @@
/* read the rest non word aligned bytes */
if (bytes) {
- rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_RD, 1000);
+ rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000);
if (rx_level < 0)
return rx_level;
tmp = readl(sfc->regbase + SFC_DATA);
@@ -492,7 +491,7 @@
{
writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR);
writel((u32)dma_buf, sfc->regbase + SFC_DMA_ADDR);
- writel(0x1, sfc->regbase + SFC_DMA_TRIGGER);
+ writel(SFC_DMA_TRIGGER_START, sfc->regbase + SFC_DMA_TRIGGER);
return len;
}
@@ -500,7 +499,7 @@
static int rockchip_sfc_xfer_data_poll(struct rockchip_sfc *sfc,
const struct spi_mem_op *op, u32 len)
{
- debug("xfer_poll len=%x\n", len);
+ dev_dbg(sfc->dev, "sfc xfer_poll len=%x\n", len);
if (op->data.dir == SPI_MEM_DATA_OUT)
return rockchip_sfc_write_fifo(sfc, op->data.buf.out, len);
@@ -516,7 +515,7 @@
void *dma_buf;
int ret;
- debug("xfer_dma len=%x\n", len);
+ dev_dbg(sfc->dev, "sfc xfer_dma len=%x\n", len);
if (op->data.dir == SPI_MEM_DATA_OUT) {
dma_buf = (void *)op->data.buf.out;
@@ -539,19 +538,17 @@
static int rockchip_sfc_xfer_done(struct rockchip_sfc *sfc, u32 timeout_us)
{
- unsigned long tbase = get_timer(0);
int ret = 0;
- u32 timeout = timeout_us;
-
- while (readl(sfc->regbase + SFC_SR) & SFC_SR_IS_BUSY) {
- if (get_timer(tbase) > timeout) {
- printf("wait sfc idle timeout\n");
- rockchip_sfc_reset(sfc);
+ u32 status;
- return -ETIMEDOUT;
- }
+ ret = readl_poll_timeout(sfc->regbase + SFC_SR, status,
+ !(status & SFC_SR_IS_BUSY),
+ timeout_us);
+ if (ret) {
+ dev_err(sfc->dev, "wait sfc idle timeout\n");
+ rockchip_sfc_reset(sfc);
- udelay(1);
+ ret = -EIO;
}
return ret;
@@ -564,33 +561,16 @@
u32 len = min_t(u32, op->data.nbytes, sfc->max_iosize);
int ret;
-#if CONFIG_IS_ENABLED(CLK)
- if (unlikely(mem->max_hz != sfc->speed)) {
- ret = clk_set_rate(&sfc->clk, clamp(mem->max_hz, (uint)SFC_MIN_SPEED_HZ,
- (uint)SFC_MAX_SPEED_HZ));
- if (ret < 0) {
- printf("set_freq=%dHz fail, check if it's the cru support level\n",
- mem->max_hz);
- return ret;
- }
-
- sfc->max_freq = mem->max_hz;
- sfc->speed = mem->max_hz;
- debug("set_freq=%dHz real_freq=%dHz\n", sfc->max_freq, sfc->speed);
- }
-#endif
-
rockchip_sfc_adjust_op_work((struct spi_mem_op *)op);
-
rockchip_sfc_xfer_setup(sfc, mem, op, len);
if (len) {
- if (likely(sfc->use_dma) && !(len & 0x3) && len >= SFC_DMA_TRANS_THRETHOLD)
+ if (likely(sfc->use_dma) && len >= SFC_DMA_TRANS_THRETHOLD)
ret = rockchip_sfc_xfer_data_dma(sfc, op, len);
else
ret = rockchip_sfc_xfer_data_poll(sfc, op, len);
if (ret != len) {
- printf("xfer data failed ret %d dir %d\n", ret, op->data.dir);
+ dev_err(sfc->dev, "xfer data failed ret %d dir %d\n", ret, op->data.dir);
return -EIO;
}
@@ -604,13 +584,32 @@
struct rockchip_sfc *sfc = dev_get_plat(mem->dev->parent);
op->data.nbytes = min(op->data.nbytes, sfc->max_iosize);
+
return 0;
}
static int rockchip_sfc_set_speed(struct udevice *bus, uint speed)
{
- /* We set up speed later for each transmission.
- */
+ struct rockchip_sfc *sfc = dev_get_plat(bus);
+
+ if (speed > sfc->max_freq)
+ speed = sfc->max_freq;
+
+ if (speed == sfc->speed)
+ return 0;
+
+#if CONFIG_IS_ENABLED(CLK)
+ int ret = clk_set_rate(&sfc->clk, speed);
+
+ if (ret < 0) {
+ dev_err(sfc->dev, "set_freq=%dHz fail, check if it's the cru support level\n",
+ speed);
+ return ret;
+ }
+ sfc->speed = speed;
+#else
+ dev_dbg(sfc->dev, "sfc failed, CLK not support\n");
+#endif
return 0;
}
diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c
index 4ca5d3a..bc2f544 100644
--- a/drivers/spi/spi-sunxi.c
+++ b/drivers/spi/spi-sunxi.c
@@ -245,7 +245,7 @@
break;
}
- pin = name_to_gpio(pin_name);
+ pin = sunxi_name_to_gpio(pin_name);
if (pin < 0)
break;
diff --git a/drivers/spi/stm32_spi.c b/drivers/spi/stm32_spi.c
index bd85140..fe5419e 100644
--- a/drivers/spi/stm32_spi.c
+++ b/drivers/spi/stm32_spi.c
@@ -97,11 +97,14 @@
#define SPI_SIMPLEX_RX 2
#define SPI_HALF_DUPLEX 3
-struct stm32_spi_priv {
+struct stm32_spi_plat {
void __iomem *base;
struct clk clk;
struct reset_ctl rst_ctl;
struct gpio_desc cs_gpios[MAX_CS_COUNT];
+};
+
+struct stm32_spi_priv {
ulong bus_clk_rate;
unsigned int fifo_size;
unsigned int cur_bpw;
@@ -115,28 +118,32 @@
bool cs_high;
};
-static void stm32_spi_write_txfifo(struct stm32_spi_priv *priv)
+static void stm32_spi_write_txfifo(struct udevice *bus)
{
+ struct stm32_spi_priv *priv = dev_get_priv(bus);
+ struct stm32_spi_plat *plat = dev_get_plat(bus);
+ void __iomem *base = plat->base;
+
while ((priv->tx_len > 0) &&
- (readl(priv->base + STM32_SPI_SR) & SPI_SR_TXP)) {
+ (readl(base + STM32_SPI_SR) & SPI_SR_TXP)) {
u32 offs = priv->cur_xferlen - priv->tx_len;
if (priv->tx_len >= sizeof(u32) &&
IS_ALIGNED((uintptr_t)(priv->tx_buf + offs), sizeof(u32))) {
const u32 *tx_buf32 = (const u32 *)(priv->tx_buf + offs);
- writel(*tx_buf32, priv->base + STM32_SPI_TXDR);
+ writel(*tx_buf32, base + STM32_SPI_TXDR);
priv->tx_len -= sizeof(u32);
} else if (priv->tx_len >= sizeof(u16) &&
IS_ALIGNED((uintptr_t)(priv->tx_buf + offs), sizeof(u16))) {
const u16 *tx_buf16 = (const u16 *)(priv->tx_buf + offs);
- writew(*tx_buf16, priv->base + STM32_SPI_TXDR);
+ writew(*tx_buf16, base + STM32_SPI_TXDR);
priv->tx_len -= sizeof(u16);
} else {
const u8 *tx_buf8 = (const u8 *)(priv->tx_buf + offs);
- writeb(*tx_buf8, priv->base + STM32_SPI_TXDR);
+ writeb(*tx_buf8, base + STM32_SPI_TXDR);
priv->tx_len -= sizeof(u8);
}
}
@@ -144,9 +151,12 @@
log_debug("%d bytes left\n", priv->tx_len);
}
-static void stm32_spi_read_rxfifo(struct stm32_spi_priv *priv)
+static void stm32_spi_read_rxfifo(struct udevice *bus)
{
- u32 sr = readl(priv->base + STM32_SPI_SR);
+ struct stm32_spi_priv *priv = dev_get_priv(bus);
+ struct stm32_spi_plat *plat = dev_get_plat(bus);
+ void __iomem *base = plat->base;
+ u32 sr = readl(base + STM32_SPI_SR);
u32 rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
while ((priv->rx_len > 0) &&
@@ -158,7 +168,7 @@
(priv->rx_len >= sizeof(u32) || (sr & SPI_SR_RXWNE))) {
u32 *rx_buf32 = (u32 *)(priv->rx_buf + offs);
- *rx_buf32 = readl(priv->base + STM32_SPI_RXDR);
+ *rx_buf32 = readl(base + STM32_SPI_RXDR);
priv->rx_len -= sizeof(u32);
} else if (IS_ALIGNED((uintptr_t)(priv->rx_buf + offs), sizeof(u16)) &&
(priv->rx_len >= sizeof(u16) ||
@@ -166,38 +176,38 @@
(rxplvl >= 2 || priv->cur_bpw > 8)))) {
u16 *rx_buf16 = (u16 *)(priv->rx_buf + offs);
- *rx_buf16 = readw(priv->base + STM32_SPI_RXDR);
+ *rx_buf16 = readw(base + STM32_SPI_RXDR);
priv->rx_len -= sizeof(u16);
} else {
u8 *rx_buf8 = (u8 *)(priv->rx_buf + offs);
- *rx_buf8 = readb(priv->base + STM32_SPI_RXDR);
+ *rx_buf8 = readb(base + STM32_SPI_RXDR);
priv->rx_len -= sizeof(u8);
}
- sr = readl(priv->base + STM32_SPI_SR);
+ sr = readl(base + STM32_SPI_SR);
rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
}
log_debug("%d bytes left\n", priv->rx_len);
}
-static int stm32_spi_enable(struct stm32_spi_priv *priv)
+static int stm32_spi_enable(void __iomem *base)
{
log_debug("\n");
/* Enable the SPI hardware */
- setbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_SPE);
+ setbits_le32(base + STM32_SPI_CR1, SPI_CR1_SPE);
return 0;
}
-static int stm32_spi_disable(struct stm32_spi_priv *priv)
+static int stm32_spi_disable(void __iomem *base)
{
log_debug("\n");
/* Disable the SPI hardware */
- clrbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_SPE);
+ clrbits_le32(base + STM32_SPI_CR1, SPI_CR1_SPE);
return 0;
}
@@ -205,45 +215,48 @@
static int stm32_spi_claim_bus(struct udevice *slave)
{
struct udevice *bus = dev_get_parent(slave);
- struct stm32_spi_priv *priv = dev_get_priv(bus);
+ struct stm32_spi_plat *plat = dev_get_plat(bus);
+ void __iomem *base = plat->base;
dev_dbg(slave, "\n");
/* Enable the SPI hardware */
- return stm32_spi_enable(priv);
+ return stm32_spi_enable(base);
}
static int stm32_spi_release_bus(struct udevice *slave)
{
struct udevice *bus = dev_get_parent(slave);
- struct stm32_spi_priv *priv = dev_get_priv(bus);
+ struct stm32_spi_plat *plat = dev_get_plat(bus);
+ void __iomem *base = plat->base;
dev_dbg(slave, "\n");
/* Disable the SPI hardware */
- return stm32_spi_disable(priv);
+ return stm32_spi_disable(base);
}
static void stm32_spi_stopxfer(struct udevice *dev)
{
- struct stm32_spi_priv *priv = dev_get_priv(dev);
+ struct stm32_spi_plat *plat = dev_get_plat(dev);
+ void __iomem *base = plat->base;
u32 cr1, sr;
int ret;
dev_dbg(dev, "\n");
- cr1 = readl(priv->base + STM32_SPI_CR1);
+ cr1 = readl(base + STM32_SPI_CR1);
if (!(cr1 & SPI_CR1_SPE))
return;
/* Wait on EOT or suspend the flow */
- ret = readl_poll_timeout(priv->base + STM32_SPI_SR, sr,
+ ret = readl_poll_timeout(base + STM32_SPI_SR, sr,
!(sr & SPI_SR_EOT), 100000);
if (ret < 0) {
if (cr1 & SPI_CR1_CSTART) {
- writel(cr1 | SPI_CR1_CSUSP, priv->base + STM32_SPI_CR1);
- if (readl_poll_timeout(priv->base + STM32_SPI_SR,
+ writel(cr1 | SPI_CR1_CSUSP, base + STM32_SPI_CR1);
+ if (readl_poll_timeout(base + STM32_SPI_SR,
sr, !(sr & SPI_SR_SUSP),
100000) < 0)
dev_err(dev, "Suspend request timeout\n");
@@ -251,11 +264,12 @@
}
/* clear status flags */
- setbits_le32(priv->base + STM32_SPI_IFCR, SPI_IFCR_ALL);
+ setbits_le32(base + STM32_SPI_IFCR, SPI_IFCR_ALL);
}
static int stm32_spi_set_cs(struct udevice *dev, unsigned int cs, bool enable)
{
+ struct stm32_spi_plat *plat = dev_get_plat(dev);
struct stm32_spi_priv *priv = dev_get_priv(dev);
dev_dbg(dev, "cs=%d enable=%d\n", cs, enable);
@@ -263,18 +277,20 @@
if (cs >= MAX_CS_COUNT)
return -ENODEV;
- if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
+ if (!dm_gpio_is_valid(&plat->cs_gpios[cs]))
return -EINVAL;
if (priv->cs_high)
enable = !enable;
- return dm_gpio_set_value(&priv->cs_gpios[cs], enable ? 1 : 0);
+ return dm_gpio_set_value(&plat->cs_gpios[cs], enable ? 1 : 0);
}
static int stm32_spi_set_mode(struct udevice *bus, uint mode)
{
struct stm32_spi_priv *priv = dev_get_priv(bus);
+ struct stm32_spi_plat *plat = dev_get_plat(bus);
+ void __iomem *base = plat->base;
u32 cfg2_clrb = 0, cfg2_setb = 0;
dev_dbg(bus, "mode=%d\n", mode);
@@ -295,7 +311,7 @@
cfg2_clrb |= SPI_CFG2_LSBFRST;
if (cfg2_clrb || cfg2_setb)
- clrsetbits_le32(priv->base + STM32_SPI_CFG2,
+ clrsetbits_le32(base + STM32_SPI_CFG2,
cfg2_clrb, cfg2_setb);
if (mode & SPI_CS_HIGH)
@@ -308,6 +324,8 @@
static int stm32_spi_set_fthlv(struct udevice *dev, u32 xfer_len)
{
struct stm32_spi_priv *priv = dev_get_priv(dev);
+ struct stm32_spi_plat *plat = dev_get_plat(dev);
+ void __iomem *base = plat->base;
u32 fthlv, half_fifo;
/* data packet should not exceed 1/2 of fifo space */
@@ -321,7 +339,7 @@
if (!fthlv)
fthlv = 1;
- clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_FTHLV,
+ clrsetbits_le32(base + STM32_SPI_CFG1, SPI_CFG1_FTHLV,
(fthlv - 1) << SPI_CFG1_FTHLV_SHIFT);
return 0;
@@ -330,6 +348,8 @@
static int stm32_spi_set_speed(struct udevice *bus, uint hz)
{
struct stm32_spi_priv *priv = dev_get_priv(bus);
+ struct stm32_spi_plat *plat = dev_get_plat(bus);
+ void __iomem *base = plat->base;
u32 mbrdiv;
long div;
@@ -353,7 +373,7 @@
if (!mbrdiv)
return -EINVAL;
- clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_MBR,
+ clrsetbits_le32(base + STM32_SPI_CFG1, SPI_CFG1_MBR,
(mbrdiv - 1) << SPI_CFG1_MBR_SHIFT);
priv->cur_hz = hz;
@@ -367,6 +387,8 @@
struct udevice *bus = dev_get_parent(slave);
struct dm_spi_slave_plat *slave_plat;
struct stm32_spi_priv *priv = dev_get_priv(bus);
+ struct stm32_spi_plat *plat = dev_get_plat(bus);
+ void __iomem *base = plat->base;
u32 sr;
u32 ifcr = 0;
u32 xferlen;
@@ -376,7 +398,7 @@
xferlen = bitlen / 8;
if (xferlen <= SPI_CR2_TSIZE)
- writel(xferlen, priv->base + STM32_SPI_CR2);
+ writel(xferlen, base + STM32_SPI_CR2);
else
return -EMSGSIZE;
@@ -396,15 +418,15 @@
priv->cur_xferlen = xferlen;
/* Disable the SPI hardware to unlock CFG1/CFG2 registers */
- stm32_spi_disable(priv);
+ stm32_spi_disable(base);
- clrsetbits_le32(priv->base + STM32_SPI_CFG2, SPI_CFG2_COMM,
+ clrsetbits_le32(base + STM32_SPI_CFG2, SPI_CFG2_COMM,
mode << SPI_CFG2_COMM_SHIFT);
stm32_spi_set_fthlv(bus, xferlen);
/* Enable the SPI hardware */
- stm32_spi_enable(priv);
+ stm32_spi_enable(base);
}
dev_dbg(bus, "priv->tx_len=%d priv->rx_len=%d\n",
@@ -416,12 +438,12 @@
/* Be sure to have data in fifo before starting data transfer */
if (priv->tx_buf)
- stm32_spi_write_txfifo(priv);
+ stm32_spi_write_txfifo(bus);
- setbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_CSTART);
+ setbits_le32(base + STM32_SPI_CR1, SPI_CR1_CSTART);
while (1) {
- sr = readl(priv->base + STM32_SPI_SR);
+ sr = readl(base + STM32_SPI_SR);
if (sr & SPI_SR_OVR) {
dev_err(bus, "Overrun: RX data lost\n");
@@ -433,7 +455,7 @@
dev_warn(bus, "System too slow is limiting data throughput\n");
if (priv->rx_buf && priv->rx_len > 0)
- stm32_spi_read_rxfifo(priv);
+ stm32_spi_read_rxfifo(bus);
ifcr |= SPI_SR_SUSP;
}
@@ -443,23 +465,23 @@
if (sr & SPI_SR_TXP)
if (priv->tx_buf && priv->tx_len > 0)
- stm32_spi_write_txfifo(priv);
+ stm32_spi_write_txfifo(bus);
if (sr & SPI_SR_RXP)
if (priv->rx_buf && priv->rx_len > 0)
- stm32_spi_read_rxfifo(priv);
+ stm32_spi_read_rxfifo(bus);
if (sr & SPI_SR_EOT) {
if (priv->rx_buf && priv->rx_len > 0)
- stm32_spi_read_rxfifo(priv);
+ stm32_spi_read_rxfifo(bus);
break;
}
- writel(ifcr, priv->base + STM32_SPI_IFCR);
+ writel(ifcr, base + STM32_SPI_IFCR);
}
/* clear status flags */
- setbits_le32(priv->base + STM32_SPI_IFCR, SPI_IFCR_ALL);
+ setbits_le32(base + STM32_SPI_IFCR, SPI_IFCR_ALL);
stm32_spi_stopxfer(bus);
if (flags & SPI_XFER_END)
@@ -470,42 +492,72 @@
static int stm32_spi_get_fifo_size(struct udevice *dev)
{
- struct stm32_spi_priv *priv = dev_get_priv(dev);
+ struct stm32_spi_plat *plat = dev_get_plat(dev);
+ void __iomem *base = plat->base;
u32 count = 0;
- stm32_spi_enable(priv);
+ stm32_spi_enable(base);
- while (readl(priv->base + STM32_SPI_SR) & SPI_SR_TXP)
- writeb(++count, priv->base + STM32_SPI_TXDR);
+ while (readl(base + STM32_SPI_SR) & SPI_SR_TXP)
+ writeb(++count, base + STM32_SPI_TXDR);
- stm32_spi_disable(priv);
+ stm32_spi_disable(base);
dev_dbg(dev, "%d x 8-bit fifo size\n", count);
return count;
}
+static int stm32_spi_of_to_plat(struct udevice *dev)
+{
+ struct stm32_spi_plat *plat = dev_get_plat(dev);
+ int ret;
+
+ plat->base = dev_read_addr_ptr(dev);
+ if (!plat->base) {
+ dev_err(dev, "can't get registers base address\n");
+ return -ENOENT;
+ }
+
+ ret = clk_get_by_index(dev, 0, &plat->clk);
+ if (ret < 0)
+ return ret;
+
+ ret = reset_get_by_index(dev, 0, &plat->rst_ctl);
+ if (ret < 0)
+ goto clk_err;
+
+ ret = gpio_request_list_by_name(dev, "cs-gpios", plat->cs_gpios,
+ ARRAY_SIZE(plat->cs_gpios), 0);
+ if (ret < 0) {
+ dev_err(dev, "Can't get %s cs gpios: %d", dev->name, ret);
+ ret = -ENOENT;
+ goto clk_err;
+ }
+
+ return 0;
+
+clk_err:
+ clk_free(&plat->clk);
+
+ return ret;
+}
+
static int stm32_spi_probe(struct udevice *dev)
{
+ struct stm32_spi_plat *plat = dev_get_plat(dev);
struct stm32_spi_priv *priv = dev_get_priv(dev);
+ void __iomem *base = plat->base;
unsigned long clk_rate;
int ret;
unsigned int i;
- priv->base = dev_remap_addr(dev);
- if (!priv->base)
- return -EINVAL;
-
/* enable clock */
- ret = clk_get_by_index(dev, 0, &priv->clk);
+ ret = clk_enable(&plat->clk);
if (ret < 0)
return ret;
- ret = clk_enable(&priv->clk);
- if (ret < 0)
- return ret;
-
- clk_rate = clk_get_rate(&priv->clk);
+ clk_rate = clk_get_rate(&plat->clk);
if (!clk_rate) {
ret = -EINVAL;
goto clk_err;
@@ -514,46 +566,34 @@
priv->bus_clk_rate = clk_rate;
/* perform reset */
- ret = reset_get_by_index(dev, 0, &priv->rst_ctl);
- if (ret < 0)
- goto clk_err;
-
- reset_assert(&priv->rst_ctl);
+ reset_assert(&plat->rst_ctl);
udelay(2);
- reset_deassert(&priv->rst_ctl);
-
- ret = gpio_request_list_by_name(dev, "cs-gpios", priv->cs_gpios,
- ARRAY_SIZE(priv->cs_gpios), 0);
- if (ret < 0) {
- dev_err(dev, "Can't get cs gpios: %d", ret);
- goto reset_err;
- }
+ reset_deassert(&plat->rst_ctl);
priv->fifo_size = stm32_spi_get_fifo_size(dev);
-
priv->cur_mode = SPI_FULL_DUPLEX;
priv->cur_xferlen = 0;
priv->cur_bpw = SPI_DEFAULT_WORDLEN;
- clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_DSIZE,
+ clrsetbits_le32(base + STM32_SPI_CFG1, SPI_CFG1_DSIZE,
priv->cur_bpw - 1);
- for (i = 0; i < ARRAY_SIZE(priv->cs_gpios); i++) {
- if (!dm_gpio_is_valid(&priv->cs_gpios[i]))
+ for (i = 0; i < ARRAY_SIZE(plat->cs_gpios); i++) {
+ if (!dm_gpio_is_valid(&plat->cs_gpios[i]))
continue;
- dm_gpio_set_dir_flags(&priv->cs_gpios[i],
+ dm_gpio_set_dir_flags(&plat->cs_gpios[i],
GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
}
/* Ensure I2SMOD bit is kept cleared */
- clrbits_le32(priv->base + STM32_SPI_I2SCFGR, SPI_I2SCFGR_I2SMOD);
+ clrbits_le32(base + STM32_SPI_I2SCFGR, SPI_I2SCFGR_I2SMOD);
/*
* - SS input value high
* - transmitter half duplex direction
* - automatic communication suspend when RX-Fifo is full
*/
- setbits_le32(priv->base + STM32_SPI_CR1,
+ setbits_le32(base + STM32_SPI_CR1,
SPI_CR1_SSI | SPI_CR1_HDDIR | SPI_CR1_MASRX);
/*
@@ -562,40 +602,38 @@
* SS input value is determined by the SSI bit
* - keep control of all associated GPIOs
*/
- setbits_le32(priv->base + STM32_SPI_CFG2,
+ setbits_le32(base + STM32_SPI_CFG2,
SPI_CFG2_MASTER | SPI_CFG2_SSM | SPI_CFG2_AFCNTR);
return 0;
-reset_err:
- reset_free(&priv->rst_ctl);
-
clk_err:
- clk_disable(&priv->clk);
- clk_free(&priv->clk);
+ clk_disable(&plat->clk);
+ clk_free(&plat->clk);
return ret;
};
static int stm32_spi_remove(struct udevice *dev)
{
- struct stm32_spi_priv *priv = dev_get_priv(dev);
+ struct stm32_spi_plat *plat = dev_get_plat(dev);
+ void __iomem *base = plat->base;
int ret;
stm32_spi_stopxfer(dev);
- stm32_spi_disable(priv);
+ stm32_spi_disable(base);
- ret = reset_assert(&priv->rst_ctl);
+ ret = reset_assert(&plat->rst_ctl);
if (ret < 0)
return ret;
- reset_free(&priv->rst_ctl);
+ reset_free(&plat->rst_ctl);
- ret = clk_disable(&priv->clk);
+ ret = clk_disable(&plat->clk);
if (ret < 0)
return ret;
- clk_free(&priv->clk);
+ clk_free(&plat->clk);
return ret;
};
@@ -618,7 +656,9 @@
.id = UCLASS_SPI,
.of_match = stm32_spi_ids,
.ops = &stm32_spi_ops,
- .priv_auto = sizeof(struct stm32_spi_priv),
+ .of_to_plat = stm32_spi_of_to_plat,
+ .plat_auto = sizeof(struct stm32_spi_plat),
+ .priv_auto = sizeof(struct stm32_spi_priv),
.probe = stm32_spi_probe,
.remove = stm32_spi_remove,
};
diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c
index 6ea9e39..cbc3647 100644
--- a/drivers/timer/timer-uclass.c
+++ b/drivers/timer/timer-uclass.c
@@ -148,7 +148,7 @@
* If the timer is not marked to be bound before
* relocation, bind it anyway.
*/
- if (!lists_bind_fdt(dm_root(), node, &dev, false)) {
+ if (!lists_bind_fdt(dm_root(), node, &dev, NULL, false)) {
ret = device_probe(dev);
if (ret)
return ret;
diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h
index 0cdf47c..06e6a48 100644
--- a/drivers/usb/gadget/gadget_chips.h
+++ b/drivers/usb/gadget/gadget_chips.h
@@ -167,6 +167,12 @@
#define gadget_is_mtu3(g) 0
#endif
+#ifdef CONFIG_USB_GADGET_DWC2_OTG
+#define gadget_is_dwc2(g) (!strcmp("dwc2-udc", (g)->name))
+#else
+#define gadget_is_dwc2(g) 0
+#endif
+
/**
* usb_gadget_controller_number - support bcdDevice id convention
* @gadget: the controller being driven
@@ -232,5 +238,7 @@
return 0x25;
else if (gadget_is_mtu3(gadget))
return 0x26;
+ else if (gadget_is_dwc2(gadget))
+ return 0x27;
return -ENOENT;
}
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 10b0479..ccecb5a 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -139,6 +139,9 @@
if USB_EHCI_HCD
+config USB_EHCI_IS_TDI
+ bool
+
config USB_EHCI_ATMEL
bool "Support for Atmel on-chip EHCI USB controller"
depends on ARCH_AT91
@@ -150,6 +153,7 @@
bool "Support for Marvell on-chip EHCI USB controller"
depends on ARCH_MVEBU || ARCH_KIRKWOOD || ARCH_ORION5X
default y
+ select USB_EHCI_IS_TDI if !ARM64
---help---
Enables support for the on-chip EHCI controller on MVEBU SoCs.
@@ -175,6 +179,14 @@
---help---
Enables support for the on-chip EHCI controller on i.MX7 SoCs.
+config USB_EHCI_MXS
+ bool "Support for i.MX23 EHCI USB controller"
+ depends on ARCH_MX23
+ default y
+ select USB_EHCI_IS_TDI
+ help
+ Enables support for the on-chip EHCI controller on i.MX23 SoCs.
+
config USB_EHCI_OMAP
bool "Support for OMAP3+ on-chip EHCI USB controller"
depends on ARCH_OMAP2PLUS
@@ -251,12 +263,14 @@
config USB_EHCI_TEGRA
bool "Support for NVIDIA Tegra on-chip EHCI USB controller"
depends on ARCH_TEGRA
+ select USB_EHCI_IS_TDI
---help---
Enable support for Tegra on-chip EHCI USB controller
config USB_EHCI_ZYNQ
bool "Support for Xilinx Zynq on-chip EHCI USB controller"
default y if ARCH_ZYNQ
+ select USB_EHCI_IS_TDI
---help---
Enable support for Zynq on-chip EHCI USB controller
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index ba75c27..e635526 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -108,7 +108,7 @@
},
};
-#if defined(CONFIG_EHCI_IS_TDI)
+#if defined(CONFIG_USB_EHCI_IS_TDI)
#define ehci_is_TDI() (1)
#else
#define ehci_is_TDI() (0)
diff --git a/drivers/usb/host/usb-sandbox.c b/drivers/usb/host/usb-sandbox.c
index d7cc92a..d1103dc 100644
--- a/drivers/usb/host/usb-sandbox.c
+++ b/drivers/usb/host/usb-sandbox.c
@@ -9,6 +9,13 @@
#include <log.h>
#include <usb.h>
#include <dm/root.h>
+#include <linux/usb/gadget.h>
+
+struct sandbox_udc {
+ struct usb_gadget gadget;
+};
+
+struct sandbox_udc *this_controller;
struct sandbox_usb_ctrl {
int rootdev;
@@ -117,6 +124,27 @@
return ret;
}
+int usb_gadget_handle_interrupts(int index)
+{
+ return 0;
+}
+
+int usb_gadget_register_driver(struct usb_gadget_driver *driver)
+{
+ struct sandbox_udc *dev = this_controller;
+
+ return driver->bind(&dev->gadget);
+}
+
+int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
+{
+ struct sandbox_udc *dev = this_controller;
+
+ driver->unbind(&dev->gadget);
+
+ return 0;
+}
+
static int sandbox_alloc_device(struct udevice *dev, struct usb_device *udev)
{
struct sandbox_usb_ctrl *ctrl = dev_get_priv(dev);
diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c
index fea4105..7e62e3f 100644
--- a/drivers/usb/musb-new/sunxi.c
+++ b/drivers/usb/musb-new/sunxi.c
@@ -25,8 +25,6 @@
#include <reset.h>
#include <asm/arch/cpu.h>
#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
-#include <asm-generic/gpio.h>
#include <dm/device_compat.h>
#include <dm/lists.h>
#include <dm/root.h>
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index b1f8a9c..2f4650f 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -452,7 +452,7 @@
default ""
---help---
The reset pin of SSD2828 chip. This takes a string in the format
- understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H.
+ understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H.
config VIDEO_LCD_TDO_TL070WSH30
bool "TDO TL070WSH30 DSI LCD panel support"
@@ -477,7 +477,7 @@
This is one of the SPI communication pins, involved in setting up a
working LCD configuration. The exact role of SPI may differ for
different hardware setups. The option takes a string in the format
- understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H.
+ understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H.
config VIDEO_LCD_SPI_SCLK
string "SPI SCLK pin for LCD related config job"
@@ -487,7 +487,7 @@
This is one of the SPI communication pins, involved in setting up a
working LCD configuration. The exact role of SPI may differ for
different hardware setups. The option takes a string in the format
- understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H.
+ understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H.
config VIDEO_LCD_SPI_MOSI
string "SPI MOSI pin for LCD related config job"
@@ -497,7 +497,7 @@
This is one of the SPI communication pins, involved in setting up a
working LCD configuration. The exact role of SPI may differ for
different hardware setups. The option takes a string in the format
- understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H.
+ understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H.
config VIDEO_LCD_SPI_MISO
string "SPI MISO pin for LCD related config job (optional)"
@@ -509,7 +509,7 @@
different hardware setups. If wired up, this pin may provide additional
useful functionality. Such as bi-directional communication with the
hardware and LCD panel id retrieval (if the panel can report it). The
- option takes a string in the format understood by 'name_to_gpio'
+ option takes a string in the format understood by 'sunxi_name_to_gpio'
function, e.g. PH1 for pin 1 of port H.
source "drivers/video/meson/Kconfig"
@@ -648,6 +648,12 @@
source "drivers/video/imx/Kconfig"
+config VIDEO_MXS
+ bool "Enable video support on i.MX28/i.MX6UL/i.MX7 SoCs"
+ depends on DM_VIDEO
+ help
+ Enable framebuffer driver for i.MX28/i.MX6UL/i.MX7 processors
+
config VIDEO_NX
bool "Enable video support on Nexell SoC"
depends on ARCH_S5P6818 || ARCH_S5P4418
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index f6d07b3..8956b5f 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -61,7 +61,6 @@
obj-${CONFIG_VIDEO_MESON} += meson/
obj-${CONFIG_VIDEO_MIPI_DSI} += mipi_dsi.o
obj-$(CONFIG_VIDEO_MVEBU) += mvebu_lcd.o
-obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
obj-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o
obj-$(CONFIG_VIDEO_NX) += nexell_display.o videomodes.o nexell/
obj-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o
diff --git a/drivers/video/anx9804.c b/drivers/video/anx9804.c
index 3037ff3..52b5988 100644
--- a/drivers/video/anx9804.c
+++ b/drivers/video/anx9804.c
@@ -21,18 +21,23 @@
* This function will init an anx9804 parallel lcd to dp bridge chip
* using the passed in parameters.
*
- * @i2c_bus: Number of the i2c bus to which the anx9804 is connected.
+ * @i2c_bus: Device of the i2c bus to which the anx9804 is connected.
* @lanes: Number of displayport lanes to use
* @data_rate: Register value for the bandwidth reg 0x06: 1.62G, 0x0a: 2.7G
* @bpp: Bits per pixel, must be 18 or 24
*/
-void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp)
+void anx9804_init(struct udevice *i2c_bus, u8 lanes, u8 data_rate, int bpp)
{
- unsigned int orig_i2c_bus = i2c_get_bus_num();
- u8 c, colordepth;
- int i;
+ struct udevice *chip0, *chip1;
+ int c, colordepth, i, ret;
- i2c_set_bus_num(i2c_bus);
+ ret = i2c_get_chip(i2c_bus, 0x38, 1, &chip0);
+ if (ret)
+ return;
+
+ ret = i2c_get_chip(i2c_bus, 0x39, 1, &chip1);
+ if (ret)
+ return;
if (bpp == 18)
colordepth = 0x00; /* 6 bit */
@@ -40,24 +45,23 @@
colordepth = 0x10; /* 8 bit */
/* Reset */
- i2c_reg_write(0x39, ANX9804_RST_CTRL_REG, 1);
+ dm_i2c_reg_write(chip1, ANX9804_RST_CTRL_REG, 1);
mdelay(100);
- i2c_reg_write(0x39, ANX9804_RST_CTRL_REG, 0);
+ dm_i2c_reg_write(chip1, ANX9804_RST_CTRL_REG, 0);
/* Write 0 to the powerdown reg (powerup everything) */
- i2c_reg_write(0x39, ANX9804_POWERD_CTRL_REG, 0);
+ dm_i2c_reg_write(chip1, ANX9804_POWERD_CTRL_REG, 0);
- c = i2c_reg_read(0x39, ANX9804_DEV_IDH_REG);
+ c = dm_i2c_reg_read(chip1, ANX9804_DEV_IDH_REG);
if (c != 0x98) {
printf("Error anx9804 chipid mismatch\n");
- i2c_set_bus_num(orig_i2c_bus);
return;
}
for (i = 0; i < 100; i++) {
- c = i2c_reg_read(0x38, ANX9804_SYS_CTRL2_REG);
- i2c_reg_write(0x38, ANX9804_SYS_CTRL2_REG, c);
- c = i2c_reg_read(0x38, ANX9804_SYS_CTRL2_REG);
+ c = dm_i2c_reg_read(chip0, ANX9804_SYS_CTRL2_REG);
+ dm_i2c_reg_write(chip0, ANX9804_SYS_CTRL2_REG, c);
+ c = dm_i2c_reg_read(chip0, ANX9804_SYS_CTRL2_REG);
if ((c & ANX9804_SYS_CTRL2_CHA_STA) == 0)
break;
@@ -66,51 +70,51 @@
if (i == 100)
printf("Error anx9804 clock is not stable\n");
- i2c_reg_write(0x39, ANX9804_VID_CTRL2_REG, colordepth);
+ dm_i2c_reg_write(chip1, ANX9804_VID_CTRL2_REG, colordepth);
/* Set a bunch of analog related register values */
- i2c_reg_write(0x38, ANX9804_PLL_CTRL_REG, 0x07);
- i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL3, 0x19);
- i2c_reg_write(0x39, ANX9804_PLL_CTRL3, 0xd9);
- i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG, ANX9804_RST_CTRL2_AC_MODE);
- i2c_reg_write(0x39, ANX9804_ANALOG_DEBUG_REG1, 0xf0);
- i2c_reg_write(0x39, ANX9804_ANALOG_DEBUG_REG3, 0x99);
- i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL1, 0x7b);
- i2c_reg_write(0x38, ANX9804_LINK_DEBUG_REG, 0x30);
- i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL, 0x06);
+ dm_i2c_reg_write(chip0, ANX9804_PLL_CTRL_REG, 0x07);
+ dm_i2c_reg_write(chip1, ANX9804_PLL_FILTER_CTRL3, 0x19);
+ dm_i2c_reg_write(chip1, ANX9804_PLL_CTRL3, 0xd9);
+ dm_i2c_reg_write(chip1, ANX9804_RST_CTRL2_REG, ANX9804_RST_CTRL2_AC_MODE);
+ dm_i2c_reg_write(chip1, ANX9804_ANALOG_DEBUG_REG1, 0xf0);
+ dm_i2c_reg_write(chip1, ANX9804_ANALOG_DEBUG_REG3, 0x99);
+ dm_i2c_reg_write(chip1, ANX9804_PLL_FILTER_CTRL1, 0x7b);
+ dm_i2c_reg_write(chip0, ANX9804_LINK_DEBUG_REG, 0x30);
+ dm_i2c_reg_write(chip1, ANX9804_PLL_FILTER_CTRL, 0x06);
/* Force HPD */
- i2c_reg_write(0x38, ANX9804_SYS_CTRL3_REG,
- ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL);
+ dm_i2c_reg_write(chip0, ANX9804_SYS_CTRL3_REG,
+ ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL);
/* Power up and configure lanes */
- i2c_reg_write(0x38, ANX9804_ANALOG_POWER_DOWN_REG, 0x00);
- i2c_reg_write(0x38, ANX9804_TRAINING_LANE0_SET_REG, 0x00);
- i2c_reg_write(0x38, ANX9804_TRAINING_LANE1_SET_REG, 0x00);
- i2c_reg_write(0x38, ANX9804_TRAINING_LANE2_SET_REG, 0x00);
- i2c_reg_write(0x38, ANX9804_TRAINING_LANE3_SET_REG, 0x00);
+ dm_i2c_reg_write(chip0, ANX9804_ANALOG_POWER_DOWN_REG, 0x00);
+ dm_i2c_reg_write(chip0, ANX9804_TRAINING_LANE0_SET_REG, 0x00);
+ dm_i2c_reg_write(chip0, ANX9804_TRAINING_LANE1_SET_REG, 0x00);
+ dm_i2c_reg_write(chip0, ANX9804_TRAINING_LANE2_SET_REG, 0x00);
+ dm_i2c_reg_write(chip0, ANX9804_TRAINING_LANE3_SET_REG, 0x00);
/* Reset AUX CH */
- i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG,
- ANX9804_RST_CTRL2_AC_MODE | ANX9804_RST_CTRL2_AUX);
- i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG,
- ANX9804_RST_CTRL2_AC_MODE);
+ dm_i2c_reg_write(chip1, ANX9804_RST_CTRL2_REG,
+ ANX9804_RST_CTRL2_AC_MODE | ANX9804_RST_CTRL2_AUX);
+ dm_i2c_reg_write(chip1, ANX9804_RST_CTRL2_REG,
+ ANX9804_RST_CTRL2_AC_MODE);
/* Powerdown audio and some other unused bits */
- i2c_reg_write(0x39, ANX9804_POWERD_CTRL_REG, ANX9804_POWERD_AUDIO);
- i2c_reg_write(0x38, ANX9804_HDCP_CONTROL_0_REG, 0x00);
- i2c_reg_write(0x38, 0xa7, 0x00);
+ dm_i2c_reg_write(chip1, ANX9804_POWERD_CTRL_REG, ANX9804_POWERD_AUDIO);
+ dm_i2c_reg_write(chip0, ANX9804_HDCP_CONTROL_0_REG, 0x00);
+ dm_i2c_reg_write(chip0, 0xa7, 0x00);
/* Set data-rate / lanes */
- i2c_reg_write(0x38, ANX9804_LINK_BW_SET_REG, data_rate);
- i2c_reg_write(0x38, ANX9804_LANE_COUNT_SET_REG, lanes);
+ dm_i2c_reg_write(chip0, ANX9804_LINK_BW_SET_REG, data_rate);
+ dm_i2c_reg_write(chip0, ANX9804_LANE_COUNT_SET_REG, lanes);
/* Link training */
- i2c_reg_write(0x38, ANX9804_LINK_TRAINING_CTRL_REG,
- ANX9804_LINK_TRAINING_CTRL_EN);
+ dm_i2c_reg_write(chip0, ANX9804_LINK_TRAINING_CTRL_REG,
+ ANX9804_LINK_TRAINING_CTRL_EN);
mdelay(5);
for (i = 0; i < 100; i++) {
- c = i2c_reg_read(0x38, ANX9804_LINK_TRAINING_CTRL_REG);
+ c = dm_i2c_reg_read(chip0, ANX9804_LINK_TRAINING_CTRL_REG);
if ((c & 0x01) == 0)
break;
@@ -118,17 +122,14 @@
}
if(i == 100) {
printf("Error anx9804 link training timeout\n");
- i2c_set_bus_num(orig_i2c_bus);
return;
}
/* Enable */
- i2c_reg_write(0x39, ANX9804_VID_CTRL1_REG,
- ANX9804_VID_CTRL1_VID_EN | ANX9804_VID_CTRL1_EDGE);
+ dm_i2c_reg_write(chip1, ANX9804_VID_CTRL1_REG,
+ ANX9804_VID_CTRL1_VID_EN | ANX9804_VID_CTRL1_EDGE);
/* Force stream valid */
- i2c_reg_write(0x38, ANX9804_SYS_CTRL3_REG,
- ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL |
- ANX9804_SYS_CTRL3_F_VALID | ANX9804_SYS_CTRL3_VALID_CTRL);
-
- i2c_set_bus_num(orig_i2c_bus);
+ dm_i2c_reg_write(chip0, ANX9804_SYS_CTRL3_REG,
+ ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL |
+ ANX9804_SYS_CTRL3_F_VALID | ANX9804_SYS_CTRL3_VALID_CTRL);
}
diff --git a/drivers/video/anx9804.h b/drivers/video/anx9804.h
index c0fe3b3..ea6c9f2 100644
--- a/drivers/video/anx9804.h
+++ b/drivers/video/anx9804.h
@@ -16,9 +16,10 @@
#define ANX9804_DATA_RATE_2700M 0x0a
#ifdef CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
-void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp);
+void anx9804_init(struct udevice *i2c_bus, u8 lanes, u8 data_rate, int bpp);
#else
-static inline void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate,
+static inline void anx9804_init(struct udevice *i2c_bus, u8 lanes, u8 data_rate,
int bpp) {}
#endif
+
#endif
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index 566fc1e..7df7d57 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -78,17 +78,6 @@
#include <dm/ofnode.h>
#include <linux/compiler.h>
-#if defined(CONFIG_VIDEO_MXS)
-#define VIDEO_FB_16BPP_WORD_SWAP
-#endif
-
-/*
- * Defines for the i.MX31 driver (mx3fb.c)
- */
-#if defined(CONFIG_VIDEO_MX3) || defined(CONFIG_VIDEO_IPUV3)
-#define VIDEO_FB_16BPP_WORD_SWAP
-#endif
-
/*
* Include video_fb.h after definitions of VIDEO_HW_RECTFILL etc.
*/
diff --git a/drivers/video/hitachi_tx18d42vm_lcd.c b/drivers/video/hitachi_tx18d42vm_lcd.c
index c6c8df6..87c4d27 100644
--- a/drivers/video/hitachi_tx18d42vm_lcd.c
+++ b/drivers/video/hitachi_tx18d42vm_lcd.c
@@ -49,9 +49,9 @@
};
int i, cs, clk, mosi, ret = 0;
- cs = name_to_gpio(CONFIG_VIDEO_LCD_SPI_CS);
- clk = name_to_gpio(CONFIG_VIDEO_LCD_SPI_SCLK);
- mosi = name_to_gpio(CONFIG_VIDEO_LCD_SPI_MOSI);
+ cs = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_CS);
+ clk = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_SCLK);
+ mosi = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_MOSI);
if (cs == -1 || clk == -1 || mosi == 1) {
printf("Error tx18d42vm spi gpio config is invalid\n");
diff --git a/drivers/video/mx3fb.c b/drivers/video/mx3fb.c
deleted file mode 100644
index e6dd2b8..0000000
--- a/drivers/video/mx3fb.c
+++ /dev/null
@@ -1,906 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2009
- * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
- * Copyright (C) 2011
- * HALE electronic GmbH, <helmut.raiger@hale.at>
- */
-#include <common.h>
-#include <env.h>
-#include <log.h>
-#include <malloc.h>
-#include <video_fb.h>
-#include <linux/delay.h>
-
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/clock.h>
-#include <linux/errno.h>
-#include <asm/io.h>
-
-#include "videomodes.h"
-
-/* this might need panel specific set-up as-well */
-#define IF_CONF 0
-
-/* -------------- controller specific stuff -------------- */
-
-/* IPU DMA Controller channel definitions. */
-enum ipu_channel {
- IDMAC_IC_0 = 0, /* IC (encoding task) to memory */
- IDMAC_IC_1 = 1, /* IC (viewfinder task) to memory */
- IDMAC_ADC_0 = 1,
- IDMAC_IC_2 = 2,
- IDMAC_ADC_1 = 2,
- IDMAC_IC_3 = 3,
- IDMAC_IC_4 = 4,
- IDMAC_IC_5 = 5,
- IDMAC_IC_6 = 6,
- IDMAC_IC_7 = 7, /* IC (sensor data) to memory */
- IDMAC_IC_8 = 8,
- IDMAC_IC_9 = 9,
- IDMAC_IC_10 = 10,
- IDMAC_IC_11 = 11,
- IDMAC_IC_12 = 12,
- IDMAC_IC_13 = 13,
- IDMAC_SDC_0 = 14, /* Background synchronous display data */
- IDMAC_SDC_1 = 15, /* Foreground data (overlay) */
- IDMAC_SDC_2 = 16,
- IDMAC_SDC_3 = 17,
- IDMAC_ADC_2 = 18,
- IDMAC_ADC_3 = 19,
- IDMAC_ADC_4 = 20,
- IDMAC_ADC_5 = 21,
- IDMAC_ADC_6 = 22,
- IDMAC_ADC_7 = 23,
- IDMAC_PF_0 = 24,
- IDMAC_PF_1 = 25,
- IDMAC_PF_2 = 26,
- IDMAC_PF_3 = 27,
- IDMAC_PF_4 = 28,
- IDMAC_PF_5 = 29,
- IDMAC_PF_6 = 30,
- IDMAC_PF_7 = 31,
-};
-
-/* More formats can be copied from the Linux driver if needed */
-enum pixel_fmt {
- /* 2 bytes */
- IPU_PIX_FMT_RGB565,
- IPU_PIX_FMT_RGB666,
- IPU_PIX_FMT_BGR666,
- /* 3 bytes */
- IPU_PIX_FMT_RGB24,
-};
-
-struct pixel_fmt_cfg {
- u32 b0;
- u32 b1;
- u32 b2;
- u32 acc;
-};
-
-static struct pixel_fmt_cfg fmt_cfg[] = {
- [IPU_PIX_FMT_RGB24] = {
- 0x1600AAAA, 0x00E05555, 0x00070000, 3,
- },
- [IPU_PIX_FMT_RGB666] = {
- 0x0005000F, 0x000B000F, 0x0011000F, 1,
- },
- [IPU_PIX_FMT_BGR666] = {
- 0x0011000F, 0x000B000F, 0x0005000F, 1,
- },
- [IPU_PIX_FMT_RGB565] = {
- 0x0004003F, 0x000A000F, 0x000F003F, 1,
- }
-};
-
-enum ipu_panel {
- IPU_PANEL_SHARP_TFT,
- IPU_PANEL_TFT,
-};
-
-/* IPU Common registers */
-/* IPU_CONF and its bits already defined in imx-regs.h */
-#define IPU_CHA_BUF0_RDY (0x04 + IPU_BASE)
-#define IPU_CHA_BUF1_RDY (0x08 + IPU_BASE)
-#define IPU_CHA_DB_MODE_SEL (0x0C + IPU_BASE)
-#define IPU_CHA_CUR_BUF (0x10 + IPU_BASE)
-#define IPU_FS_PROC_FLOW (0x14 + IPU_BASE)
-#define IPU_FS_DISP_FLOW (0x18 + IPU_BASE)
-#define IPU_TASKS_STAT (0x1C + IPU_BASE)
-#define IPU_IMA_ADDR (0x20 + IPU_BASE)
-#define IPU_IMA_DATA (0x24 + IPU_BASE)
-#define IPU_INT_CTRL_1 (0x28 + IPU_BASE)
-#define IPU_INT_CTRL_2 (0x2C + IPU_BASE)
-#define IPU_INT_CTRL_3 (0x30 + IPU_BASE)
-#define IPU_INT_CTRL_4 (0x34 + IPU_BASE)
-#define IPU_INT_CTRL_5 (0x38 + IPU_BASE)
-#define IPU_INT_STAT_1 (0x3C + IPU_BASE)
-#define IPU_INT_STAT_2 (0x40 + IPU_BASE)
-#define IPU_INT_STAT_3 (0x44 + IPU_BASE)
-#define IPU_INT_STAT_4 (0x48 + IPU_BASE)
-#define IPU_INT_STAT_5 (0x4C + IPU_BASE)
-#define IPU_BRK_CTRL_1 (0x50 + IPU_BASE)
-#define IPU_BRK_CTRL_2 (0x54 + IPU_BASE)
-#define IPU_BRK_STAT (0x58 + IPU_BASE)
-#define IPU_DIAGB_CTRL (0x5C + IPU_BASE)
-
-/* Image Converter Registers */
-#define IC_CONF (0x88 + IPU_BASE)
-#define IC_PRP_ENC_RSC (0x8C + IPU_BASE)
-#define IC_PRP_VF_RSC (0x90 + IPU_BASE)
-#define IC_PP_RSC (0x94 + IPU_BASE)
-#define IC_CMBP_1 (0x98 + IPU_BASE)
-#define IC_CMBP_2 (0x9C + IPU_BASE)
-#define PF_CONF (0xA0 + IPU_BASE)
-#define IDMAC_CONF (0xA4 + IPU_BASE)
-#define IDMAC_CHA_EN (0xA8 + IPU_BASE)
-#define IDMAC_CHA_PRI (0xAC + IPU_BASE)
-#define IDMAC_CHA_BUSY (0xB0 + IPU_BASE)
-
-/* Image Converter Register bits */
-#define IC_CONF_PRPENC_EN 0x00000001
-#define IC_CONF_PRPENC_CSC1 0x00000002
-#define IC_CONF_PRPENC_ROT_EN 0x00000004
-#define IC_CONF_PRPVF_EN 0x00000100
-#define IC_CONF_PRPVF_CSC1 0x00000200
-#define IC_CONF_PRPVF_CSC2 0x00000400
-#define IC_CONF_PRPVF_CMB 0x00000800
-#define IC_CONF_PRPVF_ROT_EN 0x00001000
-#define IC_CONF_PP_EN 0x00010000
-#define IC_CONF_PP_CSC1 0x00020000
-#define IC_CONF_PP_CSC2 0x00040000
-#define IC_CONF_PP_CMB 0x00080000
-#define IC_CONF_PP_ROT_EN 0x00100000
-#define IC_CONF_IC_GLB_LOC_A 0x10000000
-#define IC_CONF_KEY_COLOR_EN 0x20000000
-#define IC_CONF_RWS_EN 0x40000000
-#define IC_CONF_CSI_MEM_WR_EN 0x80000000
-
-/* SDC Registers */
-#define SDC_COM_CONF (0xB4 + IPU_BASE)
-#define SDC_GW_CTRL (0xB8 + IPU_BASE)
-#define SDC_FG_POS (0xBC + IPU_BASE)
-#define SDC_BG_POS (0xC0 + IPU_BASE)
-#define SDC_CUR_POS (0xC4 + IPU_BASE)
-#define SDC_PWM_CTRL (0xC8 + IPU_BASE)
-#define SDC_CUR_MAP (0xCC + IPU_BASE)
-#define SDC_HOR_CONF (0xD0 + IPU_BASE)
-#define SDC_VER_CONF (0xD4 + IPU_BASE)
-#define SDC_SHARP_CONF_1 (0xD8 + IPU_BASE)
-#define SDC_SHARP_CONF_2 (0xDC + IPU_BASE)
-
-/* Register bits */
-#define SDC_COM_TFT_COLOR 0x00000001UL
-#define SDC_COM_FG_EN 0x00000010UL
-#define SDC_COM_GWSEL 0x00000020UL
-#define SDC_COM_GLB_A 0x00000040UL
-#define SDC_COM_KEY_COLOR_G 0x00000080UL
-#define SDC_COM_BG_EN 0x00000200UL
-#define SDC_COM_SHARP 0x00001000UL
-
-#define SDC_V_SYNC_WIDTH_L 0x00000001UL
-
-/* Display Interface registers */
-#define DI_DISP_IF_CONF (0x0124 + IPU_BASE)
-#define DI_DISP_SIG_POL (0x0128 + IPU_BASE)
-#define DI_SER_DISP1_CONF (0x012C + IPU_BASE)
-#define DI_SER_DISP2_CONF (0x0130 + IPU_BASE)
-#define DI_HSP_CLK_PER (0x0134 + IPU_BASE)
-#define DI_DISP0_TIME_CONF_1 (0x0138 + IPU_BASE)
-#define DI_DISP0_TIME_CONF_2 (0x013C + IPU_BASE)
-#define DI_DISP0_TIME_CONF_3 (0x0140 + IPU_BASE)
-#define DI_DISP1_TIME_CONF_1 (0x0144 + IPU_BASE)
-#define DI_DISP1_TIME_CONF_2 (0x0148 + IPU_BASE)
-#define DI_DISP1_TIME_CONF_3 (0x014C + IPU_BASE)
-#define DI_DISP2_TIME_CONF_1 (0x0150 + IPU_BASE)
-#define DI_DISP2_TIME_CONF_2 (0x0154 + IPU_BASE)
-#define DI_DISP2_TIME_CONF_3 (0x0158 + IPU_BASE)
-#define DI_DISP3_TIME_CONF (0x015C + IPU_BASE)
-#define DI_DISP0_DB0_MAP (0x0160 + IPU_BASE)
-#define DI_DISP0_DB1_MAP (0x0164 + IPU_BASE)
-#define DI_DISP0_DB2_MAP (0x0168 + IPU_BASE)
-#define DI_DISP0_CB0_MAP (0x016C + IPU_BASE)
-#define DI_DISP0_CB1_MAP (0x0170 + IPU_BASE)
-#define DI_DISP0_CB2_MAP (0x0174 + IPU_BASE)
-#define DI_DISP1_DB0_MAP (0x0178 + IPU_BASE)
-#define DI_DISP1_DB1_MAP (0x017C + IPU_BASE)
-#define DI_DISP1_DB2_MAP (0x0180 + IPU_BASE)
-#define DI_DISP1_CB0_MAP (0x0184 + IPU_BASE)
-#define DI_DISP1_CB1_MAP (0x0188 + IPU_BASE)
-#define DI_DISP1_CB2_MAP (0x018C + IPU_BASE)
-#define DI_DISP2_DB0_MAP (0x0190 + IPU_BASE)
-#define DI_DISP2_DB1_MAP (0x0194 + IPU_BASE)
-#define DI_DISP2_DB2_MAP (0x0198 + IPU_BASE)
-#define DI_DISP2_CB0_MAP (0x019C + IPU_BASE)
-#define DI_DISP2_CB1_MAP (0x01A0 + IPU_BASE)
-#define DI_DISP2_CB2_MAP (0x01A4 + IPU_BASE)
-#define DI_DISP3_B0_MAP (0x01A8 + IPU_BASE)
-#define DI_DISP3_B1_MAP (0x01AC + IPU_BASE)
-#define DI_DISP3_B2_MAP (0x01B0 + IPU_BASE)
-#define DI_DISP_ACC_CC (0x01B4 + IPU_BASE)
-#define DI_DISP_LLA_CONF (0x01B8 + IPU_BASE)
-#define DI_DISP_LLA_DATA (0x01BC + IPU_BASE)
-
-/* DI_DISP_SIG_POL bits */
-#define DI_D3_VSYNC_POL (1 << 28)
-#define DI_D3_HSYNC_POL (1 << 27)
-#define DI_D3_DRDY_SHARP_POL (1 << 26)
-#define DI_D3_CLK_POL (1 << 25)
-#define DI_D3_DATA_POL (1 << 24)
-
-/* DI_DISP_IF_CONF bits */
-#define DI_D3_CLK_IDLE (1 << 26)
-#define DI_D3_CLK_SEL (1 << 25)
-#define DI_D3_DATAMSK (1 << 24)
-
-#define IOMUX_PADNUM_MASK 0x1ff
-#define IOMUX_GPIONUM_SHIFT 9
-#define IOMUX_GPIONUM_MASK (0xff << IOMUX_GPIONUM_SHIFT)
-
-#define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK)
-
-#define IOMUX_MODE_L(pin, mode) IOMUX_MODE(((pin) + 0xc) ^ 3, mode)
-
-struct chan_param_mem_planar {
- /* Word 0 */
- u32 xv:10;
- u32 yv:10;
- u32 xb:12;
-
- u32 yb:12;
- u32 res1:2;
- u32 nsb:1;
- u32 lnpb:6;
- u32 ubo_l:11;
-
- u32 ubo_h:15;
- u32 vbo_l:17;
-
- u32 vbo_h:9;
- u32 res2:3;
- u32 fw:12;
- u32 fh_l:8;
-
- u32 fh_h:4;
- u32 res3:28;
-
- /* Word 1 */
- u32 eba0;
-
- u32 eba1;
-
- u32 bpp:3;
- u32 sl:14;
- u32 pfs:3;
- u32 bam:3;
- u32 res4:2;
- u32 npb:6;
- u32 res5:1;
-
- u32 sat:2;
- u32 res6:30;
-} __attribute__ ((packed));
-
-struct chan_param_mem_interleaved {
- /* Word 0 */
- u32 xv:10;
- u32 yv:10;
- u32 xb:12;
-
- u32 yb:12;
- u32 sce:1;
- u32 res1:1;
- u32 nsb:1;
- u32 lnpb:6;
- u32 sx:10;
- u32 sy_l:1;
-
- u32 sy_h:9;
- u32 ns:10;
- u32 sm:10;
- u32 sdx_l:3;
-
- u32 sdx_h:2;
- u32 sdy:5;
- u32 sdrx:1;
- u32 sdry:1;
- u32 sdr1:1;
- u32 res2:2;
- u32 fw:12;
- u32 fh_l:8;
-
- u32 fh_h:4;
- u32 res3:28;
-
- /* Word 1 */
- u32 eba0;
-
- u32 eba1;
-
- u32 bpp:3;
- u32 sl:14;
- u32 pfs:3;
- u32 bam:3;
- u32 res4:2;
- u32 npb:6;
- u32 res5:1;
-
- u32 sat:2;
- u32 scc:1;
- u32 ofs0:5;
- u32 ofs1:5;
- u32 ofs2:5;
- u32 ofs3:5;
- u32 wid0:3;
- u32 wid1:3;
- u32 wid2:3;
-
- u32 wid3:3;
- u32 dec_sel:1;
- u32 res6:28;
-} __attribute__ ((packed));
-
-union chan_param_mem {
- struct chan_param_mem_planar pp;
- struct chan_param_mem_interleaved ip;
-};
-
-/* graphics setup */
-static GraphicDevice panel;
-static struct ctfb_res_modes *mode;
-static struct ctfb_res_modes var_mode;
-
-/*
- * sdc_init_panel() - initialize a synchronous LCD panel.
- * @width: width of panel in pixels.
- * @height: height of panel in pixels.
- * @di_setup: pixel format of the frame buffer
- * @di_panel: either SHARP or normal TFT
- * @return: 0 on success or negative error code on failure.
- */
-static int sdc_init_panel(u16 width, u16 height,
- enum pixel_fmt di_setup, enum ipu_panel di_panel)
-{
- u32 reg, div;
- uint32_t old_conf;
- int clock;
-
- debug("%s(width=%d, height=%d)\n", __func__, width, height);
-
- /* Init clocking, the IPU receives its clock from the hsp divder */
- clock = mxc_get_clock(MXC_IPU_CLK);
- if (clock < 0)
- return -EACCES;
-
- /* Init panel size and blanking periods */
- reg = width + mode->left_margin + mode->right_margin - 1;
- if (reg > 1023) {
- printf("mx3fb: Display width too large, coerced to 1023!");
- reg = 1023;
- }
- reg = ((mode->hsync_len - 1) << 26) | (reg << 16);
- writel(reg, SDC_HOR_CONF);
-
- reg = height + mode->upper_margin + mode->lower_margin - 1;
- if (reg > 1023) {
- printf("mx3fb: Display height too large, coerced to 1023!");
- reg = 1023;
- }
- reg = ((mode->vsync_len - 1) << 26) | SDC_V_SYNC_WIDTH_L | (reg << 16);
- writel(reg, SDC_VER_CONF);
-
- switch (di_panel) {
- case IPU_PANEL_SHARP_TFT:
- writel(0x00FD0102L, SDC_SHARP_CONF_1);
- writel(0x00F500F4L, SDC_SHARP_CONF_2);
- writel(SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF);
- /* TODO: probably IF_CONF must be adapted (see below)! */
- break;
- case IPU_PANEL_TFT:
- writel(SDC_COM_TFT_COLOR, SDC_COM_CONF);
- break;
- default:
- return -EINVAL;
- }
-
- /*
- * Calculate divider: The fractional part is 4 bits so simply
- * multiple by 2^4 to get it.
- *
- * Opposed to the kernel driver mode->pixclock is the time of one
- * pixel in pico seconds, so:
- * pixel_clk = 1e12 / mode->pixclock
- * div = ipu_clk * 16 / pixel_clk
- * leads to:
- * div = ipu_clk * 16 / (1e12 / mode->pixclock)
- * or:
- * div = ipu_clk * 16 * mode->pixclock / 1e12
- *
- * To avoid integer overflows this is split into 2 shifts and
- * one divide with sufficient accuracy:
- * 16*1024*128*476837 = 0.9999996682e12
- */
- div = ((clock/1024) * (mode->pixclock/128)) / 476837;
- debug("hsp_clk is %d, div=%d\n", clock, div);
- /* coerce to not less than 4.0, not more than 255.9375 */
- if (div < 0x40)
- div = 0x40;
- else if (div > 0xFFF)
- div = 0xFFF;
- /* DISP3_IF_CLK_DOWN_WR is half the divider value and 2 less
- * fraction bits. Subtract 1 extra from DISP3_IF_CLK_DOWN_WR
- * based on timing debug DISP3_IF_CLK_UP_WR is 0
- */
- writel((((div / 8) - 1) << 22) | div, DI_DISP3_TIME_CONF);
-
- /* DI settings for display 3: clock idle (bit 26) during vsync */
- old_conf = readl(DI_DISP_IF_CONF) & 0x78FFFFFF;
- writel(old_conf | IF_CONF, DI_DISP_IF_CONF);
-
- /* only set display 3 polarity bits */
- old_conf = readl(DI_DISP_SIG_POL) & 0xE0FFFFFF;
- writel(old_conf | mode->sync, DI_DISP_SIG_POL);
-
- writel(fmt_cfg[di_setup].b0, DI_DISP3_B0_MAP);
- writel(fmt_cfg[di_setup].b1, DI_DISP3_B1_MAP);
- writel(fmt_cfg[di_setup].b2, DI_DISP3_B2_MAP);
- writel(readl(DI_DISP_ACC_CC) |
- ((fmt_cfg[di_setup].acc - 1) << 12), DI_DISP_ACC_CC);
-
- debug("DI_DISP_IF_CONF = 0x%08X\n", readl(DI_DISP_IF_CONF));
- debug("DI_DISP_SIG_POL = 0x%08X\n", readl(DI_DISP_SIG_POL));
- debug("DI_DISP3_TIME_CONF = 0x%08X\n", readl(DI_DISP3_TIME_CONF));
- debug("SDC_HOR_CONF = 0x%08X\n", readl(SDC_HOR_CONF));
- debug("SDC_VER_CONF = 0x%08X\n", readl(SDC_VER_CONF));
-
- return 0;
-}
-
-static void ipu_ch_param_set_size(union chan_param_mem *params,
- uint pixelfmt, uint16_t width,
- uint16_t height, uint16_t stride)
-{
- debug("%s(pixelfmt=%d, width=%d, height=%d, stride=%d)\n",
- __func__, pixelfmt, width, height, stride);
-
- params->pp.fw = width - 1;
- params->pp.fh_l = height - 1;
- params->pp.fh_h = (height - 1) >> 8;
- params->pp.sl = stride - 1;
-
- /* See above, for further formats see the Linux driver */
- switch (pixelfmt) {
- case GDF_16BIT_565RGB:
- params->ip.bpp = 2;
- params->ip.pfs = 4;
- params->ip.npb = 7;
- params->ip.sat = 2; /* SAT = 32-bit access */
- params->ip.ofs0 = 0; /* Red bit offset */
- params->ip.ofs1 = 5; /* Green bit offset */
- params->ip.ofs2 = 11; /* Blue bit offset */
- params->ip.ofs3 = 16; /* Alpha bit offset */
- params->ip.wid0 = 4; /* Red bit width - 1 */
- params->ip.wid1 = 5; /* Green bit width - 1 */
- params->ip.wid2 = 4; /* Blue bit width - 1 */
- break;
- case GDF_32BIT_X888RGB:
- params->ip.bpp = 1; /* 24 BPP & RGB PFS */
- params->ip.pfs = 4;
- params->ip.npb = 7;
- params->ip.sat = 2; /* SAT = 32-bit access */
- params->ip.ofs0 = 16; /* Red bit offset */
- params->ip.ofs1 = 8; /* Green bit offset */
- params->ip.ofs2 = 0; /* Blue bit offset */
- params->ip.ofs3 = 24; /* Alpha bit offset */
- params->ip.wid0 = 7; /* Red bit width - 1 */
- params->ip.wid1 = 7; /* Green bit width - 1 */
- params->ip.wid2 = 7; /* Blue bit width - 1 */
- break;
- default:
- printf("mx3fb: Pixel format not supported!\n");
- break;
- }
-
- params->pp.nsb = 1;
-}
-
-static void ipu_ch_param_set_buffer(union chan_param_mem *params,
- void *buf0, void *buf1)
-{
- params->pp.eba0 = (u32)buf0;
- params->pp.eba1 = (u32)buf1;
-}
-
-static void ipu_write_param_mem(uint32_t addr, uint32_t *data,
- uint32_t num_words)
-{
- for (; num_words > 0; num_words--) {
- writel(addr, IPU_IMA_ADDR);
- writel(*data++, IPU_IMA_DATA);
- addr++;
- if ((addr & 0x7) == 5) {
- addr &= ~0x7; /* set to word 0 */
- addr += 8; /* increment to next row */
- }
- }
-}
-
-static uint32_t dma_param_addr(enum ipu_channel channel)
-{
- /* Channel Parameter Memory */
- return 0x10000 | (channel << 4);
-}
-
-static void ipu_init_channel_buffer(enum ipu_channel channel, void *fbmem)
-{
- union chan_param_mem params = {};
- uint32_t reg;
- uint32_t stride_bytes;
-
- stride_bytes = (panel.plnSizeX * panel.gdfBytesPP + 3) & ~3;
-
- debug("%s(channel=%d, fbmem=%p)\n", __func__, channel, fbmem);
-
- /* Build parameter memory data for DMA channel */
- ipu_ch_param_set_size(¶ms, panel.gdfIndex,
- panel.plnSizeX, panel.plnSizeY, stride_bytes);
- ipu_ch_param_set_buffer(¶ms, fbmem, NULL);
- params.pp.bam = 0;
- /* Some channels (rotation) have restriction on burst length */
-
- switch (channel) {
- case IDMAC_SDC_0:
- /* In original code only IPU_PIX_FMT_RGB565 was setting burst */
- params.pp.npb = 16 - 1;
- break;
- default:
- break;
- }
-
- ipu_write_param_mem(dma_param_addr(channel), (uint32_t *)¶ms, 10);
-
- /* Disable double-buffering */
- reg = readl(IPU_CHA_DB_MODE_SEL);
- reg &= ~(1UL << channel);
- writel(reg, IPU_CHA_DB_MODE_SEL);
-}
-
-static void ipu_channel_set_priority(enum ipu_channel channel,
- int prio)
-{
- u32 reg = readl(IDMAC_CHA_PRI);
-
- if (prio)
- reg |= 1UL << channel;
- else
- reg &= ~(1UL << channel);
-
- writel(reg, IDMAC_CHA_PRI);
-}
-
-/*
- * ipu_enable_channel() - enable an IPU channel.
- * @channel: channel ID.
- * @return: 0 on success or negative error code on failure.
- */
-static int ipu_enable_channel(enum ipu_channel channel)
-{
- uint32_t reg;
-
- /* Reset to buffer 0 */
- writel(1UL << channel, IPU_CHA_CUR_BUF);
-
- switch (channel) {
- case IDMAC_SDC_0:
- ipu_channel_set_priority(channel, 1);
- break;
- default:
- break;
- }
-
- reg = readl(IDMAC_CHA_EN);
- writel(reg | (1UL << channel), IDMAC_CHA_EN);
-
- return 0;
-}
-
-static int ipu_update_channel_buffer(enum ipu_channel channel, void *buf)
-{
- uint32_t reg;
-
- reg = readl(IPU_CHA_BUF0_RDY);
- if (reg & (1UL << channel))
- return -EACCES;
-
- /* 44.3.3.1.9 - Row Number 1 (WORD1, offset 0) */
- writel(dma_param_addr(channel) + 0x0008UL, IPU_IMA_ADDR);
- writel((u32)buf, IPU_IMA_DATA);
-
- return 0;
-}
-
-static int idmac_tx_submit(enum ipu_channel channel, void *buf)
-{
- int ret;
-
- ipu_init_channel_buffer(channel, buf);
-
-
- /* ipu_idmac.c::ipu_submit_channel_buffers() */
- ret = ipu_update_channel_buffer(channel, buf);
- if (ret < 0)
- return ret;
-
- /* ipu_idmac.c::ipu_select_buffer() */
- /* Mark buffer 0 as ready. */
- writel(1UL << channel, IPU_CHA_BUF0_RDY);
-
-
- ret = ipu_enable_channel(channel);
- return ret;
-}
-
-static void sdc_enable_channel(void *fbmem)
-{
- int ret;
- u32 reg;
-
- ret = idmac_tx_submit(IDMAC_SDC_0, fbmem);
-
- /* mx3fb.c::sdc_fb_init() */
- if (ret >= 0) {
- reg = readl(SDC_COM_CONF);
- writel(reg | SDC_COM_BG_EN, SDC_COM_CONF);
- }
-
- /*
- * Attention! Without this msleep the channel keeps generating
- * interrupts. Next sdc_set_brightness() is going to be called
- * from mx3fb_blank().
- */
- udelay(2000);
-}
-
-/*
- * mx3fb_set_par() - set framebuffer parameters and change the operating mode.
- * @return: 0 on success or negative error code on failure.
- * TODO: currently only 666 and TFT as DI setup supported
- */
-static int mx3fb_set_par(void)
-{
- int ret;
-
- ret = sdc_init_panel(panel.plnSizeX, panel.plnSizeY,
- IPU_PIX_FMT_RGB666, IPU_PANEL_TFT);
- if (ret < 0)
- return ret;
-
- writel((mode->left_margin << 16) | mode->upper_margin, SDC_BG_POS);
-
- return 0;
-}
-
-static void ll_disp3_enable(void *base)
-{
- u32 reg;
-
- debug("%s(base=0x%x)\n", __func__, (u32) base);
- /* pcm037.c::mxc_board_init() */
-
- /* Display Interface #3 */
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD0, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD1, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD2, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD3, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD4, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD5, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD6, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD7, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD8, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD9, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD10, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD11, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD12, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD13, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD14, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD15, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD16, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD17, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_VSYNC3, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_HSYNC, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_FPSHIFT, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_DRDY0, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_REV, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_CONTRAST, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_SPL, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_CLS, MUX_CTL_FUNC));
-
-
- /* ipu_idmac.c::ipu_probe() */
-
- /* Start the clock */
- __REG(CCM_CGR1) = __REG(CCM_CGR1) | (3 << 22);
-
-
- /* ipu_idmac.c::ipu_idmac_init() */
-
- /* Service request counter to maximum - shouldn't be needed */
- writel(0x00000070, IDMAC_CONF);
-
-
- /* ipu_idmac.c::ipu_init_channel() */
-
- /* Enable IPU sub modules */
- reg = readl(IPU_CONF) | IPU_CONF_SDC_EN | IPU_CONF_DI_EN;
- writel(reg, IPU_CONF);
-
-
- /* mx3fb.c::init_fb_chan() */
-
- /* set Display Interface clock period */
- writel(0x00100010L, DI_HSP_CLK_PER);
- /* Might need to trigger HSP clock change - see 44.3.3.8.5 */
-
-
- /* mx3fb.c::sdc_set_brightness() */
-
- /* This might be board-specific */
- writel(0x03000000UL | 255 << 16, SDC_PWM_CTRL);
-
-
- /* mx3fb.c::sdc_set_global_alpha() */
-
- /* Use global - not per-pixel - Alpha-blending */
- reg = readl(SDC_GW_CTRL) & 0x00FFFFFFL;
- writel(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL);
-
- reg = readl(SDC_COM_CONF);
- writel(reg | SDC_COM_GLB_A, SDC_COM_CONF);
-
-
- /* mx3fb.c::sdc_set_color_key() */
-
- /* Disable colour-keying for background */
- reg = readl(SDC_COM_CONF) &
- ~(SDC_COM_GWSEL | SDC_COM_KEY_COLOR_G);
- writel(reg, SDC_COM_CONF);
-
-
- mx3fb_set_par();
-
- sdc_enable_channel(base);
-
- /*
- * Linux driver calls sdc_set_brightness() here again,
- * once is enough for us
- */
- debug("%s() done\n", __func__);
-}
-
-/* ------------------------ public part ------------------- */
-ulong calc_fbsize(void)
-{
- return panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP;
-}
-
-/*
- * The current implementation is only tested for GDF_16BIT_565RGB!
- * It was switched from the original CONFIG_LCD setup to CONFIG_VIDEO,
- * because the lcd code seemed loaded with color table stuff, that
- * does not relate to most modern TFTs. cfb_console.c looks more
- * straight forward.
- * This is the environment setting for the original setup
- * "unknown=video=ctfb:x:240,y:320,depth:16,mode:0,pclk:185925,le:9,ri:17,
- * up:7,lo:10,hs:1,vs:1,sync:100663296,vmode:0"
- * "videomode=unknown"
- *
- * Settings for VBEST VGG322403 display:
- * "videomode=video=ctfb:x:320,y:240,depth:16,mode:0,pclk:156000,
- * "le:20,ri:68,up:7,lo:29,hs:30,vs:3,sync:100663296,vmode:0"
- *
- * Settings for COM57H5M10XRC display:
- * "videomode=video=ctfb:x:640,y:480,depth:16,mode:0,pclk:40000,
- * "le:120,ri:40,up:35,lo:10,hs:30,vs:3,sync:100663296,vmode:0"
- */
-void *video_hw_init(void)
-{
- char *penv;
- u32 memsize;
- unsigned long t1, hsynch, vsynch;
- int bits_per_pixel, i, tmp, videomode;
-
- tmp = 0;
-
- puts("Video: ");
-
- videomode = CONFIG_SYS_DEFAULT_VIDEO_MODE;
- /* get video mode via environment */
- penv = env_get("videomode");
- if (penv) {
- /* decide if it is a string */
- if (penv[0] <= '9') {
- videomode = (int)hextoul(penv, NULL);
- tmp = 1;
- }
- } else {
- tmp = 1;
- }
- if (tmp) {
- /* parameter are vesa modes */
- /* search params */
- for (i = 0; i < VESA_MODES_COUNT; i++) {
- if (vesa_modes[i].vesanr == videomode)
- break;
- }
- if (i == VESA_MODES_COUNT) {
- printf("No VESA Mode found, switching to mode 0x%x ",
- CONFIG_SYS_DEFAULT_VIDEO_MODE);
- i = 0;
- }
- mode = (struct ctfb_res_modes *)
- &res_mode_init[vesa_modes[i].resindex];
- bits_per_pixel = vesa_modes[i].bits_per_pixel;
- } else {
- mode = (struct ctfb_res_modes *) &var_mode;
- bits_per_pixel = video_get_params(mode, penv);
- }
-
- /* calculate hsynch and vsynch freq (info only) */
- t1 = (mode->left_margin + mode->xres +
- mode->right_margin + mode->hsync_len) / 8;
- t1 *= 8;
- t1 *= mode->pixclock;
- t1 /= 1000;
- hsynch = 1000000000L / t1;
- t1 *= (mode->upper_margin + mode->yres +
- mode->lower_margin + mode->vsync_len);
- t1 /= 1000;
- vsynch = 1000000000L / t1;
-
- /* fill in Graphic device struct */
- sprintf(panel.modeIdent, "%dx%dx%d %ldkHz %ldHz",
- mode->xres, mode->yres,
- bits_per_pixel, (hsynch / 1000), (vsynch / 1000));
- printf("%s\n", panel.modeIdent);
- panel.winSizeX = mode->xres;
- panel.winSizeY = mode->yres;
- panel.plnSizeX = mode->xres;
- panel.plnSizeY = mode->yres;
-
- switch (bits_per_pixel) {
- case 24:
- panel.gdfBytesPP = 4;
- panel.gdfIndex = GDF_32BIT_X888RGB;
- break;
- case 16:
- panel.gdfBytesPP = 2;
- panel.gdfIndex = GDF_16BIT_565RGB;
- break;
- default:
- panel.gdfBytesPP = 1;
- panel.gdfIndex = GDF__8BIT_INDEX;
- break;
- }
-
- /* set up Hardware */
- memsize = calc_fbsize();
-
- debug("%s() allocating %d bytes\n", __func__, memsize);
-
- /* fill in missing Graphic device struct */
- panel.frameAdrs = (u32) malloc(memsize);
- if (panel.frameAdrs == 0) {
- printf("%s() malloc(%d) failed\n", __func__, memsize);
- return 0;
- }
- panel.memSize = memsize;
-
- ll_disp3_enable((void *) panel.frameAdrs);
- memset((void *) panel.frameAdrs, 0, memsize);
-
- debug("%s() done, framebuffer at 0x%x, size=%d cleared\n",
- __func__, panel.frameAdrs, memsize);
-
- return (void *) &panel;
-}
diff --git a/drivers/video/simplefb.c b/drivers/video/simplefb.c
index fd58426..2b0d883 100644
--- a/drivers/video/simplefb.c
+++ b/drivers/video/simplefb.c
@@ -50,8 +50,18 @@
if (strcmp(format, "r5g6b5") == 0) {
uc_priv->bpix = VIDEO_BPP16;
- } else if (strcmp(format, "a8b8g8r8") == 0) {
+ } else if (strcmp(format, "a8b8g8r8") == 0 ||
+ strcmp(format, "x8b8g8r8") == 0) {
+ uc_priv->bpix = VIDEO_BPP32;
+ uc_priv->format = VIDEO_X8B8G8R8;
+ } else if (strcmp(format, "a8r8g8b8") == 0 ||
+ strcmp(format, "x8r8g8b8") == 0) {
+ uc_priv->bpix = VIDEO_BPP32;
+ uc_priv->format = VIDEO_X8R8G8B8;
+ } else if (strcmp(format, "a2r10g10b10") == 0 ||
+ strcmp(format, "x2r10g10b10") == 0) {
uc_priv->bpix = VIDEO_BPP32;
+ uc_priv->format = VIDEO_X2R10G10B10;
} else {
printf("%s: invalid format: %s\n", __func__, format);
return -EINVAL;
diff --git a/drivers/video/sunxi/sunxi_display.c b/drivers/video/sunxi/sunxi_display.c
index 4361a58..5a21f7a 100644
--- a/drivers/video/sunxi/sunxi_display.c
+++ b/drivers/video/sunxi/sunxi_display.c
@@ -17,7 +17,6 @@
#include <asm/arch/clock.h>
#include <asm/arch/display.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/lcdc.h>
#include <asm/arch/pwm.h>
#include <asm/arch/tve.h>
@@ -872,11 +871,11 @@
static int sunxi_ssd2828_init(const struct ctfb_res_modes *mode)
{
struct ssd2828_config cfg = {
- .csx_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_CS),
- .sck_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_SCLK),
- .sdi_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_MOSI),
- .sdo_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_MISO),
- .reset_pin = name_to_gpio(CONFIG_VIDEO_LCD_SSD2828_RESET),
+ .csx_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_CS),
+ .sck_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_SCLK),
+ .sdi_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_MOSI),
+ .sdo_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_MISO),
+ .reset_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SSD2828_RESET),
.ssd2828_tx_clk_khz = CONFIG_VIDEO_LCD_SSD2828_TX_CLK * 1000,
.ssd2828_color_depth = 24,
#ifdef CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
@@ -902,6 +901,42 @@
}
#endif /* CONFIG_VIDEO_LCD_SSD2828 */
+#ifdef CONFIG_VIDEO_LCD_PANEL_I2C
+static void sunxi_panel_i2c_init(struct sunxi_display_priv *sunxi_display)
+{
+ const char *name = CONFIG_VIDEO_LCD_PANEL_I2C_NAME;
+ struct udevice *i2c_bus;
+ int ret;
+
+ ret = uclass_get_device_by_name(UCLASS_I2C, name, &i2c_bus);
+ if (ret)
+ return;
+
+ if (IS_ENABLED(CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804)) {
+ /*
+ * The anx9804 needs 1.8V from eldo3, we do this here
+ * and not via CONFIG_AXP_ELDO3_VOLT from board_init()
+ * to avoid turning this on when using hdmi output.
+ */
+ axp_set_eldo(3, 1800);
+ anx9804_init(i2c_bus, 4,
+ ANX9804_DATA_RATE_1620M,
+ sunxi_display->depth);
+ }
+ if (IS_ENABLED(CONFIG_VIDEO_LCD_TL059WV5C0)) {
+ struct udevice *chip;
+
+ ret = i2c_get_chip(i2c_bus, 0x5c, 1, &chip);
+ if (ret)
+ return;
+
+ dm_i2c_reg_write(chip, 0x04, 0x42); /* Turn on the LCD */
+ }
+}
+#else
+static void sunxi_panel_i2c_init(struct sunxi_display_priv *sunxi_display) {}
+#endif
+
static void sunxi_engines_init(void)
{
sunxi_composer_init();
@@ -936,27 +971,12 @@
break;
case sunxi_monitor_lcd:
sunxi_lcdc_panel_enable();
- if (IS_ENABLED(CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804)) {
- /*
- * The anx9804 needs 1.8V from eldo3, we do this here
- * and not via CONFIG_AXP_ELDO3_VOLT from board_init()
- * to avoid turning this on when using hdmi output.
- */
- axp_set_eldo(3, 1800);
- anx9804_init(CONFIG_VIDEO_LCD_I2C_BUS, 4,
- ANX9804_DATA_RATE_1620M,
- sunxi_display->depth);
- }
if (IS_ENABLED(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM)) {
mdelay(50); /* Wait for lcd controller power on */
hitachi_tx18d42vm_init();
}
- if (IS_ENABLED(CONFIG_VIDEO_LCD_TL059WV5C0)) {
- unsigned int orig_i2c_bus = i2c_get_bus_num();
- i2c_set_bus_num(CONFIG_VIDEO_LCD_I2C_BUS);
- i2c_reg_write(0x5c, 0x04, 0x42); /* Turn on the LCD */
- i2c_set_bus_num(orig_i2c_bus);
- }
+ if (IS_ENABLED(CONFIG_VIDEO_LCD_PANEL_I2C))
+ sunxi_panel_i2c_init(sunxi_display);
sunxi_composer_mode_set(mode, address, monitor);
sunxi_lcdc_tcon0_mode_set(sunxi_display, mode, false);
sunxi_composer_enable();
diff --git a/drivers/video/sunxi/sunxi_lcd.c b/drivers/video/sunxi/sunxi_lcd.c
index 7a9eba1..8b9c3b2 100644
--- a/drivers/video/sunxi/sunxi_lcd.c
+++ b/drivers/video/sunxi/sunxi_lcd.c
@@ -15,7 +15,6 @@
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/lcdc.h>
-#include <asm/arch/gpio.h>
#include <asm/global_data.h>
#include <asm/gpio.h>
diff --git a/drivers/video/vidconsole-uclass.c b/drivers/video/vidconsole-uclass.c
index 8132efa..f42db40 100644
--- a/drivers/video/vidconsole-uclass.c
+++ b/drivers/video/vidconsole-uclass.c
@@ -155,9 +155,14 @@
break;
case VIDEO_BPP32:
if (CONFIG_IS_ENABLED(VIDEO_BPP32)) {
- return (colors[idx].r << 16) |
- (colors[idx].g << 8) |
- (colors[idx].b << 0);
+ if (priv->format == VIDEO_X2R10G10B10)
+ return (colors[idx].r << 22) |
+ (colors[idx].g << 12) |
+ (colors[idx].b << 2);
+ else
+ return (colors[idx].r << 16) |
+ (colors[idx].g << 8) |
+ (colors[idx].b << 0);
}
break;
default:
diff --git a/dts/Kconfig b/dts/Kconfig
index 0cc562c..90c7a1c 100644
--- a/dts/Kconfig
+++ b/dts/Kconfig
@@ -5,9 +5,6 @@
config SUPPORT_OF_CONTROL
bool
-config DTC
- bool
-
config PYLIBFDT
bool
@@ -22,7 +19,7 @@
config BINMAN_STANDALONE_FDT
bool
depends on BINMAN
- default y if OF_BOARD || OF_PRIOR_STAGE
+ default y if OF_BOARD
help
This option tells U-Boot build system that a standalone device tree
source is explicitly required when using binman to package U-Boot.
@@ -32,7 +29,7 @@
directory for a specific board. Such device tree sources are built for
OF_SEPARATE or OF_EMBED. However for a scenario like the board device
tree blob is not provided in the U-Boot build tree, but fed to U-Boot
- in the runtime, e.g.: in the OF_PRIOR_STAGE case that it is passed by
+ in the runtime, e.g.: in the OF_BOARD case that it is passed by
a prior stage bootloader. For such scenario, a standalone device tree
blob containing binman node to describe how to package U-Boot should
be provided explicitly.
@@ -42,7 +39,6 @@
config OF_CONTROL
bool "Run-time configuration via Device Tree"
- select DTC
select OF_LIBFDT if !OF_PLATDATA
select OF_REAL if !OF_PLATDATA
help
@@ -118,7 +114,7 @@
Boards in the mainline U-Boot tree should not use it.
config OF_BOARD
- bool "Provided by the board at runtime"
+ bool "Provided by the board (e.g a previous loader) at runtime"
depends on !SANDBOX
help
If this option is enabled, the device tree will be provided by
@@ -133,13 +129,6 @@
This is only useful for Sandbox. Use the -d flag to U-Boot to
specify the file to read.
-config OF_PRIOR_STAGE
- bool "Prior stage bootloader DTB for DT control"
- help
- If this option is enabled, the device tree used for DT
- control will be read from a device tree binary, at a memory
- location passed to U-Boot by the prior stage bootloader.
-
endchoice
config DEFAULT_DEVICE_TREE
diff --git a/env/common.c b/env/common.c
index 81e9e0b..db213b7 100644
--- a/env/common.c
+++ b/env/common.c
@@ -21,6 +21,8 @@
#include <malloc.h>
#include <u-boot/crc.h>
#include <dm/ofnode.h>
+#include <net.h>
+#include <watchdog.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -34,6 +36,184 @@
};
/*
+ * This env_set() function is defined in cmd/nvedit.c, since it calls
+ * _do_env_set(), whis is a static function in that file.
+ *
+ * int env_set(const char *varname, const char *varvalue);
+ */
+
+/**
+ * Set an environment variable to an integer value
+ *
+ * @param varname Environment variable to set
+ * @param value Value to set it to
+ * @return 0 if ok, 1 on error
+ */
+int env_set_ulong(const char *varname, ulong value)
+{
+ /* TODO: this should be unsigned */
+ char *str = simple_itoa(value);
+
+ return env_set(varname, str);
+}
+
+/**
+ * Set an environment variable to an value in hex
+ *
+ * @param varname Environment variable to set
+ * @param value Value to set it to
+ * @return 0 if ok, 1 on error
+ */
+int env_set_hex(const char *varname, ulong value)
+{
+ char str[17];
+
+ sprintf(str, "%lx", value);
+ return env_set(varname, str);
+}
+
+ulong env_get_hex(const char *varname, ulong default_val)
+{
+ const char *s;
+ ulong value;
+ char *endp;
+
+ s = env_get(varname);
+ if (s)
+ value = hextoul(s, &endp);
+ if (!s || endp == s)
+ return default_val;
+
+ return value;
+}
+
+int eth_env_get_enetaddr(const char *name, uint8_t *enetaddr)
+{
+ string_to_enetaddr(env_get(name), enetaddr);
+ return is_valid_ethaddr(enetaddr);
+}
+
+int eth_env_set_enetaddr(const char *name, const uint8_t *enetaddr)
+{
+ char buf[ARP_HLEN_ASCII + 1];
+
+ if (eth_env_get_enetaddr(name, (uint8_t *)buf))
+ return -EEXIST;
+
+ sprintf(buf, "%pM", enetaddr);
+
+ return env_set(name, buf);
+}
+
+/*
+ * Look up variable from environment,
+ * return address of storage for that variable,
+ * or NULL if not found
+ */
+char *env_get(const char *name)
+{
+ if (gd->flags & GD_FLG_ENV_READY) { /* after import into hashtable */
+ struct env_entry e, *ep;
+
+ WATCHDOG_RESET();
+
+ e.key = name;
+ e.data = NULL;
+ hsearch_r(e, ENV_FIND, &ep, &env_htab, 0);
+
+ return ep ? ep->data : NULL;
+ }
+
+ /* restricted capabilities before import */
+ if (env_get_f(name, (char *)(gd->env_buf), sizeof(gd->env_buf)) > 0)
+ return (char *)(gd->env_buf);
+
+ return NULL;
+}
+
+/*
+ * Like env_get, but prints an error if envvar isn't defined in the
+ * environment. It always returns what env_get does, so it can be used in
+ * place of env_get without changing error handling otherwise.
+ */
+char *from_env(const char *envvar)
+{
+ char *ret;
+
+ ret = env_get(envvar);
+
+ if (!ret)
+ printf("missing environment variable: %s\n", envvar);
+
+ return ret;
+}
+
+/*
+ * Look up variable from environment for restricted C runtime env.
+ */
+int env_get_f(const char *name, char *buf, unsigned len)
+{
+ const char *env, *p, *end;
+ size_t name_len;
+
+ if (name == NULL || *name == '\0')
+ return -1;
+
+ name_len = strlen(name);
+
+ if (gd->env_valid == ENV_INVALID)
+ env = (const char *)default_environment;
+ else
+ env = (const char *)gd->env_addr;
+
+ for (p = env; *p != '\0'; p = end + 1) {
+ const char *value;
+ unsigned res;
+
+ for (end = p; *end != '\0'; ++end)
+ if (end - env >= CONFIG_ENV_SIZE)
+ return -1;
+
+ if (strncmp(name, p, name_len) || p[name_len] != '=')
+ continue;
+ value = &p[name_len + 1];
+
+ res = end - value;
+ memcpy(buf, value, min(len, res + 1));
+
+ if (len <= res) {
+ buf[len - 1] = '\0';
+ printf("env_buf [%u bytes] too small for value of \"%s\"\n",
+ len, name);
+ }
+
+ return res;
+ }
+
+ return -1;
+}
+
+/**
+ * Decode the integer value of an environment variable and return it.
+ *
+ * @param name Name of environment variable
+ * @param base Number base to use (normally 10, or 16 for hex)
+ * @param default_val Default value to return if the variable is not
+ * found
+ * @return the decoded value, or default_val if not found
+ */
+ulong env_get_ulong(const char *name, int base, ulong default_val)
+{
+ /*
+ * We can use env_get() here, even before relocation, since the
+ * environment variable value is an integer and thus short.
+ */
+ const char *str = env_get(name);
+
+ return str ? simple_strtoul(str, NULL, base) : default_val;
+}
+
+/*
* Read an environment variable as a boolean
* Return -1 if variable does not exist (default to true)
*/
diff --git a/env/eeprom.c b/env/eeprom.c
index 253bdf1..f8556a4 100644
--- a/env/eeprom.c
+++ b/env/eeprom.c
@@ -64,24 +64,6 @@
return rcode;
}
-/** Call this function from overridden env_get_char_spec() if you need
- * this functionality.
- */
-int env_eeprom_get_char(int index)
-{
- uchar c;
- unsigned int off = CONFIG_ENV_OFFSET;
-
-#ifdef CONFIG_ENV_OFFSET_REDUND
- if (gd->env_valid == ENV_REDUND)
- off = CONFIG_ENV_OFFSET_REDUND;
-#endif
- eeprom_bus_read(CONFIG_SYS_I2C_EEPROM_ADDR,
- off + index + offsetof(env_t, data), &c, 1);
-
- return c;
-}
-
static int env_eeprom_load(void)
{
char buf_env[CONFIG_ENV_SIZE];
diff --git a/env/env.c b/env/env.c
index e534008..e4dfb92 100644
--- a/env/env.c
+++ b/env/env.c
@@ -166,19 +166,6 @@
return drv;
}
-__weak int env_get_char_spec(int index)
-{
- return *(uchar *)(gd->env_addr + index);
-}
-
-int env_get_char(int index)
-{
- if (gd->env_valid == ENV_INVALID)
- return default_environment[index];
- else
- return env_get_char_spec(index);
-}
-
int env_load(void)
{
struct env_driver *drv;
diff --git a/env/nowhere.c b/env/nowhere.c
index 41557f5..1fcf503 100644
--- a/env/nowhere.c
+++ b/env/nowhere.c
@@ -31,9 +31,8 @@
static int env_nowhere_load(void)
{
/*
- * for SPL, set env_valid = ENV_INVALID is enough as env_get_char()
- * return the default env if env_get is used
- * and SPL don't used env_import to reduce its size
+ * For SPL, setting env_valid = ENV_INVALID is enough, as env_get()
+ * searches default_environment array in that case.
* For U-Boot proper, import the default environment to allow reload.
*/
if (!IS_ENABLED(CONFIG_SPL_BUILD))
diff --git a/env/nvram.c b/env/nvram.c
index f412685..261b31e 100644
--- a/env/nvram.c
+++ b/env/nvram.c
@@ -42,20 +42,6 @@
static env_t *env_ptr = (env_t *)CONFIG_ENV_ADDR;
#endif
-#ifdef CONFIG_SYS_NVRAM_ACCESS_ROUTINE
-/** Call this function from overridden env_get_char_spec() if you need
- * this functionality.
- */
-int env_nvram_get_char(int index)
-{
- uchar c;
-
- nvram_read(&c, CONFIG_ENV_ADDR + index, 1);
-
- return c;
-}
-#endif
-
static int env_nvram_load(void)
{
char buf[CONFIG_ENV_SIZE];
diff --git a/examples/api/glue.c b/examples/api/glue.c
index 91d1315..075d307 100644
--- a/examples/api/glue.c
+++ b/examples/api/glue.c
@@ -365,11 +365,6 @@
env = NULL;
- /*
- * It's OK to pass only the name piece as last (and not the whole
- * 'name=val' string), since the API_ENUM_ENV call uses env_match()
- * internally, which handles such case
- */
if (!syscall(API_ENV_ENUM, NULL, last, &env))
return NULL;
diff --git a/fs/btrfs/compression.c b/fs/btrfs/compression.c
index 23efefa..7adfbb0 100644
--- a/fs/btrfs/compression.c
+++ b/fs/btrfs/compression.c
@@ -6,6 +6,7 @@
*/
#include "btrfs.h"
+#include <abuf.h>
#include <log.h>
#include <malloc.h>
#include <linux/lzo.h>
@@ -136,54 +137,12 @@
static u32 decompress_zstd(const u8 *cbuf, u32 clen, u8 *dbuf, u32 dlen)
{
- ZSTD_DStream *dstream;
- ZSTD_inBuffer in_buf;
- ZSTD_outBuffer out_buf;
- void *workspace;
- size_t wsize;
- u32 res = -1;
+ struct abuf in, out;
- wsize = ZSTD_DStreamWorkspaceBound(ZSTD_BTRFS_MAX_INPUT);
- workspace = malloc(wsize);
- if (!workspace) {
- debug("%s: cannot allocate workspace of size %zu\n", __func__,
- wsize);
- return -1;
- }
-
- dstream = ZSTD_initDStream(ZSTD_BTRFS_MAX_INPUT, workspace, wsize);
- if (!dstream) {
- printf("%s: ZSTD_initDStream failed\n", __func__);
- goto err_free;
- }
-
- in_buf.src = cbuf;
- in_buf.pos = 0;
- in_buf.size = clen;
-
- out_buf.dst = dbuf;
- out_buf.pos = 0;
- out_buf.size = dlen;
-
- while (1) {
- size_t ret;
+ abuf_init_set(&in, (u8 *)cbuf, clen);
+ abuf_init_set(&out, dbuf, dlen);
- ret = ZSTD_decompressStream(dstream, &out_buf, &in_buf);
- if (ZSTD_isError(ret)) {
- printf("%s: ZSTD_decompressStream error %d\n", __func__,
- ZSTD_getErrorCode(ret));
- goto err_free;
- }
-
- if (in_buf.pos >= clen || !ret)
- break;
- }
-
- res = out_buf.pos;
-
-err_free:
- free(workspace);
- return res;
+ return zstd_decompress(&in, &out);
}
u32 btrfs_decompress(u8 type, const char *c, u32 clen, char *d, u32 dlen)
diff --git a/fs/fat/fat.c b/fs/fat/fat.c
index 7021138..65f77c4 100644
--- a/fs/fat/fat.c
+++ b/fs/fat/fat.c
@@ -275,22 +275,19 @@
buffer += mydata->sect_size;
size -= mydata->sect_size;
}
- } else {
- __u32 idx;
+ } else if (size >= mydata->sect_size) {
+ __u32 bytes_read;
+ __u32 sect_count = size / mydata->sect_size;
- idx = size / mydata->sect_size;
- if (idx == 0)
- ret = 0;
- else
- ret = disk_read(startsect, idx, buffer);
- if (ret != idx) {
+ ret = disk_read(startsect, sect_count, buffer);
+ if (ret != sect_count) {
debug("Error reading data (got %d)\n", ret);
return -1;
}
- startsect += idx;
- idx *= mydata->sect_size;
- buffer += idx;
- size -= idx;
+ bytes_read = sect_count * mydata->sect_size;
+ startsect += sect_count;
+ buffer += bytes_read;
+ size -= bytes_read;
}
if (size) {
ALLOC_CACHE_ALIGN_BUFFER(__u8, tmpbuf, mydata->sect_size);
diff --git a/include/abuf.h b/include/abuf.h
new file mode 100644
index 0000000..d230f72
--- /dev/null
+++ b/include/abuf.h
@@ -0,0 +1,159 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Handles a buffer that can be allocated and freed
+ *
+ * Copyright 2021 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __ABUF_H
+#define __ABUF_H
+
+#include <linux/types.h>
+
+/**
+ * struct abuf - buffer that can be allocated and freed
+ *
+ * This is useful for a block of data which may be allocated with malloc(), or
+ * not, so that it needs to be freed correctly when finished with.
+ *
+ * For now it has a very simple purpose.
+ *
+ * Using memset() to zero all fields is guaranteed to be equivalent to
+ * abuf_init().
+ *
+ * @data: Pointer to data
+ * @size: Size of data in bytes
+ * @alloced: true if allocated with malloc(), so must be freed after use
+ */
+struct abuf {
+ void *data;
+ size_t size;
+ bool alloced;
+};
+
+static inline void *abuf_data(const struct abuf *abuf)
+{
+ return abuf->data;
+}
+
+static inline size_t abuf_size(const struct abuf *abuf)
+{
+ return abuf->size;
+}
+
+/**
+ * abuf_set() - set the (unallocated) data in a buffer
+ *
+ * This simply makes the abuf point to the supplied data, which must be live
+ * for the lifetime of the abuf. It is not alloced.
+ *
+ * Any existing data in the abuf is freed and the alloced member is set to
+ * false.
+ *
+ * @abuf: abuf to adjust
+ * @data: New contents of abuf
+ * @size: New size of abuf
+ */
+void abuf_set(struct abuf *abuf, void *data, size_t size);
+
+/**
+ * abuf_map_sysmem() - calls map_sysmem() to set up an abuf
+ *
+ * This is equivalent to abuf_set(abuf, map_sysmem(addr, size), size)
+ *
+ * Any existing data in the abuf is freed and the alloced member is set to
+ * false.
+ *
+ * @abuf: abuf to adjust
+ * @addr: Address to set the abuf to
+ * @size: New size of abuf
+ */
+void abuf_map_sysmem(struct abuf *abuf, ulong addr, size_t size);
+
+/**
+ * abuf_realloc() - Change the size of a buffer
+ *
+ * This uses realloc() to change the size of the buffer, with the same semantics
+ * as that function. If the abuf is not currently alloced, then it will alloc
+ * it if the size needs to increase (i.e. set the alloced member to true)
+ *
+ * @abuf: abuf to adjust
+ * @new_size: new size in bytes.
+ * if 0, the abuf is freed
+ * if greater than the current size, the abuf is extended and the new
+ * space is not inited. The alloced member is set to true
+ * if less than the current size, the abuf is contracted and the data at
+ * the end is lost. If @new_size is 0, this sets the alloced member to
+ * false
+ * @return true if OK, false if out of memory
+ */
+bool abuf_realloc(struct abuf *abuf, size_t new_size);
+
+/**
+ * abuf_uninit_move() - Return the allocated contents and uninit the abuf
+ *
+ * This returns the abuf data to the caller, allocating it if necessary, so that
+ * the caller receives data that it can be sure will hang around. The caller is
+ * responsible for freeing the data.
+ *
+ * If the abuf has allocated data, it is returned. If the abuf has data but it
+ * is not allocated, then it is first allocated, then returned.
+ *
+ * If the abuf size is 0, this returns NULL
+ *
+ * The abuf is uninited as part of this, except if the allocation fails, in
+ * which NULL is returned and the abuf remains untouched.
+ *
+ * The abuf must be inited before this can be called.
+ *
+ * @abuf: abuf to uninit
+ * @sizep: if non-NULL, returns the size of the returned data
+ * @return data contents, allocated with malloc(), or NULL if the data could not
+ * be allocated, or the data size is 0
+ */
+void *abuf_uninit_move(struct abuf *abuf, size_t *sizep);
+
+/**
+ * abuf_init_move() - Make abuf take over the management of an allocated region
+ *
+ * After this, @data must not be used. All access must be via the abuf.
+ *
+ * @abuf: abuf to init
+ * @data: Existing allocated buffer to place in the abuf
+ * @size: Size of allocated buffer
+ */
+void abuf_init_move(struct abuf *abuf, void *data, size_t size);
+
+/**
+ * abuf_init_set() - Set up a new abuf
+ *
+ * Inits a new abuf and sets up its (unallocated) data
+ *
+ * @abuf: abuf to set up
+ * @data: New contents of abuf
+ * @size: New size of abuf
+ */
+void abuf_init_set(struct abuf *abuf, void *data, size_t size);
+
+/**
+ * abuf_uninit() - Free any memory used by an abuf
+ *
+ * The buffer must be inited before this can be called.
+ *
+ * @abuf: abuf to uninit
+ */
+void abuf_uninit(struct abuf *abuf);
+
+/**
+ * abuf_init() - Set up a new abuf
+ *
+ * This initially has no data and alloced is set to false. This is equivalent to
+ * setting all fields to 0, e.g. with memset(), so callers can do that instead
+ * if desired.
+ *
+ * @abuf: abuf to set up
+ */
+void abuf_init(struct abuf *abuf);
+
+#endif
diff --git a/include/axp_pmic.h b/include/axp_pmic.h
index 405044c..46a017d 100644
--- a/include/axp_pmic.h
+++ b/include/axp_pmic.h
@@ -6,6 +6,8 @@
*/
#ifndef _AXP_PMIC_H_
+#include <stdbool.h>
+
#ifdef CONFIG_AXP152_POWER
#include <axp152.h>
#endif
@@ -25,6 +27,16 @@
#include <axp818.h>
#endif
+#define AXP_PMIC_MODE_REG 0x3e
+#define AXP_PMIC_MODE_I2C 0x00
+#define AXP_PMIC_MODE_P2WI 0x3e
+#define AXP_PMIC_MODE_RSB 0x7c
+
+#define AXP_PMIC_PRI_DEVICE_ADDR 0x3a3
+#define AXP_PMIC_PRI_RUNTIME_ADDR 0x2d
+#define AXP_PMIC_SEC_DEVICE_ADDR 0x745
+#define AXP_PMIC_SEC_RUNTIME_ADDR 0x3a
+
int axp_set_dcdc1(unsigned int mvolt);
int axp_set_dcdc2(unsigned int mvolt);
int axp_set_dcdc3(unsigned int mvolt);
diff --git a/arch/arm/include/asm/arch-sunxi/ccu.h b/include/clk/sunxi.h
similarity index 93%
rename from arch/arm/include/asm/arch-sunxi/ccu.h
rename to include/clk/sunxi.h
index cac5c5f..d4ad5fd 100644
--- a/arch/arm/include/asm/arch-sunxi/ccu.h
+++ b/include/clk/sunxi.h
@@ -4,12 +4,10 @@
* Author: Jagan Teki <jagan@amarulasolutions.com>
*/
-#ifndef _ASM_ARCH_CCU_H
-#define _ASM_ARCH_CCU_H
+#ifndef _CLK_SUNXI_H
+#define _CLK_SUNXI_H
-#ifndef __ASSEMBLY__
#include <linux/bitops.h>
-#endif
/**
* enum ccu_flags - ccu clock/reset flags
@@ -97,4 +95,4 @@
*/
int sunxi_reset_bind(struct udevice *dev, ulong count);
-#endif /* _ASM_ARCH_CCU_H */
+#endif /* _CLK_SUNXI_H */
diff --git a/include/compiler.h b/include/compiler.h
index 27b9843..8cf1179 100644
--- a/include/compiler.h
+++ b/include/compiler.h
@@ -68,6 +68,9 @@
typedef unsigned int uint;
typedef unsigned long ulong;
+/* Define these on the host so we can build some target code */
+typedef __u32 u32;
+
#define uswap_16(x) \
((((x) & 0xff00) >> 8) | \
(((x) & 0x00ff) << 8))
@@ -151,7 +154,13 @@
#define MEM_SUPPORT_64BIT_DATA 0
#endif
-static inline bool host_build(void) {
+/**
+ * tools_build() - check if we are building host tools
+ *
+ * @return true if building for the host, false if for a target
+ */
+static inline bool tools_build(void)
+{
#ifdef USE_HOSTCC
return true;
#else
diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h
index f983281..b37c915 100644
--- a/include/configs/M5235EVB.h
+++ b/include/configs/M5235EVB.h
@@ -54,7 +54,7 @@
#define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
#define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+/* this must be included AFTER the definition of CONFIG COMMANDS (if any) */
#define CONFIG_BOOTFILE "u-boot.bin"
#ifdef CONFIG_MCFFEC
# define CONFIG_IPADDR 192.162.1.2
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 3a9ea03..dcd538f 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -191,7 +191,6 @@
/* Serial Port */
#define CONFIG_CONS_ON_SCC /* define if console on SCC */
-#undef CONFIG_CONS_NONE /* define if console on something else */
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 21e56d6..198b698 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -203,7 +203,6 @@
#endif /* CONFIG_NAND_FSL_ELBC */
#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
#define CONFIG_HWCONFIG
diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h
index fc6167c..462619f 100644
--- a/include/configs/SBx81LIFKW.h
+++ b/include/configs/SBx81LIFKW.h
@@ -60,11 +60,6 @@
#undef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
/*
- * Other required minimal configurations
- */
-#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
-
-/*
* Ethernet Driver configuration
*/
#ifdef CONFIG_CMD_NET
diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h
index 06be63e..a271567 100644
--- a/include/configs/SBx81LIFXCAT.h
+++ b/include/configs/SBx81LIFXCAT.h
@@ -65,11 +65,6 @@
#undef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
/*
- * Other required minimal configurations
- */
-#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
-
-/*
* Ethernet Driver configuration
*/
#ifdef CONFIG_CMD_NET
diff --git a/include/configs/am335x_sl50.h b/include/configs/am335x_sl50.h
index dff9468..7fbf421 100644
--- a/include/configs/am335x_sl50.h
+++ b/include/configs/am335x_sl50.h
@@ -62,13 +62,6 @@
/* Bootcount using the RTC block */
#define CONFIG_SYS_BOOTCOUNT_BE
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USB_ETHER)
-/* Remove other SPL modes. */
-/* disable host part of MUSB in SPL */
-#undef CONFIG_MUSB_HOST
-/* disable EFI partitions and partition UUID support */
-#endif
-
/* Network. */
#endif /* ! __CONFIG_AM335X_SL50_H */
diff --git a/include/configs/clearfog.h b/include/configs/clearfog.h
index 7052170..a30bca5 100644
--- a/include/configs/clearfog.h
+++ b/include/configs/clearfog.h
@@ -18,9 +18,6 @@
* U-Boot into it.
*/
-/* USB/EHCI configuration */
-#define CONFIG_EHCI_IS_TDI
-
#define CONFIG_ENV_MIN_ENTRIES 128
/* Environment in MMC */
diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h
index a2f2de7..741c3fe 100644
--- a/include/configs/colibri-imx6ull.h
+++ b/include/configs/colibri-imx6ull.h
@@ -134,8 +134,7 @@
/* USB Device Firmware Update support */
#define DFU_DEFAULT_POLL_TIMEOUT 300
-#if defined(CONFIG_VIDEO) || defined(CONFIG_DM_VIDEO)
-#define CONFIG_VIDEO_MXS
+#if defined(CONFIG_DM_VIDEO)
#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h
index 07c26e3..344b266 100644
--- a/include/configs/colibri_imx7.h
+++ b/include/configs/colibri_imx7.h
@@ -200,8 +200,7 @@
#define CONFIG_USBD_HS
-#if defined(CONFIG_VIDEO) || defined(CONFIG_DM_VIDEO)
-#define CONFIG_VIDEO_MXS
+#if defined(CONFIG_DM_VIDEO)
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#endif
diff --git a/include/configs/controlcenterdc.h b/include/configs/controlcenterdc.h
index efd04c6..21e61e5 100644
--- a/include/configs/controlcenterdc.h
+++ b/include/configs/controlcenterdc.h
@@ -27,9 +27,6 @@
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
-/* USB/EHCI configuration */
-#define CONFIG_EHCI_IS_TDI
-
/* Environment in SPI NOR flash */
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 7fd1ad1..8819935 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -205,7 +205,6 @@
#endif /* CONFIG_NAND_FSL_ELBC */
#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
#define CONFIG_HWCONFIG
diff --git a/include/configs/crs3xx-98dx3236.h b/include/configs/crs3xx-98dx3236.h
index 3feaa60..27b45a7 100644
--- a/include/configs/crs3xx-98dx3236.h
+++ b/include/configs/crs3xx-98dx3236.h
@@ -13,9 +13,6 @@
#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024) /* 64 MB */
#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
-/* USB/EHCI configuration */
-#define CONFIG_EHCI_IS_TDI
-
/* Environment in SPI NOR flash */
/* Keep device tree and initrd in lower memory so the kernel can access them */
diff --git a/include/configs/db-88f6720.h b/include/configs/db-88f6720.h
index 95f5cf0..19fc669 100644
--- a/include/configs/db-88f6720.h
+++ b/include/configs/db-88f6720.h
@@ -20,7 +20,6 @@
#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
/* USB/EHCI configuration */
-#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
/* Environment in SPI NOR flash */
diff --git a/include/configs/db-88f6820-amc.h b/include/configs/db-88f6820-amc.h
index 41216b8..1f70c60 100644
--- a/include/configs/db-88f6820-amc.h
+++ b/include/configs/db-88f6820-amc.h
@@ -10,9 +10,6 @@
* High Level Configuration Options (easy to change)
*/
-/* USB/EHCI configuration */
-#define CONFIG_EHCI_IS_TDI
-
/* Environment in SPI NOR flash */
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h
index 6bae063..41dadfe 100644
--- a/include/configs/db-88f6820-gp.h
+++ b/include/configs/db-88f6820-gp.h
@@ -22,9 +22,6 @@
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
-/* USB/EHCI configuration */
-#define CONFIG_EHCI_IS_TDI
-
/* Environment in SPI NOR flash */
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h
index 4847199..dbbc33e 100644
--- a/include/configs/db-mv784mp-gp.h
+++ b/include/configs/db-mv784mp-gp.h
@@ -21,7 +21,6 @@
#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
/* USB/EHCI configuration */
-#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
/* Environment in SPI NOR flash */
diff --git a/include/configs/db-xc3-24g4xg.h b/include/configs/db-xc3-24g4xg.h
index 2c543fe..6a4c5a7 100644
--- a/include/configs/db-xc3-24g4xg.h
+++ b/include/configs/db-xc3-24g4xg.h
@@ -12,9 +12,6 @@
#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
-/* USB/EHCI configuration */
-#define CONFIG_EHCI_IS_TDI
-
/* Environment in SPI NOR flash */
/* NAND */
diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h
index 7af8fce..ee56eb6 100644
--- a/include/configs/dh_imx6.h
+++ b/include/configs/dh_imx6.h
@@ -50,8 +50,6 @@
/* USB Configs */
#ifdef CONFIG_CMD_USB
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_ASIX
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index c54f375..900c5fd 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -103,7 +103,6 @@
#define CONFIG_SYS_MAX_FLASH_SECT 512
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_FLASH_SIZE (64 * 1024 * 1024) /* 64 MB */
-/* #define CONFIG_INIT_IGNORE_ERROR */
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_FLASH_BASE (0x08000000)
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
diff --git a/include/configs/ds414.h b/include/configs/ds414.h
index 58ecc5f..1f2d2c5 100644
--- a/include/configs/ds414.h
+++ b/include/configs/ds414.h
@@ -24,9 +24,6 @@
#define CONFIG_PCI_SCAN_SHOW
#endif
-/* USB/EHCI/XHCI configuration */
-#define CONFIG_EHCI_IS_TDI
-
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
index fbe4680..664d6d1 100644
--- a/include/configs/edminiv2.h
+++ b/include/configs/edminiv2.h
@@ -151,12 +151,6 @@
* Environment variables configurations
*/
-/*
- * Other required minimal configurations
- */
-
-#define CONFIG_SYS_RESET_ADDRESS 0xffff0000
-
/* Enable command line editing */
/* provide extensive help */
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index 3f6afc1..170d6a7 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -107,6 +107,7 @@
#define CONFIG_EXTRA_ENV_SETTINGS_COMMON \
"splashpos=m,m\0" \
+ "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \
"usb_pgood_delay=2000\0" \
"console=ttymxc1\0" \
"bootdevs=usb mmc sata flash\0" \
diff --git a/include/configs/helios4.h b/include/configs/helios4.h
index b5814ed..56d35d6 100644
--- a/include/configs/helios4.h
+++ b/include/configs/helios4.h
@@ -18,9 +18,6 @@
* U-Boot into it.
*/
-/* USB/EHCI configuration */
-#define CONFIG_EHCI_IS_TDI
-
#define CONFIG_ENV_MIN_ENTRIES 128
/* Environment in MMC */
diff --git a/include/configs/imx7_spl.h b/include/configs/imx7_spl.h
index 01d1cd8..128f612 100644
--- a/include/configs/imx7_spl.h
+++ b/include/configs/imx7_spl.h
@@ -18,15 +18,23 @@
* - Set the stack at the end of the free area section, at 0x00946BB8.
* - The BOOT ROM loads what they consider the firmware image
* which consists of a 4K header in front of us that contains the IVT, DCD
- * and some padding thus 'our' max size is really 0x00946BB8 - 0x00911000.
- * 64KB is more then enough for the SPL.
+ * and some padding. However, the manual also states that the ROM uses the
+ * OCRAM_EPCD and OCRAM_PXP areas for itself. While the SPL is free to use
+ * this range for stack and malloc, the SPL itself must fit below 0x920000,
+ * or the image will be truncated in at least some boot modes like USB SDP.
+ * Thus our max size is really 0x00920000 - 0x00912000. If necessary,
+ * CONFIG_SPL_TEXT_BASE could be moved to 0x00911000 to gain 4KB of space
+ * for the SPL, but 56KB should be more than enough for the SPL.
*/
-#define CONFIG_SPL_MAX_SIZE 0x10000
+#define CONFIG_SPL_MAX_SIZE 0xE000
#define CONFIG_SPL_STACK 0x00946BB8
/*
- * Pad SPL to 68KB (4KB header + 64KB max size). This allows to write the
- * SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a
- * boot media (given that boot media specific offset is configured properly).
+ * Pad SPL to 68KB (4KB header + 56KB max size + 8KB extra padding)
+ * The extra padding could be removed, but this value was used historically
+ * based on an incorrect CONFIG_SPL_MAX_SIZE definition.
+ * This allows to write the SPL/U-Boot combination generated with
+ * u-boot-with-spl.imx directly to a boot media (given that boot media specific
+ * offset is configured properly).
*/
#define CONFIG_SPL_PAD_TO 0x11000
diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h
index a03a7a7..4c8f562 100644
--- a/include/configs/imx8mm_evk.h
+++ b/include/configs/imx8mm_evk.h
@@ -10,7 +10,7 @@
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
+#define CONFIG_SYS_BOOTM_LEN (64 * SZ_1M)
#define CONFIG_SPL_MAX_SIZE (148 * 1024)
#define CONFIG_SYS_MONITOR_LEN SZ_512K
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h
index 9b9d6fd..f2eb777 100644
--- a/include/configs/imx8mq_evk.h
+++ b/include/configs/imx8mq_evk.h
@@ -10,7 +10,7 @@
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
+#define CONFIG_SYS_BOOTM_LEN (64 * SZ_1M)
#define CONFIG_SPL_MAX_SIZE (124 * 1024)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h
index 152fa6f..803daa4 100644
--- a/include/configs/imx8qm_mek.h
+++ b/include/configs/imx8qm_mek.h
@@ -10,6 +10,8 @@
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
+#define CONFIG_SYS_BOOTM_LEN (64 * SZ_1M)
+
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_MAX_SIZE (124 * 1024)
#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
diff --git a/include/configs/imxrt1050-evk.h b/include/configs/imxrt1050-evk.h
index 1b67542..99d25c1 100644
--- a/include/configs/imxrt1050-evk.h
+++ b/include/configs/imxrt1050-evk.h
@@ -22,7 +22,6 @@
DMAMEM_SZ_ALL)
#ifdef CONFIG_DM_VIDEO
-#define CONFIG_VIDEO_MXS
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
diff --git a/include/configs/iot2050.h b/include/configs/iot2050.h
index ddb4cfc..91ed76b 100644
--- a/include/configs/iot2050.h
+++ b/include/configs/iot2050.h
@@ -17,8 +17,6 @@
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \
CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE)
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
#define CONFIG_SYS_BOOTM_LEN SZ_64M
diff --git a/include/configs/kontron-sl-mx6ul.h b/include/configs/kontron-sl-mx6ul.h
new file mode 100644
index 0000000..65aa250
--- /dev/null
+++ b/include/configs/kontron-sl-mx6ul.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ *
+ * Configuration settings for the Kontron i.MX6UL boards/SoMs.
+ */
+#ifndef __KONTRON_MX6UL_CONFIG_H
+#define __KONTRON_MX6UL_CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+
+#include "mx6_common.h"
+#ifdef CONFIG_SPL_BUILD
+#include "imx6_spl.h"
+#endif
+
+/* RAM */
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
+
+/* Board and environment settings */
+#define CONFIG_MXC_UART_BASE UART4_BASE
+#define CONFIG_HOSTNAME "kontron-mx6ul"
+#define CONFIG_ETHPRIME "eth0"
+
+#ifdef CONFIG_USB_EHCI_HCD
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#endif
+
+/* Boot order for distro boot */
+#ifndef CONFIG_SPL_BUILD
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 0) \
+ func(UBIFS, ubifs, 0) \
+ func(USB, usb, 0) \
+ func(PXE, pxe, na) \
+ func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+#else
+#define BOOTENV
+#endif
+
+/* MMC Configs */
+#ifdef CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "kernel_addr_r=0x82000000\0" \
+ "ramdisk_addr_r=0x88080000\0" \
+ "pxefile_addr_r=0x80100000\0" \
+ "scriptaddr=0x80100000\0" \
+ "bootdelay=3\0" \
+ "ethact=" CONFIG_ETHPRIME "\0" \
+ "hostname=" CONFIG_HOSTNAME "\0" \
+ BOOTENV
+
+#endif /* __KONTRON_MX6UL_CONFIG_H */
diff --git a/include/configs/kontron-sl-mx8mm.h b/include/configs/kontron-sl-mx8mm.h
new file mode 100644
index 0000000..0d9ab3b
--- /dev/null
+++ b/include/configs/kontron-sl-mx8mm.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ *
+ * Configuration settings for the Kontron SL/BL i.MX8M-Mini boards and modules (N81xx).
+ */
+#ifndef __KONTRON_MX8MM_CONFIG_H
+#define __KONTRON_MX8MM_CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+
+#ifdef CONFIG_SPL_BUILD
+#include <config.h>
+#endif
+
+/* RAM */
+#define PHYS_SDRAM DDR_CSD1_BASE_ADDR
+#define PHYS_SDRAM_SIZE (SZ_4G)
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+
+#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Board and environment settings */
+#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
+#define CONFIG_HOSTNAME "kontron-mx8mm"
+
+#ifdef CONFIG_USB_EHCI_HCD
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 0) \
+ func(USB, usb, 0) \
+ func(PXE, pxe, na)
+#include <config_distro_bootcmd.h>
+/* Do not try to probe USB net adapters for net boot */
+#undef BOOTENV_RUN_NET_USB_START
+#define BOOTENV_RUN_NET_USB_START
+#else
+#define BOOTENV
+#endif
+
+#define CONFIG_SYS_BOOTM_LEN SZ_64M
+#define CONFIG_SPL_MAX_SIZE (148 * SZ_1K)
+#define CONFIG_FSL_USDHC
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_STACK 0x91fff0
+#define CONFIG_SPL_BSS_START_ADDR 0x910000
+#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K
+#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K
+/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
+#define CONFIG_MALLOC_F_ADDR 0x930000
+#endif
+
+#define FEC_QUIRK_ENET_MAC
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "kernel_addr_r=0x42000000\0" \
+ "fdt_addr_r=0x44000000\0" \
+ "ramdisk_addr_r=0x46400000\0" \
+ "pxefile_addr_r=0x46000000\0" \
+ "scriptaddr=0x46000000\0" \
+ "dfu_alt_info=sf 0:0=flash-bin raw 0x400 0x1f0000\0" \
+ "bootdelay=3\0" \
+ "hostname=" CONFIG_HOSTNAME "\0" \
+ BOOTENV
+
+#endif /* __KONTRON_MX8MM_CONFIG_H */
diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h
index 8471dff..3061c96 100644
--- a/include/configs/kp_imx6q_tpc.h
+++ b/include/configs/kp_imx6q_tpc.h
@@ -23,8 +23,6 @@
/* USB Configs */
#ifdef CONFIG_CMD_USB
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_ASIX
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */
diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h
index 5dd5dda..375a758 100644
--- a/include/configs/m53menlo.h
+++ b/include/configs/m53menlo.h
@@ -161,6 +161,13 @@
"splashfile=boot/usplash.bmp.gz\0" \
"splashimage=0x88000000\0" \
"splashpos=m,m\0" \
+ "altbootcmd=" \
+ "if test ${mmcpart} -eq 1 ; then " \
+ "setenv mmcpart 2 ; " \
+ "else " \
+ "setenv mmcpart 1 ; " \
+ "fi ; " \
+ "boot\0" \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0" \
"addcons=" \
@@ -175,14 +182,14 @@
"setenv bootargs ${bootargs} ${miscargs}\0" \
"addargs=run addcons addmisc addmtd\0" \
"mmcload=" \
- "mmc rescan ; load mmc ${mmcdev}:${mmcpart} " \
- "${kernel_addr_r} ${bootfile}\0" \
+ "mmc rescan || reset ; load mmc ${mmcdev}:${mmcpart} " \
+ "${kernel_addr_r} ${bootfile} || reset\0" \
"miscargs=nohlt panic=1\0" \
"mmcargs=setenv bootargs root=/dev/mmcblk0p${mmcpart} rw " \
"rootwait\0" \
"mmc_mmc=" \
- "run mmcload mmcargs addargs ; " \
- "bootm ${kernel_addr_r}\0" \
+ "run mmcload mmcargs addargs || reset ; " \
+ "bootm ${kernel_addr_r} ; reset\0" \
"netload=tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \
"net_nfs=" \
"run netload nfsargs addip addargs ; " \
diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h
index e460f69..cc3b597 100644
--- a/include/configs/mv-common.h
+++ b/include/configs/mv-common.h
@@ -55,7 +55,6 @@
/*
* Other required minimal configurations
*/
-#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
/* ====> Include platform Common Definitions */
diff --git a/include/configs/mvebu_armada-37xx.h b/include/configs/mvebu_armada-37xx.h
index 755f59e..e7f7e77 100644
--- a/include/configs/mvebu_armada-37xx.h
+++ b/include/configs/mvebu_armada-37xx.h
@@ -30,18 +30,12 @@
/*
* Other required minimal configurations
*/
-#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
/* End of 16M scrubbed by training in bootrom */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0xFF0000)
/*
- * I2C
- */
-#define CONFIG_I2C_MV
-
-/*
* Environment
*/
#define DEFAULT_ENV_IS_RW /* required for configuring default fdtfile= */
diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h
index 2f8be2e..886f44c 100644
--- a/include/configs/mvebu_armada-8k.h
+++ b/include/configs/mvebu_armada-8k.h
@@ -24,7 +24,6 @@
/*
* Other required minimal configurations
*/
-#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
/* End of 16M scrubbed by training in bootrom */
diff --git a/include/configs/mx23evk.h b/include/configs/mx23evk.h
index 1f40d98..bccba5c 100644
--- a/include/configs/mx23evk.h
+++ b/include/configs/mx23evk.h
@@ -26,7 +26,7 @@
#endif
/* Framebuffer support */
-#ifdef CONFIG_VIDEO
+#ifdef CONFIG_DM_VIDEO
#define CONFIG_VIDEO_LOGO
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10)
#endif
diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h
index 10292c8..fe4ea89 100644
--- a/include/configs/mx28evk.h
+++ b/include/configs/mx28evk.h
@@ -40,7 +40,7 @@
#endif
/* Framebuffer support */
-#ifdef CONFIG_VIDEO
+#ifdef CONFIG_DM_VIDEO
#define CONFIG_VIDEO_LOGO
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10)
#endif
diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h
index b623242..f811881 100644
--- a/include/configs/mx53ppd.h
+++ b/include/configs/mx53ppd.h
@@ -14,10 +14,6 @@
#define CONFIG_SYS_FSL_CLK
/* USB Configs */
-#define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_ASIX
-#define CONFIG_USB_ETHER_MCS7830
-#define CONFIG_USB_ETHER_SMSC95XX
#define CONFIG_MXC_USB_PORT 1
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index 1237dde..df2bd97 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -161,8 +161,7 @@
#endif
#ifndef CONFIG_SPL_BUILD
-#ifdef CONFIG_VIDEO
-#define CONFIG_VIDEO_MXS
+#ifdef CONFIG_DM_VIDEO
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define MXS_LCDIF_BASE MX6SX_LCDIF1_BASE_ADDR
diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h
index ff2ad09..9ddb479 100644
--- a/include/configs/mx6ul_14x14_evk.h
+++ b/include/configs/mx6ul_14x14_evk.h
@@ -167,7 +167,6 @@
#ifndef CONFIG_SPL_BUILD
#if defined(CONFIG_DM_VIDEO)
-#define CONFIG_VIDEO_MXS
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR
diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h
index 397af53..92ce741 100644
--- a/include/configs/mx7dsabresd.h
+++ b/include/configs/mx7dsabresd.h
@@ -126,8 +126,7 @@
#define CONFIG_USBD_HS
-#ifdef CONFIG_VIDEO
-#define CONFIG_VIDEO_MXS
+#ifdef CONFIG_DM_VIDEO
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#endif
diff --git a/include/configs/mx7ulp_com.h b/include/configs/mx7ulp_com.h
index 48172de..58d48ed 100644
--- a/include/configs/mx7ulp_com.h
+++ b/include/configs/mx7ulp_com.h
@@ -60,11 +60,6 @@
"bootz ${loadaddr} - ${fdt_addr}; " \
"fi;\0" \
-#define CONFIG_BOOTCOMMAND \
- "if run loadimage; then " \
- "run mmcboot; " \
- "fi; " \
-
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE SZ_256K
diff --git a/include/configs/mxs.h b/include/configs/mxs.h
index b5c525d..51624a2 100644
--- a/include/configs/mxs.h
+++ b/include/configs/mxs.h
@@ -105,11 +105,6 @@
#endif
#endif
-/* LCD */
-#ifdef CONFIG_VIDEO
-#define CONFIG_VIDEO_MXS
-#endif
-
/* NAND */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
@@ -126,10 +121,4 @@
#define CONFIG_SPI_HALF_DUPLEX
#endif
-/* USB */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI_MXS
-#define CONFIG_EHCI_IS_TDI
-#endif
-
#endif /* __CONFIGS_MXS_H__ */
diff --git a/include/configs/nas220.h b/include/configs/nas220.h
index 16bbc9b..99b14ba 100644
--- a/include/configs/nas220.h
+++ b/include/configs/nas220.h
@@ -61,14 +61,6 @@
#endif /* CONFIG_CMD_NET */
/*
- * USB/EHCI
- */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */
-#define CONFIG_EHCI_IS_TDI
-#endif /* CONFIG_CMD_USB */
-
-/*
* File system
*/
#define CONFIG_JFFS2_NAND
diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h
index f9db8ef..d9311a4 100644
--- a/include/configs/opos6uldev.h
+++ b/include/configs/opos6uldev.h
@@ -43,7 +43,6 @@
#ifdef CONFIG_DM_VIDEO
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_VIDEO_MXS
#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR
#endif
#endif
diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h
index 7e36cee..6fed752 100644
--- a/include/configs/pico-imx6ul.h
+++ b/include/configs/pico-imx6ul.h
@@ -135,8 +135,7 @@
*/
#define CONFIG_BOARD_SIZE_LIMIT 715776
-#ifdef CONFIG_VIDEO
-#define CONFIG_VIDEO_MXS
+#ifdef CONFIG_DM_VIDEO
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR
diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h
index 36c5792..c046427 100644
--- a/include/configs/pico-imx7d.h
+++ b/include/configs/pico-imx7d.h
@@ -126,7 +126,6 @@
#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
#ifdef CONFIG_DM_VIDEO
-#define CONFIG_VIDEO_MXS
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#endif
diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h
index c13f8de..8089993 100644
--- a/include/configs/pm9263.h
+++ b/include/configs/pm9263.h
@@ -136,8 +136,6 @@
AT91_WDT_MR_WDDIS | \
AT91_WDT_MR_WDD(0xfff))
-#define CONFIG_USER_LOWLEVEL_INIT 1
-
/*
* Hardware drivers
*/
diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h
index cf80801..55ca801 100644
--- a/include/configs/smegw01.h
+++ b/include/configs/smegw01.h
@@ -26,9 +26,8 @@
"bootm_size=0x10000000\0" \
"mmcdev=0\0" \
"mmcpart=1\0" \
- "mmcroot=/dev/mmcblk0p1 rootwait rw\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
- "root=${mmcroot}\0" \
+ "root=/dev/mmcblk0p${mmcpart} rootwait rw\0" \
"loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${image}\0" \
"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} boot/${fdtfile}\0" \
"mmcboot=echo Booting from mmc ...; " \
diff --git a/include/configs/stih410-b2260.h b/include/configs/stih410-b2260.h
index b1917c9..2fe0900 100644
--- a/include/configs/stih410-b2260.h
+++ b/include/configs/stih410-b2260.h
@@ -57,11 +57,6 @@
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
-#define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_ASIX
-#define CONFIG_USB_ETHER_MCS7830
-#define CONFIG_USB_ETHER_SMSC95XX
-
/* NET Configs */
#endif /* __CONFIG_H */
diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h
index 525a527..8dddd54 100644
--- a/include/configs/stm32f429-discovery.h
+++ b/include/configs/stm32f429-discovery.h
@@ -21,15 +21,10 @@
#define CONFIG_RED_LED 110
#define CONFIG_GREEN_LED 109
-#define CONFIG_STM32_FLASH
-
#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_BOOTCOMMAND \
- "run bootcmd_romfs"
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \
"bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \
diff --git a/include/configs/stm32f429-evaluation.h b/include/configs/stm32f429-evaluation.h
index 609b4c2..c490e2d 100644
--- a/include/configs/stm32f429-evaluation.h
+++ b/include/configs/stm32f429-evaluation.h
@@ -23,8 +23,6 @@
#define CONFIG_SYS_MAX_FLASH_SECT 12
#define CONFIG_SYS_MAX_FLASH_BANKS 2
-#define CONFIG_STM32_FLASH
-
#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
#define CONFIG_SYS_CBSIZE 1024
diff --git a/include/configs/stm32f469-discovery.h b/include/configs/stm32f469-discovery.h
index a8f6fbf..246dc1f 100644
--- a/include/configs/stm32f469-discovery.h
+++ b/include/configs/stm32f469-discovery.h
@@ -23,8 +23,6 @@
#define CONFIG_SYS_MAX_FLASH_SECT 12
#define CONFIG_SYS_MAX_FLASH_BANKS 2
-#define CONFIG_STM32_FLASH
-
#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
#define CONFIG_SYS_CBSIZE 1024
diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h
index c76d290..493699e 100644
--- a/include/configs/stm32f746-disco.h
+++ b/include/configs/stm32f746-disco.h
@@ -22,8 +22,6 @@
#define CONFIG_SYS_MAX_FLASH_SECT 8
#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_STM32_FLASH
-
#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL (8)
#define CONFIG_DW_ALTDESCRIPTOR
diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h
index 06cd153..30d4e8f 100644
--- a/include/configs/stm32mp1.h
+++ b/include/configs/stm32mp1.h
@@ -108,7 +108,7 @@
* for serial/usb: execute the stm32prog command
* for mmc boot (eMMC, SD card), boot only on the same device
* for nand or spi-nand boot, boot with on ubifs partition on UBI partition
- * for nor boot, use SD card = mmc0
+ * for nor boot, use the default order
*/
#define STM32MP_BOOTCMD "bootcmd_stm32mp=" \
"echo \"Boot over ${boot_device}${boot_instance}!\";" \
@@ -121,8 +121,6 @@
"if test ${boot_device} = nand ||" \
" test ${boot_device} = spi-nand ;" \
"then env set boot_targets ubifs0; fi;" \
- "if test ${boot_device} = nor;" \
- "then env set boot_targets mmc0; fi;" \
"run distro_bootcmd;" \
"fi;\0"
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 5d8b605..c576d65 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -160,23 +160,6 @@
#define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */
#endif
-
-/* I2C */
-#if defined(CONFIG_VIDEO_LCD_PANEL_I2C)
-/* We use pin names in Kconfig and sunxi_name_to_gpio() */
-#define CONFIG_SOFT_I2C_GPIO_SDA soft_i2c_gpio_sda
-#define CONFIG_SOFT_I2C_GPIO_SCL soft_i2c_gpio_scl
-#ifndef __ASSEMBLY__
-extern int soft_i2c_gpio_sda;
-extern int soft_i2c_gpio_scl;
-#endif
-#define CONFIG_VIDEO_LCD_I2C_BUS 0 /* The lcd panel soft i2c is bus 0 */
-#define CONFIG_SYS_SPD_BUS_NUM 1 /* And the axp209 i2c bus is bus 1 */
-#else
-#define CONFIG_SYS_SPD_BUS_NUM 0 /* The axp209 i2c bus is bus 0 */
-#define CONFIG_VIDEO_LCD_I2C_BUS -1 /* NA, but necessary to compile */
-#endif
-
/* Ethernet support */
#ifdef CONFIG_USB_EHCI_HCD
diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h
index f714c52..0973721 100644
--- a/include/configs/tegra114-common.h
+++ b/include/configs/tegra114-common.h
@@ -58,7 +58,6 @@
#define CONFIG_SPL_STACK 0x800ffffc
/* For USB EHCI controller */
-#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
#endif /* _TEGRA114_COMMON_H_ */
diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h
index 4a92954..df688da 100644
--- a/include/configs/tegra124-common.h
+++ b/include/configs/tegra124-common.h
@@ -60,7 +60,6 @@
#define CONFIG_SPL_STACK 0x800ffffc
/* For USB EHCI controller */
-#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
/* GPU needs setup */
diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h
index 19934a4..063213c 100644
--- a/include/configs/tegra20-common.h
+++ b/include/configs/tegra20-common.h
@@ -78,7 +78,6 @@
* packets depending on the buffer address and size.
*/
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
-#define CONFIG_EHCI_IS_TDI
#define CONFIG_SYS_NAND_SELF_INIT
diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h
index b9e0414..3ba12be 100644
--- a/include/configs/tegra210-common.h
+++ b/include/configs/tegra210-common.h
@@ -44,10 +44,9 @@
"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"fdtfile=" FDTFILE "\0" \
"fdt_addr_r=0x83000000\0" \
- "ramdisk_addr_r=0x83200000\0"
+ "ramdisk_addr_r=0x83420000\0"
/* For USB EHCI controller */
-#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
/* GPU needs setup */
diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h
index 0ee13a2..b878b1a 100644
--- a/include/configs/tegra30-common.h
+++ b/include/configs/tegra30-common.h
@@ -55,7 +55,6 @@
#define CONFIG_SPL_STACK 0x800ffffc
/* For USB EHCI controller */
-#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
#endif /* _TEGRA30_COMMON_H_ */
diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h
index 64b7f25..b43c03d 100644
--- a/include/configs/theadorable.h
+++ b/include/configs/theadorable.h
@@ -29,7 +29,6 @@
#define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE
/* USB/EHCI configuration */
-#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
/* Environment in SPI NOR flash */
diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h
index 1ce0347..6006898 100644
--- a/include/configs/thunderx_88xx.h
+++ b/include/configs/thunderx_88xx.h
@@ -58,7 +58,6 @@
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
#define CONFIG_SYS_MAXARGS 64 /* max command args */
-#define CONFIG_NO_RELOCATION 1
#define PLL_REF_CLK 50000000 /* 50 MHz */
#define NS_PER_REF_CLK_TICK (1000000000/PLL_REF_CLK)
diff --git a/include/configs/total_compute.h b/include/configs/total_compute.h
index bbeedaf..933a145 100644
--- a/include/configs/total_compute.h
+++ b/include/configs/total_compute.h
@@ -30,6 +30,9 @@
#define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define PHYS_SDRAM_2 0x8080000000
+#define PHYS_SDRAM_2_SIZE 0x180000000
+
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 127
#define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h
index f9a0b7d..3e76d63 100644
--- a/include/configs/tplink_wdr4300.h
+++ b/include/configs/tplink_wdr4300.h
@@ -41,7 +41,6 @@
/* USB, USB storage, USB ethernet */
#define CONFIG_EHCI_MMIO_BIG_ENDIAN
#define CONFIG_EHCI_DESC_BIG_ENDIAN
-#define CONFIG_EHCI_IS_TDI
/*
* Diagnostics
diff --git a/include/configs/turris_mox.h b/include/configs/turris_mox.h
index 0bbc984..3cfad7c 100644
--- a/include/configs/turris_mox.h
+++ b/include/configs/turris_mox.h
@@ -8,20 +8,11 @@
#ifndef _CONFIG_TURRIS_MOX_H
#define _CONFIG_TURRIS_MOX_H
-#define CONFIG_SYS_BOOTM_LEN (64 << 20)
-
-#define CONFIG_LAST_STAGE_INIT
-
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_DISPLAY_BOARDINFO_LATE
-
-/* additions for new ARM relocation support */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-
-/* auto boot */
-
+#define CONFIG_SYS_BOOTM_LEN (64 << 20)
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0xFF0000)
+#define CONFIG_SYS_CBSIZE 1024
+#define CONFIG_SYS_MAXARGS 32
#define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \
9600, 19200, 38400, 57600, 115200, \
230400, 460800, 500000, 576000, \
@@ -30,31 +21,10 @@
4000000, 4500000, 5000000, 5500000, \
6000000 }
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
+#define CONFIG_ARP_TIMEOUT 200
+#define CONFIG_NET_RETRY_COUNT 50
-/*
- * Other required minimal configurations
- */
-#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
-#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
-
-/* End of 16M scrubbed by training in bootrom */
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0xFF0000)
-
-/*
- * I2C
- */
-#define CONFIG_I2C_MV
-
-/* Environment in SPI NOR flash */
-
-/*
- * Ethernet Driver configuration
- */
-#define CONFIG_ARP_TIMEOUT 200
-#define CONFIG_NET_RETRY_COUNT 50
-
-#define CONFIG_USB_MAX_CONTROLLER_COUNT (3 + 3)
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 6
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
@@ -64,22 +34,22 @@
#include <config_distro_bootcmd.h>
-#define TURRIS_MOX_BOOTCMD_RESCUE \
- "setenv bootargs \"console=ttyMV0,115200 " \
- "earlycon=ar3700_uart,0xd0012000\" && " \
- "sf probe && " \
- "sf read 0x5000000 0x190000 && " \
- "lzmadec 0x5000000 0x5800000 && " \
+#define TURRIS_MOX_BOOTCMD_RESCUE \
+ "setenv bootargs \"console=ttyMV0,115200 " \
+ "earlycon=ar3700_uart,0xd0012000\" && " \
+ "sf probe && " \
+ "sf read 0x5000000 0x190000 && " \
+ "lzmadec 0x5000000 0x5800000 && " \
"bootm 0x5800000"
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "scriptaddr=0x4d00000\0" \
- "pxefile_addr_r=0x4e00000\0" \
- "fdt_addr_r=0x4f00000\0" \
- "kernel_addr_r=0x5000000\0" \
- "ramdisk_addr_r=0x8000000\0" \
- "fdtfile=marvell/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
- "bootcmd_rescue=" TURRIS_MOX_BOOTCMD_RESCUE "\0" \
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "scriptaddr=0x4d00000\0" \
+ "pxefile_addr_r=0x4e00000\0" \
+ "fdt_addr_r=0x4f00000\0" \
+ "kernel_addr_r=0x5000000\0" \
+ "ramdisk_addr_r=0x8000000\0" \
+ "fdtfile=marvell/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
+ "bootcmd_rescue=" TURRIS_MOX_BOOTCMD_RESCUE "\0" \
BOOTENV
#endif /* _CONFIG_TURRIS_MOX_H */
diff --git a/include/configs/turris_omnia.h b/include/configs/turris_omnia.h
index 8646633..9436a62 100644
--- a/include/configs/turris_omnia.h
+++ b/include/configs/turris_omnia.h
@@ -17,9 +17,6 @@
* U-Boot into it.
*/
-/* USB/EHCI configuration */
-#define CONFIG_EHCI_IS_TDI
-
/* Environment in SPI NOR flash */
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
@@ -36,13 +33,8 @@
#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MALLOC_SIMPLE
-#endif
-
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
-#define CONFIG_SPL_DRIVERS_MISC
#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC
/* SPL related MMC defines */
diff --git a/include/configs/x530.h b/include/configs/x530.h
index d6aec6d..f4d6449 100644
--- a/include/configs/x530.h
+++ b/include/configs/x530.h
@@ -45,9 +45,6 @@
/* Additional FS support/configuration */
-/* USB/EHCI configuration */
-#define CONFIG_EHCI_IS_TDI
-
/* Environment in SPI NOR flash */
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
@@ -61,11 +58,6 @@
#include <asm/arch/config.h>
-/*
- * Other required minimal configurations
- */
-#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
-
/* Keep device tree and initrd in low memory so the kernel can access them */
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0x10000000\0" \
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 0c87f19..4de2f94 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -55,8 +55,6 @@
#endif
#ifdef CONFIG_USB_EHCI_ZYNQ
-# define CONFIG_EHCI_IS_TDI
-
# define DFU_DEFAULT_POLL_TIMEOUT 300
# define CONFIG_THOR_RESET_OFF
#endif
diff --git a/include/dm/fdtaddr.h b/include/dm/fdtaddr.h
index a4fda58..d2c1994 100644
--- a/include/dm/fdtaddr.h
+++ b/include/dm/fdtaddr.h
@@ -93,6 +93,18 @@
fdt_addr_t devfdt_get_addr_index(const struct udevice *dev, int index);
/**
+ * devfdt_get_addr_index_ptr() - Return indexed pointer to the address of the
+ * reg property of a device
+ *
+ * @dev: Pointer to a device
+ * @index: the 'reg' property can hold a list of <addr, size> pairs
+ * and @index is used to select which one is required
+ *
+ * @return Pointer to addr, or NULL if there is no such property
+ */
+void *devfdt_get_addr_index_ptr(const struct udevice *dev, int index);
+
+/**
* devfdt_get_addr_size_index() - Get the indexed reg property of a device
*
* Returns the address and size specified in the 'reg' property of a device.
diff --git a/include/dm/lists.h b/include/dm/lists.h
index 1a86552..5896ae3 100644
--- a/include/dm/lists.h
+++ b/include/dm/lists.h
@@ -53,13 +53,14 @@
* @parent: parent device (root)
* @node: device tree node to bind
* @devp: if non-NULL, returns a pointer to the bound device
+ * @drv: if non-NULL, force this driver to be bound
* @pre_reloc_only: If true, bind only nodes with special devicetree properties,
* or drivers with the DM_FLAG_PRE_RELOC flag. If false bind all drivers.
* @return 0 if device was bound, -EINVAL if the device tree is invalid,
* other -ve value on error
*/
int lists_bind_fdt(struct udevice *parent, ofnode node, struct udevice **devp,
- bool pre_reloc_only);
+ struct driver *drv, bool pre_reloc_only);
/**
* device_bind_driver() - bind a device to a driver
diff --git a/include/dm/read.h b/include/dm/read.h
index 5bf3405..890bf3d 100644
--- a/include/dm/read.h
+++ b/include/dm/read.h
@@ -181,6 +181,18 @@
fdt_addr_t dev_read_addr_index(const struct udevice *dev, int index);
/**
+ * dev_read_addr_index_ptr() - Get the indexed reg property of a device
+ * as a pointer
+ *
+ * @dev: Device to read from
+ * @index: the 'reg' property can hold a list of <addr, size> pairs
+ * and @index is used to select which one is required
+ *
+ * @return pointer or NULL if not found
+ */
+void *dev_read_addr_index_ptr(const struct udevice *dev, int index);
+
+/**
* dev_read_addr_size_index() - Get the indexed reg property of a device
*
* @dev: Device to read from
@@ -805,6 +817,12 @@
return devfdt_get_addr_index(dev, index);
}
+static inline void *dev_read_addr_index_ptr(const struct udevice *dev,
+ int index)
+{
+ return devfdt_get_addr_index_ptr(dev, index);
+}
+
static inline fdt_addr_t dev_read_addr_size_index(const struct udevice *dev,
int index,
fdt_size_t *size)
diff --git a/include/dm/util.h b/include/dm/util.h
index c634e47..17baf55 100644
--- a/include/dm/util.h
+++ b/include/dm/util.h
@@ -48,8 +48,6 @@
/* Dump out a list of drivers with static platform data */
void dm_dump_static_driver_info(void);
-#endif
-
#if CONFIG_IS_ENABLED(OF_PLATDATA_INST) && CONFIG_IS_ENABLED(READ_ONLY)
void *dm_priv_to_rw(void *priv);
#else
@@ -58,3 +56,5 @@
return priv;
}
#endif
+
+#endif
diff --git a/include/efi_load_initrd.h b/include/efi_load_initrd.h
index 478ae80..be5d5a7 100644
--- a/include/efi_load_initrd.h
+++ b/include/efi_load_initrd.h
@@ -16,6 +16,7 @@
#define EFI_INITRD_MEDIA_GUID \
EFI_GUID(0x5568e427, 0x68fc, 0x4f3d, \
0xac, 0x74, 0xca, 0x55, 0x52, 0x31, 0xcc, 0x68)
+extern const efi_guid_t efi_lf2_initrd_guid;
struct efi_initrd_dp {
struct efi_device_path_vendor vendor;
diff --git a/include/efi_loader.h b/include/efi_loader.h
index c440962..3e5ac38 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -675,6 +675,8 @@
#define efi_size_in_pages(size) (((size) + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT)
/* Generic EFI memory allocator, call this to get memory */
void *efi_alloc(uint64_t len, int memory_type);
+/* Allocate pages on the specified alignment */
+void *efi_alloc_aligned_pages(u64 len, int memory_type, size_t align);
/* More specific EFI memory allocator, called by EFI payloads */
efi_status_t efi_allocate_pages(enum efi_allocate_type type,
enum efi_memory_type memory_type,
@@ -840,7 +842,7 @@
};
struct efi_device_path *efi_dp_from_lo(struct efi_load_option *lo,
- efi_uintn_t *size, efi_guid_t guid);
+ const efi_guid_t *guid);
struct efi_device_path *efi_dp_concat(const struct efi_device_path *dp1,
const struct efi_device_path *dp2);
efi_status_t efi_deserialize_load_option(struct efi_load_option *lo, u8 *data,
diff --git a/include/env.h b/include/env.h
index d5e2bcb..ee5e30d 100644
--- a/include/env.h
+++ b/include/env.h
@@ -91,17 +91,6 @@
void env_relocate(void);
/**
- * env_match() - Match a name / name=value pair
- *
- * This is used prior to relocation for finding envrionment variables
- *
- * @name: A simple 'name', or a 'name=value' pair.
- * @index: The environment index for a 'name2=value2' pair.
- * @return index for the value if the names match, else -1.
- */
-int env_match(unsigned char *name, int index);
-
-/**
* env_get() - Look up the value of an environment variable
*
* In U-Boot proper this can be called before relocation (which is when the
@@ -131,7 +120,8 @@
* support reading the value (slowly) and some will not.
*
* @varname: Variable to look up
- * @return value of variable, or NULL if not found
+ * @return actual length of the variable value excluding the terminating
+ * NULL-byte, or -1 if the variable is not found
*/
int env_get_f(const char *name, char *buf, unsigned int len);
@@ -360,16 +350,6 @@
void env_set_default(const char *s, int flags);
/**
- * env_get_char() - Get a character from the early environment
- *
- * This reads from the pre-relocation environment
- *
- * @index: Index of character to read (0 = first)
- * @return character read, or -ve on error
- */
-int env_get_char(int index);
-
-/**
* env_reloc() - Relocate the 'env' sub-commands
*
* This is used for those unfortunate archs with crappy toolchains
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 72a5b90..88d129c 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -7,7 +7,7 @@
#ifndef __FDT_SUPPORT_H
#define __FDT_SUPPORT_H
-#ifdef CONFIG_OF_LIBFDT
+#if defined(CONFIG_OF_LIBFDT) && !defined(USE_HOSTCC)
#include <asm/u-boot.h>
#include <linux/libfdt.h>
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 23efbe7..2398142 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -55,10 +55,6 @@
#define SPL_BUILD 0
#endif
-#ifdef CONFIG_OF_PRIOR_STAGE
-extern phys_addr_t prior_stage_fdt_address;
-#endif
-
/*
* Information about a resource. start is the first address of the resource
* and end is the last address (inclusive). The length of the resource will
@@ -977,6 +973,9 @@
return fdt_setprop_u32(blob, node, "phandle", phandle);
}
+/* add "no-map" property */
+#define FDTDEC_RESERVED_MEMORY_NO_MAP (1 << 0)
+
/**
* fdtdec_add_reserved_memory() - add or find a reserved-memory node
*
@@ -995,7 +994,8 @@
* };
* uint32_t phandle;
*
- * fdtdec_add_reserved_memory(fdt, "framebuffer", &fb, &phandle, false);
+ * fdtdec_add_reserved_memory(fdt, "framebuffer", &fb, NULL, 0, &phandle,
+ * 0);
*
* This results in the following subnode being added to the top-level
* /reserved-memory node:
@@ -1020,14 +1020,17 @@
* @param blob FDT blob
* @param basename base name of the node to create
* @param carveout information about the carveout region
+ * @param compatibles list of compatible strings for the carveout region
+ * @param count number of compatible strings for the carveout region
* @param phandlep return location for the phandle of the carveout region
* can be NULL if no phandle should be added
- * @param no_map add "no-map" property if true
+ * @param flags bitmask of flags to set for the carveout region
* @return 0 on success or a negative error code on failure
*/
int fdtdec_add_reserved_memory(void *blob, const char *basename,
const struct fdt_memory *carveout,
- uint32_t *phandlep, bool no_map);
+ const char **compatibles, unsigned int count,
+ uint32_t *phandlep, unsigned long flags);
/**
* fdtdec_get_carveout() - reads a carveout from an FDT
@@ -1038,14 +1041,21 @@
*
* @param blob FDT blob
* @param node name of a node
- * @param name name of the property in the given node that contains
+ * @param prop_name name of the property in the given node that contains
* the phandle for the carveout
* @param index index of the phandle for which to read the carveout
* @param carveout return location for the carveout information
+ * @param name return location for the carveout name
+ * @param compatiblesp return location for compatible strings
+ * @param countp return location for the number of compatible strings
+ * @param flags return location for the flags of the carveout
* @return 0 on success or a negative error code on failure
*/
-int fdtdec_get_carveout(const void *blob, const char *node, const char *name,
- unsigned int index, struct fdt_memory *carveout);
+int fdtdec_get_carveout(const void *blob, const char *node,
+ const char *prop_name, unsigned int index,
+ struct fdt_memory *carveout, const char **name,
+ const char ***compatiblesp, unsigned int *countp,
+ unsigned long *flags);
/**
* fdtdec_set_carveout() - sets a carveout region for a given node
@@ -1063,7 +1073,8 @@
* .end = 0x934b2fff,
* };
*
- * fdtdec_set_carveout(fdt, node, "memory-region", 0, "framebuffer", &fb);
+ * fdtdec_set_carveout(fdt, node, "memory-region", 0, "framebuffer", NULL,
+ * 0, &fb, 0);
*
* dc@54200000 is a display controller and was set up by the bootloader to
* scan out the framebuffer specified by "fb". This would cause the following
@@ -1100,13 +1111,17 @@
* @param prop_name name of the property in which to store the phandle of
* the carveout
* @param index index of the phandle to store
- * @param name base name of the reserved-memory node to create
* @param carveout information about the carveout to add
+ * @param name base name of the reserved-memory node to create
+ * @param compatibles compatible strings to set for the carveout
+ * @param count number of compatible strings
+ * @param flags bitmask of flags to set for the carveout
* @return 0 on success or a negative error code on failure
*/
int fdtdec_set_carveout(void *blob, const char *node, const char *prop_name,
- unsigned int index, const char *name,
- const struct fdt_memory *carveout);
+ unsigned int index, const struct fdt_memory *carveout,
+ const char *name, const char **compatibles,
+ unsigned int count, unsigned long flags);
/**
* Set up the device tree ready for use
diff --git a/include/fsl_esdhc_imx.h b/include/fsl_esdhc_imx.h
index 45ed635..12e9163 100644
--- a/include/fsl_esdhc_imx.h
+++ b/include/fsl_esdhc_imx.h
@@ -194,6 +194,7 @@
#define ESDHC_STROBE_DLL_CTRL_RESET BIT(1)
#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT 0x7
#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
+#define ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT (4 << 20)
#define ESDHC_STROBE_DLL_STATUS 0x74
#define ESDHC_STROBE_DLL_STS_REF_LOCK BIT(1)
diff --git a/include/gzip.h b/include/gzip.h
index 783acbb..cb4db3d 100644
--- a/include/gzip.h
+++ b/include/gzip.h
@@ -54,11 +54,11 @@
* gzwrite_progress_finish called at end of loop to
* indicate success (retcode=0) or failure
*/
-void gzwrite_progress_init(u64 expected_size);
+void gzwrite_progress_init(ulong expected_size);
-void gzwrite_progress(int iteration, u64 bytes_written, u64 total_bytes);
+void gzwrite_progress(int iteration, ulong bytes_written, ulong total_bytes);
-void gzwrite_progress_finish(int retcode, u64 totalwritten, u64 totalsize,
+void gzwrite_progress_finish(int retcode, ulong totalwritten, ulong totalsize,
u32 expected_crc, u32 calculated_crc);
/**
@@ -74,7 +74,7 @@
* @return 0 if OK, -1 on error
*/
int gzwrite(unsigned char *src, int len, struct blk_desc *dev, ulong szwritebuf,
- u64 startoffs, u64 szexpected);
+ ulong startoffs, ulong szexpected);
/**
* gzip()- Compress data into a buffer using the gzip algorithm
diff --git a/include/hash.h b/include/hash.h
index 97bb3ed..cfafbe7 100644
--- a/include/hash.h
+++ b/include/hash.h
@@ -6,13 +6,17 @@
#ifndef _HASH_H
#define _HASH_H
+#ifdef USE_HOSTCC
+#include <linux/kconfig.h>
+#endif
+
struct cmd_tbl;
/*
* Maximum digest size for all algorithms we support. Having this value
* avoids a malloc() or C99 local declaration in common/cmd_hash.c.
*/
-#if defined(CONFIG_SHA384) || defined(CONFIG_SHA512)
+#if CONFIG_IS_ENABLED(SHA384) || CONFIG_IS_ENABLED(SHA512)
#define HASH_MAX_DIGEST_SIZE 64
#else
#define HASH_MAX_DIGEST_SIZE 32
diff --git a/include/image.h b/include/image.h
index 73a763a..34d13ad 100644
--- a/include/image.h
+++ b/include/image.h
@@ -25,19 +25,8 @@
#ifdef USE_HOSTCC
#include <sys/types.h>
+#include <linux/kconfig.h>
-/* new uImage format support enabled on host */
-#define IMAGE_ENABLE_FIT 1
-#define IMAGE_ENABLE_OF_LIBFDT 1
-#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
-#define CONFIG_FIT_RSASSA_PSS 1
-#define CONFIG_MD5
-#define CONFIG_SHA1
-#define CONFIG_SHA256
-#define CONFIG_SHA384
-#define CONFIG_SHA512
-
-#define IMAGE_ENABLE_IGNORE 0
#define IMAGE_INDENT_STRING ""
#else
@@ -47,38 +36,14 @@
#include <command.h>
#include <linker_lists.h>
-/* Take notice of the 'ignore' property for hashes */
-#define IMAGE_ENABLE_IGNORE 1
#define IMAGE_INDENT_STRING " "
-#define IMAGE_ENABLE_FIT CONFIG_IS_ENABLED(FIT)
-#define IMAGE_ENABLE_OF_LIBFDT CONFIG_IS_ENABLED(OF_LIBFDT)
-
#endif /* USE_HOSTCC */
-#if IMAGE_ENABLE_FIT
#include <hash.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
-#endif /* IMAGE_ENABLE_FIT */
-
-#ifdef CONFIG_SYS_BOOT_GET_CMDLINE
-# define IMAGE_BOOT_GET_CMDLINE 1
-#else
-# define IMAGE_BOOT_GET_CMDLINE 0
-#endif
-
-#ifdef CONFIG_OF_BOARD_SETUP
-# define IMAGE_OF_BOARD_SETUP 1
-#else
-# define IMAGE_OF_BOARD_SETUP 0
-#endif
-
-#ifdef CONFIG_OF_SYSTEM_SETUP
-# define IMAGE_OF_SYSTEM_SETUP 1
-#else
-# define IMAGE_OF_SYSTEM_SETUP 0
-#endif
+#include <u-boot/hash-checksum.h>
extern ulong image_load_addr; /* Default Load Address */
extern ulong image_save_addr; /* Default Save Address */
@@ -333,7 +298,11 @@
image_header_t legacy_hdr_os_copy; /* header copy */
ulong legacy_hdr_valid;
-#if IMAGE_ENABLE_FIT
+ /*
+ * The fit_ members are only used with FIT, but it involves a lot of
+ * #ifdefs to avoid compiling that code. Since FIT is the standard
+ * format, even for SPL, this extra data size seems worth it.
+ */
const char *fit_uname_cfg; /* configuration node unit name */
void *fit_hdr_os; /* os FIT image header */
@@ -351,7 +320,6 @@
void *fit_hdr_setup; /* x86 setup FIT image header */
const char *fit_uname_setup; /* x86 setup subimage node name */
int fit_noffset_setup;/* x86 setup subimage node offset */
-#endif
#ifndef USE_HOSTCC
image_info_t os; /* os image info */
@@ -538,8 +506,7 @@
int genimg_get_comp_id(const char *name);
void genimg_print_size(uint32_t size);
-#if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE) || \
- defined(USE_HOSTCC)
+#if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE) || defined(USE_HOSTCC)
#define IMAGE_ENABLE_TIMESTAMP 1
#else
#define IMAGE_ENABLE_TIMESTAMP 0
@@ -557,12 +524,9 @@
int boot_get_setup(bootm_headers_t *images, uint8_t arch, ulong *setup_start,
ulong *setup_len);
-#ifndef USE_HOSTCC
/* Image format types, returned by _get_format() routine */
#define IMAGE_FORMAT_INVALID 0x00
-#if defined(CONFIG_LEGACY_IMAGE_FORMAT)
#define IMAGE_FORMAT_LEGACY 0x01 /* legacy image_header based format */
-#endif
#define IMAGE_FORMAT_FIT 0x02 /* new, libfdt based format */
#define IMAGE_FORMAT_ANDROID 0x03 /* Android boot image */
@@ -601,7 +565,6 @@
*/
int boot_get_loadable(int argc, char *const argv[], bootm_headers_t *images,
uint8_t arch, const ulong *ld_start, ulong *const ld_len);
-#endif /* !USE_HOSTCC */
int boot_get_setup_fit(bootm_headers_t *images, uint8_t arch,
ulong *setup_start, ulong *setup_len);
@@ -678,7 +641,6 @@
*/
int image_source_script(ulong addr, const char *fit_uname);
-#ifndef USE_HOSTCC
/**
* fit_get_node_from_config() - Look up an image a FIT by type
*
@@ -718,10 +680,7 @@
int boot_ramdisk_high(struct lmb *lmb, ulong rd_data, ulong rd_len,
ulong *initrd_start, ulong *initrd_end);
int boot_get_cmdline(struct lmb *lmb, ulong *cmd_start, ulong *cmd_end);
-#ifdef CONFIG_SYS_BOOT_GET_KBD
int boot_get_kbd(struct lmb *lmb, struct bd_info **kbd);
-#endif /* CONFIG_SYS_BOOT_GET_KBD */
-#endif /* !USE_HOSTCC */
/*******************************************************************/
/* Legacy format specific code (prefixed with image_) */
@@ -836,11 +795,9 @@
}
static inline int image_check_arch(const image_header_t *hdr, uint8_t arch)
{
-#ifndef USE_HOSTCC
/* Let's assume that sandbox can load any architecture */
- if (IS_ENABLED(CONFIG_SANDBOX))
+ if (!tools_build() && IS_ENABLED(CONFIG_SANDBOX))
return true;
-#endif
return (image_get_arch(hdr) == arch) ||
(image_get_arch(hdr) == IH_ARCH_ARM && arch == IH_ARCH_ARM64);
}
@@ -988,7 +945,6 @@
#define FIT_MAX_HASH_LEN HASH_MAX_DIGEST_SIZE
-#if IMAGE_ENABLE_FIT
/* cmdline argument format parsing */
int fit_parse_conf(const char *spec, ulong addr_curr,
ulong *addr, const char **conf_name);
@@ -1162,7 +1118,6 @@
int fit_check_ramdisk(const void *fit, int os_noffset,
uint8_t arch, int verify);
-#endif /* IMAGE_ENABLE_FIT */
int calculate_hash(const void *data, int data_len, const char *algo,
uint8_t *value, int *value_len);
@@ -1185,7 +1140,6 @@
# define FIT_IMAGE_ENABLE_VERIFY CONFIG_IS_ENABLED(FIT_SIGNATURE)
#endif
-#if IMAGE_ENABLE_FIT
#ifdef USE_HOSTCC
void *image_get_host_blob(void);
void image_set_host_blob(void *host_blob);
@@ -1194,8 +1148,6 @@
# define gd_fdt_blob() (gd->fdt_blob)
#endif
-#endif /* IMAGE_ENABLE_FIT */
-
/*
* Information passed to the signing routines
*
@@ -1232,9 +1184,6 @@
int size;
};
-#if FIT_IMAGE_ENABLE_VERIFY
-# include <u-boot/hash-checksum.h>
-#endif
struct checksum_algo {
const char *name;
const int checksum_len;
@@ -1244,7 +1193,7 @@
const EVP_MD *(*calculate_sign)(void);
#endif
int (*calculate)(const char *name,
- const struct image_region region[],
+ const struct image_region *region,
int region_count, uint8_t *checksum);
};
@@ -1340,8 +1289,6 @@
*/
struct padding_algo *image_get_padding_algo(const char *name);
-#if IMAGE_ENABLE_FIT
-
/**
* fit_image_verify_required_sigs() - Verify signatures marked as 'required'
*
@@ -1467,23 +1414,6 @@
struct cipher_algo *image_get_cipher_algo(const char *full_name);
-#ifdef CONFIG_FIT_VERBOSE
-#define fit_unsupported(msg) printf("! %s:%d " \
- "FIT images not supported for '%s'\n", \
- __FILE__, __LINE__, (msg))
-
-#define fit_unsupported_reset(msg) printf("! %s:%d " \
- "FIT images not supported for '%s' " \
- "- must reset board to recover!\n", \
- __FILE__, __LINE__, (msg))
-#else
-#define fit_unsupported(msg)
-#define fit_unsupported_reset(msg)
-#endif /* CONFIG_FIT_VERBOSE */
-#endif /* CONFIG_FIT */
-
-#if !defined(USE_HOSTCC)
-#if defined(CONFIG_ANDROID_BOOT_IMAGE)
struct andr_img_hdr;
int android_image_check_header(const struct andr_img_hdr *hdr);
int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify,
@@ -1499,12 +1429,7 @@
ulong android_image_get_kload(const struct andr_img_hdr *hdr);
ulong android_image_get_kcomp(const struct andr_img_hdr *hdr);
void android_print_contents(const struct andr_img_hdr *hdr);
-#if !defined(CONFIG_SPL_BUILD)
bool android_image_print_dtb_contents(ulong hdr_addr);
-#endif
-
-#endif /* CONFIG_ANDROID_BOOT_IMAGE */
-#endif /* !USE_HOSTCC */
/**
* board_fit_config_name_match() - Check for a matching board name
diff --git a/include/linux/kconfig.h b/include/linux/kconfig.h
index d109ed3..a1d1a29 100644
--- a/include/linux/kconfig.h
+++ b/include/linux/kconfig.h
@@ -31,11 +31,14 @@
(config_enabled(option))
/*
- * U-Boot add-on: Helper macros to reference to different macros
- * (CONFIG_ or CONFIG_SPL_ prefixed), depending on the build context.
+ * U-Boot add-on: Helper macros to reference to different macros (prefixed by
+ * CONFIG_, CONFIG_SPL_, CONFIG_TPL_ or CONFIG_TOOLS_), depending on the build
+ * context.
*/
-#if defined(CONFIG_TPL_BUILD)
+#ifdef USE_HOSTCC
+#define _CONFIG_PREFIX TOOLS_
+#elif defined(CONFIG_TPL_BUILD)
#define _CONFIG_PREFIX TPL_
#elif defined(CONFIG_SPL_BUILD)
#define _CONFIG_PREFIX SPL_
@@ -49,6 +52,7 @@
/*
* CONFIG_VAL(FOO) evaluates to the value of
+ * CONFIG_TOOLS_FOO if USE_HOSTCC is defined,
* CONFIG_FOO if CONFIG_SPL_BUILD is undefined,
* CONFIG_SPL_FOO if CONFIG_SPL_BUILD is defined.
* CONFIG_TPL_FOO if CONFIG_TPL_BUILD is defined.
@@ -76,18 +80,21 @@
/*
* CONFIG_IS_ENABLED(FOO) expands to
+ * 1 if USE_HOSTCC is defined and CONFIG_TOOLS_FOO is set to 'y',
* 1 if CONFIG_SPL_BUILD is undefined and CONFIG_FOO is set to 'y',
* 1 if CONFIG_SPL_BUILD is defined and CONFIG_SPL_FOO is set to 'y',
* 1 if CONFIG_TPL_BUILD is defined and CONFIG_TPL_FOO is set to 'y',
* 0 otherwise.
*
* CONFIG_IS_ENABLED(FOO, (abc)) expands to
+ * abc if USE_HOSTCC is defined and CONFIG_TOOLS_FOO is set to 'y',
* abc if CONFIG_SPL_BUILD is undefined and CONFIG_FOO is set to 'y',
* abc if CONFIG_SPL_BUILD is defined and CONFIG_SPL_FOO is set to 'y',
* abc if CONFIG_TPL_BUILD is defined and CONFIG_TPL_FOO is set to 'y',
* nothing otherwise.
*
* CONFIG_IS_ENABLED(FOO, (abc), (def)) expands to
+ * abc if USE_HOSTCC is defined and CONFIG_TOOLS_FOO is set to 'y',
* abc if CONFIG_SPL_BUILD is undefined and CONFIG_FOO is set to 'y',
* abc if CONFIG_SPL_BUILD is defined and CONFIG_SPL_FOO is set to 'y',
* abc if CONFIG_TPL_BUILD is defined and CONFIG_TPL_FOO is set to 'y',
diff --git a/include/linux/string.h b/include/linux/string.h
index dd255f2..3169c93 100644
--- a/include/linux/string.h
+++ b/include/linux/string.h
@@ -129,6 +129,19 @@
void *memchr_inv(const void *, int, size_t);
#endif
+/**
+ * memdup() - allocate a buffer and copy in the contents
+ *
+ * Note that this returns a valid pointer even if @len is 0
+ *
+ * @src: data to copy in
+ * @len: number of bytes to copy
+ * @return allocated buffer with the copied contents, or NULL if not enough
+ * memory is available
+ *
+ */
+char *memdup(const void *src, size_t len);
+
unsigned long ustrtoul(const char *cp, char **endp, unsigned int base);
unsigned long long ustrtoull(const char *cp, char **endp, unsigned int base);
diff --git a/include/linux/zstd.h b/include/linux/zstd.h
index 724f693..35ba4c9 100644
--- a/include/linux/zstd.h
+++ b/include/linux/zstd.h
@@ -1144,4 +1144,15 @@
size_t ZSTD_insertBlock(ZSTD_DCtx *dctx, const void *blockStart,
size_t blockSize);
+struct abuf;
+
+/**
+ * zstd_decompress() - Decompress Zstandard data
+ *
+ * @in: Input buffer to decompress
+ * @out: Output buffer to hold the results (must be large enough)
+ * @return size of the decompressed data, or -ve on error
+ */
+int zstd_decompress(struct abuf *in, struct abuf *out);
+
#endif /* ZSTD_H */
diff --git a/include/pci.h b/include/pci.h
index 11009a2..797f224 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -495,6 +495,10 @@
#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
+#define PCI_EXP_RTCTL 28 /* Root Control */
+#define PCI_EXP_RTCTL_CRSSVE 0x0010 /* CRS Software Visibility Enable */
+#define PCI_EXP_RTCAP 30 /* Root Capabilities */
+#define PCI_EXP_RTCAP_CRSVIS 0x0001 /* CRS Software Visibility capability */
#define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */
#define PCI_EXP_DEVCAP2_ARI 0x00000020 /* ARI Forwarding Supported */
#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
diff --git a/include/relocate.h b/include/relocate.h
index 9ceeecd..26682da 100644
--- a/include/relocate.h
+++ b/include/relocate.h
@@ -7,7 +7,11 @@
#ifndef _RELOCATE_H_
#define _RELOCATE_H_
-#include <common.h>
+#ifndef USE_HOSTCC
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+#endif
/**
* copy_uboot_to_ram() - Copy U-Boot to its new relocated position
@@ -35,4 +39,28 @@
*/
int do_elf_reloc_fixups(void);
+/**
+ * manual_reloc() - Manually relocate a pointer if needed
+ *
+ * This is a nop in almost all cases, except for the systems with a broken gcc
+ * which need to manually relocate some things.
+ *
+ * @ptr: Pointer to relocate
+ * @return new pointer value
+ */
+static inline void *manual_reloc(void *ptr)
+{
+#ifndef USE_HOSTCC
+ if (IS_ENABLED(CONFIG_NEEDS_MANUAL_RELOC))
+ return ptr + gd->reloc_off;
+#endif
+ return ptr;
+}
+
+#if !defined(USE_HOSTCC) && defined(CONFIG_NEEDS_MANUAL_RELOC)
+#define MANUAL_RELOC(ptr) (ptr) = manual_reloc(ptr)
+#else
+#define MANUAL_RELOC(ptr) (void)(ptr)
+#endif
+
#endif /* _RELOCATE_H_ */
diff --git a/include/spl.h b/include/spl.h
index afbf39b..7ddb2ab 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -305,6 +305,14 @@
bool spl_load_simple_fit_skip_processing(void);
/**
+ * spl_load_simple_fit_fix_load() - Hook to make fixes
+ * after fit image header is loaded
+ *
+ * Returns pointer to fit
+ */
+void *spl_load_simple_fit_fix_load(const void *fit);
+
+/**
* spl_load_simple_fit() - Loads a fit image from a device.
* @spl_image: Image description to set up
* @info: Structure containing the information required to load data.
diff --git a/include/sysreset.h b/include/sysreset.h
index 701e4f5..9d4ed87 100644
--- a/include/sysreset.h
+++ b/include/sysreset.h
@@ -9,43 +9,55 @@
struct udevice;
+/**
+ * enum sysreset_t - system reset types
+ */
enum sysreset_t {
- SYSRESET_WARM, /* Reset CPU, keep GPIOs active */
- SYSRESET_COLD, /* Reset CPU and GPIOs */
- SYSRESET_POWER, /* Reset PMIC (remove and restore power) */
- SYSRESET_POWER_OFF, /* Turn off power */
-
+ /** @SYSRESET_WARM: reset CPU, keep GPIOs active */
+ SYSRESET_WARM,
+ /** @SYSRESET_COLD: reset CPU and GPIOs */
+ SYSRESET_COLD,
+ /** @SYSRESET_POWER: reset PMIC (remove and restore power) */
+ SYSRESET_POWER,
+ /** @SYSRESET_POWER_OFF: turn off power */
+ SYSRESET_POWER_OFF,
+ /** @SYSRESET_COUNT: number of available reset types */
SYSRESET_COUNT,
};
+/**
+ * struct sysreset_ops - operations of system reset drivers
+ */
struct sysreset_ops {
/**
- * request() - request a sysreset of the given type
+ * @request: request a sysreset of the given type
*
* Note that this function may return before the reset takes effect.
*
+ * @dev: Device to be used for system reset
* @type: Reset type to request
- * @return -EINPROGRESS if the reset has been started and
- * will complete soon, -EPROTONOSUPPORT if not supported
- * by this device, 0 if the reset has already happened
- * (in which case this method will not actually return)
+ * Return:
+ * -EINPROGRESS if the reset has been started and
+ * will complete soon, -EPROTONOSUPPORT if not supported
+ * by this device, 0 if the reset has already happened
+ * (in which case this method will not actually return)
*/
int (*request)(struct udevice *dev, enum sysreset_t type);
/**
- * get_status() - get printable reset status information
+ * @get_status: get printable reset status information
*
* @dev: Device to check
* @buf: Buffer to receive the textual reset information
* @size: Size of the passed buffer
- * @return 0 if OK, -ve on error
+ * Return: 0 if OK, -ve on error
*/
int (*get_status)(struct udevice *dev, char *buf, int size);
/**
- * get_last() - get information on the last reset
+ * @get_last: get information on the last reset
*
* @dev: Device to check
- * @return last reset state (enum sysreset_t) or -ve error
+ * Return: last reset state (enum :enum:`sysreset_t`) or -ve error
*/
int (*get_last)(struct udevice *dev);
};
@@ -55,8 +67,9 @@
/**
* sysreset_request() - request a sysreset
*
+ * @dev: Device to be used for system reset
* @type: Reset type to request
- * @return 0 if OK, -EPROTONOSUPPORT if not supported by this device
+ * Return: 0 if OK, -EPROTONOSUPPORT if not supported by this device
*/
int sysreset_request(struct udevice *dev, enum sysreset_t type);
@@ -66,7 +79,7 @@
* @dev: Device to check
* @buf: Buffer to receive the textual reset information
* @size: Size of the passed buffer
- * @return 0 if OK, -ve on error
+ * Return: 0 if OK, -ve on error
*/
int sysreset_get_status(struct udevice *dev, char *buf, int size);
@@ -74,7 +87,7 @@
* sysreset_get_last() - get information on the last reset
*
* @dev: Device to check
- * @return last reset state (enum sysreset_t) or -ve error
+ * Return: last reset state (enum sysreset_t) or -ve error
*/
int sysreset_get_last(struct udevice *dev);
@@ -88,7 +101,7 @@
* If this function fails to reset, it will display a message and halt
*
* @type: Reset type to request
- * @return -EINPROGRESS if a reset is in progress, -ENOSYS if not available
+ * Return: -EINPROGRESS if a reset is in progress, -ENOSYS if not available
*/
int sysreset_walk(enum sysreset_t type);
@@ -101,7 +114,7 @@
*
* If no device prives the information, this function returns -ENOENT
*
- * @return last reset state (enum sysreset_t) or -ve error
+ * Return: last reset state (enum sysreset_t) or -ve error
*/
int sysreset_get_last_walk(void);
@@ -110,6 +123,8 @@
*
* This calls sysreset_walk(). If it returns, indicating that reset is not
* supported, it prints a message and halts.
+ *
+ * @type: Reset type to request
*/
void sysreset_walk_halt(enum sysreset_t type);
diff --git a/include/u-boot/hash-checksum.h b/include/u-boot/hash-checksum.h
index 54e6a73..7f16b37 100644
--- a/include/u-boot/hash-checksum.h
+++ b/include/u-boot/hash-checksum.h
@@ -7,11 +7,12 @@
#define _RSA_CHECKSUM_H
#include <errno.h>
-#include <image.h>
#include <u-boot/sha1.h>
#include <u-boot/sha256.h>
#include <u-boot/sha512.h>
+struct image_region;
+
/**
* hash_calculate() - Calculate hash over the data
*
@@ -23,7 +24,7 @@
* @return 0 if OK, < 0 if error
*/
int hash_calculate(const char *name,
- const struct image_region region[], int region_count,
+ const struct image_region *region, int region_count,
uint8_t *checksum);
#endif
diff --git a/include/lz4.h b/include/u-boot/lz4.h
similarity index 100%
rename from include/lz4.h
rename to include/u-boot/lz4.h
diff --git a/include/u-boot/rsa.h b/include/u-boot/rsa.h
index 89a9c4c..7556aa5 100644
--- a/include/u-boot/rsa.h
+++ b/include/u-boot/rsa.h
@@ -103,11 +103,9 @@
uint8_t *msg, int msg_len,
const uint8_t *hash, int hash_len);
-#ifdef CONFIG_FIT_RSASSA_PSS
int padding_pss_verify(struct image_sign_info *info,
uint8_t *msg, int msg_len,
const uint8_t *hash, int hash_len);
-#endif /* CONFIG_FIT_RSASSA_PSS */
#define RSA_DEFAULT_PADDING_NAME "pkcs-1.5"
diff --git a/include/video.h b/include/video.h
index 8277333..f14fb15 100644
--- a/include/video.h
+++ b/include/video.h
@@ -64,6 +64,13 @@
#define VNBITS(bpix) (1 << (bpix))
+enum video_format {
+ VIDEO_UNKNOWN,
+ VIDEO_X8B8G8R8,
+ VIDEO_X8R8G8B8,
+ VIDEO_X2R10G10B10,
+};
+
/**
* struct video_priv - Device information used by the video uclass
*
@@ -71,6 +78,7 @@
* @ysize: Number of pixels rows (e.g.. 768)
* @rot: Display rotation (0=none, 1=90 degrees clockwise, etc.)
* @bpix: Encoded bits per pixel (enum video_log2_bpp)
+ * @format: Pixel format (enum video_format)
* @vidconsole_drv_name: Driver to use for the text console, NULL to
* select automatically
* @font_size: Font size in pixels (0 to use a default value)
@@ -95,6 +103,7 @@
ushort ysize;
ushort rot;
enum video_log2_bpp bpix;
+ enum video_format format;
const char *vidconsole_drv_name;
int font_size;
diff --git a/lib/Kconfig b/lib/Kconfig
index 034af72..70bf8e7 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -373,7 +373,6 @@
The SHA256 algorithm produces a 256-bit (32-byte) hash value
(digest).
-
config SHA512
bool "Enable SHA512 support"
help
@@ -399,6 +398,66 @@
hashing algorithms. This affects the 'hash' command and also the
hash_lookup_algo() function.
+if SPL
+
+config SPL_SHA1
+ bool "Enable SHA1 support in SPL"
+ default y if SHA1
+ help
+ This option enables support of hashing using SHA1 algorithm.
+ The hash is calculated in software.
+ The SHA1 algorithm produces a 160-bit (20-byte) hash value
+ (digest).
+
+config SPL_SHA256
+ bool "Enable SHA256 support in SPL"
+ default y if SHA256
+ help
+ This option enables support of hashing using SHA256 algorithm.
+ The hash is calculated in software.
+ The SHA256 algorithm produces a 256-bit (32-byte) hash value
+ (digest).
+
+config SPL_SHA512
+ bool "Enable SHA512 support in SPL"
+ default y if SHA512
+ help
+ This option enables support of hashing using SHA512 algorithm.
+ The hash is calculated in software.
+ The SHA512 algorithm produces a 512-bit (64-byte) hash value
+ (digest).
+
+config SPL_SHA384
+ bool "Enable SHA384 support in SPL"
+ default y if SHA384
+ select SPL_SHA512
+ help
+ This option enables support of hashing using SHA384 algorithm.
+ The hash is calculated in software. This is also selects SHA512,
+ because these implementations share the bulk of the code..
+ The SHA384 algorithm produces a 384-bit (48-byte) hash value
+ (digest).
+
+config SPL_SHA_HW_ACCEL
+ bool "Enable hardware acceleration for SHA hash functions"
+ default y if SHA_HW_ACCEL
+ help
+ This option enables hardware acceleration for the SHA1 and SHA256
+ hashing algorithms. This affects the 'hash' command and also the
+ hash_lookup_algo() function.
+
+config SPL_SHA_PROG_HW_ACCEL
+ bool "Enable Progressive hashing support using hardware in SPL"
+ depends on SHA_PROG_HW_ACCEL
+ default y
+ help
+ This option enables hardware-acceleration for SHA progressive
+ hashing.
+ Data can be streamed in a block at a time and the hashing is
+ performed in hardware.
+
+endif
+
if SHA_HW_ACCEL
config SHA512_HW_ACCEL
@@ -437,6 +496,11 @@
security applications, but it can be useful for providing a quick
checksum of a block of data.
+config CRC32
+ def_bool y
+ help
+ Enables CRC32 support in U-Boot. This is normally required.
+
config CRC32C
bool
diff --git a/lib/Makefile b/lib/Makefile
index 962470f..5ddbc77 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -96,9 +96,7 @@
CFLAGS_display_options.o := $(if $(BUILD_TAG),-DBUILD_TAG='"$(BUILD_TAG)"')
obj-$(CONFIG_BCH) += bch.o
obj-$(CONFIG_MMC_SPI) += crc7.o
-#ifndef CONFIG_TPL_BUILD
-obj-y += crc32.o
-#endif
+obj-$(CONFIG_$(SPL_TPL_)CRC32) += crc32.o
obj-$(CONFIG_CRC32C) += crc32c.o
obj-y += ctype.o
obj-y += div64.o
@@ -134,6 +132,7 @@
obj-$(CONFIG_SSCANF) += sscanf.o
endif
+obj-y += abuf.o
obj-y += date.o
obj-y += rtc-lib.o
obj-$(CONFIG_LIB_ELF) += elf.o
diff --git a/lib/abuf.c b/lib/abuf.c
new file mode 100644
index 0000000..4b17e0b
--- /dev/null
+++ b/lib/abuf.c
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Handles a buffer that can be allocated and freed
+ *
+ * Copyright 2021 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <common.h>
+#include <abuf.h>
+#include <malloc.h>
+#include <mapmem.h>
+#include <string.h>
+
+void abuf_set(struct abuf *abuf, void *data, size_t size)
+{
+ abuf_uninit(abuf);
+ abuf->data = data;
+ abuf->size = size;
+}
+
+void abuf_map_sysmem(struct abuf *abuf, ulong addr, size_t size)
+{
+ abuf_set(abuf, map_sysmem(addr, size), size);
+}
+
+bool abuf_realloc(struct abuf *abuf, size_t new_size)
+{
+ void *ptr;
+
+ if (!new_size) {
+ /* easy case, just need to uninit, freeing any allocation */
+ abuf_uninit(abuf);
+ return true;
+ } else if (abuf->alloced) {
+ /* currently allocated, so need to reallocate */
+ ptr = realloc(abuf->data, new_size);
+ if (!ptr)
+ return false;
+ abuf->data = ptr;
+ abuf->size = new_size;
+ return true;
+ } else if (new_size <= abuf->size) {
+ /*
+ * not currently alloced and new size is no larger. Just update
+ * it. Data is lost off the end if new_size < abuf->size
+ */
+ abuf->size = new_size;
+ return true;
+ } else {
+ /* not currently allocated and new size is larger. Alloc and
+ * copy in data. The new space is not inited.
+ */
+ ptr = memdup(abuf->data, new_size);
+ if (!ptr)
+ return false;
+ abuf->data = ptr;
+ abuf->size = new_size;
+ abuf->alloced = true;
+ return true;
+ }
+}
+
+void *abuf_uninit_move(struct abuf *abuf, size_t *sizep)
+{
+ void *ptr;
+
+ if (sizep)
+ *sizep = abuf->size;
+ if (!abuf->size)
+ return NULL;
+ if (abuf->alloced) {
+ ptr = abuf->data;
+ } else {
+ ptr = memdup(abuf->data, abuf->size);
+ if (!ptr)
+ return NULL;
+ }
+ /* Clear everything out so there is no record of the data */
+ abuf_init(abuf);
+
+ return ptr;
+}
+
+void abuf_init_set(struct abuf *abuf, void *data, size_t size)
+{
+ abuf_init(abuf);
+ abuf_set(abuf, data, size);
+}
+
+void abuf_init_move(struct abuf *abuf, void *data, size_t size)
+{
+ abuf_init_set(abuf, data, size);
+ abuf->alloced = true;
+}
+
+void abuf_uninit(struct abuf *abuf)
+{
+ if (abuf->alloced)
+ free(abuf->data);
+ abuf_init(abuf);
+}
+
+void abuf_init(struct abuf *abuf)
+{
+ abuf->data = NULL;
+ abuf->size = 0;
+ abuf->alloced = false;
+}
diff --git a/lib/efi_driver/Makefile b/lib/efi_driver/Makefile
index 83baa1c..f2b6c05 100644
--- a/lib/efi_driver/Makefile
+++ b/lib/efi_driver/Makefile
@@ -6,6 +6,6 @@
# object inclusion implicitly depends on it
obj-y += efi_uclass.o
-ifeq ($(CONFIG_BLK)$(CONFIG_PARTITIONS),yy)
+ifeq ($(CONFIG_PARTITIONS),y)
obj-y += efi_block_device.o
endif
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index 3d5a5cd..06633e9 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -11,6 +11,7 @@
# We need EFI_STUB_32BIT to be set on x86_32 with EFI_STUB
depends on !EFI_STUB || !X86 || X86_64 || EFI_STUB_32BIT
depends on BLK
+ depends on DM_ETH || !NET
default y if !ARM || SYS_CPU = armv7 || SYS_CPU = armv8
select LIB_UUID
select PARTITION_UUIDS
@@ -336,7 +337,7 @@
config EFI_SECURE_BOOT
bool "Enable EFI secure boot support"
- depends on EFI_LOADER
+ depends on EFI_LOADER && FIT_SIGNATURE
select HASH
select SHA256
select RSA
diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c
index cbdb466..c04439d 100644
--- a/lib/efi_loader/efi_device_path.c
+++ b/lib/efi_loader/efi_device_path.c
@@ -46,7 +46,7 @@
.guid = U_BOOT_GUID,
};
-#if defined(CONFIG_DM_MMC) && defined(CONFIG_MMC)
+#if defined(CONFIG_MMC)
/*
* Determine if an MMC device is an SD card.
*
@@ -486,7 +486,6 @@
return p->sub_type == DEVICE_PATH_SUB_TYPE_INSTANCE_END;
}
-#ifdef CONFIG_DM
/* size of device-path not including END node for device and all parents
* up to the root device.
*/
@@ -503,7 +502,6 @@
case UCLASS_ETH:
return dp_size(dev->parent) +
sizeof(struct efi_device_path_mac_addr);
-#ifdef CONFIG_BLK
case UCLASS_BLK:
switch (dev->parent->uclass->uc_drv->id) {
#ifdef CONFIG_IDE
@@ -511,12 +509,12 @@
return dp_size(dev->parent) +
sizeof(struct efi_device_path_atapi);
#endif
-#if defined(CONFIG_SCSI) && defined(CONFIG_DM_SCSI)
+#if defined(CONFIG_SCSI)
case UCLASS_SCSI:
return dp_size(dev->parent) +
sizeof(struct efi_device_path_scsi);
#endif
-#if defined(CONFIG_DM_MMC) && defined(CONFIG_MMC)
+#if defined(CONFIG_MMC)
case UCLASS_MMC:
return dp_size(dev->parent) +
sizeof(struct efi_device_path_sd_mmc_path);
@@ -554,8 +552,7 @@
default:
return dp_size(dev->parent);
}
-#endif
-#if defined(CONFIG_DM_MMC) && defined(CONFIG_MMC)
+#if defined(CONFIG_MMC)
case UCLASS_MMC:
return dp_size(dev->parent) +
sizeof(struct efi_device_path_sd_mmc_path);
@@ -590,7 +587,7 @@
*vdp = ROOT;
return &vdp[1];
}
-#ifdef CONFIG_DM_ETH
+#ifdef CONFIG_NET
case UCLASS_ETH: {
struct efi_device_path_mac_addr *dp =
dp_fill(buf, dev->parent);
@@ -607,7 +604,6 @@
return &dp[1];
}
#endif
-#ifdef CONFIG_BLK
case UCLASS_BLK:
switch (dev->parent->uclass->uc_drv->id) {
#ifdef CONFIG_SANDBOX
@@ -662,7 +658,7 @@
return &dp[1];
}
#endif
-#if defined(CONFIG_SCSI) && defined(CONFIG_DM_SCSI)
+#if defined(CONFIG_SCSI)
case UCLASS_SCSI: {
struct efi_device_path_scsi *dp =
dp_fill(buf, dev->parent);
@@ -676,7 +672,7 @@
return &dp[1];
}
#endif
-#if defined(CONFIG_DM_MMC) && defined(CONFIG_MMC)
+#if defined(CONFIG_MMC)
case UCLASS_MMC: {
struct efi_device_path_sd_mmc_path *sddp =
dp_fill(buf, dev->parent);
@@ -727,8 +723,7 @@
dev->name, dev->parent->uclass->uc_drv->id);
return dp_fill(buf, dev->parent);
}
-#endif
-#if defined(CONFIG_DM_MMC) && defined(CONFIG_MMC)
+#if defined(CONFIG_MMC)
case UCLASS_MMC: {
struct efi_device_path_sd_mmc_path *sddp =
dp_fill(buf, dev->parent);
@@ -770,24 +765,18 @@
return dp_fill(buf, dev->parent);
}
}
-#endif
static unsigned dp_part_size(struct blk_desc *desc, int part)
{
unsigned dpsize;
+ struct udevice *dev;
+ int ret;
-#ifdef CONFIG_BLK
- {
- struct udevice *dev;
- int ret = blk_find_device(desc->if_type, desc->devnum, &dev);
+ ret = blk_find_device(desc->if_type, desc->devnum, &dev);
- if (ret)
- dev = desc->bdev->parent;
- dpsize = dp_size(dev);
- }
-#else
- dpsize = sizeof(ROOT) + sizeof(struct efi_device_path_usb);
-#endif
+ if (ret)
+ dev = desc->bdev->parent;
+ dpsize = dp_size(dev);
if (part == 0) /* the actual disk, not a partition */
return dpsize;
@@ -877,36 +866,14 @@
*/
static void *dp_part_fill(void *buf, struct blk_desc *desc, int part)
{
-#ifdef CONFIG_BLK
- {
- struct udevice *dev;
- int ret = blk_find_device(desc->if_type, desc->devnum, &dev);
+ struct udevice *dev;
+ int ret;
- if (ret)
- dev = desc->bdev->parent;
- buf = dp_fill(buf, dev);
- }
-#else
- /*
- * We *could* make a more accurate path, by looking at if_type
- * and handling all the different cases like we do for non-
- * legacy (i.e. CONFIG_BLK=y) case. But most important thing
- * is just to have a unique device-path for if_type+devnum.
- * So map things to a fictitious USB device.
- */
- struct efi_device_path_usb *udp;
+ ret = blk_find_device(desc->if_type, desc->devnum, &dev);
- memcpy(buf, &ROOT, sizeof(ROOT));
- buf += sizeof(ROOT);
-
- udp = buf;
- udp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
- udp->dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_USB;
- udp->dp.length = sizeof(*udp);
- udp->parent_port_number = desc->if_type;
- udp->usb_interface = desc->devnum;
- buf = &udp[1];
-#endif
+ if (ret)
+ dev = desc->bdev->parent;
+ buf = dp_fill(buf, dev);
if (part == 0) /* the actual disk, not a partition */
return buf;
@@ -1051,39 +1018,18 @@
#ifdef CONFIG_NET
struct efi_device_path *efi_dp_from_eth(void)
{
-#ifndef CONFIG_DM_ETH
- struct efi_device_path_mac_addr *ndp;
-#endif
void *buf, *start;
unsigned dpsize = 0;
assert(eth_get_dev());
-#ifdef CONFIG_DM_ETH
dpsize += dp_size(eth_get_dev());
-#else
- dpsize += sizeof(ROOT);
- dpsize += sizeof(*ndp);
-#endif
start = buf = dp_alloc(dpsize + sizeof(END));
if (!buf)
return NULL;
-#ifdef CONFIG_DM_ETH
buf = dp_fill(buf, eth_get_dev());
-#else
- memcpy(buf, &ROOT, sizeof(ROOT));
- buf += sizeof(ROOT);
-
- ndp = buf;
- ndp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
- ndp->dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_MAC_ADDR;
- ndp->dp.length = sizeof(*ndp);
- ndp->if_type = 1; /* Ethernet */
- memcpy(ndp->mac.addr, eth_get_ethaddr(), ARP_HLEN);
- buf = &ndp[1];
-#endif
*((struct efi_device_path *)buf) = END;
@@ -1263,7 +1209,6 @@
* initrd location
*
* @lo: EFI_LOAD_OPTION containing a valid device path
- * @size: size of the discovered device path
* @guid: guid to search for
*
* Return:
@@ -1272,7 +1217,7 @@
*/
struct
efi_device_path *efi_dp_from_lo(struct efi_load_option *lo,
- efi_uintn_t *size, efi_guid_t guid)
+ const efi_guid_t *guid)
{
struct efi_device_path *fp = lo->file_path;
struct efi_device_path_vendor *vendor;
@@ -1287,8 +1232,8 @@
continue;
vendor = (struct efi_device_path_vendor *)fp;
- if (!guidcmp(&vendor->guid, &guid))
- return efi_dp_dup(fp);
+ if (!guidcmp(&vendor->guid, guid))
+ return efi_dp_dup(efi_dp_next(fp));
}
log_debug("VenMedia(%pUl) not found in %ls\n", &guid, lo->label);
diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
index 988907e..ef8b5c8 100644
--- a/lib/efi_loader/efi_disk.c
+++ b/lib/efi_loader/efi_disk.c
@@ -555,7 +555,6 @@
struct efi_disk_obj *disk;
int disks = 0;
efi_status_t ret;
-#ifdef CONFIG_BLK
struct udevice *dev;
for (uclass_first_device_check(UCLASS_BLK, &dev); dev;
@@ -583,54 +582,7 @@
&disk->header, desc, if_typename,
desc->devnum, dev->name);
}
-#else
- int i, if_type;
- /* Search for all available disk devices */
- for (if_type = 0; if_type < IF_TYPE_COUNT; if_type++) {
- const struct blk_driver *cur_drvr;
- const char *if_typename;
-
- cur_drvr = blk_driver_lookup_type(if_type);
- if (!cur_drvr)
- continue;
-
- if_typename = cur_drvr->if_typename;
- log_info("Scanning disks on %s...\n", if_typename);
- for (i = 0; i < 4; i++) {
- struct blk_desc *desc;
- char devname[32] = { 0 }; /* dp->str is u16[32] long */
-
- desc = blk_get_devnum_by_type(if_type, i);
- if (!desc)
- continue;
- if (desc->type == DEV_TYPE_UNKNOWN)
- continue;
-
- snprintf(devname, sizeof(devname), "%s%d",
- if_typename, i);
-
- /* Add block device for the full device */
- ret = efi_disk_add_dev(NULL, NULL, if_typename, desc,
- i, NULL, 0, &disk);
- if (ret == EFI_NOT_READY) {
- log_notice("Disk %s not ready\n", devname);
- continue;
- }
- if (ret) {
- log_err("ERROR: failure to add disk device %s, r = %lu\n",
- devname, ret & ~EFI_ERROR_MASK);
- return ret;
- }
- disks++;
-
- /* Partitions show up as block devices in EFI */
- disks += efi_disk_create_partitions
- (&disk->header, desc,
- if_typename, i, devname);
- }
- }
-#endif
log_info("Found %d disks\n", disks);
return EFI_SUCCESS;
diff --git a/lib/efi_loader/efi_gop.c b/lib/efi_loader/efi_gop.c
index 1206b2d..7683a34 100644
--- a/lib/efi_loader/efi_gop.c
+++ b/lib/efi_loader/efi_gop.c
@@ -64,6 +64,27 @@
return EFI_EXIT(ret);
}
+static __always_inline struct efi_gop_pixel efi_vid30_to_blt_col(u32 vid)
+{
+ struct efi_gop_pixel blt = {
+ .reserved = 0,
+ };
+
+ blt.blue = (vid & 0x3ff) >> 2;
+ vid >>= 10;
+ blt.green = (vid & 0x3ff) >> 2;
+ vid >>= 10;
+ blt.red = (vid & 0x3ff) >> 2;
+ return blt;
+}
+
+static __always_inline u32 efi_blt_col_to_vid30(struct efi_gop_pixel *blt)
+{
+ return (u32)(blt->red << 2) << 20 |
+ (u32)(blt->green << 2) << 10 |
+ (u32)(blt->blue << 2);
+}
+
static __always_inline struct efi_gop_pixel efi_vid16_to_blt_col(u16 vid)
{
struct efi_gop_pixel blt = {
@@ -191,6 +212,9 @@
if (vid_bpp == 32)
pix = *(struct efi_gop_pixel *)&fb32[
slineoff + j + sx];
+ else if (vid_bpp == 30)
+ pix = efi_vid30_to_blt_col(fb32[
+ slineoff + j + sx]);
else
pix = efi_vid16_to_blt_col(fb16[
slineoff + j + sx]);
@@ -207,6 +231,9 @@
case EFI_BLT_VIDEO_TO_VIDEO:
if (vid_bpp == 32)
fb32[dlineoff + j + dx] = *(u32 *)&pix;
+ else if (vid_bpp == 30)
+ fb32[dlineoff + j + dx] =
+ efi_blt_col_to_vid30(&pix);
else
fb16[dlineoff + j + dx] =
efi_blt_col_to_vid16(&pix);
@@ -231,7 +258,10 @@
#else
case LCD_COLOR32:
#endif
- vid_bpp = 32;
+ if (gopobj->info.pixel_format == EFI_GOT_BGRA8)
+ vid_bpp = 32;
+ else
+ vid_bpp = 30;
break;
#ifdef CONFIG_DM_VIDEO
case VIDEO_BPP16:
@@ -277,6 +307,17 @@
dy, width, height, delta, 16);
}
+static efi_status_t gop_blt_buf_to_vid30(struct efi_gop *this,
+ struct efi_gop_pixel *buffer,
+ u32 foo, efi_uintn_t sx,
+ efi_uintn_t sy, efi_uintn_t dx,
+ efi_uintn_t dy, efi_uintn_t width,
+ efi_uintn_t height, efi_uintn_t delta)
+{
+ return gop_blt_int(this, buffer, EFI_BLT_BUFFER_TO_VIDEO, sx, sy, dx,
+ dy, width, height, delta, 30);
+}
+
static efi_status_t gop_blt_buf_to_vid32(struct efi_gop *this,
struct efi_gop_pixel *buffer,
u32 foo, efi_uintn_t sx,
@@ -394,6 +435,10 @@
ret = gop_blt_buf_to_vid32(this, buffer, operation, sx,
sy, dx, dy, width, height,
delta);
+ else if (vid_bpp == 30)
+ ret = gop_blt_buf_to_vid30(this, buffer, operation, sx,
+ sy, dx, dy, width, height,
+ delta);
else
ret = gop_blt_buf_to_vid16(this, buffer, operation, sx,
sy, dx, dy, width, height,
@@ -432,7 +477,7 @@
efi_status_t efi_gop_register(void)
{
struct efi_gop_obj *gopobj;
- u32 bpix, col, row;
+ u32 bpix, format, col, row;
u64 fb_base, fb_size;
void *fb;
efi_status_t ret;
@@ -449,6 +494,7 @@
priv = dev_get_uclass_priv(vdev);
bpix = priv->bpix;
+ format = priv->format;
col = video_get_xsize(vdev);
row = video_get_ysize(vdev);
fb_base = (uintptr_t)priv->fb;
@@ -458,6 +504,7 @@
int line_len;
bpix = panel_info.vl_bpix;
+ format = VIDEO_UNKNOWN;
col = panel_info.vl_col;
row = panel_info.vl_row;
fb_base = gd->fb_base;
@@ -517,7 +564,15 @@
if (bpix == LCD_COLOR32)
#endif
{
- gopobj->info.pixel_format = EFI_GOT_BGRA8;
+ if (format == VIDEO_X2R10G10B10) {
+ gopobj->info.pixel_format = EFI_GOT_BITMASK;
+ gopobj->info.pixel_bitmask[0] = 0x3ff00000; /* red */
+ gopobj->info.pixel_bitmask[1] = 0x000ffc00; /* green */
+ gopobj->info.pixel_bitmask[2] = 0x000003ff; /* blue */
+ gopobj->info.pixel_bitmask[3] = 0xc0000000; /* reserved */
+ } else {
+ gopobj->info.pixel_format = EFI_GOT_BGRA8;
+ }
} else {
gopobj->info.pixel_format = EFI_GOT_BITMASK;
gopobj->info.pixel_bitmask[0] = 0xf800; /* red */
diff --git a/lib/efi_loader/efi_helper.c b/lib/efi_loader/efi_helper.c
index d03a736..b80a6e0 100644
--- a/lib/efi_loader/efi_helper.c
+++ b/lib/efi_loader/efi_helper.c
@@ -13,6 +13,11 @@
#include <efi_loader.h>
#include <efi_variable.h>
+#if defined(CONFIG_CMD_EFIDEBUG) || defined(CONFIG_EFI_LOAD_FILE2_INITRD)
+/* GUID used by Linux to identify the LoadFile2 protocol with the initrd */
+const efi_guid_t efi_lf2_initrd_guid = EFI_INITRD_MEDIA_GUID;
+#endif
+
/**
* efi_create_current_boot_var() - Return Boot#### name were #### is replaced by
* the value of BootCurrent
@@ -63,10 +68,8 @@
*/
struct efi_device_path *efi_get_dp_from_boot(const efi_guid_t guid)
{
- struct efi_device_path *file_path = NULL;
- struct efi_device_path *tmp = NULL;
struct efi_load_option lo;
- void *var_value = NULL;
+ void *var_value;
efi_uintn_t size;
efi_status_t ret;
u16 var_name[16];
@@ -81,18 +84,11 @@
ret = efi_deserialize_load_option(&lo, var_value, &size);
if (ret != EFI_SUCCESS)
- goto out;
-
- tmp = efi_dp_from_lo(&lo, &size, guid);
- if (!tmp)
- goto out;
+ goto err;
- /* efi_dp_dup will just return NULL if efi_dp_next is NULL */
- file_path = efi_dp_dup(efi_dp_next(tmp));
+ return efi_dp_from_lo(&lo, &guid);
-out:
- efi_free_pool(tmp);
+err:
free(var_value);
-
- return file_path;
+ return NULL;
}
diff --git a/lib/efi_loader/efi_image_loader.c b/lib/efi_loader/efi_image_loader.c
index e9572d4..eb95580 100644
--- a/lib/efi_loader/efi_image_loader.c
+++ b/lib/efi_loader/efi_image_loader.c
@@ -898,9 +898,9 @@
image_base = opt->ImageBase;
efi_set_code_and_data_type(loaded_image_info, opt->Subsystem);
handle->image_type = opt->Subsystem;
- virt_size = ALIGN(virt_size, opt->SectionAlignment);
- efi_reloc = efi_alloc(virt_size,
- loaded_image_info->image_code_type);
+ efi_reloc = efi_alloc_aligned_pages(virt_size,
+ loaded_image_info->image_code_type,
+ opt->SectionAlignment);
if (!efi_reloc) {
log_err("Out of memory\n");
ret = EFI_OUT_OF_RESOURCES;
@@ -914,9 +914,9 @@
image_base = opt->ImageBase;
efi_set_code_and_data_type(loaded_image_info, opt->Subsystem);
handle->image_type = opt->Subsystem;
- virt_size = ALIGN(virt_size, opt->SectionAlignment);
- efi_reloc = efi_alloc(virt_size,
- loaded_image_info->image_code_type);
+ efi_reloc = efi_alloc_aligned_pages(virt_size,
+ loaded_image_info->image_code_type,
+ opt->SectionAlignment);
if (!efi_reloc) {
log_err("Out of memory\n");
ret = EFI_OUT_OF_RESOURCES;
diff --git a/lib/efi_loader/efi_load_initrd.c b/lib/efi_loader/efi_load_initrd.c
index e2a8063..c5e6652 100644
--- a/lib/efi_loader/efi_load_initrd.c
+++ b/lib/efi_loader/efi_load_initrd.c
@@ -52,7 +52,6 @@
*/
static efi_status_t get_initrd_fp(struct efi_device_path **initrd_fp)
{
- const efi_guid_t lf2_initrd_guid = EFI_INITRD_MEDIA_GUID;
struct efi_device_path *dp = NULL;
/*
@@ -65,7 +64,7 @@
* We can then use this specific return value and not install the
* protocol, while allowing the boot to continue
*/
- dp = efi_get_dp_from_boot(lf2_initrd_guid);
+ dp = efi_get_dp_from_boot(efi_lf2_initrd_guid);
if (!dp)
return EFI_INVALID_PARAMETER;
diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
index f4acbee..7f0b507 100644
--- a/lib/efi_loader/efi_memory.c
+++ b/lib/efi_loader/efi_memory.c
@@ -550,6 +550,58 @@
}
/**
+ * efi_alloc_aligned_pages - allocate
+ *
+ * @len: len in bytes
+ * @memory_type: usage type of the allocated memory
+ * @align: alignment in bytes
+ * Return: aligned memory or NULL
+ */
+void *efi_alloc_aligned_pages(u64 len, int memory_type, size_t align)
+{
+ u64 req_pages = efi_size_in_pages(len);
+ u64 true_pages = req_pages + efi_size_in_pages(align) - 1;
+ u64 free_pages;
+ u64 aligned_mem;
+ efi_status_t r;
+ u64 mem;
+
+ /* align must be zero or a power of two */
+ if (align & (align - 1))
+ return NULL;
+
+ /* Check for overflow */
+ if (true_pages < req_pages)
+ return NULL;
+
+ if (align < EFI_PAGE_SIZE) {
+ r = efi_allocate_pages(EFI_ALLOCATE_ANY_PAGES, memory_type,
+ req_pages, &mem);
+ return (r == EFI_SUCCESS) ? (void *)(uintptr_t)mem : NULL;
+ }
+
+ r = efi_allocate_pages(EFI_ALLOCATE_ANY_PAGES, memory_type,
+ true_pages, &mem);
+ if (r != EFI_SUCCESS)
+ return NULL;
+
+ aligned_mem = ALIGN(mem, align);
+ /* Free pages before alignment */
+ free_pages = efi_size_in_pages(aligned_mem - mem);
+ if (free_pages)
+ efi_free_pages(mem, free_pages);
+
+ /* Free trailing pages */
+ free_pages = true_pages - (req_pages + free_pages);
+ if (free_pages) {
+ mem = aligned_mem + req_pages * EFI_PAGE_SIZE;
+ efi_free_pages(mem, free_pages);
+ }
+
+ return (void *)(uintptr_t)aligned_mem;
+}
+
+/**
* efi_allocate_pool - allocate memory from pool
*
* @pool_type: type of the pool from which memory is to be allocated
diff --git a/lib/efi_loader/efi_var_file.c b/lib/efi_loader/efi_var_file.c
index c7c6805..76a2ff9 100644
--- a/lib/efi_loader/efi_var_file.c
+++ b/lib/efi_loader/efi_var_file.c
@@ -19,6 +19,13 @@
#define PART_STR_LEN 10
+/* GUID used by Shim to store the MOK database */
+#define SHIM_LOCK_GUID \
+ EFI_GUID(0x605dab50, 0xe046, 0x4300, \
+ 0xab, 0xb6, 0x3d, 0xd8, 0x10, 0xdd, 0x8b, 0x23)
+
+static const efi_guid_t shim_lock_guid = SHIM_LOCK_GUID;
+
/**
* efi_set_blk_dev_to_system_partition() - select EFI system partition
*
@@ -175,6 +182,7 @@
if (!safe &&
(efi_auth_var_get_type(var->name, &var->guid) !=
EFI_AUTH_VAR_NONE ||
+ !guidcmp(&var->guid, &shim_lock_guid) ||
!(var->attr & EFI_VARIABLE_NON_VOLATILE)))
continue;
if (!var->length)
diff --git a/lib/efi_selftest/efi_selftest_snp.c b/lib/efi_selftest/efi_selftest_snp.c
index 79f0467..818cbfc 100644
--- a/lib/efi_selftest/efi_selftest_snp.c
+++ b/lib/efi_selftest/efi_selftest_snp.c
@@ -309,6 +309,18 @@
return EFI_ST_FAILURE;
}
+ /* Check media connected */
+ ret = net->get_status(net, NULL, NULL);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to get status");
+ return EFI_ST_FAILURE;
+ }
+ if (net->mode && net->mode->media_present_supported &&
+ !net->mode->media_present) {
+ efi_st_error("Network media is not connected");
+ return EFI_ST_FAILURE;
+ }
+
/*
* Send DHCP discover message
*/
@@ -328,8 +340,6 @@
events[0] = timer;
events[1] = net->wait_for_packet;
for (;;) {
- u32 int_status;
-
/*
* Wait for packet to be received or timer event.
*/
@@ -352,48 +362,46 @@
continue;
}
/*
- * Receive packet
+ * Receive packets until buffer is empty
*/
- buffer_size = sizeof(buffer);
- ret = net->get_status(net, &int_status, NULL);
- if (ret != EFI_SUCCESS) {
- efi_st_error("Failed to get status");
- return EFI_ST_FAILURE;
- }
- if (!(int_status & EFI_SIMPLE_NETWORK_RECEIVE_INTERRUPT)) {
- efi_st_error("RX interrupt not set");
- return EFI_ST_FAILURE;
- }
- ret = net->receive(net, NULL, &buffer_size, &buffer,
- &srcaddr, &destaddr, NULL);
- if (ret != EFI_SUCCESS) {
- efi_st_error("Failed to receive packet");
- return EFI_ST_FAILURE;
+ for (;;) {
+ buffer_size = sizeof(buffer);
+ ret = net->receive(net, NULL, &buffer_size, &buffer,
+ &srcaddr, &destaddr, NULL);
+ if (ret == EFI_NOT_READY) {
+ /* The received buffer is empty. */
+ break;
+ }
+
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to receive packet");
+ return EFI_ST_FAILURE;
+ }
+ /*
+ * Check the packet is meant for this system.
+ * Unfortunately QEMU ignores the broadcast flag.
+ * So we have to check for broadcasts too.
+ */
+ if (memcmp(&destaddr, &net->mode->current_address, ARP_HLEN) &&
+ memcmp(&destaddr, BROADCAST_MAC, ARP_HLEN))
+ continue;
+ /*
+ * Check this is a DHCP reply
+ */
+ if (buffer.p.eth_hdr.et_protlen != ntohs(PROT_IP) ||
+ buffer.p.ip_udp.ip_hl_v != 0x45 ||
+ buffer.p.ip_udp.ip_p != IPPROTO_UDP ||
+ buffer.p.ip_udp.udp_src != ntohs(67) ||
+ buffer.p.ip_udp.udp_dst != ntohs(68) ||
+ buffer.p.dhcp_hdr.op != BOOTREPLY)
+ continue;
+ /*
+ * We successfully received a DHCP reply.
+ */
+ goto received;
}
- /*
- * Check the packet is meant for this system.
- * Unfortunately QEMU ignores the broadcast flag.
- * So we have to check for broadcasts too.
- */
- if (memcmp(&destaddr, &net->mode->current_address, ARP_HLEN) &&
- memcmp(&destaddr, BROADCAST_MAC, ARP_HLEN))
- continue;
- /*
- * Check this is a DHCP reply
- */
- if (buffer.p.eth_hdr.et_protlen != ntohs(PROT_IP) ||
- buffer.p.ip_udp.ip_hl_v != 0x45 ||
- buffer.p.ip_udp.ip_p != IPPROTO_UDP ||
- buffer.p.ip_udp.udp_src != ntohs(67) ||
- buffer.p.ip_udp.udp_dst != ntohs(68) ||
- buffer.p.dhcp_hdr.op != BOOTREPLY)
- continue;
- /*
- * We successfully received a DHCP reply.
- */
- break;
}
-
+received:
/*
* Write a log message.
*/
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index af92e65..959b337 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1293,7 +1293,8 @@
int fdtdec_add_reserved_memory(void *blob, const char *basename,
const struct fdt_memory *carveout,
- uint32_t *phandlep, bool no_map)
+ const char **compatibles, unsigned int count,
+ uint32_t *phandlep, unsigned long flags)
{
fdt32_t cells[4] = {}, *ptr = cells;
uint32_t upper, lower, phandle;
@@ -1363,6 +1364,12 @@
if (node < 0)
return node;
+ if (flags & FDTDEC_RESERVED_MEMORY_NO_MAP) {
+ err = fdt_setprop(blob, node, "no-map", NULL, 0);
+ if (err < 0)
+ return err;
+ }
+
if (phandlep) {
err = fdt_generate_phandle(blob, &phandle);
if (err < 0)
@@ -1393,8 +1400,24 @@
if (err < 0)
return err;
- if (no_map) {
- err = fdt_setprop(blob, node, "no-map", NULL, 0);
+ if (compatibles && count > 0) {
+ size_t length = 0, len = 0;
+ unsigned int i;
+ char *buffer;
+
+ for (i = 0; i < count; i++)
+ length += strlen(compatibles[i]) + 1;
+
+ buffer = malloc(length);
+ if (!buffer)
+ return -FDT_ERR_INTERNAL;
+
+ for (i = 0; i < count; i++)
+ len += strlcpy(buffer + len, compatibles[i],
+ length - len) + 1;
+
+ err = fdt_setprop(blob, node, "compatible", buffer, length);
+ free(buffer);
if (err < 0)
return err;
}
@@ -1406,8 +1429,11 @@
return 0;
}
-int fdtdec_get_carveout(const void *blob, const char *node, const char *name,
- unsigned int index, struct fdt_memory *carveout)
+int fdtdec_get_carveout(const void *blob, const char *node,
+ const char *prop_name, unsigned int index,
+ struct fdt_memory *carveout, const char **name,
+ const char ***compatiblesp, unsigned int *countp,
+ unsigned long *flags)
{
const fdt32_t *prop;
uint32_t phandle;
@@ -1418,9 +1444,9 @@
if (offset < 0)
return offset;
- prop = fdt_getprop(blob, offset, name, &len);
+ prop = fdt_getprop(blob, offset, prop_name, &len);
if (!prop) {
- debug("failed to get %s for %s\n", name, node);
+ debug("failed to get %s for %s\n", prop_name, node);
return -FDT_ERR_NOTFOUND;
}
@@ -1431,7 +1457,7 @@
if (len < (sizeof(phandle) * (index + 1))) {
debug("invalid phandle index\n");
- return -FDT_ERR_BADPHANDLE;
+ return -FDT_ERR_NOTFOUND;
}
phandle = fdt32_to_cpu(prop[index]);
@@ -1442,6 +1468,48 @@
return offset;
}
+ if (name)
+ *name = fdt_get_name(blob, offset, NULL);
+
+ if (compatiblesp) {
+ const char **compatibles = NULL;
+ const char *start, *end, *ptr;
+ unsigned int count = 0;
+
+ prop = fdt_getprop(blob, offset, "compatible", &len);
+ if (!prop)
+ goto skip_compat;
+
+ start = ptr = (const char *)prop;
+ end = start + len;
+
+ while (ptr < end) {
+ ptr = strchrnul(ptr, '\0');
+ count++;
+ ptr++;
+ }
+
+ compatibles = malloc(sizeof(ptr) * count);
+ if (!compatibles)
+ return -FDT_ERR_INTERNAL;
+
+ ptr = start;
+ count = 0;
+
+ while (ptr < end) {
+ compatibles[count] = ptr;
+ ptr = strchrnul(ptr, '\0');
+ count++;
+ ptr++;
+ }
+
+skip_compat:
+ *compatiblesp = compatibles;
+
+ if (countp)
+ *countp = count;
+ }
+
carveout->start = fdtdec_get_addr_size_auto_noparent(blob, offset,
"reg", 0, &size,
true);
@@ -1452,19 +1520,28 @@
carveout->end = carveout->start + size - 1;
+ if (flags) {
+ *flags = 0;
+
+ if (fdtdec_get_bool(blob, offset, "no-map"))
+ *flags |= FDTDEC_RESERVED_MEMORY_NO_MAP;
+ }
+
return 0;
}
int fdtdec_set_carveout(void *blob, const char *node, const char *prop_name,
- unsigned int index, const char *name,
- const struct fdt_memory *carveout)
+ unsigned int index, const struct fdt_memory *carveout,
+ const char *name, const char **compatibles,
+ unsigned int count, unsigned long flags)
{
uint32_t phandle;
int err, offset, len;
fdt32_t value;
void *prop;
- err = fdtdec_add_reserved_memory(blob, name, carveout, &phandle, false);
+ err = fdtdec_add_reserved_memory(blob, name, carveout, compatibles,
+ count, &phandle, flags);
if (err < 0) {
debug("failed to add reserved memory: %d\n", err);
return err;
@@ -1536,8 +1613,6 @@
puts("Failed to read control FDT\n");
return -1;
}
-# elif defined(CONFIG_OF_PRIOR_STAGE)
- gd->fdt_blob = (void *)(uintptr_t)prior_stage_fdt_address;
# endif
# ifndef CONFIG_SPL_BUILD
/* Allow the early environment to override the fdt address */
diff --git a/lib/fdtdec_test.c b/lib/fdtdec_test.c
index e0c6e09..85351c7 100644
--- a/lib/fdtdec_test.c
+++ b/lib/fdtdec_test.c
@@ -189,8 +189,8 @@
offset = CHECK(fdt_add_subnode(fdt, 0, name + 1));
CHECK(fdt_setprop(fdt, offset, "reg", cells, (na + ns) * sizeof(*cells)));
- return fdtdec_set_carveout(fdt, name, "memory-region", 0,
- "framebuffer", &carveout);
+ return fdtdec_set_carveout(fdt, name, "memory-region", 0, &carveout,
+ "framebuffer", NULL, 0, 0);
}
static int check_fdt_carveout(void *fdt, uint32_t address_cells,
@@ -214,7 +214,8 @@
printf("carveout: %pap-%pap na=%u ns=%u: ", &expected.start,
&expected.end, address_cells, size_cells);
- CHECK(fdtdec_get_carveout(fdt, name, "memory-region", 0, &carveout));
+ CHECK(fdtdec_get_carveout(fdt, name, "memory-region", 0, &carveout,
+ NULL, NULL, NULL, NULL));
if ((carveout.start != expected.start) ||
(carveout.end != expected.end)) {
diff --git a/lib/gunzip.c b/lib/gunzip.c
index bee3b92..a8e498d 100644
--- a/lib/gunzip.c
+++ b/lib/gunzip.c
@@ -84,32 +84,32 @@
#ifdef CONFIG_CMD_UNZIP
__weak
-void gzwrite_progress_init(u64 expectedsize)
+void gzwrite_progress_init(ulong expectedsize)
{
putc('\n');
}
__weak
void gzwrite_progress(int iteration,
- u64 bytes_written,
- u64 total_bytes)
+ ulong bytes_written,
+ ulong total_bytes)
{
if (0 == (iteration & 3))
- printf("%llu/%llu\r", bytes_written, total_bytes);
+ printf("%lu/%lu\r", bytes_written, total_bytes);
}
__weak
void gzwrite_progress_finish(int returnval,
- u64 bytes_written,
- u64 total_bytes,
+ ulong bytes_written,
+ ulong total_bytes,
u32 expected_crc,
u32 calculated_crc)
{
if (0 == returnval) {
- printf("\n\t%llu bytes, crc 0x%08x\n",
+ printf("\n\t%lu bytes, crc 0x%08x\n",
total_bytes, calculated_crc);
} else {
- printf("\n\tuncompressed %llu of %llu\n"
+ printf("\n\tuncompressed %lu of %lu\n"
"\tcrcs == 0x%08x/0x%08x\n",
bytes_written, total_bytes,
expected_crc, calculated_crc);
@@ -119,15 +119,15 @@
int gzwrite(unsigned char *src, int len,
struct blk_desc *dev,
unsigned long szwritebuf,
- u64 startoffs,
- u64 szexpected)
+ ulong startoffs,
+ ulong szexpected)
{
int i, flags;
z_stream s;
int r = 0;
unsigned char *writebuf;
unsigned crc = 0;
- u64 totalfilled = 0;
+ ulong totalfilled = 0;
lbaint_t blksperbuf, outblock;
u32 expected_crc;
u32 payload_size;
@@ -142,7 +142,7 @@
}
if (startoffs & (dev->blksz-1)) {
- printf("%s: start offset %llu not a multiple of %lu\n",
+ printf("%s: start offset %lu not a multiple of %lu\n",
__func__, startoffs, dev->blksz);
return -1;
}
@@ -182,12 +182,12 @@
if (szexpected == 0) {
szexpected = le32_to_cpu(szuncompressed);
} else if (szuncompressed != (u32)szexpected) {
- printf("size of %llx doesn't match trailer low bits %x\n",
+ printf("size of %lx doesn't match trailer low bits %x\n",
szexpected, szuncompressed);
return -1;
}
if (lldiv(szexpected, dev->blksz) > (dev->lba - outblock)) {
- printf("%s: uncompressed size %llu exceeds device size\n",
+ printf("%s: uncompressed size %lu exceeds device size\n",
__func__, szexpected);
return -1;
}
diff --git a/lib/hash-checksum.c b/lib/hash-checksum.c
index d732ecc..8f2a42f 100644
--- a/lib/hash-checksum.c
+++ b/lib/hash-checksum.c
@@ -17,7 +17,7 @@
#include <image.h>
int hash_calculate(const char *name,
- const struct image_region region[],
+ const struct image_region *region,
int region_count, uint8_t *checksum)
{
struct hash_algo *algo;
diff --git a/lib/lmb.c b/lib/lmb.c
index 7936477..676b3a0 100644
--- a/lib/lmb.c
+++ b/lib/lmb.c
@@ -153,7 +153,7 @@
arch_lmb_reserve(lmb);
board_lmb_reserve(lmb);
- if (IMAGE_ENABLE_OF_LIBFDT && fdt_blob)
+ if (CONFIG_IS_ENABLED(OF_LIBFDT) && fdt_blob)
boot_fdt_add_mem_rsv_regions(lmb, fdt_blob);
}
diff --git a/lib/lz4_wrapper.c b/lib/lz4_wrapper.c
index cdbcd05..ebcb5c0 100644
--- a/lib/lz4_wrapper.c
+++ b/lib/lz4_wrapper.c
@@ -6,10 +6,10 @@
#include <common.h>
#include <compiler.h>
#include <image.h>
-#include <lz4.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <asm/unaligned.h>
+#include <u-boot/lz4.h>
static u16 LZ4_readLE16(const void *src)
{
diff --git a/lib/optee/optee.c b/lib/optee/optee.c
index 766d0d9..b036224 100644
--- a/lib/optee/optee.c
+++ b/lib/optee/optee.c
@@ -161,6 +161,7 @@
.start = res.start,
.end = res.end,
};
+ unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
char *oldname, *nodename, *tmp;
oldname = strdup(name);
@@ -177,7 +178,8 @@
ret = fdtdec_add_reserved_memory(new_blob,
nodename,
&carveout,
- NULL, true);
+ NULL, 0,
+ NULL, flags);
free(oldname);
if (ret < 0)
diff --git a/lib/rsa/Kconfig b/lib/rsa/Kconfig
index cf802a6..469596a 100644
--- a/lib/rsa/Kconfig
+++ b/lib/rsa/Kconfig
@@ -1,6 +1,6 @@
config RSA
bool "Use RSA Library"
- select RSA_FREESCALE_EXP if FSL_CAAM && !ARCH_MX7 && !ARCH_MX6 && !ARCH_MX5
+ select RSA_FREESCALE_EXP if FSL_CAAM && !ARCH_MX7 && !ARCH_MX7ULP && !ARCH_MX6 && !ARCH_MX5
select RSA_SOFTWARE_EXP if !RSA_FREESCALE_EXP
help
RSA support. This enables the RSA algorithm used for FIT image
@@ -57,7 +57,7 @@
config RSA_FREESCALE_EXP
bool "Enable RSA Modular Exponentiation with FSL crypto accelerator"
- depends on DM && FSL_CAAM && !ARCH_MX7 && !ARCH_MX6 && !ARCH_MX5
+ depends on DM && FSL_CAAM && !ARCH_MX7 && !ARCH_MX7ULP && !ARCH_MX6 && !ARCH_MX5
help
Enables driver for RSA modular exponentiation using Freescale cryptographic
accelerator - CAAM.
diff --git a/lib/rsa/rsa-sign.c b/lib/rsa/rsa-sign.c
index c27a784..0579e52 100644
--- a/lib/rsa/rsa-sign.c
+++ b/lib/rsa/rsa-sign.c
@@ -401,15 +401,14 @@
goto err_sign;
}
-#ifdef CONFIG_FIT_RSASSA_PSS
- if (padding_algo && !strcmp(padding_algo->name, "pss")) {
+ if (CONFIG_IS_ENABLED(FIT_RSASSA_PSS) && padding_algo &&
+ !strcmp(padding_algo->name, "pss")) {
if (EVP_PKEY_CTX_set_rsa_padding(ckey,
RSA_PKCS1_PSS_PADDING) <= 0) {
ret = rsa_err("Signer padding setup failed");
goto err_sign;
}
}
-#endif /* CONFIG_FIT_RSASSA_PSS */
for (i = 0; i < region_count; i++) {
if (!EVP_DigestSignUpdate(context, region[i].data,
diff --git a/lib/rsa/rsa-verify.c b/lib/rsa/rsa-verify.c
index ad6d33d..600c93a 100644
--- a/lib/rsa/rsa-verify.c
+++ b/lib/rsa/rsa-verify.c
@@ -102,7 +102,7 @@
};
#endif
-#ifdef CONFIG_FIT_RSASSA_PSS
+#if CONFIG_IS_ENABLED(FIT_RSASSA_PSS)
static void u32_i2osp(uint32_t val, uint8_t *buf)
{
buf[0] = (uint8_t)((val >> 24) & 0xff);
@@ -313,7 +313,6 @@
#endif
-#if CONFIG_IS_ENABLED(FIT_SIGNATURE) || CONFIG_IS_ENABLED(RSA_VERIFY_WITH_PKEY)
/**
* rsa_verify_key() - Verify a signature against some data using RSA Key
*
@@ -385,9 +384,7 @@
return 0;
}
-#endif
-#if CONFIG_IS_ENABLED(RSA_VERIFY_WITH_PKEY)
/**
* rsa_verify_with_pkey() - Verify a signature against some data using
* only modulus and exponent as RSA key properties.
@@ -408,6 +405,9 @@
struct key_prop *prop;
int ret;
+ if (!CONFIG_IS_ENABLED(RSA_VERIFY_WITH_PKEY))
+ return -EACCES;
+
/* Public key is self-described to fill key_prop */
ret = rsa_gen_key_prop(info->key, info->keylen, &prop);
if (ret) {
@@ -422,13 +422,6 @@
return ret;
}
-#else
-int rsa_verify_with_pkey(struct image_sign_info *info,
- const void *hash, uint8_t *sig, uint sig_len)
-{
- return -EACCES;
-}
-#endif
#if CONFIG_IS_ENABLED(FIT_SIGNATURE)
/**
diff --git a/lib/string.c b/lib/string.c
index ba176fb..78bd65c 100644
--- a/lib/string.c
+++ b/lib/string.c
@@ -659,6 +659,19 @@
}
#endif
+char *memdup(const void *src, size_t len)
+{
+ char *p;
+
+ p = malloc(len);
+ if (!p)
+ return NULL;
+
+ memcpy(p, src, len);
+
+ return p;
+}
+
#ifndef __HAVE_ARCH_STRSTR
/**
* strstr - Find the first substring in a %NUL terminated string
diff --git a/lib/zstd/Makefile b/lib/zstd/Makefile
index 33c1df4..1217089 100644
--- a/lib/zstd/Makefile
+++ b/lib/zstd/Makefile
@@ -1,4 +1,4 @@
obj-y += zstd_decompress.o
zstd_decompress-y := huf_decompress.o decompress.o \
- entropy_common.o fse_decompress.o zstd_common.o
+ entropy_common.o fse_decompress.o zstd_common.o zstd.o
diff --git a/lib/zstd/zstd.c b/lib/zstd/zstd.c
new file mode 100644
index 0000000..bf9cd19
--- /dev/null
+++ b/lib/zstd/zstd.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Google LLC
+ */
+
+#define LOG_CATEGORY LOGC_BOOT
+
+#include <common.h>
+#include <abuf.h>
+#include <log.h>
+#include <malloc.h>
+#include <linux/zstd.h>
+
+int zstd_decompress(struct abuf *in, struct abuf *out)
+{
+ ZSTD_DStream *dstream;
+ ZSTD_inBuffer in_buf;
+ ZSTD_outBuffer out_buf;
+ void *workspace;
+ size_t wsize;
+ int ret;
+
+ wsize = ZSTD_DStreamWorkspaceBound(abuf_size(in));
+ workspace = malloc(wsize);
+ if (!workspace) {
+ debug("%s: cannot allocate workspace of size %zu\n", __func__,
+ wsize);
+ return -ENOMEM;
+ }
+
+ dstream = ZSTD_initDStream(abuf_size(in), workspace, wsize);
+ if (!dstream) {
+ log_err("%s: ZSTD_initDStream failed\n", __func__);
+ ret = -EPERM;
+ goto do_free;
+ }
+
+ in_buf.src = abuf_data(in);
+ in_buf.pos = 0;
+ in_buf.size = abuf_size(in);
+
+ out_buf.dst = abuf_data(out);
+ out_buf.pos = 0;
+ out_buf.size = abuf_size(out);
+
+ while (1) {
+ size_t res;
+
+ res = ZSTD_decompressStream(dstream, &out_buf, &in_buf);
+ if (ZSTD_isError(res)) {
+ ret = ZSTD_getErrorCode(res);
+ log_err("ZSTD_decompressStream error %d\n", ret);
+ goto do_free;
+ }
+
+ if (in_buf.pos >= abuf_size(in) || !res)
+ break;
+ }
+
+ ret = out_buf.pos;
+do_free:
+ free(workspace);
+ return ret;
+}
diff --git a/scripts/Kbuild.include b/scripts/Kbuild.include
index a745cc4..09506cb 100644
--- a/scripts/Kbuild.include
+++ b/scripts/Kbuild.include
@@ -148,6 +148,7 @@
# added for U-Boot
binutils-version = $(shell $(CONFIG_SHELL) $(srctree)/scripts/binutils-version.sh $(AS))
+dtc-version = $(shell $(CONFIG_SHELL) $(srctree)/scripts/dtc-version.sh $(DTC))
# cc-ldoption
# Usage: ldflags += $(call cc-ldoption, -Wl$(comma)--hash-style=both)
diff --git a/scripts/Makefile b/scripts/Makefile
index e7b353f..cfe9fef 100644
--- a/scripts/Makefile
+++ b/scripts/Makefile
@@ -10,4 +10,3 @@
# Let clean descend into subdirs
subdir- += basic kconfig
-subdir-$(CONFIG_DTC) += dtc
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 07696e8..39f0339 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -403,7 +403,7 @@
quiet_cmd_efi_ld = LD $@
cmd_efi_ld = $(LD) -nostdlib -znocombreloc -T $(EFI_LDS_PATH) -shared \
- -Bsymbolic -s $^ -o $@
+ -Bsymbolic -znorelro -s $^ -o $@
EFI_LDS_PATH = $(srctree)/arch/$(ARCH)/lib/$(EFI_LDS)
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 02d86d7..022a272 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -71,10 +71,8 @@
CONFIG_BOARD_NAME
CONFIG_BOARD_POSTCLK_INIT
CONFIG_BOARD_SIZE_LIMIT
-CONFIG_BOOGER
CONFIG_BOOTFILE
CONFIG_BOOTMODE
-CONFIG_BOOTP_
CONFIG_BOOTP_BOOTFILESIZE
CONFIG_BOOTP_DHCP_REQUEST_DELAY
CONFIG_BOOTP_ID_CACHE_SIZE
@@ -140,12 +138,10 @@
CONFIG_CM_SPD_DETECT
CONFIG_CM_TCRAM
CONFIG_COLDFIRE
-CONFIG_COMMANDS
CONFIG_COMMON_BOOT
CONFIG_COMPAT
CONFIG_CONS_EXTC_PINSEL
CONFIG_CONS_EXTC_RATE
-CONFIG_CONS_NONE
CONFIG_CONS_ON_SCC
CONFIG_CONS_SCIF0
CONFIG_CONS_SCIF1
@@ -220,7 +216,6 @@
CONFIG_DP_DDR_CTRL
CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR
CONFIG_DP_DDR_NUM_CTRLS
-CONFIG_DRAM_TIMINGS_
CONFIG_DRIVER_DM9000
CONFIG_DSP_CLUSTER_START
CONFIG_DWCDDR21MCTL
@@ -246,7 +241,6 @@
CONFIG_EFLASH_PROTSECTORS
CONFIG_EHCI_DESC_BIG_ENDIAN
CONFIG_EHCI_HCD_INIT_AFTER_RESET
-CONFIG_EHCI_IS_TDI
CONFIG_EHCI_MMIO_BIG_ENDIAN
CONFIG_EHCI_MXS_PORT0
CONFIG_EHCI_MXS_PORT1
@@ -260,7 +254,6 @@
CONFIG_ENV_FLAGS_LIST_DEFAULT
CONFIG_ENV_FLAGS_LIST_STATIC
CONFIG_ENV_IS_EMBEDDED
-CONFIG_ENV_IS_IN_
CONFIG_ENV_MAX_ENTRIES
CONFIG_ENV_MIN_ENTRIES
CONFIG_ENV_OFFSET_OOB
@@ -450,7 +443,6 @@
CONFIG_HITACHI_SX14
CONFIG_HOSTNAME
CONFIG_HOST_MAX_DEVICES
-CONFIG_HOTPLUG
CONFIG_HPS_ALTERAGRP_DBGATCLK
CONFIG_HPS_ALTERAGRP_MAINCLK
CONFIG_HPS_ALTERAGRP_MPUCLK
@@ -601,7 +593,6 @@
CONFIG_I2C_GSC
CONFIG_I2C_MBB_TIMEOUT
CONFIG_I2C_MULTI_BUS
-CONFIG_I2C_MV
CONFIG_I2C_MVTWSI
CONFIG_I2C_MVTWSI_BASE
CONFIG_I2C_MVTWSI_BASE0
@@ -624,7 +615,6 @@
CONFIG_IMX_HDMI
CONFIG_IMX_VIDEO_SKIP
CONFIG_INETSPACE_V2
-CONFIG_INIT_IGNORE_ERROR
CONFIG_INI_ALLOW_MULTILINE
CONFIG_INI_CASE_INSENSITIVE
CONFIG_INI_MAX_LINE
@@ -818,7 +808,6 @@
CONFIG_MTD_UBI_GLUEBI
CONFIG_MTD_UBI_MODULE
CONFIG_MULTI_CS
-CONFIG_MUSB_HOST
CONFIG_MVGBE_PORTS
CONFIG_MVMFP_V2
CONFIG_MVS
@@ -880,7 +869,6 @@
CONFIG_NORBOOT
CONFIG_NORFLASH_PS32BIT
CONFIG_NO_ETH
-CONFIG_NO_RELOCATION
CONFIG_NO_WAIT
CONFIG_NS16550_MIN_FUNCTIONS
CONFIG_NS8382X
@@ -888,7 +876,6 @@
CONFIG_NUM_PAMU
CONFIG_ODROID_REV_AIN
CONFIG_OFF_PADCONF
-CONFIG_OF_
CONFIG_ORIGEN
CONFIG_OTHBOOTARGS
CONFIG_OVERWRITE_ETHADDR_ONCE
@@ -1009,10 +996,6 @@
CONFIG_REALMODE_DEBUG
CONFIG_RED_LED
CONFIG_REG
-CONFIG_REG_0
-CONFIG_REG_2
-CONFIG_REG_3
-CONFIG_REG_8
CONFIG_REMAKE_ELF
CONFIG_REQ
CONFIG_RESERVED_01_BASE
@@ -1150,8 +1133,6 @@
CONFIG_SMSTP9_ENA
CONFIG_SOCRATES
CONFIG_SOC_OMAP3430
-CONFIG_SOFT_I2C_GPIO_SCL
-CONFIG_SOFT_I2C_GPIO_SDA
CONFIG_SOFT_I2C_READ_REPEATED_START
CONFIG_SPD_EEPROM
CONFIG_SPIFLASH
@@ -1163,7 +1144,6 @@
CONFIG_SPI_HALF_DUPLEX
CONFIG_SPI_IDLE_VAL
CONFIG_SPI_N25Q256A_RESET
-CONFIG_SPL_
CONFIG_SPL_ATMEL_SIZE
CONFIG_SPL_BOARD_LOAD_IMAGE
CONFIG_SPL_BOOTROM_SAVE
@@ -1231,10 +1211,6 @@
CONFIG_STANDALONE_LOAD_ADDR
CONFIG_STATIC_BOARD_REV
CONFIG_STD_DEVICES_SETTINGS
-CONFIG_STM32_FLASH
-CONFIG_STV0991
-CONFIG_STV0991_HZ
-CONFIG_STV0991_HZ_CLOCK
CONFIG_SXNI855T
CONFIG_SYSFS
CONFIG_SYSMGR_ISWGRP_HANDOFF
@@ -1656,7 +1632,6 @@
CONFIG_SYS_FLASH1_BASE_PHYS
CONFIG_SYS_FLASH1_BASE_PHYS_EARLY
CONFIG_SYS_FLASHBOOT
-CONFIG_SYS_FLASH_AMD_CHECK_DQ7
CONFIG_SYS_FLASH_AUTOPROTECT_LIST
CONFIG_SYS_FLASH_BANKS_LIST
CONFIG_SYS_FLASH_BANKS_SIZES
@@ -2264,7 +2239,6 @@
CONFIG_SYS_MMC_U_BOOT_OFFS
CONFIG_SYS_MMC_U_BOOT_SIZE
CONFIG_SYS_MMC_U_BOOT_START
-CONFIG_SYS_MONITOR_
CONFIG_SYS_MONITOR_BASE
CONFIG_SYS_MONITOR_LEN
CONFIG_SYS_MONITOR_SEC
@@ -3036,8 +3010,6 @@
CONFIG_USB_EHCI_BASE_LIST
CONFIG_USB_EHCI_EXYNOS
CONFIG_USB_EHCI_FARADAY
-CONFIG_USB_EHCI_KIRKWOOD
-CONFIG_USB_EHCI_MXS
CONFIG_USB_EHCI_TXFIFO_THRESH
CONFIG_USB_ETH_QMULT
CONFIG_USB_ETH_SUBSET
@@ -3075,7 +3047,6 @@
CONFIG_USB_TUSB_OMAP_DMA
CONFIG_USB_ULPI_TIMEOUT
CONFIG_USB_XHCI_EXYNOS
-CONFIG_USER_LOWLEVEL_INIT
CONFIG_USE_INTERRUPT
CONFIG_USE_ONENAND_BOARD_INIT
CONFIG_UTBIPAR_INIT_TBIPA
@@ -3088,9 +3059,7 @@
CONFIG_VIDEO_BMP_LOGO
CONFIG_VIDEO_DA8XX
CONFIG_VIDEO_FONT_4X6
-CONFIG_VIDEO_LCD_I2C_BUS
CONFIG_VIDEO_LOGO
-CONFIG_VIDEO_MXS
CONFIG_VIDEO_MXS_MODE_SYSTEM
CONFIG_VIDEO_STD_TIMINGS
CONFIG_VID_FLS_ENV
diff --git a/scripts/dtc-version.sh b/scripts/dtc-version.sh
new file mode 100755
index 0000000..bfb514e
--- /dev/null
+++ b/scripts/dtc-version.sh
@@ -0,0 +1,27 @@
+#!/bin/sh
+# SPDX-License-Identifier: GPL-2.0+
+#
+# dtc-version dtc-command
+#
+# Prints the dtc version of `dtc-command' in a canonical 6-digit form
+# such as `010404' for dtc 1.4.4
+#
+
+dtc="$*"
+
+if [ ${#dtc} -eq 0 ]; then
+ echo "Error: No dtc command specified"
+ printf "Usage:\n\t$0 <dtc-command>\n"
+ exit 1
+fi
+
+if ! which $dtc >/dev/null ; then
+ echo "Error: Cannot find dtc: $dtc"
+ exit 1
+fi
+
+MAJOR=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 1)
+MINOR=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 2)
+PATCH=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 3 | cut -d - -f 1)
+
+printf "%02d%02d%02d\\n" $MAJOR $MINOR $PATCH
diff --git a/test/compression.c b/test/compression.c
index 4cd1be5..26d3c80 100644
--- a/test/compression.c
+++ b/test/compression.c
@@ -9,11 +9,11 @@
#include <gzip.h>
#include <image.h>
#include <log.h>
-#include <lz4.h>
#include <malloc.h>
#include <mapmem.h>
#include <asm/io.h>
+#include <u-boot/lz4.h>
#include <u-boot/zlib.h>
#include <bzlib.h>
diff --git a/test/dm/fdtdec.c b/test/dm/fdtdec.c
index 1f630ea..087d484 100644
--- a/test/dm/fdtdec.c
+++ b/test/dm/fdtdec.c
@@ -28,21 +28,18 @@
resv.start = 0x1000;
resv.end = 0x2000;
- ut_assertok(fdtdec_set_carveout(blob, "/a-test",
- "memory-region", 2, "test_resv1",
- &resv));
+ ut_assertok(fdtdec_set_carveout(blob, "/a-test", "memory-region", 2,
+ &resv, "test_resv1", NULL, 0, 0));
resv.start = 0x10000;
resv.end = 0x20000;
- ut_assertok(fdtdec_set_carveout(blob, "/a-test",
- "memory-region", 1, "test_resv2",
- &resv));
+ ut_assertok(fdtdec_set_carveout(blob, "/a-test", "memory-region", 1,
+ &resv, "test_resv2", NULL, 0, 0));
resv.start = 0x100000;
resv.end = 0x200000;
- ut_assertok(fdtdec_set_carveout(blob, "/a-test",
- "memory-region", 0, "test_resv3",
- &resv));
+ ut_assertok(fdtdec_set_carveout(blob, "/a-test", "memory-region", 0,
+ &resv, "test_resv3", NULL, 0, 0));
offset = fdt_path_offset(blob, "/a-test");
ut_assert(offset > 0);
@@ -67,6 +64,7 @@
fdt_addr_t addr;
fdt_size_t size;
void *blob;
+ unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
int blob_sz, parent, subnode;
uint32_t phandle, phandle1;
@@ -80,8 +78,8 @@
/* Insert a memory region in /reserved-memory node */
resv.start = 0x1000;
resv.end = 0x1fff;
- ut_assertok(fdtdec_add_reserved_memory(blob, "rsvd_region",
- &resv, &phandle, false));
+ ut_assertok(fdtdec_add_reserved_memory(blob, "rsvd_region", &resv,
+ NULL, 0, &phandle, 0));
/* Test /reserve-memory and its subnode should exist */
parent = fdt_path_offset(blob, "/reserved-memory");
@@ -101,8 +99,8 @@
resv.start = 0x2000;
resv.end = 0x2fff;
- ut_assertok(fdtdec_add_reserved_memory(blob, "rsvd_region1",
- &resv, &phandle1, true));
+ ut_assertok(fdtdec_add_reserved_memory(blob, "rsvd_region1", &resv,
+ NULL, 0, &phandle1, flags));
subnode = fdt_path_offset(blob, "/reserved-memory/rsvd_region1");
ut_assert(subnode > 0);
@@ -118,8 +116,8 @@
*/
resv.start = 0x1000;
resv.end = 0x1fff;
- ut_assertok(fdtdec_add_reserved_memory(blob, "rsvd_region2",
- &resv, &phandle1, false));
+ ut_assertok(fdtdec_add_reserved_memory(blob, "rsvd_region2", &resv,
+ NULL, 0, &phandle1, 0));
subnode = fdt_path_offset(blob, "/reserved-memory/rsvd_region2");
ut_assert(subnode < 0);
diff --git a/test/dm/nop.c b/test/dm/nop.c
index 2cd92c5..75b9e7b 100644
--- a/test/dm/nop.c
+++ b/test/dm/nop.c
@@ -25,7 +25,7 @@
const char *bind_flag = ofnode_read_string(ofnode, "bind");
if (bind_flag && (strcmp(bind_flag, "True") == 0))
- lists_bind_fdt(parent, ofnode, &dev, false);
+ lists_bind_fdt(parent, ofnode, &dev, NULL, false);
ofnode = dev_read_next_subnode(ofnode);
}
diff --git a/test/lib/Makefile b/test/lib/Makefile
index 6fd0514..d244bb4 100644
--- a/test/lib/Makefile
+++ b/test/lib/Makefile
@@ -3,6 +3,7 @@
# (C) Copyright 2018
# Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
obj-y += cmd_ut_lib.o
+obj-y += abuf.o
obj-$(CONFIG_EFI_LOADER) += efi_device_path.o
obj-$(CONFIG_EFI_SECURE_BOOT) += efi_image_region.o
obj-y += hexdump.o
diff --git a/test/lib/abuf.c b/test/lib/abuf.c
new file mode 100644
index 0000000..086c9b2
--- /dev/null
+++ b/test/lib/abuf.c
@@ -0,0 +1,344 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <common.h>
+#include <abuf.h>
+#include <mapmem.h>
+#include <test/lib.h>
+#include <test/test.h>
+#include <test/ut.h>
+
+static char test_data[] = "1234";
+#define TEST_DATA_LEN sizeof(test_data)
+
+/* Test abuf_set() */
+static int lib_test_abuf_set(struct unit_test_state *uts)
+{
+ struct abuf buf;
+ ulong start;
+
+ start = ut_check_free();
+
+ abuf_init(&buf);
+ abuf_set(&buf, test_data, TEST_DATA_LEN);
+ ut_asserteq_ptr(test_data, buf.data);
+ ut_asserteq(TEST_DATA_LEN, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ /* Force it to allocate */
+ ut_asserteq(true, abuf_realloc(&buf, TEST_DATA_LEN + 1));
+ ut_assertnonnull(buf.data);
+ ut_asserteq(TEST_DATA_LEN + 1, buf.size);
+ ut_asserteq(true, buf.alloced);
+
+ /* Now set it again, to force it to free */
+ abuf_set(&buf, test_data, TEST_DATA_LEN);
+ ut_asserteq_ptr(test_data, buf.data);
+ ut_asserteq(TEST_DATA_LEN, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ /* Check for memory leaks */
+ ut_assertok(ut_check_delta(start));
+
+ return 0;
+}
+LIB_TEST(lib_test_abuf_set, 0);
+
+/* Test abuf_map_sysmem() */
+static int lib_test_abuf_map_sysmem(struct unit_test_state *uts)
+{
+ struct abuf buf;
+ ulong addr;
+
+ abuf_init(&buf);
+ addr = 0x100;
+ abuf_map_sysmem(&buf, addr, TEST_DATA_LEN);
+
+ ut_asserteq_ptr(map_sysmem(0x100, 0), buf.data);
+ ut_asserteq(TEST_DATA_LEN, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ return 0;
+}
+LIB_TEST(lib_test_abuf_map_sysmem, 0);
+
+/* Test abuf_realloc() */
+static int lib_test_abuf_realloc(struct unit_test_state *uts)
+{
+ struct abuf buf;
+ ulong start;
+ void *ptr;
+
+ /*
+ * TODO: crashes on sandbox sometimes due to an apparent bug in
+ * realloc().
+ */
+ return 0;
+
+ start = ut_check_free();
+
+ abuf_init(&buf);
+
+ /* Allocate an empty buffer */
+ ut_asserteq(true, abuf_realloc(&buf, 0));
+ ut_assertnull(buf.data);
+ ut_asserteq(0, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ /* Allocate a non-empty abuf */
+ ut_asserteq(true, abuf_realloc(&buf, TEST_DATA_LEN));
+ ut_assertnonnull(buf.data);
+ ut_asserteq(TEST_DATA_LEN, buf.size);
+ ut_asserteq(true, buf.alloced);
+ ptr = buf.data;
+
+ /*
+ * Make it smaller; the pointer should remain the same. Note this relies
+ * on knowledge of how U-Boot's realloc() works
+ */
+ ut_asserteq(true, abuf_realloc(&buf, TEST_DATA_LEN - 1));
+ ut_asserteq(TEST_DATA_LEN - 1, buf.size);
+ ut_asserteq(true, buf.alloced);
+ ut_asserteq_ptr(ptr, buf.data);
+
+ /*
+ * Make it larger, forcing reallocation. Note this relies on knowledge
+ * of how U-Boot's realloc() works
+ */
+ ut_asserteq(true, abuf_realloc(&buf, 0x1000));
+ ut_assert(buf.data != ptr);
+ ut_asserteq(0x1000, buf.size);
+ ut_asserteq(true, buf.alloced);
+
+ /* Free it */
+ ut_asserteq(true, abuf_realloc(&buf, 0));
+ ut_assertnull(buf.data);
+ ut_asserteq(0, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ /* Check for memory leaks */
+ ut_assertok(ut_check_delta(start));
+
+ return 0;
+}
+LIB_TEST(lib_test_abuf_realloc, 0);
+
+/* Test handling of buffers that are too large */
+static int lib_test_abuf_large(struct unit_test_state *uts)
+{
+ struct abuf buf;
+ ulong start;
+ size_t size;
+ int delta;
+ void *ptr;
+
+ /*
+ * This crashes at present due to trying to allocate more memory than
+ * available, which breaks something on sandbox.
+ */
+ return 0;
+
+ start = ut_check_free();
+
+ /* Try an impossible size */
+ abuf_init(&buf);
+ ut_asserteq(false, abuf_realloc(&buf, CONFIG_SYS_MALLOC_LEN));
+ ut_assertnull(buf.data);
+ ut_asserteq(0, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ abuf_uninit(&buf);
+ ut_assertnull(buf.data);
+ ut_asserteq(0, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ /* Start with a normal size then try to increase it, to check realloc */
+ ut_asserteq(true, abuf_realloc(&buf, TEST_DATA_LEN));
+ ut_assertnonnull(buf.data);
+ ut_asserteq(TEST_DATA_LEN, buf.size);
+ ut_asserteq(true, buf.alloced);
+ ptr = buf.data;
+ delta = ut_check_delta(start);
+ ut_assert(delta > 0);
+
+ /* try to increase it */
+ ut_asserteq(false, abuf_realloc(&buf, CONFIG_SYS_MALLOC_LEN));
+ ut_asserteq_ptr(ptr, buf.data);
+ ut_asserteq(TEST_DATA_LEN, buf.size);
+ ut_asserteq(true, buf.alloced);
+ ut_asserteq(delta, ut_check_delta(start));
+
+ /* Check for memory leaks */
+ abuf_uninit(&buf);
+ ut_assertok(ut_check_delta(start));
+
+ /* Start with a huge unallocated buf and try to move it */
+ abuf_init(&buf);
+ abuf_map_sysmem(&buf, 0, CONFIG_SYS_MALLOC_LEN);
+ ut_asserteq(CONFIG_SYS_MALLOC_LEN, buf.size);
+ ut_asserteq(false, buf.alloced);
+ ut_assertnull(abuf_uninit_move(&buf, &size));
+
+ /* Check for memory leaks */
+ abuf_uninit(&buf);
+ ut_assertok(ut_check_delta(start));
+
+ return 0;
+}
+LIB_TEST(lib_test_abuf_large, 0);
+
+/* Test abuf_uninit_move() */
+static int lib_test_abuf_uninit_move(struct unit_test_state *uts)
+{
+ void *ptr, *orig_ptr;
+ struct abuf buf;
+ size_t size;
+ ulong start;
+ int delta;
+
+ start = ut_check_free();
+
+ /*
+ * TODO: crashes on sandbox sometimes due to an apparent bug in
+ * realloc().
+ */
+ return 0;
+
+ /* Move an empty buffer */
+ abuf_init(&buf);
+ ut_assertnull(abuf_uninit_move(&buf, &size));
+ ut_asserteq(0, size);
+ ut_assertnull(abuf_uninit_move(&buf, NULL));
+
+ /* Move an unallocated buffer */
+ abuf_set(&buf, test_data, TEST_DATA_LEN);
+ ut_assertok(ut_check_delta(start));
+ ptr = abuf_uninit_move(&buf, &size);
+ ut_asserteq(TEST_DATA_LEN, size);
+ ut_asserteq_str(ptr, test_data);
+ ut_assertnonnull(ptr);
+ ut_assertnull(buf.data);
+ ut_asserteq(0, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ /* Check that freeing it frees the only allocation */
+ delta = ut_check_delta(start);
+ ut_assert(delta > 0);
+ free(ptr);
+ ut_assertok(ut_check_delta(start));
+
+ /* Move an allocated buffer */
+ ut_asserteq(true, abuf_realloc(&buf, TEST_DATA_LEN));
+ orig_ptr = buf.data;
+ strcpy(orig_ptr, test_data);
+
+ delta = ut_check_delta(start);
+ ut_assert(delta > 0);
+ ptr = abuf_uninit_move(&buf, &size);
+ ut_asserteq(TEST_DATA_LEN, size);
+ ut_assertnonnull(ptr);
+ ut_asserteq_ptr(ptr, orig_ptr);
+ ut_asserteq_str(ptr, test_data);
+ ut_assertnull(buf.data);
+ ut_asserteq(0, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ /* Check there was no new allocation */
+ ut_asserteq(delta, ut_check_delta(start));
+
+ /* Check that freeing it frees the only allocation */
+ free(ptr);
+ ut_assertok(ut_check_delta(start));
+
+ /* Move an unallocated buffer, without the size */
+ abuf_set(&buf, test_data, TEST_DATA_LEN);
+ ut_assertok(ut_check_delta(start));
+ ptr = abuf_uninit_move(&buf, NULL);
+ ut_asserteq_str(ptr, test_data);
+
+ return 0;
+}
+LIB_TEST(lib_test_abuf_uninit_move, 0);
+
+/* Test abuf_uninit() */
+static int lib_test_abuf_uninit(struct unit_test_state *uts)
+{
+ struct abuf buf;
+
+ /* Nothing in the buffer */
+ abuf_init(&buf);
+ abuf_uninit(&buf);
+ ut_assertnull(buf.data);
+ ut_asserteq(0, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ /* Not allocated */
+ abuf_set(&buf, test_data, TEST_DATA_LEN);
+ abuf_uninit(&buf);
+ ut_assertnull(buf.data);
+ ut_asserteq(0, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ return 0;
+}
+LIB_TEST(lib_test_abuf_uninit, 0);
+
+/* Test abuf_init_set() */
+static int lib_test_abuf_init_set(struct unit_test_state *uts)
+{
+ struct abuf buf;
+
+ abuf_init_set(&buf, test_data, TEST_DATA_LEN);
+ ut_asserteq_ptr(test_data, buf.data);
+ ut_asserteq(TEST_DATA_LEN, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ return 0;
+}
+LIB_TEST(lib_test_abuf_init_set, 0);
+
+/* Test abuf_init_move() */
+static int lib_test_abuf_init_move(struct unit_test_state *uts)
+{
+ struct abuf buf;
+ void *ptr;
+
+ /*
+ * TODO: crashes on sandbox sometimes due to an apparent bug in
+ * realloc().
+ */
+ return 0;
+
+ ptr = strdup(test_data);
+ ut_assertnonnull(ptr);
+
+ free(ptr);
+
+ abuf_init_move(&buf, ptr, TEST_DATA_LEN);
+ ut_asserteq_ptr(ptr, abuf_data(&buf));
+ ut_asserteq(TEST_DATA_LEN, abuf_size(&buf));
+ ut_asserteq(true, buf.alloced);
+
+ return 0;
+}
+LIB_TEST(lib_test_abuf_init_move, 0);
+
+/* Test abuf_init() */
+static int lib_test_abuf_init(struct unit_test_state *uts)
+{
+ struct abuf buf;
+
+ buf.data = &buf;
+ buf.size = 123;
+ buf.alloced = true;
+ abuf_init(&buf);
+ ut_assertnull(buf.data);
+ ut_asserteq(0, buf.size);
+ ut_asserteq(false, buf.alloced);
+
+ return 0;
+}
+LIB_TEST(lib_test_abuf_init, 0);
diff --git a/test/lib/string.c b/test/lib/string.c
index 64234be..5dcf4d6 100644
--- a/test/lib/string.c
+++ b/test/lib/string.c
@@ -23,6 +23,8 @@
/* Allow for copying up to 32 bytes */
#define BUFLEN (SWEEP + 33)
+#define TEST_STR "hello"
+
/**
* init_buffer() - initialize buffer
*
@@ -193,3 +195,33 @@
}
LIB_TEST(lib_memmove, 0);
+
+/** lib_memdup() - unit test for memdup() */
+static int lib_memdup(struct unit_test_state *uts)
+{
+ char buf[BUFLEN];
+ size_t len;
+ char *p, *q;
+
+ /* Zero size should do nothing */
+ p = memdup(NULL, 0);
+ ut_assertnonnull(p);
+ free(p);
+
+ p = memdup(buf, 0);
+ ut_assertnonnull(p);
+ free(p);
+
+ strcpy(buf, TEST_STR);
+ len = sizeof(TEST_STR);
+ p = memdup(buf, len);
+ ut_asserteq_mem(p, buf, len);
+
+ q = memdup(p, len);
+ ut_asserteq_mem(q, buf, len);
+ free(q);
+ free(p);
+
+ return 0;
+}
+LIB_TEST(lib_memdup, 0);
diff --git a/test/py/test.py b/test/py/test.py
index 285fda5..95859a6 100755
--- a/test/py/test.py
+++ b/test/py/test.py
@@ -17,4 +17,9 @@
# argv; py.test test_directory_name user-supplied-arguments
args = [os.path.dirname(__file__) + '/tests']
args.extend(sys.argv)
+
+ # Use short format by default
+ if not [arg for arg in args if '--tb=' in arg]:
+ args.append('--tb=short')
+
sys.exit(pytest.main(args))
diff --git a/test/py/tests/test_bind.py b/test/py/tests/test_bind.py
index 6703325..9f234fb6 100644
--- a/test/py/tests/test_bind.py
+++ b/test/py/tests/test_bind.py
@@ -33,6 +33,13 @@
assert in_tree(tree, 'bind-test-child1', 'phy', 'phy_sandbox', 1, False)
assert in_tree(tree, 'bind-test-child2', 'simple_bus', 'simple_bus', 1, True)
+ #bind usb_ether driver (which has no compatible) to usb@1 node.
+ ##New entry usb_ether should appear in the dm tree
+ response = u_boot_console.run_command('bind /usb@1 usb_ether')
+ assert response == ''
+ tree = u_boot_console.run_command('dm tree')
+ assert in_tree(tree, 'usb@1', 'ethernet', 'usb_ether', 1, True)
+
#Unbind child #1. No error expected and all devices should be there except for bind-test-child1
response = u_boot_console.run_command('unbind /bind-test/bind-test-child1')
assert response == ''
diff --git a/test/py/u_boot_spawn.py b/test/py/u_boot_spawn.py
index 6991b78..e34cb21 100644
--- a/test/py/u_boot_spawn.py
+++ b/test/py/u_boot_spawn.py
@@ -35,6 +35,8 @@
"""
self.waited = False
+ self.exit_code = 0
+ self.exit_info = ''
self.buf = ''
self.output = ''
self.logfile_read = None
@@ -80,25 +82,44 @@
os.kill(self.pid, sig)
- def isalive(self):
+ def checkalive(self):
"""Determine whether the child process is still running.
- Args:
- None.
-
Returns:
- Boolean indicating whether process is alive.
+ tuple:
+ True if process is alive, else False
+ 0 if process is alive, else exit code of process
+ string describing what happened ('' or 'status/signal n')
"""
if self.waited:
- return False
+ return False, self.exit_code, self.exit_info
w = os.waitpid(self.pid, os.WNOHANG)
if w[0] == 0:
- return True
+ return True, 0, 'running'
+ status = w[1]
+ if os.WIFEXITED(status):
+ self.exit_code = os.WEXITSTATUS(status)
+ self.exit_info = 'status %d' % self.exit_code
+ elif os.WIFSIGNALED(status):
+ signum = os.WTERMSIG(status)
+ self.exit_code = -signum
+ self.exit_info = 'signal %d (%s)' % (signum, signal.Signals(signum))
self.waited = True
- return False
+ return False, self.exit_code, self.exit_info
+
+ def isalive(self):
+ """Determine whether the child process is still running.
+
+ Args:
+ None.
+
+ Returns:
+ Boolean indicating whether process is alive.
+ """
+ return self.checkalive()[0]
def send(self, data):
"""Send data to the sub-process's stdin.
@@ -168,9 +189,20 @@
events = self.poll.poll(poll_maxwait)
if not events:
raise Timeout()
- c = os.read(self.fd, 1024).decode(errors='replace')
- if not c:
- raise EOFError()
+ try:
+ c = os.read(self.fd, 1024).decode(errors='replace')
+ except OSError as err:
+ # With sandbox, try to detect when U-Boot exits when it
+ # shouldn't and explain why. This is much more friendly than
+ # just dying with an I/O error
+ if err.errno == 5: # Input/output error
+ alive, exit_code, info = self.checkalive()
+ if alive:
+ raise
+ else:
+ raise ValueError('U-Boot exited with %s' % info)
+ else:
+ raise
if self.logfile_read:
self.logfile_read.write(c)
self.buf += c
diff --git a/tools/Kconfig b/tools/Kconfig
index d6f82cd..91ce8ae 100644
--- a/tools/Kconfig
+++ b/tools/Kconfig
@@ -9,6 +9,11 @@
some cases the system dtc may not support all required features
and the path to a different version should be given here.
+config TOOLS_CRC32
+ def_bool y
+ help
+ Enable CRC32 support in the tools builds
+
config TOOLS_LIBCRYPTO
bool "Use OpenSSL's libcrypto library for host tools"
default y
@@ -20,4 +25,69 @@
This selection does not affect target features, such as runtime FIT
signature verification.
+config TOOLS_FIT
+ def_bool y
+ help
+ Enable FIT support in the tools builds.
+
+config TOOLS_FIT_FULL_CHECK
+ def_bool y
+ help
+ Do a full check of the FIT before using it in the tools builds
+
+config TOOLS_FIT_PRINT
+ def_bool y
+ help
+ Print the content of the FIT verbosely in the tools builds
+
+config TOOLS_FIT_RSASSA_PSS
+ def_bool y
+ help
+ Support the rsassa-pss signature scheme in the tools builds
+
+config TOOLS_FIT_SIGNATURE
+ def_bool y
+ help
+ Enable signature verification of FIT uImages in the tools builds
+
+config TOOLS_FIT_SIGNATURE_MAX_SIZE
+ hex
+ depends on TOOLS_FIT_SIGNATURE
+ default 0x10000000
+
+config TOOLS_FIT_VERBOSE
+ def_bool y
+ help
+ Support verbose FIT output in the tools builds
+
+config TOOLS_MD5
+ def_bool y
+ help
+ Enable MD5 support in the tools builds
+
+config TOOLS_OF_LIBFDT
+ def_bool y
+ help
+ Enable libfdt support in the tools builds
+
+config TOOLS_SHA1
+ def_bool y
+ help
+ Enable SHA1 support in the tools builds
+
+config TOOLS_SHA256
+ def_bool y
+ help
+ Enable SHA256 support in the tools builds
+
+config TOOLS_SHA384
+ def_bool y
+ help
+ Enable SHA384 support in the tools builds
+
+config TOOLS_SHA512
+ def_bool y
+ help
+ Enable SHA512 support in the tools builds
+
endmenu
diff --git a/tools/Makefile b/tools/Makefile
index 4a86321..b45219e 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -113,6 +113,7 @@
lib/fdtdec_common.o \
lib/fdtdec.o \
common/image.o \
+ common/image-host.o \
imagetool.o \
imximage.o \
imx8image.o \
@@ -294,8 +295,7 @@
-I$(srctree)/tools \
-DUSE_HOSTCC \
-D__KERNEL_STRICT_NAMES \
- -D_GNU_SOURCE \
- -std=gnu99
+ -D_GNU_SOURCE
__build: $(LOGO-y)
diff --git a/tools/binman/binman.rst b/tools/binman/binman.rst
index 09e7b57..614df54 100644
--- a/tools/binman/binman.rst
+++ b/tools/binman/binman.rst
@@ -232,18 +232,18 @@
inclusion' below.
-Using binman with OF_BOARD or OF_PRIOR_STAGE
+Using binman with OF_BOARD
--------------------------------------------
Normally binman is used with a board configured with OF_SEPARATE or OF_EMBED.
This is a typical scenario where a device tree source that contains the binman
node is provided in the arch/<arch>/dts directory for a specific board.
-However for a board configured with OF_BOARD or OF_PRIOR_STAGE, no device tree
-blob is provided in the U-Boot build phase hence the binman node information
-is not available. In order to support such use case, a new Kconfig option
-BINMAN_STANDALONE_FDT is introduced, to tell the build system that a standalone
-device tree blob containing binman node is explicitly required.
+However for a board configured with OF_BOARD, no device tree blob is provided
+in the U-Boot build phase hence the binman node information is not available.
+In order to support such use case, a new Kconfig option BINMAN_STANDALONE_FDT
+is introduced, to tell the build system that a standalone device tree blob
+containing binman node is explicitly required.
Note there is a Kconfig option BINMAN_FDT which enables U-Boot run time to
access information about binman entries, stored in the device tree in a binman
@@ -252,10 +252,6 @@
available as binman is invoked during the build phase, thus this option is not
turned on by default for these OF_CONTROL methods.
-See qemu-riscv64_spl_defconfig for an example of how binman is used with
-OF_PRIOR_STAGE to generate u-boot.itb image.
-
-
Access to binman entry offsets at run time (symbols)
----------------------------------------------------
diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py
index ce852eb..122f0d1 100644
--- a/tools/buildman/builder.py
+++ b/tools/buildman/builder.py
@@ -24,6 +24,17 @@
from patman import terminal
from patman.terminal import Print
+# This indicates an new int or hex Kconfig property with no default
+# It hangs the build since the 'conf' tool cannot proceed without valid input.
+#
+# We get a repeat sequence of something like this:
+# >>
+# Break things (BREAK_ME) [] (NEW)
+# Error in reading or end of file.
+# <<
+# which indicates that BREAK_ME has an empty default
+RE_NO_DEFAULT = re.compile(b'\((\w+)\) \[] \(NEW\)')
+
"""
Theory of Operation
@@ -200,6 +211,8 @@
_working_dir: Base working directory containing all threads
_single_builder: BuilderThread object for the singer builder, if
threading is not being used
+ _terminated: Thread was terminated due to an error
+ _restarting_config: True if 'Restart config' is detected in output
"""
class Outcome:
"""Records a build outcome for a single make invocation
@@ -304,6 +317,8 @@
self.work_in_output = work_in_output
if not self.squash_config_y:
self.config_filenames += EXTRA_CONFIG_FILENAMES
+ self._terminated = False
+ self._restarting_config = False
self.warnings_as_errors = warnings_as_errors
self.col = terminal.Color()
@@ -429,9 +444,35 @@
args: Arguments to pass to make
kwargs: Arguments to pass to command.RunPipe()
"""
+
+ def check_output(stream, data):
+ if b'Restart config' in data:
+ self._restarting_config = True
+
+ # If we see 'Restart config' following by multiple errors
+ if self._restarting_config:
+ m = RE_NO_DEFAULT.findall(data)
+
+ # Number of occurences of each Kconfig item
+ multiple = [m.count(val) for val in set(m)]
+
+ # If any of them occur more than once, we have a loop
+ if [val for val in multiple if val > 1]:
+ self._terminated = True
+ return True
+ return False
+
+ self._restarting_config = False
+ self._terminated = False
cmd = [self.gnu_make] + list(args)
result = command.RunPipe([cmd], capture=True, capture_stderr=True,
- cwd=cwd, raise_on_error=False, infile='/dev/null', **kwargs)
+ cwd=cwd, raise_on_error=False, infile='/dev/null',
+ output_func=check_output, **kwargs)
+
+ if self._terminated:
+ # Try to be helpful
+ result.stderr += '(** did you define an int/hex Kconfig with no default? **)'
+
if self.verbose_build:
result.stdout = '%s\n' % (' '.join(cmd)) + result.stdout
result.combined = '%s\n' % (' '.join(cmd)) + result.combined
diff --git a/tools/buildman/builderthread.py b/tools/buildman/builderthread.py
index 48128cf..3e450e4 100644
--- a/tools/buildman/builderthread.py
+++ b/tools/buildman/builderthread.py
@@ -300,16 +300,12 @@
work_in_output: Use the output directory as the work directory and
don't write to a separate output directory.
"""
- # Fatal error
- if result.return_code < 0:
- return
-
# If we think this might have been aborted with Ctrl-C, record the
# failure but not that we are 'done' with this board. A retry may fix
# it.
- maybe_aborted = result.stderr and 'No child processes' in result.stderr
+ maybe_aborted = result.stderr and 'No child processes' in result.stderr
- if result.already_done:
+ if result.return_code >= 0 and result.already_done:
return
# Write the output and stderr
@@ -332,6 +328,10 @@
elif os.path.exists(errfile):
os.remove(errfile)
+ # Fatal error
+ if result.return_code < 0:
+ return
+
if result.toolchain:
# Write the build result and toolchain information.
done_file = self.builder.GetDoneFile(result.commit_upto,
diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py
index fd137f7..4e2471f 100644
--- a/tools/buildman/toolchain.py
+++ b/tools/buildman/toolchain.py
@@ -498,7 +498,7 @@
if arch == 'aarch64':
arch = 'arm64'
base = 'https://www.kernel.org/pub/tools/crosstool/files/bin'
- versions = ['9.2.0', '7.3.0', '6.4.0', '4.9.4']
+ versions = ['11.1.0', '9.2.0', '7.3.0', '6.4.0', '4.9.4']
links = []
for version in versions:
url = '%s/%s/%s/' % (base, arch, version)
diff --git a/tools/docker/Dockerfile b/tools/docker/Dockerfile
index 92113dc..1a44423 100644
--- a/tools/docker/Dockerfile
+++ b/tools/docker/Dockerfile
@@ -2,7 +2,7 @@
# This Dockerfile is used to build an image containing basic stuff to be used
# to build U-Boot and run our test suites.
-FROM ubuntu:focal-20210827
+FROM ubuntu:focal-20210921
MAINTAINER Tom Rini <trini@konsulko.com>
LABEL Description=" This image is for building U-Boot inside a container"
@@ -12,7 +12,7 @@
# Add LLVM repository
RUN apt-get update && apt-get install -y gnupg2 wget xz-utils && rm -rf /var/lib/apt/lists/*
RUN wget -O - https://apt.llvm.org/llvm-snapshot.gpg.key | apt-key add -
-RUN echo deb http://apt.llvm.org/focal/ llvm-toolchain-focal-12 main | tee /etc/apt/sources.list.d/llvm.list
+RUN echo deb http://apt.llvm.org/focal/ llvm-toolchain-focal-13 main | tee /etc/apt/sources.list.d/llvm.list
# Manually install the kernel.org "Crosstool" based toolchains for gcc-11.1.0
RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/11.1.0/x86_64-gcc-11.1.0-nolibc-aarch64-linux.tar.xz | tar -C /opt -xJ
@@ -39,7 +39,7 @@
binutils-dev \
bison \
build-essential \
- clang-12 \
+ clang-13 \
coreutils \
cpio \
cppcheck \
diff --git a/tools/image-host.c b/tools/image-host.c
index d3a882e..a6b0a94 100644
--- a/tools/image-host.c
+++ b/tools/image-host.c
@@ -313,7 +313,7 @@
/* Check that we have read all the file */
if (n != sbuf.st_size) {
- printf("Can't read all file %s (read %zd bytes, expexted %lld)\n",
+ printf("Can't read all file %s (read %zd bytes, expected %lld)\n",
filename, n, (long long)sbuf.st_size);
goto err;
}
diff --git a/tools/imx8mimage.c b/tools/imx8mimage.c
index 11e40cc..4eed683 100644
--- a/tools/imx8mimage.c
+++ b/tools/imx8mimage.c
@@ -271,7 +271,7 @@
if (ptr == MAP_FAILED) {
fprintf(stderr, "Can't read %s: %s\n",
datafile, strerror(errno));
- exit(EXIT_FAILURE);
+ goto err_mmap;
}
size = sbuf.st_size - datafile_offset;
@@ -311,6 +311,7 @@
}
munmap((void *)ptr, sbuf.st_size);
+err_mmap:
close(dfd);
}
diff --git a/tools/patman/command.py b/tools/patman/command.py
index bf8ea6c..d54b1e0 100644
--- a/tools/patman/command.py
+++ b/tools/patman/command.py
@@ -49,7 +49,8 @@
def RunPipe(pipe_list, infile=None, outfile=None,
capture=False, capture_stderr=False, oneline=False,
- raise_on_error=True, cwd=None, binary=False, **kwargs):
+ raise_on_error=True, cwd=None, binary=False,
+ output_func=None, **kwargs):
"""
Perform a command pipeline, with optional input/output filenames.
@@ -63,6 +64,8 @@
capture: True to capture output
capture_stderr: True to capture stderr
oneline: True to strip newline chars from output
+ output_func: Output function to call with each output fragment
+ (if it returns True the function terminates)
kwargs: Additional keyword arguments to cros_subprocess.Popen()
Returns:
CommandResult object
@@ -105,7 +108,7 @@
if capture:
result.stdout, result.stderr, result.combined = (
- last_pipe.CommunicateFilter(None))
+ last_pipe.CommunicateFilter(output_func))
if result.stdout and oneline:
result.output = result.stdout.rstrip(b'\r\n')
result.return_code = last_pipe.wait()
diff --git a/tools/patman/cros_subprocess.py b/tools/patman/cros_subprocess.py
index fdd5138..88a4693 100644
--- a/tools/patman/cros_subprocess.py
+++ b/tools/patman/cros_subprocess.py
@@ -128,6 +128,9 @@
sys.stdout or sys.stderr.
data: a string containing the data
+ Returns:
+ True to terminate the process
+
Note: The data read is buffered in memory, so do not use this
method if the data size is large or unlimited.
@@ -175,6 +178,7 @@
stderr = bytearray()
combined = bytearray()
+ stop_now = False
input_offset = 0
while read_set or write_set:
try:
@@ -212,7 +216,7 @@
stdout += data
combined += data
if output:
- output(sys.stdout, data)
+ stop_now = output(sys.stdout, data)
if self.stderr in rlist:
data = b''
# We will get an error on read if the pty is closed
@@ -227,7 +231,9 @@
stderr += data
combined += data
if output:
- output(sys.stderr, data)
+ stop_now = output(sys.stderr, data)
+ if stop_now:
+ self.terminate()
# All data exchanged. Translate lists into strings.
stdout = self.ConvertData(stdout)
diff --git a/tools/termios_linux.h b/tools/termios_linux.h
index d73989b..e100c8e 100644
--- a/tools/termios_linux.h
+++ b/tools/termios_linux.h
@@ -90,7 +90,11 @@
static inline int tcsendbreak(int fd, int d)
{
- return ioctl(fd, TCSBRK, d);
+#ifdef TCSBRKP
+ return ioctl(fd, TCSBRKP, d);
+#else
+ return ioctl(fd, TCSBRK, 0);
+#endif
}
static inline int tcflow(int fd, int a)