Initial revision
diff --git a/board/evb64260/intel_flash.h b/board/evb64260/intel_flash.h
new file mode 100644
index 0000000..dc2aa00
--- /dev/null
+++ b/board/evb64260/intel_flash.h
@@ -0,0 +1,160 @@
+/*************** DEFINES for Intel StrataFlash FLASH chip ********************/
+
+/*
+ * acceptable chips types are:
+ *
+ * 28F320J5, 28F640J5, 28F320J3A, 28F640J3A and 28F128J3A
+ */
+
+/* register addresses, valid only following an CHIP_CMD_RD_ID command */
+#define CHIP_ADDR_REG_MAN 0x000000 /* manufacturer's id */
+#define CHIP_ADDR_REG_DEV 0x000001 /* device id */
+#define CHIP_ADDR_REG_CFGM 0x000003 /* master lock config */
+#define CHIP_ADDR_REG_CFG(b) (((b)<<16)|2) /* lock config for block b */
+
+/* Commands */
+#define CHIP_CMD_RST 0xFF /* reset flash */
+#define CHIP_CMD_RD_ID 0x90 /* read the id and lock bits */
+#define CHIP_CMD_RD_QUERY 0x98 /* read device capabilities */
+#define CHIP_CMD_RD_STAT 0x70 /* read the status register */
+#define CHIP_CMD_CLR_STAT 0x50 /* clear the staus register */
+#define CHIP_CMD_WR_BUF 0xE8 /* clear the staus register */
+#define CHIP_CMD_PROG 0x40 /* program word command */
+#define CHIP_CMD_ERASE1 0x20 /* 1st word for block erase */
+#define CHIP_CMD_ERASE2 0xD0 /* 2nd word for block erase */
+#define CHIP_CMD_ERASE_SUSP 0xB0 /* suspend block erase */
+#define CHIP_CMD_LOCK 0x60 /* 1st word for all lock cmds */
+#define CHIP_CMD_SET_LOCK_BLK 0x01 /* 2nd wrd set block lock bit */
+#define CHIP_CMD_SET_LOCK_MSTR 0xF1 /* 2nd wrd set master lck bit */
+#define CHIP_CMD_CLR_LOCK_BLK 0xD0 /* 2nd wrd clear blk lck bit */
+
+/* status register bits */
+#define CHIP_STAT_DPS 0x02 /* Device Protect Status */
+#define CHIP_STAT_VPPS 0x08 /* VPP Status */
+#define CHIP_STAT_PSLBS 0x10 /* Program+Set Lock Bit Stat */
+#define CHIP_STAT_ECLBS 0x20 /* Erase+Clr Lock Bit Stat */
+#define CHIP_STAT_ESS 0x40 /* Erase Suspend Status */
+#define CHIP_STAT_RDY 0x80 /* WSM Mach Status, 1=rdy */
+
+#define CHIP_STAT_ERR (CHIP_STAT_VPPS | CHIP_STAT_DPS | \
+ CHIP_STAT_ECLBS | CHIP_STAT_PSLBS)
+
+/* ID and Lock Configuration */
+#define CHIP_RD_ID_LOCK 0x01 /* Bit 0 of each byte */
+#define CHIP_RD_ID_MAN 0x89 /* Manufacturer code = 0x89 */
+#define CHIP_RD_ID_DEV CFG_FLASH_ID
+
+/* dimensions */
+#define CHIP_WIDTH 2 /* chips are in 16 bit mode */
+#define CHIP_WSHIFT 1 /* (log2 of CHIP_WIDTH) */
+#define CHIP_NBLOCKS 128
+#define CHIP_BLKSZ (128 * 1024) /* of 128Kbytes each */
+#define CHIP_SIZE (CHIP_BLKSZ * CHIP_NBLOCKS)
+
+/********************** DEFINES for Hymod Flash ******************************/
+
+/*
+ * The hymod board has 2 x 28F320J5 chips running in
+ * 16 bit mode, for a 32 bit wide bank.
+ */
+
+typedef unsigned short bank_word_t; /* 8/16/32/64bit unsigned int */
+typedef volatile bank_word_t *bank_addr_t;
+typedef unsigned long bank_size_t; /* want this big - >= 32 bit */
+
+#define BANK_CHIP_WIDTH 1 /* each bank is 1 chip wide */
+#define BANK_CHIP_WSHIFT 0 /* (log2 of BANK_CHIP_WIDTH) */
+
+#define BANK_WIDTH (CHIP_WIDTH * BANK_CHIP_WIDTH)
+#define BANK_WSHIFT (CHIP_WSHIFT + BANK_CHIP_WSHIFT)
+#define BANK_NBLOCKS CHIP_NBLOCKS
+#define BANK_BLKSZ (CHIP_BLKSZ * BANK_CHIP_WIDTH)
+#define BANK_SIZE (CHIP_SIZE * BANK_CHIP_WIDTH)
+
+#define MAX_BANKS 1 /* only one bank possible */
+
+/* align bank addresses and sizes to bank word boundaries */
+#define BANK_ADDR_WORD_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
+ & ~(BANK_WIDTH - 1)))
+#define BANK_SIZE_WORD_ALIGN(s) ((bank_size_t)BANK_ADDR_WORD_ALIGN( \
+ (bank_size_t)(s) + (BANK_WIDTH - 1)))
+
+/* align bank addresses and sizes to bank block boundaries */
+#define BANK_ADDR_BLK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
+ & ~(BANK_BLKSZ - 1)))
+#define BANK_SIZE_BLK_ALIGN(s) ((bank_size_t)BANK_ADDR_BLK_ALIGN( \
+ (bank_size_t)(s) + (BANK_BLKSZ - 1)))
+
+/* align bank addresses and sizes to bank boundaries */
+#define BANK_ADDR_BANK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
+ & ~(BANK_SIZE - 1)))
+#define BANK_SIZE_BANK_ALIGN(s) ((bank_size_t)BANK_ADDR_BANK_ALIGN( \
+ (bank_size_t)(s) + (BANK_SIZE - 1)))
+
+/* add an offset to a bank address */
+#define BANK_ADDR_OFFSET(a, o) (bank_addr_t)((bank_size_t)(a) + \
+ (bank_size_t)(o))
+
+/* get base address of bank b, given flash base address a */
+#define BANK_ADDR_BASE(a, b) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
+ (bank_size_t)(b) * BANK_SIZE)
+
+/* adjust a bank address to start of next word, block or bank */
+#define BANK_ADDR_NEXT_WORD(a) BANK_ADDR_OFFSET(BANK_ADDR_WORD_ALIGN(a), \
+ BANK_WIDTH)
+#define BANK_ADDR_NEXT_BLK(a) BANK_ADDR_OFFSET(BANK_ADDR_BLK_ALIGN(a), \
+ BANK_BLKSZ)
+#define BANK_ADDR_NEXT_BANK(a) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
+ BANK_SIZE)
+
+/* get bank address of chip register r given a bank base address a */
+#define BANK_ADDR_REG(a, r) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
+ ((bank_size_t)(r) << BANK_WSHIFT))
+
+/* make a bank address for each chip register address */
+
+#define BANK_ADDR_REG_MAN(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_MAN)
+#define BANK_ADDR_REG_DEV(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_DEV)
+#define BANK_ADDR_REG_CFGM(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFGM)
+#define BANK_ADDR_REG_CFG(b,a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG(b))
+
+/*
+ * replicate a chip cmd/stat/rd value into each byte position within a word
+ * so that multiple chips are accessed in a single word i/o operation
+ *
+ * this must be as wide as the bank_word_t type, and take into account the
+ * chip width and bank layout
+ */
+
+#define BANK_FILL_WORD(o) ((bank_word_t)(o))
+
+/* make a bank word value for each chip cmd/stat/rd value */
+
+/* Commands */
+#define BANK_CMD_RST BANK_FILL_WORD(CHIP_CMD_RST)
+#define BANK_CMD_RD_ID BANK_FILL_WORD(CHIP_CMD_RD_ID)
+#define BANK_CMD_RD_STAT BANK_FILL_WORD(CHIP_CMD_RD_STAT)
+#define BANK_CMD_CLR_STAT BANK_FILL_WORD(CHIP_CMD_CLR_STAT)
+#define BANK_CMD_ERASE1 BANK_FILL_WORD(CHIP_CMD_ERASE1)
+#define BANK_CMD_ERASE2 BANK_FILL_WORD(CHIP_CMD_ERASE2)
+#define BANK_CMD_PROG BANK_FILL_WORD(CHIP_CMD_PROG)
+#define BANK_CMD_LOCK BANK_FILL_WORD(CHIP_CMD_LOCK)
+#define BANK_CMD_SET_LOCK_BLK BANK_FILL_WORD(CHIP_CMD_SET_LOCK_BLK)
+#define BANK_CMD_SET_LOCK_MSTR BANK_FILL_WORD(CHIP_CMD_SET_LOCK_MSTR)
+#define BANK_CMD_CLR_LOCK_BLK BANK_FILL_WORD(CHIP_CMD_CLR_LOCK_BLK)
+
+/* status register bits */
+#define BANK_STAT_DPS BANK_FILL_WORD(CHIP_STAT_DPS)
+#define BANK_STAT_PSS BANK_FILL_WORD(CHIP_STAT_PSS)
+#define BANK_STAT_VPPS BANK_FILL_WORD(CHIP_STAT_VPPS)
+#define BANK_STAT_PSLBS BANK_FILL_WORD(CHIP_STAT_PSLBS)
+#define BANK_STAT_ECLBS BANK_FILL_WORD(CHIP_STAT_ECLBS)
+#define BANK_STAT_ESS BANK_FILL_WORD(CHIP_STAT_ESS)
+#define BANK_STAT_RDY BANK_FILL_WORD(CHIP_STAT_RDY)
+
+#define BANK_STAT_ERR BANK_FILL_WORD(CHIP_STAT_ERR)
+
+/* ID and Lock Configuration */
+#define BANK_RD_ID_LOCK BANK_FILL_WORD(CHIP_RD_ID_LOCK)
+#define BANK_RD_ID_MAN BANK_FILL_WORD(CHIP_RD_ID_MAN)
+#define BANK_RD_ID_DEV BANK_FILL_WORD(CHIP_RD_ID_DEV)
diff --git a/board/evb64260/zuma_pbb.h b/board/evb64260/zuma_pbb.h
new file mode 100644
index 0000000..663e10c
--- /dev/null
+++ b/board/evb64260/zuma_pbb.h
@@ -0,0 +1,346 @@
+#ifndef ZUMA_PBB_H
+#define ZUMA_PBB_H
+
+#define MAX_NUM_BUFFER_PER_RING 32
+
+#ifdef __BIG_ENDIAN
+#define cpu_bits _be_s_bits /* use with le32_to_cpu only */
+#define pci_bits _be_bits /* may contain swapped bytes,
+ but dont need le32_to_cpu */
+#endif
+
+#ifdef __LITTLE_ENDIAN
+#define cpu_bits _le_bits
+#define pci_bits _le_bits
+#endif
+
+#define VENDOR_ID_ZUMA 0x1172
+#define DEVICE_ID_ZUMA_PBB 0x0004
+
+#define RXDBP(chan) (&sip->rx_desc[chan].base) /* ch*8 */
+#define RXDP(chan) (&sip->rx_desc[chan].current) /* ch*8 + 4 */
+#define TXDBP(chan) (&sip->tx_desc[chan].base) /* ch*8 + 64 */
+#define TXDP(chan) (&sip->tx_desc[chan].current) /* ch*8 + 68 */
+
+#define PBB_DMA_OWN_BIT 0x80000000
+#define PBB_DMA_LAST_BIT 0x40000000
+
+#define EOF_RX_FLAG 1 /* bit 0 */
+#define EOB_RX_FLAG 2 /* bit 1 */
+#define EOF_TX_FLAG 4 /* bit 2 */
+#define EOB_TX_FLAG 8 /* bit 3 */
+
+#define TX_MODE(m) (((m)&7) << 16)
+
+#define RX_DESC(i) (cs->rx_desc[i])
+#define TX_DESC(i) (cs->tx_desc[i])
+
+#define RX_CONTROL(i) (RX_DESC(i).control.word)
+#define RX_CONTROL_SIZE(i) (RX_DESC(i).control.rx.size)
+#define TX_CONTROL(i) (TX_DESC(i).control.word)
+
+#define RX_DATA_P(i) (&RX_DESC(i).ptr)
+#define TX_DATA_P(i) (&TX_DESC(i).ptr)
+
+typedef volatile unsigned char V8;
+typedef volatile unsigned short V16;
+typedef volatile unsigned int V32;
+
+/* RAM descriptor layout */
+typedef struct _tag_dma_descriptor {
+ V32 ptr;
+ union {
+ struct {
+ V32 owner:1;
+ V32 last:1;
+ V32 reserved0: 10;
+ V32 tx_mode: 4;
+
+ V32 reserved1: 5;
+ V32 size: 11;
+ } tx;
+ struct {
+ V32 owner:1;
+ V32 last:1;
+ V32 reserved0: 14;
+
+ V32 reserved1: 5;
+ V32 size: 11;
+ } rx;
+ V32 word;
+ } control;
+} DMA_DESCRIPTOR;
+
+/*
+ * NOTE: DO NOT USE structure to write non-word values... all registers
+ * MUST be written 4 bytes at a time in SI version 0.
+ * Non-word writes will result in "unaccessed" bytes written as zero.
+ *
+ * Byte reads are allowed.
+ *
+ * V32 pads are because the registers are spaced every 8 bytes (64 bits)
+ *
+ */
+
+/* NOTE!!! 4 dwords */
+typedef struct _tag_dma_descriptor_ring {
+ DMA_DESCRIPTOR *base;
+ V32 pad1; /* skip high dword */
+ volatile DMA_DESCRIPTOR *current;
+ V32 pad3; /* skip high dword */
+} DMA_DESCRIPTOR_RING;
+
+/* 1 dword */
+typedef union _tag_dma_generic {
+ struct { /* byte 3 2 1 0 */
+ V32 chan7:4; /* bits 31-28 */
+ V32 chan6:4; /* bits 27-24 */
+ V32 chan5:4; /* bits 23-20 */
+ V32 chan4:4; /* bits 19-16 */
+ V32 chan3:4; /* bits 15-12 */
+ V32 chan2:4; /* bits 11-8 */
+ V32 chan1:4; /* bits 7-4 */
+ V32 chan0:4; /* bits 3-0 */
+ } _be_s_bits;
+ struct { /* byte 0 1 2 3 */
+ V32 chan1:4; /* bits 7-4 */
+ V32 chan0:4; /* bits 3-0 */
+ V32 chan3:4; /* bits 15-12 */
+ V32 chan2:4; /* bits 11-8 */
+ V32 chan5:4; /* bits 23-20 */
+ V32 chan4:4; /* bits 19-16 */
+ V32 chan7:4; /* bits 31-28 */
+ V32 chan6:4; /* bits 27-24 */
+ } _be_bits;
+ struct { /* byte 0 1 2 3 */
+ V32 chan0:4; /* bits 0-3 */
+ V32 chan1:4; /* bits 4-7 */
+ V32 chan2:4; /* bits 8-11 */
+ V32 chan3:4; /* bits 12-15 */
+ V32 chan4:4; /* bits 16-19 */
+ V32 chan5:4; /* bits 20-23 */
+ V32 chan6:4; /* bits 24-27 */
+ V32 chan7:4; /* bits 28-31 */
+ } _le_bits;
+ V8 byte[4];
+ V32 word;
+} DMA_RXTX_ENABLE, DMA_RX_DELETE,
+ DMA_INT_STATUS, DMA_INT_MASK,
+ DMA_RX_LEVEL_STATUS, DMA_RX_LEVEL_INT_MASK;
+
+/* 1 dword */
+typedef union _tag_dma_rx_timer{
+ struct {
+ V32 res0:8; /* bits 32-24 */
+ V32 res1:7; /* bits 23-17 */
+ V32 enable:1; /* bit 16 */
+ V32 value:16; /* bits 15-0 */
+ } _be_s_bits;
+ struct {
+ /* crosses byte boundary. must use swap. */
+ V32 s_value:16; /* bits 7-0,15-8 */
+ V32 enable:1; /* bit 16 */
+ V32 res1:7; /* bits 23-17 */
+ V32 res0:8; /* bits 32-24 */
+ } _be_bits;
+ struct {
+ V32 value:16; /* bits 0-15 */
+ V32 enable:1; /* bit 16 */
+ V32 res1:7; /* bits 17-23 */
+ V32 res0:8; /* bits 24-32 */
+ } _le_bits;
+ V8 byte[4];
+ V32 word;
+} DMA_RX_TIMER;
+
+/* NOTE!!!: 2 dwords */
+typedef struct _tag_dma_desc_level{
+ union {
+ struct {
+ V32 res1:8; /* bits 31-24 */
+ V32 res0:7; /* bits 23-17 */
+ V32 write:1; /* bit 16 */
+ V32 thresh:8; /* bits 15-8 */
+ V32 level:8; /* bits 7-0 */
+ } _be_s_bits;
+ struct {
+ V32 level:8; /* bits 7-0 */
+ V32 thresh:8; /* bits 15-8 */
+ V32 res0:7; /* bits 30-17 */
+ V32 write:1; /* bit 16 */
+ V32 res1:8; /* bits 31-24 */
+ } _be_bits;
+ struct {
+ V32 level:8; /* bits 0-7 */
+ V32 thresh:8; /* bits 8-15 */
+ V32 write:1; /* bit 16 */
+ V32 res0:7; /* bit 17-30 */
+ V32 res1:8; /* bits 24-31 */
+ } _le_bits;
+ V8 byte[4];
+ V32 word;
+ } desc;
+ V32 pad1;
+} DMA_DESC_LEVEL;
+
+typedef struct _tag_pbb_dma_reg_map {
+ /* 0-15 (0x000-0x078) */
+ DMA_DESCRIPTOR_RING rx_desc[8]; /* 4 dwords each, 128 bytes tot. */
+
+ /* 16-31 (0x080-0x0f8) */
+ DMA_DESCRIPTOR_RING tx_desc[8]; /* 4 dwords each, 128 bytes tot. */
+
+ /* 32/33 (0x100/0x108) */
+ V32 reserved_32;
+ V32 pad_32;
+ V32 reserved_33;
+ V32 pad_33;
+
+ /* 34 (0x110) */
+ DMA_RXTX_ENABLE rxtx_enable;
+ V32 pad_34;
+
+ /* 35 (0x118) */
+ DMA_RX_DELETE rx_delete;
+ V32 pad_35;
+
+ /* 36-38 (0x120-0x130) */
+ DMA_INT_STATUS status;
+ V32 pad_36;
+ DMA_INT_STATUS last_status;
+ V32 pad_37;
+ DMA_INT_MASK int_mask;
+ V32 pad_38;
+
+ /* 39/40 (0x138/0x140) */
+ union {
+ /* NOTE!! 4 dwords */
+ struct {
+ V32 channel_3:8;
+ V32 channel_2:8;
+ V32 channel_1:8;
+ V32 channel_0:8;
+ V32 pad1;
+ V32 channel_7:8;
+ V32 channel_6:8;
+ V32 channel_5:8;
+ V32 channel_4:8;
+ V32 pad3;
+ } _be_s_bits;
+ struct {
+ V32 channel_0:8;
+ V32 channel_1:8;
+ V32 channel_2:8;
+ V32 channel_3:8;
+ V32 pad1;
+ V32 channel_4:8;
+ V32 channel_5:8;
+ V32 channel_6:8;
+ V32 channel_7:8;
+ V32 pad3;
+ } _be_bits, _le_bits;
+ V8 byte[16];
+ V32 word[4];
+ } rx_size;
+
+ /* 41/42 (0x148/0x150) */
+ V32 reserved_41;
+ V32 pad_41;
+ V32 reserved_42;
+ V32 pad_42;
+
+ /* 43/44 (0x158/0x160) */
+ DMA_RX_LEVEL_STATUS rx_level_status;
+ V32 pad_43;
+ DMA_RX_LEVEL_INT_MASK rx_level_int_mask;
+ V32 pad_44;
+
+ /* 45 (0x168) */
+ DMA_RX_TIMER rx_timer;
+ V32 pad_45;
+
+ /* 46 (0x170) */
+ V32 reserved_46;
+ V32 pad_46;
+
+ /* 47 (0x178) */
+ V32 mbox_status;
+ V32 pad_47;
+
+ /* 48/49 (0x180/0x188) */
+ V32 mbox_out;
+ V32 pad_48;
+ V32 mbox_in;
+ V32 pad_49;
+
+ /* 50 (0x190) */
+ V32 config;
+ V32 pad_50;
+
+ /* 51/52 (0x198/0x1a0) */
+ V32 c2a_ctr;
+ V32 pad_51;
+ V32 a2c_ctr;
+ V32 pad_52;
+
+ /* 53 (0x1a8) */
+ union {
+ struct {
+ V32 rev_major:8; /* bits 31-24 */
+ V32 rev_minor:8; /* bits 23-16 */
+ V32 reserved:16; /* bits 15-0 */
+ } _be_s_bits;
+ struct {
+ V32 s_reserved:16; /* bits 7-0, 15-8 */
+ V32 rev_minor:8; /* bits 23-16 */
+ V32 rev_major:8; /* bits 31-24 */
+ } _be_bits;
+ struct {
+ V32 reserved:16; /* bits 0-15 */
+ V32 rev_minor:8; /* bits 16-23 */
+ V32 rev_major:8; /* bits 24-31 */
+ } _le_bits;
+ V8 byte[4];
+ V32 word;
+ } version;
+ V32 pad_53;
+
+ /* 54-59 (0x1b0-0x1d8) */
+ V32 debug_54;
+ V32 pad_54;
+ V32 debug_55;
+ V32 pad_55;
+ V32 debug_56;
+ V32 pad_56;
+ V32 debug_57;
+ V32 pad_57;
+ V32 debug_58;
+ V32 pad_58;
+ V32 debug_59;
+ V32 pad_59;
+
+ /* 60 (0x1e0) */
+ V32 timestamp;
+ V32 pad_60;
+
+ /* 61-63 (0x1e8-0x1f8) */
+ V32 debug_61;
+ V32 pad_61;
+ V32 debug_62;
+ V32 pad_62;
+ V32 debug_63;
+ V32 pad_63;
+
+ /* 64-71 (0x200 - 0x238) */
+ DMA_DESC_LEVEL rx_desc_level[8]; /* 2 dwords each, 32 bytes tot. */
+
+ /* 72-98 (0x240 - 0x2f8) */
+ /* reserved */
+
+ /* 96-127 (0x300 - 0x3f8) */
+ /* mirrors (0x100 - 0x1f8) */
+
+} PBB_DMA_REG_MAP;
+
+
+#endif /* ZUMA_PBB_H */