Merge tag 'u-boot-stm32-mcu-20190423' of https://github.com/pchotard/u-boot
STM32 MCUs update:
- DT rework and alignment with DT kernel v4.20
- mmc: arm_pl180_mmci: Synchronize compatible with kernel v4.20
- mmc: stm32_sdmmc2: Synchronize properties with kernel v4.20
- configs: update for F746/769 boards
diff --git a/.travis.yml b/.travis.yml
index eb531f1..951b6a3 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -34,6 +34,7 @@
- liblz4-tool
- libisl15
- clang-7
+ - srecord
install:
# Clone uboot-test-hooks
diff --git a/MAINTAINERS b/MAINTAINERS
index aa4b3bc..8651f69 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -86,6 +86,7 @@
S: Maintained
T: git git://git.denx.de/u-boot-arm.git
F: arch/arm/
+F: cmd/arm/
ARM ALTERA SOCFPGA
M: Marek Vasut <marex@denx.de>
@@ -100,7 +101,7 @@
T: git git://git.denx.de/u-boot-amlogic.git
F: arch/arm/mach-meson/
F: arch/arm/include/asm/arch-meson/
-F: drivers/clk/clk_meson*
+F: drivers/clk/meson/
F: drivers/serial/serial_meson.c
F: drivers/reset/reset-meson.c
F: drivers/i2c/meson_i2c.c
@@ -677,6 +678,7 @@
S: Maintained
T: git git://git.denx.de/u-boot-riscv.git
F: arch/riscv/
+F: cmd/riscv/
F: tools/prelink-riscv.c
ROCKUSB
@@ -788,6 +790,7 @@
S: Maintained
T: git git://git.denx.de/u-boot-x86.git
F: arch/x86/
+F: cmd/x86/
XTENSA
M: Max Filippov <jcmvbkbc@gmail.com>
diff --git a/Makefile b/Makefile
index 66a09ac..f2c7bb6 100644
--- a/Makefile
+++ b/Makefile
@@ -1977,6 +1977,13 @@
$(build)=$(build-dir) $(@:.ko=.o)
$(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modpost
+quiet_cmd_genenv = GENENV $@
+cmd_genenv = $(OBJCOPY) --dump-section .rodata.default_environment=$@ env/common.o; \
+ sed --in-place -e 's/\x00/\x0A/g' $@
+
+u-boot-initial-env: u-boot.bin
+ $(call if_changed,genenv)
+
# Consistency checks
# ---------------------------------------------------------------------------
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index a5f5433..b349b13 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -19,7 +19,9 @@
obj-y += cache.o
obj-y += tlb.o
obj-y += transition.o
+ifndef CONFIG_ARMV8_PSCI
obj-y += fwcall.o
+endif
obj-y += cpu-dt.o
obj-$(CONFIG_ARM_SMCCC) += smccc-call.o
diff --git a/arch/arm/cpu/armv8/fwcall.c b/arch/arm/cpu/armv8/fwcall.c
index 9957c29..b0aca1b 100644
--- a/arch/arm/cpu/armv8/fwcall.c
+++ b/arch/arm/cpu/armv8/fwcall.c
@@ -28,7 +28,6 @@
"ldr x4, %4\n"
"ldr x5, %5\n"
"ldr x6, %6\n"
- "ldr x7, %7\n"
"hvc #0\n"
"str x0, %0\n"
"str x1, %1\n"
@@ -37,7 +36,7 @@
: "+m" (args->regs[0]), "+m" (args->regs[1]),
"+m" (args->regs[2]), "+m" (args->regs[3])
: "m" (args->regs[4]), "m" (args->regs[5]),
- "m" (args->regs[6]), "m" (args->regs[7])
+ "m" (args->regs[6])
: "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
"x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
"x16", "x17");
diff --git a/arch/arm/cpu/armv8/psci.S b/arch/arm/cpu/armv8/psci.S
index 358df8f..7ffc8db 100644
--- a/arch/arm/cpu/armv8/psci.S
+++ b/arch/arm/cpu/armv8/psci.S
@@ -8,6 +8,7 @@
#include <config.h>
#include <linux/linkage.h>
#include <asm/psci.h>
+#include <asm/secure.h>
/* Default PSCI function, return -1, Not Implemented */
#define PSCI_DEFAULT(__fn) \
@@ -19,8 +20,8 @@
/* PSCI function and ID table definition*/
#define PSCI_TABLE(__id, __fn) \
- .word __id; \
- .word __fn
+ .quad __id; \
+ .quad __fn
.pushsection ._secure.text, "ax"
@@ -132,33 +133,52 @@
/* Caller must put PSCI function-ID table base in x9 */
handle_psci:
psci_enter
-1: ldr x10, [x9] /* Load PSCI function table */
- ubfx x11, x10, #32, #32
- ubfx x10, x10, #0, #32
+1: ldr x10, [x9] /* Load PSCI function table */
cbz x10, 3f /* If reach the end, bail out */
cmp x10, x0
b.eq 2f /* PSCI function found */
- add x9, x9, #8 /* If not match, try next entry */
+ add x9, x9, #16 /* If not match, try next entry */
b 1b
-2: blr x11 /* Call PSCI function */
+2: ldr x11, [x9, #8] /* Load PSCI function */
+ blr x11 /* Call PSCI function */
psci_return
3: mov x0, #ARM_PSCI_RET_NI
psci_return
-unknown_smc_id:
- ldr x0, =0xFFFFFFFF
+/*
+ * Handle SiP service functions defined in SiP service function table.
+ * Use DECLARE_SECURE_SVC(_name, _id, _fn) to add platform specific SiP
+ * service function into the SiP service function table.
+ * SiP service function table is located in '._secure_svc_tbl_entries' section,
+ * which is next to '._secure.text' section.
+ */
+handle_svc:
+ adr x9, __secure_svc_tbl_start
+ adr x10, __secure_svc_tbl_end
+ subs x12, x10, x9 /* Get number of entries in table */
+ b.eq 2f /* Make sure SiP function table is not empty */
+ psci_enter
+1: ldr x10, [x9] /* Load SiP function table */
+ ldr x11, [x9, #8]
+ cmp w10, w0
+ b.eq 2b /* SiP service function found */
+ add x9, x9, #SECURE_SVC_TBL_OFFSET /* Move to next entry */
+ subs x12, x12, #SECURE_SVC_TBL_OFFSET
+ b.eq 3b /* If reach the end, bail out */
+ b 1b
+2: ldr x0, =0xFFFFFFFF
eret
handle_smc32:
/* SMC function ID 0x84000000-0x8400001F: 32 bits PSCI */
ldr w9, =0x8400001F
cmp w0, w9
- b.gt unknown_smc_id
+ b.gt handle_svc
ldr w9, =0x84000000
cmp w0, w9
- b.lt unknown_smc_id
+ b.lt handle_svc
adr x9, _psci_32_table
b handle_psci
@@ -171,10 +191,10 @@
/* SMC function ID 0xC4000000-0xC400001F: 64 bits PSCI */
ldr x9, =0xC400001F
cmp x0, x9
- b.gt unknown_smc_id
+ b.gt handle_svc
ldr x9, =0xC4000000
cmp x0, x9
- b.lt unknown_smc_id
+ b.lt handle_svc
adr x9, _psci_64_table
b handle_psci
diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds
index 53de80f..2554980 100644
--- a/arch/arm/cpu/armv8/u-boot.lds
+++ b/arch/arm/cpu/armv8/u-boot.lds
@@ -58,6 +58,10 @@
AT(ADDR(.__secure_start) + SIZEOF(.__secure_start))
{
*(._secure.text)
+ . = ALIGN(8);
+ __secure_svc_tbl_start = .;
+ KEEP(*(._secure_svc_tbl_entries))
+ __secure_svc_tbl_end = .;
}
.secure_data : AT(LOADADDR(.secure_text) + SIZEOF(.secure_text))
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0aee8df..1452fd2 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -97,11 +97,15 @@
meson-gxbb-nanopi-k2.dtb \
meson-gxbb-odroidc2.dtb \
meson-gxbb-nanopi-k2.dtb \
+ meson-gxbb-p200.dtb \
+ meson-gxbb-p201.dtb \
meson-gxl-s905x-p212.dtb \
+ meson-gxl-s805x-libretech-ac.dtb \
meson-gxl-s905x-libretech-cc.dtb \
meson-gxl-s905x-khadas-vim.dtb \
meson-gxm-khadas-vim2.dtb \
- meson-axg-s400.dtb
+ meson-axg-s400.dtb \
+ meson-g12a-u200.dtb
dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
tegra20-paz00.dtb \
@@ -657,6 +661,9 @@
dtb-$(CONFIG_TARGET_SAMA5D27_SOM1_EK) += \
at91-sama5d27_som1_ek.dtb
+dtb-$(CONFIG_TARGET_SAMA5D2_ICP) += \
+ at91-sama5d2_icp.dtb
+
dtb-$(CONFIG_TARGET_SAMA5D3XEK) += \
sama5d31ek.dtb \
sama5d33ek.dtb \
diff --git a/arch/arm/dts/at91-sama5d2_icp-u-boot.dtsi b/arch/arm/dts/at91-sama5d2_icp-u-boot.dtsi
new file mode 100644
index 0000000..347fa81
--- /dev/null
+++ b/arch/arm/dts/at91-sama5d2_icp-u-boot.dtsi
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * at91-sama5d2_icp-for-uboot.dtsi - Device Tree file for SAMA5D2 ICP board
+ * SAMA5D2 Industrial Connectivity Platform
+ *
+ * Copyright (c) 2019, Microchip Technology Inc. and its subsidiaries
+ * 2019, Eugen Hristev <eugen.hristev@microchip.com>
+ */
+
+/ {
+ chosen {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&sdmmc0 {
+ u-boot,dm-pre-reloc;
+};
+
+&uart0 { /* mikrobus1 uart */
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_sdmmc0_default {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_mikrobus1_uart {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/at91-sama5d2_icp.dts b/arch/arm/dts/at91-sama5d2_icp.dts
new file mode 100644
index 0000000..cae8748
--- /dev/null
+++ b/arch/arm/dts/at91-sama5d2_icp.dts
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * at91-sama5d2_icp.dts - Device Tree file for SAMA5D2 ICP board
+ * SAMA5D2 Industrial Connectivity Board
+ *
+ * Copyright (c) 2018, Microchip Technology Inc.
+ * 2018, Eugen Hristev <eugen.hristev@microchip.com>
+ */
+/dts-v1/;
+#include "sama5d2.dtsi"
+#include "sama5d2-pinfunc.h"
+
+/ {
+ model = "Microchip SAMA5D2 ICP";
+ compatible = "atmel,sama5d2-icp", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5";
+
+ aliases {
+ serial0 = &uart0;
+ i2c1 = &i2c1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ ahb {
+
+ sdmmc0: sdio-host@a0000000 {
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdmmc0_default>;
+ status = "okay";
+ };
+
+ apb {
+ uart0: serial@f801c000 { /* mikrobus1 uart */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mikrobus1_uart>;
+ status = "okay";
+ };
+
+ macb0: ethernet@f8008000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq &pinctrl_macb0_rst>;
+ phy-mode = "internal";
+ status = "okay";
+ };
+
+ i2c1: i2c@fc028000 {
+ dmas = <0>, <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+
+ eeprom@52 {
+ compatible = "atmel,24c32";
+ reg = <0x52>;
+ pagesize = <16>;
+ };
+
+ eeprom@53 {
+ compatible = "atmel,24c32";
+ reg = <0x53>;
+ pagesize = <16>;
+ };
+ };
+ pioA: gpio@fc038000 {
+ status = "okay";
+ pinctrl {
+ pinctrl_i2c1_default: i2c1_default {
+ pinmux = <PIN_PD19__TWD1>,
+ <PIN_PD20__TWCK1>;
+ bias-disable;
+ };
+
+ pinctrl_macb0_rmii: macb0_rmii {
+ pinmux = <PIN_PD1__GRXCK>,
+ <PIN_PD2__GTXER>,
+ <PIN_PD5__GRX2>,
+ <PIN_PD6__GRX3>,
+ <PIN_PD7__GTX2>,
+ <PIN_PD8__GTX3>,
+ <PIN_PD9__GTXCK>,
+ <PIN_PD10__GTXEN>,
+ <PIN_PD11__GRXDV>,
+ <PIN_PD12__GRXER>,
+ <PIN_PD13__GRX0>,
+ <PIN_PD14__GRX1>,
+ <PIN_PD15__GTX0>,
+ <PIN_PD16__GTX1>,
+ <PIN_PD17__GMDC>,
+ <PIN_PD18__GMDIO>;
+ bias-disable;
+ };
+
+ pinctrl_macb0_phy_irq: macb0_phy_irq {
+ pinmux = <PIN_PD3__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_macb0_rst: macb0_sw_rst {
+ pinmux = <PIN_PD4__GPIO>;
+ bias-pull-up;
+ };
+
+ pinctrl_sdmmc0_default: sdmmc0_default {
+ pinmux = <PIN_PA1__SDMMC0_CMD>,
+ <PIN_PA2__SDMMC0_DAT0>,
+ <PIN_PA3__SDMMC0_DAT1>,
+ <PIN_PA4__SDMMC0_DAT2>,
+ <PIN_PA5__SDMMC0_DAT3>,
+ <PIN_PA0__SDMMC0_CK>,
+ <PIN_PA13__SDMMC0_CD>;
+ bias-disable;
+ };
+
+ pinctrl_mikrobus1_uart: mikrobus1_uart {
+ pinmux = <PIN_PB26__URXD0>,
+ <PIN_PB27__UTXD0>;
+ bias-disable;
+ };
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/at91sam9260.dtsi b/arch/arm/dts/at91sam9260.dtsi
index 476ad1d..800d96e 100644
--- a/arch/arm/dts/at91sam9260.dtsi
+++ b/arch/arm/dts/at91sam9260.dtsi
@@ -437,7 +437,7 @@
u-boot,dm-pre-reloc;
};
- pinctrl@fffff400 {
+ pinctrl: pinctrl@fffff400 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
@@ -978,7 +978,7 @@
};
};
- rtc@fffffd20 {
+ rtc: rtc@fffffd20 {
compatible = "atmel,at91sam9260-rtt";
reg = <0xfffffd20 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
@@ -986,7 +986,7 @@
status = "disabled";
};
- watchdog@fffffd40 {
+ watchdog: watchdog@fffffd40 {
compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffd40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
diff --git a/arch/arm/dts/bcm63158.dtsi b/arch/arm/dts/bcm63158.dtsi
index 4f41f62..4b2eaee 100644
--- a/arch/arm/dts/bcm63158.dtsi
+++ b/arch/arm/dts/bcm63158.dtsi
@@ -82,6 +82,13 @@
status = "disabled";
};
+ leds: led-controller@ff800800 {
+ compatible = "brcm,bcm6858-leds";
+ reg = <0x0 0xff800800 0x0 0xe4>;
+
+ status = "disabled";
+ };
+
wdt1: watchdog@ff800480 {
compatible = "brcm,bcm6345-wdt";
reg = <0x0 0xff800480 0x0 0x14>;
@@ -178,5 +185,18 @@
status = "disabled";
};
+
+ nand: nand-controller@ff801800 {
+ compatible = "brcm,nand-bcm63158",
+ "brcm,brcmnand-v5.0",
+ "brcm,brcmnand";
+ reg-names = "nand", "nand-int-base", "nand-cache";
+ reg = <0x0 0xff801800 0x0 0x180>,
+ <0x0 0xff802000 0x0 0x10>,
+ <0x0 0xff801c00 0x0 0x200>;
+ parameter-page-big-endian = <0>;
+
+ status = "disabled";
+ };
};
};
diff --git a/arch/arm/dts/bcm6858.dtsi b/arch/arm/dts/bcm6858.dtsi
index 5d5e64d..76ba0ea 100644
--- a/arch/arm/dts/bcm6858.dtsi
+++ b/arch/arm/dts/bcm6858.dtsi
@@ -82,6 +82,13 @@
status = "disabled";
};
+ leds: led-controller@ff800800 {
+ compatible = "brcm,bcm6858-leds";
+ reg = <0x0 0xff800800 0x0 0xe4>;
+
+ status = "disabled";
+ };
+
wdt1: watchdog@ff802780 {
compatible = "brcm,bcm6345-wdt";
reg = <0x0 0xff802780 0x0 0x14>;
@@ -178,5 +185,18 @@
status = "disabled";
};
+
+ nand: nand-controller@ff801800 {
+ compatible = "brcm,nand-bcm6858",
+ "brcm,brcmnand-v5.0",
+ "brcm,brcmnand";
+ reg-names = "nand", "nand-int-base", "nand-cache";
+ reg = <0x0 0xff801800 0x0 0x180>,
+ <0x0 0xff802000 0x0 0x10>,
+ <0x0 0xff801c00 0x0 0x200>;
+ parameter-page-big-endian = <0>;
+
+ status = "disabled";
+ };
};
};
diff --git a/arch/arm/dts/bcm963158.dts b/arch/arm/dts/bcm963158.dts
index b5c825b..8565944 100644
--- a/arch/arm/dts/bcm963158.dts
+++ b/arch/arm/dts/bcm963158.dts
@@ -61,3 +61,67 @@
&gpio7 {
status = "okay";
};
+
+&nand {
+ status = "okay";
+ write-protect = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nandcs@0 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ brcm,nand-oob-sector-size = <16>;
+ };
+};
+
+&leds {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ brcm,serial-led-en-pol;
+ brcm,serial-led-data-ppol;
+
+ led@16 {
+ reg = <16>;
+ label = "red:dsl2";
+ };
+
+ led@17 {
+ reg = <17>;
+ label = "green:dsl1";
+ };
+
+ led@18 {
+ reg = <18>;
+ label = "green:fxs2";
+ };
+
+ led@19 {
+ reg = <19>;
+ label = "green:fxs1";
+ };
+
+ led@26 {
+ reg = <26>;
+ label = "green:wan1_act";
+ };
+
+ led@27 {
+ reg = <27>;
+ label = "green:wps";
+ };
+
+ led@28 {
+ reg = <28>;
+ active-low;
+ label = "green:aggregate_act";
+ };
+
+ led@29 {
+ reg = <29>;
+ label = "green:aggregate_link";
+ };
+};
diff --git a/arch/arm/dts/bcm968580xref.dts b/arch/arm/dts/bcm968580xref.dts
index 15febb0..861e989 100644
--- a/arch/arm/dts/bcm968580xref.dts
+++ b/arch/arm/dts/bcm968580xref.dts
@@ -61,3 +61,66 @@
&gpio7 {
status = "okay";
};
+
+&nand {
+ status = "okay";
+ write-protect = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nandcs@0 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ brcm,nand-oob-sector-size = <16>;
+ };
+};
+
+&leds {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ brcm,serial-led-en-pol;
+ brcm,serial-led-data-ppol;
+
+ led@2 {
+ reg = <2>;
+ label = "green:inet";
+ };
+
+ led@5 {
+ reg = <5>;
+ label = "red:alarm";
+ };
+
+ led@8 {
+ reg = <8>;
+ label = "green:wlan_link";
+ };
+
+ led@11 {
+ reg = <11>;
+ label = "green:fxs1";
+ };
+
+ led@14 {
+ reg = <14>;
+ label = "green:fxs2";
+ };
+
+ led@15 {
+ reg = <15>;
+ label = "green:usb0";
+ };
+
+ led@16 {
+ reg = <16>;
+ label = "green:usb1";
+ };
+
+ led@17 {
+ reg = <17>;
+ label = "green:wps";
+ };
+};
diff --git a/arch/arm/dts/hi3798cv200-u-boot.dtsi b/arch/arm/dts/hi3798cv200-u-boot.dtsi
index 7844c52..2de06d9 100644
--- a/arch/arm/dts/hi3798cv200-u-boot.dtsi
+++ b/arch/arm/dts/hi3798cv200-u-boot.dtsi
@@ -8,7 +8,15 @@
* (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
*/
+#include <dt-bindings/reset/ti-syscon.h>
+
&soc {
+ rst: reset-controller@8a22000 {
+ compatible = "hisilicon,hi3798cv200-reset";
+ reg = <0x8a22000 0x1000>;
+ #reset-cells = <3>;
+ };
+
usb2: ehci@9890000 {
compatible = "generic-ehci";
reg = <0x9890000 0x100>;
@@ -16,6 +24,12 @@
};
};
+&gmac1 {
+ resets = <&rst 0xcc 9 ASSERT_SET>,
+ <&rst 0xcc 11 ASSERT_SET>,
+ <&rst 0xcc 13 DEASSERT_SET>;
+};
+
&uart0 {
clock = <75000000>;
status = "okay";
diff --git a/arch/arm/dts/meson-g12a-u200.dts b/arch/arm/dts/meson-g12a-u200.dts
new file mode 100644
index 0000000..c44dbdd
--- /dev/null
+++ b/arch/arm/dts/meson-g12a-u200.dts
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "meson-g12a.dtsi"
+
+/ {
+ compatible = "amlogic,u200", "amlogic,g12a";
+ model = "Amlogic Meson G12A U200 Development Board";
+
+ aliases {
+ serial0 = &uart_AO;
+ };
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+};
+
+&uart_AO {
+ status = "okay";
+};
+
diff --git a/arch/arm/dts/meson-g12a.dtsi b/arch/arm/dts/meson-g12a.dtsi
new file mode 100644
index 0000000..17c6217
--- /dev/null
+++ b/arch/arm/dts/meson-g12a.dtsi
@@ -0,0 +1,192 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "amlogic,g12a";
+
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <0x2>;
+ #size-cells = <0x0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ };
+
+ l2: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 3 MiB reserved for ARM Trusted Firmware (BL31) */
+ secmon_reserved: secmon@5000000 {
+ reg = <0x0 0x05000000 0x0 0x300000>;
+ no-map;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ apb: bus@ff600000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xff600000 0x0 0x200000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>;
+
+ periphs: bus@34400 {
+ compatible = "simple-bus";
+ reg = <0x0 0x34400 0x0 0x400>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>;
+ };
+
+ hiu: bus@3c000 {
+ compatible = "simple-bus";
+ reg = <0x0 0x3c000 0x0 0x1400>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>;
+
+ hhi: system-controller@0 {
+ compatible = "amlogic,meson-gx-hhi-sysctrl",
+ "simple-mfd", "syscon";
+ reg = <0 0 0 0x400>;
+
+ clkc: clock-controller {
+ compatible = "amlogic,g12a-clkc";
+ #clock-cells = <1>;
+ clocks = <&xtal>;
+ clock-names = "xtal";
+ };
+ };
+ };
+ };
+
+ aobus: bus@ff800000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xff800000 0x0 0x100000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
+
+ uart_AO: serial@3000 {
+ compatible = "amlogic,meson-gx-uart",
+ "amlogic,meson-ao-uart";
+ reg = <0x0 0x3000 0x0 0x18>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>, <&xtal>, <&xtal>;
+ clock-names = "xtal", "pclk", "baud";
+ status = "disabled";
+ };
+
+ uart_AO_B: serial@4000 {
+ compatible = "amlogic,meson-gx-uart",
+ "amlogic,meson-ao-uart";
+ reg = <0x0 0x4000 0x0 0x18>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>, <&xtal>, <&xtal>;
+ clock-names = "xtal", "pclk", "baud";
+ status = "disabled";
+ };
+ };
+
+ gic: interrupt-controller@ffc01000 {
+ compatible = "arm,gic-400";
+ reg = <0x0 0xffc01000 0 0x1000>,
+ <0x0 0xffc02000 0 0x2000>,
+ <0x0 0xffc04000 0 0x2000>,
+ <0x0 0xffc06000 0 0x2000>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ };
+
+ cbus: bus@ffd00000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xffd00000 0x0 0x100000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>;
+
+ clk_msr: clock-measure@18000 {
+ compatible = "amlogic,meson-g12a-clk-measure";
+ reg = <0x0 0x18000 0x0 0x10>;
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ xtal: xtal-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xtal";
+ #clock-cells = <0>;
+ };
+
+};
diff --git a/arch/arm/dts/meson-gxbb-p200-u-boot.dtsi b/arch/arm/dts/meson-gxbb-p200-u-boot.dtsi
new file mode 100644
index 0000000..c35158d
--- /dev/null
+++ b/arch/arm/dts/meson-gxbb-p200-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include "meson-gx-u-boot.dtsi"
diff --git a/arch/arm/dts/meson-gxbb-p200.dts b/arch/arm/dts/meson-gxbb-p200.dts
new file mode 100644
index 0000000..9d2406a
--- /dev/null
+++ b/arch/arm/dts/meson-gxbb-p200.dts
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2016 Andreas Färber
+ * Copyright (c) 2016 BayLibre, Inc.
+ * Author: Kevin Hilman <khilman@kernel.org>
+ */
+
+/dts-v1/;
+
+#include "meson-gxbb-p20x.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+ compatible = "amlogic,p200", "amlogic,meson-gxbb";
+ model = "Amlogic Meson GXBB P200 Development Board";
+
+ avdd18_usb_adc: regulator-avdd18_usb_adc {
+ compatible = "regulator-fixed";
+ regulator-name = "AVDD18_USB_ADC";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ adc_keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 0>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+
+ button-home {
+ label = "Home";
+ linux,code = <KEY_HOME>;
+ press-threshold-microvolt = <900000>; /* 50% */
+ };
+
+ button-esc {
+ label = "Esc";
+ linux,code = <KEY_ESC>;
+ press-threshold-microvolt = <684000>; /* 38% */
+ };
+
+ button-up {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ press-threshold-microvolt = <468000>; /* 26% */
+ };
+
+ button-down {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ press-threshold-microvolt = <252000>; /* 14% */
+ };
+
+ button-menu {
+ label = "Menu";
+ linux,code = <KEY_MENU>;
+ press-threshold-microvolt = <0>; /* 0% */
+ };
+ };
+};
+
+ðmac {
+ status = "okay";
+ pinctrl-0 = <ð_rgmii_pins>;
+ pinctrl-names = "default";
+ phy-handle = <ð_phy0>;
+ phy-mode = "rgmii";
+
+ amlogic,tx-delay-ns = <2>;
+
+ snps,reset-gpio = <&gpio GPIOZ_14 0>;
+ snps,reset-delays-us = <0 10000 1000000>;
+ snps,reset-active-low;
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eth_phy0: ethernet-phy@3 {
+ /* Micrel KSZ9031 (0x00221620) */
+ reg = <3>;
+ interrupt-parent = <&gpio_intc>;
+ /* MAC_INTR on GPIOZ_15 */
+ interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
+ };
+ };
+};
+
+&i2c_B {
+ status = "okay";
+ pinctrl-0 = <&i2c_b_pins>;
+ pinctrl-names = "default";
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&avdd18_usb_adc>;
+};
diff --git a/arch/arm/dts/meson-gxbb-p201-u-boot.dtsi b/arch/arm/dts/meson-gxbb-p201-u-boot.dtsi
new file mode 100644
index 0000000..c35158d
--- /dev/null
+++ b/arch/arm/dts/meson-gxbb-p201-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include "meson-gx-u-boot.dtsi"
diff --git a/arch/arm/dts/meson-gxbb-p201.dts b/arch/arm/dts/meson-gxbb-p201.dts
new file mode 100644
index 0000000..56e0dd1
--- /dev/null
+++ b/arch/arm/dts/meson-gxbb-p201.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2016 Andreas Färber
+ * Copyright (c) 2016 BayLibre, Inc.
+ * Author: Kevin Hilman <khilman@kernel.org>
+ */
+
+/dts-v1/;
+
+#include "meson-gxbb-p20x.dtsi"
+
+/ {
+ compatible = "amlogic,p201", "amlogic,meson-gxbb";
+ model = "Amlogic Meson GXBB P201 Development Board";
+};
+
+ðmac {
+ status = "okay";
+ pinctrl-0 = <ð_rmii_pins>;
+ pinctrl-names = "default";
+ phy-mode = "rmii";
+
+ snps,reset-gpio = <&gpio GPIOZ_14 0>;
+ snps,reset-delays-us = <0 10000 1000000>;
+ snps,reset-active-low;
+};
diff --git a/arch/arm/dts/meson-gxbb-p20x.dtsi b/arch/arm/dts/meson-gxbb-p20x.dtsi
new file mode 100644
index 0000000..0be0f2a
--- /dev/null
+++ b/arch/arm/dts/meson-gxbb-p20x.dtsi
@@ -0,0 +1,247 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2016 Andreas Färber
+ * Copyright (c) 2016 BayLibre, Inc.
+ * Author: Kevin Hilman <khilman@kernel.org>
+ */
+
+#include "meson-gxbb.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart_AO;
+ ethernet0 = ðmac;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ usb_pwr: regulator-usb-pwrs {
+ compatible = "regulator-fixed";
+
+ regulator-name = "USB_PWR";
+
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+
+ /* signal name in schematic: USB_PWR_EN */
+ gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vddio_card: gpio-regulator {
+ compatible = "regulator-gpio";
+
+ regulator-name = "VDDIO_CARD";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+
+ /* Based on P200 schematics, signal CARD_1.8V/3.3V_CTR */
+ states = <1800000 0
+ 3300000 1>;
+
+ regulator-settling-time-up-us = <10000>;
+ regulator-settling-time-down-us = <150000>;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ cvbs_connector: cvbs-connector {
+ compatible = "composite-video-connector";
+
+ port {
+ cvbs_connector_in: endpoint {
+ remote-endpoint = <&cvbs_vdac_out>;
+ };
+ };
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+};
+
+&cec_AO {
+ status = "okay";
+ pinctrl-0 = <&ao_cec_pins>;
+ pinctrl-names = "default";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&cvbs_vdac_port {
+ cvbs_vdac_out: endpoint {
+ remote-endpoint = <&cvbs_connector_in>;
+ };
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
+ pinctrl-names = "default";
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+&ir {
+ status = "okay";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
+};
+
+&pwm_ef {
+ status = "okay";
+ pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&clkc CLKID_FCLK_DIV4>;
+ clock-names = "clkin0";
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "okay";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_card>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+&usb0_phy {
+ status = "okay";
+ phy-supply = <&usb_pwr>;
+};
+
+&usb1_phy {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts b/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
new file mode 100644
index 0000000..82b1c48
--- /dev/null
+++ b/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
@@ -0,0 +1,248 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ * Author: Jerome Brunet <jbrunet@baylibre.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+
+#include "meson-gxl-s905x.dtsi"
+
+/ {
+ compatible = "libretech,aml-s805x-ac", "amlogic,s805x",
+ "amlogic,meson-gxl";
+ model = "Libre Computer Board AML-S805X-AC";
+
+ aliases {
+ serial0 = &uart_AO;
+ ethernet0 = ðmac;
+ spi0 = &spifc;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ cvbs-connector {
+ /*
+ * The pads are present but no connector is soldered on
+ * 2J2, so keep this off by default.
+ */
+ status = "disabled";
+ compatible = "composite-video-connector";
+
+ port {
+ cvbs_connector_in: endpoint {
+ remote-endpoint = <&cvbs_vdac_out>;
+ };
+ };
+ };
+
+ dc_5v: regulator-dc_5v {
+ compatible = "regulator-fixed";
+ regulator-name = "DC_5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x20000000>;
+ };
+
+ vcck: regulator-vcck {
+ compatible = "regulator-fixed";
+ regulator-name = "VCCK";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_5v>;
+
+ /*
+ * This is controlled by GPIOAO_9 we reserve this but
+ * claiming it as done below reset the board anyway
+ * Need to investigate this
+ *
+ * gpio = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>;
+ * enable-active-high;
+ */
+ regulator-always-on;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_5v>;
+ regulator-always-on;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ regulator-always-on;
+ };
+};
+
+&cec_AO {
+ status = "okay";
+ pinctrl-0 = <&ao_cec_pins>;
+ pinctrl-names = "default";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&cvbs_vdac_port {
+ cvbs_vdac_out: endpoint {
+ remote-endpoint = <&cvbs_connector_in>;
+ };
+};
+
+ðmac {
+ status = "okay";
+};
+
+&internal_phy {
+ pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>;
+ pinctrl-names = "default";
+};
+
+&ir {
+ status = "okay";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
+ pinctrl-names = "default";
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+&gpio_ao {
+ gpio-line-names = "UART TX",
+ "UART RX",
+ "7J1 Header Pin31",
+ "", "", "", "",
+ "IR In",
+ "HDMI CEC",
+ "5V VCCK Regulator",
+ /* GPIO_TEST_N */
+ "";
+};
+
+&gpio {
+ gpio-line-names = /* Bank GPIOZ */
+ "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "",
+ "Eth Link LED", "Eth Activity LED",
+ /* Bank GPIOH */
+ "HDMI HPD", "HDMI SDA", "HDMI SCL",
+ "", "7J1 Header Pin13",
+ "7J1 Header Pin15",
+ "7J1 Header Pin7",
+ "7J1 Header Pin12",
+ "7J1 Header Pin16",
+ "7J1 Header Pin18",
+ /* Bank BOOT */
+ "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3",
+ "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7",
+ "eMMC Clk", "eMMC Reset", "eMMC CMD",
+ "SPI NOR MOSI", "SPI NOR MISO", "SPI NOR Clk",
+ "", "SPI NOR Chip Select",
+ /* Bank CARD */
+ "", "", "", "", "", "", "",
+ /* Bank GPIODV */
+ "", "", "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "", "", "",
+ "7J1 Header Pin27", "7J1 Header Pin28", "",
+ "7J1 Header Pin29",
+ "VCCK Regulator", "VDDEE Regulator",
+ /* Bank GPIOX */
+ "7J1 Header Pin22", "7J1 Header Pin26",
+ "7J1 Header Pin36", "7J1 Header Pin38",
+ "7J1 Header Pin40", "7J1 Header Pin37",
+ "7J1 Header Pin33", "7J1 Header Pin35",
+ "7J1 Header Pin19", "7J1 Header Pin21",
+ "7J1 Header Pin24", "7J1 Header Pin23",
+ "7J1 Header Pin8", "7J1 Header Pin10",
+ "", "", "7J1 Header Pin32", "", "",
+ /* Bank GPIOCLK */
+ "", "";
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ disable-wp;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+&spifc {
+ status = "okay";
+ pinctrl-0 = <&nor_pins>;
+ pinctrl-names = "default";
+
+ w25q32: spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <3000000>;
+ };
+};
+
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+&usb0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/meson-gxl.dtsi b/arch/arm/dts/meson-gxl.dtsi
index 8f0bb3c..d5c3d78 100644
--- a/arch/arm/dts/meson-gxl.dtsi
+++ b/arch/arm/dts/meson-gxl.dtsi
@@ -75,6 +75,10 @@
};
};
+&efuse {
+ clocks = <&clkc CLKID_EFUSE>;
+};
+
ðmac {
reg = <0x0 0xc9410000 0x0 0x10000
0x0 0xc8834540 0x0 0x4>;
@@ -112,6 +116,7 @@
mux {
groups = "uart_tx_ao_a", "uart_rx_ao_a";
function = "uart_ao";
+ bias-disable;
};
};
@@ -120,6 +125,7 @@
groups = "uart_cts_ao_a",
"uart_rts_ao_a";
function = "uart_ao";
+ bias-disable;
};
};
@@ -127,6 +133,7 @@
mux {
groups = "uart_tx_ao_b", "uart_rx_ao_b";
function = "uart_ao_b";
+ bias-disable;
};
};
@@ -134,6 +141,7 @@
mux {
groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
function = "uart_ao_b";
+ bias-disable;
};
};
@@ -142,6 +150,7 @@
groups = "uart_cts_ao_b",
"uart_rts_ao_b";
function = "uart_ao_b";
+ bias-disable;
};
};
@@ -149,6 +158,7 @@
mux {
groups = "remote_input_ao";
function = "remote_input_ao";
+ bias-disable;
};
};
@@ -157,6 +167,7 @@
groups = "i2c_sck_ao",
"i2c_sda_ao";
function = "i2c_ao";
+ bias-disable;
};
};
@@ -164,6 +175,7 @@
mux {
groups = "pwm_ao_a_3";
function = "pwm_ao_a";
+ bias-disable;
};
};
@@ -171,6 +183,7 @@
mux {
groups = "pwm_ao_a_8";
function = "pwm_ao_a";
+ bias-disable;
};
};
@@ -178,6 +191,7 @@
mux {
groups = "pwm_ao_b";
function = "pwm_ao_b";
+ bias-disable;
};
};
@@ -185,6 +199,7 @@
mux {
groups = "pwm_ao_b_6";
function = "pwm_ao_b";
+ bias-disable;
};
};
@@ -192,6 +207,7 @@
mux {
groups = "i2s_out_ch23_ao";
function = "i2s_out_ao";
+ bias-disable;
};
};
@@ -199,6 +215,7 @@
mux {
groups = "i2s_out_ch45_ao";
function = "i2s_out_ao";
+ bias-disable;
};
};
@@ -206,6 +223,7 @@
mux {
groups = "spdif_out_ao_6";
function = "spdif_out_ao";
+ bias-disable;
};
};
@@ -213,6 +231,7 @@
mux {
groups = "spdif_out_ao_9";
function = "spdif_out_ao";
+ bias-disable;
};
};
@@ -220,6 +239,7 @@
mux {
groups = "ao_cec";
function = "cec_ao";
+ bias-disable;
};
};
@@ -227,6 +247,7 @@
mux {
groups = "ee_cec";
function = "cec_ao";
+ bias-disable;
};
};
};
@@ -239,6 +260,8 @@
&clkc_AO {
compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
+ clocks = <&xtal>, <&clkc CLKID_CLK81>;
+ clock-names = "xtal", "mpeg-clk";
};
&gpio_intc {
@@ -263,6 +286,8 @@
clkc: clock-controller {
compatible = "amlogic,gxl-clkc";
#clock-cells = <1>;
+ clocks = <&xtal>;
+ clock-names = "xtal";
};
};
@@ -306,6 +331,7 @@
"emmc_cmd",
"emmc_clk";
function = "emmc";
+ bias-disable;
};
};
@@ -313,6 +339,7 @@
mux {
groups = "emmc_ds";
function = "emmc";
+ bias-disable;
};
};
@@ -320,9 +347,6 @@
mux {
groups = "BOOT_8";
function = "gpio_periphs";
- };
- cfg-pull-down {
- pins = "BOOT_8";
bias-pull-down;
};
};
@@ -334,6 +358,7 @@
"nor_c",
"nor_cs";
function = "nor";
+ bias-disable;
};
};
@@ -343,6 +368,7 @@
"spi_mosi",
"spi_sclk";
function = "spi";
+ bias-disable;
};
};
@@ -350,6 +376,7 @@
mux {
groups = "spi_ss0";
function = "spi";
+ bias-disable;
};
};
@@ -362,6 +389,7 @@
"sdcard_cmd",
"sdcard_clk";
function = "sdcard";
+ bias-disable;
};
};
@@ -369,9 +397,6 @@
mux {
groups = "CARD_2";
function = "gpio_periphs";
- };
- cfg-pull-down {
- pins = "CARD_2";
bias-pull-down;
};
};
@@ -385,6 +410,7 @@
"sdio_cmd",
"sdio_clk";
function = "sdio";
+ bias-disable;
};
};
@@ -392,9 +418,6 @@
mux {
groups = "GPIOX_4";
function = "gpio_periphs";
- };
- cfg-pull-down {
- pins = "GPIOX_4";
bias-pull-down;
};
};
@@ -403,6 +426,7 @@
mux {
groups = "sdio_irq";
function = "sdio";
+ bias-disable;
};
};
@@ -411,6 +435,7 @@
groups = "uart_tx_a",
"uart_rx_a";
function = "uart_a";
+ bias-disable;
};
};
@@ -419,6 +444,7 @@
groups = "uart_cts_a",
"uart_rts_a";
function = "uart_a";
+ bias-disable;
};
};
@@ -427,6 +453,7 @@
groups = "uart_tx_b",
"uart_rx_b";
function = "uart_b";
+ bias-disable;
};
};
@@ -435,6 +462,7 @@
groups = "uart_cts_b",
"uart_rts_b";
function = "uart_b";
+ bias-disable;
};
};
@@ -443,6 +471,7 @@
groups = "uart_tx_c",
"uart_rx_c";
function = "uart_c";
+ bias-disable;
};
};
@@ -451,6 +480,7 @@
groups = "uart_cts_c",
"uart_rts_c";
function = "uart_c";
+ bias-disable;
};
};
@@ -459,6 +489,7 @@
groups = "i2c_sck_a",
"i2c_sda_a";
function = "i2c_a";
+ bias-disable;
};
};
@@ -467,6 +498,7 @@
groups = "i2c_sck_b",
"i2c_sda_b";
function = "i2c_b";
+ bias-disable;
};
};
@@ -475,6 +507,7 @@
groups = "i2c_sck_c",
"i2c_sda_c";
function = "i2c_c";
+ bias-disable;
};
};
@@ -495,6 +528,7 @@
"eth_txd2",
"eth_txd3";
function = "eth";
+ bias-disable;
};
};
@@ -502,6 +536,7 @@
mux {
groups = "eth_link_led";
function = "eth_led";
+ bias-disable;
};
};
@@ -516,6 +551,7 @@
mux {
groups = "pwm_a";
function = "pwm_a";
+ bias-disable;
};
};
@@ -523,6 +559,7 @@
mux {
groups = "pwm_b";
function = "pwm_b";
+ bias-disable;
};
};
@@ -530,6 +567,7 @@
mux {
groups = "pwm_c";
function = "pwm_c";
+ bias-disable;
};
};
@@ -537,6 +575,7 @@
mux {
groups = "pwm_d";
function = "pwm_d";
+ bias-disable;
};
};
@@ -544,6 +583,7 @@
mux {
groups = "pwm_e";
function = "pwm_e";
+ bias-disable;
};
};
@@ -551,6 +591,7 @@
mux {
groups = "pwm_f_clk";
function = "pwm_f";
+ bias-disable;
};
};
@@ -558,6 +599,7 @@
mux {
groups = "pwm_f_x";
function = "pwm_f";
+ bias-disable;
};
};
@@ -565,6 +607,7 @@
mux {
groups = "hdmi_hpd";
function = "hdmi_hpd";
+ bias-disable;
};
};
@@ -572,6 +615,7 @@
mux {
groups = "hdmi_sda", "hdmi_scl";
function = "hdmi_i2c";
+ bias-disable;
};
};
@@ -579,6 +623,7 @@
mux {
groups = "i2s_am_clk";
function = "i2s_out";
+ bias-disable;
};
};
@@ -586,6 +631,7 @@
mux {
groups = "i2s_out_ao_clk";
function = "i2s_out";
+ bias-disable;
};
};
@@ -593,6 +639,7 @@
mux {
groups = "i2s_out_lr_clk";
function = "i2s_out";
+ bias-disable;
};
};
@@ -600,12 +647,14 @@
mux {
groups = "i2s_out_ch01";
function = "i2s_out";
+ bias-disable;
};
};
i2sout_ch23_z_pins: i2sout_ch23_z {
mux {
groups = "i2sout_ch23_z";
function = "i2s_out";
+ bias-disable;
};
};
@@ -613,6 +662,7 @@
mux {
groups = "i2sout_ch45_z";
function = "i2s_out";
+ bias-disable;
};
};
@@ -620,6 +670,7 @@
mux {
groups = "i2sout_ch67_z";
function = "i2s_out";
+ bias-disable;
};
};
@@ -627,6 +678,7 @@
mux {
groups = "spdif_out_h";
function = "spdif_out";
+ bias-disable;
};
};
};
diff --git a/arch/arm/dts/mt8516-u-boot.dtsi b/arch/arm/dts/mt8516-u-boot.dtsi
new file mode 100644
index 0000000..3c0d843
--- /dev/null
+++ b/arch/arm/dts/mt8516-u-boot.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2019 BayLibre, SAS
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+&infracfg {
+ u-boot,dm-pre-reloc;
+};
+
+&topckgen_ {
+ u-boot,dm-pre-reloc;
+};
+
+&topckgen_cg {
+ u-boot,dm-pre-reloc;
+};
+
+&apmixedsys {
+ u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/mt8516.dtsi b/arch/arm/dts/mt8516.dtsi
new file mode 100644
index 0000000..1c33582
--- /dev/null
+++ b/arch/arm/dts/mt8516.dtsi
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2019 BayLibre, SAS
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+#include <dt-bindings/clock/mt8516-clk.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "mediatek,mt8516";
+ interrupt-parent = <&sysirq>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "mediatek,mt8516-smp";
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x0>;
+ clock-frequency = <1300000000>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x1>;
+ clock-frequency = <1300000000>;
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x2>;
+ clock-frequency = <1300000000>;
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x3>;
+ clock-frequency = <1300000000>;
+ };
+ };
+
+ topckgen: clock-controller@10000000 {
+ compatible = "mediatek,mt8516-topckgen";
+ reg = <0x10000000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ topckgen_cg: clock-controller-cg@10000000 {
+ compatible = "mediatek,mt8516-topckgen-cg";
+ reg = <0x10000000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg: clock-controller@10001000 {
+ compatible = "mediatek,mt8516-infracfg";
+ reg = <0x10001000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ apmixedsys: clock-controller@10018000 {
+ compatible = "mediatek,mt8516-apmixedsys";
+ reg = <0x10018000 0x710>;
+ #clock-cells = <1>;
+ };
+
+ gic: interrupt-controller@10310000 {
+ compatible = "arm,gic-400";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0x10310000 0x1000>,
+ <0x10320000 0x1000>,
+ <0x10340000 0x2000>,
+ <0x10360000 0x2000>;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ sysirq: interrupt-controller@10200620 {
+ compatible = "mediatek,sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0x10200620 0x20>;
+ };
+
+ watchdog: watchdog@10007000 {
+ compatible = "mediatek,wdt";
+ reg = <0x10007000 0x1000>;
+ interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_FALLING>;
+ #reset-cells = <1>;
+ status = "disabled";
+ };
+
+ pinctrl: pinctrl@10005000 {
+ compatible = "mediatek,mt8516-pinctrl";
+ reg = <0x10005000 0x1000>;
+
+ gpio: gpio-controller {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ mmc0: mmc@11120000 {
+ compatible = "mediatek,mt8516-mmc";
+ reg = <0x11120000 0x1000>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen_cg CLK_TOP_MSDC0>,
+ <&topckgen CLK_TOP_AHB_INFRA_SEL>,
+ <&topckgen_cg CLK_TOP_MSDC0_INFRA>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
+ uart0: serial@11005000 {
+ compatible = "mediatek,hsuart";
+ reg = <0x11005000 0x1000>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_UART0_SEL>,
+ <&topckgen_cg CLK_TOP_UART0>;
+ clock-names = "baud","bus";
+ status = "disabled";
+ };
+};
diff --git a/arch/arm/dts/socfpga-common-u-boot.dtsi b/arch/arm/dts/socfpga-common-u-boot.dtsi
new file mode 100644
index 0000000..322c858
--- /dev/null
+++ b/arch/arm/dts/socfpga-common-u-boot.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (c) 2019 Simon Goldschmidt
+ */
+/{
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&rst {
+ u-boot,dm-pre-reloc;
+};
+
+&sdr {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index 2458d67..51a6a51 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -84,6 +84,7 @@
#dma-requests = <32>;
clocks = <&l4_main_clk>;
clock-names = "apb_pclk";
+ resets = <&rst DMA_RESET>;
};
};
@@ -100,6 +101,7 @@
reg = <0xffc00000 0x1000>;
interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
clocks = <&can0_clk>;
+ resets = <&rst CAN0_RESET>;
status = "disabled";
};
@@ -108,6 +110,7 @@
reg = <0xffc01000 0x1000>;
interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
clocks = <&can1_clk>;
+ resets = <&rst CAN1_RESET>;
status = "disabled";
};
@@ -585,6 +588,7 @@
compatible = "snps,dw-apb-gpio";
reg = <0xff708000 0x1000>;
clocks = <&l4_mp_clk>;
+ resets = <&rst GPIO0_RESET>;
status = "disabled";
porta: gpio-controller@0 {
@@ -605,6 +609,7 @@
compatible = "snps,dw-apb-gpio";
reg = <0xff709000 0x1000>;
clocks = <&l4_mp_clk>;
+ resets = <&rst GPIO1_RESET>;
status = "disabled";
portb: gpio-controller@0 {
@@ -625,6 +630,7 @@
compatible = "snps,dw-apb-gpio";
reg = <0xff70a000 0x1000>;
clocks = <&l4_mp_clk>;
+ resets = <&rst GPIO2_RESET>;
status = "disabled";
portc: gpio-controller@0 {
@@ -735,6 +741,7 @@
#size-cells = <0>;
clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>;
clock-names = "biu", "ciu";
+ resets = <&rst SDMMC_RESET>;
status = "disabled";
};
@@ -746,9 +753,9 @@
<0xffb80000 0x10000>;
reg-names = "nand_data", "denali_reg";
interrupts = <0x0 0x90 0x4>;
- dma-mask = <0xffffffff>;
clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
clock-names = "nand", "nand_x", "ecc";
+ resets = <&rst NAND_RESET>;
status = "disabled";
};
@@ -759,7 +766,7 @@
qspi: spi@ff705000 {
compatible = "cdns,qspi-nor";
- #address-cells = <1>;
+ #address-cells = <1>;
#size-cells = <0>;
reg = <0xff705000 0x1000>,
<0xffa00000 0x1000>;
@@ -768,6 +775,7 @@
cdns,fifo-width = <4>;
cdns,trigger-address = <0x00000000>;
clocks = <&qspi_clk>;
+ resets = <&rst QSPI_RESET>;
status = "disabled";
};
@@ -783,9 +791,10 @@
reg = <0xfffec000 0x100>;
};
- sdr: sdr@ffc25000 {
+ sdr: sdr@ffc20000 {
compatible = "altr,sdr-ctl", "syscon";
- reg = <0xffc25000 0x1000>;
+ reg = <0xffc20000 0x6000>;
+ resets = <&rst SDR_RESET>;
};
sdramedac {
@@ -802,6 +811,7 @@
interrupts = <0 154 4>;
num-cs = <4>;
clocks = <&spi_m_clk>;
+ resets = <&rst SPIM0_RESET>;
status = "disabled";
};
@@ -813,6 +823,7 @@
interrupts = <0 155 4>;
num-cs = <4>;
clocks = <&spi_m_clk>;
+ resets = <&rst SPIM1_RESET>;
status = "disabled";
};
@@ -879,6 +890,7 @@
dmas = <&pdma 28>,
<&pdma 29>;
dma-names = "tx", "rx";
+ resets = <&rst UART0_RESET>;
};
uart1: serial1@ffc03000 {
@@ -891,6 +903,7 @@
dmas = <&pdma 30>,
<&pdma 31>;
dma-names = "tx", "rx";
+ resets = <&rst UART1_RESET>;
};
usbphy0: usbphy {
@@ -930,6 +943,7 @@
reg = <0xffd02000 0x1000>;
interrupts = <0 171 4>;
clocks = <&osc1>;
+ resets = <&rst L4WD0_RESET>;
status = "disabled";
};
@@ -938,6 +952,7 @@
reg = <0xffd03000 0x1000>;
interrupts = <0 172 4>;
clocks = <&osc1>;
+ resets = <&rst L4WD1_RESET>;
status = "disabled";
};
};
diff --git a/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi
index e75f290..dfaff4c 100644
--- a/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi
@@ -6,15 +6,13 @@
* Copyright (c) 2018 Simon Goldschmidt
*/
+#include "socfpga-common-u-boot.dtsi"
+
/{
aliases {
spi0 = "/soc/spi@ff705000";
udc0 = &usb1;
};
-
- soc {
- u-boot,dm-pre-reloc;
- };
};
&watchdog0 {
diff --git a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts
index a387071..6439daa 100644
--- a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts
+++ b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts
@@ -4,6 +4,7 @@
*/
#include "socfpga_cyclone5.dtsi"
+#include "socfpga-common-u-boot.dtsi"
/ {
model = "Devboards.de DBM-SoC1";
@@ -24,10 +25,6 @@
device_type = "memory";
reg = <0x0 0x40000000>; /* 1GB */
};
-
- soc {
- u-boot,dm-pre-reloc;
- };
};
&gmac1 {
diff --git a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi
index 08d81da..0219c69 100644
--- a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi
@@ -6,14 +6,12 @@
* Copyright (c) 2018 Simon Goldschmidt
*/
+#include "socfpga-common-u-boot.dtsi"
+
/{
aliases {
udc0 = &usb1;
};
-
- soc {
- u-boot,dm-pre-reloc;
- };
};
&watchdog0 {
diff --git a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
index e910574..b620dd8 100644
--- a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
+++ b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
@@ -6,6 +6,7 @@
*/
#include "socfpga_cyclone5.dtsi"
+#include "socfpga-common-u-boot.dtsi"
/ {
model = "Terasic DE10-Nano";
@@ -26,10 +27,6 @@
device_type = "memory";
reg = <0x0 0x40000000>; /* 1GB */
};
-
- soc {
- u-boot,dm-pre-reloc;
- };
};
&gmac1 {
diff --git a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
index 4f076bc..ff1e61e 100644
--- a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
+++ b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
@@ -4,6 +4,7 @@
*/
#include "socfpga_cyclone5.dtsi"
+#include "socfpga-common-u-boot.dtsi"
/ {
model = "Terasic DE1-SoC";
@@ -24,10 +25,6 @@
device_type = "memory";
reg = <0x0 0x40000000>; /* 1GB */
};
-
- soc {
- u-boot,dm-pre-reloc;
- };
};
&gmac1 {
diff --git a/arch/arm/dts/socfpga_cyclone5_is1.dts b/arch/arm/dts/socfpga_cyclone5_is1.dts
index 93e4d45..2d31412 100644
--- a/arch/arm/dts/socfpga_cyclone5_is1.dts
+++ b/arch/arm/dts/socfpga_cyclone5_is1.dts
@@ -4,6 +4,7 @@
*/
#include "socfpga_cyclone5.dtsi"
+#include "socfpga-common-u-boot.dtsi"
/ {
model = "SoCFPGA Cyclone V IS1";
@@ -31,10 +32,6 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
-
- soc {
- u-boot,dm-pre-reloc;
- };
};
&gmac1 {
diff --git a/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi
index 2fafd7e..7d9874c 100644
--- a/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi
@@ -6,15 +6,13 @@
* Copyright (c) 2018 Simon Goldschmidt
*/
+#include "socfpga-common-u-boot.dtsi"
+
/{
aliases {
spi0 = "/soc/spi@ff705000";
udc0 = &usb1;
};
-
- soc {
- u-boot,dm-pre-reloc;
- };
};
&can0 {
diff --git a/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi
index 7ef3053..85cc396 100644
--- a/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi
@@ -6,15 +6,13 @@
* Copyright (c) 2018 Simon Goldschmidt
*/
+#include "socfpga-common-u-boot.dtsi"
+
/{
aliases {
spi0 = "/soc/spi@ff705000";
udc0 = &usb1;
};
-
- soc {
- u-boot,dm-pre-reloc;
- };
};
&watchdog0 {
diff --git a/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi
index 1003115..0a4d54e 100644
--- a/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi
@@ -6,15 +6,13 @@
* Copyright (c) 2018 Simon Goldschmidt
*/
+#include "socfpga-common-u-boot.dtsi"
+
/{
aliases {
spi0 = "/soc/spi@ff705000";
udc0 = &usb1;
};
-
- soc {
- u-boot,dm-pre-reloc;
- };
};
&watchdog0 {
diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts
index 93c3fa4..8d5d399 100644
--- a/arch/arm/dts/socfpga_cyclone5_socrates.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts
@@ -76,7 +76,6 @@
&qspi {
status = "okay";
- u-boot,dm-pre-reloc;
flash: flash@0 {
#address-cells = <1>;
@@ -91,6 +90,5 @@
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
status = "okay";
- u-boot,dm-pre-reloc;
};
};
diff --git a/arch/arm/dts/socfpga_cyclone5_sr1500.dts b/arch/arm/dts/socfpga_cyclone5_sr1500.dts
index 1a18c4f..bb29da6 100644
--- a/arch/arm/dts/socfpga_cyclone5_sr1500.dts
+++ b/arch/arm/dts/socfpga_cyclone5_sr1500.dts
@@ -4,6 +4,7 @@
*/
#include "socfpga_cyclone5.dtsi"
+#include "socfpga-common-u-boot.dtsi"
/ {
model = "SoCFPGA Cyclone V SR1500";
@@ -27,10 +28,6 @@
device_type = "memory";
reg = <0x0 0x40000000>; /* 1GB */
};
-
- soc {
- u-boot,dm-pre-reloc;
- };
};
&gmac1 {
diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi
index e05ca82..db55a4e 100644
--- a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi
@@ -6,15 +6,13 @@
* Copyright (c) 2018 Simon Goldschmidt
*/
+#include "socfpga-common-u-boot.dtsi"
+
/{
aliases {
spi0 = "/soc/spi@ff705000";
udc0 = &usb0;
};
-
- soc {
- u-boot,dm-pre-reloc;
- };
};
&watchdog0 {
diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi
old mode 100644
new mode 100755
index ee93725..d1ae2fa
--- a/arch/arm/dts/socfpga_stratix10.dtsi
+++ b/arch/arm/dts/socfpga_stratix10.dtsi
@@ -237,6 +237,19 @@
reg = <0xffe00000 0x100000>;
};
+ qspi: spi@ff8d2000 {
+ compatible = "cdns,qspi-nor";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xff8d2000 0x100>,
+ <0xff900000 0x100000>;
+ interrupts = <0 3 4>;
+ cdns,fifo-depth = <128>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x00000000>;
+ status = "disabled";
+ };
+
rst: rstmgr@ffd11000 {
#reset-cells = <1>;
compatible = "altr,rst-mgr";
diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
new file mode 100755
index 0000000..e1cfb52
--- /dev/null
+++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+/{
+ aliases {
+ spi0 = &qspi;
+ };
+};
+
+&qspi {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+};
+
+&flash0 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <100000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts
old mode 100644
new mode 100755
index 6e8ddcd..2745050
--- a/arch/arm/dts/socfpga_stratix10_socdk.dts
+++ b/arch/arm/dts/socfpga_stratix10_socdk.dts
@@ -36,7 +36,9 @@
memory {
device_type = "memory";
- reg = <0 0 0 0x80000000>; /* 2GB */
+ /* 4GB */
+ reg = <0 0x00000000 0 0x80000000>,
+ <1 0x80000000 0 0x80000000>;
u-boot,dm-pre-reloc;
};
};
@@ -85,6 +87,41 @@
smplsel = <0>;
};
+&qspi {
+ flash0: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q00a";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+
+ m25p,fast-read;
+ cdns,page-size = <256>;
+ cdns,block-size = <16>;
+ cdns,read-delay = <1>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ qspi_boot: partition@0 {
+ label = "Boot and fpga data";
+ reg = <0x0 0x4000000>;
+ };
+
+ qspi_rootfs: partition@4000000 {
+ label = "Root Filesystem - JFFS2";
+ reg = <0x4000000 0x4000000>;
+ };
+ };
+ };
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm/dts/stm32mp157-pinctrl.dtsi b/arch/arm/dts/stm32mp157-pinctrl.dtsi
index c069875..0aae69b 100644
--- a/arch/arm/dts/stm32mp157-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp157-pinctrl.dtsi
@@ -375,6 +375,13 @@
};
};
+ stusb1600_pins_a: stusb1600-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 11, ANALOG)>;
+ bias-pull-up;
+ };
+ };
+
uart4_pins_a: uart4-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
index af7acfa..0f32a38 100644
--- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
@@ -11,6 +11,7 @@
aliases {
i2c3 = &i2c4;
mmc0 = &sdmmc1;
+ usb0 = &usbotg_hs;
};
config {
u-boot,boot-led = "heartbeat";
@@ -190,7 +191,7 @@
};
&usbotg_hs {
- usb1600;
+ u-boot,force-b-session-valid;
hnp-srp-disable;
};
diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts
index 0882765..e36773d 100644
--- a/arch/arm/dts/stm32mp157a-dk1.dts
+++ b/arch/arm/dts/stm32mp157a-dk1.dts
@@ -67,6 +67,24 @@
/delete-property/dmas;
/delete-property/dma-names;
+ typec: stusb1600@28 {
+ compatible = "st,stusb1600";
+ reg = <0x28>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-parent = <&gpioi>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&stusb1600_pins_a>;
+
+ status = "okay";
+
+ typec_con: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ power-role = "sink";
+ power-opmode = "default";
+ };
+ };
+
pmic: stpmic@33 {
compatible = "st,stpmic1";
reg = <0x33>;
@@ -249,11 +267,25 @@
status = "okay";
};
+&usbotg_hs {
+ dr_mode = "peripheral";
+ phys = <&usbphyc_port1 0>;
+ phy-names = "usb2-phy";
+ status = "okay";
+};
+
&usbphyc {
- vdd3v3-supply = <&vdd_usb>;
status = "okay";
};
+&usbphyc_port0 {
+ phy-supply = <&vdd_usb>;
+};
+
+&usbphyc_port1 {
+ phy-supply = <&vdd_usb>;
+};
+
&vrefbuf {
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts
index 8c0ff3c..b10208f 100644
--- a/arch/arm/dts/stm32mp157c-ed1.dts
+++ b/arch/arm/dts/stm32mp157c-ed1.dts
@@ -382,18 +382,10 @@
status = "okay";
};
-&usbotg_hs {
- usb33d-supply = <&usb33>;
-};
-
&usbphyc_port0 {
phy-supply = <&vdd_usb>;
- vdda1v1-supply = <®11>;
- vdda1v8-supply = <®18>;
};
&usbphyc_port1 {
phy-supply = <&vdd_usb>;
- vdda1v1-supply = <®11>;
- vdda1v8-supply = <®18>;
};
diff --git a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
index 8b92b1f..5b19e44 100644
--- a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
@@ -12,6 +12,7 @@
i2c4 = &i2c5;
pinctrl2 = &stmfx_pinctrl;
spi0 = &qspi;
+ usb0 = &usbotg_hs;
};
};
diff --git a/arch/arm/dts/stm32mp157c.dtsi b/arch/arm/dts/stm32mp157c.dtsi
index 7eb4bee..9463433 100644
--- a/arch/arm/dts/stm32mp157c.dtsi
+++ b/arch/arm/dts/stm32mp157c.dtsi
@@ -825,7 +825,7 @@
};
usbotg_hs: usb-otg@49000000 {
- compatible = "snps,dwc2";
+ compatible = "st,stm32mp1-hsotg", "snps,dwc2";
reg = <0x49000000 0x10000>;
clocks = <&rcc USBO_K>;
clock-names = "otg";
@@ -836,6 +836,7 @@
g-np-tx-fifo-size = <32>;
g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
dr_mode = "otg";
+ usb33d-supply = <&usb33>;
status = "disabled";
};
@@ -1161,6 +1162,8 @@
reg = <0x5a006000 0x1000>;
clocks = <&rcc USBPHY_K>;
resets = <&rcc USBPHY_R>;
+ vdda1v1-supply = <®11>;
+ vdda1v8-supply = <®18>;
status = "disabled";
usbphyc_port0: usb-phy@0 {
diff --git a/arch/arm/include/asm/arch-meson/clock-g12a.h b/arch/arm/include/asm/arch-meson/clock-g12a.h
new file mode 100644
index 0000000..d52e27e
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/clock-g12a.h
@@ -0,0 +1,104 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 - AmLogic, Inc.
+ * Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
+ * Copyright 2018 - BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+#ifndef _ARCH_MESON_CLOCK_G12A_H_
+#define _ARCH_MESON_CLOCK_G12A_H_
+
+/*
+ * Clock controller register offsets
+ *
+ * Register offsets from the data sheet are listed in comment blocks below.
+ * Those offsets must be multiplied by 4 before adding them to the base address
+ * to get the right value
+ */
+
+#define HHI_MIPI_CNTL0 0x000
+#define HHI_MIPI_CNTL1 0x004
+#define HHI_MIPI_CNTL2 0x008
+#define HHI_MIPI_STS 0x00C
+#define HHI_GP0_PLL_CNTL0 0x040
+#define HHI_GP0_PLL_CNTL1 0x044
+#define HHI_GP0_PLL_CNTL2 0x048
+#define HHI_GP0_PLL_CNTL3 0x04C
+#define HHI_GP0_PLL_CNTL4 0x050
+#define HHI_GP0_PLL_CNTL5 0x054
+#define HHI_GP0_PLL_CNTL6 0x058
+#define HHI_GP0_PLL_STS 0x05C
+#define HHI_PCIE_PLL_CNTL0 0x098
+#define HHI_PCIE_PLL_CNTL1 0x09C
+#define HHI_PCIE_PLL_CNTL2 0x0A0
+#define HHI_PCIE_PLL_CNTL3 0x0A4
+#define HHI_PCIE_PLL_CNTL4 0x0A8
+#define HHI_PCIE_PLL_CNTL5 0x0AC
+#define HHI_PCIE_PLL_STS 0x0B8
+#define HHI_HIFI_PLL_CNTL0 0x0D8
+#define HHI_HIFI_PLL_CNTL1 0x0DC
+#define HHI_HIFI_PLL_CNTL2 0x0E0
+#define HHI_HIFI_PLL_CNTL3 0x0E4
+#define HHI_HIFI_PLL_CNTL4 0x0E8
+#define HHI_HIFI_PLL_CNTL5 0x0EC
+#define HHI_HIFI_PLL_CNTL6 0x0F0
+#define HHI_VIID_CLK_DIV 0x128
+#define HHI_VIID_CLK_CNTL 0x12C
+#define HHI_GCLK_MPEG0 0x140
+#define HHI_GCLK_MPEG1 0x144
+#define HHI_GCLK_MPEG2 0x148
+#define HHI_GCLK_OTHER 0x150
+#define HHI_GCLK_OTHER2 0x154
+#define HHI_VID_CLK_DIV 0x164
+#define HHI_MPEG_CLK_CNTL 0x174
+#define HHI_AUD_CLK_CNTL 0x178
+#define HHI_VID_CLK_CNTL 0x17c
+#define HHI_TS_CLK_CNTL 0x190
+#define HHI_VID_CLK_CNTL2 0x194
+#define HHI_SYS_CPU_CLK_CNTL0 0x19c
+#define HHI_VID_PLL_CLK_DIV 0x1A0
+#define HHI_MALI_CLK_CNTL 0x1b0
+#define HHI_VPU_CLKC_CNTL 0x1b4
+#define HHI_VPU_CLK_CNTL 0x1bC
+#define HHI_HDMI_CLK_CNTL 0x1CC
+#define HHI_VDEC_CLK_CNTL 0x1E0
+#define HHI_VDEC2_CLK_CNTL 0x1E4
+#define HHI_VDEC3_CLK_CNTL 0x1E8
+#define HHI_VDEC4_CLK_CNTL 0x1EC
+#define HHI_HDCP22_CLK_CNTL 0x1F0
+#define HHI_VAPBCLK_CNTL 0x1F4
+#define HHI_VPU_CLKB_CNTL 0x20C
+#define HHI_GEN_CLK_CNTL 0x228
+#define HHI_VDIN_MEAS_CLK_CNTL 0x250
+#define HHI_MIPIDSI_PHY_CLK_CNTL 0x254
+#define HHI_NAND_CLK_CNTL 0x25C
+#define HHI_SD_EMMC_CLK_CNTL 0x264
+#define HHI_MPLL_CNTL0 0x278
+#define HHI_MPLL_CNTL1 0x27C
+#define HHI_MPLL_CNTL2 0x280
+#define HHI_MPLL_CNTL3 0x284
+#define HHI_MPLL_CNTL4 0x288
+#define HHI_MPLL_CNTL5 0x28c
+#define HHI_MPLL_CNTL6 0x290
+#define HHI_MPLL_CNTL7 0x294
+#define HHI_MPLL_CNTL8 0x298
+#define HHI_FIX_PLL_CNTL0 0x2A0
+#define HHI_FIX_PLL_CNTL1 0x2A4
+#define HHI_FIX_PLL_CNTL3 0x2AC
+#define HHI_SYS_PLL_CNTL0 0x2f4
+#define HHI_SYS_PLL_CNTL1 0x2f8
+#define HHI_SYS_PLL_CNTL2 0x2fc
+#define HHI_SYS_PLL_CNTL3 0x300
+#define HHI_SYS_PLL_CNTL4 0x304
+#define HHI_SYS_PLL_CNTL5 0x308
+#define HHI_SYS_PLL_CNTL6 0x30c
+#define HHI_HDMI_PLL_CNTL0 0x320
+#define HHI_HDMI_PLL_CNTL1 0x324
+#define HHI_HDMI_PLL_CNTL2 0x328
+#define HHI_HDMI_PLL_CNTL3 0x32c
+#define HHI_HDMI_PLL_CNTL4 0x330
+#define HHI_HDMI_PLL_CNTL5 0x334
+#define HHI_HDMI_PLL_CNTL6 0x338
+#define HHI_SPICC_CLK_CNTL 0x3dc
+
+#endif
diff --git a/arch/arm/include/asm/arch-meson/g12a.h b/arch/arm/include/asm/arch-meson/g12a.h
new file mode 100644
index 0000000..b806667
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/g12a.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#ifndef __G12A_H__
+#define __G12A_H__
+
+#define G12A_AOBUS_BASE 0xff800000
+#define G12A_PERIPHS_BASE 0xff634400
+#define G12A_HIU_BASE 0xff63c000
+#define G12A_ETH_PHY_BASE 0xff64c000
+#define G12A_ETH_BASE 0xff3f0000
+
+/* Always-On Peripherals registers */
+#define G12A_AO_ADDR(off) (G12A_AOBUS_BASE + ((off) << 2))
+
+#define G12A_AO_SEC_GP_CFG0 G12A_AO_ADDR(0x90)
+#define G12A_AO_SEC_GP_CFG3 G12A_AO_ADDR(0x93)
+#define G12A_AO_SEC_GP_CFG4 G12A_AO_ADDR(0x94)
+#define G12A_AO_SEC_GP_CFG5 G12A_AO_ADDR(0x95)
+
+#define G12A_AO_BOOT_DEVICE 0xF
+#define G12A_AO_MEM_SIZE_MASK 0xFFFF0000
+#define G12A_AO_MEM_SIZE_SHIFT 16
+#define G12A_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000
+#define G12A_AO_BL31_RSVMEM_SIZE_SHIFT 16
+#define G12A_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF
+
+/* Peripherals registers */
+#define G12A_PERIPHS_ADDR(off) (G12A_PERIPHS_BASE + ((off) << 2))
+
+#define G12A_ETH_REG_0 G12A_PERIPHS_ADDR(0x50)
+#define G12A_ETH_REG_1 G12A_PERIPHS_ADDR(0x51)
+
+#define G12A_ETH_REG_0_PHY_INTF_RGMII BIT(0)
+#define G12A_ETH_REG_0_PHY_INTF_RMII BIT(2)
+#define G12A_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5)
+#define G12A_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7)
+#define G12A_ETH_REG_0_PHY_CLK_EN BIT(10)
+#define G12A_ETH_REG_0_INVERT_RMII_CLK BIT(11)
+#define G12A_ETH_REG_0_CLK_EN BIT(12)
+
+#define G12A_ETH_PHY_ADDR(off) (G12A_ETH_PHY_BASE + ((off) << 2))
+#define ETH_PLL_CNTL0 G12A_ETH_PHY_ADDR(0x11)
+#define ETH_PLL_CNTL1 G12A_ETH_PHY_ADDR(0x12)
+#define ETH_PLL_CNTL2 G12A_ETH_PHY_ADDR(0x13)
+#define ETH_PLL_CNTL3 G12A_ETH_PHY_ADDR(0x14)
+#define ETH_PLL_CNTL4 G12A_ETH_PHY_ADDR(0x15)
+#define ETH_PLL_CNTL5 G12A_ETH_PHY_ADDR(0x16)
+#define ETH_PLL_CNTL6 G12A_ETH_PHY_ADDR(0x17)
+#define ETH_PLL_CNTL7 G12A_ETH_PHY_ADDR(0x18)
+#define ETH_PHY_CNTL0 G12A_ETH_PHY_ADDR(0x20)
+#define ETH_PHY_CNTL1 G12A_ETH_PHY_ADDR(0x21)
+#define ETH_PHY_CNTL2 G12A_ETH_PHY_ADDR(0x22)
+
+/* HIU registers */
+#define G12A_HIU_ADDR(off) (G12A_HIU_BASE + ((off) << 2))
+
+#define G12A_MEM_PD_REG_0 G12A_HIU_ADDR(0x40)
+
+/* Ethernet memory power domain */
+#define G12A_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3))
+
+#endif /* __G12A_H__ */
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 12bc7fb..e6d27b6 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -123,6 +123,27 @@
#define readq(c) ({ u64 __v = __arch_getq(c); __iormb(); __v; })
/*
+ * Relaxed I/O memory access primitives. These follow the Device memory
+ * ordering rules but do not guarantee any ordering relative to Normal memory
+ * accesses.
+ */
+#define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; })
+#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
+ __raw_readw(c)); __r; })
+#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
+ __raw_readl(c)); __r; })
+#define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64) \
+ __raw_readq(c)); __r; })
+
+#define writeb_relaxed(v, c) ((void)__raw_writeb((v), (c)))
+#define writew_relaxed(v, c) ((void)__raw_writew((__force u16) \
+ cpu_to_le16(v), (c)))
+#define writel_relaxed(v, c) ((void)__raw_writel((__force u32) \
+ cpu_to_le32(v), (c)))
+#define writeq_relaxed(v, c) ((void)__raw_writeq((__force u64) \
+ cpu_to_le64(v), (c)))
+
+/*
* The compiler seems to be incapable of optimising constants
* properly. Spell it out to the compiler in some cases.
* These are only valid for small values of "off" (< 1<<12)
diff --git a/arch/arm/include/asm/secure.h b/arch/arm/include/asm/secure.h
index d23044a..50582c9 100644
--- a/arch/arm/include/asm/secure.h
+++ b/arch/arm/include/asm/secure.h
@@ -6,6 +6,37 @@
#define __secure __attribute__ ((section ("._secure.text")))
#define __secure_data __attribute__ ((section ("._secure.data")))
+#ifndef __ASSEMBLY__
+
+typedef struct secure_svc_tbl {
+ u32 id;
+#ifdef CONFIG_ARMV8_PSCI
+ u8 pad[4];
+#endif
+ void *func;
+} secure_svc_tbl_t;
+
+/*
+ * Macro to declare a SiP function service in '_secure_svc_tbl_entries' section
+ */
+#define DECLARE_SECURE_SVC(_name, _id, _fn) \
+ static const secure_svc_tbl_t __secure_svc_ ## _name \
+ __attribute__((used, section("._secure_svc_tbl_entries"))) \
+ = { \
+ .id = _id, \
+ .func = _fn }
+
+#else
+
+#ifdef CONFIG_ARMV8_PSCI
+#define SECURE_SVC_TBL_OFFSET 16
+#else
+#define SECURE_SVC_TBL_OFFSET 8
+
+#endif
+
+#endif /* __ASSEMBLY__ */
+
#if defined(CONFIG_ARMV7_SECURE_BASE) || defined(CONFIG_ARMV8_SECURE_BASE)
/*
* Warning, horror ahead.
diff --git a/arch/arm/lib/relocate_64.S b/arch/arm/lib/relocate_64.S
index 7603f52..26d29c5 100644
--- a/arch/arm/lib/relocate_64.S
+++ b/arch/arm/lib/relocate_64.S
@@ -26,9 +26,10 @@
/*
* Copy u-boot from flash to RAM
*/
- adr x1, __image_copy_start /* x1 <- Run &__image_copy_start */
- subs x9, x0, x1 /* x8 <- Run to copy offset */
- b.eq relocate_done /* skip relocation */
+ adrp x1, __image_copy_start /* x1 <- address bits [31:12] */
+ add x1, x1, :lo12:__image_copy_start/* x1 <- address bits [11:00] */
+ subs x9, x0, x1 /* x9 <- Run to copy offset */
+ b.eq relocate_done /* skip relocation */
/*
* Don't ldr x1, __image_copy_start here, since if the code is already
* running at an address other than it was linked to, that instruction
@@ -42,8 +43,10 @@
ldr x1, _TEXT_BASE /* x1 <- Linked &__image_copy_start */
subs x9, x0, x1 /* x9 <- Link to copy offset */
- adr x1, __image_copy_start /* x1 <- Run &__image_copy_start */
- adr x2, __image_copy_end /* x2 <- Run &__image_copy_end */
+ adrp x1, __image_copy_start /* x1 <- address bits [31:12] */
+ add x1, x1, :lo12:__image_copy_start/* x1 <- address bits [11:00] */
+ adrp x2, __image_copy_end /* x2 <- address bits [31:12] */
+ add x2, x2, :lo12:__image_copy_end /* x2 <- address bits [11:00] */
copy_loop:
ldp x10, x11, [x1], #16 /* copy from source address [x1] */
stp x10, x11, [x0], #16 /* copy to target address [x0] */
@@ -54,8 +57,10 @@
/*
* Fix .rela.dyn relocations
*/
- adr x2, __rel_dyn_start /* x2 <- Run &__rel_dyn_start */
- adr x3, __rel_dyn_end /* x3 <- Run &__rel_dyn_end */
+ adrp x2, __rel_dyn_start /* x2 <- address bits [31:12] */
+ add x2, x2, :lo12:__rel_dyn_start /* x2 <- address bits [11:00] */
+ adrp x3, __rel_dyn_end /* x3 <- address bits [31:12] */
+ add x3, x3, :lo12:__rel_dyn_end /* x3 <- address bits [11:00] */
fixloop:
ldp x0, x1, [x2], #16 /* (x0,x1) <- (SRC location, fixup) */
ldr x4, [x2], #8 /* x4 <- addend */
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index a089e94..c3b21b7 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -180,6 +180,17 @@
processor-based SAMA5D2 MPU with up to 1 Gbit DDR2-SDRAM
in a single package.
+config TARGET_SAMA5D2_ICP
+ bool "SAMA5D2 Industrial Connectivity Platform (ICP)"
+ select CPU_V7A
+ select SUPPORT_SPL
+ select BOARD_EARLY_INIT_F
+ select BOARD_LATE_INIT
+ help
+ The SAMA5D2 ICP embeds SAMA5D27 rev. C SoC, together with
+ a 64Mbit QSPI flash, 3xMikrobus connectors, 4xUSB ,
+ EtherCat and WILC3000 devices on board.
+
config TARGET_SAMA5D3_XPLAINED
bool "SAMA5D3 Xplained board"
select BOARD_EARLY_INIT_F
@@ -281,6 +292,7 @@
source "board/atmel/sama5d2_ptc_ek/Kconfig"
source "board/atmel/sama5d2_xplained/Kconfig"
source "board/atmel/sama5d27_som1_ek/Kconfig"
+source "board/atmel/sama5d2_icp/Kconfig"
source "board/atmel/sama5d3_xplained/Kconfig"
source "board/atmel/sama5d3xek/Kconfig"
source "board/atmel/sama5d4_xplained/Kconfig"
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index 7a733e9..b5e91d4 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -31,6 +31,16 @@
including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet,
switch, USB3.0, PCIe, UART, SPI, I2C and PWM.
+config TARGET_MT8516
+ bool "MediaTek MT8516 SoC"
+ select ARM64
+ select ARCH_MISC_INIT
+ help
+ The MediaTek MT8516 is a ARM64-based SoC with a quad-core Cortex-A35.
+ including UART, SPI, USB2.0 and OTG, SD and MMC cards, NAND, PWM,
+ Ethernet, IR TX/RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth combo
+ chip and several DDR3 and DDR4 options.
+
endchoice
source "board/mediatek/mt7623/Kconfig"
diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile
index b5d3a37..ea414dc 100644
--- a/arch/arm/mach-mediatek/Makefile
+++ b/arch/arm/mach-mediatek/Makefile
@@ -5,3 +5,4 @@
obj-$(CONFIG_TARGET_MT7623) += mt7623/
obj-$(CONFIG_TARGET_MT7629) += mt7629/
+obj-$(CONFIG_TARGET_MT8516) += mt8516/
diff --git a/arch/arm/mach-mediatek/mt8516/Makefile b/arch/arm/mach-mediatek/mt8516/Makefile
new file mode 100644
index 0000000..886ab7e
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt8516/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += init.o
diff --git a/arch/arm/mach-mediatek/mt8516/init.c b/arch/arm/mach-mediatek/mt8516/init.c
new file mode 100644
index 0000000..26a215a
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt8516/init.c
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Copyright (C) 2019 BayLibre, SAS
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <ram.h>
+#include <asm/arch/misc.h>
+#include <asm/armv8/mmu.h>
+#include <asm/sections.h>
+#include <dm/uclass.h>
+#include <linux/io.h>
+#include <dt-bindings/clock/mt8516-clk.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define WDOG_SWRST 0x10007014
+#define WDOG_SWRST_KEY 0x1209
+
+int dram_init(void)
+{
+ int ret;
+
+ ret = fdtdec_setup_memory_banksize();
+ if (ret)
+ return ret;
+
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = gd->ram_base;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+
+ return 0;
+}
+
+int mtk_pll_early_init(void)
+{
+ unsigned long pll_rates[] = {
+ [CLK_APMIXED_ARMPLL] = 1300000000,
+ [CLK_APMIXED_MAINPLL] = 1501000000,
+ [CLK_APMIXED_UNIVPLL] = 1248000000,
+ [CLK_APMIXED_MMPLL] = 380000000,
+ };
+ struct udevice *dev;
+ int ret, i;
+
+ ret = uclass_get_device_by_driver(UCLASS_CLK,
+ DM_GET_DRIVER(mtk_clk_apmixedsys), &dev);
+ if (ret)
+ return ret;
+
+ /* configure default rate then enable apmixedsys */
+ for (i = 0; i < ARRAY_SIZE(pll_rates); i++) {
+ struct clk clk = { .id = i, .dev = dev };
+
+ ret = clk_set_rate(&clk, pll_rates[i]);
+ if (ret)
+ return ret;
+
+ ret = clk_enable(&clk);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+int mtk_soc_early_init(void)
+{
+ int ret;
+
+ /* initialize early clocks */
+ ret = mtk_pll_early_init();
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+ while (1) {
+ writel(WDOG_SWRST_KEY, WDOG_SWRST);
+ mdelay(5);
+ }
+}
+
+int print_cpuinfo(void)
+{
+ printf("CPU: MediaTek MT8516\n");
+ return 0;
+}
+
+static struct mm_region mt8516_mem_map[] = {
+ {
+ /* DDR */
+ .virt = 0x40000000UL,
+ .phys = 0x40000000UL,
+ .size = 0x20000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
+ }, {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x20000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ 0,
+ }
+};
+struct mm_region *mem_map = mt8516_mem_map;
diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index 11077bc..e29e4c0 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -41,7 +41,13 @@
bool "AXG"
select MESON64_COMMON
help
- Select this if your SoC is an A113X/D
+ Select this if your SoC is an A113X/D
+
+config MESON_G12A
+ bool "G12A"
+ select MESON64_COMMON
+ help
+ Select this if your SoC is an S905X/D2
endchoice
@@ -61,10 +67,11 @@
config SYS_BOARD
string "Board name"
- default "odroid-c2" if MESON_GXBB
+ default "p200" if MESON_GXBB
default "p212" if MESON_GXL
default "q200" if MESON_GXM
default "s400" if MESON_AXG
+ default "u200" if MESON_G12A
default ""
help
This option contains information about board name.
diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile
index b716e1a..a9e4046 100644
--- a/arch/arm/mach-meson/Makefile
+++ b/arch/arm/mach-meson/Makefile
@@ -2,6 +2,7 @@
#
# Copyright (c) 2016 Beniamino Galvani <b.galvani@gmail.com>
-obj-y += board-common.o sm.o
+obj-y += board-common.o sm.o board-info.o
obj-$(CONFIG_MESON_GX) += board-gx.o
obj-$(CONFIG_MESON_AXG) += board-axg.o
+obj-$(CONFIG_MESON_G12A) += board-g12a.o
diff --git a/arch/arm/mach-meson/board-g12a.c b/arch/arm/mach-meson/board-g12a.c
new file mode 100644
index 0000000..fc3764b
--- /dev/null
+++ b/arch/arm/mach-meson/board-g12a.c
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+ * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include <common.h>
+#include <asm/arch/boot.h>
+#include <asm/arch/eth.h>
+#include <asm/arch/g12a.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <asm/armv8/mmu.h>
+#include <linux/sizes.h>
+#include <phy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int meson_get_boot_device(void)
+{
+ return readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_BOOT_DEVICE;
+}
+
+/* Configure the reserved memory zones exported by the secure registers
+ * into EFI and DTB reserved memory entries.
+ */
+void meson_init_reserved_memory(void *fdt)
+{
+ u64 bl31_size, bl31_start;
+ u64 bl32_size, bl32_start;
+ u32 reg;
+
+ /*
+ * Get ARM Trusted Firmware reserved memory zones in :
+ * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
+ * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
+ * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
+ */
+ reg = readl(G12A_AO_SEC_GP_CFG3);
+
+ bl31_size = ((reg & G12A_AO_BL31_RSVMEM_SIZE_MASK)
+ >> G12A_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
+ bl32_size = (reg & G12A_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
+
+ bl31_start = readl(G12A_AO_SEC_GP_CFG5);
+ bl32_start = readl(G12A_AO_SEC_GP_CFG4);
+
+ /* Add BL31 reserved zone */
+ if (bl31_start && bl31_size)
+ meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
+
+ /* Add BL32 reserved zone */
+ if (bl32_start && bl32_size)
+ meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
+}
+
+phys_size_t get_effective_memsize(void)
+{
+ /* Size is reported in MiB, convert it in bytes */
+ return ((readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_MEM_SIZE_MASK)
+ >> G12A_AO_MEM_SIZE_SHIFT) * SZ_1M;
+}
+
+static struct mm_region g12a_mem_map[] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xf0000000UL,
+ .phys = 0xf0000000UL,
+ .size = 0x10000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = g12a_mem_map;
+
+static void g12a_enable_external_mdio(void)
+{
+ writel(0x0, ETH_PHY_CNTL2);
+}
+
+static void g12a_enable_internal_mdio(void)
+{
+ /* Fire up the PHY PLL */
+ writel(0x29c0040a, ETH_PLL_CNTL0);
+ writel(0x927e0000, ETH_PLL_CNTL1);
+ writel(0xac5f49e5, ETH_PLL_CNTL2);
+ writel(0x00000000, ETH_PLL_CNTL3);
+ writel(0x00000000, ETH_PLL_CNTL4);
+ writel(0x20200000, ETH_PLL_CNTL5);
+ writel(0x0000c002, ETH_PLL_CNTL6);
+ writel(0x00000023, ETH_PLL_CNTL7);
+ writel(0x39c0040a, ETH_PLL_CNTL0);
+ writel(0x19c0040a, ETH_PLL_CNTL0);
+
+ /* Select the internal MDIO */
+ writel(0x33000180, ETH_PHY_CNTL0);
+ writel(0x00074043, ETH_PHY_CNTL1);
+ writel(0x00000260, ETH_PHY_CNTL2);
+}
+
+/* Configure the Ethernet MAC with the requested interface mode
+ * with some optional flags.
+ */
+void meson_eth_init(phy_interface_t mode, unsigned int flags)
+{
+ switch (mode) {
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ /* Set RGMII mode */
+ setbits_le32(G12A_ETH_REG_0, G12A_ETH_REG_0_PHY_INTF_RGMII |
+ G12A_ETH_REG_0_TX_PHASE(1) |
+ G12A_ETH_REG_0_TX_RATIO(4) |
+ G12A_ETH_REG_0_PHY_CLK_EN |
+ G12A_ETH_REG_0_CLK_EN);
+ break;
+
+ case PHY_INTERFACE_MODE_RMII:
+ /* Set RMII mode */
+ out_le32(G12A_ETH_REG_0, G12A_ETH_REG_0_PHY_INTF_RMII |
+ G12A_ETH_REG_0_INVERT_RMII_CLK |
+ G12A_ETH_REG_0_CLK_EN);
+
+ /* Use G12A RMII Internal PHY */
+ if (flags & MESON_USE_INTERNAL_RMII_PHY)
+ g12a_enable_internal_mdio();
+ else
+ g12a_enable_external_mdio();
+
+ break;
+
+ default:
+ printf("Invalid Ethernet interface mode\n");
+ return;
+ }
+
+ /* Enable power gate */
+ clrbits_le32(G12A_MEM_PD_REG_0, G12A_MEM_PD_REG_0_ETH_MASK);
+}
diff --git a/arch/arm/mach-meson/board-info.c b/arch/arm/mach-meson/board-info.c
new file mode 100644
index 0000000..ba248e8
--- /dev/null
+++ b/arch/arm/mach-meson/board-info.c
@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Julien Masson <jmasson@baylibre.com>
+ * (C) Copyright 2019 Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <linux/bitfield.h>
+#include <regmap.h>
+#include <syscon.h>
+
+#define AO_SEC_SD_CFG8 0xe0
+#define AO_SEC_SOCINFO_OFFSET AO_SEC_SD_CFG8
+
+#define SOCINFO_MAJOR GENMASK(31, 24)
+#define SOCINFO_PACK GENMASK(23, 16)
+#define SOCINFO_MINOR GENMASK(15, 8)
+#define SOCINFO_MISC GENMASK(7, 0)
+
+static const struct meson_gx_soc_id {
+ const char *name;
+ unsigned int id;
+} soc_ids[] = {
+ { "GXBB", 0x1f },
+ { "GXTVBB", 0x20 },
+ { "GXL", 0x21 },
+ { "GXM", 0x22 },
+ { "TXL", 0x23 },
+ { "TXLX", 0x24 },
+ { "AXG", 0x25 },
+ { "GXLX", 0x26 },
+ { "TXHD", 0x27 },
+ { "G12A", 0x28 },
+ { "G12B", 0x29 },
+};
+
+static const struct meson_gx_package_id {
+ const char *name;
+ unsigned int major_id;
+ unsigned int pack_id;
+ unsigned int pack_mask;
+} soc_packages[] = {
+ { "S905", 0x1f, 0, 0x20 }, /* pack_id != 0x20 */
+ { "S905H", 0x1f, 0x3, 0xf }, /* pack_id & 0xf == 0x3 */
+ { "S905M", 0x1f, 0x20, 0xf0 }, /* pack_id == 0x20 */
+ { "S905D", 0x21, 0, 0xf0 },
+ { "S905X", 0x21, 0x80, 0xf0 },
+ { "S905W", 0x21, 0xa0, 0xf0 },
+ { "S905L", 0x21, 0xc0, 0xf0 },
+ { "S905M2", 0x21, 0xe0, 0xf0 },
+ { "S805X", 0x21, 0x30, 0xf0 },
+ { "S805Y", 0x21, 0xb0, 0xf0 },
+ { "S912", 0x22, 0, 0x0 }, /* Only S912 is known for GXM */
+ { "962X", 0x24, 0x10, 0xf0 },
+ { "962E", 0x24, 0x20, 0xf0 },
+ { "A113X", 0x25, 0x37, 0xff },
+ { "A113D", 0x25, 0x22, 0xff },
+ { "S905D2", 0x28, 0x10, 0xf0 },
+ { "S905X2", 0x28, 0x40, 0xf0 },
+ { "S922X", 0x29, 0x40, 0xf0 },
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static inline unsigned int socinfo_to_major(u32 socinfo)
+{
+ return FIELD_GET(SOCINFO_MAJOR, socinfo);
+}
+
+static inline unsigned int socinfo_to_minor(u32 socinfo)
+{
+ return FIELD_GET(SOCINFO_MINOR, socinfo);
+}
+
+static inline unsigned int socinfo_to_pack(u32 socinfo)
+{
+ return FIELD_GET(SOCINFO_PACK, socinfo);
+}
+
+static inline unsigned int socinfo_to_misc(u32 socinfo)
+{
+ return FIELD_GET(SOCINFO_MISC, socinfo);
+}
+
+static const char *socinfo_to_package_id(u32 socinfo)
+{
+ unsigned int pack = socinfo_to_pack(socinfo);
+ unsigned int major = socinfo_to_major(socinfo);
+ int i;
+
+ for (i = 0 ; i < ARRAY_SIZE(soc_packages) ; ++i) {
+ if (soc_packages[i].major_id == major &&
+ soc_packages[i].pack_id ==
+ (pack & soc_packages[i].pack_mask))
+ return soc_packages[i].name;
+ }
+
+ return "Unknown";
+}
+
+static const char *socinfo_to_soc_id(u32 socinfo)
+{
+ unsigned int id = socinfo_to_major(socinfo);
+ int i;
+
+ for (i = 0 ; i < ARRAY_SIZE(soc_ids) ; ++i) {
+ if (soc_ids[i].id == id)
+ return soc_ids[i].name;
+ }
+
+ return "Unknown";
+}
+
+static void print_board_model(void)
+{
+ const char *model;
+ model = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
+ printf("Model: %s\n", model ? model : "Unknown");
+}
+
+int show_board_info(void)
+{
+ struct regmap *regmap;
+ int nodeoffset, ret;
+ ofnode node;
+ unsigned int socinfo;
+
+ /* find the offset of compatible node */
+ nodeoffset = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
+ "amlogic,meson-gx-ao-secure");
+ if (nodeoffset < 0)
+ return 0;
+
+ /* check if chip-id is available */
+ if (!fdt_getprop(gd->fdt_blob, nodeoffset, "amlogic,has-chip-id", NULL))
+ return 0;
+
+ /* get regmap from the syscon node */
+ node = offset_to_ofnode(nodeoffset);
+ regmap = syscon_node_to_regmap(node);
+ if (IS_ERR(regmap)) {
+ printf("%s: failed to get regmap\n", __func__);
+ return 0;
+ }
+
+ /* read soc info */
+ ret = regmap_read(regmap, AO_SEC_SOCINFO_OFFSET, &socinfo);
+ if (ret && !socinfo) {
+ printf("%s: invalid chipid value\n", __func__);
+ return 0;
+ }
+
+ /* print board information */
+ print_board_model();
+ printf("Soc: Amlogic Meson %s (%s) Revision %x:%x (%x:%x)\n",
+ socinfo_to_soc_id(socinfo),
+ socinfo_to_package_id(socinfo),
+ socinfo_to_major(socinfo),
+ socinfo_to_minor(socinfo),
+ socinfo_to_pack(socinfo),
+ socinfo_to_misc(socinfo));
+
+ return 0;
+}
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
index 31b73ed..e186296 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
@@ -9,6 +9,7 @@
void reset_cpu(ulong addr);
void reset_deassert_peripherals_handoff(void);
+int cpu_has_been_warmreset(void);
void socfpga_bridges_reset(int enable);
@@ -47,6 +48,8 @@
#define RSTMGR_MPUMODRST_CORE0 0
#define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00
#define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040
+/* Watchdogs and MPU warm reset mask */
+#define RSTMGR_L4WD_MPU_WARMRESET_MASK 0x000F0F00
/*
* Define a reset identifier, from which a permodrst bank ID
diff --git a/arch/arm/mach-socfpga/include/mach/sdram_gen5.h b/arch/arm/mach-socfpga/include/mach/sdram_gen5.h
index a238d5d..c412085 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram_gen5.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram_gen5.h
@@ -7,10 +7,6 @@
#ifndef __ASSEMBLY__
-unsigned long sdram_calculate_size(void);
-int sdram_mmr_init_full(unsigned int sdr_phy_reg);
-int sdram_calibration_full(void);
-
const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem);
diff --git a/arch/arm/mach-socfpga/include/mach/sdram_s10.h b/arch/arm/mach-socfpga/include/mach/sdram_s10.h
index ca68594..f39206c 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram_s10.h
@@ -22,6 +22,7 @@
#define ECCCTRL1 0x100
#define ECCCTRL2 0x104
#define ERRINTEN 0x110
+#define ERRINTENS 0x114
#define INTMODE 0x11c
#define INTSTAT 0x120
#define AUTOWB_CORRADDR 0x138
@@ -52,6 +53,10 @@
#define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3)
#define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f
+#define DDR_HMC_ERRINTEN_INTMASK \
+ (DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK | \
+ DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK)
+
/* NOC DDR scheduler */
#define DDR_SCH_ID_COREID 0
#define DDR_SCH_ID_REVID 0x4
@@ -180,4 +185,8 @@
#define CALTIMING9_CFG_4_ACT_TO_ACT(x) \
(((x) >> 0) & 0xFF)
+/* Firewall DDR scheduler MPFE */
+#define FW_HMC_ADAPTOR_REG_ADDR 0xf8020004
+#define FW_HMC_ADAPTOR_MPU_MASK BIT(0)
+
#endif /* _SDRAM_S10_H_ */
diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
index 6e11ba6..9865f5b 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -201,16 +201,6 @@
/* Add device descriptor to FPGA device table */
socfpga_fpga_add(&altera_fpga[0]);
-#ifdef CONFIG_DESIGNWARE_SPI
- /* Get Designware SPI controller out of reset */
- socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0);
- socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);
-#endif
-
-#ifdef CONFIG_NAND_DENALI
- socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
-#endif
-
return 0;
}
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c
index f176c38..f8dd787 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -103,3 +103,12 @@
writel(~RSTMGR_PER0MODRST_OCP_MASK, &reset_manager_base->per0modrst);
writel(0, &reset_manager_base->per0modrst);
}
+
+/*
+ * Return non-zero if the CPU has been warm reset
+ */
+int cpu_has_been_warmreset(void)
+{
+ return readl(&reset_manager_base->status) &
+ RSTMGR_L4WD_MPU_WARMRESET_MASK;
+}
diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index 142b60f..9dd0afb 100644
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -21,6 +21,7 @@
#include <debug_uart.h>
#include <fdtdec.h>
#include <watchdog.h>
+#include <dm/uclass.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -38,16 +39,12 @@
return BOOT_DEVICE_RAM;
case 0x2: /* NAND Flash (1.8V) */
case 0x3: /* NAND Flash (3.0V) */
- socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
return BOOT_DEVICE_NAND;
case 0x4: /* SD/MMC External Transceiver (1.8V) */
case 0x5: /* SD/MMC Internal Transceiver (3.0V) */
- socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
- socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
return BOOT_DEVICE_MMC1;
case 0x6: /* QSPI Flash (1.8V) */
case 0x7: /* QSPI Flash (3.0V) */
- socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
return BOOT_DEVICE_SPI;
default:
printf("Invalid boot device (bsel=%08x)!\n", bsel);
@@ -123,9 +120,9 @@
void board_init_f(ulong dummy)
{
const struct cm_config *cm_default_cfg = cm_get_default_config();
- unsigned long sdram_size;
unsigned long reg;
int ret;
+ struct udevice *dev;
/*
* First C code to run. Clear fake OCRAM ECC first as SBE
@@ -156,10 +153,7 @@
socfpga_bridges_reset(1);
}
- socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
- socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
-
timer_init();
debug("Reconfigure Clock Manager\n");
@@ -181,8 +175,7 @@
sysmgr_pinmux_init();
sysmgr_config_warmrstcfgio(0);
- /* De-assert reset for peripherals and bridges based on handoff */
- reset_deassert_peripherals_handoff();
+ /* De-assert reset for bridges based on handoff */
socfpga_bridges_reset(0);
debug("Unfreezing/Thaw all I/O banks\n");
@@ -200,27 +193,16 @@
hang();
}
+ ret = uclass_get_device(UCLASS_RESET, 0, &dev);
+ if (ret)
+ debug("Reset init failed: %d\n", ret);
+
/* enable console uart printing */
preloader_console_init();
- if (sdram_mmr_init_full(0xffffffff) != 0) {
- puts("SDRAM init failed.\n");
- hang();
- }
-
- debug("SDRAM: Calibrating PHY\n");
- /* SDRAM calibration */
- if (sdram_calibration_full() == 0) {
- puts("SDRAM calibration failed.\n");
- hang();
- }
-
- sdram_size = sdram_calculate_size();
- debug("SDRAM: %ld MiB\n", sdram_size >> 20);
-
- /* Sanity check ensure correct SDRAM size specified */
- if (get_ram_size(0, sdram_size) != sdram_size) {
- puts("SDRAM size check failed!\n");
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ debug("DRAM init failed: %d\n", ret);
hang();
}
diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
index a3db20a..a141ffe 100644
--- a/arch/arm/mach-socfpga/spl_s10.c
+++ b/arch/arm/mach-socfpga/spl_s10.c
@@ -181,17 +181,6 @@
hang();
}
- gd->ram_size = sdram_calculate_size();
- printf("DDR: %d MiB\n", (int)(gd->ram_size >> 20));
-
- /* Sanity check ensure correct SDRAM size specified */
- debug("DDR: Running SDRAM size sanity check\n");
- if (get_ram_size(0, gd->ram_size) != gd->ram_size) {
- puts("DDR: SDRAM size check failed!\n");
- hang();
- }
- debug("DDR: SDRAM size check passed!\n");
-
mbox_init();
#ifdef CONFIG_CADENCE_QSPI
diff --git a/arch/mips/dts/brcm,bcm6838.dtsi b/arch/mips/dts/brcm,bcm6838.dtsi
index c060802..6676f83 100644
--- a/arch/mips/dts/brcm,bcm6838.dtsi
+++ b/arch/mips/dts/brcm,bcm6838.dtsi
@@ -125,5 +125,18 @@
status = "disabled";
};
+
+ nand: nand-controller@14e02200 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,nand-bcm6838",
+ "brcm,brcmnand-v5.0",
+ "brcm,brcmnand";
+ reg-names = "nand", "nand-int-base", "nand-cache";
+ reg = <0x14e02200 0x180>,
+ <0x14e000f0 0x10>,
+ <0x14e02600 0x180>;
+ status = "disabled";
+ };
};
};
diff --git a/arch/mips/dts/brcm,bcm968380gerg.dts b/arch/mips/dts/brcm,bcm968380gerg.dts
index 98471e3..5a5ac0e 100644
--- a/arch/mips/dts/brcm,bcm968380gerg.dts
+++ b/arch/mips/dts/brcm,bcm968380gerg.dts
@@ -50,3 +50,15 @@
&gpio_mid1 {
status = "okay";
};
+
+&nand {
+ status = "okay";
+
+ nandcs@0 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ brcm,nand-oob-sector-size = <16>;
+ };
+};
diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h
index fc52f47..e956a05 100644
--- a/arch/sandbox/include/asm/test.h
+++ b/arch/sandbox/include/asm/test.h
@@ -59,14 +59,6 @@
void sandbox_i2c_eeprom_set_offset_len(struct udevice *dev, int offset_len);
-/*
- * sandbox_timer_add_offset()
- *
- * Allow tests to add to the time reported through lib/time.c functions
- * offset: number of milliseconds to advance the system time
- */
-void sandbox_timer_add_offset(unsigned long offset);
-
/**
* sandbox_i2c_rtc_set_offset() - set the time offset from system/base time
*
diff --git a/board/amlogic/odroid-c2/MAINTAINERS b/board/amlogic/p200/MAINTAINERS
similarity index 70%
rename from board/amlogic/odroid-c2/MAINTAINERS
rename to board/amlogic/p200/MAINTAINERS
index 6a85306..96fe92d 100644
--- a/board/amlogic/odroid-c2/MAINTAINERS
+++ b/board/amlogic/p200/MAINTAINERS
@@ -1,8 +1,8 @@
-ODROID-C2
+P200
M: Beniamino Galvani <b.galvani@gmail.com>
M: Neil Armstrong <narmstrong@baylibre.com>
S: Maintained
-F: board/amlogic/odroid-c2/
-F: include/configs/odroid-c2.h
+F: board/amlogic/p200/
F: configs/nanopi-k2_defconfig
F: configs/odroid-c2_defconfig
+F: configs/p200_defconfig
diff --git a/board/amlogic/odroid-c2/Makefile b/board/amlogic/p200/Makefile
similarity index 82%
rename from board/amlogic/odroid-c2/Makefile
rename to board/amlogic/p200/Makefile
index a6a3db7..f82a7ea 100644
--- a/board/amlogic/odroid-c2/Makefile
+++ b/board/amlogic/p200/Makefile
@@ -2,4 +2,4 @@
#
# (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
-obj-y := odroid-c2.o
+obj-y := p200.o
diff --git a/board/amlogic/odroid-c2/README.nanopi-k2 b/board/amlogic/p200/README.nanopi-k2
similarity index 100%
rename from board/amlogic/odroid-c2/README.nanopi-k2
rename to board/amlogic/p200/README.nanopi-k2
diff --git a/board/amlogic/odroid-c2/README.odroid-c2 b/board/amlogic/p200/README.odroid-c2
similarity index 100%
rename from board/amlogic/odroid-c2/README.odroid-c2
rename to board/amlogic/p200/README.odroid-c2
diff --git a/board/amlogic/p200/README.p200 b/board/amlogic/p200/README.p200
new file mode 100644
index 0000000..01d82d1
--- /dev/null
+++ b/board/amlogic/p200/README.p200
@@ -0,0 +1,103 @@
+U-Boot for Amlogic P200
+=======================
+
+P200 is a reference board manufactured by Amlogic with the following
+specifications:
+
+ - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz
+ - ARM Mali 450 GPU
+ - 2GB DDR3 SDRAM
+ - Gigabit Ethernet
+ - HDMI 2.0 4K/60Hz display
+ - 2 x USB 2.0 Host
+ - eMMC, microSD
+ - Infrared receiver
+ - SDIO WiFi Module
+ - CVBS+Stereo Audio Jack
+
+Schematics are available from Amlogic on demand.
+
+Currently the u-boot port supports the following devices:
+ - serial
+ - eMMC, microSD
+ - Ethernet
+ - I2C
+ - Regulators
+ - Reset controller
+ - Clock controller
+ - USB Host
+ - ADC
+
+u-boot compilation
+==================
+
+ > export ARCH=arm
+ > export CROSS_COMPILE=aarch64-none-elf-
+ > make p200_defconfig
+ > make
+
+Image creation
+==============
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+the git tree published by the board vendor:
+
+ > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+ > git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot
+ > cd amlogic-u-boot
+ > make gxb_p200_v1_defconfig
+ > make
+ > export FIPDIR=$PWD/fip
+
+Go back to mainline U-boot source tree then :
+ > mkdir fip
+
+ > cp $FIPDIR/gxl/bl2.bin fip/
+ > cp $FIPDIR/gxl/acs.bin fip/
+ > cp $FIPDIR/gxl/bl21.bin fip/
+ > cp $FIPDIR/gxl/bl30.bin fip/
+ > cp $FIPDIR/gxl/bl301.bin fip/
+ > cp $FIPDIR/gxl/bl31.img fip/
+ > cp u-boot.bin fip/bl33.bin
+
+ > $FIPDIR/blx_fix.sh \
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
+
+ > $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+
+ > $FIPDIR/blx_fix.sh \
+ fip/bl2_acs.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/bl21.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
+ > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
+ > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
+ > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
+ > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
+ > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc
+
+and then write the image to SD with:
+
+ > DEV=/dev/your_sd_device
+ > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
diff --git a/board/amlogic/odroid-c2/odroid-c2.c b/board/amlogic/p200/p200.c
similarity index 100%
rename from board/amlogic/odroid-c2/odroid-c2.c
rename to board/amlogic/p200/p200.c
diff --git a/board/amlogic/p201/MAINTAINERS b/board/amlogic/p201/MAINTAINERS
new file mode 100644
index 0000000..3e84a8e
--- /dev/null
+++ b/board/amlogic/p201/MAINTAINERS
@@ -0,0 +1,5 @@
+P201
+M: Neil Armstrong <narmstrong@baylibre.com>
+S: Maintained
+F: board/amlogic/p201/
+F: configs/p201_defconfig
diff --git a/board/amlogic/odroid-c2/Makefile b/board/amlogic/p201/Makefile
similarity index 82%
copy from board/amlogic/odroid-c2/Makefile
copy to board/amlogic/p201/Makefile
index a6a3db7..11de539 100644
--- a/board/amlogic/odroid-c2/Makefile
+++ b/board/amlogic/p201/Makefile
@@ -2,4 +2,4 @@
#
# (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
-obj-y := odroid-c2.o
+obj-y := p201.o
diff --git a/board/amlogic/p201/README.p201 b/board/amlogic/p201/README.p201
new file mode 100644
index 0000000..c251096
--- /dev/null
+++ b/board/amlogic/p201/README.p201
@@ -0,0 +1,103 @@
+U-Boot for Amlogic P201
+=======================
+
+P201 is a reference board manufactured by Amlogic with the following
+specifications:
+
+ - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz
+ - ARM Mali 450 GPU
+ - 2GB DDR3 SDRAM
+ - 10/100 Ethernet
+ - HDMI 2.0 4K/60Hz display
+ - 2 x USB 2.0 Host
+ - eMMC, microSD
+ - Infrared receiver
+ - SDIO WiFi Module
+ - CVBS+Stereo Audio Jack
+
+Schematics are available from Amlogic on demand.
+
+Currently the u-boot port supports the following devices:
+ - serial
+ - eMMC, microSD
+ - Ethernet
+ - I2C
+ - Regulators
+ - Reset controller
+ - Clock controller
+ - USB Host
+ - ADC
+
+u-boot compilation
+==================
+
+ > export ARCH=arm
+ > export CROSS_COMPILE=aarch64-none-elf-
+ > make p201_defconfig
+ > make
+
+Image creation
+==============
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+the git tree published by the board vendor:
+
+ > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+ > git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot
+ > cd amlogic-u-boot
+ > make gxb_p201_v1_defconfig
+ > make
+ > export FIPDIR=$PWD/fip
+
+Go back to mainline U-boot source tree then :
+ > mkdir fip
+
+ > cp $FIPDIR/gxl/bl2.bin fip/
+ > cp $FIPDIR/gxl/acs.bin fip/
+ > cp $FIPDIR/gxl/bl21.bin fip/
+ > cp $FIPDIR/gxl/bl30.bin fip/
+ > cp $FIPDIR/gxl/bl301.bin fip/
+ > cp $FIPDIR/gxl/bl31.img fip/
+ > cp u-boot.bin fip/bl33.bin
+
+ > $FIPDIR/blx_fix.sh \
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
+
+ > $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+
+ > $FIPDIR/blx_fix.sh \
+ fip/bl2_acs.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/bl21.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
+ > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
+ > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
+ > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
+ > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
+ > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc
+
+and then write the image to SD with:
+
+ > DEV=/dev/your_sd_device
+ > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
diff --git a/board/amlogic/p201/p201.c b/board/amlogic/p201/p201.c
new file mode 100644
index 0000000..ef0c65c
--- /dev/null
+++ b/board/amlogic/p201/p201.c
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <environment.h>
+#include <asm/io.h>
+#include <asm/arch/gx.h>
+#include <asm/arch/sm.h>
+#include <asm/arch/eth.h>
+#include <asm/arch/mem.h>
+
+#define EFUSE_SN_OFFSET 20
+#define EFUSE_SN_SIZE 16
+#define EFUSE_MAC_OFFSET 52
+#define EFUSE_MAC_SIZE 6
+
+int misc_init_r(void)
+{
+ u8 mac_addr[EFUSE_MAC_SIZE];
+ char serial[EFUSE_SN_SIZE];
+ ssize_t len;
+
+ meson_eth_init(PHY_INTERFACE_MODE_RMII, 0);
+
+ if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
+ len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
+ mac_addr, EFUSE_MAC_SIZE);
+ if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
+ eth_env_set_enetaddr("ethaddr", mac_addr);
+ }
+
+ if (!env_get("serial#")) {
+ len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
+ EFUSE_SN_SIZE);
+ if (len == EFUSE_SN_SIZE)
+ env_set("serial#", serial);
+ }
+
+ return 0;
+}
diff --git a/board/amlogic/p212/MAINTAINERS b/board/amlogic/p212/MAINTAINERS
index 07ca6f2..74ad371 100644
--- a/board/amlogic/p212/MAINTAINERS
+++ b/board/amlogic/p212/MAINTAINERS
@@ -4,5 +4,6 @@
F: board/amlogic/p212/
F: include/configs/p212.h
F: configs/khadas-vim_defconfig
+F: configs/libretech-ac_defconfig
F: configs/libretech-cc_defconfig
F: configs/p212_defconfig
diff --git a/board/amlogic/p212/README.libretech-ac b/board/amlogic/p212/README.libretech-ac
new file mode 100644
index 0000000..5386042
--- /dev/null
+++ b/board/amlogic/p212/README.libretech-ac
@@ -0,0 +1,103 @@
+U-Boot for LibreTech AC
+=======================
+
+LibreTech AC is a single board computer manufactured by Libre Technology
+with the following specifications:
+
+ - Amlogic S805X ARM Cortex-A53 quad-core SoC @ 1.2GHz
+ - ARM Mali 450 GPU
+ - 512MiB DDR4 SDRAM
+ - 10/100 Ethernet
+ - HDMI 2.0 4K/60Hz display
+ - 40-pin GPIO header
+ - 4 x USB 2.0 Host
+ - eMMC, SPI NOR Flash
+ - Infrared receiver
+
+Schematics are available on the manufacturer website.
+
+Currently the U-Boot port supports the following devices:
+ - serial
+ - eMMC
+ - Ethernet
+ - USB
+
+U-Boot compilation
+==================
+
+ > export ARCH=arm
+ > export CROSS_COMPILE=aarch64-none-elf-
+ > make libretech-ac_defconfig
+ > make
+
+Image creation
+==============
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+the git tree published by the board vendor:
+
+ > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+ > git clone https://github.com/BayLibre/u-boot.git -b libretech-ac amlogic-u-boot
+ > cd amlogic-u-boot
+ > wget https://raw.githubusercontent.com/BayLibre/u-boot/libretech-cc/fip/blx_fix.sh
+ > make libretech_ac_defconfig
+ > make
+ > export UBOOTDIR=$PWD
+
+Download the latest Amlogic Buildroot package, and extract it :
+ > wget http://openlinux2.amlogic.com:8000/ARM/filesystem/Linux_BSP/buildroot_openlinux_kernel_4.9_fbdev_20180418.tar.gz
+ > tar xfz buildroot_openlinux_kernel_4.9_fbdev_20180418.tar.gz buildroot_openlinux_kernel_4.9_fbdev_20180418/bootloader
+ > export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180418
+
+Go back to mainline U-Boot source tree then :
+ > mkdir fip
+
+ > cp $UBOOTDIR/build/scp_task/bl301.bin fip/
+ > cp $UBOOTDIR/build/board/amlogic/libretech_ac/firmware/bl21.bin fip/
+ > cp $UBOOTDIR/build/board/amlogic/libretech_ac/firmware/acs.bin fip/
+ > cp $BRDIR/bootloader/uboot-repo/bl2/bin/gxl/bl2.bin fip/
+ > cp $BRDIR/bootloader/uboot-repo/bl30/bin/gxl/bl30.bin fip/
+ > cp $BRDIR/bootloader/uboot-repo/bl31/bin/gxl/bl31.img fip/
+ > cp u-boot.bin fip/bl33.bin
+
+ > sh $UBOOTDIR/blx_fix.sh \
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
+
+ > $BRDIR/bootloader/uboot-repo/fip/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+
+ > sh $UBOOTDIR/blx_fix.sh \
+ fip/bl2_acs.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/bl21.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
+ > $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
+ > $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
+ > $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
+ > $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
+ > $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bootmk \
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc
+
+and then write the image to SD with:
+
+ > DEV=/dev/your_sd_device
+ > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
diff --git a/board/amlogic/q200/README.khadas-vim2 b/board/amlogic/q200/README.khadas-vim2
index 578693f..8bcfc29 100644
--- a/board/amlogic/q200/README.khadas-vim2
+++ b/board/amlogic/q200/README.khadas-vim2
@@ -48,9 +48,9 @@
> tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
> tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
> export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
- > git clone https://github.com/khadas/u-boot -b Vim vim-u-boot
+ > git clone https://github.com/khadas/u-boot -b khadas-vim-v2015.01 vim-u-boot
> cd vim-u-boot
- > make kvim_defconfig
+ > make kvim2_defconfig
> make
> export FIPDIR=$PWD/fip
diff --git a/board/amlogic/u200/MAINTAINERS b/board/amlogic/u200/MAINTAINERS
new file mode 100644
index 0000000..baf3813
--- /dev/null
+++ b/board/amlogic/u200/MAINTAINERS
@@ -0,0 +1,5 @@
+U200
+M: Neil Armstrong <narmstrong@baylibre.com>
+S: Maintained
+F: board/amlogic/u200/
+F: configs/u200_defconfig
diff --git a/board/amlogic/u200/Makefile b/board/amlogic/u200/Makefile
new file mode 100644
index 0000000..485791b
--- /dev/null
+++ b/board/amlogic/u200/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2016 BayLibre, SAS
+# Author: Neil Armstrong <narmstrong@baylibre.com>
+
+obj-y := u200.o
diff --git a/board/amlogic/u200/README b/board/amlogic/u200/README
new file mode 100644
index 0000000..bffac5e
--- /dev/null
+++ b/board/amlogic/u200/README
@@ -0,0 +1,128 @@
+U-Boot for Amlogic U200
+=======================
+
+U200 is a reference board manufactured by Amlogic with the following
+specifications:
+
+ - Amlogic S905D2 ARM Cortex-A53 quad-core SoC
+ - 2GB DDR4 SDRAM
+ - 10/100 Ethernet (Internal PHY)
+ - 1 x USB 3.0 Host
+ - eMMC
+ - SDcard
+ - Infrared receiver
+ - SDIO WiFi Module
+ - MIPI DSI Connector
+ - Audio HAT Connector
+ - PCI-E M.2 Connector
+
+Schematics are available from Amlogic on demand.
+
+Currently the u-boot port supports the following devices:
+ - serial
+ - Ethernet
+ - Regulators
+ - Clock controller
+
+u-boot compilation
+==================
+
+ > export ARCH=arm
+ > export CROSS_COMPILE=aarch64-none-elf-
+ > make u200_defconfig
+ > make
+
+Image creation
+==============
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+the git tree published by the board vendor:
+
+ > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+ > git clone https://github.com/BayLibre/u-boot.git -b buildroot-openlinux-20180418 amlogic-u-boot
+ > cd amlogic-u-boot
+ > make g12a_u200_v1_defconfig
+ > make
+ > export UBOOTDIR=$PWD
+
+Download the latest Amlogic Buildroot package, and extract it :
+ > wget http://openlinux2.amlogic.com:8000/ARM/filesystem/Linux_BSP/buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz
+ > tar xfz buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz buildroot_openlinux_kernel_4.9_fbdev_20180706/bootloader
+ > export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180706
+ > export FIPDIR=$BRDIR/bootloader/uboot-repo/fip
+
+Go back to mainline U-Boot source tree then :
+ > mkdir fip
+
+ > wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh
+ > cp $UBOOTDIR/build/scp_task/bl301.bin fip/
+ > cp $UBOOTDIR/build/board/amlogic/g12a_u200_v1/firmware/acs.bin fip/
+ > cp $BRDIR/bootloader/uboot-repo/bl2/bin/g12a/bl2.bin fip/
+ > cp $BRDIR/bootloader/uboot-repo/bl30/bin/g12a/bl30.bin fip/
+ > cp $BRDIR/bootloader/uboot-repo/bl31_1.3/bin/g12a/bl31.img fip/
+ > cp $FIPDIR/g12a/ddr3_1d.fw fip/
+ > cp $FIPDIR/g12a/ddr4_1d.fw fip/
+ > cp $FIPDIR/g12a/ddr4_2d.fw fip/
+ > cp $FIPDIR/g12a/diag_lpddr4.fw fip/
+ > cp $FIPDIR/g12a/lpddr4_1d.fw fip/
+ > cp $FIPDIR/g12a/lpddr4_2d.fw fip/
+ > cp $FIPDIR/g12a/piei.fw fip/
+ > cp u-boot.bin fip/bl33.bin
+
+ > sh fip/blx_fix.sh \
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
+
+ > sh fip/blx_fix.sh \
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
+ > $FIPDIR/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \
+ --output fip/bl30_new.bin.g12a.enc \
+ --level v3
+ > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
+ > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
+ > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33
+ > $FIPDIR/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \
+ --output fip/bl2.n.bin.sig
+ > $FIPDIR/g12a/aml_encrypt_g12a --bootmk \
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc \
+ --ddrfw1 fip/ddr4_1d.fw \
+ --ddrfw2 fip/ddr4_2d.fw \
+ --ddrfw3 fip/ddr3_1d.fw \
+ --ddrfw4 fip/piei.fw \
+ --ddrfw5 fip/lpddr4_1d.fw \
+ --ddrfw6 fip/lpddr4_2d.fw \
+ --ddrfw7 fip/diag_lpddr4.fw \
+ --level v3
+
+and then write the image to SD with:
+
+ > DEV=/dev/your_sd_device
+ > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
diff --git a/board/amlogic/u200/u200.c b/board/amlogic/u200/u200.c
new file mode 100644
index 0000000..94ee3ce
--- /dev/null
+++ b/board/amlogic/u200/u200.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <environment.h>
+#include <asm/io.h>
+#include <asm/arch/axg.h>
+#include <asm/arch/sm.h>
+#include <asm/arch/eth.h>
+#include <asm/arch/mem.h>
+
+int misc_init_r(void)
+{
+ meson_eth_init(PHY_INTERFACE_MODE_RMII,
+ MESON_USE_INTERNAL_RMII_PHY);
+
+ return 0;
+}
diff --git a/board/atmel/sama5d2_icp/Kconfig b/board/atmel/sama5d2_icp/Kconfig
new file mode 100644
index 0000000..3859845
--- /dev/null
+++ b/board/atmel/sama5d2_icp/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SAMA5D2_ICP
+
+config SYS_BOARD
+ default "sama5d2_icp"
+
+config SYS_VENDOR
+ default "atmel"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "sama5d2_icp"
+
+endif
diff --git a/board/atmel/sama5d2_icp/MAINTAINERS b/board/atmel/sama5d2_icp/MAINTAINERS
new file mode 100644
index 0000000..db984b6
--- /dev/null
+++ b/board/atmel/sama5d2_icp/MAINTAINERS
@@ -0,0 +1,7 @@
+SAMA5D2 ICP BOARD
+M: Eugen Hristev <eugen.hristev@microchip.com>
+S: Maintained
+F: board/atmel/sama5d2_icp/
+F: include/configs/sama5d2_icp.h
+F: configs/sama5d2_icp_mmc_defconfig
+
diff --git a/board/atmel/sama5d2_icp/Makefile b/board/atmel/sama5d2_icp/Makefile
new file mode 100644
index 0000000..fd7e870
--- /dev/null
+++ b/board/atmel/sama5d2_icp/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018 Microchip Technology Inc.
+# Eugen Hristev <eugen.hristev@microchip.com>
+#
+
+obj-y += sama5d2_icp.o
diff --git a/board/atmel/sama5d2_icp/sama5d2_icp.c b/board/atmel/sama5d2_icp/sama5d2_icp.c
new file mode 100644
index 0000000..807cfcd
--- /dev/null
+++ b/board/atmel/sama5d2_icp/sama5d2_icp.c
@@ -0,0 +1,191 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Microchip Technology, Inc.
+ * Eugen Hristev <eugen.hristev@microchip.com>
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/atmel_pio4.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/atmel_sdhci.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sama5d2.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_late_init(void)
+{
+ return 0;
+}
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+static void board_uart0_hw_init(void)
+{
+ atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, ATMEL_PIO_PUEN_MASK); /* URXD0 */
+ atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */
+
+ at91_periph_clk_enable(ATMEL_ID_UART0);
+}
+
+void board_debug_uart_init(void)
+{
+ board_uart0_hw_init();
+}
+#endif
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+ debug_uart_init();
+#endif
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+#define MAC24AA_MAC_OFFSET 0xfa
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_I2C_EEPROM
+ at91_set_ethaddr(MAC24AA_MAC_OFFSET);
+#endif
+ return 0;
+}
+
+/* SPL */
+#ifdef CONFIG_SPL_BUILD
+
+#ifdef CONFIG_SD_BOOT
+void spl_mmc_init(void)
+{
+ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 1, 0); /* CMD */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 2, 0); /* DAT0 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 3, 0); /* DAT1 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 4, 0); /* DAT2 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 5, 0); /* DAT3 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 0, 0); /* CK */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 13, 0); /* CD */
+
+ at91_periph_clk_enable(ATMEL_ID_SDMMC0);
+}
+#endif
+
+void spl_board_init(void)
+{
+#ifdef CONFIG_SD_BOOT
+ spl_mmc_init();
+#endif
+}
+
+void spl_display_print(void)
+{
+}
+
+static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
+{
+ ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM);
+
+ ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+ ATMEL_MPDDRC_CR_NR_ROW_14 |
+ ATMEL_MPDDRC_CR_CAS_DDR_CAS5 |
+ ATMEL_MPDDRC_CR_DIC_DS |
+ ATMEL_MPDDRC_CR_NB_8BANKS |
+ ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
+ ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
+
+ ddrc->rtr = 0x298;
+
+ ddrc->tpr0 = ((6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
+ (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) |
+ (3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) |
+ (9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) |
+ (3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) |
+ (4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) |
+ (4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) |
+ (4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET));
+
+ ddrc->tpr1 = ((27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
+ (29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) |
+ (0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) |
+ (10 << ATMEL_MPDDRC_TPR1_TXP_OFFSET));
+
+ ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
+ (0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) |
+ (0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) |
+ (4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) |
+ (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
+}
+
+void mem_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
+ struct atmel_mpddrc_config ddrc_config;
+ u32 reg;
+
+ ddrc_conf(&ddrc_config);
+
+ at91_periph_clk_enable(ATMEL_ID_MPDDRC);
+ writel(AT91_PMC_DDR, &pmc->scer);
+
+ reg = readl(&mpddrc->io_calibr);
+ reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
+ reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
+ reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
+ reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
+ writel(reg, &mpddrc->io_calibr);
+
+ writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE,
+ &mpddrc->rd_data_path);
+
+ ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
+
+ writel(0x5355, &mpddrc->cal_mr4);
+ writel(64, &mpddrc->tim_cal);
+}
+
+void at91_pmc_init(void)
+{
+ u32 tmp;
+
+ /*
+ * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz
+ * so we need to slow down and configure MCKR accordingly.
+ * This is why we have a special flavor of the switching function.
+ */
+ tmp = AT91_PMC_MCKR_PLLADIV_2 |
+ AT91_PMC_MCKR_MDIV_3 |
+ AT91_PMC_MCKR_CSS_MAIN;
+ at91_mck_init_down(tmp);
+
+ tmp = AT91_PMC_PLLAR_29 |
+ AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
+ AT91_PMC_PLLXR_MUL(82) |
+ AT91_PMC_PLLXR_DIV(1);
+ at91_plla_init(tmp);
+
+ tmp = AT91_PMC_MCKR_H32MXDIV |
+ AT91_PMC_MCKR_PLLADIV_2 |
+ AT91_PMC_MCKR_MDIV_3 |
+ AT91_PMC_MCKR_CSS_PLLA;
+ at91_mck_init(tmp);
+}
+#endif
diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c
index e8ec553..1bc2682 100644
--- a/board/davinci/da8xxevm/da850evm.c
+++ b/board/davinci/da8xxevm/da850evm.c
@@ -204,25 +204,6 @@
return 0;
}
-#ifndef CONFIG_DM_MMC
-#ifdef CONFIG_MMC_DAVINCI
-static struct davinci_mmc mmc_sd0 = {
- .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
- .host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */
- .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
- .version = MMC_CTLR_VERSION_2,
-};
-
-int board_mmc_init(bd_t *bis)
-{
- mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID);
-
- /* Add slot-0 to mmc subsystem */
- return davinci_mmc_init(bis, &mmc_sd0);
-}
-#endif
-#endif
-
static const struct pinmux_config gpio_pins[] = {
#ifdef CONFIG_USE_NOR
/* GP0[11] is required for NOR to work on Rev 3 EVMs */
diff --git a/board/sandbox/sandbox.c b/board/sandbox/sandbox.c
index 397e756..9ca1eca 100644
--- a/board/sandbox/sandbox.c
+++ b/board/sandbox/sandbox.c
@@ -31,7 +31,7 @@
/* system timer offset in ms */
static unsigned long sandbox_timer_offset;
-void sandbox_timer_add_offset(unsigned long offset)
+void timer_test_add_offset(unsigned long offset)
{
sandbox_timer_offset += offset;
}
diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
index 24d299a..76917b0 100644
--- a/board/st/stm32mp1/stm32mp1.c
+++ b/board/st/stm32mp1/stm32mp1.c
@@ -7,7 +7,9 @@
#include <config.h>
#include <clk.h>
#include <dm.h>
+#include <g_dnl.h>
#include <generic-phy.h>
+#include <i2c.h>
#include <led.h>
#include <misc.h>
#include <phy.h>
@@ -58,11 +60,6 @@
*/
DECLARE_GLOBAL_DATA_PTR;
-#define STM32MP_GUSBCFG 0x40002407
-
-#define STM32MP_GGPIO 0x38
-#define STM32MP_GGPIO_VBUS_SENSING BIT(21)
-
#define USB_WARNING_LOW_THRESHOLD_UV 660000
#define USB_START_LOW_THRESHOLD_UV 1230000
#define USB_START_HIGH_THRESHOLD_UV 2100000
@@ -155,149 +152,75 @@
#endif
}
-static struct dwc2_plat_otg_data stm32mp_otg_data = {
- .usb_gusbcfg = STM32MP_GUSBCFG,
-};
+#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
-static struct reset_ctl usbotg_reset;
+/* STMicroelectronics STUSB1600 Type-C controller */
+#define STUSB1600_CC_CONNECTION_STATUS 0x0E
-int board_usb_init(int index, enum usb_init_type init)
+/* STUSB1600_CC_CONNECTION_STATUS bitfields */
+#define STUSB1600_CC_ATTACH BIT(0)
+
+static int stusb1600_init(struct udevice **dev_stusb1600)
{
- struct fdtdec_phandle_args args;
- struct udevice *dev;
- const void *blob = gd->fdt_blob;
- struct clk clk;
- struct phy phy;
- int node;
- int phy_provider;
+ ofnode node;
+ struct udevice *dev, *bus;
int ret;
+ u32 chip_addr;
- /* find the usb otg node */
- node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2");
- if (node < 0) {
- debug("Not found usb_otg device\n");
- return -ENODEV;
- }
+ *dev_stusb1600 = NULL;
- if (!fdtdec_get_is_enabled(blob, node)) {
- debug("stm32 usbotg is disabled in the device tree\n");
+ /* if node stusb1600 is present, means DK1 or DK2 board */
+ node = ofnode_by_compatible(ofnode_null(), "st,stusb1600");
+ if (!ofnode_valid(node))
return -ENODEV;
- }
-
- /* Enable clock */
- ret = fdtdec_parse_phandle_with_args(blob, node, "clocks",
- "#clock-cells", 0, 0, &args);
- if (ret) {
- debug("usbotg has no clocks defined in the device tree\n");
- return ret;
- }
- ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, &dev);
+ ret = ofnode_read_u32(node, "reg", &chip_addr);
if (ret)
- return ret;
+ return -EINVAL;
- if (args.args_count != 1) {
- debug("Can't find clock ID in the device tree\n");
- return -ENODATA;
- }
-
- clk.dev = dev;
- clk.id = args.args[0];
-
- ret = clk_enable(&clk);
- if (ret) {
- debug("Failed to enable usbotg clock\n");
- return ret;
- }
-
- /* Reset */
- ret = fdtdec_parse_phandle_with_args(blob, node, "resets",
- "#reset-cells", 0, 0, &args);
+ ret = uclass_get_device_by_ofnode(UCLASS_I2C, ofnode_get_parent(node),
+ &bus);
if (ret) {
- debug("usbotg has no resets defined in the device tree\n");
- goto clk_err;
+ printf("bus for stusb1600 not found\n");
+ return -ENODEV;
}
- ret = uclass_get_device_by_of_offset(UCLASS_RESET, args.node, &dev);
- if (ret || args.args_count != 1)
- goto clk_err;
-
- usbotg_reset.dev = dev;
- usbotg_reset.id = args.args[0];
-
- reset_assert(&usbotg_reset);
- udelay(2);
- reset_deassert(&usbotg_reset);
-
- /* Get USB PHY */
- ret = fdtdec_parse_phandle_with_args(blob, node, "phys",
- "#phy-cells", 0, 0, &args);
- if (!ret) {
- phy_provider = fdt_parent_offset(blob, args.node);
- ret = uclass_get_device_by_of_offset(UCLASS_PHY,
- phy_provider, &dev);
- if (ret)
- goto clk_err;
-
- phy.dev = dev;
- phy.id = fdtdec_get_uint(blob, args.node, "reg", -1);
-
- ret = generic_phy_power_on(&phy);
- if (ret) {
- debug("unable to power on the phy\n");
- goto clk_err;
- }
+ ret = dm_i2c_probe(bus, chip_addr, 0, &dev);
+ if (!ret)
+ *dev_stusb1600 = dev;
- ret = generic_phy_init(&phy);
- if (ret) {
- debug("failed to init usb phy\n");
- goto phy_power_err;
- }
- }
+ return ret;
+}
- /* Parse and store data needed for gadget */
- stm32mp_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
- if (stm32mp_otg_data.regs_otg == FDT_ADDR_T_NONE) {
- debug("usbotg: can't get base address\n");
- ret = -ENODATA;
- goto phy_init_err;
- }
+static int stusb1600_cable_connected(struct udevice *dev)
+{
+ u8 status;
- stm32mp_otg_data.rx_fifo_sz = fdtdec_get_int(blob, node,
- "g-rx-fifo-size", 0);
- stm32mp_otg_data.np_tx_fifo_sz = fdtdec_get_int(blob, node,
- "g-np-tx-fifo-size", 0);
- stm32mp_otg_data.tx_fifo_sz = fdtdec_get_int(blob, node,
- "g-tx-fifo-size", 0);
- /* Enable voltage level detector */
- if (!(fdtdec_parse_phandle_with_args(blob, node, "usb33d-supply",
- NULL, 0, 0, &args))) {
- if (!uclass_get_device_by_of_offset(UCLASS_REGULATOR,
- args.node, &dev)) {
- ret = regulator_set_enable(dev, true);
- if (ret) {
- debug("Failed to enable usb33d\n");
- goto phy_init_err;
- }
- }
- }
- /* Enable vbus sensing */
- setbits_le32(stm32mp_otg_data.regs_otg + STM32MP_GGPIO,
- STM32MP_GGPIO_VBUS_SENSING);
+ if (dm_i2c_read(dev, STUSB1600_CC_CONNECTION_STATUS, &status, 1))
+ return 0;
- return dwc2_udc_probe(&stm32mp_otg_data);
+ return status & STUSB1600_CC_ATTACH;
+}
-phy_init_err:
- generic_phy_exit(&phy);
+#include <usb/dwc2_udc.h>
+int g_dnl_board_usb_cable_connected(void)
+{
+ struct udevice *stusb1600;
+ struct udevice *dwc2_udc_otg;
+ int ret;
-phy_power_err:
- generic_phy_power_off(&phy);
+ if (!stusb1600_init(&stusb1600))
+ return stusb1600_cable_connected(stusb1600);
-clk_err:
- clk_disable(&clk);
+ ret = uclass_get_device_by_driver(UCLASS_USB_GADGET_GENERIC,
+ DM_GET_DRIVER(dwc2_udc_otg),
+ &dwc2_udc_otg);
+ if (!ret)
+ debug("dwc2_udc_otg init failed\n");
- return ret;
+ return dwc2_udc_B_session_valid(dwc2_udc_otg);
}
+#endif /* CONFIG_USB_GADGET */
static int get_led(struct udevice **dev, char *led_string)
{
@@ -438,16 +361,6 @@
return 0;
}
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
- /* Reset usbotg */
- reset_assert(&usbotg_reset);
- udelay(2);
- reset_deassert(&usbotg_reset);
-
- return 0;
-}
-
static void sysconf_init(void)
{
#ifndef CONFIG_STM32MP1_TRUSTED
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 2bdbfcb..5d1999e 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1433,6 +1433,12 @@
particularly for managing boot parameters as well as examining
various EFI status for debugging.
+config CMD_EXCEPTION
+ bool "exception - raise exception"
+ depends on ARM || RISCV || X86
+ help
+ Enable the 'exception' command which allows to raise an exception.
+
config CMD_LED
bool "led"
depends on LED
diff --git a/cmd/Makefile b/cmd/Makefile
index 6b1c6b0..7864fcf 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -173,6 +173,8 @@
# Android Verified Boot 2.0
obj-$(CONFIG_CMD_AVB) += avb.o
+obj-$(CONFIG_ARM) += arm/
+obj-$(CONFIG_RISCV) += riscv/
obj-$(CONFIG_X86) += x86/
obj-$(CONFIG_ARCH_MVEBU) += mvebu/
diff --git a/cmd/arm/Makefile b/cmd/arm/Makefile
new file mode 100644
index 0000000..94367dc
--- /dev/null
+++ b/cmd/arm/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+ifdef CONFIG_ARM64
+obj-$(CONFIG_CMD_EXCEPTION) += exception64.o
+else
+obj-$(CONFIG_CMD_EXCEPTION) += exception.o
+endif
diff --git a/cmd/arm/exception.c b/cmd/arm/exception.c
new file mode 100644
index 0000000..33bc759
--- /dev/null
+++ b/cmd/arm/exception.c
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * The 'exception' command can be used for testing exception handling.
+ *
+ * Copyright (c) 2018, Heinrich Schuchardt <xypron.glpk@gmx.de>
+ */
+
+#include <common.h>
+#include <command.h>
+
+static int do_unaligned(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ /*
+ * The LDRD instruction requires the data source to be four byte aligned
+ * even if strict alignment fault checking is disabled in the system
+ * control register.
+ */
+ asm volatile (
+ "MOV r5, sp\n"
+ "ADD r5, #1\n"
+ "LDRD r6, r7, [r5]\n");
+ return CMD_RET_FAILURE;
+}
+
+static int do_breakpoint(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ asm volatile ("BKPT #123\n");
+ return CMD_RET_FAILURE;
+}
+
+static int do_undefined(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ /*
+ * 0xe7f...f. is undefined in ARM mode
+ * 0xde.. is undefined in Thumb mode
+ */
+ asm volatile (".word 0xe7f7defb\n");
+ return CMD_RET_FAILURE;
+}
+
+static cmd_tbl_t cmd_sub[] = {
+ U_BOOT_CMD_MKENT(breakpoint, CONFIG_SYS_MAXARGS, 1, do_breakpoint,
+ "", ""),
+ U_BOOT_CMD_MKENT(unaligned, CONFIG_SYS_MAXARGS, 1, do_unaligned,
+ "", ""),
+ U_BOOT_CMD_MKENT(undefined, CONFIG_SYS_MAXARGS, 1, do_undefined,
+ "", ""),
+};
+
+static char exception_help_text[] =
+ "<ex>\n"
+ " The following exceptions are available:\n"
+ " breakpoint - prefetch abort\n"
+ " unaligned - data abort\n"
+ " undefined - undefined instruction\n"
+ ;
+
+#include <exception.h>
diff --git a/cmd/arm/exception64.c b/cmd/arm/exception64.c
new file mode 100644
index 0000000..a363818
--- /dev/null
+++ b/cmd/arm/exception64.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * The 'exception' command can be used for testing exception handling.
+ *
+ * Copyright (c) 2018, Heinrich Schuchardt <xypron.glpk@gmx.de>
+ */
+
+#include <common.h>
+#include <command.h>
+
+static int do_undefined(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ /*
+ * 0xe7f...f. is undefined in ARM mode
+ * 0xde.. is undefined in Thumb mode
+ */
+ asm volatile (".word 0xe7f7defb\n");
+ return CMD_RET_FAILURE;
+}
+
+static cmd_tbl_t cmd_sub[] = {
+ U_BOOT_CMD_MKENT(undefined, CONFIG_SYS_MAXARGS, 1, do_undefined,
+ "", ""),
+};
+
+static char exception_help_text[] =
+ "<ex>\n"
+ " The following exceptions are available:\n"
+ " undefined - undefined instruction\n"
+ ;
+
+#include <exception.h>
diff --git a/cmd/dfu.c b/cmd/dfu.c
index c9ba062..91a750a 100644
--- a/cmd/dfu.c
+++ b/cmd/dfu.c
@@ -27,8 +27,10 @@
#ifdef CONFIG_DFU_OVER_USB
char *usb_controller = argv[1];
#endif
+#if defined(CONFIG_DFU_OVER_USB) || defined(CONFIG_DFU_OVER_TFTP)
char *interface = argv[2];
char *devstring = argv[3];
+#endif
int ret = 0;
#ifdef CONFIG_DFU_OVER_TFTP
@@ -63,6 +65,7 @@
U_BOOT_CMD(dfu, CONFIG_SYS_MAXARGS, 1, do_dfu,
"Device Firmware Upgrade",
+ ""
#ifdef CONFIG_DFU_OVER_USB
"<USB_controller> <interface> <dev> [list]\n"
" - device firmware upgrade via <USB_controller>\n"
diff --git a/cmd/riscv/Makefile b/cmd/riscv/Makefile
new file mode 100644
index 0000000..24df023
--- /dev/null
+++ b/cmd/riscv/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-$(CONFIG_CMD_EXCEPTION) += exception.o
diff --git a/cmd/riscv/exception.c b/cmd/riscv/exception.c
new file mode 100644
index 0000000..547fb7d
--- /dev/null
+++ b/cmd/riscv/exception.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * The 'exception' command can be used for testing exception handling.
+ *
+ * Copyright (c) 2018, Heinrich Schuchardt <xypron.glpk@gmx.de>
+ */
+
+#include <common.h>
+#include <command.h>
+
+static int do_undefined(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ asm volatile (".word 0xffffffff\n");
+ return CMD_RET_FAILURE;
+}
+
+static cmd_tbl_t cmd_sub[] = {
+ U_BOOT_CMD_MKENT(undefined, CONFIG_SYS_MAXARGS, 1, do_undefined,
+ "", ""),
+};
+
+static char exception_help_text[] =
+ "<ex>\n"
+ " The following exceptions are available:\n"
+ " undefined - undefined instruction\n"
+ ;
+
+#include <exception.h>
diff --git a/cmd/usb_mass_storage.c b/cmd/usb_mass_storage.c
index 753ae4f..570cf3a 100644
--- a/cmd/usb_mass_storage.c
+++ b/cmd/usb_mass_storage.c
@@ -14,6 +14,7 @@
#include <part.h>
#include <usb.h>
#include <usb_mass_storage.h>
+#include <watchdog.h>
static int ums_read_sector(struct ums *ums_dev,
ulong start, lbaint_t blkcnt, void *buf)
@@ -226,6 +227,8 @@
rc = CMD_RET_SUCCESS;
goto cleanup_register;
}
+
+ WATCHDOG_RESET();
}
cleanup_register:
diff --git a/cmd/x86/Makefile b/cmd/x86/Makefile
index bcc6d06..7071614 100644
--- a/cmd/x86/Makefile
+++ b/cmd/x86/Makefile
@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y += mtrr.o
+obj-$(CONFIG_CMD_EXCEPTION) += exception.o
obj-$(CONFIG_HAVE_FSP) += fsp.o
diff --git a/cmd/x86/exception.c b/cmd/x86/exception.c
new file mode 100644
index 0000000..ade1e2e
--- /dev/null
+++ b/cmd/x86/exception.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * The 'exception' command can be used for testing exception handling.
+ *
+ * Copyright (c) 2018, Heinrich Schuchardt <xypron.glpk@gmx.de>
+ */
+
+#include <common.h>
+#include <command.h>
+
+static int do_undefined(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ asm volatile (".word 0xffff\n");
+ return CMD_RET_FAILURE;
+}
+
+static cmd_tbl_t cmd_sub[] = {
+ U_BOOT_CMD_MKENT(undefined, CONFIG_SYS_MAXARGS, 1, do_undefined,
+ "", ""),
+};
+
+static char exception_help_text[] =
+ "<ex>\n"
+ " The following exceptions are available:\n"
+ " undefined - undefined instruction\n"
+ ;
+
+#include <exception.h>
diff --git a/cmd/ximg.c b/cmd/ximg.c
index 8572a67..32bfae8 100644
--- a/cmd/ximg.c
+++ b/cmd/ximg.c
@@ -159,9 +159,9 @@
}
}
- /* get subimage data address and length */
- if (fit_image_get_data(fit_hdr, noffset,
- &fit_data, &fit_len)) {
+ /* get subimage/external data address and length */
+ if (fit_image_get_data_and_size(fit_hdr, noffset,
+ &fit_data, &fit_len)) {
puts("Could not find script subimage data\n");
return 1;
}
diff --git a/common/bootm.c b/common/bootm.c
index 3adbcea..b5d37d3 100644
--- a/common/bootm.c
+++ b/common/bootm.c
@@ -154,7 +154,7 @@
#ifdef CONFIG_ANDROID_BOOT_IMAGE
case IMAGE_FORMAT_ANDROID:
images.os.type = IH_TYPE_KERNEL;
- images.os.comp = IH_COMP_NONE;
+ images.os.comp = android_image_get_kcomp(os_hdr);
images.os.os = IH_OS_LINUX;
images.os.end = android_image_get_end(os_hdr);
@@ -450,7 +450,6 @@
ulong image_start = os.image_start;
ulong image_len = os.image_len;
ulong flush_start = ALIGN_DOWN(load, ARCH_DMA_MINALIGN);
- ulong flush_len;
bool no_overlap;
void *load_buf, *image_buf;
int err;
@@ -465,11 +464,7 @@
return err;
}
- flush_len = load_end - load;
- if (flush_start < load)
- flush_len += load - flush_start;
-
- flush_cache(flush_start, ALIGN(flush_len, ARCH_DMA_MINALIGN));
+ flush_cache(flush_start, ALIGN(load_end, ARCH_DMA_MINALIGN) - flush_start);
debug(" kernel loaded at 0x%08lx, end = 0x%08lx\n", load, load_end);
bootstage_mark(BOOTSTAGE_ID_KERNEL_LOADED);
diff --git a/common/dlmalloc.c b/common/dlmalloc.c
index edaad29..6f12a18 100644
--- a/common/dlmalloc.c
+++ b/common/dlmalloc.c
@@ -1893,8 +1893,7 @@
#if CONFIG_VAL(SYS_MALLOC_F_LEN)
if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT)) {
- nb = roundup(bytes, alignment);
- return malloc_simple(nb);
+ return memalign_simple(alignment, bytes);
}
#endif
diff --git a/common/image-android.c b/common/image-android.c
index 2f38c19..8b0f6b3 100644
--- a/common/image-android.c
+++ b/common/image-android.c
@@ -8,6 +8,7 @@
#include <android_image.h>
#include <malloc.h>
#include <errno.h>
+#include <asm/unaligned.h>
#define ANDROID_IMAGE_DEFAULT_KERNEL_ADDR 0x10008000
@@ -126,6 +127,16 @@
return android_image_get_kernel_addr(hdr);
}
+ulong android_image_get_kcomp(const struct andr_img_hdr *hdr)
+{
+ const void *p = (void *)((uintptr_t)hdr + hdr->page_size);
+
+ if (get_unaligned_le32(p) == LZ4F_MAGIC)
+ return IH_COMP_LZ4;
+ else
+ return IH_COMP_NONE;
+}
+
int android_image_get_ramdisk(const struct andr_img_hdr *hdr,
ulong *rd_data, ulong *rd_len)
{
@@ -186,7 +197,7 @@
printf("%skernel size: %x\n", p, hdr->kernel_size);
printf("%skernel address: %x\n", p, hdr->kernel_addr);
printf("%sramdisk size: %x\n", p, hdr->ramdisk_size);
- printf("%sramdisk addrress: %x\n", p, hdr->ramdisk_addr);
+ printf("%sramdisk address: %x\n", p, hdr->ramdisk_addr);
printf("%ssecond size: %x\n", p, hdr->second_size);
printf("%ssecond address: %x\n", p, hdr->second_addr);
printf("%stags address: %x\n", p, hdr->tags_addr);
diff --git a/common/image-fdt.c b/common/image-fdt.c
index 01186ae..9ed00b7 100644
--- a/common/image-fdt.c
+++ b/common/image-fdt.c
@@ -284,7 +284,7 @@
*of_flat_tree = NULL;
*of_size = 0;
- img_addr = simple_strtoul(argv[0], NULL, 16);
+ img_addr = (argc == 0) ? load_addr : simple_strtoul(argv[0], NULL, 16);
buf = map_sysmem(img_addr, 0);
if (argc > 2)
diff --git a/common/image-fit.c b/common/image-fit.c
index ac901e1..a74b44f 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -2118,6 +2118,18 @@
if (next_config)
*next_config++ = '\0';
uname = NULL;
+
+ /*
+ * fit_image_load() would load the first FDT from the
+ * extra config only when uconfig is specified.
+ * Check if the extra config contains multiple FDTs and
+ * if so, load them.
+ */
+ cfg_noffset = fit_conf_get_node(fit, uconfig);
+
+ i = 0;
+ count = fit_conf_get_prop_node_count(fit, cfg_noffset,
+ FIT_FDT_PROP);
}
debug("%d: using uname=%s uconfig=%s\n", i, uname, uconfig);
diff --git a/common/image.c b/common/image.c
index 4d4248f..75b84d5 100644
--- a/common/image.c
+++ b/common/image.c
@@ -957,7 +957,7 @@
*/
buf = map_sysmem(images->os.start, 0);
if (buf && genimg_get_format(buf) == IMAGE_FORMAT_ANDROID)
- select = argv[0];
+ select = (argc == 0) ? env_get("loadaddr") : argv[0];
#endif
if (argc >= 2)
diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c
index 6eb190f..e2bcefb 100644
--- a/common/spl/spl_nand.c
+++ b/common/spl/spl_nand.c
@@ -17,6 +17,10 @@
{
nand_init();
+ printf("Loading U-Boot from 0x%08x (size 0x%08x) to 0x%08x\n",
+ CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
+ CONFIG_SYS_NAND_U_BOOT_DST);
+
nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
CONFIG_SYS_NAND_U_BOOT_SIZE,
(void *)CONFIG_SYS_NAND_U_BOOT_DST);
diff --git a/common/spl/spl_ymodem.c b/common/spl/spl_ymodem.c
index 25226e9..fa539ec 100644
--- a/common/spl/spl_ymodem.c
+++ b/common/spl/spl_ymodem.c
@@ -89,7 +89,25 @@
if (res <= 0)
goto end_stream;
- if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
+ if (IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL) &&
+ image_get_magic((struct image_header *)buf) == FDT_MAGIC) {
+ addr = CONFIG_SYS_LOAD_ADDR;
+ ih = (struct image_header *)addr;
+
+ memcpy((void *)addr, buf, res);
+ size += res;
+ addr += res;
+
+ while ((res = xyzModem_stream_read(buf, BUF_SIZE, &err)) > 0) {
+ memcpy((void *)addr, buf, res);
+ size += res;
+ addr += res;
+ }
+
+ ret = spl_parse_image_header(spl_image, ih);
+ if (ret)
+ return ret;
+ } else if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
image_get_magic((struct image_header *)buf) == FDT_MAGIC) {
struct spl_load_info load;
struct ymodem_fit_info info;
diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig
index 6afda72..ffe013f 100644
--- a/configs/am335x_boneblack_vboot_defconfig
+++ b/configs/am335x_boneblack_vboot_defconfig
@@ -56,7 +56,6 @@
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_TI=y
-CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index a396a39..105ff01 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -64,7 +64,6 @@
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_TI=y
-CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
diff --git a/configs/am335x_hs_evm_defconfig b/configs/am335x_hs_evm_defconfig
index 1746df9..a37966b 100644
--- a/configs/am335x_hs_evm_defconfig
+++ b/configs/am335x_hs_evm_defconfig
@@ -60,7 +60,6 @@
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_TI=y
-CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
diff --git a/configs/am335x_hs_evm_uart_defconfig b/configs/am335x_hs_evm_uart_defconfig
index d2d6f2f..ff131eb 100644
--- a/configs/am335x_hs_evm_uart_defconfig
+++ b/configs/am335x_hs_evm_uart_defconfig
@@ -62,7 +62,6 @@
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_TI=y
-CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
diff --git a/configs/bcm963158_ram_defconfig b/configs/bcm963158_ram_defconfig
index 5659249..528b714 100644
--- a/configs/bcm963158_ram_defconfig
+++ b/configs/bcm963158_ram_defconfig
@@ -21,6 +21,8 @@
# CONFIG_CMD_UNZIP is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_CACHE=y
CONFIG_DOS_PARTITION=y
CONFIG_ISO_PARTITION=y
@@ -31,7 +33,14 @@
CONFIG_CLK=y
CONFIG_DM_GPIO=y
CONFIG_BCM6345_GPIO=y
+CONFIG_LED=y
+CONFIG_LED_BCM6858=y
+CONFIG_LED_BLINK=y
# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_NAND_BRCMNAND_63158=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_CONS_INDEX=0
diff --git a/configs/bcm968380gerg_ram_defconfig b/configs/bcm968380gerg_ram_defconfig
index fa9dc85..53423e5 100644
--- a/configs/bcm968380gerg_ram_defconfig
+++ b/configs/bcm968380gerg_ram_defconfig
@@ -26,6 +26,7 @@
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_NAND=y
# CONFIG_CMD_MISC is not set
CONFIG_DEFAULT_DEVICE_TREE="brcm,bcm968380gerg"
# CONFIG_NET is not set
@@ -36,6 +37,12 @@
CONFIG_LED=y
CONFIG_LED_BCM6328=y
CONFIG_LED_BLINK=y
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_NAND_BRCMNAND_6838=y
+CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHY=y
CONFIG_BCM6368_USBH_PHY=y
CONFIG_PINCTRL=y
diff --git a/configs/bcm968580xref_ram_defconfig b/configs/bcm968580xref_ram_defconfig
index 456ece7..62c33d1 100644
--- a/configs/bcm968580xref_ram_defconfig
+++ b/configs/bcm968580xref_ram_defconfig
@@ -16,6 +16,9 @@
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_GPIO=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PART=y
CONFIG_DOS_PARTITION=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
@@ -25,7 +28,14 @@
CONFIG_CLK=y
CONFIG_DM_GPIO=y
CONFIG_BCM6345_GPIO=y
+CONFIG_LED=y
+CONFIG_LED_BCM6858=y
+CONFIG_LED_BLINK=y
# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_NAND_BRCMNAND_6858=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_CONS_INDEX=0
diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig
index 6b0d024..63cb240 100644
--- a/configs/brppt1_mmc_defconfig
+++ b/configs/brppt1_mmc_defconfig
@@ -84,7 +84,6 @@
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_TI=y
-CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_FAT_WRITE=y
diff --git a/configs/brppt1_nand_defconfig b/configs/brppt1_nand_defconfig
index 4578f74..57cd54b 100644
--- a/configs/brppt1_nand_defconfig
+++ b/configs/brppt1_nand_defconfig
@@ -88,7 +88,6 @@
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_TI=y
-CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_FAT_WRITE=y
diff --git a/configs/brppt1_spi_defconfig b/configs/brppt1_spi_defconfig
index 739b078..31ba515 100644
--- a/configs/brppt1_spi_defconfig
+++ b/configs/brppt1_spi_defconfig
@@ -99,7 +99,6 @@
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_TI=y
-CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_FAT_WRITE=y
diff --git a/configs/chiliboard_defconfig b/configs/chiliboard_defconfig
index a6c36ed..944dd0d 100644
--- a/configs/chiliboard_defconfig
+++ b/configs/chiliboard_defconfig
@@ -50,6 +50,5 @@
CONFIG_DM_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_TI=y
-CONFIG_USB_MUSB_DSPS=y
CONFIG_FAT_WRITE=y
CONFIG_LZO=y
diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig
index a1af2f1..af159ec 100644
--- a/configs/corvus_defconfig
+++ b/configs/corvus_defconfig
@@ -18,6 +18,7 @@
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) root=/dev/mtdblock7 rw rootfstype=jffs2"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
@@ -34,10 +35,11 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_MTDPARTS=y
+CONFIG_DOS_PARTITION=y
CONFIG_OF_CONTROL=y
-CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g45-corvus"
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_BLK=y
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_DFU_NAND=y
@@ -47,8 +49,8 @@
CONFIG_PHYLIB=y
CONFIG_ATMEL_USART=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Siemens AG"
CONFIG_USB_GADGET_VENDOR_NUM=0x0908
diff --git a/configs/khadas-vim2_defconfig b/configs/khadas-vim2_defconfig
index 080dd19..d2d2967 100644
--- a/configs/khadas-vim2_defconfig
+++ b/configs/khadas-vim2_defconfig
@@ -11,7 +11,7 @@
CONFIG_CONSOLE_MUX=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
CONFIG_CMD_ADC=y
@@ -31,6 +31,7 @@
CONFIG_MTD=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
CONFIG_PHY=y
CONFIG_MESON_GXL_USB_PHY=y
CONFIG_PINCTRL=y
diff --git a/configs/khadas-vim_defconfig b/configs/khadas-vim_defconfig
index 6f1ad0e..aeec2be 100644
--- a/configs/khadas-vim_defconfig
+++ b/configs/khadas-vim_defconfig
@@ -11,7 +11,7 @@
CONFIG_CONSOLE_MUX=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
CONFIG_CMD_ADC=y
diff --git a/configs/libretech-ac_defconfig b/configs/libretech-ac_defconfig
new file mode 100644
index 0000000..2cdfcf4
--- /dev/null
+++ b/configs/libretech-ac_defconfig
@@ -0,0 +1,74 @@
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="libretech-ac"
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_MESON_GXL=y
+CONFIG_DEBUG_UART_BASE=0xc81004c0
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" libretech-ac"
+CONFIG_DEBUG_UART=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_ADC=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s805x-libretech-ac"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SARADC_MESON=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ADDR=8
+CONFIG_PHY_MESON_GXL=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY=y
+CONFIG_MESON_GXL_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_GXL=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_GX_VPU_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MESON_SPIFC=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_STORAGE=y
+CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/libretech-cc_defconfig b/configs/libretech-cc_defconfig
index d28c7ab..a1b9fd9 100644
--- a/configs/libretech-cc_defconfig
+++ b/configs/libretech-cc_defconfig
@@ -10,7 +10,7 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
CONFIG_CMD_ADC=y
diff --git a/configs/nanopi-k2_defconfig b/configs/nanopi-k2_defconfig
index 8bbf48f..3e79799 100644
--- a/configs/nanopi-k2_defconfig
+++ b/configs/nanopi-k2_defconfig
@@ -9,7 +9,7 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
CONFIG_CMD_GPIO=y
@@ -28,6 +28,7 @@
CONFIG_MMC_MESON_GX=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXBB=y
CONFIG_DM_REGULATOR=y
diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig
index 747da18..66e59e5 100644
--- a/configs/odroid-c2_defconfig
+++ b/configs/odroid-c2_defconfig
@@ -10,7 +10,7 @@
CONFIG_CONSOLE_MUX=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
CONFIG_CMD_GPIO=y
@@ -29,6 +29,7 @@
CONFIG_MMC_MESON_GX=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXBB=y
CONFIG_DM_REGULATOR=y
diff --git a/configs/p200_defconfig b/configs/p200_defconfig
new file mode 100644
index 0000000..12f3415
--- /dev/null
+++ b/configs/p200_defconfig
@@ -0,0 +1,41 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_DEBUG_UART_BASE=0xc81004c0
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" p200"
+CONFIG_DEBUG_UART=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-p200"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_GXBB=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_SYS_BOARD="p200"
diff --git a/configs/p201_defconfig b/configs/p201_defconfig
new file mode 100644
index 0000000..6e0b2ec
--- /dev/null
+++ b/configs/p201_defconfig
@@ -0,0 +1,41 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_DEBUG_UART_BASE=0xc81004c0
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" p201"
+CONFIG_DEBUG_UART=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-p201"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_GXBB=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_SYS_BOARD="p201"
diff --git a/configs/p212_defconfig b/configs/p212_defconfig
index b048863..0422740 100644
--- a/configs/p212_defconfig
+++ b/configs/p212_defconfig
@@ -11,7 +11,7 @@
CONFIG_CONSOLE_MUX=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
CONFIG_CMD_GPIO=y
diff --git a/configs/poplar_defconfig b/configs/poplar_defconfig
index 81bd370..76ab5eb 100644
--- a/configs/poplar_defconfig
+++ b/configs/poplar_defconfig
@@ -19,6 +19,9 @@
CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_K3=y
+CONFIG_DM_ETH=y
+CONFIG_HIGMACV300_ETH=y
+CONFIG_RESET_HISILICON=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
diff --git a/configs/s400_defconfig b/configs/s400_defconfig
index 1bd4b71..db8f80a 100644
--- a/configs/s400_defconfig
+++ b/configs/s400_defconfig
@@ -10,7 +10,7 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
CONFIG_CMD_GPIO=y
@@ -26,6 +26,7 @@
CONFIG_MMC_MESON_GX=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_AXG=y
CONFIG_DM_REGULATOR=y
diff --git a/configs/sama5d2_icp_mmc_defconfig b/configs/sama5d2_icp_mmc_defconfig
new file mode 100644
index 0000000..6d4d199
--- /dev/null
+++ b/configs/sama5d2_icp_mmc_defconfig
@@ -0,0 +1,76 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_SYS_TEXT_BASE=0x26f00000
+CONFIG_TARGET_SAMA5D2_ICP=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_BASE=0xf801c000
+CONFIG_DEBUG_UART_CLOCK=83000000
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_DEBUG_UART=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2"
+CONFIG_SD_BOOT=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_DISPLAY_PRINT=y
+# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_icp"
+CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_AT91_GENERIC_CLK=y
+CONFIG_DM_GPIO=y
+CONFIG_ATMEL_PIO4=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_AT91=y
+CONFIG_I2C_EEPROM=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ATMEL=y
+CONFIG_DM_ETH=y
+CONFIG_MACB=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ATMEL_USART=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
index 995290c..4848013 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -6,7 +6,7 @@
CONFIG_SPL=y
CONFIG_IDENT_STRING="socfpga_stratix10"
CONFIG_SPL_FS_FAT=y
-CONFIG_NR_DRAM_BANKS=1
+CONFIG_NR_DRAM_BANKS=2
CONFIG_BOOTDELAY=5
CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig
index 6781adb..fd164fa 100644
--- a/configs/stm32mp15_basic_defconfig
+++ b/configs/stm32mp15_basic_defconfig
@@ -69,9 +69,9 @@
CONFIG_STM32_SERIAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
-CONFIG_USB_DWC2=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics"
CONFIG_USB_GADGET_VENDOR_NUM=0x0483
diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig
index a050cee..f82b770 100644
--- a/configs/stm32mp15_trusted_defconfig
+++ b/configs/stm32mp15_trusted_defconfig
@@ -60,9 +60,9 @@
CONFIG_STM32_SERIAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
-CONFIG_USB_DWC2=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics"
CONFIG_USB_GADGET_VENDOR_NUM=0x0483
diff --git a/configs/u200_defconfig b/configs/u200_defconfig
new file mode 100644
index 0000000..c351913
--- /dev/null
+++ b/configs/u200_defconfig
@@ -0,0 +1,40 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_MESON_G12A=y
+CONFIG_DEBUG_UART_BASE=0xff803000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" u200"
+CONFIG_DEBUG_UART=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-g12a-u200"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ADDR=8
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_G12A=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/doc/device-tree-bindings/leds/leds-bcm6858.txt b/doc/device-tree-bindings/leds/leds-bcm6858.txt
new file mode 100644
index 0000000..ea2fe23
--- /dev/null
+++ b/doc/device-tree-bindings/leds/leds-bcm6858.txt
@@ -0,0 +1,51 @@
+LEDs connected to Broadcom BCM6858 controller
+
+This controller is present on BCM6858, BCM6328, BCM6362 and BCM63268.
+In these SoCs it's possible to control LEDs both as GPIOs or by hardware.
+
+Required properties:
+ - compatible : should be "brcm,bcm6858-leds".
+ - #address-cells : must be 1.
+ - #size-cells : must be 0.
+ - reg : BCM6858 LED controller address and size.
+
+Optional properties:
+ - brcm,serial-led-msb-first : Boolean, msb data come out first on serial data pin
+ Default : false
+ - brcm,serial-led-en-pol : Boolean, serial led polarity (true => active high)
+ Default : false
+ - brcm,serial-led-clk-pol : Boolean, serial clock polarity (true => active high)
+ Default : false
+ - brcm,serial-led-data-ppol : Boolean, serial data polarity (true => active high)
+ Default : false
+ - brcm,serial-shift-inv : Boolean, led test mode
+ Default : false
+
+Each LED is represented as a sub-node of the brcm,bcm6858-leds device.
+
+LED sub-node required properties:
+ - reg : LED pin number (only LEDs 0 to 32 are valid).
+
+LED sub-node optional properties:
+ - label : see Documentation/devicetree/bindings/leds/common.txt
+ - active-low : Boolean, makes LED active low.
+ Default : false
+
+Examples:
+BCM6328 with 2 GPIO LEDs
+ leds0: led-controller@ff800800 {
+ compatible = "brcm,bcm6858-leds";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0xff800800 0x0 0xe4>;
+
+ led@2 {
+ reg = <2>;
+ label = "green:inet";
+ };
+
+ led@5 {
+ reg = <5>;
+ label = "red:alarm";
+ };
+ };
diff --git a/doc/device-tree-bindings/phy/phy-stm32-usbphyc.txt b/doc/device-tree-bindings/phy/phy-stm32-usbphyc.txt
index 725ae71..da98407 100644
--- a/doc/device-tree-bindings/phy/phy-stm32-usbphyc.txt
+++ b/doc/device-tree-bindings/phy/phy-stm32-usbphyc.txt
@@ -23,6 +23,8 @@
- compatible: must be "st,stm32mp1-usbphyc"
- reg: address and length of the usb phy control register set
- clocks: phandle + clock specifier for the PLL phy clock
+- vdda1v1-supply: phandle to the regulator providing 1V1 power to the PHY
+- vdda1v8-supply: phandle to the regulator providing 1V8 power to the PHY
- #address-cells: number of address cells for phys sub-nodes, must be <1>
- #size-cells: number of size cells for phys sub-nodes, must be <0>
@@ -40,8 +42,6 @@
- reg: phy port index
- phy-supply: phandle to the regulator providing 3V3 power to the PHY,
see phy-bindings.txt in the same directory.
-- vdda1v1-supply: phandle to the regulator providing 1V1 power to the PHY
-- vdda1v8-supply: phandle to the regulator providing 1V8 power to the PHY
- #phy-cells: see phy-bindings.txt in the same directory, must be <0> for PHY
port#1 and must be <1> for PHY port#2, to select USB controller
diff --git a/doc/device-tree-bindings/usb/dwc2.txt b/doc/device-tree-bindings/usb/dwc2.txt
new file mode 100644
index 0000000..61493f7
--- /dev/null
+++ b/doc/device-tree-bindings/usb/dwc2.txt
@@ -0,0 +1,58 @@
+Platform DesignWare HS OTG USB 2.0 controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : One of:
+ - brcm,bcm2835-usb: The DWC2 USB controller instance in the BCM2835 SoC.
+ - hisilicon,hi6220-usb: The DWC2 USB controller instance in the hi6220 SoC.
+ - rockchip,rk3066-usb: The DWC2 USB controller instance in the rk3066 Soc;
+ - "rockchip,px30-usb", "rockchip,rk3066-usb", "snps,dwc2": for px30 Soc;
+ - "rockchip,rk3188-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3188 Soc;
+ - "rockchip,rk3288-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3288 Soc;
+ - "lantiq,arx100-usb": The DWC2 USB controller instance in Lantiq ARX SoCs;
+ - "lantiq,xrx200-usb": The DWC2 USB controller instance in Lantiq XRX SoCs;
+ - "amlogic,meson8-usb": The DWC2 USB controller instance in Amlogic Meson8 SoCs;
+ - "amlogic,meson8b-usb": The DWC2 USB controller instance in Amlogic Meson8b SoCs;
+ - "amlogic,meson-gxbb-usb": The DWC2 USB controller instance in Amlogic S905 SoCs;
+ - "amcc,dwc-otg": The DWC2 USB controller instance in AMCC Canyonlands 460EX SoCs;
+ - snps,dwc2: A generic DWC2 USB controller with default parameters.
+ - "st,stm32f4x9-fsotg": The DWC2 USB FS/HS controller instance in STM32F4x9 SoCs
+ configured in FS mode;
+ - "st,stm32f4x9-hsotg": The DWC2 USB HS controller instance in STM32F4x9 SoCs
+ configured in HS mode;
+ - "st,stm32f7-hsotg": The DWC2 USB HS controller instance in STM32F7 SoCs
+ configured in HS mode;
+- reg : Should contain 1 register range (address and length)
+- interrupts : Should contain 1 interrupt
+- clocks: clock provider specifier
+- clock-names: shall be "otg"
+Refer to clk/clock-bindings.txt for generic clock consumer properties
+
+Optional properties:
+- phys: phy provider specifier
+- phy-names: shall be "usb2-phy"
+Refer to phy/phy-bindings.txt for generic phy consumer properties
+- dr_mode: shall be one of "host", "peripheral" and "otg"
+ Refer to usb/generic.txt
+- g-rx-fifo-size: size of rx fifo size in gadget mode.
+- g-np-tx-fifo-size: size of non-periodic tx fifo size in gadget mode.
+- g-tx-fifo-size: size of periodic tx fifo per endpoint (except ep0) in gadget mode.
+- usb33d-supply: external VBUS and ID sensing comparators supply, in order to
+ perform OTG operation, used on STM32MP1 SoCs.
+- u-boot,force-b-session-valid: force B-peripheral session instead of relying on
+ VBUS sensing (only valid when dr_mode = "peripheral" and for u-boot).
+
+Deprecated properties:
+- g-use-dma: gadget DMA mode is automatically detected
+
+Example:
+
+ usb@101c0000 {
+ compatible = "ralink,rt3050-usb, snps,dwc2";
+ reg = <0x101c0000 40000>;
+ interrupts = <18>;
+ clocks = <&usb_otg_ahb_clk>;
+ clock-names = "otg";
+ phys = <&usbphy>;
+ phy-names = "usb2-phy";
+ };
diff --git a/doc/driver-model/fs_firmware_loader.txt b/doc/driver-model/fs_firmware_loader.txt
index b9aee84..8be6185 100644
--- a/doc/driver-model/fs_firmware_loader.txt
+++ b/doc/driver-model/fs_firmware_loader.txt
@@ -1,4 +1,4 @@
-# Copyright (C) 2018 Intel Corporation <www.intel.com>
+# Copyright (C) 2018-2019 Intel Corporation <www.intel.com>
#
# SPDX-License-Identifier: GPL-2.0
@@ -27,7 +27,7 @@
defined in fs-loader node as shown in below:
Example for block device:
- fs_loader0: fs-loader@0 {
+ fs_loader0: fs-loader {
u-boot,dm-pre-reloc;
compatible = "u-boot,fs-loader";
phandlepart = <&mmc 1>;
@@ -39,22 +39,55 @@
device, it can be described in FDT as shown in below:
Example for ubi:
- fs_loader1: fs-loader@1 {
+ fs_loader1: fs-loader {
u-boot,dm-pre-reloc;
compatible = "u-boot,fs-loader";
mtdpart = "UBI",
ubivol = "ubi0";
};
- Then, firmware_loader property would be set with the path of fs_loader
- node under /chosen node such as:
+ Then, firmware-loader property can be added with any device node, which
+ driver would use the firmware loader for loading.
+
+ The value of the firmware-loader property should be set with phandle
+ of the fs-loader node.
+ For example:
+ firmware-loader = <&fs_loader0>;
+
+ If there are majority of devices using the same fs-loader node, then
+ firmware-loader property can be added under /chosen node instead of
+ adding to each of device node.
+
+ For example:
/{
chosen {
- firmware_loader = &fs_loader0;
+ firmware-loader = <&fs_loader0>;
};
};
- However, this driver is also designed to support U-boot environment
+ In each respective driver of devices using firmware loader, the firmware
+ loaded instance should be created by DT phandle.
+
+ For example of getting DT phandle from /chosen and creating instance:
+ chosen_node = ofnode_path("/chosen");
+ if (!ofnode_valid(chosen_node)) {
+ debug("/chosen node was not found.\n");
+ return -ENOENT;
+ }
+
+ phandle_p = ofnode_get_property(chosen_node, "firmware-loader", &size);
+ if (!phandle_p) {
+ debug("firmware-loader property was not found.\n");
+ return -ENOENT;
+ }
+
+ phandle = fdt32_to_cpu(*phandle_p);
+ ret = uclass_get_device_by_phandle_id(UCLASS_FS_FIRMWARE_LOADER,
+ phandle, &dev);
+ if (ret)
+ return ret;
+
+ Firmware loader driver is also designed to support U-boot environment
variables, so all these data from FDT can be overwritten
through the U-boot environment variable during run time.
For examples:
@@ -104,9 +137,12 @@
Description:
The firmware is loaded directly into the buffer pointed to by buf
-Example of creating firmware loader instance and calling
-request_firmware_into_buf API:
- if (uclass_get_device(UCLASS_FS_FIRMWARE_LOADER, 0, &dev)) {
- request_firmware_into_buf(dev, filename, buffer_location,
- buffer_size, offset_ofreading);
- }
+Example of calling request_firmware_into_buf API after creating firmware loader
+instance:
+ ret = uclass_get_device_by_phandle_id(UCLASS_FS_FIRMWARE_LOADER,
+ phandle, &dev);
+ if (ret)
+ return ret;
+
+ request_firmware_into_buf(dev, filename, buffer_location, buffer_size,
+ offset_ofreading);
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index ff60fc5..96969b9 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -101,6 +101,7 @@
source "drivers/clk/at91/Kconfig"
source "drivers/clk/exynos/Kconfig"
source "drivers/clk/imx/Kconfig"
+source "drivers/clk/meson/Kconfig"
source "drivers/clk/mvebu/Kconfig"
source "drivers/clk/owl/Kconfig"
source "drivers/clk/renesas/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 1d9d725..719b9b8 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -12,7 +12,7 @@
obj-y += tegra/
obj-$(CONFIG_ARCH_ASPEED) += aspeed/
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
-obj-$(CONFIG_ARCH_MESON) += clk_meson.o clk_meson_axg.o
+obj-$(CONFIG_ARCH_MESON) += meson/
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_ARCH_SOCFPGA) += altera/
obj-$(CONFIG_CLK_AT91) += at91/
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 0632dc8..a47a5bd 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -5,3 +5,4 @@
# SoC Drivers
obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o
obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
+obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-mt8516.c
new file mode 100644
index 0000000..071bf69
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8516.c
@@ -0,0 +1,802 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek clock driver for MT8516 SoC
+ *
+ * Copyright (C) 2018 BayLibre, SAS
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <dt-bindings/clock/mt8516-clk.h>
+
+#include "clk-mtk.h"
+
+#define MT8516_PLL_FMAX (1502UL * MHZ)
+#define MT8516_CON0_RST_BAR BIT(27)
+
+/* apmixedsys */
+#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
+ _pd_shift, _pcw_reg, _pcw_shift) { \
+ .id = _id, \
+ .reg = _reg, \
+ .pwr_reg = _pwr_reg, \
+ .en_mask = _en_mask, \
+ .rst_bar_mask = MT8516_CON0_RST_BAR, \
+ .fmax = MT8516_PLL_FMAX, \
+ .flags = _flags, \
+ .pcwbits = _pcwbits, \
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .pcw_reg = _pcw_reg, \
+ .pcw_shift = _pcw_shift, \
+ }
+
+static const struct mtk_pll_data apmixed_plls[] = {
+ PLL(CLK_APMIXED_ARMPLL, 0x0100, 0x0110, 0x00000001, 0,
+ 21, 0x0104, 24, 0x0104, 0),
+ PLL(CLK_APMIXED_MAINPLL, 0x0120, 0x0130, 0x00000001,
+ HAVE_RST_BAR, 21, 0x0124, 24, 0x0124, 0),
+ PLL(CLK_APMIXED_UNIVPLL, 0x0140, 0x0150, 0x30000001,
+ HAVE_RST_BAR, 7, 0x0144, 24, 0x0144, 0),
+ PLL(CLK_APMIXED_MMPLL, 0x0160, 0x0170, 0x00000001, 0,
+ 21, 0x0164, 24, 0x0164, 0),
+ PLL(CLK_APMIXED_APLL1, 0x0180, 0x0190, 0x00000001, 0,
+ 31, 0x0180, 1, 0x0184, 0),
+ PLL(CLK_APMIXED_APLL2, 0x01A0, 0x01B0, 0x00000001, 0,
+ 31, 0x01A0, 1, 0x01A4, 0),
+};
+
+/* topckgen */
+#define FACTOR0(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
+
+#define FACTOR1(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
+
+#define FACTOR2(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, 0)
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+ FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 26000000),
+ FIXED_CLK(CLK_TOP_I2S_INFRA_BCK, CLK_TOP_CLK_NULL, 26000000),
+ FIXED_CLK(CLK_TOP_MEMPLL, CLK_TOP_CLK26M, 800000000),
+};
+
+static const struct mtk_fixed_factor top_fixed_divs[] = {
+ FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1),
+ FACTOR0(CLK_TOP_MAINPLL_D2, CLK_APMIXED_MAINPLL, 1, 2),
+ FACTOR0(CLK_TOP_MAINPLL_D4, CLK_APMIXED_MAINPLL, 1, 4),
+ FACTOR0(CLK_TOP_MAINPLL_D8, CLK_APMIXED_MAINPLL, 1, 8),
+ FACTOR0(CLK_TOP_MAINPLL_D16, CLK_APMIXED_MAINPLL, 1, 16),
+ FACTOR0(CLK_TOP_MAINPLL_D11, CLK_APMIXED_MAINPLL, 1, 11),
+ FACTOR0(CLK_TOP_MAINPLL_D22, CLK_APMIXED_MAINPLL, 1, 22),
+ FACTOR0(CLK_TOP_MAINPLL_D3, CLK_APMIXED_MAINPLL, 1, 3),
+ FACTOR0(CLK_TOP_MAINPLL_D6, CLK_APMIXED_MAINPLL, 1, 6),
+ FACTOR0(CLK_TOP_MAINPLL_D12, CLK_APMIXED_MAINPLL, 1, 12),
+ FACTOR0(CLK_TOP_MAINPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
+ FACTOR0(CLK_TOP_MAINPLL_D10, CLK_APMIXED_MAINPLL, 1, 10),
+ FACTOR0(CLK_TOP_MAINPLL_D20, CLK_APMIXED_MAINPLL, 1, 20),
+ FACTOR0(CLK_TOP_MAINPLL_D40, CLK_APMIXED_MAINPLL, 1, 40),
+ FACTOR0(CLK_TOP_MAINPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
+ FACTOR0(CLK_TOP_MAINPLL_D14, CLK_APMIXED_MAINPLL, 1, 14),
+ FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2),
+ FACTOR0(CLK_TOP_UNIVPLL_D4, CLK_APMIXED_UNIVPLL, 1, 4),
+ FACTOR0(CLK_TOP_UNIVPLL_D8, CLK_APMIXED_UNIVPLL, 1, 8),
+ FACTOR0(CLK_TOP_UNIVPLL_D16, CLK_APMIXED_UNIVPLL, 1, 16),
+ FACTOR0(CLK_TOP_UNIVPLL_D3, CLK_APMIXED_UNIVPLL, 1, 3),
+ FACTOR0(CLK_TOP_UNIVPLL_D6, CLK_APMIXED_UNIVPLL, 1, 6),
+ FACTOR0(CLK_TOP_UNIVPLL_D12, CLK_APMIXED_UNIVPLL, 1, 12),
+ FACTOR0(CLK_TOP_UNIVPLL_D24, CLK_APMIXED_UNIVPLL, 1, 24),
+ FACTOR0(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL, 1, 5),
+ FACTOR0(CLK_TOP_UNIVPLL_D20, CLK_APMIXED_UNIVPLL, 1, 20),
+ FACTOR0(CLK_TOP_MMPLL380M, CLK_APMIXED_MMPLL, 1, 1),
+ FACTOR0(CLK_TOP_MMPLL_D2, CLK_APMIXED_MMPLL, 1, 2),
+ FACTOR0(CLK_TOP_MMPLL_200M, CLK_APMIXED_MMPLL, 1, 3),
+ FACTOR0(CLK_TOP_USB_PHY48M, CLK_APMIXED_UNIVPLL, 1, 26),
+ FACTOR0(CLK_TOP_APLL1, CLK_APMIXED_APLL1, 1, 1),
+ FACTOR1(CLK_TOP_APLL1_D2, CLK_TOP_APLL1, 1, 2),
+ FACTOR1(CLK_TOP_APLL1_D4, CLK_TOP_RG_APLL1_D2_EN, 1, 2),
+ FACTOR1(CLK_TOP_APLL1_D8, CLK_TOP_RG_APLL1_D4_EN, 1, 2),
+ FACTOR0(CLK_TOP_APLL2, CLK_APMIXED_APLL2, 1, 1),
+ FACTOR1(CLK_TOP_APLL2_D2, CLK_TOP_APLL2, 1, 2),
+ FACTOR1(CLK_TOP_APLL2_D4, CLK_TOP_RG_APLL2_D2_EN, 1, 2),
+ FACTOR1(CLK_TOP_APLL2_D8, CLK_TOP_RG_APLL2_D4_EN, 1, 2),
+ FACTOR2(CLK_TOP_CLK26M, CLK_XTAL, 1, 1),
+ FACTOR2(CLK_TOP_CLK26M_D2, CLK_XTAL, 1, 2),
+ FACTOR1(CLK_TOP_AHB_INFRA_D2, CLK_TOP_AHB_INFRA_SEL, 1, 2),
+ FACTOR1(CLK_TOP_NFI1X, CLK_TOP_NFI2X_PAD_SEL, 1, 2),
+ FACTOR1(CLK_TOP_ETH_D2, CLK_TOP_ETH_SEL, 1, 2),
+};
+
+static const int uart0_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D24,
+};
+
+static const int gfmux_emi1x_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_DMPLL,
+};
+
+static const int emi_ddrphy_parents[] = {
+ CLK_TOP_GFMUX_EMI1X_SEL,
+ CLK_TOP_GFMUX_EMI1X_SEL,
+};
+
+static const int ahb_infra_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D11,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D12,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D10,
+};
+
+static const int csw_mux_mfg_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_UNIVPLL_D3,
+ CLK_TOP_UNIVPLL_D2,
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D4,
+ CLK_TOP_UNIVPLL_D24,
+ CLK_TOP_MMPLL380M,
+};
+
+static const int msdc0_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D6,
+ CLK_TOP_MAINPLL_D8,
+ CLK_TOP_UNIVPLL_D8,
+ CLK_TOP_MAINPLL_D16,
+ CLK_TOP_MMPLL_200M,
+ CLK_TOP_MAINPLL_D12,
+ CLK_TOP_MMPLL_D2,
+};
+
+static const int pwm_mm_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D12,
+};
+
+static const int uart1_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D24,
+};
+
+static const int msdc1_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D6,
+ CLK_TOP_MAINPLL_D8,
+ CLK_TOP_UNIVPLL_D8,
+ CLK_TOP_MAINPLL_D16,
+ CLK_TOP_MMPLL_200M,
+ CLK_TOP_MAINPLL_D12,
+ CLK_TOP_MMPLL_D2,
+};
+
+static const int spm_52m_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D24,
+};
+
+static const int pmicspi_parents[] = {
+ CLK_TOP_UNIVPLL_D20,
+ CLK_TOP_USB_PHY48M,
+ CLK_TOP_UNIVPLL_D16,
+ CLK_TOP_CLK26M,
+};
+
+static const int qaxi_aud26m_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_AHB_INFRA_SEL,
+};
+
+static const int aud_intbus_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D22,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D11,
+};
+
+static const int nfi2x_pad_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D12,
+ CLK_TOP_MAINPLL_D8,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D6,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D4,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D10,
+ CLK_TOP_MAINPLL_D7,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D5
+};
+
+static const int nfi1x_pad_parents[] = {
+ CLK_TOP_AHB_INFRA_SEL,
+ CLK_TOP_NFI1X,
+};
+
+static const int mfg_mm_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CSW_MUX_MFG_SEL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D3,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D5,
+ CLK_TOP_MAINPLL_D7,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D14
+};
+
+static const int ddrphycfg_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D16
+};
+
+static const int usb_78m_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D16,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D20,
+};
+
+static const int spinor_parents[] = {
+ CLK_TOP_CLK26M_D2,
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D40,
+ CLK_TOP_UNIVPLL_D24,
+ CLK_TOP_UNIVPLL_D20,
+ CLK_TOP_MAINPLL_D20,
+ CLK_TOP_MAINPLL_D16,
+ CLK_TOP_UNIVPLL_D12
+};
+
+static const int msdc2_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D6,
+ CLK_TOP_MAINPLL_D8,
+ CLK_TOP_UNIVPLL_D8,
+ CLK_TOP_MAINPLL_D16,
+ CLK_TOP_MMPLL_200M,
+ CLK_TOP_MAINPLL_D12,
+ CLK_TOP_MMPLL_D2
+};
+
+static const int eth_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D40,
+ CLK_TOP_UNIVPLL_D24,
+ CLK_TOP_UNIVPLL_D20,
+ CLK_TOP_MAINPLL_D20
+};
+
+static const int axi_mfg_in_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D11,
+ CLK_TOP_UNIVPLL_D24,
+ CLK_TOP_MMPLL380M,
+};
+
+static const int slow_mfg_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D12,
+ CLK_TOP_UNIVPLL_D24
+};
+
+static const int aud1_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_APLL1
+};
+
+static const int aud2_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_APLL2
+};
+
+static const int aud_engen1_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_RG_APLL1_D2_EN,
+ CLK_TOP_RG_APLL1_D4_EN,
+ CLK_TOP_RG_APLL1_D8_EN
+};
+
+static const int aud_engen2_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_RG_APLL2_D2_EN,
+ CLK_TOP_RG_APLL2_D4_EN,
+ CLK_TOP_RG_APLL2_D8_EN
+};
+
+static const int i2c_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D20,
+ CLK_TOP_UNIVPLL_D16,
+ CLK_TOP_UNIVPLL_D12
+};
+
+static const int aud_i2s0_m_parents[] = {
+ CLK_TOP_RG_AUD1,
+ CLK_TOP_RG_AUD2
+};
+
+static const int pwm_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D12
+};
+
+static const int spi_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D12,
+ CLK_TOP_UNIVPLL_D8,
+ CLK_TOP_UNIVPLL_D6
+};
+
+static const int aud_spdifin_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D2
+};
+
+static const int uart2_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D24
+};
+
+static const int bsi_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D10,
+ CLK_TOP_MAINPLL_D12,
+ CLK_TOP_MAINPLL_D20
+};
+
+static const int dbg_atclk_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D5,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_UNIVPLL_D5
+};
+
+static const int csw_nfiecc_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D7,
+ CLK_TOP_MAINPLL_D6,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D5
+};
+
+static const int nfiecc_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_NFI2X_PAD_SEL,
+ CLK_TOP_MAINPLL_D4,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CSW_NFIECC_SEL,
+};
+
+static const struct mtk_composite top_muxes[] = {
+ /* CLK_MUX_SEL0 */
+ MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
+ MUX(CLK_TOP_GFMUX_EMI1X_SEL, gfmux_emi1x_parents, 0x000, 1, 1),
+ MUX(CLK_TOP_EMI_DDRPHY_SEL, emi_ddrphy_parents, 0x000, 2, 1),
+ MUX(CLK_TOP_AHB_INFRA_SEL, ahb_infra_parents, 0x000, 4, 4),
+ MUX(CLK_TOP_CSW_MUX_MFG_SEL, csw_mux_mfg_parents, 0x000, 8, 3),
+ MUX(CLK_TOP_MSDC0_SEL, msdc0_parents, 0x000, 11, 3),
+ MUX(CLK_TOP_PWM_MM_SEL, pwm_mm_parents, 0x000, 18, 1),
+ MUX(CLK_TOP_UART1_SEL, uart1_parents, 0x000, 19, 1),
+ MUX(CLK_TOP_MSDC1_SEL, msdc1_parents, 0x000, 20, 3),
+ MUX(CLK_TOP_SPM_52M_SEL, spm_52m_parents, 0x000, 23, 1),
+ MUX(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x000, 24, 2),
+ MUX(CLK_TOP_QAXI_AUD26M_SEL, qaxi_aud26m_parents, 0x000, 26, 1),
+ MUX(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x000, 27, 3),
+ /* CLK_MUX_SEL1 */
+ MUX(CLK_TOP_NFI2X_PAD_SEL, nfi2x_pad_parents, 0x004, 0, 7),
+ MUX(CLK_TOP_NFI1X_PAD_SEL, nfi1x_pad_parents, 0x004, 7, 1),
+ MUX(CLK_TOP_MFG_MM_SEL, mfg_mm_parents, 0x004, 8, 6),
+ MUX(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x004, 15, 1),
+ MUX(CLK_TOP_USB_78M_SEL, usb_78m_parents, 0x004, 20, 3),
+ /* CLK_MUX_SEL8 */
+ MUX(CLK_TOP_SPINOR_SEL, spinor_parents, 0x040, 0, 3),
+ MUX(CLK_TOP_MSDC2_SEL, msdc2_parents, 0x040, 3, 3),
+ MUX(CLK_TOP_ETH_SEL, eth_parents, 0x040, 6, 3),
+ MUX(CLK_TOP_AXI_MFG_IN_SEL, axi_mfg_in_parents, 0x040, 18, 2),
+ MUX(CLK_TOP_SLOW_MFG_SEL, slow_mfg_parents, 0x040, 20, 2),
+ MUX(CLK_TOP_AUD1_SEL, aud1_parents, 0x040, 22, 1),
+ MUX(CLK_TOP_AUD2_SEL, aud2_parents, 0x040, 23, 1),
+ MUX(CLK_TOP_AUD_ENGEN1_SEL, aud_engen1_parents, 0x040, 24, 2),
+ MUX(CLK_TOP_AUD_ENGEN2_SEL, aud_engen2_parents, 0x040, 26, 2),
+ MUX(CLK_TOP_I2C_SEL, i2c_parents, 0x040, 28, 2),
+ /* CLK_MUX_SEL9 */
+ MUX(CLK_TOP_AUD_I2S0_M_SEL, aud_i2s0_m_parents, 0x044, 12, 1),
+ MUX(CLK_TOP_AUD_I2S1_M_SEL, aud_i2s0_m_parents, 0x044, 13, 1),
+ MUX(CLK_TOP_AUD_I2S2_M_SEL, aud_i2s0_m_parents, 0x044, 14, 1),
+ MUX(CLK_TOP_AUD_I2S3_M_SEL, aud_i2s0_m_parents, 0x044, 15, 1),
+ MUX(CLK_TOP_AUD_I2S4_M_SEL, aud_i2s0_m_parents, 0x044, 16, 1),
+ MUX(CLK_TOP_AUD_I2S5_M_SEL, aud_i2s0_m_parents, 0x044, 17, 1),
+ MUX(CLK_TOP_AUD_SPDIF_B_SEL, aud_i2s0_m_parents, 0x044, 18, 1),
+ /* CLK_MUX_SEL13 */
+ MUX(CLK_TOP_PWM_SEL, pwm_parents, 0x07c, 0, 1),
+ MUX(CLK_TOP_SPI_SEL, spi_parents, 0x07c, 1, 2),
+ MUX(CLK_TOP_AUD_SPDIFIN_SEL, aud_spdifin_parents, 0x07c, 3, 1),
+ MUX(CLK_TOP_UART2_SEL, uart2_parents, 0x07c, 4, 1),
+ MUX(CLK_TOP_BSI_SEL, bsi_parents, 0x07c, 5, 2),
+ MUX(CLK_TOP_DBG_ATCLK_SEL, dbg_atclk_parents, 0x07c, 7, 3),
+ MUX(CLK_TOP_CSW_NFIECC_SEL, csw_nfiecc_parents, 0x07c, 10, 3),
+ MUX(CLK_TOP_NFIECC_SEL, nfiecc_parents, 0x07c, 13, 3),
+};
+
+static const struct mtk_gate_regs top0_cg_regs = {
+ .set_ofs = 0x50,
+ .clr_ofs = 0x80,
+ .sta_ofs = 0x20,
+};
+
+static const struct mtk_gate_regs top1_cg_regs = {
+ .set_ofs = 0x54,
+ .clr_ofs = 0x84,
+ .sta_ofs = 0x24,
+};
+
+static const struct mtk_gate_regs top2_cg_regs = {
+ .set_ofs = 0x6c,
+ .clr_ofs = 0x9c,
+ .sta_ofs = 0x3c,
+};
+
+static const struct mtk_gate_regs top3_cg_regs = {
+ .set_ofs = 0xa0,
+ .clr_ofs = 0xb0,
+ .sta_ofs = 0x70,
+};
+
+static const struct mtk_gate_regs top4_cg_regs = {
+ .set_ofs = 0xa4,
+ .clr_ofs = 0xb4,
+ .sta_ofs = 0x74,
+};
+
+static const struct mtk_gate_regs top5_cg_regs = {
+ .set_ofs = 0x44,
+ .clr_ofs = 0x44,
+ .sta_ofs = 0x44,
+};
+
+#define GATE_TOP0(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top0_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP1(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top1_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP2(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top2_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP2_I(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top2_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP3(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top3_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP4_I(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top4_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP5(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top5_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_NO_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+static const struct mtk_gate top_clks[] = {
+ /* TOP0 */
+ GATE_TOP0(CLK_TOP_PWM_MM, CLK_TOP_PWM_MM_SEL, 0),
+ GATE_TOP0(CLK_TOP_MFG_MM, CLK_TOP_MFG_MM_SEL, 2),
+ GATE_TOP0(CLK_TOP_SPM_52M, CLK_TOP_SPM_52M_SEL, 3),
+ /* TOP1 */
+ GATE_TOP1(CLK_TOP_THEM, CLK_TOP_AHB_INFRA_SEL, 1),
+ GATE_TOP1(CLK_TOP_APDMA, CLK_TOP_AHB_INFRA_SEL, 2),
+ GATE_TOP1(CLK_TOP_I2C0, CLK_IFR_I2C0_SEL, 3),
+ GATE_TOP1(CLK_TOP_I2C1, CLK_IFR_I2C1_SEL, 4),
+ GATE_TOP1(CLK_TOP_AUXADC1, CLK_TOP_AHB_INFRA_SEL, 5),
+ GATE_TOP1(CLK_TOP_NFI, CLK_TOP_NFI1X_PAD_SEL, 6),
+ GATE_TOP1(CLK_TOP_NFIECC, CLK_TOP_RG_NFIECC, 7),
+ GATE_TOP1(CLK_TOP_DEBUGSYS, CLK_TOP_RG_DBG_ATCLK, 8),
+ GATE_TOP1(CLK_TOP_PWM, CLK_TOP_AHB_INFRA_SEL, 9),
+ GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
+ GATE_TOP1(CLK_TOP_UART1, CLK_TOP_UART1_SEL, 11),
+ GATE_TOP1(CLK_TOP_BTIF, CLK_TOP_AHB_INFRA_SEL, 12),
+ GATE_TOP1(CLK_TOP_USB, CLK_TOP_USB_78M, 13),
+ GATE_TOP1(CLK_TOP_FLASHIF_26M, CLK_TOP_CLK26M, 14),
+ GATE_TOP1(CLK_TOP_AUXADC2, CLK_TOP_AHB_INFRA_SEL, 15),
+ GATE_TOP1(CLK_TOP_I2C2, CLK_IFR_I2C2_SEL, 16),
+ GATE_TOP1(CLK_TOP_MSDC0, CLK_TOP_MSDC0_SEL, 17),
+ GATE_TOP1(CLK_TOP_MSDC1, CLK_TOP_MSDC1_SEL, 18),
+ GATE_TOP1(CLK_TOP_NFI2X, CLK_TOP_NFI2X_PAD_SEL, 19),
+ GATE_TOP1(CLK_TOP_PMICWRAP_AP, CLK_TOP_CLK26M, 20),
+ GATE_TOP1(CLK_TOP_SEJ, CLK_TOP_AHB_INFRA_SEL, 21),
+ GATE_TOP1(CLK_TOP_MEMSLP_DLYER, CLK_TOP_CLK26M, 22),
+ GATE_TOP1(CLK_TOP_SPI, CLK_TOP_SPI_SEL, 23),
+ GATE_TOP1(CLK_TOP_APXGPT, CLK_TOP_CLK26M, 24),
+ GATE_TOP1(CLK_TOP_AUDIO, CLK_TOP_CLK26M, 25),
+ GATE_TOP1(CLK_TOP_PMICWRAP_MD, CLK_TOP_CLK26M, 27),
+ GATE_TOP1(CLK_TOP_PMICWRAP_CONN, CLK_TOP_CLK26M, 28),
+ GATE_TOP1(CLK_TOP_PMICWRAP_26M, CLK_TOP_CLK26M, 29),
+ GATE_TOP1(CLK_TOP_AUX_ADC, CLK_TOP_CLK26M, 30),
+ GATE_TOP1(CLK_TOP_AUX_TP, CLK_TOP_CLK26M, 31),
+ /* TOP2 */
+ GATE_TOP2(CLK_TOP_MSDC2, CLK_TOP_AHB_INFRA_SEL, 0),
+ GATE_TOP2(CLK_TOP_RBIST, CLK_TOP_UNIVPLL_D12, 1),
+ GATE_TOP2(CLK_TOP_NFI_BUS, CLK_TOP_AHB_INFRA_SEL, 2),
+ GATE_TOP2(CLK_TOP_GCE, CLK_TOP_AHB_INFRA_SEL, 4),
+ GATE_TOP2(CLK_TOP_TRNG, CLK_TOP_AHB_INFRA_SEL, 5),
+ GATE_TOP2(CLK_TOP_SEJ_13M, CLK_TOP_CLK26M, 6),
+ GATE_TOP2(CLK_TOP_AES, CLK_TOP_AHB_INFRA_SEL, 7),
+ GATE_TOP2(CLK_TOP_PWM_B, CLK_TOP_RG_PWM_INFRA, 8),
+ GATE_TOP2(CLK_TOP_PWM1_FB, CLK_TOP_RG_PWM_INFRA, 9),
+ GATE_TOP2(CLK_TOP_PWM2_FB, CLK_TOP_RG_PWM_INFRA, 10),
+ GATE_TOP2(CLK_TOP_PWM3_FB, CLK_TOP_RG_PWM_INFRA, 11),
+ GATE_TOP2(CLK_TOP_PWM4_FB, CLK_TOP_RG_PWM_INFRA, 12),
+ GATE_TOP2(CLK_TOP_PWM5_FB, CLK_TOP_RG_PWM_INFRA, 13),
+ GATE_TOP2(CLK_TOP_USB_1P, CLK_TOP_USB_78M, 14),
+ GATE_TOP2(CLK_TOP_FLASHIF_FREERUN, CLK_TOP_AHB_INFRA_SEL, 15),
+ GATE_TOP2(CLK_TOP_66M_ETH, CLK_TOP_AHB_INFRA_D2, 19),
+ GATE_TOP2(CLK_TOP_133M_ETH, CLK_TOP_AHB_INFRA_SEL, 20),
+ GATE_TOP2(CLK_TOP_FETH_25M, CLK_IFR_ETH_25M_SEL, 21),
+ GATE_TOP2(CLK_TOP_FETH_50M, CLK_TOP_RG_ETH, 22),
+ GATE_TOP2(CLK_TOP_FLASHIF_AXI, CLK_TOP_AHB_INFRA_SEL, 23),
+ GATE_TOP2(CLK_TOP_USBIF, CLK_TOP_AHB_INFRA_SEL, 24),
+ GATE_TOP2(CLK_TOP_UART2, CLK_TOP_RG_UART2, 25),
+ GATE_TOP2(CLK_TOP_BSI, CLK_TOP_AHB_INFRA_SEL, 26),
+ GATE_TOP2_I(CLK_TOP_MSDC0_INFRA, CLK_TOP_MSDC0, 28),
+ GATE_TOP2_I(CLK_TOP_MSDC1_INFRA, CLK_TOP_MSDC1, 29),
+ GATE_TOP2_I(CLK_TOP_MSDC2_INFRA, CLK_TOP_RG_MSDC2, 30),
+ GATE_TOP2(CLK_TOP_USB_78M, CLK_TOP_USB_78M_SEL, 31),
+ /* TOP3 */
+ GATE_TOP3(CLK_TOP_RG_SPINOR, CLK_TOP_SPINOR_SEL, 0),
+ GATE_TOP3(CLK_TOP_RG_MSDC2, CLK_TOP_MSDC2_SEL, 1),
+ GATE_TOP3(CLK_TOP_RG_ETH, CLK_TOP_ETH_SEL, 2),
+ GATE_TOP3(CLK_TOP_RG_AXI_MFG, CLK_TOP_AXI_MFG_IN_SEL, 6),
+ GATE_TOP3(CLK_TOP_RG_SLOW_MFG, CLK_TOP_SLOW_MFG_SEL, 7),
+ GATE_TOP3(CLK_TOP_RG_AUD1, CLK_TOP_AUD1_SEL, 8),
+ GATE_TOP3(CLK_TOP_RG_AUD2, CLK_TOP_AUD2_SEL, 9),
+ GATE_TOP3(CLK_TOP_RG_AUD_ENGEN1, CLK_TOP_AUD_ENGEN1_SEL, 10),
+ GATE_TOP3(CLK_TOP_RG_AUD_ENGEN2, CLK_TOP_AUD_ENGEN2_SEL, 11),
+ GATE_TOP3(CLK_TOP_RG_I2C, CLK_TOP_I2C_SEL, 12),
+ GATE_TOP3(CLK_TOP_RG_PWM_INFRA, CLK_TOP_PWM_SEL, 13),
+ GATE_TOP3(CLK_TOP_RG_AUD_SPDIF_IN, CLK_TOP_AUD_SPDIFIN_SEL, 14),
+ GATE_TOP3(CLK_TOP_RG_UART2, CLK_TOP_UART2_SEL, 15),
+ GATE_TOP3(CLK_TOP_RG_BSI, CLK_TOP_BSI_SEL, 16),
+ GATE_TOP3(CLK_TOP_RG_DBG_ATCLK, CLK_TOP_DBG_ATCLK_SEL, 17),
+ GATE_TOP3(CLK_TOP_RG_NFIECC, CLK_TOP_NFIECC_SEL, 18),
+ /* TOP4 */
+ GATE_TOP4_I(CLK_TOP_RG_APLL1_D2_EN, CLK_TOP_APLL1_D2, 8),
+ GATE_TOP4_I(CLK_TOP_RG_APLL1_D4_EN, CLK_TOP_APLL1_D4, 9),
+ GATE_TOP4_I(CLK_TOP_RG_APLL1_D8_EN, CLK_TOP_APLL1_D8, 10),
+ GATE_TOP4_I(CLK_TOP_RG_APLL2_D2_EN, CLK_TOP_APLL2_D2, 11),
+ GATE_TOP4_I(CLK_TOP_RG_APLL2_D4_EN, CLK_TOP_APLL2_D4, 12),
+ GATE_TOP4_I(CLK_TOP_RG_APLL2_D8_EN, CLK_TOP_APLL2_D8, 13),
+ /* TOP5 */
+ GATE_TOP5(CLK_TOP_APLL12_DIV0, CLK_TOP_APLL12_CK_DIV0, 0),
+ GATE_TOP5(CLK_TOP_APLL12_DIV1, CLK_TOP_APLL12_CK_DIV1, 1),
+ GATE_TOP5(CLK_TOP_APLL12_DIV2, CLK_TOP_APLL12_CK_DIV2, 2),
+ GATE_TOP5(CLK_TOP_APLL12_DIV3, CLK_TOP_APLL12_CK_DIV3, 3),
+ GATE_TOP5(CLK_TOP_APLL12_DIV4, CLK_TOP_APLL12_CK_DIV4, 4),
+ GATE_TOP5(CLK_TOP_APLL12_DIV4B, CLK_TOP_APLL12_CK_DIV4B, 5),
+ GATE_TOP5(CLK_TOP_APLL12_DIV5, CLK_TOP_APLL12_CK_DIV5, 6),
+ GATE_TOP5(CLK_TOP_APLL12_DIV5B, CLK_TOP_APLL12_CK_DIV5B, 7),
+ GATE_TOP5(CLK_TOP_APLL12_DIV6, CLK_TOP_APLL12_CK_DIV6, 8),
+};
+
+static const struct mtk_clk_tree mt8516_clk_tree = {
+ .xtal_rate = 26 * MHZ,
+ .xtal2_rate = 26 * MHZ,
+ .fdivs_offs = CLK_TOP_DMPLL,
+ .muxes_offs = CLK_TOP_UART0_SEL,
+ .plls = apmixed_plls,
+ .fclks = top_fixed_clks,
+ .fdivs = top_fixed_divs,
+ .muxes = top_muxes,
+};
+
+static int mt8516_apmixedsys_probe(struct udevice *dev)
+{
+ return mtk_common_clk_init(dev, &mt8516_clk_tree);
+}
+
+static int mt8516_topckgen_probe(struct udevice *dev)
+{
+ return mtk_common_clk_init(dev, &mt8516_clk_tree);
+}
+
+static int mt8516_topckgen_cg_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt8516_clk_tree, top_clks);
+}
+
+static const struct udevice_id mt8516_apmixed_compat[] = {
+ { .compatible = "mediatek,mt8516-apmixedsys", },
+ { }
+};
+
+static const struct udevice_id mt8516_topckgen_compat[] = {
+ { .compatible = "mediatek,mt8516-topckgen", },
+ { }
+};
+
+static const struct udevice_id mt8516_topckgen_cg_compat[] = {
+ { .compatible = "mediatek,mt8516-topckgen-cg", },
+ { }
+};
+
+U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+ .name = "mt8516-apmixedsys",
+ .id = UCLASS_CLK,
+ .of_match = mt8516_apmixed_compat,
+ .probe = mt8516_apmixedsys_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .ops = &mtk_clk_apmixedsys_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_topckgen) = {
+ .name = "mt8516-topckgen",
+ .id = UCLASS_CLK,
+ .of_match = mt8516_topckgen_compat,
+ .probe = mt8516_topckgen_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .ops = &mtk_clk_topckgen_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_topckgen_cg) = {
+ .name = "mt8516-topckgen-cg",
+ .id = UCLASS_CLK,
+ .of_match = mt8516_topckgen_cg_compat,
+ .probe = mt8516_topckgen_cg_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .ops = &mtk_clk_gate_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index 870b14e..6c6b500 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -390,6 +390,12 @@
case CLK_GATE_SETCLR:
writel(bit, priv->base + gate->regs->clr_ofs);
break;
+ case CLK_GATE_SETCLR_INV:
+ writel(bit, priv->base + gate->regs->set_ofs);
+ break;
+ case CLK_GATE_NO_SETCLR:
+ clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, 0);
+ break;
case CLK_GATE_NO_SETCLR_INV:
clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, bit);
break;
@@ -411,6 +417,12 @@
case CLK_GATE_SETCLR:
writel(bit, priv->base + gate->regs->set_ofs);
break;
+ case CLK_GATE_SETCLR_INV:
+ writel(bit, priv->base + gate->regs->clr_ofs);
+ break;
+ case CLK_GATE_NO_SETCLR:
+ clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, bit);
+ break;
case CLK_GATE_NO_SETCLR_INV:
clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, 0);
break;
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
new file mode 100644
index 0000000..994b44a
--- /dev/null
+++ b/drivers/clk/meson/Kconfig
@@ -0,0 +1,23 @@
+config CLK_MESON_GX
+ bool "Enable clock support for Amlogic GX"
+ depends on CLK && ARCH_MESON
+ default MESON_GX
+ help
+ Enable clock support for the Amlogic GX SoC family, such as
+ the S905, S905X/D and S912.
+
+config CLK_MESON_AXG
+ bool "Enable clock support for Amlogic AXG"
+ depends on CLK && ARCH_MESON
+ default MESON_AXG
+ help
+ Enable clock support for the Amlogic AXG SoC family, such as
+ the A113X/D
+
+config CLK_MESON_G12A
+ bool "Enable clock support for Amlogic G12A"
+ depends on CLK && ARCH_MESON
+ default MESON_G12A
+ help
+ Enable clock support for the Amlogic G12A SoC family, such as
+ the S905X/D2
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
new file mode 100644
index 0000000..c873d69
--- /dev/null
+++ b/drivers/clk/meson/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (c) 2019 Baylibre, SAS
+# Jerome Brunet <jbrunet@baylibre.com>
+
+obj-$(CONFIG_CLK_MESON_GX) += gxbb.o
+obj-$(CONFIG_CLK_MESON_AXG) += axg.o
+obj-$(CONFIG_CLK_MESON_G12A) += g12a.o
+
diff --git a/drivers/clk/clk_meson_axg.c b/drivers/clk/meson/axg.c
similarity index 100%
rename from drivers/clk/clk_meson_axg.c
rename to drivers/clk/meson/axg.c
diff --git a/drivers/clk/clk_meson.h b/drivers/clk/meson/clk_meson.h
similarity index 100%
rename from drivers/clk/clk_meson.h
rename to drivers/clk/meson/clk_meson.h
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
new file mode 100644
index 0000000..fedc9eb
--- /dev/null
+++ b/drivers/clk/meson/g12a.c
@@ -0,0 +1,315 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
+ * (C) Copyright 2018 - BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include <common.h>
+#include <asm/arch/clock-g12a.h>
+#include <asm/io.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <div64.h>
+#include <dt-bindings/clock/g12a-clkc.h>
+#include "clk_meson.h"
+
+#define XTAL_RATE 24000000
+
+struct meson_clk {
+ struct regmap *map;
+};
+
+static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id);
+
+#define NUM_CLKS 178
+
+static struct meson_gate gates[NUM_CLKS] = {
+ /* Everything Else (EE) domain gates */
+ MESON_GATE(CLKID_SPICC0, HHI_GCLK_MPEG0, 8),
+ MESON_GATE(CLKID_I2C, HHI_GCLK_MPEG0, 9),
+ MESON_GATE(CLKID_UART0, HHI_GCLK_MPEG0, 13),
+ MESON_GATE(CLKID_SPICC1, HHI_GCLK_MPEG0, 14),
+ MESON_GATE(CLKID_SD_EMMC_B, HHI_GCLK_MPEG0, 25),
+ MESON_GATE(CLKID_SD_EMMC_C, HHI_GCLK_MPEG0, 26),
+ MESON_GATE(CLKID_ETH, HHI_GCLK_MPEG1, 3),
+ MESON_GATE(CLKID_UART1, HHI_GCLK_MPEG1, 16),
+
+ /* Peripheral Gates */
+ MESON_GATE(CLKID_SD_EMMC_B_CLK0, HHI_SD_EMMC_CLK_CNTL, 23),
+ MESON_GATE(CLKID_SD_EMMC_C_CLK0, HHI_NAND_CLK_CNTL, 7),
+};
+
+static int meson_set_gate(struct clk *clk, bool on)
+{
+ struct meson_clk *priv = dev_get_priv(clk->dev);
+ struct meson_gate *gate;
+
+ if (clk->id >= ARRAY_SIZE(gates))
+ return -ENOENT;
+
+ gate = &gates[clk->id];
+
+ if (gate->reg == 0)
+ return 0;
+
+ regmap_update_bits(priv->map, gate->reg,
+ BIT(gate->bit), on ? BIT(gate->bit) : 0);
+
+ return 0;
+}
+
+static int meson_clk_enable(struct clk *clk)
+{
+ return meson_set_gate(clk, true);
+}
+
+static int meson_clk_disable(struct clk *clk)
+{
+ return meson_set_gate(clk, false);
+}
+
+static unsigned long meson_clk81_get_rate(struct clk *clk)
+{
+ struct meson_clk *priv = dev_get_priv(clk->dev);
+ unsigned long parent_rate;
+ uint reg;
+ int parents[] = {
+ -1,
+ -1,
+ CLKID_FCLK_DIV7,
+ CLKID_MPLL1,
+ CLKID_MPLL2,
+ CLKID_FCLK_DIV4,
+ CLKID_FCLK_DIV3,
+ CLKID_FCLK_DIV5
+ };
+
+ /* mux */
+ regmap_read(priv->map, HHI_MPEG_CLK_CNTL, ®);
+ reg = (reg >> 12) & 7;
+
+ switch (reg) {
+ case 0:
+ parent_rate = XTAL_RATE;
+ break;
+ case 1:
+ return -ENOENT;
+ default:
+ parent_rate = meson_clk_get_rate_by_id(clk, parents[reg]);
+ }
+
+ /* divider */
+ regmap_read(priv->map, HHI_MPEG_CLK_CNTL, ®);
+ reg = reg & ((1 << 7) - 1);
+
+ return parent_rate / reg;
+}
+
+static long mpll_rate_from_params(unsigned long parent_rate,
+ unsigned long sdm,
+ unsigned long n2)
+{
+ unsigned long divisor = (SDM_DEN * n2) + sdm;
+
+ if (n2 < N2_MIN)
+ return -EINVAL;
+
+ return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor);
+}
+
+static struct parm meson_mpll0_parm[2] = {
+ {HHI_MPLL_CNTL1, 0, 14}, /* psdm */
+ {HHI_MPLL_CNTL1, 20, 9}, /* pn2 */
+};
+
+static struct parm meson_mpll1_parm[2] = {
+ {HHI_MPLL_CNTL3, 0, 14}, /* psdm */
+ {HHI_MPLL_CNTL3, 20, 9}, /* pn2 */
+};
+
+static struct parm meson_mpll2_parm[2] = {
+ {HHI_MPLL_CNTL5, 0, 14}, /* psdm */
+ {HHI_MPLL_CNTL5, 20, 9}, /* pn2 */
+};
+
+/*
+ * MultiPhase Locked Loops are outputs from a PLL with additional frequency
+ * scaling capabilities. MPLL rates are calculated as:
+ *
+ * f(N2_integer, SDM_IN ) = 2.0G/(N2_integer + SDM_IN/16384)
+ */
+static ulong meson_mpll_get_rate(struct clk *clk, unsigned long id)
+{
+ struct meson_clk *priv = dev_get_priv(clk->dev);
+ struct parm *psdm, *pn2;
+ unsigned long sdm, n2;
+ unsigned long parent_rate;
+ uint reg;
+
+ switch (id) {
+ case CLKID_MPLL0:
+ psdm = &meson_mpll0_parm[0];
+ pn2 = &meson_mpll0_parm[1];
+ break;
+ case CLKID_MPLL1:
+ psdm = &meson_mpll1_parm[0];
+ pn2 = &meson_mpll1_parm[1];
+ break;
+ case CLKID_MPLL2:
+ psdm = &meson_mpll2_parm[0];
+ pn2 = &meson_mpll2_parm[1];
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ parent_rate = meson_clk_get_rate_by_id(clk, CLKID_FIXED_PLL);
+ if (IS_ERR_VALUE(parent_rate))
+ return parent_rate;
+
+ regmap_read(priv->map, psdm->reg_off, ®);
+ sdm = PARM_GET(psdm->width, psdm->shift, reg);
+
+ regmap_read(priv->map, pn2->reg_off, ®);
+ n2 = PARM_GET(pn2->width, pn2->shift, reg);
+
+ return mpll_rate_from_params(parent_rate, sdm, n2);
+}
+
+static struct parm meson_fixed_pll_parm[3] = {
+ {HHI_FIX_PLL_CNTL0, 0, 8}, /* pm */
+ {HHI_FIX_PLL_CNTL0, 10, 5}, /* pn */
+ {HHI_FIX_PLL_CNTL0, 16, 2}, /* pod */
+};
+
+static struct parm meson_sys_pll_parm[3] = {
+ {HHI_SYS_PLL_CNTL0, 0, 8}, /* pm */
+ {HHI_SYS_PLL_CNTL0, 10, 5}, /* pn */
+ {HHI_SYS_PLL_CNTL0, 16, 2}, /* pod */
+};
+
+static ulong meson_pll_get_rate(struct clk *clk, unsigned long id)
+{
+ struct meson_clk *priv = dev_get_priv(clk->dev);
+ struct parm *pm, *pn, *pod;
+ unsigned long parent_rate_mhz = XTAL_RATE / 1000000;
+ u16 n, m, od;
+ uint reg;
+
+ /*
+ * FIXME: Between the unit conversion and the missing frac, we know
+ * rate will be slightly off ...
+ */
+
+ switch (id) {
+ case CLKID_FIXED_PLL:
+ pm = &meson_fixed_pll_parm[0];
+ pn = &meson_fixed_pll_parm[1];
+ pod = &meson_fixed_pll_parm[2];
+ break;
+ case CLKID_SYS_PLL:
+ pm = &meson_sys_pll_parm[0];
+ pn = &meson_sys_pll_parm[1];
+ pod = &meson_sys_pll_parm[2];
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ regmap_read(priv->map, pn->reg_off, ®);
+ n = PARM_GET(pn->width, pn->shift, reg);
+
+ regmap_read(priv->map, pm->reg_off, ®);
+ m = PARM_GET(pm->width, pm->shift, reg);
+
+ regmap_read(priv->map, pod->reg_off, ®);
+ od = PARM_GET(pod->width, pod->shift, reg);
+
+ return ((parent_rate_mhz * m / n) >> od) * 1000000;
+}
+
+static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id)
+{
+ ulong rate;
+
+ switch (id) {
+ case CLKID_FIXED_PLL:
+ case CLKID_SYS_PLL:
+ rate = meson_pll_get_rate(clk, id);
+ break;
+ case CLKID_FCLK_DIV2:
+ rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 2;
+ break;
+ case CLKID_FCLK_DIV3:
+ rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 3;
+ break;
+ case CLKID_FCLK_DIV4:
+ rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 4;
+ break;
+ case CLKID_FCLK_DIV5:
+ rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 5;
+ break;
+ case CLKID_FCLK_DIV7:
+ rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 7;
+ break;
+ case CLKID_MPLL0:
+ case CLKID_MPLL1:
+ case CLKID_MPLL2:
+ rate = meson_mpll_get_rate(clk, id);
+ break;
+ case CLKID_CLK81:
+ rate = meson_clk81_get_rate(clk);
+ break;
+ default:
+ if (gates[id].reg != 0) {
+ /* a clock gate */
+ rate = meson_clk81_get_rate(clk);
+ break;
+ }
+ return -ENOENT;
+ }
+
+ debug("clock %lu has rate %lu\n", id, rate);
+ return rate;
+}
+
+static ulong meson_clk_get_rate(struct clk *clk)
+{
+ return meson_clk_get_rate_by_id(clk, clk->id);
+}
+
+static int meson_clk_probe(struct udevice *dev)
+{
+ struct meson_clk *priv = dev_get_priv(dev);
+
+ priv->map = syscon_node_to_regmap(dev_get_parent(dev)->node);
+ if (IS_ERR(priv->map))
+ return PTR_ERR(priv->map);
+
+ debug("meson-clk-g12a: probed\n");
+
+ return 0;
+}
+
+static struct clk_ops meson_clk_ops = {
+ .disable = meson_clk_disable,
+ .enable = meson_clk_enable,
+ .get_rate = meson_clk_get_rate,
+};
+
+static const struct udevice_id meson_clk_ids[] = {
+ { .compatible = "amlogic,g12a-clkc" },
+ { }
+};
+
+U_BOOT_DRIVER(meson_clk_g12a) = {
+ .name = "meson_clk_g12a",
+ .id = UCLASS_CLK,
+ .of_match = meson_clk_ids,
+ .priv_auto_alloc_size = sizeof(struct meson_clk),
+ .ops = &meson_clk_ops,
+ .probe = meson_clk_probe,
+};
diff --git a/drivers/clk/clk_meson.c b/drivers/clk/meson/gxbb.c
similarity index 100%
rename from drivers/clk/clk_meson.c
rename to drivers/clk/meson/gxbb.c
diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig
index 2b28a97..8f60b56 100644
--- a/drivers/ddr/altera/Kconfig
+++ b/drivers/ddr/altera/Kconfig
@@ -1,5 +1,7 @@
config ALTERA_SDRAM
bool "SoCFPGA DDR SDRAM driver"
depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
+ select RAM if TARGET_SOCFPGA_GEN5
+ select SPL_RAM if TARGET_SOCFPGA_GEN5
help
Enable DDR SDRAM controller for the SoCFPGA devices.
diff --git a/drivers/ddr/altera/sdram_gen5.c b/drivers/ddr/altera/sdram_gen5.c
index 8210604..fcd89b6 100644
--- a/drivers/ddr/altera/sdram_gen5.c
+++ b/drivers/ddr/altera/sdram_gen5.c
@@ -3,14 +3,30 @@
* Copyright Altera Corporation (C) 2014-2015
*/
#include <common.h>
+#include <dm.h>
#include <errno.h>
#include <div64.h>
+#include <ram.h>
+#include <reset.h>
#include <watchdog.h>
#include <asm/arch/fpga_manager.h>
+#include <asm/arch/reset_manager.h>
#include <asm/arch/sdram.h>
#include <asm/arch/system_manager.h>
#include <asm/io.h>
+#include "sequencer.h"
+
+#ifdef CONFIG_SPL_BUILD
+
+struct altera_gen5_sdram_priv {
+ struct ram_info info;
+};
+
+struct altera_gen5_sdram_platdata {
+ struct socfpga_sdr *sdr;
+};
+
struct sdram_prot_rule {
u32 sdram_start; /* SDRAM start address */
u32 sdram_end; /* SDRAM end address */
@@ -26,8 +42,8 @@
static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-static struct socfpga_sdr_ctrl *sdr_ctrl =
- (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
+
+static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl);
/**
* get_errata_rows() - Up the number of DRAM rows to cover entire address space
@@ -104,7 +120,8 @@
}
/* SDRAM protection rules vary from 0-19, a total of 20 rules. */
-static void sdram_set_rule(struct sdram_prot_rule *prule)
+static void sdram_set_rule(struct socfpga_sdr_ctrl *sdr_ctrl,
+ struct sdram_prot_rule *prule)
{
u32 lo_addr_bits;
u32 hi_addr_bits;
@@ -141,7 +158,8 @@
writel(0, &sdr_ctrl->prot_rule_rdwr);
}
-static void sdram_get_rule(struct sdram_prot_rule *prule)
+static void sdram_get_rule(struct socfpga_sdr_ctrl *sdr_ctrl,
+ struct sdram_prot_rule *prule)
{
u32 addr;
u32 id;
@@ -172,7 +190,8 @@
}
static void
-sdram_set_protection_config(const u32 sdram_start, const u32 sdram_end)
+sdram_set_protection_config(struct socfpga_sdr_ctrl *sdr_ctrl,
+ const u32 sdram_start, const u32 sdram_end)
{
struct sdram_prot_rule rule;
int rules;
@@ -185,7 +204,7 @@
for (rules = 0; rules < 20; rules++) {
rule.rule = rules;
- sdram_set_rule(&rule);
+ sdram_set_rule(sdr_ctrl, &rule);
}
/* new rule: accept SDRAM */
@@ -200,13 +219,13 @@
rule.rule = 0;
/* set new rule */
- sdram_set_rule(&rule);
+ sdram_set_rule(sdr_ctrl, &rule);
/* default rule: reject everything */
writel(0x3ff, &sdr_ctrl->protport_default);
}
-static void sdram_dump_protection_config(void)
+static void sdram_dump_protection_config(struct socfpga_sdr_ctrl *sdr_ctrl)
{
struct sdram_prot_rule rule;
int rules;
@@ -216,7 +235,7 @@
for (rules = 0; rules < 20; rules++) {
rule.rule = rules;
- sdram_get_rule(&rule);
+ sdram_get_rule(sdr_ctrl, &rule);
debug("Rule %d, rules ...\n", rules);
debug(" sdram start %x\n", rule.sdram_start);
debug(" sdram end %x\n", rule.sdram_end);
@@ -322,7 +341,8 @@
*
* This function loads the register values into the SDRAM controller block.
*/
-static void sdr_load_regs(const struct socfpga_sdram_config *cfg)
+static void sdr_load_regs(struct socfpga_sdr_ctrl *sdr_ctrl,
+ const struct socfpga_sdram_config *cfg)
{
const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg);
const u32 dram_addrw = sdr_get_addr_rw(cfg);
@@ -426,7 +446,8 @@
*
* Initialize the SDRAM MMR.
*/
-int sdram_mmr_init_full(unsigned int sdr_phy_reg)
+int sdram_mmr_init_full(struct socfpga_sdr_ctrl *sdr_ctrl,
+ unsigned int sdr_phy_reg)
{
const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
const unsigned int rows =
@@ -436,7 +457,7 @@
writel(rows, &sysmgr_regs->iswgrp_handoff[4]);
- sdr_load_regs(cfg);
+ sdr_load_regs(sdr_ctrl, cfg);
/* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]);
@@ -459,9 +480,10 @@
SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK,
1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB);
- sdram_set_protection_config(0, sdram_calculate_size() - 1);
+ sdram_set_protection_config(sdr_ctrl, 0,
+ sdram_calculate_size(sdr_ctrl) - 1);
- sdram_dump_protection_config();
+ sdram_dump_protection_config(sdr_ctrl);
return 0;
}
@@ -472,7 +494,7 @@
* Calculate SDRAM device size based on SDRAM controller parameters.
* Size is specified in bytes.
*/
-unsigned long sdram_calculate_size(void)
+static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl)
{
unsigned long temp;
unsigned long row, bank, col, cs, width;
@@ -534,3 +556,94 @@
return temp;
}
+
+static int altera_gen5_sdram_ofdata_to_platdata(struct udevice *dev)
+{
+ struct altera_gen5_sdram_platdata *plat = dev->platdata;
+
+ plat->sdr = (struct socfpga_sdr *)devfdt_get_addr_index(dev, 0);
+ if (!plat->sdr)
+ return -ENODEV;
+
+ return 0;
+}
+
+static int altera_gen5_sdram_probe(struct udevice *dev)
+{
+ int ret;
+ unsigned long sdram_size;
+ struct altera_gen5_sdram_platdata *plat = dev->platdata;
+ struct altera_gen5_sdram_priv *priv = dev_get_priv(dev);
+ struct socfpga_sdr_ctrl *sdr_ctrl = &plat->sdr->sdr_ctrl;
+ struct reset_ctl_bulk resets;
+
+ ret = reset_get_bulk(dev, &resets);
+ if (ret) {
+ dev_err(dev, "Can't get reset: %d\n", ret);
+ return -ENODEV;
+ }
+ reset_deassert_bulk(&resets);
+
+ if (sdram_mmr_init_full(sdr_ctrl, 0xffffffff) != 0) {
+ puts("SDRAM init failed.\n");
+ goto failed;
+ }
+
+ debug("SDRAM: Calibrating PHY\n");
+ /* SDRAM calibration */
+ if (sdram_calibration_full(plat->sdr) == 0) {
+ puts("SDRAM calibration failed.\n");
+ goto failed;
+ }
+
+ sdram_size = sdram_calculate_size(sdr_ctrl);
+ debug("SDRAM: %ld MiB\n", sdram_size >> 20);
+
+ /* Sanity check ensure correct SDRAM size specified */
+ if (get_ram_size(0, sdram_size) != sdram_size) {
+ puts("SDRAM size check failed!\n");
+ goto failed;
+ }
+
+ priv->info.base = 0;
+ priv->info.size = sdram_size;
+
+ return 0;
+
+failed:
+ reset_release_bulk(&resets);
+ return -ENODEV;
+}
+
+static int altera_gen5_sdram_get_info(struct udevice *dev,
+ struct ram_info *info)
+{
+ struct altera_gen5_sdram_priv *priv = dev_get_priv(dev);
+
+ info->base = priv->info.base;
+ info->size = priv->info.size;
+
+ return 0;
+}
+
+static struct ram_ops altera_gen5_sdram_ops = {
+ .get_info = altera_gen5_sdram_get_info,
+};
+
+static const struct udevice_id altera_gen5_sdram_ids[] = {
+ { .compatible = "altr,sdr-ctl" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(altera_gen5_sdram) = {
+ .name = "altr_sdr_ctl",
+ .id = UCLASS_RAM,
+ .of_match = altera_gen5_sdram_ids,
+ .ops = &altera_gen5_sdram_ops,
+ .ofdata_to_platdata = altera_gen5_sdram_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct altera_gen5_sdram_platdata),
+ .probe = altera_gen5_sdram_probe,
+ .priv_auto_alloc_size = sizeof(struct altera_gen5_sdram_priv),
+};
+
+#endif /* CONFIG_SPL_BUILD */
diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
index a48567c..e4d4a02 100644
--- a/drivers/ddr/altera/sdram_s10.c
+++ b/drivers/ddr/altera/sdram_s10.c
@@ -7,12 +7,14 @@
#include <common.h>
#include <errno.h>
#include <div64.h>
+#include <fdtdec.h>
#include <asm/io.h>
#include <wait_bit.h>
#include <asm/arch/firewall_s10.h>
#include <asm/arch/sdram_s10.h>
#include <asm/arch/system_manager.h>
#include <asm/arch/reset_manager.h>
+#include <linux/sizes.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -21,6 +23,8 @@
#define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
+#define PGTABLE_OFF 0x4000
+
/* The followring are the supported configurations */
u32 ddr_config[] = {
/* DDR_CONFIG(Address order,Bank,Column,Row) */
@@ -134,6 +138,108 @@
SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);
}
+static void sdram_clear_mem(phys_addr_t addr, phys_size_t size)
+{
+ phys_size_t i;
+
+ if (addr % CONFIG_SYS_CACHELINE_SIZE) {
+ printf("DDR: address 0x%llx is not cacheline size aligned.\n",
+ addr);
+ hang();
+ }
+
+ if (size % CONFIG_SYS_CACHELINE_SIZE) {
+ printf("DDR: size 0x%llx is not multiple of cacheline size\n",
+ size);
+ hang();
+ }
+
+ /* Use DC ZVA instruction to clear memory to zeros by a cache line */
+ for (i = 0; i < size; i = i + CONFIG_SYS_CACHELINE_SIZE) {
+ asm volatile("dc zva, %0"
+ :
+ : "r"(addr)
+ : "memory");
+ addr += CONFIG_SYS_CACHELINE_SIZE;
+ }
+}
+
+static void sdram_init_ecc_bits(bd_t *bd)
+{
+ phys_size_t size, size_init;
+ phys_addr_t start_addr;
+ int bank = 0;
+ unsigned int start = get_timer(0);
+
+ icache_enable();
+
+ start_addr = bd->bi_dram[0].start;
+ size = bd->bi_dram[0].size;
+
+ /* Initialize small block for page table */
+ memset((void *)start_addr, 0, PGTABLE_SIZE + PGTABLE_OFF);
+ gd->arch.tlb_addr = start_addr + PGTABLE_OFF;
+ gd->arch.tlb_size = PGTABLE_SIZE;
+ start_addr += PGTABLE_SIZE + PGTABLE_OFF;
+ size -= (PGTABLE_OFF + PGTABLE_SIZE);
+ dcache_enable();
+
+ while (1) {
+ while (size) {
+ size_init = min((phys_addr_t)SZ_1G, (phys_addr_t)size);
+ sdram_clear_mem(start_addr, size_init);
+ size -= size_init;
+ start_addr += size_init;
+ WATCHDOG_RESET();
+ }
+
+ bank++;
+ if (bank >= CONFIG_NR_DRAM_BANKS)
+ break;
+
+ start_addr = bd->bi_dram[bank].start;
+ size = bd->bi_dram[bank].size;
+ }
+
+ dcache_disable();
+ icache_disable();
+
+ printf("SDRAM-ECC: Initialized success with %d ms\n",
+ (unsigned int)get_timer(start));
+}
+
+static void sdram_size_check(bd_t *bd)
+{
+ phys_size_t total_ram_check = 0;
+ phys_size_t ram_check = 0;
+ phys_addr_t start = 0;
+ int bank;
+
+ /* Sanity check ensure correct SDRAM size specified */
+ debug("DDR: Running SDRAM size sanity check\n");
+
+ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+ start = bd->bi_dram[bank].start;
+ while (ram_check < bd->bi_dram[bank].size) {
+ ram_check += get_ram_size((void *)(start + ram_check),
+ (phys_size_t)SZ_1G);
+ }
+ total_ram_check += ram_check;
+ ram_check = 0;
+ }
+
+ /* If the ram_size is 2GB smaller, we can assume the IO space is
+ * not mapped in. gd->ram_size is the actual size of the dram
+ * not the accessible size.
+ */
+ if (total_ram_check != gd->ram_size) {
+ puts("DDR: SDRAM size check failed!\n");
+ hang();
+ }
+
+ debug("DDR: SDRAM size check passed!\n");
+}
+
/**
* sdram_mmr_init_full() - Function to initialize SDRAM MMR
*
@@ -144,6 +250,8 @@
u32 update_value, io48_value, ddrioctl;
u32 i;
int ret;
+ phys_size_t hw_size;
+ bd_t bd = {0};
/* Enable access to DDR from CPU master */
clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_DDRREG),
@@ -335,9 +443,22 @@
unsigned long long size = sdram_calculate_size();
/* If the size is invalid, use default Config size */
if (size <= 0)
- gd->ram_size = PHYS_SDRAM_1_SIZE;
+ hw_size = PHYS_SDRAM_1_SIZE;
else
- gd->ram_size = size;
+ hw_size = size;
+
+ /* Get bank configuration from devicetree */
+ ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,
+ (phys_size_t *)&gd->ram_size, &bd);
+ if (ret) {
+ puts("DDR: Failed to decode memory node\n");
+ return -1;
+ }
+
+ if (gd->ram_size != hw_size)
+ printf("DDR: Warning: DRAM size from device tree mismatch with hardware.\n");
+
+ printf("DDR: %lld MiB\n", gd->ram_size >> 20);
/* Enable or disable the SDRAM ECC */
if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) {
@@ -351,6 +472,15 @@
setbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL2,
(DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
+ writel(DDR_HMC_ERRINTEN_INTMASK,
+ SOCFPGA_SDR_ADDRESS + ERRINTENS);
+
+ /* Enable non-secure writes to HMC Adapter for SDRAM ECC */
+ writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR);
+
+ /* Initialize memory content if not from warm reset */
+ if (!cpu_has_been_warmreset())
+ sdram_init_ecc_bits(&bd);
} else {
clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1,
(DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
@@ -361,6 +491,8 @@
DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
}
+ sdram_size_check(&bd);
+
debug("DDR: HMC init success\n");
return 0;
}
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 5e7a943..0e45262 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -3705,12 +3705,19 @@
&sdr_reg_file->trk_rfsh);
}
-int sdram_calibration_full(void)
+int sdram_calibration_full(struct socfpga_sdr *sdr)
{
struct param_type my_param;
struct gbl_type my_gbl;
u32 pass;
+ /*
+ * For size reasons, this file uses hard coded addresses.
+ * Check if we are called with the correct address.
+ */
+ if (sdr != (struct socfpga_sdr *)SOCFPGA_SDR_ADDRESS)
+ return -ENODEV;
+
memset(&my_param, 0, sizeof(my_param));
memset(&my_gbl, 0, sizeof(my_gbl));
diff --git a/drivers/ddr/altera/sequencer.h b/drivers/ddr/altera/sequencer.h
index a5760b0..d7f6935 100644
--- a/drivers/ddr/altera/sequencer.h
+++ b/drivers/ddr/altera/sequencer.h
@@ -223,4 +223,39 @@
u32 mem_t_add;
u32 t_rl_add;
};
+
+/* This struct describes the controller @ SOCFPGA_SDR_ADDRESS */
+struct socfpga_sdr {
+ /* SDR_PHYGRP_SCCGRP_ADDRESS */
+ u8 _align1[0xe00];
+ /* SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00 */
+ struct socfpga_sdr_scc_mgr sdr_scc_mgr;
+ u8 _align2[0x1bc];
+ /* SDR_PHYGRP_PHYMGRGRP_ADDRESS */
+ struct socfpga_phy_mgr_cmd phy_mgr_cmd;
+ u8 _align3[0x2c];
+ /* SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40 */
+ struct socfpga_phy_mgr_cfg phy_mgr_cfg;
+ u8 _align4[0xfa0];
+ /* SDR_PHYGRP_RWMGRGRP_ADDRESS */
+ u8 rwmgr_grp[0x800];
+ /* SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800 */
+ struct socfpga_sdr_rw_load_manager sdr_rw_load_mgr_regs;
+ u8 _align5[0x3f0];
+ /* SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00 */
+ struct socfpga_sdr_rw_load_jump_manager sdr_rw_load_jump_mgr_regs;
+ u8 _align6[0x13f0];
+ /* SDR_PHYGRP_DATAMGRGRP_ADDRESS */
+ struct socfpga_data_mgr data_mgr;
+ u8 _align7[0x7f0];
+ /* SDR_PHYGRP_REGFILEGRP_ADDRESS */
+ struct socfpga_sdr_reg_file sdr_reg_file;
+ u8 _align8[0x7c8];
+ /* SDR_CTRLGRP_ADDRESS */
+ struct socfpga_sdr_ctrl sdr_ctrl;
+ u8 _align9[0xea4];
+};
+
+int sdram_calibration_full(struct socfpga_sdr *sdr);
+
#endif /* _SEQUENCER_H_ */
diff --git a/drivers/fastboot/fb_getvar.c b/drivers/fastboot/fb_getvar.c
index 4d264c9..4268628 100644
--- a/drivers/fastboot/fb_getvar.c
+++ b/drivers/fastboot/fb_getvar.c
@@ -17,6 +17,7 @@
static void getvar_serialno(char *var_parameter, char *response);
static void getvar_version_baseband(char *var_parameter, char *response);
static void getvar_product(char *var_parameter, char *response);
+static void getvar_platform(char *var_parameter, char *response);
static void getvar_current_slot(char *var_parameter, char *response);
static void getvar_slot_suffixes(char *var_parameter, char *response);
static void getvar_has_slot(char *var_parameter, char *response);
@@ -56,13 +57,16 @@
.variable = "product",
.dispatch = getvar_product
}, {
+ .variable = "platform",
+ .dispatch = getvar_platform
+ }, {
.variable = "current-slot",
.dispatch = getvar_current_slot
}, {
.variable = "slot-suffixes",
.dispatch = getvar_slot_suffixes
}, {
- .variable = "has_slot",
+ .variable = "has-slot",
.dispatch = getvar_has_slot
#if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC)
}, {
@@ -117,6 +121,16 @@
fastboot_fail("Board not set", response);
}
+static void getvar_platform(char *var_parameter, char *response)
+{
+ const char *p = env_get("platform");
+
+ if (p)
+ fastboot_okay(p, response);
+ else
+ fastboot_fail("platform not set", response);
+}
+
static void getvar_current_slot(char *var_parameter, char *response)
{
/* A/B not implemented, for now always return _a */
diff --git a/drivers/fastboot/fb_mmc.c b/drivers/fastboot/fb_mmc.c
index 4c1c7fd..90ca81d 100644
--- a/drivers/fastboot/fb_mmc.c
+++ b/drivers/fastboot/fb_mmc.c
@@ -31,13 +31,13 @@
ret = part_get_info_by_name(dev_desc, name, info);
if (ret < 0) {
- /* strlen("fastboot_partition_alias_") + 32(part_name) + 1 */
- char env_alias_name[25 + 32 + 1];
+ /* strlen("fastboot_partition_alias_") + PART_NAME_LEN + 1 */
+ char env_alias_name[25 + PART_NAME_LEN + 1];
char *aliased_part_name;
/* check for alias */
strcpy(env_alias_name, "fastboot_partition_alias_");
- strncat(env_alias_name, name, 32);
+ strncat(env_alias_name, name, PART_NAME_LEN);
aliased_part_name = env_get(env_alias_name);
if (aliased_part_name != NULL)
ret = part_get_info_by_name(dev_desc,
@@ -308,8 +308,8 @@
fastboot_fail("block device not found", response);
return -ENOENT;
}
- if (!part_name) {
- fastboot_fail("partition not found", response);
+ if (!part_name || !strcmp(part_name, "")) {
+ fastboot_fail("partition not given", response);
return -ENOENT;
}
diff --git a/drivers/i2c/meson_i2c.c b/drivers/i2c/meson_i2c.c
index 7d06d95..ee59bac 100644
--- a/drivers/i2c/meson_i2c.c
+++ b/drivers/i2c/meson_i2c.c
@@ -41,7 +41,12 @@
u32 tok_rdata1;
};
+struct meson_i2c_data {
+ unsigned char div_factor;
+};
+
struct meson_i2c {
+ const struct meson_i2c_data *data;
struct clk clk;
struct i2c_regs *regs;
struct i2c_msg *msg; /* Current I2C message */
@@ -229,7 +234,7 @@
if (IS_ERR_VALUE(clk_rate))
return -EINVAL;
- div = DIV_ROUND_UP(clk_rate, speed * 4);
+ div = DIV_ROUND_UP(clk_rate, speed * i2c->data->div_factor);
/* clock divider has 12 bits */
if (div >= (1 << 12)) {
@@ -253,6 +258,8 @@
struct meson_i2c *i2c = dev_get_priv(bus);
int ret;
+ i2c->data = (const struct meson_i2c_data *)dev_get_driver_data(bus);
+
ret = clk_get_by_index(bus, 0, &i2c->clk);
if (ret < 0)
return ret;
@@ -272,11 +279,24 @@
.set_bus_speed = meson_i2c_set_bus_speed,
};
+static const struct meson_i2c_data i2c_meson6_data = {
+ .div_factor = 4,
+};
+
+static const struct meson_i2c_data i2c_gxbb_data = {
+ .div_factor = 4,
+};
+
+static const struct meson_i2c_data i2c_axg_data = {
+ .div_factor = 3,
+};
+
static const struct udevice_id meson_i2c_ids[] = {
- { .compatible = "amlogic,meson6-i2c" },
- { .compatible = "amlogic,meson-gx-i2c" },
- { .compatible = "amlogic,meson-gxbb-i2c" },
- { }
+ {.compatible = "amlogic,meson6-i2c", .data = (ulong)&i2c_meson6_data},
+ {.compatible = "amlogic,meson-gx-i2c", .data = (ulong)&i2c_gxbb_data},
+ {.compatible = "amlogic,meson-gxbb-i2c", .data = (ulong)&i2c_gxbb_data},
+ {.compatible = "amlogic,meson-axg-i2c", .data = (ulong)&i2c_axg_data},
+ {}
};
U_BOOT_DRIVER(i2c_meson) = {
diff --git a/drivers/led/Kconfig b/drivers/led/Kconfig
index 5da5c4a..5643939 100644
--- a/drivers/led/Kconfig
+++ b/drivers/led/Kconfig
@@ -28,6 +28,13 @@
LED HW controller accessed via MMIO registers.
HW has no blinking capabilities and up to 32 LEDs can be controlled.
+config LED_BCM6858
+ bool "LED Support for BCM6858"
+ depends on LED && (ARCH_BCM6858 || ARCH_BCM63158)
+ help
+ This option enables support for LEDs connected to the BCM6858
+ HW has blinking capabilities and up to 32 LEDs can be controlled.
+
config LED_BLINK
bool "Support LED blinking"
depends on LED
diff --git a/drivers/led/Makefile b/drivers/led/Makefile
index 160a8f3..3654dd3 100644
--- a/drivers/led/Makefile
+++ b/drivers/led/Makefile
@@ -6,4 +6,5 @@
obj-y += led-uclass.o
obj-$(CONFIG_LED_BCM6328) += led_bcm6328.o
obj-$(CONFIG_LED_BCM6358) += led_bcm6358.o
+obj-$(CONFIG_LED_BCM6858) += led_bcm6858.o
obj-$(CONFIG_$(SPL_)LED_GPIO) += led_gpio.o
diff --git a/drivers/led/led_bcm6858.c b/drivers/led/led_bcm6858.c
new file mode 100644
index 0000000..27a76fc
--- /dev/null
+++ b/drivers/led/led_bcm6858.c
@@ -0,0 +1,250 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Philippe Reynes <philippe.reynes@softathome.com>
+ *
+ * based on:
+ * drivers/led/led_bcm6328.c
+ * drivers/led/led_bcm6358.c
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <led.h>
+#include <asm/io.h>
+#include <dm/lists.h>
+
+#define LEDS_MAX 32
+#define LEDS_WAIT 100
+
+/* LED Mode register */
+#define LED_MODE_REG 0x0
+#define LED_MODE_OFF 0
+#define LED_MODE_ON 1
+#define LED_MODE_MASK 1
+
+/* LED Controller Global settings register */
+#define LED_CTRL_REG 0x00
+#define LED_CTRL_MASK 0x1f
+#define LED_CTRL_LED_TEST_MODE BIT(0)
+#define LED_CTRL_SERIAL_LED_DATA_PPOL BIT(1)
+#define LED_CTRL_SERIAL_LED_CLK_POL BIT(2)
+#define LED_CTRL_SERIAL_LED_EN_POL BIT(3)
+#define LED_CTRL_SERIAL_LED_MSB_FIRST BIT(4)
+
+/* LED Controller IP LED source select register */
+#define LED_HW_LED_EN_REG 0x08
+/* LED Flash control register0 */
+#define LED_FLASH_RATE_CONTROL_REG0 0x10
+/* Soft LED input register */
+#define LED_SW_LED_IP_REG 0xb8
+/* Soft LED input polarity register */
+#define LED_SW_LED_IP_PPOL_REG 0xbc
+
+struct bcm6858_led_priv {
+ void __iomem *regs;
+ u8 pin;
+};
+
+#ifdef CONFIG_LED_BLINK
+/*
+ * The value for flash rate are:
+ * 0 : no blinking
+ * 1 : rate is 25 Hz => 40 ms (period)
+ * 2 : rate is 12.5 Hz => 80 ms (period)
+ * 3 : rate is 6.25 Hz => 160 ms (period)
+ * 4 : rate is 3.125 Hz => 320 ms (period)
+ * 5 : rate is 1.5625 Hz => 640 ms (period)
+ * 6 : rate is 0.7815 Hz => 1280 ms (period)
+ * 7 : rate is 0.390625 Hz => 2560 ms (period)
+ */
+static const int bcm6858_flash_rate[8] = {
+ 0, 40, 80, 160, 320, 640, 1280, 2560
+};
+
+static u32 bcm6858_flash_rate_value(int period_ms)
+{
+ unsigned long value = 7;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(bcm6858_flash_rate); i++) {
+ if (period_ms <= bcm6858_flash_rate[i]) {
+ value = i;
+ break;
+ }
+ }
+
+ return value;
+}
+
+static int bcm6858_led_set_period(struct udevice *dev, int period_ms)
+{
+ struct bcm6858_led_priv *priv = dev_get_priv(dev);
+ u32 offset, shift, mask, value;
+
+ offset = (priv->pin / 8) * 4;
+ shift = (priv->pin % 8) * 4;
+ mask = 0x7 << shift;
+ value = bcm6858_flash_rate_value(period_ms) << shift;
+
+ clrbits_32(priv->regs + LED_FLASH_RATE_CONTROL_REG0 + offset, mask);
+ setbits_32(priv->regs + LED_FLASH_RATE_CONTROL_REG0 + offset, value);
+
+ return 0;
+}
+#endif
+
+static enum led_state_t bcm6858_led_get_state(struct udevice *dev)
+{
+ struct bcm6858_led_priv *priv = dev_get_priv(dev);
+ enum led_state_t state = LEDST_OFF;
+ u32 sw_led_ip;
+
+ sw_led_ip = readl(priv->regs + LED_SW_LED_IP_REG);
+ if (sw_led_ip & (1 << priv->pin))
+ state = LEDST_ON;
+
+ return state;
+}
+
+static int bcm6858_led_set_state(struct udevice *dev, enum led_state_t state)
+{
+ struct bcm6858_led_priv *priv = dev_get_priv(dev);
+
+ switch (state) {
+ case LEDST_OFF:
+ clrbits_32(priv->regs + LED_SW_LED_IP_REG, (1 << priv->pin));
+#ifdef CONFIG_LED_BLINK
+ bcm6858_led_set_period(dev, 0);
+#endif
+ break;
+ case LEDST_ON:
+ setbits_32(priv->regs + LED_SW_LED_IP_REG, (1 << priv->pin));
+#ifdef CONFIG_LED_BLINK
+ bcm6858_led_set_period(dev, 0);
+#endif
+ break;
+ case LEDST_TOGGLE:
+ if (bcm6858_led_get_state(dev) == LEDST_OFF)
+ return bcm6858_led_set_state(dev, LEDST_ON);
+ else
+ return bcm6858_led_set_state(dev, LEDST_OFF);
+ break;
+#ifdef CONFIG_LED_BLINK
+ case LEDST_BLINK:
+ setbits_32(priv->regs + LED_SW_LED_IP_REG, (1 << priv->pin));
+ break;
+#endif
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static const struct led_ops bcm6858_led_ops = {
+ .get_state = bcm6858_led_get_state,
+ .set_state = bcm6858_led_set_state,
+#ifdef CONFIG_LED_BLINK
+ .set_period = bcm6858_led_set_period,
+#endif
+};
+
+static int bcm6858_led_probe(struct udevice *dev)
+{
+ struct led_uc_plat *uc_plat = dev_get_uclass_platdata(dev);
+
+ /* Top-level LED node */
+ if (!uc_plat->label) {
+ void __iomem *regs;
+ u32 set_bits = 0;
+
+ regs = dev_remap_addr(dev);
+ if (!regs)
+ return -EINVAL;
+
+ if (dev_read_bool(dev, "brcm,serial-led-msb-first"))
+ set_bits |= LED_CTRL_SERIAL_LED_MSB_FIRST;
+ if (dev_read_bool(dev, "brcm,serial-led-en-pol"))
+ set_bits |= LED_CTRL_SERIAL_LED_EN_POL;
+ if (dev_read_bool(dev, "brcm,serial-led-clk-pol"))
+ set_bits |= LED_CTRL_SERIAL_LED_CLK_POL;
+ if (dev_read_bool(dev, "brcm,serial-led-data-ppol"))
+ set_bits |= LED_CTRL_SERIAL_LED_DATA_PPOL;
+ if (dev_read_bool(dev, "brcm,led-test-mode"))
+ set_bits |= LED_CTRL_LED_TEST_MODE;
+
+ clrsetbits_32(regs + LED_CTRL_REG, ~0, set_bits);
+ } else {
+ struct bcm6858_led_priv *priv = dev_get_priv(dev);
+ void __iomem *regs;
+ unsigned int pin;
+
+ regs = dev_remap_addr(dev_get_parent(dev));
+ if (!regs)
+ return -EINVAL;
+
+ pin = dev_read_u32_default(dev, "reg", LEDS_MAX);
+ if (pin >= LEDS_MAX)
+ return -EINVAL;
+
+ priv->regs = regs;
+ priv->pin = pin;
+
+ /* this led is managed by software */
+ clrbits_32(regs + LED_HW_LED_EN_REG, 1 << pin);
+
+ /* configure the polarity */
+ if (dev_read_bool(dev, "active-low"))
+ clrbits_32(regs + LED_SW_LED_IP_PPOL_REG, 1 << pin);
+ else
+ setbits_32(regs + LED_SW_LED_IP_PPOL_REG, 1 << pin);
+ }
+
+ return 0;
+}
+
+static int bcm6858_led_bind(struct udevice *parent)
+{
+ ofnode node;
+
+ dev_for_each_subnode(node, parent) {
+ struct led_uc_plat *uc_plat;
+ struct udevice *dev;
+ const char *label;
+ int ret;
+
+ label = ofnode_read_string(node, "label");
+ if (!label) {
+ debug("%s: node %s has no label\n", __func__,
+ ofnode_get_name(node));
+ return -EINVAL;
+ }
+
+ ret = device_bind_driver_to_node(parent, "bcm6858-led",
+ ofnode_get_name(node),
+ node, &dev);
+ if (ret)
+ return ret;
+
+ uc_plat = dev_get_uclass_platdata(dev);
+ uc_plat->label = label;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id bcm6858_led_ids[] = {
+ { .compatible = "brcm,bcm6858-leds" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(bcm6858_led) = {
+ .name = "bcm6858-led",
+ .id = UCLASS_LED,
+ .of_match = bcm6858_led_ids,
+ .bind = bcm6858_led_bind,
+ .probe = bcm6858_led_probe,
+ .priv_auto_alloc_size = sizeof(struct bcm6858_led_priv),
+ .ops = &bcm6858_led_ops,
+};
diff --git a/drivers/misc/fs_loader.c b/drivers/misc/fs_loader.c
index 57a14a3..f42eeff 100644
--- a/drivers/misc/fs_loader.c
+++ b/drivers/misc/fs_loader.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2018 Intel Corporation <www.intel.com>
+ * Copyright (C) 2018-2019 Intel Corporation <www.intel.com>
*
*/
#include <common.h>
@@ -219,32 +219,26 @@
static int fs_loader_ofdata_to_platdata(struct udevice *dev)
{
- const char *fs_loader_path;
u32 phandlepart[2];
- fs_loader_path = ofnode_get_chosen_prop("firmware-loader");
+ ofnode fs_loader_node = dev_ofnode(dev);
- if (fs_loader_path) {
- ofnode fs_loader_node;
+ if (ofnode_valid(fs_loader_node)) {
+ struct device_platdata *plat;
- fs_loader_node = ofnode_path(fs_loader_path);
- if (ofnode_valid(fs_loader_node)) {
- struct device_platdata *plat;
- plat = dev->platdata;
-
- if (!ofnode_read_u32_array(fs_loader_node,
- "phandlepart",
- phandlepart, 2)) {
- plat->phandlepart.phandle = phandlepart[0];
- plat->phandlepart.partition = phandlepart[1];
- }
+ plat = dev->platdata;
+ if (!ofnode_read_u32_array(fs_loader_node,
+ "phandlepart",
+ phandlepart, 2)) {
+ plat->phandlepart.phandle = phandlepart[0];
+ plat->phandlepart.partition = phandlepart[1];
+ }
- plat->mtdpart = (char *)ofnode_read_string(
- fs_loader_node, "mtdpart");
+ plat->mtdpart = (char *)ofnode_read_string(
+ fs_loader_node, "mtdpart");
- plat->ubivol = (char *)ofnode_read_string(
- fs_loader_node, "ubivol");
- }
+ plat->ubivol = (char *)ofnode_read_string(
+ fs_loader_node, "ubivol");
}
return 0;
@@ -252,6 +246,29 @@
static int fs_loader_probe(struct udevice *dev)
{
+#if CONFIG_IS_ENABLED(DM) && CONFIG_IS_ENABLED(BLK)
+ int ret;
+ struct device_platdata *plat = dev->platdata;
+
+ if (plat->phandlepart.phandle) {
+ ofnode node = ofnode_get_by_phandle(plat->phandlepart.phandle);
+ struct udevice *parent_dev = NULL;
+
+ ret = device_get_global_by_ofnode(node, &parent_dev);
+ if (!ret) {
+ struct udevice *dev;
+
+ ret = blk_get_from_parent(parent_dev, &dev);
+ if (ret) {
+ debug("fs_loader: No block device: %d\n",
+ ret);
+
+ return ret;
+ }
+ }
+ }
+#endif
+
return 0;
};
diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c
index d3f0778..e0ac3e9 100644
--- a/drivers/mmc/mtk-sd.c
+++ b/drivers/mmc/mtk-sd.c
@@ -247,6 +247,7 @@
struct msdc_compatible *dev_comp;
struct clk src_clk; /* for SD/MMC bus clock */
+ struct clk src_clk_cg; /* optional, MSDC source clock control gate */
struct clk h_clk; /* MSDC core clock */
u32 src_clk_freq; /* source clock */
@@ -269,7 +270,7 @@
bool builtin_cd;
/* card detection / write protection GPIOs */
-#if IS_ENABLED(DM_GPIO)
+#if CONFIG_IS_ENABLED(DM_GPIO)
struct gpio_desc gpio_wp;
struct gpio_desc gpio_cd;
#endif
@@ -849,7 +850,7 @@
return !(val & MSDC_PS_CDSTS);
}
-#if IS_ENABLED(DM_GPIO)
+#if CONFIG_IS_ENABLED(DM_GPIO)
if (!host->gpio_cd.dev)
return 1;
@@ -861,7 +862,7 @@
static int msdc_ops_get_wp(struct udevice *dev)
{
-#if IS_ENABLED(DM_GPIO)
+#if CONFIG_IS_ENABLED(DM_GPIO)
struct msdc_host *host = dev_get_priv(dev);
if (!host->gpio_wp.dev)
@@ -1269,6 +1270,8 @@
{
clk_enable(&host->src_clk);
clk_enable(&host->h_clk);
+ if (host->src_clk_cg.dev)
+ clk_enable(&host->src_clk_cg);
}
static int msdc_drv_probe(struct udevice *dev)
@@ -1332,7 +1335,9 @@
if (ret < 0)
return ret;
-#if IS_ENABLED(DM_GPIO)
+ clk_get_by_name(dev, "source_cg", &host->src_clk_cg); /* optional */
+
+#if CONFIG_IS_ENABLED(DM_GPIO)
gpio_request_by_name(dev, "wp-gpios", 0, &host->gpio_wp, GPIOD_IS_IN);
gpio_request_by_name(dev, "cd-gpios", 0, &host->gpio_cd, GPIOD_IS_IN);
#endif
@@ -1376,8 +1381,18 @@
.enhance_rx = false
};
+static const struct msdc_compatible mt8516_compat = {
+ .clk_div_bits = 12,
+ .pad_tune0 = true,
+ .async_fifo = true,
+ .data_tune = true,
+ .busy_check = true,
+ .stop_clk_fix = true,
+};
+
static const struct udevice_id msdc_ids[] = {
{ .compatible = "mediatek,mt7623-mmc", .data = (ulong)&mt7623_compat },
+ { .compatible = "mediatek,mt8516-mmc", .data = (ulong)&mt8516_compat },
{}
};
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index dc087ab..f86035b 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -60,6 +60,31 @@
endif
+config NAND_BRCMNAND
+ bool "Support Broadcom NAND controller"
+ depends on OF_CONTROL && DM && MTD
+ help
+ Enable the driver for NAND flash on platforms using a Broadcom NAND
+ controller.
+
+config NAND_BRCMNAND_6838
+ bool "Support Broadcom NAND controller on bcm6838"
+ depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838
+ help
+ Enable support for broadcom nand driver on bcm6838.
+
+config NAND_BRCMNAND_6858
+ bool "Support Broadcom NAND controller on bcm6858"
+ depends on NAND_BRCMNAND && ARCH_BCM6858
+ help
+ Enable support for broadcom nand driver on bcm6858.
+
+config NAND_BRCMNAND_63158
+ bool "Support Broadcom NAND controller on bcm63158"
+ depends on NAND_BRCMNAND && ARCH_BCM63158
+ help
+ Enable support for broadcom nand driver on bcm63158.
+
config NAND_DAVINCI
bool "Support TI Davinci NAND controller"
help
diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
index b10e718..9337f64 100644
--- a/drivers/mtd/nand/raw/Makefile
+++ b/drivers/mtd/nand/raw/Makefile
@@ -41,6 +41,7 @@
obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o
obj-$(CONFIG_NAND_ARASAN) += arasan_nfc.o
+obj-$(CONFIG_NAND_BRCMNAND) += brcmnand/
obj-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
obj-$(CONFIG_NAND_DENALI) += denali.o
obj-$(CONFIG_NAND_DENALI_DT) += denali_dt.o
diff --git a/drivers/mtd/nand/raw/brcmnand/Makefile b/drivers/mtd/nand/raw/brcmnand/Makefile
new file mode 100644
index 0000000..a2363cc
--- /dev/null
+++ b/drivers/mtd/nand/raw/brcmnand/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-$(CONFIG_NAND_BRCMNAND_63158) += bcm63158_nand.o
+obj-$(CONFIG_NAND_BRCMNAND_6838) += bcm6838_nand.o
+obj-$(CONFIG_NAND_BRCMNAND_6858) += bcm6858_nand.o
+obj-$(CONFIG_NAND_BRCMNAND) += brcmnand.o
+obj-$(CONFIG_NAND_BRCMNAND) += brcmnand_compat.o
diff --git a/drivers/mtd/nand/raw/brcmnand/bcm63158_nand.c b/drivers/mtd/nand/raw/brcmnand/bcm63158_nand.c
new file mode 100644
index 0000000..16b0d44
--- /dev/null
+++ b/drivers/mtd/nand/raw/brcmnand/bcm63158_nand.c
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <asm/io.h>
+#include <memalign.h>
+#include <nand.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <dm.h>
+
+#include "brcmnand.h"
+
+struct bcm63158_nand_soc {
+ struct brcmnand_soc soc;
+ void __iomem *base;
+};
+
+#define BCM63158_NAND_INT 0x00
+#define BCM63158_NAND_STATUS_SHIFT 0
+#define BCM63158_NAND_STATUS_MASK (0xfff << BCM63158_NAND_STATUS_SHIFT)
+
+#define BCM63158_NAND_INT_EN 0x04
+#define BCM63158_NAND_ENABLE_SHIFT 0
+#define BCM63158_NAND_ENABLE_MASK (0xffff << BCM63158_NAND_ENABLE_SHIFT)
+
+enum {
+ BCM63158_NP_READ = BIT(0),
+ BCM63158_BLOCK_ERASE = BIT(1),
+ BCM63158_COPY_BACK = BIT(2),
+ BCM63158_PAGE_PGM = BIT(3),
+ BCM63158_CTRL_READY = BIT(4),
+ BCM63158_DEV_RBPIN = BIT(5),
+ BCM63158_ECC_ERR_UNC = BIT(6),
+ BCM63158_ECC_ERR_CORR = BIT(7),
+};
+
+static bool bcm63158_nand_intc_ack(struct brcmnand_soc *soc)
+{
+ struct bcm63158_nand_soc *priv =
+ container_of(soc, struct bcm63158_nand_soc, soc);
+ void __iomem *mmio = priv->base + BCM63158_NAND_INT;
+ u32 val = brcmnand_readl(mmio);
+
+ if (val & (BCM63158_CTRL_READY << BCM63158_NAND_STATUS_SHIFT)) {
+ /* Ack interrupt */
+ val &= ~BCM63158_NAND_STATUS_MASK;
+ val |= BCM63158_CTRL_READY << BCM63158_NAND_STATUS_SHIFT;
+ brcmnand_writel(val, mmio);
+ return true;
+ }
+
+ return false;
+}
+
+static void bcm63158_nand_intc_set(struct brcmnand_soc *soc, bool en)
+{
+ struct bcm63158_nand_soc *priv =
+ container_of(soc, struct bcm63158_nand_soc, soc);
+ void __iomem *mmio = priv->base + BCM63158_NAND_INT_EN;
+ u32 val = brcmnand_readl(mmio);
+
+ /* Don't ack any interrupts */
+ val &= ~BCM63158_NAND_STATUS_MASK;
+
+ if (en)
+ val |= BCM63158_CTRL_READY << BCM63158_NAND_ENABLE_SHIFT;
+ else
+ val &= ~(BCM63158_CTRL_READY << BCM63158_NAND_ENABLE_SHIFT);
+
+ brcmnand_writel(val, mmio);
+}
+
+static int bcm63158_nand_probe(struct udevice *dev)
+{
+ struct udevice *pdev = dev;
+ struct bcm63158_nand_soc *priv = dev_get_priv(dev);
+ struct brcmnand_soc *soc;
+ struct resource res;
+
+ soc = &priv->soc;
+
+ dev_read_resource_byname(pdev, "nand-int-base", &res);
+ priv->base = devm_ioremap(dev, res.start, resource_size(&res));
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ soc->ctlrdy_ack = bcm63158_nand_intc_ack;
+ soc->ctlrdy_set_enabled = bcm63158_nand_intc_set;
+
+ /* Disable and ack all interrupts */
+ brcmnand_writel(0, priv->base + BCM63158_NAND_INT_EN);
+ brcmnand_writel(0, priv->base + BCM63158_NAND_INT);
+
+ return brcmnand_probe(pdev, soc);
+}
+
+static const struct udevice_id bcm63158_nand_dt_ids[] = {
+ {
+ .compatible = "brcm,nand-bcm63158",
+ },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(bcm63158_nand) = {
+ .name = "bcm63158-nand",
+ .id = UCLASS_MTD,
+ .of_match = bcm63158_nand_dt_ids,
+ .probe = bcm63158_nand_probe,
+ .priv_auto_alloc_size = sizeof(struct bcm63158_nand_soc),
+};
+
+void board_nand_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MTD,
+ DM_GET_DRIVER(bcm63158_nand), &dev);
+ if (ret && ret != -ENODEV)
+ pr_err("Failed to initialize %s. (error %d)\n", dev->name,
+ ret);
+}
diff --git a/drivers/mtd/nand/raw/brcmnand/bcm6838_nand.c b/drivers/mtd/nand/raw/brcmnand/bcm6838_nand.c
new file mode 100644
index 0000000..ece9444
--- /dev/null
+++ b/drivers/mtd/nand/raw/brcmnand/bcm6838_nand.c
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <asm/io.h>
+#include <memalign.h>
+#include <nand.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <dm.h>
+
+#include "brcmnand.h"
+
+struct bcm6838_nand_soc {
+ struct brcmnand_soc soc;
+ void __iomem *base;
+};
+
+#define BCM6838_NAND_INT 0x00
+#define BCM6838_NAND_STATUS_SHIFT 0
+#define BCM6838_NAND_STATUS_MASK (0xfff << BCM6838_NAND_STATUS_SHIFT)
+#define BCM6838_NAND_ENABLE_SHIFT 16
+#define BCM6838_NAND_ENABLE_MASK (0xffff << BCM6838_NAND_ENABLE_SHIFT)
+
+enum {
+ BCM6838_NP_READ = BIT(0),
+ BCM6838_BLOCK_ERASE = BIT(1),
+ BCM6838_COPY_BACK = BIT(2),
+ BCM6838_PAGE_PGM = BIT(3),
+ BCM6838_CTRL_READY = BIT(4),
+ BCM6838_DEV_RBPIN = BIT(5),
+ BCM6838_ECC_ERR_UNC = BIT(6),
+ BCM6838_ECC_ERR_CORR = BIT(7),
+};
+
+static bool bcm6838_nand_intc_ack(struct brcmnand_soc *soc)
+{
+ struct bcm6838_nand_soc *priv =
+ container_of(soc, struct bcm6838_nand_soc, soc);
+ void __iomem *mmio = priv->base + BCM6838_NAND_INT;
+ u32 val = brcmnand_readl(mmio);
+
+ if (val & (BCM6838_CTRL_READY << BCM6838_NAND_STATUS_SHIFT)) {
+ /* Ack interrupt */
+ val &= ~BCM6838_NAND_STATUS_MASK;
+ val |= BCM6838_CTRL_READY << BCM6838_NAND_STATUS_SHIFT;
+ brcmnand_writel(val, mmio);
+ return true;
+ }
+
+ return false;
+}
+
+static void bcm6838_nand_intc_set(struct brcmnand_soc *soc, bool en)
+{
+ struct bcm6838_nand_soc *priv =
+ container_of(soc, struct bcm6838_nand_soc, soc);
+ void __iomem *mmio = priv->base + BCM6838_NAND_INT;
+ u32 val = brcmnand_readl(mmio);
+
+ /* Don't ack any interrupts */
+ val &= ~BCM6838_NAND_STATUS_MASK;
+
+ if (en)
+ val |= BCM6838_CTRL_READY << BCM6838_NAND_ENABLE_SHIFT;
+ else
+ val &= ~(BCM6838_CTRL_READY << BCM6838_NAND_ENABLE_SHIFT);
+
+ brcmnand_writel(val, mmio);
+}
+
+static int bcm6838_nand_probe(struct udevice *dev)
+{
+ struct udevice *pdev = dev;
+ struct bcm6838_nand_soc *priv = dev_get_priv(dev);
+ struct brcmnand_soc *soc;
+ struct resource res;
+
+ soc = &priv->soc;
+
+ dev_read_resource_byname(pdev, "nand-int-base", &res);
+ priv->base = ioremap(res.start, resource_size(&res));
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ soc->ctlrdy_ack = bcm6838_nand_intc_ack;
+ soc->ctlrdy_set_enabled = bcm6838_nand_intc_set;
+
+ /* Disable and ack all interrupts */
+ brcmnand_writel(0, priv->base + BCM6838_NAND_INT);
+ brcmnand_writel(BCM6838_NAND_STATUS_MASK,
+ priv->base + BCM6838_NAND_INT);
+
+ return brcmnand_probe(pdev, soc);
+}
+
+static const struct udevice_id bcm6838_nand_dt_ids[] = {
+ {
+ .compatible = "brcm,nand-bcm6838",
+ },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(bcm6838_nand) = {
+ .name = "bcm6838-nand",
+ .id = UCLASS_MTD,
+ .of_match = bcm6838_nand_dt_ids,
+ .probe = bcm6838_nand_probe,
+ .priv_auto_alloc_size = sizeof(struct bcm6838_nand_soc),
+};
+
+void board_nand_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MTD,
+ DM_GET_DRIVER(bcm6838_nand), &dev);
+ if (ret && ret != -ENODEV)
+ pr_err("Failed to initialize %s. (error %d)\n", dev->name,
+ ret);
+}
diff --git a/drivers/mtd/nand/raw/brcmnand/bcm6858_nand.c b/drivers/mtd/nand/raw/brcmnand/bcm6858_nand.c
new file mode 100644
index 0000000..3586baa
--- /dev/null
+++ b/drivers/mtd/nand/raw/brcmnand/bcm6858_nand.c
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <asm/io.h>
+#include <memalign.h>
+#include <nand.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <dm.h>
+
+#include "brcmnand.h"
+
+struct bcm6858_nand_soc {
+ struct brcmnand_soc soc;
+ void __iomem *base;
+};
+
+#define BCM6858_NAND_INT 0x00
+#define BCM6858_NAND_STATUS_SHIFT 0
+#define BCM6858_NAND_STATUS_MASK (0xfff << BCM6858_NAND_STATUS_SHIFT)
+
+#define BCM6858_NAND_INT_EN 0x04
+#define BCM6858_NAND_ENABLE_SHIFT 0
+#define BCM6858_NAND_ENABLE_MASK (0xffff << BCM6858_NAND_ENABLE_SHIFT)
+
+enum {
+ BCM6858_NP_READ = BIT(0),
+ BCM6858_BLOCK_ERASE = BIT(1),
+ BCM6858_COPY_BACK = BIT(2),
+ BCM6858_PAGE_PGM = BIT(3),
+ BCM6858_CTRL_READY = BIT(4),
+ BCM6858_DEV_RBPIN = BIT(5),
+ BCM6858_ECC_ERR_UNC = BIT(6),
+ BCM6858_ECC_ERR_CORR = BIT(7),
+};
+
+static bool bcm6858_nand_intc_ack(struct brcmnand_soc *soc)
+{
+ struct bcm6858_nand_soc *priv =
+ container_of(soc, struct bcm6858_nand_soc, soc);
+ void __iomem *mmio = priv->base + BCM6858_NAND_INT;
+ u32 val = brcmnand_readl(mmio);
+
+ if (val & (BCM6858_CTRL_READY << BCM6858_NAND_STATUS_SHIFT)) {
+ /* Ack interrupt */
+ val &= ~BCM6858_NAND_STATUS_MASK;
+ val |= BCM6858_CTRL_READY << BCM6858_NAND_STATUS_SHIFT;
+ brcmnand_writel(val, mmio);
+ return true;
+ }
+
+ return false;
+}
+
+static void bcm6858_nand_intc_set(struct brcmnand_soc *soc, bool en)
+{
+ struct bcm6858_nand_soc *priv =
+ container_of(soc, struct bcm6858_nand_soc, soc);
+ void __iomem *mmio = priv->base + BCM6858_NAND_INT_EN;
+ u32 val = brcmnand_readl(mmio);
+
+ /* Don't ack any interrupts */
+ val &= ~BCM6858_NAND_STATUS_MASK;
+
+ if (en)
+ val |= BCM6858_CTRL_READY << BCM6858_NAND_ENABLE_SHIFT;
+ else
+ val &= ~(BCM6858_CTRL_READY << BCM6858_NAND_ENABLE_SHIFT);
+
+ brcmnand_writel(val, mmio);
+}
+
+static int bcm6858_nand_probe(struct udevice *dev)
+{
+ struct udevice *pdev = dev;
+ struct bcm6858_nand_soc *priv = dev_get_priv(dev);
+ struct brcmnand_soc *soc;
+ struct resource res;
+
+ soc = &priv->soc;
+
+ dev_read_resource_byname(pdev, "nand-int-base", &res);
+ priv->base = devm_ioremap(dev, res.start, resource_size(&res));
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ soc->ctlrdy_ack = bcm6858_nand_intc_ack;
+ soc->ctlrdy_set_enabled = bcm6858_nand_intc_set;
+
+ /* Disable and ack all interrupts */
+ brcmnand_writel(0, priv->base + BCM6858_NAND_INT_EN);
+ brcmnand_writel(0, priv->base + BCM6858_NAND_INT);
+
+ return brcmnand_probe(pdev, soc);
+}
+
+static const struct udevice_id bcm6858_nand_dt_ids[] = {
+ {
+ .compatible = "brcm,nand-bcm6858",
+ },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(bcm6858_nand) = {
+ .name = "bcm6858-nand",
+ .id = UCLASS_MTD,
+ .of_match = bcm6858_nand_dt_ids,
+ .probe = bcm6858_nand_probe,
+ .priv_auto_alloc_size = sizeof(struct bcm6858_nand_soc),
+};
+
+void board_nand_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MTD,
+ DM_GET_DRIVER(bcm6858_nand), &dev);
+ if (ret && ret != -ENODEV)
+ pr_err("Failed to initialize %s. (error %d)\n", dev->name,
+ ret);
+}
diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
new file mode 100644
index 0000000..faa6da4
--- /dev/null
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
@@ -0,0 +1,2805 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright © 2010-2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <memalign.h>
+#include <nand.h>
+#include <clk.h>
+#include <linux/ioport.h>
+#include <linux/completion.h>
+#include <linux/errno.h>
+#include <linux/log2.h>
+#include <asm/processor.h>
+#include <dm.h>
+
+#include "brcmnand.h"
+#include "brcmnand_compat.h"
+
+/*
+ * This flag controls if WP stays on between erase/write commands to mitigate
+ * flash corruption due to power glitches. Values:
+ * 0: NAND_WP is not used or not available
+ * 1: NAND_WP is set by default, cleared for erase/write operations
+ * 2: NAND_WP is always cleared
+ */
+static int wp_on = 1;
+module_param(wp_on, int, 0444);
+
+/***********************************************************************
+ * Definitions
+ ***********************************************************************/
+
+#define DRV_NAME "brcmnand"
+
+#define CMD_NULL 0x00
+#define CMD_PAGE_READ 0x01
+#define CMD_SPARE_AREA_READ 0x02
+#define CMD_STATUS_READ 0x03
+#define CMD_PROGRAM_PAGE 0x04
+#define CMD_PROGRAM_SPARE_AREA 0x05
+#define CMD_COPY_BACK 0x06
+#define CMD_DEVICE_ID_READ 0x07
+#define CMD_BLOCK_ERASE 0x08
+#define CMD_FLASH_RESET 0x09
+#define CMD_BLOCKS_LOCK 0x0a
+#define CMD_BLOCKS_LOCK_DOWN 0x0b
+#define CMD_BLOCKS_UNLOCK 0x0c
+#define CMD_READ_BLOCKS_LOCK_STATUS 0x0d
+#define CMD_PARAMETER_READ 0x0e
+#define CMD_PARAMETER_CHANGE_COL 0x0f
+#define CMD_LOW_LEVEL_OP 0x10
+
+struct brcm_nand_dma_desc {
+ u32 next_desc;
+ u32 next_desc_ext;
+ u32 cmd_irq;
+ u32 dram_addr;
+ u32 dram_addr_ext;
+ u32 tfr_len;
+ u32 total_len;
+ u32 flash_addr;
+ u32 flash_addr_ext;
+ u32 cs;
+ u32 pad2[5];
+ u32 status_valid;
+} __packed;
+
+/* Bitfields for brcm_nand_dma_desc::status_valid */
+#define FLASH_DMA_ECC_ERROR (1 << 8)
+#define FLASH_DMA_CORR_ERROR (1 << 9)
+
+/* 512B flash cache in the NAND controller HW */
+#define FC_SHIFT 9U
+#define FC_BYTES 512U
+#define FC_WORDS (FC_BYTES >> 2)
+
+#define BRCMNAND_MIN_PAGESIZE 512
+#define BRCMNAND_MIN_BLOCKSIZE (8 * 1024)
+#define BRCMNAND_MIN_DEVSIZE (4ULL * 1024 * 1024)
+
+#define NAND_CTRL_RDY (INTFC_CTLR_READY | INTFC_FLASH_READY)
+#define NAND_POLL_STATUS_TIMEOUT_MS 100
+
+/* Controller feature flags */
+enum {
+ BRCMNAND_HAS_1K_SECTORS = BIT(0),
+ BRCMNAND_HAS_PREFETCH = BIT(1),
+ BRCMNAND_HAS_CACHE_MODE = BIT(2),
+ BRCMNAND_HAS_WP = BIT(3),
+};
+
+struct brcmnand_controller {
+#ifndef __UBOOT__
+ struct device *dev;
+#else
+ struct udevice *dev;
+#endif /* __UBOOT__ */
+ struct nand_hw_control controller;
+ void __iomem *nand_base;
+ void __iomem *nand_fc; /* flash cache */
+ void __iomem *flash_dma_base;
+ unsigned int irq;
+ unsigned int dma_irq;
+ int nand_version;
+ int parameter_page_big_endian;
+
+ /* Some SoCs provide custom interrupt status register(s) */
+ struct brcmnand_soc *soc;
+
+ /* Some SoCs have a gateable clock for the controller */
+ struct clk *clk;
+
+ int cmd_pending;
+ bool dma_pending;
+ struct completion done;
+ struct completion dma_done;
+
+ /* List of NAND hosts (one for each chip-select) */
+ struct list_head host_list;
+
+ struct brcm_nand_dma_desc *dma_desc;
+ dma_addr_t dma_pa;
+
+ /* in-memory cache of the FLASH_CACHE, used only for some commands */
+ u8 flash_cache[FC_BYTES];
+
+ /* Controller revision details */
+ const u16 *reg_offsets;
+ unsigned int reg_spacing; /* between CS1, CS2, ... regs */
+ const u8 *cs_offsets; /* within each chip-select */
+ const u8 *cs0_offsets; /* within CS0, if different */
+ unsigned int max_block_size;
+ const unsigned int *block_sizes;
+ unsigned int max_page_size;
+ const unsigned int *page_sizes;
+ unsigned int max_oob;
+ u32 features;
+
+ /* for low-power standby/resume only */
+ u32 nand_cs_nand_select;
+ u32 nand_cs_nand_xor;
+ u32 corr_stat_threshold;
+ u32 flash_dma_mode;
+};
+
+struct brcmnand_cfg {
+ u64 device_size;
+ unsigned int block_size;
+ unsigned int page_size;
+ unsigned int spare_area_size;
+ unsigned int device_width;
+ unsigned int col_adr_bytes;
+ unsigned int blk_adr_bytes;
+ unsigned int ful_adr_bytes;
+ unsigned int sector_size_1k;
+ unsigned int ecc_level;
+ /* use for low-power standby/resume only */
+ u32 acc_control;
+ u32 config;
+ u32 config_ext;
+ u32 timing_1;
+ u32 timing_2;
+};
+
+struct brcmnand_host {
+ struct list_head node;
+
+ struct nand_chip chip;
+#ifndef __UBOOT__
+ struct platform_device *pdev;
+#else
+ struct udevice *pdev;
+#endif /* __UBOOT__ */
+ int cs;
+
+ unsigned int last_cmd;
+ unsigned int last_byte;
+ u64 last_addr;
+ struct brcmnand_cfg hwcfg;
+ struct brcmnand_controller *ctrl;
+};
+
+enum brcmnand_reg {
+ BRCMNAND_CMD_START = 0,
+ BRCMNAND_CMD_EXT_ADDRESS,
+ BRCMNAND_CMD_ADDRESS,
+ BRCMNAND_INTFC_STATUS,
+ BRCMNAND_CS_SELECT,
+ BRCMNAND_CS_XOR,
+ BRCMNAND_LL_OP,
+ BRCMNAND_CS0_BASE,
+ BRCMNAND_CS1_BASE, /* CS1 regs, if non-contiguous */
+ BRCMNAND_CORR_THRESHOLD,
+ BRCMNAND_CORR_THRESHOLD_EXT,
+ BRCMNAND_UNCORR_COUNT,
+ BRCMNAND_CORR_COUNT,
+ BRCMNAND_CORR_EXT_ADDR,
+ BRCMNAND_CORR_ADDR,
+ BRCMNAND_UNCORR_EXT_ADDR,
+ BRCMNAND_UNCORR_ADDR,
+ BRCMNAND_SEMAPHORE,
+ BRCMNAND_ID,
+ BRCMNAND_ID_EXT,
+ BRCMNAND_LL_RDATA,
+ BRCMNAND_OOB_READ_BASE,
+ BRCMNAND_OOB_READ_10_BASE, /* offset 0x10, if non-contiguous */
+ BRCMNAND_OOB_WRITE_BASE,
+ BRCMNAND_OOB_WRITE_10_BASE, /* offset 0x10, if non-contiguous */
+ BRCMNAND_FC_BASE,
+};
+
+/* BRCMNAND v4.0 */
+static const u16 brcmnand_regs_v40[] = {
+ [BRCMNAND_CMD_START] = 0x04,
+ [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
+ [BRCMNAND_CMD_ADDRESS] = 0x0c,
+ [BRCMNAND_INTFC_STATUS] = 0x6c,
+ [BRCMNAND_CS_SELECT] = 0x14,
+ [BRCMNAND_CS_XOR] = 0x18,
+ [BRCMNAND_LL_OP] = 0x178,
+ [BRCMNAND_CS0_BASE] = 0x40,
+ [BRCMNAND_CS1_BASE] = 0xd0,
+ [BRCMNAND_CORR_THRESHOLD] = 0x84,
+ [BRCMNAND_CORR_THRESHOLD_EXT] = 0,
+ [BRCMNAND_UNCORR_COUNT] = 0,
+ [BRCMNAND_CORR_COUNT] = 0,
+ [BRCMNAND_CORR_EXT_ADDR] = 0x70,
+ [BRCMNAND_CORR_ADDR] = 0x74,
+ [BRCMNAND_UNCORR_EXT_ADDR] = 0x78,
+ [BRCMNAND_UNCORR_ADDR] = 0x7c,
+ [BRCMNAND_SEMAPHORE] = 0x58,
+ [BRCMNAND_ID] = 0x60,
+ [BRCMNAND_ID_EXT] = 0x64,
+ [BRCMNAND_LL_RDATA] = 0x17c,
+ [BRCMNAND_OOB_READ_BASE] = 0x20,
+ [BRCMNAND_OOB_READ_10_BASE] = 0x130,
+ [BRCMNAND_OOB_WRITE_BASE] = 0x30,
+ [BRCMNAND_OOB_WRITE_10_BASE] = 0,
+ [BRCMNAND_FC_BASE] = 0x200,
+};
+
+/* BRCMNAND v5.0 */
+static const u16 brcmnand_regs_v50[] = {
+ [BRCMNAND_CMD_START] = 0x04,
+ [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
+ [BRCMNAND_CMD_ADDRESS] = 0x0c,
+ [BRCMNAND_INTFC_STATUS] = 0x6c,
+ [BRCMNAND_CS_SELECT] = 0x14,
+ [BRCMNAND_CS_XOR] = 0x18,
+ [BRCMNAND_LL_OP] = 0x178,
+ [BRCMNAND_CS0_BASE] = 0x40,
+ [BRCMNAND_CS1_BASE] = 0xd0,
+ [BRCMNAND_CORR_THRESHOLD] = 0x84,
+ [BRCMNAND_CORR_THRESHOLD_EXT] = 0,
+ [BRCMNAND_UNCORR_COUNT] = 0,
+ [BRCMNAND_CORR_COUNT] = 0,
+ [BRCMNAND_CORR_EXT_ADDR] = 0x70,
+ [BRCMNAND_CORR_ADDR] = 0x74,
+ [BRCMNAND_UNCORR_EXT_ADDR] = 0x78,
+ [BRCMNAND_UNCORR_ADDR] = 0x7c,
+ [BRCMNAND_SEMAPHORE] = 0x58,
+ [BRCMNAND_ID] = 0x60,
+ [BRCMNAND_ID_EXT] = 0x64,
+ [BRCMNAND_LL_RDATA] = 0x17c,
+ [BRCMNAND_OOB_READ_BASE] = 0x20,
+ [BRCMNAND_OOB_READ_10_BASE] = 0x130,
+ [BRCMNAND_OOB_WRITE_BASE] = 0x30,
+ [BRCMNAND_OOB_WRITE_10_BASE] = 0x140,
+ [BRCMNAND_FC_BASE] = 0x200,
+};
+
+/* BRCMNAND v6.0 - v7.1 */
+static const u16 brcmnand_regs_v60[] = {
+ [BRCMNAND_CMD_START] = 0x04,
+ [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
+ [BRCMNAND_CMD_ADDRESS] = 0x0c,
+ [BRCMNAND_INTFC_STATUS] = 0x14,
+ [BRCMNAND_CS_SELECT] = 0x18,
+ [BRCMNAND_CS_XOR] = 0x1c,
+ [BRCMNAND_LL_OP] = 0x20,
+ [BRCMNAND_CS0_BASE] = 0x50,
+ [BRCMNAND_CS1_BASE] = 0,
+ [BRCMNAND_CORR_THRESHOLD] = 0xc0,
+ [BRCMNAND_CORR_THRESHOLD_EXT] = 0xc4,
+ [BRCMNAND_UNCORR_COUNT] = 0xfc,
+ [BRCMNAND_CORR_COUNT] = 0x100,
+ [BRCMNAND_CORR_EXT_ADDR] = 0x10c,
+ [BRCMNAND_CORR_ADDR] = 0x110,
+ [BRCMNAND_UNCORR_EXT_ADDR] = 0x114,
+ [BRCMNAND_UNCORR_ADDR] = 0x118,
+ [BRCMNAND_SEMAPHORE] = 0x150,
+ [BRCMNAND_ID] = 0x194,
+ [BRCMNAND_ID_EXT] = 0x198,
+ [BRCMNAND_LL_RDATA] = 0x19c,
+ [BRCMNAND_OOB_READ_BASE] = 0x200,
+ [BRCMNAND_OOB_READ_10_BASE] = 0,
+ [BRCMNAND_OOB_WRITE_BASE] = 0x280,
+ [BRCMNAND_OOB_WRITE_10_BASE] = 0,
+ [BRCMNAND_FC_BASE] = 0x400,
+};
+
+/* BRCMNAND v7.1 */
+static const u16 brcmnand_regs_v71[] = {
+ [BRCMNAND_CMD_START] = 0x04,
+ [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
+ [BRCMNAND_CMD_ADDRESS] = 0x0c,
+ [BRCMNAND_INTFC_STATUS] = 0x14,
+ [BRCMNAND_CS_SELECT] = 0x18,
+ [BRCMNAND_CS_XOR] = 0x1c,
+ [BRCMNAND_LL_OP] = 0x20,
+ [BRCMNAND_CS0_BASE] = 0x50,
+ [BRCMNAND_CS1_BASE] = 0,
+ [BRCMNAND_CORR_THRESHOLD] = 0xdc,
+ [BRCMNAND_CORR_THRESHOLD_EXT] = 0xe0,
+ [BRCMNAND_UNCORR_COUNT] = 0xfc,
+ [BRCMNAND_CORR_COUNT] = 0x100,
+ [BRCMNAND_CORR_EXT_ADDR] = 0x10c,
+ [BRCMNAND_CORR_ADDR] = 0x110,
+ [BRCMNAND_UNCORR_EXT_ADDR] = 0x114,
+ [BRCMNAND_UNCORR_ADDR] = 0x118,
+ [BRCMNAND_SEMAPHORE] = 0x150,
+ [BRCMNAND_ID] = 0x194,
+ [BRCMNAND_ID_EXT] = 0x198,
+ [BRCMNAND_LL_RDATA] = 0x19c,
+ [BRCMNAND_OOB_READ_BASE] = 0x200,
+ [BRCMNAND_OOB_READ_10_BASE] = 0,
+ [BRCMNAND_OOB_WRITE_BASE] = 0x280,
+ [BRCMNAND_OOB_WRITE_10_BASE] = 0,
+ [BRCMNAND_FC_BASE] = 0x400,
+};
+
+/* BRCMNAND v7.2 */
+static const u16 brcmnand_regs_v72[] = {
+ [BRCMNAND_CMD_START] = 0x04,
+ [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
+ [BRCMNAND_CMD_ADDRESS] = 0x0c,
+ [BRCMNAND_INTFC_STATUS] = 0x14,
+ [BRCMNAND_CS_SELECT] = 0x18,
+ [BRCMNAND_CS_XOR] = 0x1c,
+ [BRCMNAND_LL_OP] = 0x20,
+ [BRCMNAND_CS0_BASE] = 0x50,
+ [BRCMNAND_CS1_BASE] = 0,
+ [BRCMNAND_CORR_THRESHOLD] = 0xdc,
+ [BRCMNAND_CORR_THRESHOLD_EXT] = 0xe0,
+ [BRCMNAND_UNCORR_COUNT] = 0xfc,
+ [BRCMNAND_CORR_COUNT] = 0x100,
+ [BRCMNAND_CORR_EXT_ADDR] = 0x10c,
+ [BRCMNAND_CORR_ADDR] = 0x110,
+ [BRCMNAND_UNCORR_EXT_ADDR] = 0x114,
+ [BRCMNAND_UNCORR_ADDR] = 0x118,
+ [BRCMNAND_SEMAPHORE] = 0x150,
+ [BRCMNAND_ID] = 0x194,
+ [BRCMNAND_ID_EXT] = 0x198,
+ [BRCMNAND_LL_RDATA] = 0x19c,
+ [BRCMNAND_OOB_READ_BASE] = 0x200,
+ [BRCMNAND_OOB_READ_10_BASE] = 0,
+ [BRCMNAND_OOB_WRITE_BASE] = 0x400,
+ [BRCMNAND_OOB_WRITE_10_BASE] = 0,
+ [BRCMNAND_FC_BASE] = 0x600,
+};
+
+enum brcmnand_cs_reg {
+ BRCMNAND_CS_CFG_EXT = 0,
+ BRCMNAND_CS_CFG,
+ BRCMNAND_CS_ACC_CONTROL,
+ BRCMNAND_CS_TIMING1,
+ BRCMNAND_CS_TIMING2,
+};
+
+/* Per chip-select offsets for v7.1 */
+static const u8 brcmnand_cs_offsets_v71[] = {
+ [BRCMNAND_CS_ACC_CONTROL] = 0x00,
+ [BRCMNAND_CS_CFG_EXT] = 0x04,
+ [BRCMNAND_CS_CFG] = 0x08,
+ [BRCMNAND_CS_TIMING1] = 0x0c,
+ [BRCMNAND_CS_TIMING2] = 0x10,
+};
+
+/* Per chip-select offsets for pre v7.1, except CS0 on <= v5.0 */
+static const u8 brcmnand_cs_offsets[] = {
+ [BRCMNAND_CS_ACC_CONTROL] = 0x00,
+ [BRCMNAND_CS_CFG_EXT] = 0x04,
+ [BRCMNAND_CS_CFG] = 0x04,
+ [BRCMNAND_CS_TIMING1] = 0x08,
+ [BRCMNAND_CS_TIMING2] = 0x0c,
+};
+
+/* Per chip-select offset for <= v5.0 on CS0 only */
+static const u8 brcmnand_cs_offsets_cs0[] = {
+ [BRCMNAND_CS_ACC_CONTROL] = 0x00,
+ [BRCMNAND_CS_CFG_EXT] = 0x08,
+ [BRCMNAND_CS_CFG] = 0x08,
+ [BRCMNAND_CS_TIMING1] = 0x10,
+ [BRCMNAND_CS_TIMING2] = 0x14,
+};
+
+/*
+ * Bitfields for the CFG and CFG_EXT registers. Pre-v7.1 controllers only had
+ * one config register, but once the bitfields overflowed, newer controllers
+ * (v7.1 and newer) added a CFG_EXT register and shuffled a few fields around.
+ */
+enum {
+ CFG_BLK_ADR_BYTES_SHIFT = 8,
+ CFG_COL_ADR_BYTES_SHIFT = 12,
+ CFG_FUL_ADR_BYTES_SHIFT = 16,
+ CFG_BUS_WIDTH_SHIFT = 23,
+ CFG_BUS_WIDTH = BIT(CFG_BUS_WIDTH_SHIFT),
+ CFG_DEVICE_SIZE_SHIFT = 24,
+
+ /* Only for pre-v7.1 (with no CFG_EXT register) */
+ CFG_PAGE_SIZE_SHIFT = 20,
+ CFG_BLK_SIZE_SHIFT = 28,
+
+ /* Only for v7.1+ (with CFG_EXT register) */
+ CFG_EXT_PAGE_SIZE_SHIFT = 0,
+ CFG_EXT_BLK_SIZE_SHIFT = 4,
+};
+
+/* BRCMNAND_INTFC_STATUS */
+enum {
+ INTFC_FLASH_STATUS = GENMASK(7, 0),
+
+ INTFC_ERASED = BIT(27),
+ INTFC_OOB_VALID = BIT(28),
+ INTFC_CACHE_VALID = BIT(29),
+ INTFC_FLASH_READY = BIT(30),
+ INTFC_CTLR_READY = BIT(31),
+};
+
+static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs)
+{
+ return brcmnand_readl(ctrl->nand_base + offs);
+}
+
+static inline void nand_writereg(struct brcmnand_controller *ctrl, u32 offs,
+ u32 val)
+{
+ brcmnand_writel(val, ctrl->nand_base + offs);
+}
+
+static int brcmnand_revision_init(struct brcmnand_controller *ctrl)
+{
+ static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 };
+ static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 };
+ static const unsigned int page_sizes[] = { 512, 2048, 4096, 8192, 0 };
+
+ ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff;
+
+ /* Only support v4.0+? */
+ if (ctrl->nand_version < 0x0400) {
+ dev_err(ctrl->dev, "version %#x not supported\n",
+ ctrl->nand_version);
+ return -ENODEV;
+ }
+
+ /* Register offsets */
+ if (ctrl->nand_version >= 0x0702)
+ ctrl->reg_offsets = brcmnand_regs_v72;
+ else if (ctrl->nand_version >= 0x0701)
+ ctrl->reg_offsets = brcmnand_regs_v71;
+ else if (ctrl->nand_version >= 0x0600)
+ ctrl->reg_offsets = brcmnand_regs_v60;
+ else if (ctrl->nand_version >= 0x0500)
+ ctrl->reg_offsets = brcmnand_regs_v50;
+ else if (ctrl->nand_version >= 0x0400)
+ ctrl->reg_offsets = brcmnand_regs_v40;
+
+ /* Chip-select stride */
+ if (ctrl->nand_version >= 0x0701)
+ ctrl->reg_spacing = 0x14;
+ else
+ ctrl->reg_spacing = 0x10;
+
+ /* Per chip-select registers */
+ if (ctrl->nand_version >= 0x0701) {
+ ctrl->cs_offsets = brcmnand_cs_offsets_v71;
+ } else {
+ ctrl->cs_offsets = brcmnand_cs_offsets;
+
+ /* v5.0 and earlier has a different CS0 offset layout */
+ if (ctrl->nand_version <= 0x0500)
+ ctrl->cs0_offsets = brcmnand_cs_offsets_cs0;
+ }
+
+ /* Page / block sizes */
+ if (ctrl->nand_version >= 0x0701) {
+ /* >= v7.1 use nice power-of-2 values! */
+ ctrl->max_page_size = 16 * 1024;
+ ctrl->max_block_size = 2 * 1024 * 1024;
+ } else {
+ ctrl->page_sizes = page_sizes;
+ if (ctrl->nand_version >= 0x0600)
+ ctrl->block_sizes = block_sizes_v6;
+ else
+ ctrl->block_sizes = block_sizes_v4;
+
+ if (ctrl->nand_version < 0x0400) {
+ ctrl->max_page_size = 4096;
+ ctrl->max_block_size = 512 * 1024;
+ }
+ }
+
+ /* Maximum spare area sector size (per 512B) */
+ if (ctrl->nand_version >= 0x0702)
+ ctrl->max_oob = 128;
+ else if (ctrl->nand_version >= 0x0600)
+ ctrl->max_oob = 64;
+ else if (ctrl->nand_version >= 0x0500)
+ ctrl->max_oob = 32;
+ else
+ ctrl->max_oob = 16;
+
+ /* v6.0 and newer (except v6.1) have prefetch support */
+ if (ctrl->nand_version >= 0x0600 && ctrl->nand_version != 0x0601)
+ ctrl->features |= BRCMNAND_HAS_PREFETCH;
+
+ /*
+ * v6.x has cache mode, but it's implemented differently. Ignore it for
+ * now.
+ */
+ if (ctrl->nand_version >= 0x0700)
+ ctrl->features |= BRCMNAND_HAS_CACHE_MODE;
+
+ if (ctrl->nand_version >= 0x0500)
+ ctrl->features |= BRCMNAND_HAS_1K_SECTORS;
+
+ if (ctrl->nand_version >= 0x0700)
+ ctrl->features |= BRCMNAND_HAS_WP;
+#ifndef __UBOOT__
+ else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp"))
+#else
+ else if (dev_read_bool(ctrl->dev, "brcm,nand-has-wp"))
+#endif /* __UBOOT__ */
+ ctrl->features |= BRCMNAND_HAS_WP;
+
+ return 0;
+}
+
+static inline u32 brcmnand_read_reg(struct brcmnand_controller *ctrl,
+ enum brcmnand_reg reg)
+{
+ u16 offs = ctrl->reg_offsets[reg];
+
+ if (offs)
+ return nand_readreg(ctrl, offs);
+ else
+ return 0;
+}
+
+static inline void brcmnand_write_reg(struct brcmnand_controller *ctrl,
+ enum brcmnand_reg reg, u32 val)
+{
+ u16 offs = ctrl->reg_offsets[reg];
+
+ if (offs)
+ nand_writereg(ctrl, offs, val);
+}
+
+static inline void brcmnand_rmw_reg(struct brcmnand_controller *ctrl,
+ enum brcmnand_reg reg, u32 mask, unsigned
+ int shift, u32 val)
+{
+ u32 tmp = brcmnand_read_reg(ctrl, reg);
+
+ tmp &= ~mask;
+ tmp |= val << shift;
+ brcmnand_write_reg(ctrl, reg, tmp);
+}
+
+static inline u32 brcmnand_read_fc(struct brcmnand_controller *ctrl, int word)
+{
+ return __raw_readl(ctrl->nand_fc + word * 4);
+}
+
+static inline void brcmnand_write_fc(struct brcmnand_controller *ctrl,
+ int word, u32 val)
+{
+ __raw_writel(val, ctrl->nand_fc + word * 4);
+}
+
+static inline u16 brcmnand_cs_offset(struct brcmnand_controller *ctrl, int cs,
+ enum brcmnand_cs_reg reg)
+{
+ u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE];
+ u16 offs_cs1 = ctrl->reg_offsets[BRCMNAND_CS1_BASE];
+ u8 cs_offs;
+
+ if (cs == 0 && ctrl->cs0_offsets)
+ cs_offs = ctrl->cs0_offsets[reg];
+ else
+ cs_offs = ctrl->cs_offsets[reg];
+
+ if (cs && offs_cs1)
+ return offs_cs1 + (cs - 1) * ctrl->reg_spacing + cs_offs;
+
+ return offs_cs0 + cs * ctrl->reg_spacing + cs_offs;
+}
+
+static inline u32 brcmnand_count_corrected(struct brcmnand_controller *ctrl)
+{
+ if (ctrl->nand_version < 0x0600)
+ return 1;
+ return brcmnand_read_reg(ctrl, BRCMNAND_CORR_COUNT);
+}
+
+static void brcmnand_wr_corr_thresh(struct brcmnand_host *host, u8 val)
+{
+ struct brcmnand_controller *ctrl = host->ctrl;
+ unsigned int shift = 0, bits;
+ enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD;
+ int cs = host->cs;
+
+ if (ctrl->nand_version >= 0x0702)
+ bits = 7;
+ else if (ctrl->nand_version >= 0x0600)
+ bits = 6;
+ else if (ctrl->nand_version >= 0x0500)
+ bits = 5;
+ else
+ bits = 4;
+
+ if (ctrl->nand_version >= 0x0702) {
+ if (cs >= 4)
+ reg = BRCMNAND_CORR_THRESHOLD_EXT;
+ shift = (cs % 4) * bits;
+ } else if (ctrl->nand_version >= 0x0600) {
+ if (cs >= 5)
+ reg = BRCMNAND_CORR_THRESHOLD_EXT;
+ shift = (cs % 5) * bits;
+ }
+ brcmnand_rmw_reg(ctrl, reg, (bits - 1) << shift, shift, val);
+}
+
+static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl)
+{
+ if (ctrl->nand_version < 0x0602)
+ return 24;
+ return 0;
+}
+
+/***********************************************************************
+ * NAND ACC CONTROL bitfield
+ *
+ * Some bits have remained constant throughout hardware revision, while
+ * others have shifted around.
+ ***********************************************************************/
+
+/* Constant for all versions (where supported) */
+enum {
+ /* See BRCMNAND_HAS_CACHE_MODE */
+ ACC_CONTROL_CACHE_MODE = BIT(22),
+
+ /* See BRCMNAND_HAS_PREFETCH */
+ ACC_CONTROL_PREFETCH = BIT(23),
+
+ ACC_CONTROL_PAGE_HIT = BIT(24),
+ ACC_CONTROL_WR_PREEMPT = BIT(25),
+ ACC_CONTROL_PARTIAL_PAGE = BIT(26),
+ ACC_CONTROL_RD_ERASED = BIT(27),
+ ACC_CONTROL_FAST_PGM_RDIN = BIT(28),
+ ACC_CONTROL_WR_ECC = BIT(30),
+ ACC_CONTROL_RD_ECC = BIT(31),
+};
+
+static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl)
+{
+ if (ctrl->nand_version >= 0x0702)
+ return GENMASK(7, 0);
+ else if (ctrl->nand_version >= 0x0600)
+ return GENMASK(6, 0);
+ else
+ return GENMASK(5, 0);
+}
+
+#define NAND_ACC_CONTROL_ECC_SHIFT 16
+#define NAND_ACC_CONTROL_ECC_EXT_SHIFT 13
+
+static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl)
+{
+ u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f;
+
+ mask <<= NAND_ACC_CONTROL_ECC_SHIFT;
+
+ /* v7.2 includes additional ECC levels */
+ if (ctrl->nand_version >= 0x0702)
+ mask |= 0x7 << NAND_ACC_CONTROL_ECC_EXT_SHIFT;
+
+ return mask;
+}
+
+static void brcmnand_set_ecc_enabled(struct brcmnand_host *host, int en)
+{
+ struct brcmnand_controller *ctrl = host->ctrl;
+ u16 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);
+ u32 acc_control = nand_readreg(ctrl, offs);
+ u32 ecc_flags = ACC_CONTROL_WR_ECC | ACC_CONTROL_RD_ECC;
+
+ if (en) {
+ acc_control |= ecc_flags; /* enable RD/WR ECC */
+ acc_control |= host->hwcfg.ecc_level
+ << NAND_ACC_CONTROL_ECC_SHIFT;
+ } else {
+ acc_control &= ~ecc_flags; /* disable RD/WR ECC */
+ acc_control &= ~brcmnand_ecc_level_mask(ctrl);
+ }
+
+ nand_writereg(ctrl, offs, acc_control);
+}
+
+static inline int brcmnand_sector_1k_shift(struct brcmnand_controller *ctrl)
+{
+ if (ctrl->nand_version >= 0x0702)
+ return 9;
+ else if (ctrl->nand_version >= 0x0600)
+ return 7;
+ else if (ctrl->nand_version >= 0x0500)
+ return 6;
+ else
+ return -1;
+}
+
+static int brcmnand_get_sector_size_1k(struct brcmnand_host *host)
+{
+ struct brcmnand_controller *ctrl = host->ctrl;
+ int shift = brcmnand_sector_1k_shift(ctrl);
+ u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
+ BRCMNAND_CS_ACC_CONTROL);
+
+ if (shift < 0)
+ return 0;
+
+ return (nand_readreg(ctrl, acc_control_offs) >> shift) & 0x1;
+}
+
+static void brcmnand_set_sector_size_1k(struct brcmnand_host *host, int val)
+{
+ struct brcmnand_controller *ctrl = host->ctrl;
+ int shift = brcmnand_sector_1k_shift(ctrl);
+ u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
+ BRCMNAND_CS_ACC_CONTROL);
+ u32 tmp;
+
+ if (shift < 0)
+ return;
+
+ tmp = nand_readreg(ctrl, acc_control_offs);
+ tmp &= ~(1 << shift);
+ tmp |= (!!val) << shift;
+ nand_writereg(ctrl, acc_control_offs, tmp);
+}
+
+/***********************************************************************
+ * CS_NAND_SELECT
+ ***********************************************************************/
+
+enum {
+ CS_SELECT_NAND_WP = BIT(29),
+ CS_SELECT_AUTO_DEVICE_ID_CFG = BIT(30),
+};
+
+static int bcmnand_ctrl_poll_status(struct brcmnand_controller *ctrl,
+ u32 mask, u32 expected_val,
+ unsigned long timeout_ms)
+{
+#ifndef __UBOOT__
+ unsigned long limit;
+ u32 val;
+
+ if (!timeout_ms)
+ timeout_ms = NAND_POLL_STATUS_TIMEOUT_MS;
+
+ limit = jiffies + msecs_to_jiffies(timeout_ms);
+ do {
+ val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS);
+ if ((val & mask) == expected_val)
+ return 0;
+
+ cpu_relax();
+ } while (time_after(limit, jiffies));
+#else
+ unsigned long base, limit;
+ u32 val;
+
+ if (!timeout_ms)
+ timeout_ms = NAND_POLL_STATUS_TIMEOUT_MS;
+
+ base = get_timer(0);
+ limit = CONFIG_SYS_HZ * timeout_ms / 1000;
+ do {
+ val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS);
+ if ((val & mask) == expected_val)
+ return 0;
+
+ cpu_relax();
+ } while (get_timer(base) < limit);
+#endif /* __UBOOT__ */
+
+ dev_warn(ctrl->dev, "timeout on status poll (expected %x got %x)\n",
+ expected_val, val & mask);
+
+ return -ETIMEDOUT;
+}
+
+static inline void brcmnand_set_wp(struct brcmnand_controller *ctrl, bool en)
+{
+ u32 val = en ? CS_SELECT_NAND_WP : 0;
+
+ brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, CS_SELECT_NAND_WP, 0, val);
+}
+
+/***********************************************************************
+ * Flash DMA
+ ***********************************************************************/
+
+enum flash_dma_reg {
+ FLASH_DMA_REVISION = 0x00,
+ FLASH_DMA_FIRST_DESC = 0x04,
+ FLASH_DMA_FIRST_DESC_EXT = 0x08,
+ FLASH_DMA_CTRL = 0x0c,
+ FLASH_DMA_MODE = 0x10,
+ FLASH_DMA_STATUS = 0x14,
+ FLASH_DMA_INTERRUPT_DESC = 0x18,
+ FLASH_DMA_INTERRUPT_DESC_EXT = 0x1c,
+ FLASH_DMA_ERROR_STATUS = 0x20,
+ FLASH_DMA_CURRENT_DESC = 0x24,
+ FLASH_DMA_CURRENT_DESC_EXT = 0x28,
+};
+
+static inline bool has_flash_dma(struct brcmnand_controller *ctrl)
+{
+ return ctrl->flash_dma_base;
+}
+
+static inline bool flash_dma_buf_ok(const void *buf)
+{
+#ifndef __UBOOT__
+ return buf && !is_vmalloc_addr(buf) &&
+ likely(IS_ALIGNED((uintptr_t)buf, 4));
+#else
+ return buf && likely(IS_ALIGNED((uintptr_t)buf, 4));
+#endif /* __UBOOT__ */
+}
+
+static inline void flash_dma_writel(struct brcmnand_controller *ctrl, u8 offs,
+ u32 val)
+{
+ brcmnand_writel(val, ctrl->flash_dma_base + offs);
+}
+
+static inline u32 flash_dma_readl(struct brcmnand_controller *ctrl, u8 offs)
+{
+ return brcmnand_readl(ctrl->flash_dma_base + offs);
+}
+
+/* Low-level operation types: command, address, write, or read */
+enum brcmnand_llop_type {
+ LL_OP_CMD,
+ LL_OP_ADDR,
+ LL_OP_WR,
+ LL_OP_RD,
+};
+
+/***********************************************************************
+ * Internal support functions
+ ***********************************************************************/
+
+static inline bool is_hamming_ecc(struct brcmnand_controller *ctrl,
+ struct brcmnand_cfg *cfg)
+{
+ if (ctrl->nand_version <= 0x0701)
+ return cfg->sector_size_1k == 0 && cfg->spare_area_size == 16 &&
+ cfg->ecc_level == 15;
+ else
+ return cfg->sector_size_1k == 0 && ((cfg->spare_area_size == 16 &&
+ cfg->ecc_level == 15) ||
+ (cfg->spare_area_size == 28 && cfg->ecc_level == 16));
+}
+
+/*
+ * Set mtd->ooblayout to the appropriate mtd_ooblayout_ops given
+ * the layout/configuration.
+ * Returns -ERRCODE on failure.
+ */
+static int brcmnand_hamming_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobregion)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct brcmnand_host *host = nand_get_controller_data(chip);
+ struct brcmnand_cfg *cfg = &host->hwcfg;
+ int sas = cfg->spare_area_size << cfg->sector_size_1k;
+ int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
+
+ if (section >= sectors)
+ return -ERANGE;
+
+ oobregion->offset = (section * sas) + 6;
+ oobregion->length = 3;
+
+ return 0;
+}
+
+static int brcmnand_hamming_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobregion)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct brcmnand_host *host = nand_get_controller_data(chip);
+ struct brcmnand_cfg *cfg = &host->hwcfg;
+ int sas = cfg->spare_area_size << cfg->sector_size_1k;
+ int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
+
+ if (section >= sectors * 2)
+ return -ERANGE;
+
+ oobregion->offset = (section / 2) * sas;
+
+ if (section & 1) {
+ oobregion->offset += 9;
+ oobregion->length = 7;
+ } else {
+ oobregion->length = 6;
+
+ /* First sector of each page may have BBI */
+ if (!section) {
+ /*
+ * Small-page NAND use byte 6 for BBI while large-page
+ * NAND use byte 0.
+ */
+ if (cfg->page_size > 512)
+ oobregion->offset++;
+ oobregion->length--;
+ }
+ }
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops brcmnand_hamming_ooblayout_ops = {
+ .ecc = brcmnand_hamming_ooblayout_ecc,
+ .free = brcmnand_hamming_ooblayout_free,
+};
+
+static int brcmnand_bch_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobregion)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct brcmnand_host *host = nand_get_controller_data(chip);
+ struct brcmnand_cfg *cfg = &host->hwcfg;
+ int sas = cfg->spare_area_size << cfg->sector_size_1k;
+ int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
+
+ if (section >= sectors)
+ return -ERANGE;
+
+ oobregion->offset = (section * (sas + 1)) - chip->ecc.bytes;
+ oobregion->length = chip->ecc.bytes;
+
+ return 0;
+}
+
+static int brcmnand_bch_ooblayout_free_lp(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobregion)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct brcmnand_host *host = nand_get_controller_data(chip);
+ struct brcmnand_cfg *cfg = &host->hwcfg;
+ int sas = cfg->spare_area_size << cfg->sector_size_1k;
+ int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
+
+ if (section >= sectors)
+ return -ERANGE;
+
+ if (sas <= chip->ecc.bytes)
+ return 0;
+
+ oobregion->offset = section * sas;
+ oobregion->length = sas - chip->ecc.bytes;
+
+ if (!section) {
+ oobregion->offset++;
+ oobregion->length--;
+ }
+
+ return 0;
+}
+
+static int brcmnand_bch_ooblayout_free_sp(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobregion)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct brcmnand_host *host = nand_get_controller_data(chip);
+ struct brcmnand_cfg *cfg = &host->hwcfg;
+ int sas = cfg->spare_area_size << cfg->sector_size_1k;
+
+ if (section > 1 || sas - chip->ecc.bytes < 6 ||
+ (section && sas - chip->ecc.bytes == 6))
+ return -ERANGE;
+
+ if (!section) {
+ oobregion->offset = 0;
+ oobregion->length = 5;
+ } else {
+ oobregion->offset = 6;
+ oobregion->length = sas - chip->ecc.bytes - 6;
+ }
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops brcmnand_bch_lp_ooblayout_ops = {
+ .ecc = brcmnand_bch_ooblayout_ecc,
+ .free = brcmnand_bch_ooblayout_free_lp,
+};
+
+static const struct mtd_ooblayout_ops brcmnand_bch_sp_ooblayout_ops = {
+ .ecc = brcmnand_bch_ooblayout_ecc,
+ .free = brcmnand_bch_ooblayout_free_sp,
+};
+
+static int brcmstb_choose_ecc_layout(struct brcmnand_host *host)
+{
+ struct brcmnand_cfg *p = &host->hwcfg;
+ struct mtd_info *mtd = nand_to_mtd(&host->chip);
+ struct nand_ecc_ctrl *ecc = &host->chip.ecc;
+ unsigned int ecc_level = p->ecc_level;
+ int sas = p->spare_area_size << p->sector_size_1k;
+ int sectors = p->page_size / (512 << p->sector_size_1k);
+
+ if (p->sector_size_1k)
+ ecc_level <<= 1;
+
+ if (is_hamming_ecc(host->ctrl, p)) {
+ ecc->bytes = 3 * sectors;
+ mtd_set_ooblayout(mtd, &brcmnand_hamming_ooblayout_ops);
+ return 0;
+ }
+
+ /*
+ * CONTROLLER_VERSION:
+ * < v5.0: ECC_REQ = ceil(BCH_T * 13/8)
+ * >= v5.0: ECC_REQ = ceil(BCH_T * 14/8)
+ * But we will just be conservative.
+ */
+ ecc->bytes = DIV_ROUND_UP(ecc_level * 14, 8);
+ if (p->page_size == 512)
+ mtd_set_ooblayout(mtd, &brcmnand_bch_sp_ooblayout_ops);
+ else
+ mtd_set_ooblayout(mtd, &brcmnand_bch_lp_ooblayout_ops);
+
+ if (ecc->bytes >= sas) {
+ dev_err(&host->pdev->dev,
+ "error: ECC too large for OOB (ECC bytes %d, spare sector %d)\n",
+ ecc->bytes, sas);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static void brcmnand_wp(struct mtd_info *mtd, int wp)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct brcmnand_host *host = nand_get_controller_data(chip);
+ struct brcmnand_controller *ctrl = host->ctrl;
+
+ if ((ctrl->features & BRCMNAND_HAS_WP) && wp_on == 1) {
+ static int old_wp = -1;
+ int ret;
+
+ if (old_wp != wp) {
+ dev_dbg(ctrl->dev, "WP %s\n", wp ? "on" : "off");
+ old_wp = wp;
+ }
+
+ /*
+ * make sure ctrl/flash ready before and after
+ * changing state of #WP pin
+ */
+ ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY |
+ NAND_STATUS_READY,
+ NAND_CTRL_RDY |
+ NAND_STATUS_READY, 0);
+ if (ret)
+ return;
+
+ brcmnand_set_wp(ctrl, wp);
+ nand_status_op(chip, NULL);
+ /* NAND_STATUS_WP 0x00 = protected, 0x80 = not protected */
+ ret = bcmnand_ctrl_poll_status(ctrl,
+ NAND_CTRL_RDY |
+ NAND_STATUS_READY |
+ NAND_STATUS_WP,
+ NAND_CTRL_RDY |
+ NAND_STATUS_READY |
+ (wp ? 0 : NAND_STATUS_WP), 0);
+#ifndef __UBOOT__
+ if (ret)
+ dev_err_ratelimited(&host->pdev->dev,
+ "nand #WP expected %s\n",
+ wp ? "on" : "off");
+#else
+ if (ret)
+ dev_err(&host->pdev->dev,
+ "nand #WP expected %s\n",
+ wp ? "on" : "off");
+#endif /* __UBOOT__ */
+ }
+}
+
+/* Helper functions for reading and writing OOB registers */
+static inline u8 oob_reg_read(struct brcmnand_controller *ctrl, u32 offs)
+{
+ u16 offset0, offset10, reg_offs;
+
+ offset0 = ctrl->reg_offsets[BRCMNAND_OOB_READ_BASE];
+ offset10 = ctrl->reg_offsets[BRCMNAND_OOB_READ_10_BASE];
+
+ if (offs >= ctrl->max_oob)
+ return 0x77;
+
+ if (offs >= 16 && offset10)
+ reg_offs = offset10 + ((offs - 0x10) & ~0x03);
+ else
+ reg_offs = offset0 + (offs & ~0x03);
+
+ return nand_readreg(ctrl, reg_offs) >> (24 - ((offs & 0x03) << 3));
+}
+
+static inline void oob_reg_write(struct brcmnand_controller *ctrl, u32 offs,
+ u32 data)
+{
+ u16 offset0, offset10, reg_offs;
+
+ offset0 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_BASE];
+ offset10 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_10_BASE];
+
+ if (offs >= ctrl->max_oob)
+ return;
+
+ if (offs >= 16 && offset10)
+ reg_offs = offset10 + ((offs - 0x10) & ~0x03);
+ else
+ reg_offs = offset0 + (offs & ~0x03);
+
+ nand_writereg(ctrl, reg_offs, data);
+}
+
+/*
+ * read_oob_from_regs - read data from OOB registers
+ * @ctrl: NAND controller
+ * @i: sub-page sector index
+ * @oob: buffer to read to
+ * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
+ * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
+ */
+static int read_oob_from_regs(struct brcmnand_controller *ctrl, int i, u8 *oob,
+ int sas, int sector_1k)
+{
+ int tbytes = sas << sector_1k;
+ int j;
+
+ /* Adjust OOB values for 1K sector size */
+ if (sector_1k && (i & 0x01))
+ tbytes = max(0, tbytes - (int)ctrl->max_oob);
+ tbytes = min_t(int, tbytes, ctrl->max_oob);
+
+ for (j = 0; j < tbytes; j++)
+ oob[j] = oob_reg_read(ctrl, j);
+ return tbytes;
+}
+
+/*
+ * write_oob_to_regs - write data to OOB registers
+ * @i: sub-page sector index
+ * @oob: buffer to write from
+ * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
+ * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
+ */
+static int write_oob_to_regs(struct brcmnand_controller *ctrl, int i,
+ const u8 *oob, int sas, int sector_1k)
+{
+ int tbytes = sas << sector_1k;
+ int j;
+
+ /* Adjust OOB values for 1K sector size */
+ if (sector_1k && (i & 0x01))
+ tbytes = max(0, tbytes - (int)ctrl->max_oob);
+ tbytes = min_t(int, tbytes, ctrl->max_oob);
+
+ for (j = 0; j < tbytes; j += 4)
+ oob_reg_write(ctrl, j,
+ (oob[j + 0] << 24) |
+ (oob[j + 1] << 16) |
+ (oob[j + 2] << 8) |
+ (oob[j + 3] << 0));
+ return tbytes;
+}
+
+#ifndef __UBOOT__
+static irqreturn_t brcmnand_ctlrdy_irq(int irq, void *data)
+{
+ struct brcmnand_controller *ctrl = data;
+
+ /* Discard all NAND_CTLRDY interrupts during DMA */
+ if (ctrl->dma_pending)
+ return IRQ_HANDLED;
+
+ complete(&ctrl->done);
+ return IRQ_HANDLED;
+}
+
+/* Handle SoC-specific interrupt hardware */
+static irqreturn_t brcmnand_irq(int irq, void *data)
+{
+ struct brcmnand_controller *ctrl = data;
+
+ if (ctrl->soc->ctlrdy_ack(ctrl->soc))
+ return brcmnand_ctlrdy_irq(irq, data);
+
+ return IRQ_NONE;
+}
+
+static irqreturn_t brcmnand_dma_irq(int irq, void *data)
+{
+ struct brcmnand_controller *ctrl = data;
+
+ complete(&ctrl->dma_done);
+
+ return IRQ_HANDLED;
+}
+#endif /* __UBOOT__ */
+
+static void brcmnand_send_cmd(struct brcmnand_host *host, int cmd)
+{
+ struct brcmnand_controller *ctrl = host->ctrl;
+ int ret;
+
+ dev_dbg(ctrl->dev, "send native cmd %d addr_lo 0x%x\n", cmd,
+ brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS));
+ BUG_ON(ctrl->cmd_pending != 0);
+ ctrl->cmd_pending = cmd;
+
+ ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, NAND_CTRL_RDY, 0);
+ WARN_ON(ret);
+
+ mb(); /* flush previous writes */
+ brcmnand_write_reg(ctrl, BRCMNAND_CMD_START,
+ cmd << brcmnand_cmd_shift(ctrl));
+}
+
+/***********************************************************************
+ * NAND MTD API: read/program/erase
+ ***********************************************************************/
+
+static void brcmnand_cmd_ctrl(struct mtd_info *mtd, int dat,
+ unsigned int ctrl)
+{
+ /* intentionally left blank */
+}
+
+static int brcmnand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct brcmnand_host *host = nand_get_controller_data(chip);
+ struct brcmnand_controller *ctrl = host->ctrl;
+
+#ifndef __UBOOT__
+ unsigned long timeo = msecs_to_jiffies(100);
+
+ dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending);
+ if (ctrl->cmd_pending &&
+ wait_for_completion_timeout(&ctrl->done, timeo) <= 0) {
+ u32 cmd = brcmnand_read_reg(ctrl, BRCMNAND_CMD_START)
+ >> brcmnand_cmd_shift(ctrl);
+
+ dev_err_ratelimited(ctrl->dev,
+ "timeout waiting for command %#02x\n", cmd);
+ dev_err_ratelimited(ctrl->dev, "intfc status %08x\n",
+ brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS));
+ }
+#else
+ unsigned long timeo = 100; /* 100 msec */
+ int ret;
+
+ dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending);
+
+ ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, NAND_CTRL_RDY, timeo);
+ WARN_ON(ret);
+#endif /* __UBOOT__ */
+
+ ctrl->cmd_pending = 0;
+ return brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
+ INTFC_FLASH_STATUS;
+}
+
+enum {
+ LLOP_RE = BIT(16),
+ LLOP_WE = BIT(17),
+ LLOP_ALE = BIT(18),
+ LLOP_CLE = BIT(19),
+ LLOP_RETURN_IDLE = BIT(31),
+
+ LLOP_DATA_MASK = GENMASK(15, 0),
+};
+
+static int brcmnand_low_level_op(struct brcmnand_host *host,
+ enum brcmnand_llop_type type, u32 data,
+ bool last_op)
+{
+ struct mtd_info *mtd = nand_to_mtd(&host->chip);
+ struct nand_chip *chip = &host->chip;
+ struct brcmnand_controller *ctrl = host->ctrl;
+ u32 tmp;
+
+ tmp = data & LLOP_DATA_MASK;
+ switch (type) {
+ case LL_OP_CMD:
+ tmp |= LLOP_WE | LLOP_CLE;
+ break;
+ case LL_OP_ADDR:
+ /* WE | ALE */
+ tmp |= LLOP_WE | LLOP_ALE;
+ break;
+ case LL_OP_WR:
+ /* WE */
+ tmp |= LLOP_WE;
+ break;
+ case LL_OP_RD:
+ /* RE */
+ tmp |= LLOP_RE;
+ break;
+ }
+ if (last_op)
+ /* RETURN_IDLE */
+ tmp |= LLOP_RETURN_IDLE;
+
+ dev_dbg(ctrl->dev, "ll_op cmd %#x\n", tmp);
+
+ brcmnand_write_reg(ctrl, BRCMNAND_LL_OP, tmp);
+ (void)brcmnand_read_reg(ctrl, BRCMNAND_LL_OP);
+
+ brcmnand_send_cmd(host, CMD_LOW_LEVEL_OP);
+ return brcmnand_waitfunc(mtd, chip);
+}
+
+static void brcmnand_cmdfunc(struct mtd_info *mtd, unsigned command,
+ int column, int page_addr)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct brcmnand_host *host = nand_get_controller_data(chip);
+ struct brcmnand_controller *ctrl = host->ctrl;
+ u64 addr = (u64)page_addr << chip->page_shift;
+ int native_cmd = 0;
+
+ if (command == NAND_CMD_READID || command == NAND_CMD_PARAM ||
+ command == NAND_CMD_RNDOUT)
+ addr = (u64)column;
+ /* Avoid propagating a negative, don't-care address */
+ else if (page_addr < 0)
+ addr = 0;
+
+ dev_dbg(ctrl->dev, "cmd 0x%x addr 0x%llx\n", command,
+ (unsigned long long)addr);
+
+ host->last_cmd = command;
+ host->last_byte = 0;
+ host->last_addr = addr;
+
+ switch (command) {
+ case NAND_CMD_RESET:
+ native_cmd = CMD_FLASH_RESET;
+ break;
+ case NAND_CMD_STATUS:
+ native_cmd = CMD_STATUS_READ;
+ break;
+ case NAND_CMD_READID:
+ native_cmd = CMD_DEVICE_ID_READ;
+ break;
+ case NAND_CMD_READOOB:
+ native_cmd = CMD_SPARE_AREA_READ;
+ break;
+ case NAND_CMD_ERASE1:
+ native_cmd = CMD_BLOCK_ERASE;
+ brcmnand_wp(mtd, 0);
+ break;
+ case NAND_CMD_PARAM:
+ native_cmd = CMD_PARAMETER_READ;
+ break;
+ case NAND_CMD_SET_FEATURES:
+ case NAND_CMD_GET_FEATURES:
+ brcmnand_low_level_op(host, LL_OP_CMD, command, false);
+ brcmnand_low_level_op(host, LL_OP_ADDR, column, false);
+ break;
+ case NAND_CMD_RNDOUT:
+ native_cmd = CMD_PARAMETER_CHANGE_COL;
+ addr &= ~((u64)(FC_BYTES - 1));
+ /*
+ * HW quirk: PARAMETER_CHANGE_COL requires SECTOR_SIZE_1K=0
+ * NB: hwcfg.sector_size_1k may not be initialized yet
+ */
+ if (brcmnand_get_sector_size_1k(host)) {
+ host->hwcfg.sector_size_1k =
+ brcmnand_get_sector_size_1k(host);
+ brcmnand_set_sector_size_1k(host, 0);
+ }
+ break;
+ }
+
+ if (!native_cmd)
+ return;
+
+ brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
+ (host->cs << 16) | ((addr >> 32) & 0xffff));
+ (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
+ brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, lower_32_bits(addr));
+ (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
+
+ brcmnand_send_cmd(host, native_cmd);
+ brcmnand_waitfunc(mtd, chip);
+
+ if (native_cmd == CMD_PARAMETER_READ ||
+ native_cmd == CMD_PARAMETER_CHANGE_COL) {
+ /* Copy flash cache word-wise */
+ u32 *flash_cache = (u32 *)ctrl->flash_cache;
+ int i;
+
+ brcmnand_soc_data_bus_prepare(ctrl->soc, true);
+
+ /*
+ * Must cache the FLASH_CACHE now, since changes in
+ * SECTOR_SIZE_1K may invalidate it
+ */
+ for (i = 0; i < FC_WORDS; i++) {
+ u32 fc;
+
+ fc = brcmnand_read_fc(ctrl, i);
+
+ /*
+ * Flash cache is big endian for parameter pages, at
+ * least on STB SoCs
+ */
+ if (ctrl->parameter_page_big_endian)
+ flash_cache[i] = be32_to_cpu(fc);
+ else
+ flash_cache[i] = le32_to_cpu(fc);
+ }
+
+ brcmnand_soc_data_bus_unprepare(ctrl->soc, true);
+
+ /* Cleanup from HW quirk: restore SECTOR_SIZE_1K */
+ if (host->hwcfg.sector_size_1k)
+ brcmnand_set_sector_size_1k(host,
+ host->hwcfg.sector_size_1k);
+ }
+
+ /* Re-enable protection is necessary only after erase */
+ if (command == NAND_CMD_ERASE1)
+ brcmnand_wp(mtd, 1);
+}
+
+static uint8_t brcmnand_read_byte(struct mtd_info *mtd)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct brcmnand_host *host = nand_get_controller_data(chip);
+ struct brcmnand_controller *ctrl = host->ctrl;
+ uint8_t ret = 0;
+ int addr, offs;
+
+ switch (host->last_cmd) {
+ case NAND_CMD_READID:
+ if (host->last_byte < 4)
+ ret = brcmnand_read_reg(ctrl, BRCMNAND_ID) >>
+ (24 - (host->last_byte << 3));
+ else if (host->last_byte < 8)
+ ret = brcmnand_read_reg(ctrl, BRCMNAND_ID_EXT) >>
+ (56 - (host->last_byte << 3));
+ break;
+
+ case NAND_CMD_READOOB:
+ ret = oob_reg_read(ctrl, host->last_byte);
+ break;
+
+ case NAND_CMD_STATUS:
+ ret = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
+ INTFC_FLASH_STATUS;
+ if (wp_on) /* hide WP status */
+ ret |= NAND_STATUS_WP;
+ break;
+
+ case NAND_CMD_PARAM:
+ case NAND_CMD_RNDOUT:
+ addr = host->last_addr + host->last_byte;
+ offs = addr & (FC_BYTES - 1);
+
+ /* At FC_BYTES boundary, switch to next column */
+ if (host->last_byte > 0 && offs == 0)
+ nand_change_read_column_op(chip, addr, NULL, 0, false);
+
+ ret = ctrl->flash_cache[offs];
+ break;
+ case NAND_CMD_GET_FEATURES:
+ if (host->last_byte >= ONFI_SUBFEATURE_PARAM_LEN) {
+ ret = 0;
+ } else {
+ bool last = host->last_byte ==
+ ONFI_SUBFEATURE_PARAM_LEN - 1;
+ brcmnand_low_level_op(host, LL_OP_RD, 0, last);
+ ret = brcmnand_read_reg(ctrl, BRCMNAND_LL_RDATA) & 0xff;
+ }
+ }
+
+ dev_dbg(ctrl->dev, "read byte = 0x%02x\n", ret);
+ host->last_byte++;
+
+ return ret;
+}
+
+static void brcmnand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++, buf++)
+ *buf = brcmnand_read_byte(mtd);
+}
+
+static void brcmnand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
+ int len)
+{
+ int i;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct brcmnand_host *host = nand_get_controller_data(chip);
+
+ switch (host->last_cmd) {
+ case NAND_CMD_SET_FEATURES:
+ for (i = 0; i < len; i++)
+ brcmnand_low_level_op(host, LL_OP_WR, buf[i],
+ (i + 1) == len);
+ break;
+ default:
+ BUG();
+ break;
+ }
+}
+
+/**
+ * Construct a FLASH_DMA descriptor as part of a linked list. You must know the
+ * following ahead of time:
+ * - Is this descriptor the beginning or end of a linked list?
+ * - What is the (DMA) address of the next descriptor in the linked list?
+ */
+#ifndef __UBOOT__
+static int brcmnand_fill_dma_desc(struct brcmnand_host *host,
+ struct brcm_nand_dma_desc *desc, u64 addr,
+ dma_addr_t buf, u32 len, u8 dma_cmd,
+ bool begin, bool end,
+ dma_addr_t next_desc)
+{
+ memset(desc, 0, sizeof(*desc));
+ /* Descriptors are written in native byte order (wordwise) */
+ desc->next_desc = lower_32_bits(next_desc);
+ desc->next_desc_ext = upper_32_bits(next_desc);
+ desc->cmd_irq = (dma_cmd << 24) |
+ (end ? (0x03 << 8) : 0) | /* IRQ | STOP */
+ (!!begin) | ((!!end) << 1); /* head, tail */
+#ifdef CONFIG_CPU_BIG_ENDIAN
+ desc->cmd_irq |= 0x01 << 12;
+#endif
+ desc->dram_addr = lower_32_bits(buf);
+ desc->dram_addr_ext = upper_32_bits(buf);
+ desc->tfr_len = len;
+ desc->total_len = len;
+ desc->flash_addr = lower_32_bits(addr);
+ desc->flash_addr_ext = upper_32_bits(addr);
+ desc->cs = host->cs;
+ desc->status_valid = 0x01;
+ return 0;
+}
+
+/**
+ * Kick the FLASH_DMA engine, with a given DMA descriptor
+ */
+static void brcmnand_dma_run(struct brcmnand_host *host, dma_addr_t desc)
+{
+ struct brcmnand_controller *ctrl = host->ctrl;
+ unsigned long timeo = msecs_to_jiffies(100);
+
+ flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC, lower_32_bits(desc));
+ (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC);
+ flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT, upper_32_bits(desc));
+ (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT);
+
+ /* Start FLASH_DMA engine */
+ ctrl->dma_pending = true;
+ mb(); /* flush previous writes */
+ flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0x03); /* wake | run */
+
+ if (wait_for_completion_timeout(&ctrl->dma_done, timeo) <= 0) {
+ dev_err(ctrl->dev,
+ "timeout waiting for DMA; status %#x, error status %#x\n",
+ flash_dma_readl(ctrl, FLASH_DMA_STATUS),
+ flash_dma_readl(ctrl, FLASH_DMA_ERROR_STATUS));
+ }
+ ctrl->dma_pending = false;
+ flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0); /* force stop */
+}
+
+static int brcmnand_dma_trans(struct brcmnand_host *host, u64 addr, u32 *buf,
+ u32 len, u8 dma_cmd)
+{
+ struct brcmnand_controller *ctrl = host->ctrl;
+ dma_addr_t buf_pa;
+ int dir = dma_cmd == CMD_PAGE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
+
+ buf_pa = dma_map_single(ctrl->dev, buf, len, dir);
+ if (dma_mapping_error(ctrl->dev, buf_pa)) {
+ dev_err(ctrl->dev, "unable to map buffer for DMA\n");
+ return -ENOMEM;
+ }
+
+ brcmnand_fill_dma_desc(host, ctrl->dma_desc, addr, buf_pa, len,
+ dma_cmd, true, true, 0);
+
+ brcmnand_dma_run(host, ctrl->dma_pa);
+
+ dma_unmap_single(ctrl->dev, buf_pa, len, dir);
+
+ if (ctrl->dma_desc->status_valid & FLASH_DMA_ECC_ERROR)
+ return -EBADMSG;
+ else if (ctrl->dma_desc->status_valid & FLASH_DMA_CORR_ERROR)
+ return -EUCLEAN;
+
+ return 0;
+}
+#endif /* __UBOOT__ */
+
+/*
+ * Assumes proper CS is already set
+ */
+static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip,
+ u64 addr, unsigned int trans, u32 *buf,
+ u8 *oob, u64 *err_addr)
+{
+ struct brcmnand_host *host = nand_get_controller_data(chip);
+ struct brcmnand_controller *ctrl = host->ctrl;
+ int i, j, ret = 0;
+
+ /* Clear error addresses */
+ brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_ADDR, 0);
+ brcmnand_write_reg(ctrl, BRCMNAND_CORR_ADDR, 0);
+ brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_EXT_ADDR, 0);
+ brcmnand_write_reg(ctrl, BRCMNAND_CORR_EXT_ADDR, 0);
+
+ brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
+ (host->cs << 16) | ((addr >> 32) & 0xffff));
+ (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
+
+ for (i = 0; i < trans; i++, addr += FC_BYTES) {
+ brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
+ lower_32_bits(addr));
+ (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
+ /* SPARE_AREA_READ does not use ECC, so just use PAGE_READ */
+ brcmnand_send_cmd(host, CMD_PAGE_READ);
+ brcmnand_waitfunc(mtd, chip);
+
+ if (likely(buf)) {
+ brcmnand_soc_data_bus_prepare(ctrl->soc, false);
+
+ for (j = 0; j < FC_WORDS; j++, buf++)
+ *buf = brcmnand_read_fc(ctrl, j);
+
+ brcmnand_soc_data_bus_unprepare(ctrl->soc, false);
+ }
+
+ if (oob)
+ oob += read_oob_from_regs(ctrl, i, oob,
+ mtd->oobsize / trans,
+ host->hwcfg.sector_size_1k);
+
+ if (!ret) {
+ *err_addr = brcmnand_read_reg(ctrl,
+ BRCMNAND_UNCORR_ADDR) |
+ ((u64)(brcmnand_read_reg(ctrl,
+ BRCMNAND_UNCORR_EXT_ADDR)
+ & 0xffff) << 32);
+ if (*err_addr)
+ ret = -EBADMSG;
+ }
+
+ if (!ret) {
+ *err_addr = brcmnand_read_reg(ctrl,
+ BRCMNAND_CORR_ADDR) |
+ ((u64)(brcmnand_read_reg(ctrl,
+ BRCMNAND_CORR_EXT_ADDR)
+ & 0xffff) << 32);
+ if (*err_addr)
+ ret = -EUCLEAN;
+ }
+ }
+
+ return ret;
+}
+
+/*
+ * Check a page to see if it is erased (w/ bitflips) after an uncorrectable ECC
+ * error
+ *
+ * Because the HW ECC signals an ECC error if an erase paged has even a single
+ * bitflip, we must check each ECC error to see if it is actually an erased
+ * page with bitflips, not a truly corrupted page.
+ *
+ * On a real error, return a negative error code (-EBADMSG for ECC error), and
+ * buf will contain raw data.
+ * Otherwise, buf gets filled with 0xffs and return the maximum number of
+ * bitflips-per-ECC-sector to the caller.
+ *
+ */
+static int brcmstb_nand_verify_erased_page(struct mtd_info *mtd,
+ struct nand_chip *chip, void *buf, u64 addr)
+{
+ int i, sas;
+ void *oob = chip->oob_poi;
+ int bitflips = 0;
+ int page = addr >> chip->page_shift;
+ int ret;
+
+ if (!buf) {
+#ifndef __UBOOT__
+ buf = chip->data_buf;
+#else
+ buf = chip->buffers->databuf;
+#endif
+ /* Invalidate page cache */
+ chip->pagebuf = -1;
+ }
+
+ sas = mtd->oobsize / chip->ecc.steps;
+
+ /* read without ecc for verification */
+ ret = chip->ecc.read_page_raw(mtd, chip, buf, true, page);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < chip->ecc.steps; i++, oob += sas) {
+ ret = nand_check_erased_ecc_chunk(buf, chip->ecc.size,
+ oob, sas, NULL, 0,
+ chip->ecc.strength);
+ if (ret < 0)
+ return ret;
+
+ bitflips = max(bitflips, ret);
+ }
+
+ return bitflips;
+}
+
+static int brcmnand_read(struct mtd_info *mtd, struct nand_chip *chip,
+ u64 addr, unsigned int trans, u32 *buf, u8 *oob)
+{
+ struct brcmnand_host *host = nand_get_controller_data(chip);
+ struct brcmnand_controller *ctrl = host->ctrl;
+ u64 err_addr = 0;
+ int err;
+ bool retry = true;
+
+ dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf);
+
+try_dmaread:
+ brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_COUNT, 0);
+
+#ifndef __UBOOT__
+ if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
+ err = brcmnand_dma_trans(host, addr, buf, trans * FC_BYTES,
+ CMD_PAGE_READ);
+ if (err) {
+ if (mtd_is_bitflip_or_eccerr(err))
+ err_addr = addr;
+ else
+ return -EIO;
+ }
+ } else {
+ if (oob)
+ memset(oob, 0x99, mtd->oobsize);
+
+ err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf,
+ oob, &err_addr);
+ }
+#else
+ if (oob)
+ memset(oob, 0x99, mtd->oobsize);
+
+ err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf,
+ oob, &err_addr);
+#endif /* __UBOOT__ */
+
+ if (mtd_is_eccerr(err)) {
+ /*
+ * On controller version and 7.0, 7.1 , DMA read after a
+ * prior PIO read that reported uncorrectable error,
+ * the DMA engine captures this error following DMA read
+ * cleared only on subsequent DMA read, so just retry once
+ * to clear a possible false error reported for current DMA
+ * read
+ */
+ if ((ctrl->nand_version == 0x0700) ||
+ (ctrl->nand_version == 0x0701)) {
+ if (retry) {
+ retry = false;
+ goto try_dmaread;
+ }
+ }
+
+ /*
+ * Controller version 7.2 has hw encoder to detect erased page
+ * bitflips, apply sw verification for older controllers only
+ */
+ if (ctrl->nand_version < 0x0702) {
+ err = brcmstb_nand_verify_erased_page(mtd, chip, buf,
+ addr);
+ /* erased page bitflips corrected */
+ if (err >= 0)
+ return err;
+ }
+
+ dev_dbg(ctrl->dev, "uncorrectable error at 0x%llx\n",
+ (unsigned long long)err_addr);
+ mtd->ecc_stats.failed++;
+ /* NAND layer expects zero on ECC errors */
+ return 0;
+ }
+
+ if (mtd_is_bitflip(err)) {
+ unsigned int corrected = brcmnand_count_corrected(ctrl);
+
+ dev_dbg(ctrl->dev, "corrected error at 0x%llx\n",
+ (unsigned long long)err_addr);
+ mtd->ecc_stats.corrected += corrected;
+ /* Always exceed the software-imposed threshold */
+ return max(mtd->bitflip_threshold, corrected);
+ }
+
+ return 0;
+}
+
+static int brcmnand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buf, int oob_required, int page)
+{
+ struct brcmnand_host *host = nand_get_controller_data(chip);
+ u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
+
+ nand_read_page_op(chip, page, 0, NULL, 0);
+
+ return brcmnand_read(mtd, chip, host->last_addr,
+ mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
+}
+
+static int brcmnand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buf, int oob_required, int page)
+{
+ struct brcmnand_host *host = nand_get_controller_data(chip);
+ u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
+ int ret;
+
+ nand_read_page_op(chip, page, 0, NULL, 0);
+
+ brcmnand_set_ecc_enabled(host, 0);
+ ret = brcmnand_read(mtd, chip, host->last_addr,
+ mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
+ brcmnand_set_ecc_enabled(host, 1);
+ return ret;
+}
+
+static int brcmnand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
+ int page)
+{
+ return brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
+ mtd->writesize >> FC_SHIFT,
+ NULL, (u8 *)chip->oob_poi);
+}
+
+static int brcmnand_read_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
+ int page)
+{
+ struct brcmnand_host *host = nand_get_controller_data(chip);
+
+ brcmnand_set_ecc_enabled(host, 0);
+ brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
+ mtd->writesize >> FC_SHIFT,
+ NULL, (u8 *)chip->oob_poi);
+ brcmnand_set_ecc_enabled(host, 1);
+ return 0;
+}
+
+static int brcmnand_write(struct mtd_info *mtd, struct nand_chip *chip,
+ u64 addr, const u32 *buf, u8 *oob)
+{
+ struct brcmnand_host *host = nand_get_controller_data(chip);
+ struct brcmnand_controller *ctrl = host->ctrl;
+ unsigned int i, j, trans = mtd->writesize >> FC_SHIFT;
+ int status, ret = 0;
+
+ dev_dbg(ctrl->dev, "write %llx <- %p\n", (unsigned long long)addr, buf);
+
+ if (unlikely((unsigned long)buf & 0x03)) {
+ dev_warn(ctrl->dev, "unaligned buffer: %p\n", buf);
+ buf = (u32 *)((unsigned long)buf & ~0x03);
+ }
+
+ brcmnand_wp(mtd, 0);
+
+ for (i = 0; i < ctrl->max_oob; i += 4)
+ oob_reg_write(ctrl, i, 0xffffffff);
+
+#ifndef __UBOOT__
+ if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
+ if (brcmnand_dma_trans(host, addr, (u32 *)buf,
+ mtd->writesize, CMD_PROGRAM_PAGE))
+ ret = -EIO;
+ goto out;
+ }
+#endif /* __UBOOT__ */
+
+ brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
+ (host->cs << 16) | ((addr >> 32) & 0xffff));
+ (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
+
+ for (i = 0; i < trans; i++, addr += FC_BYTES) {
+ /* full address MUST be set before populating FC */
+ brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
+ lower_32_bits(addr));
+ (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
+
+ if (buf) {
+ brcmnand_soc_data_bus_prepare(ctrl->soc, false);
+
+ for (j = 0; j < FC_WORDS; j++, buf++)
+ brcmnand_write_fc(ctrl, j, *buf);
+
+ brcmnand_soc_data_bus_unprepare(ctrl->soc, false);
+ } else if (oob) {
+ for (j = 0; j < FC_WORDS; j++)
+ brcmnand_write_fc(ctrl, j, 0xffffffff);
+ }
+
+ if (oob) {
+ oob += write_oob_to_regs(ctrl, i, oob,
+ mtd->oobsize / trans,
+ host->hwcfg.sector_size_1k);
+ }
+
+ /* we cannot use SPARE_AREA_PROGRAM when PARTIAL_PAGE_EN=0 */
+ brcmnand_send_cmd(host, CMD_PROGRAM_PAGE);
+ status = brcmnand_waitfunc(mtd, chip);
+
+ if (status & NAND_STATUS_FAIL) {
+ dev_info(ctrl->dev, "program failed at %llx\n",
+ (unsigned long long)addr);
+ ret = -EIO;
+ goto out;
+ }
+ }
+out:
+ brcmnand_wp(mtd, 1);
+ return ret;
+}
+
+static int brcmnand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
+ const uint8_t *buf, int oob_required, int page)
+{
+ struct brcmnand_host *host = nand_get_controller_data(chip);
+ void *oob = oob_required ? chip->oob_poi : NULL;
+
+ nand_prog_page_begin_op(chip, page, 0, NULL, 0);
+ brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
+
+ return nand_prog_page_end_op(chip);
+}
+
+static int brcmnand_write_page_raw(struct mtd_info *mtd,
+ struct nand_chip *chip, const uint8_t *buf,
+ int oob_required, int page)
+{
+ struct brcmnand_host *host = nand_get_controller_data(chip);
+ void *oob = oob_required ? chip->oob_poi : NULL;
+
+ nand_prog_page_begin_op(chip, page, 0, NULL, 0);
+ brcmnand_set_ecc_enabled(host, 0);
+ brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
+ brcmnand_set_ecc_enabled(host, 1);
+
+ return nand_prog_page_end_op(chip);
+}
+
+static int brcmnand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
+ int page)
+{
+ return brcmnand_write(mtd, chip, (u64)page << chip->page_shift,
+ NULL, chip->oob_poi);
+}
+
+static int brcmnand_write_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
+ int page)
+{
+ struct brcmnand_host *host = nand_get_controller_data(chip);
+ int ret;
+
+ brcmnand_set_ecc_enabled(host, 0);
+ ret = brcmnand_write(mtd, chip, (u64)page << chip->page_shift, NULL,
+ (u8 *)chip->oob_poi);
+ brcmnand_set_ecc_enabled(host, 1);
+
+ return ret;
+}
+
+/***********************************************************************
+ * Per-CS setup (1 NAND device)
+ ***********************************************************************/
+
+static int brcmnand_set_cfg(struct brcmnand_host *host,
+ struct brcmnand_cfg *cfg)
+{
+ struct brcmnand_controller *ctrl = host->ctrl;
+ struct nand_chip *chip = &host->chip;
+ u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
+ u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,
+ BRCMNAND_CS_CFG_EXT);
+ u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
+ BRCMNAND_CS_ACC_CONTROL);
+ u8 block_size = 0, page_size = 0, device_size = 0;
+ u32 tmp;
+
+ if (ctrl->block_sizes) {
+ int i, found;
+
+ for (i = 0, found = 0; ctrl->block_sizes[i]; i++)
+ if (ctrl->block_sizes[i] * 1024 == cfg->block_size) {
+ block_size = i;
+ found = 1;
+ }
+ if (!found) {
+ dev_warn(ctrl->dev, "invalid block size %u\n",
+ cfg->block_size);
+ return -EINVAL;
+ }
+ } else {
+ block_size = ffs(cfg->block_size) - ffs(BRCMNAND_MIN_BLOCKSIZE);
+ }
+
+ if (cfg->block_size < BRCMNAND_MIN_BLOCKSIZE || (ctrl->max_block_size &&
+ cfg->block_size > ctrl->max_block_size)) {
+ dev_warn(ctrl->dev, "invalid block size %u\n",
+ cfg->block_size);
+ block_size = 0;
+ }
+
+ if (ctrl->page_sizes) {
+ int i, found;
+
+ for (i = 0, found = 0; ctrl->page_sizes[i]; i++)
+ if (ctrl->page_sizes[i] == cfg->page_size) {
+ page_size = i;
+ found = 1;
+ }
+ if (!found) {
+ dev_warn(ctrl->dev, "invalid page size %u\n",
+ cfg->page_size);
+ return -EINVAL;
+ }
+ } else {
+ page_size = ffs(cfg->page_size) - ffs(BRCMNAND_MIN_PAGESIZE);
+ }
+
+ if (cfg->page_size < BRCMNAND_MIN_PAGESIZE || (ctrl->max_page_size &&
+ cfg->page_size > ctrl->max_page_size)) {
+ dev_warn(ctrl->dev, "invalid page size %u\n", cfg->page_size);
+ return -EINVAL;
+ }
+
+ if (fls64(cfg->device_size) < fls64(BRCMNAND_MIN_DEVSIZE)) {
+ dev_warn(ctrl->dev, "invalid device size 0x%llx\n",
+ (unsigned long long)cfg->device_size);
+ return -EINVAL;
+ }
+ device_size = fls64(cfg->device_size) - fls64(BRCMNAND_MIN_DEVSIZE);
+
+ tmp = (cfg->blk_adr_bytes << CFG_BLK_ADR_BYTES_SHIFT) |
+ (cfg->col_adr_bytes << CFG_COL_ADR_BYTES_SHIFT) |
+ (cfg->ful_adr_bytes << CFG_FUL_ADR_BYTES_SHIFT) |
+ (!!(cfg->device_width == 16) << CFG_BUS_WIDTH_SHIFT) |
+ (device_size << CFG_DEVICE_SIZE_SHIFT);
+ if (cfg_offs == cfg_ext_offs) {
+ tmp |= (page_size << CFG_PAGE_SIZE_SHIFT) |
+ (block_size << CFG_BLK_SIZE_SHIFT);
+ nand_writereg(ctrl, cfg_offs, tmp);
+ } else {
+ nand_writereg(ctrl, cfg_offs, tmp);
+ tmp = (page_size << CFG_EXT_PAGE_SIZE_SHIFT) |
+ (block_size << CFG_EXT_BLK_SIZE_SHIFT);
+ nand_writereg(ctrl, cfg_ext_offs, tmp);
+ }
+
+ tmp = nand_readreg(ctrl, acc_control_offs);
+ tmp &= ~brcmnand_ecc_level_mask(ctrl);
+ tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT;
+ tmp &= ~brcmnand_spare_area_mask(ctrl);
+ tmp |= cfg->spare_area_size;
+ nand_writereg(ctrl, acc_control_offs, tmp);
+
+ brcmnand_set_sector_size_1k(host, cfg->sector_size_1k);
+
+ /* threshold = ceil(BCH-level * 0.75) */
+ brcmnand_wr_corr_thresh(host, DIV_ROUND_UP(chip->ecc.strength * 3, 4));
+
+ return 0;
+}
+
+static void brcmnand_print_cfg(struct brcmnand_host *host,
+ char *buf, struct brcmnand_cfg *cfg)
+{
+ buf += sprintf(buf,
+ "%lluMiB total, %uKiB blocks, %u%s pages, %uB OOB, %u-bit",
+ (unsigned long long)cfg->device_size >> 20,
+ cfg->block_size >> 10,
+ cfg->page_size >= 1024 ? cfg->page_size >> 10 : cfg->page_size,
+ cfg->page_size >= 1024 ? "KiB" : "B",
+ cfg->spare_area_size, cfg->device_width);
+
+ /* Account for Hamming ECC and for BCH 512B vs 1KiB sectors */
+ if (is_hamming_ecc(host->ctrl, cfg))
+ sprintf(buf, ", Hamming ECC");
+ else if (cfg->sector_size_1k)
+ sprintf(buf, ", BCH-%u (1KiB sector)", cfg->ecc_level << 1);
+ else
+ sprintf(buf, ", BCH-%u", cfg->ecc_level);
+}
+
+/*
+ * Minimum number of bytes to address a page. Calculated as:
+ * roundup(log2(size / page-size) / 8)
+ *
+ * NB: the following does not "round up" for non-power-of-2 'size'; but this is
+ * OK because many other things will break if 'size' is irregular...
+ */
+static inline int get_blk_adr_bytes(u64 size, u32 writesize)
+{
+ return ALIGN(ilog2(size) - ilog2(writesize), 8) >> 3;
+}
+
+static int brcmnand_setup_dev(struct brcmnand_host *host)
+{
+ struct mtd_info *mtd = nand_to_mtd(&host->chip);
+ struct nand_chip *chip = &host->chip;
+ struct brcmnand_controller *ctrl = host->ctrl;
+ struct brcmnand_cfg *cfg = &host->hwcfg;
+ char msg[128];
+ u32 offs, tmp, oob_sector;
+ int ret;
+
+ memset(cfg, 0, sizeof(*cfg));
+
+#ifndef __UBOOT__
+ ret = of_property_read_u32(nand_get_flash_node(chip),
+ "brcm,nand-oob-sector-size",
+ &oob_sector);
+#else
+ ret = ofnode_read_u32(nand_get_flash_node(chip),
+ "brcm,nand-oob-sector-size",
+ &oob_sector);
+#endif /* __UBOOT__ */
+ if (ret) {
+ /* Use detected size */
+ cfg->spare_area_size = mtd->oobsize /
+ (mtd->writesize >> FC_SHIFT);
+ } else {
+ cfg->spare_area_size = oob_sector;
+ }
+ if (cfg->spare_area_size > ctrl->max_oob)
+ cfg->spare_area_size = ctrl->max_oob;
+ /*
+ * Set oobsize to be consistent with controller's spare_area_size, as
+ * the rest is inaccessible.
+ */
+ mtd->oobsize = cfg->spare_area_size * (mtd->writesize >> FC_SHIFT);
+
+ cfg->device_size = mtd->size;
+ cfg->block_size = mtd->erasesize;
+ cfg->page_size = mtd->writesize;
+ cfg->device_width = (chip->options & NAND_BUSWIDTH_16) ? 16 : 8;
+ cfg->col_adr_bytes = 2;
+ cfg->blk_adr_bytes = get_blk_adr_bytes(mtd->size, mtd->writesize);
+
+ if (chip->ecc.mode != NAND_ECC_HW) {
+ dev_err(ctrl->dev, "only HW ECC supported; selected: %d\n",
+ chip->ecc.mode);
+ return -EINVAL;
+ }
+
+ if (chip->ecc.algo == NAND_ECC_UNKNOWN) {
+ if (chip->ecc.strength == 1 && chip->ecc.size == 512)
+ /* Default to Hamming for 1-bit ECC, if unspecified */
+ chip->ecc.algo = NAND_ECC_HAMMING;
+ else
+ /* Otherwise, BCH */
+ chip->ecc.algo = NAND_ECC_BCH;
+ }
+
+ if (chip->ecc.algo == NAND_ECC_HAMMING && (chip->ecc.strength != 1 ||
+ chip->ecc.size != 512)) {
+ dev_err(ctrl->dev, "invalid Hamming params: %d bits per %d bytes\n",
+ chip->ecc.strength, chip->ecc.size);
+ return -EINVAL;
+ }
+
+ switch (chip->ecc.size) {
+ case 512:
+ if (chip->ecc.algo == NAND_ECC_HAMMING)
+ cfg->ecc_level = 15;
+ else
+ cfg->ecc_level = chip->ecc.strength;
+ cfg->sector_size_1k = 0;
+ break;
+ case 1024:
+ if (!(ctrl->features & BRCMNAND_HAS_1K_SECTORS)) {
+ dev_err(ctrl->dev, "1KB sectors not supported\n");
+ return -EINVAL;
+ }
+ if (chip->ecc.strength & 0x1) {
+ dev_err(ctrl->dev,
+ "odd ECC not supported with 1KB sectors\n");
+ return -EINVAL;
+ }
+
+ cfg->ecc_level = chip->ecc.strength >> 1;
+ cfg->sector_size_1k = 1;
+ break;
+ default:
+ dev_err(ctrl->dev, "unsupported ECC size: %d\n",
+ chip->ecc.size);
+ return -EINVAL;
+ }
+
+ cfg->ful_adr_bytes = cfg->blk_adr_bytes;
+ if (mtd->writesize > 512)
+ cfg->ful_adr_bytes += cfg->col_adr_bytes;
+ else
+ cfg->ful_adr_bytes += 1;
+
+ ret = brcmnand_set_cfg(host, cfg);
+ if (ret)
+ return ret;
+
+ brcmnand_set_ecc_enabled(host, 1);
+
+ brcmnand_print_cfg(host, msg, cfg);
+ dev_info(ctrl->dev, "detected %s\n", msg);
+
+ /* Configure ACC_CONTROL */
+ offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);
+ tmp = nand_readreg(ctrl, offs);
+ tmp &= ~ACC_CONTROL_PARTIAL_PAGE;
+ tmp &= ~ACC_CONTROL_RD_ERASED;
+
+ /* We need to turn on Read from erased paged protected by ECC */
+ if (ctrl->nand_version >= 0x0702)
+ tmp |= ACC_CONTROL_RD_ERASED;
+ tmp &= ~ACC_CONTROL_FAST_PGM_RDIN;
+ if (ctrl->features & BRCMNAND_HAS_PREFETCH)
+ tmp &= ~ACC_CONTROL_PREFETCH;
+
+ nand_writereg(ctrl, offs, tmp);
+
+ return 0;
+}
+
+#ifndef __UBOOT__
+static int brcmnand_init_cs(struct brcmnand_host *host, struct device_node *dn)
+#else
+static int brcmnand_init_cs(struct brcmnand_host *host, ofnode dn)
+#endif
+{
+ struct brcmnand_controller *ctrl = host->ctrl;
+#ifndef __UBOOT__
+ struct platform_device *pdev = host->pdev;
+#else
+ struct udevice *pdev = host->pdev;
+#endif /* __UBOOT__ */
+ struct mtd_info *mtd;
+ struct nand_chip *chip;
+ int ret;
+ u16 cfg_offs;
+
+#ifndef __UBOOT__
+ ret = of_property_read_u32(dn, "reg", &host->cs);
+#else
+ ret = ofnode_read_s32(dn, "reg", &host->cs);
+#endif
+ if (ret) {
+ dev_err(&pdev->dev, "can't get chip-select\n");
+ return -ENXIO;
+ }
+
+ mtd = nand_to_mtd(&host->chip);
+ chip = &host->chip;
+
+ nand_set_flash_node(chip, dn);
+ nand_set_controller_data(chip, host);
+#ifndef __UBOOT__
+ mtd->name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "brcmnand.%d",
+ host->cs);
+#else
+ mtd->name = devm_kasprintf(pdev, GFP_KERNEL, "brcmnand.%d",
+ host->cs);
+#endif /* __UBOOT__ */
+ if (!mtd->name)
+ return -ENOMEM;
+
+ mtd->owner = THIS_MODULE;
+#ifndef __UBOOT__
+ mtd->dev.parent = &pdev->dev;
+#else
+ mtd->dev->parent = pdev;
+#endif /* __UBOOT__ */
+
+ chip->IO_ADDR_R = (void __iomem *)0xdeadbeef;
+ chip->IO_ADDR_W = (void __iomem *)0xdeadbeef;
+
+ chip->cmd_ctrl = brcmnand_cmd_ctrl;
+ chip->cmdfunc = brcmnand_cmdfunc;
+ chip->waitfunc = brcmnand_waitfunc;
+ chip->read_byte = brcmnand_read_byte;
+ chip->read_buf = brcmnand_read_buf;
+ chip->write_buf = brcmnand_write_buf;
+
+ chip->ecc.mode = NAND_ECC_HW;
+ chip->ecc.read_page = brcmnand_read_page;
+ chip->ecc.write_page = brcmnand_write_page;
+ chip->ecc.read_page_raw = brcmnand_read_page_raw;
+ chip->ecc.write_page_raw = brcmnand_write_page_raw;
+ chip->ecc.write_oob_raw = brcmnand_write_oob_raw;
+ chip->ecc.read_oob_raw = brcmnand_read_oob_raw;
+ chip->ecc.read_oob = brcmnand_read_oob;
+ chip->ecc.write_oob = brcmnand_write_oob;
+
+ chip->controller = &ctrl->controller;
+
+ /*
+ * The bootloader might have configured 16bit mode but
+ * NAND READID command only works in 8bit mode. We force
+ * 8bit mode here to ensure that NAND READID commands works.
+ */
+ cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
+ nand_writereg(ctrl, cfg_offs,
+ nand_readreg(ctrl, cfg_offs) & ~CFG_BUS_WIDTH);
+
+ ret = nand_scan_ident(mtd, 1, NULL);
+ if (ret)
+ return ret;
+
+ chip->options |= NAND_NO_SUBPAGE_WRITE;
+ /*
+ * Avoid (for instance) kmap()'d buffers from JFFS2, which we can't DMA
+ * to/from, and have nand_base pass us a bounce buffer instead, as
+ * needed.
+ */
+ chip->options |= NAND_USE_BOUNCE_BUFFER;
+
+ if (chip->bbt_options & NAND_BBT_USE_FLASH)
+ chip->bbt_options |= NAND_BBT_NO_OOB;
+
+ if (brcmnand_setup_dev(host))
+ return -ENXIO;
+
+ chip->ecc.size = host->hwcfg.sector_size_1k ? 1024 : 512;
+ /* only use our internal HW threshold */
+ mtd->bitflip_threshold = 1;
+
+ ret = brcmstb_choose_ecc_layout(host);
+ if (ret)
+ return ret;
+
+ ret = nand_scan_tail(mtd);
+ if (ret)
+ return ret;
+
+#ifndef __UBOOT__
+ ret = mtd_device_register(mtd, NULL, 0);
+ if (ret)
+ nand_cleanup(chip);
+#else
+ ret = nand_register(0, mtd);
+#endif /* __UBOOT__ */
+
+ return ret;
+}
+
+#ifndef __UBOOT__
+static void brcmnand_save_restore_cs_config(struct brcmnand_host *host,
+ int restore)
+{
+ struct brcmnand_controller *ctrl = host->ctrl;
+ u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
+ u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,
+ BRCMNAND_CS_CFG_EXT);
+ u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
+ BRCMNAND_CS_ACC_CONTROL);
+ u16 t1_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING1);
+ u16 t2_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING2);
+
+ if (restore) {
+ nand_writereg(ctrl, cfg_offs, host->hwcfg.config);
+ if (cfg_offs != cfg_ext_offs)
+ nand_writereg(ctrl, cfg_ext_offs,
+ host->hwcfg.config_ext);
+ nand_writereg(ctrl, acc_control_offs, host->hwcfg.acc_control);
+ nand_writereg(ctrl, t1_offs, host->hwcfg.timing_1);
+ nand_writereg(ctrl, t2_offs, host->hwcfg.timing_2);
+ } else {
+ host->hwcfg.config = nand_readreg(ctrl, cfg_offs);
+ if (cfg_offs != cfg_ext_offs)
+ host->hwcfg.config_ext =
+ nand_readreg(ctrl, cfg_ext_offs);
+ host->hwcfg.acc_control = nand_readreg(ctrl, acc_control_offs);
+ host->hwcfg.timing_1 = nand_readreg(ctrl, t1_offs);
+ host->hwcfg.timing_2 = nand_readreg(ctrl, t2_offs);
+ }
+}
+
+static int brcmnand_suspend(struct device *dev)
+{
+ struct brcmnand_controller *ctrl = dev_get_drvdata(dev);
+ struct brcmnand_host *host;
+
+ list_for_each_entry(host, &ctrl->host_list, node)
+ brcmnand_save_restore_cs_config(host, 0);
+
+ ctrl->nand_cs_nand_select = brcmnand_read_reg(ctrl, BRCMNAND_CS_SELECT);
+ ctrl->nand_cs_nand_xor = brcmnand_read_reg(ctrl, BRCMNAND_CS_XOR);
+ ctrl->corr_stat_threshold =
+ brcmnand_read_reg(ctrl, BRCMNAND_CORR_THRESHOLD);
+
+ if (has_flash_dma(ctrl))
+ ctrl->flash_dma_mode = flash_dma_readl(ctrl, FLASH_DMA_MODE);
+
+ return 0;
+}
+
+static int brcmnand_resume(struct device *dev)
+{
+ struct brcmnand_controller *ctrl = dev_get_drvdata(dev);
+ struct brcmnand_host *host;
+
+ if (has_flash_dma(ctrl)) {
+ flash_dma_writel(ctrl, FLASH_DMA_MODE, ctrl->flash_dma_mode);
+ flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
+ }
+
+ brcmnand_write_reg(ctrl, BRCMNAND_CS_SELECT, ctrl->nand_cs_nand_select);
+ brcmnand_write_reg(ctrl, BRCMNAND_CS_XOR, ctrl->nand_cs_nand_xor);
+ brcmnand_write_reg(ctrl, BRCMNAND_CORR_THRESHOLD,
+ ctrl->corr_stat_threshold);
+ if (ctrl->soc) {
+ /* Clear/re-enable interrupt */
+ ctrl->soc->ctlrdy_ack(ctrl->soc);
+ ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
+ }
+
+ list_for_each_entry(host, &ctrl->host_list, node) {
+ struct nand_chip *chip = &host->chip;
+
+ brcmnand_save_restore_cs_config(host, 1);
+
+ /* Reset the chip, required by some chips after power-up */
+ nand_reset_op(chip);
+ }
+
+ return 0;
+}
+
+const struct dev_pm_ops brcmnand_pm_ops = {
+ .suspend = brcmnand_suspend,
+ .resume = brcmnand_resume,
+};
+EXPORT_SYMBOL_GPL(brcmnand_pm_ops);
+
+static const struct of_device_id brcmnand_of_match[] = {
+ { .compatible = "brcm,brcmnand-v4.0" },
+ { .compatible = "brcm,brcmnand-v5.0" },
+ { .compatible = "brcm,brcmnand-v6.0" },
+ { .compatible = "brcm,brcmnand-v6.1" },
+ { .compatible = "brcm,brcmnand-v6.2" },
+ { .compatible = "brcm,brcmnand-v7.0" },
+ { .compatible = "brcm,brcmnand-v7.1" },
+ { .compatible = "brcm,brcmnand-v7.2" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, brcmnand_of_match);
+#endif /* __UBOOT__ */
+
+/***********************************************************************
+ * Platform driver setup (per controller)
+ ***********************************************************************/
+
+#ifndef __UBOOT__
+int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
+#else
+int brcmnand_probe(struct udevice *dev, struct brcmnand_soc *soc)
+#endif /* __UBOOT__ */
+{
+#ifndef __UBOOT__
+ struct device *dev = &pdev->dev;
+ struct device_node *dn = dev->of_node, *child;
+#else
+ ofnode child;
+ struct udevice *pdev = dev;
+#endif /* __UBOOT__ */
+ struct brcmnand_controller *ctrl;
+#ifndef __UBOOT__
+ struct resource *res;
+#else
+ struct resource res;
+#endif /* __UBOOT__ */
+ int ret;
+
+#ifndef __UBOOT__
+ /* We only support device-tree instantiation */
+ if (!dn)
+ return -ENODEV;
+
+ if (!of_match_node(brcmnand_of_match, dn))
+ return -ENODEV;
+#endif /* __UBOOT__ */
+
+ ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
+ if (!ctrl)
+ return -ENOMEM;
+
+#ifndef __UBOOT__
+ dev_set_drvdata(dev, ctrl);
+#else
+ /*
+ * in u-boot, the data for the driver is allocated before probing
+ * so to keep the reference to ctrl, we store it in the variable soc
+ */
+ soc->ctrl = ctrl;
+#endif /* __UBOOT__ */
+ ctrl->dev = dev;
+
+ init_completion(&ctrl->done);
+ init_completion(&ctrl->dma_done);
+ nand_hw_control_init(&ctrl->controller);
+ INIT_LIST_HEAD(&ctrl->host_list);
+
+ /* Is parameter page in big endian ? */
+ ctrl->parameter_page_big_endian =
+ dev_read_u32_default(dev, "parameter-page-big-endian", 1);
+
+ /* NAND register range */
+#ifndef __UBOOT__
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ ctrl->nand_base = devm_ioremap_resource(dev, res);
+#else
+ dev_read_resource(pdev, 0, &res);
+ ctrl->nand_base = devm_ioremap(pdev, res.start, resource_size(&res));
+#endif
+ if (IS_ERR(ctrl->nand_base))
+ return PTR_ERR(ctrl->nand_base);
+
+ /* Enable clock before using NAND registers */
+ ctrl->clk = devm_clk_get(dev, "nand");
+ if (!IS_ERR(ctrl->clk)) {
+ ret = clk_prepare_enable(ctrl->clk);
+ if (ret)
+ return ret;
+ } else {
+ ret = PTR_ERR(ctrl->clk);
+ if (ret == -EPROBE_DEFER)
+ return ret;
+
+ ctrl->clk = NULL;
+ }
+
+ /* Initialize NAND revision */
+ ret = brcmnand_revision_init(ctrl);
+ if (ret)
+ goto err;
+
+ /*
+ * Most chips have this cache at a fixed offset within 'nand' block.
+ * Some must specify this region separately.
+ */
+#ifndef __UBOOT__
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-cache");
+ if (res) {
+ ctrl->nand_fc = devm_ioremap_resource(dev, res);
+ if (IS_ERR(ctrl->nand_fc)) {
+ ret = PTR_ERR(ctrl->nand_fc);
+ goto err;
+ }
+ } else {
+ ctrl->nand_fc = ctrl->nand_base +
+ ctrl->reg_offsets[BRCMNAND_FC_BASE];
+ }
+#else
+ if (!dev_read_resource_byname(pdev, "nand-cache", &res)) {
+ ctrl->nand_fc = devm_ioremap(dev, res.start,
+ resource_size(&res));
+ if (IS_ERR(ctrl->nand_fc)) {
+ ret = PTR_ERR(ctrl->nand_fc);
+ goto err;
+ }
+ } else {
+ ctrl->nand_fc = ctrl->nand_base +
+ ctrl->reg_offsets[BRCMNAND_FC_BASE];
+ }
+#endif
+
+#ifndef __UBOOT__
+ /* FLASH_DMA */
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-dma");
+ if (res) {
+ ctrl->flash_dma_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(ctrl->flash_dma_base)) {
+ ret = PTR_ERR(ctrl->flash_dma_base);
+ goto err;
+ }
+
+ flash_dma_writel(ctrl, FLASH_DMA_MODE, 1); /* linked-list */
+ flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
+
+ /* Allocate descriptor(s) */
+ ctrl->dma_desc = dmam_alloc_coherent(dev,
+ sizeof(*ctrl->dma_desc),
+ &ctrl->dma_pa, GFP_KERNEL);
+ if (!ctrl->dma_desc) {
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ ctrl->dma_irq = platform_get_irq(pdev, 1);
+ if ((int)ctrl->dma_irq < 0) {
+ dev_err(dev, "missing FLASH_DMA IRQ\n");
+ ret = -ENODEV;
+ goto err;
+ }
+
+ ret = devm_request_irq(dev, ctrl->dma_irq,
+ brcmnand_dma_irq, 0, DRV_NAME,
+ ctrl);
+ if (ret < 0) {
+ dev_err(dev, "can't allocate IRQ %d: error %d\n",
+ ctrl->dma_irq, ret);
+ goto err;
+ }
+
+ dev_info(dev, "enabling FLASH_DMA\n");
+ }
+#endif /* __UBOOT__ */
+
+ /* Disable automatic device ID config, direct addressing */
+ brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT,
+ CS_SELECT_AUTO_DEVICE_ID_CFG | 0xff, 0, 0);
+ /* Disable XOR addressing */
+ brcmnand_rmw_reg(ctrl, BRCMNAND_CS_XOR, 0xff, 0, 0);
+
+ /* Read the write-protect configuration in the device tree */
+ wp_on = dev_read_u32_default(dev, "write-protect", wp_on);
+
+ if (ctrl->features & BRCMNAND_HAS_WP) {
+ /* Permanently disable write protection */
+ if (wp_on == 2)
+ brcmnand_set_wp(ctrl, false);
+ } else {
+ wp_on = 0;
+ }
+
+#ifndef __UBOOT__
+ /* IRQ */
+ ctrl->irq = platform_get_irq(pdev, 0);
+ if ((int)ctrl->irq < 0) {
+ dev_err(dev, "no IRQ defined\n");
+ ret = -ENODEV;
+ goto err;
+ }
+
+ /*
+ * Some SoCs integrate this controller (e.g., its interrupt bits) in
+ * interesting ways
+ */
+ if (soc) {
+ ctrl->soc = soc;
+
+ ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0,
+ DRV_NAME, ctrl);
+
+ /* Enable interrupt */
+ ctrl->soc->ctlrdy_ack(ctrl->soc);
+ ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
+ } else {
+ /* Use standard interrupt infrastructure */
+ ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0,
+ DRV_NAME, ctrl);
+ }
+ if (ret < 0) {
+ dev_err(dev, "can't allocate IRQ %d: error %d\n",
+ ctrl->irq, ret);
+ goto err;
+ }
+#endif /* __UBOOT__ */
+
+#ifndef __UBOOT__
+ for_each_available_child_of_node(dn, child) {
+ if (of_device_is_compatible(child, "brcm,nandcs")) {
+ struct brcmnand_host *host;
+
+ host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
+ if (!host) {
+ of_node_put(child);
+ ret = -ENOMEM;
+ goto err;
+ }
+ host->pdev = pdev;
+ host->ctrl = ctrl;
+
+ ret = brcmnand_init_cs(host, child);
+ if (ret) {
+ devm_kfree(dev, host);
+ continue; /* Try all chip-selects */
+ }
+
+ list_add_tail(&host->node, &ctrl->host_list);
+ }
+ }
+#else
+ ofnode_for_each_subnode(child, dev_ofnode(dev)) {
+ if (ofnode_device_is_compatible(child, "brcm,nandcs")) {
+ struct brcmnand_host *host;
+
+ host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
+ if (!host) {
+ ret = -ENOMEM;
+ goto err;
+ }
+ host->pdev = pdev;
+ host->ctrl = ctrl;
+
+ ret = brcmnand_init_cs(host, child);
+ if (ret) {
+ devm_kfree(dev, host);
+ continue; /* Try all chip-selects */
+ }
+
+ list_add_tail(&host->node, &ctrl->host_list);
+ }
+ }
+#endif /* __UBOOT__ */
+
+err:
+#ifndef __UBOOT__
+ clk_disable_unprepare(ctrl->clk);
+#else
+ if (ctrl->clk)
+ clk_disable(ctrl->clk);
+#endif /* __UBOOT__ */
+ return ret;
+
+}
+EXPORT_SYMBOL_GPL(brcmnand_probe);
+
+#ifndef __UBOOT__
+int brcmnand_remove(struct platform_device *pdev)
+{
+ struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev);
+ struct brcmnand_host *host;
+
+ list_for_each_entry(host, &ctrl->host_list, node)
+ nand_release(nand_to_mtd(&host->chip));
+
+ clk_disable_unprepare(ctrl->clk);
+
+ dev_set_drvdata(&pdev->dev, NULL);
+
+ return 0;
+}
+#else
+int brcmnand_remove(struct udevice *pdev)
+{
+ return 0;
+}
+#endif /* __UBOOT__ */
+EXPORT_SYMBOL_GPL(brcmnand_remove);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Kevin Cernekee");
+MODULE_AUTHOR("Brian Norris");
+MODULE_DESCRIPTION("NAND driver for Broadcom chips");
+MODULE_ALIAS("platform:brcmnand");
diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.h b/drivers/mtd/nand/raw/brcmnand/brcmnand.h
new file mode 100644
index 0000000..6946a62
--- /dev/null
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __BRCMNAND_H__
+#define __BRCMNAND_H__
+
+#include <linux/types.h>
+#include <linux/io.h>
+
+struct brcmnand_soc {
+ bool (*ctlrdy_ack)(struct brcmnand_soc *soc);
+ void (*ctlrdy_set_enabled)(struct brcmnand_soc *soc, bool en);
+ void (*prepare_data_bus)(struct brcmnand_soc *soc, bool prepare,
+ bool is_param);
+ void *ctrl;
+};
+
+static inline void brcmnand_soc_data_bus_prepare(struct brcmnand_soc *soc,
+ bool is_param)
+{
+ if (soc && soc->prepare_data_bus)
+ soc->prepare_data_bus(soc, true, is_param);
+}
+
+static inline void brcmnand_soc_data_bus_unprepare(struct brcmnand_soc *soc,
+ bool is_param)
+{
+ if (soc && soc->prepare_data_bus)
+ soc->prepare_data_bus(soc, false, is_param);
+}
+
+static inline u32 brcmnand_readl(void __iomem *addr)
+{
+ /*
+ * MIPS endianness is configured by boot strap, which also reverses all
+ * bus endianness (i.e., big-endian CPU + big endian bus ==> native
+ * endian I/O).
+ *
+ * Other architectures (e.g., ARM) either do not support big endian, or
+ * else leave I/O in little endian mode.
+ */
+ if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_SYS_BIG_ENDIAN))
+ return __raw_readl(addr);
+ else
+ return readl_relaxed(addr);
+}
+
+static inline void brcmnand_writel(u32 val, void __iomem *addr)
+{
+ /* See brcmnand_readl() comments */
+ if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_SYS_BIG_ENDIAN))
+ __raw_writel(val, addr);
+ else
+ writel_relaxed(val, addr);
+}
+
+int brcmnand_probe(struct udevice *dev, struct brcmnand_soc *soc);
+int brcmnand_remove(struct udevice *dev);
+
+#ifndef __UBOOT__
+extern const struct dev_pm_ops brcmnand_pm_ops;
+#endif /* __UBOOT__ */
+
+#endif /* __BRCMNAND_H__ */
diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand_compat.c b/drivers/mtd/nand/raw/brcmnand/brcmnand_compat.c
new file mode 100644
index 0000000..96b27e6
--- /dev/null
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand_compat.c
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include "brcmnand_compat.h"
+
+struct clk *devm_clk_get(struct udevice *dev, const char *id)
+{
+ struct clk *clk;
+ int ret;
+
+ clk = devm_kzalloc(dev, sizeof(*clk), GFP_KERNEL);
+ if (!clk) {
+ debug("%s: can't allocate clock\n", __func__);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ ret = clk_get_by_name(dev, id, clk);
+ if (ret < 0) {
+ debug("%s: can't get clock (ret = %d)!\n", __func__, ret);
+ return ERR_PTR(ret);
+ }
+
+ return clk;
+}
+
+int clk_prepare_enable(struct clk *clk)
+{
+ return clk_enable(clk);
+}
+
+void clk_disable_unprepare(struct clk *clk)
+{
+ clk_disable(clk);
+}
+
+static char *devm_kvasprintf(struct udevice *dev, gfp_t gfp, const char *fmt,
+ va_list ap)
+{
+ unsigned int len;
+ char *p;
+ va_list aq;
+
+ va_copy(aq, ap);
+ len = vsnprintf(NULL, 0, fmt, aq);
+ va_end(aq);
+
+ p = devm_kmalloc(dev, len + 1, gfp);
+ if (!p)
+ return NULL;
+
+ vsnprintf(p, len + 1, fmt, ap);
+
+ return p;
+}
+
+char *devm_kasprintf(struct udevice *dev, gfp_t gfp, const char *fmt, ...)
+{
+ va_list ap;
+ char *p;
+
+ va_start(ap, fmt);
+ p = devm_kvasprintf(dev, gfp, fmt, ap);
+ va_end(ap);
+
+ return p;
+}
diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand_compat.h b/drivers/mtd/nand/raw/brcmnand/brcmnand_compat.h
new file mode 100644
index 0000000..02cab0f
--- /dev/null
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand_compat.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __BRCMNAND_COMPAT_H
+#define __BRCMNAND_COMPAT_H
+
+#include <clk.h>
+#include <dm.h>
+
+struct clk *devm_clk_get(struct udevice *dev, const char *id);
+int clk_prepare_enable(struct clk *clk);
+void clk_disable_unprepare(struct clk *clk);
+
+char *devm_kasprintf(struct udevice *dev, gfp_t gfp, const char *fmt, ...);
+
+#endif /* __BRCMNAND_COMPAT_H */
diff --git a/drivers/mtd/nand/raw/denali.h b/drivers/mtd/nand/raw/denali.h
index 019deda..63ae828 100644
--- a/drivers/mtd/nand/raw/denali.h
+++ b/drivers/mtd/nand/raw/denali.h
@@ -10,6 +10,7 @@
#include <linux/bitops.h>
#include <linux/mtd/rawnand.h>
#include <linux/types.h>
+#include <reset.h>
#define DEVICE_RESET 0x0
#define DEVICE_RESET__BANK(bank) BIT(bank)
@@ -315,6 +316,7 @@
void (*host_write)(struct denali_nand_info *denali, u32 addr, u32 data);
void (*setup_dma)(struct denali_nand_info *denali, dma_addr_t dma_addr,
int page, int write);
+ struct reset_ctl_bulk resets;
};
#define DENALI_CAP_HW_ECC_FIXUP BIT(0)
diff --git a/drivers/mtd/nand/raw/denali_dt.c b/drivers/mtd/nand/raw/denali_dt.c
index d384b97..0ce8132 100644
--- a/drivers/mtd/nand/raw/denali_dt.c
+++ b/drivers/mtd/nand/raw/denali_dt.c
@@ -131,15 +131,30 @@
denali->clk_x_rate = 200000000;
}
+ ret = reset_get_bulk(dev, &denali->resets);
+ if (ret)
+ dev_warn(dev, "Can't get reset: %d\n", ret);
+ else
+ reset_deassert_bulk(&denali->resets);
+
return denali_init(denali);
}
+static int denali_dt_remove(struct udevice *dev)
+{
+ struct denali_nand_info *denali = dev_get_priv(dev);
+
+ return reset_release_bulk(&denali->resets);
+}
+
U_BOOT_DRIVER(denali_nand_dt) = {
.name = "denali-nand-dt",
.id = UCLASS_MISC,
.of_match = denali_nand_dt_ids,
.probe = denali_dt_probe,
.priv_auto_alloc_size = sizeof(struct denali_nand_info),
+ .remove = denali_dt_remove,
+ .flags = DM_FLAG_OS_PREPARE,
};
void board_nand_init(void)
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index 6d2ff58..e07bd6b 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -486,14 +486,19 @@
static int nand_check_wp(struct mtd_info *mtd)
{
struct nand_chip *chip = mtd_to_nand(mtd);
+ u8 status;
+ int ret;
/* Broken xD cards report WP despite being writable */
if (chip->options & NAND_BROKEN_XD)
return 0;
/* Check the WP bit */
- chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
- return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
+ ret = nand_status_op(chip, &status);
+ if (ret)
+ return ret;
+
+ return status & NAND_STATUS_WP ? 0 : 1;
}
/**
@@ -575,11 +580,18 @@
{
register struct nand_chip *chip = mtd_to_nand(mtd);
u32 time_start;
+ int ret;
timeo = (CONFIG_SYS_HZ * timeo) / 1000;
time_start = get_timer(0);
while (get_timer(time_start) < timeo) {
- if ((chip->read_byte(mtd) & NAND_STATUS_READY))
+ u8 status;
+
+ ret = nand_read_data_op(chip, &status, sizeof(status), true);
+ if (ret)
+ return;
+
+ if (status & NAND_STATUS_READY)
break;
WATCHDOG_RESET();
}
@@ -851,7 +863,15 @@
if (chip->dev_ready(mtd))
break;
} else {
- if (chip->read_byte(mtd) & NAND_STATUS_READY)
+ int ret;
+ u8 status;
+
+ ret = nand_read_data_op(chip, &status, sizeof(status),
+ true);
+ if (ret)
+ return;
+
+ if (status & NAND_STATUS_READY)
break;
}
mdelay(1);
@@ -867,8 +887,9 @@
*/
static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
{
- int status;
unsigned long timeo = 400;
+ u8 status;
+ int ret;
led_trigger_event(nand_led_trigger, LED_FULL);
@@ -878,7 +899,9 @@
*/
ndelay(100);
- chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
+ ret = nand_status_op(chip, NULL);
+ if (ret)
+ return ret;
u32 timer = (CONFIG_SYS_HZ * timeo) / 1000;
u32 time_start;
@@ -889,13 +912,21 @@
if (chip->dev_ready(mtd))
break;
} else {
- if (chip->read_byte(mtd) & NAND_STATUS_READY)
+ ret = nand_read_data_op(chip, &status,
+ sizeof(status), true);
+ if (ret)
+ return ret;
+
+ if (status & NAND_STATUS_READY)
break;
}
}
led_trigger_event(nand_led_trigger, LED_OFF);
+ ret = nand_read_data_op(chip, &status, sizeof(status), true);
+ if (ret)
+ return ret;
+
- status = (int)chip->read_byte(mtd);
/* This can happen if in case of timeout or buggy dev_ready */
WARN_ON(!(status & NAND_STATUS_READY));
return status;
@@ -1048,6 +1079,516 @@
}
/**
+ * nand_read_page_op - Do a READ PAGE operation
+ * @chip: The NAND chip
+ * @page: page to read
+ * @offset_in_page: offset within the page
+ * @buf: buffer used to store the data
+ * @len: length of the buffer
+ *
+ * This function issues a READ PAGE operation.
+ * This function does not select/unselect the CS line.
+ *
+ * Returns 0 on success, a negative error code otherwise.
+ */
+int nand_read_page_op(struct nand_chip *chip, unsigned int page,
+ unsigned int offset_in_page, void *buf, unsigned int len)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+
+ if (len && !buf)
+ return -EINVAL;
+
+ if (offset_in_page + len > mtd->writesize + mtd->oobsize)
+ return -EINVAL;
+
+ chip->cmdfunc(mtd, NAND_CMD_READ0, offset_in_page, page);
+ if (len)
+ chip->read_buf(mtd, buf, len);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(nand_read_page_op);
+
+/**
+ * nand_read_param_page_op - Do a READ PARAMETER PAGE operation
+ * @chip: The NAND chip
+ * @page: parameter page to read
+ * @buf: buffer used to store the data
+ * @len: length of the buffer
+ *
+ * This function issues a READ PARAMETER PAGE operation.
+ * This function does not select/unselect the CS line.
+ *
+ * Returns 0 on success, a negative error code otherwise.
+ */
+static int nand_read_param_page_op(struct nand_chip *chip, u8 page, void *buf,
+ unsigned int len)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+ unsigned int i;
+ u8 *p = buf;
+
+ if (len && !buf)
+ return -EINVAL;
+
+ chip->cmdfunc(mtd, NAND_CMD_PARAM, page, -1);
+ for (i = 0; i < len; i++)
+ p[i] = chip->read_byte(mtd);
+
+ return 0;
+}
+
+/**
+ * nand_change_read_column_op - Do a CHANGE READ COLUMN operation
+ * @chip: The NAND chip
+ * @offset_in_page: offset within the page
+ * @buf: buffer used to store the data
+ * @len: length of the buffer
+ * @force_8bit: force 8-bit bus access
+ *
+ * This function issues a CHANGE READ COLUMN operation.
+ * This function does not select/unselect the CS line.
+ *
+ * Returns 0 on success, a negative error code otherwise.
+ */
+int nand_change_read_column_op(struct nand_chip *chip,
+ unsigned int offset_in_page, void *buf,
+ unsigned int len, bool force_8bit)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+
+ if (len && !buf)
+ return -EINVAL;
+
+ if (offset_in_page + len > mtd->writesize + mtd->oobsize)
+ return -EINVAL;
+
+ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset_in_page, -1);
+ if (len)
+ chip->read_buf(mtd, buf, len);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(nand_change_read_column_op);
+
+/**
+ * nand_read_oob_op - Do a READ OOB operation
+ * @chip: The NAND chip
+ * @page: page to read
+ * @offset_in_oob: offset within the OOB area
+ * @buf: buffer used to store the data
+ * @len: length of the buffer
+ *
+ * This function issues a READ OOB operation.
+ * This function does not select/unselect the CS line.
+ *
+ * Returns 0 on success, a negative error code otherwise.
+ */
+int nand_read_oob_op(struct nand_chip *chip, unsigned int page,
+ unsigned int offset_in_oob, void *buf, unsigned int len)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+
+ if (len && !buf)
+ return -EINVAL;
+
+ if (offset_in_oob + len > mtd->oobsize)
+ return -EINVAL;
+
+ chip->cmdfunc(mtd, NAND_CMD_READOOB, offset_in_oob, page);
+ if (len)
+ chip->read_buf(mtd, buf, len);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(nand_read_oob_op);
+
+/**
+ * nand_prog_page_begin_op - starts a PROG PAGE operation
+ * @chip: The NAND chip
+ * @page: page to write
+ * @offset_in_page: offset within the page
+ * @buf: buffer containing the data to write to the page
+ * @len: length of the buffer
+ *
+ * This function issues the first half of a PROG PAGE operation.
+ * This function does not select/unselect the CS line.
+ *
+ * Returns 0 on success, a negative error code otherwise.
+ */
+int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page,
+ unsigned int offset_in_page, const void *buf,
+ unsigned int len)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+
+ if (len && !buf)
+ return -EINVAL;
+
+ if (offset_in_page + len > mtd->writesize + mtd->oobsize)
+ return -EINVAL;
+
+ chip->cmdfunc(mtd, NAND_CMD_SEQIN, offset_in_page, page);
+
+ if (buf)
+ chip->write_buf(mtd, buf, len);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(nand_prog_page_begin_op);
+
+/**
+ * nand_prog_page_end_op - ends a PROG PAGE operation
+ * @chip: The NAND chip
+ *
+ * This function issues the second half of a PROG PAGE operation.
+ * This function does not select/unselect the CS line.
+ *
+ * Returns 0 on success, a negative error code otherwise.
+ */
+int nand_prog_page_end_op(struct nand_chip *chip)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+ int status;
+
+ chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+
+ status = chip->waitfunc(mtd, chip);
+ if (status & NAND_STATUS_FAIL)
+ return -EIO;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(nand_prog_page_end_op);
+
+/**
+ * nand_prog_page_op - Do a full PROG PAGE operation
+ * @chip: The NAND chip
+ * @page: page to write
+ * @offset_in_page: offset within the page
+ * @buf: buffer containing the data to write to the page
+ * @len: length of the buffer
+ *
+ * This function issues a full PROG PAGE operation.
+ * This function does not select/unselect the CS line.
+ *
+ * Returns 0 on success, a negative error code otherwise.
+ */
+int nand_prog_page_op(struct nand_chip *chip, unsigned int page,
+ unsigned int offset_in_page, const void *buf,
+ unsigned int len)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+ int status;
+
+ if (!len || !buf)
+ return -EINVAL;
+
+ if (offset_in_page + len > mtd->writesize + mtd->oobsize)
+ return -EINVAL;
+
+ chip->cmdfunc(mtd, NAND_CMD_SEQIN, offset_in_page, page);
+ chip->write_buf(mtd, buf, len);
+ chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+
+ status = chip->waitfunc(mtd, chip);
+ if (status & NAND_STATUS_FAIL)
+ return -EIO;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(nand_prog_page_op);
+
+/**
+ * nand_change_write_column_op - Do a CHANGE WRITE COLUMN operation
+ * @chip: The NAND chip
+ * @offset_in_page: offset within the page
+ * @buf: buffer containing the data to send to the NAND
+ * @len: length of the buffer
+ * @force_8bit: force 8-bit bus access
+ *
+ * This function issues a CHANGE WRITE COLUMN operation.
+ * This function does not select/unselect the CS line.
+ *
+ * Returns 0 on success, a negative error code otherwise.
+ */
+int nand_change_write_column_op(struct nand_chip *chip,
+ unsigned int offset_in_page,
+ const void *buf, unsigned int len,
+ bool force_8bit)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+
+ if (len && !buf)
+ return -EINVAL;
+
+ if (offset_in_page + len > mtd->writesize + mtd->oobsize)
+ return -EINVAL;
+
+ chip->cmdfunc(mtd, NAND_CMD_RNDIN, offset_in_page, -1);
+ if (len)
+ chip->write_buf(mtd, buf, len);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(nand_change_write_column_op);
+
+/**
+ * nand_readid_op - Do a READID operation
+ * @chip: The NAND chip
+ * @addr: address cycle to pass after the READID command
+ * @buf: buffer used to store the ID
+ * @len: length of the buffer
+ *
+ * This function sends a READID command and reads back the ID returned by the
+ * NAND.
+ * This function does not select/unselect the CS line.
+ *
+ * Returns 0 on success, a negative error code otherwise.
+ */
+int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf,
+ unsigned int len)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+ unsigned int i;
+ u8 *id = buf;
+
+ if (len && !buf)
+ return -EINVAL;
+
+ chip->cmdfunc(mtd, NAND_CMD_READID, addr, -1);
+
+ for (i = 0; i < len; i++)
+ id[i] = chip->read_byte(mtd);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(nand_readid_op);
+
+/**
+ * nand_status_op - Do a STATUS operation
+ * @chip: The NAND chip
+ * @status: out variable to store the NAND status
+ *
+ * This function sends a STATUS command and reads back the status returned by
+ * the NAND.
+ * This function does not select/unselect the CS line.
+ *
+ * Returns 0 on success, a negative error code otherwise.
+ */
+int nand_status_op(struct nand_chip *chip, u8 *status)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+
+ chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
+ if (status)
+ *status = chip->read_byte(mtd);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(nand_status_op);
+
+/**
+ * nand_exit_status_op - Exit a STATUS operation
+ * @chip: The NAND chip
+ *
+ * This function sends a READ0 command to cancel the effect of the STATUS
+ * command to avoid reading only the status until a new read command is sent.
+ *
+ * This function does not select/unselect the CS line.
+ *
+ * Returns 0 on success, a negative error code otherwise.
+ */
+int nand_exit_status_op(struct nand_chip *chip)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+
+ chip->cmdfunc(mtd, NAND_CMD_READ0, -1, -1);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(nand_exit_status_op);
+
+/**
+ * nand_erase_op - Do an erase operation
+ * @chip: The NAND chip
+ * @eraseblock: block to erase
+ *
+ * This function sends an ERASE command and waits for the NAND to be ready
+ * before returning.
+ * This function does not select/unselect the CS line.
+ *
+ * Returns 0 on success, a negative error code otherwise.
+ */
+int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+ unsigned int page = eraseblock <<
+ (chip->phys_erase_shift - chip->page_shift);
+ int status;
+
+ chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
+ chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
+
+ status = chip->waitfunc(mtd, chip);
+ if (status < 0)
+ return status;
+
+ if (status & NAND_STATUS_FAIL)
+ return -EIO;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(nand_erase_op);
+
+/**
+ * nand_set_features_op - Do a SET FEATURES operation
+ * @chip: The NAND chip
+ * @feature: feature id
+ * @data: 4 bytes of data
+ *
+ * This function sends a SET FEATURES command and waits for the NAND to be
+ * ready before returning.
+ * This function does not select/unselect the CS line.
+ *
+ * Returns 0 on success, a negative error code otherwise.
+ */
+static int nand_set_features_op(struct nand_chip *chip, u8 feature,
+ const void *data)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+ const u8 *params = data;
+ int i, status;
+
+ chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, feature, -1);
+ for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
+ chip->write_byte(mtd, params[i]);
+
+ status = chip->waitfunc(mtd, chip);
+ if (status & NAND_STATUS_FAIL)
+ return -EIO;
+
+ return 0;
+}
+
+/**
+ * nand_get_features_op - Do a GET FEATURES operation
+ * @chip: The NAND chip
+ * @feature: feature id
+ * @data: 4 bytes of data
+ *
+ * This function sends a GET FEATURES command and waits for the NAND to be
+ * ready before returning.
+ * This function does not select/unselect the CS line.
+ *
+ * Returns 0 on success, a negative error code otherwise.
+ */
+static int nand_get_features_op(struct nand_chip *chip, u8 feature,
+ void *data)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+ u8 *params = data;
+ int i;
+
+ chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, feature, -1);
+ for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
+ params[i] = chip->read_byte(mtd);
+
+ return 0;
+}
+
+/**
+ * nand_reset_op - Do a reset operation
+ * @chip: The NAND chip
+ *
+ * This function sends a RESET command and waits for the NAND to be ready
+ * before returning.
+ * This function does not select/unselect the CS line.
+ *
+ * Returns 0 on success, a negative error code otherwise.
+ */
+int nand_reset_op(struct nand_chip *chip)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+
+ chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(nand_reset_op);
+
+/**
+ * nand_read_data_op - Read data from the NAND
+ * @chip: The NAND chip
+ * @buf: buffer used to store the data
+ * @len: length of the buffer
+ * @force_8bit: force 8-bit bus access
+ *
+ * This function does a raw data read on the bus. Usually used after launching
+ * another NAND operation like nand_read_page_op().
+ * This function does not select/unselect the CS line.
+ *
+ * Returns 0 on success, a negative error code otherwise.
+ */
+int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len,
+ bool force_8bit)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+
+ if (!len || !buf)
+ return -EINVAL;
+
+ if (force_8bit) {
+ u8 *p = buf;
+ unsigned int i;
+
+ for (i = 0; i < len; i++)
+ p[i] = chip->read_byte(mtd);
+ } else {
+ chip->read_buf(mtd, buf, len);
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(nand_read_data_op);
+
+/**
+ * nand_write_data_op - Write data from the NAND
+ * @chip: The NAND chip
+ * @buf: buffer containing the data to send on the bus
+ * @len: length of the buffer
+ * @force_8bit: force 8-bit bus access
+ *
+ * This function does a raw data write on the bus. Usually used after launching
+ * another NAND operation like nand_write_page_begin_op().
+ * This function does not select/unselect the CS line.
+ *
+ * Returns 0 on success, a negative error code otherwise.
+ */
+int nand_write_data_op(struct nand_chip *chip, const void *buf,
+ unsigned int len, bool force_8bit)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+
+ if (!len || !buf)
+ return -EINVAL;
+
+ if (force_8bit) {
+ const u8 *p = buf;
+ unsigned int i;
+
+ for (i = 0; i < len; i++)
+ chip->write_byte(mtd, p[i]);
+ } else {
+ chip->write_buf(mtd, buf, len);
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(nand_write_data_op);
+
+/**
* nand_reset - Reset and initialize a NAND device
* @chip: The NAND chip
* @chipnr: Internal die id
@@ -1068,8 +1609,10 @@
* interface settings, hence this weird ->select_chip() dance.
*/
chip->select_chip(mtd, chipnr);
- chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+ ret = nand_reset_op(chip);
chip->select_chip(mtd, -1);
+ if (ret)
+ return ret;
chip->select_chip(mtd, chipnr);
ret = nand_setup_data_interface(chip, chipnr);
@@ -1220,9 +1763,19 @@
static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
uint8_t *buf, int oob_required, int page)
{
- chip->read_buf(mtd, buf, mtd->writesize);
- if (oob_required)
- chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
+ int ret;
+
+ ret = nand_read_data_op(chip, buf, mtd->writesize, false);
+ if (ret)
+ return ret;
+
+ if (oob_required) {
+ ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize,
+ false);
+ if (ret)
+ return ret;
+ }
+
return 0;
}
@@ -1243,29 +1796,46 @@
int eccsize = chip->ecc.size;
int eccbytes = chip->ecc.bytes;
uint8_t *oob = chip->oob_poi;
- int steps, size;
+ int steps, size, ret;
for (steps = chip->ecc.steps; steps > 0; steps--) {
- chip->read_buf(mtd, buf, eccsize);
+ ret = nand_read_data_op(chip, buf, eccsize, false);
+ if (ret)
+ return ret;
+
buf += eccsize;
if (chip->ecc.prepad) {
- chip->read_buf(mtd, oob, chip->ecc.prepad);
+ ret = nand_read_data_op(chip, oob, chip->ecc.prepad,
+ false);
+ if (ret)
+ return ret;
+
oob += chip->ecc.prepad;
}
+ ret = nand_read_data_op(chip, oob, eccbytes, false);
+ if (ret)
+ return ret;
+
- chip->read_buf(mtd, oob, eccbytes);
oob += eccbytes;
if (chip->ecc.postpad) {
- chip->read_buf(mtd, oob, chip->ecc.postpad);
+ ret = nand_read_data_op(chip, oob, chip->ecc.postpad,
+ false);
+ if (ret)
+ return ret;
+
oob += chip->ecc.postpad;
}
}
size = mtd->oobsize - (oob - chip->oob_poi);
- if (size)
- chip->read_buf(mtd, oob, size);
+ if (size) {
+ ret = nand_read_data_op(chip, oob, size, false);
+ if (ret)
+ return ret;
+ }
return 0;
}
@@ -1336,6 +1906,7 @@
int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
int index;
unsigned int max_bitflips = 0;
+ int ret;
/* Column address within the page aligned to ECC size (256bytes) */
start_step = data_offs / chip->ecc.size;
@@ -1353,7 +1924,9 @@
chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
p = bufpoi + data_col_addr;
- chip->read_buf(mtd, p, datafrag_len);
+ ret = nand_read_data_op(chip, p, datafrag_len, false);
+ if (ret)
+ return ret;
/* Calculate ECC */
for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
@@ -1370,8 +1943,11 @@
}
}
if (gaps) {
- chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
- chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
+ ret = nand_change_read_column_op(chip, mtd->writesize,
+ chip->oob_poi, mtd->oobsize,
+ false);
+ if (ret)
+ return ret;
} else {
/*
* Send the command to read the particular ECC bytes take care
@@ -1384,9 +1960,12 @@
if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
aligned_len++;
- chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
- mtd->writesize + aligned_pos, -1);
- chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
+ ret = nand_change_read_column_op(chip,
+ mtd->writesize + aligned_pos,
+ &chip->oob_poi[aligned_pos],
+ aligned_len, false);
+ if (ret)
+ return ret;
}
for (i = 0; i < eccfrag_len; i++)
@@ -1439,13 +2018,21 @@
uint8_t *ecc_code = chip->buffers->ecccode;
uint32_t *eccpos = chip->ecc.layout->eccpos;
unsigned int max_bitflips = 0;
+ int ret;
for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
chip->ecc.hwctl(mtd, NAND_ECC_READ);
- chip->read_buf(mtd, p, eccsize);
+
+ ret = nand_read_data_op(chip, p, eccsize, false);
+ if (ret)
+ return ret;
+
chip->ecc.calculate(mtd, p, &ecc_calc[i]);
}
- chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
+
+ ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, false);
+ if (ret)
+ return ret;
for (i = 0; i < chip->ecc.total; i++)
ecc_code[i] = chip->oob_poi[eccpos[i]];
@@ -1501,11 +2088,16 @@
uint32_t *eccpos = chip->ecc.layout->eccpos;
uint8_t *ecc_calc = chip->buffers->ecccalc;
unsigned int max_bitflips = 0;
+ int ret;
/* Read the OOB area first */
- chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
- chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
- chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
+ ret = nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
+ if (ret)
+ return ret;
+
+ ret = nand_read_page_op(chip, page, 0, NULL, 0);
+ if (ret)
+ return ret;
for (i = 0; i < chip->ecc.total; i++)
ecc_code[i] = chip->oob_poi[eccpos[i]];
@@ -1514,7 +2106,11 @@
int stat;
chip->ecc.hwctl(mtd, NAND_ECC_READ);
- chip->read_buf(mtd, p, eccsize);
+
+ ret = nand_read_data_op(chip, p, eccsize, false);
+ if (ret)
+ return ret;
+
chip->ecc.calculate(mtd, p, &ecc_calc[i]);
stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
@@ -1551,7 +2147,7 @@
static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
uint8_t *buf, int oob_required, int page)
{
- int i, eccsize = chip->ecc.size;
+ int ret, i, eccsize = chip->ecc.size;
int eccbytes = chip->ecc.bytes;
int eccsteps = chip->ecc.steps;
int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
@@ -1563,21 +2159,36 @@
int stat;
chip->ecc.hwctl(mtd, NAND_ECC_READ);
- chip->read_buf(mtd, p, eccsize);
+
+ ret = nand_read_data_op(chip, p, eccsize, false);
+ if (ret)
+ return ret;
if (chip->ecc.prepad) {
- chip->read_buf(mtd, oob, chip->ecc.prepad);
+ ret = nand_read_data_op(chip, oob, chip->ecc.prepad,
+ false);
+ if (ret)
+ return ret;
+
oob += chip->ecc.prepad;
}
chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
- chip->read_buf(mtd, oob, eccbytes);
+
+ ret = nand_read_data_op(chip, oob, eccbytes, false);
+ if (ret)
+ return ret;
+
stat = chip->ecc.correct(mtd, p, oob, NULL);
oob += eccbytes;
if (chip->ecc.postpad) {
- chip->read_buf(mtd, oob, chip->ecc.postpad);
+ ret = nand_read_data_op(chip, oob, chip->ecc.postpad,
+ false);
+ if (ret)
+ return ret;
+
oob += chip->ecc.postpad;
}
@@ -1601,8 +2212,11 @@
/* Calculate remaining oob bytes */
i = mtd->oobsize - (oob - chip->oob_poi);
- if (i)
- chip->read_buf(mtd, oob, i);
+ if (i) {
+ ret = nand_read_data_op(chip, oob, i, false);
+ if (ret)
+ return ret;
+ }
return max_bitflips;
}
@@ -1739,8 +2353,11 @@
__func__, buf);
read_retry:
- if (nand_standard_page_accessors(&chip->ecc))
- chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
+ if (nand_standard_page_accessors(&chip->ecc)) {
+ ret = nand_read_page_op(chip, page, 0, NULL, 0);
+ if (ret)
+ break;
+ }
/*
* Now read the page into the buffer. Absent an error,
@@ -1874,9 +2491,7 @@
static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
int page)
{
- chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
- chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
- return 0;
+ return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
}
/**
@@ -1893,25 +2508,43 @@
int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
int eccsize = chip->ecc.size;
uint8_t *bufpoi = chip->oob_poi;
- int i, toread, sndrnd = 0, pos;
+ int i, toread, sndrnd = 0, pos, ret;
- chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
+ ret = nand_read_page_op(chip, page, chip->ecc.size, NULL, 0);
+ if (ret)
+ return ret;
+
for (i = 0; i < chip->ecc.steps; i++) {
if (sndrnd) {
+ int ret;
+
pos = eccsize + i * (eccsize + chunk);
if (mtd->writesize > 512)
- chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
+ ret = nand_change_read_column_op(chip, pos,
+ NULL, 0,
+ false);
else
- chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
+ ret = nand_read_page_op(chip, page, pos, NULL,
+ 0);
+
+ if (ret)
+ return ret;
} else
sndrnd = 1;
toread = min_t(int, length, chunk);
- chip->read_buf(mtd, bufpoi, toread);
+
+ ret = nand_read_data_op(chip, bufpoi, toread, false);
+ if (ret)
+ return ret;
+
bufpoi += toread;
length -= toread;
}
+ if (length > 0) {
+ ret = nand_read_data_op(chip, bufpoi, length, false);
+ if (ret)
+ return ret;
+ }
- if (length > 0)
- chip->read_buf(mtd, bufpoi, length);
return 0;
}
@@ -1925,18 +2558,8 @@
static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
int page)
{
- int status = 0;
- const uint8_t *buf = chip->oob_poi;
- int length = mtd->oobsize;
-
- chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
- chip->write_buf(mtd, buf, length);
- /* Send command to program the OOB data */
- chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
-
- status = chip->waitfunc(mtd, chip);
-
- return status & NAND_STATUS_FAIL ? -EIO : 0;
+ return nand_prog_page_op(chip, page, mtd->writesize, chip->oob_poi,
+ mtd->oobsize);
}
/**
@@ -1951,7 +2574,7 @@
{
int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
int eccsize = chip->ecc.size, length = mtd->oobsize;
- int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
+ int ret, i, len, pos, sndcmd = 0, steps = chip->ecc.steps;
const uint8_t *bufpoi = chip->oob_poi;
/*
@@ -1965,7 +2588,10 @@
} else
pos = eccsize;
- chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
+ ret = nand_prog_page_begin_op(chip, page, pos, NULL, 0);
+ if (ret)
+ return ret;
+
for (i = 0; i < steps; i++) {
if (sndcmd) {
if (mtd->writesize <= 512) {
@@ -1974,28 +2600,40 @@
len = eccsize;
while (len > 0) {
int num = min_t(int, len, 4);
- chip->write_buf(mtd, (uint8_t *)&fill,
- num);
+
+ ret = nand_write_data_op(chip, &fill,
+ num, false);
+ if (ret)
+ return ret;
+
len -= num;
}
} else {
pos = eccsize + i * (eccsize + chunk);
- chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
+ ret = nand_change_write_column_op(chip, pos,
+ NULL, 0,
+ false);
+ if (ret)
+ return ret;
}
} else
sndcmd = 1;
len = min_t(int, length, chunk);
- chip->write_buf(mtd, bufpoi, len);
+
+ ret = nand_write_data_op(chip, bufpoi, len, false);
+ if (ret)
+ return ret;
+
bufpoi += len;
length -= len;
}
- if (length > 0)
- chip->write_buf(mtd, bufpoi, length);
-
- chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
- status = chip->waitfunc(mtd, chip);
+ if (length > 0) {
+ ret = nand_write_data_op(chip, bufpoi, length, false);
+ if (ret)
+ return ret;
+ }
- return status & NAND_STATUS_FAIL ? -EIO : 0;
+ return nand_prog_page_end_op(chip);
}
/**
@@ -2154,9 +2792,18 @@
static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
const uint8_t *buf, int oob_required, int page)
{
- chip->write_buf(mtd, buf, mtd->writesize);
- if (oob_required)
- chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
+ int ret;
+
+ ret = nand_write_data_op(chip, buf, mtd->writesize, false);
+ if (ret)
+ return ret;
+
+ if (oob_required) {
+ ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize,
+ false);
+ if (ret)
+ return ret;
+ }
return 0;
}
@@ -2179,29 +2826,46 @@
int eccsize = chip->ecc.size;
int eccbytes = chip->ecc.bytes;
uint8_t *oob = chip->oob_poi;
- int steps, size;
+ int steps, size, ret;
for (steps = chip->ecc.steps; steps > 0; steps--) {
- chip->write_buf(mtd, buf, eccsize);
+ ret = nand_write_data_op(chip, buf, eccsize, false);
+ if (ret)
+ return ret;
+
buf += eccsize;
if (chip->ecc.prepad) {
- chip->write_buf(mtd, oob, chip->ecc.prepad);
+ ret = nand_write_data_op(chip, oob, chip->ecc.prepad,
+ false);
+ if (ret)
+ return ret;
+
oob += chip->ecc.prepad;
}
- chip->write_buf(mtd, oob, eccbytes);
+ ret = nand_write_data_op(chip, oob, eccbytes, false);
+ if (ret)
+ return ret;
+
oob += eccbytes;
if (chip->ecc.postpad) {
- chip->write_buf(mtd, oob, chip->ecc.postpad);
+ ret = nand_write_data_op(chip, oob, chip->ecc.postpad,
+ false);
+ if (ret)
+ return ret;
+
oob += chip->ecc.postpad;
}
}
size = mtd->oobsize - (oob - chip->oob_poi);
- if (size)
- chip->write_buf(mtd, oob, size);
+ if (size) {
+ ret = nand_write_data_op(chip, oob, size, false);
+ if (ret)
+ return ret;
+ }
return 0;
}
@@ -2252,17 +2916,24 @@
uint8_t *ecc_calc = chip->buffers->ecccalc;
const uint8_t *p = buf;
uint32_t *eccpos = chip->ecc.layout->eccpos;
+ int ret;
for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
- chip->write_buf(mtd, p, eccsize);
+
+ ret = nand_write_data_op(chip, p, eccsize, false);
+ if (ret)
+ return ret;
+
chip->ecc.calculate(mtd, p, &ecc_calc[i]);
}
for (i = 0; i < chip->ecc.total; i++)
chip->oob_poi[eccpos[i]] = ecc_calc[i];
- chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
+ ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false);
+ if (ret)
+ return ret;
return 0;
}
@@ -2293,13 +2964,16 @@
uint32_t end_step = (offset + data_len - 1) / ecc_size;
int oob_bytes = mtd->oobsize / ecc_steps;
int step, i;
+ int ret;
for (step = 0; step < ecc_steps; step++) {
/* configure controller for WRITE access */
chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
/* write data (untouched subpages already masked by 0xFF) */
- chip->write_buf(mtd, buf, ecc_size);
+ ret = nand_write_data_op(chip, buf, ecc_size, false);
+ if (ret)
+ return ret;
/* mask ECC of un-touched subpages by padding 0xFF */
if ((step < start_step) || (step > end_step))
@@ -2324,7 +2998,9 @@
chip->oob_poi[eccpos[i]] = ecc_calc[i];
/* write OOB buffer to NAND device */
- chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
+ ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false);
+ if (ret)
+ return ret;
return 0;
}
@@ -2351,31 +3027,49 @@
int eccsteps = chip->ecc.steps;
const uint8_t *p = buf;
uint8_t *oob = chip->oob_poi;
+ int ret;
for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
-
chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
- chip->write_buf(mtd, p, eccsize);
+
+ ret = nand_write_data_op(chip, p, eccsize, false);
+ if (ret)
+ return ret;
if (chip->ecc.prepad) {
- chip->write_buf(mtd, oob, chip->ecc.prepad);
+ ret = nand_write_data_op(chip, oob, chip->ecc.prepad,
+ false);
+ if (ret)
+ return ret;
+
oob += chip->ecc.prepad;
}
chip->ecc.calculate(mtd, p, oob);
- chip->write_buf(mtd, oob, eccbytes);
+
+ ret = nand_write_data_op(chip, oob, eccbytes, false);
+ if (ret)
+ return ret;
+
oob += eccbytes;
if (chip->ecc.postpad) {
- chip->write_buf(mtd, oob, chip->ecc.postpad);
+ ret = nand_write_data_op(chip, oob, chip->ecc.postpad,
+ false);
+ if (ret)
+ return ret;
+
oob += chip->ecc.postpad;
}
}
/* Calculate remaining oob bytes */
i = mtd->oobsize - (oob - chip->oob_poi);
- if (i)
- chip->write_buf(mtd, oob, i);
+ if (i) {
+ ret = nand_write_data_op(chip, oob, i, false);
+ if (ret)
+ return ret;
+ }
return 0;
}
@@ -2403,8 +3097,11 @@
else
subpage = 0;
- if (nand_standard_page_accessors(&chip->ecc))
- chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
+ if (nand_standard_page_accessors(&chip->ecc)) {
+ status = nand_prog_page_begin_op(chip, page, 0, NULL, 0);
+ if (status)
+ return status;
+ }
if (unlikely(raw))
status = chip->ecc.write_page_raw(mtd, chip, buf,
@@ -2419,13 +3116,8 @@
if (status < 0)
return status;
- if (nand_standard_page_accessors(&chip->ecc)) {
- chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
-
- status = chip->waitfunc(mtd, chip);
- if (status & NAND_STATUS_FAIL)
- return -EIO;
- }
+ if (nand_standard_page_accessors(&chip->ecc))
+ return nand_prog_page_end_op(chip);
return 0;
}
@@ -2785,11 +3477,12 @@
static int single_erase(struct mtd_info *mtd, int page)
{
struct nand_chip *chip = mtd_to_nand(mtd);
+ unsigned int eraseblock;
+
/* Send commands to erase a block */
- chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
- chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
+ eraseblock = page >> (chip->phys_erase_shift - chip->page_shift);
- return chip->waitfunc(mtd, chip);
+ return nand_erase_op(chip, eraseblock);
}
/**
@@ -2982,9 +3675,6 @@
static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
int addr, uint8_t *subfeature_param)
{
- int status;
- int i;
-
#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
if (!chip->onfi_version ||
!(le16_to_cpu(chip->onfi_params.opt_cmd)
@@ -2992,14 +3682,7 @@
return -ENOTSUPP;
#endif
- chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
- for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
- chip->write_byte(mtd, subfeature_param[i]);
-
- status = chip->waitfunc(mtd, chip);
- if (status & NAND_STATUS_FAIL)
- return -EIO;
- return 0;
+ return nand_set_features_op(chip, addr, subfeature_param);
}
/**
@@ -3012,8 +3695,6 @@
static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
int addr, uint8_t *subfeature_param)
{
- int i;
-
#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
if (!chip->onfi_version ||
!(le16_to_cpu(chip->onfi_params.opt_cmd)
@@ -3021,10 +3702,7 @@
return -ENOTSUPP;
#endif
- chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
- for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
- *subfeature_param++ = chip->read_byte(mtd);
- return 0;
+ return nand_get_features_op(chip, addr, subfeature_param);
}
/* Set default functions */
@@ -3118,7 +3796,7 @@
struct onfi_ext_section *s;
struct onfi_ext_ecc_info *ecc;
uint8_t *cursor;
- int ret = -EINVAL;
+ int ret;
int len;
int i;
@@ -3128,14 +3806,18 @@
return -ENOMEM;
/* Send our own NAND_CMD_PARAM. */
- chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
+ ret = nand_read_param_page_op(chip, 0, NULL, 0);
+ if (ret)
+ goto ext_out;
/* Use the Change Read Column command to skip the ONFI param pages. */
- chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
- sizeof(*p) * p->num_of_param_pages , -1);
+ ret = nand_change_read_column_op(chip,
+ sizeof(*p) * p->num_of_param_pages,
+ ep, len, true);
+ if (ret)
+ goto ext_out;
- /* Read out the Extended Parameter Page. */
- chip->read_buf(mtd, (uint8_t *)ep, len);
+ ret = -EINVAL;
if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
!= le16_to_cpu(ep->crc))) {
pr_debug("fail in the CRC.\n");
@@ -3212,19 +3894,23 @@
int *busw)
{
struct nand_onfi_params *p = &chip->onfi_params;
- int i, j;
- int val;
+ char id[4];
+ int i, ret, val;
/* Try ONFI for unknown chip or LP */
- chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
- if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
- chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
+ ret = nand_readid_op(chip, 0x20, id, sizeof(id));
+ if (ret || strncmp(id, "ONFI", 4))
+ return 0;
+
+ ret = nand_read_param_page_op(chip, 0, NULL, 0);
+ if (ret)
return 0;
- chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
for (i = 0; i < 3; i++) {
- for (j = 0; j < sizeof(*p); j++)
- ((uint8_t *)p)[j] = chip->read_byte(mtd);
+ ret = nand_read_data_op(chip, p, sizeof(*p), true);
+ if (ret)
+ return 0;
+
if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
le16_to_cpu(p->crc)) {
break;
@@ -3324,20 +4010,22 @@
{
struct nand_jedec_params *p = &chip->jedec_params;
struct jedec_ecc_info *ecc;
- int val;
- int i, j;
+ char id[5];
+ int i, val, ret;
/* Try JEDEC for unknown chip or LP */
- chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1);
- if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' ||
- chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' ||
- chip->read_byte(mtd) != 'C')
+ ret = nand_readid_op(chip, 0x40, id, sizeof(id));
+ if (ret || strncmp(id, "JEDEC", sizeof(id)))
return 0;
- chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1);
+ ret = nand_read_param_page_op(chip, 0x40, NULL, 0);
+ if (ret)
+ return 0;
+
for (i = 0; i < 3; i++) {
- for (j = 0; j < sizeof(*p); j++)
- ((uint8_t *)p)[j] = chip->read_byte(mtd);
+ ret = nand_read_data_op(chip, p, sizeof(*p), true);
+ if (ret)
+ return 0;
if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) ==
le16_to_cpu(p->crc))
@@ -3708,25 +4396,29 @@
int *maf_id, int *dev_id,
struct nand_flash_dev *type)
{
- int busw;
- int i, maf_idx;
+ int busw, ret;
+ int maf_idx;
u8 id_data[8];
/*
* Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
* after power-up.
*/
- nand_reset(chip, 0);
+ ret = nand_reset(chip, 0);
+ if (ret)
+ return ERR_PTR(ret);
/* Select the device */
chip->select_chip(mtd, 0);
/* Send the command for reading device ID */
- chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
+ ret = nand_readid_op(chip, 0, id_data, 2);
+ if (ret)
+ return ERR_PTR(ret);
/* Read manufacturer and device IDs */
- *maf_id = chip->read_byte(mtd);
- *dev_id = chip->read_byte(mtd);
+ *maf_id = id_data[0];
+ *dev_id = id_data[1];
/*
* Try again to make sure, as some systems the bus-hold or other
@@ -3735,11 +4427,10 @@
* not match, ignore the device completely.
*/
- chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
-
/* Read entire ID string */
- for (i = 0; i < 8; i++)
- id_data[i] = chip->read_byte(mtd);
+ ret = nand_readid_op(chip, 0, id_data, 8);
+ if (ret)
+ return ERR_PTR(ret);
if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
@@ -3999,15 +4690,17 @@
/* Check for a chip array */
for (i = 1; i < maxchips; i++) {
+ u8 id[2];
+
/* See comment in nand_get_flash_type for reset */
nand_reset(chip, i);
chip->select_chip(mtd, i);
/* Send the command for reading device ID */
- chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
+ nand_readid_op(chip, 0, id, sizeof(id));
+
/* Read manufacturer and device IDs */
- if (nand_maf_id != chip->read_byte(mtd) ||
- nand_dev_id != chip->read_byte(mtd)) {
+ if (nand_maf_id != id[0] || nand_dev_id != id[1]) {
chip->select_chip(mtd, -1);
break;
}
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index d0e5426..6e436b5 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -528,4 +528,13 @@
This Driver support MediaTek Ethernet GMAC
Say Y to enable support for the MediaTek Ethernet GMAC.
+config HIGMACV300_ETH
+ bool "HiSilicon Gigabit Ethernet Controller"
+ depends on DM_ETH
+ select DM_RESET
+ select PHYLIB
+ help
+ This driver supports HIGMACV300 Ethernet controller found on
+ HiSilicon SoCs.
+
endif # NETDEVICES
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 51be72b..8d02a37 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -76,3 +76,4 @@
obj-y += ti/
obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o
obj-y += mscc_eswitch/
+obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o
diff --git a/drivers/net/higmacv300.c b/drivers/net/higmacv300.c
new file mode 100644
index 0000000..1be8359
--- /dev/null
+++ b/drivers/net/higmacv300.c
@@ -0,0 +1,597 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019, Linaro Limited
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <console.h>
+#include <linux/bug.h>
+#include <linux/mii.h>
+#include <miiphy.h>
+#include <net.h>
+#include <reset.h>
+#include <wait_bit.h>
+
+#define STATION_ADDR_LOW 0x0000
+#define STATION_ADDR_HIGH 0x0004
+#define MAC_DUPLEX_HALF_CTRL 0x0008
+#define PORT_MODE 0x0040
+#define PORT_EN 0x0044
+#define BIT_TX_EN BIT(2)
+#define BIT_RX_EN BIT(1)
+#define MODE_CHANGE_EN 0x01b4
+#define BIT_MODE_CHANGE_EN BIT(0)
+#define MDIO_SINGLE_CMD 0x03c0
+#define BIT_MDIO_BUSY BIT(20)
+#define MDIO_READ (BIT(17) | BIT_MDIO_BUSY)
+#define MDIO_WRITE (BIT(16) | BIT_MDIO_BUSY)
+#define MDIO_SINGLE_DATA 0x03c4
+#define MDIO_RDATA_STATUS 0x03d0
+#define BIT_MDIO_RDATA_INVALID BIT(0)
+#define RX_FQ_START_ADDR 0x0500
+#define RX_FQ_DEPTH 0x0504
+#define RX_FQ_WR_ADDR 0x0508
+#define RX_FQ_RD_ADDR 0x050c
+#define RX_FQ_REG_EN 0x0518
+#define RX_BQ_START_ADDR 0x0520
+#define RX_BQ_DEPTH 0x0524
+#define RX_BQ_WR_ADDR 0x0528
+#define RX_BQ_RD_ADDR 0x052c
+#define RX_BQ_REG_EN 0x0538
+#define TX_BQ_START_ADDR 0x0580
+#define TX_BQ_DEPTH 0x0584
+#define TX_BQ_WR_ADDR 0x0588
+#define TX_BQ_RD_ADDR 0x058c
+#define TX_BQ_REG_EN 0x0598
+#define TX_RQ_START_ADDR 0x05a0
+#define TX_RQ_DEPTH 0x05a4
+#define TX_RQ_WR_ADDR 0x05a8
+#define TX_RQ_RD_ADDR 0x05ac
+#define TX_RQ_REG_EN 0x05b8
+#define BIT_START_ADDR_EN BIT(2)
+#define BIT_DEPTH_EN BIT(1)
+#define DESC_WR_RD_ENA 0x05cc
+#define BIT_RX_OUTCFF_WR BIT(3)
+#define BIT_RX_CFF_RD BIT(2)
+#define BIT_TX_OUTCFF_WR BIT(1)
+#define BIT_TX_CFF_RD BIT(0)
+#define BITS_DESC_ENA (BIT_RX_OUTCFF_WR | BIT_RX_CFF_RD | \
+ BIT_TX_OUTCFF_WR | BIT_TX_CFF_RD)
+
+/* MACIF_CTRL */
+#define RGMII_SPEED_1000 0x2c
+#define RGMII_SPEED_100 0x2f
+#define RGMII_SPEED_10 0x2d
+#define MII_SPEED_100 0x0f
+#define MII_SPEED_10 0x0d
+#define GMAC_SPEED_1000 0x05
+#define GMAC_SPEED_100 0x01
+#define GMAC_SPEED_10 0x00
+#define GMAC_FULL_DUPLEX BIT(4)
+
+#define RX_DESC_NUM 64
+#define TX_DESC_NUM 2
+#define DESC_SIZE 32
+#define DESC_WORD_SHIFT 3
+#define DESC_BYTE_SHIFT 5
+#define DESC_CNT(n) ((n) >> DESC_BYTE_SHIFT)
+#define DESC_BYTE(n) ((n) << DESC_BYTE_SHIFT)
+#define DESC_VLD_FREE 0
+#define DESC_VLD_BUSY 1
+
+#define MAC_MAX_FRAME_SIZE 1600
+
+enum higmac_queue {
+ RX_FQ,
+ RX_BQ,
+ TX_BQ,
+ TX_RQ,
+};
+
+struct higmac_desc {
+ unsigned int buf_addr;
+ unsigned int buf_len:11;
+ unsigned int reserve0:5;
+ unsigned int data_len:11;
+ unsigned int reserve1:2;
+ unsigned int fl:2;
+ unsigned int descvid:1;
+ unsigned int reserve2[6];
+};
+
+struct higmac_priv {
+ void __iomem *base;
+ void __iomem *macif_ctrl;
+ struct reset_ctl rst_phy;
+ struct higmac_desc *rxfq;
+ struct higmac_desc *rxbq;
+ struct higmac_desc *txbq;
+ struct higmac_desc *txrq;
+ int rxdesc_in_use;
+ struct mii_dev *bus;
+ struct phy_device *phydev;
+ int phyintf;
+ int phyaddr;
+};
+
+#define flush_desc(d) flush_cache((unsigned long)(d), sizeof(*(d)))
+#define invalidate_desc(d) \
+ invalidate_dcache_range((unsigned long)(d), \
+ (unsigned long)(d) + sizeof(*(d)))
+
+static int higmac_write_hwaddr(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct higmac_priv *priv = dev_get_priv(dev);
+ unsigned char *mac = pdata->enetaddr;
+ u32 val;
+
+ val = mac[1] | (mac[0] << 8);
+ writel(val, priv->base + STATION_ADDR_HIGH);
+
+ val = mac[5] | (mac[4] << 8) | (mac[3] << 16) | (mac[2] << 24);
+ writel(val, priv->base + STATION_ADDR_LOW);
+
+ return 0;
+}
+
+static int higmac_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+ struct higmac_priv *priv = dev_get_priv(dev);
+
+ /* Inform GMAC that the RX descriptor is no longer in use */
+ writel(DESC_BYTE(priv->rxdesc_in_use), priv->base + RX_BQ_RD_ADDR);
+
+ return 0;
+}
+
+static int higmac_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct higmac_priv *priv = dev_get_priv(dev);
+ struct higmac_desc *fqd = priv->rxfq;
+ struct higmac_desc *bqd = priv->rxbq;
+ int fqw_pos, fqr_pos, bqw_pos, bqr_pos;
+ int timeout = 100000;
+ int len = 0;
+ int space;
+ int i;
+
+ fqw_pos = DESC_CNT(readl(priv->base + RX_FQ_WR_ADDR));
+ fqr_pos = DESC_CNT(readl(priv->base + RX_FQ_RD_ADDR));
+
+ if (fqw_pos >= fqr_pos)
+ space = RX_DESC_NUM - (fqw_pos - fqr_pos);
+ else
+ space = fqr_pos - fqw_pos;
+
+ /* Leave one free to distinguish full filled from empty buffer */
+ for (i = 0; i < space - 1; i++) {
+ fqd = priv->rxfq + fqw_pos;
+ invalidate_dcache_range(fqd->buf_addr,
+ fqd->buf_addr + MAC_MAX_FRAME_SIZE);
+
+ if (++fqw_pos >= RX_DESC_NUM)
+ fqw_pos = 0;
+
+ writel(DESC_BYTE(fqw_pos), priv->base + RX_FQ_WR_ADDR);
+ }
+
+ bqr_pos = DESC_CNT(readl(priv->base + RX_BQ_RD_ADDR));
+ bqd += bqr_pos;
+ /* BQ is only ever written by GMAC */
+ invalidate_desc(bqd);
+
+ do {
+ bqw_pos = DESC_CNT(readl(priv->base + RX_BQ_WR_ADDR));
+ udelay(1);
+ } while (--timeout && bqw_pos == bqr_pos);
+
+ if (!timeout)
+ return -ETIMEDOUT;
+
+ if (++bqr_pos >= RX_DESC_NUM)
+ bqr_pos = 0;
+
+ len = bqd->data_len;
+
+ /* CPU should not have touched this buffer since we added it to FQ */
+ invalidate_dcache_range(bqd->buf_addr, bqd->buf_addr + len);
+ *packetp = (void *)(unsigned long)bqd->buf_addr;
+
+ /* Record the RX_BQ descriptor that is holding RX data */
+ priv->rxdesc_in_use = bqr_pos;
+
+ return len;
+}
+
+static int higmac_send(struct udevice *dev, void *packet, int length)
+{
+ struct higmac_priv *priv = dev_get_priv(dev);
+ struct higmac_desc *bqd = priv->txbq;
+ int bqw_pos, rqw_pos, rqr_pos;
+ int timeout = 1000;
+
+ flush_cache((unsigned long)packet, length);
+
+ bqw_pos = DESC_CNT(readl(priv->base + TX_BQ_WR_ADDR));
+ bqd += bqw_pos;
+ bqd->buf_addr = (unsigned long)packet;
+ bqd->descvid = DESC_VLD_BUSY;
+ bqd->data_len = length;
+ flush_desc(bqd);
+
+ if (++bqw_pos >= TX_DESC_NUM)
+ bqw_pos = 0;
+
+ writel(DESC_BYTE(bqw_pos), priv->base + TX_BQ_WR_ADDR);
+
+ rqr_pos = DESC_CNT(readl(priv->base + TX_RQ_RD_ADDR));
+ if (++rqr_pos >= TX_DESC_NUM)
+ rqr_pos = 0;
+
+ do {
+ rqw_pos = DESC_CNT(readl(priv->base + TX_RQ_WR_ADDR));
+ udelay(1);
+ } while (--timeout && rqr_pos != rqw_pos);
+
+ if (!timeout)
+ return -ETIMEDOUT;
+
+ writel(DESC_BYTE(rqr_pos), priv->base + TX_RQ_RD_ADDR);
+
+ return 0;
+}
+
+static int higmac_adjust_link(struct higmac_priv *priv)
+{
+ struct phy_device *phydev = priv->phydev;
+ int interface = priv->phyintf;
+ u32 val;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ if (phydev->speed == SPEED_1000)
+ val = RGMII_SPEED_1000;
+ else if (phydev->speed == SPEED_100)
+ val = RGMII_SPEED_100;
+ else
+ val = RGMII_SPEED_10;
+ break;
+ case PHY_INTERFACE_MODE_MII:
+ if (phydev->speed == SPEED_100)
+ val = MII_SPEED_100;
+ else
+ val = MII_SPEED_10;
+ break;
+ default:
+ debug("unsupported mode: %d\n", interface);
+ return -EINVAL;
+ }
+
+ if (phydev->duplex)
+ val |= GMAC_FULL_DUPLEX;
+
+ writel(val, priv->macif_ctrl);
+
+ if (phydev->speed == SPEED_1000)
+ val = GMAC_SPEED_1000;
+ else if (phydev->speed == SPEED_100)
+ val = GMAC_SPEED_100;
+ else
+ val = GMAC_SPEED_10;
+
+ writel(BIT_MODE_CHANGE_EN, priv->base + MODE_CHANGE_EN);
+ writel(val, priv->base + PORT_MODE);
+ writel(0, priv->base + MODE_CHANGE_EN);
+ writel(phydev->duplex, priv->base + MAC_DUPLEX_HALF_CTRL);
+
+ return 0;
+}
+
+static int higmac_start(struct udevice *dev)
+{
+ struct higmac_priv *priv = dev_get_priv(dev);
+ struct phy_device *phydev = priv->phydev;
+ int ret;
+
+ ret = phy_startup(phydev);
+ if (ret)
+ return ret;
+
+ if (!phydev->link) {
+ debug("%s: link down\n", phydev->dev->name);
+ return -ENODEV;
+ }
+
+ ret = higmac_adjust_link(priv);
+ if (ret)
+ return ret;
+
+ /* Enable port */
+ writel(BITS_DESC_ENA, priv->base + DESC_WR_RD_ENA);
+ writel(BIT_TX_EN | BIT_RX_EN, priv->base + PORT_EN);
+
+ return 0;
+}
+
+static void higmac_stop(struct udevice *dev)
+{
+ struct higmac_priv *priv = dev_get_priv(dev);
+
+ /* Disable port */
+ writel(0, priv->base + PORT_EN);
+ writel(0, priv->base + DESC_WR_RD_ENA);
+}
+
+static const struct eth_ops higmac_ops = {
+ .start = higmac_start,
+ .send = higmac_send,
+ .recv = higmac_recv,
+ .free_pkt = higmac_free_pkt,
+ .stop = higmac_stop,
+ .write_hwaddr = higmac_write_hwaddr,
+};
+
+static int higmac_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
+{
+ struct higmac_priv *priv = bus->priv;
+ int ret;
+
+ ret = wait_for_bit_le32(priv->base + MDIO_SINGLE_CMD, BIT_MDIO_BUSY,
+ false, 1000, false);
+ if (ret)
+ return ret;
+
+ writel(MDIO_READ | addr << 8 | reg, priv->base + MDIO_SINGLE_CMD);
+
+ ret = wait_for_bit_le32(priv->base + MDIO_SINGLE_CMD, BIT_MDIO_BUSY,
+ false, 1000, false);
+ if (ret)
+ return ret;
+
+ if (readl(priv->base + MDIO_RDATA_STATUS) & BIT_MDIO_RDATA_INVALID)
+ return -EINVAL;
+
+ return readl(priv->base + MDIO_SINGLE_DATA) >> 16;
+}
+
+static int higmac_mdio_write(struct mii_dev *bus, int addr, int devad,
+ int reg, u16 value)
+{
+ struct higmac_priv *priv = bus->priv;
+ int ret;
+
+ ret = wait_for_bit_le32(priv->base + MDIO_SINGLE_CMD, BIT_MDIO_BUSY,
+ false, 1000, false);
+ if (ret)
+ return ret;
+
+ writel(value, priv->base + MDIO_SINGLE_DATA);
+ writel(MDIO_WRITE | addr << 8 | reg, priv->base + MDIO_SINGLE_CMD);
+
+ return 0;
+}
+
+static int higmac_init_rx_descs(struct higmac_desc *descs, int num)
+{
+ int i;
+
+ for (i = 0; i < num; i++) {
+ struct higmac_desc *desc = &descs[i];
+
+ desc->buf_addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
+ MAC_MAX_FRAME_SIZE);
+ if (!desc->buf_addr)
+ goto free_bufs;
+
+ desc->descvid = DESC_VLD_FREE;
+ desc->buf_len = MAC_MAX_FRAME_SIZE - 1;
+ flush_desc(desc);
+ }
+
+ return 0;
+
+free_bufs:
+ while (--i > 0)
+ free((void *)(unsigned long)descs[i].buf_addr);
+ return -ENOMEM;
+}
+
+static int higmac_init_hw_queue(struct higmac_priv *priv,
+ enum higmac_queue queue)
+{
+ struct higmac_desc *desc, **pdesc;
+ u32 regaddr, regen, regdep;
+ int depth;
+ int len;
+
+ switch (queue) {
+ case RX_FQ:
+ regaddr = RX_FQ_START_ADDR;
+ regen = RX_FQ_REG_EN;
+ regdep = RX_FQ_DEPTH;
+ depth = RX_DESC_NUM;
+ pdesc = &priv->rxfq;
+ break;
+ case RX_BQ:
+ regaddr = RX_BQ_START_ADDR;
+ regen = RX_BQ_REG_EN;
+ regdep = RX_BQ_DEPTH;
+ depth = RX_DESC_NUM;
+ pdesc = &priv->rxbq;
+ break;
+ case TX_BQ:
+ regaddr = TX_BQ_START_ADDR;
+ regen = TX_BQ_REG_EN;
+ regdep = TX_BQ_DEPTH;
+ depth = TX_DESC_NUM;
+ pdesc = &priv->txbq;
+ break;
+ case TX_RQ:
+ regaddr = TX_RQ_START_ADDR;
+ regen = TX_RQ_REG_EN;
+ regdep = TX_RQ_DEPTH;
+ depth = TX_DESC_NUM;
+ pdesc = &priv->txrq;
+ break;
+ }
+
+ /* Enable depth */
+ writel(BIT_DEPTH_EN, priv->base + regen);
+ writel(depth << DESC_WORD_SHIFT, priv->base + regdep);
+ writel(0, priv->base + regen);
+
+ len = depth * sizeof(*desc);
+ desc = memalign(ARCH_DMA_MINALIGN, len);
+ if (!desc)
+ return -ENOMEM;
+ memset(desc, 0, len);
+ flush_cache((unsigned long)desc, len);
+ *pdesc = desc;
+
+ /* Set up RX_FQ descriptors */
+ if (queue == RX_FQ)
+ higmac_init_rx_descs(desc, depth);
+
+ /* Enable start address */
+ writel(BIT_START_ADDR_EN, priv->base + regen);
+ writel((unsigned long)desc, priv->base + regaddr);
+ writel(0, priv->base + regen);
+
+ return 0;
+}
+
+static int higmac_hw_init(struct higmac_priv *priv)
+{
+ int ret;
+
+ /* Initialize hardware queues */
+ ret = higmac_init_hw_queue(priv, RX_FQ);
+ if (ret)
+ return ret;
+
+ ret = higmac_init_hw_queue(priv, RX_BQ);
+ if (ret)
+ goto free_rx_fq;
+
+ ret = higmac_init_hw_queue(priv, TX_BQ);
+ if (ret)
+ goto free_rx_bq;
+
+ ret = higmac_init_hw_queue(priv, TX_RQ);
+ if (ret)
+ goto free_tx_bq;
+
+ /* Reset phy */
+ reset_deassert(&priv->rst_phy);
+ mdelay(10);
+ reset_assert(&priv->rst_phy);
+ mdelay(30);
+ reset_deassert(&priv->rst_phy);
+ mdelay(30);
+
+ return 0;
+
+free_tx_bq:
+ free(priv->txbq);
+free_rx_bq:
+ free(priv->rxbq);
+free_rx_fq:
+ free(priv->rxfq);
+ return ret;
+}
+
+static int higmac_probe(struct udevice *dev)
+{
+ struct higmac_priv *priv = dev_get_priv(dev);
+ struct phy_device *phydev;
+ struct mii_dev *bus;
+ int ret;
+
+ ret = higmac_hw_init(priv);
+ if (ret)
+ return ret;
+
+ bus = mdio_alloc();
+ if (!bus)
+ return -ENOMEM;
+
+ bus->read = higmac_mdio_read;
+ bus->write = higmac_mdio_write;
+ bus->priv = priv;
+ priv->bus = bus;
+
+ ret = mdio_register_seq(bus, dev->seq);
+ if (ret)
+ return ret;
+
+ phydev = phy_connect(bus, priv->phyaddr, dev, priv->phyintf);
+ if (!phydev)
+ return -ENODEV;
+
+ phydev->supported &= PHY_GBIT_FEATURES;
+ phydev->advertising = phydev->supported;
+ priv->phydev = phydev;
+
+ return phy_config(phydev);
+}
+
+static int higmac_remove(struct udevice *dev)
+{
+ struct higmac_priv *priv = dev_get_priv(dev);
+ int i;
+
+ mdio_unregister(priv->bus);
+ mdio_free(priv->bus);
+
+ /* Free RX packet buffers */
+ for (i = 0; i < RX_DESC_NUM; i++)
+ free((void *)(unsigned long)priv->rxfq[i].buf_addr);
+
+ return 0;
+}
+
+static int higmac_ofdata_to_platdata(struct udevice *dev)
+{
+ struct higmac_priv *priv = dev_get_priv(dev);
+ int phyintf = PHY_INTERFACE_MODE_NONE;
+ const char *phy_mode;
+ ofnode phy_node;
+
+ priv->base = dev_remap_addr_index(dev, 0);
+ priv->macif_ctrl = dev_remap_addr_index(dev, 1);
+
+ phy_mode = dev_read_string(dev, "phy-mode");
+ if (phy_mode)
+ phyintf = phy_get_interface_by_name(phy_mode);
+ if (phyintf == PHY_INTERFACE_MODE_NONE)
+ return -ENODEV;
+ priv->phyintf = phyintf;
+
+ phy_node = dev_read_subnode(dev, "phy");
+ if (!ofnode_valid(phy_node)) {
+ debug("failed to find phy node\n");
+ return -ENODEV;
+ }
+ priv->phyaddr = ofnode_read_u32_default(phy_node, "reg", 0);
+
+ return reset_get_by_name(dev, "phy", &priv->rst_phy);
+}
+
+static const struct udevice_id higmac_ids[] = {
+ { .compatible = "hisilicon,hi3798cv200-gmac" },
+ { }
+};
+
+U_BOOT_DRIVER(eth_higmac) = {
+ .name = "eth_higmac",
+ .id = UCLASS_ETH,
+ .of_match = higmac_ids,
+ .ofdata_to_platdata = higmac_ofdata_to_platdata,
+ .probe = higmac_probe,
+ .remove = higmac_remove,
+ .ops = &higmac_ops,
+ .priv_auto_alloc_size = sizeof(struct higmac_priv),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
diff --git a/drivers/net/sandbox.c b/drivers/net/sandbox.c
index decce2f..c136392 100644
--- a/drivers/net/sandbox.c
+++ b/drivers/net/sandbox.c
@@ -350,7 +350,7 @@
struct eth_sandbox_priv *priv = dev_get_priv(dev);
if (skip_timeout) {
- sandbox_timer_add_offset(11000UL);
+ timer_test_add_offset(11000UL);
skip_timeout = false;
}
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 824fa11..cf1e761 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -918,6 +918,11 @@
return;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
+ if (hose->region_count == MAX_PCI_REGIONS) {
+ pr_err("maximum number of regions parsed, aborting\n");
+ break;
+ }
+
if (bd->bi_dram[i].size) {
pci_set_region(hose->regions + hose->region_count++,
bd->bi_dram[i].start,
diff --git a/drivers/phy/phy-stm32-usbphyc.c b/drivers/phy/phy-stm32-usbphyc.c
index 8e98b4b..6f11190 100644
--- a/drivers/phy/phy-stm32-usbphyc.c
+++ b/drivers/phy/phy-stm32-usbphyc.c
@@ -37,7 +37,8 @@
#define MAX_PHYS 2
-#define PLL_LOCK_TIME_US 100
+/* max 100 us for PLL lock and 100 us for PHY init */
+#define PLL_INIT_TIME_US 200
#define PLL_PWR_DOWN_TIME_US 5
#define PLL_FVCO 2880 /* in MHz */
#define PLL_INFF_MIN_RATE 19200000 /* in Hz */
@@ -51,17 +52,17 @@
struct stm32_usbphyc {
fdt_addr_t base;
struct clk clk;
+ struct udevice *vdda1v1;
+ struct udevice *vdda1v8;
struct stm32_usbphyc_phy {
struct udevice *vdd;
- struct udevice *vdda1v1;
- struct udevice *vdda1v8;
- int index;
bool init;
bool powered;
} phys[MAX_PHYS];
};
-void stm32_usbphyc_get_pll_params(u32 clk_rate, struct pll_params *pll_params)
+static void stm32_usbphyc_get_pll_params(u32 clk_rate,
+ struct pll_params *pll_params)
{
unsigned long long fvco, ndiv, frac;
@@ -154,6 +155,18 @@
if (pllen && stm32_usbphyc_is_init(usbphyc))
goto initialized;
+ if (usbphyc->vdda1v1) {
+ ret = regulator_set_enable(usbphyc->vdda1v1, true);
+ if (ret)
+ return ret;
+ }
+
+ if (usbphyc->vdda1v8) {
+ ret = regulator_set_enable(usbphyc->vdda1v8, true);
+ if (ret)
+ return ret;
+ }
+
if (pllen) {
clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
udelay(PLL_PWR_DOWN_TIME_US);
@@ -165,11 +178,8 @@
setbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
- /*
- * We must wait PLL_LOCK_TIME_US before checking that PLLEN
- * bit is still set
- */
- udelay(PLL_LOCK_TIME_US);
+ /* We must wait PLL_INIT_TIME_US before using PHY */
+ udelay(PLL_INIT_TIME_US);
if (!(readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN))
return -EIO;
@@ -184,6 +194,7 @@
{
struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
+ int ret;
pr_debug("%s phy ID = %lu\n", __func__, phy->id);
usbphyc_phy->init = false;
@@ -203,6 +214,18 @@
if (readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN)
return -EIO;
+ if (usbphyc->vdda1v1) {
+ ret = regulator_set_enable(usbphyc->vdda1v1, false);
+ if (ret)
+ return ret;
+ }
+
+ if (usbphyc->vdda1v8) {
+ ret = regulator_set_enable(usbphyc->vdda1v8, false);
+ if (ret)
+ return ret;
+ }
+
return 0;
}
@@ -213,17 +236,6 @@
int ret;
pr_debug("%s phy ID = %lu\n", __func__, phy->id);
- if (usbphyc_phy->vdda1v1) {
- ret = regulator_set_enable(usbphyc_phy->vdda1v1, true);
- if (ret)
- return ret;
- }
-
- if (usbphyc_phy->vdda1v8) {
- ret = regulator_set_enable(usbphyc_phy->vdda1v8, true);
- if (ret)
- return ret;
- }
if (usbphyc_phy->vdd) {
ret = regulator_set_enable(usbphyc_phy->vdd, true);
if (ret)
@@ -247,18 +259,6 @@
if (stm32_usbphyc_is_powered(usbphyc))
return 0;
- if (usbphyc_phy->vdda1v1) {
- ret = regulator_set_enable(usbphyc_phy->vdda1v1, false);
- if (ret)
- return ret;
- }
-
- if (usbphyc_phy->vdda1v8) {
- ret = regulator_set_enable(usbphyc_phy->vdda1v8, false);
- if (ret)
- return ret;
- }
-
if (usbphyc_phy->vdd) {
ret = regulator_set_enable(usbphyc_phy->vdd, false);
if (ret)
@@ -298,19 +298,20 @@
static int stm32_usbphyc_of_xlate(struct phy *phy,
struct ofnode_phandle_args *args)
{
- if (args->args_count > 1) {
- pr_debug("%s: invalid args_count: %d\n", __func__,
- args->args_count);
- return -EINVAL;
- }
+ if (args->args_count < 1)
+ return -ENODEV;
if (args->args[0] >= MAX_PHYS)
return -ENODEV;
- if (args->args_count)
- phy->id = args->args[0];
- else
- phy->id = 0;
+ phy->id = args->args[0];
+
+ if ((phy->id == 0 && args->args_count != 1) ||
+ (phy->id == 1 && args->args_count != 2)) {
+ dev_err(dev, "invalid number of cells for phy port%ld\n",
+ phy->id);
+ return -EINVAL;
+ }
return 0;
}
@@ -351,6 +352,21 @@
reset_deassert(&reset);
}
+ /* get usbphyc regulator */
+ ret = device_get_supply_regulator(dev, "vdda1v1-supply",
+ &usbphyc->vdda1v1);
+ if (ret) {
+ dev_err(dev, "Can't get vdda1v1-supply regulator\n");
+ return ret;
+ }
+
+ ret = device_get_supply_regulator(dev, "vdda1v8-supply",
+ &usbphyc->vdda1v8);
+ if (ret) {
+ dev_err(dev, "Can't get vdda1v8-supply regulator\n");
+ return ret;
+ }
+
/*
* parse all PHY subnodes in order to populate regulator associated
* to each PHY port
@@ -359,7 +375,6 @@
for (i = 0; i < MAX_PHYS; i++) {
struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + i;
- usbphyc_phy->index = i;
usbphyc_phy->init = false;
usbphyc_phy->powered = false;
ret = stm32_usbphyc_get_regulator(dev, node, "phy-supply",
@@ -367,16 +382,6 @@
if (ret)
return ret;
- ret = stm32_usbphyc_get_regulator(dev, node, "vdda1v1-supply",
- &usbphyc_phy->vdda1v1);
- if (ret)
- return ret;
-
- ret = stm32_usbphyc_get_regulator(dev, node, "vdda1v8-supply",
- &usbphyc_phy->vdda1v8);
- if (ret)
- return ret;
-
node = dev_read_next_subnode(node);
}
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index 1bd9a92..9930ca1 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -12,4 +12,8 @@
bool "MT7629 SoC pinctrl driver"
select PINCTRL_MTK
+config PINCTRL_MT8516
+ bool "MT8516 SoC pinctrl driver"
+ select PINCTRL_MTK
+
endif
diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
index f6ef362..c4f2908 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -5,3 +5,4 @@
# SoC Drivers
obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
+obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8516.c b/drivers/pinctrl/mediatek/pinctrl-mt8516.c
new file mode 100644
index 0000000..829b30e
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8516.c
@@ -0,0 +1,391 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 BayLibre, SAS
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+#include <dm.h>
+
+#include "pinctrl-mtk-common.h"
+
+#define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 16, false)
+
+static const struct mtk_pin_field_calc mt8516_pin_mode_range[] = {
+ PIN_FIELD_CALC(0, 124, 0x300, 0x10, 0, 3, 15, false),
+};
+
+static const struct mtk_pin_field_calc mt8516_pin_dir_range[] = {
+ PIN_FIELD(0, 124, 0x0, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8516_pin_di_range[] = {
+ PIN_FIELD(0, 124, 0x200, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8516_pin_do_range[] = {
+ PIN_FIELD(0, 124, 0x100, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8516_pin_ies_range[] = {
+ PIN_FIELD(0, 6, 0x900, 0x10, 2, 1),
+ PIN_FIELD(7, 10, 0x900, 0x10, 3, 1),
+ PIN_FIELD(11, 13, 0x900, 0x10, 12, 1),
+ PIN_FIELD(14, 17, 0x900, 0x10, 13, 1),
+ PIN_FIELD(18, 20, 0x910, 0x10, 10, 1),
+ PIN_FIELD(21, 23, 0x900, 0x10, 13, 1),
+ PIN_FIELD(24, 25, 0x900, 0x10, 12, 1),
+ PIN_FIELD(26, 30, 0x900, 0x10, 0, 1),
+ PIN_FIELD(31, 33, 0x900, 0x10, 1, 1),
+ PIN_FIELD(34, 39, 0x900, 0x10, 2, 1),
+ PIN_FIELD(40, 40, 0x910, 0x10, 11, 1),
+ PIN_FIELD(41, 43, 0x900, 0x10, 10, 1),
+ PIN_FIELD(44, 47, 0x900, 0x10, 11, 1),
+ PIN_FIELD(48, 51, 0x900, 0x10, 14, 1),
+ PIN_FIELD(52, 53, 0x910, 0x10, 0, 1),
+ PIN_FIELD(54, 54, 0x910, 0x10, 2, 1),
+ PIN_FIELD(55, 57, 0x910, 0x10, 4, 1),
+ PIN_FIELD(58, 59, 0x900, 0x10, 15, 1),
+ PIN_FIELD(60, 61, 0x910, 0x10, 1, 1),
+ PIN_FIELD(62, 65, 0x910, 0x10, 5, 1),
+ PIN_FIELD(66, 67, 0x910, 0x10, 6, 1),
+ PIN_FIELD(68, 68, 0x930, 0x10, 2, 1),
+ PIN_FIELD(69, 69, 0x930, 0x10, 1, 1),
+ PIN_FIELD(70, 70, 0x930, 0x10, 6, 1),
+ PIN_FIELD(71, 71, 0x930, 0x10, 5, 1),
+ PIN_FIELD(72, 72, 0x930, 0x10, 4, 1),
+ PIN_FIELD(73, 73, 0x930, 0x10, 3, 1),
+
+ PIN_FIELD(100, 103, 0x910, 0x10, 7, 1),
+ PIN_FIELD(104, 104, 0x920, 0x10, 12, 1),
+ PIN_FIELD(105, 105, 0x920, 0x10, 11, 1),
+ PIN_FIELD(106, 106, 0x930, 0x10, 0, 1),
+ PIN_FIELD(107, 107, 0x920, 0x10, 15, 1),
+ PIN_FIELD(108, 108, 0x920, 0x10, 14, 1),
+ PIN_FIELD(109, 109, 0x920, 0x10, 13, 1),
+ PIN_FIELD(110, 110, 0x920, 0x10, 9, 1),
+ PIN_FIELD(111, 111, 0x920, 0x10, 8, 1),
+ PIN_FIELD(112, 112, 0x920, 0x10, 7, 1),
+ PIN_FIELD(113, 113, 0x920, 0x10, 6, 1),
+ PIN_FIELD(114, 114, 0x920, 0x10, 10, 1),
+ PIN_FIELD(115, 115, 0x920, 0x10, 1, 1),
+ PIN_FIELD(116, 116, 0x920, 0x10, 0, 1),
+ PIN_FIELD(117, 117, 0x920, 0x10, 5, 1),
+ PIN_FIELD(118, 118, 0x920, 0x10, 4, 1),
+ PIN_FIELD(119, 119, 0x920, 0x10, 3, 1),
+ PIN_FIELD(120, 120, 0x920, 0x10, 2, 1),
+ PIN_FIELD(121, 124, 0x910, 0x10, 9, 1),
+};
+
+static const struct mtk_pin_field_calc mt8516_pin_smt_range[] = {
+ PIN_FIELD(0, 6, 0xA00, 0x10, 2, 1),
+ PIN_FIELD(7, 10, 0xA00, 0x10, 3, 1),
+ PIN_FIELD(11, 13, 0xA00, 0x10, 12, 1),
+ PIN_FIELD(14, 17, 0xA00, 0x10, 13, 1),
+ PIN_FIELD(18, 20, 0xA10, 0x10, 10, 1),
+ PIN_FIELD(21, 23, 0xA00, 0x10, 13, 1),
+ PIN_FIELD(24, 25, 0xA00, 0x10, 12, 1),
+ PIN_FIELD(26, 30, 0xA00, 0x10, 0, 1),
+ PIN_FIELD(31, 33, 0xA00, 0x10, 1, 1),
+ PIN_FIELD(40, 40, 0xA10, 0x10, 11, 1),
+ PIN_FIELD(41, 43, 0xA00, 0x10, 10, 1),
+ PIN_FIELD(44, 47, 0xA00, 0x10, 11, 1),
+ PIN_FIELD(48, 51, 0xA00, 0x10, 14, 1),
+ PIN_FIELD(52, 53, 0xA10, 0x10, 0, 1),
+ PIN_FIELD(54, 54, 0xA10, 0x10, 2, 1),
+ PIN_FIELD(55, 57, 0xA10, 0x10, 4, 1),
+ PIN_FIELD(58, 59, 0xA00, 0x10, 15, 1),
+ PIN_FIELD(60, 61, 0xA10, 0x10, 1, 1),
+ PIN_FIELD(62, 65, 0xA10, 0x10, 5, 1),
+ PIN_FIELD(66, 67, 0xA10, 0x10, 6, 1),
+ PIN_FIELD(68, 68, 0xA30, 0x10, 2, 1),
+ PIN_FIELD(69, 69, 0xA30, 0x10, 1, 1),
+ PIN_FIELD(70, 70, 0xA30, 0x10, 3, 1),
+ PIN_FIELD(71, 71, 0xA30, 0x10, 4, 1),
+ PIN_FIELD(72, 72, 0xA30, 0x10, 5, 1),
+ PIN_FIELD(73, 73, 0xA30, 0x10, 6, 1),
+
+ PIN_FIELD(100, 103, 0xA10, 0x10, 7, 1),
+ PIN_FIELD(104, 104, 0xA20, 0x10, 12, 1),
+ PIN_FIELD(105, 105, 0xA20, 0x10, 11, 1),
+ PIN_FIELD(106, 106, 0xA30, 0x10, 13, 1),
+ PIN_FIELD(107, 107, 0xA20, 0x10, 14, 1),
+ PIN_FIELD(108, 108, 0xA20, 0x10, 15, 1),
+ PIN_FIELD(109, 109, 0xA30, 0x10, 0, 1),
+ PIN_FIELD(110, 110, 0xA20, 0x10, 9, 1),
+ PIN_FIELD(111, 111, 0xA20, 0x10, 8, 1),
+ PIN_FIELD(112, 112, 0xA20, 0x10, 7, 1),
+ PIN_FIELD(113, 113, 0xA20, 0x10, 6, 1),
+ PIN_FIELD(114, 114, 0xA20, 0x10, 10, 1),
+ PIN_FIELD(115, 115, 0xA20, 0x10, 1, 1),
+ PIN_FIELD(116, 116, 0xA20, 0x10, 0, 1),
+ PIN_FIELD(117, 117, 0xA20, 0x10, 5, 1),
+ PIN_FIELD(118, 118, 0xA20, 0x10, 4, 1),
+ PIN_FIELD(119, 119, 0xA20, 0x10, 3, 1),
+ PIN_FIELD(120, 120, 0xA20, 0x10, 2, 1),
+ PIN_FIELD(121, 124, 0xA10, 0x10, 9, 1),
+};
+
+static const struct mtk_pin_field_calc mt8516_pin_pullen_range[] = {
+ PIN_FIELD(0, 13, 0x500, 0x10, 0, 1),
+ PIN_FIELD(18, 20, 0x510, 0x10, 2, 1),
+ PIN_FIELD(24, 31, 0x510, 0x10, 8, 1),
+ PIN_FIELD(32, 39, 0x520, 0x10, 0, 1),
+ PIN_FIELD(44, 47, 0x520, 0x10, 12, 1),
+ PIN_FIELD(48, 63, 0x530, 0x10, 0, 1),
+ PIN_FIELD(64, 67, 0x540, 0x10, 0, 1),
+ PIN_FIELD(100, 103, 0x560, 0x10, 4, 1),
+ PIN_FIELD(121, 124, 0x570, 0x10, 9, 1),
+};
+
+static const struct mtk_pin_field_calc mt8516_pin_pullsel_range[] = {
+ PIN_FIELD(0, 13, 0x600, 0x10, 0, 1),
+ PIN_FIELD(18, 20, 0x610, 0x10, 2, 1),
+ PIN_FIELD(24, 31, 0x610, 0x10, 8, 1),
+ PIN_FIELD(32, 39, 0x620, 0x10, 0, 1),
+ PIN_FIELD(44, 47, 0x620, 0x10, 12, 1),
+ PIN_FIELD(48, 63, 0x630, 0x10, 0, 1),
+ PIN_FIELD(64, 67, 0x640, 0x10, 0, 1),
+ PIN_FIELD(100, 103, 0x660, 0x10, 4, 1),
+ PIN_FIELD(121, 124, 0x670, 0x10, 9, 1),
+};
+
+static const struct mtk_pin_field_calc mt8516_pin_drv_range[] = {
+ PIN_FIELD(0, 4, 0xd00, 0x10, 0, 4),
+ PIN_FIELD(5, 10, 0xd00, 0x10, 4, 4),
+ PIN_FIELD(11, 13, 0xd00, 0x10, 8, 4),
+ PIN_FIELD(14, 17, 0xd00, 0x10, 12, 4),
+ PIN_FIELD(18, 20, 0xd10, 0x10, 0, 4),
+ PIN_FIELD(21, 23, 0xd00, 0x10, 12, 4),
+ PIN_FIELD(24, 25, 0xd00, 0x10, 8, 4),
+ PIN_FIELD(26, 30, 0xd10, 0x10, 4, 4),
+ PIN_FIELD(31, 33, 0xd10, 0x10, 8, 4),
+ PIN_FIELD(34, 35, 0xd10, 0x10, 12, 4),
+ PIN_FIELD(36, 39, 0xd20, 0x10, 0, 4),
+ PIN_FIELD(40, 40, 0xd20, 0x10, 4, 4),
+ PIN_FIELD(41, 43, 0xd20, 0x10, 8, 4),
+ PIN_FIELD(44, 47, 0xd20, 0x10, 12, 4),
+ PIN_FIELD(48, 51, 0xd30, 0x10, 0, 4),
+ PIN_FIELD(54, 54, 0xd30, 0x10, 8, 4),
+ PIN_FIELD(55, 57, 0xd30, 0x10, 12, 4),
+ PIN_FIELD(62, 67, 0xd40, 0x10, 8, 4),
+ PIN_FIELD(68, 68, 0xd40, 0x10, 12, 4),
+ PIN_FIELD(69, 69, 0xd50, 0x10, 0, 4),
+ PIN_FIELD(70, 73, 0xd50, 0x10, 4, 4),
+ PIN_FIELD(100, 103, 0xd50, 0x10, 8, 4),
+ PIN_FIELD(104, 104, 0xd50, 0x10, 12, 4),
+ PIN_FIELD(105, 105, 0xd60, 0x10, 0, 4),
+ PIN_FIELD(106, 109, 0xd60, 0x10, 4, 4),
+ PIN_FIELD(110, 113, 0xd70, 0x10, 0, 4),
+ PIN_FIELD(114, 114, 0xd70, 0x10, 4, 4),
+ PIN_FIELD(115, 115, 0xd60, 0x10, 12, 4),
+ PIN_FIELD(116, 116, 0xd60, 0x10, 8, 4),
+ PIN_FIELD(117, 120, 0xd70, 0x10, 0, 4),
+};
+
+static const struct mtk_pin_reg_calc mt8516_reg_cals[] = {
+ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8516_pin_mode_range),
+ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8516_pin_dir_range),
+ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8516_pin_di_range),
+ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8516_pin_do_range),
+ [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8516_pin_ies_range),
+ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8516_pin_smt_range),
+ [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt8516_pin_pullsel_range),
+ [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt8516_pin_pullen_range),
+ [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8516_pin_drv_range),
+};
+
+static const struct mtk_pin_desc mt8516_pins[] = {
+ MTK_PIN(0, "EINT0", DRV_GRP0),
+ MTK_PIN(1, "EINT1", DRV_GRP0),
+ MTK_PIN(2, "EINT2", DRV_GRP0),
+ MTK_PIN(3, "EINT3", DRV_GRP0),
+ MTK_PIN(4, "EINT4", DRV_GRP0),
+ MTK_PIN(5, "EINT5", DRV_GRP0),
+ MTK_PIN(6, "EINT6", DRV_GRP0),
+ MTK_PIN(7, "EINT7", DRV_GRP0),
+ MTK_PIN(8, "EINT8", DRV_GRP0),
+ MTK_PIN(9, "EINT9", DRV_GRP0),
+ MTK_PIN(10, "EINT10", DRV_GRP0),
+ MTK_PIN(11, "EINT11", DRV_GRP0),
+ MTK_PIN(12, "EINT12", DRV_GRP0),
+ MTK_PIN(13, "EINT13", DRV_GRP0),
+ MTK_PIN(14, "EINT14", DRV_GRP2),
+ MTK_PIN(15, "EINT15", DRV_GRP2),
+ MTK_PIN(16, "EINT16", DRV_GRP2),
+ MTK_PIN(17, "EINT17", DRV_GRP2),
+ MTK_PIN(18, "EINT18", DRV_GRP0),
+ MTK_PIN(19, "EINT19", DRV_GRP0),
+ MTK_PIN(20, "EINT20", DRV_GRP0),
+ MTK_PIN(21, "EINT21", DRV_GRP2),
+ MTK_PIN(22, "EINT22", DRV_GRP2),
+ MTK_PIN(23, "EINT23", DRV_GRP2),
+ MTK_PIN(24, "EINT24", DRV_GRP0),
+ MTK_PIN(25, "EINT25", DRV_GRP0),
+ MTK_PIN(26, "PWRAP_SPI0_MI", DRV_GRP4),
+ MTK_PIN(27, "PWRAP_SPI0_MO", DRV_GRP4),
+ MTK_PIN(28, "PWRAP_INT", DRV_GRP4),
+ MTK_PIN(29, "PWRAP_SPIO0_CK", DRV_GRP4),
+ MTK_PIN(30, "PWARP_SPI0_CSN", DRV_GRP4),
+ MTK_PIN(31, "RTC32K_CK", DRV_GRP4),
+ MTK_PIN(32, "WATCHDOG", DRV_GRP4),
+ MTK_PIN(33, "SRCLKENA0", DRV_GRP4),
+ MTK_PIN(34, "URXD2", DRV_GRP0),
+ MTK_PIN(35, "UTXD2", DRV_GRP0),
+ MTK_PIN(36, "MRG_CLK", DRV_GRP0),
+ MTK_PIN(37, "MRG_SYNC", DRV_GRP0),
+ MTK_PIN(38, "MRG_DI", DRV_GRP0),
+ MTK_PIN(39, "MRG_DO", DRV_GRP0),
+ MTK_PIN(40, "KPROW0", DRV_GRP2),
+ MTK_PIN(41, "KPROW1", DRV_GRP2),
+ MTK_PIN(42, "KPCOL0", DRV_GRP2),
+ MTK_PIN(43, "KPCOL1", DRV_GRP2),
+ MTK_PIN(44, "JMTS", DRV_GRP2),
+ MTK_PIN(45, "JTCK", DRV_GRP2),
+ MTK_PIN(46, "JTDI", DRV_GRP2),
+ MTK_PIN(47, "JTDO", DRV_GRP2),
+ MTK_PIN(48, "SPI_CS", DRV_GRP2),
+ MTK_PIN(49, "SPI_CK", DRV_GRP2),
+ MTK_PIN(50, "SPI_MI", DRV_GRP2),
+ MTK_PIN(51, "SPI_MO", DRV_GRP2),
+ MTK_PIN(52, "SDA1", DRV_GRP2),
+ MTK_PIN(53, "SCL1", DRV_GRP2),
+ MTK_PIN(54, "DISP_PWM", DRV_GRP2),
+ MTK_PIN(55, "I2S_DATA_IN", DRV_GRP2),
+ MTK_PIN(56, "I2S_LRCK", DRV_GRP2),
+ MTK_PIN(57, "I2S_BCK", DRV_GRP2),
+ MTK_PIN(58, "SDA0", DRV_GRP2),
+ MTK_PIN(59, "SCL0", DRV_GRP2),
+ MTK_PIN(60, "SDA2", DRV_GRP2),
+ MTK_PIN(61, "SCL2", DRV_GRP2),
+ MTK_PIN(62, "URXD0", DRV_GRP2),
+ MTK_PIN(63, "UTXD0", DRV_GRP2),
+ MTK_PIN(64, "URXD1", DRV_GRP2),
+ MTK_PIN(65, "UTXD1", DRV_GRP2),
+ MTK_PIN(66, "LCM_RST", DRV_GRP2),
+ MTK_PIN(67, "DSI_TE", DRV_GRP2),
+ MTK_PIN(68, "MSDC2_CMD", DRV_GRP4),
+ MTK_PIN(69, "MSDC2_CLK", DRV_GRP4),
+ MTK_PIN(70, "MSDC2_DAT0", DRV_GRP4),
+ MTK_PIN(71, "MSDC2_DAT1", DRV_GRP4),
+ MTK_PIN(72, "MSDC2_DAT2", DRV_GRP4),
+ MTK_PIN(73, "MSDC2_DAT3", DRV_GRP4),
+ MTK_PIN(74, "TDN3", DRV_GRP0),
+ MTK_PIN(75, "TDP3", DRV_GRP0),
+ MTK_PIN(76, "TDN2", DRV_GRP0),
+ MTK_PIN(77, "TDP2", DRV_GRP0),
+ MTK_PIN(78, "TCN", DRV_GRP0),
+ MTK_PIN(79, "TCP", DRV_GRP0),
+ MTK_PIN(80, "TDN1", DRV_GRP0),
+ MTK_PIN(81, "TDP1", DRV_GRP0),
+ MTK_PIN(82, "TDN0", DRV_GRP0),
+ MTK_PIN(83, "TDP0", DRV_GRP0),
+ MTK_PIN(84, "RDN0", DRV_GRP0),
+ MTK_PIN(85, "RDP0", DRV_GRP0),
+ MTK_PIN(86, "RDN1", DRV_GRP0),
+ MTK_PIN(87, "RDP1", DRV_GRP0),
+ MTK_PIN(88, "RCN", DRV_GRP0),
+ MTK_PIN(89, "RCP", DRV_GRP0),
+ MTK_PIN(90, "RDN2", DRV_GRP0),
+ MTK_PIN(91, "RDP2", DRV_GRP0),
+ MTK_PIN(92, "RDN3", DRV_GRP0),
+ MTK_PIN(93, "RDP3", DRV_GRP0),
+ MTK_PIN(94, "RCN_A", DRV_GRP0),
+ MTK_PIN(95, "RCP_A", DRV_GRP0),
+ MTK_PIN(96, "RDN1_A", DRV_GRP0),
+ MTK_PIN(97, "RDP1_A", DRV_GRP0),
+ MTK_PIN(98, "RDN0_A", DRV_GRP0),
+ MTK_PIN(99, "RDP0_A", DRV_GRP0),
+ MTK_PIN(100, "CMDDAT0", DRV_GRP2),
+ MTK_PIN(101, "CMDDAT1", DRV_GRP2),
+ MTK_PIN(102, "CMMCLK", DRV_GRP2),
+ MTK_PIN(103, "CMPCLK", DRV_GRP2),
+ MTK_PIN(104, "MSDC1_CMD", DRV_GRP4),
+ MTK_PIN(105, "MSDC1_CLK", DRV_GRP4),
+ MTK_PIN(106, "MSDC1_DAT0", DRV_GRP4),
+ MTK_PIN(107, "MSDC1_DAT1", DRV_GRP4),
+ MTK_PIN(108, "MSDC1_DAT2", DRV_GRP4),
+ MTK_PIN(109, "MSDC1_DAT3", DRV_GRP4),
+ MTK_PIN(110, "MSDC0_DAT7", DRV_GRP4),
+ MTK_PIN(111, "MSDC0_DAT6", DRV_GRP4),
+ MTK_PIN(112, "MSDC0_DAT5", DRV_GRP4),
+ MTK_PIN(113, "MSDC0_DAT4", DRV_GRP4),
+ MTK_PIN(114, "MSDC0_RSTB", DRV_GRP4),
+ MTK_PIN(115, "MSDC0_CMD", DRV_GRP4),
+ MTK_PIN(116, "MSDC0_CLK", DRV_GRP4),
+ MTK_PIN(117, "MSDC0_DAT3", DRV_GRP4),
+ MTK_PIN(118, "MSDC0_DAT2", DRV_GRP4),
+ MTK_PIN(119, "MSDC0_DAT1", DRV_GRP4),
+ MTK_PIN(120, "MSDC0_DAT0", DRV_GRP4),
+};
+
+/* List all groups consisting of these pins dedicated to the enablement of
+ * certain hardware block and the corresponding mode for all of the pins.
+ * The hardware probably has multiple combinations of these pinouts.
+ */
+
+/* UART */
+static int mt8516_uart0_0_rxd_txd_pins[] = { 62, 63, };
+static int mt8516_uart0_0_rxd_txd_funcs[] = { 1, 1, };
+static int mt8516_uart1_0_rxd_txd_pins[] = { 64, 65, };
+static int mt8516_uart1_0_rxd_txd_funcs[] = { 1, 1, };
+static int mt8516_uart2_0_rxd_txd_pins[] = { 34, 35, };
+static int mt8516_uart2_0_rxd_txd_funcs[] = { 1, 1, };
+
+/* Joint those groups owning the same capability in user point of view which
+ * allows that people tend to use through the device tree.
+ */
+static const char *const mt8516_uart_groups[] = { "uart0_0_rxd_txd",
+ "uart1_0_rxd_txd",
+ "uart2_0_rxd_txd", };
+
+/* MMC0 */
+static int mt8516_msdc0_pins[] = { 110, 111, 112, 113, 114, 115, 116, 117, 118,
+ 119, 120, };
+static int mt8516_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
+
+static const struct mtk_group_desc mt8516_groups[] = {
+ PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8516_uart0_0_rxd_txd),
+ PINCTRL_PIN_GROUP("uart1_0_rxd_txd", mt8516_uart1_0_rxd_txd),
+ PINCTRL_PIN_GROUP("uart2_0_rxd_txd", mt8516_uart2_0_rxd_txd),
+
+ PINCTRL_PIN_GROUP("msdc0", mt8516_msdc0),
+};
+
+static const char *const mt8516_msdc_groups[] = { "msdc0" };
+
+static const struct mtk_function_desc mt8516_functions[] = {
+ {"uart", mt8516_uart_groups, ARRAY_SIZE(mt8516_uart_groups)},
+ {"msdc", mt8516_msdc_groups, ARRAY_SIZE(mt8516_msdc_groups)},
+};
+
+static struct mtk_pinctrl_soc mt8516_data = {
+ .name = "mt8516_pinctrl",
+ .reg_cal = mt8516_reg_cals,
+ .pins = mt8516_pins,
+ .npins = ARRAY_SIZE(mt8516_pins),
+ .grps = mt8516_groups,
+ .ngrps = ARRAY_SIZE(mt8516_groups),
+ .funcs = mt8516_functions,
+ .nfuncs = ARRAY_SIZE(mt8516_functions),
+};
+
+static int mtk_pinctrl_mt8516_probe(struct udevice *dev)
+{
+ return mtk_pinctrl_common_probe(dev, &mt8516_data);
+}
+
+static const struct udevice_id mt8516_pctrl_match[] = {
+ { .compatible = "mediatek,mt8516-pinctrl" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(mt8516_pinctrl) = {
+ .name = "mt8516_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = mt8516_pctrl_match,
+ .ops = &mtk_pinctrl_ops,
+ .probe = mtk_pinctrl_mt8516_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_pinctrl_priv),
+};
diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig
index 162642d..ef02087 100644
--- a/drivers/pinctrl/meson/Kconfig
+++ b/drivers/pinctrl/meson/Kconfig
@@ -25,4 +25,8 @@
bool "Amlogic Meson AXG SoC pinctrl driver"
select PINCTRL_MESON_AXG_PMX
+config PINCTRL_MESON_G12A
+ bool "Amlogic Meson G12a SoC pinctrl driver"
+ select PINCTRL_MESON_AXG_PMX
+
endif
diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile
index 707287c..80dba65 100644
--- a/drivers/pinctrl/meson/Makefile
+++ b/drivers/pinctrl/meson/Makefile
@@ -6,3 +6,4 @@
obj-$(CONFIG_PINCTRL_MESON_GXBB) += pinctrl-meson-gxbb.o
obj-$(CONFIG_PINCTRL_MESON_GXL) += pinctrl-meson-gxl.o
obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o
+obj-$(CONFIG_PINCTRL_MESON_G12A) += pinctrl-meson-g12a.o
diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg.c b/drivers/pinctrl/meson/pinctrl-meson-axg.c
index 3bbbe81..8f23c8c 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-axg.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-axg.c
@@ -17,239 +17,239 @@
#define EE_OFF 15
/* emmc */
-static const unsigned int emmc_nand_d0_pins[] = {BOOT_0};
-static const unsigned int emmc_nand_d1_pins[] = {BOOT_1};
-static const unsigned int emmc_nand_d2_pins[] = {BOOT_2};
-static const unsigned int emmc_nand_d3_pins[] = {BOOT_3};
-static const unsigned int emmc_nand_d4_pins[] = {BOOT_4};
-static const unsigned int emmc_nand_d5_pins[] = {BOOT_5};
-static const unsigned int emmc_nand_d6_pins[] = {BOOT_6};
-static const unsigned int emmc_nand_d7_pins[] = {BOOT_7};
+static const unsigned int emmc_nand_d0_pins[] = { PIN(BOOT_0, EE_OFF) };
+static const unsigned int emmc_nand_d1_pins[] = { PIN(BOOT_1, EE_OFF) };
+static const unsigned int emmc_nand_d2_pins[] = { PIN(BOOT_2, EE_OFF) };
+static const unsigned int emmc_nand_d3_pins[] = { PIN(BOOT_3, EE_OFF) };
+static const unsigned int emmc_nand_d4_pins[] = { PIN(BOOT_4, EE_OFF) };
+static const unsigned int emmc_nand_d5_pins[] = { PIN(BOOT_5, EE_OFF) };
+static const unsigned int emmc_nand_d6_pins[] = { PIN(BOOT_6, EE_OFF) };
+static const unsigned int emmc_nand_d7_pins[] = { PIN(BOOT_7, EE_OFF) };
-static const unsigned int emmc_clk_pins[] = {BOOT_8};
-static const unsigned int emmc_cmd_pins[] = {BOOT_10};
-static const unsigned int emmc_ds_pins[] = {BOOT_13};
+static const unsigned int emmc_clk_pins[] = { PIN(BOOT_8, EE_OFF) };
+static const unsigned int emmc_cmd_pins[] = { PIN(BOOT_10, EE_OFF) };
+static const unsigned int emmc_ds_pins[] = { PIN(BOOT_13, EE_OFF) };
/* nand */
-static const unsigned int nand_ce0_pins[] = {BOOT_8};
-static const unsigned int nand_ale_pins[] = {BOOT_9};
-static const unsigned int nand_cle_pins[] = {BOOT_10};
-static const unsigned int nand_wen_clk_pins[] = {BOOT_11};
-static const unsigned int nand_ren_wr_pins[] = {BOOT_12};
-static const unsigned int nand_rb0_pins[] = {BOOT_13};
+static const unsigned int nand_ce0_pins[] = { PIN(BOOT_8, EE_OFF) };
+static const unsigned int nand_ale_pins[] = { PIN(BOOT_9, EE_OFF) };
+static const unsigned int nand_cle_pins[] = { PIN(BOOT_10, EE_OFF) };
+static const unsigned int nand_wen_clk_pins[] = { PIN(BOOT_11, EE_OFF) };
+static const unsigned int nand_ren_wr_pins[] = { PIN(BOOT_12, EE_OFF) };
+static const unsigned int nand_rb0_pins[] = { PIN(BOOT_13, EE_OFF) };
/* nor */
-static const unsigned int nor_hold_pins[] = {BOOT_3};
-static const unsigned int nor_d_pins[] = {BOOT_4};
-static const unsigned int nor_q_pins[] = {BOOT_5};
-static const unsigned int nor_c_pins[] = {BOOT_6};
-static const unsigned int nor_wp_pins[] = {BOOT_9};
-static const unsigned int nor_cs_pins[] = {BOOT_14};
+static const unsigned int nor_hold_pins[] = { PIN(BOOT_3, EE_OFF) };
+static const unsigned int nor_d_pins[] = { PIN(BOOT_4, EE_OFF) };
+static const unsigned int nor_q_pins[] = { PIN(BOOT_5, EE_OFF) };
+static const unsigned int nor_c_pins[] = { PIN(BOOT_6, EE_OFF) };
+static const unsigned int nor_wp_pins[] = { PIN(BOOT_9, EE_OFF) };
+static const unsigned int nor_cs_pins[] = { PIN(BOOT_14, EE_OFF) };
/* sdio */
-static const unsigned int sdio_d0_pins[] = {GPIOX_0};
-static const unsigned int sdio_d1_pins[] = {GPIOX_1};
-static const unsigned int sdio_d2_pins[] = {GPIOX_2};
-static const unsigned int sdio_d3_pins[] = {GPIOX_3};
-static const unsigned int sdio_clk_pins[] = {GPIOX_4};
-static const unsigned int sdio_cmd_pins[] = {GPIOX_5};
+static const unsigned int sdio_d0_pins[] = { PIN(GPIOX_0, EE_OFF) };
+static const unsigned int sdio_d1_pins[] = { PIN(GPIOX_1, EE_OFF) };
+static const unsigned int sdio_d2_pins[] = { PIN(GPIOX_2, EE_OFF) };
+static const unsigned int sdio_d3_pins[] = { PIN(GPIOX_3, EE_OFF) };
+static const unsigned int sdio_clk_pins[] = { PIN(GPIOX_4, EE_OFF) };
+static const unsigned int sdio_cmd_pins[] = { PIN(GPIOX_5, EE_OFF) };
/* spi0 */
-static const unsigned int spi0_clk_pins[] = {GPIOZ_0};
-static const unsigned int spi0_mosi_pins[] = {GPIOZ_1};
-static const unsigned int spi0_miso_pins[] = {GPIOZ_2};
-static const unsigned int spi0_ss0_pins[] = {GPIOZ_3};
-static const unsigned int spi0_ss1_pins[] = {GPIOZ_4};
-static const unsigned int spi0_ss2_pins[] = {GPIOZ_5};
+static const unsigned int spi0_clk_pins[] = { PIN(GPIOZ_0, EE_OFF) };
+static const unsigned int spi0_mosi_pins[] = { PIN(GPIOZ_1, EE_OFF) };
+static const unsigned int spi0_miso_pins[] = { PIN(GPIOZ_2, EE_OFF) };
+static const unsigned int spi0_ss0_pins[] = { PIN(GPIOZ_3, EE_OFF) };
+static const unsigned int spi0_ss1_pins[] = { PIN(GPIOZ_4, EE_OFF) };
+static const unsigned int spi0_ss2_pins[] = { PIN(GPIOZ_5, EE_OFF) };
/* spi1 */
-static const unsigned int spi1_clk_x_pins[] = {GPIOX_19};
-static const unsigned int spi1_mosi_x_pins[] = {GPIOX_17};
-static const unsigned int spi1_miso_x_pins[] = {GPIOX_18};
-static const unsigned int spi1_ss0_x_pins[] = {GPIOX_16};
+static const unsigned int spi1_clk_x_pins[] = { PIN(GPIOX_19, EE_OFF) };
+static const unsigned int spi1_mosi_x_pins[] = { PIN(GPIOX_17, EE_OFF) };
+static const unsigned int spi1_miso_x_pins[] = { PIN(GPIOX_18, EE_OFF) };
+static const unsigned int spi1_ss0_x_pins[] = { PIN(GPIOX_16, EE_OFF) };
-static const unsigned int spi1_clk_a_pins[] = {GPIOA_4};
-static const unsigned int spi1_mosi_a_pins[] = {GPIOA_2};
-static const unsigned int spi1_miso_a_pins[] = {GPIOA_3};
-static const unsigned int spi1_ss0_a_pins[] = {GPIOA_5};
-static const unsigned int spi1_ss1_pins[] = {GPIOA_6};
+static const unsigned int spi1_clk_a_pins[] = { PIN(GPIOA_4, EE_OFF) };
+static const unsigned int spi1_mosi_a_pins[] = { PIN(GPIOA_2, EE_OFF) };
+static const unsigned int spi1_miso_a_pins[] = { PIN(GPIOA_3, EE_OFF) };
+static const unsigned int spi1_ss0_a_pins[] = { PIN(GPIOA_5, EE_OFF) };
+static const unsigned int spi1_ss1_pins[] = { PIN(GPIOA_6, EE_OFF) };
/* i2c0 */
-static const unsigned int i2c0_sck_pins[] = {GPIOZ_6};
-static const unsigned int i2c0_sda_pins[] = {GPIOZ_7};
+static const unsigned int i2c0_sck_pins[] = { PIN(GPIOZ_6, EE_OFF) };
+static const unsigned int i2c0_sda_pins[] = { PIN(GPIOZ_7, EE_OFF) };
/* i2c1 */
-static const unsigned int i2c1_sck_z_pins[] = {GPIOZ_8};
-static const unsigned int i2c1_sda_z_pins[] = {GPIOZ_9};
+static const unsigned int i2c1_sck_z_pins[] = { PIN(GPIOZ_8, EE_OFF) };
+static const unsigned int i2c1_sda_z_pins[] = { PIN(GPIOZ_9, EE_OFF) };
-static const unsigned int i2c1_sck_x_pins[] = {GPIOX_16};
-static const unsigned int i2c1_sda_x_pins[] = {GPIOX_17};
+static const unsigned int i2c1_sck_x_pins[] = { PIN(GPIOX_16, EE_OFF) };
+static const unsigned int i2c1_sda_x_pins[] = { PIN(GPIOX_17, EE_OFF) };
/* i2c2 */
-static const unsigned int i2c2_sck_x_pins[] = {GPIOX_18};
-static const unsigned int i2c2_sda_x_pins[] = {GPIOX_19};
+static const unsigned int i2c2_sck_x_pins[] = { PIN(GPIOX_18, EE_OFF) };
+static const unsigned int i2c2_sda_x_pins[] = { PIN(GPIOX_19, EE_OFF) };
-static const unsigned int i2c2_sda_a_pins[] = {GPIOA_17};
-static const unsigned int i2c2_sck_a_pins[] = {GPIOA_18};
+static const unsigned int i2c2_sda_a_pins[] = { PIN(GPIOA_17, EE_OFF) };
+static const unsigned int i2c2_sck_a_pins[] = { PIN(GPIOA_18, EE_OFF) };
/* i2c3 */
-static const unsigned int i2c3_sda_a6_pins[] = {GPIOA_6};
-static const unsigned int i2c3_sck_a7_pins[] = {GPIOA_7};
+static const unsigned int i2c3_sda_a6_pins[] = { PIN(GPIOA_6, EE_OFF) };
+static const unsigned int i2c3_sck_a7_pins[] = { PIN(GPIOA_7, EE_OFF) };
-static const unsigned int i2c3_sda_a12_pins[] = {GPIOA_12};
-static const unsigned int i2c3_sck_a13_pins[] = {GPIOA_13};
+static const unsigned int i2c3_sda_a12_pins[] = { PIN(GPIOA_12, EE_OFF) };
+static const unsigned int i2c3_sck_a13_pins[] = { PIN(GPIOA_13, EE_OFF) };
-static const unsigned int i2c3_sda_a19_pins[] = {GPIOA_19};
-static const unsigned int i2c3_sck_a20_pins[] = {GPIOA_20};
+static const unsigned int i2c3_sda_a19_pins[] = { PIN(GPIOA_19, EE_OFF) };
+static const unsigned int i2c3_sck_a20_pins[] = { PIN(GPIOA_20, EE_OFF) };
/* uart_a */
-static const unsigned int uart_rts_a_pins[] = {GPIOX_11};
-static const unsigned int uart_cts_a_pins[] = {GPIOX_10};
-static const unsigned int uart_tx_a_pins[] = {GPIOX_8};
-static const unsigned int uart_rx_a_pins[] = {GPIOX_9};
+static const unsigned int uart_rts_a_pins[] = { PIN(GPIOX_11, EE_OFF) };
+static const unsigned int uart_cts_a_pins[] = { PIN(GPIOX_10, EE_OFF) };
+static const unsigned int uart_tx_a_pins[] = { PIN(GPIOX_8, EE_OFF) };
+static const unsigned int uart_rx_a_pins[] = { PIN(GPIOX_9, EE_OFF) };
/* uart_b */
-static const unsigned int uart_rts_b_z_pins[] = {GPIOZ_0};
-static const unsigned int uart_cts_b_z_pins[] = {GPIOZ_1};
-static const unsigned int uart_tx_b_z_pins[] = {GPIOZ_2};
-static const unsigned int uart_rx_b_z_pins[] = {GPIOZ_3};
+static const unsigned int uart_rts_b_z_pins[] = { PIN(GPIOZ_0, EE_OFF) };
+static const unsigned int uart_cts_b_z_pins[] = { PIN(GPIOZ_1, EE_OFF) };
+static const unsigned int uart_tx_b_z_pins[] = { PIN(GPIOZ_2, EE_OFF) };
+static const unsigned int uart_rx_b_z_pins[] = { PIN(GPIOZ_3, EE_OFF) };
-static const unsigned int uart_rts_b_x_pins[] = {GPIOX_18};
-static const unsigned int uart_cts_b_x_pins[] = {GPIOX_19};
-static const unsigned int uart_tx_b_x_pins[] = {GPIOX_16};
-static const unsigned int uart_rx_b_x_pins[] = {GPIOX_17};
+static const unsigned int uart_rts_b_x_pins[] = { PIN(GPIOX_18, EE_OFF) };
+static const unsigned int uart_cts_b_x_pins[] = { PIN(GPIOX_19, EE_OFF) };
+static const unsigned int uart_tx_b_x_pins[] = { PIN(GPIOX_16, EE_OFF) };
+static const unsigned int uart_rx_b_x_pins[] = { PIN(GPIOX_17, EE_OFF) };
/* uart_ao_b */
-static const unsigned int uart_ao_tx_b_z_pins[] = {GPIOZ_8};
-static const unsigned int uart_ao_rx_b_z_pins[] = {GPIOZ_9};
-static const unsigned int uart_ao_cts_b_z_pins[] = {GPIOZ_6};
-static const unsigned int uart_ao_rts_b_z_pins[] = {GPIOZ_7};
+static const unsigned int uart_ao_tx_b_z_pins[] = { PIN(GPIOZ_8, EE_OFF) };
+static const unsigned int uart_ao_rx_b_z_pins[] = { PIN(GPIOZ_9, EE_OFF) };
+static const unsigned int uart_ao_cts_b_z_pins[] = { PIN(GPIOZ_6, EE_OFF) };
+static const unsigned int uart_ao_rts_b_z_pins[] = { PIN(GPIOZ_7, EE_OFF) };
/* pwm_a */
-static const unsigned int pwm_a_z_pins[] = {GPIOZ_5};
+static const unsigned int pwm_a_z_pins[] = { PIN(GPIOZ_5, EE_OFF) };
-static const unsigned int pwm_a_x18_pins[] = {GPIOX_18};
-static const unsigned int pwm_a_x20_pins[] = {GPIOX_20};
+static const unsigned int pwm_a_x18_pins[] = { PIN(GPIOX_18, EE_OFF) };
+static const unsigned int pwm_a_x20_pins[] = { PIN(GPIOX_20, EE_OFF) };
-static const unsigned int pwm_a_a_pins[] = {GPIOA_14};
+static const unsigned int pwm_a_a_pins[] = { PIN(GPIOA_14, EE_OFF) };
/* pwm_b */
-static const unsigned int pwm_b_z_pins[] = {GPIOZ_4};
+static const unsigned int pwm_b_z_pins[] = { PIN(GPIOZ_4, EE_OFF) };
-static const unsigned int pwm_b_x_pins[] = {GPIOX_19};
+static const unsigned int pwm_b_x_pins[] = { PIN(GPIOX_19, EE_OFF) };
-static const unsigned int pwm_b_a_pins[] = {GPIOA_15};
+static const unsigned int pwm_b_a_pins[] = { PIN(GPIOA_15, EE_OFF) };
/* pwm_c */
-static const unsigned int pwm_c_x10_pins[] = {GPIOX_10};
-static const unsigned int pwm_c_x17_pins[] = {GPIOX_17};
+static const unsigned int pwm_c_x10_pins[] = { PIN(GPIOX_10, EE_OFF) };
+static const unsigned int pwm_c_x17_pins[] = { PIN(GPIOX_17, EE_OFF) };
-static const unsigned int pwm_c_a_pins[] = {GPIOA_16};
+static const unsigned int pwm_c_a_pins[] = { PIN(GPIOA_16, EE_OFF) };
/* pwm_d */
-static const unsigned int pwm_d_x11_pins[] = {GPIOX_11};
-static const unsigned int pwm_d_x16_pins[] = {GPIOX_16};
+static const unsigned int pwm_d_x11_pins[] = { PIN(GPIOX_11, EE_OFF) };
+static const unsigned int pwm_d_x16_pins[] = { PIN(GPIOX_16, EE_OFF) };
/* pwm_vs */
-static const unsigned int pwm_vs_pins[] = {GPIOA_0};
+static const unsigned int pwm_vs_pins[] = { PIN(GPIOA_0, EE_OFF) };
/* spdif_in */
-static const unsigned int spdif_in_z_pins[] = {GPIOZ_4};
+static const unsigned int spdif_in_z_pins[] = { PIN(GPIOZ_4, EE_OFF) };
-static const unsigned int spdif_in_a1_pins[] = {GPIOA_1};
-static const unsigned int spdif_in_a7_pins[] = {GPIOA_7};
-static const unsigned int spdif_in_a19_pins[] = {GPIOA_19};
-static const unsigned int spdif_in_a20_pins[] = {GPIOA_20};
+static const unsigned int spdif_in_a1_pins[] = { PIN(GPIOA_1, EE_OFF) };
+static const unsigned int spdif_in_a7_pins[] = { PIN(GPIOA_7, EE_OFF) };
+static const unsigned int spdif_in_a19_pins[] = { PIN(GPIOA_19, EE_OFF) };
+static const unsigned int spdif_in_a20_pins[] = { PIN(GPIOA_20, EE_OFF) };
/* spdif_out */
-static const unsigned int spdif_out_z_pins[] = {GPIOZ_5};
+static const unsigned int spdif_out_z_pins[] = { PIN(GPIOZ_5, EE_OFF) };
-static const unsigned int spdif_out_a1_pins[] = {GPIOA_1};
-static const unsigned int spdif_out_a11_pins[] = {GPIOA_11};
-static const unsigned int spdif_out_a19_pins[] = {GPIOA_19};
-static const unsigned int spdif_out_a20_pins[] = {GPIOA_20};
+static const unsigned int spdif_out_a1_pins[] = { PIN(GPIOA_1, EE_OFF) };
+static const unsigned int spdif_out_a11_pins[] = { PIN(GPIOA_11, EE_OFF) };
+static const unsigned int spdif_out_a19_pins[] = { PIN(GPIOA_19, EE_OFF) };
+static const unsigned int spdif_out_a20_pins[] = { PIN(GPIOA_20, EE_OFF) };
/* jtag_ee */
-static const unsigned int jtag_tdo_x_pins[] = {GPIOX_0};
-static const unsigned int jtag_tdi_x_pins[] = {GPIOX_1};
-static const unsigned int jtag_clk_x_pins[] = {GPIOX_4};
-static const unsigned int jtag_tms_x_pins[] = {GPIOX_5};
+static const unsigned int jtag_tdo_x_pins[] = { PIN(GPIOX_0, EE_OFF) };
+static const unsigned int jtag_tdi_x_pins[] = { PIN(GPIOX_1, EE_OFF) };
+static const unsigned int jtag_clk_x_pins[] = { PIN(GPIOX_4, EE_OFF) };
+static const unsigned int jtag_tms_x_pins[] = { PIN(GPIOX_5, EE_OFF) };
/* eth */
-static const unsigned int eth_txd0_x_pins[] = {GPIOX_8};
-static const unsigned int eth_txd1_x_pins[] = {GPIOX_9};
-static const unsigned int eth_txen_x_pins[] = {GPIOX_10};
-static const unsigned int eth_rgmii_rx_clk_x_pins[] = {GPIOX_12};
-static const unsigned int eth_rxd0_x_pins[] = {GPIOX_13};
-static const unsigned int eth_rxd1_x_pins[] = {GPIOX_14};
-static const unsigned int eth_rx_dv_x_pins[] = {GPIOX_15};
-static const unsigned int eth_mdio_x_pins[] = {GPIOX_21};
-static const unsigned int eth_mdc_x_pins[] = {GPIOX_22};
+static const unsigned int eth_txd0_x_pins[] = { PIN(GPIOX_8, EE_OFF) };
+static const unsigned int eth_txd1_x_pins[] = { PIN(GPIOX_9, EE_OFF) };
+static const unsigned int eth_txen_x_pins[] = { PIN(GPIOX_10, EE_OFF) };
+static const unsigned int eth_rgmii_rx_clk_x_pins[] = { PIN(GPIOX_12, EE_OFF) };
+static const unsigned int eth_rxd0_x_pins[] = { PIN(GPIOX_13, EE_OFF) };
+static const unsigned int eth_rxd1_x_pins[] = { PIN(GPIOX_14, EE_OFF) };
+static const unsigned int eth_rx_dv_x_pins[] = { PIN(GPIOX_15, EE_OFF) };
+static const unsigned int eth_mdio_x_pins[] = { PIN(GPIOX_21, EE_OFF) };
+static const unsigned int eth_mdc_x_pins[] = { PIN(GPIOX_22, EE_OFF) };
-static const unsigned int eth_txd0_y_pins[] = {GPIOY_10};
-static const unsigned int eth_txd1_y_pins[] = {GPIOY_11};
-static const unsigned int eth_txen_y_pins[] = {GPIOY_9};
-static const unsigned int eth_rgmii_rx_clk_y_pins[] = {GPIOY_2};
-static const unsigned int eth_rxd0_y_pins[] = {GPIOY_4};
-static const unsigned int eth_rxd1_y_pins[] = {GPIOY_5};
-static const unsigned int eth_rx_dv_y_pins[] = {GPIOY_3};
-static const unsigned int eth_mdio_y_pins[] = {GPIOY_0};
-static const unsigned int eth_mdc_y_pins[] = {GPIOY_1};
+static const unsigned int eth_txd0_y_pins[] = { PIN(GPIOY_10, EE_OFF) };
+static const unsigned int eth_txd1_y_pins[] = { PIN(GPIOY_11, EE_OFF) };
+static const unsigned int eth_txen_y_pins[] = { PIN(GPIOY_9, EE_OFF) };
+static const unsigned int eth_rgmii_rx_clk_y_pins[] = { PIN(GPIOY_2, EE_OFF) };
+static const unsigned int eth_rxd0_y_pins[] = { PIN(GPIOY_4, EE_OFF) };
+static const unsigned int eth_rxd1_y_pins[] = { PIN(GPIOY_5, EE_OFF) };
+static const unsigned int eth_rx_dv_y_pins[] = { PIN(GPIOY_3, EE_OFF) };
+static const unsigned int eth_mdio_y_pins[] = { PIN(GPIOY_0, EE_OFF) };
+static const unsigned int eth_mdc_y_pins[] = { PIN(GPIOY_1, EE_OFF) };
-static const unsigned int eth_rxd2_rgmii_pins[] = {GPIOY_6};
-static const unsigned int eth_rxd3_rgmii_pins[] = {GPIOY_7};
-static const unsigned int eth_rgmii_tx_clk_pins[] = {GPIOY_8};
-static const unsigned int eth_txd2_rgmii_pins[] = {GPIOY_12};
-static const unsigned int eth_txd3_rgmii_pins[] = {GPIOY_13};
+static const unsigned int eth_rxd2_rgmii_pins[] = { PIN(GPIOY_6, EE_OFF) };
+static const unsigned int eth_rxd3_rgmii_pins[] = { PIN(GPIOY_7, EE_OFF) };
+static const unsigned int eth_rgmii_tx_clk_pins[] = { PIN(GPIOY_8, EE_OFF) };
+static const unsigned int eth_txd2_rgmii_pins[] = { PIN(GPIOY_12, EE_OFF) };
+static const unsigned int eth_txd3_rgmii_pins[] = { PIN(GPIOY_13, EE_OFF) };
/* pdm */
-static const unsigned int pdm_dclk_a14_pins[] = {GPIOA_14};
-static const unsigned int pdm_dclk_a19_pins[] = {GPIOA_19};
-static const unsigned int pdm_din0_pins[] = {GPIOA_15};
-static const unsigned int pdm_din1_pins[] = {GPIOA_16};
-static const unsigned int pdm_din2_pins[] = {GPIOA_17};
-static const unsigned int pdm_din3_pins[] = {GPIOA_18};
+static const unsigned int pdm_dclk_a14_pins[] = { PIN(GPIOA_14, EE_OFF) };
+static const unsigned int pdm_dclk_a19_pins[] = { PIN(GPIOA_19, EE_OFF) };
+static const unsigned int pdm_din0_pins[] = { PIN(GPIOA_15, EE_OFF) };
+static const unsigned int pdm_din1_pins[] = { PIN(GPIOA_16, EE_OFF) };
+static const unsigned int pdm_din2_pins[] = { PIN(GPIOA_17, EE_OFF) };
+static const unsigned int pdm_din3_pins[] = { PIN(GPIOA_18, EE_OFF) };
/* mclk */
-static const unsigned int mclk_c_pins[] = {GPIOA_0};
-static const unsigned int mclk_b_pins[] = {GPIOA_1};
+static const unsigned int mclk_c_pins[] = { PIN(GPIOA_0, EE_OFF) };
+static const unsigned int mclk_b_pins[] = { PIN(GPIOA_1, EE_OFF) };
/* tdm */
-static const unsigned int tdma_sclk_pins[] = {GPIOX_12};
-static const unsigned int tdma_sclk_slv_pins[] = {GPIOX_12};
-static const unsigned int tdma_fs_pins[] = {GPIOX_13};
-static const unsigned int tdma_fs_slv_pins[] = {GPIOX_13};
-static const unsigned int tdma_din0_pins[] = {GPIOX_14};
-static const unsigned int tdma_dout0_x14_pins[] = {GPIOX_14};
-static const unsigned int tdma_dout0_x15_pins[] = {GPIOX_15};
-static const unsigned int tdma_dout1_pins[] = {GPIOX_15};
-static const unsigned int tdma_din1_pins[] = {GPIOX_15};
+static const unsigned int tdma_sclk_pins[] = { PIN(GPIOX_12, EE_OFF) };
+static const unsigned int tdma_sclk_slv_pins[] = { PIN(GPIOX_12, EE_OFF) };
+static const unsigned int tdma_fs_pins[] = { PIN(GPIOX_13, EE_OFF) };
+static const unsigned int tdma_fs_slv_pins[] = { PIN(GPIOX_13, EE_OFF) };
+static const unsigned int tdma_din0_pins[] = { PIN(GPIOX_14, EE_OFF) };
+static const unsigned int tdma_dout0_x14_pins[] = { PIN(GPIOX_14, EE_OFF) };
+static const unsigned int tdma_dout0_x15_pins[] = { PIN(GPIOX_15, EE_OFF) };
+static const unsigned int tdma_dout1_pins[] = { PIN(GPIOX_15, EE_OFF) };
+static const unsigned int tdma_din1_pins[] = { PIN(GPIOX_15, EE_OFF) };
-static const unsigned int tdmc_sclk_pins[] = {GPIOA_2};
-static const unsigned int tdmc_sclk_slv_pins[] = {GPIOA_2};
-static const unsigned int tdmc_fs_pins[] = {GPIOA_3};
-static const unsigned int tdmc_fs_slv_pins[] = {GPIOA_3};
-static const unsigned int tdmc_din0_pins[] = {GPIOA_4};
-static const unsigned int tdmc_dout0_pins[] = {GPIOA_4};
-static const unsigned int tdmc_din1_pins[] = {GPIOA_5};
-static const unsigned int tdmc_dout1_pins[] = {GPIOA_5};
-static const unsigned int tdmc_din2_pins[] = {GPIOA_6};
-static const unsigned int tdmc_dout2_pins[] = {GPIOA_6};
-static const unsigned int tdmc_din3_pins[] = {GPIOA_7};
-static const unsigned int tdmc_dout3_pins[] = {GPIOA_7};
+static const unsigned int tdmc_sclk_pins[] = { PIN(GPIOA_2, EE_OFF) };
+static const unsigned int tdmc_sclk_slv_pins[] = { PIN(GPIOA_2, EE_OFF) };
+static const unsigned int tdmc_fs_pins[] = { PIN(GPIOA_3, EE_OFF) };
+static const unsigned int tdmc_fs_slv_pins[] = { PIN(GPIOA_3, EE_OFF) };
+static const unsigned int tdmc_din0_pins[] = { PIN(GPIOA_4, EE_OFF) };
+static const unsigned int tdmc_dout0_pins[] = { PIN(GPIOA_4, EE_OFF) };
+static const unsigned int tdmc_din1_pins[] = { PIN(GPIOA_5, EE_OFF) };
+static const unsigned int tdmc_dout1_pins[] = { PIN(GPIOA_5, EE_OFF) };
+static const unsigned int tdmc_din2_pins[] = { PIN(GPIOA_6, EE_OFF) };
+static const unsigned int tdmc_dout2_pins[] = { PIN(GPIOA_6, EE_OFF) };
+static const unsigned int tdmc_din3_pins[] = { PIN(GPIOA_7, EE_OFF) };
+static const unsigned int tdmc_dout3_pins[] = { PIN(GPIOA_7, EE_OFF) };
-static const unsigned int tdmb_sclk_pins[] = {GPIOA_8};
-static const unsigned int tdmb_sclk_slv_pins[] = {GPIOA_8};
-static const unsigned int tdmb_fs_pins[] = {GPIOA_9};
-static const unsigned int tdmb_fs_slv_pins[] = {GPIOA_9};
-static const unsigned int tdmb_din0_pins[] = {GPIOA_10};
-static const unsigned int tdmb_dout0_pins[] = {GPIOA_10};
-static const unsigned int tdmb_din1_pins[] = {GPIOA_11};
-static const unsigned int tdmb_dout1_pins[] = {GPIOA_11};
-static const unsigned int tdmb_din2_pins[] = {GPIOA_12};
-static const unsigned int tdmb_dout2_pins[] = {GPIOA_12};
-static const unsigned int tdmb_din3_pins[] = {GPIOA_13};
-static const unsigned int tdmb_dout3_pins[] = {GPIOA_13};
+static const unsigned int tdmb_sclk_pins[] = { PIN(GPIOA_8, EE_OFF) };
+static const unsigned int tdmb_sclk_slv_pins[] = { PIN(GPIOA_8, EE_OFF) };
+static const unsigned int tdmb_fs_pins[] = { PIN(GPIOA_9, EE_OFF) };
+static const unsigned int tdmb_fs_slv_pins[] = { PIN(GPIOA_9, EE_OFF) };
+static const unsigned int tdmb_din0_pins[] = { PIN(GPIOA_10, EE_OFF) };
+static const unsigned int tdmb_dout0_pins[] = { PIN(GPIOA_10, EE_OFF) };
+static const unsigned int tdmb_din1_pins[] = { PIN(GPIOA_11, EE_OFF) };
+static const unsigned int tdmb_dout1_pins[] = { PIN(GPIOA_11, EE_OFF) };
+static const unsigned int tdmb_din2_pins[] = { PIN(GPIOA_12, EE_OFF) };
+static const unsigned int tdmb_dout2_pins[] = { PIN(GPIOA_12, EE_OFF) };
+static const unsigned int tdmb_din3_pins[] = { PIN(GPIOA_13, EE_OFF) };
+static const unsigned int tdmb_dout3_pins[] = { PIN(GPIOA_13, EE_OFF) };
static struct meson_pmx_group meson_axg_periphs_groups[] = {
GPIO_GROUP(GPIOZ_0, EE_OFF),
@@ -907,12 +907,12 @@
};
static struct meson_pmx_bank meson_axg_periphs_pmx_banks[] = {
- /* name first lask reg offset */
- BANK_PMX("Z", GPIOZ_0, GPIOZ_10, 0x2, 0),
- BANK_PMX("BOOT", BOOT_0, BOOT_14, 0x0, 0),
- BANK_PMX("A", GPIOA_0, GPIOA_20, 0xb, 0),
- BANK_PMX("X", GPIOX_0, GPIOX_22, 0x4, 0),
- BANK_PMX("Y", GPIOY_0, GPIOY_15, 0x8, 0),
+ /* name first last reg offset */
+ BANK_PMX("Z", PIN(GPIOZ_0, EE_OFF), PIN(GPIOZ_10, EE_OFF), 0x2, 0),
+ BANK_PMX("BOOT", PIN(BOOT_0, EE_OFF), PIN(BOOT_14, EE_OFF), 0x0, 0),
+ BANK_PMX("A", PIN(GPIOA_0, EE_OFF), PIN(GPIOA_20, EE_OFF), 0xb, 0),
+ BANK_PMX("X", PIN(GPIOX_0, EE_OFF), PIN(GPIOX_22, EE_OFF), 0x4, 0),
+ BANK_PMX("Y", PIN(GPIOY_0, EE_OFF), PIN(GPIOY_15, EE_OFF), 0x8, 0),
};
static struct meson_axg_pmx_data meson_axg_periphs_pmx_banks_data = {
@@ -931,7 +931,7 @@
struct meson_pinctrl_data meson_axg_periphs_pinctrl_data = {
.name = "periphs-banks",
- .pin_base = 15,
+ .pin_base = EE_OFF,
.groups = meson_axg_periphs_groups,
.funcs = meson_axg_periphs_functions,
.banks = meson_axg_periphs_banks,
diff --git a/drivers/pinctrl/meson/pinctrl-meson-g12a.c b/drivers/pinctrl/meson/pinctrl-meson-g12a.c
new file mode 100644
index 0000000..9cc2b9d
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson-g12a.c
@@ -0,0 +1,1294 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * (C) Copyright (C) 2019 Jerome Brunet <jbrunet@baylibre.com>
+ *
+ * Based on code from Linux kernel:
+ * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
+ * Author: Xingyu Chen <xingyu.chen@amlogic.com>
+ * Author: Yixun Lan <yixun.lan@amlogic.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+
+#include "pinctrl-meson-axg.h"
+
+#define EE_OFF 15
+
+/* emmc */
+static const unsigned int emmc_nand_d0_pins[] = { PIN(BOOT_0, EE_OFF) };
+static const unsigned int emmc_nand_d1_pins[] = { PIN(BOOT_1, EE_OFF) };
+static const unsigned int emmc_nand_d2_pins[] = { PIN(BOOT_2, EE_OFF) };
+static const unsigned int emmc_nand_d3_pins[] = { PIN(BOOT_3, EE_OFF) };
+static const unsigned int emmc_nand_d4_pins[] = { PIN(BOOT_4, EE_OFF) };
+static const unsigned int emmc_nand_d5_pins[] = { PIN(BOOT_5, EE_OFF) };
+static const unsigned int emmc_nand_d6_pins[] = { PIN(BOOT_6, EE_OFF) };
+static const unsigned int emmc_nand_d7_pins[] = { PIN(BOOT_7, EE_OFF) };
+static const unsigned int emmc_clk_pins[] = { PIN(BOOT_8, EE_OFF) };
+static const unsigned int emmc_cmd_pins[] = { PIN(BOOT_10, EE_OFF) };
+static const unsigned int emmc_nand_ds_pins[] = { PIN(BOOT_13, EE_OFF) };
+
+/* nand */
+static const unsigned int nand_wen_clk_pins[] = { PIN(BOOT_8, EE_OFF) };
+static const unsigned int nand_ale_pins[] = { PIN(BOOT_9, EE_OFF) };
+static const unsigned int nand_cle_pins[] = { PIN(BOOT_10, EE_OFF) };
+static const unsigned int nand_ce0_pins[] = { PIN(BOOT_11, EE_OFF) };
+static const unsigned int nand_ren_wr_pins[] = { PIN(BOOT_12, EE_OFF) };
+static const unsigned int nand_rb0_pins[] = { PIN(BOOT_14, EE_OFF) };
+static const unsigned int nand_ce1_pins[] = { PIN(BOOT_15, EE_OFF) };
+
+/* nor */
+static const unsigned int nor_hold_pins[] = { PIN(BOOT_3, EE_OFF) };
+static const unsigned int nor_d_pins[] = { PIN(BOOT_4, EE_OFF) };
+static const unsigned int nor_q_pins[] = { PIN(BOOT_5, EE_OFF) };
+static const unsigned int nor_c_pins[] = { PIN(BOOT_6, EE_OFF) };
+static const unsigned int nor_wp_pins[] = { PIN(BOOT_7, EE_OFF) };
+static const unsigned int nor_cs_pins[] = { PIN(BOOT_14, EE_OFF) };
+
+/* sdio */
+static const unsigned int sdio_d0_pins[] = { PIN(GPIOX_0, EE_OFF) };
+static const unsigned int sdio_d1_pins[] = { PIN(GPIOX_1, EE_OFF) };
+static const unsigned int sdio_d2_pins[] = { PIN(GPIOX_2, EE_OFF) };
+static const unsigned int sdio_d3_pins[] = { PIN(GPIOX_3, EE_OFF) };
+static const unsigned int sdio_clk_pins[] = { PIN(GPIOX_4, EE_OFF) };
+static const unsigned int sdio_cmd_pins[] = { PIN(GPIOX_5, EE_OFF) };
+
+/* sdcard */
+static const unsigned int sdcard_d0_c_pins[] = { PIN(GPIOC_0, EE_OFF) };
+static const unsigned int sdcard_d1_c_pins[] = { PIN(GPIOC_1, EE_OFF) };
+static const unsigned int sdcard_d2_c_pins[] = { PIN(GPIOC_2, EE_OFF) };
+static const unsigned int sdcard_d3_c_pins[] = { PIN(GPIOC_3, EE_OFF) };
+static const unsigned int sdcard_clk_c_pins[] = { PIN(GPIOC_4, EE_OFF) };
+static const unsigned int sdcard_cmd_c_pins[] = { PIN(GPIOC_5, EE_OFF) };
+
+static const unsigned int sdcard_d0_z_pins[] = { PIN(GPIOZ_2, EE_OFF) };
+static const unsigned int sdcard_d1_z_pins[] = { PIN(GPIOZ_3, EE_OFF) };
+static const unsigned int sdcard_d2_z_pins[] = { PIN(GPIOZ_4, EE_OFF) };
+static const unsigned int sdcard_d3_z_pins[] = { PIN(GPIOZ_5, EE_OFF) };
+static const unsigned int sdcard_clk_z_pins[] = { PIN(GPIOZ_6, EE_OFF) };
+static const unsigned int sdcard_cmd_z_pins[] = { PIN(GPIOZ_7, EE_OFF) };
+
+/* spi0 */
+static const unsigned int spi0_mosi_c_pins[] = { PIN(GPIOC_0, EE_OFF) };
+static const unsigned int spi0_miso_c_pins[] = { PIN(GPIOC_1, EE_OFF) };
+static const unsigned int spi0_ss0_c_pins[] = { PIN(GPIOC_2, EE_OFF) };
+static const unsigned int spi0_clk_c_pins[] = { PIN(GPIOC_3, EE_OFF) };
+
+static const unsigned int spi0_mosi_x_pins[] = { PIN(GPIOX_8, EE_OFF) };
+static const unsigned int spi0_miso_x_pins[] = { PIN(GPIOX_9, EE_OFF) };
+static const unsigned int spi0_ss0_x_pins[] = { PIN(GPIOX_10, EE_OFF) };
+static const unsigned int spi0_clk_x_pins[] = { PIN(GPIOX_11, EE_OFF) };
+
+/* spi1 */
+static const unsigned int spi1_mosi_pins[] = { PIN(GPIOH_4, EE_OFF) };
+static const unsigned int spi1_miso_pins[] = { PIN(GPIOH_5, EE_OFF) };
+static const unsigned int spi1_ss0_pins[] = { PIN(GPIOH_6, EE_OFF) };
+static const unsigned int spi1_clk_pins[] = { PIN(GPIOH_7, EE_OFF) };
+
+/* i2c0 */
+static const unsigned int i2c0_sda_c_pins[] = { PIN(GPIOC_5, EE_OFF) };
+static const unsigned int i2c0_sck_c_pins[] = { PIN(GPIOC_6, EE_OFF) };
+static const unsigned int i2c0_sda_z0_pins[] = { PIN(GPIOZ_0, EE_OFF) };
+static const unsigned int i2c0_sck_z1_pins[] = { PIN(GPIOZ_1, EE_OFF) };
+static const unsigned int i2c0_sda_z7_pins[] = { PIN(GPIOZ_7, EE_OFF) };
+static const unsigned int i2c0_sck_z8_pins[] = { PIN(GPIOZ_8, EE_OFF) };
+
+/* i2c1 */
+static const unsigned int i2c1_sda_x_pins[] = { PIN(GPIOX_10, EE_OFF) };
+static const unsigned int i2c1_sck_x_pins[] = { PIN(GPIOX_11, EE_OFF) };
+static const unsigned int i2c1_sda_h2_pins[] = { PIN(GPIOH_2, EE_OFF) };
+static const unsigned int i2c1_sck_h3_pins[] = { PIN(GPIOH_3, EE_OFF) };
+static const unsigned int i2c1_sda_h6_pins[] = { PIN(GPIOH_6, EE_OFF) };
+static const unsigned int i2c1_sck_h7_pins[] = { PIN(GPIOH_7, EE_OFF) };
+
+/* i2c2 */
+static const unsigned int i2c2_sda_x_pins[] = { PIN(GPIOX_17, EE_OFF) };
+static const unsigned int i2c2_sck_x_pins[] = { PIN(GPIOX_18, EE_OFF) };
+static const unsigned int i2c2_sda_z_pins[] = { PIN(GPIOZ_14, EE_OFF) };
+static const unsigned int i2c2_sck_z_pins[] = { PIN(GPIOZ_15, EE_OFF) };
+
+/* i2c3 */
+static const unsigned int i2c3_sda_h_pins[] = { PIN(GPIOH_0, EE_OFF) };
+static const unsigned int i2c3_sck_h_pins[] = { PIN(GPIOH_1, EE_OFF) };
+static const unsigned int i2c3_sda_a_pins[] = { PIN(GPIOA_14, EE_OFF) };
+static const unsigned int i2c3_sck_a_pins[] = { PIN(GPIOA_15, EE_OFF) };
+
+/* uart_a */
+static const unsigned int uart_a_tx_pins[] = { PIN(GPIOX_12, EE_OFF) };
+static const unsigned int uart_a_rx_pins[] = { PIN(GPIOX_13, EE_OFF) };
+static const unsigned int uart_a_cts_pins[] = { PIN(GPIOX_14, EE_OFF) };
+static const unsigned int uart_a_rts_pins[] = { PIN(GPIOX_15, EE_OFF) };
+
+/* uart_b */
+static const unsigned int uart_b_tx_pins[] = { PIN(GPIOX_6, EE_OFF) };
+static const unsigned int uart_b_rx_pins[] = { PIN(GPIOX_7, EE_OFF) };
+
+/* uart_c */
+static const unsigned int uart_c_rts_pins[] = { PIN(GPIOH_4, EE_OFF) };
+static const unsigned int uart_c_cts_pins[] = { PIN(GPIOH_5, EE_OFF) };
+static const unsigned int uart_c_rx_pins[] = { PIN(GPIOH_6, EE_OFF) };
+static const unsigned int uart_c_tx_pins[] = { PIN(GPIOH_7, EE_OFF) };
+
+/* uart_ao_a_c */
+static const unsigned int uart_ao_a_rx_c_pins[] = { PIN(GPIOC_2, EE_OFF) };
+static const unsigned int uart_ao_a_tx_c_pins[] = { PIN(GPIOC_3, EE_OFF) };
+
+/* iso7816 */
+static const unsigned int iso7816_clk_c_pins[] = { PIN(GPIOC_5, EE_OFF) };
+static const unsigned int iso7816_data_c_pins[] = { PIN(GPIOC_6, EE_OFF) };
+static const unsigned int iso7816_clk_x_pins[] = { PIN(GPIOX_8, EE_OFF) };
+static const unsigned int iso7816_data_x_pins[] = { PIN(GPIOX_9, EE_OFF) };
+static const unsigned int iso7816_clk_h_pins[] = { PIN(GPIOH_6, EE_OFF) };
+static const unsigned int iso7816_data_h_pins[] = { PIN(GPIOH_7, EE_OFF) };
+static const unsigned int iso7816_clk_z_pins[] = { PIN(GPIOZ_0, EE_OFF) };
+static const unsigned int iso7816_data_z_pins[] = { PIN(GPIOZ_1, EE_OFF) };
+
+/* eth */
+static const unsigned int eth_mdio_pins[] = { PIN(GPIOZ_0, EE_OFF) };
+static const unsigned int eth_mdc_pins[] = { PIN(GPIOZ_1, EE_OFF) };
+static const unsigned int eth_rgmii_rx_clk_pins[] = { PIN(GPIOZ_2, EE_OFF) };
+static const unsigned int eth_rx_dv_pins[] = { PIN(GPIOZ_3, EE_OFF) };
+static const unsigned int eth_rxd0_pins[] = { PIN(GPIOZ_4, EE_OFF) };
+static const unsigned int eth_rxd1_pins[] = { PIN(GPIOZ_5, EE_OFF) };
+static const unsigned int eth_rxd2_rgmii_pins[] = { PIN(GPIOZ_6, EE_OFF) };
+static const unsigned int eth_rxd3_rgmii_pins[] = { PIN(GPIOZ_7, EE_OFF) };
+static const unsigned int eth_rgmii_tx_clk_pins[] = { PIN(GPIOZ_8, EE_OFF) };
+static const unsigned int eth_txen_pins[] = { PIN(GPIOZ_9, EE_OFF) };
+static const unsigned int eth_txd0_pins[] = { PIN(GPIOZ_10, EE_OFF) };
+static const unsigned int eth_txd1_pins[] = { PIN(GPIOZ_11, EE_OFF) };
+static const unsigned int eth_txd2_rgmii_pins[] = { PIN(GPIOZ_12, EE_OFF) };
+static const unsigned int eth_txd3_rgmii_pins[] = { PIN(GPIOZ_13, EE_OFF) };
+static const unsigned int eth_link_led_pins[] = { PIN(GPIOZ_14, EE_OFF) };
+static const unsigned int eth_act_led_pins[] = { PIN(GPIOZ_15, EE_OFF) };
+
+/* pwm_a */
+static const unsigned int pwm_a_pins[] = { PIN(GPIOX_6, EE_OFF) };
+
+/* pwm_b */
+static const unsigned int pwm_b_x7_pins[] = { PIN(GPIOX_7, EE_OFF) };
+static const unsigned int pwm_b_x19_pins[] = { PIN(GPIOX_19, EE_OFF) };
+
+/* pwm_c */
+static const unsigned int pwm_c_c_pins[] = { PIN(GPIOC_4, EE_OFF) };
+static const unsigned int pwm_c_x5_pins[] = { PIN(GPIOX_5, EE_OFF) };
+static const unsigned int pwm_c_x8_pins[] = { PIN(GPIOX_8, EE_OFF) };
+
+/* pwm_d */
+static const unsigned int pwm_d_x3_pins[] = { PIN(GPIOX_3, EE_OFF) };
+static const unsigned int pwm_d_x6_pins[] = { PIN(GPIOX_6, EE_OFF) };
+
+/* pwm_e */
+static const unsigned int pwm_e_pins[] = { PIN(GPIOX_16, EE_OFF) };
+
+/* pwm_f */
+static const unsigned int pwm_f_x_pins[] = { PIN(GPIOX_7, EE_OFF) };
+static const unsigned int pwm_f_h_pins[] = { PIN(GPIOH_5, EE_OFF) };
+
+/* cec_ao */
+static const unsigned int cec_ao_a_h_pins[] = { PIN(GPIOH_3, EE_OFF) };
+static const unsigned int cec_ao_b_h_pins[] = { PIN(GPIOH_3, EE_OFF) };
+
+/* jtag_b */
+static const unsigned int jtag_b_tdo_pins[] = { PIN(GPIOC_0, EE_OFF) };
+static const unsigned int jtag_b_tdi_pins[] = { PIN(GPIOC_1, EE_OFF) };
+static const unsigned int jtag_b_clk_pins[] = { PIN(GPIOC_4, EE_OFF) };
+static const unsigned int jtag_b_tms_pins[] = { PIN(GPIOC_5, EE_OFF) };
+
+/* bt565_a */
+static const unsigned int bt565_a_vs_pins[] = { PIN(GPIOZ_0, EE_OFF) };
+static const unsigned int bt565_a_hs_pins[] = { PIN(GPIOZ_1, EE_OFF) };
+static const unsigned int bt565_a_clk_pins[] = { PIN(GPIOZ_3, EE_OFF) };
+static const unsigned int bt565_a_din0_pins[] = { PIN(GPIOZ_4, EE_OFF) };
+static const unsigned int bt565_a_din1_pins[] = { PIN(GPIOZ_5, EE_OFF) };
+static const unsigned int bt565_a_din2_pins[] = { PIN(GPIOZ_6, EE_OFF) };
+static const unsigned int bt565_a_din3_pins[] = { PIN(GPIOZ_7, EE_OFF) };
+static const unsigned int bt565_a_din4_pins[] = { PIN(GPIOZ_8, EE_OFF) };
+static const unsigned int bt565_a_din5_pins[] = { PIN(GPIOZ_9, EE_OFF) };
+static const unsigned int bt565_a_din6_pins[] = { PIN(GPIOZ_10, EE_OFF) };
+static const unsigned int bt565_a_din7_pins[] = { PIN(GPIOZ_11, EE_OFF) };
+
+/* tsin_a */
+static const unsigned int tsin_a_valid_pins[] = { PIN(GPIOX_2, EE_OFF) };
+static const unsigned int tsin_a_sop_pins[] = { PIN(GPIOX_1, EE_OFF) };
+static const unsigned int tsin_a_din0_pins[] = { PIN(GPIOX_0, EE_OFF) };
+static const unsigned int tsin_a_clk_pins[] = { PIN(GPIOX_3, EE_OFF) };
+
+/* tsin_b */
+static const unsigned int tsin_b_valid_x_pins[] = { PIN(GPIOX_9, EE_OFF) };
+static const unsigned int tsin_b_sop_x_pins[] = { PIN(GPIOX_8, EE_OFF) };
+static const unsigned int tsin_b_din0_x_pins[] = { PIN(GPIOX_10, EE_OFF) };
+static const unsigned int tsin_b_clk_x_pins[] = { PIN(GPIOX_11, EE_OFF) };
+
+static const unsigned int tsin_b_valid_z_pins[] = { PIN(GPIOZ_2, EE_OFF) };
+static const unsigned int tsin_b_sop_z_pins[] = { PIN(GPIOZ_3, EE_OFF) };
+static const unsigned int tsin_b_din0_z_pins[] = { PIN(GPIOZ_4, EE_OFF) };
+static const unsigned int tsin_b_clk_z_pins[] = { PIN(GPIOZ_5, EE_OFF) };
+
+static const unsigned int tsin_b_fail_pins[] = { PIN(GPIOZ_6, EE_OFF) };
+static const unsigned int tsin_b_din1_pins[] = { PIN(GPIOZ_7, EE_OFF) };
+static const unsigned int tsin_b_din2_pins[] = { PIN(GPIOZ_8, EE_OFF) };
+static const unsigned int tsin_b_din3_pins[] = { PIN(GPIOZ_9, EE_OFF) };
+static const unsigned int tsin_b_din4_pins[] = { PIN(GPIOZ_10, EE_OFF) };
+static const unsigned int tsin_b_din5_pins[] = { PIN(GPIOZ_11, EE_OFF) };
+static const unsigned int tsin_b_din6_pins[] = { PIN(GPIOZ_12, EE_OFF) };
+static const unsigned int tsin_b_din7_pins[] = { PIN(GPIOZ_13, EE_OFF) };
+
+/* hdmitx */
+static const unsigned int hdmitx_sda_pins[] = { PIN(GPIOH_0, EE_OFF) };
+static const unsigned int hdmitx_sck_pins[] = { PIN(GPIOH_1, EE_OFF) };
+static const unsigned int hdmitx_hpd_in_pins[] = { PIN(GPIOH_2, EE_OFF) };
+
+/* pdm */
+static const unsigned int pdm_din0_c_pins[] = { PIN(GPIOC_0, EE_OFF) };
+static const unsigned int pdm_din1_c_pins[] = { PIN(GPIOC_1, EE_OFF) };
+static const unsigned int pdm_din2_c_pins[] = { PIN(GPIOC_2, EE_OFF) };
+static const unsigned int pdm_din3_c_pins[] = { PIN(GPIOC_3, EE_OFF) };
+static const unsigned int pdm_dclk_c_pins[] = { PIN(GPIOC_4, EE_OFF) };
+
+static const unsigned int pdm_din0_x_pins[] = { PIN(GPIOX_0, EE_OFF) };
+static const unsigned int pdm_din1_x_pins[] = { PIN(GPIOX_1, EE_OFF) };
+static const unsigned int pdm_din2_x_pins[] = { PIN(GPIOX_2, EE_OFF) };
+static const unsigned int pdm_din3_x_pins[] = { PIN(GPIOX_3, EE_OFF) };
+static const unsigned int pdm_dclk_x_pins[] = { PIN(GPIOX_4, EE_OFF) };
+
+static const unsigned int pdm_din0_z_pins[] = { PIN(GPIOZ_2, EE_OFF) };
+static const unsigned int pdm_din1_z_pins[] = { PIN(GPIOZ_3, EE_OFF) };
+static const unsigned int pdm_din2_z_pins[] = { PIN(GPIOZ_4, EE_OFF) };
+static const unsigned int pdm_din3_z_pins[] = { PIN(GPIOZ_5, EE_OFF) };
+static const unsigned int pdm_dclk_z_pins[] = { PIN(GPIOZ_6, EE_OFF) };
+
+static const unsigned int pdm_din0_a_pins[] = { PIN(GPIOA_8, EE_OFF) };
+static const unsigned int pdm_din1_a_pins[] = { PIN(GPIOA_9, EE_OFF) };
+static const unsigned int pdm_din2_a_pins[] = { PIN(GPIOA_6, EE_OFF) };
+static const unsigned int pdm_din3_a_pins[] = { PIN(GPIOA_5, EE_OFF) };
+static const unsigned int pdm_dclk_a_pins[] = { PIN(GPIOA_7, EE_OFF) };
+
+/* spdif_in */
+static const unsigned int spdif_in_h_pins[] = { PIN(GPIOH_5, EE_OFF) };
+static const unsigned int spdif_in_a10_pins[] = { PIN(GPIOA_10, EE_OFF) };
+static const unsigned int spdif_in_a12_pins[] = { PIN(GPIOA_12, EE_OFF) };
+
+/* spdif_out */
+static const unsigned int spdif_out_h_pins[] = { PIN(GPIOH_4, EE_OFF) };
+static const unsigned int spdif_out_a11_pins[] = { PIN(GPIOA_11, EE_OFF) };
+static const unsigned int spdif_out_a13_pins[] = { PIN(GPIOA_13, EE_OFF) };
+
+/* mclk0 */
+static const unsigned int mclk0_a_pins[] = { PIN(GPIOA_0, EE_OFF) };
+
+/* mclk1 */
+static const unsigned int mclk1_x_pins[] = { PIN(GPIOX_5, EE_OFF) };
+static const unsigned int mclk1_z_pins[] = { PIN(GPIOZ_8, EE_OFF) };
+static const unsigned int mclk1_a_pins[] = { PIN(GPIOA_11, EE_OFF) };
+
+/* tdm */
+static const unsigned int tdm_a_slv_sclk_pins[] = { PIN(GPIOX_11, EE_OFF) };
+static const unsigned int tdm_a_slv_fs_pins[] = { PIN(GPIOX_10, EE_OFF) };
+static const unsigned int tdm_a_sclk_pins[] = { PIN(GPIOX_11, EE_OFF) };
+static const unsigned int tdm_a_fs_pins[] = { PIN(GPIOX_10, EE_OFF) };
+static const unsigned int tdm_a_din0_pins[] = { PIN(GPIOX_9, EE_OFF) };
+static const unsigned int tdm_a_din1_pins[] = { PIN(GPIOX_8, EE_OFF) };
+static const unsigned int tdm_a_dout0_pins[] = { PIN(GPIOX_9, EE_OFF) };
+static const unsigned int tdm_a_dout1_pins[] = { PIN(GPIOX_8, EE_OFF) };
+
+static const unsigned int tdm_b_slv_sclk_pins[] = { PIN(GPIOA_1, EE_OFF) };
+static const unsigned int tdm_b_slv_fs_pins[] = { PIN(GPIOA_2, EE_OFF) };
+static const unsigned int tdm_b_sclk_pins[] = { PIN(GPIOA_1, EE_OFF) };
+static const unsigned int tdm_b_fs_pins[] = { PIN(GPIOA_2, EE_OFF) };
+static const unsigned int tdm_b_din0_pins[] = { PIN(GPIOA_3, EE_OFF) };
+static const unsigned int tdm_b_din1_pins[] = { PIN(GPIOA_4, EE_OFF) };
+static const unsigned int tdm_b_din2_pins[] = { PIN(GPIOA_5, EE_OFF) };
+static const unsigned int tdm_b_din3_a_pins[] = { PIN(GPIOA_6, EE_OFF) };
+static const unsigned int tdm_b_din3_h_pins[] = { PIN(GPIOH_5, EE_OFF) };
+static const unsigned int tdm_b_dout0_pins[] = { PIN(GPIOA_3, EE_OFF) };
+static const unsigned int tdm_b_dout1_pins[] = { PIN(GPIOA_4, EE_OFF) };
+static const unsigned int tdm_b_dout2_pins[] = { PIN(GPIOA_5, EE_OFF) };
+static const unsigned int tdm_b_dout3_a_pins[] = { PIN(GPIOA_6, EE_OFF) };
+static const unsigned int tdm_b_dout3_h_pins[] = { PIN(GPIOH_5, EE_OFF) };
+
+static const unsigned int tdm_c_slv_sclk_a_pins[] = { PIN(GPIOA_12, EE_OFF) };
+static const unsigned int tdm_c_slv_fs_a_pins[] = { PIN(GPIOA_13, EE_OFF) };
+static const unsigned int tdm_c_slv_sclk_z_pins[] = { PIN(GPIOZ_7, EE_OFF) };
+static const unsigned int tdm_c_slv_fs_z_pins[] = { PIN(GPIOZ_6, EE_OFF) };
+static const unsigned int tdm_c_sclk_a_pins[] = { PIN(GPIOA_12, EE_OFF) };
+static const unsigned int tdm_c_fs_a_pins[] = { PIN(GPIOA_13, EE_OFF) };
+static const unsigned int tdm_c_sclk_z_pins[] = { PIN(GPIOZ_7, EE_OFF) };
+static const unsigned int tdm_c_fs_z_pins[] = { PIN(GPIOZ_6, EE_OFF) };
+static const unsigned int tdm_c_din0_a_pins[] = { PIN(GPIOA_10, EE_OFF) };
+static const unsigned int tdm_c_din1_a_pins[] = { PIN(GPIOA_9, EE_OFF) };
+static const unsigned int tdm_c_din2_a_pins[] = { PIN(GPIOA_8, EE_OFF) };
+static const unsigned int tdm_c_din3_a_pins[] = { PIN(GPIOA_7, EE_OFF) };
+static const unsigned int tdm_c_din0_z_pins[] = { PIN(GPIOZ_2, EE_OFF) };
+static const unsigned int tdm_c_din1_z_pins[] = { PIN(GPIOZ_3, EE_OFF) };
+static const unsigned int tdm_c_din2_z_pins[] = { PIN(GPIOZ_4, EE_OFF) };
+static const unsigned int tdm_c_din3_z_pins[] = { PIN(GPIOZ_5, EE_OFF) };
+static const unsigned int tdm_c_dout0_a_pins[] = { PIN(GPIOA_10, EE_OFF) };
+static const unsigned int tdm_c_dout1_a_pins[] = { PIN(GPIOA_9, EE_OFF) };
+static const unsigned int tdm_c_dout2_a_pins[] = { PIN(GPIOA_8, EE_OFF) };
+static const unsigned int tdm_c_dout3_a_pins[] = { PIN(GPIOA_7, EE_OFF) };
+static const unsigned int tdm_c_dout0_z_pins[] = { PIN(GPIOZ_2, EE_OFF) };
+static const unsigned int tdm_c_dout1_z_pins[] = { PIN(GPIOZ_3, EE_OFF) };
+static const unsigned int tdm_c_dout2_z_pins[] = { PIN(GPIOZ_4, EE_OFF) };
+static const unsigned int tdm_c_dout3_z_pins[] = { PIN(GPIOZ_5, EE_OFF) };
+
+static struct meson_pmx_group meson_g12a_periphs_groups[] = {
+ GPIO_GROUP(GPIOZ_0, EE_OFF),
+ GPIO_GROUP(GPIOZ_1, EE_OFF),
+ GPIO_GROUP(GPIOZ_2, EE_OFF),
+ GPIO_GROUP(GPIOZ_3, EE_OFF),
+ GPIO_GROUP(GPIOZ_4, EE_OFF),
+ GPIO_GROUP(GPIOZ_5, EE_OFF),
+ GPIO_GROUP(GPIOZ_6, EE_OFF),
+ GPIO_GROUP(GPIOZ_7, EE_OFF),
+ GPIO_GROUP(GPIOZ_8, EE_OFF),
+ GPIO_GROUP(GPIOZ_9, EE_OFF),
+ GPIO_GROUP(GPIOZ_10, EE_OFF),
+ GPIO_GROUP(GPIOZ_11, EE_OFF),
+ GPIO_GROUP(GPIOZ_12, EE_OFF),
+ GPIO_GROUP(GPIOZ_13, EE_OFF),
+ GPIO_GROUP(GPIOZ_14, EE_OFF),
+ GPIO_GROUP(GPIOZ_15, EE_OFF),
+ GPIO_GROUP(GPIOH_0, EE_OFF),
+ GPIO_GROUP(GPIOH_1, EE_OFF),
+ GPIO_GROUP(GPIOH_2, EE_OFF),
+ GPIO_GROUP(GPIOH_3, EE_OFF),
+ GPIO_GROUP(GPIOH_4, EE_OFF),
+ GPIO_GROUP(GPIOH_5, EE_OFF),
+ GPIO_GROUP(GPIOH_6, EE_OFF),
+ GPIO_GROUP(GPIOH_7, EE_OFF),
+ GPIO_GROUP(GPIOH_8, EE_OFF),
+ GPIO_GROUP(BOOT_0, EE_OFF),
+ GPIO_GROUP(BOOT_1, EE_OFF),
+ GPIO_GROUP(BOOT_2, EE_OFF),
+ GPIO_GROUP(BOOT_3, EE_OFF),
+ GPIO_GROUP(BOOT_4, EE_OFF),
+ GPIO_GROUP(BOOT_5, EE_OFF),
+ GPIO_GROUP(BOOT_6, EE_OFF),
+ GPIO_GROUP(BOOT_7, EE_OFF),
+ GPIO_GROUP(BOOT_8, EE_OFF),
+ GPIO_GROUP(BOOT_9, EE_OFF),
+ GPIO_GROUP(BOOT_10, EE_OFF),
+ GPIO_GROUP(BOOT_11, EE_OFF),
+ GPIO_GROUP(BOOT_12, EE_OFF),
+ GPIO_GROUP(BOOT_13, EE_OFF),
+ GPIO_GROUP(BOOT_14, EE_OFF),
+ GPIO_GROUP(BOOT_15, EE_OFF),
+ GPIO_GROUP(GPIOC_0, EE_OFF),
+ GPIO_GROUP(GPIOC_1, EE_OFF),
+ GPIO_GROUP(GPIOC_2, EE_OFF),
+ GPIO_GROUP(GPIOC_3, EE_OFF),
+ GPIO_GROUP(GPIOC_4, EE_OFF),
+ GPIO_GROUP(GPIOC_5, EE_OFF),
+ GPIO_GROUP(GPIOC_6, EE_OFF),
+ GPIO_GROUP(GPIOC_7, EE_OFF),
+ GPIO_GROUP(GPIOA_0, EE_OFF),
+ GPIO_GROUP(GPIOA_1, EE_OFF),
+ GPIO_GROUP(GPIOA_2, EE_OFF),
+ GPIO_GROUP(GPIOA_3, EE_OFF),
+ GPIO_GROUP(GPIOA_4, EE_OFF),
+ GPIO_GROUP(GPIOA_5, EE_OFF),
+ GPIO_GROUP(GPIOA_6, EE_OFF),
+ GPIO_GROUP(GPIOA_7, EE_OFF),
+ GPIO_GROUP(GPIOA_8, EE_OFF),
+ GPIO_GROUP(GPIOA_9, EE_OFF),
+ GPIO_GROUP(GPIOA_10, EE_OFF),
+ GPIO_GROUP(GPIOA_11, EE_OFF),
+ GPIO_GROUP(GPIOA_12, EE_OFF),
+ GPIO_GROUP(GPIOA_13, EE_OFF),
+ GPIO_GROUP(GPIOA_14, EE_OFF),
+ GPIO_GROUP(GPIOA_15, EE_OFF),
+ GPIO_GROUP(GPIOX_0, EE_OFF),
+ GPIO_GROUP(GPIOX_1, EE_OFF),
+ GPIO_GROUP(GPIOX_2, EE_OFF),
+ GPIO_GROUP(GPIOX_3, EE_OFF),
+ GPIO_GROUP(GPIOX_4, EE_OFF),
+ GPIO_GROUP(GPIOX_5, EE_OFF),
+ GPIO_GROUP(GPIOX_6, EE_OFF),
+ GPIO_GROUP(GPIOX_7, EE_OFF),
+ GPIO_GROUP(GPIOX_8, EE_OFF),
+ GPIO_GROUP(GPIOX_9, EE_OFF),
+ GPIO_GROUP(GPIOX_10, EE_OFF),
+ GPIO_GROUP(GPIOX_11, EE_OFF),
+ GPIO_GROUP(GPIOX_12, EE_OFF),
+ GPIO_GROUP(GPIOX_13, EE_OFF),
+ GPIO_GROUP(GPIOX_14, EE_OFF),
+ GPIO_GROUP(GPIOX_15, EE_OFF),
+ GPIO_GROUP(GPIOX_16, EE_OFF),
+ GPIO_GROUP(GPIOX_17, EE_OFF),
+ GPIO_GROUP(GPIOX_18, EE_OFF),
+ GPIO_GROUP(GPIOX_19, EE_OFF),
+
+ /* bank BOOT */
+ GROUP(emmc_nand_d0, 1),
+ GROUP(emmc_nand_d1, 1),
+ GROUP(emmc_nand_d2, 1),
+ GROUP(emmc_nand_d3, 1),
+ GROUP(emmc_nand_d4, 1),
+ GROUP(emmc_nand_d5, 1),
+ GROUP(emmc_nand_d6, 1),
+ GROUP(emmc_nand_d7, 1),
+ GROUP(emmc_clk, 1),
+ GROUP(emmc_cmd, 1),
+ GROUP(emmc_nand_ds, 1),
+ GROUP(nand_ce0, 2),
+ GROUP(nand_ale, 2),
+ GROUP(nand_cle, 2),
+ GROUP(nand_wen_clk, 2),
+ GROUP(nand_ren_wr, 2),
+ GROUP(nand_rb0, 2),
+ GROUP(nand_ce1, 2),
+ GROUP(nor_hold, 3),
+ GROUP(nor_d, 3),
+ GROUP(nor_q, 3),
+ GROUP(nor_c, 3),
+ GROUP(nor_wp, 3),
+ GROUP(nor_cs, 3),
+
+ /* bank GPIOZ */
+ GROUP(sdcard_d0_z, 5),
+ GROUP(sdcard_d1_z, 5),
+ GROUP(sdcard_d2_z, 5),
+ GROUP(sdcard_d3_z, 5),
+ GROUP(sdcard_clk_z, 5),
+ GROUP(sdcard_cmd_z, 5),
+ GROUP(i2c0_sda_z0, 4),
+ GROUP(i2c0_sck_z1, 4),
+ GROUP(i2c0_sda_z7, 7),
+ GROUP(i2c0_sck_z8, 7),
+ GROUP(i2c2_sda_z, 3),
+ GROUP(i2c2_sck_z, 3),
+ GROUP(iso7816_clk_z, 3),
+ GROUP(iso7816_data_z, 3),
+ GROUP(eth_mdio, 1),
+ GROUP(eth_mdc, 1),
+ GROUP(eth_rgmii_rx_clk, 1),
+ GROUP(eth_rx_dv, 1),
+ GROUP(eth_rxd0, 1),
+ GROUP(eth_rxd1, 1),
+ GROUP(eth_rxd2_rgmii, 1),
+ GROUP(eth_rxd3_rgmii, 1),
+ GROUP(eth_rgmii_tx_clk, 1),
+ GROUP(eth_txen, 1),
+ GROUP(eth_txd0, 1),
+ GROUP(eth_txd1, 1),
+ GROUP(eth_txd2_rgmii, 1),
+ GROUP(eth_txd3_rgmii, 1),
+ GROUP(eth_link_led, 1),
+ GROUP(eth_act_led, 1),
+ GROUP(bt565_a_vs, 2),
+ GROUP(bt565_a_hs, 2),
+ GROUP(bt565_a_clk, 2),
+ GROUP(bt565_a_din0, 2),
+ GROUP(bt565_a_din1, 2),
+ GROUP(bt565_a_din2, 2),
+ GROUP(bt565_a_din3, 2),
+ GROUP(bt565_a_din4, 2),
+ GROUP(bt565_a_din5, 2),
+ GROUP(bt565_a_din6, 2),
+ GROUP(bt565_a_din7, 2),
+ GROUP(tsin_b_valid_z, 3),
+ GROUP(tsin_b_sop_z, 3),
+ GROUP(tsin_b_din0_z, 3),
+ GROUP(tsin_b_clk_z, 3),
+ GROUP(tsin_b_fail, 3),
+ GROUP(tsin_b_din1, 3),
+ GROUP(tsin_b_din2, 3),
+ GROUP(tsin_b_din3, 3),
+ GROUP(tsin_b_din4, 3),
+ GROUP(tsin_b_din5, 3),
+ GROUP(tsin_b_din6, 3),
+ GROUP(tsin_b_din7, 3),
+ GROUP(pdm_din0_z, 7),
+ GROUP(pdm_din1_z, 7),
+ GROUP(pdm_din2_z, 7),
+ GROUP(pdm_din3_z, 7),
+ GROUP(pdm_dclk_z, 7),
+ GROUP(tdm_c_slv_sclk_z, 6),
+ GROUP(tdm_c_slv_fs_z, 6),
+ GROUP(tdm_c_din0_z, 6),
+ GROUP(tdm_c_din1_z, 6),
+ GROUP(tdm_c_din2_z, 6),
+ GROUP(tdm_c_din3_z, 6),
+ GROUP(tdm_c_sclk_z, 4),
+ GROUP(tdm_c_fs_z, 4),
+ GROUP(tdm_c_dout0_z, 4),
+ GROUP(tdm_c_dout1_z, 4),
+ GROUP(tdm_c_dout2_z, 4),
+ GROUP(tdm_c_dout3_z, 4),
+ GROUP(mclk1_z, 4),
+
+ /* bank GPIOX */
+ GROUP(sdio_d0, 1),
+ GROUP(sdio_d1, 1),
+ GROUP(sdio_d2, 1),
+ GROUP(sdio_d3, 1),
+ GROUP(sdio_clk, 1),
+ GROUP(sdio_cmd, 1),
+ GROUP(spi0_mosi_x, 4),
+ GROUP(spi0_miso_x, 4),
+ GROUP(spi0_ss0_x, 4),
+ GROUP(spi0_clk_x, 4),
+ GROUP(i2c1_sda_x, 5),
+ GROUP(i2c1_sck_x, 5),
+ GROUP(i2c2_sda_x, 1),
+ GROUP(i2c2_sck_x, 1),
+ GROUP(uart_a_tx, 1),
+ GROUP(uart_a_rx, 1),
+ GROUP(uart_a_cts, 1),
+ GROUP(uart_a_rts, 1),
+ GROUP(uart_b_tx, 2),
+ GROUP(uart_b_rx, 2),
+ GROUP(iso7816_clk_x, 6),
+ GROUP(iso7816_data_x, 6),
+ GROUP(pwm_a, 1),
+ GROUP(pwm_b_x7, 4),
+ GROUP(pwm_b_x19, 1),
+ GROUP(pwm_c_x5, 4),
+ GROUP(pwm_c_x8, 5),
+ GROUP(pwm_d_x3, 4),
+ GROUP(pwm_d_x6, 4),
+ GROUP(pwm_e, 1),
+ GROUP(pwm_f_x, 1),
+ GROUP(tsin_a_valid, 3),
+ GROUP(tsin_a_sop, 3),
+ GROUP(tsin_a_din0, 3),
+ GROUP(tsin_a_clk, 3),
+ GROUP(tsin_b_valid_x, 3),
+ GROUP(tsin_b_sop_x, 3),
+ GROUP(tsin_b_din0_x, 3),
+ GROUP(tsin_b_clk_x, 3),
+ GROUP(pdm_din0_x, 2),
+ GROUP(pdm_din1_x, 2),
+ GROUP(pdm_din2_x, 2),
+ GROUP(pdm_din3_x, 2),
+ GROUP(pdm_dclk_x, 2),
+ GROUP(tdm_a_slv_sclk, 2),
+ GROUP(tdm_a_slv_fs, 2),
+ GROUP(tdm_a_din0, 2),
+ GROUP(tdm_a_din1, 2),
+ GROUP(tdm_a_sclk, 1),
+ GROUP(tdm_a_fs, 1),
+ GROUP(tdm_a_dout0, 1),
+ GROUP(tdm_a_dout1, 1),
+ GROUP(mclk1_x, 2),
+
+ /* bank GPIOC */
+ GROUP(sdcard_d0_c, 1),
+ GROUP(sdcard_d1_c, 1),
+ GROUP(sdcard_d2_c, 1),
+ GROUP(sdcard_d3_c, 1),
+ GROUP(sdcard_clk_c, 1),
+ GROUP(sdcard_cmd_c, 1),
+ GROUP(spi0_mosi_c, 5),
+ GROUP(spi0_miso_c, 5),
+ GROUP(spi0_ss0_c, 5),
+ GROUP(spi0_clk_c, 5),
+ GROUP(i2c0_sda_c, 3),
+ GROUP(i2c0_sck_c, 3),
+ GROUP(uart_ao_a_rx_c, 2),
+ GROUP(uart_ao_a_tx_c, 2),
+ GROUP(iso7816_clk_c, 5),
+ GROUP(iso7816_data_c, 5),
+ GROUP(pwm_c_c, 5),
+ GROUP(jtag_b_tdo, 2),
+ GROUP(jtag_b_tdi, 2),
+ GROUP(jtag_b_clk, 2),
+ GROUP(jtag_b_tms, 2),
+ GROUP(pdm_din0_c, 4),
+ GROUP(pdm_din1_c, 4),
+ GROUP(pdm_din2_c, 4),
+ GROUP(pdm_din3_c, 4),
+ GROUP(pdm_dclk_c, 4),
+
+ /* bank GPIOH */
+ GROUP(spi1_mosi, 3),
+ GROUP(spi1_miso, 3),
+ GROUP(spi1_ss0, 3),
+ GROUP(spi1_clk, 3),
+ GROUP(i2c1_sda_h2, 2),
+ GROUP(i2c1_sck_h3, 2),
+ GROUP(i2c1_sda_h6, 4),
+ GROUP(i2c1_sck_h7, 4),
+ GROUP(i2c3_sda_h, 2),
+ GROUP(i2c3_sck_h, 2),
+ GROUP(uart_c_tx, 2),
+ GROUP(uart_c_rx, 2),
+ GROUP(uart_c_cts, 2),
+ GROUP(uart_c_rts, 2),
+ GROUP(iso7816_clk_h, 1),
+ GROUP(iso7816_data_h, 1),
+ GROUP(pwm_f_h, 4),
+ GROUP(cec_ao_a_h, 4),
+ GROUP(cec_ao_b_h, 5),
+ GROUP(hdmitx_sda, 1),
+ GROUP(hdmitx_sck, 1),
+ GROUP(hdmitx_hpd_in, 1),
+ GROUP(spdif_out_h, 1),
+ GROUP(spdif_in_h, 1),
+ GROUP(tdm_b_din3_h, 6),
+ GROUP(tdm_b_dout3_h, 5),
+
+ /* bank GPIOA */
+ GROUP(i2c3_sda_a, 2),
+ GROUP(i2c3_sck_a, 2),
+ GROUP(pdm_din0_a, 1),
+ GROUP(pdm_din1_a, 1),
+ GROUP(pdm_din2_a, 1),
+ GROUP(pdm_din3_a, 1),
+ GROUP(pdm_dclk_a, 1),
+ GROUP(spdif_in_a10, 1),
+ GROUP(spdif_in_a12, 1),
+ GROUP(spdif_out_a11, 1),
+ GROUP(spdif_out_a13, 1),
+ GROUP(tdm_b_slv_sclk, 2),
+ GROUP(tdm_b_slv_fs, 2),
+ GROUP(tdm_b_din0, 2),
+ GROUP(tdm_b_din1, 2),
+ GROUP(tdm_b_din2, 2),
+ GROUP(tdm_b_din3_a, 2),
+ GROUP(tdm_b_sclk, 1),
+ GROUP(tdm_b_fs, 1),
+ GROUP(tdm_b_dout0, 1),
+ GROUP(tdm_b_dout1, 1),
+ GROUP(tdm_b_dout2, 3),
+ GROUP(tdm_b_dout3_a, 3),
+ GROUP(tdm_c_slv_sclk_a, 3),
+ GROUP(tdm_c_slv_fs_a, 3),
+ GROUP(tdm_c_din0_a, 3),
+ GROUP(tdm_c_din1_a, 3),
+ GROUP(tdm_c_din2_a, 3),
+ GROUP(tdm_c_din3_a, 3),
+ GROUP(tdm_c_sclk_a, 2),
+ GROUP(tdm_c_fs_a, 2),
+ GROUP(tdm_c_dout0_a, 2),
+ GROUP(tdm_c_dout1_a, 2),
+ GROUP(tdm_c_dout2_a, 2),
+ GROUP(tdm_c_dout3_a, 2),
+ GROUP(mclk0_a, 1),
+ GROUP(mclk1_a, 2),
+};
+
+/* uart_ao_a */
+static const unsigned int uart_ao_a_tx_pins[] = { GPIOAO_0 };
+static const unsigned int uart_ao_a_rx_pins[] = { GPIOAO_1 };
+static const unsigned int uart_ao_a_cts_pins[] = { GPIOE_0 };
+static const unsigned int uart_ao_a_rts_pins[] = { GPIOE_1 };
+
+/* uart_ao_b */
+static const unsigned int uart_ao_b_tx_2_pins[] = { GPIOAO_2 };
+static const unsigned int uart_ao_b_rx_3_pins[] = { GPIOAO_3 };
+static const unsigned int uart_ao_b_tx_8_pins[] = { GPIOAO_8 };
+static const unsigned int uart_ao_b_rx_9_pins[] = { GPIOAO_9 };
+static const unsigned int uart_ao_b_cts_pins[] = { GPIOE_0 };
+static const unsigned int uart_ao_b_rts_pins[] = { GPIOE_1 };
+
+/* i2c_ao */
+static const unsigned int i2c_ao_sck_pins[] = { GPIOAO_2 };
+static const unsigned int i2c_ao_sda_pins[] = { GPIOAO_3 };
+
+static const unsigned int i2c_ao_sck_e_pins[] = { GPIOE_0 };
+static const unsigned int i2c_ao_sda_e_pins[] = { GPIOE_1 };
+
+/* i2c_ao_slave */
+static const unsigned int i2c_ao_slave_sck_pins[] = { GPIOAO_2 };
+static const unsigned int i2c_ao_slave_sda_pins[] = { GPIOAO_3 };
+
+/* ir_in */
+static const unsigned int remote_ao_input_pins[] = { GPIOAO_5 };
+
+/* ir_out */
+static const unsigned int remote_ao_out_pins[] = { GPIOAO_4 };
+
+/* pwm_ao_a */
+static const unsigned int pwm_ao_a_pins[] = { GPIOAO_11 };
+static const unsigned int pwm_ao_a_hiz_pins[] = { GPIOAO_11 };
+
+/* pwm_ao_b */
+static const unsigned int pwm_ao_b_pins[] = { GPIOE_0 };
+
+/* pwm_ao_c */
+static const unsigned int pwm_ao_c_4_pins[] = { GPIOAO_4 };
+static const unsigned int pwm_ao_c_hiz_pins[] = { GPIOAO_4 };
+static const unsigned int pwm_ao_c_6_pins[] = { GPIOAO_6 };
+
+/* pwm_ao_d */
+static const unsigned int pwm_ao_d_5_pins[] = { GPIOAO_5 };
+static const unsigned int pwm_ao_d_10_pins[] = { GPIOAO_10 };
+static const unsigned int pwm_ao_d_e_pins[] = { GPIOE_1 };
+
+/* jtag_a */
+static const unsigned int jtag_a_tdi_pins[] = { GPIOAO_8 };
+static const unsigned int jtag_a_tdo_pins[] = { GPIOAO_9 };
+static const unsigned int jtag_a_clk_pins[] = { GPIOAO_6 };
+static const unsigned int jtag_a_tms_pins[] = { GPIOAO_7 };
+
+/* cec_ao */
+static const unsigned int cec_ao_a_pins[] = { GPIOAO_10 };
+static const unsigned int cec_ao_b_pins[] = { GPIOAO_10 };
+
+/* tsin_ao_a */
+static const unsigned int tsin_ao_asop_pins[] = { GPIOAO_6 };
+static const unsigned int tsin_ao_adin0_pins[] = { GPIOAO_7 };
+static const unsigned int tsin_ao_aclk_pins[] = { GPIOAO_8 };
+static const unsigned int tsin_ao_a_valid_pins[] = { GPIOAO_9 };
+
+/* spdif_ao_out */
+static const unsigned int spdif_ao_out_pins[] = { GPIOAO_10 };
+
+/* tdm_ao_b */
+static const unsigned int tdm_ao_b_slv_fs_pins[] = { GPIOAO_7 };
+static const unsigned int tdm_ao_b_slv_sclk_pins[] = { GPIOAO_8 };
+static const unsigned int tdm_ao_b_fs_pins[] = { GPIOAO_7 };
+static const unsigned int tdm_ao_b_sclk_pins[] = { GPIOAO_8 };
+static const unsigned int tdm_ao_b_din0_pins[] = { GPIOAO_4 };
+static const unsigned int tdm_ao_b_din1_pins[] = { GPIOAO_10 };
+static const unsigned int tdm_ao_b_din2_pins[] = { GPIOAO_6 };
+static const unsigned int tdm_ao_b_dout0_pins[] = { GPIOAO_4 };
+static const unsigned int tdm_ao_b_dout1_pins[] = { GPIOAO_10 };
+static const unsigned int tdm_ao_b_dout2_pins[] = { GPIOAO_6 };
+
+/* mclk0_ao */
+static const unsigned int mclk0_ao_pins[] = { GPIOAO_9 };
+
+static struct meson_pmx_group meson_g12a_aobus_groups[] = {
+ GPIO_GROUP(GPIOAO_0, 0),
+ GPIO_GROUP(GPIOAO_1, 0),
+ GPIO_GROUP(GPIOAO_2, 0),
+ GPIO_GROUP(GPIOAO_3, 0),
+ GPIO_GROUP(GPIOAO_4, 0),
+ GPIO_GROUP(GPIOAO_5, 0),
+ GPIO_GROUP(GPIOAO_6, 0),
+ GPIO_GROUP(GPIOAO_7, 0),
+ GPIO_GROUP(GPIOAO_8, 0),
+ GPIO_GROUP(GPIOAO_9, 0),
+ GPIO_GROUP(GPIOAO_10, 0),
+ GPIO_GROUP(GPIOAO_11, 0),
+ GPIO_GROUP(GPIOE_0, 0),
+ GPIO_GROUP(GPIOE_1, 0),
+ GPIO_GROUP(GPIOE_2, 0),
+
+ /* bank AO */
+ GROUP(uart_ao_a_tx, 1),
+ GROUP(uart_ao_a_rx, 1),
+ GROUP(uart_ao_a_cts, 1),
+ GROUP(uart_ao_a_rts, 1),
+ GROUP(uart_ao_b_tx_2, 2),
+ GROUP(uart_ao_b_rx_3, 2),
+ GROUP(uart_ao_b_tx_8, 3),
+ GROUP(uart_ao_b_rx_9, 3),
+ GROUP(uart_ao_b_cts, 2),
+ GROUP(uart_ao_b_rts, 2),
+ GROUP(i2c_ao_sck, 1),
+ GROUP(i2c_ao_sda, 1),
+ GROUP(i2c_ao_sck_e, 4),
+ GROUP(i2c_ao_sda_e, 4),
+ GROUP(i2c_ao_slave_sck, 3),
+ GROUP(i2c_ao_slave_sda, 3),
+ GROUP(remote_ao_input, 1),
+ GROUP(remote_ao_out, 1),
+ GROUP(pwm_ao_a, 3),
+ GROUP(pwm_ao_a_hiz, 2),
+ GROUP(pwm_ao_b, 3),
+ GROUP(pwm_ao_c_4, 3),
+ GROUP(pwm_ao_c_hiz, 4),
+ GROUP(pwm_ao_c_6, 3),
+ GROUP(pwm_ao_d_5, 3),
+ GROUP(pwm_ao_d_10, 3),
+ GROUP(pwm_ao_d_e, 3),
+ GROUP(jtag_a_tdi, 1),
+ GROUP(jtag_a_tdo, 1),
+ GROUP(jtag_a_clk, 1),
+ GROUP(jtag_a_tms, 1),
+ GROUP(cec_ao_a, 1),
+ GROUP(cec_ao_b, 2),
+ GROUP(tsin_ao_asop, 4),
+ GROUP(tsin_ao_adin0, 4),
+ GROUP(tsin_ao_aclk, 4),
+ GROUP(tsin_ao_a_valid, 4),
+ GROUP(spdif_ao_out, 4),
+ GROUP(tdm_ao_b_dout0, 5),
+ GROUP(tdm_ao_b_dout1, 5),
+ GROUP(tdm_ao_b_dout2, 5),
+ GROUP(tdm_ao_b_fs, 5),
+ GROUP(tdm_ao_b_sclk, 5),
+ GROUP(tdm_ao_b_din0, 6),
+ GROUP(tdm_ao_b_din1, 6),
+ GROUP(tdm_ao_b_din2, 6),
+ GROUP(tdm_ao_b_slv_fs, 6),
+ GROUP(tdm_ao_b_slv_sclk, 6),
+ GROUP(mclk0_ao, 5),
+};
+
+static const char * const gpio_periphs_groups[] = {
+ "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4",
+ "GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9",
+ "GPIOZ_10", "GPIOZ_11", "GPIOZ_12", "GPIOZ_13", "GPIOZ_14",
+ "GPIOZ_15",
+
+ "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4",
+ "GPIOH_5", "GPIOH_6", "GPIOH_7", "GPIOH_8",
+
+ "BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4",
+ "BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9",
+ "BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14",
+ "BOOT_15",
+
+ "GPIOC_0", "GPIOC_1", "GPIOC_2", "GPIOC_3", "GPIOC_4",
+ "GPIOC_5", "GPIOC_6", "GPIOC_7",
+
+ "GPIOA_0", "GPIOA_1", "GPIOA_2", "GPIOA_3", "GPIOA_4",
+ "GPIOA_5", "GPIOA_6", "GPIOA_7", "GPIOA_8", "GPIOA_9",
+ "GPIOA_10", "GPIOA_11", "GPIOA_12", "GPIOA_13", "GPIOA_14",
+ "GPIOA_15",
+
+ "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
+ "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
+ "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14",
+ "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19",
+};
+
+static const char * const emmc_groups[] = {
+ "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2",
+ "emmc_nand_d3", "emmc_nand_d4", "emmc_nand_d5",
+ "emmc_nand_d6", "emmc_nand_d7",
+ "emmc_clk", "emmc_cmd", "emmc_nand_ds",
+};
+
+static const char * const nand_groups[] = {
+ "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2",
+ "emmc_nand_d3", "emmc_nand_d4", "emmc_nand_d5",
+ "emmc_nand_d6", "emmc_nand_d7",
+ "nand_ce0", "nand_ale", "nand_cle",
+ "nand_wen_clk", "nand_ren_wr", "nand_rb0",
+ "emmc_nand_ds", "nand_ce1",
+};
+
+static const char * const nor_groups[] = {
+ "nor_d", "nor_q", "nor_c", "nor_cs",
+ "nor_hold", "nor_wp",
+};
+
+static const char * const sdio_groups[] = {
+ "sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3",
+ "sdio_cmd", "sdio_clk", "sdio_dummy",
+};
+
+static const char * const sdcard_groups[] = {
+ "sdcard_d0_c", "sdcard_d1_c", "sdcard_d2_c", "sdcard_d3_c",
+ "sdcard_clk_c", "sdcard_cmd_c",
+ "sdcard_d0_z", "sdcard_d1_z", "sdcard_d2_z", "sdcard_d3_z",
+ "sdcard_clk_z", "sdcard_cmd_z",
+};
+
+static const char * const spi0_groups[] = {
+ "spi0_mosi_c", "spi0_miso_c", "spi0_ss0_c", "spi0_clk_c",
+ "spi0_mosi_x", "spi0_miso_x", "spi0_ss0_x", "spi0_clk_x",
+};
+
+static const char * const spi1_groups[] = {
+ "spi1_mosi", "spi1_miso", "spi1_ss0", "spi1_clk",
+};
+
+static const char * const i2c0_groups[] = {
+ "i2c0_sda_c", "i2c0_sck_c",
+ "i2c0_sda_z0", "i2c0_sck_z1",
+ "i2c0_sda_z7", "i2c0_sck_z8",
+};
+
+static const char * const i2c1_groups[] = {
+ "i2c1_sda_x", "i2c1_sck_x",
+ "i2c1_sda_h2", "i2c1_sck_h3",
+ "i2c1_sda_h6", "i2c1_sck_h7",
+};
+
+static const char * const i2c2_groups[] = {
+ "i2c2_sda_x", "i2c2_sck_x",
+ "i2c2_sda_z", "i2c2_sck_z",
+};
+
+static const char * const i2c3_groups[] = {
+ "i2c3_sda_h", "i2c3_sck_h",
+ "i2c3_sda_a", "i2c3_sck_a",
+};
+
+static const char * const uart_a_groups[] = {
+ "uart_a_tx", "uart_a_rx", "uart_a_cts", "uart_a_rts",
+};
+
+static const char * const uart_b_groups[] = {
+ "uart_b_tx", "uart_b_rx",
+};
+
+static const char * const uart_c_groups[] = {
+ "uart_c_tx", "uart_c_rx", "uart_c_cts", "uart_c_rts",
+};
+
+static const char * const uart_ao_a_c_groups[] = {
+ "uart_ao_a_rx_c", "uart_ao_a_tx_c",
+};
+
+static const char * const iso7816_groups[] = {
+ "iso7816_clk_c", "iso7816_data_c",
+ "iso7816_clk_x", "iso7816_data_x",
+ "iso7816_clk_h", "iso7816_data_h",
+ "iso7816_clk_z", "iso7816_data_z",
+};
+
+static const char * const eth_groups[] = {
+ "eth_rxd2_rgmii", "eth_rxd3_rgmii", "eth_rgmii_tx_clk",
+ "eth_txd2_rgmii", "eth_txd3_rgmii", "eth_rgmii_rx_clk",
+ "eth_txd0", "eth_txd1", "eth_txen", "eth_mdc",
+ "eth_rxd0", "eth_rxd1", "eth_rx_dv", "eth_mdio",
+ "eth_link_led", "eth_act_led",
+};
+
+static const char * const pwm_a_groups[] = {
+ "pwm_a",
+};
+
+static const char * const pwm_b_groups[] = {
+ "pwm_b_x7", "pwm_b_x19",
+};
+
+static const char * const pwm_c_groups[] = {
+ "pwm_c_c", "pwm_c_x5", "pwm_c_x8",
+};
+
+static const char * const pwm_d_groups[] = {
+ "pwm_d_x3", "pwm_d_x6",
+};
+
+static const char * const pwm_e_groups[] = {
+ "pwm_e",
+};
+
+static const char * const pwm_f_groups[] = {
+ "pwm_f_x", "pwm_f_h",
+};
+
+static const char * const cec_ao_a_h_groups[] = {
+ "cec_ao_a_h",
+};
+
+static const char * const cec_ao_b_h_groups[] = {
+ "cec_ao_b_h",
+};
+
+static const char * const jtag_b_groups[] = {
+ "jtag_b_tdi", "jtag_b_tdo", "jtag_b_clk", "jtag_b_tms",
+};
+
+static const char * const bt565_a_groups[] = {
+ "bt565_a_vs", "bt565_a_hs", "bt565_a_clk",
+ "bt565_a_din0", "bt565_a_din1", "bt565_a_din2",
+ "bt565_a_din3", "bt565_a_din4", "bt565_a_din5",
+ "bt565_a_din6", "bt565_a_din7",
+};
+
+static const char * const tsin_a_groups[] = {
+ "tsin_a_valid", "tsin_a_sop", "tsin_a_din0",
+ "tsin_a_clk",
+};
+
+static const char * const tsin_b_groups[] = {
+ "tsin_b_valid_x", "tsin_b_sop_x", "tsin_b_din0_x", "tsin_b_clk_x",
+ "tsin_b_valid_z", "tsin_b_sop_z", "tsin_b_din0_z", "tsin_b_clk_z",
+ "tsin_b_fail", "tsin_b_din1", "tsin_b_din2", "tsin_b_din3",
+ "tsin_b_din4", "tsin_b_din5", "tsin_b_din6", "tsin_b_din7",
+};
+
+static const char * const hdmitx_groups[] = {
+ "hdmitx_sda", "hdmitx_sck", "hdmitx_hpd_in",
+};
+
+static const char * const pdm_groups[] = {
+ "pdm_din0_c", "pdm_din1_c", "pdm_din2_c", "pdm_din3_c",
+ "pdm_dclk_c",
+ "pdm_din0_x", "pdm_din1_x", "pdm_din2_x", "pdm_din3_x",
+ "pdm_dclk_x",
+ "pdm_din0_z", "pdm_din1_z", "pdm_din2_z", "pdm_din3_z",
+ "pdm_dclk_z",
+ "pdm_din0_a", "pdm_din1_a", "pdm_din2_a", "pdm_din3_a",
+ "pdm_dclk_a",
+};
+
+static const char * const spdif_in_groups[] = {
+ "spdif_in_h", "spdif_in_a10", "spdif_in_a12",
+};
+
+static const char * const spdif_out_groups[] = {
+ "spdif_out_h", "spdif_out_a11", "spdif_out_a13",
+};
+
+static const char * const mclk0_groups[] = {
+ "mclk0_a",
+};
+
+static const char * const mclk1_groups[] = {
+ "mclk1_x", "mclk1_z", "mclk1_a",
+};
+
+static const char * const tdm_a_groups[] = {
+ "tdm_a_slv_sclk", "tdm_a_slv_fs", "tdm_a_sclk", "tdm_a_fs",
+ "tdm_a_din0", "tdm_a_din1", "tdm_a_dout0", "tdm_a_dout1",
+};
+
+static const char * const tdm_b_groups[] = {
+ "tdm_b_slv_sclk", "tdm_b_slv_fs", "tdm_b_sclk", "tdm_b_fs",
+ "tdm_b_din0", "tdm_b_din1", "tdm_b_din2",
+ "tdm_b_din3_a", "tdm_b_din3_h",
+ "tdm_b_dout0", "tdm_b_dout1", "tdm_b_dout2",
+ "tdm_b_dout3_a", "tdm_b_dout3_h",
+};
+
+static const char * const tdm_c_groups[] = {
+ "tdm_c_slv_sclk_a", "tdm_c_slv_fs_a",
+ "tdm_c_slv_sclk_z", "tdm_c_slv_fs_z",
+ "tdm_c_sclk_a", "tdm_c_fs_a",
+ "tdm_c_sclk_z", "tdm_c_fs_z",
+ "tdm_c_din0_a", "tdm_c_din1_a",
+ "tdm_c_din2_a", "tdm_c_din3_a",
+ "tdm_c_din0_z", "tdm_c_din1_z",
+ "tdm_c_din2_z", "tdm_c_din3_z",
+ "tdm_c_dout0_a", "tdm_c_dout1_a",
+ "tdm_c_dout2_a", "tdm_c_dout3_a",
+ "tdm_c_dout0_z", "tdm_c_dout1_z",
+ "tdm_c_dout2_z", "tdm_c_dout3_z",
+};
+
+static const char * const gpio_aobus_groups[] = {
+ "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4",
+ "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9",
+ "GPIOAO_10", "GPIOAO_11", "GPIOE_0", "GPIOE_1", "GPIOE_2",
+};
+
+static const char * const uart_ao_a_groups[] = {
+ "uart_ao_a_tx", "uart_ao_a_rx",
+ "uart_ao_a_cts", "uart_ao_a_rts",
+};
+
+static const char * const uart_ao_b_groups[] = {
+ "uart_ao_b_tx_2", "uart_ao_b_rx_3",
+ "uart_ao_b_tx_8", "uart_ao_b_rx_9",
+ "uart_ao_b_cts", "uart_ao_b_rts",
+};
+
+static const char * const i2c_ao_groups[] = {
+ "i2c_ao_sck", "i2c_ao_sda",
+ "i2c_ao_sck_e", "i2c_ao_sda_e",
+};
+
+static const char * const i2c_ao_slave_groups[] = {
+ "i2c_ao_slave_sck", "i2c_ao_slave_sda",
+};
+
+static const char * const remote_ao_input_groups[] = {
+ "remote_ao_input",
+};
+
+static const char * const remote_ao_out_groups[] = {
+ "remote_ao_out",
+};
+
+static const char * const pwm_ao_a_groups[] = {
+ "pwm_ao_a", "pwm_ao_a_hiz",
+};
+
+static const char * const pwm_ao_b_groups[] = {
+ "pwm_ao_b",
+};
+
+static const char * const pwm_ao_c_groups[] = {
+ "pwm_ao_c_4", "pwm_ao_c_hiz",
+ "pwm_ao_c_6",
+};
+
+static const char * const pwm_ao_d_groups[] = {
+ "pwm_ao_d_5", "pwm_ao_d_10", "pwm_ao_d_e",
+};
+
+static const char * const jtag_a_groups[] = {
+ "jtag_a_tdi", "jtag_a_tdo", "jtag_a_clk", "jtag_a_tms",
+};
+
+static const char * const cec_ao_a_groups[] = {
+ "cec_ao_a",
+};
+
+static const char * const cec_ao_b_groups[] = {
+ "cec_ao_b",
+};
+
+static const char * const tsin_ao_a_groups[] = {
+ "tsin_ao_asop", "tsin_ao_adin0", "tsin_ao_aclk", "tsin_ao_a_valid",
+};
+
+static const char * const spdif_ao_out_groups[] = {
+ "spdif_ao_out",
+};
+
+static const char * const tdm_ao_b_groups[] = {
+ "tdm_ao_b_dout0", "tdm_ao_b_dout1", "tdm_ao_b_dout2",
+ "tdm_ao_b_fs", "tdm_ao_b_sclk",
+ "tdm_ao_b_din0", "tdm_ao_b_din1", "tdm_ao_b_din2",
+ "tdm_ao_b_slv_fs", "tdm_ao_b_slv_sclk",
+};
+
+static const char * const mclk0_ao_groups[] = {
+ "mclk0_ao",
+};
+
+static struct meson_pmx_func meson_g12a_periphs_functions[] = {
+ FUNCTION(gpio_periphs),
+ FUNCTION(emmc),
+ FUNCTION(nor),
+ FUNCTION(spi0),
+ FUNCTION(spi1),
+ FUNCTION(sdio),
+ FUNCTION(nand),
+ FUNCTION(sdcard),
+ FUNCTION(i2c0),
+ FUNCTION(i2c1),
+ FUNCTION(i2c2),
+ FUNCTION(i2c3),
+ FUNCTION(uart_a),
+ FUNCTION(uart_b),
+ FUNCTION(uart_c),
+ FUNCTION(uart_ao_a_c),
+ FUNCTION(iso7816),
+ FUNCTION(eth),
+ FUNCTION(pwm_a),
+ FUNCTION(pwm_b),
+ FUNCTION(pwm_c),
+ FUNCTION(pwm_d),
+ FUNCTION(pwm_e),
+ FUNCTION(pwm_f),
+ FUNCTION(cec_ao_a_h),
+ FUNCTION(cec_ao_b_h),
+ FUNCTION(jtag_b),
+ FUNCTION(bt565_a),
+ FUNCTION(tsin_a),
+ FUNCTION(tsin_b),
+ FUNCTION(hdmitx),
+ FUNCTION(pdm),
+ FUNCTION(spdif_out),
+ FUNCTION(spdif_in),
+ FUNCTION(mclk0),
+ FUNCTION(mclk1),
+ FUNCTION(tdm_a),
+ FUNCTION(tdm_b),
+ FUNCTION(tdm_c),
+};
+
+static struct meson_pmx_func meson_g12a_aobus_functions[] = {
+ FUNCTION(gpio_aobus),
+ FUNCTION(uart_ao_a),
+ FUNCTION(uart_ao_b),
+ FUNCTION(i2c_ao),
+ FUNCTION(i2c_ao_slave),
+ FUNCTION(remote_ao_input),
+ FUNCTION(remote_ao_out),
+ FUNCTION(pwm_ao_a),
+ FUNCTION(pwm_ao_b),
+ FUNCTION(pwm_ao_c),
+ FUNCTION(pwm_ao_d),
+ FUNCTION(jtag_a),
+ FUNCTION(cec_ao_a),
+ FUNCTION(cec_ao_b),
+ FUNCTION(tsin_ao_a),
+ FUNCTION(spdif_ao_out),
+ FUNCTION(tdm_ao_b),
+ FUNCTION(mclk0_ao),
+};
+
+static struct meson_bank meson_g12a_periphs_banks[] = {
+ /* name first last pullen pull dir out in */
+ BANK("Z", PIN(GPIOZ_0, EE_OFF), PIN(GPIOZ_15, EE_OFF), 4, 0, 4, 0, 12, 0, 13, 0, 14, 0),
+ BANK("H", PIN(GPIOH_0, EE_OFF), PIN(GPIOH_8, EE_OFF), 3, 0, 3, 0, 9, 0, 10, 0, 11, 0),
+ BANK("BOOT", PIN(BOOT_0, EE_OFF), PIN(BOOT_15, EE_OFF), 0, 0, 0, 0, 0, 0, 1, 0, 2, 0),
+ BANK("C", PIN(GPIOC_0, EE_OFF), PIN(GPIOC_7, EE_OFF), 1, 0, 1, 0, 3, 0, 4, 0, 5, 0),
+ BANK("A", PIN(GPIOA_0, EE_OFF), PIN(GPIOA_15, EE_OFF), 5, 0, 5, 0, 16, 0, 17, 0, 18, 0),
+ BANK("X", PIN(GPIOX_0, EE_OFF), PIN(GPIOX_19, EE_OFF), 2, 0, 2, 0, 6, 0, 7, 0, 8, 0),
+};
+
+static struct meson_bank meson_g12a_aobus_banks[] = {
+ /* name first last pullen pull dir out in */
+ BANK("AO", PIN(GPIOAO_0, 0), PIN(GPIOAO_11, 0), 3, 0, 2, 0, 0, 0, 4, 0, 1, 0),
+ BANK("E", PIN(GPIOE_0, 0), PIN(GPIOE_2, 0), 3, 16, 2, 16, 0, 16, 4, 16, 1, 16),
+};
+
+static struct meson_pmx_bank meson_g12a_periphs_pmx_banks[] = {
+ /* name first last reg offset */
+ BANK_PMX("Z", PIN(GPIOZ_0, EE_OFF), PIN(GPIOZ_15, EE_OFF), 0x6, 0),
+ BANK_PMX("H", PIN(GPIOH_0, EE_OFF), PIN(GPIOH_8, EE_OFF), 0xb, 0),
+ BANK_PMX("BOOT", PIN(BOOT_0, EE_OFF), PIN(BOOT_15, EE_OFF), 0x0, 0),
+ BANK_PMX("C", PIN(GPIOC_0, EE_OFF), PIN(GPIOC_7, EE_OFF), 0x9, 0),
+ BANK_PMX("A", PIN(GPIOA_0, EE_OFF), PIN(GPIOA_15, EE_OFF), 0xd, 0),
+ BANK_PMX("X", PIN(GPIOX_0, EE_OFF), PIN(GPIOX_19, EE_OFF), 0x3, 0),
+};
+
+static struct meson_axg_pmx_data meson_g12a_periphs_pmx_banks_data = {
+ .pmx_banks = meson_g12a_periphs_pmx_banks,
+ .num_pmx_banks = ARRAY_SIZE(meson_g12a_periphs_pmx_banks),
+};
+
+static struct meson_pmx_bank meson_g12a_aobus_pmx_banks[] = {
+ BANK_PMX("AO", GPIOAO_0, GPIOAO_11, 0x0, 0),
+ BANK_PMX("E", GPIOE_0, GPIOE_2, 0x1, 16),
+};
+
+static struct meson_axg_pmx_data meson_g12a_aobus_pmx_banks_data = {
+ .pmx_banks = meson_g12a_aobus_pmx_banks,
+ .num_pmx_banks = ARRAY_SIZE(meson_g12a_aobus_pmx_banks),
+};
+
+static struct meson_pinctrl_data meson_g12a_periphs_pinctrl_data = {
+ .name = "periphs-banks",
+ .pin_base = EE_OFF,
+ .groups = meson_g12a_periphs_groups,
+ .funcs = meson_g12a_periphs_functions,
+ .banks = meson_g12a_periphs_banks,
+ .num_pins = 85,
+ .num_groups = ARRAY_SIZE(meson_g12a_periphs_groups),
+ .num_funcs = ARRAY_SIZE(meson_g12a_periphs_functions),
+ .num_banks = ARRAY_SIZE(meson_g12a_periphs_banks),
+ .gpio_driver = &meson_axg_gpio_driver,
+ .pmx_data = &meson_g12a_periphs_pmx_banks_data,
+};
+
+static struct meson_pinctrl_data meson_g12a_aobus_pinctrl_data = {
+ .name = "aobus-banks",
+ .pin_base = 0,
+ .groups = meson_g12a_aobus_groups,
+ .funcs = meson_g12a_aobus_functions,
+ .banks = meson_g12a_aobus_banks,
+ .num_pins = 15,
+ .num_groups = ARRAY_SIZE(meson_g12a_aobus_groups),
+ .num_funcs = ARRAY_SIZE(meson_g12a_aobus_functions),
+ .num_banks = ARRAY_SIZE(meson_g12a_aobus_banks),
+ .gpio_driver = &meson_axg_gpio_driver,
+ .pmx_data = &meson_g12a_aobus_pmx_banks_data,
+};
+
+static const struct udevice_id meson_g12a_pinctrl_match[] = {
+ {
+ .compatible = "amlogic,meson-g12a-periphs-pinctrl",
+ .data = (ulong)&meson_g12a_periphs_pinctrl_data,
+ },
+ {
+ .compatible = "amlogic,meson-g12a-aobus-pinctrl",
+ .data = (ulong)&meson_g12a_aobus_pinctrl_data,
+ },
+ { },
+};
+
+U_BOOT_DRIVER(meson_axg_pinctrl) = {
+ .name = "meson-g12a-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(meson_g12a_pinctrl_match),
+ .probe = meson_pinctrl_probe,
+ .priv_auto_alloc_size = sizeof(struct meson_pinctrl),
+ .ops = &meson_axg_pinctrl_ops,
+};
diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c
index fa3d788..8735418 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.c
+++ b/drivers/pinctrl/meson/pinctrl-meson.c
@@ -314,11 +314,11 @@
priv->reg_gpio = (void __iomem *)addr;
addr = parse_address(gpio, "pull", na, ns);
- if (addr == FDT_ADDR_T_NONE) {
- debug("pull address not found\n");
- return -EINVAL;
- }
- priv->reg_pull = (void __iomem *)addr;
+ /* Use gpio region if pull one is not present */
+ if (addr == FDT_ADDR_T_NONE)
+ priv->reg_pull = priv->reg_gpio;
+ else
+ priv->reg_pull = (void __iomem *)addr;
addr = parse_address(gpio, "pull-enable", na, ns);
/* Use pull region if pull-enable one is not present */
@@ -327,6 +327,13 @@
else
priv->reg_pullen = (void __iomem *)addr;
+ addr = parse_address(gpio, "ds", na, ns);
+ /* Drive strength region is optional */
+ if (addr == FDT_ADDR_T_NONE)
+ priv->reg_ds = NULL;
+ else
+ priv->reg_ds = (void __iomem *)addr;
+
priv->data = (struct meson_pinctrl_data *)dev_get_driver_data(dev);
/* Lookup GPIO driver */
diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h
index 28085a7..b3683e2 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.h
+++ b/drivers/pinctrl/meson/pinctrl-meson.h
@@ -41,6 +41,7 @@
void __iomem *reg_gpio;
void __iomem *reg_pull;
void __iomem *reg_pullen;
+ void __iomem *reg_ds;
};
/**
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index a81e767..6ec6f39 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -121,4 +121,10 @@
This enables support for common reset driver for
Allwinner SoCs.
+config RESET_HISILICON
+ bool "Reset controller driver for HiSilicon SoCs"
+ depends on DM_RESET
+ help
+ Support for reset controller on HiSilicon SoCs.
+
endmenu
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 4fad7d4..7fec75b 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -19,3 +19,4 @@
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
+obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o
diff --git a/drivers/reset/reset-hisilicon.c b/drivers/reset/reset-hisilicon.c
new file mode 100644
index 0000000..a9f052a
--- /dev/null
+++ b/drivers/reset/reset-hisilicon.c
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019, Linaro Limited
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <dm.h>
+#include <dt-bindings/reset/ti-syscon.h>
+#include <reset-uclass.h>
+
+struct hisi_reset_priv {
+ void __iomem *base;
+};
+
+static int hisi_reset_deassert(struct reset_ctl *rst)
+{
+ struct hisi_reset_priv *priv = dev_get_priv(rst->dev);
+ u32 val;
+
+ val = readl(priv->base + rst->data);
+ if (rst->polarity & DEASSERT_SET)
+ val |= BIT(rst->id);
+ else
+ val &= ~BIT(rst->id);
+ writel(val, priv->base + rst->data);
+
+ return 0;
+}
+
+static int hisi_reset_assert(struct reset_ctl *rst)
+{
+ struct hisi_reset_priv *priv = dev_get_priv(rst->dev);
+ u32 val;
+
+ val = readl(priv->base + rst->data);
+ if (rst->polarity & ASSERT_SET)
+ val |= BIT(rst->id);
+ else
+ val &= ~BIT(rst->id);
+ writel(val, priv->base + rst->data);
+
+ return 0;
+}
+
+static int hisi_reset_free(struct reset_ctl *rst)
+{
+ return 0;
+}
+
+static int hisi_reset_request(struct reset_ctl *rst)
+{
+ return 0;
+}
+
+static int hisi_reset_of_xlate(struct reset_ctl *rst,
+ struct ofnode_phandle_args *args)
+{
+ if (args->args_count != 3) {
+ debug("Invalid args_count: %d\n", args->args_count);
+ return -EINVAL;
+ }
+
+ /* Use .data field as register offset and .id field as bit shift */
+ rst->data = args->args[0];
+ rst->id = args->args[1];
+ rst->polarity = args->args[2];
+
+ return 0;
+}
+
+static const struct reset_ops hisi_reset_reset_ops = {
+ .of_xlate = hisi_reset_of_xlate,
+ .request = hisi_reset_request,
+ .free = hisi_reset_free,
+ .rst_assert = hisi_reset_assert,
+ .rst_deassert = hisi_reset_deassert,
+};
+
+static const struct udevice_id hisi_reset_ids[] = {
+ { .compatible = "hisilicon,hi3798cv200-reset" },
+ { }
+};
+
+static int hisi_reset_probe(struct udevice *dev)
+{
+ struct hisi_reset_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_remap_addr(dev);
+ if (!priv->base)
+ return -ENOMEM;
+
+ return 0;
+}
+
+U_BOOT_DRIVER(hisi_reset) = {
+ .name = "hisilicon_reset",
+ .id = UCLASS_RESET,
+ .of_match = hisi_reset_ids,
+ .ops = &hisi_reset_reset_ops,
+ .probe = hisi_reset_probe,
+ .priv_auto_alloc_size = sizeof(struct hisi_reset_priv),
+};
diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c
index 92f0469..31aa4d4 100644
--- a/drivers/reset/reset-meson.c
+++ b/drivers/reset/reset-meson.c
@@ -69,6 +69,7 @@
static const struct udevice_id meson_reset_ids[] = {
{ .compatible = "amlogic,meson-gxbb-reset" },
+ { .compatible = "amlogic,meson-axg-reset" },
{ }
};
diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
index b2acfcd..cb83126 100644
--- a/drivers/reset/reset-socfpga.c
+++ b/drivers/reset/reset-socfpga.c
@@ -24,9 +24,39 @@
#define NR_BANKS 8
struct socfpga_reset_data {
- void __iomem *membase;
+ void __iomem *modrst_base;
};
+/*
+ * For compatibility with Kernels that don't support peripheral reset, this
+ * driver can keep the old behaviour of not asserting peripheral reset before
+ * starting the OS and deasserting all peripheral resets (enabling all
+ * peripherals).
+ *
+ * For that, the reset driver checks the environment variable
+ * "socfpga_legacy_reset_compat". If this variable is '1', perihperals are not
+ * reset again once taken out of reset and all peripherals in 'permodrst' are
+ * taken out of reset before booting into the OS.
+ * Note that this should be required for gen5 systems only that are running
+ * Linux kernels without proper peripheral reset support for all drivers used.
+ */
+static bool socfpga_reset_keep_enabled(void)
+{
+#if !defined(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(ENV_SUPPORT)
+ const char *env_str;
+ long val;
+
+ env_str = env_get("socfpga_legacy_reset_compat");
+ if (env_str) {
+ val = simple_strtol(env_str, NULL, 0);
+ if (val == 1)
+ return true;
+ }
+#endif
+
+ return false;
+}
+
static int socfpga_reset_assert(struct reset_ctl *reset_ctl)
{
struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev);
@@ -35,7 +65,7 @@
int bank = id / (reg_width * BITS_PER_BYTE);
int offset = id % (reg_width * BITS_PER_BYTE);
- setbits_le32(data->membase + (bank * BANK_INCREMENT), BIT(offset));
+ setbits_le32(data->modrst_base + (bank * BANK_INCREMENT), BIT(offset));
return 0;
}
@@ -47,7 +77,7 @@
int bank = id / (reg_width * BITS_PER_BYTE);
int offset = id % (reg_width * BITS_PER_BYTE);
- clrbits_le32(data->membase + (bank * BANK_INCREMENT), BIT(offset));
+ clrbits_le32(data->modrst_base + (bank * BANK_INCREMENT), BIT(offset));
return 0;
}
@@ -80,15 +110,28 @@
const void *blob = gd->fdt_blob;
int node = dev_of_offset(dev);
u32 modrst_offset;
+ void __iomem *membase;
- data->membase = devfdt_get_addr_ptr(dev);
+ membase = devfdt_get_addr_ptr(dev);
modrst_offset = fdtdec_get_int(blob, node, "altr,modrst-offset", 0x10);
- data->membase += modrst_offset;
+ data->modrst_base = membase + modrst_offset;
return 0;
}
+static int socfpga_reset_remove(struct udevice *dev)
+{
+ struct socfpga_reset_data *data = dev_get_priv(dev);
+
+ if (socfpga_reset_keep_enabled()) {
+ puts("Deasserting all peripheral resets\n");
+ writel(0, data->modrst_base + 4);
+ }
+
+ return 0;
+}
+
static const struct udevice_id socfpga_reset_match[] = {
{ .compatible = "altr,rst-mgr" },
{ /* sentinel */ },
@@ -101,4 +144,6 @@
.probe = socfpga_reset_probe,
.priv_auto_alloc_size = sizeof(struct socfpga_reset_data),
.ops = &socfpga_reset_ops,
+ .remove = socfpga_reset_remove,
+ .flags = DM_FLAG_OS_PREPARE,
};
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index efdb178..41c8700 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -8,6 +8,7 @@
#include <dm.h>
#include <fdtdec.h>
#include <malloc.h>
+#include <reset.h>
#include <spi.h>
#include <linux/errno.h>
#include "cadence_qspi.h"
@@ -154,10 +155,17 @@
{
struct cadence_spi_platdata *plat = bus->platdata;
struct cadence_spi_priv *priv = dev_get_priv(bus);
+ int ret;
priv->regbase = plat->regbase;
priv->ahbbase = plat->ahbbase;
+ ret = reset_get_bulk(bus, &priv->resets);
+ if (ret)
+ dev_warn(bus, "Can't get reset: %d\n", ret);
+ else
+ reset_deassert_bulk(&priv->resets);
+
if (!priv->qspi_is_init) {
cadence_qspi_apb_controller_init(plat);
priv->qspi_is_init = 1;
@@ -166,6 +174,13 @@
return 0;
}
+static int cadence_spi_remove(struct udevice *dev)
+{
+ struct cadence_spi_priv *priv = dev_get_priv(dev);
+
+ return reset_release_bulk(&priv->resets);
+}
+
static int cadence_spi_set_mode(struct udevice *bus, uint mode)
{
struct cadence_spi_priv *priv = dev_get_priv(bus);
@@ -342,4 +357,6 @@
.platdata_auto_alloc_size = sizeof(struct cadence_spi_platdata),
.priv_auto_alloc_size = sizeof(struct cadence_spi_priv),
.probe = cadence_spi_probe,
+ .remove = cadence_spi_remove,
+ .flags = DM_FLAG_OS_PREPARE,
};
diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
index b491407..20cceca 100644
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@@ -7,6 +7,8 @@
#ifndef __CADENCE_QSPI_H__
#define __CADENCE_QSPI_H__
+#include <reset.h>
+
#define CQSPI_IS_ADDR(cmd_len) (cmd_len > 1 ? 1 : 0)
#define CQSPI_NO_DECODER_MAX_CS 4
@@ -42,6 +44,8 @@
unsigned int qspi_calibrated_hz;
unsigned int qspi_calibrated_cs;
unsigned int previous_hz;
+
+ struct reset_ctl_bulk resets;
};
/* Functions call declaration */
diff --git a/drivers/timer/dw-apb-timer.c b/drivers/timer/dw-apb-timer.c
index 085bfb0..cb48801 100644
--- a/drivers/timer/dw-apb-timer.c
+++ b/drivers/timer/dw-apb-timer.c
@@ -32,7 +32,7 @@
* requires the count to be incrementing. Invert the
* result.
*/
- *count = ~readl(priv->regs + DW_APB_CURR_VAL);
+ *count = timer_conv_64(~readl(priv->regs + DW_APB_CURR_VAL));
return 0;
}
diff --git a/drivers/timer/sandbox_timer.c b/drivers/timer/sandbox_timer.c
index 6d2b045..5228486 100644
--- a/drivers/timer/sandbox_timer.c
+++ b/drivers/timer/sandbox_timer.c
@@ -14,7 +14,7 @@
/* system timer offset in ms */
static unsigned long sandbox_timer_offset;
-void sandbox_timer_add_offset(unsigned long offset)
+void timer_test_add_offset(unsigned long offset)
{
sandbox_timer_offset += offset;
}
diff --git a/drivers/usb/gadget/dwc2_udc_otg.c b/drivers/usb/gadget/dwc2_udc_otg.c
index 3c7ad03..494ab53 100644
--- a/drivers/usb/gadget/dwc2_udc_otg.c
+++ b/drivers/usb/gadget/dwc2_udc_otg.c
@@ -18,11 +18,17 @@
*/
#undef DEBUG
#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <generic-phy.h>
+#include <malloc.h>
+#include <reset.h>
+
#include <linux/errno.h>
#include <linux/list.h>
-#include <malloc.h>
#include <linux/usb/ch9.h>
+#include <linux/usb/otg.h>
#include <linux/usb/gadget.h>
#include <asm/byteorder.h>
@@ -31,6 +37,8 @@
#include <asm/mach-types.h>
+#include <power/regulator.h>
+
#include "dwc2_udc_otg_regs.h"
#include "dwc2_udc_otg_priv.h"
@@ -140,7 +148,6 @@
/***********************************************************/
-void __iomem *regs_otg;
struct dwc2_usbotg_reg *reg;
bool dfu_usb_get_reset(void)
@@ -223,6 +230,7 @@
return 0;
}
+#if !CONFIG_IS_ENABLED(DM_USB_GADGET)
/*
Register entry point for the peripheral controller driver.
*/
@@ -295,9 +303,57 @@
disable_irq(IRQ_OTG);
udc_disable(dev);
+ return 0;
+}
+#else /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */
+
+static int dwc2_gadget_start(struct usb_gadget *g,
+ struct usb_gadget_driver *driver)
+{
+ struct dwc2_udc *dev = the_controller;
+
+ debug_cond(DEBUG_SETUP != 0, "%s: %s\n", __func__, "no name");
+
+ if (!driver ||
+ (driver->speed != USB_SPEED_FULL &&
+ driver->speed != USB_SPEED_HIGH) ||
+ !driver->bind || !driver->disconnect || !driver->setup)
+ return -EINVAL;
+
+ if (!dev)
+ return -ENODEV;
+
+ if (dev->driver)
+ return -EBUSY;
+
+ /* first hook up the driver ... */
+ dev->driver = driver;
+
+ debug_cond(DEBUG_SETUP != 0,
+ "Registered gadget driver %s\n", dev->gadget.name);
+ return udc_enable(dev);
+}
+
+static int dwc2_gadget_stop(struct usb_gadget *g)
+{
+ struct dwc2_udc *dev = the_controller;
+
+ if (!dev)
+ return -ENODEV;
+
+ if (!dev->driver)
+ return -EINVAL;
+
+ dev->driver = 0;
+ stop_activity(dev, dev->driver);
+
+ udc_disable(dev);
+
return 0;
}
+#endif /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */
+
/*
* done - retire a request; caller blocked irqs
*/
@@ -400,6 +456,8 @@
unsigned int uTemp = writel(CORE_SOFT_RESET, ®->grstctl);
uint32_t dflt_gusbcfg;
uint32_t rx_fifo_sz, tx_fifo_sz, np_tx_fifo_sz;
+ u32 max_hw_ep;
+ int pdata_hw_ep;
debug("Reseting OTG controller\n");
@@ -482,10 +540,23 @@
writel((np_tx_fifo_sz << 16) | rx_fifo_sz,
®->gnptxfsiz);
- for (i = 1; i < DWC2_MAX_HW_ENDPOINTS; i++)
- writel((rx_fifo_sz + np_tx_fifo_sz + tx_fifo_sz*(i-1)) |
- tx_fifo_sz << 16, ®->dieptxf[i-1]);
+ /* retrieve the number of IN Endpoints (excluding ep0) */
+ max_hw_ep = (readl(®->ghwcfg4) & GHWCFG4_NUM_IN_EPS_MASK) >>
+ GHWCFG4_NUM_IN_EPS_SHIFT;
+ pdata_hw_ep = dev->pdata->tx_fifo_sz_nb;
+ /* tx_fifo_sz_nb should equal to number of IN Endpoint */
+ if (pdata_hw_ep && max_hw_ep != pdata_hw_ep)
+ pr_warn("Got %d hw endpoint but %d tx-fifo-size in array !!\n",
+ max_hw_ep, pdata_hw_ep);
+
+ for (i = 0; i < max_hw_ep; i++) {
+ if (pdata_hw_ep)
+ tx_fifo_sz = dev->pdata->tx_fifo_sz_array[i];
+
+ writel((rx_fifo_sz + np_tx_fifo_sz + (tx_fifo_sz * i)) |
+ tx_fifo_sz << 16, ®->dieptxf[i]);
+ }
/* Flush the RX FIFO */
writel(RX_FIFO_FLUSH, ®->grstctl);
while (readl(®->grstctl) & RX_FIFO_FLUSH)
@@ -731,6 +802,10 @@
static const struct usb_gadget_ops dwc2_udc_ops = {
/* current versions must always be self-powered */
+#if CONFIG_IS_ENABLED(DM_USB_GADGET)
+ .udc_start = dwc2_gadget_start,
+ .udc_stop = dwc2_gadget_stop,
+#endif
};
static struct dwc2_udc memory = {
@@ -818,8 +893,6 @@
reg = (struct dwc2_usbotg_reg *)pdata->regs_otg;
- /* regs_otg = (void *)pdata->regs_otg; */
-
dev->gadget.is_dualspeed = 1; /* Hack only*/
dev->gadget.is_otg = 0;
dev->gadget.is_a_peripheral = 0;
@@ -844,12 +917,311 @@
return retval;
}
-int usb_gadget_handle_interrupts(int index)
+int dwc2_udc_handle_interrupt(void)
{
u32 intr_status = readl(®->gintsts);
u32 gintmsk = readl(®->gintmsk);
if (intr_status & gintmsk)
return dwc2_udc_irq(1, (void *)the_controller);
+
+ return 0;
+}
+
+#if !CONFIG_IS_ENABLED(DM_USB_GADGET)
+
+int usb_gadget_handle_interrupts(int index)
+{
+ return dwc2_udc_handle_interrupt();
+}
+
+#else /* CONFIG_IS_ENABLED(DM_USB_GADGET) */
+
+struct dwc2_priv_data {
+ struct clk_bulk clks;
+ struct reset_ctl_bulk resets;
+ struct phy *phys;
+ int num_phys;
+ struct udevice *usb33d_supply;
+};
+
+int dm_usb_gadget_handle_interrupts(struct udevice *dev)
+{
+ return dwc2_udc_handle_interrupt();
+}
+
+int dwc2_phy_setup(struct udevice *dev, struct phy **array, int *num_phys)
+{
+ int i, ret, count;
+ struct phy *usb_phys;
+
+ /* Return if no phy declared */
+ if (!dev_read_prop(dev, "phys", NULL))
+ return 0;
+
+ count = dev_count_phandle_with_args(dev, "phys", "#phy-cells");
+ if (count <= 0)
+ return count;
+
+ usb_phys = devm_kcalloc(dev, count, sizeof(struct phy),
+ GFP_KERNEL);
+ if (!usb_phys)
+ return -ENOMEM;
+
+ for (i = 0; i < count; i++) {
+ ret = generic_phy_get_by_index(dev, i, &usb_phys[i]);
+ if (ret && ret != -ENOENT) {
+ dev_err(dev, "Failed to get USB PHY%d for %s\n",
+ i, dev->name);
+ return ret;
+ }
+ }
+
+ for (i = 0; i < count; i++) {
+ ret = generic_phy_init(&usb_phys[i]);
+ if (ret) {
+ dev_err(dev, "Can't init USB PHY%d for %s\n",
+ i, dev->name);
+ goto phys_init_err;
+ }
+ }
+
+ for (i = 0; i < count; i++) {
+ ret = generic_phy_power_on(&usb_phys[i]);
+ if (ret) {
+ dev_err(dev, "Can't power USB PHY%d for %s\n",
+ i, dev->name);
+ goto phys_poweron_err;
+ }
+ }
+
+ *array = usb_phys;
+ *num_phys = count;
+
+ return 0;
+
+phys_poweron_err:
+ for (i = count - 1; i >= 0; i--)
+ generic_phy_power_off(&usb_phys[i]);
+
+ for (i = 0; i < count; i++)
+ generic_phy_exit(&usb_phys[i]);
+
+ return ret;
+
+phys_init_err:
+ for (; i >= 0; i--)
+ generic_phy_exit(&usb_phys[i]);
+
+ return ret;
+}
+
+void dwc2_phy_shutdown(struct udevice *dev, struct phy *usb_phys, int num_phys)
+{
+ int i, ret;
+
+ for (i = 0; i < num_phys; i++) {
+ if (!generic_phy_valid(&usb_phys[i]))
+ continue;
+
+ ret = generic_phy_power_off(&usb_phys[i]);
+ ret |= generic_phy_exit(&usb_phys[i]);
+ if (ret) {
+ dev_err(dev, "Can't shutdown USB PHY%d for %s\n",
+ i, dev->name);
+ }
+ }
+}
+
+static int dwc2_udc_otg_ofdata_to_platdata(struct udevice *dev)
+{
+ struct dwc2_plat_otg_data *platdata = dev_get_platdata(dev);
+ int node = dev_of_offset(dev);
+ ulong drvdata;
+ void (*set_params)(struct dwc2_plat_otg_data *data);
+
+ if (usb_get_dr_mode(node) != USB_DR_MODE_PERIPHERAL) {
+ dev_dbg(dev, "Invalid mode\n");
+ return -ENODEV;
+ }
+
+ platdata->regs_otg = dev_read_addr(dev);
+
+ platdata->rx_fifo_sz = dev_read_u32_default(dev, "g-rx-fifo-size", 0);
+ platdata->np_tx_fifo_sz = dev_read_u32_default(dev,
+ "g-np-tx-fifo-size", 0);
+ platdata->tx_fifo_sz = dev_read_u32_default(dev, "g-tx-fifo-size", 0);
+
+ platdata->force_b_session_valid =
+ dev_read_bool(dev, "u-boot,force-b-session-valid");
+
+ /* force platdata according compatible */
+ drvdata = dev_get_driver_data(dev);
+ if (drvdata) {
+ set_params = (void *)drvdata;
+ set_params(platdata);
+ }
+
+ return 0;
+}
+
+static void dwc2_set_stm32mp1_hsotg_params(struct dwc2_plat_otg_data *p)
+{
+ p->activate_stm_id_vb_detection = true;
+ p->usb_gusbcfg =
+ 0 << 15 /* PHY Low Power Clock sel*/
+ | 0x9 << 10 /* USB Turnaround time (0x9 for HS phy) */
+ | 0 << 9 /* [0:HNP disable,1:HNP enable]*/
+ | 0 << 8 /* [0:SRP disable 1:SRP enable]*/
+ | 0 << 6 /* 0: high speed utmi+, 1: full speed serial*/
+ | 0x7 << 0; /* FS timeout calibration**/
+
+ if (p->force_b_session_valid)
+ p->usb_gusbcfg |= 1 << 30; /* FDMOD: Force device mode */
+}
+
+static int dwc2_udc_otg_reset_init(struct udevice *dev,
+ struct reset_ctl_bulk *resets)
+{
+ int ret;
+
+ ret = reset_get_bulk(dev, resets);
+ if (ret == -ENOTSUPP)
+ return 0;
+
+ if (ret)
+ return ret;
+
+ ret = reset_assert_bulk(resets);
+
+ if (!ret) {
+ udelay(2);
+ ret = reset_deassert_bulk(resets);
+ }
+ if (ret) {
+ reset_release_bulk(resets);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int dwc2_udc_otg_clk_init(struct udevice *dev,
+ struct clk_bulk *clks)
+{
+ int ret;
+
+ ret = clk_get_bulk(dev, clks);
+ if (ret == -ENOSYS)
+ return 0;
+
+ if (ret)
+ return ret;
+
+ ret = clk_enable_bulk(clks);
+ if (ret) {
+ clk_release_bulk(clks);
+ return ret;
+ }
+
return 0;
}
+
+static int dwc2_udc_otg_probe(struct udevice *dev)
+{
+ struct dwc2_plat_otg_data *platdata = dev_get_platdata(dev);
+ struct dwc2_priv_data *priv = dev_get_priv(dev);
+ struct dwc2_usbotg_reg *usbotg_reg =
+ (struct dwc2_usbotg_reg *)platdata->regs_otg;
+ int ret;
+
+ ret = dwc2_udc_otg_clk_init(dev, &priv->clks);
+ if (ret)
+ return ret;
+
+ ret = dwc2_udc_otg_reset_init(dev, &priv->resets);
+ if (ret)
+ return ret;
+
+ ret = dwc2_phy_setup(dev, &priv->phys, &priv->num_phys);
+ if (ret)
+ return ret;
+
+ if (CONFIG_IS_ENABLED(DM_REGULATOR) &&
+ platdata->activate_stm_id_vb_detection &&
+ !platdata->force_b_session_valid) {
+ ret = device_get_supply_regulator(dev, "usb33d-supply",
+ &priv->usb33d_supply);
+ if (ret) {
+ dev_err(dev, "can't get voltage level detector supply\n");
+ return ret;
+ }
+ ret = regulator_set_enable(priv->usb33d_supply, true);
+ if (ret) {
+ dev_err(dev, "can't enable voltage level detector supply\n");
+ return ret;
+ }
+ /* Enable vbus sensing */
+ setbits_le32(&usbotg_reg->ggpio,
+ GGPIO_STM32_OTG_GCCFG_VBDEN |
+ GGPIO_STM32_OTG_GCCFG_IDEN);
+ }
+
+ if (platdata->force_b_session_valid)
+ /* Override B session bits : value and enable */
+ setbits_le32(&usbotg_reg->gotgctl,
+ A_VALOEN | A_VALOVAL | B_VALOEN | B_VALOVAL);
+
+ ret = dwc2_udc_probe(platdata);
+ if (ret)
+ return ret;
+
+ the_controller->driver = 0;
+
+ ret = usb_add_gadget_udc((struct device *)dev, &the_controller->gadget);
+
+ return ret;
+}
+
+static int dwc2_udc_otg_remove(struct udevice *dev)
+{
+ struct dwc2_priv_data *priv = dev_get_priv(dev);
+
+ usb_del_gadget_udc(&the_controller->gadget);
+
+ reset_release_bulk(&priv->resets);
+
+ clk_release_bulk(&priv->clks);
+
+ dwc2_phy_shutdown(dev, priv->phys, priv->num_phys);
+
+ return dm_scan_fdt_dev(dev);
+}
+
+static const struct udevice_id dwc2_udc_otg_ids[] = {
+ { .compatible = "snps,dwc2" },
+ { .compatible = "st,stm32mp1-hsotg",
+ .data = (ulong)dwc2_set_stm32mp1_hsotg_params },
+ {},
+};
+
+U_BOOT_DRIVER(dwc2_udc_otg) = {
+ .name = "dwc2-udc-otg",
+ .id = UCLASS_USB_GADGET_GENERIC,
+ .of_match = dwc2_udc_otg_ids,
+ .ofdata_to_platdata = dwc2_udc_otg_ofdata_to_platdata,
+ .probe = dwc2_udc_otg_probe,
+ .remove = dwc2_udc_otg_remove,
+ .platdata_auto_alloc_size = sizeof(struct dwc2_plat_otg_data),
+ .priv_auto_alloc_size = sizeof(struct dwc2_priv_data),
+};
+
+int dwc2_udc_B_session_valid(struct udevice *dev)
+{
+ struct dwc2_plat_otg_data *platdata = dev_get_platdata(dev);
+ struct dwc2_usbotg_reg *usbotg_reg =
+ (struct dwc2_usbotg_reg *)platdata->regs_otg;
+
+ return readl(&usbotg_reg->gotgctl) & B_SESSION_VALID;
+}
+#endif /* CONFIG_IS_ENABLED(DM_USB_GADGET) */
diff --git a/drivers/usb/gadget/dwc2_udc_otg_priv.h b/drivers/usb/gadget/dwc2_udc_otg_priv.h
index aaa9018..e72b22a 100644
--- a/drivers/usb/gadget/dwc2_udc_otg_priv.h
+++ b/drivers/usb/gadget/dwc2_udc_otg_priv.h
@@ -23,7 +23,6 @@
#define EP_FIFO_SIZE2 1024
/* ep0-control, ep1in-bulk, ep2out-bulk, ep3in-int */
#define DWC2_MAX_ENDPOINTS 4
-#define DWC2_MAX_HW_ENDPOINTS 16
#define WAIT_FOR_SETUP 0
#define DATA_STATE_XMIT 1
diff --git a/drivers/usb/gadget/dwc2_udc_otg_regs.h b/drivers/usb/gadget/dwc2_udc_otg_regs.h
index a1829b3..434db5b 100644
--- a/drivers/usb/gadget/dwc2_udc_otg_regs.h
+++ b/drivers/usb/gadget/dwc2_udc_otg_regs.h
@@ -60,22 +60,26 @@
u32 grxstsp; /* Receive Status Debug Pop/Status Pop */
u32 grxfsiz; /* Receive FIFO Size */
u32 gnptxfsiz; /* Non-Periodic Transmit FIFO Size */
- u8 res1[216];
+ u8 res0[12];
+ u32 ggpio; /* 0x038 */
+ u8 res1[20];
+ u32 ghwcfg4; /* User HW Config4 */
+ u8 res2[176];
u32 dieptxf[15]; /* Device Periodic Transmit FIFO size register */
- u8 res2[1728];
+ u8 res3[1728];
/* Device Configuration */
u32 dcfg; /* Device Configuration Register */
u32 dctl; /* Device Control */
u32 dsts; /* Device Status */
- u8 res3[4];
+ u8 res4[4];
u32 diepmsk; /* Device IN Endpoint Common Interrupt Mask */
u32 doepmsk; /* Device OUT Endpoint Common Interrupt Mask */
u32 daint; /* Device All Endpoints Interrupt */
u32 daintmsk; /* Device All Endpoints Interrupt Mask */
- u8 res4[224];
+ u8 res5[224];
struct dwc2_dev_in_endp in_endp[16];
struct dwc2_dev_out_endp out_endp[16];
- u8 res5[768];
+ u8 res6[768];
struct ep_fifo ep[16];
};
@@ -83,8 +87,15 @@
/*definitions related to CSR setting */
/* DWC2_UDC_OTG_GOTGCTL */
-#define B_SESSION_VALID (0x1<<19)
-#define A_SESSION_VALID (0x1<<18)
+#define B_SESSION_VALID BIT(19)
+#define A_SESSION_VALID BIT(18)
+#define B_VALOVAL BIT(7)
+#define B_VALOEN BIT(6)
+#define A_VALOVAL BIT(5)
+#define A_VALOEN BIT(4)
+
+/* DWC2_UDC_OTG_GOTINT */
+#define GOTGINT_SES_END_DET (1<<2)
/* DWC2_UDC_OTG_GAHBCFG */
#define PTXFE_HALF (0<<8)
@@ -118,6 +129,7 @@
#define INT_NP_TX_FIFO_EMPTY (0x1<<5)
#define INT_RX_FIFO_NOT_EMPTY (0x1<<4)
#define INT_SOF (0x1<<3)
+#define INT_OTG (0x1<<2)
#define INT_DEV_MODE (0x0<<0)
#define INT_HOST_MODE (0x1<<1)
#define INT_GOUTNakEff (0x01<<7)
@@ -246,7 +258,7 @@
/* Masks definitions */
#define GINTMSK_INIT (INT_OUT_EP | INT_IN_EP | INT_RESUME | INT_ENUMDONE\
- | INT_RESET | INT_SUSPEND)
+ | INT_RESET | INT_SUSPEND | INT_OTG)
#define DOEPMSK_INIT (CTRL_OUT_EP_SETUP_PHASE_DONE | AHB_ERROR|TRANSFER_DONE)
#define DIEPMSK_INIT (NON_ISO_IN_EP_TIMEOUT|AHB_ERROR|TRANSFER_DONE)
#define GAHBCFG_INIT (PTXFE_HALF | NPTXFE_HALF | MODE_DMA | BURST_INCR4\
@@ -269,4 +281,13 @@
/* Device ALL Endpoints Interrupt Register (DAINT) */
#define DAINT_IN_EP_INT(x) (x << 0)
#define DAINT_OUT_EP_INT(x) (x << 16)
+
+/* User HW Config4 */
+#define GHWCFG4_NUM_IN_EPS_MASK (0xf << 26)
+#define GHWCFG4_NUM_IN_EPS_SHIFT 26
+
+/* OTG general core configuration register (OTG_GCCFG:0x38) for STM32MP1 */
+#define GGPIO_STM32_OTG_GCCFG_VBDEN BIT(21)
+#define GGPIO_STM32_OTG_GCCFG_IDEN BIT(22)
+
#endif
diff --git a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
index a75af49..7eb632d 100644
--- a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
+++ b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
@@ -467,7 +467,7 @@
static int dwc2_udc_irq(int irq, void *_dev)
{
struct dwc2_udc *dev = _dev;
- u32 intr_status;
+ u32 intr_status, gotgint;
u32 usb_status, gintmsk;
unsigned long flags = 0;
@@ -521,14 +521,24 @@
&& dev->driver) {
if (dev->driver->suspend)
dev->driver->suspend(&dev->gadget);
+ }
+ }
+
+ if (intr_status & INT_OTG) {
+ gotgint = readl(®->gotgint);
+ debug_cond(DEBUG_ISR,
+ "\tOTG interrupt: (GOTGINT):0x%x\n", gotgint);
- /* HACK to let gadget detect disconnected state */
+ if (gotgint & GOTGINT_SES_END_DET) {
+ debug_cond(DEBUG_ISR, "\t\tSession End Detected\n");
+ /* Let gadget detect disconnected state */
if (dev->driver->disconnect) {
spin_unlock_irqrestore(&dev->lock, flags);
dev->driver->disconnect(&dev->gadget);
spin_lock_irqsave(&dev->lock, flags);
}
}
+ writel(gotgint, ®->gotgint);
}
if (intr_status & INT_RESUME) {
diff --git a/drivers/usb/musb-new/Kconfig b/drivers/usb/musb-new/Kconfig
index f8f2205a..75005cc 100644
--- a/drivers/usb/musb-new/Kconfig
+++ b/drivers/usb/musb-new/Kconfig
@@ -21,6 +21,7 @@
config USB_MUSB_TI
bool "Enable TI OTG USB controller"
depends on DM_USB
+ select USB_MUSB_DSPS
default n
help
Say y here to enable support for the dual role high
@@ -54,6 +55,15 @@
Say y here to enable support for the sunxi OTG / DRC USB controller
used on almost all sunxi boards.
+config USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
+ bool "Disable MUSB bulk split/combine"
+ default y
+ help
+ On TI AM335x devices, MUSB has bulk split/combine feature enabled
+ in the ConfigData register, but the current MUSB driver does not
+ support it yet. Select this option to disable the feature until the
+ driver adds the support.
+
endif
config USB_MUSB_PIO_ONLY
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 0834ff5..7721907 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -240,7 +240,6 @@
* add mass storage support and for gadget we add both RNDIS ethernet
* and DFU.
*/
-#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
#define CONFIG_AM335X_USB0
#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
#define CONFIG_AM335X_USB1
diff --git a/include/configs/baltos.h b/include/configs/baltos.h
index ccbdc0a..98ec0d6 100644
--- a/include/configs/baltos.h
+++ b/include/configs/baltos.h
@@ -251,7 +251,6 @@
* add mass storage support and for gadget we add both RNDIS ethernet
* and DFU.
*/
-#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
#define CONFIG_AM335X_USB0
#define CONFIG_AM335X_USB0_MODE MUSB_HOST
#define CONFIG_AM335X_USB1
diff --git a/include/configs/bav335x.h b/include/configs/bav335x.h
index fb9c2a6..3d4d08a 100644
--- a/include/configs/bav335x.h
+++ b/include/configs/bav335x.h
@@ -387,7 +387,6 @@
* add mass storage support and for gadget we add both RNDIS ethernet
* and DFU.
*/
-#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
#define CONFIG_AM335X_USB0
#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
#define CONFIG_AM335X_USB1
diff --git a/include/configs/broadcom_bcm963158.h b/include/configs/broadcom_bcm963158.h
index 5834e1e..2de6f21 100644
--- a/include/configs/broadcom_bcm963158.h
+++ b/include/configs/broadcom_bcm963158.h
@@ -30,6 +30,13 @@
#define CONFIG_SKIP_LOWLEVEL_INIT
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
+#endif /* CONFIG_NAND */
+
/*
* bcm963158
*/
diff --git a/include/configs/broadcom_bcm968380gerg.h b/include/configs/broadcom_bcm968380gerg.h
index 6126a88..355f3ef 100644
--- a/include/configs/broadcom_bcm968380gerg.h
+++ b/include/configs/broadcom_bcm968380gerg.h
@@ -7,3 +7,10 @@
#include <configs/bmips_bcm6838.h>
#define CONFIG_ENV_SIZE (8 * 1024)
+
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
+#endif /* CONFIG_NAND */
diff --git a/include/configs/broadcom_bcm968580xref.h b/include/configs/broadcom_bcm968580xref.h
index 1c0945e..52b4f55 100644
--- a/include/configs/broadcom_bcm968580xref.h
+++ b/include/configs/broadcom_bcm968580xref.h
@@ -29,6 +29,13 @@
#define CONFIG_SKIP_LOWLEVEL_INIT
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
+#endif /* CONFIG_NAND */
+
/*
* 968580xref
*/
diff --git a/include/configs/brppt1.h b/include/configs/brppt1.h
index ae9b75b..84c801d 100644
--- a/include/configs/brppt1.h
+++ b/include/configs/brppt1.h
@@ -182,9 +182,6 @@
#define CONFIG_NAND_OMAP_GPMC_WSCFG 1
#endif /* CONFIG_NAND */
-/* USB configuration */
-#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
-
#if defined(CONFIG_SPI)
/* SPI Flash */
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
diff --git a/include/configs/brxre1.h b/include/configs/brxre1.h
index 601b30d..7309e7d 100644
--- a/include/configs/brxre1.h
+++ b/include/configs/brxre1.h
@@ -68,9 +68,6 @@
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
-/* USB configuration */
-#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
-
/* Environment */
#define CONFIG_SYS_MMC_ENV_DEV 1
#define CONFIG_SYS_MMC_ENV_PART 2
diff --git a/include/configs/chiliboard.h b/include/configs/chiliboard.h
index 4372280..db990fc 100644
--- a/include/configs/chiliboard.h
+++ b/include/configs/chiliboard.h
@@ -148,7 +148,6 @@
/* USB configuration */
#define CONFIG_ARCH_MISC_INIT
-#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
#define CONFIG_AM335X_USB1
#define CONFIG_AM335X_USB1_MODE MUSB_HOST
diff --git a/include/configs/corvus.h b/include/configs/corvus.h
index 749a67d..e85f684 100644
--- a/include/configs/corvus.h
+++ b/include/configs/corvus.h
@@ -72,6 +72,7 @@
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8
+#define CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
#endif
/* Ethernet */
diff --git a/include/configs/libretech-ac.h b/include/configs/libretech-ac.h
new file mode 100644
index 0000000..419dc61
--- /dev/null
+++ b/include/configs/libretech-ac.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration for LibreTech AC
+ *
+ * Copyright (C) 2017 Baylibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#define CONFIG_ENV_OFFSET (-0x10000)
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(ROMUSB, romusb, na) \
+ func(MMC, mmc, 0) \
+ BOOT_TARGET_DEVICES_USB(func) \
+ func(PXE, pxe, na) \
+ func(DHCP, dhcp, na)
+
+#include <configs/meson64.h>
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h
index 48f1f7b..a535d0c 100644
--- a/include/configs/pengwyn.h
+++ b/include/configs/pengwyn.h
@@ -157,7 +157,6 @@
* board schematic and physical port wired to each. Then for host we
* add mass storage support.
*/
-#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
#define CONFIG_AM335X_USB0
#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
#define CONFIG_AM335X_USB1
diff --git a/include/configs/sama5d2_icp.h b/include/configs/sama5d2_icp.h
new file mode 100644
index 0000000..afcd22b
--- /dev/null
+++ b/include/configs/sama5d2_icp.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration file for the SAMA5D2 ICP Board.
+ *
+ * Copyright (C) 2018 Microchip Corporation
+ * Eugen Hristev <eugen.hristev@microchip.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "at91-sama5_common.h"
+
+#undef CONFIG_SYS_AT91_MAIN_CLOCK
+#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
+
+#define CONFIG_MISC_INIT_R
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE 0x20000000
+#define CONFIG_SYS_SDRAM_SIZE 0x20000000
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_INIT_SP_ADDR 0x218000
+#else
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
+
+/* NAND flash */
+#undef CONFIG_CMD_NAND
+
+/* SPI flash */
+#define CONFIG_SF_DEFAULT_SPEED 66000000
+
+#undef CONFIG_BOOTCOMMAND
+#ifdef CONFIG_SD_BOOT
+/* u-boot env in sd/mmc card */
+#define FAT_ENV_INTERFACE "mmc"
+#define FAT_ENV_DEVICE_AND_PART "0"
+#define FAT_ENV_FILE "uboot.env"
+#define CONFIG_ENV_SIZE 0x4000
+/* bootstrap + u-boot + env in sd card */
+#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 at91-sama5d2_icp.dtb; " \
+ "fatload mmc 0:1 0x22000000 zImage; " \
+ "bootz 0x22000000 - 0x21000000"
+#undef CONFIG_BOOTARGS
+#define CONFIG_BOOTARGS \
+ "console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
+#endif
+
+/* SPL */
+#define CONFIG_SPL_TEXT_BASE 0x200000
+#define CONFIG_SPL_MAX_SIZE 0x10000
+#define CONFIG_SPL_BSS_START_ADDR 0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
+#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
+
+#define CONFIG_SYS_MONITOR_LEN (512 << 10)
+
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
+#endif
+
+#endif
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index f44a428..1170f24 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -150,8 +150,6 @@
/*
* USB configuration
*/
-#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
-
#define CONFIG_AM335X_USB0
#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
#define CONFIG_AM335X_USB1
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 09c9b7c..f9e2cdc 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -338,6 +338,7 @@
"scriptaddr=0x02100000\0" \
"pxefile_addr_r=0x02200000\0" \
"ramdisk_addr_r=0x02300000\0" \
+ "socfpga_legacy_reset_compat=1\0" \
BOOTENV
#endif
diff --git a/include/dt-bindings/clock/g12a-aoclkc.h b/include/dt-bindings/clock/g12a-aoclkc.h
new file mode 100644
index 0000000..8db01ff
--- /dev/null
+++ b/include/dt-bindings/clock/g12a-aoclkc.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (c) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai@amlogic.com>
+ */
+
+#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK
+#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK
+
+#define CLKID_AO_AHB 0
+#define CLKID_AO_IR_IN 1
+#define CLKID_AO_I2C_M0 2
+#define CLKID_AO_I2C_S0 3
+#define CLKID_AO_UART 4
+#define CLKID_AO_PROD_I2C 5
+#define CLKID_AO_UART2 6
+#define CLKID_AO_IR_OUT 7
+#define CLKID_AO_SAR_ADC 8
+#define CLKID_AO_MAILBOX 9
+#define CLKID_AO_M3 10
+#define CLKID_AO_AHB_SRAM 11
+#define CLKID_AO_RTI 12
+#define CLKID_AO_M4_FCLK 13
+#define CLKID_AO_M4_HCLK 14
+#define CLKID_AO_CLK81 15
+#define CLKID_AO_SAR_ADC_CLK 18
+#define CLKID_AO_32K 23
+#define CLKID_AO_CEC 27
+#define CLKID_AO_CTS_RTC_OSCIN 28
+
+#endif
diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h
new file mode 100644
index 0000000..83b6570
--- /dev/null
+++ b/include/dt-bindings/clock/g12a-clkc.h
@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: GPL-2.0+ OR MIT */
+/*
+ * Meson-G12A clock tree IDs
+ *
+ * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __G12A_CLKC_H
+#define __G12A_CLKC_H
+
+#define CLKID_SYS_PLL 0
+#define CLKID_FIXED_PLL 1
+#define CLKID_FCLK_DIV2 2
+#define CLKID_FCLK_DIV3 3
+#define CLKID_FCLK_DIV4 4
+#define CLKID_FCLK_DIV5 5
+#define CLKID_FCLK_DIV7 6
+#define CLKID_GP0_PLL 7
+#define CLKID_CLK81 10
+#define CLKID_MPLL0 11
+#define CLKID_MPLL1 12
+#define CLKID_MPLL2 13
+#define CLKID_MPLL3 14
+#define CLKID_DDR 15
+#define CLKID_DOS 16
+#define CLKID_AUDIO_LOCKER 17
+#define CLKID_MIPI_DSI_HOST 18
+#define CLKID_ETH_PHY 19
+#define CLKID_ISA 20
+#define CLKID_PL301 21
+#define CLKID_PERIPHS 22
+#define CLKID_SPICC0 23
+#define CLKID_I2C 24
+#define CLKID_SANA 25
+#define CLKID_SD 26
+#define CLKID_RNG0 27
+#define CLKID_UART0 28
+#define CLKID_SPICC1 29
+#define CLKID_HIU_IFACE 30
+#define CLKID_MIPI_DSI_PHY 31
+#define CLKID_ASSIST_MISC 32
+#define CLKID_SD_EMMC_A 33
+#define CLKID_SD_EMMC_B 34
+#define CLKID_SD_EMMC_C 35
+#define CLKID_AUDIO_CODEC 36
+#define CLKID_AUDIO 37
+#define CLKID_ETH 38
+#define CLKID_DEMUX 39
+#define CLKID_AUDIO_IFIFO 40
+#define CLKID_ADC 41
+#define CLKID_UART1 42
+#define CLKID_G2D 43
+#define CLKID_RESET 44
+#define CLKID_PCIE_COMB 45
+#define CLKID_PARSER 46
+#define CLKID_USB 47
+#define CLKID_PCIE_PHY 48
+#define CLKID_AHB_ARB0 49
+#define CLKID_AHB_DATA_BUS 50
+#define CLKID_AHB_CTRL_BUS 51
+#define CLKID_HTX_HDCP22 52
+#define CLKID_HTX_PCLK 53
+#define CLKID_BT656 54
+#define CLKID_USB1_DDR_BRIDGE 55
+#define CLKID_MMC_PCLK 56
+#define CLKID_UART2 57
+#define CLKID_VPU_INTR 58
+#define CLKID_GIC 59
+#define CLKID_SD_EMMC_A_CLK0 60
+#define CLKID_SD_EMMC_B_CLK0 61
+#define CLKID_SD_EMMC_C_CLK0 62
+#define CLKID_HIFI_PLL 74
+#define CLKID_VCLK2_VENCI0 80
+#define CLKID_VCLK2_VENCI1 81
+#define CLKID_VCLK2_VENCP0 82
+#define CLKID_VCLK2_VENCP1 83
+#define CLKID_VCLK2_VENCT0 84
+#define CLKID_VCLK2_VENCT1 85
+#define CLKID_VCLK2_OTHER 86
+#define CLKID_VCLK2_ENCI 87
+#define CLKID_VCLK2_ENCP 88
+#define CLKID_DAC_CLK 89
+#define CLKID_AOCLK 90
+#define CLKID_IEC958 91
+#define CLKID_ENC480P 92
+#define CLKID_RNG1 93
+#define CLKID_VCLK2_ENCT 94
+#define CLKID_VCLK2_ENCL 95
+#define CLKID_VCLK2_VENCLMMC 96
+#define CLKID_VCLK2_VENCL 97
+#define CLKID_VCLK2_OTHER1 98
+#define CLKID_FCLK_DIV2P5 99
+#define CLKID_DMA 105
+#define CLKID_EFUSE 106
+#define CLKID_ROM_BOOT 107
+#define CLKID_RESET_SEC 108
+#define CLKID_SEC_AHB_APB3 109
+#define CLKID_VPU_0_SEL 110
+#define CLKID_VPU_0 112
+#define CLKID_VPU_1_SEL 113
+#define CLKID_VPU_1 115
+#define CLKID_VPU 116
+#define CLKID_VAPB_0_SEL 117
+#define CLKID_VAPB_0 119
+#define CLKID_VAPB_1_SEL 120
+#define CLKID_VAPB_1 122
+#define CLKID_VAPB_SEL 123
+#define CLKID_VAPB 124
+#define CLKID_HDMI_PLL 128
+#define CLKID_VID_PLL 129
+#define CLKID_VCLK 138
+#define CLKID_VCLK2 139
+#define CLKID_VCLK_DIV1 148
+#define CLKID_VCLK_DIV2 149
+#define CLKID_VCLK_DIV4 150
+#define CLKID_VCLK_DIV6 151
+#define CLKID_VCLK_DIV12 152
+#define CLKID_VCLK2_DIV1 153
+#define CLKID_VCLK2_DIV2 154
+#define CLKID_VCLK2_DIV4 155
+#define CLKID_VCLK2_DIV6 156
+#define CLKID_VCLK2_DIV12 157
+#define CLKID_CTS_ENCI 162
+#define CLKID_CTS_ENCP 163
+#define CLKID_CTS_VDAC 164
+#define CLKID_HDMI_TX 165
+#define CLKID_HDMI 168
+#define CLKID_MALI_0_SEL 169
+#define CLKID_MALI_0 171
+#define CLKID_MALI_1_SEL 172
+#define CLKID_MALI_1 174
+#define CLKID_MALI 175
+#define CLKID_MPLL_5OM 177
+
+#endif /* __G12A_CLKC_H */
diff --git a/include/dt-bindings/clock/mt8516-clk.h b/include/dt-bindings/clock/mt8516-clk.h
new file mode 100644
index 0000000..745b87f
--- /dev/null
+++ b/include/dt-bindings/clock/mt8516-clk.h
@@ -0,0 +1,251 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018 BayLibre, SAS
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT8516_H
+#define _DT_BINDINGS_CLK_MT8516_H
+
+
+/* APMIXEDSYS */
+
+#define CLK_APMIXED_ARMPLL 0
+#define CLK_APMIXED_MAINPLL 1
+#define CLK_APMIXED_UNIVPLL 2
+#define CLK_APMIXED_MMPLL 3
+#define CLK_APMIXED_APLL1 4
+#define CLK_APMIXED_APLL2 5
+#define CLK_APMIXED_NR_CLK 6
+
+/* TOPCKGEN */
+
+#define CLK_TOP_CLK_NULL 0
+#define CLK_TOP_I2S_INFRA_BCK 1
+#define CLK_TOP_MEMPLL 2
+#define CLK_TOP_DMPLL 3
+#define CLK_TOP_MAINPLL_D2 4
+#define CLK_TOP_MAINPLL_D4 5
+#define CLK_TOP_MAINPLL_D8 6
+#define CLK_TOP_MAINPLL_D16 7
+#define CLK_TOP_MAINPLL_D11 8
+#define CLK_TOP_MAINPLL_D22 9
+#define CLK_TOP_MAINPLL_D3 10
+#define CLK_TOP_MAINPLL_D6 11
+#define CLK_TOP_MAINPLL_D12 12
+#define CLK_TOP_MAINPLL_D5 13
+#define CLK_TOP_MAINPLL_D10 14
+#define CLK_TOP_MAINPLL_D20 15
+#define CLK_TOP_MAINPLL_D40 16
+#define CLK_TOP_MAINPLL_D7 17
+#define CLK_TOP_MAINPLL_D14 18
+#define CLK_TOP_UNIVPLL_D2 19
+#define CLK_TOP_UNIVPLL_D4 20
+#define CLK_TOP_UNIVPLL_D8 21
+#define CLK_TOP_UNIVPLL_D16 22
+#define CLK_TOP_UNIVPLL_D3 23
+#define CLK_TOP_UNIVPLL_D6 24
+#define CLK_TOP_UNIVPLL_D12 25
+#define CLK_TOP_UNIVPLL_D24 26
+#define CLK_TOP_UNIVPLL_D5 27
+#define CLK_TOP_UNIVPLL_D20 28
+#define CLK_TOP_MMPLL380M 29
+#define CLK_TOP_MMPLL_D2 30
+#define CLK_TOP_MMPLL_200M 31
+#define CLK_TOP_USB_PHY48M 32
+#define CLK_TOP_APLL1 33
+#define CLK_TOP_APLL1_D2 34
+#define CLK_TOP_APLL1_D4 35
+#define CLK_TOP_APLL1_D8 36
+#define CLK_TOP_APLL2 37
+#define CLK_TOP_APLL2_D2 38
+#define CLK_TOP_APLL2_D4 39
+#define CLK_TOP_APLL2_D8 40
+#define CLK_TOP_CLK26M 41
+#define CLK_TOP_CLK26M_D2 42
+#define CLK_TOP_AHB_INFRA_D2 43
+#define CLK_TOP_NFI1X 44
+#define CLK_TOP_ETH_D2 45
+#define CLK_TOP_UART0_SEL 46
+#define CLK_TOP_GFMUX_EMI1X_SEL 47
+#define CLK_TOP_EMI_DDRPHY_SEL 48
+#define CLK_TOP_AHB_INFRA_SEL 49
+#define CLK_TOP_CSW_MUX_MFG_SEL 50
+#define CLK_TOP_MSDC0_SEL 51
+#define CLK_TOP_PWM_MM_SEL 52
+#define CLK_TOP_UART1_SEL 53
+#define CLK_TOP_MSDC1_SEL 54
+#define CLK_TOP_SPM_52M_SEL 55
+#define CLK_TOP_PMICSPI_SEL 56
+#define CLK_TOP_QAXI_AUD26M_SEL 57
+#define CLK_TOP_AUD_INTBUS_SEL 58
+#define CLK_TOP_NFI2X_PAD_SEL 59
+#define CLK_TOP_NFI1X_PAD_SEL 60
+#define CLK_TOP_MFG_MM_SEL 61
+#define CLK_TOP_DDRPHYCFG_SEL 62
+#define CLK_TOP_USB_78M_SEL 63
+#define CLK_TOP_SPINOR_SEL 64
+#define CLK_TOP_MSDC2_SEL 65
+#define CLK_TOP_ETH_SEL 66
+#define CLK_TOP_AXI_MFG_IN_SEL 67
+#define CLK_TOP_SLOW_MFG_SEL 68
+#define CLK_TOP_AUD1_SEL 69
+#define CLK_TOP_AUD2_SEL 70
+#define CLK_TOP_AUD_ENGEN1_SEL 71
+#define CLK_TOP_AUD_ENGEN2_SEL 72
+#define CLK_TOP_I2C_SEL 73
+#define CLK_TOP_AUD_I2S0_M_SEL 74
+#define CLK_TOP_AUD_I2S1_M_SEL 75
+#define CLK_TOP_AUD_I2S2_M_SEL 76
+#define CLK_TOP_AUD_I2S3_M_SEL 77
+#define CLK_TOP_AUD_I2S4_M_SEL 78
+#define CLK_TOP_AUD_I2S5_M_SEL 79
+#define CLK_TOP_AUD_SPDIF_B_SEL 80
+#define CLK_TOP_PWM_SEL 81
+#define CLK_TOP_SPI_SEL 82
+#define CLK_TOP_AUD_SPDIFIN_SEL 83
+#define CLK_TOP_UART2_SEL 84
+#define CLK_TOP_BSI_SEL 85
+#define CLK_TOP_DBG_ATCLK_SEL 86
+#define CLK_TOP_CSW_NFIECC_SEL 87
+#define CLK_TOP_NFIECC_SEL 88
+#define CLK_TOP_APLL12_CK_DIV0 89
+#define CLK_TOP_APLL12_CK_DIV1 90
+#define CLK_TOP_APLL12_CK_DIV2 91
+#define CLK_TOP_APLL12_CK_DIV3 92
+#define CLK_TOP_APLL12_CK_DIV4 93
+#define CLK_TOP_APLL12_CK_DIV4B 94
+#define CLK_TOP_APLL12_CK_DIV5 95
+#define CLK_TOP_APLL12_CK_DIV5B 96
+#define CLK_TOP_APLL12_CK_DIV6 97
+#define CLK_TOP_NR_CLK 98
+
+/* TOPCKGEN Gates */
+#define CLK_TOP_PWM_MM 0
+#define CLK_TOP_MFG_MM 1
+#define CLK_TOP_SPM_52M 2
+#define CLK_TOP_THEM 3
+#define CLK_TOP_APDMA 4
+#define CLK_TOP_I2C0 5
+#define CLK_TOP_I2C1 6
+#define CLK_TOP_AUXADC1 7
+#define CLK_TOP_NFI 8
+#define CLK_TOP_NFIECC 9
+#define CLK_TOP_DEBUGSYS 10
+#define CLK_TOP_PWM 11
+#define CLK_TOP_UART0 12
+#define CLK_TOP_UART1 13
+#define CLK_TOP_BTIF 14
+#define CLK_TOP_USB 15
+#define CLK_TOP_FLASHIF_26M 16
+#define CLK_TOP_AUXADC2 17
+#define CLK_TOP_I2C2 18
+#define CLK_TOP_MSDC0 19
+#define CLK_TOP_MSDC1 20
+#define CLK_TOP_NFI2X 21
+#define CLK_TOP_PMICWRAP_AP 22
+#define CLK_TOP_SEJ 23
+#define CLK_TOP_MEMSLP_DLYER 24
+#define CLK_TOP_SPI 25
+#define CLK_TOP_APXGPT 26
+#define CLK_TOP_AUDIO 27
+#define CLK_TOP_PMICWRAP_MD 28
+#define CLK_TOP_PMICWRAP_CONN 29
+#define CLK_TOP_PMICWRAP_26M 30
+#define CLK_TOP_AUX_ADC 31
+#define CLK_TOP_AUX_TP 32
+#define CLK_TOP_MSDC2 33
+#define CLK_TOP_RBIST 34
+#define CLK_TOP_NFI_BUS 35
+#define CLK_TOP_GCE 36
+#define CLK_TOP_TRNG 37
+#define CLK_TOP_SEJ_13M 38
+#define CLK_TOP_AES 39
+#define CLK_TOP_PWM_B 40
+#define CLK_TOP_PWM1_FB 41
+#define CLK_TOP_PWM2_FB 42
+#define CLK_TOP_PWM3_FB 43
+#define CLK_TOP_PWM4_FB 44
+#define CLK_TOP_PWM5_FB 45
+#define CLK_TOP_USB_1P 46
+#define CLK_TOP_FLASHIF_FREERUN 47
+#define CLK_TOP_66M_ETH 48
+#define CLK_TOP_133M_ETH 49
+#define CLK_TOP_FETH_25M 50
+#define CLK_TOP_FETH_50M 51
+#define CLK_TOP_FLASHIF_AXI 52
+#define CLK_TOP_USBIF 53
+#define CLK_TOP_UART2 54
+#define CLK_TOP_BSI 55
+#define CLK_TOP_MSDC0_INFRA 56
+#define CLK_TOP_MSDC1_INFRA 57
+#define CLK_TOP_MSDC2_INFRA 58
+#define CLK_TOP_USB_78M 59
+#define CLK_TOP_RG_SPINOR 60
+#define CLK_TOP_RG_MSDC2 61
+#define CLK_TOP_RG_ETH 62
+#define CLK_TOP_RG_AXI_MFG 63
+#define CLK_TOP_RG_SLOW_MFG 64
+#define CLK_TOP_RG_AUD1 65
+#define CLK_TOP_RG_AUD2 66
+#define CLK_TOP_RG_AUD_ENGEN1 67
+#define CLK_TOP_RG_AUD_ENGEN2 68
+#define CLK_TOP_RG_I2C 69
+#define CLK_TOP_RG_PWM_INFRA 70
+#define CLK_TOP_RG_AUD_SPDIF_IN 71
+#define CLK_TOP_RG_UART2 72
+#define CLK_TOP_RG_BSI 73
+#define CLK_TOP_RG_DBG_ATCLK 74
+#define CLK_TOP_RG_NFIECC 75
+#define CLK_TOP_RG_APLL1_D2_EN 76
+#define CLK_TOP_RG_APLL1_D4_EN 77
+#define CLK_TOP_RG_APLL1_D8_EN 78
+#define CLK_TOP_RG_APLL2_D2_EN 79
+#define CLK_TOP_RG_APLL2_D4_EN 80
+#define CLK_TOP_RG_APLL2_D8_EN 81
+#define CLK_TOP_APLL12_DIV0 82
+#define CLK_TOP_APLL12_DIV1 83
+#define CLK_TOP_APLL12_DIV2 84
+#define CLK_TOP_APLL12_DIV3 85
+#define CLK_TOP_APLL12_DIV4 86
+#define CLK_TOP_APLL12_DIV4B 87
+#define CLK_TOP_APLL12_DIV5 88
+#define CLK_TOP_APLL12_DIV5B 89
+#define CLK_TOP_APLL12_DIV6 90
+
+/* INFRACFG */
+
+#define CLK_IFR_MUX1_SEL 0
+#define CLK_IFR_ETH_25M_SEL 1
+#define CLK_IFR_I2C0_SEL 2
+#define CLK_IFR_I2C1_SEL 3
+#define CLK_IFR_I2C2_SEL 4
+#define CLK_IFR_NR_CLK 5
+
+/* AUDIOTOP */
+
+#define CLK_AUD_AFE 0
+#define CLK_AUD_I2S 1
+#define CLK_AUD_22M 2
+#define CLK_AUD_24M 3
+#define CLK_AUD_INTDIR 4
+#define CLK_AUD_APLL2_TUNER 5
+#define CLK_AUD_APLL_TUNER 6
+#define CLK_AUD_HDMI 7
+#define CLK_AUD_SPDF 8
+#define CLK_AUD_ADC 9
+#define CLK_AUD_DAC 10
+#define CLK_AUD_DAC_PREDIS 11
+#define CLK_AUD_TML 12
+#define CLK_AUD_NR_CLK 13
+
+/* MFGCFG */
+
+#define CLK_MFG_BAXI 0
+#define CLK_MFG_BMEM 1
+#define CLK_MFG_BG3D 2
+#define CLK_MFG_B26M 3
+#define CLK_MFG_NR_CLK 4
+
+#endif /* _DT_BINDINGS_CLK_MT8516_H */
diff --git a/include/dt-bindings/gpio/meson-g12a-gpio.h b/include/dt-bindings/gpio/meson-g12a-gpio.h
new file mode 100644
index 0000000..f7bd693
--- /dev/null
+++ b/include/dt-bindings/gpio/meson-g12a-gpio.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
+ * Author: Xingyu Chen <xingyu.chen@amlogic.com>
+ */
+
+#ifndef _DT_BINDINGS_MESON_G12A_GPIO_H
+#define _DT_BINDINGS_MESON_G12A_GPIO_H
+
+/* First GPIO chip */
+#define GPIOAO_0 0
+#define GPIOAO_1 1
+#define GPIOAO_2 2
+#define GPIOAO_3 3
+#define GPIOAO_4 4
+#define GPIOAO_5 5
+#define GPIOAO_6 6
+#define GPIOAO_7 7
+#define GPIOAO_8 8
+#define GPIOAO_9 9
+#define GPIOAO_10 10
+#define GPIOAO_11 11
+#define GPIOE_0 12
+#define GPIOE_1 13
+#define GPIOE_2 14
+
+/* Second GPIO chip */
+#define GPIOZ_0 0
+#define GPIOZ_1 1
+#define GPIOZ_2 2
+#define GPIOZ_3 3
+#define GPIOZ_4 4
+#define GPIOZ_5 5
+#define GPIOZ_6 6
+#define GPIOZ_7 7
+#define GPIOZ_8 8
+#define GPIOZ_9 9
+#define GPIOZ_10 10
+#define GPIOZ_11 11
+#define GPIOZ_12 12
+#define GPIOZ_13 13
+#define GPIOZ_14 14
+#define GPIOZ_15 15
+#define GPIOH_0 16
+#define GPIOH_1 17
+#define GPIOH_2 18
+#define GPIOH_3 19
+#define GPIOH_4 20
+#define GPIOH_5 21
+#define GPIOH_6 22
+#define GPIOH_7 23
+#define GPIOH_8 24
+#define BOOT_0 25
+#define BOOT_1 26
+#define BOOT_2 27
+#define BOOT_3 28
+#define BOOT_4 29
+#define BOOT_5 30
+#define BOOT_6 31
+#define BOOT_7 32
+#define BOOT_8 33
+#define BOOT_9 34
+#define BOOT_10 35
+#define BOOT_11 36
+#define BOOT_12 37
+#define BOOT_13 38
+#define BOOT_14 39
+#define BOOT_15 40
+#define GPIOC_0 41
+#define GPIOC_1 42
+#define GPIOC_2 43
+#define GPIOC_3 44
+#define GPIOC_4 45
+#define GPIOC_5 46
+#define GPIOC_6 47
+#define GPIOC_7 48
+#define GPIOA_0 49
+#define GPIOA_1 50
+#define GPIOA_2 51
+#define GPIOA_3 52
+#define GPIOA_4 53
+#define GPIOA_5 54
+#define GPIOA_6 55
+#define GPIOA_7 56
+#define GPIOA_8 57
+#define GPIOA_9 58
+#define GPIOA_10 59
+#define GPIOA_11 60
+#define GPIOA_12 61
+#define GPIOA_13 62
+#define GPIOA_14 63
+#define GPIOA_15 64
+#define GPIOX_0 65
+#define GPIOX_1 66
+#define GPIOX_2 67
+#define GPIOX_3 68
+#define GPIOX_4 69
+#define GPIOX_5 70
+#define GPIOX_6 71
+#define GPIOX_7 72
+#define GPIOX_8 73
+#define GPIOX_9 74
+#define GPIOX_10 75
+#define GPIOX_11 76
+#define GPIOX_12 77
+#define GPIOX_13 78
+#define GPIOX_14 79
+#define GPIOX_15 80
+#define GPIOX_16 81
+#define GPIOX_17 82
+#define GPIOX_18 83
+#define GPIOX_19 84
+
+#endif /* _DT_BINDINGS_MESON_G12A_GPIO_H */
diff --git a/include/dt-bindings/reset/amlogic,meson-g12a-reset.h b/include/dt-bindings/reset/amlogic,meson-g12a-reset.h
new file mode 100644
index 0000000..8063e83
--- /dev/null
+++ b/include/dt-bindings/reset/amlogic,meson-g12a-reset.h
@@ -0,0 +1,134 @@
+/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
+/*
+ * Copyright (c) 2019 BayLibre, SAS.
+ * Author: Jerome Brunet <jbrunet@baylibre.com>
+ *
+ */
+
+#ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H
+#define _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H
+
+/* RESET0 */
+#define RESET_HIU 0
+/* 1 */
+#define RESET_DOS 2
+/* 3-4 */
+#define RESET_VIU 5
+#define RESET_AFIFO 6
+#define RESET_VID_PLL_DIV 7
+/* 8-9 */
+#define RESET_VENC 10
+#define RESET_ASSIST 11
+#define RESET_PCIE_CTRL_A 12
+#define RESET_VCBUS 13
+#define RESET_PCIE_PHY 14
+#define RESET_PCIE_APB 15
+#define RESET_GIC 16
+#define RESET_CAPB3_DECODE 17
+/* 18 */
+#define RESET_HDMITX_CAPB3 19
+#define RESET_DVALIN_CAPB3 20
+#define RESET_DOS_CAPB3 21
+/* 22 */
+#define RESET_CBUS_CAPB3 23
+#define RESET_AHB_CNTL 24
+#define RESET_AHB_DATA 25
+#define RESET_VCBUS_CLK81 26
+/* 27-31 */
+/* RESET1 */
+/* 32 */
+#define RESET_DEMUX 33
+#define RESET_USB 34
+#define RESET_DDR 35
+/* 36 */
+#define RESET_BT656 37
+#define RESET_AHB_SRAM 38
+/* 39 */
+#define RESET_PARSER 40
+/* 41 */
+#define RESET_ISA 42
+#define RESET_ETHERNET 43
+#define RESET_SD_EMMC_A 44
+#define RESET_SD_EMMC_B 45
+#define RESET_SD_EMMC_C 46
+/* 47-60 */
+#define RESET_AUDIO_CODEC 61
+/* 62-63 */
+/* RESET2 */
+/* 64 */
+#define RESET_AUDIO 65
+#define RESET_HDMITX_PHY 66
+/* 67 */
+#define RESET_MIPI_DSI_HOST 68
+#define RESET_ALOCKER 69
+#define RESET_GE2D 70
+#define RESET_PARSER_REG 71
+#define RESET_PARSER_FETCH 72
+#define RESET_CTL 73
+#define RESET_PARSER_TOP 74
+/* 75-77 */
+#define RESET_DVALIN 78
+#define RESET_HDMITX 79
+/* 80-95 */
+/* RESET3 */
+/* 96-95 */
+#define RESET_DEMUX_TOP 105
+#define RESET_DEMUX_DES_PL 106
+#define RESET_DEMUX_S2P_0 107
+#define RESET_DEMUX_S2P_1 108
+#define RESET_DEMUX_0 109
+#define RESET_DEMUX_1 110
+#define RESET_DEMUX_2 111
+/* 112-127 */
+/* RESET4 */
+/* 128-129 */
+#define RESET_MIPI_DSI_PHY 130
+/* 131-132 */
+#define RESET_RDMA 133
+#define RESET_VENCI 134
+#define RESET_VENCP 135
+/* 136 */
+#define RESET_VDAC 137
+/* 138-139 */
+#define RESET_VDI6 140
+#define RESET_VENCL 141
+#define RESET_I2C_M1 142
+#define RESET_I2C_M2 143
+/* 144-159 */
+/* RESET5 */
+/* 160-191 */
+/* RESET6 */
+#define RESET_GEN 192
+#define RESET_SPICC0 193
+#define RESET_SC 194
+#define RESET_SANA_3 195
+#define RESET_I2C_M0 196
+#define RESET_TS_PLL 197
+#define RESET_SPICC1 198
+#define RESET_STREAM 199
+#define RESET_TS_CPU 200
+#define RESET_UART0 201
+#define RESET_UART1_2 202
+#define RESET_ASYNC0 203
+#define RESET_ASYNC1 204
+#define RESET_SPIFC0 205
+#define RESET_I2C_M3 206
+/* 207-223 */
+/* RESET7 */
+#define RESET_USB_DDR_0 224
+#define RESET_USB_DDR_1 225
+#define RESET_USB_DDR_2 226
+#define RESET_USB_DDR_3 227
+#define RESET_TS_GPU 228
+#define RESET_DEVICE_MMC_ARB 229
+#define RESET_DVALIN_DMC_PIPL 230
+#define RESET_VID_LOCK 231
+#define RESET_NIC_DMC_PIPL 232
+#define RESET_DMC_VPU_PIPL 233
+#define RESET_GE2D_DMC_PIPL 234
+#define RESET_HCODEC_DMC_PIPL 235
+#define RESET_WAVE420_DMC_PIPL 236
+#define RESET_HEVCF_DMC_PIPL 237
+/* 238-255 */
+
+#endif
diff --git a/include/dt-bindings/reset/g12a-aoclkc.h b/include/dt-bindings/reset/g12a-aoclkc.h
new file mode 100644
index 0000000..bd2e233
--- /dev/null
+++ b/include/dt-bindings/reset/g12a-aoclkc.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (c) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_G12A_AOCLK
+#define DT_BINDINGS_RESET_AMLOGIC_MESON_G12A_AOCLK
+
+#define RESET_AO_IR_IN 0
+#define RESET_AO_UART 1
+#define RESET_AO_I2C_M 2
+#define RESET_AO_I2C_S 3
+#define RESET_AO_SAR_ADC 4
+#define RESET_AO_UART2 5
+#define RESET_AO_IR_OUT 6
+
+#endif
diff --git a/include/exception.h b/include/exception.h
new file mode 100644
index 0000000..fc02490
--- /dev/null
+++ b/include/exception.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * The 'exception' command can be used for testing exception handling.
+ *
+ * Copyright (c) 2018, Heinrich Schuchardt <xypron.glpk@gmx.de>
+ */
+
+static int do_exception(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ cmd_tbl_t *cp;
+
+ if (argc != 2)
+ return CMD_RET_USAGE;
+
+ /* drop sub-command parameter */
+ argc--;
+ argv++;
+
+ cp = find_cmd_tbl(argv[0], cmd_sub, ARRAY_SIZE(cmd_sub));
+
+ if (cp)
+ return cp->cmd(cmdtp, flag, argc, argv);
+
+ return CMD_RET_USAGE;
+}
+
+static int exception_complete(int argc, char * const argv[], char last_char,
+ int maxv, char *cmdv[])
+{
+ int len = 0;
+ int i = 0;
+ cmd_tbl_t *cmdtp;
+
+ switch (argc) {
+ case 1:
+ break;
+ case 2:
+ len = strlen(argv[1]);
+ break;
+ default:
+ return 0;
+ }
+ for (cmdtp = cmd_sub; cmdtp != cmd_sub + ARRAY_SIZE(cmd_sub); cmdtp++) {
+ if (i >= maxv - 1)
+ return i;
+ if (!strncmp(argv[1], cmdtp->name, len))
+ cmdv[i++] = cmdtp->name;
+ }
+ cmdv[i] = NULL;
+ return i;
+}
+
+U_BOOT_CMD_COMPLETE(
+ exception, 2, 0, do_exception,
+ "Forces an exception to occur",
+ exception_help_text, exception_complete
+);
diff --git a/include/image.h b/include/image.h
index 765ffec..889305c 100644
--- a/include/image.h
+++ b/include/image.h
@@ -306,6 +306,7 @@
IH_COMP_COUNT,
};
+#define LZ4F_MAGIC 0x184D2204 /* LZ4 Magic Number */
#define IH_MAGIC 0x27051956 /* Image Magic Number */
#define IH_NMLEN 32 /* Image Name Length */
@@ -1312,6 +1313,7 @@
ulong *second_data, ulong *second_len);
ulong android_image_get_end(const struct andr_img_hdr *hdr);
ulong android_image_get_kload(const struct andr_img_hdr *hdr);
+ulong android_image_get_kcomp(const struct andr_img_hdr *hdr);
void android_print_contents(const struct andr_img_hdr *hdr);
#endif /* CONFIG_ANDROID_BOOT_IMAGE */
diff --git a/include/linux/completion.h b/include/linux/completion.h
new file mode 100644
index 0000000..9835826
--- /dev/null
+++ b/include/linux/completion.h
@@ -0,0 +1,173 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __LINUX_COMPLETION_H
+#define __LINUX_COMPLETION_H
+
+/*
+ * (C) Copyright 2001 Linus Torvalds
+ *
+ * Atomic wait-for-completion handler data structures.
+ * See kernel/sched/completion.c for details.
+ */
+#ifndef __UBOOT__
+#include <linux/wait.h>
+#endif /* __UBOOT__ */
+
+/*
+ * struct completion - structure used to maintain state for a "completion"
+ *
+ * This is the opaque structure used to maintain the state for a "completion".
+ * Completions currently use a FIFO to queue threads that have to wait for
+ * the "completion" event.
+ *
+ * See also: complete(), wait_for_completion() (and friends _timeout,
+ * _interruptible, _interruptible_timeout, and _killable), init_completion(),
+ * reinit_completion(), and macros DECLARE_COMPLETION(),
+ * DECLARE_COMPLETION_ONSTACK().
+ */
+struct completion {
+ unsigned int done;
+#ifndef __UBOOT__
+ wait_queue_head_t wait;
+#endif /* __UBOOT__ */
+};
+
+#define init_completion_map(x, m) __init_completion(x)
+#define init_completion(x) __init_completion(x)
+static inline void complete_acquire(struct completion *x) {}
+static inline void complete_release(struct completion *x) {}
+
+#define COMPLETION_INITIALIZER(work) \
+ { 0, __WAIT_QUEUE_HEAD_INITIALIZER((work).wait) }
+
+#define COMPLETION_INITIALIZER_ONSTACK_MAP(work, map) \
+ (*({ init_completion_map(&(work), &(map)); &(work); }))
+
+#define COMPLETION_INITIALIZER_ONSTACK(work) \
+ (*({ init_completion(&work); &work; }))
+
+/**
+ * DECLARE_COMPLETION - declare and initialize a completion structure
+ * @work: identifier for the completion structure
+ *
+ * This macro declares and initializes a completion structure. Generally used
+ * for static declarations. You should use the _ONSTACK variant for automatic
+ * variables.
+ */
+#define DECLARE_COMPLETION(work) \
+ struct completion work = COMPLETION_INITIALIZER(work)
+
+/*
+ * Lockdep needs to run a non-constant initializer for on-stack
+ * completions - so we use the _ONSTACK() variant for those that
+ * are on the kernel stack:
+ */
+/**
+ * DECLARE_COMPLETION_ONSTACK - declare and initialize a completion structure
+ * @work: identifier for the completion structure
+ *
+ * This macro declares and initializes a completion structure on the kernel
+ * stack.
+ */
+#ifdef CONFIG_LOCKDEP
+# define DECLARE_COMPLETION_ONSTACK(work) \
+ struct completion work = COMPLETION_INITIALIZER_ONSTACK(work)
+# define DECLARE_COMPLETION_ONSTACK_MAP(work, map) \
+ struct completion work = COMPLETION_INITIALIZER_ONSTACK_MAP(work, map)
+#else
+# define DECLARE_COMPLETION_ONSTACK(work) DECLARE_COMPLETION(work)
+# define DECLARE_COMPLETION_ONSTACK_MAP(work, map) DECLARE_COMPLETION(work)
+#endif
+
+/**
+ * init_completion - Initialize a dynamically allocated completion
+ * @x: pointer to completion structure that is to be initialized
+ *
+ * This inline function will initialize a dynamically created completion
+ * structure.
+ */
+static inline void __init_completion(struct completion *x)
+{
+ x->done = 0;
+#ifndef __UBOOT__
+ init_waitqueue_head(&x->wait);
+#endif /* __UBOOT__ */
+}
+
+/**
+ * reinit_completion - reinitialize a completion structure
+ * @x: pointer to completion structure that is to be reinitialized
+ *
+ * This inline function should be used to reinitialize a completion structure so it can
+ * be reused. This is especially important after complete_all() is used.
+ */
+static inline void reinit_completion(struct completion *x)
+{
+ x->done = 0;
+}
+
+#ifndef __UBOOT__
+extern void wait_for_completion(struct completion *);
+extern void wait_for_completion_io(struct completion *);
+extern int wait_for_completion_interruptible(struct completion *x);
+extern int wait_for_completion_killable(struct completion *x);
+extern unsigned long wait_for_completion_timeout(struct completion *x,
+ unsigned long timeout);
+extern unsigned long wait_for_completion_io_timeout(struct completion *x,
+ unsigned long timeout);
+extern long wait_for_completion_interruptible_timeout(
+ struct completion *x, unsigned long timeout);
+extern long wait_for_completion_killable_timeout(
+ struct completion *x, unsigned long timeout);
+extern bool try_wait_for_completion(struct completion *x);
+extern bool completion_done(struct completion *x);
+
+extern void complete(struct completion *);
+extern void complete_all(struct completion *);
+
+#else /* __UBOOT __ */
+
+#define wait_for_completion(x) do {} while (0)
+#define wait_for_completion_io(x) do {} while (0)
+
+inline int wait_for_completion_interruptible(struct completion *x)
+{
+ return 1;
+}
+inline int wait_for_completion_killable(struct completion *x)
+{
+ return 1;
+}
+inline unsigned long wait_for_completion_timeout(struct completion *x,
+ unsigned long timeout)
+{
+ return 1;
+}
+inline unsigned long wait_for_completion_io_timeout(struct completion *x,
+ unsigned long timeout)
+{
+ return 1;
+}
+inline long wait_for_completion_interruptible_timeout(struct completion *x,
+ unsigned long timeout)
+{
+ return 1;
+}
+inline long wait_for_completion_killable_timeout(struct completion *x,
+ unsigned long timeout)
+{
+ return 1;
+}
+inline bool try_wait_for_completion(struct completion *x)
+{
+ return 1;
+}
+inline bool completion_done(struct completion *x)
+{
+ return 1;
+}
+
+#define complete(x) do {} while (0)
+#define complete_all(x) do {} while (0)
+#endif /* __UBOOT__ */
+
+#endif
diff --git a/include/linux/io.h b/include/linux/io.h
index 9badab4..7984788 100644
--- a/include/linux/io.h
+++ b/include/linux/io.h
@@ -65,8 +65,8 @@
static inline void iounmap(void __iomem *addr)
{
}
+#endif
#define devm_ioremap(dev, offset, size) ioremap(offset, size)
-#endif
#endif /* _LINUX_IO_H */
diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
index 9f5dc81..bd373b9 100644
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
@@ -15,6 +15,7 @@
#include <config.h>
+#include <dm/device.h>
#include <linux/compat.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/flashchip.h>
@@ -498,6 +499,13 @@
struct nand_chip *active;
};
+static inline void nand_hw_control_init(struct nand_hw_control *nfc)
+{
+ nfc->active = NULL;
+ spin_lock_init(&nfc->lock);
+ init_waitqueue_head(&nfc->wq);
+}
+
/**
* struct nand_ecc_step_info - ECC step information of ECC engine
* @stepsize: data bytes per ECC step
@@ -961,6 +969,17 @@
void *priv;
};
+static inline void nand_set_flash_node(struct nand_chip *chip,
+ ofnode node)
+{
+ chip->flash_node = ofnode_to_offset(node);
+}
+
+static inline ofnode nand_get_flash_node(struct nand_chip *chip)
+{
+ return offset_to_ofnode(chip->flash_node);
+}
+
static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
{
return container_of(mtd, struct nand_chip, mtd);
@@ -1280,4 +1299,34 @@
/* Reset and initialize a NAND device */
int nand_reset(struct nand_chip *chip, int chipnr);
+
+/* NAND operation helpers */
+int nand_reset_op(struct nand_chip *chip);
+int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf,
+ unsigned int len);
+int nand_status_op(struct nand_chip *chip, u8 *status);
+int nand_exit_status_op(struct nand_chip *chip);
+int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock);
+int nand_read_page_op(struct nand_chip *chip, unsigned int page,
+ unsigned int offset_in_page, void *buf, unsigned int len);
+int nand_change_read_column_op(struct nand_chip *chip,
+ unsigned int offset_in_page, void *buf,
+ unsigned int len, bool force_8bit);
+int nand_read_oob_op(struct nand_chip *chip, unsigned int page,
+ unsigned int offset_in_page, void *buf, unsigned int len);
+int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page,
+ unsigned int offset_in_page, const void *buf,
+ unsigned int len);
+int nand_prog_page_end_op(struct nand_chip *chip);
+int nand_prog_page_op(struct nand_chip *chip, unsigned int page,
+ unsigned int offset_in_page, const void *buf,
+ unsigned int len);
+int nand_change_write_column_op(struct nand_chip *chip,
+ unsigned int offset_in_page, const void *buf,
+ unsigned int len, bool force_8bit);
+int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len,
+ bool force_8bit);
+int nand_write_data_op(struct nand_chip *chip, const void *buf,
+ unsigned int len, bool force_8bit);
+
#endif /* __LINUX_MTD_RAWNAND_H */
diff --git a/include/malloc.h b/include/malloc.h
index b714fed..5efa692 100644
--- a/include/malloc.h
+++ b/include/malloc.h
@@ -878,7 +878,6 @@
#define memalign memalign_simple
static inline void free(void *ptr) {}
void *calloc(size_t nmemb, size_t size);
-void *memalign_simple(size_t alignment, size_t bytes);
void *realloc_simple(void *ptr, size_t size);
void malloc_simple_info(void);
#else
@@ -914,6 +913,7 @@
/* Simple versions which can be used when space is tight */
void *malloc_simple(size_t size);
+void *memalign_simple(size_t alignment, size_t bytes);
#pragma GCC visibility push(hidden)
# if __STD_C
diff --git a/include/pci.h b/include/pci.h
index 5fb212c..9668503 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -545,7 +545,11 @@
extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,
struct pci_config_table *);
-#define MAX_PCI_REGIONS 7
+#ifdef CONFIG_NR_DRAM_BANKS
+#define MAX_PCI_REGIONS (CONFIG_NR_DRAM_BANKS + 7)
+#else
+#define MAX_PCI_REGIONS 7
+#endif
#define INDIRECT_TYPE_NO_PCIE_LINK 1
diff --git a/include/regmap.h b/include/regmap.h
index 8359c51..3cd7a66 100644
--- a/include/regmap.h
+++ b/include/regmap.h
@@ -274,7 +274,7 @@
if (cond) \
break; \
if (IS_ENABLED(CONFIG_SANDBOX) && test_add_time) \
- sandbox_timer_add_offset(test_add_time); \
+ timer_test_add_offset(test_add_time); \
if ((timeout_ms) && get_timer(__start) > (timeout_ms)) { \
__ret = regmap_read((map), (addr), &(val)); \
break; \
diff --git a/include/reset.h b/include/reset.h
index 65aa7a4..a1a9ad5 100644
--- a/include/reset.h
+++ b/include/reset.h
@@ -43,6 +43,8 @@
* @data: An optional data field for scenarios where a single integer ID is not
* sufficient. If used, it can be populated through an .of_xlate op and
* processed during the various reset ops.
+ * @polarity: An optional polarity field for drivers that support
+ * different reset polarities.
*
* Should additional information to identify and configure any reset signal
* for any provider be required in the future, the struct could be expanded to
@@ -59,6 +61,7 @@
*/
unsigned long id;
unsigned long data;
+ unsigned long polarity;
};
/**
diff --git a/include/time.h b/include/time.h
index 825991e..9fd0d73 100644
--- a/include/time.h
+++ b/include/time.h
@@ -14,6 +14,14 @@
unsigned long timer_get_us(void);
/*
+ * timer_test_add_offset()
+ *
+ * Allow tests to add to the time reported through lib/time.c functions
+ * offset: number of milliseconds to advance the system time
+ */
+void timer_test_add_offset(unsigned long offset);
+
+/*
* These inlines deal with timer wrapping correctly. You are
* strongly encouraged to use them
* 1. Because people otherwise forget
diff --git a/include/usb/dwc2_udc.h b/include/usb/dwc2_udc.h
index 4068de0..a6c1221 100644
--- a/include/usb/dwc2_udc.h
+++ b/include/usb/dwc2_udc.h
@@ -9,6 +9,7 @@
#define __DWC2_USB_GADGET
#define PHY0_SLEEP (1 << 5)
+#define DWC2_MAX_HW_ENDPOINTS 16
struct dwc2_plat_otg_data {
void *priv;
@@ -22,8 +23,14 @@
unsigned int rx_fifo_sz;
unsigned int np_tx_fifo_sz;
unsigned int tx_fifo_sz;
+ unsigned int tx_fifo_sz_array[DWC2_MAX_HW_ENDPOINTS];
+ unsigned char tx_fifo_sz_nb;
+ bool force_b_session_valid;
+ bool activate_stm_id_vb_detection;
};
int dwc2_udc_probe(struct dwc2_plat_otg_data *pdata);
+int dwc2_udc_B_session_valid(struct udevice *dev);
+
#endif /* __DWC2_USB_GADGET */
diff --git a/lib/lz4_wrapper.c b/lib/lz4_wrapper.c
index 487d39e..1c68e67 100644
--- a/lib/lz4_wrapper.c
+++ b/lib/lz4_wrapper.c
@@ -5,6 +5,7 @@
#include <common.h>
#include <compiler.h>
+#include <image.h>
#include <linux/kernel.h>
#include <linux/types.h>
@@ -23,8 +24,6 @@
/* Unaltered (except removing unrelated code) from github.com/Cyan4973/lz4. */
#include "lz4.c" /* #include for inlining, do not link! */
-#define LZ4F_MAGIC 0x184D2204
-
struct lz4_frame_header {
u32 magic;
union {
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 5092c3f..421362d 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -4537,7 +4537,6 @@
CONFIG_USB_INVENTRA_DMA
CONFIG_USB_ISP1301_I2C_ADDR
CONFIG_USB_MAX_CONTROLLER_COUNT
-CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
CONFIG_USB_MUSB_TIMEOUT
CONFIG_USB_MUSB_TUSB6010
CONFIG_USB_OHCI_EP93XX
diff --git a/test/env/Kconfig b/test/env/Kconfig
index ff16413..6cb8233 100644
--- a/test/env/Kconfig
+++ b/test/env/Kconfig
@@ -1,6 +1,7 @@
config UT_ENV
bool "Enable env unit tests"
depends on UNIT_TEST
+ default y
help
This enables the 'ut env' command which runs a series of unit
tests on the env code.
diff --git a/test/lib/hexdump.c b/test/lib/hexdump.c
index 567b576..5dccf43 100644
--- a/test/lib/hexdump.c
+++ b/test/lib/hexdump.c
@@ -6,7 +6,8 @@
#include <common.h>
#include <hexdump.h>
-#include <dm/test.h>
+#include <test/lib.h>
+#include <test/test.h>
#include <test/ut.h>
static int lib_test_hex_to_bin(struct unit_test_state *uts)
@@ -32,7 +33,7 @@
return 0;
}
-DM_TEST(lib_test_hex_to_bin, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+LIB_TEST(lib_test_hex_to_bin, 0);
static int lib_test_hex2bin(struct unit_test_state *uts)
{
@@ -62,7 +63,7 @@
return 0;
}
-DM_TEST(lib_test_hex2bin, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+LIB_TEST(lib_test_hex2bin, 0);
static int lib_test_bin2hex(struct unit_test_state *uts)
{
@@ -92,4 +93,4 @@
return 0;
}
-DM_TEST(lib_test_bin2hex, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+LIB_TEST(lib_test_bin2hex, 0);