commit d7696a55b9a616d86ea8bccb208833c65519be51
author Soren Brinkmann <soren.brinkmann@xilinx.com> Thu Sep 29 11:44:41 2016 -0700
committer Michal Simek <michal.simek@xilinx.com> Tue Nov 15 15:28:05 2016 +0100
tree e8f1197d4d81af1511dd360fa04bf5aa1ec8fac2
parent 82c970208df423778986f2762fc17cf3a7cfee25

ARM64: zynqmp: Adjust to new SMC interface to get silicon version

The new FW interface returns the IDCODE and version register, leaving
extracting bitfields to the caller.

Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

board/xilinx/zynqmp/zynqmp.c

diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index ba4dfbb..b0acaa5 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -86,6 +86,17 @@
 
 	smc_call(&regs);
 
+	/*
+	 * SMC returns:
+	 * regs[0][31:0]  = status of the operation
+	 * regs[0][63:32] = CSU.IDCODE register
+	 * regs[1][31:0]  = CSU.version register
+	 */
+	regs.regs[0] = upper_32_bits(regs.regs[0]);
+	regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
+			ZYNQMP_CSU_IDCODE_SVD_MASK;
+	regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
+
 	return regs.regs[0];
 }
 

include/zynqmppl.h

diff --git a/include/zynqmppl.h b/include/zynqmppl.h
index 542ace9..fb5200e 100644
--- a/include/zynqmppl.h
+++ b/include/zynqmppl.h
@@ -16,6 +16,12 @@
 #define ZYNQMP_FPGA_OP_LOAD			(1 << 1)
 #define ZYNQMP_FPGA_OP_DONE			(1 << 2)
 
+#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT	15
+#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK	(0xf << \
+					ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT)
+#define ZYNQMP_CSU_IDCODE_SVD_SHIFT	12
+#define ZYNQMP_CSU_IDCODE_SVD_MASK	(0xe << ZYNQMP_CSU_IDCODE_SVD_SHIFT)
+
 extern struct xilinx_fpga_op zynqmp_op;
 
 #define XILINX_ZYNQMP_DESC \