Merge git://git.denx.de/u-boot-mpc85xx
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index 28bf778..f94568a 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -28,6 +28,12 @@
int "Maximum DDR controllers"
default 1
+config SECURE_BOOT
+ bool "Secure Boot"
+ help
+ Enable Freescale Secure Boot feature. Normally selected
+ by defconfig. If unsure, do not change.
+
config SYS_FSL_ERRATUM_A010315
bool "Workaround for PCIe erratum A010315"
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 94ec8d5..ed1c4ee 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -71,6 +71,11 @@
default 3 if ARCH_LS2080A
default 1
+config SECURE_BOOT
+ bool
+ help
+ Enable Freescale Secure Boot feature
+
config SYS_FSL_IFC_BANK_COUNT
int "Maximum banks of Integrated flash controller"
depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 6c3ba49..c50894a 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -138,7 +138,6 @@
#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000
#define CONFIG_SYS_FSL_CCSR_SCFG_BE
#define CONFIG_SYS_FSL_ESDHC_BE
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index d88543d..d684a07 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -120,7 +120,7 @@
#endif
#ifndef CONFIG_SYS_CCSRBAR
-#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
+#define CONFIG_SYS_CCSRBAR 0x01000000
#endif
#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
@@ -128,7 +128,7 @@
#endif
#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW 0x01000000
#endif
#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 3ee7d2f..e4873f5 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -309,125 +309,179 @@
bool "Support uCP1020"
select ARCH_P1020
-config TARGET_CYRUS
- bool "Support Varisys Cyrus"
+config TARGET_CYRUS_P5020
+ bool "Support Varisys Cyrus P5020"
+ select ARCH_P5020
select PHYS_64BIT
+config TARGET_CYRUS_P5040
+ bool "Support Varisys Cyrus P5040"
+ select ARCH_P5040
+ select PHYS_64BIT
+
endchoice
config ARCH_B4420
bool
+ select FSL_LAW
config ARCH_B4860
bool
+ select FSL_LAW
config ARCH_BSC9131
bool
+ select FSL_LAW
config ARCH_BSC9132
bool
+ select FSL_LAW
config ARCH_C29X
bool
+ select FSL_LAW
config ARCH_MPC8536
bool
+ select FSL_LAW
config ARCH_MPC8540
bool
+ select FSL_LAW
config ARCH_MPC8541
bool
+ select FSL_LAW
config ARCH_MPC8544
bool
+ select FSL_LAW
config ARCH_MPC8548
bool
+ select FSL_LAW
config ARCH_MPC8555
bool
+ select FSL_LAW
config ARCH_MPC8560
bool
+ select FSL_LAW
config ARCH_MPC8568
bool
+ select FSL_LAW
config ARCH_MPC8569
bool
+ select FSL_LAW
config ARCH_MPC8572
bool
+ select FSL_LAW
config ARCH_P1010
bool
+ select FSL_LAW
config ARCH_P1011
bool
+ select FSL_LAW
config ARCH_P1020
bool
+ select FSL_LAW
config ARCH_P1021
bool
+ select FSL_LAW
config ARCH_P1022
bool
+ select FSL_LAW
config ARCH_P1023
bool
+ select FSL_LAW
config ARCH_P1024
bool
+ select FSL_LAW
config ARCH_P1025
bool
+ select FSL_LAW
config ARCH_P2020
bool
+ select FSL_LAW
config ARCH_P2041
bool
+ select FSL_LAW
config ARCH_P3041
bool
+ select FSL_LAW
config ARCH_P4080
bool
+ select FSL_LAW
config ARCH_P5020
bool
+ select FSL_LAW
config ARCH_P5040
bool
+ select FSL_LAW
config ARCH_QEMU_E500
bool
config ARCH_T1023
bool
+ select FSL_LAW
config ARCH_T1024
bool
+ select FSL_LAW
config ARCH_T1040
bool
+ select FSL_LAW
config ARCH_T1042
bool
+ select FSL_LAW
config ARCH_T2080
bool
+ select FSL_LAW
config ARCH_T2081
bool
+ select FSL_LAW
config ARCH_T4160
bool
+ select FSL_LAW
config ARCH_T4240
bool
+ select FSL_LAW
+
+config FSL_LAW
+ bool
+ help
+ Use Freescale common code for Local Access Window
+
+config SECURE_BOOT
+ bool "Secure Boot"
+ help
+ Enable Freescale Secure Boot feature. Normally selected
+ by defconfig. If unsure, do not change.
config MAX_CPUS
int "Maximum number of CPUs permitted for MPC85xx"
@@ -465,6 +519,104 @@
cores, count the reserved ports. This will allocate enough memory
in spin table to properly handle all cores.
+config SYS_CCSRBAR_DEFAULT
+ hex "Default CCSRBAR address"
+ default 0xff700000 if ARCH_BSC9131 || \
+ ARCH_BSC9132 || \
+ ARCH_C29X || \
+ ARCH_MPC8536 || \
+ ARCH_MPC8540 || \
+ ARCH_MPC8541 || \
+ ARCH_MPC8544 || \
+ ARCH_MPC8548 || \
+ ARCH_MPC8555 || \
+ ARCH_MPC8560 || \
+ ARCH_MPC8568 || \
+ ARCH_MPC8569 || \
+ ARCH_MPC8572 || \
+ ARCH_P1010 || \
+ ARCH_P1011 || \
+ ARCH_P1020 || \
+ ARCH_P1021 || \
+ ARCH_P1022 || \
+ ARCH_P1024 || \
+ ARCH_P1025 || \
+ ARCH_P2020
+ default 0xff600000 if ARCH_P1023
+ default 0xfe000000 if ARCH_B4420 || \
+ ARCH_B4860 || \
+ ARCH_P2041 || \
+ ARCH_P3041 || \
+ ARCH_P4080 || \
+ ARCH_P5020 || \
+ ARCH_P5040 || \
+ ARCH_T1013 || \
+ ARCH_T1014 || \
+ ARCH_T1020 || \
+ ARCH_T1022 || \
+ ARCH_T1023 || \
+ ARCH_T1024 || \
+ ARCH_T1040 || \
+ ARCH_T1042 || \
+ ARCH_T2080 || \
+ ARCH_T2081 || \
+ ARCH_T4160 || \
+ ARCH_T4240
+ default 0xe0000000 if ARCH_QEMU_E500
+ help
+ Default value of CCSRBAR comes from power-on-reset. It
+ is fixed on each SoC. Some SoCs can have different value
+ if changed by pre-boot regime. The value here must match
+ the current value in SoC. If not sure, do not change.
+
+config SYS_FSL_NUM_LAWS
+ int "Number of local access windows"
+ depends on FSL_LAW
+ default 32 if ARCH_B4420 || \
+ ARCH_B4860 || \
+ ARCH_P2041 || \
+ ARCH_P3041 || \
+ ARCH_P4080 || \
+ ARCH_P5020 || \
+ ARCH_P5040 || \
+ ARCH_T2080 || \
+ ARCH_T2081 || \
+ ARCH_T4160 || \
+ ARCH_T4240
+ default 16 if ARCH_T1013 || \
+ ARCH_T1014 || \
+ ARCH_T1020 || \
+ ARCH_T1022 || \
+ ARCH_T1023 || \
+ ARCH_T1024 || \
+ ARCH_T1040 || \
+ ARCH_T1042
+ default 12 if ARCH_BSC9131 || \
+ ARCH_BSC9132 || \
+ ARCH_C29X || \
+ ARCH_MPC8536 || \
+ ARCH_MPC8572 || \
+ ARCH_P1010 || \
+ ARCH_P1011 || \
+ ARCH_P1020 || \
+ ARCH_P1021 || \
+ ARCH_P1022 || \
+ ARCH_P1023 || \
+ ARCH_P1024 || \
+ ARCH_P1025 || \
+ ARCH_P2020
+ default 10 if ARCH_MPC8544 || \
+ ARCH_MPC8548 || \
+ ARCH_MPC8568 || \
+ ARCH_MPC8569
+ default 8 if ARCH_MPC8540 || \
+ ARCH_MPC8541 || \
+ ARCH_MPC8555 || \
+ ARCH_MPC8560
+ help
+ Number of local access windows. This is fixed per SoC.
+ If not sure, do not change.
+
source "board/freescale/b4860qds/Kconfig"
source "board/freescale/bsc9131rdb/Kconfig"
source "board/freescale/bsc9132qds/Kconfig"
diff --git a/arch/powerpc/cpu/mpc86xx/Kconfig b/arch/powerpc/cpu/mpc86xx/Kconfig
index 98fb702..11afffa 100644
--- a/arch/powerpc/cpu/mpc86xx/Kconfig
+++ b/arch/powerpc/cpu/mpc86xx/Kconfig
@@ -28,9 +28,31 @@
config ARCH_MPC8610
bool
+ select FSL_LAW
config ARCH_MPC8641
bool
+ select FSL_LAW
+
+config FSL_LAW
+ bool
+ help
+ Use Freescale common code for Local Access Window
+
+config SYS_CCSRBAR_DEFAULT
+ hex "Default CCSRBAR address"
+ default 0xff700000 if ARCH_MPC8610 || ARCH_MPC8641
+ help
+ Default value of CCSRBAR comes from power-on-reset. It
+ is fixed on each SoC. Some SoCs can have different value
+ if changed by pre-boot regime. The value here must match
+ the current value in SoC. If not sure, do not change.
+config SYS_FSL_NUM_LAWS
+ int "Number of local access windows"
+ default 10 if ARCH_MPC8610 || ARCH_MPC8641
+ help
+ Number of local access windows. This is fixed per SoC.
+ If not sure, do not change.
source "board/freescale/mpc8610hpcd/Kconfig"
source "board/freescale/mpc8641hpcn/Kconfig"
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index c92bc1e..4877b75 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -9,10 +9,6 @@
/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
-#ifdef CONFIG_SYS_CCSRBAR_DEFAULT
-#error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
-#endif
-
/*
* This macro should be removed when we no longer care about backwards
* compatibility with older operating systems.
@@ -36,38 +32,28 @@
#endif
#if defined(CONFIG_ARCH_MPC8536)
-#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_MPC8540)
-#define CONFIG_SYS_FSL_NUM_LAWS 8
#define CONFIG_SYS_FSL_DDRC_GEN1
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#elif defined(CONFIG_ARCH_MPC8541)
-#define CONFIG_SYS_FSL_NUM_LAWS 8
#define CONFIG_SYS_FSL_DDRC_GEN1
#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#elif defined(CONFIG_ARCH_MPC8544)
-#define CONFIG_SYS_FSL_NUM_LAWS 10
#define CONFIG_SYS_FSL_DDRC_GEN2
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_MPC8548)
-#define CONFIG_SYS_FSL_NUM_LAWS 10
#define CONFIG_SYS_FSL_DDRC_GEN2
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
#define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
@@ -81,24 +67,18 @@
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
#elif defined(CONFIG_ARCH_MPC8555)
-#define CONFIG_SYS_FSL_NUM_LAWS 8
#define CONFIG_SYS_FSL_DDRC_GEN1
#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#elif defined(CONFIG_ARCH_MPC8560)
-#define CONFIG_SYS_FSL_NUM_LAWS 8
#define CONFIG_SYS_FSL_DDRC_GEN1
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#elif defined(CONFIG_ARCH_MPC8568)
-#define CONFIG_SYS_FSL_NUM_LAWS 10
#define CONFIG_SYS_FSL_DDRC_GEN2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define QE_MURAM_SIZE 0x10000UL
#define MAX_QE_RISC 2
#define QE_NUM_OF_SNUM 28
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
@@ -106,12 +86,10 @@
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_ARCH_MPC8569)
-#define CONFIG_SYS_FSL_NUM_LAWS 10
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define QE_MURAM_SIZE 0x20000UL
#define MAX_QE_RISC 4
#define QE_NUM_OF_SNUM 46
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
@@ -121,10 +99,8 @@
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_MPC8572)
-#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_DDR_115
#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
#define CONFIG_SYS_FSL_ERRATUM_A004508
@@ -132,7 +108,6 @@
#elif defined(CONFIG_ARCH_P1010)
#define CONFIG_FSL_SDHC_V2_3
-#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 4
@@ -140,7 +115,6 @@
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
@@ -159,25 +133,21 @@
/* P1011 is single core version of P1020 */
#elif defined(CONFIG_ARCH_P1011)
-#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_P1020)
-#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_A004508
@@ -187,12 +157,10 @@
#endif
#elif defined(CONFIG_ARCH_P1021)
-#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define QE_MURAM_SIZE 0x6000UL
@@ -203,12 +171,10 @@
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#elif defined(CONFIG_ARCH_P1022)
-#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_FSL_SATA_ERRATUM_A001
@@ -217,7 +183,6 @@
#define CONFIG_SYS_FSL_ERRATUM_A004477
#elif defined(CONFIG_ARCH_P1023)
-#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 2
@@ -227,7 +192,6 @@
#define CONFIG_SYS_BMAN_NUM_PORTALS 3
#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
@@ -235,13 +199,11 @@
/* P1024 is lower end variant of P1020 */
#elif defined(CONFIG_ARCH_P1024)
-#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_A004508
@@ -249,13 +211,11 @@
/* P1025 is lower end variant of P1021 */
#elif defined(CONFIG_ARCH_P1025)
-#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define QE_MURAM_SIZE 0x6000UL
@@ -265,10 +225,8 @@
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_P2020)
-#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
@@ -285,7 +243,6 @@
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
-#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
@@ -295,7 +252,6 @@
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 32
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
@@ -322,7 +278,6 @@
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
-#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
@@ -332,7 +287,6 @@
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 32
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
@@ -361,7 +315,6 @@
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
-#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 2
#define CONFIG_SYS_NUM_FM1_DTSEC 4
@@ -374,7 +327,6 @@
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 16
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
@@ -412,7 +364,6 @@
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
-#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
@@ -423,7 +374,6 @@
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 32
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
@@ -447,7 +397,6 @@
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
-#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 2
#define CONFIG_SYS_NUM_FM1_DTSEC 5
@@ -460,7 +409,6 @@
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 16
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
@@ -477,7 +425,6 @@
#elif defined(CONFIG_ARCH_BSC9131)
#define CONFIG_FSL_SDHC_V2_3
-#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_NUM_DDR_CONTROLLERS 1
@@ -486,7 +433,6 @@
#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_A005125
@@ -496,7 +442,6 @@
#elif defined(CONFIG_ARCH_BSC9132)
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
#define CONFIG_FSL_SDHC_V2_3
-#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_NUM_DDR_CONTROLLERS 2
@@ -507,7 +452,6 @@
#define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
@@ -545,7 +489,6 @@
#endif
#endif
#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
-#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SRDS_2
#define CONFIG_SYS_FSL_SRDS_3
@@ -575,7 +518,6 @@
#define CONFIG_SYS_FSL_ERRATUM_A007186
#define CONFIG_SYS_FSL_ERRATUM_A006593
#define CONFIG_SYS_FSL_ERRATUM_A007798
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_SFP_VER_3_0
#define CONFIG_SYS_FSL_PCI_VER_3_X
@@ -588,7 +530,6 @@
#define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */
#define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/
#define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/
-#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SRDS_2
#define CONFIG_SYS_MAPLE
@@ -618,7 +559,6 @@
#define CONFIG_SYS_FSL_ERRATUM_A006384
#define CONFIG_SYS_FSL_ERRATUM_A007212
#define CONFIG_SYS_FSL_ERRATUM_A004477
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_SFP_VER_3_0
#ifdef CONFIG_ARCH_B4860
@@ -657,7 +597,6 @@
#endif
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
-#define CONFIG_SYS_FSL_NUM_LAWS 16
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_SYS_NUM_FMAN 1
@@ -681,7 +620,6 @@
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
#define QE_MURAM_SIZE 0x6000UL
@@ -704,7 +642,6 @@
#endif
#define CONFIG_SYS_FSL_NUM_CC_PLL 2
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
-#define CONFIG_SYS_FSL_NUM_LAWS 16
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_SYS_NUM_FMAN 1
@@ -725,7 +662,6 @@
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
#define QE_MURAM_SIZE 0x6000UL
@@ -743,7 +679,6 @@
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_QMAN_V3
-#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
@@ -778,7 +713,6 @@
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_A007212
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_SFP_VER_3_0
#define CONFIG_SYS_FSL_ISBC_VER 2
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -791,7 +725,6 @@
#elif defined(CONFIG_ARCH_C29X)
#define CONFIG_FSL_SDHC_V2_3
-#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
#define CONFIG_TSECV2_1
#define CONFIG_SYS_FSL_SEC_COMPAT 6
@@ -799,22 +732,16 @@
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
#define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
#elif defined(CONFIG_ARCH_QEMU_E500)
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000
#else
#error Processor type not defined for this platform
#endif
-#ifndef CONFIG_SYS_CCSRBAR_DEFAULT
-#error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
-#endif
-
#ifdef CONFIG_E6500
#define CONFIG_SYS_FSL_THREADS_PER_CORE 2
#else
diff --git a/arch/powerpc/include/asm/config_mpc86xx.h b/arch/powerpc/include/asm/config_mpc86xx.h
index c41dc99..f053b9c 100644
--- a/arch/powerpc/include/asm/config_mpc86xx.h
+++ b/arch/powerpc/include/asm/config_mpc86xx.h
@@ -9,16 +9,4 @@
#define CONFIG_SYS_FSL_DDR_86XX
-/* SoC specific defines for Freescale MPC86xx processors */
-
-#if defined(CONFIG_ARCH_MPC8610)
-#define CONFIG_SYS_FSL_NUM_LAWS 10
-
-#elif defined(CONFIG_ARCH_MPC8641)
-#define CONFIG_SYS_FSL_NUM_LAWS 10
-
-#else
-#error Processor type not defined for this platform
-#endif
-
#endif /* _ASM_MPC85xx_CONFIG_H_ */
diff --git a/board/varisys/cyrus/Kconfig b/board/varisys/cyrus/Kconfig
index d9ea7ef..c7b5253 100644
--- a/board/varisys/cyrus/Kconfig
+++ b/board/varisys/cyrus/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_CYRUS
+if TARGET_CYRUS_P5020 || TARGET_CYRUS_P5040
config SYS_BOARD
default "cyrus"
diff --git a/configs/B4860QDS_SECURE_BOOT_defconfig b/configs/B4860QDS_SECURE_BOOT_defconfig
index 53c122c..e2e16fb 100644
--- a/configs/B4860QDS_SECURE_BOOT_defconfig
+++ b/configs/B4860QDS_SECURE_BOOT_defconfig
@@ -6,7 +6,7 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
index a8fa5ab..52d5fe9 100644
--- a/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
+++ b/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
@@ -6,7 +6,8 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT,SYS_CLK_100_DDR_100,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT,SYS_CLK_100_DDR_100"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
index 4d79281..afa4aad 100644
--- a/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
+++ b/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
@@ -6,7 +6,8 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT,SYS_CLK_100_DDR_133,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT,SYS_CLK_100_DDR_133"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
index 2ad2c6e..5c3f150 100644
--- a/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
+++ b/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
@@ -6,7 +6,8 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_100,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_100"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
index e5ef6ad..0c0b5e3 100644
--- a/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
+++ b/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
@@ -6,7 +6,8 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_133,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_133"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
index e90044a..45b46df 100644
--- a/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
+++ b/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
@@ -6,7 +6,8 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD,SYS_CLK_100_DDR_100,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="SDCARD,SYS_CLK_100_DDR_100"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
index 19252c1..417ac5a 100644
--- a/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
+++ b/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
@@ -6,7 +6,8 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD,SYS_CLK_100_DDR_133,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="SDCARD,SYS_CLK_100_DDR_133"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
index d08dd8e..5145c3a 100644
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
+++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
@@ -6,7 +6,8 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100_DDR_100,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100_DDR_100"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
index 6519e22..0f65f96 100644
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
+++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
@@ -6,7 +6,8 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100_DDR_133,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100_DDR_133"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/C29XPCIE_NOR_SECBOOT_defconfig b/configs/C29XPCIE_NOR_SECBOOT_defconfig
index 2f1ed21..ed46dbe 100644
--- a/configs/C29XPCIE_NOR_SECBOOT_defconfig
+++ b/configs/C29XPCIE_NOR_SECBOOT_defconfig
@@ -6,7 +6,7 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
index 0c2c0b7..ef1100f 100644
--- a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
+++ b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
@@ -6,7 +6,8 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/Cyrus_P5020_defconfig b/configs/Cyrus_P5020_defconfig
index 94fc387..4c124d9 100644
--- a/configs/Cyrus_P5020_defconfig
+++ b/configs/Cyrus_P5020_defconfig
@@ -1,11 +1,11 @@
CONFIG_PPC=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_CYRUS=y
+CONFIG_TARGET_CYRUS_P5020=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000,ARCH_P5020"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000"
CONFIG_BOOTDELAY=10
CONFIG_CONSOLE_MUX=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/Cyrus_P5040_defconfig b/configs/Cyrus_P5040_defconfig
index 4b50772..aa68322 100644
--- a/configs/Cyrus_P5040_defconfig
+++ b/configs/Cyrus_P5040_defconfig
@@ -1,11 +1,11 @@
CONFIG_PPC=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_CYRUS=y
+CONFIG_TARGET_CYRUS_P5040=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000,ARCH_P5040"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000"
CONFIG_BOOTDELAY=10
CONFIG_CONSOLE_MUX=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
index b07900c..0430076 100644
--- a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
@@ -7,7 +7,8 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
index 72df737..f091938 100644
--- a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
@@ -7,7 +7,7 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
index 7bab7f4..f78a54d 100644
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
@@ -7,7 +7,8 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/P1010RDB-PA_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_NAND_SECBOOT_defconfig
index 28c33e5..ef3cd29 100644
--- a/configs/P1010RDB-PA_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_NAND_SECBOOT_defconfig
@@ -6,7 +6,8 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/P1010RDB-PA_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_NOR_SECBOOT_defconfig
index 319e40d..9716b4a 100644
--- a/configs/P1010RDB-PA_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_NOR_SECBOOT_defconfig
@@ -6,7 +6,7 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
index 61a745a..1f03841 100644
--- a/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
@@ -6,7 +6,8 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
index 868af10..5145f41 100644
--- a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
@@ -7,7 +7,8 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
index bf0194e..205df6d 100644
--- a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
@@ -7,7 +7,7 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
index 48d8dfc..7b6340d 100644
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
@@ -7,7 +7,8 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/P1010RDB-PB_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_NAND_SECBOOT_defconfig
index 898fc26..589223d 100644
--- a/configs/P1010RDB-PB_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_NAND_SECBOOT_defconfig
@@ -6,7 +6,8 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/P1010RDB-PB_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_NOR_SECBOOT_defconfig
index cb56ce9..a9494ee 100644
--- a/configs/P1010RDB-PB_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_NOR_SECBOOT_defconfig
@@ -6,7 +6,7 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
index 3a64b20..1a26a5d 100644
--- a/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
@@ -6,7 +6,8 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/P2041RDB_SECURE_BOOT_defconfig b/configs/P2041RDB_SECURE_BOOT_defconfig
index 295919a..7a811ae 100644
--- a/configs/P2041RDB_SECURE_BOOT_defconfig
+++ b/configs/P2041RDB_SECURE_BOOT_defconfig
@@ -6,7 +6,7 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
diff --git a/configs/P3041DS_NAND_SECURE_BOOT_defconfig b/configs/P3041DS_NAND_SECURE_BOOT_defconfig
index a359708..38407ba 100644
--- a/configs/P3041DS_NAND_SECURE_BOOT_defconfig
+++ b/configs/P3041DS_NAND_SECURE_BOOT_defconfig
@@ -6,7 +6,8 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
diff --git a/configs/P3041DS_SECURE_BOOT_defconfig b/configs/P3041DS_SECURE_BOOT_defconfig
index 89108b5..75c0ef3 100644
--- a/configs/P3041DS_SECURE_BOOT_defconfig
+++ b/configs/P3041DS_SECURE_BOOT_defconfig
@@ -6,7 +6,7 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
diff --git a/configs/P4080DS_SECURE_BOOT_defconfig b/configs/P4080DS_SECURE_BOOT_defconfig
index 51b2bb5..46b4672 100644
--- a/configs/P4080DS_SECURE_BOOT_defconfig
+++ b/configs/P4080DS_SECURE_BOOT_defconfig
@@ -6,7 +6,7 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
diff --git a/configs/P5020DS_NAND_SECURE_BOOT_defconfig b/configs/P5020DS_NAND_SECURE_BOOT_defconfig
index d89326c..592aae7 100644
--- a/configs/P5020DS_NAND_SECURE_BOOT_defconfig
+++ b/configs/P5020DS_NAND_SECURE_BOOT_defconfig
@@ -6,7 +6,8 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
diff --git a/configs/P5020DS_SECURE_BOOT_defconfig b/configs/P5020DS_SECURE_BOOT_defconfig
index 074d159..27f43ef 100644
--- a/configs/P5020DS_SECURE_BOOT_defconfig
+++ b/configs/P5020DS_SECURE_BOOT_defconfig
@@ -6,7 +6,7 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
diff --git a/configs/P5040DS_NAND_SECURE_BOOT_defconfig b/configs/P5040DS_NAND_SECURE_BOOT_defconfig
index abe6de2..9fdf4b25 100644
--- a/configs/P5040DS_NAND_SECURE_BOOT_defconfig
+++ b/configs/P5040DS_NAND_SECURE_BOOT_defconfig
@@ -6,7 +6,8 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
diff --git a/configs/P5040DS_SECURE_BOOT_defconfig b/configs/P5040DS_SECURE_BOOT_defconfig
index 0b9b0d1..b8d7d3b 100644
--- a/configs/P5040DS_SECURE_BOOT_defconfig
+++ b/configs/P5040DS_SECURE_BOOT_defconfig
@@ -6,7 +6,7 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
diff --git a/configs/T1023RDB_SECURE_BOOT_defconfig b/configs/T1023RDB_SECURE_BOOT_defconfig
index 633128a..1b474d3 100644
--- a/configs/T1023RDB_SECURE_BOOT_defconfig
+++ b/configs/T1023RDB_SECURE_BOOT_defconfig
@@ -6,7 +6,8 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="T1023RDB,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="T1023RDB"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig b/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
index d7bd23a..bdc0a9d 100644
--- a/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
+++ b/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
@@ -7,7 +7,8 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
diff --git a/configs/T1024QDS_SECURE_BOOT_defconfig b/configs/T1024QDS_SECURE_BOOT_defconfig
index ce7d142..b092068 100644
--- a/configs/T1024QDS_SECURE_BOOT_defconfig
+++ b/configs/T1024QDS_SECURE_BOOT_defconfig
@@ -7,7 +7,7 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
diff --git a/configs/T1024RDB_SECURE_BOOT_defconfig b/configs/T1024RDB_SECURE_BOOT_defconfig
index 806cc21..9d082f7 100644
--- a/configs/T1024RDB_SECURE_BOOT_defconfig
+++ b/configs/T1024RDB_SECURE_BOOT_defconfig
@@ -6,7 +6,8 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="T1024RDB,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="T1024RDB"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
diff --git a/configs/T1040D4RDB_SECURE_BOOT_defconfig b/configs/T1040D4RDB_SECURE_BOOT_defconfig
index a89786a..6f948a1 100644
--- a/configs/T1040D4RDB_SECURE_BOOT_defconfig
+++ b/configs/T1040D4RDB_SECURE_BOOT_defconfig
@@ -6,7 +6,8 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
diff --git a/configs/T1040QDS_SECURE_BOOT_defconfig b/configs/T1040QDS_SECURE_BOOT_defconfig
index 9666832..3f15b09 100644
--- a/configs/T1040QDS_SECURE_BOOT_defconfig
+++ b/configs/T1040QDS_SECURE_BOOT_defconfig
@@ -7,7 +7,7 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
diff --git a/configs/T1040RDB_SECURE_BOOT_defconfig b/configs/T1040RDB_SECURE_BOOT_defconfig
index db5316d..a9b61a8 100644
--- a/configs/T1040RDB_SECURE_BOOT_defconfig
+++ b/configs/T1040RDB_SECURE_BOOT_defconfig
@@ -6,7 +6,7 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
diff --git a/configs/T1042D4RDB_SECURE_BOOT_defconfig b/configs/T1042D4RDB_SECURE_BOOT_defconfig
index ced54e1..e20d412 100644
--- a/configs/T1042D4RDB_SECURE_BOOT_defconfig
+++ b/configs/T1042D4RDB_SECURE_BOOT_defconfig
@@ -7,7 +7,8 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
diff --git a/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig b/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
index c07a29c..26db750 100644
--- a/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
+++ b/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
@@ -13,7 +13,8 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=0
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
diff --git a/configs/T1042RDB_SECURE_BOOT_defconfig b/configs/T1042RDB_SECURE_BOOT_defconfig
index 2e6e441..edd1ff6 100644
--- a/configs/T1042RDB_SECURE_BOOT_defconfig
+++ b/configs/T1042RDB_SECURE_BOOT_defconfig
@@ -6,7 +6,7 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig
index ac8842e..95f6804 100644
--- a/configs/T2080QDS_SECURE_BOOT_defconfig
+++ b/configs/T2080QDS_SECURE_BOOT_defconfig
@@ -6,7 +6,7 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
diff --git a/configs/T2080RDB_SECURE_BOOT_defconfig b/configs/T2080RDB_SECURE_BOOT_defconfig
index 4675ac6..64204e0 100644
--- a/configs/T2080RDB_SECURE_BOOT_defconfig
+++ b/configs/T2080RDB_SECURE_BOOT_defconfig
@@ -6,7 +6,7 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MEMTEST=y
diff --git a/configs/T4160QDS_SECURE_BOOT_defconfig b/configs/T4160QDS_SECURE_BOOT_defconfig
index 36940e4..e637f1e 100644
--- a/configs/T4160QDS_SECURE_BOOT_defconfig
+++ b/configs/T4160QDS_SECURE_BOOT_defconfig
@@ -6,7 +6,7 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
diff --git a/configs/T4240QDS_SECURE_BOOT_defconfig b/configs/T4240QDS_SECURE_BOOT_defconfig
index ed2d093..61028e3 100644
--- a/configs/T4240QDS_SECURE_BOOT_defconfig
+++ b/configs/T4240QDS_SECURE_BOOT_defconfig
@@ -6,7 +6,7 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
index 567c852..8b869fa 100644
--- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
@@ -7,7 +7,7 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
index f218e8f..946945f 100644
--- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
@@ -6,7 +6,7 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
index ae0d814..5e74645 100644
--- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
@@ -13,7 +13,8 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=0
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig
index 6f93612..b892e35 100644
--- a/configs/ls1043ardb_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_SECURE_BOOT_defconfig
@@ -5,7 +5,7 @@
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig
index 41ae2b1..0c70f92 100644
--- a/configs/ls2080aqds_SECURE_BOOT_defconfig
+++ b/configs/ls2080aqds_SECURE_BOOT_defconfig
@@ -6,7 +6,8 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A, SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig
index e176607..1d20175 100644
--- a/configs/ls2080ardb_SECURE_BOOT_defconfig
+++ b/configs/ls2080ardb_SECURE_BOOT_defconfig
@@ -6,7 +6,8 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A, SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
diff --git a/doc/README.ramboot-ppc85xx b/doc/README.ramboot-ppc85xx
index 5cc546a..c9fef53 100644
--- a/doc/README.ramboot-ppc85xx
+++ b/doc/README.ramboot-ppc85xx
@@ -90,8 +90,8 @@
This will finally use the CONFIG_SYS_RAMBOOT.
-3. File name-> arch/powerpc/include/asm/config_mpc85xx.h
- In the section of the particular SOC, for example P1020,
+3. Change CONFIG_SYS_CCSRBAR_DEFAULT in menuconfig accordingly.
+ In the section of the particular SOC, for example P1020, pseudo code
#if defined(CONFIG_GO)
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xffe00000
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index cd4333f..7d3ebf3 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -19,7 +19,6 @@
#else
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x00201000
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
@@ -80,8 +79,6 @@
#define CONFIG_SRIO_PCIE_BOOT_MASTER
#endif
-#define CONFIG_FSL_LAW /* Use common FSL init code */
-
/* I2C bus multiplexer */
#define I2C_MUX_PCA_ADDR 0x77
diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h
index aaf7106..eecbd75 100644
--- a/include/configs/BSC9131RDB.h
+++ b/include/configs/BSC9131RDB.h
@@ -51,7 +51,6 @@
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_TSEC_ENET
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
index 8eee738..5cfdbb2 100644
--- a/include/configs/BSC9132QDS.h
+++ b/include/configs/BSC9132QDS.h
@@ -103,7 +103,6 @@
#define CONFIG_DOS_PARTITION
#endif
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_TSEC_ENET /* ethernet */
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index 39eefb4..79cf09e 100644
--- a/include/configs/C29XPCIE.h
+++ b/include/configs/C29XPCIE.h
@@ -102,7 +102,6 @@
#define CONFIG_DOS_PARTITION
#endif
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_TSEC_ENET
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 446303d..d8f7961 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -51,7 +51,6 @@
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 54932fd..9fd7109 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -36,7 +36,6 @@
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
/*
* sysclk for MPC85xx
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index 29bca4c..2dad188 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -25,8 +25,6 @@
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
-
#define CONFIG_FSL_VIA
#ifndef __ASSEMBLY__
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 6c17a3b..4bab893 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -28,8 +28,6 @@
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
-
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 310c070..41ba9e7 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -35,7 +35,6 @@
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_FSL_VIA
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index 3cf8d97..0f035dd 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -24,7 +24,6 @@
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_FSL_VIA
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 641521c..343287e 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -34,7 +34,6 @@
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
/*
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index e7adb17..3cddb5f 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -28,7 +28,6 @@
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_QE /* Enable QE */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#ifndef __ASSEMBLY__
extern unsigned long get_clock_freq(void);
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 91f0104..bd52054 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -26,7 +26,6 @@
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_QE /* Enable QE */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#ifndef __ASSEMBLY__
extern unsigned long get_clock_freq(void);
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index e134560..bffcad1 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -39,8 +39,6 @@
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
-
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 75693a0..761032e 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -42,7 +42,6 @@
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
@@ -72,7 +71,6 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index c94b329..8845ea9 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -44,7 +44,6 @@
#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#define CONFIG_FSL_LAW 1 /* Use common FSL law init code */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
@@ -87,7 +86,6 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index 3ced88d..78e0064 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -19,7 +19,6 @@
#define CONFIG_SPL_MMC_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x11001000
#define CONFIG_SPL_TEXT_BASE 0xD0001000
#define CONFIG_SPL_PAD_TO 0x18000
@@ -45,7 +44,6 @@
#define CONFIG_SPL_SPI_FLASH_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x11001000
#define CONFIG_SPL_TEXT_BASE 0xD0001000
#define CONFIG_SPL_PAD_TO 0x18000
@@ -201,7 +199,6 @@
#define CONFIG_DOS_PARTITION
#endif
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_TSEC_ENET
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index 6f07080..81e8c29 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -15,7 +15,6 @@
#define CONFIG_SPL_MMC_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x11001000
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
#define CONFIG_SPL_PAD_TO 0x20000
@@ -36,7 +35,6 @@
#define CONFIG_SPL_SPI_FLASH_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x11001000
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
#define CONFIG_SPL_PAD_TO 0x20000
@@ -115,8 +113,6 @@
#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
#endif
-#define CONFIG_FSL_LAW /* Use common FSL init code */
-
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h
index 5061286..d5728a1 100644
--- a/include/configs/P1023RDB.h
+++ b/include/configs/P1023RDB.h
@@ -35,7 +35,6 @@
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#ifndef __ASSEMBLY__
extern unsigned long get_clock_freq(void);
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 417bfd3..91e5f8b 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -58,8 +58,6 @@
#define CONFIG_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_DPAA_RMAN /* RMan */
-#define CONFIG_FSL_LAW /* Use common FSL init code */
-
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_SYS_NO_FLASH
diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h
index 3c0a0c9..fda83d2 100644
--- a/include/configs/T102xQDS.h
+++ b/include/configs/T102xQDS.h
@@ -28,7 +28,6 @@
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
#define CONFIG_FSL_IFC /* Enable IFC Support */
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_DEEP_SLEEP
@@ -42,7 +41,6 @@
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x00201000
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index e2aea8b..054b323 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -28,7 +28,6 @@
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
#define CONFIG_FSL_IFC /* Enable IFC Support */
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
@@ -45,7 +44,6 @@
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x30001000
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index ba1c38b..00676dd 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -69,8 +69,6 @@
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-#define CONFIG_FSL_LAW /* Use common FSL init code */
-
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_SYS_NO_FLASH
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index ed568f3..7521dd0 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -24,7 +24,6 @@
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x30001000
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
@@ -180,8 +179,6 @@
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-#define CONFIG_FSL_LAW /* Use common FSL init code */
-
#define CONFIG_ENV_OVERWRITE
#ifndef CONFIG_SYS_NO_FLASH
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 17176f4..b984fcd 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -41,7 +41,6 @@
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_RAMBOOT_PBL
@@ -49,7 +48,6 @@
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x00201000
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index bca6a5b..e013e72 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -34,7 +34,6 @@
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_RAMBOOT_PBL
@@ -42,7 +41,6 @@
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x00201000
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h
index 1d18316..d90fb35 100644
--- a/include/configs/T4240QDS.h
+++ b/include/configs/T4240QDS.h
@@ -24,7 +24,6 @@
#else
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x00201000
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index 6c743e3..fd5dbc5 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -23,7 +23,6 @@
#else
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x00201000
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
@@ -85,8 +84,6 @@
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-#define CONFIG_FSL_LAW /* Use common FSL init code */
-
#define CONFIG_ENV_OVERWRITE
/*
diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h
index 1163b0d..c194ec7 100644
--- a/include/configs/UCP1020.h
+++ b/include/configs/UCP1020.h
@@ -124,8 +124,6 @@
#define CONFIG_MP
-#define CONFIG_FSL_LAW
-
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CMD_SATA
diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h
index b824e3b..971549e 100644
--- a/include/configs/controlcenterd.h
+++ b/include/configs/controlcenterd.h
@@ -42,7 +42,6 @@
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENABLE_36BIT_PHYS
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_ADDR_MAP
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 67a5034..c4d172d 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -69,8 +69,6 @@
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-#define CONFIG_FSL_LAW /* Use common FSL init code */
-
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_SYS_NO_FLASH
diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h
index 13e4690..45caf9f 100644
--- a/include/configs/cyrus.h
+++ b/include/configs/cyrus.h
@@ -59,8 +59,6 @@
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-#define CONFIG_FSL_LAW /* Use common FSL init code */
-
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_NO_FLASH
diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h
index fad8865..affcb48 100644
--- a/include/configs/km/kmp204x-common.h
+++ b/include/configs/km/kmp204x-common.h
@@ -46,8 +46,6 @@
#define CONFIG_SYS_DPAA_RMAN /* RMan */
-#define CONFIG_FSL_LAW /* Use common FSL init code */
-
/* Environment in SPI Flash */
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_IS_IN_SPI_FLASH
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 77f3d81..c20ef5e 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -174,7 +174,6 @@
#define CONFIG_SPL_MMC_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x11001000
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
#define CONFIG_SPL_PAD_TO 0x20000
@@ -195,7 +194,6 @@
#define CONFIG_SPL_SPI_FLASH_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x11001000
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
#define CONFIG_SPL_PAD_TO 0x20000
@@ -274,7 +272,6 @@
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-#define CONFIG_FSL_LAW
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h
index c122f8e..5ff2e35 100644
--- a/include/configs/p1_twr.h
+++ b/include/configs/p1_twr.h
@@ -52,7 +52,6 @@
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-#define CONFIG_FSL_LAW
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index 008781e..617be27 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -69,8 +69,6 @@
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
-
/*
* Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4]
*/
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index 2bd89f4..87056db 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -46,7 +46,6 @@
#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
@@ -87,7 +86,6 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index c697f63..81afed0 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -31,8 +31,6 @@
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
-
/*
* Only possible on E500 Version 2 or newer cores.
*/
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
index 0aba18b..e2b1171 100644
--- a/include/configs/t4qds.h
+++ b/include/configs/t4qds.h
@@ -40,8 +40,6 @@
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */
-#define CONFIG_FSL_LAW /* Use common FSL init code */
-
#define CONFIG_ENV_OVERWRITE
/*
diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h
index 6d95789..df36ad7 100644
--- a/include/configs/xpedite517x.h
+++ b/include/configs/xpedite517x.h
@@ -31,7 +31,6 @@
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
/*
* DDR config
@@ -76,7 +75,6 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h
index 7f6927b..fee8c34 100644
--- a/include/configs/xpedite520x.h
+++ b/include/configs/xpedite520x.h
@@ -30,7 +30,6 @@
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
/*
* DDR config
diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h
index a6bdffc..7e811d5 100644
--- a/include/configs/xpedite537x.h
+++ b/include/configs/xpedite537x.h
@@ -31,7 +31,6 @@
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_FSL_ELBC 1
/*
diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h
index f12f8fe..4dfb79d 100644
--- a/include/configs/xpedite550x.h
+++ b/include/configs/xpedite550x.h
@@ -32,7 +32,6 @@
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_FSL_ELBC 1
/*
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 121b4f2..8814841 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -1273,7 +1273,6 @@
CONFIG_FSL_IFC
CONFIG_FSL_IIM
CONFIG_FSL_ISBC_KEY_EXT
-CONFIG_FSL_LAW
CONFIG_FSL_LAYERSCAPE
CONFIG_FSL_LBC
CONFIG_FSL_LINFLEXUART
@@ -4475,7 +4474,6 @@
CONFIG_SYS_CCCR
CONFIG_SYS_CCI400_ADDR
CONFIG_SYS_CCSRBAR
-CONFIG_SYS_CCSRBAR_DEFAULT
CONFIG_SYS_CCSRBAR_PHYS
CONFIG_SYS_CCSRBAR_PHYS_HIGH
CONFIG_SYS_CCSRBAR_PHYS_LOW
@@ -5506,7 +5504,6 @@
CONFIG_SYS_FSL_NO_SERDES
CONFIG_SYS_FSL_NUM_CC_PLL
CONFIG_SYS_FSL_NUM_CC_PLLS
-CONFIG_SYS_FSL_NUM_LAWS
CONFIG_SYS_FSL_OCRAM_BASE
CONFIG_SYS_FSL_OCRAM_SIZE
CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS