Modified the DDR SDRAM clock control register to delay MCK/MCK_B 3/4 clock
With the original value of 1/2 clock cycle delay, the system ran relatively
stable except when we run benchmarks that are intensive users of memory.
When I run samba connected disk with a HDBENCH test, the system locks-up
or reboots sporadically.
Signed-off by: Joe D'Abbraccio <Joe.D'abbraccio@freescale.com>
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 0e50186..6b8b74d 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -156,7 +156,7 @@
#define CFG_MEMTEST_END 0x2000
#define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
- DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
#ifdef CONFIG_HARD_I2C
#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/