| commit | 69b8eb01ecd44fec39d2f9616e98b13b46a2af79 | [log] [tgz] |
|---|---|---|
| author | Bai Ping <ping.bai@nxp.com> | Thu Aug 08 09:59:05 2019 +0000 |
| committer | Stefano Babic <sbabic@denx.de> | Tue Oct 08 16:36:37 2019 +0200 |
| tree | 4cdfbc1d24d7e338454ced1b2283a947b6f7b25e | |
| parent | f19c31cf61c148fabf72b4e1605de765be00c563 [diff] |
imx8mq: Update the ddrc QoS setting for B1 chip Update the ddrc Qos setting for B1 to align with B0's setting. Correct the initial clock for dram_pll. This setting will be overwrite before ddr phy training. Although there is no impact on the dram init, we still need to correct it to eliminate confusion. Signed-off-by: Bai Ping <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Tested-by: Robby Cai <robby.cai@nxp.com>