Merge branch 'master' of git://git.denx.de/u-boot-mmc
diff --git a/README b/README
index 1bcb63c..95f2d9d 100644
--- a/README
+++ b/README
@@ -705,6 +705,7 @@
CONFIG_ARM_ERRATA_454179
CONFIG_ARM_ERRATA_621766
CONFIG_ARM_ERRATA_798870
+ CONFIG_ARM_ERRATA_801819
- Tegra SoC options:
CONFIG_TEGRA_SUPPORT_NON_SECURE
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 8b8269f..ee9a1b3 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -64,7 +64,7 @@
choice
prompt "Target select"
- optional
+ default ARCH_VERSATILE
config ARCH_AT91
bool "Atmel AT91"
@@ -121,6 +121,7 @@
config TARGET_DEVKIT3250
bool "Support devkit3250"
select CPU_ARM926EJS
+ select SUPPORT_SPL
config TARGET_WORK_92105
bool "Support work_92105"
@@ -457,6 +458,8 @@
config ARCH_INTEGRATOR
bool "ARM Ltd. Integrator family"
+ select DM
+ select DM_SERIAL
config ARCH_KEYSTONE
bool "TI Keystone"
@@ -640,6 +643,11 @@
select DM_SPI_FLASH
select DM_SPI
+config TARGET_CM_T43
+ bool "Support cm_t43"
+ select CPU_V7
+ select SUPPORT_SPL
+
config ARCH_SUNXI
bool "Support sunxi (Allwinner) SoCs"
select CMD_USB
@@ -733,6 +741,13 @@
development platform that supports the QorIQ LS2085A
Layerscape Architecture processor.
+config TARGET_HIKEY
+ bool "Support HiKey 96boards Consumer Edition Platform"
+ select ARM64
+ help
+ Support for HiKey 96boards platform. It features a HI6220
+ SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
+
config TARGET_LS1021AQDS
bool "Support ls1021aqds"
select CPU_V7
@@ -880,6 +895,7 @@
source "board/armadeus/apf27/Kconfig"
source "board/armltd/vexpress/Kconfig"
source "board/armltd/vexpress64/Kconfig"
+source "board/hisilicon/hikey/Kconfig"
source "board/bachmann/ot1200/Kconfig"
source "board/balloon3/Kconfig"
source "board/barco/platinum/Kconfig"
@@ -891,6 +907,7 @@
source "board/broadcom/bcmnsp/Kconfig"
source "board/cirrus/edb93xx/Kconfig"
source "board/compulab/cm_t335/Kconfig"
+source "board/compulab/cm_t43/Kconfig"
source "board/compulab/cm_fx6/Kconfig"
source "board/congatec/cgtqmx6eval/Kconfig"
source "board/creative/xfi3/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 6f30098..ab0e9ce 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -78,7 +78,7 @@
libs-y += arch/arm/lib/
ifeq ($(CONFIG_SPL_BUILD),y)
-ifneq (,$(CONFIG_MX23)$(CONFIG_MX35)$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35))
+ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35))
libs-y += arch/arm/imx-common/
endif
else
diff --git a/arch/arm/cpu/arm11/Makefile b/arch/arm/cpu/arm11/Makefile
new file mode 100644
index 0000000..2379b0f
--- /dev/null
+++ b/arch/arm/cpu/arm11/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = cpu.o
diff --git a/arch/arm/cpu/arm1136/cpu.c b/arch/arm/cpu/arm11/cpu.c
similarity index 84%
rename from arch/arm/cpu/arm1136/cpu.c
rename to arch/arm/cpu/arm11/cpu.c
index a7aed4b..1e4c214 100644
--- a/arch/arm/cpu/arm1136/cpu.c
+++ b/arch/arm/cpu/arm11/cpu.c
@@ -32,16 +32,6 @@
disable_interrupts ();
-#ifdef CONFIG_LCD
- {
- extern void lcd_disable(void);
- extern void lcd_panel_disable(void);
-
- lcd_disable(); /* proper disable of lcd & panel */
- lcd_panel_disable();
- }
-#endif
-
/* turn off I/D-cache */
icache_disable();
dcache_disable();
@@ -120,11 +110,6 @@
asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
}
-void flush_cache(unsigned long start, unsigned long size)
-{
- flush_dcache_range(start, start + size);
-}
-
#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
void invalidate_dcache_all(void)
{
@@ -133,18 +118,6 @@
void flush_dcache_all(void)
{
}
-
-void invalidate_dcache_range(unsigned long start, unsigned long stop)
-{
-}
-
-void flush_dcache_range(unsigned long start, unsigned long stop)
-{
-}
-
-void flush_cache(unsigned long start, unsigned long size)
-{
-}
#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
#if !defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)
diff --git a/arch/arm/cpu/arm1136/Makefile b/arch/arm/cpu/arm1136/Makefile
index 56a9390..dbdafeb 100644
--- a/arch/arm/cpu/arm1136/Makefile
+++ b/arch/arm/cpu/arm1136/Makefile
@@ -6,7 +6,7 @@
#
extra-y = start.o
-obj-y = cpu.o
+obj-y += ../arm11/
obj-$(CONFIG_MX31) += mx31/
obj-$(CONFIG_MX35) += mx35/
diff --git a/arch/arm/cpu/arm1176/Makefile b/arch/arm/cpu/arm1176/Makefile
index deec427..cd6dc9c 100644
--- a/arch/arm/cpu/arm1176/Makefile
+++ b/arch/arm/cpu/arm1176/Makefile
@@ -8,5 +8,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
+obj- += dummy.o
extra-y = start.o
-obj-y = cpu.o
+
+obj-y += ../arm11/
diff --git a/arch/arm/cpu/arm1176/cpu.c b/arch/arm/cpu/arm1176/cpu.c
deleted file mode 100644
index 2d81651..0000000
--- a/arch/arm/cpu/arm1176/cpu.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * (C) Copyright 2004 Texas Insturments
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * CPU specific code
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/system.h>
-
-static void cache_flush (void);
-
-int cleanup_before_linux (void)
-{
- /*
- * this function is called just before we call linux
- * it prepares the processor for linux
- *
- * we turn off caches etc ...
- */
-
- disable_interrupts ();
-
- /* turn off I/D-cache */
- icache_disable();
- dcache_disable();
- /* flush I/D-cache */
- cache_flush();
-
- return 0;
-}
-
-/* flush I/D-cache */
-static void cache_flush (void)
-{
- /* invalidate both caches and flush btb */
- asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (0));
- /* mem barrier to sync things */
- asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (0));
-}
diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
index 8d7873c..e5c1a6a 100644
--- a/arch/arm/cpu/arm926ejs/cache.c
+++ b/arch/arm/cpu/arm926ejs/cache.c
@@ -69,11 +69,6 @@
asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0));
}
-
-void flush_cache(unsigned long start, unsigned long size)
-{
- flush_dcache_range(start, start + size);
-}
#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
void invalidate_dcache_all(void)
{
@@ -82,18 +77,6 @@
void flush_dcache_all(void)
{
}
-
-void invalidate_dcache_range(unsigned long start, unsigned long stop)
-{
-}
-
-void flush_dcache_range(unsigned long start, unsigned long stop)
-{
-}
-
-void flush_cache(unsigned long start, unsigned long size)
-{
-}
#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
/*
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index 5a453e3..c0c9c6c 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -45,7 +45,12 @@
{
/* Enable MAC interface */
writel(CLK_MAC_REG | CLK_MAC_SLAVE | CLK_MAC_MASTER
- | CLK_MAC_MII, &clk->macclk_ctrl);
+#if defined(CONFIG_RMII)
+ | CLK_MAC_RMII,
+#else
+ | CLK_MAC_MII,
+#endif
+ &clk->macclk_ctrl);
}
void lpc32xx_mlc_nand_init(void)
@@ -54,6 +59,12 @@
writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, &clk->flashclk_ctrl);
}
+void lpc32xx_slc_nand_init(void)
+{
+ /* Enable SLC NAND interface */
+ writel(CLK_NAND_SLC | CLK_NAND_SLC_SELECT, &clk->flashclk_ctrl);
+}
+
void lpc32xx_i2c_init(unsigned int devnum)
{
/* Enable I2C interface */
diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c
index ef130ae..b1d8721 100644
--- a/arch/arm/cpu/arm926ejs/mxs/mxs.c
+++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c
@@ -24,7 +24,7 @@
DECLARE_GLOBAL_DATA_PTR;
/* Lowlevel init isn't used on i.MX28, so just have a dummy here */
-inline void lowlevel_init(void) {}
+void lowlevel_init(void) {}
void reset_cpu(ulong ignored) __attribute__((noreturn));
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 377c611..bd14326 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -38,45 +38,22 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_DM_GPIO
-static const struct omap_gpio_platdata am33xx_gpio[] = {
- { 0, AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
- { 1, AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
- { 2, AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
- { 3, AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
-#ifdef CONFIG_AM43XX
- { 4, AM33XX_GPIO4_BASE, METHOD_GPIO_24XX },
- { 5, AM33XX_GPIO5_BASE, METHOD_GPIO_24XX },
-#endif
-};
-
-U_BOOT_DEVICES(am33xx_gpios) = {
- { "gpio_omap", &am33xx_gpio[0] },
- { "gpio_omap", &am33xx_gpio[1] },
- { "gpio_omap", &am33xx_gpio[2] },
- { "gpio_omap", &am33xx_gpio[3] },
-#ifdef CONFIG_AM43XX
- { "gpio_omap", &am33xx_gpio[4] },
- { "gpio_omap", &am33xx_gpio[5] },
-#endif
-};
-
-# ifndef CONFIG_OF_CONTROL
+#if defined(CONFIG_DM_SERIAL) && !defined(CONFIG_OF_CONTROL)
/*
* TODO(sjg@chromium.org): When we can move SPL serial to DM, we can remove
* the CONFIGs. At the same time, we should move this to the board files.
*/
static const struct ns16550_platdata am33xx_serial[] = {
{ CONFIG_SYS_NS16550_COM1, 2, CONFIG_SYS_NS16550_CLK },
-# ifdef CONFIG_SYS_NS16550_COM2
+# ifdef CONFIG_SYS_NS16550_COM2
{ CONFIG_SYS_NS16550_COM2, 2, CONFIG_SYS_NS16550_CLK },
-# ifdef CONFIG_SYS_NS16550_COM3
+# ifdef CONFIG_SYS_NS16550_COM3
{ CONFIG_SYS_NS16550_COM3, 2, CONFIG_SYS_NS16550_CLK },
{ CONFIG_SYS_NS16550_COM4, 2, CONFIG_SYS_NS16550_CLK },
{ CONFIG_SYS_NS16550_COM5, 2, CONFIG_SYS_NS16550_CLK },
{ CONFIG_SYS_NS16550_COM6, 2, CONFIG_SYS_NS16550_CLK },
-# endif
# endif
+# endif
};
U_BOOT_DEVICES(am33xx_uarts) = {
@@ -91,23 +68,22 @@
# endif
# endif
};
-# endif
+#endif
-#else
+#ifndef CONFIG_DM_GPIO
static const struct gpio_bank gpio_bank_am33xx[] = {
- { (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
- { (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
- { (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
- { (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
+ { (void *)AM33XX_GPIO0_BASE },
+ { (void *)AM33XX_GPIO1_BASE },
+ { (void *)AM33XX_GPIO2_BASE },
+ { (void *)AM33XX_GPIO3_BASE },
#ifdef CONFIG_AM43XX
- { (void *)AM33XX_GPIO4_BASE, METHOD_GPIO_24XX },
- { (void *)AM33XX_GPIO5_BASE, METHOD_GPIO_24XX },
+ { (void *)AM33XX_GPIO4_BASE },
+ { (void *)AM33XX_GPIO5_BASE },
#endif
};
const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
-
#endif
#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
index b1c0025..b639694 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
@@ -115,6 +115,7 @@
&cmper->usbphyocp2scp0clkctrl,
&cmper->usb1clkctrl,
&cmper->usbphyocp2scp1clkctrl,
+ &cmper->spi0clkctrl,
0
};
diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
index e8ee875..a5aa4fa 100644
--- a/arch/arm/cpu/armv7/cache_v7.c
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -286,15 +286,6 @@
flush_dcache_range(start, stop);
v7_inval_tlb();
}
-
-/*
- * Flush range from all levels of d-cache/unified-cache used:
- * Affects the range [start, start + size - 1]
- */
-void flush_cache(unsigned long start, unsigned long size)
-{
- flush_dcache_range(start, start + size);
-}
#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
void invalidate_dcache_all(void)
{
@@ -304,22 +295,10 @@
{
}
-void invalidate_dcache_range(unsigned long start, unsigned long stop)
-{
-}
-
-void flush_dcache_range(unsigned long start, unsigned long stop)
-{
-}
-
void arm_init_before_mmu(void)
{
}
-void flush_cache(unsigned long start, unsigned long size)
-{
-}
-
void mmu_page_table_flush(unsigned long start, unsigned long stop)
{
}
diff --git a/arch/arm/cpu/armv7/lowlevel_init.S b/arch/arm/cpu/armv7/lowlevel_init.S
index 427b0b1..1872c57 100644
--- a/arch/arm/cpu/armv7/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/lowlevel_init.S
@@ -21,7 +21,7 @@
*/
ldr sp, =CONFIG_SYS_INIT_SP_ADDR
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
-#ifdef CONFIG_DM
+#ifdef CONFIG_SPL_DM
mov r9, #0
#else
/*
diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig
index b32a6b0..f4fb6cb 100644
--- a/arch/arm/cpu/armv7/omap3/Kconfig
+++ b/arch/arm/cpu/armv7/omap3/Kconfig
@@ -114,6 +114,13 @@
select DM_SERIAL
select DM_GPIO
+config TARGET_SNIPER
+ bool "Sniper"
+ select SUPPORT_SPL
+ select DM
+ select DM_SERIAL
+ select DM_GPIO
+
endchoice
config SYS_SOC
@@ -142,5 +149,6 @@
source "board/technexion/tao3530/Kconfig"
source "board/technexion/twister/Kconfig"
source "board/quipos/cairo/Kconfig"
+source "board/lge/sniper/Kconfig"
endif
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index 17cb5b7..8252b32 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -38,12 +38,12 @@
#ifdef CONFIG_DM_GPIO
static const struct omap_gpio_platdata omap34xx_gpio[] = {
- { 0, OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
- { 1, OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
- { 2, OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
- { 3, OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
- { 4, OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
- { 5, OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
+ { 0, OMAP34XX_GPIO1_BASE },
+ { 1, OMAP34XX_GPIO2_BASE },
+ { 2, OMAP34XX_GPIO3_BASE },
+ { 3, OMAP34XX_GPIO4_BASE },
+ { 4, OMAP34XX_GPIO5_BASE },
+ { 5, OMAP34XX_GPIO6_BASE },
};
U_BOOT_DEVICES(am33xx_gpios) = {
@@ -58,12 +58,12 @@
#else
static const struct gpio_bank gpio_bank_34xx[6] = {
- { (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
- { (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
- { (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
- { (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
- { (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
- { (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
+ { (void *)OMAP34XX_GPIO1_BASE },
+ { (void *)OMAP34XX_GPIO2_BASE },
+ { (void *)OMAP34XX_GPIO3_BASE },
+ { (void *)OMAP34XX_GPIO4_BASE },
+ { (void *)OMAP34XX_GPIO5_BASE },
+ { (void *)OMAP34XX_GPIO6_BASE },
};
const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
diff --git a/arch/arm/cpu/armv7/omap3/boot.c b/arch/arm/cpu/armv7/omap3/boot.c
index 66576b2..44d7c30 100644
--- a/arch/arm/cpu/armv7/omap3/boot.c
+++ b/arch/arm/cpu/armv7/omap3/boot.c
@@ -56,3 +56,41 @@
return boot_devices[sys_boot];
}
+
+char omap_reboot_mode(void)
+{
+ u32 reboot_mode;
+ char c;
+
+ reboot_mode = readl((u32 *)(OMAP34XX_SCRATCHPAD + 4));
+
+ c = (reboot_mode >> 24) & 0xff;
+ if (c != 'B')
+ return -1;
+
+ c = (reboot_mode >> 16) & 0xff;
+ if (c != 'M')
+ return -1;
+
+ c = reboot_mode & 0xff;
+
+ return c;
+}
+
+int omap_reboot_mode_clear(void)
+{
+ writel(0, (u32 *)(OMAP34XX_SCRATCHPAD + 4));
+
+ return 0;
+}
+
+int omap_reboot_mode_store(char c)
+{
+ u32 reboot_mode;
+
+ reboot_mode = 'B' << 24 | 'M' << 16 | c;
+
+ writel(reboot_mode, (u32 *)(OMAP34XX_SCRATCHPAD + 4));
+
+ return 0;
+}
diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c
index 9792761..a68947f 100644
--- a/arch/arm/cpu/armv7/omap4/hwinit.c
+++ b/arch/arm/cpu/armv7/omap4/hwinit.c
@@ -25,12 +25,12 @@
u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
static const struct gpio_bank gpio_bank_44xx[6] = {
- { (void *)OMAP44XX_GPIO1_BASE, METHOD_GPIO_24XX },
- { (void *)OMAP44XX_GPIO2_BASE, METHOD_GPIO_24XX },
- { (void *)OMAP44XX_GPIO3_BASE, METHOD_GPIO_24XX },
- { (void *)OMAP44XX_GPIO4_BASE, METHOD_GPIO_24XX },
- { (void *)OMAP44XX_GPIO5_BASE, METHOD_GPIO_24XX },
- { (void *)OMAP44XX_GPIO6_BASE, METHOD_GPIO_24XX },
+ { (void *)OMAP44XX_GPIO1_BASE },
+ { (void *)OMAP44XX_GPIO2_BASE },
+ { (void *)OMAP44XX_GPIO3_BASE },
+ { (void *)OMAP44XX_GPIO4_BASE },
+ { (void *)OMAP44XX_GPIO5_BASE },
+ { (void *)OMAP44XX_GPIO6_BASE },
};
const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx;
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
index 39f8d0d..3699050 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -27,18 +27,20 @@
u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
+#ifndef CONFIG_DM_GPIO
static struct gpio_bank gpio_bank_54xx[8] = {
- { (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX },
- { (void *)OMAP54XX_GPIO2_BASE, METHOD_GPIO_24XX },
- { (void *)OMAP54XX_GPIO3_BASE, METHOD_GPIO_24XX },
- { (void *)OMAP54XX_GPIO4_BASE, METHOD_GPIO_24XX },
- { (void *)OMAP54XX_GPIO5_BASE, METHOD_GPIO_24XX },
- { (void *)OMAP54XX_GPIO6_BASE, METHOD_GPIO_24XX },
- { (void *)OMAP54XX_GPIO7_BASE, METHOD_GPIO_24XX },
- { (void *)OMAP54XX_GPIO8_BASE, METHOD_GPIO_24XX },
+ { (void *)OMAP54XX_GPIO1_BASE },
+ { (void *)OMAP54XX_GPIO2_BASE },
+ { (void *)OMAP54XX_GPIO3_BASE },
+ { (void *)OMAP54XX_GPIO4_BASE },
+ { (void *)OMAP54XX_GPIO5_BASE },
+ { (void *)OMAP54XX_GPIO6_BASE },
+ { (void *)OMAP54XX_GPIO7_BASE },
+ { (void *)OMAP54XX_GPIO8_BASE },
};
const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
+#endif
void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size)
{
@@ -418,3 +420,20 @@
{
omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl);
}
+
+void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
+ u32 cpu_variant, u32 cpu_rev)
+{
+
+#ifdef CONFIG_ARM_ERRATA_801819
+ /*
+ * DRA72x processors are uniprocessors and DONOT have
+ * ACP (Accelerator Coherency Port) hooked to ACE (AXI Coherency
+ * Extensions) Hence the erratum workaround is not applicable for
+ * DRA72x processors.
+ */
+ if (is_dra72x())
+ acr &= ~((0x3 << 23) | (0x3 << 25));
+#endif
+ omap_smc1(OMAP5_SERVICE_ACR_SET, acr);
+}
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 1c7e6f0..b180944 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -187,6 +187,27 @@
skip_errata_798870:
#endif
+#ifdef CONFIG_ARM_ERRATA_801819
+ cmp r2, #0x24 @ Applies to lt including R2p4
+ bgt skip_errata_801819 @ skip if not affected rev
+ cmp r2, #0x20 @ Applies to including and above R2p0
+ blt skip_errata_801819 @ skip if not affected rev
+ mrc p15, 0, r0, c0, c0, 6 @ pick up REVIDR reg
+ and r0, r0, #1 << 3 @ check REVIDR[3]
+ cmp r0, #1 << 3
+ beq skip_errata_801819 @ skip erratum if REVIDR[3] is set
+
+ mrc p15, 0, r0, c1, c0, 1 @ read auxilary control register
+ orr r0, r0, #3 << 27 @ Disables streaming. All write-allocate
+ @ lines allocate in the L1 or L2 cache.
+ orr r0, r0, #3 << 25 @ Disables streaming. All write-allocate
+ @ lines allocate in the L1 cache.
+ push {r1-r5} @ Save the cpu info registers
+ bl v7_arch_cp15_set_acr
+ pop {r1-r5} @ Restore the cpu info - fall through
+skip_errata_801819:
+#endif
+
#ifdef CONFIG_ARM_ERRATA_454179
cmp r2, #0x21 @ Only on < r2p1
bge skip_errata_454179
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index 6466ebb..adb11b3 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -17,3 +17,4 @@
obj-$(CONFIG_FSL_LSCH3) += fsl-lsch3/
obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/
+obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index c22f7b6..835f6a6 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -180,14 +180,6 @@
{
}
-void invalidate_dcache_range(unsigned long start, unsigned long stop)
-{
-}
-
-void flush_dcache_range(unsigned long start, unsigned long stop)
-{
-}
-
void dcache_enable(void)
{
}
@@ -261,11 +253,3 @@
icache_enable();
dcache_enable();
}
-
-/*
- * Flush range from all levels of d-cache/unified-cache
- */
-void flush_cache(unsigned long start, unsigned long size)
-{
- flush_dcache_range(start, start + size);
-}
diff --git a/arch/arm/cpu/armv8/hisilicon/Makefile b/arch/arm/cpu/armv8/hisilicon/Makefile
new file mode 100644
index 0000000..2c9aefe
--- /dev/null
+++ b/arch/arm/cpu/armv8/hisilicon/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2015 Linaro
+# Peter Griffin <peter.griffin@linaro.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += pinmux.o
diff --git a/arch/arm/cpu/armv8/hisilicon/pinmux.c b/arch/arm/cpu/armv8/hisilicon/pinmux.c
new file mode 100644
index 0000000..3e4c9ce
--- /dev/null
+++ b/arch/arm/cpu/armv8/hisilicon/pinmux.c
@@ -0,0 +1,184 @@
+/*
+ * Copyright (C) 2015 Linaro.
+ * Peter Griffin <peter.griffin@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/pinmux.h>
+
+struct hi6220_pinmux0_regs *pmx0 =
+ (struct hi6220_pinmux0_regs *)HI6220_PINMUX0_BASE;
+
+struct hi6220_pinmux1_regs *pmx1 =
+ (struct hi6220_pinmux1_regs *)HI6220_PINMUX1_BASE;
+
+static void hi6220_uart_config(int peripheral)
+{
+ switch (peripheral) {
+ case PERIPH_ID_UART0:
+ writel(MUX_M0, &pmx0->iomg[48]); /* UART0_RXD */
+ writel(MUX_M0, &pmx0->iomg[49]); /* UART0_TXD */
+
+ writel(DRIVE1_02MA | PULL_UP, &pmx1->iocfg[49]); /* UART0_RXD */
+ writel(DRIVE1_02MA | PULL_UP, &pmx1->iocfg[50]); /* UART0_TXD */
+ break;
+
+ case PERIPH_ID_UART1:
+ writel(MUX_M0, &pmx0->iomg[50]); /* UART1_CTS_N */
+ writel(MUX_M0, &pmx0->iomg[51]); /* UART1_RTS_N */
+ writel(MUX_M0, &pmx0->iomg[52]); /* UART1_RXD */
+ writel(MUX_M0, &pmx0->iomg[53]); /* UART1_TXD */
+
+ writel(DRIVE1_02MA | PULL_UP, &pmx1->iocfg[51]); /*UART1_CTS_N*/
+ writel(DRIVE1_02MA | PULL_UP, &pmx1->iocfg[53]); /* UART1_RXD */
+ writel(DRIVE1_02MA, &pmx1->iocfg[52]); /* UART1_RTS_N */
+ writel(DRIVE1_02MA, &pmx1->iocfg[54]); /* UART1_TXD */
+ break;
+
+ case PERIPH_ID_UART2:
+ writel(MUX_M0, &pmx0->iomg[54]); /* UART2_CTS_N */
+ writel(MUX_M0, &pmx0->iomg[55]); /* UART2_RTS_N */
+ writel(MUX_M0, &pmx0->iomg[56]); /* UART2_RXD */
+ writel(MUX_M0, &pmx0->iomg[57]); /* UART2_TXD */
+
+ writel(DRIVE1_02MA, &pmx1->iocfg[55]); /* UART2_CTS_N */
+ writel(DRIVE1_02MA, &pmx1->iocfg[56]); /* UART2_RTS_N */
+ writel(DRIVE1_02MA, &pmx1->iocfg[57]); /* UART2_RXD */
+ writel(DRIVE1_02MA, &pmx1->iocfg[58]); /* UART2_TXD */
+ break;
+
+ case PERIPH_ID_UART3:
+ writel(MUX_M1, &pmx0->iomg[96]); /* UART3_CTS_N */
+ writel(MUX_M1, &pmx0->iomg[97]); /* UART3_RTS_N */
+ writel(MUX_M1, &pmx0->iomg[98]); /* UART3_RXD */
+ writel(MUX_M1, &pmx0->iomg[99]); /* UART3_TXD */
+
+ /* UART3_TXD */
+ writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[100]);
+ /* UART3_RTS_N */
+ writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[101]);
+ /* UART3_RXD */
+ writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[102]);
+ /* UART3_TXD */
+ writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[103]);
+ break;
+
+ case PERIPH_ID_UART4:
+ writel(MUX_M1, &pmx0->iomg[116]); /* UART4_CTS_N */
+ writel(MUX_M1, &pmx0->iomg[117]); /* UART4_RTS_N */
+ writel(MUX_M1, &pmx0->iomg[118]); /* UART4_RXD */
+ writel(MUX_M1, &pmx0->iomg[119]); /* UART4_TXD */
+
+ /* UART4_CTS_N */
+ writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[120]);
+ /* UART4_RTS_N */
+ writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[121]);
+ /* UART4_RXD */
+ writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[122]);
+ /* UART4_TXD */
+ writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[123]);
+ break;
+ case PERIPH_ID_UART5:
+ writel(MUX_M1, &pmx0->iomg[114]); /* UART5_RXD */
+ writel(MUX_M1, &pmx0->iomg[115]); /* UART5_TXD */
+
+ /* UART5_RXD */
+ writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[118]);
+ /* UART5_TXD */
+ writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[119]);
+
+ break;
+
+ default:
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return;
+ }
+}
+
+static int hi6220_mmc_config(int peripheral)
+{
+ u32 tmp;
+
+ switch (peripheral) {
+ case PERIPH_ID_SDMMC0:
+
+ /* eMMC pinmux config */
+ writel(MUX_M0, &pmx0->iomg[64]); /* EMMC_CLK */
+ writel(MUX_M0, &pmx0->iomg[65]); /* EMMC_CMD */
+ writel(MUX_M0, &pmx0->iomg[66]); /* EMMC_DATA0 */
+ writel(MUX_M0, &pmx0->iomg[67]); /* EMMC_DATA1 */
+ writel(MUX_M0, &pmx0->iomg[68]); /* EMMC_DATA2 */
+ writel(MUX_M0, &pmx0->iomg[69]); /* EMMC_DATA3 */
+ writel(MUX_M0, &pmx0->iomg[70]); /* EMMC_DATA4 */
+ writel(MUX_M0, &pmx0->iomg[71]); /* EMMC_DATA5 */
+ writel(MUX_M0, &pmx0->iomg[72]); /* EMMC_DATA6 */
+ writel(MUX_M0, &pmx0->iomg[73]); /* EMMC_DATA7 */
+
+ /*eMMC configure up/down/drive */
+ writel(DRIVE1_08MA, &pmx1->iocfg[65]); /* EMMC_CLK */
+
+ tmp = DRIVE1_04MA | PULL_UP;
+ writel(tmp, &pmx1->iocfg[65]); /* EMMC_CMD */
+ writel(tmp, &pmx1->iocfg[66]); /* EMMC_DATA0 */
+ writel(tmp, &pmx1->iocfg[67]); /* EMMC_DATA1 */
+ writel(tmp, &pmx1->iocfg[68]); /* EMMC_DATA2 */
+ writel(tmp, &pmx1->iocfg[69]); /* EMMC_DATA3 */
+ writel(tmp, &pmx1->iocfg[70]); /* EMMC_DATA4 */
+ writel(tmp, &pmx1->iocfg[71]); /* EMMC_DATA5 */
+ writel(tmp, &pmx1->iocfg[72]); /* EMMC_DATA6 */
+ writel(tmp, &pmx1->iocfg[73]); /* EMMC_DATA7 */
+
+ writel(DRIVE1_04MA, &pmx1->iocfg[73]); /* EMMC_RST_N */
+ break;
+
+ case PERIPH_ID_SDMMC1:
+
+ writel(MUX_M0, &pmx0->iomg[3]); /* SD_CLK */
+ writel(MUX_M0, &pmx0->iomg[4]); /* SD_CMD */
+ writel(MUX_M0, &pmx0->iomg[5]); /* SD_DATA0 */
+ writel(MUX_M0, &pmx0->iomg[6]); /* SD_DATA1 */
+ writel(MUX_M0, &pmx0->iomg[7]); /* SD_DATA2 */
+ writel(MUX_M0, &pmx0->iomg[8]); /* SD_DATA3 */
+
+ writel(DRIVE1_10MA | BIT(2), &pmx1->iocfg[3]); /*SD_CLK*/
+ writel(DRIVE1_08MA | BIT(2), &pmx1->iocfg[4]); /*SD_CMD*/
+ writel(DRIVE1_08MA | BIT(2), &pmx1->iocfg[5]); /*SD_DATA0*/
+ writel(DRIVE1_08MA | BIT(2), &pmx1->iocfg[6]); /*SD_DATA1*/
+ writel(DRIVE1_08MA | BIT(2), &pmx1->iocfg[7]); /*SD_DATA2*/
+ writel(DRIVE1_08MA | BIT(2), &pmx1->iocfg[8]); /*SD_DATA3*/
+ break;
+
+ default:
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return -1;
+ }
+
+ return 0;
+}
+
+int hi6220_pinmux_config(int peripheral)
+{
+ switch (peripheral) {
+ case PERIPH_ID_UART0:
+ case PERIPH_ID_UART1:
+ case PERIPH_ID_UART2:
+ case PERIPH_ID_UART3:
+ hi6220_uart_config(peripheral);
+ break;
+ case PERIPH_ID_SDMMC0:
+ case PERIPH_ID_SDMMC1:
+ return hi6220_mmc_config(peripheral);
+ default:
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return -1;
+ }
+
+ return 0;
+}
+
+
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3aaeb6a..ff86891 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -52,12 +52,13 @@
zynq-zc770-xm011.dtb \
zynq-zc770-xm012.dtb \
zynq-zc770-xm013.dtb
-dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb
+dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_arria5_socdk.dtb \
socfpga_cyclone5_socdk.dtb \
socfpga_cyclone5_socrates.dtb
+dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb
dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \
diff --git a/arch/arm/dts/am335x-bone-common.dtsi b/arch/arm/dts/am335x-bone-common.dtsi
index e70b4d1..fec7834 100644
--- a/arch/arm/dts/am335x-bone-common.dtsi
+++ b/arch/arm/dts/am335x-bone-common.dtsi
@@ -7,13 +7,6 @@
*/
/ {
- model = "TI AM335x BeagleBone";
- compatible = "ti,am335x-bone", "ti,am33xx";
-
- chosen {
- stdout-path = &uart0;
- };
-
cpus {
cpu@0 {
cpu0-supply = <&dcdc2_reg>;
@@ -25,184 +18,299 @@
reg = <0x80000000 0x10000000>; /* 256 MB */
};
- am33xx_pinmux: pinmux@44e10800 {
+ leds {
pinctrl-names = "default";
- pinctrl-0 = <&clkout2_pin>;
+ pinctrl-0 = <&user_leds_s0>;
- user_leds_s0: user_leds_s0 {
- pinctrl-single,pins = <
- 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
- 0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */
- 0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */
- 0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */
- >;
- };
+ compatible = "gpio-leds";
- i2c0_pins: pinmux_i2c0_pins {
- pinctrl-single,pins = <
- 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
- 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
- >;
+ led@2 {
+ label = "beaglebone:green:heartbeat";
+ gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
};
- uart0_pins: pinmux_uart0_pins {
- pinctrl-single,pins = <
- 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
- 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
- >;
+ led@3 {
+ label = "beaglebone:green:mmc0";
+ gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc0";
+ default-state = "off";
};
- clkout2_pin: pinmux_clkout2_pin {
- pinctrl-single,pins = <
- 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
- >;
+ led@4 {
+ label = "beaglebone:green:usr2";
+ gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "cpu0";
+ default-state = "off";
};
- cpsw_default: cpsw_default {
- pinctrl-single,pins = <
- /* Slave 1 */
- 0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */
- 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */
- 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
- 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
- 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
- 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
- 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
- 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */
- 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
- 0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */
- 0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */
- 0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */
- 0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
- >;
+ led@5 {
+ label = "beaglebone:green:usr3";
+ gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc1";
+ default-state = "off";
};
+ };
- cpsw_sleep: cpsw_sleep {
- pinctrl-single,pins = <
- /* Slave 1 reset value */
- 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
- 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
- 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
- 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
- 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
- 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
- 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
- 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
- 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
- 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
- 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
- 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
- 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
- >;
- };
+ vmmcsd_fixed: fixedregulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vmmcsd_fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
- davinci_mdio_default: davinci_mdio_default {
- pinctrl-single,pins = <
- /* MDIO */
- 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
- 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
- >;
- };
+&am33xx_pinmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&clkout2_pin>;
- davinci_mdio_sleep: davinci_mdio_sleep {
- pinctrl-single,pins = <
- /* MDIO reset value */
- 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
- 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
- >;
- };
+ user_leds_s0: user_leds_s0 {
+ pinctrl-single,pins = <
+ 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
+ 0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */
+ 0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */
+ 0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */
+ >;
};
- ocp {
- uart0: serial@44e09000 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins>;
+ i2c0_pins: pinmux_i2c0_pins {
+ pinctrl-single,pins = <
+ 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
+ 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
+ >;
+ };
- status = "okay";
- };
+ i2c2_pins: pinmux_i2c2_pins {
+ pinctrl-single,pins = <
+ 0x178 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.i2c2_sda */
+ 0x17c (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.i2c2_scl */
+ >;
+ };
- musb: usb@47400000 {
- status = "okay";
+ uart0_pins: pinmux_uart0_pins {
+ pinctrl-single,pins = <
+ 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
+ 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
+ >;
+ };
- control@44e10000 {
- status = "okay";
- };
+ clkout2_pin: pinmux_clkout2_pin {
+ pinctrl-single,pins = <
+ 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
+ >;
+ };
- usb-phy@47401300 {
- status = "okay";
- };
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins = <
+ /* Slave 1 */
+ 0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */
+ 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */
+ 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
+ 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
+ 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
+ 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
+ 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
+ 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */
+ 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
+ 0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */
+ 0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */
+ 0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */
+ 0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
+ >;
+ };
- usb-phy@47401b00 {
- status = "okay";
- };
+ cpsw_sleep: cpsw_sleep {
+ pinctrl-single,pins = <
+ /* Slave 1 reset value */
+ 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
- usb@47401000 {
- status = "okay";
- };
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins = <
+ /* MDIO */
+ 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
+ 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
+ >;
+ };
- usb@47401800 {
- status = "okay";
- dr_mode = "host";
- };
+ davinci_mdio_sleep: davinci_mdio_sleep {
+ pinctrl-single,pins = <
+ /* MDIO reset value */
+ 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
- dma-controller@07402000 {
- status = "okay";
- };
- };
+ mmc1_pins: pinmux_mmc1_pins {
+ pinctrl-single,pins = <
+ 0x160 (PIN_INPUT | MUX_MODE7) /* GPIO0_6 */
+ >;
+ };
+
+ emmc_pins: pinmux_emmc_pins {
+ pinctrl-single,pins = <
+ 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
+ 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
+ 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
+ 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
+ 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
+ 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
+ 0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
+ 0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
+ 0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
+ 0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
+ >;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
- i2c0: i2c@44e0b000 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins>;
+ status = "okay";
+};
- status = "okay";
- clock-frequency = <400000>;
+&usb {
+ status = "okay";
+};
- tps: tps@24 {
- reg = <0x24>;
- };
+&usb_ctrl_mod {
+ status = "okay";
+};
+&usb0_phy {
+ status = "okay";
+};
+
+&usb1_phy {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "peripheral";
+};
+
+&usb1 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&cppi41dma {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tps: tps@24 {
+ reg = <0x24>;
+ };
+
+ baseboard_eeprom: baseboard_eeprom@50 {
+ compatible = "at,24c256";
+ reg = <0x50>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ baseboard_data: baseboard_data@0 {
+ reg = <0 0x100>;
};
};
+};
- leds {
- pinctrl-names = "default";
- pinctrl-0 = <&user_leds_s0>;
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
- compatible = "gpio-leds";
+ status = "okay";
+ clock-frequency = <100000>;
- led@2 {
- label = "beaglebone:green:heartbeat";
- gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- default-state = "off";
+ cape_eeprom0: cape_eeprom0@54 {
+ compatible = "at,24c256";
+ reg = <0x54>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cape0_data: cape_data@0 {
+ reg = <0 0x100>;
};
+ };
- led@3 {
- label = "beaglebone:green:mmc0";
- gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "mmc0";
- default-state = "off";
+ cape_eeprom1: cape_eeprom1@55 {
+ compatible = "at,24c256";
+ reg = <0x55>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cape1_data: cape_data@0 {
+ reg = <0 0x100>;
};
+ };
- led@4 {
- label = "beaglebone:green:usr2";
- gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
- default-state = "off";
+ cape_eeprom2: cape_eeprom2@56 {
+ compatible = "at,24c256";
+ reg = <0x56>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cape2_data: cape_data@0 {
+ reg = <0 0x100>;
};
+ };
- led@5 {
- label = "beaglebone:green:usr3";
- gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
- default-state = "off";
+ cape_eeprom3: cape_eeprom3@57 {
+ compatible = "at,24c256";
+ reg = <0x57>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cape3_data: cape_data@0 {
+ reg = <0 0x100>;
};
};
};
+
/include/ "tps65217.dtsi"
&tps {
+ /*
+ * Configure pmic to enter OFF-state instead of SLEEP-state ("RTC-only
+ * mode") at poweroff. Most BeagleBone versions do not support RTC-only
+ * mode and risk hardware damage if this mode is entered.
+ *
+ * For details, see linux-omap mailing list May 2015 thread
+ * [PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller
+ * In particular, messages:
+ * http://www.spinics.net/lists/linux-omap/msg118585.html
+ * http://www.spinics.net/lists/linux-omap/msg118615.html
+ *
+ * You can override this later with
+ * &tps { /delete-property/ ti,pmic-shutdown-controller; }
+ * if you want to use RTC-only mode and made sure you are not affected
+ * by the hardware problems. (Tip: double-check by performing a current
+ * measurement after shutdown: it should be less than 1 mA.)
+ */
+ ti,pmic-shutdown-controller;
+
regulators {
dcdc1_reg: regulator@0 {
+ regulator-name = "vdds_dpr";
regulator-always-on;
};
@@ -225,18 +333,22 @@
};
ldo1_reg: regulator@3 {
+ regulator-name = "vio,vrtc,vdds";
regulator-always-on;
};
ldo2_reg: regulator@4 {
+ regulator-name = "vdd_3v3aux";
regulator-always-on;
};
ldo3_reg: regulator@5 {
+ regulator-name = "vdd_1v8";
regulator-always-on;
};
ldo4_reg: regulator@6 {
+ regulator-name = "vdd_3v3a";
regulator-always-on;
};
};
@@ -256,11 +368,29 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
-
+ status = "okay";
};
&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
+ status = "okay";
+};
+
+&mmc1 {
+ status = "okay";
+ bus-width = <0x4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+};
+
+&aes {
+ status = "okay";
+};
+
+&sham {
+ status = "okay";
};
diff --git a/arch/arm/dts/am335x-bone.dts b/arch/arm/dts/am335x-bone.dts
new file mode 100644
index 0000000..81441cc
--- /dev/null
+++ b/arch/arm/dts/am335x-bone.dts
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "am33xx.dtsi"
+#include "am335x-bone-common.dtsi"
+
+/ {
+ model = "TI AM335x BeagleBone";
+ compatible = "ti,am335x-bone", "ti,am33xx";
+ chosen {
+ stdout-path = &uart0;
+ };
+};
+
+&ldo3_reg {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+};
+
+&mmc1 {
+ vmmc-supply = <&ldo3_reg>;
+};
diff --git a/arch/arm/dts/am335x-boneblack.dts b/arch/arm/dts/am335x-boneblack.dts
index 197cadf..679248a 100644
--- a/arch/arm/dts/am335x-boneblack.dts
+++ b/arch/arm/dts/am335x-boneblack.dts
@@ -10,8 +10,80 @@
#include "am33xx.dtsi"
#include "am335x-bone-common.dtsi"
+/ {
+ model = "TI AM335x BeagleBone Black";
+ compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
+ chosen {
+ stdout-path = &uart0;
+ };
+};
+
&ldo3_reg {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
+
+&mmc1 {
+ vmmc-supply = <&vmmcsd_fixed>;
+};
+
+&mmc2 {
+ vmmc-supply = <&vmmcsd_fixed>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_pins>;
+ bus-width = <8>;
+ status = "okay";
+};
+
+&am33xx_pinmux {
+ nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins {
+ pinctrl-single,pins = <
+ 0x1b0 0x03 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
+ 0xa0 0x08 /* lcd_data0.lcd_data0, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+ 0xa4 0x08 /* lcd_data1.lcd_data1, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+ 0xa8 0x08 /* lcd_data2.lcd_data2, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+ 0xac 0x08 /* lcd_data3.lcd_data3, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+ 0xb0 0x08 /* lcd_data4.lcd_data4, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+ 0xb4 0x08 /* lcd_data5.lcd_data5, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+ 0xb8 0x08 /* lcd_data6.lcd_data6, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+ 0xbc 0x08 /* lcd_data7.lcd_data7, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+ 0xc0 0x08 /* lcd_data8.lcd_data8, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+ 0xc4 0x08 /* lcd_data9.lcd_data9, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+ 0xc8 0x08 /* lcd_data10.lcd_data10, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+ 0xcc 0x08 /* lcd_data11.lcd_data11, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+ 0xd0 0x08 /* lcd_data12.lcd_data12, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+ 0xd4 0x08 /* lcd_data13.lcd_data13, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+ 0xd8 0x08 /* lcd_data14.lcd_data14, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+ 0xdc 0x08 /* lcd_data15.lcd_data15, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+ 0xe0 0x00 /* lcd_vsync.lcd_vsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
+ 0xe4 0x00 /* lcd_hsync.lcd_hsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
+ 0xe8 0x00 /* lcd_pclk.lcd_pclk, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
+ 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
+ >;
+ };
+ nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins {
+ pinctrl-single,pins = <
+ 0x1b0 0x03 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
+ >;
+ };
+};
+
+&lcdc {
+ status = "okay";
+};
+
+/ {
+ hdmi {
+ compatible = "ti,tilcdc,slave";
+ i2c = <&i2c0>;
+ pinctrl-names = "default", "off";
+ pinctrl-0 = <&nxp_hdmi_bonelt_pins>;
+ pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>;
+ status = "okay";
+ };
+};
+
+&rtc {
+ system-power-controller;
+};
diff --git a/arch/arm/dts/am335x-evm.dts b/arch/arm/dts/am335x-evm.dts
new file mode 100644
index 0000000..e1c5d4f
--- /dev/null
+++ b/arch/arm/dts/am335x-evm.dts
@@ -0,0 +1,765 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "am33xx.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ model = "TI AM335x EVM";
+ compatible = "ti,am335x-evm", "ti,am33xx";
+
+ chosen {
+ stdout-path = &uart0;
+ };
+
+ cpus {
+ cpu@0 {
+ cpu0-supply = <&vdd1_reg>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>; /* 256 MB */
+ };
+
+ vbat: fixedregulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vbat";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ };
+
+ lis3_reg: fixedregulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "lis3_reg";
+ regulator-boot-on;
+ };
+
+ wlan_en_reg: fixedregulator@2 {
+ compatible = "regulator-fixed";
+ regulator-name = "wlan-en-regulator";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ /* WLAN_EN GPIO for this board - Bank1, pin16 */
+ gpio = <&gpio1 16 0>;
+
+ /* WLAN card specific delay */
+ startup-delay-us = <70000>;
+ enable-active-high;
+ };
+
+ matrix_keypad: matrix_keypad@0 {
+ compatible = "gpio-matrix-keypad";
+ debounce-delay-ms = <5>;
+ col-scan-delay-us = <2>;
+
+ row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */
+ &gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */
+ &gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */
+
+ col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */
+ &gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */
+
+ linux,keymap = <0x0000008b /* MENU */
+ 0x0100009e /* BACK */
+ 0x02000069 /* LEFT */
+ 0x0001006a /* RIGHT */
+ 0x0101001c /* ENTER */
+ 0x0201006c>; /* DOWN */
+ };
+
+ gpio_keys: volume_keys@0 {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+
+ switch@9 {
+ label = "volume-up";
+ linux,code = <115>;
+ gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+ gpio-key,wakeup;
+ };
+
+ switch@10 {
+ label = "volume-down";
+ linux,code = <114>;
+ gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
+ gpio-key,wakeup;
+ };
+ };
+
+ backlight {
+ compatible = "pwm-backlight";
+ pwms = <&ecap0 0 50000 0>;
+ brightness-levels = <0 51 53 56 62 75 101 152 255>;
+ default-brightness-level = <8>;
+ };
+
+ panel {
+ compatible = "ti,tilcdc,panel";
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_pins_s0>;
+ panel-info {
+ ac-bias = <255>;
+ ac-bias-intrpt = <0>;
+ dma-burst-sz = <16>;
+ bpp = <32>;
+ fdd = <0x80>;
+ sync-edge = <0>;
+ sync-ctrl = <1>;
+ raster-order = <0>;
+ fifo-th = <0>;
+ };
+
+ display-timings {
+ 800x480p62 {
+ clock-frequency = <30000000>;
+ hactive = <800>;
+ vactive = <480>;
+ hfront-porch = <39>;
+ hback-porch = <39>;
+ hsync-len = <47>;
+ vback-porch = <29>;
+ vfront-porch = <13>;
+ vsync-len = <2>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ };
+ };
+ };
+
+ sound {
+ compatible = "ti,da830-evm-audio";
+ ti,model = "AM335x-EVM";
+ ti,audio-codec = <&tlv320aic3106>;
+ ti,mcasp-controller = <&mcasp1>;
+ ti,codec-clock-rate = <12000000>;
+ ti,audio-routing =
+ "Headphone Jack", "HPLOUT",
+ "Headphone Jack", "HPROUT",
+ "LINE1L", "Line In",
+ "LINE1R", "Line In";
+ };
+};
+
+&am33xx_pinmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>;
+
+ matrix_keypad_s0: matrix_keypad_s0 {
+ pinctrl-single,pins = <
+ 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
+ 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */
+ 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */
+ 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */
+ 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */
+ >;
+ };
+
+ volume_keys_s0: volume_keys_s0 {
+ pinctrl-single,pins = <
+ 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */
+ 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */
+ >;
+ };
+
+ i2c0_pins: pinmux_i2c0_pins {
+ pinctrl-single,pins = <
+ 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
+ 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
+ >;
+ };
+
+ i2c1_pins: pinmux_i2c1_pins {
+ pinctrl-single,pins = <
+ 0x158 (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */
+ 0x15c (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */
+ >;
+ };
+
+ uart0_pins: pinmux_uart0_pins {
+ pinctrl-single,pins = <
+ 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
+ 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
+ >;
+ };
+
+ uart1_pins: pinmux_uart1_pins {
+ pinctrl-single,pins = <
+ 0x178 (PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */
+ 0x17C (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */
+ 0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
+ 0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
+ >;
+ };
+
+ clkout2_pin: pinmux_clkout2_pin {
+ pinctrl-single,pins = <
+ 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
+ >;
+ };
+
+ nandflash_pins_s0: nandflash_pins_s0 {
+ pinctrl-single,pins = <
+ 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
+ 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
+ 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
+ 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
+ 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
+ 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
+ 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
+ 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
+ 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
+ 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
+ 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
+ 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
+ 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
+ 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
+ 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
+ >;
+ };
+
+ ecap0_pins: backlight_pins {
+ pinctrl-single,pins = <
+ 0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
+ >;
+ };
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins = <
+ /* Slave 1 */
+ 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
+ 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
+ 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
+ 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
+ 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
+ 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
+ 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
+ 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
+ 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
+ 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
+ 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
+ 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
+ >;
+ };
+
+ cpsw_sleep: cpsw_sleep {
+ pinctrl-single,pins = <
+ /* Slave 1 reset value */
+ 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins = <
+ /* MDIO */
+ 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
+ 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
+ >;
+ };
+
+ davinci_mdio_sleep: davinci_mdio_sleep {
+ pinctrl-single,pins = <
+ /* MDIO reset value */
+ 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+
+ mmc1_pins: pinmux_mmc1_pins {
+ pinctrl-single,pins = <
+ 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
+ >;
+ };
+
+ mmc3_pins: pinmux_mmc3_pins {
+ pinctrl-single,pins = <
+ 0x44 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */
+ 0x48 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */
+ 0x4C (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */
+ 0x78 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */
+ 0x88 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */
+ 0x8C (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */
+ >;
+ };
+
+ wlan_pins: pinmux_wlan_pins {
+ pinctrl-single,pins = <
+ 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 */
+ 0x19C (PIN_INPUT | MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */
+ 0x1AC (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 */
+ >;
+ };
+
+ lcd_pins_s0: lcd_pins_s0 {
+ pinctrl-single,pins = <
+ 0x20 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */
+ 0x24 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */
+ 0x28 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */
+ 0x2c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */
+ 0x30 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */
+ 0x34 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */
+ 0x38 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */
+ 0x3c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */
+ 0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
+ 0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
+ 0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
+ 0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
+ 0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
+ 0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
+ 0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
+ 0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
+ 0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
+ 0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
+ 0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
+ 0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
+ 0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
+ 0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
+ 0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
+ 0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
+ 0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */
+ 0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */
+ 0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */
+ 0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
+ >;
+ };
+
+ am335x_evm_audio_pins: am335x_evm_audio_pins {
+ pinctrl-single,pins = <
+ 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
+ 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
+ 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
+ 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
+ >;
+ };
+
+ dcan1_pins_default: dcan1_pins_default {
+ pinctrl-single,pins = <
+ 0x168 (PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.d_can1_tx */
+ 0x16c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart0_rtsn.d_can1_rx */
+ >;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tps: tps@2d {
+ reg = <0x2d>;
+ };
+};
+
+&usb {
+ status = "okay";
+};
+
+&usb_ctrl_mod {
+ status = "okay";
+};
+
+&usb0_phy {
+ status = "okay";
+};
+
+&usb1_phy {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&cppi41dma {
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+
+ status = "okay";
+ clock-frequency = <100000>;
+
+ lis331dlh: lis331dlh@18 {
+ compatible = "st,lis331dlh", "st,lis3lv02d";
+ reg = <0x18>;
+ Vdd-supply = <&lis3_reg>;
+ Vdd_IO-supply = <&lis3_reg>;
+
+ st,click-single-x;
+ st,click-single-y;
+ st,click-single-z;
+ st,click-thresh-x = <10>;
+ st,click-thresh-y = <10>;
+ st,click-thresh-z = <10>;
+ st,irq1-click;
+ st,irq2-click;
+ st,wakeup-x-lo;
+ st,wakeup-x-hi;
+ st,wakeup-y-lo;
+ st,wakeup-y-hi;
+ st,wakeup-z-lo;
+ st,wakeup-z-hi;
+ st,min-limit-x = <120>;
+ st,min-limit-y = <120>;
+ st,min-limit-z = <140>;
+ st,max-limit-x = <550>;
+ st,max-limit-y = <550>;
+ st,max-limit-z = <750>;
+ };
+
+ tsl2550: tsl2550@39 {
+ compatible = "taos,tsl2550";
+ reg = <0x39>;
+ };
+
+ tmp275: tmp275@48 {
+ compatible = "ti,tmp275";
+ reg = <0x48>;
+ };
+
+ tlv320aic3106: tlv320aic3106@1b {
+ compatible = "ti,tlv320aic3106";
+ reg = <0x1b>;
+ status = "okay";
+
+ /* Regulators */
+ AVDD-supply = <&vaux2_reg>;
+ IOVDD-supply = <&vaux2_reg>;
+ DRVDD-supply = <&vaux2_reg>;
+ DVDD-supply = <&vbat>;
+ };
+};
+
+&lcdc {
+ status = "okay";
+};
+
+&elm {
+ status = "okay";
+};
+
+&epwmss0 {
+ status = "okay";
+
+ ecap0: ecap@48300100 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&ecap0_pins>;
+ };
+};
+
+&gpmc {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&nandflash_pins_s0>;
+ ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
+ nand@0,0 {
+ reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+ ti,nand-ecc-opt = "bch8";
+ ti,elm-id = <&elm>;
+ nand-bus-width = <8>;
+ gpmc,device-width = <1>;
+ gpmc,sync-clk-ps = <0>;
+ gpmc,cs-on-ns = <0>;
+ gpmc,cs-rd-off-ns = <44>;
+ gpmc,cs-wr-off-ns = <44>;
+ gpmc,adv-on-ns = <6>;
+ gpmc,adv-rd-off-ns = <34>;
+ gpmc,adv-wr-off-ns = <44>;
+ gpmc,we-on-ns = <0>;
+ gpmc,we-off-ns = <40>;
+ gpmc,oe-on-ns = <0>;
+ gpmc,oe-off-ns = <54>;
+ gpmc,access-ns = <64>;
+ gpmc,rd-cycle-ns = <82>;
+ gpmc,wr-cycle-ns = <82>;
+ gpmc,wait-on-read = "true";
+ gpmc,wait-on-write = "true";
+ gpmc,bus-turnaround-ns = <0>;
+ gpmc,cycle2cycle-delay-ns = <0>;
+ gpmc,clk-activation-ns = <0>;
+ gpmc,wait-monitoring-ns = <0>;
+ gpmc,wr-access-ns = <40>;
+ gpmc,wr-data-mux-bus-ns = <0>;
+ /* MTD partition table */
+ /* All SPL-* partitions are sized to minimal length
+ * which can be independently programmable. For
+ * NAND flash this is equal to size of erase-block */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "NAND.SPL";
+ reg = <0x00000000 0x000020000>;
+ };
+ partition@1 {
+ label = "NAND.SPL.backup1";
+ reg = <0x00020000 0x00020000>;
+ };
+ partition@2 {
+ label = "NAND.SPL.backup2";
+ reg = <0x00040000 0x00020000>;
+ };
+ partition@3 {
+ label = "NAND.SPL.backup3";
+ reg = <0x00060000 0x00020000>;
+ };
+ partition@4 {
+ label = "NAND.u-boot-spl-os";
+ reg = <0x00080000 0x00040000>;
+ };
+ partition@5 {
+ label = "NAND.u-boot";
+ reg = <0x000C0000 0x00100000>;
+ };
+ partition@6 {
+ label = "NAND.u-boot-env";
+ reg = <0x001C0000 0x00020000>;
+ };
+ partition@7 {
+ label = "NAND.u-boot-env.backup1";
+ reg = <0x001E0000 0x00020000>;
+ };
+ partition@8 {
+ label = "NAND.kernel";
+ reg = <0x00200000 0x00800000>;
+ };
+ partition@9 {
+ label = "NAND.file-system";
+ reg = <0x00A00000 0x0F600000>;
+ };
+ };
+};
+
+#include "tps65910.dtsi"
+
+&mcasp1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&am335x_evm_audio_pins>;
+
+ status = "okay";
+
+ op-mode = <0>; /* MCASP_IIS_MODE */
+ tdm-slots = <2>;
+ /* 4 serializers */
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 0 0 1 2
+ >;
+ tx-num-evt = <32>;
+ rx-num-evt = <32>;
+};
+
+&tps {
+ vcc1-supply = <&vbat>;
+ vcc2-supply = <&vbat>;
+ vcc3-supply = <&vbat>;
+ vcc4-supply = <&vbat>;
+ vcc5-supply = <&vbat>;
+ vcc6-supply = <&vbat>;
+ vcc7-supply = <&vbat>;
+ vccio-supply = <&vbat>;
+
+ regulators {
+ vrtc_reg: regulator@0 {
+ regulator-always-on;
+ };
+
+ vio_reg: regulator@1 {
+ regulator-always-on;
+ };
+
+ vdd1_reg: regulator@2 {
+ /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
+ regulator-name = "vdd_mpu";
+ regulator-min-microvolt = <912500>;
+ regulator-max-microvolt = <1312500>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd2_reg: regulator@3 {
+ /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+ regulator-name = "vdd_core";
+ regulator-min-microvolt = <912500>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd3_reg: regulator@4 {
+ regulator-always-on;
+ };
+
+ vdig1_reg: regulator@5 {
+ regulator-always-on;
+ };
+
+ vdig2_reg: regulator@6 {
+ regulator-always-on;
+ };
+
+ vpll_reg: regulator@7 {
+ regulator-always-on;
+ };
+
+ vdac_reg: regulator@8 {
+ regulator-always-on;
+ };
+
+ vaux1_reg: regulator@9 {
+ regulator-always-on;
+ };
+
+ vaux2_reg: regulator@10 {
+ regulator-always-on;
+ };
+
+ vaux33_reg: regulator@11 {
+ regulator-always-on;
+ };
+
+ vmmc_reg: regulator@12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+};
+
+&mac {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&cpsw_default>;
+ pinctrl-1 = <&cpsw_sleep>;
+ status = "okay";
+};
+
+&davinci_mdio {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&davinci_mdio_default>;
+ pinctrl-1 = <&davinci_mdio_sleep>;
+ status = "okay";
+};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <0>;
+ phy-mode = "rgmii-txid";
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <1>;
+ phy-mode = "rgmii-txid";
+};
+
+&tscadc {
+ status = "okay";
+ tsc {
+ ti,wires = <4>;
+ ti,x-plate-resistance = <200>;
+ ti,coordinate-readouts = <5>;
+ ti,wire-config = <0x00 0x11 0x22 0x33>;
+ ti,charge-delay = <0x400>;
+ };
+
+ adc {
+ ti,adc-channels = <4 5 6 7>;
+ };
+};
+
+&mmc1 {
+ status = "okay";
+ vmmc-supply = <&vmmc_reg>;
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+};
+
+&mmc3 {
+ /* these are on the crossbar and are outlined in the
+ xbar-event-map element */
+ dmas = <&edma 12
+ &edma 13>;
+ dma-names = "tx", "rx";
+ status = "okay";
+ vmmc-supply = <&wlan_en_reg>;
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc3_pins &wlan_pins>;
+ ti,non-removable;
+ ti,needs-special-hs-handling;
+ cap-power-off-card;
+ keep-power-in-suspend;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ wlcore: wlcore@0 {
+ compatible = "ti,wl1835";
+ reg = <2>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
+
+&edma {
+ ti,edma-xbar-event-map = /bits/ 16 <1 12
+ 2 13>;
+};
+
+&sham {
+ status = "okay";
+};
+
+&aes {
+ status = "okay";
+};
+
+&dcan1 {
+ status = "disabled"; /* Enable only if Profile 1 is selected */
+ pinctrl-names = "default";
+ pinctrl-0 = <&dcan1_pins_default>;
+};
diff --git a/arch/arm/dts/am33xx-clocks.dtsi b/arch/arm/dts/am33xx-clocks.dtsi
new file mode 100644
index 0000000..afb4b3a
--- /dev/null
+++ b/arch/arm/dts/am33xx-clocks.dtsi
@@ -0,0 +1,646 @@
+/*
+ * Device Tree Source for AM33xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&scm_clocks {
+ sys_clkin_ck: sys_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
+ ti,bit-shift = <22>;
+ reg = <0x0040>;
+ };
+
+ adc_tsc_fck: adc_tsc_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ dcan0_fck: dcan0_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ dcan1_fck: dcan1_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ mcasp0_fck: mcasp0_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ mcasp1_fck: mcasp1_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ smartreflex0_fck: smartreflex0_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ smartreflex1_fck: smartreflex1_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ sha0_fck: sha0_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ aes0_fck: aes0_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ rng_fck: rng_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l4ls_gclk>;
+ ti,bit-shift = <0>;
+ reg = <0x0664>;
+ };
+
+ ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l4ls_gclk>;
+ ti,bit-shift = <1>;
+ reg = <0x0664>;
+ };
+
+ ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l4ls_gclk>;
+ ti,bit-shift = <2>;
+ reg = <0x0664>;
+ };
+};
+&prcm_clocks {
+ clk_32768_ck: clk_32768_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ clk_rc32k_ck: clk_rc32k_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ };
+
+ virt_19200000_ck: virt_19200000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <19200000>;
+ };
+
+ virt_24000000_ck: virt_24000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+
+ virt_25000000_ck: virt_25000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ };
+
+ virt_26000000_ck: virt_26000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+ };
+
+ tclkin_ck: tclkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+ };
+
+ dpll_core_ck: dpll_core_ck {
+ #clock-cells = <0>;
+ compatible = "ti,am3-dpll-core-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x0490>, <0x045c>, <0x0468>;
+ };
+
+ dpll_core_x2_ck: dpll_core_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,am3-dpll-x2-clock";
+ clocks = <&dpll_core_ck>;
+ };
+
+ dpll_core_m4_ck: dpll_core_m4_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <31>;
+ reg = <0x0480>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_core_m5_ck: dpll_core_m5_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <31>;
+ reg = <0x0484>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_core_m6_ck: dpll_core_m6_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <31>;
+ reg = <0x04d8>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_mpu_ck: dpll_mpu_ck {
+ #clock-cells = <0>;
+ compatible = "ti,am3-dpll-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x0488>, <0x0420>, <0x042c>;
+ };
+
+ dpll_mpu_m2_ck: dpll_mpu_m2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_mpu_ck>;
+ ti,max-div = <31>;
+ reg = <0x04a8>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_ddr_ck: dpll_ddr_ck {
+ #clock-cells = <0>;
+ compatible = "ti,am3-dpll-no-gate-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x0494>, <0x0434>, <0x0440>;
+ };
+
+ dpll_ddr_m2_ck: dpll_ddr_m2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_ddr_ck>;
+ ti,max-div = <31>;
+ reg = <0x04a0>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_ddr_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ dpll_disp_ck: dpll_disp_ck {
+ #clock-cells = <0>;
+ compatible = "ti,am3-dpll-no-gate-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x0498>, <0x0448>, <0x0454>;
+ };
+
+ dpll_disp_m2_ck: dpll_disp_m2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_disp_ck>;
+ ti,max-div = <31>;
+ reg = <0x04a4>;
+ ti,index-starts-at-one;
+ ti,set-rate-parent;
+ };
+
+ dpll_per_ck: dpll_per_ck {
+ #clock-cells = <0>;
+ compatible = "ti,am3-dpll-no-gate-j-type-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x048c>, <0x0470>, <0x049c>;
+ };
+
+ dpll_per_m2_ck: dpll_per_m2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_ck>;
+ ti,max-div = <31>;
+ reg = <0x04ac>;
+ ti,index-starts-at-one;
+ };
+
+ dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+ };
+
+ dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+ };
+
+ cefuse_fck: cefuse_fck {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_clkin_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x0a20>;
+ };
+
+ clk_24mhz: clk_24mhz {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <8>;
+ };
+
+ clkdiv32k_ck: clkdiv32k_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_24mhz>;
+ clock-mult = <1>;
+ clock-div = <732>;
+ };
+
+ clkdiv32k_ick: clkdiv32k_ick {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&clkdiv32k_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x014c>;
+ };
+
+ l3_gclk: l3_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ pruss_ocp_gclk: pruss_ocp_gclk {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
+ reg = <0x0530>;
+ };
+
+ mmu_fck: mmu_fck {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_core_m4_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x0914>;
+ };
+
+ timer1_fck: timer1_fck {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
+ reg = <0x0528>;
+ };
+
+ timer2_fck: timer2_fck {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x0508>;
+ };
+
+ timer3_fck: timer3_fck {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x050c>;
+ };
+
+ timer4_fck: timer4_fck {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x0510>;
+ };
+
+ timer5_fck: timer5_fck {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x0518>;
+ };
+
+ timer6_fck: timer6_fck {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x051c>;
+ };
+
+ timer7_fck: timer7_fck {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ reg = <0x0504>;
+ };
+
+ usbotg_fck: usbotg_fck {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_per_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x047c>;
+ };
+
+ dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ ieee5000_fck: ieee5000_fck {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_core_m4_div2_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x00e4>;
+ };
+
+ wdt1_fck: wdt1_fck {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
+ reg = <0x0538>;
+ };
+
+ l4_rtc_gclk: l4_rtc_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ l4hs_gclk: l4hs_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ l3s_gclk: l3s_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_div2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ l4fw_gclk: l4fw_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_div2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ l4ls_gclk: l4ls_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_div2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ sysclk_div_ck: sysclk_div_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m4_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ cpsw_125mhz_gclk: cpsw_125mhz_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m5_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
+ reg = <0x0520>;
+ };
+
+ gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>;
+ reg = <0x053c>;
+ };
+
+ gpio0_dbclk: gpio0_dbclk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&gpio0_dbclk_mux_ck>;
+ ti,bit-shift = <18>;
+ reg = <0x0408>;
+ };
+
+ gpio1_dbclk: gpio1_dbclk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&clkdiv32k_ick>;
+ ti,bit-shift = <18>;
+ reg = <0x00ac>;
+ };
+
+ gpio2_dbclk: gpio2_dbclk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&clkdiv32k_ick>;
+ ti,bit-shift = <18>;
+ reg = <0x00b0>;
+ };
+
+ gpio3_dbclk: gpio3_dbclk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&clkdiv32k_ick>;
+ ti,bit-shift = <18>;
+ reg = <0x00b4>;
+ };
+
+ lcd_gclk: lcd_gclk {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
+ reg = <0x0534>;
+ ti,set-rate-parent;
+ };
+
+ mmc_clk: mmc_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ gfx_fclk_clksel_ck: gfx_fclk_clksel_ck {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x052c>;
+ };
+
+ gfx_fck_div_ck: gfx_fck_div_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&gfx_fclk_clksel_ck>;
+ reg = <0x052c>;
+ ti,max-div = <2>;
+ };
+
+ sysclkout_pre_ck: sysclkout_pre_ck {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
+ reg = <0x0700>;
+ };
+
+ clkout2_div_ck: clkout2_div_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&sysclkout_pre_ck>;
+ ti,bit-shift = <3>;
+ ti,max-div = <8>;
+ reg = <0x0700>;
+ };
+
+ dbg_sysclk_ck: dbg_sysclk_ck {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_clkin_ck>;
+ ti,bit-shift = <19>;
+ reg = <0x0414>;
+ };
+
+ dbg_clka_ck: dbg_clka_ck {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_core_m4_ck>;
+ ti,bit-shift = <30>;
+ reg = <0x0414>;
+ };
+
+ stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
+ ti,bit-shift = <22>;
+ reg = <0x0414>;
+ };
+
+ trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
+ ti,bit-shift = <20>;
+ reg = <0x0414>;
+ };
+
+ stm_clk_div_ck: stm_clk_div_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&stm_pmd_clock_mux_ck>;
+ ti,bit-shift = <27>;
+ ti,max-div = <64>;
+ reg = <0x0414>;
+ ti,index-power-of-two;
+ };
+
+ trace_clk_div_ck: trace_clk_div_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&trace_pmd_clk_mux_ck>;
+ ti,bit-shift = <24>;
+ ti,max-div = <64>;
+ reg = <0x0414>;
+ ti,index-power-of-two;
+ };
+
+ clkout2_ck: clkout2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&clkout2_div_ck>;
+ ti,bit-shift = <7>;
+ reg = <0x0700>;
+ };
+};
+
+&prcm_clockdomains {
+ clk_24mhz_clkdm: clk_24mhz_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&clkdiv32k_ick>;
+ };
+};
diff --git a/arch/arm/dts/am33xx.dtsi b/arch/arm/dts/am33xx.dtsi
index f9c5da9..21fcc44 100644
--- a/arch/arm/dts/am33xx.dtsi
+++ b/arch/arm/dts/am33xx.dtsi
@@ -18,6 +18,9 @@
interrupt-parent = <&intc>;
aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
@@ -30,6 +33,8 @@
usb1 = &usb1;
phy0 = &usb0_phy;
phy1 = &usb1_phy;
+ ethernet0 = &cpsw_emac0;
+ ethernet1 = &cpsw_emac1;
};
cpus {
@@ -53,12 +58,21 @@
275000 1125000
>;
voltage-tolerance = <2>; /* 2 percentage */
+
+ clocks = <&dpll_mpu_ck>;
+ clock-names = "cpu";
+
clock-latency = <300000>; /* From omap-cpufreq driver */
};
};
+ pmu {
+ compatible = "arm,cortex-a8-pmu";
+ interrupts = <3>;
+ };
+
/*
- * The soc node represents the soc top level view. It is uses for IPs
+ * The soc node represents the soc top level view. It is used for IPs
* that are not memory mapped in the MPU view or for the MPU itself.
*/
soc {
@@ -69,19 +83,10 @@
};
};
- am33xx_pinmux: pinmux@44e10800 {
- compatible = "pinctrl-single";
- reg = <0x44e10800 0x0238>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x7f>;
- };
-
/*
* XXX: Use a flat representation of the AM33XX interconnect.
- * The real AM33XX interconnect network is quite complex.Since
- * that will not bring real advantage to represent that in DT
+ * The real AM33XX interconnect network is quite complex. Since
+ * it will not bring real advantage to represent that in DT
* for the moment, just use a fake OCP bus entry to represent
* the whole bus hierarchy.
*/
@@ -92,21 +97,81 @@
ranges;
ti,hwmods = "l3_main";
+ l4_wkup: l4_wkup@44c00000 {
+ compatible = "ti,am3-l4-wkup", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x44c00000 0x280000>;
+
+ prcm: prcm@200000 {
+ compatible = "ti,am3-prcm";
+ reg = <0x200000 0x4000>;
+
+ prcm_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ prcm_clockdomains: clockdomains {
+ };
+ };
+
+ scm: scm@210000 {
+ compatible = "ti,am3-scm", "simple-bus";
+ reg = <0x210000 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x210000 0x2000>;
+
+ am33xx_pinmux: pinmux@800 {
+ compatible = "pinctrl-single";
+ reg = <0x800 0x238>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x7f>;
+ };
+
+ scm_conf: scm_conf@0 {
+ compatible = "syscon";
+ reg = <0x0 0x800>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ scm_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ scm_clockdomains: clockdomains {
+ };
+ };
+ };
+
intc: interrupt-controller@48200000 {
- compatible = "ti,omap2-intc";
+ compatible = "ti,am33xx-intc";
interrupt-controller;
#interrupt-cells = <1>;
- ti,intc-size = <128>;
reg = <0x48200000 0x1000>;
};
+ edma: edma@49000000 {
+ compatible = "ti,edma3";
+ ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
+ reg = <0x49000000 0x10000>,
+ <0x44e10f90 0x40>;
+ interrupts = <12 13 14>;
+ #dma-cells = <1>;
+ };
+
gpio0: gpio@44e07000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio1";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
- #interrupt-cells = <1>;
+ #interrupt-cells = <2>;
reg = <0x44e07000 0x1000>;
interrupts = <96>;
};
@@ -117,7 +182,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
- #interrupt-cells = <1>;
+ #interrupt-cells = <2>;
reg = <0x4804c000 0x1000>;
interrupts = <98>;
};
@@ -128,7 +193,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
- #interrupt-cells = <1>;
+ #interrupt-cells = <2>;
reg = <0x481ac000 0x1000>;
interrupts = <32>;
};
@@ -139,7 +204,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
- #interrupt-cells = <1>;
+ #interrupt-cells = <2>;
reg = <0x481ae000 0x1000>;
interrupts = <62>;
};
@@ -151,6 +216,8 @@
reg = <0x44e09000 0x2000>;
interrupts = <72>;
status = "disabled";
+ dmas = <&edma 26>, <&edma 27>;
+ dma-names = "tx", "rx";
};
uart1: serial@48022000 {
@@ -160,6 +227,8 @@
reg = <0x48022000 0x2000>;
interrupts = <73>;
status = "disabled";
+ dmas = <&edma 28>, <&edma 29>;
+ dma-names = "tx", "rx";
};
uart2: serial@48024000 {
@@ -169,6 +238,8 @@
reg = <0x48024000 0x2000>;
interrupts = <74>;
status = "disabled";
+ dmas = <&edma 30>, <&edma 31>;
+ dma-names = "tx", "rx";
};
uart3: serial@481a6000 {
@@ -228,6 +299,51 @@
status = "disabled";
};
+ mmc1: mmc@48060000 {
+ compatible = "ti,omap4-hsmmc";
+ ti,hwmods = "mmc1";
+ ti,dual-volt;
+ ti,needs-special-reset;
+ ti,needs-special-hs-handling;
+ dmas = <&edma 24
+ &edma 25>;
+ dma-names = "tx", "rx";
+ interrupts = <64>;
+ interrupt-parent = <&intc>;
+ reg = <0x48060000 0x1000>;
+ status = "disabled";
+ };
+
+ mmc2: mmc@481d8000 {
+ compatible = "ti,omap4-hsmmc";
+ ti,hwmods = "mmc2";
+ ti,needs-special-reset;
+ dmas = <&edma 2
+ &edma 3>;
+ dma-names = "tx", "rx";
+ interrupts = <28>;
+ interrupt-parent = <&intc>;
+ reg = <0x481d8000 0x1000>;
+ status = "disabled";
+ };
+
+ mmc3: mmc@47810000 {
+ compatible = "ti,omap4-hsmmc";
+ ti,hwmods = "mmc3";
+ ti,needs-special-reset;
+ interrupts = <29>;
+ interrupt-parent = <&intc>;
+ reg = <0x47810000 0x1000>;
+ status = "disabled";
+ };
+
+ hwspinlock: spinlock@480ca000 {
+ compatible = "ti,omap4-hwspinlock";
+ reg = <0x480ca000 0x1000>;
+ ti,hwmods = "spinlock";
+ #hwlock-cells = <1>;
+ };
+
wdt2: wdt@44e35000 {
compatible = "ti,omap3-wdt";
ti,hwmods = "wd_timer2";
@@ -235,24 +351,42 @@
interrupts = <91>;
};
- dcan0: d_can@481cc000 {
- compatible = "bosch,d_can";
+ dcan0: can@481cc000 {
+ compatible = "ti,am3352-d_can";
ti,hwmods = "d_can0";
- reg = <0x481cc000 0x2000
- 0x44e10644 0x4>;
+ reg = <0x481cc000 0x2000>;
+ clocks = <&dcan0_fck>;
+ clock-names = "fck";
+ syscon-raminit = <&scm_conf 0x644 0>;
interrupts = <52>;
status = "disabled";
};
- dcan1: d_can@481d0000 {
- compatible = "bosch,d_can";
+ dcan1: can@481d0000 {
+ compatible = "ti,am3352-d_can";
ti,hwmods = "d_can1";
- reg = <0x481d0000 0x2000
- 0x44e10644 0x4>;
+ reg = <0x481d0000 0x2000>;
+ clocks = <&dcan1_fck>;
+ clock-names = "fck";
+ syscon-raminit = <&scm_conf 0x644 1>;
interrupts = <55>;
status = "disabled";
};
+ mailbox: mailbox@480C8000 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x480C8000 0x200>;
+ interrupts = <77>;
+ ti,hwmods = "mailbox";
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <8>;
+ mbox_wkupm3: wkup_m3 {
+ ti,mbox-tx = <0 0 0>;
+ ti,mbox-rx = <0 0 3>;
+ };
+ };
+
timer1: timer@44e31000 {
compatible = "ti,am335x-timer-1ms";
reg = <0x44e31000 0x400>;
@@ -307,8 +441,8 @@
ti,timer-pwm;
};
- rtc@44e3e000 {
- compatible = "ti,da830-rtc";
+ rtc: rtc@44e3e000 {
+ compatible = "ti,am3352-rtc", "ti,da830-rtc";
reg = <0x44e3e000 0x1000>;
interrupts = <75
76>;
@@ -323,6 +457,11 @@
interrupts = <65>;
ti,spi-num-cs = <2>;
ti,hwmods = "spi0";
+ dmas = <&edma 16
+ &edma 17
+ &edma 18
+ &edma 19>;
+ dma-names = "tx0", "rx0", "tx1", "rx1";
status = "disabled";
};
@@ -334,6 +473,11 @@
interrupts = <125>;
ti,spi-num-cs = <2>;
ti,hwmods = "spi1";
+ dmas = <&edma 42
+ &edma 43
+ &edma 44
+ &edma 45>;
+ dma-names = "tx0", "rx0", "tx1", "rx1";
status = "disabled";
};
@@ -346,7 +490,7 @@
ti,hwmods = "usb_otg_hs";
status = "disabled";
- ctrl_mod: control@44e10000 {
+ usb_ctrl_mod: control@44e10620 {
compatible = "ti,am335x-usb-ctrl-module";
reg = <0x44e10620 0x10
0x44e10648 0x4>;
@@ -359,7 +503,7 @@
reg = <0x47401300 0x100>;
reg-names = "phy";
status = "disabled";
- ti,ctrl_mod = <&ctrl_mod>;
+ ti,ctrl_mod = <&usb_ctrl_mod>;
};
usb0: usb@47401000 {
@@ -407,7 +551,7 @@
reg = <0x47401b00 0x100>;
reg-names = "phy";
status = "disabled";
- ti,ctrl_mod = <&ctrl_mod>;
+ ti,ctrl_mod = <&usb_ctrl_mod>;
};
usb1: usb@47401800 {
@@ -449,7 +593,7 @@
"tx14", "tx15";
};
- cppi41dma: dma-controller@07402000 {
+ cppi41dma: dma-controller@47402000 {
compatible = "ti,am3359-cppi41";
reg = <0x47400000 0x1000
0x47402000 0x1000
@@ -480,6 +624,8 @@
compatible = "ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48300100 0x80>;
+ interrupts = <31>;
+ interrupt-names = "ecap0";
ti,hwmods = "ecap0";
status = "disabled";
};
@@ -508,6 +654,8 @@
compatible = "ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48302100 0x80>;
+ interrupts = <47>;
+ interrupt-names = "ecap1";
ti,hwmods = "ecap1";
status = "disabled";
};
@@ -536,6 +684,8 @@
compatible = "ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48304100 0x80>;
+ interrupts = <61>;
+ interrupt-names = "ecap2";
ti,hwmods = "ecap2";
status = "disabled";
};
@@ -552,6 +702,8 @@
mac: ethernet@4a100000 {
compatible = "ti,cpsw";
ti,hwmods = "cpgmac0";
+ clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
+ clock-names = "fck", "cpts";
cpdma_channels = <8>;
ale_entries = <1024>;
bd_ram_size = <0x2000>;
@@ -575,6 +727,8 @@
*/
interrupts = <40 41 42 43>;
ranges;
+ syscon = <&scm_conf>;
+ status = "disabled";
davinci_mdio: mdio@4a101000 {
compatible = "ti,davinci_mdio";
@@ -583,6 +737,7 @@
ti,hwmods = "davinci_mdio";
bus_freq = <1000000>;
reg = <0x4a101000 0x100>;
+ status = "disabled";
};
cpsw_emac0: slave@4a100200 {
@@ -594,12 +749,17 @@
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
};
+
+ phy_sel: cpsw-phy-sel@44e10650 {
+ compatible = "ti,am3352-cpsw-phy-sel";
+ reg= <0x44e10650 0x4>;
+ reg-names = "gmii-sel";
+ };
};
ocmcram: ocmcram@40300000 {
- compatible = "ti,am3352-ocmcram";
- reg = <0x40300000 0x10000>;
- ti,hwmods = "ocmcram";
+ compatible = "mmio-sram";
+ reg = <0x40300000 0x10000>; /* 64k */
};
wkup_m3: wkup_m3@44d00000 {
@@ -607,6 +767,7 @@
reg = <0x44d00000 0x4000 /* M3 UMEM */
0x44d80000 0x2000>; /* M3 DMEM */
ti,hwmods = "wkup_m3";
+ ti,no-reset-on-init;
};
elm: elm@48080000 {
@@ -617,6 +778,15 @@
status = "disabled";
};
+ lcdc: lcdc@4830e000 {
+ compatible = "ti,am33xx-tilcdc";
+ reg = <0x4830e000 0x1000>;
+ interrupt-parent = <&intc>;
+ interrupts = <36>;
+ ti,hwmods = "lcdc";
+ status = "disabled";
+ };
+
tscadc: tscadc@44e0d000 {
compatible = "ti,am3359-tscadc";
reg = <0x44e0d000 0x1000>;
@@ -637,6 +807,7 @@
gpmc: gpmc@50000000 {
compatible = "ti,am3352-gpmc";
ti,hwmods = "gpmc";
+ ti,no-idle-on-init;
reg = <0x50000000 0x2000>;
interrupts = <100>;
gpmc,num-cs = <7>;
@@ -644,6 +815,62 @@
#address-cells = <2>;
#size-cells = <1>;
status = "disabled";
+ };
+
+ sham: sham@53100000 {
+ compatible = "ti,omap4-sham";
+ ti,hwmods = "sham";
+ reg = <0x53100000 0x200>;
+ interrupts = <109>;
+ dmas = <&edma 36>;
+ dma-names = "rx";
+ };
+
+ aes: aes@53500000 {
+ compatible = "ti,omap4-aes";
+ ti,hwmods = "aes";
+ reg = <0x53500000 0xa0>;
+ interrupts = <103>;
+ dmas = <&edma 6>,
+ <&edma 5>;
+ dma-names = "tx", "rx";
+ };
+
+ mcasp0: mcasp@48038000 {
+ compatible = "ti,am33xx-mcasp-audio";
+ ti,hwmods = "mcasp0";
+ reg = <0x48038000 0x2000>,
+ <0x46000000 0x400000>;
+ reg-names = "mpu", "dat";
+ interrupts = <80>, <81>;
+ interrupt-names = "tx", "rx";
+ status = "disabled";
+ dmas = <&edma 8>,
+ <&edma 9>;
+ dma-names = "tx", "rx";
+ };
+
+ mcasp1: mcasp@4803C000 {
+ compatible = "ti,am33xx-mcasp-audio";
+ ti,hwmods = "mcasp1";
+ reg = <0x4803C000 0x2000>,
+ <0x46400000 0x400000>;
+ reg-names = "mpu", "dat";
+ interrupts = <82>, <83>;
+ interrupt-names = "tx", "rx";
+ status = "disabled";
+ dmas = <&edma 10>,
+ <&edma 11>;
+ dma-names = "tx", "rx";
+ };
+
+ rng: rng@48310000 {
+ compatible = "ti,omap4-rng";
+ ti,hwmods = "rng";
+ reg = <0x48310000 0x2000>;
+ interrupts = <111>;
};
};
};
+
+/include/ "am33xx-clocks.dtsi"
diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi
new file mode 100644
index 0000000..8f1e25b
--- /dev/null
+++ b/arch/arm/dts/dra7.dtsi
@@ -0,0 +1,1529 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ * Based on "omap4.dtsi"
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/dra.h>
+
+#include "skeleton.dtsi"
+
+#define MAX_SOURCES 400
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ compatible = "ti,dra7xx";
+ interrupt-parent = <&crossbar_mpu>;
+
+ aliases {
+ i2c0 = &i2c1;
+ i2c1 = &i2c2;
+ i2c2 = &i2c3;
+ i2c3 = &i2c4;
+ i2c4 = &i2c5;
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ serial4 = &uart5;
+ serial5 = &uart6;
+ serial6 = &uart7;
+ serial7 = &uart8;
+ serial8 = &uart9;
+ serial9 = &uart10;
+ ethernet0 = &cpsw_emac0;
+ ethernet1 = &cpsw_emac1;
+ d_can0 = &dcan1;
+ d_can1 = &dcan2;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-parent = <&gic>;
+ };
+
+ gic: interrupt-controller@48211000 {
+ compatible = "arm,cortex-a15-gic";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x48211000 0x1000>,
+ <0x48212000 0x1000>,
+ <0x48214000 0x2000>,
+ <0x48216000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupt-parent = <&gic>;
+ };
+
+ wakeupgen: interrupt-controller@48281000 {
+ compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x48281000 0x1000>;
+ interrupt-parent = <&gic>;
+ };
+
+ /*
+ * The soc node represents the soc top level view. It is used for IPs
+ * that are not memory mapped in the MPU view or for the MPU itself.
+ */
+ soc {
+ compatible = "ti,omap-infra";
+ mpu {
+ compatible = "ti,omap5-mpu";
+ ti,hwmods = "mpu";
+ };
+ };
+
+ /*
+ * XXX: Use a flat representation of the SOC interconnect.
+ * The real OMAP interconnect network is quite complex.
+ * Since it will not bring real advantage to represent that in DT for
+ * the moment, just use a fake OCP bus entry to represent the whole bus
+ * hierarchy.
+ */
+ ocp {
+ compatible = "ti,dra7-l3-noc", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ ti,hwmods = "l3_main_1", "l3_main_2";
+ reg = <0x44000000 0x1000000>,
+ <0x45000000 0x1000>;
+ interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+
+ l4_cfg: l4@4a000000 {
+ compatible = "ti,dra7-l4-cfg", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x4a000000 0x22c000>;
+
+ scm: scm@2000 {
+ compatible = "ti,dra7-scm-core", "simple-bus";
+ reg = <0x2000 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x2000 0x2000>;
+
+ scm_conf: scm_conf@0 {
+ compatible = "syscon";
+ reg = <0x0 0x1400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pbias_regulator: pbias_regulator {
+ compatible = "ti,pbias-omap";
+ reg = <0xe00 0x4>;
+ syscon = <&scm_conf>;
+ pbias_mmc_reg: pbias_mmc_omap5 {
+ regulator-name = "pbias_mmc_omap5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ };
+ };
+
+ scm_conf_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ dra7_pmx_core: pinmux@1400 {
+ compatible = "ti,dra7-padconf",
+ "pinctrl-single";
+ reg = <0x1400 0x0464>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x3fffffff>;
+ };
+ };
+
+ cm_core_aon: cm_core_aon@5000 {
+ compatible = "ti,dra7-cm-core-aon";
+ reg = <0x5000 0x2000>;
+
+ cm_core_aon_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cm_core_aon_clockdomains: clockdomains {
+ };
+ };
+
+ cm_core: cm_core@8000 {
+ compatible = "ti,dra7-cm-core";
+ reg = <0x8000 0x3000>;
+
+ cm_core_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cm_core_clockdomains: clockdomains {
+ };
+ };
+ };
+
+ l4_wkup: l4@4ae00000 {
+ compatible = "ti,dra7-l4-wkup", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x4ae00000 0x3f000>;
+
+ counter32k: counter@4000 {
+ compatible = "ti,omap-counter32k";
+ reg = <0x4000 0x40>;
+ ti,hwmods = "counter_32k";
+ };
+
+ prm: prm@6000 {
+ compatible = "ti,dra7-prm";
+ reg = <0x6000 0x3000>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+
+ prm_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ prm_clockdomains: clockdomains {
+ };
+ };
+ };
+
+ axi@0 {
+ compatible = "simple-bus";
+ #size-cells = <1>;
+ #address-cells = <1>;
+ ranges = <0x51000000 0x51000000 0x3000
+ 0x0 0x20000000 0x10000000>;
+ pcie@51000000 {
+ compatible = "ti,dra7-pcie";
+ reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
+ reg-names = "rc_dbics", "ti_conf", "config";
+ interrupts = <0 232 0x4>, <0 233 0x4>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x81000000 0 0 0x03000 0 0x00010000
+ 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
+ #interrupt-cells = <1>;
+ num-lanes = <1>;
+ ti,hwmods = "pcie1";
+ phys = <&pcie1_phy>;
+ phy-names = "pcie-phy0";
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie1_intc 1>,
+ <0 0 0 2 &pcie1_intc 2>,
+ <0 0 0 3 &pcie1_intc 3>,
+ <0 0 0 4 &pcie1_intc 4>;
+ pcie1_intc: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+ };
+
+ axi@1 {
+ compatible = "simple-bus";
+ #size-cells = <1>;
+ #address-cells = <1>;
+ ranges = <0x51800000 0x51800000 0x3000
+ 0x0 0x30000000 0x10000000>;
+ status = "disabled";
+ pcie@51000000 {
+ compatible = "ti,dra7-pcie";
+ reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
+ reg-names = "rc_dbics", "ti_conf", "config";
+ interrupts = <0 355 0x4>, <0 356 0x4>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x81000000 0 0 0x03000 0 0x00010000
+ 0x82000000 0 0x30013000 0x13000 0 0xffed000>;
+ #interrupt-cells = <1>;
+ num-lanes = <1>;
+ ti,hwmods = "pcie2";
+ phys = <&pcie2_phy>;
+ phy-names = "pcie-phy0";
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie2_intc 1>,
+ <0 0 0 2 &pcie2_intc 2>,
+ <0 0 0 3 &pcie2_intc 3>,
+ <0 0 0 4 &pcie2_intc 4>;
+ pcie2_intc: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+ };
+
+ bandgap: bandgap@4a0021e0 {
+ reg = <0x4a0021e0 0xc
+ 0x4a00232c 0xc
+ 0x4a002380 0x2c
+ 0x4a0023C0 0x3c
+ 0x4a002564 0x8
+ 0x4a002574 0x50>;
+ compatible = "ti,dra752-bandgap";
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ dra7_ctrl_core: ctrl_core@4a002000 {
+ compatible = "syscon";
+ reg = <0x4a002000 0x6d0>;
+ };
+
+ dra7_ctrl_general: tisyscon@4a002e00 {
+ compatible = "syscon";
+ reg = <0x4a002e00 0x7c>;
+ };
+
+ sdma: dma-controller@4a056000 {
+ compatible = "ti,omap4430-sdma";
+ reg = <0x4a056000 0x1000>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ dma-channels = <32>;
+ dma-requests = <127>;
+ };
+
+ gpio1: gpio@4ae10000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x4ae10000 0x200>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "gpio1";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@48055000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x48055000 0x200>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "gpio2";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@48057000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x48057000 0x200>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "gpio3";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@48059000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x48059000 0x200>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "gpio4";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio5: gpio@4805b000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x4805b000 0x200>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "gpio5";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio6: gpio@4805d000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x4805d000 0x200>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "gpio6";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio7: gpio@48051000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x48051000 0x200>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "gpio7";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio8: gpio@48053000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x48053000 0x200>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "gpio8";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ uart1: serial@4806a000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x4806a000 0x100>;
+ interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "uart1";
+ clock-frequency = <48000000>;
+ status = "disabled";
+ dmas = <&sdma 49>, <&sdma 50>;
+ dma-names = "tx", "rx";
+ };
+
+ uart2: serial@4806c000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x4806c000 0x100>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "uart2";
+ clock-frequency = <48000000>;
+ status = "disabled";
+ dmas = <&sdma 51>, <&sdma 52>;
+ dma-names = "tx", "rx";
+ };
+
+ uart3: serial@48020000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x48020000 0x100>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "uart3";
+ clock-frequency = <48000000>;
+ status = "disabled";
+ dmas = <&sdma 53>, <&sdma 54>;
+ dma-names = "tx", "rx";
+ };
+
+ uart4: serial@4806e000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x4806e000 0x100>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "uart4";
+ clock-frequency = <48000000>;
+ status = "disabled";
+ dmas = <&sdma 55>, <&sdma 56>;
+ dma-names = "tx", "rx";
+ };
+
+ uart5: serial@48066000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x48066000 0x100>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "uart5";
+ clock-frequency = <48000000>;
+ status = "disabled";
+ dmas = <&sdma 63>, <&sdma 64>;
+ dma-names = "tx", "rx";
+ };
+
+ uart6: serial@48068000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x48068000 0x100>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "uart6";
+ clock-frequency = <48000000>;
+ status = "disabled";
+ dmas = <&sdma 79>, <&sdma 80>;
+ dma-names = "tx", "rx";
+ };
+
+ uart7: serial@48420000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x48420000 0x100>;
+ interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "uart7";
+ clock-frequency = <48000000>;
+ status = "disabled";
+ };
+
+ uart8: serial@48422000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x48422000 0x100>;
+ interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "uart8";
+ clock-frequency = <48000000>;
+ status = "disabled";
+ };
+
+ uart9: serial@48424000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x48424000 0x100>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "uart9";
+ clock-frequency = <48000000>;
+ status = "disabled";
+ };
+
+ uart10: serial@4ae2b000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x4ae2b000 0x100>;
+ interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "uart10";
+ clock-frequency = <48000000>;
+ status = "disabled";
+ };
+
+ mailbox1: mailbox@4a0f4000 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x4a0f4000 0x200>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mailbox1";
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <3>;
+ ti,mbox-num-fifos = <8>;
+ status = "disabled";
+ };
+
+ mailbox2: mailbox@4883a000 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x4883a000 0x200>;
+ interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mailbox2";
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <12>;
+ status = "disabled";
+ };
+
+ mailbox3: mailbox@4883c000 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x4883c000 0x200>;
+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mailbox3";
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <12>;
+ status = "disabled";
+ };
+
+ mailbox4: mailbox@4883e000 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x4883e000 0x200>;
+ interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mailbox4";
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <12>;
+ status = "disabled";
+ };
+
+ mailbox5: mailbox@48840000 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x48840000 0x200>;
+ interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mailbox5";
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <12>;
+ status = "disabled";
+ };
+
+ mailbox6: mailbox@48842000 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x48842000 0x200>;
+ interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mailbox6";
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <12>;
+ status = "disabled";
+ };
+
+ mailbox7: mailbox@48844000 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x48844000 0x200>;
+ interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mailbox7";
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <12>;
+ status = "disabled";
+ };
+
+ mailbox8: mailbox@48846000 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x48846000 0x200>;
+ interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mailbox8";
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <12>;
+ status = "disabled";
+ };
+
+ mailbox9: mailbox@4885e000 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x4885e000 0x200>;
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mailbox9";
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <12>;
+ status = "disabled";
+ };
+
+ mailbox10: mailbox@48860000 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x48860000 0x200>;
+ interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mailbox10";
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <12>;
+ status = "disabled";
+ };
+
+ mailbox11: mailbox@48862000 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x48862000 0x200>;
+ interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mailbox11";
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <12>;
+ status = "disabled";
+ };
+
+ mailbox12: mailbox@48864000 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x48864000 0x200>;
+ interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mailbox12";
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <12>;
+ status = "disabled";
+ };
+
+ mailbox13: mailbox@48802000 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x48802000 0x200>;
+ interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mailbox13";
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <12>;
+ status = "disabled";
+ };
+
+ timer1: timer@4ae18000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x4ae18000 0x80>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "timer1";
+ ti,timer-alwon;
+ };
+
+ timer2: timer@48032000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x48032000 0x80>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "timer2";
+ };
+
+ timer3: timer@48034000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x48034000 0x80>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "timer3";
+ };
+
+ timer4: timer@48036000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x48036000 0x80>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "timer4";
+ };
+
+ timer5: timer@48820000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x48820000 0x80>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "timer5";
+ };
+
+ timer6: timer@48822000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x48822000 0x80>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "timer6";
+ };
+
+ timer7: timer@48824000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x48824000 0x80>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "timer7";
+ };
+
+ timer8: timer@48826000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x48826000 0x80>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "timer8";
+ };
+
+ timer9: timer@4803e000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x4803e000 0x80>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "timer9";
+ };
+
+ timer10: timer@48086000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x48086000 0x80>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "timer10";
+ };
+
+ timer11: timer@48088000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x48088000 0x80>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "timer11";
+ };
+
+ timer13: timer@48828000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x48828000 0x80>;
+ interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "timer13";
+ status = "disabled";
+ };
+
+ timer14: timer@4882a000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x4882a000 0x80>;
+ interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "timer14";
+ status = "disabled";
+ };
+
+ timer15: timer@4882c000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x4882c000 0x80>;
+ interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "timer15";
+ status = "disabled";
+ };
+
+ timer16: timer@4882e000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x4882e000 0x80>;
+ interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "timer16";
+ status = "disabled";
+ };
+
+ wdt2: wdt@4ae14000 {
+ compatible = "ti,omap3-wdt";
+ reg = <0x4ae14000 0x80>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "wd_timer2";
+ };
+
+ hwspinlock: spinlock@4a0f6000 {
+ compatible = "ti,omap4-hwspinlock";
+ reg = <0x4a0f6000 0x1000>;
+ ti,hwmods = "spinlock";
+ #hwlock-cells = <1>;
+ };
+
+ dmm@4e000000 {
+ compatible = "ti,omap5-dmm";
+ reg = <0x4e000000 0x800>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "dmm";
+ };
+
+ i2c1: i2c@48070000 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x48070000 0x100>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c1";
+ status = "disabled";
+ };
+
+ i2c2: i2c@48072000 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x48072000 0x100>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c2";
+ status = "disabled";
+ };
+
+ i2c3: i2c@48060000 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x48060000 0x100>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c3";
+ status = "disabled";
+ };
+
+ i2c4: i2c@4807a000 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x4807a000 0x100>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c4";
+ status = "disabled";
+ };
+
+ i2c5: i2c@4807c000 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x4807c000 0x100>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c5";
+ status = "disabled";
+ };
+
+ mmc1: mmc@4809c000 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x4809c000 0x400>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mmc1";
+ ti,dual-volt;
+ ti,needs-special-reset;
+ dmas = <&sdma 61>, <&sdma 62>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ pbias-supply = <&pbias_mmc_reg>;
+ };
+
+ mmc2: mmc@480b4000 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x480b4000 0x400>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mmc2";
+ ti,needs-special-reset;
+ dmas = <&sdma 47>, <&sdma 48>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ mmc3: mmc@480ad000 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x480ad000 0x400>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mmc3";
+ ti,needs-special-reset;
+ dmas = <&sdma 77>, <&sdma 78>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ mmc4: mmc@480d1000 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x480d1000 0x400>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mmc4";
+ ti,needs-special-reset;
+ dmas = <&sdma 57>, <&sdma 58>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ abb_mpu: regulator-abb-mpu {
+ compatible = "ti,abb-v3";
+ regulator-name = "abb_mpu";
+ #address-cells = <0>;
+ #size-cells = <0>;
+ clocks = <&sys_clkin1>;
+ ti,settling-time = <50>;
+ ti,clock-cycles = <16>;
+
+ reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
+ <0x4ae06014 0x4>, <0x4a003b20 0xc>,
+ <0x4ae0c158 0x4>;
+ reg-names = "setup-address", "control-address",
+ "int-address", "efuse-address",
+ "ldo-address";
+ ti,tranxdone-status-mask = <0x80>;
+ /* LDOVBBMPU_FBB_MUX_CTRL */
+ ti,ldovbb-override-mask = <0x400>;
+ /* LDOVBBMPU_FBB_VSET_OUT */
+ ti,ldovbb-vset-mask = <0x1F>;
+
+ /*
+ * NOTE: only FBB mode used but actual vset will
+ * determine final biasing
+ */
+ ti,abb_info = <
+ /*uV ABB efuse rbb_m fbb_m vset_m*/
+ 1060000 0 0x0 0 0x02000000 0x01F00000
+ 1160000 0 0x4 0 0x02000000 0x01F00000
+ 1210000 0 0x8 0 0x02000000 0x01F00000
+ >;
+ };
+
+ abb_ivahd: regulator-abb-ivahd {
+ compatible = "ti,abb-v3";
+ regulator-name = "abb_ivahd";
+ #address-cells = <0>;
+ #size-cells = <0>;
+ clocks = <&sys_clkin1>;
+ ti,settling-time = <50>;
+ ti,clock-cycles = <16>;
+
+ reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
+ <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
+ <0x4a002470 0x4>;
+ reg-names = "setup-address", "control-address",
+ "int-address", "efuse-address",
+ "ldo-address";
+ ti,tranxdone-status-mask = <0x40000000>;
+ /* LDOVBBIVA_FBB_MUX_CTRL */
+ ti,ldovbb-override-mask = <0x400>;
+ /* LDOVBBIVA_FBB_VSET_OUT */
+ ti,ldovbb-vset-mask = <0x1F>;
+
+ /*
+ * NOTE: only FBB mode used but actual vset will
+ * determine final biasing
+ */
+ ti,abb_info = <
+ /*uV ABB efuse rbb_m fbb_m vset_m*/
+ 1055000 0 0x0 0 0x02000000 0x01F00000
+ 1150000 0 0x4 0 0x02000000 0x01F00000
+ 1250000 0 0x8 0 0x02000000 0x01F00000
+ >;
+ };
+
+ abb_dspeve: regulator-abb-dspeve {
+ compatible = "ti,abb-v3";
+ regulator-name = "abb_dspeve";
+ #address-cells = <0>;
+ #size-cells = <0>;
+ clocks = <&sys_clkin1>;
+ ti,settling-time = <50>;
+ ti,clock-cycles = <16>;
+
+ reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
+ <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
+ <0x4a00246c 0x4>;
+ reg-names = "setup-address", "control-address",
+ "int-address", "efuse-address",
+ "ldo-address";
+ ti,tranxdone-status-mask = <0x20000000>;
+ /* LDOVBBDSPEVE_FBB_MUX_CTRL */
+ ti,ldovbb-override-mask = <0x400>;
+ /* LDOVBBDSPEVE_FBB_VSET_OUT */
+ ti,ldovbb-vset-mask = <0x1F>;
+
+ /*
+ * NOTE: only FBB mode used but actual vset will
+ * determine final biasing
+ */
+ ti,abb_info = <
+ /*uV ABB efuse rbb_m fbb_m vset_m*/
+ 1055000 0 0x0 0 0x02000000 0x01F00000
+ 1150000 0 0x4 0 0x02000000 0x01F00000
+ 1250000 0 0x8 0 0x02000000 0x01F00000
+ >;
+ };
+
+ abb_gpu: regulator-abb-gpu {
+ compatible = "ti,abb-v3";
+ regulator-name = "abb_gpu";
+ #address-cells = <0>;
+ #size-cells = <0>;
+ clocks = <&sys_clkin1>;
+ ti,settling-time = <50>;
+ ti,clock-cycles = <16>;
+
+ reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
+ <0x4ae06010 0x4>, <0x4a003b08 0xc>,
+ <0x4ae0c154 0x4>;
+ reg-names = "setup-address", "control-address",
+ "int-address", "efuse-address",
+ "ldo-address";
+ ti,tranxdone-status-mask = <0x10000000>;
+ /* LDOVBBGPU_FBB_MUX_CTRL */
+ ti,ldovbb-override-mask = <0x400>;
+ /* LDOVBBGPU_FBB_VSET_OUT */
+ ti,ldovbb-vset-mask = <0x1F>;
+
+ /*
+ * NOTE: only FBB mode used but actual vset will
+ * determine final biasing
+ */
+ ti,abb_info = <
+ /*uV ABB efuse rbb_m fbb_m vset_m*/
+ 1090000 0 0x0 0 0x02000000 0x01F00000
+ 1210000 0 0x4 0 0x02000000 0x01F00000
+ 1280000 0 0x8 0 0x02000000 0x01F00000
+ >;
+ };
+
+ mcspi1: spi@48098000 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x48098000 0x200>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "mcspi1";
+ ti,spi-num-cs = <4>;
+ dmas = <&sdma 35>,
+ <&sdma 36>,
+ <&sdma 37>,
+ <&sdma 38>,
+ <&sdma 39>,
+ <&sdma 40>,
+ <&sdma 41>,
+ <&sdma 42>;
+ dma-names = "tx0", "rx0", "tx1", "rx1",
+ "tx2", "rx2", "tx3", "rx3";
+ status = "disabled";
+ };
+
+ mcspi2: spi@4809a000 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x4809a000 0x200>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "mcspi2";
+ ti,spi-num-cs = <2>;
+ dmas = <&sdma 43>,
+ <&sdma 44>,
+ <&sdma 45>,
+ <&sdma 46>;
+ dma-names = "tx0", "rx0", "tx1", "rx1";
+ status = "disabled";
+ };
+
+ mcspi3: spi@480b8000 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x480b8000 0x200>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "mcspi3";
+ ti,spi-num-cs = <2>;
+ dmas = <&sdma 15>, <&sdma 16>;
+ dma-names = "tx0", "rx0";
+ status = "disabled";
+ };
+
+ mcspi4: spi@480ba000 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x480ba000 0x200>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "mcspi4";
+ ti,spi-num-cs = <1>;
+ dmas = <&sdma 70>, <&sdma 71>;
+ dma-names = "tx0", "rx0";
+ status = "disabled";
+ };
+
+ qspi: qspi@4b300000 {
+ compatible = "ti,dra7xxx-qspi";
+ reg = <0x4b300000 0x100>;
+ reg-names = "qspi_base";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "qspi";
+ clocks = <&qspi_gfclk_div>;
+ clock-names = "fck";
+ num-cs = <4>;
+ interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ omap_control_sata: control-phy@4a002374 {
+ compatible = "ti,control-phy-pipe3";
+ reg = <0x4a002374 0x4>;
+ reg-names = "power";
+ clocks = <&sys_clkin1>;
+ clock-names = "sysclk";
+ };
+
+ /* OCP2SCP3 */
+ ocp2scp@4a090000 {
+ compatible = "ti,omap-ocp2scp";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ reg = <0x4a090000 0x20>;
+ ti,hwmods = "ocp2scp3";
+ sata_phy: phy@4A096000 {
+ compatible = "ti,phy-pipe3-sata";
+ reg = <0x4A096000 0x80>, /* phy_rx */
+ <0x4A096400 0x64>, /* phy_tx */
+ <0x4A096800 0x40>; /* pll_ctrl */
+ reg-names = "phy_rx", "phy_tx", "pll_ctrl";
+ ctrl-module = <&omap_control_sata>;
+ clocks = <&sys_clkin1>, <&sata_ref_clk>;
+ clock-names = "sysclk", "refclk";
+ #phy-cells = <0>;
+ };
+
+ pcie1_phy: pciephy@4a094000 {
+ compatible = "ti,phy-pipe3-pcie";
+ reg = <0x4a094000 0x80>, /* phy_rx */
+ <0x4a094400 0x64>; /* phy_tx */
+ reg-names = "phy_rx", "phy_tx";
+ ctrl-module = <&omap_control_pcie1phy>;
+ clocks = <&dpll_pcie_ref_ck>,
+ <&dpll_pcie_ref_m2ldo_ck>,
+ <&optfclk_pciephy1_32khz>,
+ <&optfclk_pciephy1_clk>,
+ <&optfclk_pciephy1_div_clk>,
+ <&optfclk_pciephy_div>;
+ clock-names = "dpll_ref", "dpll_ref_m2",
+ "wkupclk", "refclk",
+ "div-clk", "phy-div";
+ #phy-cells = <0>;
+ };
+
+ pcie2_phy: pciephy@4a095000 {
+ compatible = "ti,phy-pipe3-pcie";
+ reg = <0x4a095000 0x80>, /* phy_rx */
+ <0x4a095400 0x64>; /* phy_tx */
+ reg-names = "phy_rx", "phy_tx";
+ ctrl-module = <&omap_control_pcie2phy>;
+ clocks = <&dpll_pcie_ref_ck>,
+ <&dpll_pcie_ref_m2ldo_ck>,
+ <&optfclk_pciephy2_32khz>,
+ <&optfclk_pciephy2_clk>,
+ <&optfclk_pciephy2_div_clk>,
+ <&optfclk_pciephy_div>;
+ clock-names = "dpll_ref", "dpll_ref_m2",
+ "wkupclk", "refclk",
+ "div-clk", "phy-div";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ sata: sata@4a141100 {
+ compatible = "snps,dwc-ahci";
+ reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&sata_phy>;
+ phy-names = "sata-phy";
+ clocks = <&sata_ref_clk>;
+ ti,hwmods = "sata";
+ };
+
+ omap_control_pcie1phy: control-phy@0x4a003c40 {
+ compatible = "ti,control-phy-pcie";
+ reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
+ reg-names = "power", "control_sma", "pcie_pcs";
+ clocks = <&sys_clkin1>;
+ clock-names = "sysclk";
+ };
+
+ omap_control_pcie2phy: control-pcie@0x4a003c44 {
+ compatible = "ti,control-phy-pcie";
+ reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
+ reg-names = "power", "control_sma", "pcie_pcs";
+ clocks = <&sys_clkin1>;
+ clock-names = "sysclk";
+ status = "disabled";
+ };
+
+ rtc: rtc@48838000 {
+ compatible = "ti,am3352-rtc";
+ reg = <0x48838000 0x100>;
+ interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "rtcss";
+ clocks = <&sys_32k_ck>;
+ };
+
+ omap_control_usb2phy1: control-phy@4a002300 {
+ compatible = "ti,control-phy-usb2";
+ reg = <0x4a002300 0x4>;
+ reg-names = "power";
+ };
+
+ omap_control_usb3phy1: control-phy@4a002370 {
+ compatible = "ti,control-phy-pipe3";
+ reg = <0x4a002370 0x4>;
+ reg-names = "power";
+ };
+
+ omap_control_usb2phy2: control-phy@0x4a002e74 {
+ compatible = "ti,control-phy-usb2-dra7";
+ reg = <0x4a002e74 0x4>;
+ reg-names = "power";
+ };
+
+ /* OCP2SCP1 */
+ ocp2scp@4a080000 {
+ compatible = "ti,omap-ocp2scp";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ reg = <0x4a080000 0x20>;
+ ti,hwmods = "ocp2scp1";
+
+ usb2_phy1: phy@4a084000 {
+ compatible = "ti,omap-usb2";
+ reg = <0x4a084000 0x400>;
+ ctrl-module = <&omap_control_usb2phy1>;
+ clocks = <&usb_phy1_always_on_clk32k>,
+ <&usb_otg_ss1_refclk960m>;
+ clock-names = "wkupclk",
+ "refclk";
+ #phy-cells = <0>;
+ };
+
+ usb2_phy2: phy@4a085000 {
+ compatible = "ti,omap-usb2";
+ reg = <0x4a085000 0x400>;
+ ctrl-module = <&omap_control_usb2phy2>;
+ clocks = <&usb_phy2_always_on_clk32k>,
+ <&usb_otg_ss2_refclk960m>;
+ clock-names = "wkupclk",
+ "refclk";
+ #phy-cells = <0>;
+ };
+
+ usb3_phy1: phy@4a084400 {
+ compatible = "ti,omap-usb3";
+ reg = <0x4a084400 0x80>,
+ <0x4a084800 0x64>,
+ <0x4a084c00 0x40>;
+ reg-names = "phy_rx", "phy_tx", "pll_ctrl";
+ ctrl-module = <&omap_control_usb3phy1>;
+ clocks = <&usb_phy3_always_on_clk32k>,
+ <&sys_clkin1>,
+ <&usb_otg_ss1_refclk960m>;
+ clock-names = "wkupclk",
+ "sysclk",
+ "refclk";
+ #phy-cells = <0>;
+ };
+ };
+
+ omap_dwc3_1: omap_dwc3_1@48880000 {
+ compatible = "ti,dwc3";
+ ti,hwmods = "usb_otg_ss1";
+ reg = <0x48880000 0x10000>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ utmi-mode = <2>;
+ ranges;
+ usb1: usb@48890000 {
+ compatible = "snps,dwc3";
+ reg = <0x48890000 0x17000>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb2_phy1>, <&usb3_phy1>;
+ phy-names = "usb2-phy", "usb3-phy";
+ tx-fifo-resize;
+ maximum-speed = "super-speed";
+ dr_mode = "otg";
+ snps,dis_u3_susphy_quirk;
+ snps,dis_u2_susphy_quirk;
+ };
+ };
+
+ omap_dwc3_2: omap_dwc3_2@488c0000 {
+ compatible = "ti,dwc3";
+ ti,hwmods = "usb_otg_ss2";
+ reg = <0x488c0000 0x10000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ utmi-mode = <2>;
+ ranges;
+ usb2: usb@488d0000 {
+ compatible = "snps,dwc3";
+ reg = <0x488d0000 0x17000>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb2_phy2>;
+ phy-names = "usb2-phy";
+ tx-fifo-resize;
+ maximum-speed = "high-speed";
+ dr_mode = "otg";
+ snps,dis_u3_susphy_quirk;
+ snps,dis_u2_susphy_quirk;
+ };
+ };
+
+ /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
+ omap_dwc3_3: omap_dwc3_3@48900000 {
+ compatible = "ti,dwc3";
+ ti,hwmods = "usb_otg_ss3";
+ reg = <0x48900000 0x10000>;
+ interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ utmi-mode = <2>;
+ ranges;
+ status = "disabled";
+ usb3: usb@48910000 {
+ compatible = "snps,dwc3";
+ reg = <0x48910000 0x17000>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ tx-fifo-resize;
+ maximum-speed = "high-speed";
+ dr_mode = "otg";
+ snps,dis_u3_susphy_quirk;
+ snps,dis_u2_susphy_quirk;
+ };
+ };
+
+ elm: elm@48078000 {
+ compatible = "ti,am3352-elm";
+ reg = <0x48078000 0xfc0>; /* device IO registers */
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "elm";
+ status = "disabled";
+ };
+
+ gpmc: gpmc@50000000 {
+ compatible = "ti,am3352-gpmc";
+ ti,hwmods = "gpmc";
+ reg = <0x50000000 0x37c>; /* device IO registers */
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ gpmc,num-cs = <8>;
+ gpmc,num-waitpins = <2>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ status = "disabled";
+ };
+
+ atl: atl@4843c000 {
+ compatible = "ti,dra7-atl";
+ reg = <0x4843c000 0x3ff>;
+ ti,hwmods = "atl";
+ ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
+ <&atl_clkin2_ck>, <&atl_clkin3_ck>;
+ clocks = <&atl_gfclk_mux>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+
+ crossbar_mpu: crossbar@4a002a48 {
+ compatible = "ti,irq-crossbar";
+ reg = <0x4a002a48 0x130>;
+ interrupt-controller;
+ interrupt-parent = <&wakeupgen>;
+ #interrupt-cells = <3>;
+ ti,max-irqs = <160>;
+ ti,max-crossbar-sources = <MAX_SOURCES>;
+ ti,reg-size = <2>;
+ ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
+ ti,irqs-skip = <10 133 139 140>;
+ ti,irqs-safe-map = <0>;
+ };
+
+ mac: ethernet@4a100000 {
+ compatible = "ti,cpsw";
+ ti,hwmods = "gmac";
+ clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
+ clock-names = "fck", "cpts";
+ cpdma_channels = <8>;
+ ale_entries = <1024>;
+ bd_ram_size = <0x2000>;
+ no_bd_ram = <0>;
+ rx_descs = <64>;
+ mac_control = <0x20>;
+ slaves = <2>;
+ active_slave = <0>;
+ cpts_clock_mult = <0x80000000>;
+ cpts_clock_shift = <29>;
+ reg = <0x48484000 0x1000
+ 0x48485200 0x2E00>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ /*
+ * rx_thresh_pend
+ * rx_pend
+ * tx_pend
+ * misc_pend
+ */
+ interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ status = "disabled";
+
+ davinci_mdio: mdio@48485000 {
+ compatible = "ti,davinci_mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "davinci_mdio";
+ bus_freq = <1000000>;
+ reg = <0x48485000 0x100>;
+ };
+
+ cpsw_emac0: slave@48480200 {
+ /* Filled in by U-Boot */
+ mac-address = [ 00 00 00 00 00 00 ];
+ };
+
+ cpsw_emac1: slave@48480300 {
+ /* Filled in by U-Boot */
+ mac-address = [ 00 00 00 00 00 00 ];
+ };
+
+ phy_sel: cpsw-phy-sel@4a002554 {
+ compatible = "ti,dra7xx-cpsw-phy-sel";
+ reg= <0x4a002554 0x4>;
+ reg-names = "gmii-sel";
+ };
+ };
+
+ dcan1: can@481cc000 {
+ compatible = "ti,dra7-d_can";
+ ti,hwmods = "dcan1";
+ reg = <0x4ae3c000 0x2000>;
+ syscon-raminit = <&scm_conf 0x558 0>;
+ interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&dcan1_sys_clk_mux>;
+ status = "disabled";
+ };
+
+ dcan2: can@481d0000 {
+ compatible = "ti,dra7-d_can";
+ ti,hwmods = "dcan2";
+ reg = <0x48480000 0x2000>;
+ syscon-raminit = <&scm_conf 0x558 1>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sys_clkin1>;
+ status = "disabled";
+ };
+
+ dss: dss@58000000 {
+ compatible = "ti,dra7-dss";
+ /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
+ /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
+ status = "disabled";
+ ti,hwmods = "dss_core";
+ /* CTRL_CORE_DSS_PLL_CONTROL */
+ syscon-pll-ctrl = <&scm_conf 0x538>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ dispc@58001000 {
+ compatible = "ti,dra7-dispc";
+ reg = <0x58001000 0x1000>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "dss_dispc";
+ clocks = <&dss_dss_clk>;
+ clock-names = "fck";
+ /* CTRL_CORE_SMA_SW_1 */
+ syscon-pol = <&scm_conf 0x534>;
+ };
+
+ hdmi: encoder@58060000 {
+ compatible = "ti,dra7-hdmi";
+ reg = <0x58040000 0x200>,
+ <0x58040200 0x80>,
+ <0x58040300 0x80>,
+ <0x58060000 0x19000>;
+ reg-names = "wp", "pll", "phy", "core";
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ ti,hwmods = "dss_hdmi";
+ clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>;
+ clock-names = "fck", "sys_clk";
+ };
+ };
+ };
+
+ thermal_zones: thermal-zones {
+ #include "omap4-cpu-thermal.dtsi"
+ #include "omap5-gpu-thermal.dtsi"
+ #include "omap5-core-thermal.dtsi"
+ };
+
+};
+
+&cpu_thermal {
+ polling-delay = <500>; /* milliseconds */
+};
+
+/include/ "dra7xx-clocks.dtsi"
diff --git a/arch/arm/dts/dra72-evm.dts b/arch/arm/dts/dra72-evm.dts
new file mode 100644
index 0000000..efb544c
--- /dev/null
+++ b/arch/arm/dts/dra72-evm.dts
@@ -0,0 +1,683 @@
+/*
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "dra72x.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "TI DRA722";
+ compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>; /* 1024 MB */
+ };
+
+ aliases {
+ display0 = &hdmi0;
+ };
+
+ evm_3v3: fixedregulator-evm_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "evm_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ extcon_usb1: extcon_usb1 {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ extcon_usb2: extcon_usb2 {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ hdmi0: connector {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&tpd12s015_out>;
+ };
+ };
+ };
+
+ tpd12s015: encoder {
+ compatible = "ti,tpd12s015";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&tpd12s015_pins>;
+
+ gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
+ <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
+ <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tpd12s015_in: endpoint {
+ remote-endpoint = <&hdmi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tpd12s015_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
+};
+
+&dra7_pmx_core {
+ i2c1_pins: pinmux_i2c1_pins {
+ pinctrl-single,pins = <
+ 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
+ 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
+ >;
+ };
+
+ i2c5_pins: pinmux_i2c5_pins {
+ pinctrl-single,pins = <
+ 0x2b4 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
+ 0x2b8 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
+ >;
+ };
+
+ nand_default: nand_default {
+ pinctrl-single,pins = <
+ 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
+ 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
+ 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
+ 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
+ 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
+ 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
+ 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
+ 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
+ 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
+ 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
+ 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
+ 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
+ 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
+ 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
+ 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
+ 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
+ 0xb4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
+ 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
+ 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
+ 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
+ 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
+ 0xd8 (PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */
+ >;
+ };
+
+ usb1_pins: pinmux_usb1_pins {
+ pinctrl-single,pins = <
+ 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
+ >;
+ };
+
+ usb2_pins: pinmux_usb2_pins {
+ pinctrl-single,pins = <
+ 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
+ >;
+ };
+
+ tps65917_pins_default: tps65917_pins_default {
+ pinctrl-single,pins = <
+ 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
+ >;
+ };
+
+ mmc1_pins_default: mmc1_pins_default {
+ pinctrl-single,pins = <
+ 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
+ 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
+ 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+ 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+ 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+ 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+ 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc2_pins_default: mmc2_pins_default {
+ pinctrl-single,pins = <
+ 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+
+ dcan1_pins_default: dcan1_pins_default {
+ pinctrl-single,pins = <
+ 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
+ 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
+ >;
+ };
+
+ dcan1_pins_sleep: dcan1_pins_sleep {
+ pinctrl-single,pins = <
+ 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
+ 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
+ >;
+ };
+
+ qspi1_pins: pinmux_qspi1_pins {
+ pinctrl-single,pins = <
+ 0x74 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
+ 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
+ 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
+ 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
+ 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
+ 0x88 (PIN_OUTPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
+ 0xb8 (PIN_OUTPUT | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
+ >;
+ };
+
+ hdmi_pins: pinmux_hdmi_pins {
+ pinctrl-single,pins = <
+ 0x408 (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
+ 0x40c (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
+ >;
+ };
+
+ tpd12s015_pins: pinmux_tpd12s015_pins {
+ pinctrl-single,pins = <
+ 0x3b8 (PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */
+ >;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ clock-frequency = <400000>;
+
+ tps65917: tps65917@58 {
+ compatible = "ti,tps65917";
+ reg = <0x58>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&tps65917_pins_default>;
+
+ interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ ti,system-power-controller;
+
+ tps65917_pmic {
+ compatible = "ti,tps65917-pmic";
+
+ regulators {
+ smps1_reg: smps1 {
+ /* VDD_MPU */
+ regulator-name = "smps1";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps2_reg: smps2 {
+ /* VDD_CORE */
+ regulator-name = "smps2";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1060000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ smps3_reg: smps3 {
+ /* VDD_GPU IVA DSPEVE */
+ regulator-name = "smps3";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ smps4_reg: smps4 {
+ /* VDDS1V8 */
+ regulator-name = "smps4";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps5_reg: smps5 {
+ /* VDD_DDR */
+ regulator-name = "smps5";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1_reg: ldo1 {
+ /* LDO1_OUT --> SDIO */
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ };
+
+ ldo2_reg: ldo2 {
+ /* LDO2_OUT --> TP1017 (UNUSED) */
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo3_reg: ldo3 {
+ /* VDDA_1V8_PHY */
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo5_reg: ldo5 {
+ /* VDDA_1V8_PLL */
+ regulator-name = "ldo5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo4_reg: ldo4 {
+ /* VDDA_3V_USB: VDDA_USBHS33 */
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ };
+ };
+ };
+
+ tps65917_power_button {
+ compatible = "ti,palmas-pwrbutton";
+ interrupt-parent = <&tps65917>;
+ interrupts = <1 IRQ_TYPE_NONE>;
+ wakeup-source;
+ ti,palmas-long-press-seconds = <6>;
+ };
+ };
+
+ pcf_gpio_21: gpio@21 {
+ compatible = "ti,pcf8575";
+ reg = <0x21>;
+ lines-initial-states = <0x1408>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
+
+&i2c5 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5_pins>;
+ clock-frequency = <400000>;
+
+ pcf_hdmi: pcf8575@26 {
+ compatible = "nxp,pcf8575";
+ reg = <0x26>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /*
+ * initial state is used here to keep the mdio interface
+ * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
+ * VIN2_S0 driven high otherwise Ethernet stops working
+ * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
+ */
+ lines-initial-states = <0x0f2b>;
+ };
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&elm {
+ status = "okay";
+};
+
+&gpmc {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&nand_default>;
+ ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
+ nand@0,0 {
+ /* To use NAND, DIP switch SW5 must be set like so:
+ * SW5.1 (NAND_SELn) = ON (LOW)
+ * SW5.9 (GPMC_WPN) = OFF (HIGH)
+ */
+ reg = <0 0 4>; /* device IO registers */
+ ti,nand-ecc-opt = "bch8";
+ ti,elm-id = <&elm>;
+ nand-bus-width = <16>;
+ gpmc,device-width = <2>;
+ gpmc,sync-clk-ps = <0>;
+ gpmc,cs-on-ns = <0>;
+ gpmc,cs-rd-off-ns = <80>;
+ gpmc,cs-wr-off-ns = <80>;
+ gpmc,adv-on-ns = <0>;
+ gpmc,adv-rd-off-ns = <60>;
+ gpmc,adv-wr-off-ns = <60>;
+ gpmc,we-on-ns = <10>;
+ gpmc,we-off-ns = <50>;
+ gpmc,oe-on-ns = <4>;
+ gpmc,oe-off-ns = <40>;
+ gpmc,access-ns = <40>;
+ gpmc,wr-access-ns = <80>;
+ gpmc,rd-cycle-ns = <80>;
+ gpmc,wr-cycle-ns = <80>;
+ gpmc,bus-turnaround-ns = <0>;
+ gpmc,cycle2cycle-delay-ns = <0>;
+ gpmc,clk-activation-ns = <0>;
+ gpmc,wait-monitoring-ns = <0>;
+ gpmc,wr-data-mux-bus-ns = <0>;
+ /* MTD partition table */
+ /* All SPL-* partitions are sized to minimal length
+ * which can be independently programmable. For
+ * NAND flash this is equal to size of erase-block */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "NAND.SPL";
+ reg = <0x00000000 0x000020000>;
+ };
+ partition@1 {
+ label = "NAND.SPL.backup1";
+ reg = <0x00020000 0x00020000>;
+ };
+ partition@2 {
+ label = "NAND.SPL.backup2";
+ reg = <0x00040000 0x00020000>;
+ };
+ partition@3 {
+ label = "NAND.SPL.backup3";
+ reg = <0x00060000 0x00020000>;
+ };
+ partition@4 {
+ label = "NAND.u-boot-spl-os";
+ reg = <0x00080000 0x00040000>;
+ };
+ partition@5 {
+ label = "NAND.u-boot";
+ reg = <0x000c0000 0x00100000>;
+ };
+ partition@6 {
+ label = "NAND.u-boot-env";
+ reg = <0x001c0000 0x00020000>;
+ };
+ partition@7 {
+ label = "NAND.u-boot-env.backup1";
+ reg = <0x001e0000 0x00020000>;
+ };
+ partition@8 {
+ label = "NAND.kernel";
+ reg = <0x00200000 0x00800000>;
+ };
+ partition@9 {
+ label = "NAND.file-system";
+ reg = <0x00a00000 0x0f600000>;
+ };
+ };
+};
+
+&usb2_phy1 {
+ phy-supply = <&ldo4_reg>;
+};
+
+&usb2_phy2 {
+ phy-supply = <&ldo4_reg>;
+};
+
+&omap_dwc3_1 {
+ extcon = <&extcon_usb1>;
+};
+
+&omap_dwc3_2 {
+ extcon = <&extcon_usb2>;
+};
+
+&usb1 {
+ dr_mode = "peripheral";
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb1_pins>;
+};
+
+&usb2 {
+ dr_mode = "host";
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb2_pins>;
+};
+
+&mmc1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins_default>;
+
+ vmmc-supply = <&ldo1_reg>;
+ bus-width = <4>;
+ /*
+ * SDCD signal is not being used here - using the fact that GPIO mode
+ * is a viable alternative
+ */
+ cd-gpios = <&gpio6 27 0>;
+};
+
+&mmc2 {
+ /* SW5-3 in ON position */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins_default>;
+
+ vmmc-supply = <&evm_3v3>;
+ bus-width = <8>;
+ ti,non-removable;
+};
+
+&dra7_pmx_core {
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins = <
+ /* Slave 2 */
+ 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
+ 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
+ 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
+ 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
+ 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
+ 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
+ 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
+ 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
+ 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
+ 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
+ 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
+ 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
+ >;
+
+ };
+
+ cpsw_sleep: cpsw_sleep {
+ pinctrl-single,pins = <
+ /* Slave 2 */
+ 0x198 (MUX_MODE15)
+ 0x19c (MUX_MODE15)
+ 0x1a0 (MUX_MODE15)
+ 0x1a4 (MUX_MODE15)
+ 0x1a8 (MUX_MODE15)
+ 0x1ac (MUX_MODE15)
+ 0x1b0 (MUX_MODE15)
+ 0x1b4 (MUX_MODE15)
+ 0x1b8 (MUX_MODE15)
+ 0x1bc (MUX_MODE15)
+ 0x1c0 (MUX_MODE15)
+ 0x1c4 (MUX_MODE15)
+ >;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins = <
+ /* MDIO */
+ 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
+ 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
+ >;
+ };
+
+ davinci_mdio_sleep: davinci_mdio_sleep {
+ pinctrl-single,pins = <
+ 0x23c (MUX_MODE15)
+ 0x240 (MUX_MODE15)
+ >;
+ };
+};
+
+&mac {
+ status = "okay";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&cpsw_default>;
+ pinctrl-1 = <&cpsw_sleep>;
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <3>;
+ phy-mode = "rgmii";
+};
+
+&davinci_mdio {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&davinci_mdio_default>;
+ pinctrl-1 = <&davinci_mdio_sleep>;
+ active_slave = <1>;
+};
+
+&dcan1 {
+ status = "ok";
+ pinctrl-names = "default", "sleep", "active";
+ pinctrl-0 = <&dcan1_pins_sleep>;
+ pinctrl-1 = <&dcan1_pins_sleep>;
+ pinctrl-2 = <&dcan1_pins_default>;
+};
+
+&qspi {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qspi1_pins>;
+
+ spi-max-frequency = <48000000>;
+ m25p80@0 {
+ compatible = "s25fl256s1";
+ spi-max-frequency = <48000000>;
+ reg = <0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-cpol;
+ spi-cpha;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* MTD partition table.
+ * The ROM checks the first four physical blocks
+ * for a valid file to boot and the flash here is
+ * 64KiB block size.
+ */
+ partition@0 {
+ label = "QSPI.SPL";
+ reg = <0x00000000 0x000010000>;
+ };
+ partition@1 {
+ label = "QSPI.SPL.backup1";
+ reg = <0x00010000 0x00010000>;
+ };
+ partition@2 {
+ label = "QSPI.SPL.backup2";
+ reg = <0x00020000 0x00010000>;
+ };
+ partition@3 {
+ label = "QSPI.SPL.backup3";
+ reg = <0x00030000 0x00010000>;
+ };
+ partition@4 {
+ label = "QSPI.u-boot";
+ reg = <0x00040000 0x00100000>;
+ };
+ partition@5 {
+ label = "QSPI.u-boot-spl-os";
+ reg = <0x00140000 0x00080000>;
+ };
+ partition@6 {
+ label = "QSPI.u-boot-env";
+ reg = <0x001c0000 0x00010000>;
+ };
+ partition@7 {
+ label = "QSPI.u-boot-env.backup1";
+ reg = <0x001d0000 0x0010000>;
+ };
+ partition@8 {
+ label = "QSPI.kernel";
+ reg = <0x001e0000 0x0800000>;
+ };
+ partition@9 {
+ label = "QSPI.file-system";
+ reg = <0x009e0000 0x01620000>;
+ };
+ };
+};
+
+&dss {
+ status = "ok";
+
+ vdda_video-supply = <&ldo5_reg>;
+};
+
+&hdmi {
+ status = "ok";
+ vdda-supply = <&ldo3_reg>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_pins>;
+
+ port {
+ hdmi_out: endpoint {
+ remote-endpoint = <&tpd12s015_in>;
+ };
+ };
+};
diff --git a/arch/arm/dts/dra72x.dtsi b/arch/arm/dts/dra72x.dtsi
new file mode 100644
index 0000000..eaca143
--- /dev/null
+++ b/arch/arm/dts/dra72x.dtsi
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ * Based on "omap4.dtsi"
+ */
+
+#include "dra7.dtsi"
+
+/ {
+ compatible = "ti,dra722", "ti,dra72", "ti,dra7";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+
+ /* cooling options */
+ cooling-min-level = <0>;
+ cooling-max-level = <2>;
+ #cooling-cells = <2>; /* min followed by max */
+ };
+ };
+
+ pmu {
+ compatible = "arm,cortex-a15-pmu";
+ interrupt-parent = <&wakeupgen>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
+
+&dss {
+ reg = <0x58000000 0x80>,
+ <0x58004054 0x4>,
+ <0x58004300 0x20>;
+ reg-names = "dss", "pll1_clkctrl", "pll1";
+
+ clocks = <&dss_dss_clk>,
+ <&dss_video1_clk>;
+ clock-names = "fck", "video1_clk";
+};
diff --git a/arch/arm/dts/dra7xx-clocks.dtsi b/arch/arm/dts/dra7xx-clocks.dtsi
new file mode 100644
index 0000000..357bede
--- /dev/null
+++ b/arch/arm/dts/dra7xx-clocks.dtsi
@@ -0,0 +1,2149 @@
+/*
+ * Device Tree Source for DRA7xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&cm_core_aon_clocks {
+ atl_clkin0_ck: atl_clkin0_ck {
+ #clock-cells = <0>;
+ compatible = "ti,dra7-atl-clock";
+ clocks = <&atl_gfclk_mux>;
+ };
+
+ atl_clkin1_ck: atl_clkin1_ck {
+ #clock-cells = <0>;
+ compatible = "ti,dra7-atl-clock";
+ clocks = <&atl_gfclk_mux>;
+ };
+
+ atl_clkin2_ck: atl_clkin2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,dra7-atl-clock";
+ clocks = <&atl_gfclk_mux>;
+ };
+
+ atl_clkin3_ck: atl_clkin3_ck {
+ #clock-cells = <0>;
+ compatible = "ti,dra7-atl-clock";
+ clocks = <&atl_gfclk_mux>;
+ };
+
+ hdmi_clkin_ck: hdmi_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ mlb_clkin_ck: mlb_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ mlbp_clkin_ck: mlbp_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ pciesref_acs_clk_ck: pciesref_acs_clk_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ };
+
+ ref_clkin0_ck: ref_clkin0_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ ref_clkin1_ck: ref_clkin1_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ ref_clkin2_ck: ref_clkin2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ ref_clkin3_ck: ref_clkin3_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ rmii_clk_ck: rmii_clk_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ sdvenc_clkin_ck: sdvenc_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ sys_32k_ck: sys_32k_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ virt_12000000_ck: virt_12000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+ };
+
+ virt_13000000_ck: virt_13000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <13000000>;
+ };
+
+ virt_16800000_ck: virt_16800000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <16800000>;
+ };
+
+ virt_19200000_ck: virt_19200000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <19200000>;
+ };
+
+ virt_20000000_ck: virt_20000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <20000000>;
+ };
+
+ virt_26000000_ck: virt_26000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+ };
+
+ virt_27000000_ck: virt_27000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <27000000>;
+ };
+
+ virt_38400000_ck: virt_38400000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <38400000>;
+ };
+
+ sys_clkin2: sys_clkin2 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <22579200>;
+ };
+
+ usb_otg_clkin_ck: usb_otg_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ video1_clkin_ck: video1_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ video1_m2_clkin_ck: video1_m2_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ video2_clkin_ck: video2_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ video2_m2_clkin_ck: video2_m2_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ dpll_abe_ck: dpll_abe_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-m4xen-clock";
+ clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
+ reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
+ };
+
+ dpll_abe_x2_ck: dpll_abe_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_abe_ck>;
+ };
+
+ dpll_abe_m2x2_ck: dpll_abe_m2x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x01f0>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ abe_clk: abe_clk {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ ti,max-div = <4>;
+ reg = <0x0108>;
+ ti,index-power-of-two;
+ };
+
+ dpll_abe_m2_ck: dpll_abe_m2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x01f0>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x01f4>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_core_byp_mux: dpll_core_byp_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+ ti,bit-shift = <23>;
+ reg = <0x012c>;
+ };
+
+ dpll_core_ck: dpll_core_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-core-clock";
+ clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
+ reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
+ };
+
+ dpll_core_x2_ck: dpll_core_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_core_ck>;
+ };
+
+ dpll_core_h12x2_ck: dpll_core_h12x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x013c>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h12x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ dpll_mpu_ck: dpll_mpu_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap5-mpu-dpll-clock";
+ clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
+ reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
+ };
+
+ dpll_mpu_m2_ck: dpll_mpu_m2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_mpu_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0170>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ mpu_dclk_div: mpu_dclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_mpu_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h12x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ dpll_dsp_byp_mux: dpll_dsp_byp_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
+ ti,bit-shift = <23>;
+ reg = <0x0240>;
+ };
+
+ dpll_dsp_ck: dpll_dsp_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
+ reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
+ };
+
+ dpll_dsp_m2_ck: dpll_dsp_m2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_dsp_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0244>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h12x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ dpll_iva_byp_mux: dpll_iva_byp_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
+ ti,bit-shift = <23>;
+ reg = <0x01ac>;
+ };
+
+ dpll_iva_ck: dpll_iva_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
+ reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
+ };
+
+ dpll_iva_m2_ck: dpll_iva_m2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_iva_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x01b0>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ iva_dclk: iva_dclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_iva_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ dpll_gpu_byp_mux: dpll_gpu_byp_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+ ti,bit-shift = <23>;
+ reg = <0x02e4>;
+ };
+
+ dpll_gpu_ck: dpll_gpu_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
+ reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
+ };
+
+ dpll_gpu_m2_ck: dpll_gpu_m2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gpu_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x02e8>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_core_m2_ck: dpll_core_m2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0130>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ core_dpll_out_dclk_div: core_dpll_out_dclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ dpll_ddr_byp_mux: dpll_ddr_byp_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+ ti,bit-shift = <23>;
+ reg = <0x021c>;
+ };
+
+ dpll_ddr_ck: dpll_ddr_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
+ reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
+ };
+
+ dpll_ddr_m2_ck: dpll_ddr_m2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_ddr_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0220>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_gmac_byp_mux: dpll_gmac_byp_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+ ti,bit-shift = <23>;
+ reg = <0x02b4>;
+ };
+
+ dpll_gmac_ck: dpll_gmac_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
+ reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
+ };
+
+ dpll_gmac_m2_ck: dpll_gmac_m2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gmac_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x02b8>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ video2_dclk_div: video2_dclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&video2_m2_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ video1_dclk_div: video1_dclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&video1_m2_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ hdmi_dclk_div: hdmi_dclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&hdmi_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ per_dpll_hs_clk_div: per_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m3x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m3x2_ck>;
+ clock-mult = <1>;
+ clock-div = <3>;
+ };
+
+ eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h12x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ dpll_eve_byp_mux: dpll_eve_byp_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
+ ti,bit-shift = <23>;
+ reg = <0x0290>;
+ };
+
+ dpll_eve_ck: dpll_eve_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
+ reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
+ };
+
+ dpll_eve_m2_ck: dpll_eve_m2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_eve_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0294>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ eve_dclk_div: eve_dclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_eve_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ dpll_core_h13x2_ck: dpll_core_h13x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0140>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_core_h14x2_ck: dpll_core_h14x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0144>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_core_h22x2_ck: dpll_core_h22x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0154>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_core_h23x2_ck: dpll_core_h23x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0158>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_core_h24x2_ck: dpll_core_h24x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x015c>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_ddr_x2_ck: dpll_ddr_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_ddr_ck>;
+ };
+
+ dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_ddr_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0228>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_dsp_x2_ck: dpll_dsp_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_dsp_ck>;
+ };
+
+ dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_dsp_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0248>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_gmac_x2_ck: dpll_gmac_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_gmac_ck>;
+ };
+
+ dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gmac_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x02c0>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gmac_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x02c4>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gmac_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x02c8>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gmac_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x02bc>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ gmii_m_clk_div: gmii_m_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_gmac_h11x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ hdmi_clk2_div: hdmi_clk2_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&hdmi_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ hdmi_div_clk: hdmi_div_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&hdmi_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ l3_iclk_div: l3_iclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ ti,max-div = <2>;
+ ti,bit-shift = <4>;
+ reg = <0x0100>;
+ clocks = <&dpll_core_h12x2_ck>;
+ ti,index-power-of-two;
+ };
+
+ l4_root_clk_div: l4_root_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l3_iclk_div>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ video1_clk2_div: video1_clk2_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&video1_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ video1_div_clk: video1_div_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&video1_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ video2_clk2_div: video2_clk2_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&video2_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ video2_div_clk: video2_div_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&video2_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ ipu1_gfclk_mux: ipu1_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x0520>;
+ };
+
+ mcasp1_ahclkr_mux: mcasp1_ahclkr_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ ti,bit-shift = <28>;
+ reg = <0x0550>;
+ };
+
+ mcasp1_ahclkx_mux: mcasp1_ahclkx_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x0550>;
+ };
+
+ mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+ ti,bit-shift = <22>;
+ reg = <0x0550>;
+ };
+
+ timer5_gfclk_mux: timer5_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+ ti,bit-shift = <24>;
+ reg = <0x0558>;
+ };
+
+ timer6_gfclk_mux: timer6_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+ ti,bit-shift = <24>;
+ reg = <0x0560>;
+ };
+
+ timer7_gfclk_mux: timer7_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+ ti,bit-shift = <24>;
+ reg = <0x0568>;
+ };
+
+ timer8_gfclk_mux: timer8_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+ ti,bit-shift = <24>;
+ reg = <0x0570>;
+ };
+
+ uart6_gfclk_mux: uart6_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x0580>;
+ };
+
+ dummy_ck: dummy_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+};
+&prm_clocks {
+ sys_clkin1: sys_clkin1 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+ reg = <0x0110>;
+ ti,index-starts-at-one;
+ };
+
+ abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&sys_clkin2>;
+ reg = <0x0118>;
+ };
+
+ abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
+ reg = <0x0114>;
+ };
+
+ abe_dpll_clk_mux: abe_dpll_clk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
+ reg = <0x010c>;
+ };
+
+ abe_24m_fclk: abe_24m_fclk {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ reg = <0x011c>;
+ ti,dividers = <8>, <16>;
+ };
+
+ aess_fclk: aess_fclk {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&abe_clk>;
+ reg = <0x0178>;
+ ti,max-div = <2>;
+ };
+
+ abe_giclk_div: abe_giclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&aess_fclk>;
+ reg = <0x0174>;
+ ti,max-div = <2>;
+ };
+
+ abe_lp_clk_div: abe_lp_clk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ reg = <0x01d8>;
+ ti,dividers = <16>, <32>;
+ };
+
+ abe_sys_clk_div: abe_sys_clk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&sys_clkin1>;
+ reg = <0x0120>;
+ ti,max-div = <2>;
+ };
+
+ adc_gfclk_mux: adc_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
+ reg = <0x01dc>;
+ };
+
+ sys_clk1_dclk_div: sys_clk1_dclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&sys_clkin1>;
+ ti,max-div = <64>;
+ reg = <0x01c8>;
+ ti,index-power-of-two;
+ };
+
+ sys_clk2_dclk_div: sys_clk2_dclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&sys_clkin2>;
+ ti,max-div = <64>;
+ reg = <0x01cc>;
+ ti,index-power-of-two;
+ };
+
+ per_abe_x1_dclk_div: per_abe_x1_dclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_m2_ck>;
+ ti,max-div = <64>;
+ reg = <0x01bc>;
+ ti,index-power-of-two;
+ };
+
+ dsp_gclk_div: dsp_gclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_dsp_m2_ck>;
+ ti,max-div = <64>;
+ reg = <0x018c>;
+ ti,index-power-of-two;
+ };
+
+ gpu_dclk: gpu_dclk {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gpu_m2_ck>;
+ ti,max-div = <64>;
+ reg = <0x01a0>;
+ ti,index-power-of-two;
+ };
+
+ emif_phy_dclk_div: emif_phy_dclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_ddr_m2_ck>;
+ ti,max-div = <64>;
+ reg = <0x0190>;
+ ti,index-power-of-two;
+ };
+
+ gmac_250m_dclk_div: gmac_250m_dclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gmac_m2_ck>;
+ ti,max-div = <64>;
+ reg = <0x019c>;
+ ti,index-power-of-two;
+ };
+
+ l3init_480m_dclk_div: l3init_480m_dclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_usb_m2_ck>;
+ ti,max-div = <64>;
+ reg = <0x01ac>;
+ ti,index-power-of-two;
+ };
+
+ usb_otg_dclk_div: usb_otg_dclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&usb_otg_clkin_ck>;
+ ti,max-div = <64>;
+ reg = <0x0184>;
+ ti,index-power-of-two;
+ };
+
+ sata_dclk_div: sata_dclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&sys_clkin1>;
+ ti,max-div = <64>;
+ reg = <0x01c0>;
+ ti,index-power-of-two;
+ };
+
+ pcie2_dclk_div: pcie2_dclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_pcie_ref_m2_ck>;
+ ti,max-div = <64>;
+ reg = <0x01b8>;
+ ti,index-power-of-two;
+ };
+
+ pcie_dclk_div: pcie_dclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&apll_pcie_m2_ck>;
+ ti,max-div = <64>;
+ reg = <0x01b4>;
+ ti,index-power-of-two;
+ };
+
+ emu_dclk_div: emu_dclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&sys_clkin1>;
+ ti,max-div = <64>;
+ reg = <0x0194>;
+ ti,index-power-of-two;
+ };
+
+ secure_32k_dclk_div: secure_32k_dclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&secure_32k_clk_src_ck>;
+ ti,max-div = <64>;
+ reg = <0x01c4>;
+ ti,index-power-of-two;
+ };
+
+ clkoutmux0_clk_mux: clkoutmux0_clk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
+ reg = <0x0158>;
+ };
+
+ clkoutmux1_clk_mux: clkoutmux1_clk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
+ reg = <0x015c>;
+ };
+
+ clkoutmux2_clk_mux: clkoutmux2_clk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
+ reg = <0x0160>;
+ };
+
+ custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin1>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ eve_clk: eve_clk {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
+ reg = <0x0180>;
+ };
+
+ hdmi_dpll_clk_mux: hdmi_dpll_clk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&sys_clkin2>;
+ reg = <0x0164>;
+ };
+
+ mlb_clk: mlb_clk {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&mlb_clkin_ck>;
+ ti,max-div = <64>;
+ reg = <0x0134>;
+ ti,index-power-of-two;
+ };
+
+ mlbp_clk: mlbp_clk {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&mlbp_clkin_ck>;
+ ti,max-div = <64>;
+ reg = <0x0130>;
+ ti,index-power-of-two;
+ };
+
+ per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_m2_ck>;
+ ti,max-div = <64>;
+ reg = <0x0138>;
+ ti,index-power-of-two;
+ };
+
+ timer_sys_clk_div: timer_sys_clk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&sys_clkin1>;
+ reg = <0x0144>;
+ ti,max-div = <2>;
+ };
+
+ video1_dpll_clk_mux: video1_dpll_clk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&sys_clkin2>;
+ reg = <0x0168>;
+ };
+
+ video2_dpll_clk_mux: video2_dpll_clk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&sys_clkin2>;
+ reg = <0x016c>;
+ };
+
+ wkupaon_iclk_mux: wkupaon_iclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
+ reg = <0x0108>;
+ };
+
+ gpio1_dbclk: gpio1_dbclk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x1838>;
+ };
+
+ dcan1_sys_clk_mux: dcan1_sys_clk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&sys_clkin2>;
+ ti,bit-shift = <24>;
+ reg = <0x1888>;
+ };
+
+ timer1_gfclk_mux: timer1_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x1840>;
+ };
+
+ uart10_gfclk_mux: uart10_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x1880>;
+ };
+};
+&cm_core_clocks {
+ dpll_pcie_ref_ck: dpll_pcie_ref_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&sys_clkin1>;
+ reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
+ };
+
+ dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_pcie_ref_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0210>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
+ #clock-cells = <0>;
+ reg = <0x021c 0x4>;
+ ti,bit-shift = <7>;
+ };
+
+ apll_pcie_ck: apll_pcie_ck {
+ #clock-cells = <0>;
+ compatible = "ti,dra7-apll-clock";
+ clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
+ reg = <0x021c>, <0x0220>;
+ };
+
+ optfclk_pciephy1_32khz: optfclk_pciephy1_32khz@4a0093b0 {
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ #clock-cells = <0>;
+ reg = <0x13b0>;
+ ti,bit-shift = <8>;
+ };
+
+ optfclk_pciephy2_32khz: optfclk_pciephy2_32khz@4a0093b8 {
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ #clock-cells = <0>;
+ reg = <0x13b8>;
+ ti,bit-shift = <8>;
+ };
+
+ optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
+ compatible = "ti,divider-clock";
+ clocks = <&apll_pcie_ck>;
+ #clock-cells = <0>;
+ reg = <0x021c>;
+ ti,dividers = <2>, <1>;
+ ti,bit-shift = <8>;
+ ti,max-div = <2>;
+ };
+
+ optfclk_pciephy1_clk: optfclk_pciephy1_clk@4a0093b0 {
+ compatible = "ti,gate-clock";
+ clocks = <&apll_pcie_ck>;
+ #clock-cells = <0>;
+ reg = <0x13b0>;
+ ti,bit-shift = <9>;
+ };
+
+ optfclk_pciephy2_clk: optfclk_pciephy2_clk@4a0093b8 {
+ compatible = "ti,gate-clock";
+ clocks = <&apll_pcie_ck>;
+ #clock-cells = <0>;
+ reg = <0x13b8>;
+ ti,bit-shift = <9>;
+ };
+
+ optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk@4a0093b0 {
+ compatible = "ti,gate-clock";
+ clocks = <&optfclk_pciephy_div>;
+ #clock-cells = <0>;
+ reg = <0x13b0>;
+ ti,bit-shift = <10>;
+ };
+
+ optfclk_pciephy2_div_clk: optfclk_pciephy2_div_clk@4a0093b8 {
+ compatible = "ti,gate-clock";
+ clocks = <&optfclk_pciephy_div>;
+ #clock-cells = <0>;
+ reg = <0x13b8>;
+ ti,bit-shift = <10>;
+ };
+
+ apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&apll_pcie_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&apll_pcie_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ apll_pcie_m2_ck: apll_pcie_m2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&apll_pcie_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ dpll_per_byp_mux: dpll_per_byp_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
+ ti,bit-shift = <23>;
+ reg = <0x014c>;
+ };
+
+ dpll_per_ck: dpll_per_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
+ reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
+ };
+
+ dpll_per_m2_ck: dpll_per_m2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0150>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ func_96m_aon_dclk_div: func_96m_aon_dclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ dpll_usb_byp_mux: dpll_usb_byp_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
+ ti,bit-shift = <23>;
+ reg = <0x018c>;
+ };
+
+ dpll_usb_ck: dpll_usb_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-j-type-clock";
+ clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
+ reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
+ };
+
+ dpll_usb_m2_ck: dpll_usb_m2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_usb_ck>;
+ ti,max-div = <127>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0190>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_pcie_ref_ck>;
+ ti,max-div = <127>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0210>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_per_x2_ck: dpll_per_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_per_ck>;
+ };
+
+ dpll_per_h11x2_ck: dpll_per_h11x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0158>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_per_h12x2_ck: dpll_per_h12x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x015c>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_per_h13x2_ck: dpll_per_h13x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0160>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_per_h14x2_ck: dpll_per_h14x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0164>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_per_m2x2_ck: dpll_per_m2x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0150>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_usb_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ func_128m_clk: func_128m_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_h11x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ func_12m_fclk: func_12m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <16>;
+ };
+
+ func_24m_clk: func_24m_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+ };
+
+ func_48m_fclk: func_48m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+ };
+
+ func_96m_fclk: func_96m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ l3init_60m_fclk: l3init_60m_fclk {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_usb_m2_ck>;
+ reg = <0x0104>;
+ ti,dividers = <1>, <8>;
+ };
+
+ clkout2_clk: clkout2_clk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&clkoutmux2_clk_mux>;
+ ti,bit-shift = <8>;
+ reg = <0x06b0>;
+ };
+
+ l3init_960m_gfclk: l3init_960m_gfclk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_usb_clkdcoldo>;
+ ti,bit-shift = <8>;
+ reg = <0x06c0>;
+ };
+
+ dss_32khz_clk: dss_32khz_clk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <11>;
+ reg = <0x1120>;
+ };
+
+ dss_48mhz_clk: dss_48mhz_clk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&func_48m_fclk>;
+ ti,bit-shift = <9>;
+ reg = <0x1120>;
+ };
+
+ dss_dss_clk: dss_dss_clk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_per_h12x2_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x1120>;
+ ti,set-rate-parent;
+ };
+
+ dss_hdmi_clk: dss_hdmi_clk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&hdmi_dpll_clk_mux>;
+ ti,bit-shift = <10>;
+ reg = <0x1120>;
+ };
+
+ dss_video1_clk: dss_video1_clk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&video1_dpll_clk_mux>;
+ ti,bit-shift = <12>;
+ reg = <0x1120>;
+ };
+
+ dss_video2_clk: dss_video2_clk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&video2_dpll_clk_mux>;
+ ti,bit-shift = <13>;
+ reg = <0x1120>;
+ };
+
+ gpio2_dbclk: gpio2_dbclk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x1760>;
+ };
+
+ gpio3_dbclk: gpio3_dbclk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x1768>;
+ };
+
+ gpio4_dbclk: gpio4_dbclk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x1770>;
+ };
+
+ gpio5_dbclk: gpio5_dbclk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x1778>;
+ };
+
+ gpio6_dbclk: gpio6_dbclk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x1780>;
+ };
+
+ gpio7_dbclk: gpio7_dbclk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x1810>;
+ };
+
+ gpio8_dbclk: gpio8_dbclk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x1818>;
+ };
+
+ mmc1_clk32k: mmc1_clk32k {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x1328>;
+ };
+
+ mmc2_clk32k: mmc2_clk32k {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x1330>;
+ };
+
+ mmc3_clk32k: mmc3_clk32k {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x1820>;
+ };
+
+ mmc4_clk32k: mmc4_clk32k {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x1828>;
+ };
+
+ sata_ref_clk: sata_ref_clk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_clkin1>;
+ ti,bit-shift = <8>;
+ reg = <0x1388>;
+ };
+
+ usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l3init_960m_gfclk>;
+ ti,bit-shift = <8>;
+ reg = <0x13f0>;
+ };
+
+ usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l3init_960m_gfclk>;
+ ti,bit-shift = <8>;
+ reg = <0x1340>;
+ };
+
+ usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0640>;
+ };
+
+ usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0688>;
+ };
+
+ usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0698>;
+ };
+
+ atl_dpll_clk_mux: atl_dpll_clk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x0c00>;
+ };
+
+ atl_gfclk_mux: atl_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>;
+ ti,bit-shift = <26>;
+ reg = <0x0c00>;
+ };
+
+ gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gmac_m2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x13d0>;
+ ti,dividers = <2>;
+ };
+
+ gmac_rft_clk_mux: gmac_rft_clk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>;
+ ti,bit-shift = <25>;
+ reg = <0x13d0>;
+ };
+
+ gpu_core_gclk_mux: gpu_core_gclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x1220>;
+ };
+
+ gpu_hyd_gclk_mux: gpu_hyd_gclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
+ ti,bit-shift = <26>;
+ reg = <0x1220>;
+ };
+
+ l3instr_ts_gclk_div: l3instr_ts_gclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&wkupaon_iclk_mux>;
+ ti,bit-shift = <24>;
+ reg = <0x0e50>;
+ ti,dividers = <8>, <16>, <32>;
+ };
+
+ mcasp2_ahclkr_mux: mcasp2_ahclkr_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ ti,bit-shift = <28>;
+ reg = <0x1860>;
+ };
+
+ mcasp2_ahclkx_mux: mcasp2_ahclkx_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x1860>;
+ };
+
+ mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+ ti,bit-shift = <22>;
+ reg = <0x1860>;
+ };
+
+ mcasp3_ahclkx_mux: mcasp3_ahclkx_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x1868>;
+ };
+
+ mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+ ti,bit-shift = <22>;
+ reg = <0x1868>;
+ };
+
+ mcasp4_ahclkx_mux: mcasp4_ahclkx_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x1898>;
+ };
+
+ mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+ ti,bit-shift = <22>;
+ reg = <0x1898>;
+ };
+
+ mcasp5_ahclkx_mux: mcasp5_ahclkx_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x1878>;
+ };
+
+ mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+ ti,bit-shift = <22>;
+ reg = <0x1878>;
+ };
+
+ mcasp6_ahclkx_mux: mcasp6_ahclkx_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x1904>;
+ };
+
+ mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+ ti,bit-shift = <22>;
+ reg = <0x1904>;
+ };
+
+ mcasp7_ahclkx_mux: mcasp7_ahclkx_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x1908>;
+ };
+
+ mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+ ti,bit-shift = <22>;
+ reg = <0x1908>;
+ };
+
+ mcasp8_ahclk_mux: mcasp8_ahclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ ti,bit-shift = <22>;
+ reg = <0x1890>;
+ };
+
+ mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+ ti,bit-shift = <24>;
+ reg = <0x1890>;
+ };
+
+ mmc1_fclk_mux: mmc1_fclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x1328>;
+ };
+
+ mmc1_fclk_div: mmc1_fclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&mmc1_fclk_mux>;
+ ti,bit-shift = <25>;
+ ti,max-div = <4>;
+ reg = <0x1328>;
+ ti,index-power-of-two;
+ };
+
+ mmc2_fclk_mux: mmc2_fclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x1330>;
+ };
+
+ mmc2_fclk_div: mmc2_fclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&mmc2_fclk_mux>;
+ ti,bit-shift = <25>;
+ ti,max-div = <4>;
+ reg = <0x1330>;
+ ti,index-power-of-two;
+ };
+
+ mmc3_gfclk_mux: mmc3_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x1820>;
+ };
+
+ mmc3_gfclk_div: mmc3_gfclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&mmc3_gfclk_mux>;
+ ti,bit-shift = <25>;
+ ti,max-div = <4>;
+ reg = <0x1820>;
+ ti,index-power-of-two;
+ };
+
+ mmc4_gfclk_mux: mmc4_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x1828>;
+ };
+
+ mmc4_gfclk_div: mmc4_gfclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&mmc4_gfclk_mux>;
+ ti,bit-shift = <25>;
+ ti,max-div = <4>;
+ reg = <0x1828>;
+ ti,index-power-of-two;
+ };
+
+ qspi_gfclk_mux: qspi_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x1838>;
+ };
+
+ qspi_gfclk_div: qspi_gfclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&qspi_gfclk_mux>;
+ ti,bit-shift = <25>;
+ ti,max-div = <4>;
+ reg = <0x1838>;
+ ti,index-power-of-two;
+ };
+
+ timer10_gfclk_mux: timer10_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x1728>;
+ };
+
+ timer11_gfclk_mux: timer11_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x1730>;
+ };
+
+ timer13_gfclk_mux: timer13_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x17c8>;
+ };
+
+ timer14_gfclk_mux: timer14_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x17d0>;
+ };
+
+ timer15_gfclk_mux: timer15_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x17d8>;
+ };
+
+ timer16_gfclk_mux: timer16_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x1830>;
+ };
+
+ timer2_gfclk_mux: timer2_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x1738>;
+ };
+
+ timer3_gfclk_mux: timer3_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x1740>;
+ };
+
+ timer4_gfclk_mux: timer4_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x1748>;
+ };
+
+ timer9_gfclk_mux: timer9_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x1750>;
+ };
+
+ uart1_gfclk_mux: uart1_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x1840>;
+ };
+
+ uart2_gfclk_mux: uart2_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x1848>;
+ };
+
+ uart3_gfclk_mux: uart3_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x1850>;
+ };
+
+ uart4_gfclk_mux: uart4_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x1858>;
+ };
+
+ uart5_gfclk_mux: uart5_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x1870>;
+ };
+
+ uart7_gfclk_mux: uart7_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x18d0>;
+ };
+
+ uart8_gfclk_mux: uart8_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x18e0>;
+ };
+
+ uart9_gfclk_mux: uart9_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x18e8>;
+ };
+
+ vip1_gclk_mux: vip1_gclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x1020>;
+ };
+
+ vip2_gclk_mux: vip2_gclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x1028>;
+ };
+
+ vip3_gclk_mux: vip3_gclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x1030>;
+ };
+};
+
+&cm_core_clockdomains {
+ coreaon_clkdm: coreaon_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll_usb_ck>;
+ };
+};
+
+&scm_conf_clocks {
+ dss_deshdcp_clk: dss_deshdcp_clk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l3_iclk_div>;
+ ti,bit-shift = <0>;
+ reg = <0x558>;
+ };
+};
diff --git a/arch/arm/dts/omap4-cpu-thermal.dtsi b/arch/arm/dts/omap4-cpu-thermal.dtsi
new file mode 100644
index 0000000..ab7f87a
--- /dev/null
+++ b/arch/arm/dts/omap4-cpu-thermal.dtsi
@@ -0,0 +1,41 @@
+/*
+ * Device Tree Source for OMAP4/5 SoC CPU thermal
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Contact: Eduardo Valentin <eduardo.valentin@ti.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/thermal/thermal.h>
+
+cpu_thermal: cpu_thermal {
+ polling-delay-passive = <250>; /* milliseconds */
+ polling-delay = <1000>; /* milliseconds */
+
+ /* sensor ID */
+ thermal-sensors = <&bandgap 0>;
+
+ cpu_trips: trips {
+ cpu_alert0: cpu_alert {
+ temperature = <100000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+ cpu_crit: cpu_crit {
+ temperature = <125000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "critical";
+ };
+ };
+
+ cpu_cooling_maps: cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device =
+ <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+};
diff --git a/arch/arm/dts/omap5-core-thermal.dtsi b/arch/arm/dts/omap5-core-thermal.dtsi
new file mode 100644
index 0000000..de8a3d4
--- /dev/null
+++ b/arch/arm/dts/omap5-core-thermal.dtsi
@@ -0,0 +1,28 @@
+/*
+ * Device Tree Source for OMAP543x SoC CORE thermal
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Contact: Eduardo Valentin <eduardo.valentin@ti.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/thermal/thermal.h>
+
+core_thermal: core_thermal {
+ polling-delay-passive = <250>; /* milliseconds */
+ polling-delay = <500>; /* milliseconds */
+
+ /* sensor ID */
+ thermal-sensors = <&bandgap 2>;
+
+ trips {
+ core_crit: core_crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+};
diff --git a/arch/arm/dts/omap5-gpu-thermal.dtsi b/arch/arm/dts/omap5-gpu-thermal.dtsi
new file mode 100644
index 0000000..bc3090f
--- /dev/null
+++ b/arch/arm/dts/omap5-gpu-thermal.dtsi
@@ -0,0 +1,28 @@
+/*
+ * Device Tree Source for OMAP543x SoC GPU thermal
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Contact: Eduardo Valentin <eduardo.valentin@ti.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/thermal/thermal.h>
+
+gpu_thermal: gpu_thermal {
+ polling-delay-passive = <250>; /* milliseconds */
+ polling-delay = <500>; /* milliseconds */
+
+ /* sensor ID */
+ thermal-sensors = <&bandgap 1>;
+
+ trips {
+ gpu_crit: gpu_crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+};
diff --git a/arch/arm/dts/tps65910.dtsi b/arch/arm/dts/tps65910.dtsi
new file mode 100644
index 0000000..b0ac665
--- /dev/null
+++ b/arch/arm/dts/tps65910.dtsi
@@ -0,0 +1,91 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Integrated Power Management Chip
+ * http://www.ti.com/lit/ds/symlink/tps65910.pdf
+ */
+
+&tps {
+ compatible = "ti,tps65910";
+
+ regulators {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vrtc_reg: regulator@0 {
+ reg = <0>;
+ regulator-compatible = "vrtc";
+ };
+
+ vio_reg: regulator@1 {
+ reg = <1>;
+ regulator-compatible = "vio";
+ };
+
+ vdd1_reg: regulator@2 {
+ reg = <2>;
+ regulator-compatible = "vdd1";
+ };
+
+ vdd2_reg: regulator@3 {
+ reg = <3>;
+ regulator-compatible = "vdd2";
+ };
+
+ vdd3_reg: regulator@4 {
+ reg = <4>;
+ regulator-compatible = "vdd3";
+ };
+
+ vdig1_reg: regulator@5 {
+ reg = <5>;
+ regulator-compatible = "vdig1";
+ };
+
+ vdig2_reg: regulator@6 {
+ reg = <6>;
+ regulator-compatible = "vdig2";
+ };
+
+ vpll_reg: regulator@7 {
+ reg = <7>;
+ regulator-compatible = "vpll";
+ };
+
+ vdac_reg: regulator@8 {
+ reg = <8>;
+ regulator-compatible = "vdac";
+ };
+
+ vaux1_reg: regulator@9 {
+ reg = <9>;
+ regulator-compatible = "vaux1";
+ };
+
+ vaux2_reg: regulator@10 {
+ reg = <10>;
+ regulator-compatible = "vaux2";
+ };
+
+ vaux33_reg: regulator@11 {
+ reg = <11>;
+ regulator-compatible = "vaux33";
+ };
+
+ vmmc_reg: regulator@12 {
+ reg = <12>;
+ regulator-compatible = "vmmc";
+ };
+
+ vbb_reg: regulator@13 {
+ reg = <13>;
+ regulator-compatible = "vbb";
+ };
+ };
+};
diff --git a/arch/arm/include/asm/arch-am33xx/gpio.h b/arch/arm/include/asm/arch-am33xx/gpio.h
index 220603d..89ab055 100644
--- a/arch/arm/include/asm/arch-am33xx/gpio.h
+++ b/arch/arm/include/asm/arch-am33xx/gpio.h
@@ -6,7 +6,11 @@
#include <asm/omap_gpio.h>
+#ifdef CONFIG_AM43XX
+#define OMAP_MAX_GPIO 192
+#else
#define OMAP_MAX_GPIO 128
+#endif
#define AM33XX_GPIO0_BASE 0x44E07000
#define AM33XX_GPIO1_BASE 0x4804C000
diff --git a/arch/arm/include/asm/arch-bcmcygnus/configs.h b/arch/arm/include/asm/arch-bcmcygnus/configs.h
index 5354637..3c07160 100644
--- a/arch/arm/include/asm/arch-bcmcygnus/configs.h
+++ b/arch/arm/include/asm/arch-bcmcygnus/configs.h
@@ -22,4 +22,15 @@
#define CONFIG_CONS_INDEX 3
#define CONFIG_SYS_NS16550_COM3 0x18023000
+/* Ethernet */
+#define CONFIG_BCM_SF2_ETH
+#define CONFIG_BCM_SF2_ETH_GMAC
+
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_BROADCOM
+#define CONFIG_PHY_RESET_DELAY 10000 /* PHY reset delay in us*/
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+
#endif /* __ARCH_CONFIGS_H */
diff --git a/arch/arm/include/asm/arch-hi6220/dwmmc.h b/arch/arm/include/asm/arch-hi6220/dwmmc.h
new file mode 100644
index 0000000..c747383
--- /dev/null
+++ b/arch/arm/include/asm/arch-hi6220/dwmmc.h
@@ -0,0 +1,8 @@
+/*
+ * (C) Copyright 2015 Linaro
+ * Peter Griffin <peter.griffin@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+int hi6220_dwmci_add_port(int index, u32 regbase, int bus_width);
diff --git a/arch/arm/include/asm/arch-hi6220/gpio.h b/arch/arm/include/asm/arch-hi6220/gpio.h
new file mode 100644
index 0000000..98122a2
--- /dev/null
+++ b/arch/arm/include/asm/arch-hi6220/gpio.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2015 Linaro
+ * Peter Griffin <peter.griffin@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _HI6220_GPIO_H_
+#define _HI6220_GPIO_H_
+
+#define HI6220_GPIO_BASE(bank) (((bank < 4) ? 0xf8011000 : \
+ 0xf7020000 - 0x4000) + (0x1000 * bank))
+
+#define BIT(x) (1 << (x))
+
+#define HI6220_GPIO_PER_BANK 8
+#define HI6220_GPIO_DIR 0x400
+
+struct gpio_bank {
+ u8 *base; /* address of registers in physical memory */
+};
+
+/* Information about a GPIO bank */
+struct hikey_gpio_platdata {
+ int bank_index;
+ unsigned int base; /* address of registers in physical memory */
+};
+
+#endif /* _HI6220_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-hi6220/hi6220.h b/arch/arm/include/asm/arch-hi6220/hi6220.h
new file mode 100644
index 0000000..4b987c2
--- /dev/null
+++ b/arch/arm/include/asm/arch-hi6220/hi6220.h
@@ -0,0 +1,387 @@
+/*
+ * (C) Copyright 2015 Linaro
+ * Peter Griffin <peter.griffin@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __HI6220_H__
+#define __HI6220_H__
+
+#include "hi6220_regs_alwayson.h"
+
+#define HI6220_MMC0_BASE 0xF723D000
+#define HI6220_MMC1_BASE 0xF723E000
+
+#define HI6220_PMUSSI_BASE 0xF8000000
+
+#define HI6220_PERI_BASE 0xF7030000
+
+struct peri_sc_periph_regs {
+ u32 ctrl1; /*0x0*/
+ u32 ctrl2;
+ u32 ctrl3;
+ u32 ctrl4;
+ u32 ctrl5;
+ u32 ctrl6;
+ u32 ctrl8;
+ u32 ctrl9;
+ u32 ctrl10;
+ u32 ctrl12;
+ u32 ctrl13;
+ u32 ctrl14;
+
+ u32 unknown_1[8];
+
+ u32 ddr_ctrl0; /*0x50*/
+
+ u32 unknown_2[16];
+
+ u32 stat1; /*0x94*/
+
+ u32 unknown_3[90];
+
+ u32 clk0_en; /*0x200*/
+ u32 clk0_dis;
+ u32 clk0_stat;
+
+ u32 unknown_4;
+
+ u32 clk1_en; /*0x210*/
+ u32 clk1_dis;
+ u32 clk1_stat;
+
+ u32 unknown_5;
+
+ u32 clk2_en; /*0x220*/
+ u32 clk2_dis;
+ u32 clk2_stat;
+
+ u32 unknown_6;
+
+ u32 clk3_en; /*0x230*/
+ u32 clk3_dis;
+ u32 clk3_stat;
+
+ u32 unknown_7;
+
+ u32 clk8_en; /*0x240*/
+ u32 clk8_dis;
+ u32 clk8_stat;
+
+ u32 unknown_8;
+
+ u32 clk9_en; /*0x250*/
+ u32 clk9_dis;
+ u32 clk9_stat;
+
+ u32 unknown_9;
+
+ u32 clk10_en; /*0x260*/
+ u32 clk10_dis;
+ u32 clk10_stat;
+
+ u32 unknown_10;
+
+ u32 clk12_en; /*0x270*/
+ u32 clk12_dis;
+ u32 clk12_stat;
+
+ u32 unknown_11[33];
+
+ u32 rst0_en; /*0x300*/
+ u32 rst0_dis;
+ u32 rst0_stat;
+
+ u32 unknown_12;
+
+ u32 rst1_en; /*0x310*/
+ u32 rst1_dis;
+ u32 rst1_stat;
+
+ u32 unknown_13;
+
+ u32 rst2_en; /*0x320*/
+ u32 rst2_dis;
+ u32 rst2_stat;
+
+ u32 unknown_14;
+
+ u32 rst3_en; /*0x330*/
+ u32 rst3_dis;
+ u32 rst3_stat;
+
+ u32 unknown_15;
+
+ u32 rst8_en; /*0x340*/
+ u32 rst8_dis;
+ u32 rst8_stat;
+
+ u32 unknown_16[45];
+
+ u32 clk0_sel; /*0x400*/
+
+ u32 unknown_17[36];
+
+ u32 clkcfg8bit1; /*0x494*/
+ u32 clkcfg8bit2;
+
+ u32 unknown_18[538];
+
+ u32 reserved8_addr; /*0xd04*/
+};
+
+
+/* CTRL1 bit definitions */
+
+#define PERI_CTRL1_ETR_AXI_CSYSREQ_N (1 << 0)
+#define PERI_CTRL1_HIFI_INT_MASK (1 << 1)
+#define PERI_CTRL1_HIFI_ALL_INT_MASK (1 << 2)
+#define PERI_CTRL1_ETR_AXI_CSYSREQ_N_MSK (1 << 16)
+#define PERI_CTRL1_HIFI_INT_MASK_MSK (1 << 17)
+#define PERI_CTRL1_HIFI_ALL_INT_MASK_MSK (1 << 18)
+
+
+/* CTRL2 bit definitions */
+
+#define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC0 (1 << 0)
+#define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC1 (1 << 2)
+#define PERI_CTRL2_NAND_SYS_MEM_SEL (1 << 6)
+#define PERI_CTRL2_G3D_DDRT_AXI_SEL (1 << 7)
+#define PERI_CTRL2_GU_MDM_BBP_TESTPIN_SEL (1 << 8)
+#define PERI_CTRL2_CODEC_SSI_MASTER_CHECK (1 << 9)
+#define PERI_CTRL2_FUNC_TEST_SOFT (1 << 12)
+#define PERI_CTRL2_CSSYS_TS_ENABLE (1 << 15)
+#define PERI_CTRL2_HIFI_RAMCTRL_S_EMA (1 << 16)
+#define PERI_CTRL2_HIFI_RAMCTRL_S_EMAW (1 << 20)
+#define PERI_CTRL2_HIFI_RAMCTRL_S_EMAS (1 << 22)
+#define PERI_CTRL2_HIFI_RAMCTRL_S_RET1N (1 << 26)
+#define PERI_CTRL2_HIFI_RAMCTRL_S_RET2N (1 << 27)
+#define PERI_CTRL2_HIFI_RAMCTRL_S_PGEN (1 << 28)
+
+/* CTRL3 bit definitions */
+
+#define PERI_CTRL3_HIFI_DDR_HARQMEM_ADDR (1 << 0)
+#define PERI_CTRL3_HIFI_HARQMEMRMP_EN (1 << 12)
+#define PERI_CTRL3_HARQMEM_SYS_MED_SEL (1 << 13)
+#define PERI_CTRL3_SOC_AP_OCCUPY_GRP1 (1 << 14)
+#define PERI_CTRL3_SOC_AP_OCCUPY_GRP2 (1 << 16)
+#define PERI_CTRL3_SOC_AP_OCCUPY_GRP3 (1 << 18)
+#define PERI_CTRL3_SOC_AP_OCCUPY_GRP4 (1 << 20)
+#define PERI_CTRL3_SOC_AP_OCCUPY_GRP5 (1 << 22)
+#define PERI_CTRL3_SOC_AP_OCCUPY_GRP6 (1 << 24)
+
+/* CTRL4 bit definitions */
+
+#define PERI_CTRL4_PICO_FSELV (1 << 0)
+#define PERI_CTRL4_FPGA_EXT_PHY_SEL (1 << 3)
+#define PERI_CTRL4_PICO_REFCLKSEL (1 << 4)
+#define PERI_CTRL4_PICO_SIDDQ (1 << 6)
+#define PERI_CTRL4_PICO_SUSPENDM_SLEEPM (1 << 7)
+#define PERI_CTRL4_PICO_OGDISABLE (1 << 8)
+#define PERI_CTRL4_PICO_COMMONONN (1 << 9)
+#define PERI_CTRL4_PICO_VBUSVLDEXT (1 << 10)
+#define PERI_CTRL4_PICO_VBUSVLDEXTSEL (1 << 11)
+#define PERI_CTRL4_PICO_VATESTENB (1 << 12)
+#define PERI_CTRL4_PICO_SUSPENDM (1 << 14)
+#define PERI_CTRL4_PICO_SLEEPM (1 << 15)
+#define PERI_CTRL4_BC11_C (1 << 16)
+#define PERI_CTRL4_BC11_B (1 << 17)
+#define PERI_CTRL4_BC11_A (1 << 18)
+#define PERI_CTRL4_BC11_GND (1 << 19)
+#define PERI_CTRL4_BC11_FLOAT (1 << 20)
+#define PERI_CTRL4_OTG_PHY_SEL (1 << 21)
+#define PERI_CTRL4_USB_OTG_SS_SCALEDOWN_MODE (1 << 22)
+#define PERI_CTRL4_OTG_DM_PULLDOWN (1 << 24)
+#define PERI_CTRL4_OTG_DP_PULLDOWN (1 << 25)
+#define PERI_CTRL4_OTG_IDPULLUP (1 << 26)
+#define PERI_CTRL4_OTG_DRVBUS (1 << 27)
+#define PERI_CTRL4_OTG_SESSEND (1 << 28)
+#define PERI_CTRL4_OTG_BVALID (1 << 29)
+#define PERI_CTRL4_OTG_AVALID (1 << 30)
+#define PERI_CTRL4_OTG_VBUSVALID (1 << 31)
+
+/* CTRL5 bit definitions */
+
+#define PERI_CTRL5_USBOTG_RES_SEL (1 << 3)
+#define PERI_CTRL5_PICOPHY_ACAENB (1 << 4)
+#define PERI_CTRL5_PICOPHY_BC_MODE (1 << 5)
+#define PERI_CTRL5_PICOPHY_CHRGSEL (1 << 6)
+#define PERI_CTRL5_PICOPHY_VDATSRCEND (1 << 7)
+#define PERI_CTRL5_PICOPHY_VDATDETENB (1 << 8)
+#define PERI_CTRL5_PICOPHY_DCDENB (1 << 9)
+#define PERI_CTRL5_PICOPHY_IDDIG (1 << 10)
+#define PERI_CTRL5_DBG_MUX (1 << 11)
+
+/* CTRL6 bit definitions */
+
+#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMA (1 << 0)
+#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMAW (1 << 4)
+#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMAS (1 << 6)
+#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_RET1N (1 << 10)
+#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_RET2N (1 << 11)
+#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_PGEN (1 << 12)
+
+/* CTRL8 bit definitions */
+
+#define PERI_CTRL8_PICOPHY_TXRISETUNE0 (1 << 0)
+#define PERI_CTRL8_PICOPHY_TXPREEMPAMPTUNE0 (1 << 2)
+#define PERI_CTRL8_PICOPHY_TXRESTUNE0 (1 << 4)
+#define PERI_CTRL8_PICOPHY_TXHSSVTUNE0 (1 << 6)
+#define PERI_CTRL8_PICOPHY_COMPDISTUNE0 (1 << 8)
+#define PERI_CTRL8_PICOPHY_TXPREEMPPULSETUNE0 (1 << 11)
+#define PERI_CTRL8_PICOPHY_OTGTUNE0 (1 << 12)
+#define PERI_CTRL8_PICOPHY_SQRXTUNE0 (1 << 16)
+#define PERI_CTRL8_PICOPHY_TXVREFTUNE0 (1 << 20)
+#define PERI_CTRL8_PICOPHY_TXFSLSTUNE0 (1 << 28)
+
+/* CTRL9 bit definitions */
+
+#define PERI_CTRL9_PICOPLY_TESTCLKEN (1 << 0)
+#define PERI_CTRL9_PICOPLY_TESTDATAOUTSEL (1 << 1)
+#define PERI_CTRL9_PICOPLY_TESTADDR (1 << 4)
+#define PERI_CTRL9_PICOPLY_TESTDATAIN (1 << 8)
+
+/* CLK0 EN/DIS/STAT bit definitions */
+
+#define PERI_CLK0_MMC0 (1 << 0)
+#define PERI_CLK0_MMC1 (1 << 1)
+#define PERI_CLK0_MMC2 (1 << 2)
+#define PERI_CLK0_NANDC (1 << 3)
+#define PERI_CLK0_USBOTG (1 << 4)
+#define PERI_CLK0_PICOPHY (1 << 5)
+#define PERI_CLK0_PLL (1 << 6)
+
+/* CLK1 EN/DIS/STAT bit definitions */
+
+#define PERI_CLK1_HIFI (1 << 0)
+#define PERI_CLK1_DIGACODEC (1 << 5)
+
+/* CLK2 EN/DIS/STAT bit definitions */
+
+#define PERI_CLK2_IPF (1 << 0)
+#define PERI_CLK2_SOCP (1 << 1)
+#define PERI_CLK2_DMAC (1 << 2)
+#define PERI_CLK2_SECENG (1 << 3)
+#define PERI_CLK2_HPM0 (1 << 5)
+#define PERI_CLK2_HPM1 (1 << 6)
+#define PERI_CLK2_HPM2 (1 << 7)
+#define PERI_CLK2_HPM3 (1 << 8)
+
+/* CLK8 EN/DIS/STAT bit definitions */
+
+#define PERI_CLK8_RS0 (1 << 0)
+#define PERI_CLK8_RS2 (1 << 1)
+#define PERI_CLK8_RS3 (1 << 2)
+#define PERI_CLK8_MS0 (1 << 3)
+#define PERI_CLK8_MS2 (1 << 5)
+#define PERI_CLK8_XG2RAM0 (1 << 6)
+#define PERI_CLK8_X2SRAM (1 << 7)
+#define PERI_CLK8_SRAM (1 << 8)
+#define PERI_CLK8_ROM (1 << 9)
+#define PERI_CLK8_HARQ (1 << 10)
+#define PERI_CLK8_MMU (1 << 11)
+#define PERI_CLK8_DDRC (1 << 12)
+#define PERI_CLK8_DDRPHY (1 << 13)
+#define PERI_CLK8_DDRPHY_REF (1 << 14)
+#define PERI_CLK8_X2X_SYSNOC (1 << 15)
+#define PERI_CLK8_X2X_CCPU (1 << 16)
+#define PERI_CLK8_DDRT (1 << 17)
+#define PERI_CLK8_DDRPACK_RS (1 << 18)
+
+/* CLK9 EN/DIS/STAT bit definitions */
+
+#define PERI_CLK9_CARM_DAP (1 << 0)
+#define PERI_CLK9_CARM_ATB (1 << 1)
+#define PERI_CLK9_CARM_LBUS (1 << 2)
+#define PERI_CLK9_CARM_KERNEL (1 << 3)
+
+/* CLK10 EN/DIS/STAT bit definitions */
+
+#define PERI_CLK10_IPF_CCPU (1 << 0)
+#define PERI_CLK10_SOCP_CCPU (1 << 1)
+#define PERI_CLK10_SECENG_CCPU (1 << 2)
+#define PERI_CLK10_HARQ_CCPU (1 << 3)
+#define PERI_CLK10_IPF_MCU (1 << 16)
+#define PERI_CLK10_SOCP_MCU (1 << 17)
+#define PERI_CLK10_SECENG_MCU (1 << 18)
+#define PERI_CLK10_HARQ_MCU (1 << 19)
+
+/* CLK12 EN/DIS/STAT bit definitions */
+
+#define PERI_CLK12_HIFI_SRC (1 << 0)
+#define PERI_CLK12_MMC0_SRC (1 << 1)
+#define PERI_CLK12_MMC1_SRC (1 << 2)
+#define PERI_CLK12_MMC2_SRC (1 << 3)
+#define PERI_CLK12_SYSPLL_DIV (1 << 4)
+#define PERI_CLK12_TPIU_SRC (1 << 5)
+#define PERI_CLK12_MMC0_HF (1 << 6)
+#define PERI_CLK12_MMC1_HF (1 << 7)
+#define PERI_CLK12_PLL_TEST_SRC (1 << 8)
+#define PERI_CLK12_CODEC_SOC (1 << 9)
+#define PERI_CLK12_MEDIA (1 << 10)
+
+/* RST0 EN/DIS/STAT bit definitions */
+
+#define PERI_RST0_MMC0 (1 << 0)
+#define PERI_RST0_MMC1 (1 << 1)
+#define PERI_RST0_MMC2 (1 << 2)
+#define PERI_RST0_NANDC (1 << 3)
+#define PERI_RST0_USBOTG_BUS (1 << 4)
+#define PERI_RST0_POR_PICOPHY (1 << 5)
+#define PERI_RST0_USBOTG (1 << 6)
+#define PERI_RST0_USBOTG_32K (1 << 7)
+
+/* RST1 EN/DIS/STAT bit definitions */
+
+#define PERI_RST1_HIFI (1 << 0)
+#define PERI_RST1_DIGACODEC (1 << 5)
+
+/* RST2 EN/DIS/STAT bit definitions */
+
+#define PERI_RST2_IPF (1 << 0)
+#define PERI_RST2_SOCP (1 << 1)
+#define PERI_RST2_DMAC (1 << 2)
+#define PERI_RST2_SECENG (1 << 3)
+#define PERI_RST2_ABB (1 << 4)
+#define PERI_RST2_HPM0 (1 << 5)
+#define PERI_RST2_HPM1 (1 << 6)
+#define PERI_RST2_HPM2 (1 << 7)
+#define PERI_RST2_HPM3 (1 << 8)
+
+/* RST3 EN/DIS/STAT bit definitions */
+
+#define PERI_RST3_CSSYS (1 << 0)
+#define PERI_RST3_I2C0 (1 << 1)
+#define PERI_RST3_I2C1 (1 << 2)
+#define PERI_RST3_I2C2 (1 << 3)
+#define PERI_RST3_I2C3 (1 << 4)
+#define PERI_RST3_UART1 (1 << 5)
+#define PERI_RST3_UART2 (1 << 6)
+#define PERI_RST3_UART3 (1 << 7)
+#define PERI_RST3_UART4 (1 << 8)
+#define PERI_RST3_SSP (1 << 9)
+#define PERI_RST3_PWM (1 << 10)
+#define PERI_RST3_BLPWM (1 << 11)
+#define PERI_RST3_TSENSOR (1 << 12)
+#define PERI_RST3_DAPB (1 << 18)
+#define PERI_RST3_HKADC (1 << 19)
+#define PERI_RST3_CODEC (1 << 20)
+
+/* RST8 EN/DIS/STAT bit definitions */
+
+#define PERI_RST8_RS0 (1 << 0)
+#define PERI_RST8_RS2 (1 << 1)
+#define PERI_RST8_RS3 (1 << 2)
+#define PERI_RST8_MS0 (1 << 3)
+#define PERI_RST8_MS2 (1 << 5)
+#define PERI_RST8_XG2RAM0 (1 << 6)
+#define PERI_RST8_X2SRAM_TZMA (1 << 7)
+#define PERI_RST8_SRAM (1 << 8)
+#define PERI_RST8_HARQ (1 << 10)
+#define PERI_RST8_DDRC (1 << 12)
+#define PERI_RST8_DDRC_APB (1 << 13)
+#define PERI_RST8_DDRPACK_APB (1 << 14)
+#define PERI_RST8_DDRT (1 << 17)
+
+#endif /*__HI62220_H__*/
diff --git a/arch/arm/include/asm/arch-hi6220/hi6220_regs_alwayson.h b/arch/arm/include/asm/arch-hi6220/hi6220_regs_alwayson.h
new file mode 100644
index 0000000..7d286c0
--- /dev/null
+++ b/arch/arm/include/asm/arch-hi6220/hi6220_regs_alwayson.h
@@ -0,0 +1,420 @@
+/*
+ * (C) Copyright 2015 Linaro
+ * Peter Griffin <peter.griffin@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __HI6220_ALWAYSON_H__
+#define __HI6220_ALWAYSON_H__
+
+#define ALWAYSON_CTRL_BASE 0xF7800000
+
+struct alwayson_sc_regs {
+ u32 ctrl0; /*0x0*/
+ u32 ctrl1;
+ u32 ctrl2;
+
+ u32 unknown;
+
+ u32 stat0; /*0x10*/
+ u32 stat1;
+ u32 mcu_imctrl;
+ u32 mcu_imstat;
+
+ u32 unknown_1[9];
+
+ u32 secondary_int_en0; /*0x44*/
+ u32 secondary_int_statr0;
+ u32 secondary_int_statm0;
+
+ u32 unknown_2;
+
+ u32 mcu_wkup_int_en6; /*0x54*/
+ u32 mcu_wkup_int_statr6;
+ u32 mcu_wkup_int_statm6;
+
+ u32 unknown_3;
+
+ u32 mcu_wkup_int_en5; /*0x64*/
+ u32 mcu_wkup_int_statr5;
+ u32 mcu_wkup_int_statm5;
+
+ u32 unknown_4[9];
+
+ u32 mcu_wkup_int_en4; /*0x94*/
+ u32 mcu_wkup_int_statr4;
+ u32 mcu_wkup_int_statm4;
+
+ u32 unknown_5[2];
+
+ u32 mcu_wkup_int_en0; /*0xa8*/
+ u32 mcu_wkup_int_statr0;
+ u32 mcu_wkup_int_statm0;
+
+ u32 mcu_wkup_int_en1; /*0xb4*/
+ u32 mcu_wkup_int_statr1;
+ u32 mcu_wkup_int_statm1;
+
+ u32 unknown_6;
+
+ u32 int_statr; /*0xc4*/
+ u32 int_statm;
+ u32 int_clear;
+
+ u32 int_en_set; /*0xd0*/
+ u32 int_en_dis;
+ u32 int_en_stat;
+
+ u32 unknown_7[2];
+
+ u32 int_statr1; /*0xc4*/
+ u32 int_statm1;
+ u32 int_clear1;
+
+ u32 int_en_set1; /*0xf0*/
+ u32 int_en_dis1;
+ u32 int_en_stat1;
+
+ u32 unknown_8[53];
+
+ u32 timer_en0; /*0x1d0*/
+ u32 timer_en1;
+
+ u32 unknown_9[6];
+
+ u32 timer_en4; /*0x1f0*/
+ u32 timer_en5;
+
+ u32 unknown_10[130];
+
+ u32 mcu_subsys_ctrl0; /*0x400*/
+ u32 mcu_subsys_ctrl1;
+ u32 mcu_subsys_ctrl2;
+ u32 mcu_subsys_ctrl3;
+ u32 mcu_subsys_ctrl4;
+ u32 mcu_subsys_ctrl5;
+ u32 mcu_subsys_ctrl6;
+ u32 mcu_subsys_ctrl7;
+
+ u32 unknown_10_1[8];
+
+ u32 mcu_subsys_stat0; /*0x440*/
+ u32 mcu_subsys_stat1;
+ u32 mcu_subsys_stat2;
+ u32 mcu_subsys_stat3;
+ u32 mcu_subsys_stat4;
+ u32 mcu_subsys_stat5;
+ u32 mcu_subsys_stat6;
+ u32 mcu_subsys_stat7;
+
+ u32 unknown_11[116];
+
+ u32 clk4_en; /*0x630*/
+ u32 clk4_dis;
+ u32 clk4_stat;
+
+ u32 clk5_en; /*0x63c*/
+ u32 clk5_dis;
+ u32 clk5_stat;
+
+ u32 unknown_12[42];
+
+ u32 rst4_en; /*0x6f0*/
+ u32 rst4_dis;
+ u32 rst4_stat;
+
+ u32 rst5_en; /*0x6fc*/
+ u32 rst5_dis;
+ u32 rst5_stat;
+
+ u32 unknown_13[62];
+
+ u32 pw_clk0_en; /*0x800*/
+ u32 pw_clk0_dis;
+ u32 pw_clk0_stat;
+
+ u32 unknown_13_1;
+
+ u32 pw_rst0_en; /*0x810*/
+ u32 pw_rst0_dis;
+ u32 pw_rst0_stat;
+
+ u32 unknown_14;
+
+ u32 pw_isoen0; /*0x820*/
+ u32 pw_isodis0;
+ u32 pw_iso_stat0;
+
+ u32 unknown_14_1;
+
+ u32 pw_mtcmos_en0; /*0x830*/
+ u32 pw_mtcmos_dis0;
+ u32 pw_mtcmos_stat0;
+ u32 pw_mtcmos_ack_stat0;
+ u32 pw_mtcmos_timeout_stat0;
+
+ u32 unknown_14_2[3];
+
+ u32 pw_stat0; /*0x850*/
+ u32 pw_stat1;
+
+ u32 unknown_15[10];
+
+ u32 systest_stat; /*0x880*/
+
+ u32 unknown_16[3];
+
+ u32 systest_slicer_cnt0;/*0x890*/
+ u32 systest_slicer_cnt1;
+
+ u32 unknown_17[12];
+
+ u32 pw_ctrl1; /*0x8C8*/
+ u32 pw_ctrl;
+
+ u32 mcpu_voteen;
+ u32 mcpu_votedis;
+ u32 mcpu_votestat;
+
+ u32 unknown_17_1;
+
+ u32 mcpu_vote_msk0; /*0x8E0*/
+ u32 mcpu_vote_msk1;
+ u32 mcpu_votestat0_msk;
+ u32 mcpu_votestat1_msk;
+
+ u32 peri_voteen; /*0x8F0*/
+ u32 peri_votedis;
+ u32 peri_votestat;
+
+ u32 unknown_17_2;
+
+ u32 peri_vote_msk0; /*0x900*/
+ u32 peri_vote_msk1;
+ u32 peri_votestat0_msk;
+ u32 erpi_votestat1_msk;
+ u32 acpu_voteen;
+ u32 acpu_votedis;
+ u32 acpu_votestat;
+
+ u32 unknown_18;
+
+ u32 acpu_vote_msk0; /*0x920*/
+ u32 acpu_vote_msk1;
+ u32 acpu_votestat0_msk;
+ u32 acpu_votestat1_msk;
+ u32 mcu_voteen;
+ u32 mcu_votedis;
+ u32 mcu_votestat;
+
+ u32 unknown_18_1;
+
+ u32 mcu_vote_msk0; /*0x940*/
+ u32 mcu_vote_msk1;
+ u32 mcu_vote_votestat0_msk;
+ u32 mcu_vote_votestat1_msk;
+
+ u32 unknown_18_1_2[4];
+
+ u32 mcu_vote_vote1en; /*0x960*/
+ u32 mcu_vote_vote1dis;
+ u32 mcu_vote_vote1stat;
+
+ u32 unknown_18_2;
+
+ u32 mcu_vote_vote1_msk0;/*0x970*/
+ u32 mcu_vote_vote1_msk1;
+ u32 mcu_vote_vote1stat0_msk;
+ u32 mcu_vote_vote1stat1_msk;
+ u32 mcu_vote_vote2en;
+ u32 mcu_vote_vote2dis;
+ u32 mcu_vote_vote2stat;
+
+ u32 unknown_18_3;
+
+ u32 mcu_vote2_msk0; /*0x990*/
+ u32 mcu_vote2_msk1;
+ u32 mcu_vote2stat0_msk;
+ u32 mcu_vote2stat1_msk;
+ u32 vote_ctrl;
+ u32 vote_stat; /*0x9a4*/
+
+ u32 unknown_19[342];
+
+ u32 econum; /*0xf00*/
+
+ u32 unknown_20_1[3];
+
+ u32 scchipid; /*0xf10*/
+
+ u32 unknown_20_2[2];
+
+ u32 scsocid; /*0xf1c*/
+
+ u32 unknown_20[48];
+
+ u32 soc_fpga_rtl_def; /*0xfe0*/
+ u32 soc_fpga_pr_def;
+ u32 soc_fpga_res_def0;
+ u32 soc_fpga_res_def1; /*0xfec*/
+};
+
+/* ctrl0 bit definitions */
+
+#define ALWAYSON_SC_SYS_CTRL0_MODE_NORMAL 0x004
+#define ALWAYSON_SC_SYS_CTRL0_MODE_MASK 0x007
+
+/* ctrl1 bit definitions */
+
+#define ALWAYSON_SC_SYS_CTRL1_AARM_WD_RST_CFG (1 << 0)
+#define ALWAYSON_SC_SYS_CTRL1_REMAP_SRAM_AARM (1 << 1)
+#define ALWAYSON_SC_SYS_CTRL1_EFUSEC_REMAP (1 << 2)
+#define ALWAYSON_SC_SYS_CTRL1_EXT_PLL_SEL (1 << 3)
+#define ALWAYSON_SC_SYS_CTRL1_MCU_WDG0_RSTMCU_CFG (1 << 4)
+#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_DE_BOUNCE_CFG (1 << 6)
+#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_CFG (1 << 7)
+#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_DE_BOUNCE_CFG (1 << 8)
+#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_CFG (1 << 9)
+#define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG (1 << 10)
+#define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG1 (1 << 11)
+#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_SFT (1 << 12)
+#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_SFT (1 << 13)
+#define ALWAYSON_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG (1 << 15)
+#define ALWAYSON_SC_SYS_CTRL1_AARM_WD_RST_CFG_MSK (1 << 16)
+#define ALWAYSON_SC_SYS_CTRL1_REMAP_SRAM_AARM_MSK (1 << 17)
+#define ALWAYSON_SC_SYS_CTRL1_EFUSEC_REMAP_MSK (1 << 18)
+#define ALWAYSON_SC_SYS_CTRL1_EXT_PLL_SEL_MSK (1 << 19)
+#define ALWAYSON_SC_SYS_CTRL1_MCU_WDG0_RSTMCU_CFG_MSK (1 << 20)
+#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_DE_BOUNCE_CFG_MSK (1 << 22)
+#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_CFG_MSK (1 << 23)
+#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_DE_BOUNCE_CFG_MSK (1 << 24)
+#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_CFG_MSK (1 << 25)
+#define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG_MSK (1 << 26)
+#define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG1_MSK (1 << 27)
+#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_SFT_MSK (1 << 28)
+#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_SFT_MSK (1 << 29)
+#define ALWAYSON_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG_MSK (1 << 31)
+
+/* ctrl2 bit definitions */
+
+#define ALWAYSON_SC_SYS_CTRL2_MCU_SFT_RST_STAT_CLEAR (1 << 26)
+#define ALWAYSON_SC_SYS_CTRL2_MCU_WDG0_RST_STAT_CLEAR (1 << 27)
+#define ALWAYSON_SC_SYS_CTRL2_TSENSOR_RST_STAT_CLEAR (1 << 28)
+#define ALWAYSON_SC_SYS_CTRL2_ACPU_WDG_RST_STAT_CLEAR (1 << 29)
+#define ALWAYSON_SC_SYS_CTRL2_MCU_WDG1_RST_STAT_CLEAR (1 << 30)
+#define ALWAYSON_SC_SYS_CTRL2_GLB_SRST_STAT_CLEAR (1 << 31)
+
+/* stat0 bit definitions */
+
+#define ALWAYSON_SC_SYS_STAT0_MCU_RST_STAT (1 << 25)
+#define ALWAYSON_SC_SYS_STAT0_MCU_SOFTRST_STAT (1 << 26)
+#define ALWAYSON_SC_SYS_STAT0_MCU_WDGRST_STAT (1 << 27)
+#define ALWAYSON_SC_SYS_STAT0_TSENSOR_HARDRST_STAT (1 << 28)
+#define ALWAYSON_SC_SYS_STAT0_ACPU_WD_GLB_RST_STAT (1 << 29)
+#define ALWAYSON_SC_SYS_STAT0_CM3_WDG1_RST_STAT (1 << 30)
+#define ALWAYSON_SC_SYS_STAT0_GLB_SRST_STAT (1 << 31)
+
+/* stat1 bit definitions */
+
+#define ALWAYSON_SC_SYS_STAT1_MODE_STATUS (1 << 0)
+#define ALWAYSON_SC_SYS_STAT1_BOOT_SEL_LOCK (1 << 16)
+#define ALWAYSON_SC_SYS_STAT1_FUNC_MODE_LOCK (1 << 17)
+#define ALWAYSON_SC_SYS_STAT1_BOOT_MODE_LOCK (1 << 19)
+#define ALWAYSON_SC_SYS_STAT1_FUN_JTAG_MODE_OUT (1 << 20)
+#define ALWAYSON_SC_SYS_STAT1_SECURITY_BOOT_FLG (1 << 27)
+#define ALWAYSON_SC_SYS_STAT1_EFUSE_NANDBOOT_MSK (1 << 28)
+#define ALWAYSON_SC_SYS_STAT1_EFUSE_NAND_BITWIDE (1 << 29)
+
+/* ctrl3 bit definitions */
+
+#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_3 0x003
+#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_MASK 0x007
+#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_CSSYS_CTRL_PROT (1 << 3)
+#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_TCXO_AFC_OEN_CRG (1 << 4)
+#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_USIM1 (1 << 8)
+#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_USIM0 (1 << 9)
+#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_SD (1 << 10)
+#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_MCU_SUBSYS_CTRL3_RESERVED (1 << 11)
+
+/* clk4_en bit definitions */
+
+#define ALWAYSON_SC_PERIPH_CLK4_EN_HCLK_MCU (1 << 0)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_MCU_DAP (1 << 3)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_TIMER0 (1 << 4)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_TIMER1 (1 << 5)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_WDT0 (1 << 6)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_WDT1 (1 << 7)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_HCLK_IPC_S (1 << 8)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_HCLK_IPC_NS (1 << 9)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_EFUSEC (1 << 10)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TZPC (1 << 11)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_WDT0 (1 << 12)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_WDT1 (1 << 13)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_WDT2 (1 << 14)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER0 (1 << 15)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER1 (1 << 16)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER2 (1 << 17)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER3 (1 << 18)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER4 (1 << 19)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER5 (1 << 20)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER6 (1 << 21)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER7 (1 << 22)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER8 (1 << 23)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_UART0 (1 << 24)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_RTC0 (1 << 25)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_RTC1 (1 << 26)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_PMUSSI (1 << 27)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_JTAG_AUTH (1 << 28)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_CS_DAPB_ON (1 << 29)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_PDM (1 << 30)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_SSI_PAD (1 << 31)
+
+/* clk5_en bit definitions */
+
+#define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_CCPU (1 << 0)
+#define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_EFUSEC_CCPU (1 << 1)
+#define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_CCPU (1 << 2)
+#define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_NS_CCPU (1 << 3)
+#define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_MCU (1 << 16)
+#define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_EFUSEC_MCU (1 << 17)
+#define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_MCU (1 << 18)
+#define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_NS_MCU (1 << 19)
+
+/* rst4_dis bit definitions */
+
+#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_ECTR_N (1 << 0)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_SYS_N (1 << 1)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_POR_N (1 << 2)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_DAP_N (1 << 3)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_TIMER0_N (1 << 4)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_TIMER1_N (1 << 5)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_WDT0_N (1 << 6)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_WDT1_N (1 << 7)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_HRESET_IPC_S_N (1 << 8)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_HRESET_IPC_NS_N (1 << 9)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_EFUSEC_N (1 << 10)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_WDT0_N (1 << 12)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_WDT1_N (1 << 13)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_WDT2_N (1 << 14)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER0_N (1 << 15)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER1_N (1 << 16)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER2_N (1 << 17)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER3_N (1 << 18)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER4_N (1 << 19)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER5_N (1 << 20)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER6_N (1 << 21)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER7_N (1 << 22)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER8_N (1 << 23)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_UART0_N (1 << 24)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_RTC0_N (1 << 25)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_RTC1_N (1 << 26)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N (1 << 27)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_JTAG_AUTH_N (1 << 28)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_CS_DAPB_ON_N (1 << 29)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_MDM_SUBSYS_GLB (1 << 30)
+
+#define PCLK_TIMER1 (1 << 16)
+#define PCLK_TIMER0 (1 << 15)
+
+#endif /* __HI6220_ALWAYSON_H__ */
diff --git a/arch/arm/include/asm/arch-hi6220/periph.h b/arch/arm/include/asm/arch-hi6220/periph.h
new file mode 100644
index 0000000..7155f60
--- /dev/null
+++ b/arch/arm/include/asm/arch-hi6220/periph.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2015 Linaro
+ * Peter Griffin <peter.griffin@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_PERIPH_H
+#define __ASM_ARM_ARCH_PERIPH_H
+
+/*
+ * Peripherals required for pinmux configuration. List will
+ * grow with support for more devices getting added.
+ * Numbering based on interrupt table.
+ *
+ */
+enum periph_id {
+ PERIPH_ID_UART0 = 36,
+ PERIPH_ID_UART1,
+ PERIPH_ID_UART2,
+ PERIPH_ID_UART3,
+ PERIPH_ID_UART4,
+ PERIPH_ID_UART5,
+ PERIPH_ID_SDMMC0 = 72,
+ PERIPH_ID_SDMMC1,
+
+ PERIPH_ID_NONE = -1,
+};
+
+#endif /* __ASM_ARM_ARCH_PERIPH_H */
diff --git a/arch/arm/include/asm/arch-hi6220/pinmux.h b/arch/arm/include/asm/arch-hi6220/pinmux.h
new file mode 100644
index 0000000..1dd5f9b
--- /dev/null
+++ b/arch/arm/include/asm/arch-hi6220/pinmux.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (C) 2015 Linaro
+ * Peter Griffin <peter.griffin@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_PINMUX_H
+#define __ASM_ARM_ARCH_PINMUX_H
+
+#include "periph.h"
+
+
+/* iomg bit definition */
+#define MUX_M0 0
+#define MUX_M1 1
+#define MUX_M2 2
+#define MUX_M3 3
+#define MUX_M4 4
+#define MUX_M5 5
+#define MUX_M6 6
+#define MUX_M7 7
+
+/* iocg bit definition */
+#define PULL_MASK (3)
+#define PULL_DIS (0)
+#define PULL_UP (1 << 0)
+#define PULL_DOWN (1 << 1)
+
+/* drive strength definition */
+#define DRIVE_MASK (7 << 4)
+#define DRIVE1_02MA (0 << 4)
+#define DRIVE1_04MA (1 << 4)
+#define DRIVE1_08MA (2 << 4)
+#define DRIVE1_10MA (3 << 4)
+#define DRIVE2_02MA (0 << 4)
+#define DRIVE2_04MA (1 << 4)
+#define DRIVE2_08MA (2 << 4)
+#define DRIVE2_10MA (3 << 4)
+#define DRIVE3_04MA (0 << 4)
+#define DRIVE3_08MA (1 << 4)
+#define DRIVE3_12MA (2 << 4)
+#define DRIVE3_16MA (3 << 4)
+#define DRIVE3_20MA (4 << 4)
+#define DRIVE3_24MA (5 << 4)
+#define DRIVE3_32MA (6 << 4)
+#define DRIVE3_40MA (7 << 4)
+#define DRIVE4_02MA (0 << 4)
+#define DRIVE4_04MA (2 << 4)
+#define DRIVE4_08MA (4 << 4)
+#define DRIVE4_10MA (6 << 4)
+
+#define HI6220_PINMUX0_BASE 0xf7010000
+#define HI6220_PINMUX1_BASE 0xf7010800
+
+#ifndef __ASSEMBLY__
+
+/* maybe more registers, but highest used is 123 */
+#define REG_NUM 123
+
+struct hi6220_pinmux0_regs {
+ uint32_t iomg[REG_NUM];
+};
+
+struct hi6220_pinmux1_regs {
+ uint32_t iocfg[REG_NUM];
+};
+
+#endif
+
+/**
+ * Configures the pinmux for a particular peripheral.
+ *
+ * This function will configure the peripheral pinmux along with
+ * pull-up/down and drive strength.
+ *
+ * @param peripheral peripheral to be configured
+ * @return 0 if ok, -1 on error (e.g. unsupported peripheral)
+ */
+int hi6220_pinmux_config(int peripheral);
+
+#endif
diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h b/arch/arm/include/asm/arch-lpc32xx/clk.h
index 9449869..010211a 100644
--- a/arch/arm/include/asm/arch-lpc32xx/clk.h
+++ b/arch/arm/include/asm/arch-lpc32xx/clk.h
@@ -153,7 +153,9 @@
#define CLK_DMA_ENABLE (1 << 0)
/* NAND Clock Control Register bits */
+#define CLK_NAND_SLC (1 << 0)
#define CLK_NAND_MLC (1 << 1)
+#define CLK_NAND_SLC_SELECT (1 << 2)
#define CLK_NAND_MLC_INT (1 << 5)
/* SSP Clock Control Register bits */
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
index c3d890d..0845f83 100644
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -12,6 +12,7 @@
void lpc32xx_uart_init(unsigned int uart_id);
void lpc32xx_mac_init(void);
void lpc32xx_mlc_nand_init(void);
+void lpc32xx_slc_nand_init(void);
void lpc32xx_i2c_init(unsigned int devnum);
void lpc32xx_ssp_init(void);
#if defined(CONFIG_SPL_BUILD)
diff --git a/arch/arm/include/asm/arch-ls102xa/gpio.h b/arch/arm/include/asm/arch-ls102xa/gpio.h
index b704436..707a1f3 100644
--- a/arch/arm/include/asm/arch-ls102xa/gpio.h
+++ b/arch/arm/include/asm/arch-ls102xa/gpio.h
@@ -1,4 +1,6 @@
/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
* SPDX-License-Identifier: GPL-2.0+
*/
diff --git a/arch/arm/include/asm/arch-omap3/omap.h b/arch/arm/include/asm/arch-omap3/omap.h
index 537d13b..2c94a81 100644
--- a/arch/arm/include/asm/arch-omap3/omap.h
+++ b/arch/arm/include/asm/arch-omap3/omap.h
@@ -51,6 +51,9 @@
/* Bit definition for CONTROL_PROG_IO1 */
#define PRG_I2C2_PULLUPRESX 0x00000001
+/* Scratchpad memory */
+#define OMAP34XX_SCRATCHPAD (OMAP34XX_CTRL_BASE + 0x910)
+
/* UART */
#define OMAP34XX_UART1 (OMAP34XX_L4_IO_BASE + 0x6a000)
#define OMAP34XX_UART2 (OMAP34XX_L4_IO_BASE + 0x6c000)
@@ -256,6 +259,10 @@
unsigned char ch_flags;
unsigned int boot_device_descriptor;
};
+
+char omap_reboot_mode(void);
+int omap_reboot_mode_clear(void);
+int omap_reboot_mode_store(char c);
#endif
#endif
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h
index 6da8297..7fcb783 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -81,5 +81,6 @@
}
#define OMAP5_SERVICE_L2ACTLR_SET 0x104
+#define OMAP5_SERVICE_ACR_SET 0x107
#endif
diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h
index 5afe791..847da59 100644
--- a/arch/arm/include/asm/mach-types.h
+++ b/arch/arm/include/asm/mach-types.h
@@ -276,6 +276,7 @@
#define MACH_TYPE_TRIZEPS4WL 1649
#define MACH_TYPE_TS78XX 1652
#define MACH_TYPE_SFFSDR 1657
+#define MACH_TYPE_SMARTWEB 1668
#define MACH_TYPE_PCM037 1673
#define MACH_TYPE_DB88F6281_BP 1680
#define MACH_TYPE_RD88F6192_NAS 1681
diff --git a/arch/arm/include/asm/omap_gpio.h b/arch/arm/include/asm/omap_gpio.h
index 839af54..ef38b63 100644
--- a/arch/arm/include/asm/omap_gpio.h
+++ b/arch/arm/include/asm/omap_gpio.h
@@ -23,24 +23,19 @@
#include <asm/arch/cpu.h>
-enum gpio_method {
- METHOD_GPIO_24XX = 4,
-};
-
#ifdef CONFIG_DM_GPIO
/* Information about a GPIO bank */
struct omap_gpio_platdata {
int bank_index;
ulong base; /* address of registers in physical memory */
- enum gpio_method method;
+ const char *port_name;
};
#else
struct gpio_bank {
void *base;
- int method;
};
extern const struct gpio_bank *const omap_gpio_bank;
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index 74cfde6..cd13db3 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -10,29 +10,13 @@
#include <common.h>
#include <malloc.h>
+/*
+ * Flush range from all levels of d-cache/unified-cache.
+ * Affects the range [start, start + size - 1].
+ */
__weak void flush_cache(unsigned long start, unsigned long size)
{
-#if defined(CONFIG_CPU_ARM1136)
-
-#if !defined(CONFIG_SYS_ICACHE_OFF)
- asm("mcr p15, 0, r1, c7, c5, 0"); /* invalidate I cache */
-#endif
-
-#if !defined(CONFIG_SYS_DCACHE_OFF)
- asm("mcr p15, 0, r1, c7, c14, 0"); /* Clean+invalidate D cache */
-#endif
-
-#endif /* CONFIG_CPU_ARM1136 */
-
-#ifdef CONFIG_CPU_ARM926EJS
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
- /* test and clean, page 2-23 of arm926ejs manual */
- asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");
- /* disable write buffer as well (page 2-22) */
- asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
-#endif
-#endif /* CONFIG_CPU_ARM926EJS */
- return;
+ flush_dcache_range(start, start + size);
}
/*
@@ -53,6 +37,15 @@
puts("WARNING: Caches not enabled\n");
}
+__weak void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+ /* An empty stub, real implementation should be in platform code */
+}
+__weak void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+ /* An empty stub, real implementation should be in platform code */
+}
+
#ifdef CONFIG_SYS_NONCACHED_MEMORY
/*
* Reserve one MMU section worth of address space below the malloc() area that
diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c
index 06f4679..ec3fb77 100644
--- a/arch/arm/lib/interrupts.c
+++ b/arch/arm/lib/interrupts.c
@@ -123,8 +123,8 @@
void show_regs (struct pt_regs *regs)
{
- unsigned long flags;
- const char *processor_modes[] = {
+ unsigned long __maybe_unused flags;
+ const char __maybe_unused *processor_modes[] = {
"USER_26", "FIQ_26", "IRQ_26", "SVC_26",
"UK4_26", "UK5_26", "UK6_26", "UK7_26",
"UK8_26", "UK9_26", "UK10_26", "UK11_26",
diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c
index bd8c7d2..d737a5c 100644
--- a/arch/arm/lib/spl.c
+++ b/arch/arm/lib/spl.c
@@ -13,7 +13,7 @@
#include <image.h>
#include <linux/compiler.h>
-#ifndef CONFIG_DM
+#ifndef CONFIG_SPL_DM
/* Pointer to as well as the global data structure for SPL */
DECLARE_GLOBAL_DATA_PTR;
@@ -35,7 +35,7 @@
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
-#ifndef CONFIG_DM
+#ifndef CONFIG_SPL_DM
/* TODO: Remove settings of the global data pointer here */
gd = &gdata;
#endif
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index bbf4228..d8d46dc 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -124,6 +124,11 @@
select CPU_ARM926EJS
select SUPPORT_SPL
+config TARGET_SMARTWEB
+ bool "Support smartweb"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
+
endchoice
config SYS_SOC
@@ -155,6 +160,7 @@
source "board/ronetix/pm9g45/Kconfig"
source "board/siemens/corvus/Kconfig"
source "board/siemens/taurus/Kconfig"
+source "board/siemens/smartweb/Kconfig"
source "board/taskit/stamp9g20/Kconfig"
endif
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 0d3ee48..313eb47 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -1,5 +1,6 @@
obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o
ifneq ($(CONFIG_SPL_BUILD),)
+obj-$(CONFIG_AT91SAM9260) += sdram.o spl_at91.o
obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o
obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o
obj-$(CONFIG_AT91SAM9N12) += mpddrc.o spl_at91.o
diff --git a/arch/arm/mach-at91/arm926ejs/cpu.c b/arch/arm/mach-at91/arm926ejs/cpu.c
index da1d359..990c689 100644
--- a/arch/arm/mach-at91/arm926ejs/cpu.c
+++ b/arch/arm/mach-at91/arm926ejs/cpu.c
@@ -42,7 +42,7 @@
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
- char buf[32];
+ char __maybe_unused buf[32];
printf("CPU: %s\n", ATMEL_CPU_NAME);
printf("Crystal frequency: %8s MHz\n",
diff --git a/arch/arm/mach-at91/spl_at91.c b/arch/arm/mach-at91/spl_at91.c
index a79a9dc..b19f95b 100644
--- a/arch/arm/mach-at91/spl_at91.c
+++ b/arch/arm/mach-at91/spl_at91.c
@@ -123,9 +123,12 @@
at91_periph_clk_enable(ATMEL_ID_PIOB);
at91_periph_clk_enable(ATMEL_ID_PIOC);
#endif
+
+#if defined(CONFIG_SPL_SERIAL_SUPPORT)
/* init console */
at91_seriald_hw_init();
preloader_console_init();
+#endif
mem_init();
diff --git a/arch/arm/mach-bcm283x/include/mach/mbox.h b/arch/arm/mach-bcm283x/include/mach/mbox.h
index 54d369c..ff959c8 100644
--- a/arch/arm/mach-bcm283x/include/mach/mbox.h
+++ b/arch/arm/mach-bcm283x/include/mach/mbox.h
@@ -522,6 +522,9 @@
* a termination value are expected to immediately follow the header in
* memory, as required by the property protocol.
*
+ * Each struct bcm2835_mbox_hdr passed must be allocated with
+ * ALLOC_CACHE_ALIGN_BUFFER(x, y, z) to ensure proper cache flush/invalidate.
+ *
* Returns 0 for success, any other value for error.
*/
int bcm2835_mbox_call_prop(u32 chan, struct bcm2835_mbox_hdr *buffer);
diff --git a/arch/arm/mach-bcm283x/mbox.c b/arch/arm/mach-bcm283x/mbox.c
index 1af9be7..311bd8f 100644
--- a/arch/arm/mach-bcm283x/mbox.c
+++ b/arch/arm/mach-bcm283x/mbox.c
@@ -111,9 +111,18 @@
dump_buf(buffer);
#endif
+ flush_dcache_range((unsigned long)buffer,
+ (unsigned long)((void *)buffer +
+ roundup(buffer->buf_size, ARCH_DMA_MINALIGN)));
+
ret = bcm2835_mbox_call_raw(chan, phys_to_bus((u32)buffer), &rbuffer);
if (ret)
return ret;
+
+ invalidate_dcache_range((unsigned long)buffer,
+ (unsigned long)((void *)buffer +
+ roundup(buffer->buf_size, ARCH_DMA_MINALIGN)));
+
if (rbuffer != phys_to_bus((u32)buffer)) {
printf("mbox: Response buffer mismatch\n");
return -1;
diff --git a/arch/arm/mach-integrator/Kconfig b/arch/arm/mach-integrator/Kconfig
index c54d69d..d506ee5 100644
--- a/arch/arm/mach-integrator/Kconfig
+++ b/arch/arm/mach-integrator/Kconfig
@@ -53,4 +53,7 @@
default "integratorap" if ARCH_INTEGRATOR_AP
default "integratorcp" if ARCH_INTEGRATOR_CP
+config SYS_MALLOC_F_LEN
+ default 0x2000
+
endmenu
diff --git a/arch/arm/mach-keystone/Makefile b/arch/arm/mach-keystone/Makefile
index ed030db..ffd9ead 100644
--- a/arch/arm/mach-keystone/Makefile
+++ b/arch/arm/mach-keystone/Makefile
@@ -8,9 +8,6 @@
obj-y += init.o
obj-y += psc.o
obj-y += clock.o
-obj-$(CONFIG_SOC_K2HK) += clock-k2hk.o
-obj-$(CONFIG_SOC_K2E) += clock-k2e.o
-obj-$(CONFIG_SOC_K2L) += clock-k2l.o
obj-y += cmd_clock.o
obj-y += cmd_mon.o
obj-y += msmc.o
diff --git a/arch/arm/mach-keystone/clock-k2e.c b/arch/arm/mach-keystone/clock-k2e.c
index 31f6661..7d163a4 100644
--- a/arch/arm/mach-keystone/clock-k2e.c
+++ b/arch/arm/mach-keystone/clock-k2e.c
@@ -11,28 +11,6 @@
#include <asm/arch/clock.h>
#include <asm/arch/clock_defs.h>
-const struct keystone_pll_regs keystone_pll_regs[] = {
- [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
- [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
- [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
-};
-
-int dev_speeds[] = {
- SPD800,
- SPD850,
- SPD1000,
- SPD1250,
- SPD1350,
- SPD1400,
- SPD1500,
- SPD1400,
- SPD1350,
- SPD1250,
- SPD1000,
- SPD850,
- SPD800
-};
-
/**
* pll_freq_get - get pll frequency
* Fout = Fref * NF(mult) / NR(prediv) / OD
@@ -65,7 +43,7 @@
reg = KS2_PASSPLLCTL0;
break;
case DDR3_PLL:
- ret = external_clk[ddr3_clk];
+ ret = external_clk[ddr3a_clk];
reg = KS2_DDR3APLLCTL0;
break;
default:
diff --git a/arch/arm/mach-keystone/clock-k2hk.c b/arch/arm/mach-keystone/clock-k2hk.c
index 1591960..2e36891 100644
--- a/arch/arm/mach-keystone/clock-k2hk.c
+++ b/arch/arm/mach-keystone/clock-k2hk.c
@@ -11,46 +11,6 @@
#include <asm/arch/clock.h>
#include <asm/arch/clock_defs.h>
-const struct keystone_pll_regs keystone_pll_regs[] = {
- [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
- [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
- [TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
- [DDR3A_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
- [DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
-};
-
-int dev_speeds[] = {
- SPD800,
- SPD1000,
- SPD1200,
- SPD800,
- SPD800,
- SPD800,
- SPD800,
- SPD800,
- SPD1200,
- SPD1000,
- SPD800,
- SPD800,
- SPD800,
-};
-
-int arm_speeds[] = {
- SPD800,
- SPD1000,
- SPD1200,
- SPD1350,
- SPD1400,
- SPD800,
- SPD1400,
- SPD1350,
- SPD1200,
- SPD1000,
- SPD800,
- SPD800,
- SPD800,
-};
-
/**
* pll_freq_get - get pll frequency
* Fout = Fref * NF(mult) / NR(prediv) / OD
diff --git a/arch/arm/mach-keystone/clock-k2l.c b/arch/arm/mach-keystone/clock-k2l.c
index 1c5e4d5..0004059 100644
--- a/arch/arm/mach-keystone/clock-k2l.c
+++ b/arch/arm/mach-keystone/clock-k2l.c
@@ -11,45 +11,6 @@
#include <asm/arch/clock.h>
#include <asm/arch/clock_defs.h>
-const struct keystone_pll_regs keystone_pll_regs[] = {
- [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
- [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
- [TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
- [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
-};
-
-int dev_speeds[] = {
- SPD800,
- SPD1000,
- SPD1200,
- SPD800,
- SPD800,
- SPD800,
- SPD800,
- SPD800,
- SPD1200,
- SPD1000,
- SPD800,
- SPD800,
- SPD800,
-};
-
-int arm_speeds[] = {
- SPD800,
- SPD1000,
- SPD1200,
- SPD1350,
- SPD1400,
- SPD800,
- SPD1400,
- SPD1350,
- SPD1200,
- SPD1000,
- SPD800,
- SPD800,
- SPD800,
-};
-
/**
* pll_freq_get - get pll frequency
* Fout = Fref * NF(mult) / NR(prediv) / OD
@@ -86,7 +47,7 @@
reg = KS2_ARMPLLCTL0;
break;
case DDR3_PLL:
- ret = external_clk[ddr3_clk];
+ ret = external_clk[ddr3a_clk];
reg = KS2_DDR3APLLCTL0;
break;
default:
diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c
index 625907f..fc3eadb 100644
--- a/arch/arm/mach-keystone/clock.c
+++ b/arch/arm/mach-keystone/clock.c
@@ -11,196 +11,198 @@
#include <asm/arch/clock.h>
#include <asm/arch/clock_defs.h>
-#define MAX_SPEEDS 13
+/* DEV and ARM speed definitions as specified in DEVSPEED register */
+int __weak speeds[DEVSPEED_NUMSPDS] = {
+ SPD1000,
+ SPD1200,
+ SPD1350,
+ SPD1400,
+ SPD1500,
+ SPD1400,
+ SPD1350,
+ SPD1200,
+ SPD1000,
+ SPD800,
+};
+
+const struct keystone_pll_regs keystone_pll_regs[] = {
+ [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
+ [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
+ [TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
+ [DDR3A_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
+ [DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
+};
static void wait_for_completion(const struct pll_init_data *data)
{
int i;
for (i = 0; i < 100; i++) {
sdelay(450);
- if ((pllctl_reg_read(data->pll, stat) & PLLSTAT_GO) == 0)
+ if (!(pllctl_reg_read(data->pll, stat) & PLLSTAT_GOSTAT_MASK))
break;
}
}
-void init_pll(const struct pll_init_data *data)
+static inline void bypass_main_pll(const struct pll_init_data *data)
+{
+ pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC_MASK |
+ PLLCTL_PLLEN_MASK);
+
+ /* 4 cycles of reference clock CLKIN*/
+ sdelay(340);
+}
+
+static void configure_mult_div(const struct pll_init_data *data)
{
- u32 tmp, tmp_ctl, pllm, plld, pllod, bwadj;
+ u32 pllm, plld, bwadj;
pllm = data->pll_m - 1;
- plld = (data->pll_d - 1) & PLL_DIV_MASK;
- pllod = (data->pll_od - 1) & PLL_CLKOD_MASK;
+ plld = (data->pll_d - 1) & CFG_PLLCTL0_PLLD_MASK;
- if (data->pll == MAIN_PLL) {
- /* The requered delay before main PLL configuration */
- sdelay(210000);
+ /* Program Multiplier */
+ if (data->pll == MAIN_PLL)
+ pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK);
- tmp = pllctl_reg_read(data->pll, secctl);
+ clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
+ CFG_PLLCTL0_PLLM_MASK,
+ pllm << CFG_PLLCTL0_PLLM_SHIFT);
- if (tmp & (PLLCTL_BYPASS)) {
- setbits_le32(keystone_pll_regs[data->pll].reg1,
- BIT(MAIN_ENSAT_OFFSET));
+ /* Program BWADJ */
+ bwadj = (data->pll_m - 1) >> 1; /* Divide pllm by 2 */
+ clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
+ CFG_PLLCTL0_BWADJ_MASK,
+ (bwadj << CFG_PLLCTL0_BWADJ_SHIFT) &
+ CFG_PLLCTL0_BWADJ_MASK);
+ bwadj = bwadj >> CFG_PLLCTL0_BWADJ_BITS;
+ clrsetbits_le32(keystone_pll_regs[data->pll].reg1,
+ CFG_PLLCTL1_BWADJ_MASK, bwadj);
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN |
- PLLCTL_PLLENSRC);
- sdelay(340);
+ /* Program Divider */
+ clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
+ CFG_PLLCTL0_PLLD_MASK, plld);
+}
- pllctl_reg_setbits(data->pll, secctl, PLLCTL_BYPASS);
- pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLPWRDN);
- sdelay(21000);
+void configure_main_pll(const struct pll_init_data *data)
+{
+ u32 tmp, pllod, i, alnctl_val = 0;
+ u32 *offset;
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN);
- } else {
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN |
- PLLCTL_PLLENSRC);
- sdelay(340);
- }
+ pllod = data->pll_od - 1;
- pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK);
+ /* 100 micro sec for stabilization */
+ sdelay(210000);
- clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
- PLLM_MULT_HI_SMASK, (pllm << 6));
+ tmp = pllctl_reg_read(data->pll, secctl);
- /* Set the BWADJ (12 bit field) */
- tmp_ctl = pllm >> 1; /* Divide the pllm by 2 */
- clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
- PLL_BWADJ_LO_SMASK,
- (tmp_ctl << PLL_BWADJ_LO_SHIFT));
- clrsetbits_le32(keystone_pll_regs[data->pll].reg1,
- PLL_BWADJ_HI_MASK,
- (tmp_ctl >> 8));
+ /* Check for Bypass */
+ if (tmp & SECCTL_BYPASS_MASK) {
+ setbits_le32(keystone_pll_regs[data->pll].reg1,
+ CFG_PLLCTL1_ENSAT_MASK);
- /*
- * Set the pll divider (6 bit field) *
- * PLLD[5:0] is located in MAINPLLCTL0
- */
- clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
- PLL_DIV_MASK, plld);
+ bypass_main_pll(data);
- /* Set the OUTPUT DIVIDE (4 bit field) in SECCTL */
- pllctl_reg_rmw(data->pll, secctl, PLL_CLKOD_SMASK,
- (pllod << PLL_CLKOD_SHIFT));
- wait_for_completion(data);
+ /* Powerdown and powerup Main Pll */
+ pllctl_reg_setbits(data->pll, secctl, SECCTL_BYPASS_MASK);
+ pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLPWRDN_MASK);
+ /* 5 micro sec */
+ sdelay(21000);
+
+ pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN_MASK);
+ } else {
+ bypass_main_pll(data);
+ }
- pllctl_reg_write(data->pll, div1, PLLM_RATIO_DIV1);
- pllctl_reg_write(data->pll, div2, PLLM_RATIO_DIV2);
- pllctl_reg_write(data->pll, div3, PLLM_RATIO_DIV3);
- pllctl_reg_write(data->pll, div4, PLLM_RATIO_DIV4);
- pllctl_reg_write(data->pll, div5, PLLM_RATIO_DIV5);
+ configure_mult_div(data);
- pllctl_reg_setbits(data->pll, alnctl, 0x1f);
+ /* Program Output Divider */
+ pllctl_reg_rmw(data->pll, secctl, SECCTL_OP_DIV_MASK,
+ ((pllod << SECCTL_OP_DIV_SHIFT) & SECCTL_OP_DIV_MASK));
+ /* Program PLLDIVn */
+ wait_for_completion(data);
+ for (i = 0; i < PLLDIV_MAX; i++) {
+ if (i < 3)
+ offset = pllctl_reg(data->pll, div1) + i;
+ else
+ offset = pllctl_reg(data->pll, div4) + (i - 3);
+
+ if (divn_val[i] != -1) {
+ __raw_writel(divn_val[i] | PLLDIV_ENABLE_MASK, offset);
+ alnctl_val |= BIT(i);
+ }
+ }
+
+ if (alnctl_val) {
+ pllctl_reg_setbits(data->pll, alnctl, alnctl_val);
/*
* Set GOSET bit in PLLCMD to initiate the GO operation
* to change the divide
*/
- pllctl_reg_setbits(data->pll, cmd, PLLSTAT_GO);
- sdelay(1500); /* wait for the phase adj */
+ pllctl_reg_setbits(data->pll, cmd, PLLSTAT_GOSTAT_MASK);
wait_for_completion(data);
+ }
- /* Reset PLL */
- pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST);
- sdelay(21000); /* Wait for a minimum of 7 us*/
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST);
- sdelay(105000); /* Wait for PLL Lock time (min 50 us) */
+ /* Reset PLL */
+ pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST_MASK);
+ sdelay(21000); /* Wait for a minimum of 7 us*/
+ pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST_MASK);
+ sdelay(105000); /* Wait for PLL Lock time (min 50 us) */
- pllctl_reg_clrbits(data->pll, secctl, PLLCTL_BYPASS);
+ /* Enable PLL */
+ pllctl_reg_clrbits(data->pll, secctl, SECCTL_BYPASS_MASK);
+ pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN_MASK);
+}
- tmp = pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
+void configure_secondary_pll(const struct pll_init_data *data)
+{
+ int pllod = data->pll_od - 1;
-#ifndef CONFIG_SOC_K2E
- } else if (data->pll == TETRIS_PLL) {
- bwadj = pllm >> 1;
- /* 1.5 Set PLLCTL0[BYPASS] =1 (enable bypass), */
- setbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
- /*
- * Set CHIPMISCCTL1[13] = 0 (enable glitchfree bypass)
- * only applicable for Kepler
- */
- clrbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
- /* 2 In PLLCTL1, write PLLRST = 1 (PLL is reset) */
- setbits_le32(keystone_pll_regs[data->pll].reg1 ,
- PLL_PLLRST | PLLCTL_ENSAT);
+ /* Enable Bypass mode */
+ setbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_ENSAT_MASK);
+ setbits_le32(keystone_pll_regs[data->pll].reg0,
+ CFG_PLLCTL0_BYPASS_MASK);
- /*
- * 3 Program PLLM and PLLD in PLLCTL0 register
- * 4 Program BWADJ[7:0] in PLLCTL0 and BWADJ[11:8] in
- * PLLCTL1 register. BWADJ value must be set
- * to ((PLLM + 1) >> 1) – 1)
- */
- tmp = ((bwadj & PLL_BWADJ_LO_MASK) << PLL_BWADJ_LO_SHIFT) |
- (pllm << 6) |
- (plld & PLL_DIV_MASK) |
- (pllod << PLL_CLKOD_SHIFT) | PLLCTL_BYPASS;
- __raw_writel(tmp, keystone_pll_regs[data->pll].reg0);
+ /* Enable Glitch free bypass for ARM PLL */
+ if (cpu_is_k2hk() && data->pll == TETRIS_PLL)
+ clrbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN);
- /* Set BWADJ[11:8] bits */
- tmp = __raw_readl(keystone_pll_regs[data->pll].reg1);
- tmp &= ~(PLL_BWADJ_HI_MASK);
- tmp |= ((bwadj>>8) & PLL_BWADJ_HI_MASK);
- __raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
- /*
- * 5 Wait for at least 5 us based on the reference
- * clock (PLL reset time)
- */
- sdelay(21000); /* Wait for a minimum of 7 us*/
+ configure_mult_div(data);
- /* 6 In PLLCTL1, write PLLRST = 0 (PLL reset is released) */
- clrbits_le32(keystone_pll_regs[data->pll].reg1, PLL_PLLRST);
- /*
- * 7 Wait for at least 500 * REFCLK cycles * (PLLD + 1)
- * (PLL lock time)
- */
- sdelay(105000);
- /* 8 disable bypass */
- clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
- /*
- * 9 Set CHIPMISCCTL1[13] = 1 (disable glitchfree bypass)
- * only applicable for Kepler
- */
- setbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
-#endif
- } else {
- setbits_le32(keystone_pll_regs[data->pll].reg1, PLLCTL_ENSAT);
- /*
- * process keeps state of Bypass bit while programming
- * all other DDR PLL settings
- */
- tmp = __raw_readl(keystone_pll_regs[data->pll].reg0);
- tmp &= PLLCTL_BYPASS; /* clear everything except Bypass */
+ /* Program Output Divider */
+ clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
+ CFG_PLLCTL0_CLKOD_MASK,
+ (pllod << CFG_PLLCTL0_CLKOD_SHIFT) &
+ CFG_PLLCTL0_CLKOD_MASK);
- /*
- * Set the BWADJ[7:0], PLLD[5:0] and PLLM to PLLCTL0,
- * bypass disabled
- */
- bwadj = pllm >> 1;
- tmp |= ((bwadj & PLL_BWADJ_LO_MASK) << PLL_BWADJ_LO_SHIFT) |
- (pllm << PLL_MULT_SHIFT) |
- (plld & PLL_DIV_MASK) |
- (pllod << PLL_CLKOD_SHIFT);
- __raw_writel(tmp, keystone_pll_regs[data->pll].reg0);
+ /* Reset PLL */
+ setbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_RST_MASK);
+ /* Wait for 5 micro seconds */
+ sdelay(21000);
- /* Set BWADJ[11:8] bits */
- tmp = __raw_readl(keystone_pll_regs[data->pll].reg1);
- tmp &= ~(PLL_BWADJ_HI_MASK);
- tmp |= ((bwadj >> 8) & PLL_BWADJ_HI_MASK);
+ /* Select the Output of PASS PLL as input to PASS */
+ if (data->pll == PASS_PLL)
+ setbits_le32(keystone_pll_regs[data->pll].reg1,
+ CFG_PLLCTL1_PAPLL_MASK);
- __raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
+ /* Select the Output of ARM PLL as input to ARM */
+ if (data->pll == TETRIS_PLL)
+ setbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN);
- /* Reset bit: bit 14 for both DDR3 & PASS PLL */
- tmp = PLL_PLLRST;
- /* Set RESET bit = 1 */
- setbits_le32(keystone_pll_regs[data->pll].reg1, tmp);
- /* Wait for a minimum of 7 us*/
- sdelay(21000);
- /* Clear RESET bit */
- clrbits_le32(keystone_pll_regs[data->pll].reg1, tmp);
- sdelay(105000);
+ clrbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_RST_MASK);
+ /* Wait for 500 * REFCLK cucles * (PLLD + 1) */
+ sdelay(105000);
- /* clear BYPASS (Enable PLL Mode) */
- clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
- sdelay(21000); /* Wait for a minimum of 7 us*/
- }
+ /* Switch to PLL mode */
+ clrbits_le32(keystone_pll_regs[data->pll].reg0,
+ CFG_PLLCTL0_BYPASS_MASK);
+}
+
+void init_pll(const struct pll_init_data *data)
+{
+ if (data->pll == MAIN_PLL)
+ configure_main_pll(data);
+ else
+ configure_secondary_pll(data);
/*
* This is required to provide a delay between multiple
@@ -209,64 +211,195 @@
sdelay(210000);
}
-void init_plls(int num_pll, struct pll_init_data *config)
+void init_plls(void)
{
- int i;
+ struct pll_init_data *data;
+ int pll;
- for (i = 0; i < num_pll; i++)
- init_pll(&config[i]);
+ for (pll = MAIN_PLL; pll < MAX_PLL_COUNT; pll++) {
+ data = get_pll_init_data(pll);
+ if (data)
+ init_pll(data);
+ }
}
-static int get_max_speed(u32 val, int *speeds)
+static int get_max_speed(u32 val, u32 speed_supported)
{
- int j;
+ int speed;
- if (!val)
- return speeds[0];
-
- for (j = 1; j < MAX_SPEEDS; j++) {
- if (val == 1)
- return speeds[j];
- val >>= 1;
+ /* Left most setbit gives the speed */
+ for (speed = DEVSPEED_NUMSPDS; speed >= 0; speed--) {
+ if ((val & BIT(speed)) & speed_supported)
+ return speeds[speed];
}
+ /* If no bit is set, use SPD800 */
return SPD800;
}
-#ifdef CONFIG_SOC_K2HK
-static u32 read_efuse_bootrom(void)
-{
- return (cpu_revision() > 1) ? __raw_readl(KS2_EFUSE_BOOTROM) :
- __raw_readl(KS2_REV1_DEVSPEED);
-}
-#else
static inline u32 read_efuse_bootrom(void)
{
- return __raw_readl(KS2_EFUSE_BOOTROM);
+ if (cpu_is_k2hk() && (cpu_revision() <= 1))
+ return __raw_readl(KS2_REV1_DEVSPEED);
+ else
+ return __raw_readl(KS2_EFUSE_BOOTROM);
}
-#endif
-#ifndef CONFIG_SOC_K2E
-inline int get_max_arm_speed(void)
+int get_max_arm_speed(void)
{
- return get_max_speed(read_efuse_bootrom() & 0xffff, arm_speeds);
+ u32 armspeed = read_efuse_bootrom();
+
+ armspeed = (armspeed & DEVSPEED_ARMSPEED_MASK) >>
+ DEVSPEED_ARMSPEED_SHIFT;
+
+ return get_max_speed(armspeed, ARM_SUPPORTED_SPEEDS);
}
-#endif
-inline int get_max_dev_speed(void)
+int get_max_dev_speed(void)
{
- return get_max_speed((read_efuse_bootrom() >> 16) & 0xffff, dev_speeds);
+ u32 devspeed = read_efuse_bootrom();
+
+ devspeed = (devspeed & DEVSPEED_DEVSPEED_MASK) >>
+ DEVSPEED_DEVSPEED_SHIFT;
+
+ return get_max_speed(devspeed, DEV_SUPPORTED_SPEEDS);
}
-void pass_pll_pa_clk_enable(void)
+/**
+ * pll_freq_get - get pll frequency
+ * @pll: pll identifier
+ */
+static unsigned long pll_freq_get(int pll)
{
- u32 reg;
+ unsigned long mult = 1, prediv = 1, output_div = 2;
+ unsigned long ret;
+ u32 tmp, reg;
+
+ if (pll == MAIN_PLL) {
+ ret = external_clk[sys_clk];
+ if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN_MASK) {
+ /* PLL mode */
+ tmp = __raw_readl(KS2_MAINPLLCTL0);
+ prediv = (tmp & CFG_PLLCTL0_PLLD_MASK) + 1;
+ mult = ((tmp & CFG_PLLCTL0_PLLM_HI_MASK) >>
+ CFG_PLLCTL0_PLLM_SHIFT |
+ (pllctl_reg_read(pll, mult) &
+ PLLM_MULT_LO_MASK)) + 1;
+ output_div = ((pllctl_reg_read(pll, secctl) &
+ SECCTL_OP_DIV_MASK) >>
+ SECCTL_OP_DIV_SHIFT) + 1;
+
+ ret = ret / prediv / output_div * mult;
+ }
+ } else {
+ switch (pll) {
+ case PASS_PLL:
+ ret = external_clk[pa_clk];
+ reg = KS2_PASSPLLCTL0;
+ break;
+ case TETRIS_PLL:
+ ret = external_clk[tetris_clk];
+ reg = KS2_ARMPLLCTL0;
+ break;
+ case DDR3A_PLL:
+ ret = external_clk[ddr3a_clk];
+ reg = KS2_DDR3APLLCTL0;
+ break;
+ case DDR3B_PLL:
+ ret = external_clk[ddr3b_clk];
+ reg = KS2_DDR3BPLLCTL0;
+ break;
+ default:
+ return 0;
+ }
- reg = readl(keystone_pll_regs[PASS_PLL].reg1);
+ tmp = __raw_readl(reg);
- reg |= PLLCTL_PAPLL;
- writel(reg, keystone_pll_regs[PASS_PLL].reg1);
+ if (!(tmp & CFG_PLLCTL0_BYPASS_MASK)) {
+ /* Bypass disabled */
+ prediv = (tmp & CFG_PLLCTL0_PLLD_MASK) + 1;
+ mult = ((tmp & CFG_PLLCTL0_PLLM_MASK) >>
+ CFG_PLLCTL0_PLLM_SHIFT) + 1;
+ output_div = ((tmp & CFG_PLLCTL0_CLKOD_MASK) >>
+ CFG_PLLCTL0_CLKOD_SHIFT) + 1;
+ ret = ((ret / prediv) * mult) / output_div;
+ }
+ }
+
+ return ret;
+}
+
+unsigned long clk_get_rate(unsigned int clk)
+{
+ unsigned long freq = 0;
+
+ switch (clk) {
+ case core_pll_clk:
+ freq = pll_freq_get(CORE_PLL);
+ break;
+ case pass_pll_clk:
+ freq = pll_freq_get(PASS_PLL);
+ break;
+ case tetris_pll_clk:
+ if (!cpu_is_k2e())
+ freq = pll_freq_get(TETRIS_PLL);
+ break;
+ case ddr3a_pll_clk:
+ freq = pll_freq_get(DDR3A_PLL);
+ break;
+ case ddr3b_pll_clk:
+ if (cpu_is_k2hk())
+ freq = pll_freq_get(DDR3B_PLL);
+ break;
+ case sys_clk0_1_clk:
+ case sys_clk0_clk:
+ freq = pll_freq_get(CORE_PLL) / pll0div_read(1);
+ break;
+ case sys_clk1_clk:
+ return pll_freq_get(CORE_PLL) / pll0div_read(2);
+ break;
+ case sys_clk2_clk:
+ freq = pll_freq_get(CORE_PLL) / pll0div_read(3);
+ break;
+ case sys_clk3_clk:
+ freq = pll_freq_get(CORE_PLL) / pll0div_read(4);
+ break;
+ case sys_clk0_2_clk:
+ freq = clk_get_rate(sys_clk0_clk) / 2;
+ break;
+ case sys_clk0_3_clk:
+ freq = clk_get_rate(sys_clk0_clk) / 3;
+ break;
+ case sys_clk0_4_clk:
+ freq = clk_get_rate(sys_clk0_clk) / 4;
+ break;
+ case sys_clk0_6_clk:
+ freq = clk_get_rate(sys_clk0_clk) / 6;
+ break;
+ case sys_clk0_8_clk:
+ freq = clk_get_rate(sys_clk0_clk) / 8;
+ break;
+ case sys_clk0_12_clk:
+ freq = clk_get_rate(sys_clk0_clk) / 12;
+ break;
+ case sys_clk0_24_clk:
+ freq = clk_get_rate(sys_clk0_clk) / 24;
+ break;
+ case sys_clk1_3_clk:
+ freq = clk_get_rate(sys_clk1_clk) / 3;
+ break;
+ case sys_clk1_4_clk:
+ freq = clk_get_rate(sys_clk1_clk) / 4;
+ break;
+ case sys_clk1_6_clk:
+ freq = clk_get_rate(sys_clk1_clk) / 6;
+ break;
+ case sys_clk1_12_clk:
+ freq = clk_get_rate(sys_clk1_clk) / 12;
+ break;
+ default:
+ break;
+ }
- /* wait till clock is enabled */
- sdelay(15000);
+ return freq;
}
diff --git a/arch/arm/mach-keystone/cmd_clock.c b/arch/arm/mach-keystone/cmd_clock.c
index af1b701..3d5cf3f 100644
--- a/arch/arm/mach-keystone/cmd_clock.c
+++ b/arch/arm/mach-keystone/cmd_clock.c
@@ -67,7 +67,7 @@
int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
unsigned int clk;
- unsigned int freq;
+ unsigned long freq;
if (argc != 2)
goto getclk_cmd_usage;
@@ -75,7 +75,10 @@
clk = simple_strtoul(argv[1], NULL, 10);
freq = clk_get_rate(clk);
- printf("clock index [%d] - frequency %u\n", clk, freq);
+ if (freq)
+ printf("clock index [%d] - frequency %lu\n", clk, freq);
+ else
+ printf("clock index [%d] Not available\n", clk);
return 0;
getclk_cmd_usage:
diff --git a/arch/arm/mach-keystone/include/mach/clock-k2e.h b/arch/arm/mach-keystone/include/mach/clock-k2e.h
index d013b83..4618560 100644
--- a/arch/arm/mach-keystone/include/mach/clock-k2e.h
+++ b/arch/arm/mach-keystone/include/mach/clock-k2e.h
@@ -10,64 +10,10 @@
#ifndef __ASM_ARCH_CLOCK_K2E_H
#define __ASM_ARCH_CLOCK_K2E_H
-enum ext_clk_e {
- sys_clk,
- alt_core_clk,
- pa_clk,
- ddr3_clk,
- mcm_clk,
- pcie_clk,
- sgmii_clk,
- xgmii_clk,
- usb_clk,
- ext_clk_count /* number of external clocks */
-};
-
-extern unsigned int external_clk[ext_clk_count];
-
-#define CLK_LIST(CLK)\
- CLK(0, core_pll_clk)\
- CLK(1, pass_pll_clk)\
- CLK(2, ddr3_pll_clk)\
- CLK(3, sys_clk0_clk)\
- CLK(4, sys_clk0_1_clk)\
- CLK(5, sys_clk0_2_clk)\
- CLK(6, sys_clk0_3_clk)\
- CLK(7, sys_clk0_4_clk)\
- CLK(8, sys_clk0_6_clk)\
- CLK(9, sys_clk0_8_clk)\
- CLK(10, sys_clk0_12_clk)\
- CLK(11, sys_clk0_24_clk)\
- CLK(12, sys_clk1_clk)\
- CLK(13, sys_clk1_3_clk)\
- CLK(14, sys_clk1_4_clk)\
- CLK(15, sys_clk1_6_clk)\
- CLK(16, sys_clk1_12_clk)\
- CLK(17, sys_clk2_clk)\
- CLK(18, sys_clk3_clk)
-
#define PLLSET_CMD_LIST "<pa|ddr3>"
#define KS2_CLK1_6 sys_clk0_6_clk
-/* PLL identifiers */
-enum pll_type_e {
- CORE_PLL,
- PASS_PLL,
- DDR3_PLL,
-};
-
-enum {
- SPD800,
- SPD850,
- SPD1000,
- SPD1250,
- SPD1350,
- SPD1400,
- SPD1500,
- SPD_RSV
-};
-
#define CORE_PLL_800 {CORE_PLL, 16, 1, 2}
#define CORE_PLL_850 {CORE_PLL, 17, 1, 2}
#define CORE_PLL_1000 {CORE_PLL, 20, 1, 2}
@@ -82,4 +28,8 @@
#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2}
#define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6}
+/* k2e DEV supports 800, 850, 1000, 1250, 1350, 1400, 1500 MHz */
+#define DEV_SUPPORTED_SPEEDS 0xFFF
+#define ARM_SUPPORTED_SPEEDS 0
+
#endif
diff --git a/arch/arm/mach-keystone/include/mach/clock-k2hk.h b/arch/arm/mach-keystone/include/mach/clock-k2hk.h
index f28d5f0..b8f3e76 100644
--- a/arch/arm/mach-keystone/include/mach/clock-k2hk.h
+++ b/arch/arm/mach-keystone/include/mach/clock-k2hk.h
@@ -10,69 +10,10 @@
#ifndef __ASM_ARCH_CLOCK_K2HK_H
#define __ASM_ARCH_CLOCK_K2HK_H
-enum ext_clk_e {
- sys_clk,
- alt_core_clk,
- pa_clk,
- tetris_clk,
- ddr3a_clk,
- ddr3b_clk,
- mcm_clk,
- pcie_clk,
- sgmii_srio_clk,
- xgmii_clk,
- usb_clk,
- rp1_clk,
- ext_clk_count /* number of external clocks */
-};
-
-extern unsigned int external_clk[ext_clk_count];
-
-#define CLK_LIST(CLK)\
- CLK(0, core_pll_clk)\
- CLK(1, pass_pll_clk)\
- CLK(2, tetris_pll_clk)\
- CLK(3, ddr3a_pll_clk)\
- CLK(4, ddr3b_pll_clk)\
- CLK(5, sys_clk0_clk)\
- CLK(6, sys_clk0_1_clk)\
- CLK(7, sys_clk0_2_clk)\
- CLK(8, sys_clk0_3_clk)\
- CLK(9, sys_clk0_4_clk)\
- CLK(10, sys_clk0_6_clk)\
- CLK(11, sys_clk0_8_clk)\
- CLK(12, sys_clk0_12_clk)\
- CLK(13, sys_clk0_24_clk)\
- CLK(14, sys_clk1_clk)\
- CLK(15, sys_clk1_3_clk)\
- CLK(16, sys_clk1_4_clk)\
- CLK(17, sys_clk1_6_clk)\
- CLK(18, sys_clk1_12_clk)\
- CLK(19, sys_clk2_clk)\
- CLK(20, sys_clk3_clk)
-
#define PLLSET_CMD_LIST "<pa|arm|ddr3a|ddr3b>"
#define KS2_CLK1_6 sys_clk0_6_clk
-/* PLL identifiers */
-enum pll_type_e {
- CORE_PLL,
- PASS_PLL,
- TETRIS_PLL,
- DDR3A_PLL,
- DDR3B_PLL,
-};
-
-enum {
- SPD800,
- SPD1000,
- SPD1200,
- SPD1350,
- SPD1400,
- SPD_RSV
-};
-
#define CORE_PLL_799 {CORE_PLL, 13, 1, 2}
#define CORE_PLL_983 {CORE_PLL, 16, 1, 2}
#define CORE_PLL_999 {CORE_PLL, 122, 15, 1}
@@ -100,4 +41,9 @@
#define DDR3_PLL_800(x) {DDR3##x##_PLL, 16, 1, 2}
#define DDR3_PLL_333(x) {DDR3##x##_PLL, 20, 1, 6}
+/* k2h DEV supports 800, 1000, 1200 MHz */
+#define DEV_SUPPORTED_SPEEDS 0x383
+/* k2h ARM supportd 800, 1000, 1200, 1350, 1400 MHz */
+#define ARM_SUPPORTED_SPEEDS 0x3EF
+
#endif
diff --git a/arch/arm/mach-keystone/include/mach/clock-k2l.h b/arch/arm/mach-keystone/include/mach/clock-k2l.h
index bb9a5c4..8772a7d 100644
--- a/arch/arm/mach-keystone/include/mach/clock-k2l.h
+++ b/arch/arm/mach-keystone/include/mach/clock-k2l.h
@@ -10,64 +10,10 @@
#ifndef __ASM_ARCH_CLOCK_K2L_H
#define __ASM_ARCH_CLOCK_K2L_H
-enum ext_clk_e {
- sys_clk,
- alt_core_clk,
- pa_clk,
- tetris_clk,
- ddr3_clk,
- pcie_clk,
- sgmii_clk,
- usb_clk,
- rp1_clk,
- ext_clk_count /* number of external clocks */
-};
-
-extern unsigned int external_clk[ext_clk_count];
-
-#define CLK_LIST(CLK)\
- CLK(0, core_pll_clk)\
- CLK(1, pass_pll_clk)\
- CLK(2, tetris_pll_clk)\
- CLK(3, ddr3_pll_clk)\
- CLK(4, sys_clk0_clk)\
- CLK(5, sys_clk0_1_clk)\
- CLK(6, sys_clk0_2_clk)\
- CLK(7, sys_clk0_3_clk)\
- CLK(8, sys_clk0_4_clk)\
- CLK(9, sys_clk0_6_clk)\
- CLK(10, sys_clk0_8_clk)\
- CLK(11, sys_clk0_12_clk)\
- CLK(12, sys_clk0_24_clk)\
- CLK(13, sys_clk1_clk)\
- CLK(14, sys_clk1_3_clk)\
- CLK(15, sys_clk1_4_clk)\
- CLK(16, sys_clk1_6_clk)\
- CLK(17, sys_clk1_12_clk)\
- CLK(18, sys_clk2_clk)\
- CLK(19, sys_clk3_clk)\
-
#define PLLSET_CMD_LIST "<pa|arm|ddr3>"
#define KS2_CLK1_6 sys_clk0_6_clk
-/* PLL identifiers */
-enum pll_type_e {
- CORE_PLL,
- PASS_PLL,
- TETRIS_PLL,
- DDR3_PLL,
-};
-
-enum {
- SPD800,
- SPD1000,
- SPD1200,
- SPD1350,
- SPD1400,
- SPD_RSV
-};
-
#define CORE_PLL_799 {CORE_PLL, 13, 1, 2}
#define CORE_PLL_983 {CORE_PLL, 16, 1, 2}
#define CORE_PLL_1000 {CORE_PLL, 114, 7, 2}
@@ -92,4 +38,9 @@
#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2}
#define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6}
+/* k2l DEV supports 800, 1000, 1200 MHz */
+#define DEV_SUPPORTED_SPEEDS 0x383
+/* k2l ARM supportd 800, 1000, 1200, MHz */
+#define ARM_SUPPORTED_SPEEDS 0x383
+
#endif
diff --git a/arch/arm/mach-keystone/include/mach/clock.h b/arch/arm/mach-keystone/include/mach/clock.h
index 9f6cfb2..ddc5f8e 100644
--- a/arch/arm/mach-keystone/include/mach/clock.h
+++ b/arch/arm/mach-keystone/include/mach/clock.h
@@ -24,7 +24,31 @@
#include <asm/arch/clock-k2l.h>
#endif
-#define MAIN_PLL CORE_PLL
+#define CORE_PLL MAIN_PLL
+#define DDR3_PLL DDR3A_PLL
+
+#define CLK_LIST(CLK)\
+ CLK(0, core_pll_clk)\
+ CLK(1, pass_pll_clk)\
+ CLK(2, tetris_pll_clk)\
+ CLK(3, ddr3a_pll_clk)\
+ CLK(4, ddr3b_pll_clk)\
+ CLK(5, sys_clk0_clk)\
+ CLK(6, sys_clk0_1_clk)\
+ CLK(7, sys_clk0_2_clk)\
+ CLK(8, sys_clk0_3_clk)\
+ CLK(9, sys_clk0_4_clk)\
+ CLK(10, sys_clk0_6_clk)\
+ CLK(11, sys_clk0_8_clk)\
+ CLK(12, sys_clk0_12_clk)\
+ CLK(13, sys_clk0_24_clk)\
+ CLK(14, sys_clk1_clk)\
+ CLK(15, sys_clk1_3_clk)\
+ CLK(16, sys_clk1_4_clk)\
+ CLK(17, sys_clk1_6_clk)\
+ CLK(18, sys_clk1_12_clk)\
+ CLK(19, sys_clk2_clk)\
+ CLK(20, sys_clk3_clk)
#include <asm/types.h>
@@ -32,6 +56,38 @@
#define GENERATE_INDX_STR(NUM, STRING) #NUM"\t- "#STRING"\n"
#define CLOCK_INDEXES_LIST CLK_LIST(GENERATE_INDX_STR)
+enum {
+ SPD800,
+ SPD850,
+ SPD1000,
+ SPD1200,
+ SPD1250,
+ SPD1350,
+ SPD1400,
+ SPD1500,
+ NUM_SPDS,
+};
+
+/* PLL identifiers */
+enum {
+ MAIN_PLL,
+ TETRIS_PLL,
+ PASS_PLL,
+ DDR3A_PLL,
+ DDR3B_PLL,
+ MAX_PLL_COUNT,
+};
+
+enum ext_clk_e {
+ sys_clk,
+ alt_core_clk,
+ pa_clk,
+ tetris_clk,
+ ddr3a_clk,
+ ddr3b_clk,
+ ext_clk_count /* number of external clocks */
+};
+
enum clk_e {
CLK_LIST(GENERATE_ENUM)
};
@@ -49,16 +105,17 @@
int pll_od; /* PLL output divider */
};
+extern unsigned int external_clk[ext_clk_count];
extern const struct keystone_pll_regs keystone_pll_regs[];
-extern int dev_speeds[];
-extern int arm_speeds[];
+extern s16 divn_val[];
+extern int speeds[];
-void init_plls(int num_pll, struct pll_init_data *config);
+void init_plls(void);
void init_pll(const struct pll_init_data *data);
+struct pll_init_data *get_pll_init_data(int pll);
unsigned long clk_get_rate(unsigned int clk);
unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
int clk_set_rate(unsigned int clk, unsigned long hz);
-void pass_pll_pa_clk_enable(void);
int get_max_dev_speed(void);
int get_max_arm_speed(void);
diff --git a/arch/arm/mach-keystone/include/mach/clock_defs.h b/arch/arm/mach-keystone/include/mach/clock_defs.h
index 85a046b..8ad371f 100644
--- a/arch/arm/mach-keystone/include/mach/clock_defs.h
+++ b/arch/arm/mach-keystone/include/mach/clock_defs.h
@@ -70,42 +70,66 @@
#define pll0div_read(N) ((pllctl_reg_read(CORE_PLL, div##N) & 0xff) + 1)
/* PLLCTL Bits */
-#define PLLCTL_BYPASS BIT(23)
-#define PLL_PLLRST BIT(14)
-#define PLLCTL_PAPLL BIT(13)
-#define PLLCTL_CLKMODE BIT(8)
-#define PLLCTL_PLLSELB BIT(7)
-#define PLLCTL_ENSAT BIT(6)
-#define PLLCTL_PLLENSRC BIT(5)
-#define PLLCTL_PLLDIS BIT(4)
-#define PLLCTL_PLLRST BIT(3)
-#define PLLCTL_PLLPWRDN BIT(1)
-#define PLLCTL_PLLEN BIT(0)
-#define PLLSTAT_GO BIT(0)
+#define PLLCTL_PLLENSRC_SHIF 5
+#define PLLCTL_PLLENSRC_MASK BIT(5)
+#define PLLCTL_PLLRST_SHIFT 3
+#define PLLCTL_PLLRST_MASK BIT(3)
+#define PLLCTL_PLLPWRDN_SHIFT 1
+#define PLLCTL_PLLPWRDN_MASK BIT(1)
+#define PLLCTL_PLLEN_SHIFT 0
+#define PLLCTL_PLLEN_MASK BIT(0)
-#define MAIN_ENSAT_OFFSET 6
+/* SECCTL Bits */
+#define SECCTL_BYPASS_SHIFT 23
+#define SECCTL_BYPASS_MASK BIT(23)
+#define SECCTL_OP_DIV_SHIFT 19
+#define SECCTL_OP_DIV_MASK (0xf << 19)
-#define PLLDIV_ENABLE BIT(15)
+/* PLLM Bits */
+#define PLLM_MULT_LO_SHIFT 0
+#define PLLM_MULT_LO_MASK 0x3f
+#define PLLM_MULT_LO_BITS 6
-#define PLL_DIV_MASK 0x3f
-#define PLL_MULT_MASK 0x1fff
-#define PLL_MULT_SHIFT 6
-#define PLLM_MULT_HI_MASK 0x7f
-#define PLLM_MULT_HI_SHIFT 12
-#define PLLM_MULT_HI_SMASK (PLLM_MULT_HI_MASK << PLLM_MULT_HI_SHIFT)
-#define PLLM_MULT_LO_MASK 0x3f
-#define PLL_CLKOD_MASK 0xf
-#define PLL_CLKOD_SHIFT 19
-#define PLL_CLKOD_SMASK (PLL_CLKOD_MASK << PLL_CLKOD_SHIFT)
-#define PLL_BWADJ_LO_MASK 0xff
-#define PLL_BWADJ_LO_SHIFT 24
-#define PLL_BWADJ_LO_SMASK (PLL_BWADJ_LO_MASK << PLL_BWADJ_LO_SHIFT)
-#define PLL_BWADJ_HI_MASK 0xf
+/* PLLDIVn Bits */
+#define PLLDIV_ENABLE_SHIFT 15
+#define PLLDIV_ENABLE_MASK BIT(15)
+#define PLLDIV_RATIO_SHIFT 0x0
+#define PLLDIV_RATIO_MASK 0xff
+#define PLLDIV_MAX 16
+
+/* PLLCMD Bits */
+#define PLLCMD_GOSET_SHIFT 0
+#define PLLCMD_GOSET_MASK BIT(0)
+
+/* PLLSTAT Bits */
+#define PLLSTAT_GOSTAT_SHIFT 0
+#define PLLSTAT_GOSTAT_MASK BIT(0)
+
+/* Device Config PLLCTL0 */
+#define CFG_PLLCTL0_BWADJ_SHIFT 24
+#define CFG_PLLCTL0_BWADJ_MASK (0xff << 24)
+#define CFG_PLLCTL0_BWADJ_BITS 8
+#define CFG_PLLCTL0_BYPASS_SHIFT 23
+#define CFG_PLLCTL0_BYPASS_MASK BIT(23)
+#define CFG_PLLCTL0_CLKOD_SHIFT 19
+#define CFG_PLLCTL0_CLKOD_MASK (0xf << 19)
+#define CFG_PLLCTL0_PLLM_HI_SHIFT 12
+#define CFG_PLLCTL0_PLLM_HI_MASK (0x7f << 12)
+#define CFG_PLLCTL0_PLLM_SHIFT 6
+#define CFG_PLLCTL0_PLLM_MASK (0x1fff << 6)
+#define CFG_PLLCTL0_PLLD_SHIFT 0
+#define CFG_PLLCTL0_PLLD_MASK 0x3f
+
+/* Device Config PLLCTL1 */
+#define CFG_PLLCTL1_RST_SHIFT 14
+#define CFG_PLLCTL1_RST_MASK BIT(14)
+#define CFG_PLLCTL1_PAPLL_SHIFT 13
+#define CFG_PLLCTL1_PAPLL_MASK BIT(13)
+#define CFG_PLLCTL1_ENSAT_SHIFT 6
+#define CFG_PLLCTL1_ENSAT_MASK BIT(6)
+#define CFG_PLLCTL1_BWADJ_SHIFT 0
+#define CFG_PLLCTL1_BWADJ_MASK 0xf
-#define PLLM_RATIO_DIV1 (PLLDIV_ENABLE | 0x0)
-#define PLLM_RATIO_DIV2 (PLLDIV_ENABLE | 0x0)
-#define PLLM_RATIO_DIV3 (PLLDIV_ENABLE | 0x1)
-#define PLLM_RATIO_DIV4 (PLLDIV_ENABLE | 0x4)
-#define PLLM_RATIO_DIV5 (PLLDIV_ENABLE | 0x17)
+#define MISC_CTL1_ARM_PLL_EN BIT(13)
#endif /* _CLOCK_DEFS_H_ */
diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2hk.h b/arch/arm/mach-keystone/include/mach/hardware-k2hk.h
index 195c0d3..8c771dc 100644
--- a/arch/arm/mach-keystone/include/mach/hardware-k2hk.h
+++ b/arch/arm/mach-keystone/include/mach/hardware-k2hk.h
@@ -15,10 +15,6 @@
/* PA SS Registers */
#define KS2_PASS_BASE 0x02000000
-/* PLL control registers */
-#define KS2_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
-#define KS2_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
-
/* Power and Sleep Controller (PSC) Domains */
#define KS2_LPSC_MOD 0
#define KS2_LPSC_DUMMY1 1
diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h
index 16cbcee..53f28ec 100644
--- a/arch/arm/mach-keystone/include/mach/hardware.h
+++ b/arch/arm/mach-keystone/include/mach/hardware.h
@@ -165,6 +165,8 @@
#define KS2_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
#define KS2_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360)
#define KS2_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364)
+#define KS2_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
+#define KS2_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
#define KS2_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
#define KS2_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374)
@@ -237,6 +239,24 @@
/* SGMII SerDes */
#define KS2_SGMII_SERDES_BASE 0x0232a000
+/* JTAG ID register */
+#define JTAGID_VARIANT_SHIFT 28
+#define JTAGID_VARIANT_MASK (0xf << 28)
+#define JTAGID_PART_NUM_SHIFT 12
+#define JTAGID_PART_NUM_MASK (0xffff << 12)
+
+/* PART NUMBER definitions */
+#define CPU_66AK2Hx 0xb981
+#define CPU_66AK2Ex 0xb9a6
+#define CPU_66AK2Lx 0xb9a7
+
+/* DEVSPEED register */
+#define DEVSPEED_DEVSPEED_SHIFT 16
+#define DEVSPEED_DEVSPEED_MASK (0xfff << 16)
+#define DEVSPEED_ARMSPEED_SHIFT 0
+#define DEVSPEED_ARMSPEED_MASK 0xfff
+#define DEVSPEED_NUMSPDS 12
+
#ifdef CONFIG_SOC_K2HK
#include <asm/arch/hardware-k2hk.h>
#endif
@@ -250,34 +270,33 @@
#endif
#ifndef __ASSEMBLY__
-static inline int cpu_is_k2hk(void)
+
+static inline u16 get_part_number(void)
{
- unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG);
- unsigned int part_no = (jtag_id >> 12) & 0xffff;
+ u32 jtag_id = __raw_readl(KS2_JTAG_ID_REG);
- return (part_no == 0xb981) ? 1 : 0;
+ return (jtag_id & JTAGID_PART_NUM_MASK) >> JTAGID_PART_NUM_SHIFT;
}
-static inline int cpu_is_k2e(void)
+static inline u8 cpu_is_k2hk(void)
{
- unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG);
- unsigned int part_no = (jtag_id >> 12) & 0xffff;
-
- return (part_no == 0xb9a6) ? 1 : 0;
+ return get_part_number() == CPU_66AK2Hx;
}
-static inline int cpu_is_k2l(void)
+static inline u8 cpu_is_k2e(void)
{
- unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG);
- unsigned int part_no = (jtag_id >> 12) & 0xffff;
+ return get_part_number() == CPU_66AK2Ex;
+}
- return (part_no == 0xb9a7) ? 1 : 0;
+static inline u8 cpu_is_k2l(void)
+{
+ return get_part_number() == CPU_66AK2Lx;
}
-static inline int cpu_revision(void)
+static inline u8 cpu_revision(void)
{
- unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG);
- unsigned int rev = (jtag_id >> 28) & 0xf;
+ u32 jtag_id = __raw_readl(KS2_JTAG_ID_REG);
+ u8 rev = (jtag_id & JTAGID_VARIANT_MASK) >> JTAGID_VARIANT_SHIFT;
return rev;
}
diff --git a/arch/arm/mach-keystone/init.c b/arch/arm/mach-keystone/init.c
index c96845c..a9a7d41 100644
--- a/arch/arm/mach-keystone/init.c
+++ b/arch/arm/mach-keystone/init.c
@@ -149,3 +149,35 @@
dcache_enable();
#endif
}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+ u16 cpu = get_part_number();
+ u8 rev = cpu_revision();
+
+ puts("CPU: ");
+ switch (cpu) {
+ case CPU_66AK2Hx:
+ puts("66AK2Hx SR");
+ break;
+ case CPU_66AK2Lx:
+ puts("66AK2Lx SR");
+ break;
+ case CPU_66AK2Ex:
+ puts("66AK2Ex SR");
+ break;
+ default:
+ puts("Unknown\n");
+ }
+
+ if (rev == 2)
+ puts("2.0\n");
+ else if (rev == 1)
+ puts("1.1\n");
+ else if (rev == 0)
+ puts("1.0\n");
+
+ return 0;
+}
+#endif
diff --git a/arch/m68k/lib/cache.c b/arch/m68k/lib/cache.c
index 21daf3d..ace791b 100644
--- a/arch/m68k/lib/cache.c
+++ b/arch/m68k/lib/cache.c
@@ -132,3 +132,12 @@
__asm__ __volatile__("movec %0, %%cacr"::"r"(temp));
#endif
}
+
+__weak void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+ /* An empty stub, real implementation should be in platform code */
+}
+__weak void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+ /* An empty stub, real implementation should be in platform code */
+}
diff --git a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
index 71794a8..da7352a 100644
--- a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
+++ b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
@@ -1,4 +1,6 @@
/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
* SPDX-License-Identifier: GPL-2.0+
*/
diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c
index e94ac85..cbe7061 100644
--- a/board/armltd/integrator/integrator.c
+++ b/board/armltd/integrator/integrator.c
@@ -20,11 +20,29 @@
#include <common.h>
#include <netdev.h>
#include <asm/io.h>
+#include <dm/platdata.h>
+#include <dm/platform_data/serial_pl01x.h>
#include "arm-ebi.h"
#include "integrator-sc.h"
DECLARE_GLOBAL_DATA_PTR;
+static const struct pl01x_serial_platdata serial_platdata = {
+ .base = 0x16000000,
+#ifdef CONFIG_ARCH_CINTEGRATOR
+ .type = TYPE_PL011,
+ .clock = 14745600,
+#else
+ .type = TYPE_PL010,
+ .clock = 0, /* Not used for PL010 */
+#endif
+};
+
+U_BOOT_DEVICE(integrator_serials) = {
+ .name = "serial_pl01x",
+ .platdata = &serial_platdata,
+};
+
void peripheral_power_enable (void);
#if defined(CONFIG_SHOW_BOOT_PROGRESS)
diff --git a/board/broadcom/bcm_ep/board.c b/board/broadcom/bcm_ep/board.c
index eaad0b3..c28b203 100644
--- a/board/broadcom/bcm_ep/board.c
+++ b/board/broadcom/bcm_ep/board.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <asm/io.h>
#include <config.h>
+#include <netdev.h>
#include <asm/system.h>
#include <asm/iproc-common/armpll.h>
@@ -67,3 +68,13 @@
{
}
#endif
+
+#ifdef CONFIG_BCM_SF2_ETH
+int board_eth_init(bd_t *bis)
+{
+ int rc = -1;
+ printf("Registering BCM sf2 eth\n");
+ rc = bcm_sf2_eth_register(bis, 0);
+ return rc;
+}
+#endif
diff --git a/board/compulab/cm_t43/Kconfig b/board/compulab/cm_t43/Kconfig
new file mode 100644
index 0000000..a191889
--- /dev/null
+++ b/board/compulab/cm_t43/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_CM_T43
+
+config SYS_BOARD
+ default "cm_t43"
+
+config SYS_VENDOR
+ default "compulab"
+
+config SYS_SOC
+ default "am33xx"
+
+config SYS_CONFIG_NAME
+ default "cm_t43"
+
+endif
diff --git a/board/compulab/cm_t43/MAINTAINERS b/board/compulab/cm_t43/MAINTAINERS
new file mode 100644
index 0000000..951c370
--- /dev/null
+++ b/board/compulab/cm_t43/MAINTAINERS
@@ -0,0 +1,6 @@
+CM_T43 BOARD
+M: Nikita Kiryanov <nikita@compulab.co.il>
+S: Maintained
+F: board/compulab/cm_t43/
+F: include/configs/cm_t43.h
+F: configs/cm_t43_defconfig
diff --git a/board/compulab/cm_t43/Makefile b/board/compulab/cm_t43/Makefile
new file mode 100644
index 0000000..3993689
--- /dev/null
+++ b/board/compulab/cm_t43/Makefile
@@ -0,0 +1,9 @@
+#
+# Makefile
+#
+# Copyright (C) 2015 Compulab, Ltd.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += board.o mux.o
diff --git a/board/compulab/cm_t43/board.c b/board/compulab/cm_t43/board.c
new file mode 100644
index 0000000..4272c45
--- /dev/null
+++ b/board/compulab/cm_t43/board.c
@@ -0,0 +1,272 @@
+/*
+ * Copyright (C) 2015 Compulab, Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <spl.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/emif.h>
+#include <power/pmic.h>
+#include <power/tps65218.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+
+const struct dpll_params dpll_mpu = { 800, 24, 1, -1, -1, -1, -1 };
+const struct dpll_params dpll_core = { 1000, 24, -1, -1, 10, 8, 4 };
+const struct dpll_params dpll_per = { 960, 24, 5, -1, -1, -1, -1 };
+const struct dpll_params dpll_ddr = { 400, 23, 1, -1, 1, -1, -1 };
+
+const struct ctrl_ioregs ioregs_ddr3 = {
+ .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
+ .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
+ .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
+ .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,
+ .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
+ .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
+ .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
+ .emif_sdram_config_ext = 0x0143,
+};
+
+/* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
+struct emif_regs ddr3_emif_regs = {
+ .sdram_config = 0x638413B2,
+ .ref_ctrl = 0x00000C30,
+ .sdram_tim1 = 0xEAAAD4DB,
+ .sdram_tim2 = 0x266B7FDA,
+ .sdram_tim3 = 0x107F8678,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x50074BE4,
+ .temp_alert_config = 0x0,
+ .emif_ddr_phy_ctlr_1 = 0x0E004008,
+ .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00000066,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
+ .emif_ddr_ext_phy_ctrl_4 = 0x000000B9,
+ .emif_ddr_ext_phy_ctrl_5 = 0x000000E6,
+ .emif_rd_wr_exec_thresh = 0x80000405,
+ .emif_prio_class_serv_map = 0x80000001,
+ .emif_connect_id_serv_1_map = 0x80000094,
+ .emif_connect_id_serv_2_map = 0x00000000,
+ .emif_cos_config = 0x000FFFFF
+};
+
+const u32 ext_phy_ctrl_const_base_ddr3[] = {
+ 0x00000000,
+ 0x00000044,
+ 0x00000044,
+ 0x00000046,
+ 0x00000046,
+ 0x00000000,
+ 0x00000059,
+ 0x00000077,
+ 0x00000093,
+ 0x000000A8,
+ 0x00000000,
+ 0x00000019,
+ 0x00000037,
+ 0x00000053,
+ 0x00000068,
+ 0x00000000,
+ 0x0,
+ 0x0,
+ 0x40000000,
+ 0x08102040
+};
+
+void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
+{
+ *regs = ext_phy_ctrl_const_base_ddr3;
+ *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+ return &dpll_ddr;
+}
+
+const struct dpll_params *get_dpll_mpu_params(void)
+{
+ return &dpll_mpu;
+}
+
+const struct dpll_params *get_dpll_core_params(void)
+{
+ return &dpll_core;
+}
+
+const struct dpll_params *get_dpll_per_params(void)
+{
+ return &dpll_per;
+}
+
+static void enable_vtt_regulator(void)
+{
+ u32 temp;
+
+ writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
+ writel(GPIO_SETDATAOUT(7), AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
+ temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
+ temp = temp & ~(GPIO_OE_ENABLE(7));
+ writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
+}
+
+void sdram_init(void)
+{
+ unsigned long ram_size;
+
+ enable_vtt_regulator();
+ config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0);
+ ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ if (ram_size == 0x80000000 ||
+ ram_size == 0x40000000 ||
+ ram_size == 0x20000000)
+ return;
+
+ ddr3_emif_regs.sdram_config = 0x638453B2;
+ config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0);
+ ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ if (ram_size == 0x08000000)
+ return;
+
+ hang();
+}
+#endif
+
+/* setup board specific PMIC */
+int power_init_board(void)
+{
+ struct pmic *p;
+
+ power_tps65218_init(I2C_PMIC);
+ p = pmic_get("TPS65218_PMIC");
+ if (p && !pmic_probe(p))
+ puts("PMIC: TPS65218\n");
+
+ return 0;
+}
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gpmc_init();
+ set_i2c_pin_mux();
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+ i2c_probe(TPS65218_CHIP_PM);
+
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+
+static void cpsw_control(int enabled)
+{
+ return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_addr = 0,
+ .phy_if = PHY_INTERFACE_MODE_RGMII,
+ },
+ {
+ .slave_reg_ofs = 0x308,
+ .sliver_reg_ofs = 0xdc0,
+ .phy_addr = 1,
+ .phy_if = PHY_INTERFACE_MODE_RGMII,
+ },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 2,
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .bd_ram_ofs = 0x2000,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+
+#define GPIO_PHY1_RST 170
+#define GPIO_PHY2_RST 168
+
+int board_phy_config(struct phy_device *phydev)
+{
+ unsigned short val;
+
+ /* introduce tx clock delay */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+ val |= 0x0100;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+ if (phydev->drv->config)
+ return phydev->drv->config(phydev);
+
+ return 0;
+}
+
+static void board_phy_init(void)
+{
+ set_mdio_pin_mux();
+ writel(0x40003, 0x44e10a74); /* Mux pin as clkout2 */
+ writel(0x10006, 0x44df4108); /* Select EXTDEV as clock source */
+ writel(0x4, 0x44df2e60); /* Set EXTDEV as MNbypass */
+
+ /* For revision A */
+ writel(0x2000009, 0x44df2e6c);
+ writel(0x38a, 0x44df2e70);
+
+ mdelay(10);
+
+ gpio_request(GPIO_PHY1_RST, "phy1_rst");
+ gpio_request(GPIO_PHY2_RST, "phy2_rst");
+ gpio_direction_output(GPIO_PHY1_RST, 0);
+ gpio_direction_output(GPIO_PHY2_RST, 0);
+ mdelay(2);
+
+ gpio_set_value(GPIO_PHY1_RST, 1);
+ gpio_set_value(GPIO_PHY2_RST, 1);
+ mdelay(2);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rv;
+
+ set_rgmii_pin_mux();
+ writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel);
+ board_phy_init();
+
+ rv = cpsw_register(&cpsw_data);
+ if (rv < 0)
+ printf("Error %d registering CPSW switch\n", rv);
+
+ return rv;
+}
+#endif
diff --git a/board/compulab/cm_t43/board.h b/board/compulab/cm_t43/board.h
new file mode 100644
index 0000000..b585db0
--- /dev/null
+++ b/board/compulab/cm_t43/board.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2015 Compulab, Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+void set_i2c_pin_mux(void);
+void set_mdio_pin_mux(void);
+void set_rgmii_pin_mux(void);
+#endif
diff --git a/board/compulab/cm_t43/mux.c b/board/compulab/cm_t43/mux.c
new file mode 100644
index 0000000..d4bf4b2
--- /dev/null
+++ b/board/compulab/cm_t43/mux.c
@@ -0,0 +1,143 @@
+/*
+ * Copyright (C) 2015 Compulab, Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mux.h>
+#include "board.h"
+
+static struct module_pin_mux rgmii1_pin_mux[] = {
+ {OFFSET(mii1_txen), MODE(2)},
+ {OFFSET(mii1_txd3), MODE(2)},
+ {OFFSET(mii1_txd2), MODE(2)},
+ {OFFSET(mii1_txd1), MODE(2)},
+ {OFFSET(mii1_txd0), MODE(2)},
+ {OFFSET(mii1_txclk), MODE(2)},
+ {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE | PULLDOWN_EN},
+ {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE | PULLDOWN_EN},
+ {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE | PULLDOWN_EN},
+ {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE | PULLDOWN_EN},
+ {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE | PULLDOWN_EN},
+ {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE | PULLDOWN_EN},
+ {-1},
+};
+
+static struct module_pin_mux rgmii2_pin_mux[] = {
+ {OFFSET(gpmc_a0), MODE(2)}, /* txen */
+ {OFFSET(gpmc_a2), MODE(2)}, /* txd3 */
+ {OFFSET(gpmc_a3), MODE(2)}, /* txd2 */
+ {OFFSET(gpmc_a4), MODE(2)}, /* txd1 */
+ {OFFSET(gpmc_a5), MODE(2)}, /* txd0 */
+ {OFFSET(gpmc_a6), MODE(2)}, /* txclk */
+ {OFFSET(gpmc_a1), MODE(2) | RXACTIVE | PULLDOWN_EN}, /* rxvd */
+ {OFFSET(gpmc_a7), MODE(2) | RXACTIVE | PULLDOWN_EN}, /* rxclk */
+ {OFFSET(gpmc_a8), MODE(2) | RXACTIVE | PULLDOWN_EN}, /* rxd3 */
+ {OFFSET(gpmc_a9), MODE(2) | RXACTIVE | PULLDOWN_EN}, /* rxd2 */
+ {OFFSET(gpmc_a10), MODE(2) | RXACTIVE | PULLDOWN_EN}, /* rxd1 */
+ {OFFSET(gpmc_a11), MODE(2) | RXACTIVE | PULLUP_EN}, /* rxd0 */
+ {-1},
+};
+
+static struct module_pin_mux mdio_pin_mux[] = {
+ {OFFSET(mdio_data), (MODE(0) | PULLUP_EN | RXACTIVE)},
+ {OFFSET(mdio_clk), (MODE(0) | PULLUP_EN)},
+ {-1},
+};
+
+static struct module_pin_mux uart0_pin_mux[] = {
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)},
+ {-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+ {OFFSET(mmc0_clk), (MODE(0) | PULLUDDIS | RXACTIVE)},
+ {OFFSET(mmc0_cmd), (MODE(0) | PULLUP_EN | RXACTIVE)},
+ {OFFSET(mmc0_dat0), (MODE(0) | PULLUP_EN | RXACTIVE)},
+ {OFFSET(mmc0_dat1), (MODE(0) | PULLUP_EN | RXACTIVE)},
+ {OFFSET(mmc0_dat2), (MODE(0) | PULLUP_EN | RXACTIVE)},
+ {OFFSET(mmc0_dat3), (MODE(0) | PULLUP_EN | RXACTIVE)},
+ {-1},
+};
+
+static struct module_pin_mux i2c_pin_mux[] = {
+ {OFFSET(i2c0_sda), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+ {OFFSET(i2c0_scl), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+ {OFFSET(spi2_sclk), (MODE(1) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+ {OFFSET(spi2_cs0), (MODE(1) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+ {-1},
+};
+
+static struct module_pin_mux nand_pin_mux[] = {
+ {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)},
+ {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)},
+ {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)},
+ {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)},
+ {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)},
+ {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)},
+ {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)},
+ {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)},
+ {OFFSET(gpmc_wait0), (MODE(0) | PULLUP_EN | RXACTIVE)},
+ {OFFSET(gpmc_wpn), (MODE(0) | PULLUP_EN)},
+ {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)},
+ {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)},
+ {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)},
+ {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)},
+ {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)},
+ {-1},
+};
+
+static struct module_pin_mux emmc_pin_mux[] = {
+ {OFFSET(gpmc_csn1), (MODE(2) | PULLUDDIS | RXACTIVE)}, /* EMMC_CLK */
+ {OFFSET(gpmc_csn2), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_CMD */
+ {OFFSET(gpmc_ad8), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT0 */
+ {OFFSET(gpmc_ad9), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT1 */
+ {OFFSET(gpmc_ad10), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT2 */
+ {OFFSET(gpmc_ad11), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT3 */
+ {OFFSET(gpmc_ad12), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT4 */
+ {OFFSET(gpmc_ad13), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT5 */
+ {OFFSET(gpmc_ad14), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT6 */
+ {OFFSET(gpmc_ad15), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT7 */
+ {-1},
+};
+
+static struct module_pin_mux spi_flash_pin_mux[] = {
+ {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | PULLUDEN)},
+ {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)},
+ {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDEN)},
+ {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)},
+ {-1},
+};
+
+void set_uart_mux_conf(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
+
+void set_mdio_pin_mux(void)
+{
+ configure_module_pin_mux(mdio_pin_mux);
+}
+
+void set_rgmii_pin_mux(void)
+{
+ configure_module_pin_mux(rgmii1_pin_mux);
+ configure_module_pin_mux(rgmii2_pin_mux);
+}
+
+void set_mux_conf_regs(void)
+{
+ configure_module_pin_mux(mmc0_pin_mux);
+ configure_module_pin_mux(emmc_pin_mux);
+ configure_module_pin_mux(i2c_pin_mux);
+ configure_module_pin_mux(spi_flash_pin_mux);
+ configure_module_pin_mux(nand_pin_mux);
+}
+
+void set_i2c_pin_mux(void)
+{
+ configure_module_pin_mux(i2c_pin_mux);
+}
diff --git a/board/freescale/common/pfuze.c b/board/freescale/common/pfuze.c
index d6a209e..783c46d 100644
--- a/board/freescale/common/pfuze.c
+++ b/board/freescale/common/pfuze.c
@@ -9,6 +9,7 @@
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
+#ifndef CONFIG_DM_PMIC_PFUZE100
int pfuze_mode_init(struct pmic *p, u32 mode)
{
unsigned char offset, i, switch_num;
@@ -90,3 +91,4 @@
return p;
}
+#endif
diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c
index 469ee8e..55999ed 100644
--- a/board/highbank/highbank.c
+++ b/board/highbank/highbank.c
@@ -96,12 +96,6 @@
return 0;
}
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-}
-
#if defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *fdt, bd_t *bd)
{
diff --git a/board/hisilicon/hikey/Kconfig b/board/hisilicon/hikey/Kconfig
new file mode 100644
index 0000000..f7f1055
--- /dev/null
+++ b/board/hisilicon/hikey/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_HIKEY
+
+config SYS_BOARD
+ default "hikey"
+
+config SYS_VENDOR
+ default "hisilicon"
+
+config SYS_SOC
+ default "hi6220"
+
+config SYS_CONFIG_NAME
+ default "hikey"
+
+endif
diff --git a/board/hisilicon/hikey/Makefile b/board/hisilicon/hikey/Makefile
new file mode 100644
index 0000000..d4ec8c7
--- /dev/null
+++ b/board/hisilicon/hikey/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := hikey.o
diff --git a/board/hisilicon/hikey/README b/board/hisilicon/hikey/README
new file mode 100644
index 0000000..25c8143
--- /dev/null
+++ b/board/hisilicon/hikey/README
@@ -0,0 +1,160 @@
+Introduction
+============
+
+HiKey is the first certified 96Boards Consumer Edition board. The board/SoC has: -
+* HiSilicon Kirin 6220 eight-core ARM Cortex-A53 64-bit SoC running at 1.2GHz.
+* ARM Mali 450-MP4 GPU
+* 1GB 800MHz LPDDR3 DRAM
+* 4GB eMMC Flash Storage
+* microSD
+* 802.11a/b/g/n WiFi, Bluetooth
+
+The HiKey schematic can be found here: -
+https://github.com/96boards/documentation/blob/master/hikey/96Boards-Hikey-Rev-A1.pdf
+
+A SoC datasheet can be found here: -
+https://github.com/96boards/documentation/blob/master/hikey/
+Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf
+
+Currently the u-boot port supports: -
+* USB
+* eMMC
+* SD card
+* GPIO
+
+Compile u-boot
+==============
+
+make CROSS_COMPILE=aarch64-linux-gnu- hikey_config
+make CROSS_COMPILE=aarch64-linux-gnu-
+
+ARM Trusted Firmware (ATF) & l-loader
+=====================================
+
+This u-boot port has been tested with l-loader, booting ATF, which then boots
+u-boot as the bl33.bin executable.
+
+1. Get ATF source code
+git clone https://github.com/96boards/arm-trusted-firmware.git
+
+2. Compile ATF I use the makefile here
+http://people.linaro.org/~peter.griffin/hikey/hikey-u-boot-release_r1/build-tf.mak
+
+3. Get l-loader
+git clone https://github.com/96boards/l-loader.git
+
+4. Make sym links to ATF bip / fip binaries
+ln -s /home/griffinp/aarch64/bl1-hikey.bin bl1.bin
+ln -s /home/griffinp/aarch64/fip-hikey.bin fip.bin
+
+arm-linux-gnueabihf-gcc -c -o start.o start.S
+arm-linux-gnueabihf-gcc -c -o debug.o debug.S
+arm-linux-gnueabihf-ld -Bstatic -Tl-loader.lds -Ttext 0xf9800800 start.o debug.o -o loader
+arm-linux-gnueabihf-objcopy -O binary loader temp
+
+python gen_loader.py -o l-loader.bin --img_loader=temp --img_bl1=bl1.bin
+sudo bash -x generate_ptable.sh
+python gen_loader.py -o ptable.img --img_prm_ptable=prm_ptable.img --img_sec_ptable=sec_ptable.img
+
+These instructions are adapted from
+https://github.com/96boards/documentation/wiki/HiKeyUEFI
+
+FLASHING
+========
+
+1. Connect jumper J2 to go into recovery mode and flash l-loader.bin with
+ fastboot using the hisi-idt.py utility
+
+> git clone https://github.com/96boards/burn-boot.git
+> sudo python /home/griffinp/Software/hikey/burn-boot/hisi-idt.py -d /dev/ttyUSB0 --img1=/tmp/l-loader.bin
+
+2. Once LED 0 comes on solid, it should be detected as a fastboot device
+ (on some boards I've found this to be unreliable)
+
+sudo fastboot devices
+
+3. Flash the images
+wget https://builds.96boards.org/releases/hikey/nvme.img
+sudo fastboot flash ptable ptable.img
+sudo fastboot flash fastboot fip.bin
+sudo fastboot flash nvme nvme.img
+
+4. Disconnect jumper J2, and reset the board and you will now (hopefully)
+ have ATF, booting u-boot from eMMC. On 'new' boards I've had to do the
+ flashing twice in the past to avoid an ATF error.
+
+See working boot trace below: -
+
+debug EMMC boot: print init OK
+debug EMMC boot: send RST_N .
+debug EMMC boot: start eMMC boot......
+load fastboot1!
+Switch to aarch64 mode. CPU0 executes at 0xf9801000!
+NOTICE: Booting Trusted Firmware
+NOTICE: BL1: v1.1(release):a0c0399
+NOTICE: BL1: Built : 13:23:48, May 22 2015
+NOTICE: succeed to init lpddr3 rank0 dram phy
+INFO: lpddr3_freq_init, set ddrc 533mhz
+INFO: init ddr3 rank0
+INFO: ddr3 rank1 init pass
+INFO: lpddr3_freq_init, set ddrc 800mhz
+INFO: init ddr3 rank0
+INFO: ddr3 rank1 init pass
+INFO: Elpida DDR
+NOTICE: BL1: Booting BL2
+INFO: [BDID] [fff91c18] midr: 0x410fd033
+INFO: [BDID] [fff91c1c] board type: 0
+INFO: [BDID] [fff91c20] board id: 0x2b
+INFO: init_acpu_dvfs: pmic version 17
+INFO: init_acpu_dvfs: ACPU_CHIP_MAX_FREQ=0x186a00.
+INFO: acpu_dvfs_volt_init: success!
+INFO: acpu_dvfs_set_freq: support freq num is 5
+INFO: acpu_dvfs_set_freq: start prof is 0x4
+INFO: acpu_dvfs_set_freq: magic is 0x5a5ac5c5
+INFO: acpu_dvfs_set_freq: voltage:
+INFO: - 0: 0x3a
+INFO: - 1: 0x3a
+INFO: - 2: 0x4a
+INFO: - 3: 0x5b
+INFO: - 4: 0x6b
+NOTICE: acpu_dvfs_set_freq: set acpu freq success!NOTICE: BL2: v1.1(debug):a0c0399
+NOTICE: BL2: Built : 10:19:28, May 27 2015
+INFO: BL2: Loading BL3-0
+INFO: Using FIP
+WARNING: Failed to access image 'bl30.bin' (-1)
+ERROR: Failed to load BL3-0 (-1)
+ERROR: Please burn mcu image:
+ERROR: sudo fastboot flash mcuimage mcuimage.bin
+INFO: BL2: TrustZone: protecting 16777216 bytes of memory at 0x3f000000
+INFO: BL2: Loading BL3-1
+INFO: Using FIP
+INFO: Loading file 'bl31.bin' at address 0xf9858000
+INFO: File 'bl31.bin' loaded: 0xf9858000 - 0xf9860010
+INFO: BL2: Loading BL3-2
+INFO: Using FIP
+WARNING: Failed to access image 'bl32.bin' (-1)
+WARNING: Failed to load BL3-2 (-1)
+INFO: BL2: Loading BL3-3
+INFO: Using FIP
+INFO: Loading file 'bl33.bin' at address 0x35000000
+INFO: File 'bl33.bin' loaded: 0x35000000 - 0x35042938
+NOTICE: BL1: Booting BL3-1
+NOTICE: BL3-1: v1.1(debug):a0c0399
+NOTICE: BL3-1: Built : 10:19:31, May 27 2015
+INFO: BL3-1: Initializing runtime services
+INFO: BL3-1: Preparing for EL3 exit to normal world
+INFO: BL3-1: Next image address = 0x35000000
+INFO: BL3-1: Next image spsr = 0x3c9
+
+
+U-Boot 2015.04-00007-g1b3d379-dirty (May 27 2015 - 10:18:16) hikey
+
+DRAM: 1008 MiB
+MMC: sd_card_detect: SD card present
+HiKey DWMMC: 0, HiKey DWMMC: 1
+In: serial
+Out: serial
+Err: serial
+Net: Net Initialization Skipped
+No ethernet found.
+Hit any key to stop autoboot: 0
diff --git a/board/hisilicon/hikey/hikey.c b/board/hisilicon/hikey/hikey.c
new file mode 100644
index 0000000..8c1271b
--- /dev/null
+++ b/board/hisilicon/hikey/hikey.c
@@ -0,0 +1,356 @@
+/*
+ * (C) Copyright 2015 Linaro
+ * Peter Griffin <peter.griffin@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <usb.h>
+#include <power/hi6553_pmic.h>
+#include <asm-generic/gpio.h>
+#include <asm/arch/dwmmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/hi6220.h>
+
+/*TODO drop this table in favour of device tree */
+static const struct hikey_gpio_platdata hi6220_gpio[] = {
+ { 0, HI6220_GPIO_BASE(0)},
+ { 1, HI6220_GPIO_BASE(1)},
+ { 2, HI6220_GPIO_BASE(2)},
+ { 3, HI6220_GPIO_BASE(3)},
+ { 4, HI6220_GPIO_BASE(4)},
+ { 5, HI6220_GPIO_BASE(5)},
+ { 6, HI6220_GPIO_BASE(6)},
+ { 7, HI6220_GPIO_BASE(7)},
+ { 8, HI6220_GPIO_BASE(8)},
+ { 9, HI6220_GPIO_BASE(9)},
+ { 10, HI6220_GPIO_BASE(10)},
+ { 11, HI6220_GPIO_BASE(11)},
+ { 12, HI6220_GPIO_BASE(12)},
+ { 13, HI6220_GPIO_BASE(13)},
+ { 14, HI6220_GPIO_BASE(14)},
+ { 15, HI6220_GPIO_BASE(15)},
+ { 16, HI6220_GPIO_BASE(16)},
+ { 17, HI6220_GPIO_BASE(17)},
+ { 18, HI6220_GPIO_BASE(18)},
+ { 19, HI6220_GPIO_BASE(19)},
+
+};
+
+U_BOOT_DEVICES(hi6220_gpios) = {
+ { "gpio_hi6220", &hi6220_gpio[0] },
+ { "gpio_hi6220", &hi6220_gpio[1] },
+ { "gpio_hi6220", &hi6220_gpio[2] },
+ { "gpio_hi6220", &hi6220_gpio[3] },
+ { "gpio_hi6220", &hi6220_gpio[4] },
+ { "gpio_hi6220", &hi6220_gpio[5] },
+ { "gpio_hi6220", &hi6220_gpio[6] },
+ { "gpio_hi6220", &hi6220_gpio[7] },
+ { "gpio_hi6220", &hi6220_gpio[8] },
+ { "gpio_hi6220", &hi6220_gpio[9] },
+ { "gpio_hi6220", &hi6220_gpio[10] },
+ { "gpio_hi6220", &hi6220_gpio[11] },
+ { "gpio_hi6220", &hi6220_gpio[12] },
+ { "gpio_hi6220", &hi6220_gpio[13] },
+ { "gpio_hi6220", &hi6220_gpio[14] },
+ { "gpio_hi6220", &hi6220_gpio[15] },
+ { "gpio_hi6220", &hi6220_gpio[16] },
+ { "gpio_hi6220", &hi6220_gpio[17] },
+ { "gpio_hi6220", &hi6220_gpio[18] },
+ { "gpio_hi6220", &hi6220_gpio[19] },
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct peri_sc_periph_regs *peri_sc =
+ (struct peri_sc_periph_regs *)HI6220_PERI_BASE;
+
+struct alwayson_sc_regs *ao_sc =
+ (struct alwayson_sc_regs *)ALWAYSON_CTRL_BASE;
+
+/* status offset from enable reg */
+#define STAT_EN_OFF 0x2
+
+void hi6220_clk_enable(u32 bitfield, unsigned int *clk_base)
+{
+ uint32_t data;
+
+ data = readl(clk_base);
+ data |= bitfield;
+
+ writel(bitfield, clk_base);
+ do {
+ data = readl(clk_base + STAT_EN_OFF);
+ } while ((data & bitfield) == 0);
+}
+
+/* status offset from disable reg */
+#define STAT_DIS_OFF 0x1
+
+void hi6220_clk_disable(u32 bitfield, unsigned int *clk_base)
+{
+ uint32_t data;
+
+ data = readl(clk_base);
+ data |= bitfield;
+
+ writel(data, clk_base);
+ do {
+ data = readl(clk_base + STAT_DIS_OFF);
+ } while (data & bitfield);
+}
+
+#define EYE_PATTERN 0x70533483
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ unsigned int data;
+
+ /* enable USB clock */
+ hi6220_clk_enable(PERI_CLK0_USBOTG, &peri_sc->clk0_en);
+
+ /* take usb IPs out of reset */
+ writel(PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY |
+ PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K,
+ &peri_sc->rst0_dis);
+ do {
+ data = readl(&peri_sc->rst0_stat);
+ data &= PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY |
+ PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K;
+ } while (data);
+
+ /*CTRL 5*/
+ data = readl(&peri_sc->ctrl5);
+ data &= ~PERI_CTRL5_PICOPHY_BC_MODE;
+ data |= PERI_CTRL5_USBOTG_RES_SEL | PERI_CTRL5_PICOPHY_ACAENB;
+ data |= 0x300;
+ writel(data, &peri_sc->ctrl5);
+
+ /*CTRL 4*/
+
+ /* configure USB PHY */
+ data = readl(&peri_sc->ctrl4);
+
+ /* make PHY out of low power mode */
+ data &= ~PERI_CTRL4_PICO_SIDDQ;
+ data &= ~PERI_CTRL4_PICO_OGDISABLE;
+ data |= PERI_CTRL4_PICO_VBUSVLDEXTSEL | PERI_CTRL4_PICO_VBUSVLDEXT;
+ writel(data, &peri_sc->ctrl4);
+
+ writel(EYE_PATTERN, &peri_sc->ctrl8);
+
+ mdelay(5);
+ return 0;
+}
+
+static int config_sd_carddetect(void)
+{
+ int ret;
+
+ /* configure GPIO8 as nopull */
+ writel(0, 0xf8001830);
+
+ gpio_request(8, "SD CD");
+
+ gpio_direction_input(8);
+ ret = gpio_get_value(8);
+
+ if (!ret) {
+ printf("%s: SD card present\n", __func__);
+ return 1;
+ }
+
+ printf("%s: SD card not present\n", __func__);
+ return 0;
+}
+
+
+static void mmc1_init_pll(void)
+{
+ uint32_t data;
+
+ /* select SYSPLL as the source of MMC1 */
+ /* select SYSPLL as the source of MUX1 (SC_CLK_SEL0) */
+ writel(1 << 11 | 1 << 27, &peri_sc->clk0_sel);
+ do {
+ data = readl(&peri_sc->clk0_sel);
+ } while (!(data & (1 << 11)));
+
+ /* select MUX1 as the source of MUX2 (SC_CLK_SEL0) */
+ writel(1 << 30, &peri_sc->clk0_sel);
+ do {
+ data = readl(&peri_sc->clk0_sel);
+ } while (data & (1 << 14));
+
+ hi6220_clk_enable(PERI_CLK0_MMC1, &peri_sc->clk0_en);
+
+ hi6220_clk_enable(PERI_CLK12_MMC1_SRC, &peri_sc->clk12_en);
+
+ do {
+ /* 1.2GHz / 50 = 24MHz */
+ writel(0x31 | (1 << 7), &peri_sc->clkcfg8bit2);
+ data = readl(&peri_sc->clkcfg8bit2);
+ } while ((data & 0x31) != 0x31);
+}
+
+static void mmc1_reset_clk(void)
+{
+ unsigned int data;
+
+ /* disable mmc1 bus clock */
+ hi6220_clk_disable(PERI_CLK0_MMC1, &peri_sc->clk0_dis);
+
+ /* enable mmc1 bus clock */
+ hi6220_clk_enable(PERI_CLK0_MMC1, &peri_sc->clk0_en);
+
+ /* reset mmc1 clock domain */
+ writel(PERI_RST0_MMC1, &peri_sc->rst0_en);
+
+ /* bypass mmc1 clock phase */
+ data = readl(&peri_sc->ctrl2);
+ data |= 3 << 2;
+ writel(data, &peri_sc->ctrl2);
+
+ /* disable low power */
+ data = readl(&peri_sc->ctrl13);
+ data |= 1 << 4;
+ writel(data, &peri_sc->ctrl13);
+ do {
+ data = readl(&peri_sc->rst0_stat);
+ } while (!(data & PERI_RST0_MMC1));
+
+ /* unreset mmc0 clock domain */
+ writel(PERI_RST0_MMC1, &peri_sc->rst0_dis);
+ do {
+ data = readl(&peri_sc->rst0_stat);
+ } while (data & PERI_RST0_MMC1);
+}
+
+/* PMU SSI is the IP that maps the external PMU hi6553 registers as IO */
+static void hi6220_pmussi_init(void)
+{
+ uint32_t data;
+
+ /* Take PMUSSI out of reset */
+ writel(ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N,
+ &ao_sc->rst4_dis);
+ do {
+ data = readl(&ao_sc->rst4_stat);
+ } while (data & ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N);
+
+ /* set PMU SSI clock latency for read operation */
+ data = readl(&ao_sc->mcu_subsys_ctrl3);
+ data &= ~ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_MASK;
+ data |= ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_3;
+ writel(data, &ao_sc->mcu_subsys_ctrl3);
+
+ /* enable PMUSSI clock */
+ data = ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_CCPU |
+ ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_MCU;
+
+ hi6220_clk_enable(data, &ao_sc->clk5_en);
+
+ /* Output high to PMIC on PWR_HOLD_GPIO0_0 */
+ gpio_request(0, "PWR_HOLD_GPIO0_0");
+ gpio_direction_output(0, 1);
+}
+
+int misc_init_r(void)
+{
+ return 0;
+}
+
+int board_init(void)
+{
+ gd->flags = 0;
+
+ return 0;
+}
+
+#ifdef CONFIG_GENERIC_MMC
+
+static int init_dwmmc(void)
+{
+ int ret;
+
+#ifdef CONFIG_DWMMC
+
+ /* mmc0 clocks are already configured by ATF */
+ ret = hi6220_pinmux_config(PERIPH_ID_SDMMC0);
+ if (ret)
+ printf("%s: Error configuring pinmux for eMMC (%d)\n"
+ , __func__, ret);
+
+ ret |= hi6220_dwmci_add_port(0, HI6220_MMC0_BASE, 8);
+ if (ret)
+ printf("%s: Error adding eMMC port (%d)\n", __func__, ret);
+
+
+ /* take mmc1 (sd slot) out of reset, configure clocks and pinmuxing */
+ mmc1_init_pll();
+ mmc1_reset_clk();
+
+ ret |= hi6220_pinmux_config(PERIPH_ID_SDMMC1);
+ if (ret)
+ printf("%s: Error configuring pinmux for eMMC (%d)\n"
+ , __func__, ret);
+
+ config_sd_carddetect();
+
+ ret |= hi6220_dwmci_add_port(1, HI6220_MMC1_BASE, 4);
+ if (ret)
+ printf("%s: Error adding SD port (%d)\n", __func__, ret);
+
+#endif
+ return ret;
+}
+
+/* setup board specific PMIC */
+int power_init_board(void)
+{
+ /* init the hi6220 pmussi ip */
+ hi6220_pmussi_init();
+
+ power_hi6553_init((u8 *)HI6220_PMUSSI_BASE);
+
+ return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int ret;
+
+ /* add the eMMC and sd ports */
+ ret = init_dwmmc();
+
+ if (ret)
+ debug("init_dwmmc failed\n");
+
+ return ret;
+}
+#endif
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
+/* Use the Watchdog to cause reset */
+void reset_cpu(ulong addr)
+{
+ /* TODO program the watchdog */
+}
diff --git a/board/lge/sniper/Kconfig b/board/lge/sniper/Kconfig
new file mode 100644
index 0000000..f7a682e
--- /dev/null
+++ b/board/lge/sniper/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SNIPER
+
+config SYS_BOARD
+ default "sniper"
+
+config SYS_VENDOR
+ default "lge"
+
+config SYS_CONFIG_NAME
+ default "sniper"
+
+endif
diff --git a/board/lge/sniper/MAINTAINERS b/board/lge/sniper/MAINTAINERS
new file mode 100644
index 0000000..0e7baa5
--- /dev/null
+++ b/board/lge/sniper/MAINTAINERS
@@ -0,0 +1,6 @@
+SNIPER BOARD
+M: Paul Kocialkowski <contact@paulk.fr>
+S: Maintained
+F: board/lge/sniper/
+F: include/configs/sniper.h
+F: configs/sniper_defconfig
diff --git a/board/lge/sniper/Makefile b/board/lge/sniper/Makefile
new file mode 100644
index 0000000..2d216fc
--- /dev/null
+++ b/board/lge/sniper/Makefile
@@ -0,0 +1,9 @@
+#
+# LG Optimus Black (P970) codename sniper board
+#
+# Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := sniper.o
diff --git a/board/lge/sniper/sniper.c b/board/lge/sniper/sniper.c
new file mode 100644
index 0000000..a43f640
--- /dev/null
+++ b/board/lge/sniper/sniper.c
@@ -0,0 +1,202 @@
+/*
+ * LG Optimus Black (P970) codename sniper board
+ *
+ * Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <dm.h>
+#include <linux/ctype.h>
+#include <linux/usb/musb.h>
+#include <asm/omap_musb.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <ns16550.h>
+#include <twl4030.h>
+#include "sniper.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const omap3_sysinfo sysinfo = {
+ .mtype = DDR_STACKED,
+ .board_string = "Sniper",
+ .nand_string = "MMC"
+};
+
+static const struct ns16550_platdata serial_omap_platdata = {
+ .base = OMAP34XX_UART3,
+ .reg_shift = 2,
+ .clock = V_NS16550_CLK
+};
+
+U_BOOT_DEVICE(sniper_serial) = {
+ .name = "serial_omap",
+ .platdata = &serial_omap_platdata
+};
+
+static struct musb_hdrc_config musb_config = {
+ .multipoint = 1,
+ .dyn_fifo = 1,
+ .num_eps = 16,
+ .ram_bits = 12
+};
+
+static struct omap_musb_board_data musb_board_data = {
+ .interface_type = MUSB_INTERFACE_ULPI,
+};
+
+static struct musb_hdrc_platform_data musb_platform_data = {
+ .mode = MUSB_PERIPHERAL,
+ .config = &musb_config,
+ .power = 100,
+ .platform_ops = &omap2430_ops,
+ .board_data = &musb_board_data,
+};
+
+#ifdef CONFIG_SPL_BUILD
+void get_board_mem_timings(struct board_sdrc_timings *timings)
+{
+ timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
+ timings->ctrla = HYNIX_V_ACTIMA_200;
+ timings->ctrlb = HYNIX_V_ACTIMB_200;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+ timings->mr = MICRON_V_MR_165;
+}
+#endif
+
+u32 get_board_rev(void)
+{
+ /* Sold devices are expected to be at least revision F. */
+ return 6;
+}
+
+int board_init(void)
+{
+ /* GPMC init */
+ gpmc_init();
+
+ /* MACH number */
+ gd->bd->bi_arch_number = 3000;
+
+ /* ATAGs location */
+ gd->bd->bi_boot_params = OMAP34XX_SDRC_CS0 + 0x100;
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ unsigned char keypad_matrix[64] = { 0 };
+ char serial_string[17] = { 0 };
+ char reboot_mode[2] = { 0 };
+ u32 dieid[4] = { 0 };
+ unsigned char keys[3];
+ unsigned char data = 0;
+
+ /* Power button reset init */
+
+ twl4030_power_reset_init();
+
+ /* Keypad */
+
+ twl4030_keypad_scan((unsigned char *)&keypad_matrix);
+
+ keys[0] = twl4030_keypad_key((unsigned char *)&keypad_matrix, 0, 0);
+ keys[1] = twl4030_keypad_key((unsigned char *)&keypad_matrix, 0, 1);
+ keys[2] = twl4030_keypad_key((unsigned char *)&keypad_matrix, 0, 2);
+
+ /* Reboot mode */
+
+ reboot_mode[0] = omap_reboot_mode();
+
+ if (keys[0])
+ reboot_mode[0] = 'r';
+ else if (keys[1])
+ reboot_mode[0] = 'b';
+
+ if (reboot_mode[0] > 0 && isascii(reboot_mode[0])) {
+ if (!getenv("reboot-mode"))
+ setenv("reboot-mode", (char *)reboot_mode);
+
+ omap_reboot_mode_clear();
+ } else {
+ /*
+ * When not rebooting, valid power on reasons are either the
+ * power button, charger plug or USB plug.
+ */
+
+ data |= twl4030_input_power_button();
+ data |= twl4030_input_charger();
+ data |= twl4030_input_usb();
+
+ if (!data)
+ twl4030_power_off();
+ }
+
+ /* Serial number */
+
+ get_dieid((u32 *)&dieid);
+
+ if (!getenv("serial#")) {
+ snprintf(serial_string, sizeof(serial_string),
+ "%08x%08x", dieid[0], dieid[3]);
+
+ setenv("serial#", serial_string);
+ }
+
+ /* MUSB */
+
+ musb_register(&musb_platform_data, &musb_board_data, (void *)MUSB_BASE);
+
+ return 0;
+}
+
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+ char *serial_string;
+ unsigned long long serial;
+
+ serial_string = getenv("serial#");
+
+ if (serial_string) {
+ serial = simple_strtoull(serial_string, NULL, 16);
+
+ serialnr->high = (unsigned int) (serial >> 32);
+ serialnr->low = (unsigned int) (serial & 0xffffffff);
+ } else {
+ serialnr->high = 0;
+ serialnr->low = 0;
+ }
+}
+
+void reset_misc(void)
+{
+ omap_reboot_mode_store('u');
+}
+
+int fb_set_reboot_flag(void)
+{
+ return omap_reboot_mode_store('b');
+}
+
+void set_muxconf_regs(void)
+{
+ MUX_SNIPER();
+}
+
+#ifndef CONFIG_SPL_BUILD
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(1, 0, 0, -1, -1);
+}
+#endif
+
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(1);
+}
diff --git a/board/lge/sniper/sniper.h b/board/lge/sniper/sniper.h
new file mode 100644
index 0000000..b2a09b3
--- /dev/null
+++ b/board/lge/sniper/sniper.h
@@ -0,0 +1,365 @@
+/*
+ * LG Optimus Black (P970) codename sniper board
+ *
+ * Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SNIPER_H_
+#define _SNIPER_H_
+
+#include <asm/arch/mux.h>
+
+#define MUX_SNIPER() \
+ /* SDRC */ \
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /* SDRC_D0 */\
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /* SDRC_D1 */\
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /* SDRC_D2 */\
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /* SDRC_D3 */\
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /* SDRC_D4 */\
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /* SDRC_D5 */\
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /* SDRC_D6 */\
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /* SDRC_D7 */\
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /* SDRC_D8 */\
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /* SDRC_D9 */\
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /* SDRC_D10 */\
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /* SDRC_D11 */\
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /* SDRC_D12 */\
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /* SDRC_D13 */\
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /* SDRC_D14 */\
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /* SDRC_D15 */\
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /* SDRC_D16 */\
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /* SDRC_D17 */\
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /* SDRC_D18 */\
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /* SDRC_D19 */\
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /* SDRC_D20 */\
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /* SDRC_D21 */\
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /* SDRC_D22 */\
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /* SDRC_D23 */\
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /* SDRC_D24 */\
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /* SDRC_D25 */\
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /* SDRC_D26 */\
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /* SDRC_D27 */\
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /* SDRC_D28 */\
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /* SDRC_D29 */\
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /* SDRC_D30 */\
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /* SDRC_D31 */\
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /* SDRC_CLK */\
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /* SDRC_DQS0 */\
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /* SDRC_DQS1 */\
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /* SDRC_DQS2 */\
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /* SDRC_DQS3 */ \
+ /* GPMC */ \
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | DIS | M4)) /* GPIO_34: LCD_RESET_N */ \
+ MUX_VAL(CP(GPMC_A2), (IEN | PTU | DIS | M4)) /* GPIO_35: TOUCH_INT_N */ \
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | DIS | M4)) /* GPIO_36: VT_CAM_PWDN */ \
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | DIS | M4)) /* GPIO_37: CAM_SUBPM_EN */\
+ MUX_VAL(CP(GPMC_A5), (IEN | PTD | DIS | M4)) /* GPIO_38: MODEM_PWR_CHK */\
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M4)) /* GPIO_39: MODEM_WAKE */\
+ MUX_VAL(CP(GPMC_A7), (IEN | PTU | DIS | M4)) /* GPIO_40: MUIC_INT_N */\
+ MUX_VAL(CP(GPMC_A8), (IEN | PTD | DIS | M4)) /* GPIO_41: GYRO_INT_N */\
+ MUX_VAL(CP(GPMC_A9), (IEN | PTD | EN | M4)) /* GPIO_42: MOTION_INT_N */\
+ MUX_VAL(CP(GPMC_A10), (IEN | PTD | DIS | M4)) /* GPIO_43: BT_HOST_WAKEUP */\
+ MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /* GPMC_D0 */ \
+ MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /* GPMC_D1 */ \
+ MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /* GPMC_D2 */ \
+ MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /* GPMC_D3 */ \
+ MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /* GPMC_D4 */ \
+ MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /* GPMC_D5 */ \
+ MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /* GPMC_D6 */ \
+ MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /* GPMC_D7 */ \
+ MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /* GPMC_D8 */ \
+ MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /* GPMC_D9 */ \
+ MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /* GPMC_D10 */ \
+ MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /* GPMC_D11 */ \
+ MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /* GPMC_D12 */ \
+ MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /* GPMC_D13 */ \
+ MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /* GPMC_D14 */ \
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTD | DIS | M7)) \
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTD | DIS | M4)) /* GPIO_52: BT_WAKE_UP */ \
+ MUX_VAL(CP(GPMC_NCS2), (IEN | PTD | DIS | M4)) /* GPIO_53: LCD_TE */ \
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M4)) /* GPIO_54: LCD_CS */ \
+ MUX_VAL(CP(GPMC_NCS4), (IDIS | PTD | DIS | M4)) /* GPIO_55: BT_MAKER_ID */ \
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M3)) /* GPIO_56: VIBE_PWM */ \
+ MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | DIS | M4)) /* GPIO_57: VIBE_EN */ \
+ MUX_VAL(CP(GPMC_NCS7), (IEN | PTD | DIS | M4)) /* GPIO_58: COM_INT */ \
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M7)) /* SAFE_MODE */ \
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M7)) \
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M7)) \
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M7)) \
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M4)) /* GPIO_60: PROXI_LDO_EN */ \
+ MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M4)) /* GPIO_61: VT_RESET_N */ \
+ MUX_VAL(CP(GPMC_NWP), (IDIS | PTD | DIS | M4)) /* GPIO_62: LCD_CP_EN */ \
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTD | DIS | M4)) /* GPIO_63: ONENAND_INT */ \
+ MUX_VAL(CP(GPMC_WAIT2), (IDIS | PTD | DIS | M2)) /* GPIO_64: UART4_TX_IPC */ \
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTD | DIS | M2)) /* GPIO_65: UART4_RX_IPC */ \
+ /* DSS */ \
+ MUX_VAL(CP(DSS_PCLK), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
+ MUX_VAL(CP(DSS_HSYNC), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
+ MUX_VAL(CP(DSS_VSYNC), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
+ MUX_VAL(CP(DSS_ACBIAS), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M1)) /* DSI_DX0 */ \
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M1)) /* DSI_DY0 */ \
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M1)) /* DSI_DX1 */ \
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M1)) /* DSI_DY1 */ \
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M1)) /* DSI_DX2 */ \
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M1)) /* DSI_DY2 */ \
+ MUX_VAL(CP(DSS_DATA6), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
+ MUX_VAL(CP(DSS_DATA7), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
+ MUX_VAL(CP(DSS_DATA8), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
+ MUX_VAL(CP(DSS_DATA9), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
+ MUX_VAL(CP(DSS_DATA10), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
+ MUX_VAL(CP(DSS_DATA11), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
+ MUX_VAL(CP(DSS_DATA12), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
+ MUX_VAL(CP(DSS_DATA13), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
+ MUX_VAL(CP(DSS_DATA14), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
+ MUX_VAL(CP(DSS_DATA15), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
+ MUX_VAL(CP(DSS_DATA16), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M4)) /* GPIO_87: MIC_SEL */ \
+ MUX_VAL(CP(DSS_DATA18), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
+ MUX_VAL(CP(DSS_DATA19), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
+ MUX_VAL(CP(DSS_DATA20), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
+ MUX_VAL(CP(DSS_DATA21), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
+ MUX_VAL(CP(DSS_DATA22), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
+ MUX_VAL(CP(DSS_DATA23), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
+ /* CAM */ \
+ MUX_VAL(CP(CAM_HS), (IEN | PTD | EN | M0)) /* CAM_HS */ \
+ MUX_VAL(CP(CAM_VS), (IEN | PTD | EN | M0)) /* CAM_VS */ \
+ MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /* CAM_XCLKA */ \
+ MUX_VAL(CP(CAM_PCLK), (IEN | PTD | EN | M0)) /* CAM_PCLK */ \
+ MUX_VAL(CP(CAM_FLD), (IDIS | PTU | DIS | M4)) /* GPIO_98: 5M_RESET_N */ \
+ MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M2)) /* CSI2_DX2 */ \
+ MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M2)) /* CSI2_DY2 */ \
+ MUX_VAL(CP(CAM_D2), (IDIS | PTD | EN | M4)) /* GPIO_101: IFX_USB_VBUS_EN */ \
+ MUX_VAL(CP(CAM_D3), (IDIS | PTD | DIS | M7)) /* SAFE_MODE */ \
+ MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /* CAM_D4 */ \
+ MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /* CAM_D5 */ \
+ MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /* CAM_D6 */ \
+ MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /* CAM_D7 */ \
+ MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /* CAM_D8 */ \
+ MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /* CAM_D9 */ \
+ MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /* CAM_D10 */ \
+ MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /* CAM_D11 */ \
+ MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | DIS | M0)) /* CAM_XCLKB */ \
+ MUX_VAL(CP(CAM_WEN), (IDIS | PTD | DIS | M4)) /* GPIO_167: 5M_CAM_VCN_EN */ \
+ MUX_VAL(CP(CAM_STROBE), (IEN | PTD | DIS | M7)) /* SAFE_MODE */ \
+ /* CSI2 */ \
+ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /* CSI2_DX0 */ \
+ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /* CSI2_DY0 */ \
+ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /* CSI2_DX1 */ \
+ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /* CSI2_DY1 */ \
+ /* MCBSP2 */ \
+ MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /* MCBSP2_FSX */ \
+ MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /* MCBSP2_CLKX */ \
+ MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /* MCBSP2_DR */ \
+ MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /* MCBSP2_DX */ \
+ /* MMC1 */ \
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTD | DIS | M0)) /* MMC1_CLK */ \
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) /* MMC1_CMD */ \
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) /* MMC1_DAT0 */ \
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) /* MMC1_DAT1 */ \
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) /* MMC1_DAT2 */ \
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) /* MMC1_DAT3 */ \
+ MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | DIS | M7)) /* SAFE_MODE */ \
+ MUX_VAL(CP(MMC1_DAT5), (IEN | PTD | DIS | M7)) /* SAFE_MODE */ \
+ MUX_VAL(CP(MMC1_DAT6), (IEN | PTD | DIS | M7)) /* SAFE_MODE */ \
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTD | DIS | M7)) /* SAFE_MODE */ \
+ /* MMC2 */ \
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M0)) /* MMC2_CLK */ \
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M0)) /* MMC2_CMD */ \
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M0)) /* MMC2_DAT0 */ \
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | DIS | M0)) /* MMC2_DAT1 */ \
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | DIS | M0)) /* MMC2_DAT2 */ \
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | DIS | M0)) /* MMC2_DAT3 */ \
+ MUX_VAL(CP(MMC2_DAT4), (IEN | PTD | DIS | M0)) /* MMC2_DAT4 */ \
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTD | DIS | M0)) /* MMC2_DAT5 */ \
+ MUX_VAL(CP(MMC2_DAT6), (IEN | PTD | DIS | M0)) /* MMC2_DAT6 */ \
+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTD | DIS | M0)) /* MMC2_DAT7 */ \
+ /* MCBSP3 */ \
+ MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) /* MCBSP3_DX */ \
+ MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) /* MCBSP3_DR */ \
+ MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)) /* MCBSP3_CLKX */ \
+ MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) /* MCBSP3_FSX */ \
+ /* UART2 */ \
+ MUX_VAL(CP(UART2_CTS), (IEN | PTU | DIS | M0)) /* UART2_CTS */ \
+ MUX_VAL(CP(UART2_RTS), (IDIS | PTU | DIS | M0)) /* UART2_RTS */ \
+ MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /* UART2_TX */ \
+ MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) /* UART2_RX */ \
+ /* UART1 */ \
+ MUX_VAL(CP(UART1_TX), (IDIS | PTU | DIS | M0)) /* UART1_TX */ \
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTU | DIS | M0)) /* UART1_RTS */ \
+ MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /* UART1_CTS */ \
+ MUX_VAL(CP(UART1_RX), (IEN | PTU | DIS | M0)) /* UART1_RX */ \
+ /* MCBSP4 */ \
+ MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /* GPIO_152: GPS_PWR_ON */ \
+ MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /* GPIO_153: GPS_RESET_N */ \
+ MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /* GPIO_154: FLASH_LED_TORCH */ \
+ MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | DIS | M4)) /* GPIO_155: FLASH_LED_EN */ \
+ /* MCBSP1 */ \
+ MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) /* MCBSP1_CLKR */ \
+ MUX_VAL(CP(MCBSP1_FSR), (IEN | PTD | DIS | M0)) /* MCBSP1_FSR */ \
+ MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) /* MCBSP1_DX */ \
+ MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) /* MCBSP1_DR */ \
+ MUX_VAL(CP(MCBSP_CLKS), (IDIS | PTD | DIS | M7)) /* SAFE_MODE */ \
+ MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /* GPIO_161: OMAP_UART_SW */ \
+ MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /* GPIO_162: IFX_UART_SW */ \
+ /* UART3 */ \
+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M4)) /* GPIO_163: HOOK_DIG */ \
+ MUX_VAL(CP(UART3_RTS_SD), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /* UART3_RX_IRRX */ \
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /* UART3_TX_IRTX */ \
+ /* HSUSB0 */ \
+ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | EN | M0)) /* HSUSB0_CLK */\
+ MUX_VAL(CP(HSUSB0_STP), (IDIS | PTD | DIS | M0)) /* HSUSB0_STP */\
+ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | EN | M0)) /* HSUSB0_DIR */\
+ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | EN | M0)) /* HSUSB0_NXT */\
+ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | EN | M0)) /* HSUSB0_DATA0 */\
+ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | EN | M0)) /* HSUSB0_DATA1 */\
+ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | EN | M0)) /* HSUSB0_DATA2 */\
+ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | EN | M0)) /* HSUSB0_DATA3 */\
+ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | EN | M0)) /* HSUSB0_DATA4 */\
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | EN | M0)) /* HSUSB0_DATA5 */\
+ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | EN | M0)) /* HSUSB0_DATA6 */\
+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | EN | M0)) /* HSUSB0_DATA7 */ \
+ /* I2C1 */ \
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* I2C1_SCL */ \
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /* I2C1_SDA */ \
+ /* I2C2 */ \
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | DIS | M0)) /* I2C2_SCL */ \
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | DIS | M0)) /* I2C2_SDA */ \
+ /* I2C3 */ \
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | DIS | M0)) /* I2C3_SCL */ \
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | DIS | M0)) /* I2C3_SDA */ \
+ /* I2C4 */ \
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /* I2C4_SCL */ \
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /* I2C4_SDA */ \
+ /* HDQ */ \
+ MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) /* GPIO_170: EAR_SENSE */ \
+ /* MCSPI1 */ \
+ MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
+ MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
+ MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
+ MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
+ MUX_VAL(CP(MCSPI1_CS1), (IEN | PTU | DIS | M4)) /* GPIO_175: GAUGE_INT */ \
+ MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /* GPIO_176: MODEM_SEND */ \
+ MUX_VAL(CP(MCSPI1_CS3), (IDIS | PTU | DIS | M4)) /* GPIO_177: MODEM_CHK */ \
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M0)) /* MCSPI2_CLK */ \
+ MUX_VAL(CP(MCSPI2_SIMO), (IDIS | PTD | DIS | M0)) /* MCSPI2_SIMO */ \
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /* MCSPI2_SOMI */ \
+ MUX_VAL(CP(MCSPI2_CS0), (IDIS | PTU | DIS | M4)) /* GPIO_181: WLAN_WAKEUP */ \
+ MUX_VAL(CP(MCSPI2_CS1), (IDIS | PTD | DIS | M4)) /* GPIO_182: USIF1_SW */ \
+ /* SYS */ \
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /* SYS_32K */ \
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /* SYS_CLKREQ */ \
+ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /* SYS_NIRQ */ \
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTU | EN | M7)) /* SAFE_MODE */ \
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTU | EN | M7)) /* SAFE_MODE */ \
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
+ MUX_VAL(CP(SYS_BOOT6), (IEN | PTU | EN | M7)) /* SAFE_MODE */ \
+ MUX_VAL(CP(SYS_OFF_MODE), (IDIS | PTD | DIS | M0)) /* SYS_OFF_MODE */ \
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTU | DIS | M4)) /* GPIO_10: MICROSD_DET_N */ \
+ MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | EN | M7)) /* SAFE_MODE */ \
+ /* JTAG */ \
+ MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) /* JTAG_NTRST */ \
+ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /* JTAG_TCK */ \
+ MUX_VAL(CP(JTAG_TMS), (IEN | PTU | EN | M0)) /* JTAG_TMS */ \
+ MUX_VAL(CP(JTAG_TDI), (IEN | PTU | EN | M0)) /* JTAG_TDI */ \
+ MUX_VAL(CP(JTAG_EMU0), (IEN | PTU | DIS | M0)) /* JTAG_EMU0 */ \
+ MUX_VAL(CP(JTAG_EMU1), (IEN | PTU | DIS | M0)) /* JTAG_EMU1 */ \
+ /* ETK */ \
+ MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTD | DIS | M2)) /* SDMMC3_CLK */ \
+ MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /* SDMMC3_CMD */ \
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M4)) /* GPIO_14: PROX_OUT */ \
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M4)) /* GPIO_15: CHG_STATUS_N_OMAP */ \
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | DIS | M4)) /* GPIO_16: BT_EN */ \
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M2)) /* SDMMC3_DAT3 */ \
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M2)) /* SDMMC3_DAT0 */ \
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M2)) /* SDMMC3_DAT1 */ \
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M2)) /* SDMMC3_DAT2 */ \
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M4)) /* GPIO_21: IPC_SRDY */ \
+ MUX_VAL(CP(ETK_D8_ES2), (IDIS | PTD | DIS | M4)) /* GPIO_22: IPC_MRDY */ \
+ MUX_VAL(CP(ETK_D9_ES2), (IDIS | PTD | DIS | M4)) /* GPIO_23: WLAN_EN */ \
+ MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | EN | M4)) /* GPIO_24: WLAN_HOST_WAKEUP */ \
+ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M4)) /* GPIO_25: CHG_EN_SET_N_OMAP */ \
+ MUX_VAL(CP(ETK_D12_ES2), (IDIS | PTD | DIS | M4)) /* GPIO_26: IFX_RESET_1.8V */ \
+ MUX_VAL(CP(ETK_D13_ES2), (IDIS | PTD | DIS | M4)) /* GPIO_27: IFX_PWRON_1.8V */ \
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | EN | M4)) /* GPIO_28: CRADLE_DETECT_N */ \
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | EN | M4)) /* GPIO_29: CRADLE_DETECT_S */ \
+ /* D2D */ \
+ MUX_VAL(CP(D2D_MCAD0), (IEN | PTD | EN | M0)) /* D2D_MCAD0 */ \
+ MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /* D2D_MCAD1 */ \
+ MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /* D2D_MCAD2 */ \
+ MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /* D2D_MCAD3 */ \
+ MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /* D2D_MCAD4 */ \
+ MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /* D2D_MCAD5 */ \
+ MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /* D2D_MCAD6 */ \
+ MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /* D2D_MCAD7 */ \
+ MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /* D2D_MCAD8 */ \
+ MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /* D2D_MCAD9 */ \
+ MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /* D2D_MCAD10 */ \
+ MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /* D2D_MCAD11 */ \
+ MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /* D2D_MCAD12 */ \
+ MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /* D2D_MCAD13 */ \
+ MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /* D2D_MCAD14 */ \
+ MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /* D2D_MCAD15 */ \
+ MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /* D2D_MCAD16 */ \
+ MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /* D2D_MCAD17 */ \
+ MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /* D2D_MCAD18 */ \
+ MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /* D2D_MCAD19 */ \
+ MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /* D2D_MCAD20 */ \
+ MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /* D2D_MCAD21 */ \
+ MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /* D2D_MCAD22 */ \
+ MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /* D2D_MCAD23 */ \
+ MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /* D2D_MCAD24 */ \
+ MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /* D2D_MCAD25 */ \
+ MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /* D2D_MCAD26 */ \
+ MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /* D2D_MCAD27 */ \
+ MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /* D2D_MCAD28 */ \
+ MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /* D2D_MCAD29 */ \
+ MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /* D2D_MCAD30 */ \
+ MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /* D2D_MCAD31 */ \
+ MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /* D2D_MCAD32 */ \
+ MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /* D2D_MCAD33 */ \
+ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /* D2D_MCAD34 */ \
+ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /* D2D_MCAD35 */ \
+ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /* D2D_MCAD36 */ \
+ MUX_VAL(CP(D2D_CLK26MI), (IDIS | PTD | DIS | M0)) /* D2D_CLK26MI */ \
+ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTU | EN | M0)) /* D2D_NRESPWRON */ \
+ MUX_VAL(CP(D2D_NRESWARM), (IDIS | PTU | DIS | M0)) /* D2D_NRESWARM */ \
+ MUX_VAL(CP(D2D_ARM9NIRQ), (IDIS | PTD | DIS | M0)) /* D2D_ARM9NIRQ */ \
+ MUX_VAL(CP(D2D_UMA2P6FIQ), (IDIS | PTD | DIS | M0)) /* D2D_UMA2P6FIQ */ \
+ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | DIS | M0)) /* D2D_SPINT */ \
+ MUX_VAL(CP(D2D_FRINT), (IEN | PTD | DIS | M0)) /* D2D_FRINT */ \
+ MUX_VAL(CP(D2D_DMAREQ0), (IDIS | PTD | DIS | M0)) /* D2D_DMAREQ0 */ \
+ MUX_VAL(CP(D2D_DMAREQ1), (IDIS | PTD | DIS | M0)) /* D2D_DMAREQ1 */ \
+ MUX_VAL(CP(D2D_DMAREQ2), (IDIS | PTD | DIS | M0)) /* D2D_DMAREQ2 */ \
+ MUX_VAL(CP(D2D_DMAREQ3), (IDIS | PTD | DIS | M0)) /* D2D_DMAREQ3 */ \
+ MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /* D2D_N3GTRST */ \
+ MUX_VAL(CP(D2D_N3GTDI), (IEN | PTU | EN | M0)) /* D2D_N3GTDI */ \
+ MUX_VAL(CP(D2D_N3GTDO), (IDIS | PTD | DIS | M0)) /* D2D_N3GTDO */ \
+ MUX_VAL(CP(D2D_N3GTMS), (IEN | PTU | EN | M0)) /* D2D_N3GTMS */ \
+ MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /* D2D_N3GTCK */ \
+ MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /* D2D_N3GRTCK */ \
+ MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /* D2D_MSTDBY */ \
+ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /* D2D_SWAKEUP */ \
+ MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /* D2D_IDLEREQ */ \
+ MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /* D2D_IDLEACK */ \
+ MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /* D2D_MWRITE */ \
+ MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /* D2D_SWRITE */ \
+ MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /* D2D_MREAD */ \
+ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /* D2D_SREAD */ \
+ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /* D2D_MBUSFLAG */ \
+ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /* D2D_SBUSFLAG */ \
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | DIS | M0)) /* SDRC_CKE0 */ \
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | DIS | M0)) /* SDRC_CKE1 */ \
+ MUX_VAL(CP(GPIO127), (IEN | PTD | DIS | M7)) /* SAFE_MODE */ \
+ MUX_VAL(CP(GPIO126), (IDIS | PTD | DIS | M4)) /* GPIO_126: OMAP_SEND */ \
+ MUX_VAL(CP(GPIO128), (IDIS | PTD | DIS | M4)) /* GPIO_128: KEY_LED_RESET */ \
+ MUX_VAL(CP(GPIO129), (IEN | PTD | DIS | M4)) /* GPIO_129: MODEM_AP_WAKE */
+
+#endif
diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
index 96fe870..d21750e 100644
--- a/board/raspberrypi/rpi/rpi.c
+++ b/board/raspberrypi/rpi/rpi.c
@@ -182,7 +182,7 @@
int dram_init(void)
{
- ALLOC_ALIGN_BUFFER(struct msg_get_arm_mem, msg, 1, 16);
+ ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_arm_mem, msg, 1);
int ret;
BCM2835_MBOX_INIT_HDR(msg);
@@ -212,7 +212,7 @@
static void set_usbethaddr(void)
{
- ALLOC_ALIGN_BUFFER(struct msg_get_mac_address, msg, 1, 16);
+ ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_mac_address, msg, 1);
int ret;
if (!models[rpi_board_rev].has_onboard_eth)
@@ -245,7 +245,7 @@
static int power_on_module(u32 module)
{
- ALLOC_ALIGN_BUFFER(struct msg_set_power_state, msg_pwr, 1, 16);
+ ALLOC_CACHE_ALIGN_BUFFER(struct msg_set_power_state, msg_pwr, 1);
int ret;
BCM2835_MBOX_INIT_HDR(msg_pwr);
@@ -269,7 +269,7 @@
static void get_board_rev(void)
{
- ALLOC_ALIGN_BUFFER(struct msg_get_board_rev, msg, 1, 16);
+ ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_board_rev, msg, 1);
int ret;
const char *name;
@@ -324,7 +324,7 @@
int board_mmc_init(bd_t *bis)
{
- ALLOC_ALIGN_BUFFER(struct msg_get_clock_rate, msg_clk, 1, 16);
+ ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_clock_rate, msg_clk, 1);
int ret;
power_on_module(BCM2835_MBOX_POWER_DEVID_SDHCI);
diff --git a/board/siemens/smartweb/Kconfig b/board/siemens/smartweb/Kconfig
new file mode 100644
index 0000000..0871bcc
--- /dev/null
+++ b/board/siemens/smartweb/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SMARTWEB
+
+config SYS_BOARD
+ default "smartweb"
+
+config SYS_VENDOR
+ default "siemens"
+
+config SYS_CONFIG_NAME
+ default "smartweb"
+
+endif
diff --git a/board/siemens/smartweb/MAINTAINERS b/board/siemens/smartweb/MAINTAINERS
new file mode 100644
index 0000000..51298ff
--- /dev/null
+++ b/board/siemens/smartweb/MAINTAINERS
@@ -0,0 +1,6 @@
+SMARTWEB_HW BOARD
+M: Heiko Schocher <hs@denx.de>
+S: Maintained
+F: board/siemens/smartweb
+F: include/configs/smartweb.h
+F: configs/smartweb_defconfig
diff --git a/board/siemens/smartweb/Makefile b/board/siemens/smartweb/Makefile
new file mode 100644
index 0000000..55e7798
--- /dev/null
+++ b/board/siemens/smartweb/Makefile
@@ -0,0 +1,20 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# (C) Copyright 2012
+# Markus Hubig <mhubig@imko.de>
+# IMKO GmbH <www.imko.de>
+#
+# (C) Copyright 2014
+# Heiko Schocher <hs@denx.de>
+# DENX Software Engineering GmbH
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += smartweb.o
diff --git a/board/siemens/smartweb/smartweb.c b/board/siemens/smartweb/smartweb.c
new file mode 100644
index 0000000..cf8a7f5
--- /dev/null
+++ b/board/siemens/smartweb/smartweb.c
@@ -0,0 +1,220 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Achim Ehrlich <aehrlich@taskit.de>
+ * taskit GmbH <www.taskit.de>
+ *
+ * (C) Copyright 2012-
+ * Markus Hubig <mhubig@imko.de>
+ * IMKO GmbH <www.imko.de>
+ * (C) Copyright 2014
+ * Heiko Schocher <hs@denx.de>
+ * DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9_sdramc.h>
+#include <asm/arch/at91sam9260_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_spi.h>
+#include <spi.h>
+#include <asm/arch/gpio.h>
+#include <watchdog.h>
+#ifdef CONFIG_MACB
+# include <net.h>
+# include <netdev.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void smartweb_nand_hw_init(void)
+{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ unsigned long csa;
+
+ /* Assign CS3 to NAND/SmartMedia Interface */
+ csa = readl(&matrix->ebicsa);
+ csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+ writel(csa, &matrix->ebicsa);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+ AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_TDF_CYCLE(2),
+ &smc->cs[3].mode);
+
+ /* Configure RDY/BSY */
+ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+ /* Enable NandFlash */
+ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+
+#ifdef CONFIG_MACB
+static void smartweb_macb_hw_init(void)
+{
+ struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
+
+ /* Enable the PHY Chip via PA26 on the Stamp 2 Adaptor */
+ at91_set_gpio_output(AT91_PIN_PA26, 0);
+
+ /*
+ * Disable pull-up on:
+ * RXDV (PA17) => PHY normal mode (not Test mode)
+ * ERX0 (PA14) => PHY ADDR0
+ * ERX1 (PA15) => PHY ADDR1
+ * ERX2 (PA25) => PHY ADDR2
+ * ERX3 (PA26) => PHY ADDR3
+ * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
+ *
+ * PHY has internal pull-down
+ */
+ writel(pin_to_mask(AT91_PIN_PA14) |
+ pin_to_mask(AT91_PIN_PA15) |
+ pin_to_mask(AT91_PIN_PA17) |
+ pin_to_mask(AT91_PIN_PA25) |
+ pin_to_mask(AT91_PIN_PA26) |
+ pin_to_mask(AT91_PIN_PA28),
+ &pioa->pudr);
+
+ at91_phy_reset();
+
+ /* Re-enable pull-up */
+ writel(pin_to_mask(AT91_PIN_PA14) |
+ pin_to_mask(AT91_PIN_PA15) |
+ pin_to_mask(AT91_PIN_PA17) |
+ pin_to_mask(AT91_PIN_PA25) |
+ pin_to_mask(AT91_PIN_PA26) |
+ pin_to_mask(AT91_PIN_PA28),
+ &pioa->puer);
+
+ /* Initialize EMAC=MACB hardware */
+ at91_macb_hw_init();
+}
+#endif /* CONFIG_MACB */
+
+int board_early_init_f(void)
+{
+ /* enable this here, as we have SPL without serial support */
+ at91_seriald_hw_init();
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ smartweb_nand_hw_init();
+#ifdef CONFIG_MACB
+ smartweb_macb_hw_init();
+#endif
+ /* power LED red */
+ at91_set_gpio_output(AT91_PIN_PC6, 0);
+ at91_set_gpio_output(AT91_PIN_PC7, 1);
+ /* alarm LED off */
+ at91_set_gpio_output(AT91_PIN_PC8, 0);
+ at91_set_gpio_output(AT91_PIN_PC9, 0);
+ /* prog LED red */
+ at91_set_gpio_output(AT91_PIN_PC10, 0);
+ at91_set_gpio_output(AT91_PIN_PC11, 1);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size(
+ (void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+#ifdef CONFIG_MACB
+int board_eth_init(bd_t *bis)
+{
+ return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
+}
+#endif /* CONFIG_MACB */
+
+#if defined(CONFIG_SPL_BUILD)
+#include <spl.h>
+#include <nand.h>
+#include <spi_flash.h>
+
+void matrix_init(void)
+{
+ struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+
+ writel((readl(&mat->scfg[3]) & (~AT91_MATRIX_SLOT_CYCLE))
+ | AT91_MATRIX_SLOT_CYCLE_(0x40),
+ &mat->scfg[3]);
+}
+
+void spl_board_init(void)
+{
+ at91_set_gpio_output(AT91_PIN_PC6, 1);
+ at91_set_gpio_output(AT91_PIN_PC7, 1);
+ /* alarm LED orange */
+ at91_set_gpio_output(AT91_PIN_PC8, 1);
+ at91_set_gpio_output(AT91_PIN_PC9, 1);
+ /* prog LED red */
+ at91_set_gpio_output(AT91_PIN_PC10, 0);
+ at91_set_gpio_output(AT91_PIN_PC11, 1);
+
+ smartweb_nand_hw_init();
+ at91_set_gpio_input(AT91_PIN_PA28, 1);
+ at91_set_gpio_input(AT91_PIN_PA29, 1);
+
+ /* check if both button are pressed */
+ if (at91_get_gpio_value(AT91_PIN_PA28) == 0 &&
+ at91_get_gpio_value(AT91_PIN_PA29) == 0) {
+ debug("Recovery button pressed\n");
+ nand_init();
+ spl_nand_erase_one(0, 0);
+ }
+}
+
+#define SDRAM_BASE_CONF (AT91_SDRAMC_NC_9 | AT91_SDRAMC_NR_13 \
+ | AT91_SDRAMC_CAS_2 \
+ | AT91_SDRAMC_NB_4 | AT91_SDRAMC_DBW_32 \
+ | AT91_SDRAMC_TWR_VAL(2) | AT91_SDRAMC_TRC_VAL(7) \
+ | AT91_SDRAMC_TRP_VAL(2) | AT91_SDRAMC_TRCD_VAL(2) \
+ | AT91_SDRAMC_TRAS_VAL(5) | AT91_SDRAMC_TXSR_VAL(8))
+
+void mem_init(void)
+{
+ struct at91_matrix *ma = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ struct at91_port *port = (struct at91_port *)ATMEL_BASE_PIOC;
+ struct sdramc_reg setting;
+
+ setting.cr = SDRAM_BASE_CONF;
+ setting.mdr = AT91_SDRAMC_MD_SDRAM;
+ setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000;
+
+ /*
+ * I write here directly in this register, because this
+ * approach is smaller than calling at91_set_a_periph() in a
+ * for loop. This saved me 96 bytes.
+ */
+ writel(0xffff0000, &port->pdr);
+
+ writel(readl(&ma->ebicsa) | AT91_MATRIX_CS1A_SDRAMC, &ma->ebicsa);
+ sdramc_initialize(ATMEL_BASE_CS1, &setting);
+}
+#endif
diff --git a/board/ti/dra7xx/Kconfig b/board/ti/dra7xx/Kconfig
index 3bbd866..80341d9 100644
--- a/board/ti/dra7xx/Kconfig
+++ b/board/ti/dra7xx/Kconfig
@@ -9,4 +9,12 @@
config SYS_CONFIG_NAME
default "dra7xx_evm"
+config CONS_INDEX
+ int "UART used for console"
+ range 1 6
+ default 1
+ help
+ The DRA7xx (and AM57x) SoC has a total of 6 UARTs available to it.
+ Depending on your specific board you may want something other than UART1
+ here.
endif
diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index 0cefb34..859a260 100644
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -80,7 +80,6 @@
return -1;
if (psc_enable_module(KS2_LPSC_CRYPTO))
return -1;
- pass_pll_pa_clk_enable();
port_num = get_num_eth_ports();
diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c
index 43dfc48..dc00cf6 100644
--- a/board/ti/ks2_evm/board_k2e.c
+++ b/board/ti/ks2_evm/board_k2e.c
@@ -18,27 +18,62 @@
[sys_clk] = 100000000,
[alt_core_clk] = 100000000,
[pa_clk] = 100000000,
- [ddr3_clk] = 100000000,
- [mcm_clk] = 312500000,
- [pcie_clk] = 100000000,
- [sgmii_clk] = 156250000,
- [xgmii_clk] = 156250000,
- [usb_clk] = 100000000,
+ [ddr3a_clk] = 100000000,
};
-static struct pll_init_data core_pll_config[] = {
- CORE_PLL_800,
- CORE_PLL_850,
- CORE_PLL_1000,
- CORE_PLL_1250,
- CORE_PLL_1350,
- CORE_PLL_1400,
- CORE_PLL_1500,
+static struct pll_init_data core_pll_config[NUM_SPDS] = {
+ [SPD800] = CORE_PLL_800,
+ [SPD850] = CORE_PLL_850,
+ [SPD1000] = CORE_PLL_1000,
+ [SPD1250] = CORE_PLL_1250,
+ [SPD1350] = CORE_PLL_1350,
+ [SPD1400] = CORE_PLL_1400,
+ [SPD1500] = CORE_PLL_1500,
};
+/* DEV and ARM speed definitions as specified in DEVSPEED register */
+int speeds[DEVSPEED_NUMSPDS] = {
+ SPD850,
+ SPD1000,
+ SPD1250,
+ SPD1350,
+ SPD1400,
+ SPD1500,
+ SPD1400,
+ SPD1350,
+ SPD1250,
+ SPD1000,
+ SPD850,
+ SPD800,
+};
+
+s16 divn_val[16] = {
+ 0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
+};
+
static struct pll_init_data pa_pll_config =
PASS_PLL_1000;
+struct pll_init_data *get_pll_init_data(int pll)
+{
+ int speed;
+ struct pll_init_data *data;
+
+ switch (pll) {
+ case MAIN_PLL:
+ speed = get_max_dev_speed();
+ data = &core_pll_config[speed];
+ break;
+ case PASS_PLL:
+ data = &pa_pll_config;
+ break;
+ default:
+ data = NULL;
+ }
+
+ return data;
+}
+
#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
struct eth_priv_t eth_priv_cfg[] = {
{
@@ -108,24 +143,15 @@
#if defined(CONFIG_BOARD_EARLY_INIT_F)
int board_early_init_f(void)
{
- int speed;
-
- speed = get_max_dev_speed();
- init_pll(&core_pll_config[speed]);
-
- init_pll(&pa_pll_config);
+ init_plls();
return 0;
}
#endif
#ifdef CONFIG_SPL_BUILD
-static struct pll_init_data spl_pll_config[] = {
- CORE_PLL_800,
-};
-
void spl_init_keystone_plls(void)
{
- init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
+ init_plls();
}
#endif
diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c
index ed181f4..6e681d7 100644
--- a/board/ti/ks2_evm/board_k2hk.c
+++ b/board/ti/ks2_evm/board_k2hk.c
@@ -21,31 +21,53 @@
[tetris_clk] = 125000000,
[ddr3a_clk] = 100000000,
[ddr3b_clk] = 100000000,
- [mcm_clk] = 312500000,
- [pcie_clk] = 100000000,
- [sgmii_srio_clk] = 156250000,
- [xgmii_clk] = 156250000,
- [usb_clk] = 100000000,
- [rp1_clk] = 123456789
};
-static struct pll_init_data core_pll_config[] = {
- CORE_PLL_799,
- CORE_PLL_999,
- CORE_PLL_1200,
+static struct pll_init_data core_pll_config[NUM_SPDS] = {
+ [SPD800] = CORE_PLL_799,
+ [SPD1000] = CORE_PLL_999,
+ [SPD1200] = CORE_PLL_1200,
};
+s16 divn_val[16] = {
+ 0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
+};
+
static struct pll_init_data tetris_pll_config[] = {
- TETRIS_PLL_800,
- TETRIS_PLL_1000,
- TETRIS_PLL_1200,
- TETRIS_PLL_1350,
- TETRIS_PLL_1400,
+ [SPD800] = TETRIS_PLL_800,
+ [SPD1000] = TETRIS_PLL_1000,
+ [SPD1200] = TETRIS_PLL_1200,
+ [SPD1350] = TETRIS_PLL_1350,
+ [SPD1400] = TETRIS_PLL_1400,
};
static struct pll_init_data pa_pll_config =
PASS_PLL_983;
+struct pll_init_data *get_pll_init_data(int pll)
+{
+ int speed;
+ struct pll_init_data *data;
+
+ switch (pll) {
+ case MAIN_PLL:
+ speed = get_max_dev_speed();
+ data = &core_pll_config[speed];
+ break;
+ case TETRIS_PLL:
+ speed = get_max_arm_speed();
+ data = &tetris_pll_config[speed];
+ break;
+ case PASS_PLL:
+ data = &pa_pll_config;
+ break;
+ default:
+ data = NULL;
+ }
+
+ return data;
+}
+
#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
struct eth_priv_t eth_priv_cfg[] = {
{
@@ -87,28 +109,15 @@
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
- int speed;
-
- speed = get_max_dev_speed();
- init_pll(&core_pll_config[speed]);
-
- init_pll(&pa_pll_config);
-
- speed = get_max_arm_speed();
- init_pll(&tetris_pll_config[speed]);
+ init_plls();
return 0;
}
#endif
#ifdef CONFIG_SPL_BUILD
-static struct pll_init_data spl_pll_config[] = {
- CORE_PLL_799,
- TETRIS_PLL_500,
-};
-
void spl_init_keystone_plls(void)
{
- init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
+ init_plls();
}
#endif
diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c
index 729a193..70e25f1 100644
--- a/board/ti/ks2_evm/board_k2l.c
+++ b/board/ti/ks2_evm/board_k2l.c
@@ -19,29 +19,54 @@
[alt_core_clk] = 100000000,
[pa_clk] = 122880000,
[tetris_clk] = 122880000,
- [ddr3_clk] = 100000000,
- [pcie_clk] = 100000000,
- [sgmii_clk] = 156250000,
- [usb_clk] = 100000000,
+ [ddr3a_clk] = 100000000,
};
-static struct pll_init_data core_pll_config[] = {
- CORE_PLL_799,
- CORE_PLL_1000,
- CORE_PLL_1198,
+static struct pll_init_data core_pll_config[NUM_SPDS] = {
+ [SPD800] = CORE_PLL_799,
+ [SPD1000] = CORE_PLL_1000,
+ [SPD800] = CORE_PLL_1198,
};
+s16 divn_val[16] = {
+ 0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
+};
+
static struct pll_init_data tetris_pll_config[] = {
- TETRIS_PLL_799,
- TETRIS_PLL_1000,
- TETRIS_PLL_1198,
- TETRIS_PLL_1352,
- TETRIS_PLL_1401,
+ [SPD800] = TETRIS_PLL_799,
+ [SPD1000] = TETRIS_PLL_1000,
+ [SPD1200] = TETRIS_PLL_1198,
+ [SPD1350] = TETRIS_PLL_1352,
+ [SPD1400] = TETRIS_PLL_1401,
};
static struct pll_init_data pa_pll_config =
PASS_PLL_983;
+struct pll_init_data *get_pll_init_data(int pll)
+{
+ int speed;
+ struct pll_init_data *data;
+
+ switch (pll) {
+ case MAIN_PLL:
+ speed = get_max_dev_speed();
+ data = &core_pll_config[speed];
+ break;
+ case TETRIS_PLL:
+ speed = get_max_arm_speed();
+ data = &tetris_pll_config[speed];
+ break;
+ case PASS_PLL:
+ data = &pa_pll_config;
+ break;
+ default:
+ data = NULL;
+ }
+
+ return data;
+}
+
#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
struct eth_priv_t eth_priv_cfg[] = {
{
@@ -83,28 +108,15 @@
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
- int speed;
-
- speed = get_max_dev_speed();
- init_pll(&core_pll_config[speed]);
-
- init_pll(&pa_pll_config);
-
- speed = get_max_arm_speed();
- init_pll(&tetris_pll_config[speed]);
+ init_plls();
return 0;
}
#endif
#ifdef CONFIG_SPL_BUILD
-static struct pll_init_data spl_pll_config[] = {
- CORE_PLL_799,
- TETRIS_PLL_491,
-};
-
void spl_init_keystone_plls(void)
{
- init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
+ init_plls();
}
#endif
diff --git a/board/timll/devkit3250/Makefile b/board/timll/devkit3250/Makefile
index 4722986..74d5cd3 100644
--- a/board/timll/devkit3250/Makefile
+++ b/board/timll/devkit3250/Makefile
@@ -6,3 +6,4 @@
#
obj-y := devkit3250.o
+obj-$(CONFIG_SPL_BUILD) += devkit3250_spl.o
diff --git a/board/timll/devkit3250/devkit3250.c b/board/timll/devkit3250/devkit3250.c
index 6acc416..4b3c94e 100644
--- a/board/timll/devkit3250/devkit3250.c
+++ b/board/timll/devkit3250/devkit3250.c
@@ -1,23 +1,52 @@
/*
* Embest/Timll DevKit3250 board support
*
- * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
+ * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/sys_proto.h>
+#include <asm/arch/clk.h>
#include <asm/arch/cpu.h>
#include <asm/arch/emc.h>
+#include <asm/arch/wdt.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
static struct emc_regs *emc = (struct emc_regs *)EMC_BASE;
+static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
+static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE;
+
+void reset_periph(void)
+{
+ /* This function resets peripherals by triggering RESOUT_N */
+ setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
+ writel(WDTIM_MCTRL_RESFRC1, &wdt->mctrl);
+ udelay(300);
+
+ writel(0, &wdt->mctrl);
+ clrbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
+
+ /* Such a long delay is needed to initialize SMSC phy */
+ udelay(10000);
+}
int board_early_init_f(void)
{
lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
+ lpc32xx_i2c_init(1);
+ lpc32xx_i2c_init(2);
+ lpc32xx_ssp_init();
+ lpc32xx_mac_init();
+
+ /*
+ * nWP may be controlled by GPO19, but unpopulated by default R23
+ * makes no sense to configure this GPIO level, nWP is always high
+ */
+ lpc32xx_slc_nand_init();
return 0;
}
diff --git a/board/timll/devkit3250/devkit3250_spl.c b/board/timll/devkit3250/devkit3250_spl.c
new file mode 100644
index 0000000..bf52698
--- /dev/null
+++ b/board/timll/devkit3250/devkit3250_spl.c
@@ -0,0 +1,68 @@
+/*
+ * Timll DevKit3250 board support, SPL board configuration
+ *
+ * (C) Copyright 2015 Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/emc.h>
+#include <asm/arch-lpc32xx/gpio.h>
+#include <spl.h>
+
+static struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
+
+/*
+ * SDRAM K4S561632N-LC60 settings are selected in assumption that
+ * SDRAM clock may be set up to 166 MHz, however at the moment
+ * it is 104 MHz. Most delay values are converted to be a multiple of
+ * base clock, and precise pinned values are not needed here.
+ */
+struct emc_dram_settings dram_64mb = {
+ .cmddelay = 0x0001C000,
+ .config0 = 0x00005682,
+ .rascas0 = 0x00000302,
+ .rdconfig = 0x00000011, /* undocumented but crucial value */
+
+ .trp = 83333333,
+ .tras = 23809524,
+ .tsrex = 12500000,
+ .twr = 83000000, /* tWR = tRDL = 2 CLK */
+ .trc = 15384616,
+ .trfc = 15384616,
+ .txsr = 12500000,
+ .trrd = 1,
+ .tmrd = 1,
+ .tcdlr = 0,
+
+ .refresh = 130000, /* 800 clock cycles */
+
+ .mode = 0x00018000,
+ .emode = 0x02000000,
+};
+
+void spl_board_init(void)
+{
+ /* First of all silence buzzer controlled by GPO_20 */
+ writel((1 << 20), &gpio->p3_outp_clr);
+
+ lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
+ preloader_console_init();
+
+ ddr_init(&dram_64mb);
+
+ /*
+ * NAND initialization is done by nand_init(),
+ * here just enable NAND SLC clocks
+ */
+ lpc32xx_slc_nand_init();
+}
+
+u32 spl_boot_device(void)
+{
+ return BOOT_DEVICE_NAND;
+}
diff --git a/common/Kconfig b/common/Kconfig
index 40cd69e..88dc016 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -17,6 +17,13 @@
help
Backward compatibility.
+config SYS_PROMPT
+ string "Shell prompt"
+ default "=> "
+ help
+ This string is displayed in the command line to the left of the
+ cursor.
+
menu "Autoboot options"
config AUTOBOOT_KEYED
diff --git a/common/Makefile b/common/Makefile
index 6dc4c89..dc82433 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -251,7 +251,11 @@
obj-$(CONFIG_SPD_EEPROM) += ddr_spd.o
obj-$(CONFIG_HWCONFIG) += hwconfig.o
obj-$(CONFIG_BOUNCE_BUFFER) += bouncebuf.o
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SPL_SERIAL_SUPPORT) += console.o
+else
obj-y += console.o
+endif
obj-$(CONFIG_CROS_EC) += cros_ec.o
obj-y += dlmalloc.o
ifdef CONFIG_SYS_MALLOC_F_LEN
diff --git a/common/board_info.c b/common/board_info.c
index 6afe98e..bd5dcfa 100644
--- a/common/board_info.c
+++ b/common/board_info.c
@@ -17,7 +17,7 @@
*/
int show_board_info(void)
{
-#ifdef CONFIG_OF_CONTROL
+#if defined(CONFIG_OF_CONTROL) && !defined(CONFIG_CUSTOM_BOARDINFO)
DECLARE_GLOBAL_DATA_PTR;
const char *model;
diff --git a/common/cli_readline.c b/common/cli_readline.c
index 9a9fb35..c1476e4 100644
--- a/common/cli_readline.c
+++ b/common/cli_readline.c
@@ -597,7 +597,7 @@
puts(tab_seq + (col & 07));
col += 8 - (col & 07);
} else {
- char buf[2];
+ char __maybe_unused buf[2];
/*
* Echo input using puts() to force an
diff --git a/common/cli_simple.c b/common/cli_simple.c
index 6c65cc6..00a8d2f 100644
--- a/common/cli_simple.c
+++ b/common/cli_simple.c
@@ -68,7 +68,7 @@
/* 1 = waiting for '(' or '{' */
/* 2 = waiting for ')' or '}' */
/* 3 = waiting for ''' */
- char *output_start = output;
+ char __maybe_unused *output_start = output;
debug_parser("[PROCESS_MACROS] INPUT len %zd: \"%s\"\n", strlen(input),
input);
diff --git a/common/cmd_source.c b/common/cmd_source.c
index d2a881d..db7ab7e 100644
--- a/common/cmd_source.c
+++ b/common/cmd_source.c
@@ -33,7 +33,7 @@
#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
const image_header_t *hdr;
#endif
- ulong *data;
+ u32 *data;
int verify;
void *buf;
#if defined(CONFIG_FIT)
@@ -74,7 +74,7 @@
}
/* get length of script */
- data = (ulong *)image_get_data (hdr);
+ data = (u32 *)image_get_data (hdr);
if ((len = uimage_to_cpu (*data)) == 0) {
puts ("Empty Script\n");
@@ -128,7 +128,7 @@
return 1;
}
- data = (ulong *)fit_data;
+ data = (u32 *)fit_data;
len = (ulong)fit_len;
break;
#endif
diff --git a/common/image-fdt.c b/common/image-fdt.c
index 80e3e63..5180a03 100644
--- a/common/image-fdt.c
+++ b/common/image-fdt.c
@@ -492,7 +492,8 @@
}
}
if (IMAGE_OF_SYSTEM_SETUP) {
- if (ft_system_setup(blob, gd->bd)) {
+ fdt_ret = ft_system_setup(blob, gd->bd);
+ if (fdt_ret) {
printf("ERROR: system-specific fdt fixup failed: %s\n",
fdt_strerror(fdt_ret));
goto err;
diff --git a/common/image.c b/common/image.c
index 9efacf8..ca721c5 100644
--- a/common/image.c
+++ b/common/image.c
@@ -54,6 +54,10 @@
#include <u-boot/md5.h>
#include <time.h>
#include <image.h>
+
+#ifndef __maybe_unused
+# define __maybe_unused /* unimplemented */
+#endif
#endif /* !USE_HOSTCC*/
#include <u-boot/crc.h>
@@ -274,7 +278,7 @@
static void image_print_type(const image_header_t *hdr)
{
- const char *os, *arch, *type, *comp;
+ const char __maybe_unused *os, *arch, *type, *comp;
os = genimg_get_os_name(image_get_os(hdr));
arch = genimg_get_arch_name(image_get_arch(hdr));
@@ -299,7 +303,7 @@
void image_print_contents(const void *ptr)
{
const image_header_t *hdr = (const image_header_t *)ptr;
- const char *p;
+ const char __maybe_unused *p;
p = IMAGE_INDENT_STRING;
printf("%sImage Name: %.*s\n", p, IH_NMLEN, image_get_name(hdr));
@@ -902,6 +906,7 @@
if (argc >= 2)
select = argv[1];
+
/*
* Look for a '-' which indicates to ignore the
* ramdisk argument
@@ -1001,6 +1006,12 @@
images->fit_noffset_rd = rd_noffset;
break;
#endif
+#ifdef CONFIG_ANDROID_BOOT_IMAGE
+ case IMAGE_FORMAT_ANDROID:
+ android_image_get_ramdisk((void *)images->os.start,
+ &rd_data, &rd_len);
+ break;
+#endif
default:
#ifdef CONFIG_SUPPORT_RAW_INITRD
end = NULL;
@@ -1031,16 +1042,7 @@
(ulong)images->legacy_hdr_os);
image_multi_getimg(images->legacy_hdr_os, 1, &rd_data, &rd_len);
- }
-#ifdef CONFIG_ANDROID_BOOT_IMAGE
- else if ((genimg_get_format((void *)images->os.start)
- == IMAGE_FORMAT_ANDROID) &&
- (!android_image_get_ramdisk((void *)images->os.start,
- &rd_data, &rd_len))) {
- /* empty */
- }
-#endif
- else {
+ } else {
/*
* no initrd image
*/
diff --git a/common/lcd.c b/common/lcd.c
index 5a52fe4..d29308a 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -234,8 +234,8 @@
lcd_logo();
#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO)
addr = (ulong)lcd_base + BMP_LOGO_HEIGHT * lcd_line_length;
- lcd_init_console((void *)addr, panel_info.vl_row,
- panel_info.vl_col, panel_info.vl_rot);
+ lcd_init_console((void *)addr, panel_info.vl_col,
+ panel_info.vl_row, panel_info.vl_rot);
#endif
lcd_sync();
}
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index 494f683..ce58c58 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -44,7 +44,7 @@
/* Read the header too to avoid extra memcpy */
count = mmc->block_dev.block_read(0, sector, image_size_sectors,
- (void *)spl_image.load_addr);
+ (void *)(ulong)spl_image.load_addr);
debug("read %x sectors to %x\n", image_size_sectors,
spl_image.load_addr);
diff --git a/configs/M5208EVBE_defconfig b/configs/M5208EVBE_defconfig
index 58de96b..6a46194 100644
--- a/configs/M5208EVBE_defconfig
+++ b/configs/M5208EVBE_defconfig
@@ -1,3 +1,4 @@
CONFIG_M68K=y
CONFIG_TARGET_M5208EVBE=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="-> "
diff --git a/configs/M52277EVB_defconfig b/configs/M52277EVB_defconfig
index 6a2d175..608edc5 100644
--- a/configs/M52277EVB_defconfig
+++ b/configs/M52277EVB_defconfig
@@ -5,3 +5,4 @@
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="-> "
diff --git a/configs/M5235EVB_defconfig b/configs/M5235EVB_defconfig
index 3292cff..e9c2b7c 100644
--- a/configs/M5235EVB_defconfig
+++ b/configs/M5235EVB_defconfig
@@ -4,3 +4,4 @@
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="-> "
diff --git a/configs/M5272C3_defconfig b/configs/M5272C3_defconfig
index 23d5468..6ad4e13 100644
--- a/configs/M5272C3_defconfig
+++ b/configs/M5272C3_defconfig
@@ -3,3 +3,4 @@
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="-> "
diff --git a/configs/M5275EVB_defconfig b/configs/M5275EVB_defconfig
index f051bf1..b29021b 100644
--- a/configs/M5275EVB_defconfig
+++ b/configs/M5275EVB_defconfig
@@ -3,3 +3,4 @@
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="-> "
diff --git a/configs/M5282EVB_defconfig b/configs/M5282EVB_defconfig
index 6c130e8..322ee9a 100644
--- a/configs/M5282EVB_defconfig
+++ b/configs/M5282EVB_defconfig
@@ -3,3 +3,4 @@
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="-> "
diff --git a/configs/M53017EVB_defconfig b/configs/M53017EVB_defconfig
index 1f5bc86..3e72290 100644
--- a/configs/M53017EVB_defconfig
+++ b/configs/M53017EVB_defconfig
@@ -1,3 +1,4 @@
CONFIG_M68K=y
CONFIG_TARGET_M53017EVB=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="-> "
diff --git a/configs/M5329AFEE_defconfig b/configs/M5329AFEE_defconfig
index 02af3a4..1d2bb81 100644
--- a/configs/M5329AFEE_defconfig
+++ b/configs/M5329AFEE_defconfig
@@ -2,3 +2,4 @@
CONFIG_TARGET_M5329EVB=y
CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=0"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="-> "
diff --git a/configs/M5329BFEE_defconfig b/configs/M5329BFEE_defconfig
index f757a35..915734c 100644
--- a/configs/M5329BFEE_defconfig
+++ b/configs/M5329BFEE_defconfig
@@ -2,3 +2,4 @@
CONFIG_TARGET_M5329EVB=y
CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="-> "
diff --git a/configs/M5373EVB_defconfig b/configs/M5373EVB_defconfig
index 304ca48..eb7a96a 100644
--- a/configs/M5373EVB_defconfig
+++ b/configs/M5373EVB_defconfig
@@ -2,3 +2,4 @@
CONFIG_TARGET_M5373EVB=y
CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="-> "
diff --git a/configs/M54418TWR_defconfig b/configs/M54418TWR_defconfig
index 9a93b3b..a5c35d1 100644
--- a/configs/M54418TWR_defconfig
+++ b/configs/M54418TWR_defconfig
@@ -7,3 +7,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="-> "
diff --git a/configs/M54418TWR_nand_mii_defconfig b/configs/M54418TWR_nand_mii_defconfig
index c194ea7..20eadcf 100644
--- a/configs/M54418TWR_nand_mii_defconfig
+++ b/configs/M54418TWR_nand_mii_defconfig
@@ -7,3 +7,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="-> "
diff --git a/configs/M54418TWR_nand_rmii_defconfig b/configs/M54418TWR_nand_rmii_defconfig
index 4ee35ff..d47127c 100644
--- a/configs/M54418TWR_nand_rmii_defconfig
+++ b/configs/M54418TWR_nand_rmii_defconfig
@@ -7,3 +7,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="-> "
diff --git a/configs/M54418TWR_nand_rmii_lowfreq_defconfig b/configs/M54418TWR_nand_rmii_lowfreq_defconfig
index 4c4b70a..700745d 100644
--- a/configs/M54418TWR_nand_rmii_lowfreq_defconfig
+++ b/configs/M54418TWR_nand_rmii_lowfreq_defconfig
@@ -7,3 +7,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="-> "
diff --git a/configs/M54418TWR_serial_mii_defconfig b/configs/M54418TWR_serial_mii_defconfig
index 3be102c..4450084 100644
--- a/configs/M54418TWR_serial_mii_defconfig
+++ b/configs/M54418TWR_serial_mii_defconfig
@@ -7,3 +7,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="-> "
diff --git a/configs/M54418TWR_serial_rmii_defconfig b/configs/M54418TWR_serial_rmii_defconfig
index 9a93b3b..a5c35d1 100644
--- a/configs/M54418TWR_serial_rmii_defconfig
+++ b/configs/M54418TWR_serial_rmii_defconfig
@@ -7,3 +7,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="-> "
diff --git a/configs/M54451EVB_defconfig b/configs/M54451EVB_defconfig
index b35bb81..0b446b8 100644
--- a/configs/M54451EVB_defconfig
+++ b/configs/M54451EVB_defconfig
@@ -5,3 +5,4 @@
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="-> "
diff --git a/configs/M54455EVB_defconfig b/configs/M54455EVB_defconfig
index cb56586..c7a0164 100644
--- a/configs/M54455EVB_defconfig
+++ b/configs/M54455EVB_defconfig
@@ -5,3 +5,4 @@
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="-> "
diff --git a/configs/M5475AFE_defconfig b/configs/M5475AFE_defconfig
index 343f52f..b29d1a6 100644
--- a/configs/M5475AFE_defconfig
+++ b/configs/M5475AFE_defconfig
@@ -2,3 +2,4 @@
CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="-> "
diff --git a/configs/M5475BFE_defconfig b/configs/M5475BFE_defconfig
index c9667da..e62fbf6 100644
--- a/configs/M5475BFE_defconfig
+++ b/configs/M5475BFE_defconfig
@@ -2,3 +2,4 @@
CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="-> "
diff --git a/configs/M5475CFE_defconfig b/configs/M5475CFE_defconfig
index c1a9558..195b4e3 100644
--- a/configs/M5475CFE_defconfig
+++ b/configs/M5475CFE_defconfig
@@ -2,3 +2,4 @@
CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="-> "
diff --git a/configs/M5475DFE_defconfig b/configs/M5475DFE_defconfig
index d879894..314ced6 100644
--- a/configs/M5475DFE_defconfig
+++ b/configs/M5475DFE_defconfig
@@ -2,3 +2,4 @@
CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="-> "
diff --git a/configs/M5475EFE_defconfig b/configs/M5475EFE_defconfig
index 9b677ee..279808f 100644
--- a/configs/M5475EFE_defconfig
+++ b/configs/M5475EFE_defconfig
@@ -2,3 +2,4 @@
CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="-> "
diff --git a/configs/M5475FFE_defconfig b/configs/M5475FFE_defconfig
index 4989b00..a00100e 100644
--- a/configs/M5475FFE_defconfig
+++ b/configs/M5475FFE_defconfig
@@ -2,3 +2,4 @@
CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="-> "
diff --git a/configs/M5475GFE_defconfig b/configs/M5475GFE_defconfig
index 31df40e..1ea82a7 100644
--- a/configs/M5475GFE_defconfig
+++ b/configs/M5475GFE_defconfig
@@ -2,3 +2,4 @@
CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=4,SYS_DRAMSZ=64"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="-> "
diff --git a/configs/M5485AFE_defconfig b/configs/M5485AFE_defconfig
index 5381b74..70cfa8f 100644
--- a/configs/M5485AFE_defconfig
+++ b/configs/M5485AFE_defconfig
@@ -2,3 +2,4 @@
CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="-> "
diff --git a/configs/M5485BFE_defconfig b/configs/M5485BFE_defconfig
index 36dcccf..377b87f 100644
--- a/configs/M5485BFE_defconfig
+++ b/configs/M5485BFE_defconfig
@@ -2,3 +2,4 @@
CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="-> "
diff --git a/configs/M5485CFE_defconfig b/configs/M5485CFE_defconfig
index e5cc1e1..faa0196 100644
--- a/configs/M5485CFE_defconfig
+++ b/configs/M5485CFE_defconfig
@@ -2,3 +2,4 @@
CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="-> "
diff --git a/configs/M5485DFE_defconfig b/configs/M5485DFE_defconfig
index fdf667a..71a028f 100644
--- a/configs/M5485DFE_defconfig
+++ b/configs/M5485DFE_defconfig
@@ -2,3 +2,4 @@
CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="-> "
diff --git a/configs/M5485EFE_defconfig b/configs/M5485EFE_defconfig
index a5933f2..784803e 100644
--- a/configs/M5485EFE_defconfig
+++ b/configs/M5485EFE_defconfig
@@ -2,3 +2,4 @@
CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="-> "
diff --git a/configs/M5485FFE_defconfig b/configs/M5485FFE_defconfig
index 116c5cc..8a831e3 100644
--- a/configs/M5485FFE_defconfig
+++ b/configs/M5485FFE_defconfig
@@ -2,3 +2,4 @@
CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="-> "
diff --git a/configs/M5485GFE_defconfig b/configs/M5485GFE_defconfig
index fd5fc1a..00c7479 100644
--- a/configs/M5485GFE_defconfig
+++ b/configs/M5485GFE_defconfig
@@ -2,3 +2,4 @@
CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=4,SYS_DRAMSZ=64"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="-> "
diff --git a/configs/M5485HFE_defconfig b/configs/M5485HFE_defconfig
index 6e2768c..887bd4d 100644
--- a/configs/M5485HFE_defconfig
+++ b/configs/M5485HFE_defconfig
@@ -2,3 +2,4 @@
CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="-> "
diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig
index 7a43fa0..4578b32 100644
--- a/configs/MPC8349ITXGP_defconfig
+++ b/configs/MPC8349ITXGP_defconfig
@@ -3,3 +3,4 @@
CONFIG_TARGET_MPC8349ITX=y
CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITXGP,SYS_TEXT_BASE=0xFE000000"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="MPC8349E-mITX-GP> "
diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig
index f74d42c..c5fbeb9 100644
--- a/configs/MPC8349ITX_LOWBOOT_defconfig
+++ b/configs/MPC8349ITX_LOWBOOT_defconfig
@@ -3,3 +3,4 @@
CONFIG_TARGET_MPC8349ITX=y
CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX,SYS_TEXT_BASE=0xFE000000"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="MPC8349E-mITX> "
diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig
index 84c117c..a895c53 100644
--- a/configs/MPC8349ITX_defconfig
+++ b/configs/MPC8349ITX_defconfig
@@ -3,3 +3,4 @@
CONFIG_TARGET_MPC8349ITX=y
CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="MPC8349E-mITX> "
diff --git a/configs/PATI_defconfig b/configs/PATI_defconfig
index da8525e..6c1bf17 100644
--- a/configs/PATI_defconfig
+++ b/configs/PATI_defconfig
@@ -13,3 +13,4 @@
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_PROMPT="pati=> "
diff --git a/configs/UCP1020_defconfig b/configs/UCP1020_defconfig
index 010b15f..cada7bb 100644
--- a/configs/UCP1020_defconfig
+++ b/configs/UCP1020_defconfig
@@ -5,3 +5,4 @@
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc>\" to stop\n"
CONFIG_AUTOBOOT_STOP_STR="\x1b"
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="B$ "
diff --git a/configs/VCMA9_defconfig b/configs/VCMA9_defconfig
index 8885f1a..e9b28a8 100644
--- a/configs/VCMA9_defconfig
+++ b/configs/VCMA9_defconfig
@@ -1,3 +1,4 @@
CONFIG_ARM=y
CONFIG_TARGET_VCMA9=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="VCMA9 # "
diff --git a/configs/ac14xx_defconfig b/configs/ac14xx_defconfig
index 37fb0e0..238630e 100644
--- a/configs/ac14xx_defconfig
+++ b/configs/ac14xx_defconfig
@@ -2,3 +2,4 @@
CONFIG_MPC512X=y
CONFIG_TARGET_AC14XX=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="ac14xx> "
diff --git a/configs/adp-ag101_defconfig b/configs/adp-ag101_defconfig
index e550f71..ac1dcaa 100644
--- a/configs/adp-ag101_defconfig
+++ b/configs/adp-ag101_defconfig
@@ -1,3 +1,4 @@
CONFIG_NDS32=y
CONFIG_TARGET_ADP_AG101=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="NDS32 # "
diff --git a/configs/adp-ag101p_defconfig b/configs/adp-ag101p_defconfig
index 740cb57..92aa0be 100644
--- a/configs/adp-ag101p_defconfig
+++ b/configs/adp-ag101p_defconfig
@@ -1,3 +1,4 @@
CONFIG_NDS32=y
CONFIG_TARGET_ADP_AG101P=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="NDS32 # "
diff --git a/configs/adp-ag102_defconfig b/configs/adp-ag102_defconfig
index 721f61d..1bef350 100644
--- a/configs/adp-ag102_defconfig
+++ b/configs/adp-ag102_defconfig
@@ -3,3 +3,4 @@
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="NDS32 # "
diff --git a/configs/am335x_gp_evm_defconfig b/configs/am335x_gp_evm_defconfig
new file mode 100644
index 0000000..62d3b6b
--- /dev/null
+++ b/configs/am335x_gp_evm_defconfig
@@ -0,0 +1,14 @@
+CONFIG_ARM=y
+CONFIG_TARGET_AM335X_EVM=y
+CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SYS_EXTRA_OPTIONS="NAND"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_DISABLE_OF_CONTROL=y
+CONFIG_SPI_FLASH=y
+CONFIG_RSA=y
diff --git a/configs/am3517_crane_defconfig b/configs/am3517_crane_defconfig
index a44ffe7..806dc3a 100644
--- a/configs/am3517_crane_defconfig
+++ b/configs/am3517_crane_defconfig
@@ -9,3 +9,4 @@
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_PROMPT="AM3517_CRANE # "
diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig
index c72d29e..95b6754 100644
--- a/configs/am3517_evm_defconfig
+++ b/configs/am3517_evm_defconfig
@@ -8,3 +8,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="AM3517_EVM # "
diff --git a/configs/amcore_defconfig b/configs/amcore_defconfig
index 47c4f3d..dc16d5b 100644
--- a/configs/amcore_defconfig
+++ b/configs/amcore_defconfig
@@ -6,3 +6,4 @@
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_PROMPT="amcore $ "
diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig
index fa9f365..c0bc3c5 100644
--- a/configs/apalis_t30_defconfig
+++ b/configs/apalis_t30_defconfig
@@ -12,3 +12,4 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_PROMPT="Apalis T30 # "
diff --git a/configs/apf27_defconfig b/configs/apf27_defconfig
index 854a2b7..4503235 100644
--- a/configs/apf27_defconfig
+++ b/configs/apf27_defconfig
@@ -3,3 +3,4 @@
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_SYS_PROMPT="BIOS> "
diff --git a/configs/arcangel4_defconfig b/configs/arcangel4_defconfig
index 5683b81..cd9aafd 100644
--- a/configs/arcangel4_defconfig
+++ b/configs/arcangel4_defconfig
@@ -11,3 +11,4 @@
CONFIG_DM=y
CONFIG_DM_SERIAL=y
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_PROMPT="arcangel4# "
diff --git a/configs/arndale_defconfig b/configs/arndale_defconfig
index ebac9ad..1f94ff0 100644
--- a/configs/arndale_defconfig
+++ b/configs/arndale_defconfig
@@ -15,3 +15,4 @@
CONFIG_DM_USB=y
CONFIG_DM_I2C=y
CONFIG_DM_I2C_COMPAT=y
+CONFIG_SYS_PROMPT="ARNDALE # "
diff --git a/configs/astro_mcf5373l_defconfig b/configs/astro_mcf5373l_defconfig
index f394f4d..8676120 100644
--- a/configs/astro_mcf5373l_defconfig
+++ b/configs/astro_mcf5373l_defconfig
@@ -3,3 +3,4 @@
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_PROMPT="URMEL > "
diff --git a/configs/at91rm9200ek_defconfig b/configs/at91rm9200ek_defconfig
index 74d4f3a..10df5f8 100644
--- a/configs/at91rm9200ek_defconfig
+++ b/configs/at91rm9200ek_defconfig
@@ -3,3 +3,4 @@
CONFIG_TARGET_AT91RM9200EK=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/at91rm9200ek_ram_defconfig b/configs/at91rm9200ek_ram_defconfig
index f499453..2765e9d 100644
--- a/configs/at91rm9200ek_ram_defconfig
+++ b/configs/at91rm9200ek_ram_defconfig
@@ -4,3 +4,4 @@
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT"
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/at91sam9260ek_dataflash_cs0_defconfig b/configs/at91sam9260ek_dataflash_cs0_defconfig
index 96c5eee..9909bc8 100644
--- a/configs/at91sam9260ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9260ek_dataflash_cs0_defconfig
@@ -9,3 +9,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/at91sam9260ek_dataflash_cs1_defconfig b/configs/at91sam9260ek_dataflash_cs1_defconfig
index 6330c3e..8fdbd88 100644
--- a/configs/at91sam9260ek_dataflash_cs1_defconfig
+++ b/configs/at91sam9260ek_dataflash_cs1_defconfig
@@ -9,3 +9,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/at91sam9260ek_nandflash_defconfig b/configs/at91sam9260ek_nandflash_defconfig
index ae2defd..e4fc8d7 100644
--- a/configs/at91sam9260ek_nandflash_defconfig
+++ b/configs/at91sam9260ek_nandflash_defconfig
@@ -9,3 +9,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/at91sam9261ek_dataflash_cs0_defconfig b/configs/at91sam9261ek_dataflash_cs0_defconfig
index 838b235..e182f70 100644
--- a/configs/at91sam9261ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9261ek_dataflash_cs0_defconfig
@@ -9,3 +9,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/at91sam9261ek_dataflash_cs3_defconfig b/configs/at91sam9261ek_dataflash_cs3_defconfig
index 6104479..b3a35dd 100644
--- a/configs/at91sam9261ek_dataflash_cs3_defconfig
+++ b/configs/at91sam9261ek_dataflash_cs3_defconfig
@@ -9,3 +9,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/at91sam9261ek_nandflash_defconfig b/configs/at91sam9261ek_nandflash_defconfig
index 4015c9f..58aa38f 100644
--- a/configs/at91sam9261ek_nandflash_defconfig
+++ b/configs/at91sam9261ek_nandflash_defconfig
@@ -9,3 +9,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/at91sam9263ek_dataflash_cs0_defconfig b/configs/at91sam9263ek_dataflash_cs0_defconfig
index d9003ff..82e1b86 100644
--- a/configs/at91sam9263ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9263ek_dataflash_cs0_defconfig
@@ -9,3 +9,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/at91sam9263ek_dataflash_defconfig b/configs/at91sam9263ek_dataflash_defconfig
index d9003ff..82e1b86 100644
--- a/configs/at91sam9263ek_dataflash_defconfig
+++ b/configs/at91sam9263ek_dataflash_defconfig
@@ -9,3 +9,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/at91sam9263ek_nandflash_defconfig b/configs/at91sam9263ek_nandflash_defconfig
index 600c5dd..bac882e 100644
--- a/configs/at91sam9263ek_nandflash_defconfig
+++ b/configs/at91sam9263ek_nandflash_defconfig
@@ -9,3 +9,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/at91sam9263ek_norflash_boot_defconfig b/configs/at91sam9263ek_norflash_boot_defconfig
index 2e34b79..75f0ec6 100644
--- a/configs/at91sam9263ek_norflash_boot_defconfig
+++ b/configs/at91sam9263ek_norflash_boot_defconfig
@@ -9,3 +9,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/at91sam9263ek_norflash_defconfig b/configs/at91sam9263ek_norflash_defconfig
index f72ed85..5bcdab0 100644
--- a/configs/at91sam9263ek_norflash_defconfig
+++ b/configs/at91sam9263ek_norflash_defconfig
@@ -9,3 +9,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/at91sam9g10ek_dataflash_cs0_defconfig b/configs/at91sam9g10ek_dataflash_cs0_defconfig
index 5f8d803..80e6a8a 100644
--- a/configs/at91sam9g10ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9g10ek_dataflash_cs0_defconfig
@@ -9,3 +9,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/at91sam9g10ek_dataflash_cs3_defconfig b/configs/at91sam9g10ek_dataflash_cs3_defconfig
index 3ed763e..e6c9f61 100644
--- a/configs/at91sam9g10ek_dataflash_cs3_defconfig
+++ b/configs/at91sam9g10ek_dataflash_cs3_defconfig
@@ -9,3 +9,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/at91sam9g10ek_nandflash_defconfig b/configs/at91sam9g10ek_nandflash_defconfig
index c27e39a..0adaf11 100644
--- a/configs/at91sam9g10ek_nandflash_defconfig
+++ b/configs/at91sam9g10ek_nandflash_defconfig
@@ -9,3 +9,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/at91sam9g20ek_2mmc_defconfig b/configs/at91sam9g20ek_2mmc_defconfig
index d58de8e..40cd6b1 100644
--- a/configs/at91sam9g20ek_2mmc_defconfig
+++ b/configs/at91sam9g20ek_2mmc_defconfig
@@ -9,3 +9,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/at91sam9g20ek_2mmc_nandflash_defconfig b/configs/at91sam9g20ek_2mmc_nandflash_defconfig
index 4b28839..6f59305 100644
--- a/configs/at91sam9g20ek_2mmc_nandflash_defconfig
+++ b/configs/at91sam9g20ek_2mmc_nandflash_defconfig
@@ -9,3 +9,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/at91sam9g20ek_dataflash_cs0_defconfig b/configs/at91sam9g20ek_dataflash_cs0_defconfig
index ee86dad..b63c6d6 100644
--- a/configs/at91sam9g20ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9g20ek_dataflash_cs0_defconfig
@@ -9,3 +9,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/at91sam9g20ek_dataflash_cs1_defconfig b/configs/at91sam9g20ek_dataflash_cs1_defconfig
index 39d4b09..aad9c1e 100644
--- a/configs/at91sam9g20ek_dataflash_cs1_defconfig
+++ b/configs/at91sam9g20ek_dataflash_cs1_defconfig
@@ -9,3 +9,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/at91sam9g20ek_nandflash_defconfig b/configs/at91sam9g20ek_nandflash_defconfig
index d636485..f247084 100644
--- a/configs/at91sam9g20ek_nandflash_defconfig
+++ b/configs/at91sam9g20ek_nandflash_defconfig
@@ -9,3 +9,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/at91sam9m10g45ek_mmc_defconfig b/configs/at91sam9m10g45ek_mmc_defconfig
index 1472d20..f88b48b 100644
--- a/configs/at91sam9m10g45ek_mmc_defconfig
+++ b/configs/at91sam9m10g45ek_mmc_defconfig
@@ -10,3 +10,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/at91sam9m10g45ek_nandflash_defconfig b/configs/at91sam9m10g45ek_nandflash_defconfig
index 526419c..7675f52 100644
--- a/configs/at91sam9m10g45ek_nandflash_defconfig
+++ b/configs/at91sam9m10g45ek_nandflash_defconfig
@@ -10,3 +10,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/at91sam9n12ek_mmc_defconfig b/configs/at91sam9n12ek_mmc_defconfig
index c549baf..1702a32 100644
--- a/configs/at91sam9n12ek_mmc_defconfig
+++ b/configs/at91sam9n12ek_mmc_defconfig
@@ -7,3 +7,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/at91sam9n12ek_nandflash_defconfig b/configs/at91sam9n12ek_nandflash_defconfig
index 756db2a..9f87469 100644
--- a/configs/at91sam9n12ek_nandflash_defconfig
+++ b/configs/at91sam9n12ek_nandflash_defconfig
@@ -8,3 +8,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig
index 0430de9..a7d0581 100644
--- a/configs/at91sam9n12ek_spiflash_defconfig
+++ b/configs/at91sam9n12ek_spiflash_defconfig
@@ -8,3 +8,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/at91sam9rlek_dataflash_defconfig b/configs/at91sam9rlek_dataflash_defconfig
index c555caa..ed2f5d2 100644
--- a/configs/at91sam9rlek_dataflash_defconfig
+++ b/configs/at91sam9rlek_dataflash_defconfig
@@ -12,3 +12,4 @@
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/at91sam9rlek_mmc_defconfig b/configs/at91sam9rlek_mmc_defconfig
index 5cb5655..760cf92 100644
--- a/configs/at91sam9rlek_mmc_defconfig
+++ b/configs/at91sam9rlek_mmc_defconfig
@@ -12,3 +12,4 @@
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/at91sam9rlek_nandflash_defconfig b/configs/at91sam9rlek_nandflash_defconfig
index 3e3528e..191a261 100644
--- a/configs/at91sam9rlek_nandflash_defconfig
+++ b/configs/at91sam9rlek_nandflash_defconfig
@@ -12,3 +12,4 @@
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/at91sam9x5ek_dataflash_defconfig b/configs/at91sam9x5ek_dataflash_defconfig
index c757fc4..38607d0 100644
--- a/configs/at91sam9x5ek_dataflash_defconfig
+++ b/configs/at91sam9x5ek_dataflash_defconfig
@@ -8,3 +8,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/at91sam9x5ek_mmc_defconfig b/configs/at91sam9x5ek_mmc_defconfig
index 82e67f3..8776627 100644
--- a/configs/at91sam9x5ek_mmc_defconfig
+++ b/configs/at91sam9x5ek_mmc_defconfig
@@ -8,3 +8,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/at91sam9x5ek_nandflash_defconfig b/configs/at91sam9x5ek_nandflash_defconfig
index b45d8d0..cedc560 100644
--- a/configs/at91sam9x5ek_nandflash_defconfig
+++ b/configs/at91sam9x5ek_nandflash_defconfig
@@ -9,3 +9,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig
index f33a2fd..3896300 100644
--- a/configs/at91sam9x5ek_spiflash_defconfig
+++ b/configs/at91sam9x5ek_spiflash_defconfig
@@ -9,3 +9,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/at91sam9xeek_dataflash_cs0_defconfig b/configs/at91sam9xeek_dataflash_cs0_defconfig
index 585d564..fbdb564 100644
--- a/configs/at91sam9xeek_dataflash_cs0_defconfig
+++ b/configs/at91sam9xeek_dataflash_cs0_defconfig
@@ -9,3 +9,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/at91sam9xeek_dataflash_cs1_defconfig b/configs/at91sam9xeek_dataflash_cs1_defconfig
index 1c38777..4f0cc11 100644
--- a/configs/at91sam9xeek_dataflash_cs1_defconfig
+++ b/configs/at91sam9xeek_dataflash_cs1_defconfig
@@ -9,3 +9,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/at91sam9xeek_nandflash_defconfig b/configs/at91sam9xeek_nandflash_defconfig
index 5e9a080..3dde55c 100644
--- a/configs/at91sam9xeek_nandflash_defconfig
+++ b/configs/at91sam9xeek_nandflash_defconfig
@@ -9,3 +9,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/atngw100_defconfig b/configs/atngw100_defconfig
index 0f5be56..51facf7 100644
--- a/configs/atngw100_defconfig
+++ b/configs/atngw100_defconfig
@@ -9,3 +9,4 @@
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/atngw100mkii_defconfig b/configs/atngw100mkii_defconfig
index b4d8d1c..b7099f5 100644
--- a/configs/atngw100mkii_defconfig
+++ b/configs/atngw100mkii_defconfig
@@ -8,3 +8,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/atstk1002_defconfig b/configs/atstk1002_defconfig
index bb0406e..78e2256 100644
--- a/configs/atstk1002_defconfig
+++ b/configs/atstk1002_defconfig
@@ -8,3 +8,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig
index 04aec0b..9a6cef3 100644
--- a/configs/axs101_defconfig
+++ b/configs/axs101_defconfig
@@ -10,3 +10,4 @@
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_PROMPT="AXS# "
diff --git a/configs/beaver_defconfig b/configs/beaver_defconfig
index ad74b85..02e19d2 100644
--- a/configs/beaver_defconfig
+++ b/configs/beaver_defconfig
@@ -14,3 +14,4 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_PROMPT="Tegra30 (Beaver) # "
diff --git a/configs/bf537-minotaur_defconfig b/configs/bf537-minotaur_defconfig
index 57e9a24..212f2bb 100644
--- a/configs/bf537-minotaur_defconfig
+++ b/configs/bf537-minotaur_defconfig
@@ -5,3 +5,4 @@
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="minotaur> "
diff --git a/configs/bf537-srv1_defconfig b/configs/bf537-srv1_defconfig
index 51022d8..52abf99 100644
--- a/configs/bf537-srv1_defconfig
+++ b/configs/bf537-srv1_defconfig
@@ -5,3 +5,4 @@
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="srv1> "
diff --git a/configs/bf561-acvilon_defconfig b/configs/bf561-acvilon_defconfig
index 897e44f..1409901 100644
--- a/configs/bf561-acvilon_defconfig
+++ b/configs/bf561-acvilon_defconfig
@@ -6,3 +6,4 @@
CONFIG_SPI_FLASH=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_LIB_RAND=y
+CONFIG_SYS_PROMPT="Acvilon> "
diff --git a/configs/br4_defconfig b/configs/br4_defconfig
index b129899..540dbef 100644
--- a/configs/br4_defconfig
+++ b/configs/br4_defconfig
@@ -6,3 +6,4 @@
CONFIG_SPI_FLASH=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_LIB_RAND=y
+CONFIG_SYS_PROMPT="br4>"
diff --git a/configs/cairo_defconfig b/configs/cairo_defconfig
index b837de3..756457c 100644
--- a/configs/cairo_defconfig
+++ b/configs/cairo_defconfig
@@ -7,3 +7,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_NET is not set
+CONFIG_SYS_PROMPT="Cairo # "
diff --git a/configs/calimain_defconfig b/configs/calimain_defconfig
index 35f73e3..4d952cd 100644
--- a/configs/calimain_defconfig
+++ b/configs/calimain_defconfig
@@ -4,3 +4,4 @@
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR="\x0b"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="Calimain > "
diff --git a/configs/cam_enc_4xx_defconfig b/configs/cam_enc_4xx_defconfig
index f7f6f12..a67bf0e 100644
--- a/configs/cam_enc_4xx_defconfig
+++ b/configs/cam_enc_4xx_defconfig
@@ -7,3 +7,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="cam_enc_4xx> "
diff --git a/configs/cardhu_defconfig b/configs/cardhu_defconfig
index c0e98a5..5c298d7 100644
--- a/configs/cardhu_defconfig
+++ b/configs/cardhu_defconfig
@@ -14,3 +14,4 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_PROMPT="Tegra30 (Cardhu) # "
diff --git a/configs/cgtqmx6qeval_defconfig b/configs/cgtqmx6qeval_defconfig
index 6fd29a0..af322bc 100644
--- a/configs/cgtqmx6qeval_defconfig
+++ b/configs/cgtqmx6qeval_defconfig
@@ -7,3 +7,4 @@
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="CGT-QMX6-Quad U-Boot > "
diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig
index 2aba359..66fc382 100644
--- a/configs/cm_fx6_defconfig
+++ b/configs/cm_fx6_defconfig
@@ -30,3 +30,4 @@
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
+CONFIG_SYS_PROMPT="CM-FX6 # "
diff --git a/configs/cm_t335_defconfig b/configs/cm_t335_defconfig
index 9ebd327..4f4bd0b 100644
--- a/configs/cm_t335_defconfig
+++ b/configs/cm_t335_defconfig
@@ -4,3 +4,4 @@
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="CM-T335 # "
diff --git a/configs/cm_t3517_defconfig b/configs/cm_t3517_defconfig
index 57b44ba..1eb4250 100644
--- a/configs/cm_t3517_defconfig
+++ b/configs/cm_t3517_defconfig
@@ -5,3 +5,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="CM-T3517 # "
diff --git a/configs/cm_t35_defconfig b/configs/cm_t35_defconfig
index c8dc124..99dd2f4 100644
--- a/configs/cm_t35_defconfig
+++ b/configs/cm_t35_defconfig
@@ -6,3 +6,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="CM-T3x # "
diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig
new file mode 100644
index 0000000..19ac18a
--- /dev/null
+++ b/configs/cm_t43_defconfig
@@ -0,0 +1,10 @@
+CONFIG_ARM=y
+CONFIG_TARGET_CM_T43=y
+CONFIG_SPL=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
diff --git a/configs/cm_t54_defconfig b/configs/cm_t54_defconfig
index af7c880..fc72ffa 100644
--- a/configs/cm_t54_defconfig
+++ b/configs/cm_t54_defconfig
@@ -6,3 +6,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_PROMPT="CM-T54 # "
diff --git a/configs/cobra5272_defconfig b/configs/cobra5272_defconfig
index 2ccb80c..77ad34d 100644
--- a/configs/cobra5272_defconfig
+++ b/configs/cobra5272_defconfig
@@ -3,3 +3,4 @@
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="COBRA > "
diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig
index 4e1369b..0d28b06 100644
--- a/configs/colibri_t20_defconfig
+++ b/configs/colibri_t20_defconfig
@@ -12,3 +12,4 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_PROMPT="Colibri T20 # "
diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig
index 45cf20a..d1ed09d 100644
--- a/configs/colibri_t30_defconfig
+++ b/configs/colibri_t30_defconfig
@@ -12,3 +12,4 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_PROMPT="Colibri T30 # "
diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig
index ffb3b4f..74af563 100644
--- a/configs/colibri_vf_defconfig
+++ b/configs/colibri_vf_defconfig
@@ -6,3 +6,4 @@
CONFIG_DM=y
CONFIG_NAND_VF610_NFC=y
CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y
+CONFIG_SYS_PROMPT="Colibri VFxx # "
diff --git a/configs/colibri_vf_dtb_defconfig b/configs/colibri_vf_dtb_defconfig
index 49f2105..54c3f2d 100644
--- a/configs/colibri_vf_dtb_defconfig
+++ b/configs/colibri_vf_dtb_defconfig
@@ -9,3 +9,4 @@
CONFIG_DM=y
CONFIG_NAND_VF610_NFC=y
CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y
+CONFIG_SYS_PROMPT="Colibri VFxx # "
diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig
index 13afb08..1fed14e 100644
--- a/configs/corvus_defconfig
+++ b/configs/corvus_defconfig
@@ -9,3 +9,4 @@
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/cpu9260_128M_defconfig b/configs/cpu9260_128M_defconfig
index f423980..187fced 100644
--- a/configs/cpu9260_128M_defconfig
+++ b/configs/cpu9260_128M_defconfig
@@ -8,3 +8,4 @@
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="CPU9260=> "
diff --git a/configs/cpu9260_defconfig b/configs/cpu9260_defconfig
index 88afe9f..4b50505 100644
--- a/configs/cpu9260_defconfig
+++ b/configs/cpu9260_defconfig
@@ -8,3 +8,4 @@
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="CPU9260=> "
diff --git a/configs/cpu9260_nand_128M_defconfig b/configs/cpu9260_nand_128M_defconfig
index f59b000..797fb85 100644
--- a/configs/cpu9260_nand_128M_defconfig
+++ b/configs/cpu9260_nand_128M_defconfig
@@ -8,3 +8,4 @@
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="CPU9260=> "
diff --git a/configs/cpu9260_nand_defconfig b/configs/cpu9260_nand_defconfig
index e914c2b..8d155d0 100644
--- a/configs/cpu9260_nand_defconfig
+++ b/configs/cpu9260_nand_defconfig
@@ -8,3 +8,4 @@
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="CPU9260=> "
diff --git a/configs/cpu9G20_128M_defconfig b/configs/cpu9G20_128M_defconfig
index d215cc0..650c934 100644
--- a/configs/cpu9G20_128M_defconfig
+++ b/configs/cpu9G20_128M_defconfig
@@ -8,3 +8,4 @@
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="CPU9G20=> "
diff --git a/configs/cpu9G20_defconfig b/configs/cpu9G20_defconfig
index 51b19f0..997eec5 100644
--- a/configs/cpu9G20_defconfig
+++ b/configs/cpu9G20_defconfig
@@ -8,3 +8,4 @@
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="CPU9G20=> "
diff --git a/configs/cpu9G20_nand_128M_defconfig b/configs/cpu9G20_nand_128M_defconfig
index da4cbdd..6d62732 100644
--- a/configs/cpu9G20_nand_128M_defconfig
+++ b/configs/cpu9G20_nand_128M_defconfig
@@ -8,3 +8,4 @@
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="CPU9G20=> "
diff --git a/configs/cpu9G20_nand_defconfig b/configs/cpu9G20_nand_defconfig
index b9e4b3c..52f916f 100644
--- a/configs/cpu9G20_nand_defconfig
+++ b/configs/cpu9G20_nand_defconfig
@@ -8,3 +8,4 @@
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="CPU9G20=> "
diff --git a/configs/cpuat91_defconfig b/configs/cpuat91_defconfig
index cfc62aa..10b8ad2 100644
--- a/configs/cpuat91_defconfig
+++ b/configs/cpuat91_defconfig
@@ -10,3 +10,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_PROMPT="CPUAT91=> "
diff --git a/configs/da830evm_defconfig b/configs/da830evm_defconfig
index e0c8e25..d37ede3 100644
--- a/configs/da830evm_defconfig
+++ b/configs/da830evm_defconfig
@@ -6,3 +6,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="U-Boot > "
diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig
index 41395e3..557c0d5 100644
--- a/configs/da850evm_defconfig
+++ b/configs/da850evm_defconfig
@@ -7,3 +7,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="U-Boot > "
diff --git a/configs/da850evm_direct_nor_defconfig b/configs/da850evm_direct_nor_defconfig
index a1cba1a..79b877f 100644
--- a/configs/da850evm_direct_nor_defconfig
+++ b/configs/da850evm_direct_nor_defconfig
@@ -4,3 +4,4 @@
CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH,USE_NOR,DIRECT_NOR_BOOT"
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="U-Boot > "
diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig
index 2d80247..bf0ee84 100644
--- a/configs/dalmore_defconfig
+++ b/configs/dalmore_defconfig
@@ -15,3 +15,4 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_PROMPT="Tegra114 (Dalmore) # "
diff --git a/configs/davinci_dm355evm_defconfig b/configs/davinci_dm355evm_defconfig
index f10b643..4513ce4 100644
--- a/configs/davinci_dm355evm_defconfig
+++ b/configs/davinci_dm355evm_defconfig
@@ -6,3 +6,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="DM355 EVM # "
diff --git a/configs/davinci_dm355leopard_defconfig b/configs/davinci_dm355leopard_defconfig
index 7b33f6d..7945605 100644
--- a/configs/davinci_dm355leopard_defconfig
+++ b/configs/davinci_dm355leopard_defconfig
@@ -6,3 +6,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="DM355 LEOPARD # "
diff --git a/configs/davinci_dm365evm_defconfig b/configs/davinci_dm365evm_defconfig
index f139b58..3550e75 100644
--- a/configs/davinci_dm365evm_defconfig
+++ b/configs/davinci_dm365evm_defconfig
@@ -6,3 +6,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="DM36x EVM # "
diff --git a/configs/davinci_dm6467evm_defconfig b/configs/davinci_dm6467evm_defconfig
index 2a5262a..b2021af 100644
--- a/configs/davinci_dm6467evm_defconfig
+++ b/configs/davinci_dm6467evm_defconfig
@@ -7,3 +7,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="DM6467 EVM > "
diff --git a/configs/davinci_dvevm_defconfig b/configs/davinci_dvevm_defconfig
index aa30d1b..7c6f03e 100644
--- a/configs/davinci_dvevm_defconfig
+++ b/configs/davinci_dvevm_defconfig
@@ -6,3 +6,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot > "
diff --git a/configs/davinci_schmoogie_defconfig b/configs/davinci_schmoogie_defconfig
index 7c11c8c..2fb4d9f 100644
--- a/configs/davinci_schmoogie_defconfig
+++ b/configs/davinci_schmoogie_defconfig
@@ -6,3 +6,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot > "
diff --git a/configs/davinci_sffsdr_defconfig b/configs/davinci_sffsdr_defconfig
index 7aca606..633b4a8 100644
--- a/configs/davinci_sffsdr_defconfig
+++ b/configs/davinci_sffsdr_defconfig
@@ -6,3 +6,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot > "
diff --git a/configs/davinci_sonata_defconfig b/configs/davinci_sonata_defconfig
index 6014eee..697ce06 100644
--- a/configs/davinci_sonata_defconfig
+++ b/configs/davinci_sonata_defconfig
@@ -4,3 +4,4 @@
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot > "
diff --git a/configs/dbau1000_defconfig b/configs/dbau1000_defconfig
index 58da5b7..5dc12d2 100644
--- a/configs/dbau1000_defconfig
+++ b/configs/dbau1000_defconfig
@@ -10,3 +10,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_PROMPT="DbAu1xx0 # "
diff --git a/configs/dbau1100_defconfig b/configs/dbau1100_defconfig
index 14aeb4c..522b9bc 100644
--- a/configs/dbau1100_defconfig
+++ b/configs/dbau1100_defconfig
@@ -10,3 +10,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_PROMPT="DbAu1xx0 # "
diff --git a/configs/dbau1500_defconfig b/configs/dbau1500_defconfig
index 699b968..2fdddc7 100644
--- a/configs/dbau1500_defconfig
+++ b/configs/dbau1500_defconfig
@@ -10,3 +10,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_PROMPT="DbAu1xx0 # "
diff --git a/configs/dbau1550_defconfig b/configs/dbau1550_defconfig
index 6b17da7..07be3f1 100644
--- a/configs/dbau1550_defconfig
+++ b/configs/dbau1550_defconfig
@@ -8,3 +8,4 @@
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_PROMPT="DbAu1xx0 # "
diff --git a/configs/dbau1550_el_defconfig b/configs/dbau1550_el_defconfig
index 845bc87..7bd1e0c 100644
--- a/configs/dbau1550_el_defconfig
+++ b/configs/dbau1550_el_defconfig
@@ -9,3 +9,4 @@
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_PROMPT="DbAu1xx0 # "
diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig
index f0c4ee1..7246da5 100644
--- a/configs/devkit3250_defconfig
+++ b/configs/devkit3250_defconfig
@@ -1,3 +1,7 @@
CONFIG_ARM=y
CONFIG_TARGET_DEVKIT3250=y
+CONFIG_SPL=y
+# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
diff --git a/configs/dig297_defconfig b/configs/dig297_defconfig
index 483c20e..4c2c982 100644
--- a/configs/dig297_defconfig
+++ b/configs/dig297_defconfig
@@ -7,3 +7,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_PROMPT="DIG297# "
diff --git a/configs/dockstar_defconfig b/configs/dockstar_defconfig
index 40f6e0f..e4da466 100644
--- a/configs/dockstar_defconfig
+++ b/configs/dockstar_defconfig
@@ -4,3 +4,4 @@
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="DockStar> "
diff --git a/configs/dra72_evm_defconfig b/configs/dra72_evm_defconfig
new file mode 100644
index 0000000..3205e72
--- /dev/null
+++ b/configs/dra72_evm_defconfig
@@ -0,0 +1,17 @@
+CONFIG_ARM=y
+CONFIG_OMAP54XX=y
+CONFIG_TARGET_DRA7XX_EVM=y
+CONFIG_DEFAULT_DEVICE_TREE="dra72-evm"
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_DISABLE_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_DM_GPIO=y
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 463a7e2..f98e7b7 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -2,7 +2,8 @@
CONFIG_OMAP54XX=y
CONFIG_TARGET_DRA7XX_EVM=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/dra7xx_evm_qspiboot_defconfig b/configs/dra7xx_evm_qspiboot_defconfig
index 90e3cf4..f14fa62 100644
--- a/configs/dra7xx_evm_qspiboot_defconfig
+++ b/configs/dra7xx_evm_qspiboot_defconfig
@@ -2,7 +2,9 @@
CONFIG_OMAP54XX=y
CONFIG_TARGET_DRA7XX_EVM=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1,QSPI_BOOT"
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/dra7xx_evm_uart3_defconfig b/configs/dra7xx_evm_uart3_defconfig
index 474cada..8882260 100644
--- a/configs/dra7xx_evm_uart3_defconfig
+++ b/configs/dra7xx_evm_uart3_defconfig
@@ -1,8 +1,11 @@
CONFIG_ARM=y
CONFIG_OMAP54XX=y
CONFIG_TARGET_DRA7XX_EVM=y
+CONFIG_CONS_INDEX=3
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3,SPL_YMODEM_SUPPORT"
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SYS_EXTRA_OPTIONS="SPL_YMODEM_SUPPORT"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/draco_defconfig b/configs/draco_defconfig
index 8b177b3..d2fc98d 100644
--- a/configs/draco_defconfig
+++ b/configs/draco_defconfig
@@ -8,3 +8,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="U-Boot# "
diff --git a/configs/duovero_defconfig b/configs/duovero_defconfig
index 57410d3..d3de28a 100644
--- a/configs/duovero_defconfig
+++ b/configs/duovero_defconfig
@@ -6,3 +6,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_PROMPT="duovero # "
diff --git a/configs/ea20_defconfig b/configs/ea20_defconfig
index 388dfec..1d7494f 100644
--- a/configs/ea20_defconfig
+++ b/configs/ea20_defconfig
@@ -5,3 +5,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="ea20 > "
diff --git a/configs/eb_cpu5282_defconfig b/configs/eb_cpu5282_defconfig
index 1e19d3a..0044de6 100644
--- a/configs/eb_cpu5282_defconfig
+++ b/configs/eb_cpu5282_defconfig
@@ -3,3 +3,4 @@
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF000000,SYS_MONITOR_BASE=0xFF000400"
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="\nEB+CPU5282> "
diff --git a/configs/eb_cpux9k2_defconfig b/configs/eb_cpux9k2_defconfig
index bff6595..6a6f3cd 100644
--- a/configs/eb_cpux9k2_defconfig
+++ b/configs/eb_cpux9k2_defconfig
@@ -2,3 +2,4 @@
CONFIG_ARCH_AT91=y
CONFIG_TARGET_EB_CPUX9K2=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/eco5pk_defconfig b/configs/eco5pk_defconfig
index c43603b..8b5874d 100644
--- a/configs/eco5pk_defconfig
+++ b/configs/eco5pk_defconfig
@@ -5,3 +5,4 @@
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="ECO5-PK # "
diff --git a/configs/edminiv2_defconfig b/configs/edminiv2_defconfig
index 80ff33f..b2a2506 100644
--- a/configs/edminiv2_defconfig
+++ b/configs/edminiv2_defconfig
@@ -3,3 +3,4 @@
CONFIG_TARGET_EDMINIV2=y
CONFIG_SPL=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="EDMiniV2> "
diff --git a/configs/ethernut5_defconfig b/configs/ethernut5_defconfig
index d2379ec..d97008a 100644
--- a/configs/ethernut5_defconfig
+++ b/configs/ethernut5_defconfig
@@ -6,3 +6,4 @@
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FPGA is not set
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/flea3_defconfig b/configs/flea3_defconfig
index 7ea5da2..c9e4a28 100644
--- a/configs/flea3_defconfig
+++ b/configs/flea3_defconfig
@@ -1,3 +1,4 @@
CONFIG_ARM=y
CONFIG_TARGET_FLEA3=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="flea3 U-Boot > "
diff --git a/configs/fx12mm_defconfig b/configs/fx12mm_defconfig
index 1013b70..0213681 100644
--- a/configs/fx12mm_defconfig
+++ b/configs/fx12mm_defconfig
@@ -6,3 +6,4 @@
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_PROMPT="FX12MM:/# "
diff --git a/configs/goflexhome_defconfig b/configs/goflexhome_defconfig
index d1b9ba1..059ce80 100644
--- a/configs/goflexhome_defconfig
+++ b/configs/goflexhome_defconfig
@@ -4,3 +4,4 @@
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="GoFlexHome> "
diff --git a/configs/grasshopper_defconfig b/configs/grasshopper_defconfig
index 2d9c8ad..eefc5f2 100644
--- a/configs/grasshopper_defconfig
+++ b/configs/grasshopper_defconfig
@@ -6,3 +6,4 @@
CONFIG_AUTOBOOT_STOP_STR=" "
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/gwventana_defconfig b/configs/gwventana_defconfig
index 401f77e..d81f941 100644
--- a/configs/gwventana_defconfig
+++ b/configs/gwventana_defconfig
@@ -8,3 +8,4 @@
# CONFIG_CMD_FLASH is not set
CONFIG_DM=y
CONFIG_DM_SERIAL=y
+CONFIG_SYS_PROMPT="Ventana > "
diff --git a/configs/h2200_defconfig b/configs/h2200_defconfig
index f90a4a6..07b1706 100644
--- a/configs/h2200_defconfig
+++ b/configs/h2200_defconfig
@@ -17,3 +17,4 @@
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
+CONFIG_SYS_PROMPT="> "
diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig
index d88a082..c9c0618 100644
--- a/configs/harmony_defconfig
+++ b/configs/harmony_defconfig
@@ -13,3 +13,4 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_PROMPT="Tegra20 (Harmony) # "
diff --git a/configs/hikey_defconfig b/configs/hikey_defconfig
new file mode 100644
index 0000000..aa4fb0d
--- /dev/null
+++ b/configs/hikey_defconfig
@@ -0,0 +1,5 @@
+# 96boards HiKey
+CONFIG_ARM=y
+CONFIG_TARGET_HIKEY=y
+CONFIG_NET=y
+# CONFIG_CMD_IMLS is not set
diff --git a/configs/ib62x0_defconfig b/configs/ib62x0_defconfig
index e418d8f..b3fa890 100644
--- a/configs/ib62x0_defconfig
+++ b/configs/ib62x0_defconfig
@@ -4,3 +4,4 @@
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="ib62x0 => "
diff --git a/configs/iconnect_defconfig b/configs/iconnect_defconfig
index 49d4fa0..4c34290 100644
--- a/configs/iconnect_defconfig
+++ b/configs/iconnect_defconfig
@@ -4,3 +4,4 @@
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="iconnect => "
diff --git a/configs/ima3-mx53_defconfig b/configs/ima3-mx53_defconfig
index ef15127..1f5e3a6 100644
--- a/configs/ima3-mx53_defconfig
+++ b/configs/ima3-mx53_defconfig
@@ -3,3 +3,4 @@
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg"
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="IMA3 MX53 U-Boot > "
diff --git a/configs/imx31_litekit_defconfig b/configs/imx31_litekit_defconfig
index b197935..f10759b 100644
--- a/configs/imx31_litekit_defconfig
+++ b/configs/imx31_litekit_defconfig
@@ -1,3 +1,4 @@
CONFIG_ARM=y
CONFIG_TARGET_IMX31_LITEKIT=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="uboot> "
diff --git a/configs/imx31_phycore_defconfig b/configs/imx31_phycore_defconfig
index 161a604..e801ee7 100644
--- a/configs/imx31_phycore_defconfig
+++ b/configs/imx31_phycore_defconfig
@@ -1,3 +1,4 @@
CONFIG_ARM=y
CONFIG_TARGET_IMX31_PHYCORE=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="uboot> "
diff --git a/configs/integratorap_cm720t_defconfig b/configs/integratorap_cm720t_defconfig
index 369add7..50c6005 100644
--- a/configs/integratorap_cm720t_defconfig
+++ b/configs/integratorap_cm720t_defconfig
@@ -3,3 +3,4 @@
CONFIG_ARCH_INTEGRATOR_AP=y
CONFIG_CM720T=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="Integrator-AP # "
diff --git a/configs/integratorap_cm920t_defconfig b/configs/integratorap_cm920t_defconfig
index aa27cbd..ab0cdbd 100644
--- a/configs/integratorap_cm920t_defconfig
+++ b/configs/integratorap_cm920t_defconfig
@@ -3,3 +3,4 @@
CONFIG_ARCH_INTEGRATOR_AP=y
CONFIG_CM920T=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="Integrator-AP # "
diff --git a/configs/integratorap_cm926ejs_defconfig b/configs/integratorap_cm926ejs_defconfig
index 8155b67..317c6d8 100644
--- a/configs/integratorap_cm926ejs_defconfig
+++ b/configs/integratorap_cm926ejs_defconfig
@@ -3,3 +3,4 @@
CONFIG_ARCH_INTEGRATOR_AP=y
CONFIG_CM926EJ_S=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="Integrator-AP # "
diff --git a/configs/integratorap_cm946es_defconfig b/configs/integratorap_cm946es_defconfig
index b3b5edf..5ce1c00 100644
--- a/configs/integratorap_cm946es_defconfig
+++ b/configs/integratorap_cm946es_defconfig
@@ -3,3 +3,4 @@
CONFIG_ARCH_INTEGRATOR_AP=y
CONFIG_CM946ES=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="Integrator-AP # "
diff --git a/configs/integratorcp_cm1136_defconfig b/configs/integratorcp_cm1136_defconfig
index 5ab7c27..ddd2ce7 100644
--- a/configs/integratorcp_cm1136_defconfig
+++ b/configs/integratorcp_cm1136_defconfig
@@ -3,3 +3,4 @@
CONFIG_ARCH_INTEGRATOR_CP=y
CONFIG_CM1136=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="Integrator-CP # "
diff --git a/configs/integratorcp_cm920t_defconfig b/configs/integratorcp_cm920t_defconfig
index d0ed78d..036b32e 100644
--- a/configs/integratorcp_cm920t_defconfig
+++ b/configs/integratorcp_cm920t_defconfig
@@ -3,3 +3,4 @@
CONFIG_ARCH_INTEGRATOR_CP=y
CONFIG_CM920T=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="Integrator-CP # "
diff --git a/configs/integratorcp_cm926ejs_defconfig b/configs/integratorcp_cm926ejs_defconfig
index 9aa8602..6fc2a84 100644
--- a/configs/integratorcp_cm926ejs_defconfig
+++ b/configs/integratorcp_cm926ejs_defconfig
@@ -3,3 +3,4 @@
CONFIG_ARCH_INTEGRATOR_CP=y
CONFIG_CM926EJ_S=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="Integrator-CP # "
diff --git a/configs/integratorcp_cm946es_defconfig b/configs/integratorcp_cm946es_defconfig
index ef9d7d6..e077a5e 100644
--- a/configs/integratorcp_cm946es_defconfig
+++ b/configs/integratorcp_cm946es_defconfig
@@ -3,3 +3,4 @@
CONFIG_ARCH_INTEGRATOR_CP=y
CONFIG_CM946ES=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="Integrator-CP # "
diff --git a/configs/ipam390_defconfig b/configs/ipam390_defconfig
index c053b38..c416340 100644
--- a/configs/ipam390_defconfig
+++ b/configs/ipam390_defconfig
@@ -5,3 +5,4 @@
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot > "
diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig
index 44c7a8e..1dc2679 100644
--- a/configs/jetson-tk1_defconfig
+++ b/configs/jetson-tk1_defconfig
@@ -15,3 +15,4 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_PROMPT="Tegra124 (Jetson TK1) # "
diff --git a/configs/jornada_defconfig b/configs/jornada_defconfig
index 735c75f..65cbc2a 100644
--- a/configs/jornada_defconfig
+++ b/configs/jornada_defconfig
@@ -6,3 +6,4 @@
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
+CONFIG_SYS_PROMPT="HP Jornada# "
diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig
index f422886..c4cbadd 100644
--- a/configs/k2e_evm_defconfig
+++ b/configs/k2e_evm_defconfig
@@ -6,3 +6,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="K2E EVM # "
diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig
index 297183f..a604939 100644
--- a/configs/k2hk_evm_defconfig
+++ b/configs/k2hk_evm_defconfig
@@ -6,3 +6,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="K2HK EVM # "
diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
index 7aa538d..a687e0c 100644
--- a/configs/k2l_evm_defconfig
+++ b/configs/k2l_evm_defconfig
@@ -6,3 +6,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="K2L EVM # "
diff --git a/configs/kwb_defconfig b/configs/kwb_defconfig
index 5bca811..928c4bf 100644
--- a/configs/kwb_defconfig
+++ b/configs/kwb_defconfig
@@ -14,3 +14,4 @@
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_PROMPT="U-Boot (BuR V2.0)# "
diff --git a/configs/kzm9g_defconfig b/configs/kzm9g_defconfig
index 3df79d4..0669bbc 100644
--- a/configs/kzm9g_defconfig
+++ b/configs/kzm9g_defconfig
@@ -2,3 +2,4 @@
CONFIG_RMOBILE=y
CONFIG_TARGET_KZM9G=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="KZM-A9-GT# "
diff --git a/configs/mcx_defconfig b/configs/mcx_defconfig
index 1d3e978..1f38640 100644
--- a/configs/mcx_defconfig
+++ b/configs/mcx_defconfig
@@ -7,3 +7,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="mcx # "
diff --git a/configs/medcom-wide_defconfig b/configs/medcom-wide_defconfig
index bb33542..c0ba9d1 100644
--- a/configs/medcom-wide_defconfig
+++ b/configs/medcom-wide_defconfig
@@ -13,3 +13,4 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_PROMPT="Tegra20 (Medcom-Wide) # "
diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig
index 8355c67..5de1bcd 100644
--- a/configs/microblaze-generic_defconfig
+++ b/configs/microblaze-generic_defconfig
@@ -6,3 +6,4 @@
CONFIG_OF_CONTROL=y
CONFIG_SPL_DISABLE_OF_CONTROL=y
CONFIG_OF_EMBED=y
+CONFIG_SYS_PROMPT="U-Boot-mONStR> "
diff --git a/configs/ml507_defconfig b/configs/ml507_defconfig
index 3f66c86..44b7c31 100644
--- a/configs/ml507_defconfig
+++ b/configs/ml507_defconfig
@@ -6,3 +6,4 @@
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_PROMPT="ml507:/# "
diff --git a/configs/mt_ventoux_defconfig b/configs/mt_ventoux_defconfig
index 0a6b7d6..d5d26cf 100644
--- a/configs/mt_ventoux_defconfig
+++ b/configs/mt_ventoux_defconfig
@@ -5,3 +5,4 @@
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="mt_ventoux => "
diff --git a/configs/mx51_efikamx_defconfig b/configs/mx51_efikamx_defconfig
index 9c0deb1..a88c223 100644
--- a/configs/mx51_efikamx_defconfig
+++ b/configs/mx51_efikamx_defconfig
@@ -4,3 +4,4 @@
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="Efika> "
diff --git a/configs/nas220_defconfig b/configs/nas220_defconfig
index 47e5911..257c305 100644
--- a/configs/nas220_defconfig
+++ b/configs/nas220_defconfig
@@ -4,3 +4,4 @@
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="nas220> "
diff --git a/configs/nhk8815_defconfig b/configs/nhk8815_defconfig
index f9fac6f..218d92a 100644
--- a/configs/nhk8815_defconfig
+++ b/configs/nhk8815_defconfig
@@ -4,3 +4,4 @@
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="Nomadik> "
diff --git a/configs/nokia_rx51_defconfig b/configs/nokia_rx51_defconfig
index c40dadf..3dd24e0 100644
--- a/configs/nokia_rx51_defconfig
+++ b/configs/nokia_rx51_defconfig
@@ -10,3 +10,4 @@
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_PROMPT="Nokia RX-51 # "
diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig
index ccf656b..44bae73 100644
--- a/configs/nyan-big_defconfig
+++ b/configs/nyan-big_defconfig
@@ -21,3 +21,4 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_PROMPT="Tegra124 (Nyan-big) # "
diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig
index 155ce39..f0facf3 100644
--- a/configs/odroid-xu3_defconfig
+++ b/configs/odroid-xu3_defconfig
@@ -13,3 +13,4 @@
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_VIDEO_BRIDGE=y
+CONFIG_SYS_PROMPT="ODROID-XU3 # "
diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig
index 3104f88..0a4f63b 100644
--- a/configs/odroid_defconfig
+++ b/configs/odroid_defconfig
@@ -21,3 +21,4 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_ERRNO_STR=y
+CONFIG_SYS_PROMPT="Odroid # "
diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig
index 65b6f6a..de8fbd9 100644
--- a/configs/omap3_evm_defconfig
+++ b/configs/omap3_evm_defconfig
@@ -7,3 +7,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="OMAP3_EVM # "
diff --git a/configs/omap3_evm_quick_mmc_defconfig b/configs/omap3_evm_quick_mmc_defconfig
index 527b465..7d15b16 100644
--- a/configs/omap3_evm_quick_mmc_defconfig
+++ b/configs/omap3_evm_quick_mmc_defconfig
@@ -23,3 +23,4 @@
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
+CONFIG_SYS_PROMPT="OMAP3_EVM # "
diff --git a/configs/omap3_evm_quick_nand_defconfig b/configs/omap3_evm_quick_nand_defconfig
index e3278b5..cd30134 100644
--- a/configs/omap3_evm_quick_nand_defconfig
+++ b/configs/omap3_evm_quick_nand_defconfig
@@ -23,3 +23,4 @@
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
+CONFIG_SYS_PROMPT="OMAP3_EVM # "
diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
index b11d2e4..5d0ac9e 100644
--- a/configs/omap3_logic_defconfig
+++ b/configs/omap3_logic_defconfig
@@ -5,3 +5,4 @@
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+CONFIG_SYS_PROMPT="OMAP Logic # "
diff --git a/configs/omap3_mvblx_defconfig b/configs/omap3_mvblx_defconfig
index 415b02e..fb12a70 100644
--- a/configs/omap3_mvblx_defconfig
+++ b/configs/omap3_mvblx_defconfig
@@ -6,3 +6,4 @@
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="mvblx # "
diff --git a/configs/omap3_overo_defconfig b/configs/omap3_overo_defconfig
index 8d55590..5d03485 100644
--- a/configs/omap3_overo_defconfig
+++ b/configs/omap3_overo_defconfig
@@ -8,3 +8,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_PROMPT="Overo # "
diff --git a/configs/omap3_pandora_defconfig b/configs/omap3_pandora_defconfig
index f18a520..4fb7899 100644
--- a/configs/omap3_pandora_defconfig
+++ b/configs/omap3_pandora_defconfig
@@ -8,3 +8,4 @@
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_PROMPT="Pandora # "
diff --git a/configs/omap3_sdp3430_defconfig b/configs/omap3_sdp3430_defconfig
index df9e709..2e46091 100644
--- a/configs/omap3_sdp3430_defconfig
+++ b/configs/omap3_sdp3430_defconfig
@@ -4,3 +4,4 @@
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="OMAP34XX SDP # "
diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig
index a49be95..4cff178 100644
--- a/configs/omapl138_lcdk_defconfig
+++ b/configs/omapl138_lcdk_defconfig
@@ -6,3 +6,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="U-Boot > "
diff --git a/configs/origen_defconfig b/configs/origen_defconfig
index 6961978..d69d497 100644
--- a/configs/origen_defconfig
+++ b/configs/origen_defconfig
@@ -13,3 +13,4 @@
CONFIG_SPL_DISABLE_OF_CONTROL=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_SYS_PROMPT="ORIGEN # "
diff --git a/configs/palmld_defconfig b/configs/palmld_defconfig
index 8bf6c53..354071a 100644
--- a/configs/palmld_defconfig
+++ b/configs/palmld_defconfig
@@ -4,3 +4,4 @@
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_PROMPT="$ "
diff --git a/configs/palmtc_defconfig b/configs/palmtc_defconfig
index 4042466..de617e1 100644
--- a/configs/palmtc_defconfig
+++ b/configs/palmtc_defconfig
@@ -3,3 +3,4 @@
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_PROMPT="$ "
diff --git a/configs/paz00_defconfig b/configs/paz00_defconfig
index 60fb2d6..5cba318 100644
--- a/configs/paz00_defconfig
+++ b/configs/paz00_defconfig
@@ -13,3 +13,4 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_PROMPT="Tegra20 (Paz00) MOD # "
diff --git a/configs/pb1000_defconfig b/configs/pb1000_defconfig
index 72756a7..c6221a3 100644
--- a/configs/pb1000_defconfig
+++ b/configs/pb1000_defconfig
@@ -10,3 +10,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_PROMPT="Pb1x00 # "
diff --git a/configs/pcm030_defconfig b/configs/pcm030_defconfig
index df9309e..6305092 100644
--- a/configs/pcm030_defconfig
+++ b/configs/pcm030_defconfig
@@ -2,3 +2,4 @@
CONFIG_MPC5xxx=y
CONFIG_TARGET_PCM030=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="uboot> "
diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig
index 86d5a0b..a02e2ed 100644
--- a/configs/peach-pi_defconfig
+++ b/configs/peach-pi_defconfig
@@ -31,3 +31,4 @@
CONFIG_ERRNO_STR=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y
+CONFIG_SYS_PROMPT="Peach-Pi # "
diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig
index 8fe423e..e9fc6ae 100644
--- a/configs/peach-pit_defconfig
+++ b/configs/peach-pit_defconfig
@@ -31,3 +31,4 @@
CONFIG_ERRNO_STR=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y
+CONFIG_SYS_PROMPT="Peach-Pit # "
diff --git a/configs/pepper_defconfig b/configs/pepper_defconfig
index eb1b6cf..787c5f9 100644
--- a/configs/pepper_defconfig
+++ b/configs/pepper_defconfig
@@ -4,3 +4,4 @@
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="pepper# "
diff --git a/configs/platinum_picon_defconfig b/configs/platinum_picon_defconfig
index 3484c46..64da7c4 100644
--- a/configs/platinum_picon_defconfig
+++ b/configs/platinum_picon_defconfig
@@ -5,3 +5,4 @@
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="picon > "
diff --git a/configs/platinum_titanium_defconfig b/configs/platinum_titanium_defconfig
index 6a2cacf..67957c3 100644
--- a/configs/platinum_titanium_defconfig
+++ b/configs/platinum_titanium_defconfig
@@ -5,3 +5,4 @@
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="titanium > "
diff --git a/configs/plutux_defconfig b/configs/plutux_defconfig
index 8d96e33..07fa7f9 100644
--- a/configs/plutux_defconfig
+++ b/configs/plutux_defconfig
@@ -13,3 +13,4 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_PROMPT="Tegra20 (Plutux) # "
diff --git a/configs/pm9261_defconfig b/configs/pm9261_defconfig
index 2c842b4..0a7716e 100644
--- a/configs/pm9261_defconfig
+++ b/configs/pm9261_defconfig
@@ -8,3 +8,4 @@
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="pm9261> "
diff --git a/configs/pm9263_defconfig b/configs/pm9263_defconfig
index a065ce0..45e060b 100644
--- a/configs/pm9263_defconfig
+++ b/configs/pm9263_defconfig
@@ -8,3 +8,4 @@
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="u-boot-pm9263> "
diff --git a/configs/pm9g45_defconfig b/configs/pm9g45_defconfig
index bbaeae8..3f34b3c 100644
--- a/configs/pm9g45_defconfig
+++ b/configs/pm9g45_defconfig
@@ -6,3 +6,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/pogo_e02_defconfig b/configs/pogo_e02_defconfig
index f21237f..50a058e 100644
--- a/configs/pogo_e02_defconfig
+++ b/configs/pogo_e02_defconfig
@@ -4,3 +4,4 @@
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="PogoE02> "
diff --git a/configs/pr1_defconfig b/configs/pr1_defconfig
index b06babc..583f132 100644
--- a/configs/pr1_defconfig
+++ b/configs/pr1_defconfig
@@ -6,3 +6,4 @@
CONFIG_SPI_FLASH=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_LIB_RAND=y
+CONFIG_SYS_PROMPT="pr1>"
diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig
index 0bb42ff..41c2849 100644
--- a/configs/pxm2_defconfig
+++ b/configs/pxm2_defconfig
@@ -8,3 +8,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="U-Boot# "
diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig
index 2b126ac..7a3ac70 100644
--- a/configs/rastaban_defconfig
+++ b/configs/rastaban_defconfig
@@ -8,3 +8,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="U-Boot# "
diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig
index 139189d..4b92045 100644
--- a/configs/rpi_2_defconfig
+++ b/configs/rpi_2_defconfig
@@ -6,3 +6,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_PHYS_TO_BUS=y
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig
index db8da68..195ff99 100644
--- a/configs/rpi_defconfig
+++ b/configs/rpi_defconfig
@@ -6,3 +6,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_PHYS_TO_BUS=y
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/rut_defconfig b/configs/rut_defconfig
index da9dfe3..774957c 100644
--- a/configs/rut_defconfig
+++ b/configs/rut_defconfig
@@ -8,3 +8,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="U-Boot# "
diff --git a/configs/s5p_goni_defconfig b/configs/s5p_goni_defconfig
index 7e03b9d..5c873f7 100644
--- a/configs/s5p_goni_defconfig
+++ b/configs/s5p_goni_defconfig
@@ -10,3 +10,4 @@
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
+CONFIG_SYS_PROMPT="Goni # "
diff --git a/configs/s5pc210_universal_defconfig b/configs/s5pc210_universal_defconfig
index 21a4708..1a49978 100644
--- a/configs/s5pc210_universal_defconfig
+++ b/configs/s5pc210_universal_defconfig
@@ -12,3 +12,4 @@
CONFIG_SPL_DISABLE_OF_CONTROL=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_SYS_PROMPT="Universal # "
diff --git a/configs/scb9328_defconfig b/configs/scb9328_defconfig
index 3104586..c9c5034 100644
--- a/configs/scb9328_defconfig
+++ b/configs/scb9328_defconfig
@@ -4,3 +4,4 @@
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="scb9328> "
diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig
index 942f17e..54afbdb 100644
--- a/configs/seaboard_defconfig
+++ b/configs/seaboard_defconfig
@@ -13,3 +13,4 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_PROMPT="Tegra20 (SeaBoard) # "
diff --git a/configs/secomx6quq7_defconfig b/configs/secomx6quq7_defconfig
index 0095ceb..c97172d 100644
--- a/configs/secomx6quq7_defconfig
+++ b/configs/secomx6quq7_defconfig
@@ -7,3 +7,4 @@
CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_MMC"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_SYS_PROMPT="SECO MX6Q uQ7 U-Boot > "
diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig
new file mode 100644
index 0000000..8f12f30
--- /dev/null
+++ b/configs/smartweb_defconfig
@@ -0,0 +1,7 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SMARTWEB=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260"
+CONFIG_CMD_NET=y
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/smdk2410_defconfig b/configs/smdk2410_defconfig
index 74bb9e3..51f348e 100644
--- a/configs/smdk2410_defconfig
+++ b/configs/smdk2410_defconfig
@@ -1,3 +1,4 @@
CONFIG_ARM=y
CONFIG_TARGET_SMDK2410=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="SMDK2410 # "
diff --git a/configs/smdk5250_defconfig b/configs/smdk5250_defconfig
index b061e47..f0c9e01 100644
--- a/configs/smdk5250_defconfig
+++ b/configs/smdk5250_defconfig
@@ -24,3 +24,4 @@
CONFIG_DM_PMIC_MAX77686=y
CONFIG_DM_REGULATOR_MAX77686=y
CONFIG_VIDEO_BRIDGE=y
+CONFIG_SYS_PROMPT="SMDK5250 # "
diff --git a/configs/smdk5420_defconfig b/configs/smdk5420_defconfig
index 1561f6a..253fbe5 100644
--- a/configs/smdk5420_defconfig
+++ b/configs/smdk5420_defconfig
@@ -14,3 +14,4 @@
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_VIDEO_BRIDGE=y
+CONFIG_SYS_PROMPT="SMDK5420 # "
diff --git a/configs/smdkc100_defconfig b/configs/smdkc100_defconfig
index 6c8359e..676781e 100644
--- a/configs/smdkc100_defconfig
+++ b/configs/smdkc100_defconfig
@@ -5,3 +5,4 @@
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="SMDKC100 # "
diff --git a/configs/smdkv310_defconfig b/configs/smdkv310_defconfig
index 39dd5be..7833f62 100644
--- a/configs/smdkv310_defconfig
+++ b/configs/smdkv310_defconfig
@@ -10,3 +10,4 @@
# CONFIG_CMD_MISC is not set
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_SYS_PROMPT="SMDKV310 # "
diff --git a/configs/snapper9260_defconfig b/configs/snapper9260_defconfig
index d319a4f..31cc5a0 100644
--- a/configs/snapper9260_defconfig
+++ b/configs/snapper9260_defconfig
@@ -10,3 +10,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="Snapper> "
diff --git a/configs/sniper_defconfig b/configs/sniper_defconfig
new file mode 100644
index 0000000..dd66ca0
--- /dev/null
+++ b/configs/sniper_defconfig
@@ -0,0 +1,10 @@
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_SNIPER=y
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_SYS_PROMPT="Sniper # "
diff --git a/configs/snow_defconfig b/configs/snow_defconfig
index a7d9e7a..4a90f0a 100644
--- a/configs/snow_defconfig
+++ b/configs/snow_defconfig
@@ -41,3 +41,4 @@
CONFIG_VIDEO_BRIDGE=y
CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y
CONFIG_VIDEO_BRIDGE_NXP_PTN3460=y
+CONFIG_SYS_PROMPT="snow # "
diff --git a/configs/snowball_defconfig b/configs/snowball_defconfig
index 31aa583..e73bc48 100644
--- a/configs/snowball_defconfig
+++ b/configs/snowball_defconfig
@@ -10,3 +10,4 @@
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_PROMPT="U8500 $ "
diff --git a/configs/spring_defconfig b/configs/spring_defconfig
index a3abb35..2a9c6a9 100644
--- a/configs/spring_defconfig
+++ b/configs/spring_defconfig
@@ -40,3 +40,4 @@
CONFIG_REGULATOR_S5M8767=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y
+CONFIG_SYS_PROMPT="spring # "
diff --git a/configs/stamp9g20_defconfig b/configs/stamp9g20_defconfig
index 78c4775..40d6232 100644
--- a/configs/stamp9g20_defconfig
+++ b/configs/stamp9g20_defconfig
@@ -8,3 +8,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/stm32f429-discovery_defconfig b/configs/stm32f429-discovery_defconfig
index 188adc5..0c54d5b 100644
--- a/configs/stm32f429-discovery_defconfig
+++ b/configs/stm32f429-discovery_defconfig
@@ -1,3 +1,4 @@
CONFIG_ARM=y
CONFIG_TARGET_STM32F429_DISCOVERY=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot > "
diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig
index 3bdb1fc..f71206a 100644
--- a/configs/stv0991_defconfig
+++ b/configs/stv0991_defconfig
@@ -12,3 +12,4 @@
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_OF_CONTROL=y
+CONFIG_SYS_PROMPT="STV0991> "
diff --git a/configs/stxgp3_defconfig b/configs/stxgp3_defconfig
index 86afe88..816092d 100644
--- a/configs/stxgp3_defconfig
+++ b/configs/stxgp3_defconfig
@@ -2,3 +2,4 @@
CONFIG_MPC85xx=y
CONFIG_TARGET_STXGP3=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="GPPP=> "
diff --git a/configs/stxssa_defconfig b/configs/stxssa_defconfig
index c072417..ec812c1 100644
--- a/configs/stxssa_defconfig
+++ b/configs/stxssa_defconfig
@@ -2,3 +2,4 @@
CONFIG_MPC85xx=y
CONFIG_TARGET_STXSSA=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="SSA=> "
diff --git a/configs/tao3530_defconfig b/configs/tao3530_defconfig
index ae4b49b..779f400 100644
--- a/configs/tao3530_defconfig
+++ b/configs/tao3530_defconfig
@@ -7,3 +7,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="TAO-3530 # "
diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig
index 3787493..838d0ed 100644
--- a/configs/taurus_defconfig
+++ b/configs/taurus_defconfig
@@ -11,3 +11,4 @@
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/tb100_defconfig b/configs/tb100_defconfig
index cc8f527..acd1f3a 100644
--- a/configs/tb100_defconfig
+++ b/configs/tb100_defconfig
@@ -14,3 +14,4 @@
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_SERIAL=y
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_PROMPT="[tb100]:~# "
diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig
index f0e5106..745d32e 100644
--- a/configs/tbs2910_defconfig
+++ b/configs/tbs2910_defconfig
@@ -5,3 +5,4 @@
# CONFIG_CMD_FLASH is not set
CONFIG_DM=y
CONFIG_DM_THERMAL=y
+CONFIG_SYS_PROMPT="Matrix U-Boot> "
diff --git a/configs/tec-ng_defconfig b/configs/tec-ng_defconfig
index e731205..4e8f5c6 100644
--- a/configs/tec-ng_defconfig
+++ b/configs/tec-ng_defconfig
@@ -14,3 +14,4 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_PROMPT="Tegra30 (TEC-NG) # "
diff --git a/configs/tec_defconfig b/configs/tec_defconfig
index 3f815fe..84fa0be 100644
--- a/configs/tec_defconfig
+++ b/configs/tec_defconfig
@@ -13,3 +13,4 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_PROMPT="Tegra20 (TEC) # "
diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig
index 8192b28..e2a6b0c 100644
--- a/configs/thuban_defconfig
+++ b/configs/thuban_defconfig
@@ -8,3 +8,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="U-Boot# "
diff --git a/configs/ti814x_evm_defconfig b/configs/ti814x_evm_defconfig
index ade4ea2..f7d1e11 100644
--- a/configs/ti814x_evm_defconfig
+++ b/configs/ti814x_evm_defconfig
@@ -4,3 +4,4 @@
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot# "
diff --git a/configs/ti816x_evm_defconfig b/configs/ti816x_evm_defconfig
index 67e5e60..1fd2719 100644
--- a/configs/ti816x_evm_defconfig
+++ b/configs/ti816x_evm_defconfig
@@ -4,3 +4,4 @@
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="u-boot/ti816x# "
diff --git a/configs/titanium_defconfig b/configs/titanium_defconfig
index e892d3e..d286fd6 100644
--- a/configs/titanium_defconfig
+++ b/configs/titanium_defconfig
@@ -4,3 +4,4 @@
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="Titanium > "
diff --git a/configs/trats2_defconfig b/configs/trats2_defconfig
index f3cbe6d..f0dd2b9 100644
--- a/configs/trats2_defconfig
+++ b/configs/trats2_defconfig
@@ -13,3 +13,4 @@
CONFIG_SPL_DISABLE_OF_CONTROL=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_SYS_PROMPT="Trats2 # "
diff --git a/configs/trats_defconfig b/configs/trats_defconfig
index 6553edb..6412f31 100644
--- a/configs/trats_defconfig
+++ b/configs/trats_defconfig
@@ -12,3 +12,4 @@
CONFIG_SPL_DISABLE_OF_CONTROL=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_SYS_PROMPT="Trats # "
diff --git a/configs/tricorder_defconfig b/configs/tricorder_defconfig
index cbd4dd3..1da9e94 100644
--- a/configs/tricorder_defconfig
+++ b/configs/tricorder_defconfig
@@ -9,3 +9,4 @@
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_PROMPT="OMAP3 Tricorder # "
diff --git a/configs/trimslice_defconfig b/configs/trimslice_defconfig
index 9d2fb2d..a1bcb11 100644
--- a/configs/trimslice_defconfig
+++ b/configs/trimslice_defconfig
@@ -14,3 +14,4 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_PROMPT="Tegra20 (TrimSlice) # "
diff --git a/configs/tseries_mmc_defconfig b/configs/tseries_mmc_defconfig
index 9ed13b6..a083ee0 100644
--- a/configs/tseries_mmc_defconfig
+++ b/configs/tseries_mmc_defconfig
@@ -14,3 +14,4 @@
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_PROMPT="U-Boot (BuR V2.0)# "
diff --git a/configs/tseries_nand_defconfig b/configs/tseries_nand_defconfig
index 0b577edc..aa66a0e 100644
--- a/configs/tseries_nand_defconfig
+++ b/configs/tseries_nand_defconfig
@@ -14,3 +14,4 @@
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_PROMPT="U-Boot (BuR V2.0)# "
diff --git a/configs/tseries_spi_defconfig b/configs/tseries_spi_defconfig
index 1602a43..1cb90d6 100644
--- a/configs/tseries_spi_defconfig
+++ b/configs/tseries_spi_defconfig
@@ -15,3 +15,4 @@
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="U-Boot (BuR V2.0)# "
diff --git a/configs/tt01_defconfig b/configs/tt01_defconfig
index d23904d..08f9f7b 100644
--- a/configs/tt01_defconfig
+++ b/configs/tt01_defconfig
@@ -1,3 +1,4 @@
CONFIG_ARM=y
CONFIG_TARGET_TT01=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="TT01> "
diff --git a/configs/twister_defconfig b/configs/twister_defconfig
index 7381665..c3edd34 100644
--- a/configs/twister_defconfig
+++ b/configs/twister_defconfig
@@ -5,3 +5,4 @@
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="twister => "
diff --git a/configs/u8500_href_defconfig b/configs/u8500_href_defconfig
index 5a82ca8..0aebc78 100644
--- a/configs/u8500_href_defconfig
+++ b/configs/u8500_href_defconfig
@@ -10,3 +10,4 @@
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_PROMPT="U8500 $ "
diff --git a/configs/usb_a9263_dataflash_defconfig b/configs/usb_a9263_dataflash_defconfig
index 5f3974e..8cf3c4c 100644
--- a/configs/usb_a9263_dataflash_defconfig
+++ b/configs/usb_a9263_dataflash_defconfig
@@ -10,3 +10,4 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/v5fx30teval_defconfig b/configs/v5fx30teval_defconfig
index 8173f3e..e77dce9 100644
--- a/configs/v5fx30teval_defconfig
+++ b/configs/v5fx30teval_defconfig
@@ -6,3 +6,4 @@
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_PROMPT="v5fx30t:/# "
diff --git a/configs/vct_platinum_defconfig b/configs/vct_platinum_defconfig
index 81cf280..9a46dcb 100644
--- a/configs/vct_platinum_defconfig
+++ b/configs/vct_platinum_defconfig
@@ -3,3 +3,4 @@
CONFIG_VCT_PLATINUM=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_PROMPT="$ "
diff --git a/configs/vct_platinum_onenand_defconfig b/configs/vct_platinum_onenand_defconfig
index 8d91aa5..8c8d69a 100644
--- a/configs/vct_platinum_onenand_defconfig
+++ b/configs/vct_platinum_onenand_defconfig
@@ -6,3 +6,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_PROMPT="$ "
diff --git a/configs/vct_platinum_onenand_small_defconfig b/configs/vct_platinum_onenand_small_defconfig
index 6eaec0c..4e6cbc7 100644
--- a/configs/vct_platinum_onenand_small_defconfig
+++ b/configs/vct_platinum_onenand_small_defconfig
@@ -17,3 +17,4 @@
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_PROMPT="$ "
diff --git a/configs/vct_platinum_small_defconfig b/configs/vct_platinum_small_defconfig
index 088ab7e..f896822 100644
--- a/configs/vct_platinum_small_defconfig
+++ b/configs/vct_platinum_small_defconfig
@@ -14,3 +14,4 @@
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_PROMPT="$ "
diff --git a/configs/vct_platinumavc_defconfig b/configs/vct_platinumavc_defconfig
index faeb6a2..6e867b2 100644
--- a/configs/vct_platinumavc_defconfig
+++ b/configs/vct_platinumavc_defconfig
@@ -5,3 +5,4 @@
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_PROMPT="VCT# "
diff --git a/configs/vct_platinumavc_onenand_defconfig b/configs/vct_platinumavc_onenand_defconfig
index 900a626..55f8c91 100644
--- a/configs/vct_platinumavc_onenand_defconfig
+++ b/configs/vct_platinumavc_onenand_defconfig
@@ -8,3 +8,4 @@
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_PROMPT="$ "
diff --git a/configs/vct_platinumavc_onenand_small_defconfig b/configs/vct_platinumavc_onenand_small_defconfig
index e9928a0..343ab8f 100644
--- a/configs/vct_platinumavc_onenand_small_defconfig
+++ b/configs/vct_platinumavc_onenand_small_defconfig
@@ -17,3 +17,4 @@
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_PROMPT="$ "
diff --git a/configs/vct_platinumavc_small_defconfig b/configs/vct_platinumavc_small_defconfig
index 719bd64..b4acc4a 100644
--- a/configs/vct_platinumavc_small_defconfig
+++ b/configs/vct_platinumavc_small_defconfig
@@ -14,3 +14,4 @@
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_PROMPT="$ "
diff --git a/configs/vct_premium_defconfig b/configs/vct_premium_defconfig
index 7b04e7c..d71dd53 100644
--- a/configs/vct_premium_defconfig
+++ b/configs/vct_premium_defconfig
@@ -3,3 +3,4 @@
CONFIG_VCT_PREMIUM=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_PROMPT="$ "
diff --git a/configs/vct_premium_onenand_defconfig b/configs/vct_premium_onenand_defconfig
index 769f8bd..6923db8 100644
--- a/configs/vct_premium_onenand_defconfig
+++ b/configs/vct_premium_onenand_defconfig
@@ -6,3 +6,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_PROMPT="$ "
diff --git a/configs/vct_premium_onenand_small_defconfig b/configs/vct_premium_onenand_small_defconfig
index c062a01..04a2855 100644
--- a/configs/vct_premium_onenand_small_defconfig
+++ b/configs/vct_premium_onenand_small_defconfig
@@ -17,3 +17,4 @@
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_PROMPT="$ "
diff --git a/configs/vct_premium_small_defconfig b/configs/vct_premium_small_defconfig
index 4a5cdb0..265a6a5 100644
--- a/configs/vct_premium_small_defconfig
+++ b/configs/vct_premium_small_defconfig
@@ -14,3 +14,4 @@
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_PROMPT="$ "
diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig
index a4735f6..73a2558 100644
--- a/configs/venice2_defconfig
+++ b/configs/venice2_defconfig
@@ -15,3 +15,4 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_PROMPT="Tegra124 (Venice2) # "
diff --git a/configs/ventana_defconfig b/configs/ventana_defconfig
index f728585..d347317 100644
--- a/configs/ventana_defconfig
+++ b/configs/ventana_defconfig
@@ -13,3 +13,4 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_PROMPT="Tegra20 (Ventana) # "
diff --git a/configs/versatileab_defconfig b/configs/versatileab_defconfig
index 765fe6e..3dc7d19 100644
--- a/configs/versatileab_defconfig
+++ b/configs/versatileab_defconfig
@@ -1,5 +1,4 @@
CONFIG_ARM=y
-CONFIG_ARCH_VERSATILE=y
CONFIG_SYS_EXTRA_OPTIONS="ARCH_VERSATILE_AB"
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
diff --git a/configs/versatilepb_defconfig b/configs/versatilepb_defconfig
index 1973c38..9fe83b9 100644
--- a/configs/versatilepb_defconfig
+++ b/configs/versatilepb_defconfig
@@ -1,5 +1,4 @@
CONFIG_ARM=y
-CONFIG_ARCH_VERSATILE=y
CONFIG_SYS_EXTRA_OPTIONS="ARCH_VERSATILE_PB"
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
diff --git a/configs/versatileqemu_defconfig b/configs/versatileqemu_defconfig
index ea9c5b9..9ddef4d 100644
--- a/configs/versatileqemu_defconfig
+++ b/configs/versatileqemu_defconfig
@@ -1,5 +1,4 @@
CONFIG_ARM=y
-CONFIG_ARCH_VERSATILE=y
CONFIG_SYS_EXTRA_OPTIONS="ARCH_VERSATILE_QEMU,ARCH_VERSATILE_PB"
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig
index 0baaa91..3390f0e 100644
--- a/configs/vexpress_aemv8a_juno_defconfig
+++ b/configs/vexpress_aemv8a_juno_defconfig
@@ -15,3 +15,4 @@
# CONFIG_CMD_MISC is not set
CONFIG_DM=y
CONFIG_DM_SERIAL=y
+CONFIG_SYS_PROMPT="VExpress64# "
diff --git a/configs/vexpress_aemv8a_semi_defconfig b/configs/vexpress_aemv8a_semi_defconfig
index bf5576a..9890e64 100644
--- a/configs/vexpress_aemv8a_semi_defconfig
+++ b/configs/vexpress_aemv8a_semi_defconfig
@@ -16,3 +16,4 @@
# CONFIG_CMD_MISC is not set
CONFIG_DM=y
CONFIG_DM_SERIAL=y
+CONFIG_SYS_PROMPT="VExpress64# "
diff --git a/configs/vision2_defconfig b/configs/vision2_defconfig
index afe3b3c..962dc5b 100644
--- a/configs/vision2_defconfig
+++ b/configs/vision2_defconfig
@@ -4,3 +4,4 @@
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SYS_PROMPT="Vision II U-boot > "
diff --git a/configs/vl_ma2sc_defconfig b/configs/vl_ma2sc_defconfig
index 7a66783..c908c6e 100644
--- a/configs/vl_ma2sc_defconfig
+++ b/configs/vl_ma2sc_defconfig
@@ -6,3 +6,4 @@
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/vpac270_nor_128_defconfig b/configs/vpac270_nor_128_defconfig
index bbc6e6a..1d11653 100644
--- a/configs/vpac270_nor_128_defconfig
+++ b/configs/vpac270_nor_128_defconfig
@@ -3,3 +3,4 @@
CONFIG_SYS_EXTRA_OPTIONS="NOR,RAM_128M"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="$ "
diff --git a/configs/vpac270_nor_256_defconfig b/configs/vpac270_nor_256_defconfig
index 3f1ae1e..bcd1006 100644
--- a/configs/vpac270_nor_256_defconfig
+++ b/configs/vpac270_nor_256_defconfig
@@ -3,3 +3,4 @@
CONFIG_SYS_EXTRA_OPTIONS="NOR,RAM_256M"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="$ "
diff --git a/configs/vpac270_ond_256_defconfig b/configs/vpac270_ond_256_defconfig
index 7500b7c..d989819 100644
--- a/configs/vpac270_ond_256_defconfig
+++ b/configs/vpac270_ond_256_defconfig
@@ -5,3 +5,4 @@
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="$ "
diff --git a/configs/whistler_defconfig b/configs/whistler_defconfig
index 43d725b..e3ce9fd 100644
--- a/configs/whistler_defconfig
+++ b/configs/whistler_defconfig
@@ -13,3 +13,4 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_PROMPT="Tegra20 (Whistler) # "
diff --git a/configs/wireless_space_defconfig b/configs/wireless_space_defconfig
index 5551d27..63013f6 100644
--- a/configs/wireless_space_defconfig
+++ b/configs/wireless_space_defconfig
@@ -4,3 +4,4 @@
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+ONFIG_SYS_PROMPT="ws> "
diff --git a/configs/woodburn_defconfig b/configs/woodburn_defconfig
index 8dcf3e1..3b463c1 100644
--- a/configs/woodburn_defconfig
+++ b/configs/woodburn_defconfig
@@ -1,3 +1,4 @@
CONFIG_ARM=y
CONFIG_TARGET_WOODBURN=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="woodburn U-Boot > "
diff --git a/configs/woodburn_sd_defconfig b/configs/woodburn_sd_defconfig
index 96a00b3..59f2ad0 100644
--- a/configs/woodburn_sd_defconfig
+++ b/configs/woodburn_sd_defconfig
@@ -3,3 +3,4 @@
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/woodburn/imximage.cfg"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="woodburn U-Boot > "
diff --git a/configs/x600_defconfig b/configs/x600_defconfig
index fdd4d3b..6be6cc3 100644
--- a/configs/x600_defconfig
+++ b/configs/x600_defconfig
@@ -7,3 +7,4 @@
# CONFIG_CMD_SETEXPR is not set
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_PROMPT="X600> "
diff --git a/configs/xilinx-ppc405-generic_defconfig b/configs/xilinx-ppc405-generic_defconfig
index 9dae755..98030d0 100644
--- a/configs/xilinx-ppc405-generic_defconfig
+++ b/configs/xilinx-ppc405-generic_defconfig
@@ -6,3 +6,4 @@
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_PROMPT="xlx-ppc405:/# "
diff --git a/configs/xilinx-ppc440-generic_defconfig b/configs/xilinx-ppc440-generic_defconfig
index 398362b..de69773 100644
--- a/configs/xilinx-ppc440-generic_defconfig
+++ b/configs/xilinx-ppc440-generic_defconfig
@@ -6,3 +6,4 @@
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_PROMPT="board:/# "
diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig
index fda44ea..9c4d872 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_ep_defconfig
@@ -16,3 +16,5 @@
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_SYS_PROMPT="ZynqMP> "
+
diff --git a/configs/zipitz2_defconfig b/configs/zipitz2_defconfig
index 3591849..2977ccc 100644
--- a/configs/zipitz2_defconfig
+++ b/configs/zipitz2_defconfig
@@ -4,3 +4,4 @@
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_PROMPT="$ "
diff --git a/configs/zmx25_defconfig b/configs/zmx25_defconfig
index a34e827..c759cdf 100644
--- a/configs/zmx25_defconfig
+++ b/configs/zmx25_defconfig
@@ -5,3 +5,4 @@
CONFIG_AUTOBOOT_DELAY_STR="delaygs"
CONFIG_AUTOBOOT_STOP_STR="stopgs"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_PROMPT="zmx25> "
diff --git a/doc/device-tree-bindings/regulator/regulator.txt b/doc/device-tree-bindings/regulator/regulator.txt
index 68b02a8..2cf4b9d 100644
--- a/doc/device-tree-bindings/regulator/regulator.txt
+++ b/doc/device-tree-bindings/regulator/regulator.txt
@@ -15,15 +15,8 @@
Example the prefix "ldo" will pass for: "ldo1", "ldo@1", "LDO1", "LDOREG@1"...
-Required properties:
-- regulator-name: a string, required by the regulator uclass
-
-Note
-The "regulator-name" constraint is used for setting the device's uclass
-platform data '.name' field. And the regulator device name is set from
-it's node name.
-
Optional properties:
+- regulator-name: a string, required by the regulator uclass
- regulator-min-microvolt: a minimum allowed Voltage value
- regulator-max-microvolt: a maximum allowed Voltage value
- regulator-min-microamp: a minimum allowed Current value
@@ -31,6 +24,12 @@
- regulator-always-on: regulator should never be disabled
- regulator-boot-on: enabled by bootloader/firmware
+Note
+The "regulator-name" constraint is used for setting the device's uclass
+platform data '.name' field. And the regulator device name is set from
+it's node name. If "regulator-name" is not provided in dts, node name
+is chosen for setting the device's uclass platform data '.name' field.
+
Other kernel-style properties, are currently not used.
Note:
@@ -41,10 +40,8 @@
Example:
ldo0 {
- /* Mandatory */
- regulator-name = "VDDQ_EMMC_1.8V";
-
/* Optional */
+ regulator-name = "VDDQ_EMMC_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-min-microamp = <100000>;
diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index c82b564..788f8b7 100644
--- a/drivers/core/Kconfig
+++ b/drivers/core/Kconfig
@@ -1,3 +1,5 @@
+menu "Generic Driver Options"
+
config DM
bool "Enable Driver Model"
help
@@ -102,3 +104,5 @@
debug resource management for a managed device.
If you are unsure about this, Say N here.
+
+endmenu
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index bd26a2b..1ea116b 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -1 +1,5 @@
+menu "Hardware crypto devices"
+
source drivers/crypto/fsl/Kconfig
+
+endmenu
diff --git a/drivers/crypto/fsl/Makefile b/drivers/crypto/fsl/Makefile
index 4aa91e4..fd736cf 100644
--- a/drivers/crypto/fsl/Makefile
+++ b/drivers/crypto/fsl/Makefile
@@ -1,9 +1,7 @@
#
# Copyright 2014 Freescale Semiconductor, Inc.
#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# Version 2 as published by the Free Software Foundation.
+# SPDX-License-Identifier: GPL-2.0+
#
obj-y += sec.o
diff --git a/drivers/demo/Kconfig b/drivers/demo/Kconfig
index 7a8ce18..98bb633 100644
--- a/drivers/demo/Kconfig
+++ b/drivers/demo/Kconfig
@@ -1,3 +1,5 @@
+menu "Demo for driver model"
+
config DM_DEMO
bool "Enable demo uclass support"
depends on DM
@@ -24,3 +26,5 @@
a shape when the 'demo hello' command is executed which targets
this device. It can be used to help understand how driver model
works.
+
+endmenu
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 0c43777..5934597 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -1,3 +1,9 @@
+#
+# GPIO infrastructure and drivers
+#
+
+menu "GPIO Support"
+
config DM_GPIO
bool "Enable Driver Model for GPIO drivers"
depends on DM
@@ -42,3 +48,5 @@
default n
help
Say yes here to support Vybrid vf610 GPIOs.
+
+endmenu
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 67c6374..26f2574 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -42,3 +42,5 @@
obj-$(CONFIG_STM32_GPIO) += stm32_gpio.o
obj-$(CONFIG_ZYNQ_GPIO) += zynq_gpio.o
obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o
+obj-$(CONFIG_HIKEY_GPIO) += hi6220_gpio.o
+
diff --git a/drivers/gpio/hi6220_gpio.c b/drivers/gpio/hi6220_gpio.c
new file mode 100644
index 0000000..3f41bff
--- /dev/null
+++ b/drivers/gpio/hi6220_gpio.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2015 Linaro
+ * Peter Griffin <peter.griffin@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <errno.h>
+
+static int hi6220_gpio_direction_input(struct udevice *dev, unsigned int gpio)
+{
+ struct gpio_bank *bank = dev_get_priv(dev);
+ u8 data;
+
+ data = readb(bank->base + HI6220_GPIO_DIR);
+ data &= ~(1 << gpio);
+ writeb(data, bank->base + HI6220_GPIO_DIR);
+
+ return 0;
+}
+
+static int hi6220_gpio_set_value(struct udevice *dev, unsigned gpio,
+ int value)
+{
+ struct gpio_bank *bank = dev_get_priv(dev);
+
+ writeb(!!value << gpio, bank->base + (BIT(gpio + 2)));
+ return 0;
+}
+
+static int hi6220_gpio_direction_output(struct udevice *dev, unsigned gpio,
+ int value)
+{
+ struct gpio_bank *bank = dev_get_priv(dev);
+ u8 data;
+
+ data = readb(bank->base + HI6220_GPIO_DIR);
+ data |= 1 << gpio;
+ writeb(data, bank->base + HI6220_GPIO_DIR);
+
+ hi6220_gpio_set_value(dev, gpio, value);
+
+ return 0;
+}
+
+static int hi6220_gpio_get_value(struct udevice *dev, unsigned gpio)
+{
+ struct gpio_bank *bank = dev_get_priv(dev);
+
+ return !!readb(bank->base + (BIT(gpio + 2)));
+}
+
+
+
+static const struct dm_gpio_ops gpio_hi6220_ops = {
+ .direction_input = hi6220_gpio_direction_input,
+ .direction_output = hi6220_gpio_direction_output,
+ .get_value = hi6220_gpio_get_value,
+ .set_value = hi6220_gpio_set_value,
+};
+
+static int hi6220_gpio_probe(struct udevice *dev)
+{
+ struct gpio_bank *bank = dev_get_priv(dev);
+ struct hikey_gpio_platdata *plat = dev_get_platdata(dev);
+ struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+ char name[18], *str;
+
+ sprintf(name, "GPIO%d_", plat->bank_index);
+
+ str = strdup(name);
+ if (!str)
+ return -ENOMEM;
+
+ uc_priv->bank_name = str;
+ uc_priv->gpio_count = HI6220_GPIO_PER_BANK;
+
+ bank->base = (u8 *)plat->base;
+
+ return 0;
+}
+
+U_BOOT_DRIVER(gpio_hi6220) = {
+ .name = "gpio_hi6220",
+ .id = UCLASS_GPIO,
+ .ops = &gpio_hi6220_ops,
+ .probe = hi6220_gpio_probe,
+ .priv_auto_alloc_size = sizeof(struct gpio_bank),
+};
+
+
diff --git a/drivers/gpio/omap_gpio.c b/drivers/gpio/omap_gpio.c
index 0a1e124..cd960dc 100644
--- a/drivers/gpio/omap_gpio.c
+++ b/drivers/gpio/omap_gpio.c
@@ -20,9 +20,13 @@
*/
#include <common.h>
#include <dm.h>
+#include <fdtdec.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/errno.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
#define OMAP_GPIO_DIR_OUT 0
#define OMAP_GPIO_DIR_IN 1
@@ -34,7 +38,6 @@
struct gpio_bank {
/* TODO(sjg@chromium.org): Can we use a struct here? */
void *base; /* address of registers in physical memory */
- enum gpio_method method;
};
#endif
@@ -55,13 +58,8 @@
void *reg = bank->base;
u32 l;
- switch (bank->method) {
- case METHOD_GPIO_24XX:
- reg += OMAP_GPIO_OE;
- break;
- default:
- return;
- }
+ reg += OMAP_GPIO_OE;
+
l = __raw_readl(reg);
if (is_input)
l |= 1 << gpio;
@@ -79,13 +77,7 @@
void *reg = bank->base;
u32 v;
- switch (bank->method) {
- case METHOD_GPIO_24XX:
- reg += OMAP_GPIO_OE;
- break;
- default:
- return -1;
- }
+ reg += OMAP_GPIO_OE;
v = __raw_readl(reg);
@@ -101,19 +93,12 @@
void *reg = bank->base;
u32 l = 0;
- switch (bank->method) {
- case METHOD_GPIO_24XX:
- if (enable)
- reg += OMAP_GPIO_SETDATAOUT;
- else
- reg += OMAP_GPIO_CLEARDATAOUT;
- l = 1 << gpio;
- break;
- default:
- printf("omap3-gpio unknown bank method %s %d\n",
- __FILE__, __LINE__);
- return;
- }
+ if (enable)
+ reg += OMAP_GPIO_SETDATAOUT;
+ else
+ reg += OMAP_GPIO_CLEARDATAOUT;
+
+ l = 1 << gpio;
__raw_writel(l, reg);
}
@@ -122,19 +107,13 @@
void *reg = bank->base;
int input;
- switch (bank->method) {
- case METHOD_GPIO_24XX:
- input = _get_gpio_direction(bank, gpio);
- switch (input) {
- case OMAP_GPIO_DIR_IN:
- reg += OMAP_GPIO_DATAIN;
- break;
- case OMAP_GPIO_DIR_OUT:
- reg += OMAP_GPIO_DATAOUT;
- break;
- default:
- return -1;
- }
+ input = _get_gpio_direction(bank, gpio);
+ switch (input) {
+ case OMAP_GPIO_DIR_IN:
+ reg += OMAP_GPIO_DATAIN;
+ break;
+ case OMAP_GPIO_DIR_OUT:
+ reg += OMAP_GPIO_DATAOUT;
break;
default:
return -1;
@@ -310,24 +289,56 @@
struct gpio_bank *bank = dev_get_priv(dev);
struct omap_gpio_platdata *plat = dev_get_platdata(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
- char name[18], *str;
- sprintf(name, "GPIO%d_", plat->bank_index);
- str = strdup(name);
- if (!str)
- return -ENOMEM;
- uc_priv->bank_name = str;
+ uc_priv->bank_name = plat->port_name;
uc_priv->gpio_count = GPIO_PER_BANK;
bank->base = (void *)plat->base;
- bank->method = plat->method;
+
+ return 0;
+}
+
+static int omap_gpio_bind(struct udevice *dev)
+{
+ struct omap_gpio_platdata *plat = dev->platdata;
+ fdt_addr_t base_addr;
+
+ if (plat)
+ return 0;
+
+ base_addr = dev_get_addr(dev);
+ if (base_addr == FDT_ADDR_T_NONE)
+ return -ENODEV;
+
+ /*
+ * TODO:
+ * When every board is converted to driver model and DT is
+ * supported, this can be done by auto-alloc feature, but
+ * not using calloc to alloc memory for platdata.
+ */
+ plat = calloc(1, sizeof(*plat));
+ if (!plat)
+ return -ENOMEM;
+
+ plat->base = base_addr;
+ plat->port_name = fdt_get_name(gd->fdt_blob, dev->of_offset, NULL);
+ dev->platdata = plat;
return 0;
}
+static const struct udevice_id omap_gpio_ids[] = {
+ { .compatible = "ti,omap3-gpio" },
+ { .compatible = "ti,omap4-gpio" },
+ { .compatible = "ti,am4372-gpio" },
+ { }
+};
+
U_BOOT_DRIVER(gpio_omap) = {
.name = "gpio_omap",
.id = UCLASS_GPIO,
.ops = &gpio_omap_ops,
+ .of_match = omap_gpio_ids,
+ .bind = omap_gpio_bind,
.probe = omap_gpio_probe,
.priv_auto_alloc_size = sizeof(struct gpio_bank),
};
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 9a62ddd..c40bd5c 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -1,3 +1,9 @@
+#
+# I2C subsystem configuration
+#
+
+menu "I2C support"
+
config DM_I2C
bool "Enable Driver Model for I2C drivers"
depends on DM
@@ -99,3 +105,5 @@
This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs.
source "drivers/i2c/muxes/Kconfig"
+
+endmenu
diff --git a/drivers/input/Makefile b/drivers/input/Makefile
index a8e9be2..24fec9b 100644
--- a/drivers/input/Makefile
+++ b/drivers/input/Makefile
@@ -7,6 +7,7 @@
obj-$(CONFIG_I8042_KBD) += i8042.o
obj-$(CONFIG_TEGRA_KEYBOARD) += tegra-kbc.o
+obj-$(CONFIG_TWL4030_INPUT) += twl4030.o
obj-$(CONFIG_CROS_EC_KEYB) += cros_ec_keyb.o
ifdef CONFIG_PS2KBD
obj-y += keyboard.o pc_keyb.o
diff --git a/drivers/input/twl4030.c b/drivers/input/twl4030.c
new file mode 100644
index 0000000..dc5868c
--- /dev/null
+++ b/drivers/input/twl4030.c
@@ -0,0 +1,88 @@
+/*
+ * TWL4030 input
+ *
+ * Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <twl4030.h>
+
+int twl4030_input_power_button(void)
+{
+ u8 data;
+
+ twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER,
+ TWL4030_PM_MASTER_STS_HW_CONDITIONS, &data);
+
+ if (data & TWL4030_PM_MASTER_STS_HW_CONDITIONS_PWON)
+ return 1;
+
+ return 0;
+}
+
+int twl4030_input_charger(void)
+{
+ u8 data;
+
+ twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER,
+ TWL4030_PM_MASTER_STS_HW_CONDITIONS, &data);
+
+ if (data & TWL4030_PM_MASTER_STS_HW_CONDITIONS_CHG)
+ return 1;
+
+ return 0;
+}
+
+int twl4030_input_usb(void)
+{
+ u8 data;
+
+ twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER,
+ TWL4030_PM_MASTER_STS_HW_CONDITIONS, &data);
+
+ if (data & TWL4030_PM_MASTER_STS_HW_CONDITIONS_USB ||
+ data & TWL4030_PM_MASTER_STS_HW_CONDITIONS_VBUS)
+ return 1;
+
+ return 0;
+}
+
+int twl4030_keypad_scan(unsigned char *matrix)
+{
+ u8 data;
+ u8 c, r;
+
+ twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD,
+ TWL4030_KEYPAD_KEYP_CTRL_REG, &data);
+
+ data |= TWL4030_KEYPAD_CTRL_SOFT_NRST | TWL4030_KEYPAD_CTRL_KBD_ON;
+ data &= ~TWL4030_KEYPAD_CTRL_SOFTMODEN;
+
+ twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD,
+ TWL4030_KEYPAD_KEYP_CTRL_REG, data);
+
+ for (c = 0; c < 8; c++) {
+ data = 0xff & ~(1 << c);
+ twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD,
+ TWL4030_KEYPAD_KBC_REG, data);
+
+ data = 0xff;
+ twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD,
+ TWL4030_KEYPAD_KBR_REG, &data);
+
+ for (r = 0; r < 8; r++)
+ matrix[c * 8 + r] = !(data & (1 << r));
+ }
+
+ data = 0xff & ~(TWL4030_KEYPAD_CTRL_SOFT_NRST);
+ twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD,
+ TWL4030_KEYPAD_KEYP_CTRL_REG, data);
+
+ return 0;
+}
+
+int twl4030_keypad_key(unsigned char *matrix, u8 c, u8 r)
+{
+ return matrix[c * 8 + r];
+}
diff --git a/drivers/led/Kconfig b/drivers/led/Kconfig
index de5feea..b21bc94 100644
--- a/drivers/led/Kconfig
+++ b/drivers/led/Kconfig
@@ -1,3 +1,5 @@
+menu "LED Support"
+
config LED
bool "Enable LED support"
depends on DM
@@ -24,3 +26,5 @@
GPIOs may be on the SoC or some other device which provides GPIOs.
The GPIO driver must used driver model. LEDs are configured using
the device tree.
+
+endmenu
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 3b7f76a..f29a169 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -1,3 +1,9 @@
+#
+# Multifunction miscellaneous devices
+#
+
+menu "Multifunction device drivers"
+
config CMD_CROS_EC
bool "Enable crosec command"
depends on CROS_EC
@@ -82,3 +88,5 @@
Each driver can provide a reset method which will be called to
effect a reset. The uclass will try all available drivers when
reset_walk() is called.
+
+endmenu
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 286df2f..cae207c 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -13,6 +13,7 @@
obj-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o
obj-$(CONFIG_DWMMC) += dw_mmc.o
obj-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o
+obj-$(CONFIG_HIKEY_DWMMC) += hi6220_dw_mmc.o
obj-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
obj-$(CONFIG_FTSDC010) += ftsdc010_mci.o
obj-$(CONFIG_FTSDC021) += ftsdc021_sdhci.o
diff --git a/drivers/mmc/hi6220_dw_mmc.c b/drivers/mmc/hi6220_dw_mmc.c
new file mode 100644
index 0000000..731458c
--- /dev/null
+++ b/drivers/mmc/hi6220_dw_mmc.c
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2015 Linaro
+ * peter.griffin <peter.griffin@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dwmmc.h>
+#include <malloc.h>
+#include <asm-generic/errno.h>
+
+#define DWMMC_MAX_CH_NUM 4
+
+#define DWMMC_MAX_FREQ 50000000
+#define DWMMC_MIN_FREQ 400000
+
+/* Source clock is configured to 100MHz by ATF bl1*/
+#define MMC0_DEFAULT_FREQ 100000000
+
+static int hi6220_dwmci_core_init(struct dwmci_host *host, int index)
+{
+ host->name = "HiKey DWMMC";
+
+ host->dev_index = index;
+
+ /* Add the mmc channel to be registered with mmc core */
+ if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
+ printf("DWMMC%d registration failed\n", index);
+ return -1;
+ }
+ return 0;
+}
+
+/*
+ * This function adds the mmc channel to be registered with mmc core.
+ * index - mmc channel number.
+ * regbase - register base address of mmc channel specified in 'index'.
+ * bus_width - operating bus width of mmc channel specified in 'index'.
+ */
+int hi6220_dwmci_add_port(int index, u32 regbase, int bus_width)
+{
+ struct dwmci_host *host = NULL;
+
+ host = calloc(1, sizeof(struct dwmci_host));
+ if (!host) {
+ error("dwmci_host calloc failed!\n");
+ return -ENOMEM;
+ }
+
+ host->ioaddr = (void *)regbase;
+ host->buswidth = bus_width;
+ host->bus_hz = MMC0_DEFAULT_FREQ;
+
+ return hi6220_dwmci_core_init(host, index);
+}
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index 8238a7e..d7b388f 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -296,7 +296,7 @@
* (reset procedure is completed).
*/
#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
- defined(CONFIG_AM33XX)
+ defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
if (!(readl(&mmc_base->sysctl) & bit)) {
start = get_timer(0);
while (!(readl(&mmc_base->sysctl) & bit)) {
@@ -661,8 +661,8 @@
case 1:
priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
#if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
- defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)) && \
- defined(CONFIG_HSMMC2_8BIT)
+ defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) || \
+ defined(CONFIG_AM43XX)) && defined(CONFIG_HSMMC2_8BIT)
/* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
host_caps_val |= MMC_MODE_8BIT;
#endif
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index b40dda8..46dce72 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -54,6 +54,7 @@
obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o
obj-$(CONFIG_NAND_LPC32XX_MLC) += lpc32xx_nand_mlc.o
+obj-$(CONFIG_NAND_LPC32XX_SLC) += lpc32xx_nand_slc.o
obj-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o
obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o
obj-$(CONFIG_NAND_MXC) += mxc_nand.o
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index a2016e7..0d4f327 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -1378,9 +1378,7 @@
hwctrl(&mtd, (page_addr >> 16) & 0x0f,
NAND_CTRL_ALE | NAND_CTRL_CHANGE);
#endif
-
hwctrl(&mtd, NAND_CMD_ERASE2, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
- udelay(2000);
while (!this->dev_ready(&mtd))
;
diff --git a/drivers/mtd/nand/lpc32xx_nand_slc.c b/drivers/mtd/nand/lpc32xx_nand_slc.c
new file mode 100644
index 0000000..719a74d
--- /dev/null
+++ b/drivers/mtd/nand/lpc32xx_nand_slc.c
@@ -0,0 +1,176 @@
+/*
+ * LPC32xx SLC NAND flash controller driver
+ *
+ * (C) Copyright 2015 Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/sys_proto.h>
+
+struct lpc32xx_nand_slc_regs {
+ u32 data;
+ u32 addr;
+ u32 cmd;
+ u32 stop;
+ u32 ctrl;
+ u32 cfg;
+ u32 stat;
+ u32 int_stat;
+ u32 ien;
+ u32 isr;
+ u32 icr;
+ u32 tac;
+ u32 tc;
+ u32 ecc;
+ u32 dma_data;
+};
+
+/* CFG register */
+#define CFG_CE_LOW (1 << 5)
+
+/* CTRL register */
+#define CTRL_SW_RESET (1 << 2)
+
+/* STAT register */
+#define STAT_NAND_READY (1 << 0)
+
+/* INT_STAT register */
+#define INT_STAT_TC (1 << 1)
+#define INT_STAT_RDY (1 << 0)
+
+/* TAC register bits, be aware of overflows */
+#define TAC_W_RDY(n) (max_t(uint32_t, (n), 0xF) << 28)
+#define TAC_W_WIDTH(n) (max_t(uint32_t, (n), 0xF) << 24)
+#define TAC_W_HOLD(n) (max_t(uint32_t, (n), 0xF) << 20)
+#define TAC_W_SETUP(n) (max_t(uint32_t, (n), 0xF) << 16)
+#define TAC_R_RDY(n) (max_t(uint32_t, (n), 0xF) << 12)
+#define TAC_R_WIDTH(n) (max_t(uint32_t, (n), 0xF) << 8)
+#define TAC_R_HOLD(n) (max_t(uint32_t, (n), 0xF) << 4)
+#define TAC_R_SETUP(n) (max_t(uint32_t, (n), 0xF) << 0)
+
+static struct lpc32xx_nand_slc_regs __iomem *lpc32xx_nand_slc_regs
+ = (struct lpc32xx_nand_slc_regs __iomem *)SLC_NAND_BASE;
+
+static void lpc32xx_nand_init(void)
+{
+ uint32_t hclk = get_hclk_clk_rate();
+
+ /* Reset SLC NAND controller */
+ writel(CTRL_SW_RESET, &lpc32xx_nand_slc_regs->ctrl);
+
+ /* 8-bit bus, no DMA, no ECC, ordinary CE signal */
+ writel(0, &lpc32xx_nand_slc_regs->cfg);
+
+ /* Interrupts disabled and cleared */
+ writel(0, &lpc32xx_nand_slc_regs->ien);
+ writel(INT_STAT_TC | INT_STAT_RDY,
+ &lpc32xx_nand_slc_regs->icr);
+
+ /* Configure NAND flash timings */
+ writel(TAC_W_RDY(CONFIG_LPC32XX_NAND_SLC_WDR_CLKS) |
+ TAC_W_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_WWIDTH) |
+ TAC_W_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_WHOLD) |
+ TAC_W_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_WSETUP) |
+ TAC_R_RDY(CONFIG_LPC32XX_NAND_SLC_RDR_CLKS) |
+ TAC_R_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_RWIDTH) |
+ TAC_R_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_RHOLD) |
+ TAC_R_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_RSETUP),
+ &lpc32xx_nand_slc_regs->tac);
+}
+
+static void lpc32xx_nand_cmd_ctrl(struct mtd_info *mtd,
+ int cmd, unsigned int ctrl)
+{
+ debug("ctrl: 0x%08x, cmd: 0x%08x\n", ctrl, cmd);
+
+ if (ctrl & NAND_NCE)
+ setbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_CE_LOW);
+ else
+ clrbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_CE_LOW);
+
+ if (cmd == NAND_CMD_NONE)
+ return;
+
+ if (ctrl & NAND_CLE)
+ writel(cmd & 0xFF, &lpc32xx_nand_slc_regs->cmd);
+ else if (ctrl & NAND_ALE)
+ writel(cmd & 0xFF, &lpc32xx_nand_slc_regs->addr);
+}
+
+static int lpc32xx_nand_dev_ready(struct mtd_info *mtd)
+{
+ return readl(&lpc32xx_nand_slc_regs->stat) & STAT_NAND_READY;
+}
+
+static void lpc32xx_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+ while (len-- > 0)
+ *buf++ = readl(&lpc32xx_nand_slc_regs->data);
+}
+
+static uint8_t lpc32xx_read_byte(struct mtd_info *mtd)
+{
+ return readl(&lpc32xx_nand_slc_regs->data);
+}
+
+static void lpc32xx_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
+{
+ while (len-- > 0)
+ writel(*buf++, &lpc32xx_nand_slc_regs->data);
+}
+
+static void lpc32xx_write_byte(struct mtd_info *mtd, uint8_t byte)
+{
+ writel(byte, &lpc32xx_nand_slc_regs->data);
+}
+
+/*
+ * LPC32xx has only one SLC NAND controller, don't utilize
+ * CONFIG_SYS_NAND_SELF_INIT to be able to reuse this function
+ * both in SPL NAND and U-boot images.
+ */
+int board_nand_init(struct nand_chip *lpc32xx_chip)
+{
+ lpc32xx_chip->cmd_ctrl = lpc32xx_nand_cmd_ctrl;
+ lpc32xx_chip->dev_ready = lpc32xx_nand_dev_ready;
+
+ /*
+ * Hardware ECC calculation is not supported by the driver,
+ * because it requires DMA support, see LPC32x0 User Manual,
+ * note after SLC_ECC register description (UM10326, p.198)
+ */
+ lpc32xx_chip->ecc.mode = NAND_ECC_SOFT;
+
+ /*
+ * The implementation of these functions is quite common, but
+ * they MUST be defined, because access to data register
+ * is strictly 32-bit aligned.
+ */
+ lpc32xx_chip->read_buf = lpc32xx_read_buf;
+ lpc32xx_chip->read_byte = lpc32xx_read_byte;
+ lpc32xx_chip->write_buf = lpc32xx_write_buf;
+ lpc32xx_chip->write_byte = lpc32xx_write_byte;
+
+ /*
+ * Use default ECC layout, but these values are predefined
+ * for both small and large page NAND flash devices.
+ */
+ lpc32xx_chip->ecc.size = 256;
+ lpc32xx_chip->ecc.bytes = 3;
+ lpc32xx_chip->ecc.strength = 1;
+
+#if defined(CONFIG_SYS_NAND_USE_FLASH_BBT)
+ lpc32xx_chip->bbt_options |= NAND_BBT_USE_FLASH;
+#endif
+
+ /* Initialize NAND interface */
+ lpc32xx_nand_init();
+
+ return 0;
+}
diff --git a/drivers/mtd/nand/nand_spl_simple.c b/drivers/mtd/nand/nand_spl_simple.c
index 700ca32..e69f662 100644
--- a/drivers/mtd/nand/nand_spl_simple.c
+++ b/drivers/mtd/nand/nand_spl_simple.c
@@ -115,6 +115,7 @@
static int nand_is_bad_block(int block)
{
struct nand_chip *this = mtd.priv;
+ u_char bb_data[2];
nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS,
NAND_CMD_READOOB);
@@ -123,10 +124,12 @@
* Read one byte (or two if it's a 16 bit chip).
*/
if (this->options & NAND_BUSWIDTH_16) {
- if (readw(this->IO_ADDR_R) != 0xffff)
+ this->read_buf(&mtd, bb_data, 2);
+ if (bb_data[0] != 0xff || bb_data[1] != 0xff)
return 1;
} else {
- if (readb(this->IO_ADDR_R) != 0xff)
+ this->read_buf(&mtd, bb_data, 1);
+ if (bb_data[0] != 0xff)
return 1;
}
diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c
index 427ad3e..0444795 100644
--- a/drivers/net/davinci_emac.c
+++ b/drivers/net/davinci_emac.c
@@ -598,7 +598,8 @@
debug_emac("+ emac_close\n");
davinci_eth_ch_teardown(EMAC_CH_TX); /* TX Channel teardown */
- davinci_eth_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */
+ if (readl(&adap_emac->RXCONTROL) & 1)
+ davinci_eth_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */
/* Reset EMAC module and disable interrupts in wrapper */
writel(1, &adap_emac->SOFTRESET);
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index 96e6bb0..d5d48b1 100644
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c
@@ -126,6 +126,7 @@
static void e1000_set_media_type(struct e1000_hw *hw);
static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
+static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
#ifndef CONFIG_E1000_NO_NVM
@@ -729,7 +730,10 @@
eecd &= ~E1000_EECD_REQ;
E1000_WRITE_REG(hw, EECD, eecd);
}
+
+ e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
}
+
/******************************************************************************
* Reads a 16 bit word from the EEPROM.
*
@@ -992,10 +996,6 @@
DEBUGFUNC();
- swsm = E1000_READ_REG(hw, SWSM);
- swsm &= ~E1000_SWSM_SMBI;
- E1000_WRITE_REG(hw, SWSM, swsm);
-
if (hw->mac_type != e1000_80003es2lan)
return E1000_SUCCESS;
@@ -1102,6 +1102,7 @@
return E1000_SUCCESS;
}
+/* Take ownership of the PHY */
static int32_t
e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
{
@@ -1115,10 +1116,7 @@
if (e1000_get_hw_eeprom_semaphore(hw))
return -E1000_ERR_SWFW_SYNC;
- if (hw->mac_type == e1000_igb)
- swfw_sync = E1000_READ_REG(hw, I210_SW_FW_SYNC);
- else
- swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
+ swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
if (!(swfw_sync & (fwmask | swmask)))
break;
@@ -1141,6 +1139,21 @@
return E1000_SUCCESS;
}
+static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
+{
+ uint32_t swfw_sync = 0;
+
+ DEBUGFUNC();
+ while (e1000_get_hw_eeprom_semaphore(hw))
+ ; /* Empty */
+
+ swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
+ swfw_sync &= ~mask;
+ E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
+
+ e1000_put_hw_eeprom_semaphore(hw);
+}
+
static bool e1000_is_second_port(struct e1000_hw *hw)
{
switch (hw->mac_type) {
@@ -4004,7 +4017,7 @@
DEBUGFUNC();
DEBUGOUT("Waiting for Auto-Neg to complete.\n");
- /* We will wait for autoneg to complete or 4.5 seconds to expire. */
+ /* We will wait for autoneg to complete or timeout to expire. */
for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
/* Read the MII Status Register and wait for Auto-Neg
* Complete bit to be set.
@@ -4438,6 +4451,7 @@
if (hw->mac_type >= e1000_82571)
mdelay(10);
+
} else {
/* Read the Extended Device Control Register, assert the PHY_RESET_DIR
* bit to put the PHY into reset. Then, take it out of reset.
@@ -4462,6 +4476,8 @@
E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
}
+ e1000_swfw_sync_release(hw, swfw);
+
/* Wait for FW to finish PHY configuration. */
ret_val = e1000_get_phy_cfg_done(hw);
if (ret_val != E1000_SUCCESS)
diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h
index f3b77b1..23a81e6 100644
--- a/drivers/net/e1000.h
+++ b/drivers/net/e1000.h
@@ -2460,7 +2460,7 @@
#define MII_CR_SPEED_100 0x2000
#define MII_CR_SPEED_10 0x0000
#define E1000_PHY_ADDRESS 0x01
-#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */
+#define PHY_AUTO_NEG_TIME 80 /* 8.0 Seconds */
#define PHY_FORCE_TIME 20 /* 2.0 Seconds */
#define PHY_REVISION_MASK 0xFFFFFFF0
#define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */
@@ -2496,7 +2496,6 @@
#define ICH_GFPREG_BASE_MASK 0x1FFF
#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
-#define E1000_I210_SW_FW_SYNC 0x5B50 /* Software-Firmware Synchronization - RW */
#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
/* SPI EEPROM Status Register */
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index d7a37f3..6702f5a 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -520,6 +520,7 @@
u16 status, len;
u8 *data;
u16 offset_out;
+ int ret = 1;
fm_eth = (struct fm_eth *)dev->priv;
pram = fm_eth->rx_pram;
@@ -533,7 +534,7 @@
net_process_received_packet(data, len);
} else {
printf("%s: Rx error\n", dev->name);
- return 0;
+ ret = 0;
}
/* clear the RxBDs */
@@ -559,7 +560,7 @@
}
fm_eth->cur_rxbd = (void *)rxbd;
- return 1;
+ return ret;
}
static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
diff --git a/drivers/net/lpc32xx_eth.c b/drivers/net/lpc32xx_eth.c
index 8dcbb4a..e76e9bc 100644
--- a/drivers/net/lpc32xx_eth.c
+++ b/drivers/net/lpc32xx_eth.c
@@ -151,7 +151,7 @@
#define SUPP_SPEED 0x00000100
/* MCFG register bitfields/masks and offsets (see Table 292) */
-#define MCFG_CLOCK_SELECT_MASK 0x0000001C
+#define MCFG_RESET_MII_MGMT 0x00008000
/* divide clock by 28 (see Table 293) */
#define MCFG_CLOCK_SELECT_DIV28 0x0000001C
@@ -168,9 +168,10 @@
#define COMMAND_RXENABLE 0x00000001
#define COMMAND_TXENABLE 0x00000002
#define COMMAND_PASSRUNTFRAME 0x00000040
+#define COMMAND_RMII 0x00000200
#define COMMAND_FULL_DUPLEX 0x00000400
/* Helper: general reset */
-#define COMMAND_RESETS 0x0000001C
+#define COMMAND_RESETS 0x00000038
/* STATUS register bitfields/masks and offsets (see Table 283) */
#define STATUS_RXSTATUS 0x00000001
@@ -201,6 +202,7 @@
struct eth_device dev;
struct lpc32xx_eth_registers *regs;
struct lpc32xx_eth_buffers *bufs;
+ bool phy_rmii;
};
#define LPC32XX_ETH_DEVICE_SIZE (sizeof(struct lpc32xx_eth_device))
@@ -351,15 +353,20 @@
#endif
/*
+ * Provide default Ethernet buffers base address if target did not.
* Locate buffers in SRAM at 0x00001000 to avoid cache issues and
* maximize throughput.
*/
-
-#define LPC32XX_ETH_BUFS 0x00001000
+#if !defined(CONFIG_LPC32XX_ETH_BUFS_BASE)
+#define CONFIG_LPC32XX_ETH_BUFS_BASE 0x00001000
+#endif
static struct lpc32xx_eth_device lpc32xx_eth = {
.regs = (struct lpc32xx_eth_registers *)LPC32XX_ETH_BASE,
- .bufs = (struct lpc32xx_eth_buffers *)LPC32XX_ETH_BUFS
+ .bufs = (struct lpc32xx_eth_buffers *)CONFIG_LPC32XX_ETH_BUFS_BASE,
+#if defined(CONFIG_RMII)
+ .phy_rmii = true,
+#endif
};
#define TX_TIMEOUT 10000
@@ -459,8 +466,22 @@
struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs;
int index;
- /* Release SOFT reset to let MII talk to PHY */
- clrbits_le32(®s->mac1, MAC1_SOFT_RESET);
+ /* Initial MAC initialization */
+ writel(MAC1_PASS_ALL_RX_FRAMES, ®s->mac1);
+ writel(MAC2_PAD_CRC_ENABLE | MAC2_CRC_ENABLE, ®s->mac2);
+ writel(PKTSIZE_ALIGN, ®s->maxf);
+
+ /* Retries: 15 (0xF). Collision window: 57 (0x37). */
+ writel(0x370F, ®s->clrt);
+
+ /* Set IP gap pt 2 to default 0x12 but pt 1 to non-default 0 */
+ writel(0x0012, ®s->ipgr);
+
+ /* pass runt (smaller than 64 bytes) frames */
+ if (lpc32xx_eth_device->phy_rmii)
+ writel(COMMAND_PASSRUNTFRAME | COMMAND_RMII, ®s->command);
+ else
+ writel(COMMAND_PASSRUNTFRAME, ®s->command);
/* Configure Full/Half Duplex mode */
if (miiphy_duplex(dev->name, CONFIG_PHY_ADDR) == FULL) {
@@ -477,20 +498,6 @@
else
writel(0, ®s->supp);
- /* Initial MAC initialization */
- writel(MAC1_PASS_ALL_RX_FRAMES, ®s->mac1);
- writel(MAC2_PAD_CRC_ENABLE | MAC2_CRC_ENABLE, ®s->mac2);
- writel(PKTSIZE_ALIGN, ®s->maxf);
-
- /* Retries: 15 (0xF). Collision window: 57 (0x37). */
- writel(0x370F, ®s->clrt);
-
- /* Set IP gap pt 2 to default 0x12 but pt 1 to non-default 0 */
- writel(0x0012, ®s->ipgr);
-
- /* pass runt (smaller than 64 bytes) frames */
- writel(COMMAND_PASSRUNTFRAME, ®s->command);
-
/* Save station address */
writel((unsigned long) (dev->enetaddr[0] |
(dev->enetaddr[1] << 8)), ®s->sa2);
@@ -562,6 +569,8 @@
#if defined(CONFIG_PHYLIB)
int lpc32xx_eth_phylib_init(struct eth_device *dev, int phyid)
{
+ struct lpc32xx_eth_device *lpc32xx_eth_device =
+ container_of(dev, struct lpc32xx_eth_device, dev);
struct mii_dev *bus;
struct phy_device *phydev;
int ret;
@@ -582,7 +591,11 @@
return -ENOMEM;
}
+ if (lpc32xx_eth_device->phy_rmii)
+ phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_RMII);
+ else
+ phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_MII);
+
- phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_MII);
if (!phydev) {
printf("phy_connect failed\n");
return -ENODEV;
@@ -604,7 +617,7 @@
* Set RMII management clock rate. With HCLK at 104 MHz and
* a divider of 28, this will be 3.72 MHz.
*/
-
+ writel(MCFG_RESET_MII_MGMT, ®s->mcfg);
writel(MCFG_CLOCK_SELECT_DIV28, ®s->mcfg);
/* Reset all MAC logic */
@@ -630,7 +643,7 @@
eth_register(dev);
#if defined(CONFIG_PHYLIB)
- lpc32xx_eth_phylib_init(dev, 0);
+ lpc32xx_eth_phylib_init(dev, CONFIG_PHY_ADDR);
#elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
miiphy_register(dev->name, mii_reg_read, mii_reg_write);
#endif
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index f949161..a5c1880 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -54,6 +54,7 @@
#define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc))
#define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE))
#define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
+#define MACB_TX_DUMMY_DMA_DESC_SIZE (DMA_DESC_BYTES(1))
#define RXADDR_USED 0x00000001
#define RXADDR_WRAP 0x00000002
@@ -93,6 +94,9 @@
unsigned long rx_ring_dma;
unsigned long tx_ring_dma;
+ struct macb_dma_desc *dummy_desc;
+ unsigned long dummy_desc_dma;
+
const struct device *dev;
struct eth_device netdev;
unsigned short phy_addr;
@@ -525,6 +529,30 @@
return 1;
}
+static int gmac_init_multi_queues(struct macb_device *macb)
+{
+ int i, num_queues = 1;
+ u32 queue_mask;
+
+ /* bit 0 is never set but queue 0 always exists */
+ queue_mask = gem_readl(macb, DCFG6) & 0xff;
+ queue_mask |= 0x1;
+
+ for (i = 1; i < MACB_MAX_QUEUES; i++)
+ if (queue_mask & (1 << i))
+ num_queues++;
+
+ macb->dummy_desc->ctrl = TXBUF_USED;
+ macb->dummy_desc->addr = 0;
+ flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma +
+ MACB_TX_DUMMY_DMA_DESC_SIZE);
+
+ for (i = 1; i < num_queues; i++)
+ gem_writel_queue_TBQP(macb, macb->dummy_desc_dma, i - 1);
+
+ return 0;
+}
+
static int macb_init(struct eth_device *netdev, bd_t *bd)
{
struct macb_device *macb = to_macb(netdev);
@@ -565,6 +593,9 @@
macb_writel(macb, TBQP, macb->tx_ring_dma);
if (macb_is_gem(macb)) {
+ /* Check the multi queue and initialize the queue for tx */
+ gmac_init_multi_queues(macb);
+
/*
* When the GMAC IP with GE feature, this bit is used to
* select interface between RGMII and GMII.
@@ -712,6 +743,8 @@
&macb->rx_ring_dma);
macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE,
&macb->tx_ring_dma);
+ macb->dummy_desc = dma_alloc_coherent(MACB_TX_DUMMY_DMA_DESC_SIZE,
+ &macb->dummy_desc_dma);
/* TODO: we need check the rx/tx_ring_dma is dcache line aligned */
diff --git a/drivers/net/macb.h b/drivers/net/macb.h
index 06f7c66..5bb48f4 100644
--- a/drivers/net/macb.h
+++ b/drivers/net/macb.h
@@ -60,6 +60,13 @@
/* GEM specific register offsets */
#define GEM_DCFG1 0x0280
+#define GEM_DCFG6 0x0294
+
+#define MACB_MAX_QUEUES 8
+
+/* GEM specific multi queues register offset */
+/* hw_q can be 0~7 */
+#define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2))
/* Bitfields in NCR */
#define MACB_LB_OFFSET 0
@@ -309,5 +316,7 @@
readl((port)->regs + GEM_##reg)
#define gem_writel(port, reg, value) \
writel((value), (port)->regs + GEM_##reg)
+#define gem_writel_queue_TBQP(port, value, queue_num) \
+ writel((value), (port)->regs + GEM_TBQP(queue_num))
#endif /* __DRIVERS_MACB_H__ */
diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
index 4512763..4b2808e 100644
--- a/drivers/net/phy/broadcom.c
+++ b/drivers/net/phy/broadcom.c
@@ -137,6 +137,24 @@
return 0;
}
+static int bcm_cygnus_startup(struct phy_device *phydev)
+{
+ /* Read the Status (2x to make sure link is right) */
+ genphy_update_link(phydev);
+ genphy_parse_link(phydev);
+
+ return 0;
+}
+
+static int bcm_cygnus_config(struct phy_device *phydev)
+{
+ genphy_config_aneg(phydev);
+
+ phy_reset(phydev);
+
+ return 0;
+}
+
/*
* Find out if PHY is in copper or serdes mode by looking at Expansion Reg
* 0x42 - "Operating Mode Status Register"
@@ -264,11 +282,22 @@
.shutdown = &genphy_shutdown,
};
+static struct phy_driver BCM_CYGNUS_driver = {
+ .name = "Broadcom CYGNUS GPHY",
+ .uid = 0xae025200,
+ .mask = 0xfffff0,
+ .features = PHY_GBIT_FEATURES,
+ .config = &bcm_cygnus_config,
+ .startup = &bcm_cygnus_startup,
+ .shutdown = &genphy_shutdown,
+};
+
int phy_broadcom_init(void)
{
phy_register(&BCM5482S_driver);
phy_register(&BCM5464S_driver);
phy_register(&BCM5461S_driver);
+ phy_register(&BCM_CYGNUS_driver);
return 0;
}
diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index 9437c3b..eab1558 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -303,30 +303,58 @@
* As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512
* /88E1514 Rev A0, Errata Section 3.1
*/
+
+ /* EEE initialization */
+ phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00ff);
+ phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x214B);
+ phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2144);
+ phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x0C28);
+ phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2146);
+ phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xB233);
+ phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x214D);
+ phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xCC0C);
+ phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2159);
+ phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000);
+
+ /* SGMII-to-Copper mode initialization */
if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
- phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00ff); /* page 0xff */
- phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x214B);
- phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2144);
- phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x0C28);
- phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2146);
- phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xB233);
- phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x214D);
- phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xCC0C);
- phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2159);
- phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000); /* reg page 0 */
- phy_write(phydev, MDIO_DEVAD_NONE, 22, 18); /* reg page 18 */
- /* Write HWCFG_MODE = SGMII to Copper */
+ /* Select page 18 */
+ phy_write(phydev, MDIO_DEVAD_NONE, 22, 18);
+
+ /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */
m88e1518_phy_writebits(phydev, 20, 0, 3, 1);
- /* Phy reset */
+ /* PHY reset is necessary after changing MODE[2:0] */
m88e1518_phy_writebits(phydev, 20, 15, 1, 1);
- phy_write(phydev, MDIO_DEVAD_NONE, 22, 0); /* reg page 18 */
+
+ /* Reset page selection */
+ phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
+
udelay(100);
}
return m88e1111s_config(phydev);
}
+/* Marvell 88E1510 */
+static int m88e1510_config(struct phy_device *phydev)
+{
+ /* Select page 3 */
+ phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
+
+ /* Enable INTn output on LED[2] */
+ m88e1518_phy_writebits(phydev, 18, 7, 1, 1);
+
+ /* Configure LEDs */
+ m88e1518_phy_writebits(phydev, 16, 0, 4, 3); /* LED[0]:0011 (ACT) */
+ m88e1518_phy_writebits(phydev, 16, 4, 4, 6); /* LED[1]:0110 (LINK) */
+
+ /* Reset page selection */
+ phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
+
+ return m88e1518_config(phydev);
+}
+
/* Marvell 88E1118 */
static int m88e1118_config(struct phy_device *phydev)
{
@@ -539,6 +567,16 @@
.shutdown = &genphy_shutdown,
};
+static struct phy_driver M88E1510_driver = {
+ .name = "Marvell 88E1510",
+ .uid = 0x1410dd0,
+ .mask = 0xffffff0,
+ .features = PHY_GBIT_FEATURES,
+ .config = &m88e1510_config,
+ .startup = &m88e1011s_startup,
+ .shutdown = &genphy_shutdown,
+};
+
static struct phy_driver M88E1518_driver = {
.name = "Marvell 88E1518",
.uid = 0x1410dd1,
@@ -569,6 +607,7 @@
phy_register(&M88E1118R_driver);
phy_register(&M88E1111S_driver);
phy_register(&M88E1011S_driver);
+ phy_register(&M88E1510_driver);
phy_register(&M88E1518_driver);
return 0;
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index c8d08e8..65c731a 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -554,7 +554,7 @@
}
static struct phy_device *phy_device_create(struct mii_dev *bus, int addr,
- int phy_id,
+ u32 phy_id,
phy_interface_t interface)
{
struct phy_device *dev;
@@ -763,11 +763,13 @@
phy_interface_t interface)
{
/* Reset the bus */
- if (bus->reset)
+ if (bus->reset) {
bus->reset(bus);
- /* Wait 15ms to make sure the PHY has come out of hard reset */
- udelay(15000);
+ /* Wait 15ms to make sure the PHY has come out of hard reset */
+ udelay(15000);
+ }
+
return get_phy_device_by_mask(bus, phy_mask, interface);
}
diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index 79452a8..bba48da 100644
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -41,6 +41,7 @@
#define MIIM_RTL8211F_PAGE_SELECT 0x1f
#define MIIM_RTL8211F_TX_DELAY 0x100
+#define MIIM_RTL8211F_LCR 0x10
/* RealTek RTL8211x */
static int rtl8211x_config(struct phy_device *phydev)
@@ -79,6 +80,13 @@
MIIM_RTL8211F_PAGE_SELECT, 0x0);
}
+ /* Set green LED for Link, yellow LED for Active */
+ phy_write(phydev, MDIO_DEVAD_NONE,
+ MIIM_RTL8211F_PAGE_SELECT, 0xd04);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x617f);
+ phy_write(phydev, MDIO_DEVAD_NONE,
+ MIIM_RTL8211F_PAGE_SELECT, 0x0);
+
genphy_config_aneg(phydev);
return 0;
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index 6ef149a..99c5778 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -7,6 +7,7 @@
obj-$(CONFIG_DM_PMIC) += pmic-uclass.o
obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o
+obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze100.o
obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o
obj-$(CONFIG_PMIC_TPS65090) += tps65090.o
obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o
@@ -22,3 +23,4 @@
obj-$(CONFIG_POWER_TPS65218) += pmic_tps62362.o
obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o
obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o
+obj-$(CONFIG_POWER_HI6553) += pmic_hi6553.o
diff --git a/drivers/power/pmic/pmic_hi6553.c b/drivers/power/pmic/pmic_hi6553.c
new file mode 100644
index 0000000..0af7987
--- /dev/null
+++ b/drivers/power/pmic/pmic_hi6553.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (C) 2015 Linaro
+ * Peter Griffin <peter.griffin@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <asm/io.h>
+#include <common.h>
+#include <power/pmic.h>
+#include <power/max8997_muic.h>
+#include <power/hi6553_pmic.h>
+#include <errno.h>
+
+u8 *pmussi_base;
+
+uint8_t hi6553_readb(u32 offset)
+{
+ return readb(pmussi_base + (offset << 2));
+}
+
+void hi6553_writeb(u32 offset, uint8_t value)
+{
+ writeb(value, pmussi_base + (offset << 2));
+}
+
+int pmic_reg_write(struct pmic *p, u32 reg, u32 val)
+{
+ if (check_reg(p, reg))
+ return -1;
+
+ hi6553_writeb(reg, (uint8_t)val);
+
+ return 0;
+}
+
+int pmic_reg_read(struct pmic *p, u32 reg, u32 *val)
+{
+ if (check_reg(p, reg))
+ return -1;
+
+ *val = (u32)hi6553_readb(reg);
+
+ return 0;
+}
+
+static void hi6553_init(void)
+{
+ int data;
+
+ hi6553_writeb(HI6553_PERI_EN_MARK, 0x1e);
+ hi6553_writeb(HI6553_NP_REG_ADJ1, 0);
+ data = HI6553_DISABLE6_XO_CLK_CONN | HI6553_DISABLE6_XO_CLK_NFC |
+ HI6553_DISABLE6_XO_CLK_RF1 | HI6553_DISABLE6_XO_CLK_RF2;
+ hi6553_writeb(HI6553_DISABLE6_XO_CLK, data);
+
+ /* configure BUCK0 & BUCK1 */
+ hi6553_writeb(HI6553_BUCK01_CTRL2, 0x5e);
+ hi6553_writeb(HI6553_BUCK0_CTRL7, 0x10);
+ hi6553_writeb(HI6553_BUCK1_CTRL7, 0x10);
+ hi6553_writeb(HI6553_BUCK0_CTRL5, 0x1e);
+ hi6553_writeb(HI6553_BUCK1_CTRL5, 0x1e);
+ hi6553_writeb(HI6553_BUCK0_CTRL1, 0xfc);
+ hi6553_writeb(HI6553_BUCK1_CTRL1, 0xfc);
+
+ /* configure BUCK2 */
+ hi6553_writeb(HI6553_BUCK2_REG1, 0x4f);
+ hi6553_writeb(HI6553_BUCK2_REG5, 0x99);
+ hi6553_writeb(HI6553_BUCK2_REG6, 0x45);
+ mdelay(1);
+ hi6553_writeb(HI6553_VSET_BUCK2_ADJ, 0x22);
+ mdelay(1);
+
+ /* configure BUCK3 */
+ hi6553_writeb(HI6553_BUCK3_REG3, 0x02);
+ hi6553_writeb(HI6553_BUCK3_REG5, 0x99);
+ hi6553_writeb(HI6553_BUCK3_REG6, 0x41);
+ hi6553_writeb(HI6553_VSET_BUCK3_ADJ, 0x02);
+ mdelay(1);
+
+ /* configure BUCK4 */
+ hi6553_writeb(HI6553_BUCK4_REG2, 0x9a);
+ hi6553_writeb(HI6553_BUCK4_REG5, 0x99);
+ hi6553_writeb(HI6553_BUCK4_REG6, 0x45);
+
+ /* configure LDO20 */
+ hi6553_writeb(HI6553_LDO20_REG_ADJ, 0x50);
+
+ hi6553_writeb(HI6553_NP_REG_CHG, 0x0f);
+ hi6553_writeb(HI6553_CLK_TOP0, 0x06);
+ hi6553_writeb(HI6553_CLK_TOP3, 0xc0);
+ hi6553_writeb(HI6553_CLK_TOP4, 0x00);
+
+ /* configure LDO7 & LDO10 for SD slot */
+ data = hi6553_readb(HI6553_LDO7_REG_ADJ);
+ data = (data & 0xf8) | 0x2;
+ hi6553_writeb(HI6553_LDO7_REG_ADJ, data);
+ mdelay(5);
+ /* enable LDO7 */
+ hi6553_writeb(HI6553_ENABLE2_LDO1_8, 1 << 6);
+ mdelay(5);
+ data = hi6553_readb(HI6553_LDO10_REG_ADJ);
+ data = (data & 0xf8) | 0x5;
+ hi6553_writeb(HI6553_LDO10_REG_ADJ, data);
+ mdelay(5);
+ /* enable LDO10 */
+ hi6553_writeb(HI6553_ENABLE3_LDO9_16, 1 << 1);
+ mdelay(5);
+
+ /* select 32.764KHz */
+ hi6553_writeb(HI6553_CLK19M2_600_586_EN, 0x01);
+}
+
+int power_hi6553_init(u8 *base)
+{
+ static const char name[] = "HI6553 PMIC";
+ struct pmic *p = pmic_alloc();
+
+ if (!p) {
+ printf("%s: POWER allocation error!\n", __func__);
+ return -ENOMEM;
+ }
+
+ p->name = name;
+ p->interface = PMIC_NONE;
+ p->number_of_regs = 44;
+ pmussi_base = base;
+
+ hi6553_init();
+
+ puts("HI6553 PMIC init\n");
+
+ return 0;
+}
diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig
index e85c692..77d64e43 100644
--- a/drivers/power/regulator/Kconfig
+++ b/drivers/power/regulator/Kconfig
@@ -16,6 +16,14 @@
for this purpose if PMIC I/O driver is implemented or dm_scan_fdt_node()
otherwise. Detailed information can be found in the header file.
+config DM_REGULATOR_PFUZE100
+ bool "Enable Driver Model for REGULATOR PFUZE100"
+ depends on DM_REGULATOR && DM_PMIC_PFUZE100
+ ---help---
+ This config enables implementation of driver-model regulator uclass
+ features for REGULATOR PFUZE100. The driver implements get/set api for:
+ value, enable and mode.
+
config DM_REGULATOR_MAX77686
bool "Enable Driver Model for REGULATOR MAX77686"
depends on DM_REGULATOR && DM_PMIC_MAX77686
diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile
index 08d7b0d..7035936 100644
--- a/drivers/power/regulator/Makefile
+++ b/drivers/power/regulator/Makefile
@@ -7,6 +7,7 @@
obj-$(CONFIG_DM_REGULATOR) += regulator-uclass.o
obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o
+obj-$(CONFIG_DM_REGULATOR_PFUZE100) += pfuze100.o
obj-$(CONFIG_DM_REGULATOR_FIXED) += fixed.o
obj-$(CONFIG_REGULATOR_S5M8767) += s5m8767.o
obj-$(CONFIG_DM_REGULATOR_SANDBOX) += sandbox.o
diff --git a/drivers/power/regulator/max77686.c b/drivers/power/regulator/max77686.c
index 946b87c..71678b6 100644
--- a/drivers/power/regulator/max77686.c
+++ b/drivers/power/regulator/max77686.c
@@ -87,8 +87,8 @@
* hex = (uV - 750000) / 50000. We assume that dynamic voltage
* scaling via GPIOs is not enabled and don't support that.
* If this is enabled then the driver will need to take that
- * into account anrd check different registers depending on
- * the current setting See the datasheet for details.
+ * into account and check different registers depending on
+ * the current setting. See the datasheet for details.
*/
hex = (uV - MAX77686_BUCK_UV_HMIN) / MAX77686_BUCK_UV_HSTEP;
hex_max = MAX77686_BUCK_VOLT_MAX_HEX;
@@ -319,9 +319,9 @@
static int max77686_ldo_val(struct udevice *dev, int op, int *uV)
{
- unsigned int ret, hex, adr;
+ unsigned int hex, adr;
unsigned char val;
- int ldo;
+ int ldo, ret;
if (op == PMIC_OP_GET)
*uV = 0;
@@ -360,9 +360,9 @@
static int max77686_buck_val(struct udevice *dev, int op, int *uV)
{
- unsigned int hex, ret, mask, adr;
+ unsigned int hex, mask, adr;
unsigned char val;
- int buck;
+ int buck, ret;
buck = dev->driver_data;
if (buck < 1 || buck > MAX77686_BUCK_NUM) {
@@ -414,9 +414,9 @@
static int max77686_ldo_mode(struct udevice *dev, int op, int *opmode)
{
- unsigned int ret, adr, mode;
+ unsigned int adr, mode;
unsigned char val;
- int ldo;
+ int ldo, ret;
if (op == PMIC_OP_GET)
*opmode = -EINVAL;
@@ -545,9 +545,9 @@
static int max77686_buck_mode(struct udevice *dev, int op, int *opmode)
{
- unsigned int ret, mask, adr, mode, mode_shift;
+ unsigned int mask, adr, mode, mode_shift;
unsigned char val;
- int buck;
+ int buck, ret;
buck = dev->driver_data;
if (buck < 1 || buck > MAX77686_BUCK_NUM) {
diff --git a/drivers/power/regulator/pfuze100.c b/drivers/power/regulator/pfuze100.c
new file mode 100644
index 0000000..4702161
--- /dev/null
+++ b/drivers/power/regulator/pfuze100.c
@@ -0,0 +1,568 @@
+#include <common.h>
+#include <fdtdec.h>
+#include <errno.h>
+#include <dm.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <power/pfuze100_pmic.h>
+
+/**
+ * struct pfuze100_regulator_desc - regulator descriptor
+ *
+ * @name: Identify name for the regulator.
+ * @type: Indicates the regulator type.
+ * @uV_step: Voltage increase for each selector.
+ * @vsel_reg: Register for adjust regulator voltage for normal.
+ * @vsel_mask: Mask bit for setting regulator voltage for normal.
+ * @stby_reg: Register for adjust regulator voltage for standby.
+ * @stby_mask: Mask bit for setting regulator voltage for standby.
+ * @volt_table: Voltage mapping table (if table based mapping).
+ * @voltage: Current voltage for REGULATOR_TYPE_FIXED type regulator.
+ */
+struct pfuze100_regulator_desc {
+ char *name;
+ enum regulator_type type;
+ unsigned int uV_step;
+ unsigned int vsel_reg;
+ unsigned int vsel_mask;
+ unsigned int stby_reg;
+ unsigned int stby_mask;
+ unsigned int *volt_table;
+ unsigned int voltage;
+};
+
+/**
+ * struct pfuze100_regulator_platdata - platform data for pfuze100
+ *
+ * @desc: Points the description entry of one regulator of pfuze100
+ */
+struct pfuze100_regulator_platdata {
+ struct pfuze100_regulator_desc *desc;
+};
+
+#define PFUZE100_FIXED_REG(_name, base, vol) \
+ { \
+ .name = #_name, \
+ .type = REGULATOR_TYPE_FIXED, \
+ .voltage = (vol), \
+ }
+
+#define PFUZE100_SW_REG(_name, base, step) \
+ { \
+ .name = #_name, \
+ .type = REGULATOR_TYPE_BUCK, \
+ .uV_step = (step), \
+ .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
+ .vsel_mask = 0x3F, \
+ .stby_reg = (base) + PFUZE100_STBY_OFFSET, \
+ .stby_mask = 0x3F, \
+ }
+
+#define PFUZE100_SWB_REG(_name, base, mask, step, voltages) \
+ { \
+ .name = #_name, \
+ .type = REGULATOR_TYPE_BUCK, \
+ .uV_step = (step), \
+ .vsel_reg = (base), \
+ .vsel_mask = (mask), \
+ .volt_table = (voltages), \
+ }
+
+#define PFUZE100_SNVS_REG(_name, base, mask, voltages) \
+ { \
+ .name = #_name, \
+ .type = REGULATOR_TYPE_OTHER, \
+ .vsel_reg = (base), \
+ .vsel_mask = (mask), \
+ .volt_table = (voltages), \
+ }
+
+#define PFUZE100_VGEN_REG(_name, base, step) \
+ { \
+ .name = #_name, \
+ .type = REGULATOR_TYPE_LDO, \
+ .uV_step = (step), \
+ .vsel_reg = (base), \
+ .vsel_mask = 0xF, \
+ .stby_reg = (base), \
+ .stby_mask = 0x20, \
+ }
+
+#define PFUZE3000_VCC_REG(_name, base, step) \
+ { \
+ .name = #_name, \
+ .type = REGULATOR_TYPE_LDO, \
+ .uV_step = (step), \
+ .vsel_reg = (base), \
+ .vsel_mask = 0x3, \
+ .stby_reg = (base), \
+ .stby_mask = 0x20, \
+}
+
+#define PFUZE3000_SW1_REG(_name, base, step) \
+ { \
+ .name = #_name, \
+ .type = REGULATOR_TYPE_BUCK, \
+ .uV_step = (step), \
+ .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
+ .vsel_mask = 0x1F, \
+ .stby_reg = (base) + PFUZE100_STBY_OFFSET, \
+ .stby_mask = 0x1F, \
+ }
+
+#define PFUZE3000_SW2_REG(_name, base, step) \
+ { \
+ .name = #_name, \
+ .type = REGULATOR_TYPE_BUCK, \
+ .uV_step = (step), \
+ .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
+ .vsel_mask = 0x7, \
+ .stby_reg = (base) + PFUZE100_STBY_OFFSET, \
+ .stby_mask = 0x7, \
+ }
+
+#define PFUZE3000_SW3_REG(_name, base, step) \
+ { \
+ .name = #_name, \
+ .type = REGULATOR_TYPE_BUCK, \
+ .uV_step = (step), \
+ .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
+ .vsel_mask = 0xF, \
+ .stby_reg = (base) + PFUZE100_STBY_OFFSET, \
+ .stby_mask = 0xF, \
+ }
+
+static unsigned int pfuze100_swbst[] = {
+ 5000000, 5050000, 5100000, 5150000
+};
+
+static unsigned int pfuze100_vsnvs[] = {
+ 1000000, 1100000, 1200000, 1300000, 1500000, 1800000, 3000000, -1
+};
+
+static unsigned int pfuze3000_vsnvs[] = {
+ -1, -1, -1, -1, -1, -1, 3000000, -1
+};
+
+static unsigned int pfuze3000_sw2lo[] = {
+ 1500000, 1550000, 1600000, 1650000, 1700000, 1750000, 1800000, 1850000
+};
+
+/* PFUZE100 */
+static struct pfuze100_regulator_desc pfuze100_regulators[] = {
+ PFUZE100_SW_REG(sw1ab, PFUZE100_SW1ABVOL, 25000),
+ PFUZE100_SW_REG(sw1c, PFUZE100_SW1CVOL, 25000),
+ PFUZE100_SW_REG(sw2, PFUZE100_SW2VOL, 25000),
+ PFUZE100_SW_REG(sw3a, PFUZE100_SW3AVOL, 25000),
+ PFUZE100_SW_REG(sw3b, PFUZE100_SW3BVOL, 25000),
+ PFUZE100_SW_REG(sw4, PFUZE100_SW4VOL, 25000),
+ PFUZE100_SWB_REG(swbst, PFUZE100_SWBSTCON1, 0x3, 50000, pfuze100_swbst),
+ PFUZE100_SNVS_REG(vsnvs, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
+ PFUZE100_FIXED_REG(vrefddr, PFUZE100_VREFDDRCON, 750000),
+ PFUZE100_VGEN_REG(vgen1, PFUZE100_VGEN1VOL, 50000),
+ PFUZE100_VGEN_REG(vgen2, PFUZE100_VGEN2VOL, 50000),
+ PFUZE100_VGEN_REG(vgen3, PFUZE100_VGEN3VOL, 100000),
+ PFUZE100_VGEN_REG(vgen4, PFUZE100_VGEN4VOL, 100000),
+ PFUZE100_VGEN_REG(vgen5, PFUZE100_VGEN5VOL, 100000),
+ PFUZE100_VGEN_REG(vgen6, PFUZE100_VGEN6VOL, 100000),
+};
+
+/* PFUZE200 */
+static struct pfuze100_regulator_desc pfuze200_regulators[] = {
+ PFUZE100_SW_REG(sw1ab, PFUZE100_SW1ABVOL, 25000),
+ PFUZE100_SW_REG(sw2, PFUZE100_SW2VOL, 25000),
+ PFUZE100_SW_REG(sw3a, PFUZE100_SW3AVOL, 25000),
+ PFUZE100_SW_REG(sw3b, PFUZE100_SW3BVOL, 25000),
+ PFUZE100_SWB_REG(swbst, PFUZE100_SWBSTCON1, 0x3, 50000, pfuze100_swbst),
+ PFUZE100_SNVS_REG(vsnvs, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
+ PFUZE100_FIXED_REG(vrefddr, PFUZE100_VREFDDRCON, 750000),
+ PFUZE100_VGEN_REG(vgen1, PFUZE100_VGEN1VOL, 50000),
+ PFUZE100_VGEN_REG(vgen2, PFUZE100_VGEN2VOL, 50000),
+ PFUZE100_VGEN_REG(vgen3, PFUZE100_VGEN3VOL, 100000),
+ PFUZE100_VGEN_REG(vgen4, PFUZE100_VGEN4VOL, 100000),
+ PFUZE100_VGEN_REG(vgen5, PFUZE100_VGEN5VOL, 100000),
+ PFUZE100_VGEN_REG(vgen6, PFUZE100_VGEN6VOL, 100000),
+};
+
+/* PFUZE3000 */
+static struct pfuze100_regulator_desc pfuze3000_regulators[] = {
+ PFUZE3000_SW1_REG(sw1a, PFUZE100_SW1ABVOL, 25000),
+ PFUZE3000_SW1_REG(sw1b, PFUZE100_SW1CVOL, 25000),
+ PFUZE100_SWB_REG(sw2, PFUZE100_SW2VOL, 0x7, 50000, pfuze3000_sw2lo),
+ PFUZE3000_SW3_REG(sw3, PFUZE100_SW3AVOL, 50000),
+ PFUZE100_SWB_REG(swbst, PFUZE100_SWBSTCON1, 0x3, 50000, pfuze100_swbst),
+ PFUZE100_SNVS_REG(vsnvs, PFUZE100_VSNVSVOL, 0x7, pfuze3000_vsnvs),
+ PFUZE100_FIXED_REG(vrefddr, PFUZE100_VREFDDRCON, 750000),
+ PFUZE100_VGEN_REG(vldo1, PFUZE100_VGEN1VOL, 100000),
+ PFUZE100_VGEN_REG(vldo2, PFUZE100_VGEN2VOL, 50000),
+ PFUZE3000_VCC_REG(vccsd, PFUZE100_VGEN3VOL, 150000),
+ PFUZE3000_VCC_REG(v33, PFUZE100_VGEN4VOL, 150000),
+ PFUZE100_VGEN_REG(vldo3, PFUZE100_VGEN5VOL, 100000),
+ PFUZE100_VGEN_REG(vldo4, PFUZE100_VGEN6VOL, 100000),
+};
+
+#define MODE(_id, _val, _name) { \
+ .id = _id, \
+ .register_value = _val, \
+ .name = _name, \
+}
+
+/* SWx Buck regulator mode */
+static struct dm_regulator_mode pfuze_sw_modes[] = {
+ MODE(OFF_OFF, OFF_OFF, "OFF_OFF"),
+ MODE(PWM_OFF, PWM_OFF, "PWM_OFF"),
+ MODE(PFM_OFF, PFM_OFF, "PFM_OFF"),
+ MODE(APS_OFF, APS_OFF, "APS_OFF"),
+ MODE(PWM_PWM, PWM_PWM, "PWM_PWM"),
+ MODE(PWM_APS, PWM_APS, "PWM_APS"),
+ MODE(APS_APS, APS_APS, "APS_APS"),
+ MODE(APS_PFM, APS_PFM, "APS_PFM"),
+ MODE(PWM_PFM, PWM_PFM, "PWM_PFM"),
+};
+
+/* Boost Buck regulator mode for normal operation */
+static struct dm_regulator_mode pfuze_swbst_modes[] = {
+ MODE(SWBST_MODE_OFF, SWBST_MODE_OFF , "SWBST_MODE_OFF"),
+ MODE(SWBST_MODE_PFM, SWBST_MODE_PFM, "SWBST_MODE_PFM"),
+ MODE(SWBST_MODE_AUTO, SWBST_MODE_AUTO, "SWBST_MODE_AUTO"),
+ MODE(SWBST_MODE_APS, SWBST_MODE_APS, "SWBST_MODE_APS"),
+};
+
+/* VGENx LDO regulator mode for normal operation */
+static struct dm_regulator_mode pfuze_ldo_modes[] = {
+ MODE(LDO_MODE_OFF, LDO_MODE_OFF, "LDO_MODE_OFF"),
+ MODE(LDO_MODE_ON, LDO_MODE_ON, "LDO_MODE_ON"),
+};
+
+static struct pfuze100_regulator_desc *se_desc(struct pfuze100_regulator_desc *desc,
+ int size,
+ const char *name)
+{
+ int i;
+
+ for (i = 0; i < size; desc++) {
+ if (!strcmp(desc->name, name))
+ return desc;
+ continue;
+ }
+
+ return NULL;
+}
+
+static int pfuze100_regulator_probe(struct udevice *dev)
+{
+ struct dm_regulator_uclass_platdata *uc_pdata;
+ struct pfuze100_regulator_platdata *plat = dev_get_platdata(dev);
+ struct pfuze100_regulator_desc *desc;
+
+ switch (dev_get_driver_data(dev_get_parent(dev))) {
+ case PFUZE100:
+ desc = se_desc(pfuze100_regulators,
+ ARRAY_SIZE(pfuze100_regulators),
+ dev->name);
+ break;
+ case PFUZE200:
+ desc = se_desc(pfuze200_regulators,
+ ARRAY_SIZE(pfuze200_regulators),
+ dev->name);
+ break;
+ case PFUZE3000:
+ desc = se_desc(pfuze3000_regulators,
+ ARRAY_SIZE(pfuze3000_regulators),
+ dev->name);
+ break;
+ default:
+ debug("Unsupported PFUZE\n");
+ return -EINVAL;
+ }
+ if (!desc) {
+ debug("Do not support regulator %s\n", dev->name);
+ return -EINVAL;
+ }
+
+ plat->desc = desc;
+ uc_pdata = dev_get_uclass_platdata(dev);
+
+ uc_pdata->type = desc->type;
+ if (uc_pdata->type == REGULATOR_TYPE_BUCK) {
+ if (!strcmp(dev->name, "swbst")) {
+ uc_pdata->mode = pfuze_swbst_modes;
+ uc_pdata->mode_count = ARRAY_SIZE(pfuze_swbst_modes);
+ } else {
+ uc_pdata->mode = pfuze_sw_modes;
+ uc_pdata->mode_count = ARRAY_SIZE(pfuze_sw_modes);
+ }
+ } else if (uc_pdata->type == REGULATOR_TYPE_LDO) {
+ uc_pdata->mode = pfuze_ldo_modes;
+ uc_pdata->mode_count = ARRAY_SIZE(pfuze_ldo_modes);
+ } else {
+ uc_pdata->mode = NULL;
+ uc_pdata->mode_count = 0;
+ }
+
+ return 0;
+}
+
+static int pfuze100_regulator_mode(struct udevice *dev, int op, int *opmode)
+{
+ unsigned char val;
+ struct pfuze100_regulator_platdata *plat = dev_get_platdata(dev);
+ struct pfuze100_regulator_desc *desc = plat->desc;
+
+ if (op == PMIC_OP_GET) {
+ if (desc->type == REGULATOR_TYPE_BUCK) {
+ if (!strcmp(dev->name, "swbst")) {
+ val = pmic_reg_read(dev->parent,
+ desc->vsel_reg);
+ if (val < 0)
+ return val;
+
+ val &= SWBST_MODE_MASK;
+ val >>= SWBST_MODE_SHIFT;
+ *opmode = val;
+
+ return 0;
+ }
+ val = pmic_reg_read(dev->parent,
+ desc->vsel_reg +
+ PFUZE100_MODE_OFFSET);
+ if (val < 0)
+ return val;
+
+ val &= SW_MODE_MASK;
+ val >>= SW_MODE_SHIFT;
+ *opmode = val;
+
+ return 0;
+
+ } else if (desc->type == REGULATOR_TYPE_LDO) {
+ val = pmic_reg_read(dev->parent, desc->vsel_reg);
+ if (val < 0)
+ return val;
+
+ val &= LDO_MODE_MASK;
+ val >>= LDO_MODE_SHIFT;
+ *opmode = val;
+
+ return 0;
+ } else {
+ return -EINVAL;
+ }
+ }
+
+ if (desc->type == REGULATOR_TYPE_BUCK) {
+ if (!strcmp(dev->name, "swbst"))
+ return pmic_clrsetbits(dev->parent, desc->vsel_reg,
+ SWBST_MODE_MASK,
+ *opmode << SWBST_MODE_SHIFT);
+
+ val = pmic_clrsetbits(dev->parent,
+ desc->vsel_reg + PFUZE100_MODE_OFFSET,
+ SW_MODE_MASK,
+ *opmode << SW_MODE_SHIFT);
+
+ } else if (desc->type == REGULATOR_TYPE_LDO) {
+ val = pmic_clrsetbits(dev->parent, desc->vsel_reg,
+ LDO_MODE_MASK,
+ *opmode << LDO_MODE_SHIFT);
+ return val;
+ } else {
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int pfuze100_regulator_enable(struct udevice *dev, int op, bool *enable)
+{
+ unsigned char val;
+ int ret, on_off;
+ struct dm_regulator_uclass_platdata *uc_pdata =
+ dev_get_uclass_platdata(dev);
+
+ if (op == PMIC_OP_GET) {
+ if (!strcmp(dev->name, "vrefddr")) {
+ val = pmic_reg_read(dev->parent, PFUZE100_VREFDDRCON);
+ if (val < 0)
+ return val;
+
+ if (val & VREFDDRCON_EN)
+ *enable = true;
+ else
+ *enable = false;
+ return 0;
+ }
+ ret = pfuze100_regulator_mode(dev, op, &on_off);
+ if (ret)
+ return ret;
+ switch (on_off) {
+ /* OFF_OFF, SWBST_MODE_OFF, LDO_MODE_OFF have same value */
+ case OFF_OFF:
+ *enable = false;
+ break;
+ default:
+ *enable = true;
+ break;
+ }
+ } else if (op == PMIC_OP_SET) {
+ if (!strcmp(dev->name, "vrefddr")) {
+ val = pmic_reg_read(dev->parent, PFUZE100_VREFDDRCON);
+ if (val < 0)
+ return val;
+
+ if (val & VREFDDRCON_EN)
+ return 0;
+ val |= VREFDDRCON_EN;
+
+ return pmic_reg_write(dev->parent, PFUZE100_VREFDDRCON,
+ val);
+ }
+
+ if (uc_pdata->type == REGULATOR_TYPE_LDO) {
+ on_off = *enable ? LDO_MODE_ON : LDO_MODE_OFF;
+ } else if (uc_pdata->type == REGULATOR_TYPE_BUCK) {
+ if (!strcmp(dev->name, "swbst"))
+ on_off = *enable ? SWBST_MODE_AUTO :
+ SWBST_MODE_OFF;
+ else
+ on_off = *enable ? APS_PFM : OFF_OFF;
+ } else {
+ return -EINVAL;
+ }
+
+ return pfuze100_regulator_mode(dev, op, &on_off);
+ }
+
+ return 0;
+}
+
+static int pfuze100_regulator_val(struct udevice *dev, int op, int *uV)
+{
+ int i;
+ unsigned char val;
+ struct pfuze100_regulator_platdata *plat = dev_get_platdata(dev);
+ struct pfuze100_regulator_desc *desc = plat->desc;
+ struct dm_regulator_uclass_platdata *uc_pdata =
+ dev_get_uclass_platdata(dev);
+
+ if (op == PMIC_OP_GET) {
+ *uV = 0;
+ if (uc_pdata->type == REGULATOR_TYPE_FIXED) {
+ *uV = desc->voltage;
+ } else if (desc->volt_table) {
+ val = pmic_reg_read(dev->parent, desc->vsel_reg);
+ if (val < 0)
+ return val;
+ val &= desc->vsel_mask;
+ *uV = desc->volt_table[val];
+ } else {
+ if (uc_pdata->min_uV < 0) {
+ debug("Need to provide min_uV in dts.\n");
+ return -EINVAL;
+ }
+ val = pmic_reg_read(dev->parent, desc->vsel_reg);
+ if (val < 0)
+ return val;
+ val &= desc->vsel_mask;
+ *uV = uc_pdata->min_uV + (int)val * desc->uV_step;
+ }
+
+ return 0;
+ }
+
+ if (uc_pdata->type == REGULATOR_TYPE_FIXED) {
+ debug("Set voltage for REGULATOR_TYPE_FIXED regulator\n");
+ return -EINVAL;
+ } else if (desc->volt_table) {
+ for (i = 0; i < desc->vsel_mask; i++) {
+ if (*uV == desc->volt_table[i])
+ break;
+ }
+ if (i == desc->vsel_mask) {
+ debug("Unsupported voltage %u\n", *uV);
+ return -EINVAL;
+ }
+
+ return pmic_clrsetbits(dev->parent, desc->vsel_reg,
+ desc->vsel_mask, i);
+ } else {
+ if (uc_pdata->min_uV < 0) {
+ debug("Need to provide min_uV in dts.\n");
+ return -EINVAL;
+ }
+ return pmic_clrsetbits(dev->parent, desc->vsel_reg,
+ desc->vsel_mask,
+ (*uV - uc_pdata->min_uV) / desc->uV_step);
+ }
+
+ return 0;
+}
+
+static int pfuze100_regulator_get_value(struct udevice *dev)
+{
+ int uV;
+ int ret;
+
+ ret = pfuze100_regulator_val(dev, PMIC_OP_GET, &uV);
+ if (ret)
+ return ret;
+
+ return uV;
+}
+
+static int pfuze100_regulator_set_value(struct udevice *dev, int uV)
+{
+ return pfuze100_regulator_val(dev, PMIC_OP_SET, &uV);
+}
+
+static bool pfuze100_regulator_get_enable(struct udevice *dev)
+{
+ int ret;
+ bool enable = false;
+
+ ret = pfuze100_regulator_enable(dev, PMIC_OP_GET, &enable);
+ if (ret)
+ return ret;
+
+ return enable;
+}
+
+static int pfuze100_regulator_set_enable(struct udevice *dev, bool enable)
+{
+ return pfuze100_regulator_enable(dev, PMIC_OP_SET, &enable);
+}
+
+static int pfuze100_regulator_get_mode(struct udevice *dev)
+{
+ int mode;
+ int ret;
+
+ ret = pfuze100_regulator_mode(dev, PMIC_OP_GET, &mode);
+ if (ret)
+ return ret;
+
+ return mode;
+}
+
+static int pfuze100_regulator_set_mode(struct udevice *dev, int mode)
+{
+ return pfuze100_regulator_mode(dev, PMIC_OP_SET, &mode);
+}
+
+static const struct dm_regulator_ops pfuze100_regulator_ops = {
+ .get_value = pfuze100_regulator_get_value,
+ .set_value = pfuze100_regulator_set_value,
+ .get_enable = pfuze100_regulator_get_enable,
+ .set_enable = pfuze100_regulator_set_enable,
+ .get_mode = pfuze100_regulator_get_mode,
+ .set_mode = pfuze100_regulator_set_mode,
+};
+
+U_BOOT_DRIVER(pfuze100_regulator) = {
+ .name = "pfuze100_regulator",
+ .id = UCLASS_REGULATOR,
+ .ops = &pfuze100_regulator_ops,
+ .probe = pfuze100_regulator_probe,
+ .platdata_auto_alloc_size = sizeof(struct pfuze100_regulator_platdata),
+};
diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c
index f3fe7a5..a5170df 100644
--- a/drivers/power/regulator/regulator-uclass.c
+++ b/drivers/power/regulator/regulator-uclass.c
@@ -256,7 +256,9 @@
if (!uc_pdata->name) {
debug("%s: dev: %s has no property 'regulator-name'\n",
__func__, dev->name);
- return -EINVAL;
+ uc_pdata->name = fdt_get_name(blob, offset, NULL);
+ if (!uc_pdata->name)
+ return -EINVAL;
}
if (regulator_name_is_unique(dev, uc_pdata->name))
diff --git a/drivers/power/twl4030.c b/drivers/power/twl4030.c
index 7f1fdd1..8866bf1 100644
--- a/drivers/power/twl4030.c
+++ b/drivers/power/twl4030.c
@@ -46,6 +46,66 @@
}
/*
+ * Power off
+ */
+void twl4030_power_off(void)
+{
+ u8 data;
+
+ /* PM master unlock (CFG and TST keys) */
+
+ data = 0xCE;
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+ TWL4030_PM_MASTER_PROTECT_KEY, data);
+ data = 0xEC;
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+ TWL4030_PM_MASTER_PROTECT_KEY, data);
+
+ /* VBAT start disable */
+
+ twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER,
+ TWL4030_PM_MASTER_CFG_P1_TRANSITION, &data);
+ data &= ~TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_VBAT;
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+ TWL4030_PM_MASTER_CFG_P1_TRANSITION, data);
+
+ twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER,
+ TWL4030_PM_MASTER_CFG_P2_TRANSITION, &data);
+ data &= ~TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_VBAT;
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+ TWL4030_PM_MASTER_CFG_P2_TRANSITION, data);
+
+ twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER,
+ TWL4030_PM_MASTER_CFG_P3_TRANSITION, &data);
+ data &= ~TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_VBAT;
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+ TWL4030_PM_MASTER_CFG_P3_TRANSITION, data);
+
+ /* High jitter for PWRANA2 */
+
+ twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER,
+ TWL4030_PM_MASTER_CFG_PWRANA2, &data);
+ data &= ~(TWL4030_PM_MASTER_CFG_PWRANA2_LOJIT0_LOWV |
+ TWL4030_PM_MASTER_CFG_PWRANA2_LOJIT1_LOWV);
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+ TWL4030_PM_MASTER_CFG_PWRANA2, data);
+
+ /* PM master lock */
+
+ data = 0xFF;
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+ TWL4030_PM_MASTER_PROTECT_KEY, data);
+
+ /* Power off */
+
+ twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER,
+ TWL4030_PM_MASTER_P1_SW_EVENTS, &data);
+ data |= TWL4030_PM_MASTER_SW_EVENTS_DEVOFF;
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+ TWL4030_PM_MASTER_P1_SW_EVENTS, data);
+}
+
+/*
* Set Device Group and Voltage
*/
void twl4030_pmrecv_vsel_cfg(u8 vsel_reg, u8 vsel_val,
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index bd63621..b5d9048 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -1,3 +1,9 @@
+#
+# RTC drivers configuration
+#
+
+menu "Real Time Clock"
+
config DM_RTC
bool "Enable Driver Model for RTC drivers"
depends on DM
@@ -6,3 +12,5 @@
then provides the rtc_get()/rtc_set() interface, delegating to
drivers to perform the actual functions. See rtc.h for a
description of the API.
+
+endmenu
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index a880eac..4f6a3b8 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -1,3 +1,9 @@
+#
+# Serial device configuration
+#
+
+menu "Serial drivers"
+
config REQUIRE_SERIAL_CONSOLE
bool "Require a serial port for console"
# Running without a serial console is not supported by the
@@ -139,3 +145,5 @@
enabled in the device tree with the correct input clock frequency
provided (default 1843200). Enable this to obtain serial console
output.
+
+endmenu
diff --git a/drivers/serial/serial_omap.c b/drivers/serial/serial_omap.c
index 265fe00..325fe42 100644
--- a/drivers/serial/serial_omap.c
+++ b/drivers/serial/serial_omap.c
@@ -15,6 +15,7 @@
#ifdef CONFIG_OF_CONTROL
static const struct udevice_id omap_serial_ids[] = {
{ .compatible = "ti,omap3-uart" },
+ { .compatible = "ti,omap4-uart" },
{ }
};
diff --git a/drivers/sound/Kconfig b/drivers/sound/Kconfig
index 3b96e84..5de86c0 100644
--- a/drivers/sound/Kconfig
+++ b/drivers/sound/Kconfig
@@ -1,3 +1,5 @@
+menu "Sound support"
+
config SOUND
bool "Enable sound support"
help
@@ -53,3 +55,5 @@
Enable the wm8994 audio codec. This is connected via I2S for
audio data and I2C for codec control. At present it only works
with the Samsung I2S driver.
+
+endmenu
diff --git a/drivers/spi/omap3_spi.h b/drivers/spi/omap3_spi.h
index ab7cd84..4af22c1 100644
--- a/drivers/spi/omap3_spi.h
+++ b/drivers/spi/omap3_spi.h
@@ -14,7 +14,7 @@
#ifndef _OMAP3_SPI_H_
#define _OMAP3_SPI_H_
-#ifdef CONFIG_AM33XX
+#if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
#define OMAP3_MCSPI1_BASE 0x48030100
#define OMAP3_MCSPI2_BASE 0x481A0100
#else
diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index 702ef63..09f91f1 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -27,8 +27,8 @@
struct dwc2_priv {
#ifdef CONFIG_DM_USB
- uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(8);
- uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(8);
+ uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
+ uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
#else
uint8_t *aligned_buffer;
uint8_t *status_buffer;
@@ -39,9 +39,11 @@
};
#ifndef CONFIG_DM_USB
-/* We need doubleword-aligned buffers for DMA transfers */
-DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE, 8);
-DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE, 8);
+/* We need cacheline-aligned buffers for DMA transfers and dcache support */
+DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE,
+ ARCH_DMA_MINALIGN);
+DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE,
+ ARCH_DMA_MINALIGN);
static struct dwc2_priv local;
#endif
@@ -821,8 +823,11 @@
&hc_regs->hctsiz);
if (!in) {
- memcpy(priv->aligned_buffer, (char *)buffer + done,
- len);
+ memcpy(priv->aligned_buffer, (char *)buffer + done, len);
+
+ flush_dcache_range((unsigned long)priv->aligned_buffer,
+ (unsigned long)((void *)priv->aligned_buffer +
+ roundup(len, ARCH_DMA_MINALIGN)));
}
writel(phys_to_bus((unsigned long)priv->aligned_buffer),
@@ -840,6 +845,11 @@
if (in) {
xfer_len -= sub;
+
+ invalidate_dcache_range((unsigned long)priv->aligned_buffer,
+ (unsigned long)((void *)priv->aligned_buffer +
+ roundup(xfer_len, ARCH_DMA_MINALIGN)));
+
memcpy(buffer + done, priv->aligned_buffer, xfer_len);
if (sub)
stop_transfer = 1;
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index 691ed1c..0ffd838 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -105,21 +105,13 @@
# define m32_swap(x) cpu_to_le32(x)
#endif /* CONFIG_SYS_OHCI_BE_CONTROLLER */
-#ifdef CONFIG_DM_USB
-/*
- * We really should do proper cache flushing everywhere, but for now we only
- * do it for new (driver-model) usb code to avoid regressions.
- */
+/* We really should do proper cache flushing everywhere */
#define flush_dcache_buffer(addr, size) \
flush_dcache_range((unsigned long)(addr), \
ALIGN((unsigned long)(addr) + size, ARCH_DMA_MINALIGN))
#define invalidate_dcache_buffer(addr, size) \
invalidate_dcache_range((unsigned long)(addr), \
ALIGN((unsigned long)(addr) + size, ARCH_DMA_MINALIGN))
-#else
-#define flush_dcache_buffer(addr, size)
-#define invalidate_dcache_buffer(addr, size)
-#endif
/* Do not use sizeof(ed / td) as our ed / td structs contain extra members */
#define flush_dcache_ed(addr) flush_dcache_buffer(addr, 16)
@@ -763,12 +755,10 @@
if (((struct ed *)
m32_swap((unsigned long)ed_p)) == ed) {
*ed_p = ed->hwNextED;
-#ifdef CONFIG_DM_USB
aligned_ed_p = (unsigned long)ed_p;
aligned_ed_p &= ~(ARCH_DMA_MINALIGN - 1);
flush_dcache_range(aligned_ed_p,
aligned_ed_p + ARCH_DMA_MINALIGN);
-#endif
break;
}
ed_p = &(((struct ed *)
diff --git a/drivers/usb/host/ohci.h b/drivers/usb/host/ohci.h
index f1526d4..9b0c4a2 100644
--- a/drivers/usb/host/ohci.h
+++ b/drivers/usb/host/ohci.h
@@ -18,7 +18,7 @@
# define ohci_writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a))
#endif /* CONFIG_SYS_OHCI_SWAP_REG_ACCESS */
-#if defined CONFIG_DM_USB && ARCH_DMA_MINALIGN > 16
+#if ARCH_DMA_MINALIGN > 16
#define ED_ALIGNMENT ARCH_DMA_MINALIGN
#else
#define ED_ALIGNMENT 16
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 3244cd7..5cb3685 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -1,3 +1,9 @@
+#
+# Video configuration
+#
+
+menu "Graphics support"
+
config VIDEO_VESA
bool "Enable VESA video driver support"
default n
@@ -242,3 +248,5 @@
have an eDP display connected.
source "drivers/video/bridge/Kconfig"
+
+endmenu
diff --git a/drivers/video/bcm2835.c b/drivers/video/bcm2835.c
index 1f18231..61d054d 100644
--- a/drivers/video/bcm2835.c
+++ b/drivers/video/bcm2835.c
@@ -38,8 +38,8 @@
void lcd_ctrl_init(void *lcdbase)
{
- ALLOC_ALIGN_BUFFER(struct msg_query, msg_query, 1, 16);
- ALLOC_ALIGN_BUFFER(struct msg_setup, msg_setup, 1, 16);
+ ALLOC_CACHE_ALIGN_BUFFER(struct msg_query, msg_query, 1);
+ ALLOC_CACHE_ALIGN_BUFFER(struct msg_setup, msg_setup, 1);
int ret;
u32 w, h;
diff --git a/fs/fs.c b/fs/fs.c
index ac0897d..827b143 100644
--- a/fs/fs.c
+++ b/fs/fs.c
@@ -301,10 +301,8 @@
unmap_sysmem(buf);
/* If we requested a specific number of bytes, check we got it */
- if (ret == 0 && len && *actread != len) {
- printf("** Unable to read file %s **\n", filename);
- ret = -1;
- }
+ if (ret == 0 && len && *actread != len)
+ printf("** %s shorter than offset + len **\n", filename);
fs_close();
return ret;
diff --git a/fs/jffs2/Makefile b/fs/jffs2/Makefile
index 4cb0600..3625d74 100644
--- a/fs/jffs2/Makefile
+++ b/fs/jffs2/Makefile
@@ -10,4 +10,5 @@
obj-y += compr_rubin.o
obj-y += compr_zlib.o
obj-y += jffs2_1pass.o
+obj-$(CONFIG_SYS_JFFS2_SORT_FRAGMENTS) += mergesort.o
obj-y += mini_inflate.o
diff --git a/fs/jffs2/jffs2_1pass.c b/fs/jffs2/jffs2_1pass.c
index b1d6470..64f5542 100644
--- a/fs/jffs2/jffs2_1pass.c
+++ b/fs/jffs2/jffs2_1pass.c
@@ -545,49 +545,19 @@
insert_node(struct b_list *list, u32 offset)
{
struct b_node *new;
-#ifdef CONFIG_SYS_JFFS2_SORT_FRAGMENTS
- struct b_node *b, *prev;
-#endif
if (!(new = add_node(list))) {
putstr("add_node failed!\r\n");
return NULL;
}
new->offset = offset;
+ new->next = NULL;
-#ifdef CONFIG_SYS_JFFS2_SORT_FRAGMENTS
- if (list->listTail != NULL && list->listCompare(new, list->listTail))
- prev = list->listTail;
- else if (list->listLast != NULL && list->listCompare(new, list->listLast))
- prev = list->listLast;
+ if (list->listTail != NULL)
+ list->listTail->next = new;
else
- prev = NULL;
-
- for (b = (prev ? prev->next : list->listHead);
- b != NULL && list->listCompare(new, b);
- prev = b, b = b->next) {
- list->listLoops++;
- }
- if (b != NULL)
- list->listLast = prev;
-
- if (b != NULL) {
- new->next = b;
- if (prev != NULL)
- prev->next = new;
- else
- list->listHead = new;
- } else
-#endif
- {
- new->next = (struct b_node *) NULL;
- if (list->listTail != NULL) {
- list->listTail->next = new;
- list->listTail = new;
- } else {
- list->listTail = list->listHead = new;
- }
- }
+ list->listHead = new;
+ list->listTail = new;
return new;
}
@@ -598,14 +568,18 @@
*/
static int compare_inodes(struct b_node *new, struct b_node *old)
{
- struct jffs2_raw_inode ojNew;
- struct jffs2_raw_inode ojOld;
- struct jffs2_raw_inode *jNew =
- (struct jffs2_raw_inode *)get_fl_mem(new->offset, sizeof(ojNew), &ojNew);
- struct jffs2_raw_inode *jOld =
- (struct jffs2_raw_inode *)get_fl_mem(old->offset, sizeof(ojOld), &ojOld);
+ /*
+ * Only read in the version info from flash, not the entire inode.
+ * This can make a big difference to speed if flash is slow.
+ */
+ u32 new_version;
+ u32 old_version;
+ get_fl_mem(new->offset + offsetof(struct jffs2_raw_inode, version),
+ sizeof(new_version), &new_version);
+ get_fl_mem(old->offset + offsetof(struct jffs2_raw_inode, version),
+ sizeof(old_version), &old_version);
- return jNew->version > jOld->version;
+ return new_version > old_version;
}
/* Sort directory entries so all entries in the same directory
@@ -615,42 +589,45 @@
*/
static int compare_dirents(struct b_node *new, struct b_node *old)
{
- struct jffs2_raw_dirent ojNew;
- struct jffs2_raw_dirent ojOld;
- struct jffs2_raw_dirent *jNew =
- (struct jffs2_raw_dirent *)get_fl_mem(new->offset, sizeof(ojNew), &ojNew);
- struct jffs2_raw_dirent *jOld =
- (struct jffs2_raw_dirent *)get_fl_mem(old->offset, sizeof(ojOld), &ojOld);
- int cmp;
-
- /* ascending sort by pino */
- if (jNew->pino != jOld->pino)
- return jNew->pino > jOld->pino;
-
- /* pino is the same, so use ascending sort by nsize, so
- * we don't do strncmp unless we really must.
+ /*
+ * Using NULL as the buffer for NOR flash prevents the entire node
+ * being read. This makes most comparisons much quicker as only one
+ * or two entries from the node will be used most of the time.
*/
- if (jNew->nsize != jOld->nsize)
- return jNew->nsize > jOld->nsize;
-
- /* length is also the same, so use ascending sort by name
- */
- cmp = strncmp((char *)jNew->name, (char *)jOld->name, jNew->nsize);
- if (cmp != 0)
- return cmp > 0;
+ struct jffs2_raw_dirent *jNew = get_node_mem(new->offset, NULL);
+ struct jffs2_raw_dirent *jOld = get_node_mem(old->offset, NULL);
+ int cmp;
+ int ret;
- /* we have duplicate names in this directory, so use ascending
- * sort by version
- */
- if (jNew->version > jOld->version) {
- /* since jNew is newer, we know jOld is not valid, so
- * mark it with inode 0 and it will not be used
+ if (jNew->pino != jOld->pino) {
+ /* ascending sort by pino */
+ ret = jNew->pino > jOld->pino;
+ } else if (jNew->nsize != jOld->nsize) {
+ /*
+ * pino is the same, so use ascending sort by nsize,
+ * so we don't do strncmp unless we really must.
*/
- jOld->ino = 0;
- return 1;
+ ret = jNew->nsize > jOld->nsize;
+ } else {
+ /*
+ * length is also the same, so use ascending sort by name
+ */
+ cmp = strncmp((char *)jNew->name, (char *)jOld->name,
+ jNew->nsize);
+ if (cmp != 0) {
+ ret = cmp > 0;
+ } else {
+ /*
+ * we have duplicate names in this directory,
+ * so use ascending sort by version
+ */
+ ret = jNew->version > jOld->version;
+ }
}
+ put_fl_mem(jNew, NULL);
+ put_fl_mem(jOld, NULL);
- return 0;
+ return ret;
}
#endif
@@ -719,11 +696,22 @@
}
put_fl_mem(jNode, pL->readbuf);
}
+ /*
+ * If no destination is provided, we are done.
+ * Just return the total size.
+ */
+ if (!dest)
+ return totalSize;
#endif
for (b = pL->frag.listHead; b != NULL; b = b->next) {
- jNode = (struct jffs2_raw_inode *) get_node_mem(b->offset,
- pL->readbuf);
+ /*
+ * Copy just the node and not the data at this point,
+ * since we don't yet know if we need this data.
+ */
+ jNode = (struct jffs2_raw_inode *)get_fl_mem(b->offset,
+ sizeof(struct jffs2_raw_inode),
+ pL->readbuf);
if (inode == jNode->ino) {
#if 0
putLabeledWord("\r\n\r\nread_inode: totlen = ", jNode->totlen);
@@ -747,7 +735,15 @@
#endif
if(dest) {
- src = ((uchar *) jNode) + sizeof(struct jffs2_raw_inode);
+ /*
+ * Now that the inode has been checked,
+ * read the entire inode, including data.
+ */
+ put_fl_mem(jNode, pL->readbuf);
+ jNode = (struct jffs2_raw_inode *)
+ get_node_mem(b->offset, pL->readbuf);
+ src = ((uchar *)jNode) +
+ sizeof(struct jffs2_raw_inode);
/* ignore data behind latest known EOF */
if (jNode->offset > totalSize) {
put_fl_mem(jNode, pL->readbuf);
@@ -832,7 +828,6 @@
jDir = (struct jffs2_raw_dirent *) get_node_mem(b->offset,
pL->readbuf);
if ((pino == jDir->pino) && (len == jDir->nsize) &&
- (jDir->ino) && /* 0 for unlink */
(!strncmp((char *)jDir->name, name, len))) { /* a match */
if (jDir->version < version) {
put_fl_mem(jDir, pL->readbuf);
@@ -953,16 +948,47 @@
for (b = pL->dir.listHead; b; b = b->next) {
jDir = (struct jffs2_raw_dirent *) get_node_mem(b->offset,
pL->readbuf);
- if ((pino == jDir->pino) && (jDir->ino)) { /* ino=0 -> unlink */
+ if (pino == jDir->pino) {
u32 i_version = 0;
- struct jffs2_raw_inode ojNode;
struct jffs2_raw_inode *jNode, *i = NULL;
- struct b_node *b2 = pL->frag.listHead;
+ struct b_node *b2;
+
+#ifdef CONFIG_SYS_JFFS2_SORT_FRAGMENTS
+ /* Check for more recent versions of this file */
+ int match;
+ do {
+ struct b_node *next = b->next;
+ struct jffs2_raw_dirent *jDirNext;
+ if (!next)
+ break;
+ jDirNext = (struct jffs2_raw_dirent *)
+ get_node_mem(next->offset, NULL);
+ match = jDirNext->pino == jDir->pino &&
+ jDirNext->nsize == jDir->nsize &&
+ strncmp((char *)jDirNext->name,
+ (char *)jDir->name,
+ jDir->nsize) == 0;
+ if (match) {
+ /* Use next. It is more recent */
+ b = next;
+ /* Update buffer with the new info */
+ *jDir = *jDirNext;
+ }
+ put_fl_mem(jDirNext, NULL);
+ } while (match);
+#endif
+ if (jDir->ino == 0) {
+ /* Deleted file */
+ put_fl_mem(jDir, pL->readbuf);
+ continue;
+ }
- while (b2) {
+ for (b2 = pL->frag.listHead; b2; b2 = b2->next) {
jNode = (struct jffs2_raw_inode *)
- get_fl_mem(b2->offset, sizeof(ojNode), &ojNode);
- if (jNode->ino == jDir->ino && jNode->version >= i_version) {
+ get_fl_mem(b2->offset, sizeof(*jNode),
+ NULL);
+ if (jNode->ino == jDir->ino &&
+ jNode->version >= i_version) {
i_version = jNode->version;
if (i)
put_fl_mem(i, NULL);
@@ -975,7 +1001,7 @@
sizeof(*i),
NULL);
}
- b2 = b2->next;
+ put_fl_mem(jNode, NULL);
}
dump_inode(pL, jDir, i);
@@ -1424,7 +1450,7 @@
}
#endif
-#define DEFAULT_EMPTY_SCAN_SIZE 4096
+#define DEFAULT_EMPTY_SCAN_SIZE 256
static inline uint32_t EMPTY_SCAN_SIZE(uint32_t sector_size)
{
@@ -1445,7 +1471,7 @@
u32 counterF = 0;
u32 counterN = 0;
u32 max_totlen = 0;
- u32 buf_size = DEFAULT_EMPTY_SCAN_SIZE;
+ u32 buf_size;
char *buf;
nr_sectors = lldiv(part->size, part->sector_size);
@@ -1457,7 +1483,7 @@
/* if we are building a list we need to refresh the cache. */
jffs_init_1pass_list(part);
pL = (struct b_lists *)part->jffs2_priv;
- buf = malloc(buf_size);
+ buf = malloc(DEFAULT_EMPTY_SCAN_SIZE);
puts ("Scanning JFFS2 FS: ");
/* start at the beginning of the partition */
@@ -1472,7 +1498,11 @@
uint32_t sumlen;
int ret;
#endif
+ /* Indicates a sector with a CLEANMARKER was found */
+ int clean_sector = 0;
+ /* Set buf_size to maximum length */
+ buf_size = DEFAULT_EMPTY_SCAN_SIZE;
WATCHDOG_RESET();
#ifdef CONFIG_JFFS2_SUMMARY
@@ -1547,6 +1577,11 @@
ofs += sector_ofs;
prevofs = ofs - 1;
+ /*
+ * Set buf_size down to the minimum size required.
+ * This prevents reading in chunks of flash data unnecessarily.
+ */
+ buf_size = sizeof(union jffs2_node_union);
scan_more:
while (ofs < sector_ofs + part->sector_size) {
@@ -1589,6 +1624,14 @@
ofs += 4;
}
/* Ran off end. */
+ /*
+ * If this sector had a clean marker at the
+ * beginning, and immediately following this
+ * have been a bunch of FF bytes, treat the
+ * entire sector as empty.
+ */
+ if (clean_sector)
+ break;
/* See how much more there is to read in this
* eraseblock...
@@ -1610,6 +1653,11 @@
buf_ofs = ofs;
goto more_empty;
}
+ /*
+ * Found something not erased in the sector, so reset
+ * the 'clean_sector' flag.
+ */
+ clean_sector = 0;
if (node->magic != JFFS2_MAGIC_BITMASK ||
!hdr_crc(node)) {
ofs += 4;
@@ -1627,13 +1675,18 @@
case JFFS2_NODETYPE_INODE:
if (buf_ofs + buf_len < ofs + sizeof(struct
jffs2_raw_inode)) {
+ buf_len = min_t(uint32_t,
+ sizeof(struct jffs2_raw_inode),
+ sector_ofs +
+ part->sector_size -
+ ofs);
get_fl_mem((u32)part->offset + ofs,
buf_len, buf);
buf_ofs = ofs;
node = (void *)buf;
}
- if (!inode_crc((struct jffs2_raw_inode *) node))
- break;
+ if (!inode_crc((struct jffs2_raw_inode *)node))
+ break;
if (insert_node(&pL->frag, (u32) part->offset +
ofs) == NULL) {
@@ -1650,6 +1703,11 @@
((struct
jffs2_raw_dirent *)
node)->nsize) {
+ buf_len = min_t(uint32_t,
+ node->totlen,
+ sector_ofs +
+ part->sector_size -
+ ofs);
get_fl_mem((u32)part->offset + ofs,
buf_len, buf);
buf_ofs = ofs;
@@ -1681,6 +1739,16 @@
"%d != %zu\n",
node->totlen,
sizeof(struct jffs2_unknown_node));
+ if ((node->totlen ==
+ sizeof(struct jffs2_unknown_node)) &&
+ (ofs == sector_ofs)) {
+ /*
+ * Found a CLEANMARKER at the beginning
+ * of the sector. It's in the correct
+ * place with correct size and CRC.
+ */
+ clean_sector = 1;
+ }
break;
case JFFS2_NODETYPE_PADDING:
if (node->totlen < sizeof(struct jffs2_unknown_node))
@@ -1702,6 +1770,13 @@
}
free(buf);
+#if defined(CONFIG_SYS_JFFS2_SORT_FRAGMENTS)
+ /*
+ * Sort the lists.
+ */
+ sort_list(&pL->frag);
+ sort_list(&pL->dir);
+#endif
putstr("\b\b done.\r\n"); /* close off the dots */
/* We don't care if malloc failed - then each read operation will
diff --git a/fs/jffs2/jffs2_private.h b/fs/jffs2/jffs2_private.h
index 658b325..06b6ca2 100644
--- a/fs/jffs2/jffs2_private.h
+++ b/fs/jffs2/jffs2_private.h
@@ -98,4 +98,8 @@
}
}
+#if defined(CONFIG_SYS_JFFS2_SORT_FRAGMENTS)
+/* External merge sort. */
+int sort_list(struct b_list *list);
+#endif
#endif /* jffs2_private.h */
diff --git a/fs/jffs2/mergesort.c b/fs/jffs2/mergesort.c
new file mode 100644
index 0000000..6e633a1
--- /dev/null
+++ b/fs/jffs2/mergesort.c
@@ -0,0 +1,52 @@
+/*
+ * This file is copyright 2001 Simon Tatham.
+ * Rewritten from original source 2006 by Dan Merillat for use in u-boot.
+ *
+ * Original code can be found at:
+ * http://www.chiark.greenend.org.uk/~sgtatham/algorithms/listsort.html
+ *
+ * SPDX-License-Identifier: MIT
+ */
+
+#include <common.h>
+#include "jffs2_private.h"
+
+int sort_list(struct b_list *list)
+{
+ struct b_node *p, *q, *e, **tail;
+ int k, psize, qsize;
+
+ if (!list->listHead)
+ return 0;
+
+ for (k = 1; k < list->listCount; k *= 2) {
+ tail = &list->listHead;
+ for (p = q = list->listHead; p; p = q) {
+ /* step 'k' places from p; */
+ for (psize = 0; q && psize < k; psize++)
+ q = q->next;
+ qsize = k;
+
+ /* two lists, merge them. */
+ while (psize || (qsize && q)) {
+ /* merge the next element */
+ if (psize == 0 ||
+ ((qsize && q) &&
+ list->listCompare(p, q))) {
+ /* p is empty, or p > q, so q next */
+ e = q;
+ q = q->next;
+ qsize--;
+ } else {
+ e = p;
+ p = p->next;
+ psize--;
+ }
+ e->next = NULL; /* break accidental loops. */
+ *tail = e;
+ tail = &e->next;
+ }
+ }
+ }
+ return 0;
+}
diff --git a/include/bitfield.h b/include/bitfield.h
index ec4815c..b884c74 100644
--- a/include/bitfield.h
+++ b/include/bitfield.h
@@ -54,5 +54,5 @@
{
uint mask = bitfield_mask(shift, width);
- return (reg_val & ~mask) | (bitfield_val << shift);
+ return (reg_val & ~mask) | ((bitfield_val << shift) & mask);
}
diff --git a/include/common.h b/include/common.h
index fcc9ae7..5c076d6 100644
--- a/include/common.h
+++ b/include/common.h
@@ -830,11 +830,18 @@
int tstc(void);
/* stdout */
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_SERIAL_SUPPORT)
+#define putc(...) do { } while (0)
+#define puts(...) do { } while (0)
+#define printf(...) do { } while (0)
+#define vprintf(...) do { } while (0)
+#else
void putc(const char c);
void puts(const char *s);
int printf(const char *fmt, ...)
__attribute__ ((format (__printf__, 1, 2)));
int vprintf(const char *fmt, va_list args);
+#endif
/* stderr */
#define eputc(c) fputc(stderr, c)
diff --git a/include/config_distro_defaults.h b/include/config_distro_defaults.h
index bd8fbca..d8165cc 100644
--- a/include/config_distro_defaults.h
+++ b/include/config_distro_defaults.h
@@ -23,12 +23,18 @@
#if defined(__arm__) || defined(__aarch64__)
#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100
#if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__)
+#if !defined(CONFIG_BOOTP_VCI_STRING)
#define CONFIG_BOOTP_VCI_STRING "U-boot.armv7"
+#endif
#elif defined(__aarch64__)
+#if !defined(CONFIG_BOOTP_VCI_STRING)
#define CONFIG_BOOTP_VCI_STRING "U-boot.armv8"
+#endif
#else
+#if !defined(CONFIG_BOOTP_VCI_STRING)
#define CONFIG_BOOTP_VCI_STRING "U-boot.arm"
#endif
+#endif
#elif defined(__i386__)
#define CONFIG_BOOTP_PXE_CLIENTARCH 0x0
#elif defined(__x86_64__)
diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h
index a2468c3..5e15dd9 100644
--- a/include/configs/M5208EVBE.h
+++ b/include/configs/M5208EVBE.h
@@ -88,7 +88,6 @@
""
#define CONFIG_PRAM 512 /* 512 KB */
-#define CONFIG_SYS_PROMPT "-> "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#ifdef CONFIG_CMD_KGDB
diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h
index 2e86016..d1cadc0 100644
--- a/include/configs/M52277EVB.h
+++ b/include/configs/M52277EVB.h
@@ -150,7 +150,6 @@
#define CONFIG_PRAM 2048 /* 2048 KB */
-#define CONFIG_SYS_PROMPT "-> "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h
index ae11e7d..1472672 100644
--- a/include/configs/M5235EVB.h
+++ b/include/configs/M5235EVB.h
@@ -106,7 +106,6 @@
""
#define CONFIG_PRAM 512 /* 512 KB */
-#define CONFIG_SYS_PROMPT "-> "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#if defined(CONFIG_KGDB)
diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h
index d888c3e..006f2d8 100644
--- a/include/configs/M5272C3.h
+++ b/include/configs/M5272C3.h
@@ -105,7 +105,6 @@
"save\0" \
""
-#define CONFIG_SYS_PROMPT "-> "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h
index fa9b973..116e8e2 100644
--- a/include/configs/M5275EVB.h
+++ b/include/configs/M5275EVB.h
@@ -98,7 +98,6 @@
#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0)
#define CONFIG_SYS_I2C_PINMUX_SET (0x000F)
-#define CONFIG_SYS_PROMPT "-> "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#if (CONFIG_CMD_KGDB)
diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h
index 860abe7..eff0aa6 100644
--- a/include/configs/M5282EVB.h
+++ b/include/configs/M5282EVB.h
@@ -94,7 +94,6 @@
"save\0" \
""
-#define CONFIG_SYS_PROMPT "-> "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h
index 817b142..a48ae6b 100644
--- a/include/configs/M53017EVB.h
+++ b/include/configs/M53017EVB.h
@@ -108,7 +108,6 @@
""
#define CONFIG_PRAM 512 /* 512 KB */
-#define CONFIG_SYS_PROMPT "-> "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#ifdef CONFIG_CMD_KGDB
diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
index 4724a9c..e806b7a 100644
--- a/include/configs/M5329EVB.h
+++ b/include/configs/M5329EVB.h
@@ -102,7 +102,6 @@
""
#define CONFIG_PRAM 512 /* 512 KB */
-#define CONFIG_SYS_PROMPT "-> "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#ifdef CONFIG_CMD_KGDB
diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h
index 32afa44..1df98f7 100644
--- a/include/configs/M5373EVB.h
+++ b/include/configs/M5373EVB.h
@@ -102,7 +102,6 @@
""
#define CONFIG_PRAM 512 /* 512 KB */
-#define CONFIG_SYS_PROMPT "-> "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#ifdef CONFIG_CMD_KGDB
diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h
index 1f65918..db0ddcd 100644
--- a/include/configs/M54418TWR.h
+++ b/include/configs/M54418TWR.h
@@ -216,7 +216,6 @@
#define CONFIG_SYS_HUSH_PARSER 1
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#define CONFIG_SYS_PROMPT "-> "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h
index 2c08512..de747a4 100644
--- a/include/configs/M54451EVB.h
+++ b/include/configs/M54451EVB.h
@@ -160,7 +160,6 @@
#define CONFIG_PRAM 2048 /* 2048 KB */
-#define CONFIG_SYS_PROMPT "-> "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h
index e82ba32..06da5f0 100644
--- a/include/configs/M54455EVB.h
+++ b/include/configs/M54455EVB.h
@@ -219,7 +219,6 @@
#define CONFIG_PRAM 2048 /* 2048 KB */
-#define CONFIG_SYS_PROMPT "-> "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h
index 3c1bb90..e30b645 100644
--- a/include/configs/M5475EVB.h
+++ b/include/configs/M5475EVB.h
@@ -146,7 +146,6 @@
""
#define CONFIG_PRAM 512 /* 512 KB */
-#define CONFIG_SYS_PROMPT "-> "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#ifdef CONFIG_CMD_KGDB
diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h
index 7e1b364..051c940 100644
--- a/include/configs/M5485EVB.h
+++ b/include/configs/M5485EVB.h
@@ -134,7 +134,6 @@
""
#define CONFIG_PRAM 512 /* 512 KB */
-#define CONFIG_SYS_PROMPT "-> "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#ifdef CONFIG_CMD_KGDB
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 32cb007..834786d 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -544,12 +544,6 @@
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
-#ifdef CONFIG_MPC8349ITX
-#define CONFIG_SYS_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */
-#else
-#define CONFIG_SYS_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */
-#endif
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
diff --git a/include/configs/PATI.h b/include/configs/PATI.h
index dfc4fc0..5d0e422 100644
--- a/include/configs/PATI.h
+++ b/include/configs/PATI.h
@@ -71,7 +71,6 @@
#define CONFIG_PREBOOT
#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "pati=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h
index 0fa03cf..21a918a 100644
--- a/include/configs/T102xQDS.h
+++ b/include/configs/T102xQDS.h
@@ -871,7 +871,6 @@
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#ifdef CONFIG_CMD_KGDB
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index bde71fb..242c239 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -873,7 +873,6 @@
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#ifdef CONFIG_CMD_KGDB
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h
index bdedef5..76611b0 100644
--- a/include/configs/UCP1020.h
+++ b/include/configs/UCP1020.h
@@ -550,7 +550,6 @@
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_SYS_PROMPT "B$ " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h
index 60c2948..5b2e092 100644
--- a/include/configs/VCMA9.h
+++ b/include/configs/VCMA9.h
@@ -140,7 +140,6 @@
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "VCMA9 # "
#define CONFIG_SYS_CBSIZE 256
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
diff --git a/include/configs/ac14xx.h b/include/configs/ac14xx.h
index 8a5d1e6..f05d9ec 100644
--- a/include/configs/ac14xx.h
+++ b/include/configs/ac14xx.h
@@ -421,7 +421,6 @@
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_SYS_PROMPT "ac14xx> " /* Monitor Command Prompt */
#ifdef CONFIG_CMD_KGDB
# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
diff --git a/include/configs/adp-ag101.h b/include/configs/adp-ag101.h
index 141fc99..0f256d8 100644
--- a/include/configs/adp-ag101.h
+++ b/include/configs/adp-ag101.h
@@ -117,7 +117,6 @@
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "NDS32 # " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
diff --git a/include/configs/adp-ag101p.h b/include/configs/adp-ag101p.h
index 4296c6b..94fcdbd 100644
--- a/include/configs/adp-ag101p.h
+++ b/include/configs/adp-ag101p.h
@@ -117,7 +117,6 @@
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "NDS32 # " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
diff --git a/include/configs/adp-ag102.h b/include/configs/adp-ag102.h
index 0c7573a..6f05d87 100644
--- a/include/configs/adp-ag102.h
+++ b/include/configs/adp-ag102.h
@@ -180,7 +180,6 @@
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "NDS32 # " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h
index 600fefb..654b778 100644
--- a/include/configs/am3517_crane.h
+++ b/include/configs/am3517_crane.h
@@ -207,11 +207,8 @@
/*
* Miscellaneous configurable options
*/
-#define V_PROMPT "AM3517_CRANE # "
-
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT V_PROMPT
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
@@ -318,7 +315,7 @@
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
/* NAND boot config */
-#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 30f31a9..7049091 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -218,11 +218,8 @@
/*
* Miscellaneous configurable options
*/
-#define V_PROMPT "AM3517_EVM # "
-
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT V_PROMPT
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
diff --git a/include/configs/amcore.h b/include/configs/amcore.h
index 45fd265..bbab8b2 100644
--- a/include/configs/amcore.h
+++ b/include/configs/amcore.h
@@ -26,7 +26,6 @@
#define CONFIG_CMD_TIMER
#define CONFIG_CMD_DIAG
-#define CONFIG_SYS_PROMPT "amcore $ "
/* undef to save memory */
#undef CONFIG_SYS_LONGHELP
diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h
index 620ca02..bcaea95 100644
--- a/include/configs/apalis_t30.h
+++ b/include/configs/apalis_t30.h
@@ -12,7 +12,6 @@
#include "tegra30-common.h"
/* High-level configuration options */
-#define V_PROMPT "Apalis T30 # "
#define CONFIG_TEGRA_BOARD_STRING "Toradex Apalis T30"
/* Board-specific serial config */
diff --git a/include/configs/apf27.h b/include/configs/apf27.h
index a0a26bb..43fbdd3 100644
--- a/include/configs/apf27.h
+++ b/include/configs/apf27.h
@@ -40,6 +40,7 @@
#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
#define CONFIG_SPL_MAX_SIZE 2048
#define CONFIG_SPL_TEXT_BASE 0xA0000000
+#define CONFIG_SPL_SERIAL_SUPPORT
/* NAND boot config */
#define CONFIG_SPL_NAND_SUPPORT
@@ -139,7 +140,6 @@
* U-Boot general configurations
*/
#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_PROMPT "BIOS> " /* prompt string */
#define CONFIG_SYS_CBSIZE 2048 /* console I/O buffer */
#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
diff --git a/include/configs/arcangel4.h b/include/configs/arcangel4.h
index 6636e0e..a342d7e 100644
--- a/include/configs/arcangel4.h
+++ b/include/configs/arcangel4.h
@@ -67,7 +67,6 @@
* Console configuration
*/
#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_PROMPT "arcangel4# "
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
diff --git a/include/configs/arndale.h b/include/configs/arndale.h
index 8784c4e..437a745 100644
--- a/include/configs/arndale.h
+++ b/include/configs/arndale.h
@@ -25,7 +25,6 @@
#define CONFIG_EXYNOS_SPL
/* Miscellaneous configurable options */
-#define CONFIG_SYS_PROMPT "ARNDALE # "
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
#define CONFIG_IDENT_STRING " for ARNDALE"
diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h
index c6e1f56..1c3a1c9 100644
--- a/include/configs/astro_mcf5373l.h
+++ b/include/configs/astro_mcf5373l.h
@@ -207,8 +207,6 @@
#define CONFIG_BOOTARGS " console=ttyS2,115200 rootfstype=romfs"\
" loaderversion=$loaderversion"
-#define CONFIG_SYS_PROMPT "URMEL > "
-
/* default RAM address for user programs */
#define CONFIG_SYS_LOAD_ADDR 0x20000
diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h
index c2621ff..2bded45 100644
--- a/include/configs/at91-sama5_common.h
+++ b/include/configs/at91-sama5_common.h
@@ -66,7 +66,6 @@
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_PROMPT "U-Boot> "
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h
index 6f1f65f..7e026ef 100644
--- a/include/configs/at91rm9200ek.h
+++ b/include/configs/at91rm9200ek.h
@@ -194,7 +194,6 @@
#define CONFIG_SYS_LONGHELP
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT "U-Boot> "
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
/* Print Buffer Size */
diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h
index e98cf0c..459b8f9 100644
--- a/include/configs/at91sam9260ek.h
+++ b/include/configs/at91sam9260ek.h
@@ -254,7 +254,6 @@
"root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait"
#endif
-#define CONFIG_SYS_PROMPT "U-Boot> "
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h
index 42461d2..9c595f2 100644
--- a/include/configs/at91sam9261ek.h
+++ b/include/configs/at91sam9261ek.h
@@ -201,7 +201,6 @@
"root=/dev/mtdblock7 rw rootfstype=jffs2"
#endif
-#define CONFIG_SYS_PROMPT "U-Boot> "
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index 731c7f1..3eb0154 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -330,7 +330,6 @@
"root=/dev/mtdblock7 rw rootfstype=jffs2"
#endif
-#define CONFIG_SYS_PROMPT "U-Boot> "
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h
index 09d8bec..4d90209 100644
--- a/include/configs/at91sam9m10g45ek.h
+++ b/include/configs/at91sam9m10g45ek.h
@@ -181,7 +181,6 @@
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_PROMPT "U-Boot> "
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h
index a19d4d9..ea0a94b 100644
--- a/include/configs/at91sam9n12ek.h
+++ b/include/configs/at91sam9n12ek.h
@@ -221,7 +221,6 @@
#endif
-#define CONFIG_SYS_PROMPT "U-Boot> "
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) \
diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h
index e709f9c..f7a174e 100644
--- a/include/configs/at91sam9rlek.h
+++ b/include/configs/at91sam9rlek.h
@@ -184,7 +184,6 @@
"root=/dev/mmcblk0p2 rw rootwait"
#endif
-#define CONFIG_SYS_PROMPT "U-Boot> "
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h
index b9a7754..9f76786 100644
--- a/include/configs/at91sam9x5ek.h
+++ b/include/configs/at91sam9x5ek.h
@@ -223,7 +223,6 @@
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_PROMPT "U-Boot> "
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) \
diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h
index 1cab0a9..c436fef 100644
--- a/include/configs/atngw100.h
+++ b/include/configs/atngw100.h
@@ -135,7 +135,6 @@
#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
/* Other configuration settings that shouldn't have to change all that often */
-#define CONFIG_SYS_PROMPT "U-Boot> "
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
diff --git a/include/configs/atngw100mkii.h b/include/configs/atngw100mkii.h
index 486d9ee..3935811 100644
--- a/include/configs/atngw100mkii.h
+++ b/include/configs/atngw100mkii.h
@@ -156,7 +156,6 @@
#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
/* Other configuration settings that shouldn't have to change all that often */
-#define CONFIG_SYS_PROMPT "U-Boot> "
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h
index 1cd99e9..8cd7c35 100644
--- a/include/configs/atstk1002.h
+++ b/include/configs/atstk1002.h
@@ -151,7 +151,6 @@
#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
/* Other configuration settings that shouldn't have to change all that often */
-#define CONFIG_SYS_PROMPT "U-Boot> "
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
diff --git a/include/configs/axs101.h b/include/configs/axs101.h
index 25116e5..7cb8853 100644
--- a/include/configs/axs101.h
+++ b/include/configs/axs101.h
@@ -155,7 +155,6 @@
* Console configuration
*/
#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_PROMPT "AXS# "
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
diff --git a/include/configs/balloon3.h b/include/configs/balloon3.h
index 12c5a6c..124a766 100644
--- a/include/configs/balloon3.h
+++ b/include/configs/balloon3.h
@@ -64,6 +64,7 @@
#define CONFIG_SYS_HUSH_PARSER 1
#define CONFIG_SYS_LONGHELP
+#undef CONFIG_SYS_PROMPT
#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT "$ "
#else
diff --git a/include/configs/beaver.h b/include/configs/beaver.h
index adc578a..1790f60 100644
--- a/include/configs/beaver.h
+++ b/include/configs/beaver.h
@@ -25,7 +25,6 @@
#define CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1
/* High-level configuration options */
-#define V_PROMPT "Tegra30 (Beaver) # "
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Beaver"
/* Board-specific serial config */
diff --git a/include/configs/bf537-minotaur.h b/include/configs/bf537-minotaur.h
index 7e52d17..6674d28 100644
--- a/include/configs/bf537-minotaur.h
+++ b/include/configs/bf537-minotaur.h
@@ -159,7 +159,6 @@
#define CONFIG_BOOTCOMMAND "run ramboot"
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw"
-#define CONFIG_SYS_PROMPT "minotaur> "
#define BOOT_ENV_SETTINGS \
"update=tftpboot $(loadaddr) u-boot.ldr;" \
diff --git a/include/configs/bf537-srv1.h b/include/configs/bf537-srv1.h
index d8a0cc6..15d912e 100644
--- a/include/configs/bf537-srv1.h
+++ b/include/configs/bf537-srv1.h
@@ -158,7 +158,6 @@
#define CONFIG_BOOTCOMMAND "run flashboot"
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw"
-#define CONFIG_SYS_PROMPT "srv1> "
#define BOOT_ENV_SETTINGS \
"update=tftpboot $(loadaddr) u-boot.ldr;" \
diff --git a/include/configs/bf561-acvilon.h b/include/configs/bf561-acvilon.h
index da28396..b3c6d29 100644
--- a/include/configs/bf561-acvilon.h
+++ b/include/configs/bf561-acvilon.h
@@ -153,7 +153,6 @@
*/
#define CONFIG_UART_CONSOLE 0
#define CONFIG_BAUDRATE 57600
-#define CONFIG_SYS_PROMPT "Acvilon> "
/*
* Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/br4.h b/include/configs/br4.h
index cbef809..959f9a9 100644
--- a/include/configs/br4.h
+++ b/include/configs/br4.h
@@ -127,7 +127,6 @@
#define CONFIG_BAUDRATE 115200
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 0
-#define CONFIG_SYS_PROMPT "br4>"
#define CONFIG_BOOTCOMMAND "run nandboot"
#define CONFIG_BOOTDELAY 2
#define CONFIG_LOADADDR 0x2000000
diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h
index 1521415..838ef1f 100644
--- a/include/configs/bur_am335x_common.h
+++ b/include/configs/bur_am335x_common.h
@@ -129,7 +129,6 @@
*/
#define CONFIG_SYS_MALLOC_LEN (5120 << 10)
#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT "U-Boot (BuR V2.0)# "
#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_ENV_OVERWRITE /* Overwrite ethaddr / serial# */
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
diff --git a/include/configs/calimain.h b/include/configs/calimain.h
index 7d8bb47..c8b15fb 100644
--- a/include/configs/calimain.h
+++ b/include/configs/calimain.h
@@ -194,7 +194,6 @@
* U-Boot general configuration
*/
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_PROMPT "Calimain > " /* Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
diff --git a/include/configs/cam_enc_4xx.h b/include/configs/cam_enc_4xx.h
index 3400dd4..578c4ab 100644
--- a/include/configs/cam_enc_4xx.h
+++ b/include/configs/cam_enc_4xx.h
@@ -124,7 +124,6 @@
/* U-Boot general configuration */
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_PROMPT "cam_enc_4xx> " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE /* Print buffer size */ \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h
index 93c5f48..ce6b158 100644
--- a/include/configs/cardhu.h
+++ b/include/configs/cardhu.h
@@ -25,7 +25,6 @@
#define CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3
/* High-level configuration options */
-#define V_PROMPT "Tegra30 (Cardhu) # "
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Cardhu"
#define BOARD_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index bbd9f38..ddf6b5f 100644
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h
@@ -45,7 +45,6 @@
#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
/* Shell */
-#define CONFIG_SYS_PROMPT "CM-FX6 # "
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h
index 767ef3a..adf05b1 100644
--- a/include/configs/cm_t335.h
+++ b/include/configs/cm_t335.h
@@ -27,9 +27,6 @@
#undef CONFIG_MAX_RAM_BANK_SIZE
#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 512MB */
-#undef CONFIG_SYS_PROMPT
-#define CONFIG_SYS_PROMPT "CM-T335 # "
-
#define CONFIG_OMAP_COMMON
#define MACH_TYPE_CM_T335 4586 /* Until the next sync */
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index 6885ae1..281d614 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -222,7 +222,6 @@
#define CONFIG_SYS_AUTOLOAD "no"
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT "CM-T3x # "
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h
index cf08414..33b22a7 100644
--- a/include/configs/cm_t3517.h
+++ b/include/configs/cm_t3517.h
@@ -227,7 +227,6 @@
#define CONFIG_SYS_AUTOLOAD "no"
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT "CM-T3517 # "
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h
new file mode 100644
index 0000000..c4d3b94
--- /dev/null
+++ b/include/configs/cm_t43.h
@@ -0,0 +1,182 @@
+/*
+ * cm_t43.h
+ *
+ * Copyright (C) 2015 Compulab, Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_CM_T43_H
+#define __CONFIG_CM_T43_H
+
+#define CONFIG_AM43XX
+#define CONFIG_CM_T43
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2GB */
+#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
+
+#include <asm/arch/omap.h>
+
+/* Serial support */
+#define CONFIG_OMAP_SERIAL
+#define CONFIG_DM_SERIAL
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_CLK 48000000
+#define CONFIG_SYS_NS16550_COM1 0x44e09000
+
+/* NAND support */
+#define CONFIG_NAND
+#define CONFIG_NAND_OMAP_ELM
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCSIZE 512
+#define CONFIG_SYS_NAND_ECCBYTES 14
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
+#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
+ CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+ 10, 11, 12, 13, 14, 15, 16, 17, \
+ 18, 19, 20, 21, 22, 23, 24, 25, \
+ 26, 27, 28, 29, 30, 31, 32, 33, \
+ 34, 35, 36, 37, 38, 39, 40, 41, \
+ 42, 43, 44, 45, 46, 47, 48, 49, \
+ 50, 51, 52, 53, 54, 55, 56, 57, }
+
+/* CPSW Ethernet support */
+#define CONFIG_DRIVER_TI_CPSW
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_NET_MULTI
+#define CONFIG_PHY_GIGE
+#define CONFIG_PHY_ATHEROS
+#define CONFIG_PHYLIB
+#define CONFIG_SYS_RX_ETH_BUFFER 64
+
+/* USB support */
+#define CONFIG_USB_HOST
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_OMAP
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_STORAGE
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+#define CONFIG_OMAP_USB_PHY
+#define CONFIG_AM437X_USB2PHY2_HOST
+
+/* SPI Flash support */
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_MACRONIX
+#define CONFIG_SPI_FLASH_ATMEL
+#define CONFIG_SPI_FLASH_EON
+#define CONFIG_SPI_FLASH_GIGADEVICE
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_TI_SPI_MMAP
+#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SF_DEFAULT_SPEED 48000000
+#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3
+
+/* Power */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_TPS65218
+
+/* Enabling L2 Cache */
+#define CONFIG_SYS_L2_PL310
+#define CONFIG_SYS_PL310_BASE 0x48242000
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
+/*
+ * Since SPL did pll and ddr initialization for us,
+ * we don't need to do it twice.
+ */
+#if !defined(CONFIG_SPL_BUILD)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+#define CONFIG_HSMMC2_8BIT
+
+#include <configs/ti_armv7_omap.h>
+#undef CONFIG_SPL_OS_BOOT
+#undef CONFIG_SPL_GPIO_SUPPORT
+#undef CONFIG_SPL_NAND_SUPPORT
+#undef CONFIG_SPL_BOARD_INIT
+#undef CONFIG_BOOTDELAY
+#include <config_distro_defaults.h>
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_ENV_SIZE (16 * 1024)
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#define V_OSCK 24000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK)
+
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#define CONFIG_ENV_OFFSET (768 * 1024)
+#define CONFIG_ENV_SPI_MAX_HZ 48000000
+
+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+
+/* Enhance our eMMC support / experience. */
+#define CONFIG_CMD_GPT
+#define CONFIG_EFI_PARTITION
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x80200000\0" \
+ "fdtaddr=0x81200000\0" \
+ "bootm_size=0x8000000\0" \
+ "autoload=no\0" \
+ "console=ttyO0,115200n8\0" \
+ "fdtfile=am437x-sb-som-t43.dtb\0" \
+ "kernel=zImage-cm-t43\0" \
+ "bootscr=bootscr.img\0" \
+ "emmcroot=/dev/mmcblk0p2 rw\0" \
+ "emmcrootfstype=ext4 rootwait\0" \
+ "emmcargs=setenv bootargs console=${console} " \
+ "root=${emmcroot} " \
+ "rootfstype=${emmcrootfstype}\0" \
+ "loadbootscript=load mmc 0 ${loadaddr} ${bootscr}\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source ${loadaddr}\0" \
+ "emmcboot=echo Booting from emmc ... && " \
+ "run emmcargs && " \
+ "load mmc 1 ${loadaddr} ${kernel} && " \
+ "load mmc 1 ${fdtaddr} ${fdtfile} && " \
+ "bootz ${loadaddr} - ${fdtaddr}\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev 0; " \
+ "if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "fi; " \
+ "fi; " \
+ "mmc dev 1; " \
+ "if mmc rescan; then " \
+ "run emmcboot; " \
+ "fi;"
+
+
+#define CONFIG_CONS_INDEX 1
+
+/* SPL defines. */
+#define CONFIG_SPL_TEXT_BASE 0x40300350
+#define CONFIG_SPL_MAX_SIZE (64 * 1024)
+#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + (128 << 20))
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SYS_SPI_U_BOOT_OFFS (256 * 1024)
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+
+#endif /* __CONFIG_CM_T43_H */
diff --git a/include/configs/cm_t54.h b/include/configs/cm_t54.h
index 2a8b730..95a5a60 100644
--- a/include/configs/cm_t54.h
+++ b/include/configs/cm_t54.h
@@ -105,14 +105,12 @@
* Miscellaneous configurable options
*/
#undef CONFIG_SYS_AUTOLOAD
-#undef CONFIG_SYS_PROMPT
#undef CONFIG_EXTRA_ENV_SETTINGS
#undef CONFIG_BOOTCOMMAND
#undef CONFIG_BOOTDELAY
#define CONFIG_BOOTDELAY 3
#define CONFIG_SYS_AUTOLOAD "no"
-#define CONFIG_SYS_PROMPT "CM-T54 # "
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h
index 8a6106d..8e70d8c 100644
--- a/include/configs/cobra5272.h
+++ b/include/configs/cobra5272.h
@@ -178,8 +178,6 @@
#endif
-#define CONFIG_SYS_PROMPT "COBRA > " /* Layout of u-boot prompt*/
-
#define CONFIG_SYS_LOAD_ADDR 0x20000 /*Defines default RAM address
from which user programs will be started */
diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h
index e3f0ab0..a1b64c6 100644
--- a/include/configs/colibri_pxa270.h
+++ b/include/configs/colibri_pxa270.h
@@ -81,6 +81,7 @@
#define CONFIG_SYS_HUSH_PARSER 1
#undef CONFIG_SYS_LONGHELP /* Saves 10 KB */
+#undef CONFIG_SYS_PROMPT
#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT "$ "
#else
diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h
index 6d73f9d..06c51c0 100644
--- a/include/configs/colibri_t20.h
+++ b/include/configs/colibri_t20.h
@@ -10,7 +10,6 @@
#include "tegra20-common.h"
/* High-level configuration options */
-#define V_PROMPT "Colibri T20 # "
#define CONFIG_TEGRA_BOARD_STRING "Toradex Colibri T20"
/* Board-specific serial config */
diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h
index 1e94c34..fbfebcf 100644
--- a/include/configs/colibri_t30.h
+++ b/include/configs/colibri_t30.h
@@ -12,7 +12,6 @@
#include "tegra30-common.h"
/* High-level configuration options */
-#define V_PROMPT "Colibri T30 # "
#define CONFIG_TEGRA_BOARD_STRING "Toradex Colibri T30"
/* Board-specific serial config */
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index ab8d293..2583155 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -69,7 +69,6 @@
"512k(u-boot-env)," \
"-(ubi)"
-
#define CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
@@ -177,7 +176,6 @@
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#define CONFIG_SYS_PROMPT "Colibri VFxx # "
#undef CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE \
diff --git a/include/configs/corvus.h b/include/configs/corvus.h
index 3cfae21..2d2f3c1 100644
--- a/include/configs/corvus.h
+++ b/include/configs/corvus.h
@@ -133,7 +133,6 @@
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_PROMPT "U-Boot> "
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
diff --git a/include/configs/cpu9260.h b/include/configs/cpu9260.h
index d3c6f75..82f4fe7 100644
--- a/include/configs/cpu9260.h
+++ b/include/configs/cpu9260.h
@@ -464,11 +464,6 @@
#define CONFIG_BAUDRATE 115200
-#if defined(CONFIG_CPU9G20)
-#define CONFIG_SYS_PROMPT "CPU9G20=> "
-#elif defined(CONFIG_CPU9260)
-#define CONFIG_SYS_PROMPT "CPU9260=> "
-#endif
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_PBSIZE \
diff --git a/include/configs/cpuat91.h b/include/configs/cpuat91.h
index f990cf7..29cd842 100644
--- a/include/configs/cpuat91.h
+++ b/include/configs/cpuat91.h
@@ -173,7 +173,6 @@
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_PROMPT "CPUAT91=> "
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_MAXARGS 32
#define CONFIG_SYS_PBSIZE \
diff --git a/include/configs/da830evm.h b/include/configs/da830evm.h
index b82140e..7ac3224 100644
--- a/include/configs/da830evm.h
+++ b/include/configs/da830evm.h
@@ -143,7 +143,6 @@
#undef CONFIG_MISC_INIT_R
#undef CONFIG_BOOTDELAY
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_PROMPT "U-Boot > " /* Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 3da9da4..1cd11c0 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -262,7 +262,6 @@
#define CONFIG_MISC_INIT_R
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_PROMPT "U-Boot > " /* Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h
index 30aecca..2251f59 100644
--- a/include/configs/dalmore.h
+++ b/include/configs/dalmore.h
@@ -22,7 +22,6 @@
#include "tegra114-common.h"
/* High-level configuration options */
-#define V_PROMPT "Tegra114 (Dalmore) # "
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Dalmore"
/* Board-specific serial config */
diff --git a/include/configs/davinci_dm355evm.h b/include/configs/davinci_dm355evm.h
index e873fa4..72296a0 100644
--- a/include/configs/davinci_dm355evm.h
+++ b/include/configs/davinci_dm355evm.h
@@ -110,7 +110,6 @@
/* U-Boot general configuration */
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_PROMPT "DM355 EVM # " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE /* Print buffer size */ \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
diff --git a/include/configs/davinci_dm355leopard.h b/include/configs/davinci_dm355leopard.h
index d4b994a..e3ff943 100644
--- a/include/configs/davinci_dm355leopard.h
+++ b/include/configs/davinci_dm355leopard.h
@@ -78,7 +78,6 @@
/* U-Boot general configuration */
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_PROMPT "DM355 LEOPARD # "
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE /* Print buffer size */ \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
diff --git a/include/configs/davinci_dm365evm.h b/include/configs/davinci_dm365evm.h
index 9bdd2d6..bbc801b 100644
--- a/include/configs/davinci_dm365evm.h
+++ b/include/configs/davinci_dm365evm.h
@@ -143,7 +143,6 @@
/* U-Boot general configuration */
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_PROMPT "DM36x EVM # " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE /* Print buffer size */ \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
diff --git a/include/configs/davinci_dm6467evm.h b/include/configs/davinci_dm6467evm.h
index 8571cbd..6346422 100644
--- a/include/configs/davinci_dm6467evm.h
+++ b/include/configs/davinci_dm6467evm.h
@@ -94,7 +94,6 @@
/* U-Boot general configuration */
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_PROMPT "DM6467 EVM > " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h
index 35e9a15..15d8150 100644
--- a/include/configs/davinci_dvevm.h
+++ b/include/configs/davinci_dvevm.h
@@ -143,7 +143,6 @@
#define CONFIG_MISC_INIT_R
#undef CONFIG_BOOTDELAY
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_PROMPT "U-Boot > " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buffer sz */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h
index db636e4..bc5e1ca 100644
--- a/include/configs/davinci_schmoogie.h
+++ b/include/configs/davinci_schmoogie.h
@@ -87,7 +87,6 @@
#define CONFIG_MISC_INIT_R
#undef CONFIG_BOOTDELAY
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_PROMPT "U-Boot > " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buffer sz */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h
index 9ecf6ce..e719388 100644
--- a/include/configs/davinci_sffsdr.h
+++ b/include/configs/davinci_sffsdr.h
@@ -74,7 +74,6 @@
#define CONFIG_MISC_INIT_R
#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds. */
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_PROMPT "U-Boot > " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print buffer size */
diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h
index 410cf6874..b85c988 100644
--- a/include/configs/davinci_sonata.h
+++ b/include/configs/davinci_sonata.h
@@ -133,7 +133,6 @@
#define CONFIG_MISC_INIT_R
#undef CONFIG_BOOTDELAY
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_PROMPT "U-Boot > " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buffer sz */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h
index 0abab78..46e3a6c 100644
--- a/include/configs/dbau1x00.h
+++ b/include/configs/dbau1x00.h
@@ -98,8 +98,6 @@
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "DbAu1xx0 # " /* Monitor Command Prompt */
-
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h
index 4f35234..cc6a53e 100644
--- a/include/configs/devkit3250.h
+++ b/include/configs/devkit3250.h
@@ -1,7 +1,7 @@
/*
* Embest/Timll DevKit3250 board configuration file
*
- * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
+ * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -21,7 +21,9 @@
#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_DCACHE_OFF
+#if !defined(CONFIG_SPL_BUILD)
#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
#define CONFIG_BOARD_EARLY_INIT_F
/*
@@ -43,10 +45,44 @@
/*
* Serial Driver
*/
-#define CONFIG_SYS_LPC32XX_UART 2 /* UART2 */
+#define CONFIG_SYS_LPC32XX_UART 5 /* UART5 */
#define CONFIG_BAUDRATE 115200
/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_LPC32XX
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_CMD_I2C
+
+/*
+ * GPIO
+ */
+#define CONFIG_LPC32XX_GPIO
+#define CONFIG_CMD_GPIO
+
+/*
+ * SSP/SPI
+ */
+#define CONFIG_LPC32XX_SSP
+#define CONFIG_LPC32XX_SSP_TIMEOUT 100000
+#define CONFIG_CMD_SPI
+
+/*
+ * Ethernet
+ */
+#define CONFIG_RMII
+#define CONFIG_PHY_SMSC
+#define CONFIG_LPC32XX_ETH
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ADDR 0x1F
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+
+/*
* NOR Flash
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1
@@ -56,6 +92,29 @@
#define CONFIG_SYS_FLASH_CFI
/*
+ * NAND controller
+ */
+#define CONFIG_NAND_LPC32XX_SLC
+#define CONFIG_SYS_NAND_BASE SLC_NAND_BASE
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+
+/*
+ * NAND chip timings
+ */
+#define CONFIG_LPC32XX_NAND_SLC_WDR_CLKS 14
+#define CONFIG_LPC32XX_NAND_SLC_WWIDTH 66666666
+#define CONFIG_LPC32XX_NAND_SLC_WHOLD 200000000
+#define CONFIG_LPC32XX_NAND_SLC_WSETUP 50000000
+#define CONFIG_LPC32XX_NAND_SLC_RDR_CLKS 14
+#define CONFIG_LPC32XX_NAND_SLC_RWIDTH 66666666
+#define CONFIG_LPC32XX_NAND_SLC_RHOLD 200000000
+#define CONFIG_LPC32XX_NAND_SLC_RSETUP 50000000
+
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_CMD_NAND
+
+/*
* U-Boot General Configurations
*/
#define CONFIG_SYS_LONGHELP
@@ -71,8 +130,33 @@
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
-#define CONFIG_ENV_IS_NOWHERE
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_SIZE SZ_128K
+#define CONFIG_ENV_OFFSET 0x000A0000
+
+#define CONFIG_BOOTCOMMAND \
+ "dhcp; " \
+ "tftp ${loadaddr} ${serverip}:${tftpdir}/${bootfile}; " \
+ "tftp ${dtbaddr} ${serverip}:${tftpdir}/devkit3250.dtb; " \
+ "setenv nfsargs ip=dhcp root=/dev/nfs nfsroot=${serverip}:${nfsroot},tcp; " \
+ "setenv bootargs ${bootargs} ${nfsargs} ${userargs}; " \
+ "bootm ${loadaddr} - ${dtbaddr}"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "autoload=no\0" \
+ "ethaddr=00:01:90:00:C0:81\0" \
+ "dtbaddr=0x81000000\0" \
+ "nfsroot=/opt/projects/images/vladimir/oe/devkit3250/rootfs\0" \
+ "tftpdir=vladimir/oe/devkit3250\0" \
+ "userargs=oops=panic\0"
/*
* U-Boot Commands
@@ -85,13 +169,64 @@
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTDELAY 1
#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_BOOTARGS "console=ttyS2,115200n8"
+#define CONFIG_BOOTARGS "console=ttyS0,115200n8"
#define CONFIG_LOADADDR 0x80008000
/*
+ * SPL specific defines
+ */
+/* SPL will be executed at offset 0 */
+#define CONFIG_SPL_TEXT_BASE 0x00000000
+
+/* SPL will use SRAM as stack */
+#define CONFIG_SPL_STACK 0x0000FFF8
+#define CONFIG_SPL_BOARD_INIT
+
+/* Use the framework and generic lib */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+
+/* SPL will use serial */
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+/* SPL loads an image from NAND */
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_NAND_RAW_ONLY
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_DRIVERS
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
+#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
+#define CONFIG_SYS_NAND_ECCSIZE 0x100
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
+ 48, 49, 50, 51, 52, 53, 54, 55, \
+ 56, 57, 58, 59, 60, 61, 62, 63, }
+#define CONFIG_SYS_NAND_ECCBYTES 3
+#define CONFIG_SYS_NAND_PAGE_COUNT 64
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
+
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_NAND_SOFTECC
+
+#define CONFIG_SPL_MAX_SIZE 0x20000
+#define CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE
+
+/* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
+
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
+
+/* See common/spl/spl.c spl_set_header_raw_uboot() */
+#define CONFIG_SYS_MONITOR_LEN CONFIG_SYS_NAND_U_BOOT_SIZE
+
+/*
* Include SoC specific configuration
*/
#include <asm/arch/config.h>
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
index 215dc30..6d2c22e 100644
--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h
@@ -213,7 +213,7 @@
#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
/* NAND boot config */
-#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
diff --git a/include/configs/dig297.h b/include/configs/dig297.h
index f6d7ec4..98205ad 100644
--- a/include/configs/dig297.h
+++ b/include/configs/dig297.h
@@ -132,7 +132,7 @@
* Board NAND Info.
*/
#define CONFIG_NAND_OMAP_GPMC
-#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
/* to access nand */
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
@@ -208,7 +208,6 @@
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT "DIG297# "
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
diff --git a/include/configs/dockstar.h b/include/configs/dockstar.h
index b27b202..a62f4e3 100644
--- a/include/configs/dockstar.h
+++ b/include/configs/dockstar.h
@@ -43,9 +43,6 @@
*/
#include "mv-common.h"
-#undef CONFIG_SYS_PROMPT /* previously defined in mv-common.h */
-#define CONFIG_SYS_PROMPT "DockStar> " /* Command Prompt */
-
/*
* Environment variables configurations
*/
diff --git a/include/configs/duovero.h b/include/configs/duovero.h
index 6e53da5..28d12ad 100644
--- a/include/configs/duovero.h
+++ b/include/configs/duovero.h
@@ -27,9 +27,6 @@
#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
-#undef CONFIG_SYS_PROMPT
-#define CONFIG_SYS_PROMPT "duovero # "
-
/* USB UHH support options */
#define CONFIG_CMD_USB
#define CONFIG_USB_HOST
diff --git a/include/configs/ea20.h b/include/configs/ea20.h
index b9f28a3..9a70aae 100644
--- a/include/configs/ea20.h
+++ b/include/configs/ea20.h
@@ -122,7 +122,6 @@
* U-Boot general configuration
*/
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_PROMPT "ea20 > " /* Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h
index 924362c..f9ec028 100644
--- a/include/configs/eb_cpu5282.h
+++ b/include/configs/eb_cpu5282.h
@@ -73,7 +73,6 @@
#define CONFIG_MCFTMR
#define CONFIG_BOOTDELAY 5
-#define CONFIG_SYS_PROMPT "\nEB+CPU5282> "
#define CONFIG_SYS_LONGHELP 1
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
diff --git a/include/configs/eb_cpux9k2.h b/include/configs/eb_cpux9k2.h
index 271e071..d27f7e0 100644
--- a/include/configs/eb_cpux9k2.h
+++ b/include/configs/eb_cpux9k2.h
@@ -44,7 +44,6 @@
#define CONFIG_BOOT_RETRY_TIME 30
#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_PROMPT "U-Boot> " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
#define CONFIG_SYS_PBSIZE \
diff --git a/include/configs/eco5pk.h b/include/configs/eco5pk.h
index 49c53e4..f23d383 100644
--- a/include/configs/eco5pk.h
+++ b/include/configs/eco5pk.h
@@ -37,12 +37,6 @@
#define CONFIG_AUTO_COMPLETE
/*
- * Miscellaneous configurable options
- */
-#define V_PROMPT "ECO5-PK # "
-#define CONFIG_SYS_PROMPT V_PROMPT
-
-/*
* Set its own mtdparts, different from common
*/
#undef MTDIDS_DEFAULT
diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h
index 87b29f8..efe2a9d 100644
--- a/include/configs/edb93xx.h
+++ b/include/configs/edb93xx.h
@@ -39,7 +39,7 @@
#define CONFIG_SYS_LDSCRIPT "board/cirrus/edb93xx/u-boot.lds"
-
+#undef CONFIG_SYS_PROMPT
#ifdef CONFIG_EDB9301
#define CONFIG_EP9301
#define CONFIG_MACH_TYPE MACH_TYPE_EDB9301
diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
index b5e8e0e..8b38d7e 100644
--- a/include/configs/edminiv2.h
+++ b/include/configs/edminiv2.h
@@ -130,7 +130,6 @@
#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
-#define CONFIG_SYS_PROMPT "EDMiniV2> " /* Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */
diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h
index c7b1e5c..b49b903 100644
--- a/include/configs/ethernut5.h
+++ b/include/configs/ethernut5.h
@@ -237,7 +237,6 @@
#endif
/* Misc. u-boot settings */
-#define CONFIG_SYS_PROMPT "U-Boot> "
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_MAXARGS 16
diff --git a/include/configs/flea3.h b/include/configs/flea3.h
index 5d66901..5b4b011 100644
--- a/include/configs/flea3.h
+++ b/include/configs/flea3.h
@@ -108,7 +108,6 @@
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "flea3 U-Boot > "
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
diff --git a/include/configs/fx12mm.h b/include/configs/fx12mm.h
index f1cbc8e..fa32a2e 100644
--- a/include/configs/fx12mm.h
+++ b/include/configs/fx12mm.h
@@ -37,7 +37,6 @@
#define CONFIG_ENV_OVERWRITE 1
/*Misc*/
-#define CONFIG_SYS_PROMPT "FX12MM:/# " /* Monitor Command Prompt */
#define CONFIG_PREBOOT "echo U-Boot is up and running;"
/*Flash*/
diff --git a/include/configs/goflexhome.h b/include/configs/goflexhome.h
index 967a05a..2a42e7c 100644
--- a/include/configs/goflexhome.h
+++ b/include/configs/goflexhome.h
@@ -70,9 +70,6 @@
*/
#include "mv-common.h"
-#undef CONFIG_SYS_PROMPT /* previously defined in mv-common.h */
-#define CONFIG_SYS_PROMPT "GoFlexHome> " /* Command Prompt */
-
/*
* Environment variables configurations
*/
diff --git a/include/configs/grasshopper.h b/include/configs/grasshopper.h
index 231f25a..274175b 100644
--- a/include/configs/grasshopper.h
+++ b/include/configs/grasshopper.h
@@ -144,7 +144,6 @@
#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
/* Other configuration settings that shouldn't have to change all that often */
-#define CONFIG_SYS_PROMPT "U-Boot> "
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index 7c90812..1c0d96e 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -226,7 +226,6 @@
#define CONFIG_IMX_VIDEO_SKIP
/* Miscellaneous configurable options */
-#define CONFIG_SYS_PROMPT "Ventana > "
#define CONFIG_HWCONFIG
/* Print Buffer Size */
diff --git a/include/configs/h2200.h b/include/configs/h2200.h
index 1d2d09a..e8dfa74 100644
--- a/include/configs/h2200.h
+++ b/include/configs/h2200.h
@@ -123,7 +123,6 @@
#define CONFIG_INITRD_TAG
/* Monitor Command Prompt */
-#define CONFIG_SYS_PROMPT "> "
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "$ "
diff --git a/include/configs/harmony.h b/include/configs/harmony.h
index 99a63d6..e0bc7c0 100644
--- a/include/configs/harmony.h
+++ b/include/configs/harmony.h
@@ -12,7 +12,6 @@
#include "tegra20-common.h"
/* High-level configuration options */
-#define V_PROMPT "Tegra20 (Harmony) # "
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Harmony"
/* Board-specific serial config */
diff --git a/include/configs/highbank.h b/include/configs/highbank.h
index 86823e2..7f331a6 100644
--- a/include/configs/highbank.h
+++ b/include/configs/highbank.h
@@ -75,8 +75,9 @@
/*-----------------------------------------------------------------------
* Physical Memory Map
+ * The DRAM is already setup, so do not touch the DT node later.
*/
-#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_NR_DRAM_BANKS 0
#define PHYS_SDRAM_1_SIZE (4089 << 20)
#define CONFIG_SYS_MEMTEST_START 0x100000
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1_SIZE - 0x100000)
diff --git a/include/configs/hikey.h b/include/configs/hikey.h
new file mode 100644
index 0000000..8ff9077
--- /dev/null
+++ b/include/configs/hikey.h
@@ -0,0 +1,159 @@
+/*
+ * (C) Copyright 2015 Linaro
+ *
+ * Peter Griffin <peter.griffin@linaro.org>
+ *
+ * Configuration for HiKey 96boards CE. Parts were derived from other ARM
+ * configurations.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __HIKEY_H
+#define __HIKEY_H
+
+/* We use generic board for hikey */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_POWER
+#define CONFIG_POWER_HI6553
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_SUPPORT_RAW_INITRD
+
+/* Cache Definitions */
+#define CONFIG_SYS_DCACHE_OFF
+
+#define CONFIG_IDENT_STRING "hikey"
+
+/* Flat Device Tree Definitions */
+#define CONFIG_OF_LIBFDT
+
+/* Physical Memory Map */
+
+/* CONFIG_SYS_TEXT_BASE needs to align with where ATF loads bl33.bin */
+#define CONFIG_SYS_TEXT_BASE 0x35000000
+
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 0x00000000
+
+/* 1008 MB (the last 16Mb are secured for TrustZone by ATF*/
+#define PHYS_SDRAM_1_SIZE 0x3f000000
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
+
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000)
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY 19000000
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE 0xf6801000
+#define GICC_BASE 0xf6802000
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20))
+
+/* PL011 Serial Configuration */
+#define CONFIG_PL011_SERIAL
+
+#define CONFIG_PL011_CLOCK 19200000
+#define CONFIG_PL01x_PORTS {(void *)0xF8015000}
+#define CONFIG_CONS_INDEX 0
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_DWC2
+#define CONFIG_USB_DWC2_REG_ADDR 0xF72C0000
+/*#define CONFIG_DWC2_DFLT_SPEED_FULL*/
+#define CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
+
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MISC_INIT_R
+#endif
+
+#define CONFIG_HIKEY_GPIO
+#define CONFIG_DM_GPIO
+#define CONFIG_CMD_GPIO
+#define CONFIG_DM
+
+/* SD/MMC configuration */
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_DWMMC
+#define CONFIG_HIKEY_DWMMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_CMD_MMC
+
+#define CONFIG_FS_EXT4
+
+/* Command line configuration */
+#define CONFIG_MENU
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_UNZIP
+#define CONFIG_CMD_ENV
+
+#define CONFIG_MTD_PARTITIONS
+
+/* BOOTP options */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+#include <config_distro_defaults.h>
+
+/* Initial environment variables */
+
+/*
+ * Defines where the kernel and FDT will be put in RAM
+ */
+
+/* Assume we boot with root on the seventh partition of eMMC */
+#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 root=/dev/mmcblk0p9 rw"
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(USB, usb, 0) \
+ func(MMC, mmc, 1) \
+ func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "kernel_name=Image\0" \
+ "kernel_addr_r=0x00080000\0" \
+ "fdt_name=hi6220-hikey.dtb\0" \
+ "fdt_addr_r=0x02000000\0" \
+ "fdt_high=0xffffffffffffffff\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ BOOTENV
+
+
+/* Preserve enviroment on sd card */
+#define CONFIG_COMMAND_HISTORY
+
+#define CONFIG_ENV_SIZE 0x1000
+#define CONFIG_ENV_IS_IN_FAT
+#define FAT_ENV_INTERFACE "mmc"
+#define FAT_ENV_DEVICE_AND_PART "1:1"
+#define FAT_ENV_FILE "uboot.env"
+#define CONFIG_FAT_WRITE
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_MAXARGS 64 /* max command args */
+
+#define CONFIG_SYS_NO_FLASH
+
+#endif /* __HIKEY_H */
diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h
index 08e2f42..558edfc 100644
--- a/include/configs/hrcon.h
+++ b/include/configs/hrcon.h
@@ -484,7 +484,6 @@
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
diff --git a/include/configs/ib62x0.h b/include/configs/ib62x0.h
index ee52452..6afe340 100644
--- a/include/configs/ib62x0.h
+++ b/include/configs/ib62x0.h
@@ -59,9 +59,6 @@
*/
#include "mv-common.h"
-#undef CONFIG_SYS_PROMPT
-#define CONFIG_SYS_PROMPT "ib62x0 => "
-
/*
* Environment variables configuration
*/
diff --git a/include/configs/iconnect.h b/include/configs/iconnect.h
index 1a5c93d..bce97dc 100644
--- a/include/configs/iconnect.h
+++ b/include/configs/iconnect.h
@@ -52,9 +52,6 @@
*/
#include "mv-common.h"
-#undef CONFIG_SYS_PROMPT
-#define CONFIG_SYS_PROMPT "iconnect => "
-
/*
* Environment variables configuration
*/
diff --git a/include/configs/ima3-mx53.h b/include/configs/ima3-mx53.h
index 5a02917..2fa6c3d 100644
--- a/include/configs/ima3-mx53.h
+++ b/include/configs/ima3-mx53.h
@@ -94,7 +94,6 @@
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT "IMA3 MX53 U-Boot > "
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h
index c552e9f..23e3a6c 100644
--- a/include/configs/imx31_litekit.h
+++ b/include/configs/imx31_litekit.h
@@ -101,7 +101,6 @@
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "uboot> "
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h
index 54e8121..86f327c 100644
--- a/include/configs/imx31_phycore.h
+++ b/include/configs/imx31_phycore.h
@@ -102,7 +102,6 @@
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "uboot> "
/* Console I/O Buffer Size */
#define CONFIG_SYS_CBSIZE 256
/* Print Buffer Size */
diff --git a/include/configs/integrator-common.h b/include/configs/integrator-common.h
index 1d307ca..a22efd6 100644
--- a/include/configs/integrator-common.h
+++ b/include/configs/integrator-common.h
@@ -20,6 +20,11 @@
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) /* Size of malloc() pool */
+/* Serial port PL010/PL011 through the device model */
+#define CONFIG_PL01X_SERIAL
+#define CONFIG_BAUDRATE 38400
+#define CONFIG_CONS_INDEX 0
+
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_OF_LIBFDT /* enable passing a Device Tree */
diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h
index c76ebcb..c80e915 100644
--- a/include/configs/integratorap.h
+++ b/include/configs/integratorap.h
@@ -21,17 +21,6 @@
#define CONFIG_SYS_HZ_CLOCK 24000000 /* Timer 1 is clocked at 24Mhz */
/*
- * PL010 Configuration
- */
-#define CONFIG_PL010_SERIAL
-#define CONFIG_CONS_INDEX 0
-#define CONFIG_BAUDRATE 38400
-#define CONFIG_PL01x_PORTS { (void *) (CONFIG_SYS_SERIAL0), (void *) (CONFIG_SYS_SERIAL1) }
-#define CONFIG_SYS_SERIAL0 0x16000000
-#define CONFIG_SYS_SERIAL1 0x17000000
-
-
-/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
@@ -47,11 +36,6 @@
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyAM0 console=tty"
#define CONFIG_BOOTCOMMAND ""
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_PROMPT "Integrator-AP # " /* Monitor Command Prompt */
-
/* Flash settings */
#define CONFIG_SYS_FLASH_SIZE 0x02000000 /* 32 MiB */
#define CONFIG_SYS_MAX_FLASH_SECT 128
diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h
index d6f2602..af69ad9 100644
--- a/include/configs/integratorcp.h
+++ b/include/configs/integratorcp.h
@@ -28,15 +28,6 @@
#define CONFIG_SMC91111_BASE 0xC8000000
#undef CONFIG_SMC91111_EXT_PHY
-/* PL011 configuration */
-#define CONFIG_PL011_SERIAL
-#define CONFIG_PL011_CLOCK 14745600
-#define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, (void *)CONFIG_SYS_SERIAL1 }
-#define CONFIG_CONS_INDEX 0
-#define CONFIG_BAUDRATE 38400
-#define CONFIG_SYS_SERIAL0 0x16000000
-#define CONFIG_SYS_SERIAL1 0x17000000
-
/*
* Command line configuration.
*/
@@ -50,8 +41,6 @@
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_PROMPT "Integrator-CP # " /* Monitor Command Prompt */
-
#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */
#define CONFIG_SYS_MAX_FLASH_SECT 64
#define CONFIG_ENV_IS_IN_FLASH 1
diff --git a/include/configs/ipam390.h b/include/configs/ipam390.h
index e68b661..b1cd7df 100644
--- a/include/configs/ipam390.h
+++ b/include/configs/ipam390.h
@@ -207,7 +207,6 @@
#define CONFIG_MISC_INIT_R
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_PROMPT "U-Boot > " /* Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h
index def0ab4..e87a010 100644
--- a/include/configs/jetson-tk1.h
+++ b/include/configs/jetson-tk1.h
@@ -16,7 +16,6 @@
#include "tegra124-common.h"
/* High-level configuration options */
-#define V_PROMPT "Tegra124 (Jetson TK1) # "
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Jetson TK1"
/* Board-specific serial config */
diff --git a/include/configs/jornada.h b/include/configs/jornada.h
index 71f2ee1..3090476 100644
--- a/include/configs/jornada.h
+++ b/include/configs/jornada.h
@@ -55,7 +55,6 @@
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "HP Jornada# "
#define CONFIG_SYS_CBSIZE 256 /* console buffsize */
#define CONFIG_SYS_PBSIZE (256+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h
index 93c2976..8a451ec 100644
--- a/include/configs/kzm9g.h
+++ b/include/configs/kzm9g.h
@@ -53,7 +53,6 @@
/* prompt */
#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_PROMPT "KZM-A9-GT# "
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_PBSIZE 256
#define CONFIG_SYS_MAXARGS 16
diff --git a/include/configs/lp8x4x.h b/include/configs/lp8x4x.h
index e9ee3fb..10a7b05 100644
--- a/include/configs/lp8x4x.h
+++ b/include/configs/lp8x4x.h
@@ -97,6 +97,7 @@
#define CONFIG_SYS_HUSH_PARSER 1
#define CONFIG_SYS_LONGHELP
+#undef CONFIG_SYS_PROMPT
#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT "$ "
#else
diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h
index 5afee55..39fb464 100644
--- a/include/configs/ls2085a_common.h
+++ b/include/configs/ls2085a_common.h
@@ -260,7 +260,6 @@
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PROMPT "=> "
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_HUSH_PARSER
diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h
index ddbf5ce..1837258 100644
--- a/include/configs/lsxl.h
+++ b/include/configs/lsxl.h
@@ -88,7 +88,6 @@
#define CONFIG_SF_DEFAULT_SPEED 25000000
-#undef CONFIG_SYS_PROMPT
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
/*
diff --git a/include/configs/malta.h b/include/configs/malta.h
index ab2335f..2f33f63 100644
--- a/include/configs/malta.h
+++ b/include/configs/malta.h
@@ -59,6 +59,7 @@
/*
* Console configuration
*/
+#undef CONFIG_SYS_PROMPT
#if defined(CONFIG_SYS_LITTLE_ENDIAN)
#define CONFIG_SYS_PROMPT "maltael # "
#else
diff --git a/include/configs/mcx.h b/include/configs/mcx.h
index 0a7b7cf..0f70c47 100644
--- a/include/configs/mcx.h
+++ b/include/configs/mcx.h
@@ -111,6 +111,9 @@
#define CONFIG_USB_ULPI_VIEWPORT_OMAP
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_MCS7830
/* commands to include */
#define CONFIG_CMD_EXT2 /* EXT2 Support */
@@ -267,11 +270,8 @@
/*
* Miscellaneous configurable options
*/
-#define V_PROMPT "mcx # "
-
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT V_PROMPT
#define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
@@ -309,7 +309,10 @@
*/
/* **** PISMO SUPPORT *** */
+#define CONFIG_NAND
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_NAND_OMAP_GPMC_PREFETCH
#define CONFIG_ENV_IS_IN_NAND
#define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */
diff --git a/include/configs/medcom-wide.h b/include/configs/medcom-wide.h
index b5d72e3..6dfd5e2 100644
--- a/include/configs/medcom-wide.h
+++ b/include/configs/medcom-wide.h
@@ -13,7 +13,6 @@
#include "tegra20-common.h"
/* High-level configuration options */
-#define V_PROMPT "Tegra20 (Medcom-Wide) # "
#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Medcom-Wide"
/* Board-specific serial config */
diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index e16965c..626fa44 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -316,8 +316,6 @@
"1m(cramfs),-(jffs2)"
#endif
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_PROMPT "U-Boot-mONStR> "
/* size of console buffer */
#define CONFIG_SYS_CBSIZE 512
/* print buffer size */
diff --git a/include/configs/ml507.h b/include/configs/ml507.h
index b9ecb09..89a7290 100644
--- a/include/configs/ml507.h
+++ b/include/configs/ml507.h
@@ -24,7 +24,6 @@
#define CONFIG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CONFIG_ENV_OFFSET)
/*Misc*/
-#define CONFIG_SYS_PROMPT "ml507:/# " /* Monitor Command Prompt */
#define CONFIG_PREBOOT "echo U-Boot is up and runnining;"
/*Flash*/
diff --git a/include/configs/mt_ventoux.h b/include/configs/mt_ventoux.h
index dd516ac..3073db9 100644
--- a/include/configs/mt_ventoux.h
+++ b/include/configs/mt_ventoux.h
@@ -30,12 +30,6 @@
#define CONFIG_HOSTNAME mt_ventoux
/*
- * Miscellaneous configurable options
- */
-#define V_PROMPT "mt_ventoux => "
-#define CONFIG_SYS_PROMPT V_PROMPT
-
-/*
* Set its own mtdparts, different from common
*/
#undef MTDIDS_DEFAULT
diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h
index b90de14..92e5429 100644
--- a/include/configs/mv-common.h
+++ b/include/configs/mv-common.h
@@ -70,7 +70,6 @@
#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
-#define CONFIG_SYS_PROMPT "Marvell>> " /* Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */
diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h
index 7e709cd..72d28c9 100644
--- a/include/configs/mx31pdk.h
+++ b/include/configs/mx31pdk.h
@@ -35,6 +35,7 @@
#define CONFIG_SPL_MAX_SIZE 2048
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_TEXT_BASE 0x87dc0000
#define CONFIG_SYS_TEXT_BASE 0x87e00000
diff --git a/include/configs/mx51_efikamx.h b/include/configs/mx51_efikamx.h
index 22aec4f..373cfcb 100644
--- a/include/configs/mx51_efikamx.h
+++ b/include/configs/mx51_efikamx.h
@@ -205,7 +205,6 @@
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT "Efika> "
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h
index 436b022..6ae736f 100644
--- a/include/configs/mx6ul_14x14_evk.h
+++ b/include/configs/mx6ul_14x14_evk.h
@@ -151,7 +151,6 @@
"else run netboot; fi"
/* Miscellaneous configurable options */
-#define CONFIG_SYS_PROMPT "=> "
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
diff --git a/include/configs/mxs.h b/include/configs/mxs.h
index 38b1e93..9d823de 100644
--- a/include/configs/mxs.h
+++ b/include/configs/mxs.h
@@ -55,6 +55,7 @@
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
/* Memory sizes */
diff --git a/include/configs/nas220.h b/include/configs/nas220.h
index 61af61f..ebf6750 100644
--- a/include/configs/nas220.h
+++ b/include/configs/nas220.h
@@ -64,10 +64,6 @@
*/
#include "mv-common.h"
-/* Remove or override few declarations from mv-common.h */
-#undef CONFIG_SYS_PROMPT /* previously defined in mv-common.h */
-#define CONFIG_SYS_PROMPT "nas220> "
-
/*
* Environment variables configurations
*/
diff --git a/include/configs/nhk8815.h b/include/configs/nhk8815.h
index 8755be7..dd70adc 100644
--- a/include/configs/nhk8815.h
+++ b/include/configs/nhk8815.h
@@ -27,7 +27,6 @@
/* user interface */
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT "Nomadik> "
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h
index 7ec9965..915df52 100644
--- a/include/configs/nokia_rx51.h
+++ b/include/configs/nokia_rx51.h
@@ -396,7 +396,6 @@
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#define CONFIG_SYS_PROMPT "Nokia RX-51 # "
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h
index eac24d3..4b693e8 100644
--- a/include/configs/nyan-big.h
+++ b/include/configs/nyan-big.h
@@ -13,7 +13,6 @@
#include "tegra124-common.h"
/* High-level configuration options */
-#define V_PROMPT "Tegra124 (Nyan-big) # "
#define CONFIG_TEGRA_BOARD_STRING "Google/NVIDIA Nyan-big"
/* Board-specific serial config */
diff --git a/include/configs/odroid.h b/include/configs/odroid.h
index 69be496..1afe04a 100644
--- a/include/configs/odroid.h
+++ b/include/configs/odroid.h
@@ -14,9 +14,6 @@
#include <configs/exynos4-common.h>
-#define CONFIG_SYS_PROMPT "Odroid # " /* Monitor Command Prompt */
-
-
#define CONFIG_SYS_L2CACHE_OFF
#ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_L2_PL310
diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h
index 0deff46..3c70158 100644
--- a/include/configs/odroid_xu3.h
+++ b/include/configs/odroid_xu3.h
@@ -12,7 +12,6 @@
#include <configs/exynos5-common.h>
#undef CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_SYS_PROMPT "ODROID-XU3 # "
#define CONFIG_IDENT_STRING " for ODROID-XU3"
#define CONFIG_BOARD_COMMON
diff --git a/include/configs/odroid_xu3.h.rej b/include/configs/odroid_xu3.h.rej
new file mode 100644
index 0000000..a1c2964
--- /dev/null
+++ b/include/configs/odroid_xu3.h.rej
@@ -0,0 +1,10 @@
+--- include/configs/odroid_xu3.h
++++ include/configs/odroid_xu3.h
+@@ -10,7 +10,6 @@
+
+ #include "exynos5420-common.h"
+
+-#define CONFIG_SYS_PROMPT "ODROID-XU3 # "
+ #define CONFIG_IDENT_STRING " for ODROID-XU3"
+
+ #define CONFIG_BOARD_COMMON
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index dbe3e9b..f309b2e 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -296,7 +296,7 @@
#define CONFIG_SPL_OMAP3_ID_NAND
/* NAND boot config */
-#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
diff --git a/include/configs/omap3_cairo.h b/include/configs/omap3_cairo.h
index 81d4b34..713df3c 100644
--- a/include/configs/omap3_cairo.h
+++ b/include/configs/omap3_cairo.h
@@ -241,10 +241,6 @@
#define CONFIG_SERIAL2
#endif
-/* Keep old prompt in case some existing script depends on it */
-#undef CONFIG_SYS_PROMPT
-#define CONFIG_SYS_PROMPT "Cairo # "
-
/* Provide MACH_TYPE for compatibility with non-DT kernels */
#define MACH_TYPE_OMAP3_CAIRO 3063
#define CONFIG_MACH_TYPE MACH_TYPE_OMAP3_CAIRO
diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h
index 66c314f..7e7f6f2 100644
--- a/include/configs/omap3_evm_common.h
+++ b/include/configs/omap3_evm_common.h
@@ -120,7 +120,7 @@
/* Max number of NAND devices */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
/* Timeout values (in ticks) */
#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
@@ -179,7 +179,6 @@
* U-boot features
* ----------------------------------------------------------------------------
*/
-#define CONFIG_SYS_PROMPT "OMAP3_EVM # "
#define CONFIG_SYS_MAXARGS 16 /* max args for a command */
#define CONFIG_MISC_INIT_R
diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h
index 8785d8f..04433ed 100644
--- a/include/configs/omap3_igep00x0.h
+++ b/include/configs/omap3_igep00x0.h
@@ -193,7 +193,7 @@
/* NAND boot config */
#ifdef CONFIG_NAND
-#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
index af6ae73..e09e617 100644
--- a/include/configs/omap3_logic.h
+++ b/include/configs/omap3_logic.h
@@ -135,7 +135,7 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
/* NAND devices */
-#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV "nand0"
@@ -235,7 +235,6 @@
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT "OMAP Logic # "
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h
index 19543a1..9e2cf73 100644
--- a/include/configs/omap3_mvblx.h
+++ b/include/configs/omap3_mvblx.h
@@ -205,7 +205,6 @@
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT "mvblx # "
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index a1a90ec..53ff61d 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -186,12 +186,6 @@
"fi;" \
"run nanddtsboot; " \
-/*
- * Miscellaneous configurable options
- */
-#undef CONFIG_SYS_PROMPT
-#define CONFIG_SYS_PROMPT "Overo # "
-
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
@@ -227,7 +221,7 @@
#define CONFIG_SYS_CACHELINE_SIZE 64
/* NAND boot config */
-#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
#define CONFIG_SYS_NAND_MAX_ECCPOS 56
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT 64
diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h
index 49467c9..4e93705 100644
--- a/include/configs/omap3_pandora.h
+++ b/include/configs/omap3_pandora.h
@@ -64,7 +64,7 @@
*/
#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
/* to access nand */
-#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64
@@ -101,12 +101,6 @@
"ubi part boot && ubifsmount ubi:boot && " \
"ubifsload ${loadaddr} uImage && bootm ${loadaddr}"
-/*
- * Miscellaneous configurable options
- */
-#undef CONFIG_SYS_PROMPT
-#define CONFIG_SYS_PROMPT "Pandora # "
-
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h
index 16ceb91..f43e477 100644
--- a/include/configs/omap3_sdp3430.h
+++ b/include/configs/omap3_sdp3430.h
@@ -240,7 +240,6 @@
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT "OMAP34XX SDP # "
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h
index 2d1d53d..cef2243 100644
--- a/include/configs/omap3_zoom1.h
+++ b/include/configs/omap3_zoom1.h
@@ -97,7 +97,7 @@
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access nand at */
/* CS0 */
-#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
/* Environment information */
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index 6d0d020..d9a3aa4 100644
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h
@@ -199,7 +199,6 @@
#define CONFIG_MISC_INIT_R
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_PROMPT "U-Boot > " /* Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
diff --git a/include/configs/origen.h b/include/configs/origen.h
index dae8fd5..21d8e7a 100644
--- a/include/configs/origen.h
+++ b/include/configs/origen.h
@@ -11,9 +11,6 @@
#include <configs/exynos4-common.h>
-#define CONFIG_SYS_PROMPT "ORIGEN # "
-
-
/* High Level Configuration Options */
#define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */
#define CONFIG_ORIGEN 1 /* working with ORIGEN*/
diff --git a/include/configs/palmld.h b/include/configs/palmld.h
index a9f92fa..ec48c14 100644
--- a/include/configs/palmld.h
+++ b/include/configs/palmld.h
@@ -96,9 +96,6 @@
#define CONFIG_SYS_HUSH_PARSER 1
#define CONFIG_SYS_LONGHELP
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT "$ "
-#endif
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
diff --git a/include/configs/palmtc.h b/include/configs/palmtc.h
index b68ad3b..81c3f02 100644
--- a/include/configs/palmtc.h
+++ b/include/configs/palmtc.h
@@ -99,9 +99,6 @@
#define CONFIG_SYS_HUSH_PARSER 1
#define CONFIG_SYS_LONGHELP
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT "$ "
-#endif
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
diff --git a/include/configs/palmtreo680.h b/include/configs/palmtreo680.h
index 3946607..ffb0d1e 100644
--- a/include/configs/palmtreo680.h
+++ b/include/configs/palmtreo680.h
@@ -92,6 +92,7 @@
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_LONGHELP
+#undef CONFIG_SYS_PROMPT
#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT "$ "
#else
diff --git a/include/configs/paz00.h b/include/configs/paz00.h
index 0bdeccc..8eac81a 100644
--- a/include/configs/paz00.h
+++ b/include/configs/paz00.h
@@ -21,7 +21,6 @@
#include "tegra20-common.h"
/* High-level configuration options */
-#define V_PROMPT "Tegra20 (Paz00) MOD # "
#define CONFIG_TEGRA_BOARD_STRING "Compal Paz00"
/* Board-specific serial config */
diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h
index af2654e..516d381 100644
--- a/include/configs/pb1x00.h
+++ b/include/configs/pb1x00.h
@@ -52,7 +52,6 @@
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "Pb1x00 # " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
diff --git a/include/configs/pcm030.h b/include/configs/pcm030.h
index 83c96a8..29feb7b 100644
--- a/include/configs/pcm030.h
+++ b/include/configs/pcm030.h
@@ -337,7 +337,6 @@
Miscellaneous configurable options
-------------------------------------------------------------------------------*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
diff --git a/include/configs/peach-pi.h b/include/configs/peach-pi.h
index 0f5e9fe..6c42aaa 100644
--- a/include/configs/peach-pi.h
+++ b/include/configs/peach-pi.h
@@ -29,7 +29,6 @@
#define CONFIG_SERIAL3 /* use SERIAL 3 */
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
-#define CONFIG_SYS_PROMPT "Peach-Pi # "
#define CONFIG_IDENT_STRING " for Peach-Pi"
/* Display */
diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h
index f259434..6c68dd2 100644
--- a/include/configs/peach-pit.h
+++ b/include/configs/peach-pit.h
@@ -29,7 +29,6 @@
#define CONFIG_SERIAL3 /* use SERIAL 3 */
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
-#define CONFIG_SYS_PROMPT "Peach-Pit # "
#define CONFIG_IDENT_STRING " for Peach-Pit"
/* DRAM Memory Banks */
diff --git a/include/configs/pepper.h b/include/configs/pepper.h
index 0bdcf22..1bc8c4b 100644
--- a/include/configs/pepper.h
+++ b/include/configs/pepper.h
@@ -17,9 +17,6 @@
#define V_OSCK 24000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
-#undef CONFIG_SYS_PROMPT
-#define CONFIG_SYS_PROMPT "pepper# "
-
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
/* Mach type */
diff --git a/include/configs/platinum_picon.h b/include/configs/platinum_picon.h
index f5b476f..3679530 100644
--- a/include/configs/platinum_picon.h
+++ b/include/configs/platinum_picon.h
@@ -19,8 +19,6 @@
#define CONFIG_HOSTNAME picon
-#define CONFIG_SYS_PROMPT "picon > "
-
#define CONFIG_PLATFORM_ENV_SETTINGS "\0"
#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_COMMON_ENV_SETTINGS \
diff --git a/include/configs/platinum_titanium.h b/include/configs/platinum_titanium.h
index 9bca10f..ccb6441 100644
--- a/include/configs/platinum_titanium.h
+++ b/include/configs/platinum_titanium.h
@@ -26,8 +26,6 @@
#define CONFIG_HOSTNAME titanium
-#define CONFIG_SYS_PROMPT "titanium > "
-
#define CONFIG_PLATFORM_ENV_SETTINGS "\0"
#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_COMMON_ENV_SETTINGS \
diff --git a/include/configs/plutux.h b/include/configs/plutux.h
index 7f7ea97..1d6df32 100644
--- a/include/configs/plutux.h
+++ b/include/configs/plutux.h
@@ -13,7 +13,6 @@
#include "tegra20-common.h"
/* High-level configuration options */
-#define V_PROMPT "Tegra20 (Plutux) # "
#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Plutux"
/* Board-specific serial config */
diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h
index f9a1d51..f4f96a7 100644
--- a/include/configs/pm9261.h
+++ b/include/configs/pm9261.h
@@ -336,7 +336,6 @@
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_PROMPT "pm9261> "
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_PBSIZE \
diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h
index 6c434f0..bd43577 100644
--- a/include/configs/pm9263.h
+++ b/include/configs/pm9263.h
@@ -370,7 +370,6 @@
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_PROMPT "u-boot-pm9263> "
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_PBSIZE \
diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h
index c793865..09f0744 100644
--- a/include/configs/pm9g45.h
+++ b/include/configs/pm9g45.h
@@ -149,7 +149,6 @@
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_PROMPT "U-Boot> "
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
diff --git a/include/configs/pogo_e02.h b/include/configs/pogo_e02.h
index 3a0992a..8cf3ad8 100644
--- a/include/configs/pogo_e02.h
+++ b/include/configs/pogo_e02.h
@@ -47,10 +47,6 @@
*/
#include "mv-common.h"
-/* Remove or override few declarations from mv-common.h */
-#undef CONFIG_SYS_PROMPT /* previously defined in mv-common.h */
-#define CONFIG_SYS_PROMPT "PogoE02> "
-
/*
* Environment variables configurations
*/
diff --git a/include/configs/pr1.h b/include/configs/pr1.h
index 3e4aab4..f76e023 100644
--- a/include/configs/pr1.h
+++ b/include/configs/pr1.h
@@ -128,7 +128,6 @@
#define CONFIG_BAUDRATE 115200
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 0
-#define CONFIG_SYS_PROMPT "pr1>"
#define CONFIG_BOOTCOMMAND "run nandboot"
#define CONFIG_BOOTDELAY 2
#define CONFIG_LOADADDR 0x2000000
diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h
index 3edeb08..332d79f 100644
--- a/include/configs/pxa255_idp.h
+++ b/include/configs/pxa255_idp.h
@@ -205,6 +205,7 @@
#define CONFIG_SYS_HUSH_PARSER 1
#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#undef CONFIG_SYS_PROMPT
#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
#else
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index b22637b..a7ec8f5 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -78,6 +78,7 @@
#define CONFIG_SYS_LONGHELP /* undef to save memory */
/* Monitor Command Prompt */
+#undef CONFIG_SYS_PROMPT
#if defined(CONFIG_SYS_LITTLE_ENDIAN)
#define CONFIG_SYS_PROMPT "qemu-mipsel # "
#else
diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h
index fae5b05..4de15bf 100644
--- a/include/configs/qemu-mips64.h
+++ b/include/configs/qemu-mips64.h
@@ -80,6 +80,7 @@
#define CONFIG_SYS_LONGHELP /* undef to save memory */
/* Monitor Command Prompt */
+#undef CONFIG_SYS_PROMPT
#if defined(CONFIG_SYS_LITTLE_ENDIAN)
#define CONFIG_SYS_PROMPT "qemu-mips64el # "
#else
diff --git a/include/configs/rpi-common.h b/include/configs/rpi-common.h
index 1012cdd..8830a10 100644
--- a/include/configs/rpi-common.h
+++ b/include/configs/rpi-common.h
@@ -14,7 +14,6 @@
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_BCM2835
#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_SYS_TIMER_RATE 1000000
#define CONFIG_SYS_TIMER_COUNTER \
@@ -116,7 +115,6 @@
/* Shell */
#define CONFIG_SYS_MAXARGS 8
-#define CONFIG_SYS_PROMPT "U-Boot> "
#define CONFIG_COMMAND_HISTORY
/* Commands */
diff --git a/include/configs/rpi.h b/include/configs/rpi.h
index ab2f4db..86422e3 100644
--- a/include/configs/rpi.h
+++ b/include/configs/rpi.h
@@ -7,6 +7,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
#include "rpi-common.h"
#endif
diff --git a/include/configs/rpi_2.h b/include/configs/rpi_2.h
index 2e7e74f..bea4ebd 100644
--- a/include/configs/rpi_2.h
+++ b/include/configs/rpi_2.h
@@ -9,6 +9,8 @@
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BCM2836
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_SYS_DCACHE_OFF
#include "rpi-common.h"
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
index 235bba5..aff264b 100644
--- a/include/configs/s5p_goni.h
+++ b/include/configs/s5p_goni.h
@@ -197,7 +197,6 @@
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT "Goni # "
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h
index e7bace4..35fef2b 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h
@@ -12,9 +12,6 @@
#include <configs/exynos4-common.h>
-#define CONFIG_SYS_PROMPT "Universal # " /* Monitor Command Prompt */
-
-
#define CONFIG_TIZEN /* TIZEN lib */
/* Keep L2 Cache Disabled */
diff --git a/include/configs/scb9328.h b/include/configs/scb9328.h
index f367d62..d4ffb46 100644
--- a/include/configs/scb9328.h
+++ b/include/configs/scb9328.h
@@ -51,7 +51,6 @@
* General options for u-boot. Modify to save memory foot print
*/
#define CONFIG_SYS_LONGHELP /* undef saves memory */
-#define CONFIG_SYS_PROMPT "scb9328> " /* prompt string */
#define CONFIG_SYS_CBSIZE 256 /* console I/O buffer */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* print buffer size */
#define CONFIG_SYS_MAXARGS 16 /* max command args */
diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
index fdeffb5..3e90474 100644
--- a/include/configs/seaboard.h
+++ b/include/configs/seaboard.h
@@ -20,7 +20,6 @@
#include "tegra20-common.h"
/* High-level configuration options */
-#define V_PROMPT "Tegra20 (SeaBoard) # "
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Seaboard"
/* Board-specific serial config */
diff --git a/include/configs/secomx6quq7.h b/include/configs/secomx6quq7.h
index 114d1fd..703f4fc 100644
--- a/include/configs/secomx6quq7.h
+++ b/include/configs/secomx6quq7.h
@@ -74,9 +74,6 @@
"stderr=serial\0"
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_PROMPT "SECO MX6Q uQ7 U-Boot > "
-
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index ceac5e0..bcc8dcb 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -27,7 +27,6 @@
#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024)
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT "U-Boot# "
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_SYS_NO_FLASH
diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h
new file mode 100644
index 0000000..d696d4b
--- /dev/null
+++ b/include/configs/smartweb.h
@@ -0,0 +1,288 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2010
+ * Achim Ehrlich <aehrlich@taskit.de>
+ * taskit GmbH <www.taskit.de>
+ *
+ * (C) Copyright 2012
+ * Markus Hubig <mhubig@imko.de>
+ * IMKO GmbH <www.imko.de>
+ *
+ * (C) Copyright 2014
+ * Heiko Schocher <hs@denx.de>
+ * DENX Software Engineering GmbH
+ *
+ * Configuation settings for the smartweb.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * SoC must be defined first, before hardware.h is included.
+ * In this case SoC is defined in boards.cfg.
+ */
+#include <asm/hardware.h>
+
+/*
+ * Warning: changing CONFIG_SYS_TEXT_BASE requires adapting the initial boot
+ * program. Since the linker has to swallow that define, we must use a pure
+ * hex number here!
+ */
+#define CONFIG_SYS_TEXT_BASE 0x23000000
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432MHz crystal */
+
+/* misc settings */
+#define CONFIG_CMDLINE_TAG /* pass commandline to Kernel */
+#define CONFIG_SETUP_MEMORY_TAGS /* pass memory defs to kernel */
+#define CONFIG_INITRD_TAG /* pass initrd param to kernel */
+#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
+#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
+#define CONFIG_DISPLAY_CPUINFO /* display CPU Info at startup */
+
+/* setting board specific options */
+# define CONFIG_MACH_TYPE MACH_TYPE_SMARTWEB
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+
+/* The LED PINs */
+#define CONFIG_RED_LED AT91_PIN_PA9
+#define CONFIG_GREEN_LED AT91_PIN_PA6
+
+/*
+ * SDRAM: 1 bank, 64 MB, base address 0x20000000
+ * Already initialized before u-boot gets started.
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
+#define CONFIG_SYS_SDRAM_SIZE (64 << 20)
+
+/*
+ * Perform a SDRAM Memtest from the start of SDRAM
+ * till the beginning of the U-Boot position in RAM.
+ */
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN \
+ ROUND(3 * CONFIG_ENV_SIZE + (128 << 10), 0x1000)
+
+/* NAND flash settings */
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_DBW_8
+#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
+
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define MTDIDS_NAME_STR "atmel_nand"
+#define MTDIDS_DEFAULT "nand0=" MTDIDS_NAME_STR
+#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
+ "128k(Bootstrap)," \
+ "896k(U-Boot)," \
+ "512k(ENV0)," \
+ "512k(ENV1)," \
+ "4M(Linux)," \
+ "-(Root-FS)"
+
+/* general purpose I/O */
+#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
+#define CONFIG_AT91_GPIO /* enable the GPIO features */
+#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE ATMEL_BASE_DBGU
+#define CONFIG_USART_ID ATMEL_ID_SYS
+#define CONFIG_BAUDRATE 115200
+
+/*
+ * Ethernet configuration
+ *
+ */
+#define CONFIG_MACB
+#define CONFIG_RMII /* use reduced MII inteface */
+#define CONFIG_NET_RETRY_COUNT 20 /* # of DHCP/BOOTP retries */
+#define CONFIG_AT91_WANTS_COMMON_PHY
+
+/* BOOTP and DHCP options */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv autoload yes; setenv autoboot yes; " \
+ "setenv bootargs ${basicargs} ${mtdparts} " \
+ "root=/dev/nfs ip=dhcp nfsroot=${serverip}:/srv/nfs/rootfs; " \
+ "dhcp"
+
+/* Enable the watchdog */
+#define CONFIG_AT91SAM9_WATCHDOG
+#if !defined(CONFIG_SPL_BUILD)
+#define CONFIG_HW_WATCHDOG
+#endif
+#define CONFIG_AT91_HW_WDT_TIMEOUT 15
+
+#if !defined(CONFIG_SPL_BUILD)
+/* USB configuration */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#endif
+
+/* General Boot Parameter */
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTCOMMAND "run flashboot"
+#define CONFIG_SYS_CBSIZE 512
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+
+/*
+ * RAM Memory address where to put the
+ * Linux Kernel befor starting.
+ */
+#define CONFIG_SYS_LOAD_ADDR 0x22000000
+
+/*
+ * The NAND Flash partitions:
+ */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET (0x100000)
+#define CONFIG_ENV_OFFSET_REDUND (0x180000)
+#define CONFIG_ENV_RANGE (0x80000)
+#define CONFIG_ENV_SIZE (0x20000)
+
+/*
+ * Predefined environment variables.
+ * Usefull to define some easy to use boot commands.
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ \
+ "basicargs=console=ttyS0,115200\0" \
+ \
+ "mtdparts="MTDPARTS_DEFAULT"\0"
+
+/* Command line & features configuration */
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_LOADS
+
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_FAT
+
+#ifdef CONFIG_MACB
+# define CONFIG_CMD_PING
+# define CONFIG_CMD_DHCP
+#else
+# undef CONFIG_CMD_BOOTD
+# undef CONFIG_CMD_NET
+# undef CONFIG_CMD_NFS
+#endif /* CONFIG_MACB */
+
+#if !defined(CONFIG_SPL_BUILD)
+/* Enable Device-Tree (FDT) support */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_FDT
+#define CONFIG_FIT
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_INIT_SP_ADDR 0x301000
+#define CONFIG_SPL_STACK_R
+#define CONFIG_SPL_STACK_R_ADDR CONFIG_SYS_TEXT_BASE
+#else
+/*
+ * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
+ * leaving the correct space for initial global data structure above that
+ * address while providing maximum stack area below.
+ */
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
+#endif
+
+
+/* Defines for SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE 0x0
+#define CONFIG_SPL_MAX_SIZE (4 * 1024)
+
+#define CONFIG_SPL_BSS_START_ADDR CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SPL_BSS_MAX_SIZE (16 * 1024)
+#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
+ CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14)
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SYS_USE_NANDFLASH 1
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_NAND_RAW_ONLY
+#define CONFIG_SPL_NAND_SOFTECC
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+
+#define CONFIG_SYS_NAND_SIZE (256*1024*1024)
+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
+#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
+ CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCSIZE 256
+#define CONFIG_SYS_NAND_ECCBYTES 3
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
+ 48, 49, 50, 51, 52, 53, 54, 55, \
+ 56, 57, 58, 59, 60, 61, 62, 63, }
+
+#define CONFIG_SPL_ATMEL_SIZE
+#define CONFIG_SYS_MASTER_CLOCK (198656000/2)
+#define AT91_PLL_LOCK_TIMEOUT 1000000
+#define CONFIG_SYS_AT91_PLLA 0x2060bf09
+#define CONFIG_SYS_MCKR 0x100
+#define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR)
+#define CONFIG_SYS_AT91_PLLB 0x10483f0e
+
+#if defined(CONFIG_SPL_BUILD)
+#define CONFIG_SYS_THUMB_BUILD
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
+#undef CONFIG_SPL_OS_BOOT /* Not supported by existing map */
+#endif
+#endif /* __CONFIG_H */
diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h
index 7b4b3b0..a6bfa76 100644
--- a/include/configs/smdk2410.h
+++ b/include/configs/smdk2410.h
@@ -106,7 +106,6 @@
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "SMDK2410 # "
#define CONFIG_SYS_CBSIZE 256
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h
index 82d41cc..f66bb12 100644
--- a/include/configs/smdk5250.h
+++ b/include/configs/smdk5250.h
@@ -17,7 +17,6 @@
#define CONFIG_BOARD_COMMON
-#define CONFIG_SYS_PROMPT "SMDK5250 # "
#define CONFIG_IDENT_STRING " for SMDK5250"
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h
index 623efa8..9cf886c 100644
--- a/include/configs/smdk5420.h
+++ b/include/configs/smdk5420.h
@@ -27,7 +27,6 @@
#define CONFIG_SERIAL3 /* use SERIAL 3 */
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
-#define CONFIG_SYS_PROMPT "SMDK5420 # "
#define CONFIG_IDENT_STRING " for SMDK5420"
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h
index 08a2e9f..4ec9c65 100644
--- a/include/configs/smdkc100.h
+++ b/include/configs/smdkc100.h
@@ -152,7 +152,6 @@
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT "SMDKC100 # "
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h
index d26e5ec..dbba88b 100644
--- a/include/configs/smdkv310.h
+++ b/include/configs/smdkv310.h
@@ -55,7 +55,6 @@
#define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000"
/* Miscellaneous configurable options */
-#define CONFIG_SYS_PROMPT "SMDKV310 # "
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h
index 70ef939..7758b0f 100644
--- a/include/configs/snapper9260.h
+++ b/include/configs/snapper9260.h
@@ -89,7 +89,6 @@
#define CONFIG_USART_ID ATMEL_ID_SYS
#endif
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_PROMPT "Snapper> "
/* I2C - Bit-bashed */
#define CONFIG_SYS_I2C
diff --git a/include/configs/sniper.h b/include/configs/sniper.h
new file mode 100644
index 0000000..a0ee5bd
--- /dev/null
+++ b/include/configs/sniper.h
@@ -0,0 +1,307 @@
+/*
+ * LG Optimus Black (P970) codename sniper config
+ *
+ * Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap.h>
+
+/*
+ * CPU
+ */
+
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
+#define CONFIG_ARM_ARCH_CP15_ERRATA
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
+
+/*
+ * Platform
+ */
+
+#define CONFIG_OMAP
+#define CONFIG_OMAP_COMMON
+
+/*
+ * Board
+ */
+
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_MISC_INIT_R
+
+/*
+ * Clocks
+ */
+
+#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
+#define CONFIG_SYS_PTV 2
+
+#define V_NS16550_CLK 48000000
+#define V_OSCK 26000000
+#define V_SCLK (V_OSCK >> 1)
+
+/*
+ * DRAM
+ */
+
+#define CONFIG_SDRC
+#define CONFIG_NR_DRAM_BANKS 2
+#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
+
+/*
+ * Memory
+ */
+
+#define CONFIG_SYS_TEXT_BASE 0x80100000
+#define CONFIG_SYS_SDRAM_BASE OMAP34XX_SDRC_CS0
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020F800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024 + CONFIG_ENV_SIZE)
+
+/*
+ * GPIO
+ */
+
+#define CONFIG_OMAP_GPIO
+#define CONFIG_OMAP3_GPIO_2
+#define CONFIG_OMAP3_GPIO_3
+#define CONFIG_OMAP3_GPIO_4
+#define CONFIG_OMAP3_GPIO_5
+#define CONFIG_OMAP3_GPIO_6
+
+/*
+ * I2C
+ */
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED 400000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_OMAP34XX
+#define CONFIG_I2C_MULTI_BUS
+
+#define CONFIG_CMD_I2C
+
+/*
+ * Flash
+ */
+
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * MMC
+ */
+
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_OMAP_HSMMC
+
+#define CONFIG_CMD_MMC
+
+/*
+ * Power
+ */
+
+#define CONFIG_TWL4030_POWER
+
+/*
+ * Input
+ */
+
+#define CONFIG_TWL4030_INPUT
+
+/*
+ * Partitions
+ */
+
+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+
+#define CONFIG_CMD_PART
+
+/*
+ * Filesystems
+ */
+
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_FAT
+
+/*
+ * SPL
+ */
+
+#define CONFIG_SPL_FRAMEWORK
+
+#define CONFIG_SPL_TEXT_BASE 0x40200000
+#define CONFIG_SPL_MAX_SIZE (54 * 1024)
+#define CONFIG_SPL_BSS_START_ADDR 0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE (512 * 1024)
+#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE (1024 * 1024)
+#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+#define CONFIG_SPL_BOARD_INIT
+
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 2
+
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
+
+/*
+ * Console
+ */
+
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_AUTO_COMPLETE
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_CBSIZE 512
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) \
+ + 16)
+
+/*
+ * Serial
+ */
+
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_OMAP_SERIAL
+#else
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+#endif
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_SERIAL3 3
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, \
+ 115200 }
+
+/*
+ * USB gadget
+ */
+
+#define CONFIG_USB_MUSB_PIO_ONLY
+#define CONFIG_USB_MUSB_OMAP2PLUS
+#define CONFIG_TWL4030_USB
+
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_VBUS_DRAW 0
+
+/*
+ * Download
+ */
+
+#define CONFIG_USB_GADGET_DOWNLOAD
+
+#define CONFIG_G_DNL_VENDOR_NUM 0x0451
+#define CONFIG_G_DNL_PRODUCT_NUM 0xd022
+#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
+
+/*
+ * Fastboot
+ */
+
+#define CONFIG_USB_FUNCTION_FASTBOOT
+
+#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
+#define CONFIG_FASTBOOT_BUF_SIZE 0x2000000
+
+#define CONFIG_FASTBOOT_FLASH
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 0
+
+#define CONFIG_CMD_FASTBOOT
+
+/*
+ * Environment
+ */
+
+#define CONFIG_ENV_SIZE (128 * 1024)
+#define CONFIG_ENV_IS_NOWHERE
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "kernel_addr_r=0x82000000\0" \
+ "boot_mmc_dev=0\0" \
+ "kernel_mmc_part=3\0" \
+ "recovery_mmc_part=4\0" \
+ "bootargs=console=ttyO2 vram=5M,0x9FA00000 omapfb.vram=0:5M\0"
+
+/*
+ * ATAGs / Device Tree
+ */
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SERIAL_TAG
+
+/*
+ * Boot
+ */
+
+#define CONFIG_SYS_LOAD_ADDR 0x82000000
+#define CONFIG_BOOTDELAY 1
+
+#define CONFIG_ANDROID_BOOT_IMAGE
+
+#define CONFIG_BOOTCOMMAND \
+ "setenv boot_mmc_part ${kernel_mmc_part}; " \
+ "if test reboot-${reboot-mode} = reboot-r; then " \
+ "echo recovery; setenv boot_mmc_part ${recovery_mmc_part}; fi; " \
+ "if test reboot-${reboot-mode} = reboot-b; then " \
+ "echo fastboot; fastboot 0; fi; " \
+ "part start mmc ${boot_mmc_dev} ${boot_mmc_part} boot_mmc_start; " \
+ "part size mmc ${boot_mmc_dev} ${boot_mmc_part} boot_mmc_size; " \
+ "mmc dev ${boot_mmc_dev}; " \
+ "mmc read ${kernel_addr_r} ${boot_mmc_start} ${boot_mmc_size} && " \
+ "bootm ${kernel_addr_r};"
+
+/*
+ * Defaults
+ */
+
+#include <config_defaults.h>
+
+#endif
diff --git a/include/configs/snow.h b/include/configs/snow.h
index bf3377c..1d8d8da 100644
--- a/include/configs/snow.h
+++ b/include/configs/snow.h
@@ -15,7 +15,6 @@
#define CONFIG_BOARD_COMMON
-#define CONFIG_SYS_PROMPT "snow # "
#define CONFIG_IDENT_STRING " for snow"
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
diff --git a/include/configs/snowball.h b/include/configs/snowball.h
index 91aaffa..de03e76 100644
--- a/include/configs/snowball.h
+++ b/include/configs/snowball.h
@@ -154,7 +154,6 @@
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "U8500 $ " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
/* Print Buffer Size */
diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
index f75c306..fb1bf66 100644
--- a/include/configs/spear-common.h
+++ b/include/configs/spear-common.h
@@ -201,7 +201,6 @@
#define CONFIG_SYS_MALLOC_LEN (1024*1024)
#define CONFIG_IDENT_STRING "-SPEAr"
#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_PROMPT "u-boot> "
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
diff --git a/include/configs/spring.h b/include/configs/spring.h
index a692dfd..8940123 100644
--- a/include/configs/spring.h
+++ b/include/configs/spring.h
@@ -13,7 +13,6 @@
#define CONFIG_BOARD_COMMON
-#define CONFIG_SYS_PROMPT "spring # "
#define CONFIG_IDENT_STRING " for spring"
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
diff --git a/include/configs/stamp9g20.h b/include/configs/stamp9g20.h
index 086ebcf..87df70b 100644
--- a/include/configs/stamp9g20.h
+++ b/include/configs/stamp9g20.h
@@ -180,7 +180,6 @@
/* General Boot Parameter */
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTCOMMAND "run flashboot"
-#define CONFIG_SYS_PROMPT "U-Boot> "
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_PBSIZE \
diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h
index 1ac3db6..19d9cf9 100644
--- a/include/configs/stm32f429-discovery.h
+++ b/include/configs/stm32f429-discovery.h
@@ -100,7 +100,6 @@
*/
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT "U-Boot > "
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h
index 887f31a..b1b6919 100644
--- a/include/configs/stv0991.h
+++ b/include/configs/stv0991.h
@@ -36,7 +36,6 @@
#define CONFIG_PL01X_SERIAL
/* user interface */
-#define CONFIG_SYS_PROMPT "STV0991> "
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+sizeof(CONFIG_SYS_PROMPT) + 16)
diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h
index 6676f37..25b7d5f 100644
--- a/include/configs/stxgp3.h
+++ b/include/configs/stxgp3.h
@@ -315,7 +315,6 @@
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "GPPP=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h
index 5b1f3ab..ee16fea 100644
--- a/include/configs/stxssa.h
+++ b/include/configs/stxssa.h
@@ -349,7 +349,6 @@
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "SSA=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index a2cbcf5..0ecb91b 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -50,8 +50,6 @@
*/
#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_SYS_PROMPT "sunxi# "
-
/* Serial & console */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h
index 34f1228..801220a 100644
--- a/include/configs/tam3517-common.h
+++ b/include/configs/tam3517-common.h
@@ -241,7 +241,7 @@
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
/* NAND boot config */
-#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64
diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h
index c8ec79b..408895f 100644
--- a/include/configs/tao3530.h
+++ b/include/configs/tao3530.h
@@ -136,7 +136,7 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
-#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
/* Environment information */
#define CONFIG_BOOTDELAY 3
@@ -196,7 +196,6 @@
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT "TAO-3530 # "
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* turn on command-line edit/hist/auto */
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
index d5b93eb..2c9f5da 100644
--- a/include/configs/taurus.h
+++ b/include/configs/taurus.h
@@ -165,7 +165,6 @@
"512k(dtb),6M(kernel)ro,-(rootfs) " \
"root=/dev/mtdblock7 rw rootfstype=jffs2"
-#define CONFIG_SYS_PROMPT "U-Boot> "
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_PBSIZE \
diff --git a/include/configs/tb100.h b/include/configs/tb100.h
index 42817ae..41c2c72 100644
--- a/include/configs/tb100.h
+++ b/include/configs/tb100.h
@@ -96,7 +96,6 @@
* Console configuration
*/
#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_PROMPT "[tb100]:~# "
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h
index 14985f8..66cb274 100644
--- a/include/configs/tbs2910.h
+++ b/include/configs/tbs2910.h
@@ -18,7 +18,6 @@
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_SYS_PROMPT "Matrix U-Boot> "
#define CONFIG_SYS_HZ 1000
#define CONFIG_IMX6_THERMAL
diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h
index 08345cc..3297424 100644
--- a/include/configs/tec-ng.h
+++ b/include/configs/tec-ng.h
@@ -11,7 +11,6 @@
#include "tegra30-common.h"
/* High-level configuration options */
-#define V_PROMPT "Tegra30 (TEC-NG) # "
#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Tamonten™ NG Evaluation Carrier"
/* Board-specific serial config */
diff --git a/include/configs/tec.h b/include/configs/tec.h
index 3b543eb..4b8ca5e 100644
--- a/include/configs/tec.h
+++ b/include/configs/tec.h
@@ -13,7 +13,6 @@
#include "tegra20-common.h"
/* High-level configuration options */
-#define V_PROMPT "Tegra20 (TEC) # "
#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Tamonten Evaluation Carrier"
/* Board-specific serial config */
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
index ffe167e..145f635 100644
--- a/include/configs/tegra-common.h
+++ b/include/configs/tegra-common.h
@@ -88,10 +88,6 @@
#endif
/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_PROMPT V_PROMPT
-/*
* Increasing the size of the IO buffer as default nfsargs size is more
* than 256 and so it is not possible to edit it
*/
diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h
index fcfb70e..7fa35a1 100644
--- a/include/configs/ti814x_evm.h
+++ b/include/configs/ti814x_evm.h
@@ -28,7 +28,6 @@
#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* Use HUSH for command parsing */
-#define CONFIG_SYS_PROMPT "U-Boot# "
#define CONFIG_SYS_NO_FLASH
#define CONFIG_MACH_TYPE MACH_TYPE_TI8148EVM
diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h
index 8d52057..01d8233 100644
--- a/include/configs/ti816x_evm.h
+++ b/include/configs/ti816x_evm.h
@@ -24,7 +24,6 @@
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (32 * 1024))
#define CONFIG_SYS_LONGHELP /* undef save memory */
#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT "u-boot/ti816x# "
#define CONFIG_MACH_TYPE MACH_TYPE_TI8168EVM
#define CONFIG_OF_LIBFDT
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index 6dc5ebd..18fca02 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -115,7 +115,6 @@
#define CONFIG_SYS_MALLOC_LEN (16 << 20)
#endif
#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT "U-Boot# "
#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_BAUDRATE 115200
#define CONFIG_ENV_VARS_UBOOT_CONFIG /* Strongly encouraged */
diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h
index af89f70..b441590 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -15,6 +15,7 @@
/* U-Boot Build Configuration */
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage loader */
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_CPUINFO
/* SoC Configuration */
#define CONFIG_ARCH_CPU_INIT
@@ -254,7 +255,7 @@
"init_ramfs=run args_all args_ramfs get_fs_ramfs\0" \
"args_ramfs=setenv bootargs ${bootargs} " \
"rdinit=/sbin/init rw root=/dev/ram0 " \
- "initrd=0x802000000,9M\0" \
+ "initrd=0x808080000,80M\0" \
"no_post=1\0" \
"mtdparts=mtdparts=davinci_nand.0:" \
"1024k(bootloader)ro,512k(params)ro,-(ubifs)\0"
diff --git a/include/configs/titanium.h b/include/configs/titanium.h
index 49aa3c7..1b4ca29 100644
--- a/include/configs/titanium.h
+++ b/include/configs/titanium.h
@@ -141,9 +141,6 @@
#define CONFIG_BOOTCOMMAND "run nand_ubifs"
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_PROMPT "Titanium > "
-
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
diff --git a/include/configs/trats.h b/include/configs/trats.h
index 6808e78..5fb991b 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -12,8 +12,6 @@
#include <configs/exynos4-common.h>
-#define CONFIG_SYS_PROMPT "Trats # " /* Monitor Command Prompt */
-
#define CONFIG_TRATS
diff --git a/include/configs/trats2.h b/include/configs/trats2.h
index 94c31fb..f12a952 100644
--- a/include/configs/trats2.h
+++ b/include/configs/trats2.h
@@ -13,9 +13,6 @@
#include <configs/exynos4-common.h>
-#define CONFIG_SYS_PROMPT "Trats2 # " /* Monitor Command Prompt */
-
-
#define CONFIG_TIZEN /* TIZEN lib */
#define CONFIG_SYS_L2CACHE_OFF
diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h
index 23bf599..f04b572 100644
--- a/include/configs/tricorder.h
+++ b/include/configs/tricorder.h
@@ -284,7 +284,6 @@
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_CMDLINE_EDITING /* enable cmdline history */
#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_PROMPT "OMAP3 Tricorder # "
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h
index 2db38e5..2ab5511 100644
--- a/include/configs/trimslice.h
+++ b/include/configs/trimslice.h
@@ -12,7 +12,6 @@
#include "tegra20-common.h"
/* High-level configuration options */
-#define V_PROMPT "Tegra20 (TrimSlice) # "
#define CONFIG_TEGRA_BOARD_STRING "Compulab Trimslice"
/* Board-specific serial config */
diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h
index 8368931..40c8d71 100644
--- a/include/configs/trizepsiv.h
+++ b/include/configs/trizepsiv.h
@@ -130,6 +130,7 @@
#define CONFIG_SYS_HUSH_PARSER 1
#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#undef CONFIG_SYS_PROMPT
#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
#else
diff --git a/include/configs/tt01.h b/include/configs/tt01.h
index 9501a83..ca1e2e2 100644
--- a/include/configs/tt01.h
+++ b/include/configs/tt01.h
@@ -224,7 +224,6 @@
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "TT01> "
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
diff --git a/include/configs/twister.h b/include/configs/twister.h
index f24dc13..4f5560f 100644
--- a/include/configs/twister.h
+++ b/include/configs/twister.h
@@ -29,8 +29,6 @@
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_PROMPT "twister => "
-
#define CONFIG_SMC911X
#define CONFIG_SMC911X_16_BIT
#define CONFIG_SMC911X_BASE 0x2C000000
diff --git a/include/configs/tx25.h b/include/configs/tx25.h
index e7b006c..834b616 100644
--- a/include/configs/tx25.h
+++ b/include/configs/tx25.h
@@ -26,6 +26,7 @@
#define CONFIG_SPL_MAX_SIZE 2048
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_TEXT_BASE 0x810c0000
#define CONFIG_SYS_TEXT_BASE 0x81200000
diff --git a/include/configs/u8500_href.h b/include/configs/u8500_href.h
index 6a22571..a8cc030 100644
--- a/include/configs/u8500_href.h
+++ b/include/configs/u8500_href.h
@@ -111,7 +111,6 @@
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "U8500 $ " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
/* Print Buffer Size */
diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h
index 4774de5..10a1664 100644
--- a/include/configs/usb_a9263.h
+++ b/include/configs/usb_a9263.h
@@ -140,7 +140,6 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"mtdparts=" MTDPARTS_DEFAULT "\0" \
-#define CONFIG_SYS_PROMPT "U-Boot> "
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
diff --git a/include/configs/v5fx30teval.h b/include/configs/v5fx30teval.h
index f30a090..298fa3e 100644
--- a/include/configs/v5fx30teval.h
+++ b/include/configs/v5fx30teval.h
@@ -24,7 +24,6 @@
#define CONFIG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CONFIG_ENV_OFFSET)
/*Misc*/
-#define CONFIG_SYS_PROMPT "v5fx30t:/# " /* Monitor Command Prompt */
#define CONFIG_PREBOOT "echo U-Boot is up and runnining;"
/*Flash*/
diff --git a/include/configs/vct.h b/include/configs/vct.h
index b54519d..80f6a60 100644
--- a/include/configs/vct.h
+++ b/include/configs/vct.h
@@ -145,7 +145,6 @@
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "VCT# " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
diff --git a/include/configs/venice2.h b/include/configs/venice2.h
index 8b1189e..0fc8cf7 100644
--- a/include/configs/venice2.h
+++ b/include/configs/venice2.h
@@ -13,7 +13,6 @@
#include "tegra124-common.h"
/* High-level configuration options */
-#define V_PROMPT "Tegra124 (Venice2) # "
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Venice2"
/* Board-specific serial config */
diff --git a/include/configs/ventana.h b/include/configs/ventana.h
index 3f1ebcd..e9c3500 100644
--- a/include/configs/ventana.h
+++ b/include/configs/ventana.h
@@ -12,7 +12,6 @@
#include "tegra20-common.h"
/* High-level configuration options */
-#define V_PROMPT "Tegra20 (Ventana) # "
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Ventana"
/* Board-specific serial config */
diff --git a/include/configs/versatile.h b/include/configs/versatile.h
index de23375..636ca43 100644
--- a/include/configs/versatile.h
+++ b/include/configs/versatile.h
@@ -108,6 +108,7 @@
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Monitor Command Prompt */
+#undef CONFIG_SYS_PROMPT
#ifdef CONFIG_ARCH_VERSATILE_AB
# define CONFIG_SYS_PROMPT "VersatileAB # "
#else
diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h
index c36237f..6107c64 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -239,7 +239,6 @@
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PROMPT "VExpress64# "
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_HUSH_PARSER
diff --git a/include/configs/vexpress_ca15_tc2.h b/include/configs/vexpress_ca15_tc2.h
index b43afa2..59b6310 100644
--- a/include/configs/vexpress_ca15_tc2.h
+++ b/include/configs/vexpress_ca15_tc2.h
@@ -12,8 +12,8 @@
#define __VEXPRESS_CA15X2_TC2_h
#define CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP
-#include "vexpress_common.h"
#define CONFIG_BOOTP_VCI_STRING "U-boot.armv7.vexpress_ca15x2_tc2"
+#include "vexpress_common.h"
#define CONFIG_SYSFLAGS_ADDR 0x1c010030
#define CONFIG_SMP_PEN_ADDR CONFIG_SYSFLAGS_ADDR
diff --git a/include/configs/vexpress_ca5x2.h b/include/configs/vexpress_ca5x2.h
index 7719d59..a4ffdf5 100644
--- a/include/configs/vexpress_ca5x2.h
+++ b/include/configs/vexpress_ca5x2.h
@@ -12,7 +12,7 @@
#define __VEXPRESS_CA5X2_h
#define CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP
-#include "vexpress_common.h"
#define CONFIG_BOOTP_VCI_STRING "U-boot.armv7.vexpress_ca5x2"
+#include "vexpress_common.h"
#endif /* __VEXPRESS_CA5X2_h */
diff --git a/include/configs/vexpress_ca9x4.h b/include/configs/vexpress_ca9x4.h
index 38ac4ed..71233d8 100644
--- a/include/configs/vexpress_ca9x4.h
+++ b/include/configs/vexpress_ca9x4.h
@@ -12,7 +12,7 @@
#define __VEXPRESS_CA9X4_H
#define CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
-#include "vexpress_common.h"
#define CONFIG_BOOTP_VCI_STRING "U-boot.armv7.vexpress_ca9x4"
+#include "vexpress_common.h"
#endif /* VEXPRESS_CA9X4_H */
diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h
index 0c1da01..98f6ae9 100644
--- a/include/configs/vexpress_common.h
+++ b/include/configs/vexpress_common.h
@@ -123,7 +123,6 @@
#define CONFIG_SYS_L2CACHE_OFF 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_SYS_GENERIC_BOARD
-#define CONFIG_OF_LIBFDT 1
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
@@ -152,18 +151,6 @@
#define CONFIG_SYS_SERIAL0 V2M_UART0
#define CONFIG_SYS_SERIAL1 V2M_UART1
-/* Command line configuration */
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PXE
-#define CONFIG_MENU
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_BOOTZ
-#define CONFIG_SUPPORT_RAW_INITRD
-
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION 1
#define CONFIG_MMC 1
#define CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
@@ -177,8 +164,6 @@
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_PXE
-#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100
/* Miscellaneous configurable options */
#define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x8000)
@@ -200,9 +185,22 @@
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET
+#define CONFIG_CMD_ECHO
+
+#include <config_distro_defaults.h>
/* Basic environment settings */
-#define CONFIG_BOOTCOMMAND "run bootflash;"
+#define CONFIG_BOOTCOMMAND \
+ "run distro_bootcmd; " \
+ "run bootflash; "
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 0) \
+ func(PXE, pxe, na) \
+ func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+
#ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
#define CONFIG_PLATFORM_ENV_SETTINGS \
"loadaddr=0x80008000\0" \
@@ -211,6 +209,7 @@
"ramdisk_addr=0x44800000\0" \
"maxramdisk=0x1800000\0" \
"pxefile_addr_r=0x88000000\0" \
+ "scriptaddr=0x88000000\0" \
"kernel_addr_r=0x80008000\0"
#elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP)
#define CONFIG_PLATFORM_ENV_SETTINGS \
@@ -220,10 +219,12 @@
"ramdisk_addr=0x0c800000\0" \
"maxramdisk=0x1800000\0" \
"pxefile_addr_r=0xa8000000\0" \
+ "scriptaddr=0xa8000000\0" \
"kernel_addr_r=0xa0008000\0"
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_PLATFORM_ENV_SETTINGS \
+ BOOTENV \
"console=ttyAMA0,38400n8\0" \
"dram=1024M\0" \
"root=/dev/sda1 rw\0" \
@@ -280,14 +281,12 @@
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PROMPT "VExpress# "
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
#define CONFIG_SYS_LONGHELP
-#define CONFIG_CMDLINE_EDITING 1
#define CONFIG_SYS_MAXARGS 16 /* max command args */
#endif /* VEXPRESS_COMMON_H */
diff --git a/include/configs/vision2.h b/include/configs/vision2.h
index 93c7348..b43373f 100644
--- a/include/configs/vision2.h
+++ b/include/configs/vision2.h
@@ -137,7 +137,6 @@
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_PROMPT "Vision II U-boot > "
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
diff --git a/include/configs/vl_ma2sc.h b/include/configs/vl_ma2sc.h
index e4958ce..3facd7f 100644
--- a/include/configs/vl_ma2sc.h
+++ b/include/configs/vl_ma2sc.h
@@ -340,7 +340,6 @@
#define CONFIG_SYS_BAUDRATE_TABLE {312500, 230400, 115200, 19200, \
38400, 57600, 9600 }
-#define CONFIG_SYS_PROMPT "U-Boot> "
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
#define CONFIG_SYS_PBSIZE \
diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h
index 95a69b3..976ba5d 100644
--- a/include/configs/vpac270.h
+++ b/include/configs/vpac270.h
@@ -126,7 +126,6 @@
#define CONFIG_SYS_LONGHELP
#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT "$ "
#else
#endif
#define CONFIG_SYS_CBSIZE 256
diff --git a/include/configs/whistler.h b/include/configs/whistler.h
index 13cc3d3..ff85964 100644
--- a/include/configs/whistler.h
+++ b/include/configs/whistler.h
@@ -12,7 +12,6 @@
#include "tegra20-common.h"
/* High-level configuration options */
-#define V_PROMPT "Tegra20 (Whistler) # "
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Whistler"
/* Board-specific serial config */
diff --git a/include/configs/wireless_space.h b/include/configs/wireless_space.h
index 7219034..191ac1b 100644
--- a/include/configs/wireless_space.h
+++ b/include/configs/wireless_space.h
@@ -64,8 +64,6 @@
#undef CONFIG_SYS_IDE_MAXDEVICE
#define CONFIG_SYS_IDE_MAXBUS 1
#define CONFIG_SYS_IDE_MAXDEVICE 1
-#undef CONFIG_SYS_PROMPT
-#define CONFIG_SYS_PROMPT "ws> "
/*
* Ethernet Driver configuration
diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h
index 52d392c..5d9f529 100644
--- a/include/configs/woodburn_common.h
+++ b/include/configs/woodburn_common.h
@@ -130,7 +130,6 @@
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "woodburn U-Boot > "
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
diff --git a/include/configs/x600.h b/include/configs/x600.h
index 1d4c1a9..edb16b1 100644
--- a/include/configs/x600.h
+++ b/include/configs/x600.h
@@ -151,7 +151,6 @@
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
#define CONFIG_IDENT_STRING "-SPEAr"
#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_PROMPT "X600> "
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h
index a072464..8d19bff 100644
--- a/include/configs/xaeniax.h
+++ b/include/configs/xaeniax.h
@@ -94,7 +94,7 @@
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER 1
-
+#undef CONFIG_SYS_PROMPT
#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT "u-boot$ " /* Monitor Command Prompt */
#else
diff --git a/include/configs/xilinx-ppc405-generic.h b/include/configs/xilinx-ppc405-generic.h
index 75b119f..40fa087 100644
--- a/include/configs/xilinx-ppc405-generic.h
+++ b/include/configs/xilinx-ppc405-generic.h
@@ -26,7 +26,6 @@
#define CONFIG_ENV_OVERWRITE 1
/*Misc*/
-#define CONFIG_SYS_PROMPT "xlx-ppc405:/# " /* Monitor Command Prompt */
#define CONFIG_PREBOOT "echo U-Boot is up and runnining;"
/*Flash*/
diff --git a/include/configs/xilinx-ppc440-generic.h b/include/configs/xilinx-ppc440-generic.h
index 8e68415..95b8834 100644
--- a/include/configs/xilinx-ppc440-generic.h
+++ b/include/configs/xilinx-ppc440-generic.h
@@ -24,7 +24,6 @@
#define CONFIG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CONFIG_ENV_OFFSET)
/*Misc*/
-#define CONFIG_SYS_PROMPT "board:/# " /* Monitor Command Prompt */
#define CONFIG_PREBOOT "echo U-Boot is up and runnining;"
/*Flash*/
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 68853b6..01b7993 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -131,7 +131,6 @@
/* Monitor Command Prompt */
/* Console I/O Buffer Size */
#define CONFIG_SYS_CBSIZE 2048
-#define CONFIG_SYS_PROMPT "ZynqMP> "
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_HUSH_PARSER
diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h
index cff3ba8..0199190 100644
--- a/include/configs/zipitz2.h
+++ b/include/configs/zipitz2.h
@@ -119,9 +119,6 @@
#define CONFIG_SYS_HUSH_PARSER 1
#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
-#endif
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h
index af7cc49..81b9ce4 100644
--- a/include/configs/zmx25.h
+++ b/include/configs/zmx25.h
@@ -138,7 +138,6 @@
#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM + (512*1024))
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM + PHYS_SDRAM_SIZE)
-#define CONFIG_SYS_PROMPT "zmx25> "
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 98bebd0..cc72c86 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -235,7 +235,6 @@
#define CONFIG_SYS_LOAD_ADDR 0 /* default? */
/* Miscellaneous configurable options */
-#define CONFIG_SYS_PROMPT "zynq-uboot> "
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_CMDLINE_EDITING
diff --git a/include/dt-bindings/pinctrl/dra.h b/include/dt-bindings/pinctrl/dra.h
new file mode 100644
index 0000000..7448edf
--- /dev/null
+++ b/include/dt-bindings/pinctrl/dra.h
@@ -0,0 +1,51 @@
+/*
+ * This header provides constants for DRA pinctrl bindings.
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Author: Rajendra Nayak <rnayak@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_DRA_H
+#define _DT_BINDINGS_PINCTRL_DRA_H
+
+/* DRA7 mux mode options for each pin. See TRM for options */
+#define MUX_MODE0 0x0
+#define MUX_MODE1 0x1
+#define MUX_MODE2 0x2
+#define MUX_MODE3 0x3
+#define MUX_MODE4 0x4
+#define MUX_MODE5 0x5
+#define MUX_MODE6 0x6
+#define MUX_MODE7 0x7
+#define MUX_MODE8 0x8
+#define MUX_MODE9 0x9
+#define MUX_MODE10 0xa
+#define MUX_MODE11 0xb
+#define MUX_MODE12 0xc
+#define MUX_MODE13 0xd
+#define MUX_MODE14 0xe
+#define MUX_MODE15 0xf
+
+#define PULL_ENA (0 << 16)
+#define PULL_DIS (1 << 16)
+#define PULL_UP (1 << 17)
+#define INPUT_EN (1 << 18)
+#define SLEWCONTROL (1 << 19)
+#define WAKEUP_EN (1 << 24)
+#define WAKEUP_EVENT (1 << 25)
+
+/* Active pin states */
+#define PIN_OUTPUT (0 | PULL_DIS)
+#define PIN_OUTPUT_PULLUP (PULL_UP)
+#define PIN_OUTPUT_PULLDOWN (0)
+#define PIN_INPUT (INPUT_EN | PULL_DIS)
+#define PIN_INPUT_SLEW (INPUT_EN | SLEWCONTROL)
+#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP)
+#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN)
+
+#endif
+
diff --git a/include/fsl_sec.h b/include/fsl_sec.h
index 672bcef..abc62da 100644
--- a/include/fsl_sec.h
+++ b/include/fsl_sec.h
@@ -3,6 +3,7 @@
*
* Copyright 2014 Freescale Semiconductor, Inc.
*
+ * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __FSL_SEC_H
diff --git a/include/power/hi6553_pmic.h b/include/power/hi6553_pmic.h
new file mode 100644
index 0000000..fcd131a
--- /dev/null
+++ b/include/power/hi6553_pmic.h
@@ -0,0 +1,79 @@
+/*
+ * (C) Copyright 2015 Linaro
+ * Peter Griffin <peter.griffin@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __HI6553_PMIC_H__
+#define __HI6553_PMIC_H__
+
+/* Registers */
+enum {
+ HI6553_VERSION_REG = 0x000,
+ HI6553_ENABLE2_LDO1_8 = 0x029,
+ HI6553_DISABLE2_LDO1_8,
+ HI6553_ONOFF_STATUS2_LDO1_8,
+ HI6553_ENABLE3_LDO9_16,
+ HI6553_DISABLE3_LDO9_16,
+ HI6553_ONOFF_STATUS3_LDO9_16,
+
+ HI6553_DISABLE6_XO_CLK = 0x036,
+ HI6553_PERI_EN_MARK = 0x040,
+ HI6553_BUCK2_REG1 = 0x04a,
+ HI6553_BUCK2_REG5 = 0x04e,
+ HI6553_BUCK2_REG6,
+
+ HI6553_BUCK3_REG3 = 0x054,
+ HI6553_BUCK3_REG5 = 0x056,
+ HI6553_BUCK3_REG6,
+ HI6553_BUCK4_REG2 = 0x05b,
+ HI6553_BUCK4_REG5 = 0x05e,
+ HI6553_BUCK4_REG6,
+
+ HI6553_CLK_TOP0 = 0x063,
+ HI6553_CLK_TOP3 = 0x066,
+ HI6553_CLK_TOP4,
+ HI6553_VSET_BUCK2_ADJ = 0x06d,
+ HI6553_VSET_BUCK3_ADJ,
+ HI6553_LDO7_REG_ADJ = 0x078,
+ HI6553_LDO10_REG_ADJ = 0x07b,
+ HI6553_LDO19_REG_ADJ = 0x084,
+ HI6553_LDO20_REG_ADJ,
+ HI6553_DR_LED_CTRL = 0x098,
+ HI6553_DR_OUT_CTRL,
+ HI6553_DR3_ISET,
+ HI6553_DR3_START_DEL,
+ HI6553_DR4_ISET,
+ HI6553_DR4_START_DEL,
+ HI6553_DR345_TIM_CONF0 = 0x0a0,
+ HI6553_NP_REG_ADJ1 = 0x0be,
+ HI6553_NP_REG_CHG = 0x0c0,
+ HI6553_BUCK01_CTRL2 = 0x0d9,
+ HI6553_BUCK0_CTRL1 = 0x0dd,
+ HI6553_BUCK0_CTRL5 = 0x0e1,
+ HI6553_BUCK0_CTRL7 = 0x0e3,
+ HI6553_BUCK1_CTRL1 = 0x0e8,
+ HI6553_BUCK1_CTRL5 = 0x0ec,
+ HI6553_BUCK1_CTRL7 = 0x0ef,
+ HI6553_CLK19M2_600_586_EN = 0x0fe,
+};
+
+#define HI6553_DISABLE6_XO_CLK_BB (1 << 0)
+#define HI6553_DISABLE6_XO_CLK_CONN (1 << 1)
+#define HI6553_DISABLE6_XO_CLK_NFC (1 << 2)
+#define HI6553_DISABLE6_XO_CLK_RF1 (1 << 3)
+#define HI6553_DISABLE6_XO_CLK_RF2 (1 << 4)
+
+#define HI6553_LED_START_DELAY_TIME 0x00
+#define HI6553_LED_ELEC_VALUE 0x07
+#define HI6553_LED_LIGHT_TIME 0xf0
+#define HI6553_LED_GREEN_ENABLE (1 << 1)
+#define HI6553_LED_OUT_CTRL 0x00
+
+#define HI6553_PMU_V300 0x30
+#define HI6553_PMU_V310 0x31
+
+int power_hi6553_init(u8 *base);
+
+#endif /* __HI6553_PMIC_H__ */
diff --git a/include/power/pfuze100_pmic.h b/include/power/pfuze100_pmic.h
index 57b9ca9..138132a 100644
--- a/include/power/pfuze100_pmic.h
+++ b/include/power/pfuze100_pmic.h
@@ -57,6 +57,13 @@
PMIC_NUM_OF_REGS = 0x7f,
};
+/* Registor offset based on VOLT register */
+#define PFUZE100_VOL_OFFSET 0
+#define PFUZE100_STBY_OFFSET 1
+#define PFUZE100_OFF_OFFSET 2
+#define PFUZE100_MODE_OFFSET 3
+#define PFUZE100_CONF_OFFSET 4
+
/*
* Buck Regulators
*/
@@ -133,6 +140,9 @@
#define SW1x_STBY_MASK 0x3f
#define SW1x_OFF_MASK 0x3f
+#define SW_MODE_MASK 0xf
+#define SW_MODE_SHIFT 0
+
#define SW1xCONF_DVSSPEED_MASK 0xc0
#define SW1xCONF_DVSSPEED_2US 0x00
#define SW1xCONF_DVSSPEED_4US 0x40
@@ -181,7 +191,12 @@
#define LDO_VOL_MASK 0xf
#define LDO_EN (1 << 4)
+#define LDO_MODE_SHIFT 4
+#define LDO_MODE_MASK (1 << 4)
+#define LDO_MODE_OFF 0
+#define LDO_MODE_ON 1
+#define VREFDDRCON_EN (1 << 4)
/*
* Boost Regulator
*/
@@ -193,11 +208,12 @@
#define SWBST_5_15V 3
#define SWBST_VOL_MASK 0x3
-#define SWBST_MODE_MASK 0x6
-#define SWBST_MODE_OFF (2 << 0)
-#define SWBST_MODE_PFM (2 << 1)
-#define SWBST_MODE_AUTO (2 << 2)
-#define SWBST_MODE_APS (2 << 3)
+#define SWBST_MODE_MASK 0xC
+#define SWBST_MODE_SHIFT 0x2
+#define SWBST_MODE_OFF 0
+#define SWBST_MODE_PFM 1
+#define SWBST_MODE_AUTO 2
+#define SWBST_MODE_APS 3
/*
* Regulator Mode Control
diff --git a/include/power/regulator.h b/include/power/regulator.h
index 0152290..1a51c3f 100644
--- a/include/power/regulator.h
+++ b/include/power/regulator.h
@@ -46,6 +46,7 @@
* Note: For the proper operation, at least name constraint is needed, since
* it can be used when calling regulator_get_by_platname(). And the mandatory
* rule for this name is, that it must be globally unique for the single dts.
+ * If regulator-name property is not provided, node name will be chosen.
*
* Regulator bind:
* For each regulator device, the device_bind() should be called with passed
diff --git a/include/twl4030.h b/include/twl4030.h
index 50f8da8..1031373 100644
--- a/include/twl4030.h
+++ b/include/twl4030.h
@@ -129,14 +129,6 @@
#define TWL4030_PM_MASTER_BB_CFG 0x6D
#define TWL4030_PM_MASTER_MISC_TST 0x6E
#define TWL4030_PM_MASTER_TRIM1 0x6F
-/* P[1-3]_SW_EVENTS */
-#define TWL4030_PM_MASTER_SW_EVENTS_STOPON_PWRON (1 << 6)
-#define TWL4030_PM_MASTER_SW_EVENTS_STOPON_SYSEN (1 << 5)
-#define TWL4030_PM_MASTER_SW_EVENTS_ENABLE_WARMRESET (1 << 4)
-#define TWL4030_PM_MASTER_SW_EVENTS_LVL_WAKEUP (1 << 3)
-#define TWL4030_PM_MASTER_SW_EVENTS_DEVACT (1 << 2)
-#define TWL4030_PM_MASTER_SW_EVENTS_DEVSLP (1 << 1)
-#define TWL4030_PM_MASTER_SW_EVENTS_DEVOFF (1 << 0)
/* Power bus message definitions */
@@ -207,6 +199,34 @@
/* Power Reference */
#define RES_Main_Ref 28
+/* P[1-3]_SW_EVENTS */
+#define TWL4030_PM_MASTER_SW_EVENTS_STOPON_PWRON (1 << 6)
+#define TWL4030_PM_MASTER_SW_EVENTS_STOPON_SYSEN (1 << 5)
+#define TWL4030_PM_MASTER_SW_EVENTS_ENABLE_WARMRESET (1 << 4)
+#define TWL4030_PM_MASTER_SW_EVENTS_LVL_WAKEUP (1 << 3)
+#define TWL4030_PM_MASTER_SW_EVENTS_DEVACT (1 << 2)
+#define TWL4030_PM_MASTER_SW_EVENTS_DEVSLP (1 << 1)
+#define TWL4030_PM_MASTER_SW_EVENTS_DEVOFF (1 << 0)
+
+/* HW conditions */
+#define TWL4030_PM_MASTER_STS_HW_CONDITIONS_PWON (1 << 0)
+#define TWL4030_PM_MASTER_STS_HW_CONDITIONS_CHG (1 << 1)
+#define TWL4030_PM_MASTER_STS_HW_CONDITIONS_USB (1 << 2)
+#define TWL4030_PM_MASTER_STS_HW_CONDITIONS_VBUS (1 << 7)
+
+/* Power transition */
+#define TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_PWON (1 << 0)
+#define TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_CHG (1 << 1)
+#define TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_USB (1 << 2)
+#define TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_RTC (1 << 3)
+#define TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_VBAT (1 << 4)
+#define TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_VBUS (1 << 5)
+#define TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_SWBUG (1 << 7)
+
+/* PWRANA2 */
+#define TWL4030_PM_MASTER_CFG_PWRANA2_LOJIT0_LOWV (1 << 1)
+#define TWL4030_PM_MASTER_CFG_PWRANA2_LOJIT1_LOWV (1 << 2)
+
#define TOTAL_RESOURCES 28
/*
* Power Bus Message Format ... these can be sent individually by Linux,
@@ -645,6 +665,8 @@
/* For hardware resetting */
void twl4030_power_reset_init(void);
+/* For power off */
+void twl4030_power_off(void);
/* For setting device group and voltage */
void twl4030_pmrecv_vsel_cfg(u8 vsel_reg, u8 vsel_val,
u8 dev_grp, u8 dev_grp_sel);
@@ -654,6 +676,17 @@
void twl4030_power_mmc_init(int dev_index);
/*
+ * Input
+ */
+
+int twl4030_input_power_button(void);
+int twl4030_input_charger(void);
+int twl4030_input_usb(void);
+
+int twl4030_keypad_scan(unsigned char *matrix);
+int twl4030_keypad_key(unsigned char *matrix, u8 c, u8 r);
+
+/*
* LED
*/
void twl4030_led_init(unsigned char ledon_mask);
diff --git a/include/u-boot/rsa-mod-exp.h b/include/u-boot/rsa-mod-exp.h
index fce445a..45a031b 100644
--- a/include/u-boot/rsa-mod-exp.h
+++ b/include/u-boot/rsa-mod-exp.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014, Ruchika Gupta.
+ * Copyright 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
diff --git a/lib/display_options.c b/lib/display_options.c
index 57fb974..df134cd 100644
--- a/lib/display_options.c
+++ b/lib/display_options.c
@@ -25,7 +25,10 @@
void print_freq(uint64_t freq, const char *s)
{
- unsigned long m = 0, n;
+ unsigned long m = 0;
+#if defined(CONFIG_SPL_SERIAL_SUPPORT)
+ unsigned long n;
+#endif
uint32_t f;
static const char names[] = {'G', 'M', 'K'};
unsigned long d = 1e9;
@@ -45,7 +48,9 @@
}
f = do_div(freq, d);
+#if defined(CONFIG_SPL_SERIAL_SUPPORT)
n = freq;
+#endif
/* If there's a remainder, show the first few digits */
if (f) {
@@ -58,7 +63,9 @@
m = (m / 10) + (m % 100 >= 50);
}
+#if defined(CONFIG_SPL_SERIAL_SUPPORT)
printf("%lu", n);
+#endif
if (m)
printf(".%ld", m);
printf(" %cHz%s", c, s);
@@ -121,9 +128,9 @@
} lb;
int i;
#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
- uint64_t x;
+ uint64_t __maybe_unused x;
#else
- uint32_t x;
+ uint32_t __maybe_unused x;
#endif
if (linelen*width > MAX_LINE_LENGTH_BYTES)
diff --git a/net/tftp.c b/net/tftp.c
index 3e99e73..89be32a 100644
--- a/net/tftp.c
+++ b/net/tftp.c
@@ -249,6 +249,8 @@
if (tftp_tsize) {
ulong pos = tftp_cur_block * tftp_block_size +
tftp_block_wrap_offset;
+ if (pos > tftp_tsize)
+ pos = tftp_tsize;
while (tftp_tsize_num_hash < pos * 50 / tftp_tsize) {
putc('#');
diff --git a/tools/logos/toradex.bmp b/tools/logos/toradex.bmp
new file mode 100644
index 0000000..3e2dcf2
--- /dev/null
+++ b/tools/logos/toradex.bmp
Binary files differ
