tree 158c31f2ae6ec60ec5175a59b0ceb9bbf737f6d4
parent 35a3ea1faad49296b35c8ba352420f7a73e6c4d2
author Andrew Gabbasov <andrew_gabbasov@mentor.com> 1395646841 -0500
committer Pantelis Antoniou <panto@antoniou-consulting.com> 1396433816 +0300

mmc: fsl_esdhc: fix calculation of timeout for data transactions

Calculation of the timeout value should be based on actual clock value,
written to controller registers. Since mmc->tran_speed is either the
maximum allowed speed, or the preliminary value, that is be not yet
set to registers, the actual timeout, taken by the controller, based
on its clock settings, may be much longer than expected, based on
mmc->tran_speed value. In particular it happens at early initialization
stage, when typical value of mmc->tran_speed is 20MHz or 26MHz, while
actual clock setting, configured in the controller, is 400kHz.
It's more correct to use mmc->clock value for timeout calculation instead.

Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>