Merge patch series "board: BuS: Remove duplicate newlines"
Drop all duplicate newlines from the board directory files.
diff --git a/board/BuS/eb_cpu5282/eb_cpu5282.c b/board/BuS/eb_cpu5282/eb_cpu5282.c
index cf56108..c254da6 100644
--- a/board/BuS/eb_cpu5282/eb_cpu5282.c
+++ b/board/BuS/eb_cpu5282/eb_cpu5282.c
@@ -181,5 +181,4 @@
/*---------------------------------------------------------------------------*/
-
/* EOF EB+MCF-EV123.c */
diff --git a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
index 070933f..cc3a662 100644
--- a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
+++ b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
@@ -59,7 +59,6 @@
#endif /* EFI_HAVE_CAPSULE_SUPPORT */
-
int board_early_init_f(void)
{
init_uart_clk(2);
diff --git a/board/altera/arria5-socdk/qts/iocsr_config.h b/board/altera/arria5-socdk/qts/iocsr_config.h
index f201ad3..9bd3e1b 100644
--- a/board/altera/arria5-socdk/qts/iocsr_config.h
+++ b/board/altera/arria5-socdk/qts/iocsr_config.h
@@ -691,5 +691,4 @@
0x00004100,
};
-
#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/board/altera/arria5-socdk/qts/pll_config.h b/board/altera/arria5-socdk/qts/pll_config.h
index 7fe290b..902caf4 100644
--- a/board/altera/arria5-socdk/qts/pll_config.h
+++ b/board/altera/arria5-socdk/qts/pll_config.h
@@ -80,5 +80,4 @@
#define CFG_HPS_ALTERAGRP_MAINCLK 2
#define CFG_HPS_ALTERAGRP_DBGATCLK 3
-
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/altera/cyclone5-socdk/qts/iocsr_config.h b/board/altera/cyclone5-socdk/qts/iocsr_config.h
index a571fb3..6df8cdb1 100644
--- a/board/altera/cyclone5-socdk/qts/iocsr_config.h
+++ b/board/altera/cyclone5-socdk/qts/iocsr_config.h
@@ -655,5 +655,4 @@
0x00004100,
};
-
#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h b/board/altera/cyclone5-socdk/qts/pll_config.h
index a46d124..59a9dcf 100644
--- a/board/altera/cyclone5-socdk/qts/pll_config.h
+++ b/board/altera/cyclone5-socdk/qts/pll_config.h
@@ -80,5 +80,4 @@
#define CFG_HPS_ALTERAGRP_MAINCLK 4
#define CFG_HPS_ALTERAGRP_DBGATCLK 4
-
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/aries/mcvevk/qts/iocsr_config.h b/board/aries/mcvevk/qts/iocsr_config.h
index dbcc1d7..3084c6a 100644
--- a/board/aries/mcvevk/qts/iocsr_config.h
+++ b/board/aries/mcvevk/qts/iocsr_config.h
@@ -655,5 +655,4 @@
0x00004000,
};
-
#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/board/aries/mcvevk/qts/pll_config.h b/board/aries/mcvevk/qts/pll_config.h
index 62cf679..fc1ba89 100644
--- a/board/aries/mcvevk/qts/pll_config.h
+++ b/board/aries/mcvevk/qts/pll_config.h
@@ -80,5 +80,4 @@
#define CFG_HPS_ALTERAGRP_MAINCLK 3
#define CFG_HPS_ALTERAGRP_DBGATCLK 3
-
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/armltd/vexpress64/pcie.c b/board/armltd/vexpress64/pcie.c
index 1045c90..301d95e 100644
--- a/board/armltd/vexpress64/pcie.c
+++ b/board/armltd/vexpress64/pcie.c
@@ -109,7 +109,6 @@
XR3_PCI_MEMSPACE64_SIZE,
XR3PCI_ATR_TRSLID_AXIMEMORY);
-
/* setup CPU to PCIe address translation table */
base = XR3_CONFIG_BASE + XR3PCI_ATR_AXI4_SLV0;
diff --git a/board/cadence/xtfpga/xtfpga.c b/board/cadence/xtfpga/xtfpga.c
index 6b92fe3..5e6470d 100644
--- a/board/cadence/xtfpga/xtfpga.c
+++ b/board/cadence/xtfpga/xtfpga.c
@@ -23,7 +23,6 @@
* (Print information about the board to stdout.)
*/
-
#if defined(CONFIG_XTFPGA_LX60)
const char *board = "XT_AV60";
const char *description = "Avnet Xilinx LX60 FPGA Evaluation Board / ";
diff --git a/board/cobra5272/flash.c b/board/cobra5272/flash.c
index 157b71d..616842e 100644
--- a/board/cobra5272/flash.c
+++ b/board/cobra5272/flash.c
@@ -61,7 +61,6 @@
return;
}
-
unsigned long flash_init(void)
{
int i, j;
@@ -112,7 +111,6 @@
return size;
}
-
#define CMD_READ_ARRAY 0x00F0
#define CMD_UNLOCK1 0x00AA
#define CMD_UNLOCK2 0x0055
@@ -133,7 +131,6 @@
#define ERR 2
#define TMO 4
-
int flash_erase(flash_info_t *info, int s_first, int s_last)
{
ulong result;
@@ -267,7 +264,6 @@
if ((result & data) != data)
return ERR_NOT_ERASED;
-
/*
* Disable interrupts which might cause a timeout
* here. Remember that our exception vectors are
@@ -317,7 +313,6 @@
return rc;
}
-
int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
ulong wp, data;
diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c
index 4a6cc3e..c6d33c3 100644
--- a/board/compulab/cm_fx6/cm_fx6.c
+++ b/board/compulab/cm_fx6/cm_fx6.c
@@ -252,7 +252,6 @@
PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL),
IMX_GPIO_NR(1, 6));
-
static int cm_fx6_setup_one_i2c(int busnum, struct i2c_pads_info *pads)
{
int ret;
diff --git a/board/compulab/cm_fx6/common.h b/board/compulab/cm_fx6/common.h
index debef15..17b56dd 100644
--- a/board/compulab/cm_fx6/common.h
+++ b/board/compulab/cm_fx6/common.h
@@ -31,6 +31,5 @@
#define CM_FX6_SATA_NRSTDLY IMX_GPIO_NR(6, 6)
#define CM_FX6_SATA_PWLOSS_INT IMX_GPIO_NR(6, 31)
-
void cm_fx6_set_usdhc_iomux(void);
void cm_fx6_set_ecspi_iomux(void);
diff --git a/board/congatec/cgtqmx8/cgtqmx8.c b/board/congatec/cgtqmx8/cgtqmx8.c
index 99c33a1..054e4e1 100644
--- a/board/congatec/cgtqmx8/cgtqmx8.c
+++ b/board/congatec/cgtqmx8/cgtqmx8.c
@@ -371,7 +371,6 @@
puts("\nDDR ");
}
-
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, struct bd_info *bd)
{
diff --git a/board/davinci/da8xxevm/omapl138_lcdk.c b/board/davinci/da8xxevm/omapl138_lcdk.c
index 607e05a..03c3445 100644
--- a/board/davinci/da8xxevm/omapl138_lcdk.c
+++ b/board/davinci/da8xxevm/omapl138_lcdk.c
@@ -167,7 +167,6 @@
/* address of boot parameters */
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
-
/* setup the SUSPSRC for ARM to control emulation suspend */
writel(readl(&davinci_syscfg_regs->suspsrc) &
~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
@@ -195,7 +194,6 @@
&davinci_emif_regs->ab2cr); /* CS3 */
#endif
-
#ifdef CONFIG_MMC_DAVINCI
if (davinci_configure_pin_mux(mmc0_pins, ARRAY_SIZE(mmc0_pins)) != 0)
return 1;
diff --git a/board/devboards/dbm-soc1/qts/iocsr_config.h b/board/devboards/dbm-soc1/qts/iocsr_config.h
index 56b2130..6bec839 100644
--- a/board/devboards/dbm-soc1/qts/iocsr_config.h
+++ b/board/devboards/dbm-soc1/qts/iocsr_config.h
@@ -655,5 +655,4 @@
0x00004000,
};
-
#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/board/devboards/dbm-soc1/qts/pll_config.h b/board/devboards/dbm-soc1/qts/pll_config.h
index 104e324..52f1eb0 100644
--- a/board/devboards/dbm-soc1/qts/pll_config.h
+++ b/board/devboards/dbm-soc1/qts/pll_config.h
@@ -80,5 +80,4 @@
#define CFG_HPS_ALTERAGRP_MAINCLK 3
#define CFG_HPS_ALTERAGRP_DBGATCLK 3
-
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
index 3a5495e..a50763e 100644
--- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c
+++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
@@ -541,7 +541,6 @@
return ret;
}
-
/* DRAM */
static void dhcom_spl_dram_init(void)
{
diff --git a/board/ebv/socrates/qts/iocsr_config.h b/board/ebv/socrates/qts/iocsr_config.h
index c24b5cb..d9a0c72 100644
--- a/board/ebv/socrates/qts/iocsr_config.h
+++ b/board/ebv/socrates/qts/iocsr_config.h
@@ -655,5 +655,4 @@
0x00004000,
};
-
#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/board/ebv/socrates/qts/pll_config.h b/board/ebv/socrates/qts/pll_config.h
index eaa18c1..baee1a9 100644
--- a/board/ebv/socrates/qts/pll_config.h
+++ b/board/ebv/socrates/qts/pll_config.h
@@ -80,5 +80,4 @@
#define CFG_HPS_ALTERAGRP_MAINCLK 3
#define CFG_HPS_ALTERAGRP_DBGATCLK 3
-
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/engicam/imx6q/imx6q.c b/board/engicam/imx6q/imx6q.c
index d799fe6..a8d5412 100644
--- a/board/engicam/imx6q/imx6q.c
+++ b/board/engicam/imx6q/imx6q.c
@@ -5,7 +5,6 @@
* Author: Jagan Teki <jagan@amarulasolutions.com>
*/
-
#include <asm/io.h>
#include <asm/gpio.h>
#include <linux/sizes.h>
diff --git a/board/freescale/common/cadmus.c b/board/freescale/common/cadmus.c
index 6f66ed6..e5ecd0e 100644
--- a/board/freescale/common/cadmus.c
+++ b/board/freescale/common/cadmus.c
@@ -3,7 +3,6 @@
* Copyright 2004, 2011 Freescale Semiconductor.
*/
-
#include <config.h>
#include <clock_legacy.h>
#include <linux/types.h>
@@ -27,7 +26,6 @@
u_char cm_reserved[248]; /* Total 256 bytes */
} cadmus_reg_t;
-
unsigned int
get_board_version(void)
{
@@ -36,7 +34,6 @@
return cadmus->cm_ver;
}
-
unsigned long
get_board_sys_clk(void)
{
@@ -54,7 +51,6 @@
}
}
-
unsigned int
get_pci_slot(void)
{
@@ -66,7 +62,6 @@
return ((cadmus->cm_csr >> 6) & 0x3) + 1;
}
-
unsigned int
get_pci_dual(void)
{
diff --git a/board/freescale/common/cadmus.h b/board/freescale/common/cadmus.h
index fb74e8f..93cea12 100644
--- a/board/freescale/common/cadmus.h
+++ b/board/freescale/common/cadmus.h
@@ -6,7 +6,6 @@
#ifndef __CADMUS_H_
#define __CADMUS_H_
-
/*
* CADMUS Board System Register interface.
*/
@@ -21,17 +20,14 @@
*/
extern unsigned long get_board_sys_clk(void);
-
/*
* Returns 1 - 4, as found in the USER CSR[6:7] bits.
*/
extern unsigned int get_pci_slot(void);
-
/*
* Returns PCI DUAL as found in CM_PCI[3].
*/
extern unsigned int get_pci_dual(void);
-
#endif /* __CADMUS_H_ */
diff --git a/board/freescale/common/eeprom.h b/board/freescale/common/eeprom.h
index 328fd39..1d0685f 100644
--- a/board/freescale/common/eeprom.h
+++ b/board/freescale/common/eeprom.h
@@ -6,12 +6,10 @@
#ifndef __EEPROM_H_
#define __EEPROM_H_
-
/*
* EEPROM Board System Register interface.
*/
-
/*
* CPU Board Revision
*/
@@ -29,5 +27,4 @@
*/
extern unsigned int get_cpu_board_revision(void);
-
#endif /* __CADMUS_H_ */
diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c
index e03434d..657f453 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -327,7 +327,6 @@
}
#endif
-
/* This function return length of public key.*/
static inline u32 get_key_len(struct fsl_secboot_img_priv *img)
{
@@ -858,7 +857,6 @@
return 0;
}
-
/* haddr - Address of the header of image to be validated.
* arg_hash_str - Option hash string. If provided, this
* overrides the key hash in the SFP fuses.
diff --git a/board/freescale/imx8mn_evk/ddr4_timing.c b/board/freescale/imx8mn_evk/ddr4_timing.c
index 77611ea..ce39c9e 100644
--- a/board/freescale/imx8mn_evk/ddr4_timing.c
+++ b/board/freescale/imx8mn_evk/ddr4_timing.c
@@ -787,7 +787,6 @@
{ 0xd0000, 0x1 },
};
-
/* P0 2D message block paremeter for training firmware */
struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{ 0xd0000, 0x0 },
diff --git a/board/freescale/imx8mn_evk/ddr4_timing_ld.c b/board/freescale/imx8mn_evk/ddr4_timing_ld.c
index a3577ef..d719b59 100644
--- a/board/freescale/imx8mn_evk/ddr4_timing_ld.c
+++ b/board/freescale/imx8mn_evk/ddr4_timing_ld.c
@@ -765,7 +765,6 @@
{ 0xd0000, 0x1 },
};
-
/* P1 message block paremeter for training firmware */
struct dram_cfg_param ddr_fsp1_cfg[] = {
{ 0xd0000, 0x0 },
@@ -791,7 +790,6 @@
{ 0xd0000, 0x1 },
};
-
/* P0 2D message block paremeter for training firmware */
struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{ 0xd0000, 0x0 },
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
index 7f8001b..5f0564f 100644
--- a/board/freescale/ls1012ardb/ls1012ardb.c
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
@@ -147,7 +147,6 @@
}
#endif
-
int board_early_init_f(void)
{
fsl_lsch2_early_init_f();
diff --git a/board/freescale/ls1021aiot/ls1021aiot.c b/board/freescale/ls1021aiot/ls1021aiot.c
index 7abc412..2fdac87 100644
--- a/board/freescale/ls1021aiot/ls1021aiot.c
+++ b/board/freescale/ls1021aiot/ls1021aiot.c
@@ -33,7 +33,6 @@
#define DDR_SIZE 0x40000000
-
int checkboard(void)
{
puts("Board: LS1021AIOT\n");
diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c
index fdf011e..2ecf5a7 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -508,7 +508,6 @@
return 0;
}
-
#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
diff --git a/board/freescale/ls1088a/ddr.c b/board/freescale/ls1088a/ddr.c
index d2e239c..54b432a 100644
--- a/board/freescale/ls1088a/ddr.c
+++ b/board/freescale/ls1088a/ddr.c
@@ -94,7 +94,6 @@
popts->wrlvl_override = 1;
popts->wrlvl_sample = 0xf;
-
/* Enable ZQ calibration */
popts->zq_en = 1;
diff --git a/board/freescale/ls2080aqds/ddr.c b/board/freescale/ls2080aqds/ddr.c
index 2986ffb..d19c061 100644
--- a/board/freescale/ls2080aqds/ddr.c
+++ b/board/freescale/ls2080aqds/ddr.c
@@ -46,7 +46,6 @@
else
pbsp = udimms[ctrl_num];
-
/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
* freqency and n_banks specified in board_specific_parameters table.
*/
diff --git a/board/freescale/ls2080aqds/ddr.h b/board/freescale/ls2080aqds/ddr.h
index b5d790a..465155e 100644
--- a/board/freescale/ls2080aqds/ddr.h
+++ b/board/freescale/ls2080aqds/ddr.h
@@ -87,5 +87,4 @@
rdimm2,
};
-
#endif
diff --git a/board/freescale/ls2080ardb/ddr.c b/board/freescale/ls2080ardb/ddr.c
index ec34b42..a1a97f9 100644
--- a/board/freescale/ls2080ardb/ddr.c
+++ b/board/freescale/ls2080ardb/ddr.c
@@ -46,7 +46,6 @@
else
pbsp = udimms[ctrl_num];
-
/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
* freqency and n_banks specified in board_specific_parameters table.
*/
diff --git a/board/freescale/ls2080ardb/ddr.h b/board/freescale/ls2080ardb/ddr.h
index c5f2a95..43301dc 100644
--- a/board/freescale/ls2080ardb/ddr.h
+++ b/board/freescale/ls2080ardb/ddr.h
@@ -72,5 +72,4 @@
udimm2, /* DP-DDR doesn't support RDIMM */
};
-
#endif
diff --git a/board/freescale/m5249evb/m5249evb.c b/board/freescale/m5249evb/m5249evb.c
index 717dc08..68524e5 100644
--- a/board/freescale/m5249evb/m5249evb.c
+++ b/board/freescale/m5249evb/m5249evb.c
@@ -32,7 +32,6 @@
return 0;
};
-
int dram_init(void)
{
unsigned long junk = 0xa5a59696;
@@ -91,7 +90,6 @@
return 0;
};
-
int testdram(void)
{
/* TODO: XXX XXX XXX */
diff --git a/board/freescale/m5253demo/m5253demo.c b/board/freescale/m5253demo/m5253demo.c
index d0b01f8..446a79e 100644
--- a/board/freescale/m5253demo/m5253demo.c
+++ b/board/freescale/m5253demo/m5253demo.c
@@ -133,7 +133,6 @@
}
#endif /* CONFIG_IDE */
-
#ifdef CONFIG_DRIVER_DM9000
int board_eth_init(struct bd_info *bis)
{
diff --git a/board/freescale/m5275evb/m5275evb.c b/board/freescale/m5275evb/m5275evb.c
index e1d94fc..8b986d4 100644
--- a/board/freescale/m5275evb/m5275evb.c
+++ b/board/freescale/m5275evb/m5275evb.c
@@ -74,7 +74,6 @@
*((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
*((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
-
out_be32(&sdp->sdmr, 0x018d0000);
*((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
diff --git a/board/freescale/mpc8548cds/ddr.c b/board/freescale/mpc8548cds/ddr.c
index 14202cd..4b8ddcc 100644
--- a/board/freescale/mpc8548cds/ddr.c
+++ b/board/freescale/mpc8548cds/ddr.c
@@ -3,7 +3,6 @@
* Copyright 2008 Freescale Semiconductor, Inc.
*/
-
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
diff --git a/board/freescale/mx6sabreauto/mx6sabreauto.c b/board/freescale/mx6sabreauto/mx6sabreauto.c
index e782543..bab62fd 100644
--- a/board/freescale/mx6sabreauto/mx6sabreauto.c
+++ b/board/freescale/mx6sabreauto/mx6sabreauto.c
@@ -138,7 +138,6 @@
struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
int cscmr1, ccgr6;
-
/* Turn off EIM clock */
ccgr6 = readl(&imx_ccm->CCGR6);
ccgr6 &= ~(0x3 << 10);
@@ -170,7 +169,6 @@
}
#endif
-
static iomux_v3_cfg_t const usdhc3_pads[] = {
IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
@@ -480,7 +478,6 @@
if (ret != 0)
return ret;
-
if (is_mx6dqp()) {
/* set SW2 staby volatage 0.975V*/
value = pmic_reg_read(dev, PFUZE100_SW2STBY);
diff --git a/board/freescale/mx6sllevk/mx6sllevk.c b/board/freescale/mx6sllevk/mx6sllevk.c
index 7114444..9e39e39 100644
--- a/board/freescale/mx6sllevk/mx6sllevk.c
+++ b/board/freescale/mx6sllevk/mx6sllevk.c
@@ -54,7 +54,6 @@
rev_id = pmic_reg_read(dev, PFUZE100_REVID);
printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
-
/* Init mode to APS_PFM */
pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
diff --git a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
index 6176f73..d80cfd4 100644
--- a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
+++ b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
@@ -135,7 +135,6 @@
rev_id = pmic_reg_read(dev, PFUZE100_REVID);
printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
-
/* Init mode to APS_PFM */
pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
index 6b0665a..e5a0197 100644
--- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
+++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
@@ -108,7 +108,6 @@
MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
-
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
@@ -352,7 +351,6 @@
#include <spl.h>
#include <asm/arch/mx6-ddr.h>
-
static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
.grp_addds = 0x00000030,
.grp_ddrmode_ctl = 0x00020000,
diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c
index ab00314..e386840 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -622,7 +622,6 @@
}
#endif
-
int misc_init_r(void)
{
ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
diff --git a/board/freescale/t102xrdb/cpld.h b/board/freescale/t102xrdb/cpld.h
index bd40cc3..b504c3f 100644
--- a/board/freescale/t102xrdb/cpld.h
+++ b/board/freescale/t102xrdb/cpld.h
@@ -23,7 +23,6 @@
u8 boot_config2; /* 0x1A - Boot config override register*/
};
-
/* Pointer to the CPLD register set */
u8 cpld_read(unsigned int reg);
diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c
index d5c084e..c35ec36 100644
--- a/board/freescale/t104xrdb/eth.c
+++ b/board/freescale/t104xrdb/eth.c
@@ -84,7 +84,6 @@
DEFAULT_FM_MDIO_NAME));
}
-
cpu_eth_init(bis);
#endif
diff --git a/board/freescale/t208xqds/t208xqds_qixis.h b/board/freescale/t208xqds/t208xqds_qixis.h
index 0f9a45a..6665142 100644
--- a/board/freescale/t208xqds/t208xqds_qixis.h
+++ b/board/freescale/t208xqds/t208xqds_qixis.h
@@ -11,7 +11,6 @@
#define QIXIS_SRDS1CLK_122 0x5a
#define QIXIS_SRDS1CLK_125 0x5e
-
/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
#define BRDCFG4_EMISEL_MASK 0xE0
#define BRDCFG4_EMISEL_SHIFT 5
diff --git a/board/freescale/t208xqds/tlb.c b/board/freescale/t208xqds/tlb.c
index f99d51c..a4cc532 100644
--- a/board/freescale/t208xqds/tlb.c
+++ b/board/freescale/t208xqds/tlb.c
@@ -81,7 +81,6 @@
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_256M, 1),
-
/* *I*G* - PCIe 4, 0xc0000000 */
SET_TLB_ENTRY(1, CFG_SYS_PCIE4_MEM_VIRT, CFG_SYS_PCIE4_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
diff --git a/board/freescale/t208xrdb/tlb.c b/board/freescale/t208xrdb/tlb.c
index df58315..a9a0390 100644
--- a/board/freescale/t208xrdb/tlb.c
+++ b/board/freescale/t208xrdb/tlb.c
@@ -81,7 +81,6 @@
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_256M, 1),
-
/* *I*G* - PCIe 4, 0xc0000000 */
SET_TLB_ENTRY(1, CFG_SYS_PCIE4_MEM_VIRT, CFG_SYS_PCIE4_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
diff --git a/board/freescale/t4rdb/ddr.c b/board/freescale/t4rdb/ddr.c
index 5b60b50..bbe31d4 100644
--- a/board/freescale/t4rdb/ddr.c
+++ b/board/freescale/t4rdb/ddr.c
@@ -39,7 +39,6 @@
else
pbsp = udimms[0];
-
/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
* freqency and n_banks specified in board_specific_parameters table.
*/
diff --git a/board/freescale/t4rdb/ddr.h b/board/freescale/t4rdb/ddr.h
index 74a2779..241b134 100644
--- a/board/freescale/t4rdb/ddr.h
+++ b/board/freescale/t4rdb/ddr.h
@@ -73,5 +73,4 @@
rdimm0,
};
-
#endif
diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c
index 80a798a..bfb49ad 100644
--- a/board/freescale/vf610twr/vf610twr.c
+++ b/board/freescale/vf610twr/vf610twr.c
@@ -214,7 +214,6 @@
}
#endif
-
static void setup_iomux_qspi(void)
{
static const iomux_v3_cfg_t qspi0_pads[] = {
diff --git a/board/gdsys/common/dp501.c b/board/gdsys/common/dp501.c
index 7698e76..715544c 100644
--- a/board/gdsys/common/dp501.c
+++ b/board/gdsys/common/dp501.c
@@ -136,7 +136,6 @@
dp501_setbits(addr, 0x0a, 0x30); /* power down encoder, standby mode */
}
-
int dp501_probe(unsigned screen, bool power)
{
#ifdef CONFIG_SYS_DP501_BASE
diff --git a/board/gdsys/common/ioep-fpga.c b/board/gdsys/common/ioep-fpga.c
index f01b48b..eea486a 100644
--- a/board/gdsys/common/ioep-fpga.c
+++ b/board/gdsys/common/ioep-fpga.c
@@ -6,7 +6,6 @@
#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
-
#include <gdsys_fpga.h>
#include <linux/bitops.h>
diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c
index bd9c5ca..915b733 100644
--- a/board/gdsys/common/osd.c
+++ b/board/gdsys/common/osd.c
@@ -165,7 +165,6 @@
return fout_calc;
}
-
static void ics8n3qv01_calc_parameters(unsigned int fout,
unsigned int *_mint, unsigned int *_mfrac,
unsigned int *_n)
@@ -424,7 +423,6 @@
y = hextoul(argv[2], NULL);
rp = argv[3];
-
while (*rp) {
char substr[5];
diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
index 2d89519..e1d0847 100644
--- a/board/ge/bx50v3/bx50v3.c
+++ b/board/ge/bx50v3/bx50v3.c
@@ -434,7 +434,6 @@
};
#endif
-
/*
* The SoM used by these boards has XTAL not connected despite datasheet
* suggesting connecting unused XTAL pins to ground. Without explicitly
diff --git a/board/hisilicon/hikey/hikey.c b/board/hisilicon/hikey/hikey.c
index 95a831e..2916526 100644
--- a/board/hisilicon/hikey/hikey.c
+++ b/board/hisilicon/hikey/hikey.c
@@ -244,7 +244,6 @@
return 0;
}
-
static void mmc1_init_pll(void)
{
uint32_t data;
@@ -339,7 +338,6 @@
} while (data & PERI_RST0_MMC0);
}
-
/* PMU SSI is the IP that maps the external PMU hi6553 registers as IO */
static void hi6220_pmussi_init(void)
{
@@ -398,7 +396,6 @@
if (ret)
printf("%s: Error adding eMMC port (%d)\n", __func__, ret);
-
/* take mmc1 (sd slot) out of reset, configure clocks and pinmuxing */
mmc1_init_pll();
mmc1_reset_clk();
diff --git a/board/is1/qts/iocsr_config.h b/board/is1/qts/iocsr_config.h
index e54af2c..619b8a6 100644
--- a/board/is1/qts/iocsr_config.h
+++ b/board/is1/qts/iocsr_config.h
@@ -655,5 +655,4 @@
0x00004000,
};
-
#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/board/is1/qts/pll_config.h b/board/is1/qts/pll_config.h
index 0a5f5dd..95a4fb6 100644
--- a/board/is1/qts/pll_config.h
+++ b/board/is1/qts/pll_config.h
@@ -80,5 +80,4 @@
#define CFG_HPS_ALTERAGRP_MAINCLK 4
#define CFG_HPS_ALTERAGRP_DBGATCLK 4
-
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/kontron/pitx_imx8m/pitx_imx8m.c b/board/kontron/pitx_imx8m/pitx_imx8m.c
index a908aee..2ee9716 100644
--- a/board/kontron/pitx_imx8m/pitx_imx8m.c
+++ b/board/kontron/pitx_imx8m/pitx_imx8m.c
@@ -84,7 +84,6 @@
return 0;
}
-
#ifdef CONFIG_FEC_MXC
#define FEC_RST_PAD IMX_GPIO_NR(1, 11)
static iomux_v3_cfg_t const fec1_rst_pads[] = {
diff --git a/board/kontron/pitx_imx8m/spl.c b/board/kontron/pitx_imx8m/spl.c
index 475e52f..bd5981b 100644
--- a/board/kontron/pitx_imx8m/spl.c
+++ b/board/kontron/pitx_imx8m/spl.c
@@ -28,7 +28,6 @@
DECLARE_GLOBAL_DATA_PTR;
-
static void spl_dram_init(void)
{
struct dram_timing_info *dram_timing;
@@ -89,7 +88,6 @@
return 0;
}
-
#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
PAD_CTL_FSEL2)
#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
diff --git a/board/l+g/vinco/vinco.c b/board/l+g/vinco/vinco.c
index 066d315..39e7ff6 100644
--- a/board/l+g/vinco/vinco.c
+++ b/board/l+g/vinco/vinco.c
@@ -62,7 +62,6 @@
}
#endif /* CONFIG_ATMEL_SPI */
-
#ifdef CONFIG_CMD_USB
static void vinco_usb_hw_init(void)
{
@@ -72,7 +71,6 @@
}
#endif
-
#ifdef CONFIG_GENERIC_ATMEL_MCI
void vinco_mci0_hw_init(void)
{
diff --git a/board/logicpd/omap3som/omap3logic.h b/board/logicpd/omap3som/omap3logic.h
index ba63aa0..55d8f42 100644
--- a/board/logicpd/omap3som/omap3logic.h
+++ b/board/logicpd/omap3som/omap3logic.h
@@ -19,7 +19,6 @@
#define NET_LAN92XX_GPMC_CONFIG5 0x00080a0a
#define NET_LAN92XX_GPMC_CONFIG6 0x03000280
-
const omap3_sysinfo sysinfo = {
DDR_DISCRETE,
"Logic DM37x/OMAP35x reference board",
diff --git a/board/mntre/imx8mq_reform2/imx8mq_reform2.c b/board/mntre/imx8mq_reform2/imx8mq_reform2.c
index ebc490e..6ee1c5c 100644
--- a/board/mntre/imx8mq_reform2/imx8mq_reform2.c
+++ b/board/mntre/imx8mq_reform2/imx8mq_reform2.c
@@ -28,14 +28,12 @@
DECLARE_GLOBAL_DATA_PTR;
-
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
static iomux_v3_cfg_t const wdog_pads[] = {
IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
-
int board_early_init_f(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
diff --git a/board/mntre/imx8mq_reform2/lpddr4_timing.c b/board/mntre/imx8mq_reform2/lpddr4_timing.c
index e5303db..96d2a3f 100644
--- a/board/mntre/imx8mq_reform2/lpddr4_timing.c
+++ b/board/mntre/imx8mq_reform2/lpddr4_timing.c
@@ -312,7 +312,6 @@
{ 0xd0000, 1 },
};
-
/* P1 message block parameter for training firmware */
static struct dram_cfg_param lpddr4_fsp1_cfg[] = {
{ 0xd0000, 0 },
@@ -352,7 +351,6 @@
{ 0xd0000, 1 },
};
-
/* P0 2D message block parameter for training firmware */
static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
{ 0xd0000, 0 },
diff --git a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
index 0cbfc08..1c63277d 100644
--- a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
+++ b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
@@ -254,7 +254,6 @@
EMIT_EXIT(),
};
-
int ps7_post_config(void)
{
return ps7_config(ps7_post_config_3_0);
diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c b/board/qualcomm/dragonboard410c/dragonboard410c.c
index bd2e213..fcbf2c3 100644
--- a/board/qualcomm/dragonboard410c/dragonboard410c.c
+++ b/board/qualcomm/dragonboard410c/dragonboard410c.c
@@ -115,7 +115,6 @@
do_fixup_by_compat(blob, "qcom,wcnss-wlan",
"local-mac-address", mac, ARP_HLEN, 1);
-
if (!eth_env_get_enetaddr("btaddr", mac)) {
msm_generate_mac_addr(mac);
diff --git a/board/siemens/common/board_am335x.c b/board/siemens/common/board_am335x.c
index 445af9d..2a72760 100644
--- a/board/siemens/common/board_am335x.c
+++ b/board/siemens/common/board_am335x.c
@@ -22,7 +22,6 @@
DECLARE_GLOBAL_DATA_PTR;
-
#ifdef CONFIG_SPL_BUILD
void set_uart_mux_conf(void)
{
diff --git a/board/siemens/pxm2/pmic.h b/board/siemens/pxm2/pmic.h
index f4ce7f1..6990fd7 100644
--- a/board/siemens/pxm2/pmic.h
+++ b/board/siemens/pxm2/pmic.h
@@ -50,7 +50,6 @@
#define PMIC_REG_ST_OFF_1 (0x2)
#define PMIC_REG_ST_ON_LOW_POW (0x3)
-
/* VDD2 & VDD1 voltage selection register. (VDD2_OP_REG & VDD1_OP_REG) */
#define PMIC_OP_REG_SEL (0x7F)
diff --git a/board/socrates/ddr.c b/board/socrates/ddr.c
index bf4894e..317c6b0 100644
--- a/board/socrates/ddr.c
+++ b/board/socrates/ddr.c
@@ -3,7 +3,6 @@
* Copyright 2008 Freescale Semiconductor, Inc.
*/
-
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
diff --git a/board/socrates/nand.c b/board/socrates/nand.c
index 517a4a0..b8e6e2c 100644
--- a/board/socrates/nand.c
+++ b/board/socrates/nand.c
@@ -56,7 +56,6 @@
}
}
-
/**
* sc_nand_read_byte - read one byte from the chip
* @mtd: MTD device structure
diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c
index d0415d2..00a3f2b 100644
--- a/board/socrates/sdram.c
+++ b/board/socrates/sdram.c
@@ -14,7 +14,6 @@
#include <spd_sdram.h>
#include <linux/delay.h>
-
#if !defined(CONFIG_SPD_EEPROM)
/*
* Autodetect onboard DDR SDRAM on 85xx platforms
diff --git a/board/socrates/tlb.c b/board/socrates/tlb.c
index 0cc6757..b4ddb1b 100644
--- a/board/socrates/tlb.c
+++ b/board/socrates/tlb.c
@@ -28,7 +28,6 @@
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
-
/*
* TLB 1: 64M Non-cacheable, guarded
* 0xfc000000 64M FLASH
diff --git a/board/softing/vining_fpga/qts/iocsr_config.h b/board/softing/vining_fpga/qts/iocsr_config.h
index 4059ed5..62a25b9 100644
--- a/board/softing/vining_fpga/qts/iocsr_config.h
+++ b/board/softing/vining_fpga/qts/iocsr_config.h
@@ -655,5 +655,4 @@
0x00004000,
};
-
#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/board/softing/vining_fpga/qts/pll_config.h b/board/softing/vining_fpga/qts/pll_config.h
index 40bc8f7..2b930fa9 100644
--- a/board/softing/vining_fpga/qts/pll_config.h
+++ b/board/softing/vining_fpga/qts/pll_config.h
@@ -80,5 +80,4 @@
#define CFG_HPS_ALTERAGRP_MAINCLK 3
#define CFG_HPS_ALTERAGRP_DBGATCLK 3
-
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/sr1500/qts/iocsr_config.h b/board/sr1500/qts/iocsr_config.h
index 2622b96..f94769b 100644
--- a/board/sr1500/qts/iocsr_config.h
+++ b/board/sr1500/qts/iocsr_config.h
@@ -655,5 +655,4 @@
0x00004000,
};
-
#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/board/sr1500/qts/pll_config.h b/board/sr1500/qts/pll_config.h
index 885fe91..990432ac 100644
--- a/board/sr1500/qts/pll_config.h
+++ b/board/sr1500/qts/pll_config.h
@@ -80,5 +80,4 @@
#define CFG_HPS_ALTERAGRP_MAINCLK 3
#define CFG_HPS_ALTERAGRP_DBGATCLK 3
-
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/synopsys/emsdp/emsdp.c b/board/synopsys/emsdp/emsdp.c
index adec7d3..ffa544f 100644
--- a/board/synopsys/emsdp/emsdp.c
+++ b/board/synopsys/emsdp/emsdp.c
@@ -76,7 +76,6 @@
// Switch PSRAM controller back to memory mode
writel(0, PSRAM_FLASH_CONFIG_REG_0);
-
// Switch PSRAM controller to command mode
writel(CRE_ENABLE | CRE_DRIVE_CMD, PSRAM_FLASH_CONFIG_REG_1);
// Program Refresh Configuration Register (RCR) for BANK1
diff --git a/board/tcl/sl50/board.c b/board/tcl/sl50/board.c
index 2e54ede..484b4e2 100644
--- a/board/tcl/sl50/board.c
+++ b/board/tcl/sl50/board.c
@@ -348,7 +348,6 @@
eth_env_set_enetaddr("eth1addr", mac_addr);
}
-
writel(MII_MODE_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
PHY_INTERFACE_MODE_MII;
diff --git a/board/tcl/sl50/mux.c b/board/tcl/sl50/mux.c
index 6d89c4a..2e2bd63 100644
--- a/board/tcl/sl50/mux.c
+++ b/board/tcl/sl50/mux.c
@@ -107,7 +107,6 @@
{-1},
};
-
void enable_uart0_pin_mux(void)
{
configure_module_pin_mux(uart0_pin_mux);
diff --git a/board/terasic/de1-soc/qts/iocsr_config.h b/board/terasic/de1-soc/qts/iocsr_config.h
index 359fd0e..46ef828 100644
--- a/board/terasic/de1-soc/qts/iocsr_config.h
+++ b/board/terasic/de1-soc/qts/iocsr_config.h
@@ -655,5 +655,4 @@
0x00004000,
};
-
#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/board/terasic/de1-soc/qts/pll_config.h b/board/terasic/de1-soc/qts/pll_config.h
index 2811e04..ae3cd31 100644
--- a/board/terasic/de1-soc/qts/pll_config.h
+++ b/board/terasic/de1-soc/qts/pll_config.h
@@ -86,5 +86,4 @@
#define CFG_HPS_ALTERAGRP_MAINCLK 3
#define CFG_HPS_ALTERAGRP_DBGATCLK 3
-
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/terasic/de10-nano/qts/iocsr_config.h b/board/terasic/de10-nano/qts/iocsr_config.h
index a889d3d..1555500 100644
--- a/board/terasic/de10-nano/qts/iocsr_config.h
+++ b/board/terasic/de10-nano/qts/iocsr_config.h
@@ -655,5 +655,4 @@
0x00004000,
};
-
#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/board/terasic/de10-nano/qts/pll_config.h b/board/terasic/de10-nano/qts/pll_config.h
index 192ffb4..794fa20 100644
--- a/board/terasic/de10-nano/qts/pll_config.h
+++ b/board/terasic/de10-nano/qts/pll_config.h
@@ -80,5 +80,4 @@
#define CFG_HPS_ALTERAGRP_MAINCLK 3
#define CFG_HPS_ALTERAGRP_DBGATCLK 3
-
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/terasic/de10-standard/qts/iocsr_config.h b/board/terasic/de10-standard/qts/iocsr_config.h
index 4aed74e..80086b0 100644
--- a/board/terasic/de10-standard/qts/iocsr_config.h
+++ b/board/terasic/de10-standard/qts/iocsr_config.h
@@ -655,5 +655,4 @@
0x00004000,
};
-
#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/board/terasic/de10-standard/qts/pll_config.h b/board/terasic/de10-standard/qts/pll_config.h
index c1ecd4b..b09b6ad 100644
--- a/board/terasic/de10-standard/qts/pll_config.h
+++ b/board/terasic/de10-standard/qts/pll_config.h
@@ -80,5 +80,4 @@
#define CFG_HPS_ALTERAGRP_MAINCLK 4
#define CFG_HPS_ALTERAGRP_DBGATCLK 4
-
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/terasic/sockit/qts/iocsr_config.h b/board/terasic/sockit/qts/iocsr_config.h
index 7b72ae9..8c247c8 100644
--- a/board/terasic/sockit/qts/iocsr_config.h
+++ b/board/terasic/sockit/qts/iocsr_config.h
@@ -655,5 +655,4 @@
0x00004000,
};
-
#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/board/terasic/sockit/qts/pll_config.h b/board/terasic/sockit/qts/pll_config.h
index 104e324..52f1eb0 100644
--- a/board/terasic/sockit/qts/pll_config.h
+++ b/board/terasic/sockit/qts/pll_config.h
@@ -80,5 +80,4 @@
#define CFG_HPS_ALTERAGRP_MAINCLK 3
#define CFG_HPS_ALTERAGRP_DBGATCLK 3
-
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/theadorable/theadorable.c b/board/theadorable/theadorable.c
index cca5c3d..d723453 100644
--- a/board/theadorable/theadorable.c
+++ b/board/theadorable/theadorable.c
@@ -288,7 +288,6 @@
}
} while (get_timer(start_time) < ABORT_TIMEOUT);
-
/*
* At this stage the bootcounter has not been incremented
* yet. We need to do this manually here to get an actually
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 34f4a91..681002b 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -339,7 +339,6 @@
if (power_tps65217_init(0))
return;
-
/*
* On Beaglebone White we need to ensure we have AC power
* before increasing the frequency.
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 40b7fcf..4313729 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -336,7 +336,6 @@
return NULL;
}
-
/*
* get_opp_offset:
* Returns the index for safest OPP of the device to boot.
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 4866888..cc5e64c 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -515,7 +515,6 @@
return opp;
}
-
#ifdef CONFIG_SPL_BUILD
/* No env to setup for SPL */
static inline void setup_board_eeprom_env(void) { }
diff --git a/board/ti/ks2_evm/ddr3_cfg.c b/board/ti/ks2_evm/ddr3_cfg.c
index fe350fe..690c4e2 100644
--- a/board/ti/ks2_evm/ddr3_cfg.c
+++ b/board/ti/ks2_evm/ddr3_cfg.c
@@ -6,7 +6,6 @@
* Texas Instruments Incorporated, <www.ti.com>
*/
-
#include <asm/arch/ddr3.h>
#include "ddr3_cfg.h"
diff --git a/board/ti/panda/panda_mux_data.h b/board/ti/panda/panda_mux_data.h
index ad9e365..3bf6c01 100644
--- a/board/ti/panda/panda_mux_data.h
+++ b/board/ti/panda/panda_mux_data.h
@@ -11,7 +11,6 @@
#include <asm/arch/mux_omap4.h>
-
const struct pad_conf_entry core_padconf_array_essential[] = {
{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c
index 2dcc042..4a1cfb8 100644
--- a/board/toradex/apalis_imx6/apalis_imx6.c
+++ b/board/toradex/apalis_imx6/apalis_imx6.c
@@ -783,7 +783,6 @@
writel(0x010E0101, &ccm->ccosr);
}
-
#define PAD_CTL_INPUT_DDR BIT(17)
struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
@@ -951,7 +950,6 @@
.SRT = 1,
};
-
/* Perform DDR DRAM calibration */
static void spl_dram_perform_cal(const struct mx6_ddr_sysinfo *ddr_sysinfo)
{
diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c
index 34e82c2..251970b 100644
--- a/board/toradex/colibri_imx6/colibri_imx6.c
+++ b/board/toradex/colibri_imx6/colibri_imx6.c
@@ -759,7 +759,6 @@
*/
MX6_MMDC_P0_MDSCR, 0x00008000,
-
/* 800mhz_2x64mx16.cfg */
MX6_MMDC_P0_MDPDC, 0x0002002D,
@@ -891,7 +890,6 @@
*/
MX6_MMDC_P0_MDSCR, 0x00008000,
-
/* 800mhz_2x64mx16.cfg */
MX6_MMDC_P0_MDPDC, 0x0002002D,
diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c
index e966ffb..7de29e3 100644
--- a/board/toradex/colibri_imx7/colibri_imx7.c
+++ b/board/toradex/colibri_imx7/colibri_imx7.c
@@ -223,7 +223,6 @@
int reg, ver;
int ret;
-
ret = pmic_get("pmic@33", &dev);
if (ret)
return ret;
diff --git a/board/vscom/baltos/board.c b/board/vscom/baltos/board.c
index 2c91e9f..cea25f8 100644
--- a/board/vscom/baltos/board.c
+++ b/board/vscom/baltos/board.c
@@ -285,7 +285,6 @@
mac_addr[4] = header.MAC1[4];
mac_addr[5] = header.MAC1[5];
-
node = fdt_path_offset(blob, "ethernet0");
if (node < 0) {
printf("no ethernet0 path offset\n");
diff --git a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
index 602a789..e7f1d6e 100644
--- a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
@@ -4060,7 +4060,6 @@
//
};
-
unsigned long ps7_pll_init_data_2_0[] = {
// START: top
// .. START: SLCR SETTINGS
@@ -8263,7 +8262,6 @@
//
};
-
unsigned long ps7_pll_init_data_1_0[] = {
// START: top
// .. START: SLCR SETTINGS
diff --git a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c
index 9343683..4800126 100644
--- a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c
@@ -4167,7 +4167,6 @@
//
};
-
unsigned long ps7_pll_init_data_2_0[] = {
// START: top
// .. START: SLCR SETTINGS
@@ -8483,7 +8482,6 @@
//
};
-
unsigned long ps7_pll_init_data_1_0[] = {
// START: top
// .. START: SLCR SETTINGS
diff --git a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c
index 6b153aa..76ef5d9 100644
--- a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c
@@ -4136,7 +4136,6 @@
//
};
-
unsigned long ps7_pll_init_data_2_0[] = {
// START: top
// .. START: SLCR SETTINGS
@@ -8421,7 +8420,6 @@
//
};
-
unsigned long ps7_pll_init_data_1_0[] = {
// START: top
// .. START: SLCR SETTINGS
diff --git a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c
index 6f2edf1..6764279 100644
--- a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c
@@ -4026,7 +4026,6 @@
//
};
-
unsigned long ps7_pll_init_data_2_0[] = {
// START: top
// .. START: SLCR SETTINGS
@@ -8195,7 +8194,6 @@
//
};
-
unsigned long ps7_pll_init_data_1_0[] = {
// START: top
// .. START: SLCR SETTINGS
diff --git a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
index 04d2e5f..6a3236c 100644
--- a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
@@ -4082,7 +4082,6 @@
/* */
};
-
unsigned long ps7_pll_init_data_2_0[] = {
/* START: top */
/* .. START: SLCR SETTINGS */
@@ -8313,7 +8312,6 @@
/* */
};
-
unsigned long ps7_pll_init_data_1_0[] = {
/* START: top */
/* .. START: SLCR SETTINGS */
@@ -12477,7 +12475,6 @@
/* */
};
-
#include "xil_io.h"
unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;