Merge patch series "Add Turris 1.x board"
Marek Mojík <marek.mojik@nic.cz> says:
Hello all,
this is a continuation of previous work by Pali to add support for the
Turris 1.x board. As the patches were based on u-boot v2022.04, a
nontrivial rebasing was needed.
Some notes:
- Some options that are in SD defconfig are disabled in NOR defconfig
because over the years u-boot grew and the old NOR defconfig will not
fit into NOR memory.
- SD boot with RAM larger than 2GB will only allocate 2GB of RAM (We
were not able to fix this yet)
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index 27f6958..e1b2f87 100644
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -8,6 +8,17 @@
# since our $(ci_runner_image) user is not root.
container_option: -u 0
work_dir: /u
+ # We define all of these as variables so we can easily reference them twice
+ am33xx_kirkwood_ls1_mvebu_omap: "am33xx kirkwood ls1 mvebu omap -x siemens,freescale"
+ amlogic_bcm_boundary_engicam_siemens_technexion_oradex: "amlogic bcm boundary engicam siemens technexion toradex -x mips"
+ arm_nxp_minus_imx_and_at91: "at91 freescale -x powerpc,m68k,imx,mx"
+ imx: "mx imx -x boundary,engicam,technexion,toradex"
+ rk: "rk"
+ sunxi: "sunxi"
+ powerpc: "powerpc"
+ arm_catch_all: "arm -x aarch64,am33xx,at91,bcm,ls1,kirkwood,mvebu,omap,rk,siemens,mx,sunxi,technexion,toradex"
+ aarch64_catch_all: "aarch64 -x amlogic,bcm,engicam,imx,ls1,ls2,lx216,mvebu,rk,siemens,sunxi,toradex"
+ everything_but_arm_and_powerpc: "arc m68k microblaze mips nios2 riscv sandbox sh x86 xtensa -x arm,powerpc"
stages:
- stage: testsuites
@@ -185,6 +196,34 @@
steps:
- script: make pip
+ - job: count_built_machines
+ displayName: 'Ensure we build all possible machines'
+ pool:
+ vmImage: $(ubuntu_vm)
+ container:
+ image: $(ci_runner_image)
+ options: $(container_option)
+ steps:
+ - script: |
+ BMANARGS="-o /tmp --dry-run -v"
+ # First get the total number of boards
+ total=$(tools/buildman/buildman ${BMANARGS} | grep "Total boards to build for each commit" | cut -d ' ' -f 8)
+ # Now build up the list of what each job built.
+ built="$(tools/buildman/buildman ${BMANARGS} $(am33xx_kirkwood_ls1_mvebu_omap) | grep '^ ')"
+ built="$built $(tools/buildman/buildman ${BMANARGS} $(amlogic_bcm_boundary_engicam_siemens_technexion_oradex) | grep '^ ')"
+ built="$built $(tools/buildman/buildman ${BMANARGS} $(arm_nxp_minus_imx_and_at91) | grep '^ ')"
+ built="$built $(tools/buildman/buildman ${BMANARGS} $(imx) | grep '^ ')"
+ built="$built $(tools/buildman/buildman ${BMANARGS} $(rk) | grep '^ ')"
+ built="$built $(tools/buildman/buildman ${BMANARGS} $(sunxi) | grep '^ ')"
+ built="$built $(tools/buildman/buildman ${BMANARGS} $(powerpc) | grep '^ ')"
+ built="$built $(tools/buildman/buildman ${BMANARGS} $(arm_catch_all) | grep '^ ')"
+ built="$built $(tools/buildman/buildman ${BMANARGS} $(aarch64_catch_all) | grep '^ ')"
+ built="$built $(tools/buildman/buildman ${BMANARGS} $(everything_but_arm_and_powerpc) | grep '^ ')"
+ # Finally see how many machines that is.
+ actual=$(tools/buildman/buildman ${BMANARGS} $built | grep "Total boards to build for each commit" | cut -d ' ' -f 8)
+ echo We would build a total of $actual out of $total platforms this CI run
+ [ $actual -eq $total ] && exit 0 || exit 1
+
- job: create_test_py_wrapper_script
displayName: 'Create and stage a wrapper for test.py runs'
pool:
@@ -248,7 +287,7 @@
export PATH=/opt/qemu/bin:/tmp/uboot-test-hooks/bin:\${PATH}
export PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci
# "\${var:+"-k \$var"}" expands to "" if \$var is empty, "-k \$var" if not
- ./test/py/test.py -ra -o cache_dir="\$UBOOT_TRAVIS_BUILD_DIR"/.pytest_cache --bd \${TEST_PY_BD} \${TEST_PY_ID} \${TEST_PY_TEST_SPEC:+"-k \${TEST_PY_TEST_SPEC}"} --build-dir "\$UBOOT_TRAVIS_BUILD_DIR" --report-dir "\$UBOOT_TRAVIS_BUILD_DIR"
+ ./test/py/test.py -ra -o cache_dir="\$UBOOT_TRAVIS_BUILD_DIR"/.pytest_cache --bd \${TEST_PY_BD} \${TEST_PY_ID} \${TEST_PY_TEST_SPEC:+"-k \${TEST_PY_TEST_SPEC}"} --build-dir "\$UBOOT_TRAVIS_BUILD_DIR" --report-dir "\$UBOOT_TRAVIS_BUILD_DIR" --junitxml=\$(System.DefaultWorkingDirectory)/results.xml
# the below corresponds to .gitlab-ci.yml "after_script"
rm -rf /tmp/uboot-test-hooks /tmp/venv
EOF
@@ -332,6 +371,7 @@
docker run "$@" --device /dev/fuse:/dev/fuse \
-v $PWD:$(work_dir) \
-v $(Pipeline.Workspace):$(Pipeline.Workspace) \
+ -v $(System.DefaultWorkingDirectory):$(System.DefaultWorkingDirectory) \
-e WORK_DIR="${WORK_DIR}" \
-e TEST_PY_BD="${TEST_PY_BD}" \
-e TEST_PY_ID="${TEST_PY_ID}" \
@@ -339,6 +379,10 @@
-e OVERRIDE="${OVERRIDE}" \
-e BUILD_ENV="${BUILD_ENV}" $(ci_runner_image) \
$(Pipeline.Workspace)/testsh/test.sh
+ - task: PublishTestResults@2
+ inputs:
+ testResultsFormat: 'JUnit'
+ testResultsFiles: 'results.xml'
- stage: test_py_qemu
jobs:
@@ -413,6 +457,9 @@
qemu_x86_64:
TEST_PY_BD: "qemu-x86_64"
TEST_PY_TEST_SPEC: "not sleep"
+ qemu_xtensa_dc233c:
+ TEST_PY_BD: "qemu-xtensa-dc233c"
+ TEST_PY_TEST_SPEC: "not sleep and not efi"
r2dplus_i82557c:
TEST_PY_BD: "r2dplus"
TEST_PY_ID: "--id i82557c_qemu"
@@ -456,6 +503,7 @@
docker run "$@" --device /dev/fuse:/dev/fuse \
-v $PWD:$(work_dir) \
-v $(Pipeline.Workspace):$(Pipeline.Workspace) \
+ -v $(System.DefaultWorkingDirectory):$(System.DefaultWorkingDirectory) \
-e WORK_DIR="${WORK_DIR}" \
-e TEST_PY_BD="${TEST_PY_BD}" \
-e TEST_PY_ID="${TEST_PY_ID}" \
@@ -464,6 +512,10 @@
-e BUILD_ENV="${BUILD_ENV}" $(ci_runner_image) \
$(Pipeline.Workspace)/testsh/test.sh
retryCountOnTaskFailure: 2 # QEMU may be too slow, etc.
+ - task: PublishTestResults@2
+ inputs:
+ testResultsFormat: 'JUnit'
+ testResultsFiles: 'results.xml'
- stage: world_build
jobs:
@@ -473,29 +525,29 @@
pool:
vmImage: $(ubuntu_vm)
strategy:
- # Use almost the same target division in .travis.yml, only merged
- # 3 small build jobs (arc/microblaze/xtensa) into one.
+ # We split the world up in to 10 jobs as we can have at most 10
+ # parallel jobs going on the free tier of Azure.
matrix:
- am33xx_at91_kirkwood_mvebu_omap:
- BUILDMAN: "am33xx at91_kirkwood mvebu omap -x siemens"
+ am33xx_kirkwood_ls1_mvebu_omap:
+ BUILDMAN: $(am33xx_kirkwood_ls1_mvebu_omap)
amlogic_bcm_boundary_engicam_siemens_technexion_oradex:
- BUILDMAN: "amlogic bcm boundary engicam siemens technexion toradex -x mips"
- arm_nxp_minus_imx:
- BUILDMAN: "freescale -x powerpc,m68k,imx,mx"
+ BUILDMAN: $(amlogic_bcm_boundary_engicam_siemens_technexion_oradex)
+ arm_nxp_minus_imx_and_at91:
+ BUILDMAN: $(arm_nxp_minus_imx_and_at91)
imx:
- BUILDMAN: "mx imx -x boundary,engicam,technexion,toradex"
+ BUILDMAN: $(imx)
rk:
- BUILDMAN: "rk"
+ BUILDMAN: $(rk)
sunxi:
- BUILDMAN: "sunxi"
+ BUILDMAN: $(sunxi)
powerpc:
- BUILDMAN: "powerpc"
+ BUILDMAN: $(powerpc)
arm_catch_all:
- BUILDMAN: "arm -x aarch64,am33xx,at91,bcm,ls1,kirkwood,mvebu,omap,rk,siemens,mx,sunxi,technexion,toradex"
+ BUILDMAN: $(arm_catch_all)
aarch64_catch_all:
- BUILDMAN: "aarch64 -x amlogic,bcm,engicam,imx,ls1,ls2,lx216,mvebu,rk,siemens,sunxi,toradex"
+ BUILDMAN: $(aarch64_catch_all)
everything_but_arm_and_powerpc:
- BUILDMAN: "-x arm,powerpc"
+ BUILDMAN: $(everything_but_arm_and_powerpc)
steps:
- script: |
cat << EOF > build.sh
diff --git a/.gitignore b/.gitignore
index 37f71c2..502a7e6 100644
--- a/.gitignore
+++ b/.gitignore
@@ -73,6 +73,8 @@
/capsule.*.efi-capsule
/capsule*.map
/keep-syms-lto.*
+/*imx8mimage*
+/*imx8mcst*
#
# Generated include files
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 165f765..0a15b73 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -41,7 +41,7 @@
fi
after_script:
- - cp -v /tmp/${TEST_PY_BD}/*.{html,css} .
+ - cp -v /tmp/${TEST_PY_BD}/*.{html,css,xml} .
- rm -rf /tmp/uboot-test-hooks /tmp/venv
script:
# If we've been asked to use clang only do one configuration.
@@ -83,11 +83,14 @@
./test/py/test.py -ra --bd ${TEST_PY_BD} ${TEST_PY_ID}
${TEST_PY_TEST_SPEC:+"-k ${TEST_PY_TEST_SPEC}"}
--build-dir "$UBOOT_TRAVIS_BUILD_DIR"
+ --junitxml=/tmp/${TEST_PY_BD}/results.xml
artifacts:
when: always
paths:
- "*.html"
- "*.css"
+ reports:
+ junit: results.xml
expire_in: 1 week
.world_build:
@@ -419,6 +422,12 @@
TEST_PY_TEST_SPEC: "not sleep"
<<: *buildman_and_testpy_dfn
+qemu-xtensa-dc233c test.py:
+ variables:
+ TEST_PY_BD: "qemu-xtensa-dc233c"
+ TEST_PY_TEST_SPEC: "not sleep and not efi"
+ <<: *buildman_and_testpy_dfn
+
r2dplus_i82557c test.py:
variables:
TEST_PY_BD: "r2dplus"
diff --git a/.mailmap b/.mailmap
index 8049856..952e1da 100644
--- a/.mailmap
+++ b/.mailmap
@@ -42,6 +42,7 @@
Fabio Estevam <fabio.estevam@nxp.com>
Harini Katakam <harini.katakam@amd.com> <harini.katakam@xilinx.com>
Harsha <harsha.harsha@amd.com> <harsha.harsha@xilinx.com>
+Heiko Stuebner <heiko.stuebner@cherry.de> <heiko.stuebner@theobroma-systems.com>
Heinrich Schuchardt <xypron.glpk@gmx.de> <heinrich.schuchardt@canonical.com>
Heinrich Schuchardt <xypron.glpk@gmx.de> xypron.glpk@gmx.de <xypron.glpk@gmx.de>
Ibai Erkiaga <ibai.erkiaga-elorza@amd.com> <ibai.erkiaga-elorza@xilinx.com>
@@ -53,12 +54,14 @@
Jagan Teki <jaganna@xilinx.com>
Jagan Teki <jagannadh.teki@gmail.com>
Jagan Teki <jagannadha.sutradharudu-teki@xilinx.com>
+Jakob Unterwurzacher <jakob.unterwurzacher@cherry.de> <jakob.unterwurzacher@theobroma-systems.com>
Jay Buddhabhatti <jay.buddhabhatti@amd.com> <jay.buddhabhatti@xilinx.com>
Jernej Skrabec <jernej.skrabec@gmail.com> <jernej.skrabec@siol.net>
John Linn <john.linn@amd.com> <john.linn@xilinx.com>
Jyotheeswar Reddy Mutthareddyvari <jyotheeswar.reddy.mutthareddyvari@amd.com> <jyothee@xilinx.com>
Jyotheeswar Reddy Mutthareddyvari <jyotheeswar.reddy.mutthareddyvari@amd.com> <jyotheeswar.reddy.mutthareddyvari@xilinx.com>
Kalyani Akula <kalyani.akula@amd.com> <kalyani.akula@xilinx.com>
+Klaus Goger <klaus.goger@cherry.de> <klaus.goger@theobroma-systems.com>
Masahisa Kojima <kojima.masahisa@socionext.com> <masahisa.kojima@linaro.org>
Love Kumar <love.kumar@amd.com> <love.kumar@xilinx.com>
Lukasz Majewski <lukma@denx.de>
@@ -88,9 +91,11 @@
Patrice Chotard <patrice.chotard@foss.st.com> <patrice.chotard@st.com>
Patrick Delaunay <patrick.delaunay@foss.st.com> <patrick.delaunay@st.com>
Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com>
+Philipp Tomsich <philipp.tomsich@vrull.eu> <philipp.tomsich@theobroma-systems.com>
Piyush Mehta <piyush.mehta@amd.com> <piyush.mehta@xilinx.com>
Prabhakar Kushwaha <prabhakar@freescale.com>
Punnaiah Choudary Kalluri <punnaiah.choudary.kalluri@amd.com> <punnaiah.choudary.kalluri@xilinx.com>
+Quentin Schulz <quentin.schulz@cherry.de> <quentin.schulz@theobroma-systems.com>
Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> <radhey.shyam.pandey@xilinx.com>
Rajeshwari Shinde <rajeshwari.s@samsung.com>
Raju Kumar Pothuraju <rajukumar.pothuraju@amd.com> <raju.kumar-pothuraju@xilinx.com>
diff --git a/MAINTAINERS b/MAINTAINERS
index 6d02176..2c6de3a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -306,6 +306,7 @@
F: board/freescale/*mx*/
F: board/freescale/common/
F: common/spl/spl_imx_container.c
+F: doc/imx/
F: drivers/serial/serial_mxc.c
F: include/imx_container.h
@@ -333,17 +334,16 @@
ARM IPQ40XX
M: Robert Marko <robert.marko@sartura.hr>
-M: Luka Kovacic <luka.kovacic@sartura.hr>
M: Luka Perkov <luka.perkov@sartura.hr>
S: Maintained
F: arch/arm/mach-ipq40xx/
-F: include/dt-bindings/clock/qcom,ipq4019-gcc.h
-F: include/dt-bindings/reset/qcom,ipq4019-reset.h
-F: drivers/reset/reset-ipq4019.c
+F: include/dt-bindings/clock/qcom,gcc-ipq4019.h
+F: drivers/clk/qcom/clock-ipq4019.c
F: drivers/phy/phy-qcom-ipq4019-usb.c
F: drivers/spi/spi-qup.c
F: drivers/net/mdio-ipq4019.c
F: drivers/rng/msm_rng.c
+F: drivers/pinctrl/qcom/pinctrl-ipq4019.c
ARM LAYERSCAPE SFP
M: Sean Anderson <sean.anderson@seco.com>
@@ -533,6 +533,7 @@
F: arch/arm/mach-rockchip/
F: board/amarula/vyasa-rk3288/
F: board/anbernic/rgxx3_rk3566/
+F: board/armsom/sige7-rk3588/
F: board/chipspark/popmetal_rk3288
F: board/engicam/px30_core/
F: board/firefly/
@@ -578,19 +579,14 @@
ARM SAMSUNG EXYNOS850 SOC
M: Sam Protsenko <semen.protsenko@linaro.org>
S: Maintained
-F: arch/arm/dts/exynos850-pinctrl.dtsi
-F: arch/arm/dts/exynos850.dtsi
-F: doc/device-tree-bindings/clock/samsung,exynos850-clock.yaml
F: drivers/clk/exynos/clk-exynos850.c
F: drivers/pinctrl/exynos/pinctrl-exynos850.c
-F: include/dt-bindings/clock/exynos850.h
ARM SAMSUNG SOC DRIVERS
M: Sam Protsenko <semen.protsenko@linaro.org>
S: Maintained
-F: doc/device-tree-bindings/soc/samsung/*
+F: doc/device-tree-bindings/soc/samsung/exynos-pmu.yaml
F: drivers/soc/samsung/*
-F: include/dt-bindings/soc/samsung,*.h
ARM SANCLOUD
M: Paul Barker <paul.barker@sancloud.com>
@@ -1167,6 +1163,14 @@
F: drivers/watchdog/sp805_wdt.c
F: drivers/watchdog/sbsa_gwdt.c
+FWU Multi Bank Update
+M: Sughosh Ganu <sughosh.ganu@linaro.org>
+S: Maintained
+T: git https://source.denx.de/u-boot/custodians/u-boot-efi.git
+F: lib/fwu_updates/*
+F: drivers/fwu-mdata/*
+F: tools/mkfwumdata.c
+
GATEWORKS_SC
M: Tim Harvey <tharvey@gateworks.com>
S: Maintained
diff --git a/Makefile b/Makefile
index 79b28c2..f5b2512 100644
--- a/Makefile
+++ b/Makefile
@@ -3,7 +3,7 @@
VERSION = 2024
PATCHLEVEL = 07
SUBLEVEL =
-EXTRAVERSION = -rc3
+EXTRAVERSION =
NAME =
# *DOCUMENTATION*
@@ -1898,8 +1898,11 @@
# is "yes"), so compile examples after U-Boot is compiled.
examples: $(filter-out examples, $(u-boot-dirs))
+# The setlocalversion script comes from linux and expects a
+# KERNELVERSION variable in the environment for figuring out which
+# annotated tags are relevant. Pass UBOOTVERSION.
define filechk_uboot.release
- echo "$(UBOOTVERSION)$$($(CONFIG_SHELL) $(srctree)/scripts/setlocalversion $(srctree))"
+ KERNELVERSION=$(UBOOTVERSION) $(CONFIG_SHELL) $(srctree)/scripts/setlocalversion $(srctree)
endef
# Store (new) UBOOTRELEASE string in include/config/uboot.release
@@ -2210,7 +2213,7 @@
# Remove include/asm symlink created by U-Boot before v2014.01
MRPROPER_FILES += .config .config.old include/autoconf.mk* include/config.h \
ctags etags tags TAGS cscope* GPATH GTAGS GRTAGS GSYMS \
- drivers/video/fonts/*.S include/asm
+ drivers/video/fonts/*.S include/asm *imx8mimage* *imx8mcst*
# clean - Delete most, but leave enough to build external modules
#
@@ -2426,7 +2429,7 @@
$(PERL) $(src)/scripts/checkstack.pl $(ARCH)
ubootrelease:
- @echo "$(UBOOTVERSION)$$($(CONFIG_SHELL) $(srctree)/scripts/setlocalversion $(srctree))"
+ @$(filechk_uboot.release)
ubootversion:
@echo $(UBOOTVERSION)
diff --git a/arch/arc/lib/cpu.c b/arch/arc/lib/cpu.c
index 5939504..269b4db 100644
--- a/arch/arc/lib/cpu.c
+++ b/arch/arc/lib/cpu.c
@@ -7,7 +7,7 @@
#include <clock_legacy.h>
#include <init.h>
#include <malloc.h>
-#include <vsprintf.h>
+#include <stdio.h>
#include <asm/arcregs.h>
#include <asm/cache.h>
#include <asm/global_data.h>
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 39ad03ac..ba0359f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -769,6 +769,7 @@
select CLK_QCOM_IPQ4019
select PINCTRL_QCOM_IPQ4019
imply CMD_DM
+ imply OF_UPSTREAM
config ARCH_KEYSTONE
bool "TI Keystone"
@@ -1235,6 +1236,18 @@
imply BOARD_LATE_INIT
imply ENV_VARS_UBOOT_RUNTIME_CONFIG
+config ARCH_VERSAL2
+ bool "Support AMD Versal Gen 2 Platform"
+ select ARM64
+ select CLK
+ select DM
+ select DM_MMC if MMC
+ select DM_SERIAL
+ select OF_CONTROL
+ imply BOARD_LATE_INIT
+ imply ENV_VARS_UBOOT_RUNTIME_CONFIG
+ imply ZYNQMP_FIRMWARE
+
config ARCH_VERSAL_NET
bool "Support Xilinx Versal NET Platform"
select ARM64
@@ -1272,7 +1285,7 @@
select OF_CONTROL
select MTD
select SPI
- select SPL_BOARD_INIT if SPL
+ select SPL_SOC_INIT if SPL
select SPL_CLK if SPL
select SPL_DM if SPL
select SPL_DM_SPI if SPL
@@ -1315,7 +1328,7 @@
imply FIRMWARE
select GICV2
select OF_CONTROL
- select SPL_BOARD_INIT if SPL
+ select SPL_SOC_INIT if SPL
select SPL_CLK if SPL
select SPL_DM if SPL
select SPL_DM_SPI if SPI && SPL_DM
@@ -2317,6 +2330,8 @@
source "arch/arm/mach-versal/Kconfig"
+source "arch/arm/mach-versal2/Kconfig"
+
source "arch/arm/mach-versal-net/Kconfig"
source "arch/arm/mach-zynqmp-r5/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 734c6d6..dbeedbe 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -90,6 +90,7 @@
machine-$(CONFIG_ARCH_OCTEONTX2) += octeontx2
machine-$(CONFIG_ARCH_UNIPHIER) += uniphier
machine-$(CONFIG_ARCH_VERSAL) += versal
+machine-$(CONFIG_ARCH_VERSAL2) += versal2
machine-$(CONFIG_ARCH_VERSAL_NET) += versal-net
machine-$(CONFIG_ARCH_ZYNQ) += zynq
machine-$(CONFIG_ARCH_ZYNQMP) += zynqmp
diff --git a/arch/arm/cpu/arm11/cpu.c b/arch/arm/cpu/arm11/cpu.c
index 01d2e1a..4bf0446 100644
--- a/arch/arm/cpu/arm11/cpu.c
+++ b/arch/arm/cpu/arm11/cpu.c
@@ -116,3 +116,15 @@
#endif
}
#endif
+
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
+/* Invalidate entire I-cache */
+void invalidate_icache_all(void)
+{
+ unsigned long i = 0;
+
+ asm ("mcr p15, 0, %0, c7, c5, 0" : : "r" (i));
+}
+#else
+void invalidate_icache_all(void) {}
+#endif
diff --git a/arch/arm/cpu/arm1136/u-boot-spl.lds b/arch/arm/cpu/arm1136/u-boot-spl.lds
index f83988f..b7af291 100644
--- a/arch/arm/cpu/arm1136/u-boot-spl.lds
+++ b/arch/arm/cpu/arm1136/u-boot-spl.lds
@@ -33,11 +33,7 @@
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
. = ALIGN(4);
__image_copy_end = .;
-
- .end :
- {
- *(.__end)
- }
+ _end = .;
.bss :
{
diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
index 7e20448..7c63092 100644
--- a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
+++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
@@ -49,11 +49,7 @@
__bss_end = .;
}
- .end :
- {
- *(.__end)
- }
-
+ _end = .;
_image_binary_end = .;
.dynsym _image_binary_end : { *(.dynsym) }
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index d4c64f2..c3f8dac 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -396,6 +396,251 @@
return count;
}
+#define ALL_ATTRS (3 << 8 | PMD_ATTRINDX_MASK)
+#define PTE_IS_TABLE(pte, level) (pte_type(&(pte)) == PTE_TYPE_TABLE && (level) < 3)
+
+enum walker_state {
+ WALKER_STATE_START = 0,
+ WALKER_STATE_TABLE,
+ WALKER_STATE_REGION, /* block or page, depending on level */
+};
+
+
+/**
+ * __pagetable_walk() - Walk through the pagetable and call cb() for each memory region
+ *
+ * This is a software implementation of the ARMv8-A MMU translation table walk. As per
+ * section D5.4 of the ARMv8-A Architecture Reference Manual. It recursively walks the
+ * 4 or 3 levels of the page table and calls the callback function for each discrete
+ * region of memory (that being the discovery of a new table, a collection of blocks
+ * with the same attributes, or of pages with the same attributes).
+ *
+ * U-Boot picks the smallest number of virtual address (VA) bits that it can based on the
+ * memory map configured by the board. If this is less than 39 then the MMU will only use
+ * 3 levels of translation instead of 3 - skipping level 0.
+ *
+ * Each level has 512 entries of 64-bits each. Each entry includes attribute bits and
+ * an address. When the attribute bits indicate a table, the address is the physical
+ * address of the table, so we can recursively call _pagetable_walk() on it (after calling
+ * @cb). If instead they indicate a block or page, we record the start address and attributes
+ * and continue walking until we find a region with different attributes, or the end of the
+ * table, in either case we call @cb with the start and end address of the region.
+ *
+ * This approach can be used to fully emulate the MMU's translation table walk, as per
+ * Figure D5-25 of the ARMv8-A Architecture Reference Manual.
+ *
+ * @addr: The address of the table to walk
+ * @tcr: The TCR register value
+ * @level: The current level of the table
+ * @cb: The callback function to call for each region
+ * @priv: Private data to pass to the callback function
+ */
+static void __pagetable_walk(u64 addr, u64 tcr, int level, pte_walker_cb_t cb, void *priv)
+{
+ u64 *table = (u64 *)addr;
+ u64 attrs, last_attrs = 0, last_addr = 0, entry_start = 0;
+ int i;
+ u64 va_bits = 64 - (tcr & (BIT(6) - 1));
+ static enum walker_state state[4] = { 0 };
+ static bool exit;
+
+ if (!level) {
+ exit = false;
+ if (va_bits < 39)
+ level = 1;
+ }
+
+ state[level] = WALKER_STATE_START;
+
+ /* Walk through the table entries */
+ for (i = 0; i < MAX_PTE_ENTRIES; i++) {
+ u64 pte = table[i];
+ u64 _addr = pte & GENMASK_ULL(va_bits, PAGE_SHIFT);
+
+ if (exit)
+ return;
+
+ if (pte_type(&pte) == PTE_TYPE_FAULT)
+ continue;
+
+ attrs = pte & ALL_ATTRS;
+ /* If we're currently inside a block or set of pages */
+ if (state[level] > WALKER_STATE_START && state[level] != WALKER_STATE_TABLE) {
+ /*
+ * Continue walking if this entry has the same attributes as the last and
+ * is one page/block away -- it's a contiguous region.
+ */
+ if (attrs == last_attrs && _addr == last_addr + (1 << level2shift(level))) {
+ last_attrs = attrs;
+ last_addr = _addr;
+ continue;
+ } else {
+ /* We either hit a table or a new region */
+ exit = cb(entry_start, last_addr + (1 << level2shift(level)),
+ va_bits, level, priv);
+ if (exit)
+ return;
+ state[level] = WALKER_STATE_START;
+ }
+ }
+ last_attrs = attrs;
+ last_addr = _addr;
+
+ if (PTE_IS_TABLE(pte, level)) {
+ /* After the end of the table might be corrupted data */
+ if (!_addr || (pte & 0xfff) > 0x3ff)
+ return;
+ state[level] = WALKER_STATE_TABLE;
+ /* Signify the start of a table */
+ exit = cb(pte, 0, va_bits, level, priv);
+ if (exit)
+ return;
+
+ /* Go down a level */
+ __pagetable_walk(_addr, tcr, level + 1, cb, priv);
+ state[level] = WALKER_STATE_START;
+ } else if (pte_type(&pte) == PTE_TYPE_BLOCK || pte_type(&pte) == PTE_TYPE_PAGE) {
+ /* We foud a block or page, start walking */
+ entry_start = pte;
+ state[level] = WALKER_STATE_REGION;
+ }
+ }
+
+ if (state[level] > WALKER_STATE_START)
+ exit = cb(entry_start, last_addr + (1 << level2shift(level)), va_bits, level, priv);
+}
+
+static void pretty_print_pte_type(u64 pte)
+{
+ switch (pte_type(&pte)) {
+ case PTE_TYPE_FAULT:
+ printf(" %-5s", "Fault");
+ break;
+ case PTE_TYPE_BLOCK:
+ printf(" %-5s", "Block");
+ break;
+ case PTE_TYPE_PAGE:
+ printf(" %-5s", "Pages");
+ break;
+ default:
+ printf(" %-5s", "Unk");
+ }
+}
+
+static void pretty_print_table_attrs(u64 pte)
+{
+ int ap = (pte & PTE_TABLE_AP) >> 61;
+
+ printf(" | %2s %10s",
+ (ap & 2) ? "RO" : "",
+ (ap & 1) ? "!EL0" : "");
+ printf(" | %3s %2s %2s",
+ (pte & PTE_TABLE_PXN) ? "PXN" : "",
+ (pte & PTE_TABLE_XN) ? "XN" : "",
+ (pte & PTE_TABLE_NS) ? "NS" : "");
+}
+
+static void pretty_print_block_attrs(u64 pte)
+{
+ u64 attrs = pte & PMD_ATTRINDX_MASK;
+
+ switch (attrs) {
+ case PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE):
+ printf(" | %-13s", "Device-nGnRnE");
+ break;
+ case PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE):
+ printf(" | %-13s", "Device-nGnRE");
+ break;
+ case PTE_BLOCK_MEMTYPE(MT_DEVICE_GRE):
+ printf(" | %-13s", "Device-GRE");
+ break;
+ case PTE_BLOCK_MEMTYPE(MT_NORMAL_NC):
+ printf(" | %-13s", "Normal-NC");
+ break;
+ case PTE_BLOCK_MEMTYPE(MT_NORMAL):
+ printf(" | %-13s", "Normal");
+ break;
+ default:
+ printf(" | %-13s", "Unknown");
+ }
+}
+
+static void pretty_print_block_memtype(u64 pte)
+{
+ u64 share = pte & (3 << 8);
+
+ switch (share) {
+ case PTE_BLOCK_NON_SHARE:
+ printf(" | %-16s", "Non-shareable");
+ break;
+ case PTE_BLOCK_OUTER_SHARE:
+ printf(" | %-16s", "Outer-shareable");
+ break;
+ case PTE_BLOCK_INNER_SHARE:
+ printf(" | %-16s", "Inner-shareable");
+ break;
+ default:
+ printf(" | %-16s", "Unknown");
+ }
+}
+
+static void print_pte(u64 pte, int level)
+{
+ if (PTE_IS_TABLE(pte, level)) {
+ printf(" %-5s", "Table");
+ pretty_print_table_attrs(pte);
+ } else {
+ pretty_print_pte_type(pte);
+ pretty_print_block_attrs(pte);
+ pretty_print_block_memtype(pte);
+ }
+ printf("\n");
+}
+
+/**
+ * pagetable_print_entry() - Callback function to print a single pagetable region
+ *
+ * This is the default callback used by @dump_pagetable(). It does some basic pretty
+ * printing (see example in the U-Boot arm64 documentation). It can be replaced by
+ * a custom callback function if more detailed information is needed.
+ *
+ * @start_attrs: The start address and attributes of the region (or table address)
+ * @end: The end address of the region (or 0 if it's a table)
+ * @va_bits: The number of bits used for the virtual address
+ * @level: The level of the region
+ * @priv: Private data for the callback (unused)
+ */
+static bool pagetable_print_entry(u64 start_attrs, u64 end, int va_bits, int level, void *priv)
+{
+ u64 _addr = start_attrs & GENMASK_ULL(va_bits, PAGE_SHIFT);
+ int indent = va_bits < 39 ? level - 1 : level;
+
+ printf("%*s", indent * 2, "");
+ if (PTE_IS_TABLE(start_attrs, level))
+ printf("[%#011llx]%14s", _addr, "");
+ else
+ printf("[%#011llx - %#011llx]", _addr, end);
+
+ printf("%*s | ", (3 - level) * 2, "");
+ print_pte(start_attrs, level);
+
+ return false;
+}
+
+void walk_pagetable(u64 ttbr, u64 tcr, pte_walker_cb_t cb, void *priv)
+{
+ __pagetable_walk(ttbr, tcr, 0, cb, priv);
+}
+
+void dump_pagetable(u64 ttbr, u64 tcr)
+{
+ u64 va_bits = 64 - (tcr & (BIT(6) - 1));
+
+ printf("Walking pagetable at %p, va_bits: %lld. Using %d levels\n", (void *)ttbr,
+ va_bits, va_bits < 39 ? 3 : 4);
+ walk_pagetable(ttbr, tcr, pagetable_print_entry, NULL);
+}
+
/* Returns the estimated required size of all page tables */
__weak u64 get_page_table_size(void)
{
diff --git a/arch/arm/cpu/armv8/u-boot-spl.lds b/arch/arm/cpu/armv8/u-boot-spl.lds
index ef8af67..215cedd 100644
--- a/arch/arm/cpu/armv8/u-boot-spl.lds
+++ b/arch/arm/cpu/armv8/u-boot-spl.lds
@@ -53,12 +53,7 @@
. = ALIGN(8);
__image_copy_end = .;
-
- .end : {
- . = ALIGN(8);
- *(.__end)
- } >.sram
-
+ _end = .;
_image_binary_end = .;
.bss : {
diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds
index 9ed6239..eee463a 100644
--- a/arch/arm/cpu/u-boot-spl.lds
+++ b/arch/arm/cpu/u-boot-spl.lds
@@ -53,12 +53,8 @@
__rel_dyn_end = .;
}
- .end :
- {
- *(.__end)
- }
-
_image_binary_end = .;
+ _end = .;
.bss __rel_dyn_start (OVERLAY) : {
__bss_start = .;
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index 707b197..2f50087 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -166,11 +166,7 @@
__rel_dyn_end = .;
}
- .end :
- {
- *(.__end)
- }
-
+ _end = .;
_image_binary_end = .;
/*
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index f7032f1..45af766 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -31,7 +31,6 @@
dtb-$(CONFIG_TARGET_A5Y17LTE) += exynos78x0-axy17lte.dtb
dtb-$(CONFIG_TARGET_A3Y17LTE) += exynos78x0-axy17lte.dtb
dtb-$(CONFIG_TARGET_A7Y17LTE) += exynos78x0-axy17lte.dtb
-dtb-$(CONFIG_TARGET_E850_96) += exynos850-e850-96.dtb
dtb-$(CONFIG_ARCH_APPLE) += \
t8103-j274.dtb \
@@ -53,14 +52,6 @@
dtb-$(CONFIG_MACH_S700) += \
s700-cubieboard7.dtb
-dtb-$(CONFIG_ROCKCHIP_PX30) += \
- px30-evb.dtb \
- px30-firefly.dtb \
- px30-engicam-px30-core-ctouch2.dtb \
- px30-engicam-px30-core-ctouch2-of10.dtb \
- px30-engicam-px30-core-edimm2.2.dtb \
- rk3326-odroid-go2.dtb
-
dtb-$(CONFIG_ROCKCHIP_RK3036) += \
rk3036-sdk.dtb
@@ -97,16 +88,17 @@
rk3368-geekbox.dtb \
rk3368-px5-evb.dtb \
-dtb-$(CONFIG_ROCKCHIP_RV1126) += \
- rv1126-edgeble-neu2-io.dtb
-
dtb-$(CONFIG_ARCH_S5P4418) += \
s5p4418-nanopi2.dtb
dtb-$(CONFIG_ARCH_MESON) += \
meson-a1-ad401.dtb
-dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
+dtb-$(CONFIG_ARCH_TEGRA) += \
+ tegra20-asus-sl101.dtb \
+ tegra20-asus-tf101.dtb \
+ tegra20-asus-tf101g.dtb \
+ tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
tegra20-paz00.dtb \
tegra20-plutux.dtb \
@@ -130,9 +122,12 @@
tegra30-cardhu.dtb \
tegra30-colibri.dtb \
tegra30-htc-endeavoru.dtb \
+ tegra30-lenovo-ideapad-yoga-11.dtb \
tegra30-lg-p880.dtb \
tegra30-lg-p895.dtb \
+ tegra30-microsoft-surface-rt.dtb \
tegra30-tec-ng.dtb \
+ tegra30-wexler-qc750.dtb \
tegra114-dalmore.dtb \
tegra124-apalis.dtb \
tegra124-jetson-tk1.dtb \
@@ -345,6 +340,8 @@
versal-mini-qspi-x2-single.dtb \
versal-mini-qspi-x2-stacked.dtb \
xilinx-versal-virt.dtb
+dtb-$(CONFIG_ARCH_VERSAL2) += \
+ amd-versal2-virt.dtb
dtb-$(CONFIG_ARCH_VERSAL_NET) += \
versal-net-mini.dtb \
versal-net-mini-emmc.dtb \
@@ -874,7 +871,6 @@
imx6ull-phytec-segin-ff-rdk-emmc.dtb \
imx6ull-dart-6ul.dtb \
imx6ull-somlabs-visionsom.dtb \
- imx6ulz-bsh-smm-m2.dtb \
imx6ulz-14x14-evk.dtb
dtb-$(CONFIG_ARCH_MX6) += \
@@ -926,10 +922,6 @@
imx8mm-kontron-bl-osm-s.dtb \
imx8mm-mx8menlo.dtb \
imx8mm-phg.dtb \
- imx8mm-phyboard-polis-rdk.dtb \
- imx8mm-phygate-tauri-l.dtb \
- imx8mn-bsh-smm-s2.dtb \
- imx8mn-bsh-smm-s2pro.dtb \
imx8mq-cm.dtb \
imx8mn-var-som-symphony.dtb \
imx8mq-mnt-reform2.dtb \
@@ -945,7 +937,6 @@
imx8mp-dhcom-pdk3-overlay-rev100.dtbo \
imx8mp-icore-mx8mp-edimm2.2.dtb \
imx8mp-msc-sm2s.dtb \
- imx8mp-phyboard-pollux-rdk.dtb \
imx8mq-pico-pi.dtb \
imx8mq-kontron-pitx-imx8m.dtb \
imx8mq-librem5-r4.dtb
@@ -958,9 +949,6 @@
imxrt1020-evk.dtb \
imxrt1170-evk.dtb \
-dtb-$(CONFIG_RCAR_GEN4) += \
- r8a779h0-gray-hawk.dtb
-
dtb-$(CONFIG_TARGET_RZG2L) += \
r9a07g044l2-smarc.dts
@@ -1030,9 +1018,6 @@
dtb-$(CONFIG_TARGET_DEVKIT8000) += omap3-devkit8000.dtb
-dtb-$(CONFIG_TARGET_OMAP3_IGEP00X0) += \
- omap3-igep0020.dtb
-
dtb-$(CONFIG_TARGET_OMAP4_PANDA) += \
omap4-panda.dtb \
omap4-panda-es.dtb
@@ -1153,6 +1138,7 @@
dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
dtb-$(CONFIG_STM32MP13X) += \
+ stm32mp135f-dhcor-dhsbc.dtb \
stm32mp135f-dk.dtb
dtb-$(CONFIG_STM32MP15X) += \
@@ -1192,11 +1178,8 @@
k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtbo \
k3-am654-icssg2.dtbo
-dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
- k3-j721e-r5-common-proc-board.dtb \
- k3-j7200-common-proc-board.dtb \
+dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-r5-common-proc-board.dtb \
k3-j7200-r5-common-proc-board.dtb \
- k3-j721e-sk.dtb \
k3-j721e-r5-sk.dtb \
k3-j721e-beagleboneai64.dtb \
k3-j721e-r5-beagleboneai64.dtb
@@ -1207,19 +1190,18 @@
dtb-$(CONFIG_SOC_K3_J784S4) += k3-am69-r5-sk.dtb \
k3-j784s4-r5-evm.dtb
+dtb-$(CONFIG_SOC_K3_J722S) += k3-j722s-r5-evm.dtb
+
dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-r5-evm.dtb \
k3-am642-r5-sk.dtb \
k3-am642-r5-phycore-som-2gb.dtb
-dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \
- k3-am625-r5-sk.dtb \
- k3-am625-beagleplay.dtb \
+dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-r5-sk.dtb \
k3-am625-r5-beagleplay.dtb \
k3-am625-verdin-r5.dtb \
k3-am625-r5-phycore-som-2gb.dtb
-dtb-$(CONFIG_SOC_K3_AM62A7) += k3-am62a7-sk.dtb \
- k3-am62a7-r5-sk.dtb
+dtb-$(CONFIG_SOC_K3_AM62A7) += k3-am62a7-r5-sk.dtb
dtb-$(CONFIG_SOC_K3_AM62P5) += k3-am62p5-r5-sk.dtb
@@ -1316,6 +1298,7 @@
# Add any required device tree compiler flags here
DTC_FLAGS += -a 0x8
+DTC_FLAGS_imx8mp-dhcom-som-overlay-rev100 += -Wno-avoid_default_addr_size -Wno-reg_format
DTC_FLAGS_imx8mp-dhcom-pdk3-overlay-rev100 += -Wno-avoid_default_addr_size -Wno-reg_format
PHONY += dtbs
diff --git a/arch/arm/dts/amd-versal2-virt.dts b/arch/arm/dts/amd-versal2-virt.dts
new file mode 100644
index 0000000..3b6cbba
--- /dev/null
+++ b/arch/arm/dts/amd-versal2-virt.dts
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Empty device tree for amd-versal2-virt board
+ *
+ * Copyright (C) 2024, Advanced Micro Devices, Inc.
+ */
+
+/dts-v1/;
+
+/ {
+};
diff --git a/arch/arm/dts/armada-385-thecus-n2350.dts b/arch/arm/dts/armada-385-thecus-n2350.dts
index 253cf01..fdaa444 100644
--- a/arch/arm/dts/armada-385-thecus-n2350.dts
+++ b/arch/arm/dts/armada-385-thecus-n2350.dts
@@ -2,7 +2,7 @@
/*
* Device Tree file for Thecus N2350 board
*
- * Copyright (C) 2018-2023 Tony Dinh <mibodhi@gmail.com>
+ * Copyright (C) 2018-2024 Tony Dinh <mibodhi@gmail.com>
* Copyright (C) 2018 Manuel Jung <manuel.jung@hotmail.com>
*/
@@ -143,9 +143,9 @@
fan {
compatible = "gpio-fan";
gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
- gpio-fan,speed-map = < 0 0
- 600 1
- 3000 2 >;
+ gpio-fan,speed-map = < 0 0>,
+ <600 1>,
+ <3000 2 >;
pinctrl-0 = <&pmx_fan>;
pinctrl-names = "default";
};
@@ -415,7 +415,7 @@
compatible = "jedec,spi-nor";
reg = <0>;
- spi-max-frequency = <108000000>;
+ spi-max-frequency = <50000000>;
spi-cpha;
partition@0 {
diff --git a/arch/arm/dts/bcm283x-u-boot.dtsi b/arch/arm/dts/bcm283x-u-boot.dtsi
index 8c17c6f..ec0f93d 100644
--- a/arch/arm/dts/bcm283x-u-boot.dtsi
+++ b/arch/arm/dts/bcm283x-u-boot.dtsi
@@ -6,25 +6,6 @@
* (C) Copyright 2016 Fabian Vogt <fvogt@suse.com>
*/
-/ {
- smbios {
- compatible = "u-boot,sysinfo-smbios";
- smbios {
- system {
- manufacturer = "raspberrypi";
- product = "rpi";
- };
- baseboard {
- manufacturer = "raspberrypi";
- product = "rpi";
- };
- chassis {
- manufacturer = "raspberrypi";
- };
- };
- };
-};
-
&uart0 {
skip-init;
bootph-all;
diff --git a/arch/arm/dts/corstone1000-fvp.dts b/arch/arm/dts/corstone1000-fvp.dts
index 26b0f1b..3076fb9 100644
--- a/arch/arm/dts/corstone1000-fvp.dts
+++ b/arch/arm/dts/corstone1000-fvp.dts
@@ -49,3 +49,28 @@
clock-names = "smclk", "apb_pclk";
};
};
+
+&cpus {
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x1>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x2>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x3>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+};
+
diff --git a/arch/arm/dts/corstone1000.dtsi b/arch/arm/dts/corstone1000.dtsi
index 1e0ec07..5d9d95b 100644
--- a/arch/arm/dts/corstone1000.dtsi
+++ b/arch/arm/dts/corstone1000.dtsi
@@ -21,7 +21,7 @@
stdout-path = "serial0:115200n8";
};
- cpus {
+ cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/dts/exynos850-e850-96-u-boot.dtsi b/arch/arm/dts/exynos850-e850-96-u-boot.dtsi
index 7ad11e9..6d7148f 100644
--- a/arch/arm/dts/exynos850-e850-96-u-boot.dtsi
+++ b/arch/arm/dts/exynos850-e850-96-u-boot.dtsi
@@ -3,35 +3,7 @@
* Copyright (c) 2023 Linaro Ltd.
*/
-&cmu_top {
- bootph-all;
-};
-
-&cmu_peri {
- bootph-all;
-};
-
-&oscclk {
- bootph-all;
-};
-
-&pinctrl_alive {
- bootph-all;
-};
-
&pmu_system_controller {
bootph-all;
samsung,uart-debug-1;
};
-
-&serial_0 {
- bootph-all;
-};
-
-&uart1_pins {
- bootph-all;
-};
-
-&usi_uart {
- bootph-all;
-};
diff --git a/arch/arm/dts/exynos850-e850-96.dts b/arch/arm/dts/exynos850-e850-96.dts
deleted file mode 100644
index f074df8..0000000
--- a/arch/arm/dts/exynos850-e850-96.dts
+++ /dev/null
@@ -1,273 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * WinLink E850-96 board device tree source
- *
- * Copyright (C) 2018 Samsung Electronics Co., Ltd.
- * Copyright (C) 2021 Linaro Ltd.
- *
- * Device tree source file for WinLink's E850-96 board which is based on
- * Samsung Exynos850 SoC.
- */
-
-/dts-v1/;
-
-#include "exynos850.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "WinLink E850-96 board";
- compatible = "winlink,e850-96", "samsung,exynos850";
-
- aliases {
- mmc0 = &mmc_0;
- serial0 = &serial_0;
- };
-
- chosen {
- stdout-path = &serial_0;
- };
-
- connector {
- compatible = "gpio-usb-b-connector", "usb-b-connector";
- label = "micro-USB";
- type = "micro";
- vbus-supply = <®_usb_host_vbus>;
- id-gpios = <&gpa0 0 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <µ_usb_det_pins>;
-
- port {
- usb_dr_connector: endpoint {
- remote-endpoint = <&usb1_drd_sw>;
- };
- };
- };
-
- /*
- * RAM: 4 GiB (eMCP):
- * - 2 GiB at 0x80000000
- * - 2 GiB at 0x880000000
- *
- * 0xbab00000..0xbfffffff: secure memory (85 MiB).
- */
- memory@80000000 {
- device_type = "memory";
- reg = <0x0 0x80000000 0x3ab00000>,
- <0x0 0xc0000000 0x40000000>,
- <0x8 0x80000000 0x80000000>;
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&key_voldown_pins &key_volup_pins>;
-
- volume-down-key {
- label = "Volume Down";
- linux,code = <KEY_VOLUMEDOWN>;
- gpios = <&gpa1 0 GPIO_ACTIVE_LOW>;
- };
-
- volume-up-key {
- label = "Volume Up";
- linux,code = <KEY_VOLUMEUP>;
- gpios = <&gpa0 7 GPIO_ACTIVE_LOW>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- /* HEART_BEAT_LED */
- user_led1: led-1 {
- label = "yellow:user1";
- gpios = <&gpg2 2 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_YELLOW>;
- function = LED_FUNCTION_HEARTBEAT;
- linux,default-trigger = "heartbeat";
- };
-
- /* eMMC_LED */
- user_led2: led-2 {
- label = "yellow:user2";
- gpios = <&gpg2 3 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_YELLOW>;
- linux,default-trigger = "mmc0";
- };
-
- /* SD_LED */
- user_led3: led-3 {
- label = "white:user3";
- gpios = <&gpg2 4 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_WHITE>;
- function = LED_FUNCTION_SD;
- linux,default-trigger = "mmc2";
- };
-
- /* WIFI_LED */
- wlan_active_led: led-4 {
- label = "yellow:wlan";
- gpios = <&gpg2 6 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_YELLOW>;
- function = LED_FUNCTION_WLAN;
- linux,default-trigger = "phy0tx";
- default-state = "off";
- };
-
- /* BLUETOOTH_LED */
- bt_active_led: led-5 {
- label = "blue:bt";
- gpios = <&gpg2 7 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_BLUETOOTH;
- linux,default-trigger = "hci0-power";
- default-state = "off";
- };
- };
-
- /* TODO: Remove this once PMIC is implemented */
- reg_dummy: regulator-0 {
- compatible = "regulator-fixed";
- regulator-name = "dummy_reg";
- };
-
- reg_usb_host_vbus: regulator-1 {
- compatible = "regulator-fixed";
- regulator-name = "usb_host_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpa3 5 GPIO_ACTIVE_LOW>;
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
-
- ramoops@f0000000 {
- compatible = "ramoops";
- reg = <0x0 0xf0000000 0x200000>;
- record-size = <0x20000>;
- console-size = <0x20000>;
- ftrace-size = <0x100000>;
- pmsg-size = <0x20000>;
- };
- };
-
- /*
- * RTC clock (XrtcXTI); external, must be 32.768 kHz.
- *
- * TODO: Remove this once RTC clock is implemented properly as part of
- * PMIC driver.
- */
- rtcclk: clock-rtcclk {
- compatible = "fixed-clock";
- clock-output-names = "rtcclk";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
-};
-
-&cmu_hsi {
- clocks = <&oscclk>, <&rtcclk>,
- <&cmu_top CLK_DOUT_HSI_BUS>,
- <&cmu_top CLK_DOUT_HSI_MMC_CARD>,
- <&cmu_top CLK_DOUT_HSI_USB20DRD>;
- clock-names = "oscclk", "rtcclk", "dout_hsi_bus",
- "dout_hsi_mmc_card", "dout_hsi_usb20drd";
-};
-
-&mmc_0 {
- status = "okay";
- mmc-hs200-1_8v;
- mmc-hs400-1_8v;
- cap-mmc-highspeed;
- non-removable;
- mmc-hs400-enhanced-strobe;
- card-detect-delay = <200>;
- clock-frequency = <800000000>;
- bus-width = <8>;
- samsung,dw-mshc-ciu-div = <3>;
- samsung,dw-mshc-sdr-timing = <0 4>;
- samsung,dw-mshc-ddr-timing = <2 4>;
- samsung,dw-mshc-hs400-timing = <0 2>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&sd0_clk_pins &sd0_cmd_pins &sd0_rdqs_pins &sd0_nreset_pins
- &sd0_bus1_pins &sd0_bus4_pins &sd0_bus8_pins>;
-};
-
-&oscclk {
- clock-frequency = <26000000>;
-};
-
-&pinctrl_alive {
- key_voldown_pins: key-voldown-pins {
- samsung,pins = "gpa1-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
- };
-
- key_volup_pins: key-volup-pins {
- samsung,pins = "gpa0-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
- };
-
- micro_usb_det_pins: micro-usb-det-pins {
- samsung,pins = "gpa0-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- };
-};
-
-&rtc {
- status = "okay";
- clocks = <&cmu_apm CLK_GOUT_RTC_PCLK>, <&rtcclk>;
- clock-names = "rtc", "rtc_src";
-};
-
-&serial_0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins>;
-};
-
-&usbdrd {
- status = "okay";
- vdd10-supply = <®_dummy>;
- vdd33-supply = <®_dummy>;
-};
-
-&usbdrd_dwc3 {
- dr_mode = "otg";
- usb-role-switch;
- role-switch-default-mode = "host";
-
- port {
- usb1_drd_sw: endpoint {
- remote-endpoint = <&usb_dr_connector>;
- };
- };
-};
-
-&usbdrd_phy {
- status = "okay";
-};
-
-&usi_uart {
- samsung,clkreq-on; /* needed for UART mode */
- status = "okay";
-};
-
-&watchdog_cl0 {
- status = "okay";
-};
-
-&watchdog_cl1 {
- status = "okay";
-};
diff --git a/arch/arm/dts/exynos850-pinctrl.dtsi b/arch/arm/dts/exynos850-pinctrl.dtsi
deleted file mode 100644
index 424bc80..0000000
--- a/arch/arm/dts/exynos850-pinctrl.dtsi
+++ /dev/null
@@ -1,663 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Samsung's Exynos850 SoC pin-mux and pin-config device tree source
- *
- * Copyright (C) 2017 Samsung Electronics Co., Ltd.
- * Copyright (C) 2021 Linaro Ltd.
- *
- * Samsung's Exynos850 SoC pin-mux and pin-config options are listed as device
- * tree nodes in this file.
- */
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include "exynos-pinctrl.h"
-
-&pinctrl_alive {
- gpa0: gpa0-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- gpa1: gpa1-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- gpa2: gpa2-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- gpa3: gpa3-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- gpa4: gpa4-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- gpq0: gpq0-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- /* I2C5 (also called CAM_PMIC_I2C in TRM) */
- i2c5_pins: i2c5-pins {
- samsung,pins = "gpa3-5", "gpa3-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
- };
-
- /* I2C6 (also called MOTOR_I2C in TRM) */
- i2c6_pins: i2c6-pins {
- samsung,pins = "gpa3-7", "gpa4-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
- };
-
- /* USI: UART_DEBUG_0 pins */
- uart0_pins: uart0-pins {
- samsung,pins = "gpq0-0", "gpq0-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- };
-
- /* USI: UART_DEBUG_1 pins */
- uart1_pins: uart1-pins {
- samsung,pins = "gpa3-7", "gpa4-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- };
-};
-
-&pinctrl_cmgp {
- gpm0: gpm0-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- gpm1: gpm1-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- gpm2: gpm2-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- gpm3: gpm3-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- gpm4: gpm4-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- gpm5: gpm5-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- gpm6: gpm6-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- gpm7: gpm7-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- /* USI_CMGP0: HSI2C function */
- hsi2c3_pins: hsi2c3-pins {
- samsung,pins = "gpm0-0", "gpm1-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
- };
-
- /* USI_CMGP0: UART function (4 pins, Auto Flow Control) */
- uart1_single_pins: uart1-single-pins {
- samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0", "gpm3-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- };
-
- /* USI_CMGP0: UART function (2 pins, Non-Auto Flow Control) */
- uart1_dual_pins: uart1-dual-pins {
- samsung,pins = "gpm0-0", "gpm1-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- };
-
- /* USI_CMGP0: SPI function */
- spi1_pins: spi1-pins {
- samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0", "gpm3-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
- };
-
- /* USI_CMGP1: HSI2C function */
- hsi2c4_pins: hsi2c4-pins {
- samsung,pins = "gpm4-0", "gpm5-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
- };
-
- /* USI_CMGP1: UART function (4 pins, Auto Flow Control) */
- uart2_single_pins: uart2-single-pins {
- samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0", "gpm7-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- };
-
- /* USI_CMGP1: UART function (2 pins, Non-Auto Flow Control) */
- uart2_dual_pins: uart2-dual-pins {
- samsung,pins = "gpm4-0", "gpm5-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- };
-
- /* USI_CMGP1: SPI function */
- spi2_pins: spi2-pins {
- samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0", "gpm7-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
- };
-};
-
-&pinctrl_aud {
- gpb0: gpb0-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpb1: gpb1-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- aud_codec_mclk_pins: aud-codec-mclk-pins {
- samsung,pins = "gpb0-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
- };
-
- aud_codec_mclk_idle_pins: aud-codec-mclk-idle-pins {
- samsung,pins = "gpb0-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
- };
-
- aud_i2s0_pins: aud-i2s0-pins {
- samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
- };
-
- aud_i2s0_idle_pins: aud-i2s0-idle-pins {
- samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
- };
-
- aud_i2s1_pins: aud-i2s1-pins {
- samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
- };
-
- aud_i2s1_idle_pins: aud-i2s1-idle-pins {
- samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
- };
-
- aud_fm_pins: aud-fm-pins {
- samsung,pins = "gpb1-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
- };
-
- aud_fm_idle_pins: aud-fm-idle-pins {
- samsung,pins = "gpb1-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
- };
-};
-
-&pinctrl_hsi {
- gpf2: gpf2-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- sd2_clk_pins: sd2-clk-pins {
- samsung,pins = "gpf2-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2>;
- };
-
- sd2_cmd_pins: sd2-cmd-pins {
- samsung,pins = "gpf2-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2>;
- };
-
- sd2_bus1_pins: sd2-bus1-pins {
- samsung,pins = "gpf2-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2>;
- };
-
- sd2_bus4_pins: sd2-bus4-pins {
- samsung,pins = "gpf2-3", "gpf2-4", "gpf2-5";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2>;
- };
-
- sd2_pdn_pins: sd2-pdn-pins {
- samsung,pins = "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
- "gpf2-4", "gpf2-5";
- samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
- };
-};
-
-&pinctrl_core {
- gpf0: gpf0-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpf1: gpf1-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- sd0_clk_pins: sd0-clk-pins {
- samsung,pins = "gpf0-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
- };
-
- sd0_cmd_pins: sd0-cmd-pins {
- samsung,pins = "gpf0-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
- };
-
- sd0_rdqs_pins: sd0-rdqs-pins {
- samsung,pins = "gpf0-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
- };
-
- sd0_nreset_pins: sd0-nreset-pins {
- samsung,pins = "gpf0-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
- };
-
- sd0_bus1_pins: sd0-bus1-pins {
- samsung,pins = "gpf1-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
- };
-
- sd0_bus4_pins: sd0-bus4-pins {
- samsung,pins = "gpf1-1", "gpf1-2", "gpf1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
- };
-
- sd0_bus8_pins: sd0-bus8-pins {
- samsung,pins = "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
- };
-};
-
-&pinctrl_peri {
- gpc0: gpc0-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpc1: gpc1-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpg0: gpg0-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpg1: gpg1-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpg2: gpg2-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpg3: gpg3-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpp0: gpp0-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
- gpp1: gpp1-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpp2: gpp2-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- sensor_mclk0_in_pins: sensor-mclk0-in-pins {
- samsung,pins = "gpc0-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
- };
-
- sensor_mclk0_out_pins: sensor-mclk0-out-pins {
- samsung,pins = "gpc0-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
- };
-
- sensor_mclk0_fn_pins: sensor-mclk0-fn-pins {
- samsung,pins = "gpc0-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
- };
-
- sensor_mclk1_in_pins: sensor-mclk1-in-pins {
- samsung,pins = "gpc0-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
- };
-
- sensor_mclk1_out_pins: sensor-mclk1-out-pins {
- samsung,pins = "gpc0-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
- };
-
- sensor_mclk1_fn_pins: sensor-mclk1-fn-pins {
- samsung,pins = "gpc0-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
- };
-
- sensor_mclk2_in_pins: sensor-mclk2-in-pins {
- samsung,pins = "gpc0-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
- };
-
- sensor_mclk2_out_pins: sensor-mclk2-out-pins {
- samsung,pins = "gpc0-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
- };
-
- sensor_mclk2_fn_pins: sensor-mclk2-fn-pins {
- samsung,pins = "gpc0-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
- };
-
- /* USI: HSI2C0 */
- hsi2c0_pins: hsi2c0-pins {
- samsung,pins = "gpc1-0", "gpc1-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
- };
-
- /* USI: HSI2C1 */
- hsi2c1_pins: hsi2c1-pins {
- samsung,pins = "gpc1-2", "gpc1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
- };
-
- /* USI: HSI2C2 */
- hsi2c2_pins: hsi2c2-pins {
- samsung,pins = "gpc1-4", "gpc1-5";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
- };
-
- /* USI: SPI */
- spi0_pins: spi0-pins {
- samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2", "gpp2-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
- };
-
- i2c0_pins: i2c0-pins {
- samsung,pins = "gpp0-0", "gpp0-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
- };
-
- i2c1_pins: i2c1-pins {
- samsung,pins = "gpp0-2", "gpp0-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
- };
-
- i2c2_pins: i2c2-pins {
- samsung,pins = "gpp0-4", "gpp0-5";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
- };
-
- i2c3_pins: i2c3-pins {
- samsung,pins = "gpp1-0", "gpp1-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
- };
-
- i2c4_pins: i2c4-pins {
- samsung,pins = "gpp1-2", "gpp1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
- };
-
- xclkout_pins: xclkout-pins {
- samsung,pins = "gpq0-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- };
-};
diff --git a/arch/arm/dts/exynos850.dtsi b/arch/arm/dts/exynos850.dtsi
deleted file mode 100644
index 53104e6..0000000
--- a/arch/arm/dts/exynos850.dtsi
+++ /dev/null
@@ -1,809 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Samsung Exynos850 SoC device tree source
- *
- * Copyright (C) 2018 Samsung Electronics Co., Ltd.
- * Copyright (C) 2021 Linaro Ltd.
- *
- * Samsung Exynos850 SoC device nodes are listed in this file.
- * Exynos850 based board files can include this file and provide
- * values for board specific bindings.
- */
-
-#include <dt-bindings/clock/exynos850.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/soc/samsung,exynos-usi.h>
-
-/ {
- /* Also known under engineering name Exynos3830 */
- compatible = "samsung,exynos850";
- #address-cells = <2>;
- #size-cells = <1>;
-
- interrupt-parent = <&gic>;
-
- aliases {
- pinctrl0 = &pinctrl_alive;
- pinctrl1 = &pinctrl_cmgp;
- pinctrl2 = &pinctrl_aud;
- pinctrl3 = &pinctrl_hsi;
- pinctrl4 = &pinctrl_core;
- pinctrl5 = &pinctrl_peri;
- };
-
- arm-pmu {
- compatible = "arm,cortex-a55-pmu";
- interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
- <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
- };
-
- /* Main system clock (XTCXO); external, must be 26 MHz */
- oscclk: clock-oscclk {
- compatible = "fixed-clock";
- clock-output-names = "oscclk";
- #clock-cells = <0>;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu-map {
- cluster0 {
- core0 {
- cpu = <&cpu0>;
- };
- core1 {
- cpu = <&cpu1>;
- };
- core2 {
- cpu = <&cpu2>;
- };
- core3 {
- cpu = <&cpu3>;
- };
- };
-
- cluster1 {
- core0 {
- cpu = <&cpu4>;
- };
- core1 {
- cpu = <&cpu5>;
- };
- core2 {
- cpu = <&cpu6>;
- };
- core3 {
- cpu = <&cpu7>;
- };
- };
- };
-
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a55";
- reg = <0x0>;
- enable-method = "psci";
- };
- cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a55";
- reg = <0x1>;
- enable-method = "psci";
- };
- cpu2: cpu@2 {
- device_type = "cpu";
- compatible = "arm,cortex-a55";
- reg = <0x2>;
- enable-method = "psci";
- };
- cpu3: cpu@3 {
- device_type = "cpu";
- compatible = "arm,cortex-a55";
- reg = <0x3>;
- enable-method = "psci";
- };
- cpu4: cpu@100 {
- device_type = "cpu";
- compatible = "arm,cortex-a55";
- reg = <0x100>;
- enable-method = "psci";
- };
- cpu5: cpu@101 {
- device_type = "cpu";
- compatible = "arm,cortex-a55";
- reg = <0x101>;
- enable-method = "psci";
- };
- cpu6: cpu@102 {
- device_type = "cpu";
- compatible = "arm,cortex-a55";
- reg = <0x102>;
- enable-method = "psci";
- };
- cpu7: cpu@103 {
- device_type = "cpu";
- compatible = "arm,cortex-a55";
- reg = <0x103>;
- enable-method = "psci";
- };
- };
-
- psci {
- compatible = "arm,psci-1.0";
- method = "smc";
- };
-
- timer {
- compatible = "arm,armv8-timer";
- /* Hypervisor Virtual Timer interrupt is not wired to GIC */
- interrupts =
- <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
- soc: soc@0 {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0x0 0x20000000>;
-
- chipid@10000000 {
- compatible = "samsung,exynos850-chipid";
- reg = <0x10000000 0x100>;
- };
-
- timer@10040000 {
- compatible = "samsung,exynos850-mct",
- "samsung,exynos4210-mct";
- reg = <0x10040000 0x800>;
- interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&oscclk>, <&cmu_peri CLK_GOUT_MCT_PCLK>;
- clock-names = "fin_pll", "mct";
- };
-
- gic: interrupt-controller@12a01000 {
- compatible = "arm,gic-400";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- reg = <0x12a01000 0x1000>,
- <0x12a02000 0x2000>,
- <0x12a04000 0x2000>,
- <0x12a06000 0x2000>;
- interrupt-controller;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
- IRQ_TYPE_LEVEL_HIGH)>;
- };
-
- pmu_system_controller: system-controller@11860000 {
- compatible = "samsung,exynos850-pmu", "syscon";
- reg = <0x11860000 0x10000>;
-
- reboot: syscon-reboot {
- compatible = "syscon-reboot";
- regmap = <&pmu_system_controller>;
- offset = <0x3a00>; /* SYSTEM_CONFIGURATION */
- mask = <0x2>; /* SWRESET_SYSTEM */
- value = <0x2>; /* reset value */
- };
- };
-
- watchdog_cl0: watchdog@10050000 {
- compatible = "samsung,exynos850-wdt";
- reg = <0x10050000 0x100>;
- interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cmu_peri CLK_GOUT_WDT0_PCLK>, <&oscclk>;
- clock-names = "watchdog", "watchdog_src";
- samsung,syscon-phandle = <&pmu_system_controller>;
- samsung,cluster-index = <0>;
- status = "disabled";
- };
-
- watchdog_cl1: watchdog@10060000 {
- compatible = "samsung,exynos850-wdt";
- reg = <0x10060000 0x100>;
- interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cmu_peri CLK_GOUT_WDT1_PCLK>, <&oscclk>;
- clock-names = "watchdog", "watchdog_src";
- samsung,syscon-phandle = <&pmu_system_controller>;
- samsung,cluster-index = <1>;
- status = "disabled";
- };
-
- cmu_peri: clock-controller@10030000 {
- compatible = "samsung,exynos850-cmu-peri";
- reg = <0x10030000 0x8000>;
- #clock-cells = <1>;
-
- clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>,
- <&cmu_top CLK_DOUT_PERI_UART>,
- <&cmu_top CLK_DOUT_PERI_IP>;
- clock-names = "oscclk", "dout_peri_bus",
- "dout_peri_uart", "dout_peri_ip";
- };
-
- cmu_g3d: clock-controller@11400000 {
- compatible = "samsung,exynos850-cmu-g3d";
- reg = <0x11400000 0x8000>;
- #clock-cells = <1>;
-
- clocks = <&oscclk>, <&cmu_top CLK_DOUT_G3D_SWITCH>;
- clock-names = "oscclk", "dout_g3d_switch";
- };
-
- cmu_apm: clock-controller@11800000 {
- compatible = "samsung,exynos850-cmu-apm";
- reg = <0x11800000 0x8000>;
- #clock-cells = <1>;
-
- clocks = <&oscclk>, <&cmu_top CLK_DOUT_CLKCMU_APM_BUS>;
- clock-names = "oscclk", "dout_clkcmu_apm_bus";
- };
-
- cmu_cmgp: clock-controller@11c00000 {
- compatible = "samsung,exynos850-cmu-cmgp";
- reg = <0x11c00000 0x8000>;
- #clock-cells = <1>;
-
- clocks = <&oscclk>, <&cmu_apm CLK_GOUT_CLKCMU_CMGP_BUS>;
- clock-names = "oscclk", "gout_clkcmu_cmgp_bus";
- };
-
- cmu_core: clock-controller@12000000 {
- compatible = "samsung,exynos850-cmu-core";
- reg = <0x12000000 0x8000>;
- #clock-cells = <1>;
-
- clocks = <&oscclk>, <&cmu_top CLK_DOUT_CORE_BUS>,
- <&cmu_top CLK_DOUT_CORE_CCI>,
- <&cmu_top CLK_DOUT_CORE_MMC_EMBD>,
- <&cmu_top CLK_DOUT_CORE_SSS>;
- clock-names = "oscclk", "dout_core_bus",
- "dout_core_cci", "dout_core_mmc_embd",
- "dout_core_sss";
- };
-
- cmu_top: clock-controller@120e0000 {
- compatible = "samsung,exynos850-cmu-top";
- reg = <0x120e0000 0x8000>;
- #clock-cells = <1>;
-
- clocks = <&oscclk>;
- clock-names = "oscclk";
- };
-
- cmu_mfcmscl: clock-controller@12c00000 {
- compatible = "samsung,exynos850-cmu-mfcmscl";
- reg = <0x12c00000 0x8000>;
- #clock-cells = <1>;
-
- clocks = <&oscclk>,
- <&cmu_top CLK_DOUT_MFCMSCL_MFC>,
- <&cmu_top CLK_DOUT_MFCMSCL_M2M>,
- <&cmu_top CLK_DOUT_MFCMSCL_MCSC>,
- <&cmu_top CLK_DOUT_MFCMSCL_JPEG>;
- clock-names = "oscclk", "dout_mfcmscl_mfc",
- "dout_mfcmscl_m2m", "dout_mfcmscl_mcsc",
- "dout_mfcmscl_jpeg";
- };
-
- cmu_dpu: clock-controller@13000000 {
- compatible = "samsung,exynos850-cmu-dpu";
- reg = <0x13000000 0x8000>;
- #clock-cells = <1>;
-
- clocks = <&oscclk>, <&cmu_top CLK_DOUT_DPU>;
- clock-names = "oscclk", "dout_dpu";
- };
-
- cmu_hsi: clock-controller@13400000 {
- compatible = "samsung,exynos850-cmu-hsi";
- reg = <0x13400000 0x8000>;
- #clock-cells = <1>;
-
- clocks = <&oscclk>,
- <&cmu_top CLK_DOUT_HSI_BUS>,
- <&cmu_top CLK_DOUT_HSI_MMC_CARD>,
- <&cmu_top CLK_DOUT_HSI_USB20DRD>;
- clock-names = "oscclk", "dout_hsi_bus",
- "dout_hsi_mmc_card", "dout_hsi_usb20drd";
- };
-
- cmu_is: clock-controller@14500000 {
- compatible = "samsung,exynos850-cmu-is";
- reg = <0x14500000 0x8000>;
- #clock-cells = <1>;
-
- clocks = <&oscclk>,
- <&cmu_top CLK_DOUT_IS_BUS>,
- <&cmu_top CLK_DOUT_IS_ITP>,
- <&cmu_top CLK_DOUT_IS_VRA>,
- <&cmu_top CLK_DOUT_IS_GDC>;
- clock-names = "oscclk", "dout_is_bus", "dout_is_itp",
- "dout_is_vra", "dout_is_gdc";
- };
-
- cmu_aud: clock-controller@14a00000 {
- compatible = "samsung,exynos850-cmu-aud";
- reg = <0x14a00000 0x8000>;
- #clock-cells = <1>;
-
- clocks = <&oscclk>, <&cmu_top CLK_DOUT_AUD>;
- clock-names = "oscclk", "dout_aud";
- };
-
- pinctrl_alive: pinctrl@11850000 {
- compatible = "samsung,exynos850-pinctrl";
- reg = <0x11850000 0x1000>;
-
- wakeup-interrupt-controller {
- compatible = "samsung,exynos850-wakeup-eint";
- };
- };
-
- pinctrl_cmgp: pinctrl@11c30000 {
- compatible = "samsung,exynos850-pinctrl";
- reg = <0x11c30000 0x1000>;
-
- wakeup-interrupt-controller {
- compatible = "samsung,exynos850-wakeup-eint";
- };
- };
-
- pinctrl_core: pinctrl@12070000 {
- compatible = "samsung,exynos850-pinctrl";
- reg = <0x12070000 0x1000>;
- interrupts = <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- pinctrl_hsi: pinctrl@13430000 {
- compatible = "samsung,exynos850-pinctrl";
- reg = <0x13430000 0x1000>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- pinctrl_peri: pinctrl@139b0000 {
- compatible = "samsung,exynos850-pinctrl";
- reg = <0x139b0000 0x1000>;
- interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- pinctrl_aud: pinctrl@14a60000 {
- compatible = "samsung,exynos850-pinctrl";
- reg = <0x14a60000 0x1000>;
- };
-
- rtc: rtc@11a30000 {
- compatible = "samsung,s3c6410-rtc";
- reg = <0x11a30000 0x100>;
- interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cmu_apm CLK_GOUT_RTC_PCLK>;
- clock-names = "rtc";
- status = "disabled";
- };
-
- mmc_0: mmc@12100000 {
- compatible = "samsung,exynos7-dw-mshc-smu";
- reg = <0x12100000 0x2000>;
- interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cmu_core CLK_GOUT_MMC_EMBD_ACLK>,
- <&cmu_core CLK_GOUT_MMC_EMBD_SDCLKIN>;
- clock-names = "biu", "ciu";
- fifo-depth = <0x40>;
- status = "disabled";
- };
-
- i2c_0: i2c@13830000 {
- compatible = "samsung,s3c2440-i2c";
- reg = <0x13830000 0x100>;
- interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins>;
- clocks = <&cmu_peri CLK_GOUT_I2C0_PCLK>;
- clock-names = "i2c";
- status = "disabled";
- };
-
- i2c_1: i2c@13840000 {
- compatible = "samsung,s3c2440-i2c";
- reg = <0x13840000 0x100>;
- interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins>;
- clocks = <&cmu_peri CLK_GOUT_I2C1_PCLK>;
- clock-names = "i2c";
- status = "disabled";
- };
-
- i2c_2: i2c@13850000 {
- compatible = "samsung,s3c2440-i2c";
- reg = <0x13850000 0x100>;
- interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins>;
- clocks = <&cmu_peri CLK_GOUT_I2C2_PCLK>;
- clock-names = "i2c";
- status = "disabled";
- };
-
- i2c_3: i2c@13860000 {
- compatible = "samsung,s3c2440-i2c";
- reg = <0x13860000 0x100>;
- interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3_pins>;
- clocks = <&cmu_peri CLK_GOUT_I2C3_PCLK>;
- clock-names = "i2c";
- status = "disabled";
- };
-
- i2c_4: i2c@13870000 {
- compatible = "samsung,s3c2440-i2c";
- reg = <0x13870000 0x100>;
- interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c4_pins>;
- clocks = <&cmu_peri CLK_GOUT_I2C4_PCLK>;
- clock-names = "i2c";
- status = "disabled";
- };
-
- /* I2C_5 (also called CAM_PMIC_I2C in TRM) */
- i2c_5: i2c@13880000 {
- compatible = "samsung,s3c2440-i2c";
- reg = <0x13880000 0x100>;
- interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c5_pins>;
- clocks = <&cmu_peri CLK_GOUT_I2C5_PCLK>;
- clock-names = "i2c";
- status = "disabled";
- };
-
- /* I2C_6 (also called MOTOR_I2C in TRM) */
- i2c_6: i2c@13890000 {
- compatible = "samsung,s3c2440-i2c";
- reg = <0x13890000 0x100>;
- interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c6_pins>;
- clocks = <&cmu_peri CLK_GOUT_I2C6_PCLK>;
- clock-names = "i2c";
- status = "disabled";
- };
-
- sysmmu_mfcmscl: sysmmu@12c50000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x12c50000 0x9000>;
- interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "sysmmu";
- clocks = <&cmu_mfcmscl CLK_GOUT_MFCMSCL_SYSMMU_CLK>;
- #iommu-cells = <0>;
- };
-
- sysmmu_dpu: sysmmu@130c0000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x130c0000 0x9000>;
- interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "sysmmu";
- clocks = <&cmu_dpu CLK_GOUT_DPU_SMMU_CLK>;
- #iommu-cells = <0>;
- };
-
- sysmmu_is0: sysmmu@14550000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x14550000 0x9000>;
- interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "sysmmu";
- clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS0_CLK>;
- #iommu-cells = <0>;
- };
-
- sysmmu_is1: sysmmu@14570000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x14570000 0x9000>;
- interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "sysmmu";
- clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS1_CLK>;
- #iommu-cells = <0>;
- };
-
- sysmmu_aud: sysmmu@14850000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x14850000 0x9000>;
- interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "sysmmu";
- clocks = <&cmu_aud CLK_GOUT_AUD_SYSMMU_CLK>;
- #iommu-cells = <0>;
- };
-
- sysreg_peri: syscon@10020000 {
- compatible = "samsung,exynos850-peri-sysreg",
- "samsung,exynos850-sysreg", "syscon";
- reg = <0x10020000 0x10000>;
- clocks = <&cmu_peri CLK_GOUT_SYSREG_PERI_PCLK>;
- };
-
- sysreg_cmgp: syscon@11c20000 {
- compatible = "samsung,exynos850-cmgp-sysreg",
- "samsung,exynos850-sysreg", "syscon";
- reg = <0x11c20000 0x10000>;
- clocks = <&cmu_cmgp CLK_GOUT_SYSREG_CMGP_PCLK>;
- };
-
- usbdrd: usb@13600000 {
- compatible = "samsung,exynos850-dwusb3";
- ranges = <0x0 0x13600000 0x10000>;
- clocks = <&cmu_hsi CLK_GOUT_USB_BUS_EARLY_CLK>,
- <&cmu_hsi CLK_GOUT_USB_REF_CLK>;
- clock-names = "bus_early", "ref";
- #address-cells = <1>;
- #size-cells = <1>;
- status = "disabled";
-
- usbdrd_dwc3: usb@0 {
- compatible = "snps,dwc3";
- reg = <0x0 0x10000>;
- interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&usbdrd_phy 0>;
- phy-names = "usb2-phy";
- };
- };
-
- usbdrd_phy: phy@135d0000 {
- compatible = "samsung,exynos850-usbdrd-phy";
- reg = <0x135d0000 0x100>;
- clocks = <&cmu_hsi CLK_GOUT_USB_PHY_ACLK>,
- <&cmu_hsi CLK_GOUT_USB_PHY_REF_CLK>;
- clock-names = "phy", "ref";
- samsung,pmu-syscon = <&pmu_system_controller>;
- #phy-cells = <1>;
- status = "disabled";
- };
-
- usi_uart: usi@138200c0 {
- compatible = "samsung,exynos850-usi";
- reg = <0x138200c0 0x20>;
- samsung,sysreg = <&sysreg_peri 0x1010>;
- samsung,mode = <USI_V2_UART>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- clocks = <&cmu_peri CLK_GOUT_UART_PCLK>,
- <&cmu_peri CLK_GOUT_UART_IPCLK>;
- clock-names = "pclk", "ipclk";
- status = "disabled";
-
- serial_0: serial@13820000 {
- compatible = "samsung,exynos850-uart";
- reg = <0x13820000 0xc0>;
- interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins>;
- clocks = <&cmu_peri CLK_GOUT_UART_PCLK>,
- <&cmu_peri CLK_GOUT_UART_IPCLK>;
- clock-names = "uart", "clk_uart_baud0";
- status = "disabled";
- };
- };
-
- usi_hsi2c_0: usi@138a00c0 {
- compatible = "samsung,exynos850-usi";
- reg = <0x138a00c0 0x20>;
- samsung,sysreg = <&sysreg_peri 0x1020>;
- samsung,mode = <USI_V2_I2C>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- clocks = <&cmu_peri CLK_GOUT_HSI2C0_PCLK>,
- <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>;
- clock-names = "pclk", "ipclk";
- status = "disabled";
-
- hsi2c_0: i2c@138a0000 {
- compatible = "samsung,exynosautov9-hsi2c";
- reg = <0x138a0000 0xc0>;
- interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c0_pins>;
- clocks = <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>,
- <&cmu_peri CLK_GOUT_HSI2C0_PCLK>;
- clock-names = "hsi2c", "hsi2c_pclk";
- status = "disabled";
- };
- };
-
- usi_hsi2c_1: usi@138b00c0 {
- compatible = "samsung,exynos850-usi";
- reg = <0x138b00c0 0x20>;
- samsung,sysreg = <&sysreg_peri 0x1030>;
- samsung,mode = <USI_V2_I2C>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- clocks = <&cmu_peri CLK_GOUT_HSI2C1_PCLK>,
- <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>;
- clock-names = "pclk", "ipclk";
- status = "disabled";
-
- hsi2c_1: i2c@138b0000 {
- compatible = "samsung,exynosautov9-hsi2c";
- reg = <0x138b0000 0xc0>;
- interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c1_pins>;
- clocks = <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>,
- <&cmu_peri CLK_GOUT_HSI2C1_PCLK>;
- clock-names = "hsi2c", "hsi2c_pclk";
- status = "disabled";
- };
- };
-
- usi_hsi2c_2: usi@138c00c0 {
- compatible = "samsung,exynos850-usi";
- reg = <0x138c00c0 0x20>;
- samsung,sysreg = <&sysreg_peri 0x1040>;
- samsung,mode = <USI_V2_I2C>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- clocks = <&cmu_peri CLK_GOUT_HSI2C2_PCLK>,
- <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>;
- clock-names = "pclk", "ipclk";
- status = "disabled";
-
- hsi2c_2: i2c@138c0000 {
- compatible = "samsung,exynosautov9-hsi2c";
- reg = <0x138c0000 0xc0>;
- interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c2_pins>;
- clocks = <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>,
- <&cmu_peri CLK_GOUT_HSI2C2_PCLK>;
- clock-names = "hsi2c", "hsi2c_pclk";
- status = "disabled";
- };
- };
-
- usi_spi_0: usi@139400c0 {
- compatible = "samsung,exynos850-usi";
- reg = <0x139400c0 0x20>;
- samsung,sysreg = <&sysreg_peri 0x1050>;
- samsung,mode = <USI_V2_SPI>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- clocks = <&cmu_peri CLK_GOUT_SPI0_PCLK>,
- <&cmu_peri CLK_GOUT_SPI0_IPCLK>;
- clock-names = "pclk", "ipclk";
- status = "disabled";
- };
-
- usi_cmgp0: usi@11d000c0 {
- compatible = "samsung,exynos850-usi";
- reg = <0x11d000c0 0x20>;
- samsung,sysreg = <&sysreg_cmgp 0x2000>;
- samsung,mode = <USI_V2_I2C>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>,
- <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>;
- clock-names = "pclk", "ipclk";
- status = "disabled";
-
- hsi2c_3: i2c@11d00000 {
- compatible = "samsung,exynosautov9-hsi2c";
- reg = <0x11d00000 0xc0>;
- interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c3_pins>;
- clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>,
- <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>;
- clock-names = "hsi2c", "hsi2c_pclk";
- status = "disabled";
- };
-
- serial_1: serial@11d00000 {
- compatible = "samsung,exynos850-uart";
- reg = <0x11d00000 0xc0>;
- interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_single_pins>;
- clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>,
- <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>;
- clock-names = "uart", "clk_uart_baud0";
- status = "disabled";
- };
- };
-
- usi_cmgp1: usi@11d200c0 {
- compatible = "samsung,exynos850-usi";
- reg = <0x11d200c0 0x20>;
- samsung,sysreg = <&sysreg_cmgp 0x2010>;
- samsung,mode = <USI_V2_I2C>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>,
- <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>;
- clock-names = "pclk", "ipclk";
- status = "disabled";
-
- hsi2c_4: i2c@11d20000 {
- compatible = "samsung,exynosautov9-hsi2c";
- reg = <0x11d20000 0xc0>;
- interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c4_pins>;
- clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>,
- <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>;
- clock-names = "hsi2c", "hsi2c_pclk";
- status = "disabled";
- };
-
- serial_2: serial@11d20000 {
- compatible = "samsung,exynos850-uart";
- reg = <0x11d20000 0xc0>;
- interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_single_pins>;
- clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>,
- <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>;
- clock-names = "uart", "clk_uart_baud0";
- status = "disabled";
- };
- };
- };
-};
-
-#include "exynos850-pinctrl.dtsi"
diff --git a/arch/arm/dts/imx6ulz-bsh-smm-m2.dts b/arch/arm/dts/imx6ulz-bsh-smm-m2.dts
deleted file mode 100644
index 59bcfc9..0000000
--- a/arch/arm/dts/imx6ulz-bsh-smm-m2.dts
+++ /dev/null
@@ -1,146 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 BSH Hausgeraete GmbH
- */
-
-/dts-v1/;
-
-#include <dt-bindings/input/input.h>
-#include "imx6ulz.dtsi"
-
-/ {
- model = "BSH SMM M2";
- compatible = "bsh,imx6ulz-bsh-smm-m2", "fsl,imx6ull", "fsl,imx6ulz";
-
- chosen {
- stdout-path = &uart4;
- };
-
- usdhc2_pwrseq: usdhc2-pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>;
- };
-};
-
-&gpmi {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpmi_nand>;
- nand-on-flash-bbt;
- status = "okay";
-};
-
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- uart-has-rtscts;
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm4330-bt";
- max-speed = <3000000>;
- shutdown-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
- device-wakeup-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
- host-wakeup-gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&uart4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart4>;
- status = "okay";
-};
-
-&usbotg1 {
- dr_mode = "peripheral";
- srp-disable;
- hnp-disable;
- adp-disable;
- status = "okay";
-};
-
-&usbphy1 {
- fsl,tx-d-cal = <106>;
-};
-
-&usdhc2 {
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wlan>;
- bus-width = <4>;
- no-1-8-v;
- non-removable;
- cap-power-off-card;
- keep-power-in-suspend;
- cap-sdio-irq;
- mmc-pwrseq = <&usdhc2_pwrseq>;
- status = "okay";
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- interrupt-parent = <&gpio1>;
- interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "host-wake";
- };
-};
-
-&wdog1 {
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_gpmi_nand: gpmi-nand {
- fsl,pins = <
- MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
- MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
- MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
- MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
- MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
- MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
- MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
- MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
- MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
- MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
- MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
- MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
- MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
- MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
- MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
- >;
- };
-
- pinctrl_uart3: uart3grp {
- fsl,pins = <
- MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
- MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b099
- MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1
- MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b099
- MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x79 /* BT_REG_ON */
- MX6UL_PAD_SD1_CLK__GPIO2_IO17 0x100b1 /* BT_DEV_WAKE out */
- MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x1b0b0 /* BT_HOST_WAKE in */
- >;
- };
-
- pinctrl_uart4: uart4grp {
- fsl,pins = <
- MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1
- MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1
- >;
- };
-
- pinctrl_wlan: wlangrp {
- fsl,pins = <
- MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059
- MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10059
- MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059
- MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059
- MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059
- MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059
- MX6UL_PAD_SD1_DATA3__GPIO2_IO21 0x79 /* WL_REG_ON */
- MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0x100b1 /* WL_DEV_WAKE - WiFi_GPIO_4 - WiFi FW UART */
- MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b1 /* WL_HOST_WAKE - WIFI_GPIO_0 - OOB IRQ */
- MX6UL_PAD_ENET1_RX_EN__OSC32K_32K_OUT 0x4001b031 /* OSC 32Khz wifi clk in */
- >;
- };
-};
diff --git a/arch/arm/dts/imx8mm-phyboard-polis-rdk.dts b/arch/arm/dts/imx8mm-phyboard-polis-rdk.dts
deleted file mode 100644
index 03e7679..0000000
--- a/arch/arm/dts/imx8mm-phyboard-polis-rdk.dts
+++ /dev/null
@@ -1,460 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2022 PHYTEC Messtechnik GmbH
- * Author: Teresa Remmet <t.remmet@phytec.de>
- */
-
-/dts-v1/;
-
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/phy/phy-imx8-pcie.h>
-#include "imx8mm-phycore-som.dtsi"
-
-/ {
- model = "PHYTEC phyBOARD-Polis-i.MX8MM RDK";
- compatible = "phytec,imx8mm-phyboard-polis-rdk",
- "phytec,imx8mm-phycore-som", "fsl,imx8mm";
-
- chosen {
- stdout-path = &uart3;
- };
-
- bt_osc_32k: bt-lp-clock {
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- clock-output-names = "bt_osc_32k";
- #clock-cells = <0>;
- };
-
- can_osc_40m: can-clock {
- compatible = "fixed-clock";
- clock-frequency = <40000000>;
- clock-output-names = "can_osc_40m";
- #clock-cells = <0>;
- };
-
- fan {
- compatible = "gpio-fan";
- gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;
- gpio-fan,speed-map = <0 0
- 13000 1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_fan>;
- #cooling-cells = <2>;
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_leds>;
-
- led-0 {
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_DISK;
- gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "mmc2";
- };
-
- led-1 {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_DISK;
- gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "mmc1";
- };
-
- led-2 {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_CPU;
- gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- usdhc1_pwrseq: pwr-seq {
- compatible = "mmc-pwrseq-simple";
- post-power-on-delay-ms = <100>;
- power-off-delay-us = <60>;
- reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
- };
-
- reg_can_en: regulator-can-en {
- compatible = "regulator-fixed";
- gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_can_en>;
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3300000>;
- regulator-name = "CAN_EN";
- startup-delay-us = <20>;
- };
-
- reg_usb_otg1_vbus: regulator-usb-otg1 {
- compatible = "regulator-fixed";
- gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg1pwrgrp>;
- regulator-name = "usb_otg1_vbus";
- regulator-max-microvolt = <5000000>;
- regulator-min-microvolt = <5000000>;
- };
-
- reg_usdhc2_vmmc: regulator-usdhc2 {
- compatible = "regulator-fixed";
- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- off-on-delay-us = <20000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3300000>;
- regulator-name = "VSD_3V3";
- };
-
- reg_vcc_3v3: regulator-vcc-3v3 {
- compatible = "regulator-fixed";
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3300000>;
- regulator-name = "VCC_3V3";
- };
-};
-
-/* SPI - CAN MCP251XFD */
-&ecspi1 {
- cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi1>;
- status = "okay";
-
- can0: can@0 {
- compatible = "microchip,mcp251xfd";
- clocks = <&can_osc_40m>;
- interrupt-parent = <&gpio1>;
- interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_can_int>;
- reg = <0>;
- spi-max-frequency = <20000000>;
- xceiver-supply = <®_can_en>;
- };
-};
-
-&gpio1 {
- gpio-line-names = "nINT_ETHPHY", "LED_RED", "WDOG_INT", "X_RTC_INT",
- "", "", "", "RESET_ETHPHY",
- "CAN_nINT", "CAN_EN", "nENABLE_FLATLINK", "",
- "USB_OTG_VBUS_EN", "", "LED_GREEN", "LED_BLUE";
-};
-
-&gpio2 {
- gpio-line-names = "", "", "", "",
- "", "", "BT_REG_ON", "WL_REG_ON",
- "BT_DEV_WAKE", "BT_HOST_WAKE", "", "",
- "X_SD2_CD_B", "", "", "",
- "", "", "", "SD2_RESET_B";
-};
-
-&gpio4 {
- gpio-line-names = "", "", "", "",
- "", "", "", "",
- "FAN", "miniPCIe_nPERST", "", "",
- "COEX1", "COEX2";
-};
-
-&gpio5 {
- gpio-line-names = "", "", "", "",
- "", "", "", "",
- "", "ECSPI1_SS0";
-};
-
-&i2c4 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c4>;
-};
-
-/* PCIe */
-&pcie0 {
- assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
- <&clk IMX8MM_CLK_PCIE1_CTRL>;
- assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
- <&clk IMX8MM_SYS_PLL2_250M>;
- assigned-clock-rates = <10000000>, <250000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie>;
- reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>;
- status = "okay";
-};
-
-&pcie_phy {
- clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
- fsl,clkreq-unsupported;
- fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
- fsl,tx-deemph-gen1 = <0x2d>;
- fsl,tx-deemph-gen2 = <0xf>;
- status = "okay";
-};
-
-&rv3028 {
- trickle-resistor-ohms = <3000>;
-};
-
-&snvs_pwrkey {
- status = "okay";
-};
-
-/* UART - RS232/RS485 */
-&uart1 {
- assigned-clocks = <&clk IMX8MM_CLK_UART1>;
- assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- uart-has-rtscts;
- status = "okay";
-};
-
-/* UART - Sterling-LWB Bluetooth */
-&uart2 {
- assigned-clocks = <&clk IMX8MM_CLK_UART2>;
- assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
- fsl,dte-mode;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2_bt>;
- uart-has-rtscts;
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- clocks = <&bt_osc_32k>;
- clock-names = "lpo";
- device-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
- interrupt-names = "host-wakeup";
- interrupt-parent = <&gpio2>;
- interrupts = <9 IRQ_TYPE_EDGE_BOTH>;
- max-speed = <2000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_bt>;
- shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
- vddio-supply = <®_vcc_3v3>;
- };
-};
-
-/* UART - console */
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- status = "okay";
-};
-
-/* USB */
-&usbotg1 {
- adp-disable;
- dr_mode = "otg";
- over-current-active-low;
- samsung,picophy-pre-emp-curr-control = <3>;
- samsung,picophy-dc-vol-level-adjust = <7>;
- srp-disable;
- vbus-supply = <®_usb_otg1_vbus>;
- status = "okay";
-};
-
-&usbotg2 {
- disable-over-current;
- dr_mode = "host";
- samsung,picophy-pre-emp-curr-control = <3>;
- samsung,picophy-dc-vol-level-adjust = <7>;
- status = "okay";
-};
-
-/* SDIO - Sterling-LWB Wifi */
-&usdhc1 {
- assigned-clocks = <&clk IMX8MM_CLK_USDHC1>;
- assigned-clock-rates = <200000000>;
- bus-width = <4>;
- mmc-pwrseq = <&usdhc1_pwrseq>;
- non-removable;
- no-1-8-v;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- brcmf: wifi@1 {
- compatible = "brcm,bcm4329-fmac";
- reg = <1>;
- };
-};
-
-/* SD-Card */
-&usdhc2 {
- assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
- assigned-clock-rates = <200000000>;
- bus-width = <4>;
- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
- disable-wp;
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
- vmmc-supply = <®_usdhc2_vmmc>;
- vqmmc-supply = <®_nvcc_sd2>;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_bt: btgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x00
- MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x00
- MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x00
- >;
- };
-
- pinctrl_can_en: can-engrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00
- >;
- };
-
- pinctrl_can_int: can-intgrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00
- >;
- };
-
- pinctrl_ecspi1: ecspi1grp {
- fsl,pins = <
- MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x80
- MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x80
- MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x80
- MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00
- >;
- };
-
- pinctrl_fan: fan0grp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x16
- >;
- };
-
- pinctrl_i2c4: i2c4grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c2
- MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c2
- >;
- };
-
- pinctrl_leds: leds1grp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x16
- MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16
- MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16
- >;
- };
-
- pinctrl_pcie: pciegrp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x00
- MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12
- MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x12
- >;
- };
-
- pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x00
- MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x00
- MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x00
- MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x00
- >;
- };
-
- pinctrl_uart2_bt: uart2btgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x00
- MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x00
- MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x00
- MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x00
- >;
- };
-
- pinctrl_uart3: uart3grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x40
- MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x40
- >;
- };
-
- pinctrl_usbotg1pwrgrp: usbotg1pwrgrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00
- >;
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182
- MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6
- MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6
- MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6
- MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6
- MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6
- >;
- };
-
- pinctrl_usdhc2_gpio: usdhc2gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192
- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2
- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2
- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2
- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2
- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2
- >;
- };
-
- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
- >;
- };
-
- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
- >;
- };
-
- pinctrl_wlan: wlangrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x00
- >;
- };
-};
diff --git a/arch/arm/dts/imx8mm-phycore-som.dtsi b/arch/arm/dts/imx8mm-phycore-som.dtsi
deleted file mode 100644
index 92616bc..0000000
--- a/arch/arm/dts/imx8mm-phycore-som.dtsi
+++ /dev/null
@@ -1,440 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2022 PHYTEC Messtechnik GmbH
- * Author: Teresa Remmet <t.remmet@phytec.de>
- */
-
-#include "imx8mm.dtsi"
-#include <dt-bindings/net/ti-dp83867.h>
-
-/ {
- model = "PHYTEC phyCORE-i.MX8MM";
- compatible = "phytec,imx8mm-phycore-som", "fsl,imx8mm";
-
- aliases {
- rtc0 = &rv3028;
- rtc1 = &snvs_rtc;
- };
-
- memory@40000000 {
- device_type = "memory";
- reg = <0x0 0x40000000 0 0x80000000>;
- };
-
- reg_vdd_3v3_s: regulator-vdd-3v3-s {
- compatible = "regulator-fixed";
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3300000>;
- regulator-name = "VDD_3V3_S";
- };
-};
-
-&A53_0 {
- cpu-supply = <®_vdd_arm>;
-};
-
-&A53_1 {
- cpu-supply = <®_vdd_arm>;
-};
-
-&A53_2 {
- cpu-supply = <®_vdd_arm>;
-};
-
-&A53_3 {
- cpu-supply = <®_vdd_arm>;
-};
-
-&ddrc {
- operating-points-v2 = <&ddrc_opp_table>;
-
- ddrc_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- opp-25000000 {
- opp-hz = /bits/ 64 <25000000>;
- };
-
- opp-100000000 {
- opp-hz = /bits/ 64 <100000000>;
- };
-
- opp-750000000 {
- opp-hz = /bits/ 64 <750000000>;
- };
- };
-};
-
-/* Ethernet */
-&fec1 {
- fsl,magic-packet;
- phy-mode = "rgmii-id";
- phy-handle = <ðphy0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_fec1>;
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy0: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- enet-phy-lane-no-swap;
- ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- reg = <0>;
- reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
- reset-assert-us = <1000>;
- reset-deassert-us = <1000>;
- };
- };
-};
-
-/* SPI Flash */
-&flexspi {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexspi0>;
- status = "okay";
-
- som_flash: flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <80000000>;
- spi-rx-bus-width = <4>;
- spi-tx-bus-width = <1>;
- };
-};
-
-&gpio1 {
- gpio-line-names = "nINT_ETHPHY", "", "WDOG_INT", "X_RTC_INT",
- "", "", "", "RESET_ETHPHY",
- "", "", "nENABLE_FLATLINK";
-};
-
-/* I2C1 */
-&i2c1 {
- clock-frequency = <400000>;
- pinctrl-names = "default","gpio";
- pinctrl-0 = <&pinctrl_i2c1>;
- pinctrl-1 = <&pinctrl_i2c1_gpio>;
- scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-
- pmic@8 {
- compatible = "nxp,pf8121a";
- reg = <0x08>;
-
- regulators {
- reg_nvcc_sd1: ldo1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3300000>;
- regulator-name = "NVCC_SD1 (LDO1)";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- reg_nvcc_sd2: ldo2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <1800000>;
- regulator-name = "NVCC_SD2 (LDO2)";
- vselect-en;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- reg_vcc_enet: ldo3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <2500000>;
- regulator-min-microvolt = <1500000>;
- regulator-name = "VCC_ENET_2V5 (LDO3)";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- reg_vdda_1v8: ldo4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <1800000>;
- regulator-min-microvolt = <1500000>;
- regulator-name = "VDDA_1V8 (LDO4)";
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-min-microvolt = <1500000>;
- regulator-suspend-max-microvolt = <1500000>;
- };
- };
-
- reg_soc_vdda_phy: buck1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <900000>;
- regulator-min-microvolt = <400000>;
- regulator-name = "VDD_SOC_VDDA_PHY_0P8 (BUCK1)";
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-min-microvolt = <400000>;
- regulator-suspend-max-microvolt = <400000>;
- };
- };
-
- reg_vdd_gpu_dram: buck2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <1000000>;
- regulator-min-microvolt = <1000000>;
- regulator-name = "VDD_GPU_DRAM (BUCK2)";
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-max-microvolt = <1000000>;
- regulator-suspend-min-microvolt = <1000000>;
- };
- };
-
- reg_vdd_gpu: buck3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <1000000>;
- regulator-min-microvolt = <400000>;
- regulator-name = "VDD_VPU (BUCK3)";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- reg_vdd_mipi: buck4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <1050000>;
- regulator-min-microvolt = <900000>;
- regulator-name = "VDD_MIPI_0P9 (BUCK4)";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- reg_vdd_arm: buck5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <1050000>;
- regulator-min-microvolt = <400000>;
- regulator-name = "VDD_ARM (BUCK5)";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- reg_vdd_1v8: buck6 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <1800000>;
- regulator-min-microvolt = <1800000>;
- regulator-name = "VDD_1V8 (BUCK6)";
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-max-microvolt = <1800000>;
- regulator-suspend-min-microvolt = <1800000>;
- };
- };
-
- reg_nvcc_dram: buck7 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <1100000>;
- regulator-min-microvolt = <1100000>;
- regulator-name = "NVCC_DRAM_1P1V (BUCK7)";
- };
-
- reg_vsnvs: vsnvs {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <1800000>;
- regulator-min-microvolt = <1800000>;
- regulator-name = "NVCC_SNVS_1P8 (VSNVS)";
- };
- };
- };
-
- sn65dsi83: bridge@2d {
- compatible = "ti,sn65dsi83";
- enable-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sn65dsi83>;
- reg = <0x2d>;
- status = "disabled";
- };
-
- eeprom@51 {
- compatible = "atmel,24c32";
- pagesize = <32>;
- reg = <0x51>;
- vcc-supply = <®_vdd_3v3_s>;
- };
-
- rv3028: rtc@52 {
- compatible = "microcrystal,rv3028";
- interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpio1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_rtc>;
- reg = <0x52>;
- };
-};
-
-/* EMMC */
-&usdhc3 {
- assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
- assigned-clock-rates = <400000000>;
- bus-width = <8>;
- keep-power-in-suspend;
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc3>;
- pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
- non-removable;
- status = "okay";
-};
-
-/* Watchdog */
-&wdog1 {
- fsl,ext-reset-output;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdog>;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_fec1: fec1grp {
- fsl,pins = <
- MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x2
- MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x2
- MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90
- MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90
- MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90
- MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90
- MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90
- MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90
- MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x16
- MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x16
- MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x16
- MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x16
- MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x16
- MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x16
- MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x10
- >;
- };
-
- pinctrl_flexspi0: flexspi0grp {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
- MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
- MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
- MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
- MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
- MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c0
- MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c0
- >;
- };
-
- pinctrl_i2c1_gpio: i2c1gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1e0
- MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1e0
- >;
- };
-
- pinctrl_rtc: rtcgrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0
- >;
- };
-
- pinctrl_sn65dsi83: sn65dsi83grp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x0
- >;
- };
-
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
- >;
- };
-
- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
- >;
- };
-
- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
- >;
- };
-
- pinctrl_wdog: wdoggrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x26
- >;
- };
-};
diff --git a/arch/arm/dts/imx8mm-phygate-tauri-l.dts b/arch/arm/dts/imx8mm-phygate-tauri-l.dts
deleted file mode 100644
index 968f475..0000000
--- a/arch/arm/dts/imx8mm-phygate-tauri-l.dts
+++ /dev/null
@@ -1,489 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2023 PHYTEC Messtechnik GmbH
- */
-
-/dts-v1/;
-
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/leds/common.h>
-#include "imx8mm-phycore-som.dtsi"
-
-/ {
- model = "PHYTEC phyGATE-Tauri-L-iMX8MM";
- compatible = "phytec,imx8mm-phygate-tauri-l",
- "phytec,imx8mm-phycore-som", "fsl,imx8mm";
-
- chosen {
- stdout-path = &uart3;
- };
-
- can_osc_40m: clock-can {
- compatible = "fixed-clock";
- clock-frequency = <40000000>;
- clock-output-names = "can_osc_40m";
- #clock-cells = <0>;
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpiokeys>;
-
- key {
- gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
- label = "KEY-A";
- linux,code = <KEY_A>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_leds>;
-
- led-1 {
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "none";
- };
-
- led-2 {
- color = <LED_COLOR_ID_YELLOW>;
- gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "none";
- };
- };
-
- usdhc1_pwrseq: pwr-seq {
- compatible = "mmc-pwrseq-simple";
- post-power-on-delay-ms = <100>;
- power-off-delay-us = <60>;
- reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
- };
-
- reg_usb_hub_vbus: regulator-hub-otg1 {
- compatible = "regulator-fixed";
- gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbhubpwr>;
- regulator-name = "usb_hub_vbus";
- regulator-max-microvolt = <5000000>;
- regulator-min-microvolt = <5000000>;
- };
-
- reg_usb_otg1_vbus: regulator-usb-otg1 {
- compatible = "regulator-fixed";
- gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg1pwr>;
- regulator-name = "usb_otg1_vbus";
- regulator-max-microvolt = <5000000>;
- regulator-min-microvolt = <5000000>;
- };
-
- reg_usdhc2_vmmc: regulator-usdhc2 {
- compatible = "regulator-fixed";
- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- off-on-delay-us = <20000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3300000>;
- regulator-name = "VSD_3V3";
- };
-};
-
-&ecspi1 {
- cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>,
- <&gpio5 13 GPIO_ACTIVE_LOW>,
- <&gpio5 2 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- /* CAN MCP251XFD */
- can0: can@0 {
- compatible = "microchip,mcp251xfd";
- reg = <0>;
- clocks = <&can_osc_40m>;
- interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpio1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_can_int>;
- spi-max-frequency = <10000000>;
- };
-
- tpm: tpm@1 {
- compatible = "tcg,tpm_tis-spi";
- interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpio2>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_tpm>;
- reg = <1>;
- spi-max-frequency = <38000000>;
- };
-};
-
-&i2c2 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- pinctrl-1 = <&pinctrl_i2c2_gpio>;
- scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-
- temp_sense0: temperature-sensor@49 {
- compatible = "ti,tmp102";
- reg = <0x49>;
- interrupt-parent = <&gpio4>;
- interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_tempsense>;
- #thermal-sensor-cells = <1>;
- };
-};
-
-&i2c3 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- pinctrl-1 = <&pinctrl_i2c3_gpio>;
- scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-};
-
-&i2c4 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c4>;
- pinctrl-1 = <&pinctrl_i2c4_gpio>;
- scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-};
-
-/* PCIe */
-&pcie0 {
- assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
- <&clk IMX8MM_CLK_PCIE1_PHY>,
- <&clk IMX8MM_CLK_PCIE1_CTRL>;
- assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
- <&clk IMX8MM_SYS_PLL2_100M>,
- <&clk IMX8MM_SYS_PLL2_250M>;
- assigned-clock-rates = <10000000>, <100000000>, <250000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie>;
- reset-gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
- status = "okay";
-};
-
-&pwm1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm1>;
- status = "okay";
-};
-
-&pwm3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm3>;
- status = "okay";
-};
-
-&pwm4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm4>;
- status = "okay";
-};
-
-/* RTC */
-&rv3028 {
- trickle-resistor-ohms = <3000>;
-};
-
-&uart1 {
- assigned-clocks = <&clk IMX8MM_CLK_UART1>;
- assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- status = "okay";
-};
-
-/* UART2 - RS232 */
-&uart2 {
- assigned-clocks = <&clk IMX8MM_CLK_UART2>;
- assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- status = "okay";
-};
-
-/* UART - console */
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- status = "okay";
-};
-
-/* USB */
-&usbotg1 {
- adp-disable;
- dr_mode = "otg";
- over-current-active-low;
- samsung,picophy-pre-emp-curr-control = <3>;
- samsung,picophy-dc-vol-level-adjust = <7>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg1>;
- srp-disable;
- vbus-supply = <®_usb_otg1_vbus>;
- status = "okay";
-};
-
-&usbotg2 {
- disable-over-current;
- dr_mode = "host";
- samsung,picophy-pre-emp-curr-control = <3>;
- samsung,picophy-dc-vol-level-adjust = <7>;
- vbus-supply = <®_usb_hub_vbus>;
- status = "okay";
-};
-
-/* SD-Card */
-&usdhc2 {
- assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
- assigned-clock-rates = <200000000>;
- bus-width = <4>;
- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
- disable-wp;
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
- vmmc-supply = <®_usdhc2_vmmc>;
- vqmmc-supply = <®_nvcc_sd2>;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_can_int: can-intgrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00
- >;
- };
-
- pinctrl_ecspi1: ecspi1grp {
- fsl,pins = <
- MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
- MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
- MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
- >;
- };
-
- pinctrl_ecspi1_cs: ecspi1csgrp {
- fsl,pins = <
- MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00
- MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x00
- MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x00
- >;
- };
-
- pinctrl_gpiokeys: keygrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00
- >;
- };
-
- pinctrl_i2c2: i2c2grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c2
- MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c2
- >;
- };
-
- pinctrl_i2c2_gpio: i2c2gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1e0
- MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1e0
- >;
- };
-
-
- pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2
- MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2
- >;
- };
-
- pinctrl_i2c3_gpio: i2c3gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1e0
- MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1e0
- >;
- };
-
- pinctrl_i2c4: i2c4grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c2
- MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c2
- >;
- };
-
- pinctrl_i2c4_gpio: i2c4gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x1e0
- MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x1e0
- >;
- };
-
- pinctrl_leds: leds1grp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x00
- MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x00
- >;
- };
-
- pinctrl_pcie: pciegrp {
- fsl,pins = <
- /* COEX2 */
- MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x00
- /* COEX1 */
- MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12
- >;
- };
-
- pinctrl_pwm1: pwm1grp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x40
- >;
- };
-
- pinctrl_pwm3: pwm3grp {
- fsl,pins = <
- MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x40
- >;
- };
-
- pinctrl_pwm4: pwm4grp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT 0x40
- >;
- };
-
- pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40
- >;
- };
-
- pinctrl_tempsense: tempsensegrp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x00
- >;
- };
-
- pinctrl_tpm: tpmgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x140
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x00
- MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x00
- >;
- };
-
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x00
- MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x00
- >;
- };
-
- pinctrl_uart3: uart3grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
- MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
- >;
- };
-
- pinctrl_usbhubpwr: usbhubpwrgrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x00
- >;
- };
-
- pinctrl_usbotg1pwr: usbotg1pwrgrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00
- >;
- };
-
- pinctrl_usbotg1: usbotg1grp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x80
- >;
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182
- MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6
- MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6
- MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6
- MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6
- MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6
- >;
- };
-
- pinctrl_usdhc2_gpio: usdhc2gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192
- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2
- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2
- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2
- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2
- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2
- >;
- };
-
- pinctrl_usdhc2_100mhz: usdhc2100mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
- >;
- };
-
- pinctrl_usdhc2_200mhz: usdhc2200mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
- >;
- };
-};
diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi
index 6ab8f66..c02e11d 100644
--- a/arch/arm/dts/imx8mm-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-u-boot.dtsi
@@ -54,126 +54,151 @@
};
#endif
- nxp-imx8mimage {
- filename = "u-boot-spl-mkimage.bin";
- nxp,boot-from = "sd";
- nxp,rom-version = <1>;
+#ifdef CONFIG_IMX_HAB
+ nxp-imx8mcst@0 {
+ filename = "u-boot-spl-mkimage.signed.bin";
nxp,loader-address = <CONFIG_SPL_TEXT_BASE>;
+ nxp,unlock;
args; /* Needed by mkimage etype superclass */
+#endif
- section {
- align = <4>;
- align-size = <4>;
- filename = "u-boot-spl-ddr.bin";
- pad-byte = <0xff>;
+ binman_imx_spl: nxp-imx8mimage {
+ filename = "u-boot-spl-mkimage.bin";
+ nxp,boot-from = "sd";
+ nxp,rom-version = <1>;
+ nxp,loader-address = <CONFIG_SPL_TEXT_BASE>;
+ args; /* Needed by mkimage etype superclass */
- u-boot-spl {
- align-end = <4>;
- filename = "u-boot-spl.bin";
- };
+ section {
+ align = <4>;
+ align-size = <4>;
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
- ddr-1d-imem-fw {
- filename = "lpddr4_pmu_train_1d_imem.bin";
- align-end = <4>;
- type = "blob-ext";
- };
+ u-boot-spl {
+ align-end = <4>;
+ filename = "u-boot-spl.bin";
+ };
- ddr-1d-dmem-fw {
- filename = "lpddr4_pmu_train_1d_dmem.bin";
- align-end = <4>;
- type = "blob-ext";
- };
+ ddr-1d-imem-fw {
+ filename = "lpddr4_pmu_train_1d_imem.bin";
+ align-end = <4>;
+ type = "blob-ext";
+ };
- ddr-2d-imem-fw {
- filename = "lpddr4_pmu_train_2d_imem.bin";
- align-end = <4>;
- type = "blob-ext";
- };
+ ddr-1d-dmem-fw {
+ filename = "lpddr4_pmu_train_1d_dmem.bin";
+ align-end = <4>;
+ type = "blob-ext";
+ };
- ddr-2d-dmem-fw {
- filename = "lpddr4_pmu_train_2d_dmem.bin";
- align-end = <4>;
- type = "blob-ext";
+ ddr-2d-imem-fw {
+ filename = "lpddr4_pmu_train_2d_imem.bin";
+ align-end = <4>;
+ type = "blob-ext";
+ };
+
+ ddr-2d-dmem-fw {
+ filename = "lpddr4_pmu_train_2d_dmem.bin";
+ align-end = <4>;
+ type = "blob-ext";
+ };
};
};
+#ifdef CONFIG_IMX_HAB
};
- fit {
- description = "Configuration to load ATF before U-Boot";
-#ifndef CONFIG_IMX_HAB
- fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
-#endif
- fit,fdt-list = "of-list";
- #address-cells = <1>;
+ nxp-imx8mcst@1 {
+ filename = "u-boot-fit.signed.bin";
+ nxp,loader-address = <CONFIG_SPL_LOAD_FIT_ADDRESS>;
#ifdef CONFIG_FSPI_CONF_HEADER
offset = <0x58C00>;
#else
offset = <0x57c00>;
#endif
- images {
- uboot {
- arch = "arm64";
- compression = "none";
- description = "U-Boot (64-bit)";
- load = <CONFIG_TEXT_BASE>;
- type = "standalone";
+ args; /* Needed by mkimage etype superclass */
+#endif
- uboot-blob {
- filename = "u-boot-nodtb.bin";
- type = "blob-ext";
+ binman_imx_fit: fit {
+ description = "Configuration to load ATF before U-Boot";
+#ifndef CONFIG_IMX_HAB
+ fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
+#endif
+ fit,fdt-list = "of-list";
+ #address-cells = <1>;
+#ifdef CONFIG_FSPI_CONF_HEADER
+ offset = <0x58C00>;
+#else
+ offset = <0x57c00>;
+#endif
+
+ images {
+ uboot {
+ arch = "arm64";
+ compression = "none";
+ description = "U-Boot (64-bit)";
+ load = <CONFIG_TEXT_BASE>;
+ type = "standalone";
+
+ uboot-blob {
+ filename = "u-boot-nodtb.bin";
+ type = "blob-ext";
+ };
};
- };
#ifndef CONFIG_ARMV8_PSCI
- atf {
- arch = "arm64";
- compression = "none";
- description = "ARM Trusted Firmware";
- entry = <0x920000>;
- load = <0x920000>;
- type = "firmware";
+ atf {
+ arch = "arm64";
+ compression = "none";
+ description = "ARM Trusted Firmware";
+ entry = <0x920000>;
+ load = <0x920000>;
+ type = "firmware";
- atf-blob {
- filename = "bl31.bin";
- type = "atf-bl31";
+ atf-blob {
+ filename = "bl31.bin";
+ type = "atf-bl31";
+ };
};
- };
#endif
- binman_fip: fip {
- arch = "arm64";
- compression = "none";
- description = "Trusted Firmware FIP";
- load = <0x40310000>;
- type = "firmware";
- };
+ binman_fip: fip {
+ arch = "arm64";
+ compression = "none";
+ description = "Trusted Firmware FIP";
+ load = <0x40310000>;
+ type = "firmware";
+ };
- @fdt-SEQ {
- compression = "none";
- description = "NAME";
- type = "flat_dt";
+ @fdt-SEQ {
+ compression = "none";
+ description = "NAME";
+ type = "flat_dt";
- uboot-fdt-blob {
- filename = "u-boot.dtb";
- type = "blob-ext";
+ uboot-fdt-blob {
+ filename = "u-boot.dtb";
+ type = "blob-ext";
+ };
};
};
- };
- configurations {
- default = "@config-DEFAULT-SEQ";
+ configurations {
+ default = "@config-DEFAULT-SEQ";
- @config-SEQ {
- description = "NAME";
- fdt = "fdt-SEQ";
- firmware = "uboot";
+ @config-SEQ {
+ description = "NAME";
+ fdt = "fdt-SEQ";
+ firmware = "uboot";
#ifndef CONFIG_ARMV8_PSCI
- loadables = "atf";
+ loadables = "atf";
#endif
+ };
};
};
+#ifdef CONFIG_IMX_HAB
};
+#endif
};
};
diff --git a/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi
index 90183af..183de46 100644
--- a/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi
@@ -35,12 +35,8 @@
bootph-pre-ram;
};
-&binman {
- section {
- fit {
- offset = <0x5fc00>;
- };
- };
+&binman_imx_fit {
+ offset = <0x5fc00>;
};
&gpio1 {
diff --git a/arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi b/arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi
deleted file mode 100644
index c11895d..0000000
--- a/arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi
+++ /dev/null
@@ -1,426 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2021 Collabora Ltd.
- * Copyright 2021 BSH Hausgeraete GmbH
- */
-
-/dts-v1/;
-
-#include "imx8mn.dtsi"
-
-/ {
- chosen {
- stdout-path = &uart4;
- };
-
- fec_supply: fec-supply-en {
- compatible = "regulator-fixed";
- vin-supply = <&buck4_reg>;
- regulator-name = "tja1101_en";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- usdhc2_pwrseq: usdhc2-pwrseq {
- compatible = "mmc-pwrseq-simple";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc2_pwrseq>;
- reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
- };
-};
-
-&A53_0 {
- cpu-supply = <&buck2_reg>;
-};
-
-&A53_1 {
- cpu-supply = <&buck2_reg>;
-};
-
-&A53_2 {
- cpu-supply = <&buck2_reg>;
-};
-
-&A53_3 {
- cpu-supply = <&buck2_reg>;
-};
-
-&ecspi2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_espi2>;
- status = "okay";
-};
-
-&fec1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_fec1>;
- phy-mode = "rmii";
- phy-handle = <ðphy0>;
- phy-supply = <&fec_supply>;
- fsl,magic-packet;
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy0: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
- reset-assert-us = <20>;
- reset-deassert-us = <2000>;
- };
- };
-};
-
-&i2c1 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- status = "okay";
-
- bd71847: pmic@4b {
- compatible = "rohm,bd71847";
- reg = <0x4b>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pmic>;
- interrupt-parent = <&gpio1>;
- interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
- rohm,reset-snvs-powered;
-
- #clock-cells = <0>;
- clocks = <&osc_32k 0>;
- clock-output-names = "clk-32k-out";
-
- regulators {
- buck1_reg: BUCK1 {
- /* PMIC_BUCK1 - VDD_SOC */
- regulator-name = "buck1";
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1300000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <1250>;
- };
-
- buck2_reg: BUCK2 {
- /* PMIC_BUCK2 - VDD_ARM */
- regulator-name = "buck2";
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1300000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <1250>;
- };
-
- buck3_reg: BUCK3 {
- /* PMIC_BUCK5 - VDD_DRAM_VPU_GPU */
- regulator-name = "buck3";
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1350000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck4_reg: BUCK4 {
- /* PMIC_BUCK6 - VDD_3V3 */
- regulator-name = "buck4";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck5_reg: BUCK5 {
- /* PMIC_BUCK7 - VDD_1V8 */
- regulator-name = "buck5";
- regulator-min-microvolt = <1605000>;
- regulator-max-microvolt = <1995000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck6_reg: BUCK6 {
- /* PMIC_BUCK8 - NVCC_DRAM */
- regulator-name = "buck6";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1400000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo1_reg: LDO1 {
- /* PMIC_LDO1 - NVCC_SNVS_1V8 */
- regulator-name = "ldo1";
- regulator-min-microvolt = <1600000>;
- regulator-max-microvolt = <1900000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo2_reg: LDO2 {
- /* PMIC_LDO2 - VDD_SNVS_0V8 */
- regulator-name = "ldo2";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <900000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo3_reg: LDO3 {
- /* PMIC_LDO3 - VDDA_1V8 */
- regulator-name = "ldo3";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo4_reg: LDO4 {
- /* PMIC_LDO4 - VDD_MIPI_0V9 */
- regulator-name = "ldo4";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo6_reg: LDO6 {
- /* PMIC_LDO6 - VDD_MIPI_1V2 */
- regulator-name = "ldo6";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
-};
-
-&i2c3 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- status = "okay";
-};
-
-&i2c4 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c4>;
- status = "okay";
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- status = "okay";
-};
-
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- assigned-clocks = <&clk IMX8MN_CLK_UART3>;
- assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
- uart-has-rtscts;
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_bluetooth>;
- shutdown-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
- device-wakeup-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
- host-wakeup-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
- max-speed = <3000000>;
- };
-};
-
-/* Console */
-&uart4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart4>;
- status = "okay";
-};
-
-&usbotg1 {
- dr_mode = "peripheral";
- disable-over-current;
- status = "okay";
-};
-
-&usdhc2 {
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc2>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
- mmc-pwrseq = <&usdhc2_pwrseq>;
- bus-width = <4>;
- non-removable;
- status = "okay";
-
- brcmf: bcrmf@1 {
- compatible = "brcm,bcm4329-fmac";
- reg = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wlan>;
- interrupt-parent = <&gpio1>;
- interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "host-wake";
- };
-};
-
-&wdog1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdog>;
- fsl,ext-reset-output;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_bluetooth: bluetoothgrp {
- fsl,pins = <
- MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x044 /* BT_REG_ON */
- MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x046 /* BT_DEV_WAKE */
- MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x090 /* BT_HOST_WAKE */
- >;
- };
-
- pinctrl_espi2: espi2grp {
- fsl,pins = <
- MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x082
- MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x082
- MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x082
- MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x040
- >;
- };
-
- pinctrl_fec1: fec1grp {
- fsl,pins = <
- MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x002
- MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x002
- MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090
- MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x090
- MX8MN_IOMUXC_ENET_RXC_ENET1_RX_ER 0x090
- MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x016
- MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x016
- MX8MN_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x016
- MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x016
- MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x090
- MX8MN_IOMUXC_ENET_TXC_ENET1_TX_ER 0x016
- MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x150 /* RMII_INT - ENET_INT */
- MX8MN_IOMUXC_SD2_WP_GPIO2_IO20 0x150 /* RMII_EN - ENET_EN */
- MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x016 /* RMII_WAKE - GPIO_ENET_WAKE */
- MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x016 /* RMII_RESET - GPIO_ENET_RST */
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400000c2
- MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400000c2
- >;
- };
-
- pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400000c2
- MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400000c2
- >;
- };
-
- pinctrl_i2c4: i2c4grp {
- fsl,pins = <
- MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400000c2
- MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400000c2
- >;
- };
-
- pinctrl_pmic: pmicirq {
- fsl,pins = <
- MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x040
- >;
- };
-
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x040
- MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x040
- >;
- };
-
- pinctrl_uart3: uart3grp {
- fsl,pins = <
- MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x040
- MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x040
- MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x040
- MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x040
- >;
- };
-
- pinctrl_uart4: uart4grp {
- fsl,pins = <
- MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x040
- MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x040
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x090
- MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d0
- MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0d0
- MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0d0
- MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0d0
- MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0d0
- >;
- };
-
- pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
- fsl,pins = <
- MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x094
- MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d4
- MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0d4
- MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0d4
- MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0d4
- MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0d4
- >;
- };
-
- pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
- fsl,pins = <
- MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x096
- MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d6
- MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0d6
- MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0d6
- MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0d6
- MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0d6
- >;
- };
-
- pinctrl_usdhc2_pwrseq: usdhc2pwrseqgrp {
- fsl,pins = <
- MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x040 /* WL_REG_ON */
- >;
- };
-
- pinctrl_wdog: wdoggrp {
- fsl,pins = <
- MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x046
- >;
- };
-
- pinctrl_wlan: wlangrp {
- fsl,pins = <
- MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x0d6 /* GPIO_0 - WIFI_GPIO_0 */
- MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x0d6 /* GPIO_1 - WIFI_GPIO_1 */
- MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x0d6 /* BT_GPIO_5 - WIFI_GPIO_5 */
- MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x0d6 /* I2S_CLK - WIFI_GPIO_6 */
- >;
- };
-};
diff --git a/arch/arm/dts/imx8mn-bsh-smm-s2.dts b/arch/arm/dts/imx8mn-bsh-smm-s2.dts
deleted file mode 100644
index 33f9858..0000000
--- a/arch/arm/dts/imx8mn-bsh-smm-s2.dts
+++ /dev/null
@@ -1,48 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2021 Collabora Ltd.
- * Copyright 2021 BSH Hausgeraete GmbH
- */
-
-/dts-v1/;
-
-#include "imx8mn-bsh-smm-s2-common.dtsi"
-
-/ {
- model = "BSH SMM S2";
- compatible = "bsh,imx8mn-bsh-smm-s2", "fsl,imx8mn";
-
- memory@40000000 {
- device_type = "memory";
- reg = <0x0 0x40000000 0x0 0x10000000>;
- };
-};
-
-&gpmi {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpmi_nand>;
- nand-on-flash-bbt;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_gpmi_nand: gpmi-nand {
- fsl,pins = <
- MX8MN_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096
- MX8MN_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096
- MX8MN_IOMUXC_NAND_CLE_RAWNAND_CLE 0x00000096
- MX8MN_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x00000096
- MX8MN_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x00000096
- MX8MN_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x00000096
- MX8MN_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x00000096
- MX8MN_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x00000096
- MX8MN_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x00000096
- MX8MN_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x00000096
- MX8MN_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x00000096
- MX8MN_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x00000096
- MX8MN_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x00000056
- MX8MN_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x00000096
- MX8MN_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x00000096
- >;
- };
-};
diff --git a/arch/arm/dts/imx8mn-bsh-smm-s2pro.dts b/arch/arm/dts/imx8mn-bsh-smm-s2pro.dts
deleted file mode 100644
index fbbb336..0000000
--- a/arch/arm/dts/imx8mn-bsh-smm-s2pro.dts
+++ /dev/null
@@ -1,170 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2021 Collabora Ltd.
- * Copyright 2021 BSH Hausgeraete GmbH
- */
-
-/dts-v1/;
-
-#include "imx8mn-bsh-smm-s2-common.dtsi"
-#include <dt-bindings/sound/tlv320aic31xx.h>
-
-/ {
- model = "BSH SMM S2 PRO";
- compatible = "bsh,imx8mn-bsh-smm-s2pro", "fsl,imx8mn";
-
- memory@40000000 {
- device_type = "memory";
- reg = <0x0 0x40000000 0x0 0x20000000>;
- };
-
- sound-tlv320aic31xx {
- compatible = "fsl,imx-audio-tlv320aic31xx";
- model = "tlv320aic31xx-hifi";
- audio-cpu = <&sai3>;
- audio-codec = <&tlv320dac3101>;
- audio-asrc = <&easrc>;
- audio-routing =
- "Ext Spk", "SPL",
- "Ext Spk", "SPR";
- mclk-id = <PLL_CLKIN_BCLK>;
- };
-
- vdd_input: vdd_input {
- compatible = "regulator-fixed";
- regulator-name = "vdd_input";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-};
-
-&easrc {
- fsl,asrc-rate = <48000>;
- fsl,asrc-format = <10>;
- status = "okay";
-};
-
-&i2c2 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- status = "okay";
-
- tlv320dac3101: audio-codec@18 {
- compatible = "ti,tlv320dac3101";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_dac_rst>;
- reg = <0x18>;
- #sound-dai-cells = <0>;
- HPVDD-supply = <&buck4_reg>;
- SPRVDD-supply = <&vdd_input>;
- SPLVDD-supply = <&vdd_input>;
- AVDD-supply = <&buck4_reg>;
- IOVDD-supply = <&buck4_reg>;
- DVDD-supply = <&buck5_reg>;
- reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
- ai31xx-micbias-vg = <MICBIAS_AVDDV>;
- clocks = <&clk IMX8MN_CLK_SAI3_ROOT>;
- };
-};
-
-&sai3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sai3>;
- assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
- assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
- assigned-clock-rates = <24576000>;
- fsl,sai-mclk-direction-output;
- status = "okay";
-};
-
-/* eMMC */
-&usdhc1 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc1>;
- pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
- bus-width = <8>;
- non-removable;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_dac_rst: dacrstgrp {
- fsl,pins = <
- MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 /* DAC_RST */
- >;
- };
-
- pinctrl_espi2: espi2grp {
- fsl,pins = <
- MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x082
- MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x082
- MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x082
- MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x040
- >;
- };
-
- pinctrl_i2c2: i2c2grp {
- fsl,pins = <
- MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400000c3
- MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400000c3
- >;
- };
-
- pinctrl_sai3: sai3grp {
- fsl,pins = <
- MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
- MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
- MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
- >;
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000090
- MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d0
- MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0d0
- MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0d0
- MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0d0
- MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0d0
- MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0d0
- MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0d0
- MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0d0
- MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0d0
- MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x090
- >;
- };
-
- pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
- fsl,pins = <
- MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000094
- MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d4
- MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0d4
- MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0d4
- MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0d4
- MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0d4
- MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0d4
- MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0d4
- MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0d4
- MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0d4
- MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x094
- >;
- };
-
- pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
- fsl,pins = <
- MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000096
- MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d6
- MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0d6
- MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0d6
- MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0d6
- MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0d6
- MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0d6
- MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0d6
- MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0d6
- MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0d6
- MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x096
- >;
- };
-};
diff --git a/arch/arm/dts/imx8mn-u-boot.dtsi b/arch/arm/dts/imx8mn-u-boot.dtsi
index ba9967d..732191f 100644
--- a/arch/arm/dts/imx8mn-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-u-boot.dtsi
@@ -103,147 +103,172 @@
};
#endif
- nxp-imx8mimage {
- filename = "u-boot-spl-mkimage.bin";
- nxp,boot-from = "sd";
- nxp,rom-version = <2>;
+#ifdef CONFIG_IMX_HAB
+ nxp-imx8mcst@0 {
+ filename = "u-boot-spl-mkimage.signed.bin";
nxp,loader-address = <CONFIG_SPL_TEXT_BASE>;
+ nxp,unlock;
args; /* Needed by mkimage etype superclass */
+#endif
- section {
- filename = "u-boot-spl-ddr.bin";
- pad-byte = <0xff>;
- align-size = <4>;
- align = <4>;
+ binman_imx_spl: nxp-imx8mimage {
+ filename = "u-boot-spl-mkimage.bin";
+ nxp,boot-from = "sd";
+ nxp,rom-version = <2>;
+ nxp,loader-address = <CONFIG_SPL_TEXT_BASE>;
+ args; /* Needed by mkimage etype superclass */
- u-boot-spl {
- align-end = <4>;
- filename = "u-boot-spl.bin";
- };
+ section {
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+ align-size = <4>;
+ align = <4>;
- ddr-1d-imem-fw {
+ u-boot-spl {
+ align-end = <4>;
+ filename = "u-boot-spl.bin";
+ };
+
+ ddr-1d-imem-fw {
#ifdef CONFIG_IMX8M_LPDDR4
- filename = "lpddr4_pmu_train_1d_imem.bin";
+ filename = "lpddr4_pmu_train_1d_imem.bin";
#elif CONFIG_IMX8M_DDR4
- filename = "ddr4_imem_1d_201810.bin";
+ filename = "ddr4_imem_1d_201810.bin";
#else
- filename = "ddr3_imem_1d.bin";
+ filename = "ddr3_imem_1d.bin";
#endif
- type = "blob-ext";
- align-end = <4>;
- };
+ type = "blob-ext";
+ align-end = <4>;
+ };
- ddr-1d-dmem-fw {
+ ddr-1d-dmem-fw {
#ifdef CONFIG_IMX8M_LPDDR4
- filename = "lpddr4_pmu_train_1d_dmem.bin";
+ filename = "lpddr4_pmu_train_1d_dmem.bin";
#elif CONFIG_IMX8M_DDR4
- filename = "ddr4_dmem_1d_201810.bin";
+ filename = "ddr4_dmem_1d_201810.bin";
#else
- filename = "ddr3_dmem_1d.bin";
+ filename = "ddr3_dmem_1d.bin";
#endif
- type = "blob-ext";
- align-end = <4>;
- };
+ type = "blob-ext";
+ align-end = <4>;
+ };
#if defined(CONFIG_IMX8M_LPDDR4) || defined(CONFIG_IMX8M_DDR4)
- ddr-2d-imem-fw {
+ ddr-2d-imem-fw {
#ifdef CONFIG_IMX8M_LPDDR4
- filename = "lpddr4_pmu_train_2d_imem.bin";
+ filename = "lpddr4_pmu_train_2d_imem.bin";
#else
- filename = "ddr4_imem_2d_201810.bin";
+ filename = "ddr4_imem_2d_201810.bin";
#endif
- type = "blob-ext";
- align-end = <4>;
- };
+ type = "blob-ext";
+ align-end = <4>;
+ };
- ddr-2d-dmem-fw {
+ ddr-2d-dmem-fw {
#ifdef CONFIG_IMX8M_LPDDR4
- filename = "lpddr4_pmu_train_2d_dmem.bin";
+ filename = "lpddr4_pmu_train_2d_dmem.bin";
#else
- filename = "ddr4_dmem_2d_201810.bin";
+ filename = "ddr4_dmem_2d_201810.bin";
#endif
- type = "blob-ext";
- align-end = <4>;
- };
+ type = "blob-ext";
+ align-end = <4>;
+ };
#endif
+ };
};
+
+#ifdef CONFIG_IMX_HAB
};
- fit {
- description = "Configuration to load ATF before U-Boot";
-#ifndef CONFIG_IMX_HAB
- fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
-#endif
- fit,fdt-list = "of-list";
- #address-cells = <1>;
+ nxp-imx8mcst@1 {
+ filename = "u-boot-fit.signed.bin";
+ nxp,loader-address = <CONFIG_SPL_LOAD_FIT_ADDRESS>;
#ifdef CONFIG_FSPI_CONF_HEADER
offset = <0x59000>;
#else
offset = <0x58000>;
#endif
+ args; /* Needed by mkimage etype superclass */
+#endif
- images {
- uboot {
- arch = "arm64";
- compression = "none";
- description = "U-Boot (64-bit)";
- load = <CONFIG_TEXT_BASE>;
- type = "standalone";
+ binman_imx_fit: fit {
+ description = "Configuration to load ATF before U-Boot";
+#ifndef CONFIG_IMX_HAB
+ fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
+#endif
+ fit,fdt-list = "of-list";
+ #address-cells = <1>;
+#ifdef CONFIG_FSPI_CONF_HEADER
+ offset = <0x59000>;
+#else
+ offset = <0x58000>;
+#endif
- uboot-blob {
- filename = "u-boot-nodtb.bin";
- type = "blob-ext";
+ images {
+ uboot {
+ arch = "arm64";
+ compression = "none";
+ description = "U-Boot (64-bit)";
+ load = <CONFIG_TEXT_BASE>;
+ type = "standalone";
+
+ uboot-blob {
+ filename = "u-boot-nodtb.bin";
+ type = "blob-ext";
+ };
};
- };
#ifndef CONFIG_ARMV8_PSCI
- atf {
- arch = "arm64";
- compression = "none";
- description = "ARM Trusted Firmware";
- entry = <0x960000>;
- load = <0x960000>;
- type = "firmware";
+ atf {
+ arch = "arm64";
+ compression = "none";
+ description = "ARM Trusted Firmware";
+ entry = <0x960000>;
+ load = <0x960000>;
+ type = "firmware";
- atf-blob {
- filename = "bl31.bin";
- type = "atf-bl31";
+ atf-blob {
+ filename = "bl31.bin";
+ type = "atf-bl31";
+ };
};
- };
#endif
- binman_fip: fip {
- arch = "arm64";
- compression = "none";
- description = "Trusted Firmware FIP";
- load = <0x40310000>;
- type = "firmware";
- };
+ binman_fip: fip {
+ arch = "arm64";
+ compression = "none";
+ description = "Trusted Firmware FIP";
+ load = <0x40310000>;
+ type = "firmware";
+ };
- @fdt-SEQ {
- compression = "none";
- description = "NAME";
- type = "flat_dt";
+ @fdt-SEQ {
+ compression = "none";
+ description = "NAME";
+ type = "flat_dt";
- uboot-fdt-blob {
- filename = "u-boot.dtb";
- type = "blob-ext";
+ uboot-fdt-blob {
+ filename = "u-boot.dtb";
+ type = "blob-ext";
+ };
};
};
- };
- configurations {
- default = "@config-DEFAULT-SEQ";
+ configurations {
+ default = "@config-DEFAULT-SEQ";
- @config-SEQ {
- description = "NAME";
- fdt = "fdt-SEQ";
- firmware = "uboot";
+ @config-SEQ {
+ description = "NAME";
+ fdt = "fdt-SEQ";
+ firmware = "uboot";
#ifndef CONFIG_ARMV8_PSCI
- loadables = "atf";
+ loadables = "atf";
#endif
+ };
};
};
+#ifdef CONFIG_IMX_HAB
};
+#endif
};
};
diff --git a/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi b/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi
index ed183f8..3801465 100644
--- a/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi
@@ -32,12 +32,6 @@
bootph-pre-ram;
};
-&eqos {
- /delete-property/ assigned-clocks;
- /delete-property/ assigned-clock-parents;
- /delete-property/ assigned-clock-rates;
-};
-
ðphy0 {
reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
reset-assert-us = <15000>;
diff --git a/arch/arm/dts/imx8mp-dhcom-som-overlay-rev100.dts b/arch/arm/dts/imx8mp-dhcom-som-overlay-rev100.dts
index 0e5d329..b2154d5 100644
--- a/arch/arm/dts/imx8mp-dhcom-som-overlay-rev100.dts
+++ b/arch/arm/dts/imx8mp-dhcom-som-overlay-rev100.dts
@@ -35,6 +35,7 @@
ðphy0f { /* SMSC LAN8740Ai */
pinctrl-0 = <&pinctrl_ethphy0 &pinctrl_ioexp>;
reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
+ reg = <0>;
};
ðphy0g { /* Micrel KSZ9131RNXI */
@@ -42,6 +43,10 @@
reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
};
+ðphy1f { /* SMSC LAN8740Ai */
+ reg = <1>;
+};
+
&i2c3 {
adc@48 {
compatible = "ti,tla2024";
diff --git a/arch/arm/dts/imx8mp-dhcom-som.dtsi b/arch/arm/dts/imx8mp-dhcom-som.dtsi
index b504d36..f2d99d0 100644
--- a/arch/arm/dts/imx8mp-dhcom-som.dtsi
+++ b/arch/arm/dts/imx8mp-dhcom-som.dtsi
@@ -100,14 +100,14 @@
#size-cells = <0>;
/* Up to one of these two PHYs may be populated. */
- ethphy0f: ethernet-phy@0 { /* SMSC LAN8740Ai */
+ ethphy0f: ethernet-phy@1 { /* SMSC LAN8740Ai */
compatible = "ethernet-phy-id0007.c110",
"ethernet-phy-ieee802.3-c22";
interrupt-parent = <&gpio3>;
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&pinctrl_ethphy0>;
pinctrl-names = "default";
- reg = <0>;
+ reg = <1>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
reset-gpios = <&ioexp 4 GPIO_ACTIVE_LOW>;
@@ -146,14 +146,14 @@
#size-cells = <0>;
/* Up to one PHY may be populated. */
- ethphy1f: ethernet-phy@1 { /* SMSC LAN8740Ai */
+ ethphy1f: ethernet-phy@2 { /* SMSC LAN8740Ai */
compatible = "ethernet-phy-id0007.c110",
"ethernet-phy-ieee802.3-c22";
interrupt-parent = <&gpio4>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&pinctrl_ethphy1>;
pinctrl-names = "default";
- reg = <1>;
+ reg = <2>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi b/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi
index cb37e28..c065fb8 100644
--- a/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi
@@ -135,73 +135,69 @@
bootph-pre-ram;
};
-&binman {
- section {
- fit {
- images {
- fdt-dto-imx8mp-dhcom-som-overlay-eth1xfast {
- description = "imx8mp-dhcom-som-overlay-eth1xfast";
- type = "flat_dt";
- compression = "none";
+&binman_imx_fit {
+ images {
+ fdt-dto-imx8mp-dhcom-som-overlay-eth1xfast {
+ description = "imx8mp-dhcom-som-overlay-eth1xfast";
+ type = "flat_dt";
+ compression = "none";
- blob-ext {
- filename = "imx8mp-dhcom-som-overlay-eth1xfast.dtbo";
- };
- };
+ blob-ext {
+ filename = "imx8mp-dhcom-som-overlay-eth1xfast.dtbo";
+ };
+ };
- fdt-dto-imx8mp-dhcom-som-overlay-eth2xfast {
- description = "imx8mp-dhcom-som-overlay-eth2xfast";
- type = "flat_dt";
- compression = "none";
+ fdt-dto-imx8mp-dhcom-som-overlay-eth2xfast {
+ description = "imx8mp-dhcom-som-overlay-eth2xfast";
+ type = "flat_dt";
+ compression = "none";
- blob-ext {
- filename = "imx8mp-dhcom-som-overlay-eth2xfast.dtbo";
- };
- };
+ blob-ext {
+ filename = "imx8mp-dhcom-som-overlay-eth2xfast.dtbo";
+ };
+ };
- fdt-dto-imx8mp-dhcom-pdk-overlay-eth2xfast {
- description = "imx8mp-dhcom-pdk-overlay-eth2xfast";
- type = "flat_dt";
- compression = "none";
+ fdt-dto-imx8mp-dhcom-pdk-overlay-eth2xfast {
+ description = "imx8mp-dhcom-pdk-overlay-eth2xfast";
+ type = "flat_dt";
+ compression = "none";
- blob-ext {
- filename = "imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo";
- };
- };
+ blob-ext {
+ filename = "imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo";
+ };
+ };
- fdt-dto-imx8mp-dhcom-som-overlay-rev100 {
- description = "imx8mp-dhcom-som-overlay-rev100";
- type = "flat_dt";
- compression = "none";
+ fdt-dto-imx8mp-dhcom-som-overlay-rev100 {
+ description = "imx8mp-dhcom-som-overlay-rev100";
+ type = "flat_dt";
+ compression = "none";
- blob-ext {
- filename = "imx8mp-dhcom-som-overlay-rev100.dtbo";
- };
- };
+ blob-ext {
+ filename = "imx8mp-dhcom-som-overlay-rev100.dtbo";
+ };
+ };
- fdt-dto-imx8mp-dhcom-pdk3-overlay-rev100 {
- description = "imx8mp-dhcom-pdk3-overlay-rev100";
- type = "flat_dt";
- compression = "none";
+ fdt-dto-imx8mp-dhcom-pdk3-overlay-rev100 {
+ description = "imx8mp-dhcom-pdk3-overlay-rev100";
+ type = "flat_dt";
+ compression = "none";
- blob-ext {
- filename = "imx8mp-dhcom-pdk3-overlay-rev100.dtbo";
- };
- };
+ blob-ext {
+ filename = "imx8mp-dhcom-pdk3-overlay-rev100.dtbo";
};
+ };
+ };
- configurations {
- default = "@config-DEFAULT-SEQ";
+ configurations {
+ default = "@config-DEFAULT-SEQ";
- @config-SEQ {
- fdt = "fdt-1",
- "fdt-dto-imx8mp-dhcom-som-overlay-eth1xfast",
- "fdt-dto-imx8mp-dhcom-som-overlay-eth2xfast",
- "fdt-dto-imx8mp-dhcom-pdk-overlay-eth2xfast",
- "fdt-dto-imx8mp-dhcom-som-overlay-rev100",
- "fdt-dto-imx8mp-dhcom-pdk3-overlay-rev100";
- };
- };
+ @config-SEQ {
+ fdt = "fdt-1",
+ "fdt-dto-imx8mp-dhcom-som-overlay-eth1xfast",
+ "fdt-dto-imx8mp-dhcom-som-overlay-eth2xfast",
+ "fdt-dto-imx8mp-dhcom-pdk-overlay-eth2xfast",
+ "fdt-dto-imx8mp-dhcom-som-overlay-rev100",
+ "fdt-dto-imx8mp-dhcom-pdk3-overlay-rev100";
};
};
};
diff --git a/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts b/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts
deleted file mode 100644
index c8640ca..0000000
--- a/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts
+++ /dev/null
@@ -1,361 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2020 PHYTEC Messtechnik GmbH
- * Author: Teresa Remmet <t.remmet@phytec.de>
- */
-
-/dts-v1/;
-
-#include <dt-bindings/leds/leds-pca9532.h>
-#include <dt-bindings/pwm/pwm.h>
-#include "imx8mp-phycore-som.dtsi"
-
-/ {
- model = "PHYTEC phyBOARD-Pollux i.MX8MP";
- compatible = "phytec,imx8mp-phyboard-pollux-rdk",
- "phytec,imx8mp-phycore-som", "fsl,imx8mp";
-
- chosen {
- stdout-path = &uart1;
- };
-
- reg_can1_stby: regulator-can1-stby {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan1_reg>;
- gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3300000>;
- regulator-name = "can1-stby";
- };
-
- reg_can2_stby: regulator-can2-stby {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan2_reg>;
- gpio = <&gpio3 21 GPIO_ACTIVE_LOW>;
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3300000>;
- regulator-name = "can2-stby";
- };
-
- reg_usb1_vbus: regulator-usb1-vbus {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1_vbus>;
- gpio = <&gpio1 12 GPIO_ACTIVE_LOW>;
- regulator-max-microvolt = <5000000>;
- regulator-min-microvolt = <5000000>;
- regulator-name = "usb1_host_vbus";
- };
-
- reg_usdhc2_vmmc: regulator-usdhc2 {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
- regulator-name = "VSD_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- startup-delay-us = <100>;
- off-on-delay-us = <12000>;
- };
-};
-
-&eqos {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_eqos>;
- phy-mode = "rgmii-id";
- phy-handle = <ðphy0>;
- status = "okay";
-
- mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy0: ethernet-phy@1 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0x1>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
- ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
- enet-phy-lane-no-swap;
- };
- };
-};
-
-/* CAN FD */
-&flexcan1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan1>;
- xceiver-supply = <®_can1_stby>;
- status = "okay";
-};
-
-&flexcan2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan2>;
- xceiver-supply = <®_can2_stby>;
- status = "okay";
-};
-
-&i2c2 {
- clock-frequency = <400000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c2>;
- pinctrl-1 = <&pinctrl_i2c2_gpio>;
- sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-
- eeprom@51 {
- compatible = "atmel,24c02";
- reg = <0x51>;
- pagesize = <16>;
- };
-
- leds@62 {
- compatible = "nxp,pca9533";
- reg = <0x62>;
-
- led-1 {
- type = <PCA9532_TYPE_LED>;
- };
-
- led-2 {
- type = <PCA9532_TYPE_LED>;
- };
-
- led-3 {
- type = <PCA9532_TYPE_LED>;
- };
- };
-};
-
-&snvs_pwrkey {
- status = "okay";
-};
-
-/* debug console */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- status = "okay";
-};
-
-/* USB1 Host mode Type-A */
-&usb3_phy0 {
- vbus-supply = <®_usb1_vbus>;
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-};
-
-&usb_dwc3_0 {
- dr_mode = "host";
- status = "okay";
-};
-
-/* USB2 4-port USB3.0 HUB */
-&usb3_phy1 {
- status = "okay";
-};
-
-&usb3_1 {
- fsl,permanently-attached;
- fsl,disable-port-power-control;
- status = "okay";
-};
-
-&usb_dwc3_1 {
- dr_mode = "host";
- status = "okay";
-};
-
-/* RS232/RS485 */
-&uart2 {
- assigned-clocks = <&clk IMX8MP_CLK_UART2>;
- assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- uart-has-rtscts;
- status = "okay";
-};
-
-/* SD-Card */
-&usdhc2 {
- assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
- assigned-clock-rates = <200000000>;
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_pins>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_pins>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_pins>;
- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
- vmmc-supply = <®_usdhc2_vmmc>;
- bus-width = <4>;
- status = "okay";
-};
-
-&gpio1 {
- gpio-line-names = "", "", "X_PMIC_WDOG_B", "",
- "PMIC_SD_VSEL", "", "", "", "", "",
- "", "", "USB1_OTG_PWR", "", "", "X_nETHPHY_INT";
-};
-
-&gpio2 {
- gpio-line-names = "", "", "", "",
- "", "", "", "", "", "",
- "", "", "X_SD2_CD_B", "", "", "",
- "", "", "", "SD2_RESET_B";
-};
-
-&gpio3 {
- gpio-line-names = "", "", "", "",
- "", "", "", "", "", "",
- "", "", "", "", "", "",
- "", "", "", "", "nCAN1_EN", "nCAN2_EN";
-};
-
-&gpio4 {
- gpio-line-names = "", "", "", "",
- "", "", "", "", "", "",
- "", "", "", "", "", "",
- "", "", "X_PMIC_IRQ_B", "", "nENET0_INT_PWDN";
-};
-
-&iomuxc {
- pinctrl_eqos: eqosgrp {
- fsl,pins = <
- MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
- MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
- MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
- MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
- MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
- MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
- MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
- MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
- MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
- MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
- MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
- MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
- MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
- MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
- MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10
- >;
- };
-
- pinctrl_flexcan1: flexcan1grp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154
- MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154
- >;
- };
-
- pinctrl_flexcan2: flexcan2grp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
- MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
- >;
- };
-
- pinctrl_flexcan1_reg: flexcan1reggrp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x154
- >;
- };
-
- pinctrl_flexcan2_reg: flexcan2reggrp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x154
- >;
- };
-
- pinctrl_i2c2: i2c2grp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
- MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
- >;
- };
-
- pinctrl_i2c2_gpio: i2c2gpiogrp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e2
- MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e2
- >;
- };
-
- pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x40
- MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x40
- >;
- };
-
- pinctrl_usb1_vbus: usb1vbusgrp {
- fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x10
- >;
- };
-
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
- MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
- MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 0x140
- MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x140
- >;
- };
-
- pinctrl_usdhc2_pins: usdhc2-gpiogrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
- >;
- };
-
- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
- >;
- };
-
- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
- >;
- };
-};
diff --git a/arch/arm/dts/imx8mp-phycore-som.dtsi b/arch/arm/dts/imx8mp-phycore-som.dtsi
deleted file mode 100644
index 79b290a..0000000
--- a/arch/arm/dts/imx8mp-phycore-som.dtsi
+++ /dev/null
@@ -1,323 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2020 PHYTEC Messtechnik GmbH
- * Author: Teresa Remmet <t.remmet@phytec.de>
- */
-
-#include <dt-bindings/net/ti-dp83867.h>
-#include "imx8mp.dtsi"
-
-/ {
- model = "PHYTEC phyCORE-i.MX8MP";
- compatible = "phytec,imx8mp-phycore-som", "fsl,imx8mp";
-
- aliases {
- rtc0 = &rv3028;
- rtc1 = &snvs_rtc;
- };
-
- memory@40000000 {
- device_type = "memory";
- reg = <0x0 0x40000000 0 0x80000000>;
- };
-};
-
-&A53_0 {
- cpu-supply = <&buck2>;
-};
-
-&A53_1 {
- cpu-supply = <&buck2>;
-};
-
-&A53_2 {
- cpu-supply = <&buck2>;
-};
-
-&A53_3 {
- cpu-supply = <&buck2>;
-};
-
-/* ethernet 1 */
-&fec {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_fec>;
- phy-mode = "rgmii-id";
- phy-handle = <ðphy1>;
- fsl,magic-packet;
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy1: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- interrupt-parent = <&gpio1>;
- interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
- ti,min-output-impedance;
- enet-phy-lane-no-swap;
- };
- };
-};
-
-&flexspi {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexspi0>;
- status = "okay";
-
- som_flash: flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <80000000>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <4>;
- };
-};
-
-&i2c1 {
- clock-frequency = <400000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c1>;
- pinctrl-1 = <&pinctrl_i2c1_gpio>;
- sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-
- pmic: pmic@25 {
- reg = <0x25>;
- compatible = "nxp,pca9450c";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pmic>;
- interrupt-parent = <&gpio4>;
- interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
-
- regulators {
- buck1: BUCK1 {
- regulator-compatible = "BUCK1";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <2187500>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <3125>;
- };
-
- buck2: BUCK2 {
- regulator-compatible = "BUCK2";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <2187500>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <3125>;
- nxp,dvs-run-voltage = <950000>;
- nxp,dvs-standby-voltage = <850000>;
- };
-
- buck4: BUCK4 {
- regulator-compatible = "BUCK4";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <3400000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck5: BUCK5 {
- regulator-compatible = "BUCK5";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <3400000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck6: BUCK6 {
- regulator-compatible = "BUCK6";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <3400000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo1: LDO1 {
- regulator-compatible = "LDO1";
- regulator-min-microvolt = <1600000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo2: LDO2 {
- regulator-compatible = "LDO2";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1150000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo3: LDO3 {
- regulator-compatible = "LDO3";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo4: LDO4 {
- regulator-compatible = "LDO4";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <3300000>;
- };
-
- ldo5: LDO5 {
- regulator-compatible = "LDO5";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
-
- eeprom@51 {
- compatible = "atmel,24c32";
- reg = <0x51>;
- pagesize = <32>;
- };
-
- rv3028: rtc@52 {
- compatible = "microcrystal,rv3028";
- reg = <0x52>;
- trickle-resistor-ohms = <3000>;
- };
-};
-
-/* eMMC */
-&usdhc3 {
- assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>;
- assigned-clock-rates = <400000000>;
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc3>;
- pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
- bus-width = <8>;
- non-removable;
- status = "okay";
-};
-
-&wdog1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdog>;
- fsl,ext-reset-output;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_fec: fecgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
- MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
- MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
- MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
- MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
- MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
- MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
- MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
- MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12
- MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12
- MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x14
- MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x14
- MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x14
- MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14
- MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x11
- >;
- };
-
- pinctrl_flexspi0: flexspi0grp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
- MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
- MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
- MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
- MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
- MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
- MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
- >;
- };
-
- pinctrl_i2c1_gpio: i2c1gpiogrp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1e3
- MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1e3
- >;
- };
-
- pinctrl_pmic: pmicirqgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x141
- >;
- };
-
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
- MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
- MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
- MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
- MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
- MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
- MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
- MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
- >;
- };
-
- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
- MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
- MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
- MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
- MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
- MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
- MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
- MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
- >;
- };
-
- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
- MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
- MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2
- MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2
- MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2
- MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2
- MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2
- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2
- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2
- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2
- MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
- >;
- };
-
- pinctrl_wdog: wdoggrp {
- fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xe6
- >;
- };
-};
diff --git a/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi b/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi
index aff5dcf..21eff6d 100644
--- a/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi
@@ -135,21 +135,17 @@
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
};
-&binman {
- section {
- fit {
- images {
- fip {
- description = "Trusted Firmware FIP";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- load = <0x40310000>;
+&binman_imx_fit {
+ images {
+ fip {
+ description = "Trusted Firmware FIP";
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <0x40310000>;
- fip_blob: blob-ext{
- filename = "fip.bin";
- };
- };
+ fip_blob: blob-ext{
+ filename = "fip.bin";
};
};
};
diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi
index c4c1a17..f2655a4 100644
--- a/arch/arm/dts/imx8mp-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-u-boot.dtsi
@@ -86,110 +86,130 @@
section {
pad-byte = <0x00>;
- nxp-imx8mimage {
- filename = "u-boot-spl-mkimage.bin";
- nxp,boot-from = "sd";
- nxp,rom-version = <2>;
+#ifdef CONFIG_IMX_HAB
+ nxp-imx8mcst@0 {
+ filename = "u-boot-spl-mkimage.signed.bin";
nxp,loader-address = <CONFIG_SPL_TEXT_BASE>;
+ nxp,unlock;
args; /* Needed by mkimage etype superclass */
+#endif
- section {
- filename = "u-boot-spl-ddr.bin";
- pad-byte = <0xff>;
- align-size = <4>;
- align = <4>;
+ binman_imx_spl: nxp-imx8mimage {
+ filename = "u-boot-spl-mkimage.bin";
+ nxp,boot-from = "sd";
+ nxp,rom-version = <2>;
+ nxp,loader-address = <CONFIG_SPL_TEXT_BASE>;
+ args; /* Needed by mkimage etype superclass */
- u-boot-spl {
- align-end = <4>;
- };
+ section {
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+ align-size = <4>;
+ align = <4>;
- ddr-1d-imem-fw {
- filename = "lpddr4_pmu_train_1d_imem_202006.bin";
- type = "blob-ext";
- align-end = <4>;
- };
+ u-boot-spl {
+ align-end = <4>;
+ };
- ddr-1d-dmem-fw {
- filename = "lpddr4_pmu_train_1d_dmem_202006.bin";
- type = "blob-ext";
- align-end = <4>;
- };
+ ddr-1d-imem-fw {
+ filename = "lpddr4_pmu_train_1d_imem_202006.bin";
+ type = "blob-ext";
+ align-end = <4>;
+ };
- ddr-2d-imem-fw {
- filename = "lpddr4_pmu_train_2d_imem_202006.bin";
- type = "blob-ext";
- align-end = <4>;
- };
+ ddr-1d-dmem-fw {
+ filename = "lpddr4_pmu_train_1d_dmem_202006.bin";
+ type = "blob-ext";
+ align-end = <4>;
+ };
- ddr-2d-dmem-fw {
- filename = "lpddr4_pmu_train_2d_dmem_202006.bin";
- type = "blob-ext";
- align-end = <4>;
+ ddr-2d-imem-fw {
+ filename = "lpddr4_pmu_train_2d_imem_202006.bin";
+ type = "blob-ext";
+ align-end = <4>;
+ };
+
+ ddr-2d-dmem-fw {
+ filename = "lpddr4_pmu_train_2d_dmem_202006.bin";
+ type = "blob-ext";
+ align-end = <4>;
+ };
};
};
+#ifdef CONFIG_IMX_HAB
};
- fit {
- description = "Configuration to load ATF before U-Boot";
+ nxp-imx8mcst@1 {
+ filename = "u-boot-fit.signed.bin";
+ nxp,loader-address = <CONFIG_SPL_LOAD_FIT_ADDRESS>;
+ offset = <0x58000>;
+ args; /* Needed by mkimage etype superclass */
+#endif
+
+ binman_imx_fit: fit {
+ description = "Configuration to load ATF before U-Boot";
#ifndef CONFIG_IMX_HAB
- fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
+ fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
#endif
- fit,fdt-list = "of-list";
- #address-cells = <1>;
- offset = <0x58000>;
+ fit,fdt-list = "of-list";
+ #address-cells = <1>;
+ offset = <0x58000>;
- images {
- uboot {
- description = "U-Boot (64-bit)";
- type = "standalone";
- arch = "arm64";
- compression = "none";
- load = <CONFIG_TEXT_BASE>;
+ images {
+ uboot {
+ description = "U-Boot (64-bit)";
+ type = "standalone";
+ arch = "arm64";
+ compression = "none";
+ load = <CONFIG_TEXT_BASE>;
- uboot_blob: blob-ext {
- filename = "u-boot-nodtb.bin";
+ uboot_blob: blob-ext {
+ filename = "u-boot-nodtb.bin";
+ };
};
- };
#ifndef CONFIG_ARMV8_PSCI
- atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- load = <0x970000>;
- entry = <0x970000>;
+ atf {
+ description = "ARM Trusted Firmware";
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <0x970000>;
+ entry = <0x970000>;
- atf_blob: atf-blob {
- filename = "bl31.bin";
- type = "atf-bl31";
+ atf_blob: atf-blob {
+ filename = "bl31.bin";
+ type = "atf-bl31";
+ };
};
- };
#endif
- @fdt-SEQ {
- description = "NAME";
- type = "flat_dt";
- compression = "none";
+ @fdt-SEQ {
+ description = "NAME";
+ type = "flat_dt";
+ compression = "none";
- blob-ext {
- filename = "u-boot.dtb";
+ blob-ext {
+ filename = "u-boot.dtb";
+ };
};
};
- };
- configurations {
- default = "@config-DEFAULT-SEQ";
+ configurations {
+ default = "@config-DEFAULT-SEQ";
- @config-SEQ {
- description = "NAME";
- fdt = "fdt-SEQ";
- firmware = "uboot";
+ @config-SEQ {
+ description = "NAME";
+ fdt = "fdt-SEQ";
+ firmware = "uboot";
#ifndef CONFIG_ARMV8_PSCI
- loadables = "atf";
+ loadables = "atf";
#endif
+ };
};
};
+#ifdef CONFIG_IMX_HAB
};
+#endif
};
};
diff --git a/arch/arm/dts/imx8mp-venice-gw702x-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-gw702x-u-boot.dtsi
index b9e3db7..98f71c7 100644
--- a/arch/arm/dts/imx8mp-venice-gw702x-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-venice-gw702x-u-boot.dtsi
@@ -4,9 +4,3 @@
*/
#include "imx8mp-venice-u-boot.dtsi"
-
-&eqos {
- /delete-property/ assigned-clocks;
- /delete-property/ assigned-clock-parents;
- /delete-property/ assigned-clock-rates;
-};
diff --git a/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi
index 240fbc1..a90794d 100644
--- a/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi
@@ -243,3 +243,8 @@
&wdog1 {
bootph-pre-ram;
};
+
+/* gpio-usb-con not supported yet in U-Boot so make this a host for now */
+&usb_dwc3_0 {
+ dr_mode = "host";
+};
diff --git a/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi b/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi
index 1a4568d..98da015 100644
--- a/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi
@@ -10,14 +10,10 @@
bootph-pre-ram;
};
-&binman {
+&binman_imx_spl {
section {
- nxp-imx8mimage {
- section {
- signed-hdmi-imx8m {
- filename = "signed_dp_imx8m.bin";
- };
- };
+ signed-hdmi-imx8m {
+ filename = "signed_dp_imx8m.bin";
};
};
};
diff --git a/arch/arm/dts/imx8mq-u-boot.dtsi b/arch/arm/dts/imx8mq-u-boot.dtsi
index 48dbe94..e1cd6f8 100644
--- a/arch/arm/dts/imx8mq-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-u-boot.dtsi
@@ -38,116 +38,136 @@
section {
pad-byte = <0x00>;
- nxp-imx8mimage {
- filename = "u-boot-spl-mkimage.bin";
- nxp,boot-from = "sd";
- nxp,rom-version = <1>;
+#ifdef CONFIG_IMX_HAB
+ nxp-imx8mcst@0 {
+ filename = "u-boot-spl-mkimage.signed.bin";
nxp,loader-address = <CONFIG_SPL_TEXT_BASE>;
+ nxp,unlock;
args; /* Needed by mkimage etype superclass */
+#endif
- section {
- align = <4>;
- align-size = <4>;
- filename = "u-boot-spl-ddr.bin";
- pad-byte = <0xff>;
+ binman_imx_spl: nxp-imx8mimage {
+ filename = "u-boot-spl-mkimage.bin";
+ nxp,boot-from = "sd";
+ nxp,rom-version = <1>;
+ nxp,loader-address = <CONFIG_SPL_TEXT_BASE>;
+ args; /* Needed by mkimage etype superclass */
- u-boot-spl {
- align-end = <4>;
- filename = "u-boot-spl.bin";
- };
+ section {
+ align = <4>;
+ align-size = <4>;
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
- ddr-1d-imem-fw {
- filename = "lpddr4_pmu_train_1d_imem.bin";
- align-end = <4>;
- type = "blob-ext";
- };
+ u-boot-spl {
+ align-end = <4>;
+ filename = "u-boot-spl.bin";
+ };
- ddr-1d-dmem-fw {
- filename = "lpddr4_pmu_train_1d_dmem.bin";
- align-end = <4>;
- type = "blob-ext";
- };
+ ddr-1d-imem-fw {
+ filename = "lpddr4_pmu_train_1d_imem.bin";
+ align-end = <4>;
+ type = "blob-ext";
+ };
- ddr-2d-imem-fw {
- filename = "lpddr4_pmu_train_2d_imem.bin";
- align-end = <4>;
- type = "blob-ext";
- };
+ ddr-1d-dmem-fw {
+ filename = "lpddr4_pmu_train_1d_dmem.bin";
+ align-end = <4>;
+ type = "blob-ext";
+ };
- ddr-2d-dmem-fw {
- filename = "lpddr4_pmu_train_2d_dmem.bin";
- align-end = <4>;
- type = "blob-ext";
- };
+ ddr-2d-imem-fw {
+ filename = "lpddr4_pmu_train_2d_imem.bin";
+ align-end = <4>;
+ type = "blob-ext";
+ };
- signed-hdmi-imx8m {
- filename = "signed_hdmi_imx8m.bin";
- type = "blob-ext";
+ ddr-2d-dmem-fw {
+ filename = "lpddr4_pmu_train_2d_dmem.bin";
+ align-end = <4>;
+ type = "blob-ext";
+ };
+
+ signed-hdmi-imx8m {
+ filename = "signed_hdmi_imx8m.bin";
+ type = "blob-ext";
+ };
};
};
+#ifdef CONFIG_IMX_HAB
};
- fit {
- description = "Configuration to load ATF before U-Boot";
+ nxp-imx8mcst@1 {
+ filename = "u-boot-fit.signed.bin";
+ nxp,loader-address = <CONFIG_SPL_LOAD_FIT_ADDRESS>;
+ offset = <0x58000>;
+ args; /* Needed by mkimage etype superclass */
+#endif
+
+ binman_imx_fit: fit {
+ description = "Configuration to load ATF before U-Boot";
#ifndef CONFIG_IMX_HAB
- fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
+ fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
#endif
- #address-cells = <1>;
+ #address-cells = <1>;
- images {
- uboot {
- arch = "arm64";
- compression = "none";
- description = "U-Boot (64-bit)";
- load = <CONFIG_TEXT_BASE>;
- type = "standalone";
+ images {
+ uboot {
+ arch = "arm64";
+ compression = "none";
+ description = "U-Boot (64-bit)";
+ load = <CONFIG_TEXT_BASE>;
+ type = "standalone";
- uboot-blob {
- filename = "u-boot-nodtb.bin";
- type = "blob-ext";
+ uboot-blob {
+ filename = "u-boot-nodtb.bin";
+ type = "blob-ext";
+ };
};
- };
#ifndef CONFIG_ARMV8_PSCI
- atf {
- arch = "arm64";
- compression = "none";
- description = "ARM Trusted Firmware";
- entry = <0x910000>;
- load = <0x910000>;
- type = "firmware";
+ atf {
+ arch = "arm64";
+ compression = "none";
+ description = "ARM Trusted Firmware";
+ entry = <0x910000>;
+ load = <0x910000>;
+ type = "firmware";
- atf-blob {
- filename = "bl31.bin";
- type = "blob-ext";
+ atf-blob {
+ filename = "bl31.bin";
+ type = "blob-ext";
+ };
};
- };
#endif
- fdt {
- compression = "none";
- description = "NAME";
- type = "flat_dt";
+ fdt {
+ compression = "none";
+ description = "NAME";
+ type = "flat_dt";
- uboot-fdt-blob {
- filename = "u-boot.dtb";
- type = "blob-ext";
+ uboot-fdt-blob {
+ filename = "u-boot.dtb";
+ type = "blob-ext";
+ };
};
};
- };
- configurations {
- default = "conf";
+ configurations {
+ default = "conf";
- conf {
- description = "NAME";
- fdt = "fdt";
- firmware = "uboot";
+ conf {
+ description = "NAME";
+ fdt = "fdt";
+ firmware = "uboot";
#ifndef CONFIG_ARMV8_PSCI
- loadables = "atf";
+ loadables = "atf";
#endif
+ };
};
};
+#ifdef CONFIG_IMX_HAB
};
+#endif
};
};
diff --git a/arch/arm/dts/k3-am62-lp-sk-binman.dtsi b/arch/arm/dts/k3-am62-lp-sk-binman.dtsi
new file mode 100644
index 0000000..18341d0
--- /dev/null
+++ b/arch/arm/dts/k3-am62-lp-sk-binman.dtsi
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include "k3-binman.dtsi"
+#include "k3-am625-sk-binman.dtsi"
+
+#ifdef CONFIG_TARGET_AM625_A53_EVM
+
+#define SPL_AM62_LP_SK_DTB "spl/dts/ti/k3-am62-lp-sk.dtb"
+
+&spl_am625_sk_dtb {
+ filename = SPL_AM62_LP_SK_DTB;
+};
+
+&spl_am625_sk_dtb_unsigned {
+ filename = SPL_AM62_LP_SK_DTB;
+};
+
+#endif
diff --git a/arch/arm/dts/k3-am62-lp-sk-u-boot.dtsi b/arch/arm/dts/k3-am62-lp-sk-u-boot.dtsi
new file mode 100644
index 0000000..cbcc7f3
--- /dev/null
+++ b/arch/arm/dts/k3-am62-lp-sk-u-boot.dtsi
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * AM62x LP SK dts file for SPLs
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include "k3-am62-lp-sk-binman.dtsi"
+
+/ {
+ chosen {
+ tick-timer = &main_timer0;
+ };
+};
+
+&main_timer0 {
+ clock-frequency = <25000000>;
+};
diff --git a/arch/arm/dts/k3-am62-lp4-50-800-800.dtsi b/arch/arm/dts/k3-am62-lp4-50-800-800.dtsi
new file mode 100644
index 0000000..c255ae6
--- /dev/null
+++ b/arch/arm/dts/k3-am62-lp4-50-800-800.dtsi
@@ -0,0 +1,2190 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * This file was generated with the
+ * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.07
+ * Wed Mar 01 2023 17:52:11 GMT-0600 (Central Standard Time)
+ * DDR Type: LPDDR4
+ * F0 = 50MHz F1 = NA F2 = 800MHz
+ * Density (per channel): 16Gb
+ * Write DBI: Enable
+ * Number of Ranks: 1
+ */
+
+#define DDRSS_PLL_FHS_CNT 3
+#define DDRSS_PLL_FREQUENCY_1 400000000
+#define DDRSS_PLL_FREQUENCY_2 400000000
+
+#define DDRSS_CTL_0_DATA 0x00000B00
+#define DDRSS_CTL_1_DATA 0x00000000
+#define DDRSS_CTL_2_DATA 0x00000000
+#define DDRSS_CTL_3_DATA 0x00000000
+#define DDRSS_CTL_4_DATA 0x00000000
+#define DDRSS_CTL_5_DATA 0x00000000
+#define DDRSS_CTL_6_DATA 0x00000000
+#define DDRSS_CTL_7_DATA 0x00002710
+#define DDRSS_CTL_8_DATA 0x000186A0
+#define DDRSS_CTL_9_DATA 0x00000005
+#define DDRSS_CTL_10_DATA 0x00000064
+#define DDRSS_CTL_11_DATA 0x00027100
+#define DDRSS_CTL_12_DATA 0x00186A00
+#define DDRSS_CTL_13_DATA 0x00000005
+#define DDRSS_CTL_14_DATA 0x00000640
+#define DDRSS_CTL_15_DATA 0x00027100
+#define DDRSS_CTL_16_DATA 0x00186A00
+#define DDRSS_CTL_17_DATA 0x00000005
+#define DDRSS_CTL_18_DATA 0x00000640
+#define DDRSS_CTL_19_DATA 0x01010100
+#define DDRSS_CTL_20_DATA 0x01010100
+#define DDRSS_CTL_21_DATA 0x01000110
+#define DDRSS_CTL_22_DATA 0x02010002
+#define DDRSS_CTL_23_DATA 0x0000000A
+#define DDRSS_CTL_24_DATA 0x000186A0
+#define DDRSS_CTL_25_DATA 0x00000000
+#define DDRSS_CTL_26_DATA 0x00000000
+#define DDRSS_CTL_27_DATA 0x00000000
+#define DDRSS_CTL_28_DATA 0x00000000
+#define DDRSS_CTL_29_DATA 0x00020200
+#define DDRSS_CTL_30_DATA 0x00000000
+#define DDRSS_CTL_31_DATA 0x00000000
+#define DDRSS_CTL_32_DATA 0x00000000
+#define DDRSS_CTL_33_DATA 0x00000000
+#define DDRSS_CTL_34_DATA 0x08000010
+#define DDRSS_CTL_35_DATA 0x00002020
+#define DDRSS_CTL_36_DATA 0x00000000
+#define DDRSS_CTL_37_DATA 0x00000000
+#define DDRSS_CTL_38_DATA 0x0000040C
+#define DDRSS_CTL_39_DATA 0x00000000
+#define DDRSS_CTL_40_DATA 0x0000081C
+#define DDRSS_CTL_41_DATA 0x00000000
+#define DDRSS_CTL_42_DATA 0x0000081C
+#define DDRSS_CTL_43_DATA 0x00000000
+#define DDRSS_CTL_44_DATA 0x05000804
+#define DDRSS_CTL_45_DATA 0x00000700
+#define DDRSS_CTL_46_DATA 0x09090004
+#define DDRSS_CTL_47_DATA 0x00000203
+#define DDRSS_CTL_48_DATA 0x00320007
+#define DDRSS_CTL_49_DATA 0x09090023
+#define DDRSS_CTL_50_DATA 0x0000190F
+#define DDRSS_CTL_51_DATA 0x00320007
+#define DDRSS_CTL_52_DATA 0x09090023
+#define DDRSS_CTL_53_DATA 0x0900190F
+#define DDRSS_CTL_54_DATA 0x000A0A09
+#define DDRSS_CTL_55_DATA 0x040006DB
+#define DDRSS_CTL_56_DATA 0x09092004
+#define DDRSS_CTL_57_DATA 0x00000C0A
+#define DDRSS_CTL_58_DATA 0x06006DB0
+#define DDRSS_CTL_59_DATA 0x09092006
+#define DDRSS_CTL_60_DATA 0x00000C0A
+#define DDRSS_CTL_61_DATA 0x06006DB0
+#define DDRSS_CTL_62_DATA 0x03042006
+#define DDRSS_CTL_63_DATA 0x04050002
+#define DDRSS_CTL_64_DATA 0x100F100F
+#define DDRSS_CTL_65_DATA 0x01010008
+#define DDRSS_CTL_66_DATA 0x041F1F07
+#define DDRSS_CTL_67_DATA 0x03111103
+#define DDRSS_CTL_68_DATA 0x00001111
+#define DDRSS_CTL_69_DATA 0x00000101
+#define DDRSS_CTL_70_DATA 0x00000000
+#define DDRSS_CTL_71_DATA 0x01000000
+#define DDRSS_CTL_72_DATA 0x00130803
+#define DDRSS_CTL_73_DATA 0x000000BB
+#define DDRSS_CTL_74_DATA 0x00000130
+#define DDRSS_CTL_75_DATA 0x00000C28
+#define DDRSS_CTL_76_DATA 0x00000130
+#define DDRSS_CTL_77_DATA 0x00000C28
+#define DDRSS_CTL_78_DATA 0x00000005
+#define DDRSS_CTL_79_DATA 0x0000000A
+#define DDRSS_CTL_80_DATA 0x00000010
+#define DDRSS_CTL_81_DATA 0x00000098
+#define DDRSS_CTL_82_DATA 0x0000017E
+#define DDRSS_CTL_83_DATA 0x00000098
+#define DDRSS_CTL_84_DATA 0x0000017E
+#define DDRSS_CTL_85_DATA 0x03004000
+#define DDRSS_CTL_86_DATA 0x00001201
+#define DDRSS_CTL_87_DATA 0x00060005
+#define DDRSS_CTL_88_DATA 0x00000006
+#define DDRSS_CTL_89_DATA 0x00000000
+#define DDRSS_CTL_90_DATA 0x05121208
+#define DDRSS_CTL_91_DATA 0x05030A05
+#define DDRSS_CTL_92_DATA 0x05030C06
+#define DDRSS_CTL_93_DATA 0x01030C06
+#define DDRSS_CTL_94_DATA 0x02010201
+#define DDRSS_CTL_95_DATA 0x00001401
+#define DDRSS_CTL_96_DATA 0x01360014
+#define DDRSS_CTL_97_DATA 0x01360136
+#define DDRSS_CTL_98_DATA 0x00000136
+#define DDRSS_CTL_99_DATA 0x00000000
+#define DDRSS_CTL_100_DATA 0x05010303
+#define DDRSS_CTL_101_DATA 0x0C040505
+#define DDRSS_CTL_102_DATA 0x06050203
+#define DDRSS_CTL_103_DATA 0x030C0605
+#define DDRSS_CTL_104_DATA 0x05060502
+#define DDRSS_CTL_105_DATA 0x03030306
+#define DDRSS_CTL_106_DATA 0x03010000
+#define DDRSS_CTL_107_DATA 0x00010000
+#define DDRSS_CTL_108_DATA 0x00000000
+#define DDRSS_CTL_109_DATA 0x01000000
+#define DDRSS_CTL_110_DATA 0x80104002
+#define DDRSS_CTL_111_DATA 0x00040003
+#define DDRSS_CTL_112_DATA 0x00040005
+#define DDRSS_CTL_113_DATA 0x00030000
+#define DDRSS_CTL_114_DATA 0x00050004
+#define DDRSS_CTL_115_DATA 0x00000004
+#define DDRSS_CTL_116_DATA 0x00040003
+#define DDRSS_CTL_117_DATA 0x00040005
+#define DDRSS_CTL_118_DATA 0x00000000
+#define DDRSS_CTL_119_DATA 0x00002EC0
+#define DDRSS_CTL_120_DATA 0x00002EC0
+#define DDRSS_CTL_121_DATA 0x00002EC0
+#define DDRSS_CTL_122_DATA 0x00002EC0
+#define DDRSS_CTL_123_DATA 0x00002EC0
+#define DDRSS_CTL_124_DATA 0x00000000
+#define DDRSS_CTL_125_DATA 0x0000051D
+#define DDRSS_CTL_126_DATA 0x00030A00
+#define DDRSS_CTL_127_DATA 0x00030A00
+#define DDRSS_CTL_128_DATA 0x00030A00
+#define DDRSS_CTL_129_DATA 0x00030A00
+#define DDRSS_CTL_130_DATA 0x00030A00
+#define DDRSS_CTL_131_DATA 0x00000000
+#define DDRSS_CTL_132_DATA 0x00005518
+#define DDRSS_CTL_133_DATA 0x00030A00
+#define DDRSS_CTL_134_DATA 0x00030A00
+#define DDRSS_CTL_135_DATA 0x00030A00
+#define DDRSS_CTL_136_DATA 0x00030A00
+#define DDRSS_CTL_137_DATA 0x00030A00
+#define DDRSS_CTL_138_DATA 0x00000000
+#define DDRSS_CTL_139_DATA 0x00005518
+#define DDRSS_CTL_140_DATA 0x00000000
+#define DDRSS_CTL_141_DATA 0x00000000
+#define DDRSS_CTL_142_DATA 0x00000000
+#define DDRSS_CTL_143_DATA 0x00000000
+#define DDRSS_CTL_144_DATA 0x00000000
+#define DDRSS_CTL_145_DATA 0x00000000
+#define DDRSS_CTL_146_DATA 0x00000000
+#define DDRSS_CTL_147_DATA 0x00000000
+#define DDRSS_CTL_148_DATA 0x00000000
+#define DDRSS_CTL_149_DATA 0x00000000
+#define DDRSS_CTL_150_DATA 0x00000000
+#define DDRSS_CTL_151_DATA 0x00000000
+#define DDRSS_CTL_152_DATA 0x00000000
+#define DDRSS_CTL_153_DATA 0x00000000
+#define DDRSS_CTL_154_DATA 0x00000000
+#define DDRSS_CTL_155_DATA 0x00000000
+#define DDRSS_CTL_156_DATA 0x03050000
+#define DDRSS_CTL_157_DATA 0x03050305
+#define DDRSS_CTL_158_DATA 0x00000000
+#define DDRSS_CTL_159_DATA 0x08010000
+#define DDRSS_CTL_160_DATA 0x000E0808
+#define DDRSS_CTL_161_DATA 0x01000000
+#define DDRSS_CTL_162_DATA 0x0E080808
+#define DDRSS_CTL_163_DATA 0x00000000
+#define DDRSS_CTL_164_DATA 0x08080801
+#define DDRSS_CTL_165_DATA 0x0000080E
+#define DDRSS_CTL_166_DATA 0x00040003
+#define DDRSS_CTL_167_DATA 0x00000007
+#define DDRSS_CTL_168_DATA 0x00000000
+#define DDRSS_CTL_169_DATA 0x00000000
+#define DDRSS_CTL_170_DATA 0x00000000
+#define DDRSS_CTL_171_DATA 0x00000000
+#define DDRSS_CTL_172_DATA 0x00000000
+#define DDRSS_CTL_173_DATA 0x00000000
+#define DDRSS_CTL_174_DATA 0x01000000
+#define DDRSS_CTL_175_DATA 0x00000000
+#define DDRSS_CTL_176_DATA 0x00001500
+#define DDRSS_CTL_177_DATA 0x0000100E
+#define DDRSS_CTL_178_DATA 0x00000002
+#define DDRSS_CTL_179_DATA 0x00000000
+#define DDRSS_CTL_180_DATA 0x00000001
+#define DDRSS_CTL_181_DATA 0x00000002
+#define DDRSS_CTL_182_DATA 0x00000C00
+#define DDRSS_CTL_183_DATA 0x00001000
+#define DDRSS_CTL_184_DATA 0x00000C00
+#define DDRSS_CTL_185_DATA 0x00001000
+#define DDRSS_CTL_186_DATA 0x00000C00
+#define DDRSS_CTL_187_DATA 0x00001000
+#define DDRSS_CTL_188_DATA 0x00000000
+#define DDRSS_CTL_189_DATA 0x00000000
+#define DDRSS_CTL_190_DATA 0x00000000
+#define DDRSS_CTL_191_DATA 0x00000000
+#define DDRSS_CTL_192_DATA 0x0005000A
+#define DDRSS_CTL_193_DATA 0x0404000D
+#define DDRSS_CTL_194_DATA 0x0000000D
+#define DDRSS_CTL_195_DATA 0x005000A0
+#define DDRSS_CTL_196_DATA 0x060600C8
+#define DDRSS_CTL_197_DATA 0x000000C8
+#define DDRSS_CTL_198_DATA 0x005000A0
+#define DDRSS_CTL_199_DATA 0x060600C8
+#define DDRSS_CTL_200_DATA 0x000000C8
+#define DDRSS_CTL_201_DATA 0x00000000
+#define DDRSS_CTL_202_DATA 0x00000000
+#define DDRSS_CTL_203_DATA 0x00000000
+#define DDRSS_CTL_204_DATA 0x00000000
+#define DDRSS_CTL_205_DATA 0x00000004
+#define DDRSS_CTL_206_DATA 0x00000000
+#define DDRSS_CTL_207_DATA 0x00000000
+#define DDRSS_CTL_208_DATA 0x00000024
+#define DDRSS_CTL_209_DATA 0x00000012
+#define DDRSS_CTL_210_DATA 0x00000000
+#define DDRSS_CTL_211_DATA 0x00000024
+#define DDRSS_CTL_212_DATA 0x00000012
+#define DDRSS_CTL_213_DATA 0x00000000
+#define DDRSS_CTL_214_DATA 0x00000004
+#define DDRSS_CTL_215_DATA 0x00000000
+#define DDRSS_CTL_216_DATA 0x00000000
+#define DDRSS_CTL_217_DATA 0x00000024
+#define DDRSS_CTL_218_DATA 0x00000012
+#define DDRSS_CTL_219_DATA 0x00000000
+#define DDRSS_CTL_220_DATA 0x00000024
+#define DDRSS_CTL_221_DATA 0x00000012
+#define DDRSS_CTL_222_DATA 0x00000000
+#define DDRSS_CTL_223_DATA 0x00000000
+#define DDRSS_CTL_224_DATA 0x00000031
+#define DDRSS_CTL_225_DATA 0x000000B1
+#define DDRSS_CTL_226_DATA 0x000000B1
+#define DDRSS_CTL_227_DATA 0x00000031
+#define DDRSS_CTL_228_DATA 0x000000B1
+#define DDRSS_CTL_229_DATA 0x000000B1
+#define DDRSS_CTL_230_DATA 0x00000000
+#define DDRSS_CTL_231_DATA 0x00000000
+#define DDRSS_CTL_232_DATA 0x00000000
+#define DDRSS_CTL_233_DATA 0x00000000
+#define DDRSS_CTL_234_DATA 0x00000000
+#define DDRSS_CTL_235_DATA 0x00000000
+#define DDRSS_CTL_236_DATA 0x00000000
+#define DDRSS_CTL_237_DATA 0x00000000
+#define DDRSS_CTL_238_DATA 0x00000000
+#define DDRSS_CTL_239_DATA 0x00000000
+#define DDRSS_CTL_240_DATA 0x00000000
+#define DDRSS_CTL_241_DATA 0x00000000
+#define DDRSS_CTL_242_DATA 0x00000000
+#define DDRSS_CTL_243_DATA 0x00000000
+#define DDRSS_CTL_244_DATA 0x00000000
+#define DDRSS_CTL_245_DATA 0x00000000
+#define DDRSS_CTL_246_DATA 0x00000000
+#define DDRSS_CTL_247_DATA 0x00000000
+#define DDRSS_CTL_248_DATA 0x00000000
+#define DDRSS_CTL_249_DATA 0x00000000
+#define DDRSS_CTL_250_DATA 0x00000000
+#define DDRSS_CTL_251_DATA 0x00000000
+#define DDRSS_CTL_252_DATA 0x00000000
+#define DDRSS_CTL_253_DATA 0x00000000
+#define DDRSS_CTL_254_DATA 0x46004646
+#define DDRSS_CTL_255_DATA 0x00002746
+#define DDRSS_CTL_256_DATA 0x00000027
+#define DDRSS_CTL_257_DATA 0x00000027
+#define DDRSS_CTL_258_DATA 0x00000027
+#define DDRSS_CTL_259_DATA 0x00000027
+#define DDRSS_CTL_260_DATA 0x00000027
+#define DDRSS_CTL_261_DATA 0x00000000
+#define DDRSS_CTL_262_DATA 0x00000000
+#define DDRSS_CTL_263_DATA 0x0000000F
+#define DDRSS_CTL_264_DATA 0x0000000F
+#define DDRSS_CTL_265_DATA 0x0000000F
+#define DDRSS_CTL_266_DATA 0x0000000F
+#define DDRSS_CTL_267_DATA 0x0000000F
+#define DDRSS_CTL_268_DATA 0x0000000F
+#define DDRSS_CTL_269_DATA 0x00000000
+#define DDRSS_CTL_270_DATA 0x00001000
+#define DDRSS_CTL_271_DATA 0x00000015
+#define DDRSS_CTL_272_DATA 0x00000015
+#define DDRSS_CTL_273_DATA 0x00000010
+#define DDRSS_CTL_274_DATA 0x00000015
+#define DDRSS_CTL_275_DATA 0x00000015
+#define DDRSS_CTL_276_DATA 0x00000020
+#define DDRSS_CTL_277_DATA 0x00010000
+#define DDRSS_CTL_278_DATA 0x00000100
+#define DDRSS_CTL_279_DATA 0x00000000
+#define DDRSS_CTL_280_DATA 0x00000000
+#define DDRSS_CTL_281_DATA 0x00000101
+#define DDRSS_CTL_282_DATA 0x00000000
+#define DDRSS_CTL_283_DATA 0x00000000
+#define DDRSS_CTL_284_DATA 0x00000000
+#define DDRSS_CTL_285_DATA 0x00000000
+#define DDRSS_CTL_286_DATA 0x00000000
+#define DDRSS_CTL_287_DATA 0x00000000
+#define DDRSS_CTL_288_DATA 0x00000000
+#define DDRSS_CTL_289_DATA 0x00000000
+#define DDRSS_CTL_290_DATA 0x0C181511
+#define DDRSS_CTL_291_DATA 0x00000304
+#define DDRSS_CTL_292_DATA 0x00000000
+#define DDRSS_CTL_293_DATA 0x00000000
+#define DDRSS_CTL_294_DATA 0x00000000
+#define DDRSS_CTL_295_DATA 0x00000000
+#define DDRSS_CTL_296_DATA 0x00000000
+#define DDRSS_CTL_297_DATA 0x00000000
+#define DDRSS_CTL_298_DATA 0x00000000
+#define DDRSS_CTL_299_DATA 0x00000000
+#define DDRSS_CTL_300_DATA 0x00000000
+#define DDRSS_CTL_301_DATA 0x00000000
+#define DDRSS_CTL_302_DATA 0x00000000
+#define DDRSS_CTL_303_DATA 0x00000000
+#define DDRSS_CTL_304_DATA 0x00000000
+#define DDRSS_CTL_305_DATA 0x00020000
+#define DDRSS_CTL_306_DATA 0x00400100
+#define DDRSS_CTL_307_DATA 0x00080032
+#define DDRSS_CTL_308_DATA 0x01000200
+#define DDRSS_CTL_309_DATA 0x03200040
+#define DDRSS_CTL_310_DATA 0x00020018
+#define DDRSS_CTL_311_DATA 0x00400100
+#define DDRSS_CTL_312_DATA 0x00180320
+#define DDRSS_CTL_313_DATA 0x00030000
+#define DDRSS_CTL_314_DATA 0x00280028
+#define DDRSS_CTL_315_DATA 0x00000100
+#define DDRSS_CTL_316_DATA 0x01010000
+#define DDRSS_CTL_317_DATA 0x00000000
+#define DDRSS_CTL_318_DATA 0x3FFF0000
+#define DDRSS_CTL_319_DATA 0x000FFF00
+#define DDRSS_CTL_320_DATA 0xFFFFFFFF
+#define DDRSS_CTL_321_DATA 0x00FFFF00
+#define DDRSS_CTL_322_DATA 0x0B000000
+#define DDRSS_CTL_323_DATA 0x0001FFFF
+#define DDRSS_CTL_324_DATA 0x01010101
+#define DDRSS_CTL_325_DATA 0x01010101
+#define DDRSS_CTL_326_DATA 0x00000118
+#define DDRSS_CTL_327_DATA 0x00000C01
+#define DDRSS_CTL_328_DATA 0x01000100
+#define DDRSS_CTL_329_DATA 0x00000000
+#define DDRSS_CTL_330_DATA 0x00000000
+#define DDRSS_CTL_331_DATA 0x01030303
+#define DDRSS_CTL_332_DATA 0x00000001
+#define DDRSS_CTL_333_DATA 0x00000000
+#define DDRSS_CTL_334_DATA 0x00000000
+#define DDRSS_CTL_335_DATA 0x00000000
+#define DDRSS_CTL_336_DATA 0x00000000
+#define DDRSS_CTL_337_DATA 0x00000000
+#define DDRSS_CTL_338_DATA 0x00000000
+#define DDRSS_CTL_339_DATA 0x00000000
+#define DDRSS_CTL_340_DATA 0x00000000
+#define DDRSS_CTL_341_DATA 0x00000000
+#define DDRSS_CTL_342_DATA 0x00000000
+#define DDRSS_CTL_343_DATA 0x00000000
+#define DDRSS_CTL_344_DATA 0x00000000
+#define DDRSS_CTL_345_DATA 0x00000000
+#define DDRSS_CTL_346_DATA 0x00000000
+#define DDRSS_CTL_347_DATA 0x00000000
+#define DDRSS_CTL_348_DATA 0x00000000
+#define DDRSS_CTL_349_DATA 0x00000000
+#define DDRSS_CTL_350_DATA 0x00000000
+#define DDRSS_CTL_351_DATA 0x00000000
+#define DDRSS_CTL_352_DATA 0x00000000
+#define DDRSS_CTL_353_DATA 0x00000000
+#define DDRSS_CTL_354_DATA 0x00000000
+#define DDRSS_CTL_355_DATA 0x00000000
+#define DDRSS_CTL_356_DATA 0x00000000
+#define DDRSS_CTL_357_DATA 0x00000000
+#define DDRSS_CTL_358_DATA 0x00000000
+#define DDRSS_CTL_359_DATA 0x00000000
+#define DDRSS_CTL_360_DATA 0x00000000
+#define DDRSS_CTL_361_DATA 0x00000000
+#define DDRSS_CTL_362_DATA 0x00000000
+#define DDRSS_CTL_363_DATA 0x00000000
+#define DDRSS_CTL_364_DATA 0x00000000
+#define DDRSS_CTL_365_DATA 0x00000000
+#define DDRSS_CTL_366_DATA 0x00000000
+#define DDRSS_CTL_367_DATA 0x00000000
+#define DDRSS_CTL_368_DATA 0x00000000
+#define DDRSS_CTL_369_DATA 0x00000000
+#define DDRSS_CTL_370_DATA 0x00000000
+#define DDRSS_CTL_371_DATA 0x01000101
+#define DDRSS_CTL_372_DATA 0x01010001
+#define DDRSS_CTL_373_DATA 0x00010101
+#define DDRSS_CTL_374_DATA 0x01050503
+#define DDRSS_CTL_375_DATA 0x05020201
+#define DDRSS_CTL_376_DATA 0x08080C0C
+#define DDRSS_CTL_377_DATA 0x00080308
+#define DDRSS_CTL_378_DATA 0x000B030E
+#define DDRSS_CTL_379_DATA 0x000B0310
+#define DDRSS_CTL_380_DATA 0x0B0B0810
+#define DDRSS_CTL_381_DATA 0x01000000
+#define DDRSS_CTL_382_DATA 0x03020301
+#define DDRSS_CTL_383_DATA 0x04000102
+#define DDRSS_CTL_384_DATA 0x1B000004
+#define DDRSS_CTL_385_DATA 0x00000176
+#define DDRSS_CTL_386_DATA 0x00000200
+#define DDRSS_CTL_387_DATA 0x00000200
+#define DDRSS_CTL_388_DATA 0x00000200
+#define DDRSS_CTL_389_DATA 0x00000200
+#define DDRSS_CTL_390_DATA 0x00000693
+#define DDRSS_CTL_391_DATA 0x00000E9C
+#define DDRSS_CTL_392_DATA 0x03050202
+#define DDRSS_CTL_393_DATA 0x00250201
+#define DDRSS_CTL_394_DATA 0x00001850
+#define DDRSS_CTL_395_DATA 0x00000200
+#define DDRSS_CTL_396_DATA 0x00000200
+#define DDRSS_CTL_397_DATA 0x00000200
+#define DDRSS_CTL_398_DATA 0x00000200
+#define DDRSS_CTL_399_DATA 0x00006D68
+#define DDRSS_CTL_400_DATA 0x0000F320
+#define DDRSS_CTL_401_DATA 0x070D0402
+#define DDRSS_CTL_402_DATA 0x00250405
+#define DDRSS_CTL_403_DATA 0x00001850
+#define DDRSS_CTL_404_DATA 0x00000200
+#define DDRSS_CTL_405_DATA 0x00000200
+#define DDRSS_CTL_406_DATA 0x00000200
+#define DDRSS_CTL_407_DATA 0x00000200
+#define DDRSS_CTL_408_DATA 0x00006D68
+#define DDRSS_CTL_409_DATA 0x0000F320
+#define DDRSS_CTL_410_DATA 0x070D0402
+#define DDRSS_CTL_411_DATA 0x00000405
+#define DDRSS_CTL_412_DATA 0x00000000
+#define DDRSS_CTL_413_DATA 0x0302000A
+#define DDRSS_CTL_414_DATA 0x01000500
+#define DDRSS_CTL_415_DATA 0x01010001
+#define DDRSS_CTL_416_DATA 0x00010001
+#define DDRSS_CTL_417_DATA 0x01010001
+#define DDRSS_CTL_418_DATA 0x02010000
+#define DDRSS_CTL_419_DATA 0x00000200
+#define DDRSS_CTL_420_DATA 0x02000201
+#define DDRSS_CTL_421_DATA 0x10100600
+#define DDRSS_CTL_422_DATA 0x00202020
+#define DDRSS_PI_0_DATA 0x00000B00
+#define DDRSS_PI_1_DATA 0x00000000
+#define DDRSS_PI_2_DATA 0x00000000
+#define DDRSS_PI_3_DATA 0x01000000
+#define DDRSS_PI_4_DATA 0x00000001
+#define DDRSS_PI_5_DATA 0x00010064
+#define DDRSS_PI_6_DATA 0x00000000
+#define DDRSS_PI_7_DATA 0x00000000
+#define DDRSS_PI_8_DATA 0x00000000
+#define DDRSS_PI_9_DATA 0x00000000
+#define DDRSS_PI_10_DATA 0x00000000
+#define DDRSS_PI_11_DATA 0x00000002
+#define DDRSS_PI_12_DATA 0x00000005
+#define DDRSS_PI_13_DATA 0x00010001
+#define DDRSS_PI_14_DATA 0x08000000
+#define DDRSS_PI_15_DATA 0x00010300
+#define DDRSS_PI_16_DATA 0x00000005
+#define DDRSS_PI_17_DATA 0x00000000
+#define DDRSS_PI_18_DATA 0x00000000
+#define DDRSS_PI_19_DATA 0x00000000
+#define DDRSS_PI_20_DATA 0x00000000
+#define DDRSS_PI_21_DATA 0x00000000
+#define DDRSS_PI_22_DATA 0x00000000
+#define DDRSS_PI_23_DATA 0x00010000
+#define DDRSS_PI_24_DATA 0x280A0001
+#define DDRSS_PI_25_DATA 0x00000000
+#define DDRSS_PI_26_DATA 0x00010000
+#define DDRSS_PI_27_DATA 0x00003200
+#define DDRSS_PI_28_DATA 0x00000000
+#define DDRSS_PI_29_DATA 0x00000000
+#define DDRSS_PI_30_DATA 0x01010102
+#define DDRSS_PI_31_DATA 0x00000000
+#define DDRSS_PI_32_DATA 0x00000000
+#define DDRSS_PI_33_DATA 0x00000000
+#define DDRSS_PI_34_DATA 0x00000001
+#define DDRSS_PI_35_DATA 0x000000AA
+#define DDRSS_PI_36_DATA 0x00000055
+#define DDRSS_PI_37_DATA 0x000000B5
+#define DDRSS_PI_38_DATA 0x0000004A
+#define DDRSS_PI_39_DATA 0x00000056
+#define DDRSS_PI_40_DATA 0x000000A9
+#define DDRSS_PI_41_DATA 0x000000A9
+#define DDRSS_PI_42_DATA 0x000000B5
+#define DDRSS_PI_43_DATA 0x00000000
+#define DDRSS_PI_44_DATA 0x00000000
+#define DDRSS_PI_45_DATA 0x00010100
+#define DDRSS_PI_46_DATA 0x00000015
+#define DDRSS_PI_47_DATA 0x000007D0
+#define DDRSS_PI_48_DATA 0x00000300
+#define DDRSS_PI_49_DATA 0x00000000
+#define DDRSS_PI_50_DATA 0x00000000
+#define DDRSS_PI_51_DATA 0x01000000
+#define DDRSS_PI_52_DATA 0x00010101
+#define DDRSS_PI_53_DATA 0x01000000
+#define DDRSS_PI_54_DATA 0x03000000
+#define DDRSS_PI_55_DATA 0x00000000
+#define DDRSS_PI_56_DATA 0x00001701
+#define DDRSS_PI_57_DATA 0x00000000
+#define DDRSS_PI_58_DATA 0x00000000
+#define DDRSS_PI_59_DATA 0x00000000
+#define DDRSS_PI_60_DATA 0x0A0A140A
+#define DDRSS_PI_61_DATA 0x10020101
+#define DDRSS_PI_62_DATA 0x01000210
+#define DDRSS_PI_63_DATA 0x05000404
+#define DDRSS_PI_64_DATA 0x00010001
+#define DDRSS_PI_65_DATA 0x0001000E
+#define DDRSS_PI_66_DATA 0x01010100
+#define DDRSS_PI_67_DATA 0x00010000
+#define DDRSS_PI_68_DATA 0x00000034
+#define DDRSS_PI_69_DATA 0x00000000
+#define DDRSS_PI_70_DATA 0x00000000
+#define DDRSS_PI_71_DATA 0x0000FFFF
+#define DDRSS_PI_72_DATA 0x00000000
+#define DDRSS_PI_73_DATA 0x00000000
+#define DDRSS_PI_74_DATA 0x00000000
+#define DDRSS_PI_75_DATA 0x00000000
+#define DDRSS_PI_76_DATA 0x01000000
+#define DDRSS_PI_77_DATA 0x08000100
+#define DDRSS_PI_78_DATA 0x00020000
+#define DDRSS_PI_79_DATA 0x00010002
+#define DDRSS_PI_80_DATA 0x00000001
+#define DDRSS_PI_81_DATA 0x00020001
+#define DDRSS_PI_82_DATA 0x00020002
+#define DDRSS_PI_83_DATA 0x00000000
+#define DDRSS_PI_84_DATA 0x00000000
+#define DDRSS_PI_85_DATA 0x00000000
+#define DDRSS_PI_86_DATA 0x00000000
+#define DDRSS_PI_87_DATA 0x00000000
+#define DDRSS_PI_88_DATA 0x00000000
+#define DDRSS_PI_89_DATA 0x00000000
+#define DDRSS_PI_90_DATA 0x00000000
+#define DDRSS_PI_91_DATA 0x00000400
+#define DDRSS_PI_92_DATA 0x0A090B0C
+#define DDRSS_PI_93_DATA 0x04060708
+#define DDRSS_PI_94_DATA 0x01000005
+#define DDRSS_PI_95_DATA 0x00000800
+#define DDRSS_PI_96_DATA 0x00000000
+#define DDRSS_PI_97_DATA 0x00010008
+#define DDRSS_PI_98_DATA 0x00000000
+#define DDRSS_PI_99_DATA 0x0000AA00
+#define DDRSS_PI_100_DATA 0x00000000
+#define DDRSS_PI_101_DATA 0x00010000
+#define DDRSS_PI_102_DATA 0x00000000
+#define DDRSS_PI_103_DATA 0x00000000
+#define DDRSS_PI_104_DATA 0x00000000
+#define DDRSS_PI_105_DATA 0x00000000
+#define DDRSS_PI_106_DATA 0x00000000
+#define DDRSS_PI_107_DATA 0x00000000
+#define DDRSS_PI_108_DATA 0x00000000
+#define DDRSS_PI_109_DATA 0x00000000
+#define DDRSS_PI_110_DATA 0x00000000
+#define DDRSS_PI_111_DATA 0x00000000
+#define DDRSS_PI_112_DATA 0x00000000
+#define DDRSS_PI_113_DATA 0x00000000
+#define DDRSS_PI_114_DATA 0x00000000
+#define DDRSS_PI_115_DATA 0x00000000
+#define DDRSS_PI_116_DATA 0x00000000
+#define DDRSS_PI_117_DATA 0x00000000
+#define DDRSS_PI_118_DATA 0x00000000
+#define DDRSS_PI_119_DATA 0x00000000
+#define DDRSS_PI_120_DATA 0x00000000
+#define DDRSS_PI_121_DATA 0x00000000
+#define DDRSS_PI_122_DATA 0x00000000
+#define DDRSS_PI_123_DATA 0x00000000
+#define DDRSS_PI_124_DATA 0x00000008
+#define DDRSS_PI_125_DATA 0x00000000
+#define DDRSS_PI_126_DATA 0x00000000
+#define DDRSS_PI_127_DATA 0x00000000
+#define DDRSS_PI_128_DATA 0x00000000
+#define DDRSS_PI_129_DATA 0x00000000
+#define DDRSS_PI_130_DATA 0x00000000
+#define DDRSS_PI_131_DATA 0x00000000
+#define DDRSS_PI_132_DATA 0x00000000
+#define DDRSS_PI_133_DATA 0x00010000
+#define DDRSS_PI_134_DATA 0x00000000
+#define DDRSS_PI_135_DATA 0x00000000
+#define DDRSS_PI_136_DATA 0x0000000A
+#define DDRSS_PI_137_DATA 0x000186A0
+#define DDRSS_PI_138_DATA 0x00000100
+#define DDRSS_PI_139_DATA 0x00000000
+#define DDRSS_PI_140_DATA 0x00000000
+#define DDRSS_PI_141_DATA 0x00000000
+#define DDRSS_PI_142_DATA 0x00000000
+#define DDRSS_PI_143_DATA 0x00000000
+#define DDRSS_PI_144_DATA 0x01000000
+#define DDRSS_PI_145_DATA 0x00010003
+#define DDRSS_PI_146_DATA 0x02000101
+#define DDRSS_PI_147_DATA 0x01030001
+#define DDRSS_PI_148_DATA 0x00010400
+#define DDRSS_PI_149_DATA 0x06000105
+#define DDRSS_PI_150_DATA 0x01070001
+#define DDRSS_PI_151_DATA 0x00000000
+#define DDRSS_PI_152_DATA 0x00000000
+#define DDRSS_PI_153_DATA 0x00000000
+#define DDRSS_PI_154_DATA 0x00010001
+#define DDRSS_PI_155_DATA 0x00000000
+#define DDRSS_PI_156_DATA 0x00000000
+#define DDRSS_PI_157_DATA 0x00000000
+#define DDRSS_PI_158_DATA 0x00000000
+#define DDRSS_PI_159_DATA 0x00010000
+#define DDRSS_PI_160_DATA 0x00000004
+#define DDRSS_PI_161_DATA 0x00000000
+#define DDRSS_PI_162_DATA 0x00000000
+#define DDRSS_PI_163_DATA 0x00000000
+#define DDRSS_PI_164_DATA 0x00000800
+#define DDRSS_PI_165_DATA 0x00780078
+#define DDRSS_PI_166_DATA 0x00101001
+#define DDRSS_PI_167_DATA 0x00000034
+#define DDRSS_PI_168_DATA 0x00000042
+#define DDRSS_PI_169_DATA 0x00020042
+#define DDRSS_PI_170_DATA 0x02000200
+#define DDRSS_PI_171_DATA 0x00000004
+#define DDRSS_PI_172_DATA 0x0000080C
+#define DDRSS_PI_173_DATA 0x00081C00
+#define DDRSS_PI_174_DATA 0x001C0000
+#define DDRSS_PI_175_DATA 0x00000013
+#define DDRSS_PI_176_DATA 0x000000BB
+#define DDRSS_PI_177_DATA 0x00000130
+#define DDRSS_PI_178_DATA 0x00000C28
+#define DDRSS_PI_179_DATA 0x00000130
+#define DDRSS_PI_180_DATA 0x04000C28
+#define DDRSS_PI_181_DATA 0x01010404
+#define DDRSS_PI_182_DATA 0x00001501
+#define DDRSS_PI_183_DATA 0x001D001D
+#define DDRSS_PI_184_DATA 0x01000100
+#define DDRSS_PI_185_DATA 0x00000100
+#define DDRSS_PI_186_DATA 0x00000000
+#define DDRSS_PI_187_DATA 0x05050503
+#define DDRSS_PI_188_DATA 0x01010C0C
+#define DDRSS_PI_189_DATA 0x01010101
+#define DDRSS_PI_190_DATA 0x000C0C0A
+#define DDRSS_PI_191_DATA 0x00000000
+#define DDRSS_PI_192_DATA 0x00000000
+#define DDRSS_PI_193_DATA 0x04000000
+#define DDRSS_PI_194_DATA 0x04020808
+#define DDRSS_PI_195_DATA 0x04040204
+#define DDRSS_PI_196_DATA 0x00090031
+#define DDRSS_PI_197_DATA 0x00110039
+#define DDRSS_PI_198_DATA 0x00110039
+#define DDRSS_PI_199_DATA 0x01010101
+#define DDRSS_PI_200_DATA 0x0002000D
+#define DDRSS_PI_201_DATA 0x000200C8
+#define DDRSS_PI_202_DATA 0x010000C8
+#define DDRSS_PI_203_DATA 0x000E000E
+#define DDRSS_PI_204_DATA 0x00C90100
+#define DDRSS_PI_205_DATA 0x010000C9
+#define DDRSS_PI_206_DATA 0x00C900C9
+#define DDRSS_PI_207_DATA 0x32103200
+#define DDRSS_PI_208_DATA 0x01013210
+#define DDRSS_PI_209_DATA 0x0A070601
+#define DDRSS_PI_210_DATA 0x0D09070D
+#define DDRSS_PI_211_DATA 0x0D09070D
+#define DDRSS_PI_212_DATA 0x000C000D
+#define DDRSS_PI_213_DATA 0x00001000
+#define DDRSS_PI_214_DATA 0x00000C00
+#define DDRSS_PI_215_DATA 0x00001000
+#define DDRSS_PI_216_DATA 0x00000C00
+#define DDRSS_PI_217_DATA 0x02001000
+#define DDRSS_PI_218_DATA 0x0016000D
+#define DDRSS_PI_219_DATA 0x001600C8
+#define DDRSS_PI_220_DATA 0x000000C8
+#define DDRSS_PI_221_DATA 0x00001900
+#define DDRSS_PI_222_DATA 0x32000056
+#define DDRSS_PI_223_DATA 0x06000101
+#define DDRSS_PI_224_DATA 0x001D0204
+#define DDRSS_PI_225_DATA 0x32120058
+#define DDRSS_PI_226_DATA 0x05000101
+#define DDRSS_PI_227_DATA 0x001D0408
+#define DDRSS_PI_228_DATA 0x32120058
+#define DDRSS_PI_229_DATA 0x05000101
+#define DDRSS_PI_230_DATA 0x00000408
+#define DDRSS_PI_231_DATA 0x05030900
+#define DDRSS_PI_232_DATA 0x00040900
+#define DDRSS_PI_233_DATA 0x0000062B
+#define DDRSS_PI_234_DATA 0x20010004
+#define DDRSS_PI_235_DATA 0x0A0A0A03
+#define DDRSS_PI_236_DATA 0x11090000
+#define DDRSS_PI_237_DATA 0x1009000F
+#define DDRSS_PI_238_DATA 0x000062B8
+#define DDRSS_PI_239_DATA 0x20030023
+#define DDRSS_PI_240_DATA 0x0C0A0C0C
+#define DDRSS_PI_241_DATA 0x11090000
+#define DDRSS_PI_242_DATA 0x1009000F
+#define DDRSS_PI_243_DATA 0x000062B8
+#define DDRSS_PI_244_DATA 0x20030023
+#define DDRSS_PI_245_DATA 0x0C0A0C0C
+#define DDRSS_PI_246_DATA 0x00000000
+#define DDRSS_PI_247_DATA 0x00000176
+#define DDRSS_PI_248_DATA 0x00000E9C
+#define DDRSS_PI_249_DATA 0x00001850
+#define DDRSS_PI_250_DATA 0x0000F320
+#define DDRSS_PI_251_DATA 0x00001850
+#define DDRSS_PI_252_DATA 0x0000F320
+#define DDRSS_PI_253_DATA 0x01360014
+#define DDRSS_PI_254_DATA 0x03030136
+#define DDRSS_PI_255_DATA 0x00000003
+#define DDRSS_PI_256_DATA 0x00000000
+#define DDRSS_PI_257_DATA 0x05030503
+#define DDRSS_PI_258_DATA 0x00000503
+#define DDRSS_PI_259_DATA 0x00002710
+#define DDRSS_PI_260_DATA 0x000186A0
+#define DDRSS_PI_261_DATA 0x00000005
+#define DDRSS_PI_262_DATA 0x00000064
+#define DDRSS_PI_263_DATA 0x00000014
+#define DDRSS_PI_264_DATA 0x00027100
+#define DDRSS_PI_265_DATA 0x000186A0
+#define DDRSS_PI_266_DATA 0x00000005
+#define DDRSS_PI_267_DATA 0x00000640
+#define DDRSS_PI_268_DATA 0x00000136
+#define DDRSS_PI_269_DATA 0x00027100
+#define DDRSS_PI_270_DATA 0x000186A0
+#define DDRSS_PI_271_DATA 0x00000005
+#define DDRSS_PI_272_DATA 0x00000640
+#define DDRSS_PI_273_DATA 0x01000136
+#define DDRSS_PI_274_DATA 0x00320040
+#define DDRSS_PI_275_DATA 0x00010008
+#define DDRSS_PI_276_DATA 0x03200040
+#define DDRSS_PI_277_DATA 0x00010018
+#define DDRSS_PI_278_DATA 0x03200040
+#define DDRSS_PI_279_DATA 0x00000318
+#define DDRSS_PI_280_DATA 0x00280028
+#define DDRSS_PI_281_DATA 0x03040404
+#define DDRSS_PI_282_DATA 0x00000303
+#define DDRSS_PI_283_DATA 0x02020101
+#define DDRSS_PI_284_DATA 0x67676767
+#define DDRSS_PI_285_DATA 0x00000000
+#define DDRSS_PI_286_DATA 0x55000000
+#define DDRSS_PI_287_DATA 0x00000000
+#define DDRSS_PI_288_DATA 0x3C00005A
+#define DDRSS_PI_289_DATA 0x00005500
+#define DDRSS_PI_290_DATA 0x00005A00
+#define DDRSS_PI_291_DATA 0x0D100F3C
+#define DDRSS_PI_292_DATA 0x0003020E
+#define DDRSS_PI_293_DATA 0x00000001
+#define DDRSS_PI_294_DATA 0x01000000
+#define DDRSS_PI_295_DATA 0x00020201
+#define DDRSS_PI_296_DATA 0x00000000
+#define DDRSS_PI_297_DATA 0x00000000
+#define DDRSS_PI_298_DATA 0x00000004
+#define DDRSS_PI_299_DATA 0x00000000
+#define DDRSS_PI_300_DATA 0x00000031
+#define DDRSS_PI_301_DATA 0x00000000
+#define DDRSS_PI_302_DATA 0x00000000
+#define DDRSS_PI_303_DATA 0x00000000
+#define DDRSS_PI_304_DATA 0x00100F27
+#define DDRSS_PI_305_DATA 0x00000000
+#define DDRSS_PI_306_DATA 0x00000024
+#define DDRSS_PI_307_DATA 0x00000012
+#define DDRSS_PI_308_DATA 0x000000B1
+#define DDRSS_PI_309_DATA 0x00000000
+#define DDRSS_PI_310_DATA 0x00000000
+#define DDRSS_PI_311_DATA 0x46000000
+#define DDRSS_PI_312_DATA 0x00150F27
+#define DDRSS_PI_313_DATA 0x00000000
+#define DDRSS_PI_314_DATA 0x00000024
+#define DDRSS_PI_315_DATA 0x00000012
+#define DDRSS_PI_316_DATA 0x000000B1
+#define DDRSS_PI_317_DATA 0x00000000
+#define DDRSS_PI_318_DATA 0x00000000
+#define DDRSS_PI_319_DATA 0x46000000
+#define DDRSS_PI_320_DATA 0x00150F27
+#define DDRSS_PI_321_DATA 0x00000000
+#define DDRSS_PI_322_DATA 0x00000004
+#define DDRSS_PI_323_DATA 0x00000000
+#define DDRSS_PI_324_DATA 0x00000031
+#define DDRSS_PI_325_DATA 0x00000000
+#define DDRSS_PI_326_DATA 0x00000000
+#define DDRSS_PI_327_DATA 0x00000000
+#define DDRSS_PI_328_DATA 0x00100F27
+#define DDRSS_PI_329_DATA 0x00000000
+#define DDRSS_PI_330_DATA 0x00000024
+#define DDRSS_PI_331_DATA 0x00000012
+#define DDRSS_PI_332_DATA 0x000000B1
+#define DDRSS_PI_333_DATA 0x00000000
+#define DDRSS_PI_334_DATA 0x00000000
+#define DDRSS_PI_335_DATA 0x46000000
+#define DDRSS_PI_336_DATA 0x00150F27
+#define DDRSS_PI_337_DATA 0x00000000
+#define DDRSS_PI_338_DATA 0x00000024
+#define DDRSS_PI_339_DATA 0x00000012
+#define DDRSS_PI_340_DATA 0x000000B1
+#define DDRSS_PI_341_DATA 0x00000000
+#define DDRSS_PI_342_DATA 0x00000000
+#define DDRSS_PI_343_DATA 0x46000000
+#define DDRSS_PI_344_DATA 0x00150F27
+#define DDRSS_PHY_0_DATA 0x04F00000
+#define DDRSS_PHY_1_DATA 0x00000000
+#define DDRSS_PHY_2_DATA 0x00030200
+#define DDRSS_PHY_3_DATA 0x00000000
+#define DDRSS_PHY_4_DATA 0x00000000
+#define DDRSS_PHY_5_DATA 0x01000000
+#define DDRSS_PHY_6_DATA 0x03000400
+#define DDRSS_PHY_7_DATA 0x00000001
+#define DDRSS_PHY_8_DATA 0x00000001
+#define DDRSS_PHY_9_DATA 0x00000000
+#define DDRSS_PHY_10_DATA 0x00000000
+#define DDRSS_PHY_11_DATA 0x01010000
+#define DDRSS_PHY_12_DATA 0x00010000
+#define DDRSS_PHY_13_DATA 0x00C00001
+#define DDRSS_PHY_14_DATA 0x00CC0008
+#define DDRSS_PHY_15_DATA 0x00660601
+#define DDRSS_PHY_16_DATA 0x00000003
+#define DDRSS_PHY_17_DATA 0x00000000
+#define DDRSS_PHY_18_DATA 0x00000000
+#define DDRSS_PHY_19_DATA 0x0000AAAA
+#define DDRSS_PHY_20_DATA 0x00005555
+#define DDRSS_PHY_21_DATA 0x0000B5B5
+#define DDRSS_PHY_22_DATA 0x00004A4A
+#define DDRSS_PHY_23_DATA 0x00005656
+#define DDRSS_PHY_24_DATA 0x0000A9A9
+#define DDRSS_PHY_25_DATA 0x0000B7B7
+#define DDRSS_PHY_26_DATA 0x00004848
+#define DDRSS_PHY_27_DATA 0x00000000
+#define DDRSS_PHY_28_DATA 0x00000000
+#define DDRSS_PHY_29_DATA 0x08000000
+#define DDRSS_PHY_30_DATA 0x0F000008
+#define DDRSS_PHY_31_DATA 0x00000F0F
+#define DDRSS_PHY_32_DATA 0x00E4E400
+#define DDRSS_PHY_33_DATA 0x00071020
+#define DDRSS_PHY_34_DATA 0x000C0020
+#define DDRSS_PHY_35_DATA 0x00062000
+#define DDRSS_PHY_36_DATA 0x00000000
+#define DDRSS_PHY_37_DATA 0x55555555
+#define DDRSS_PHY_38_DATA 0xAAAAAAAA
+#define DDRSS_PHY_39_DATA 0x55555555
+#define DDRSS_PHY_40_DATA 0xAAAAAAAA
+#define DDRSS_PHY_41_DATA 0x00005555
+#define DDRSS_PHY_42_DATA 0x01000100
+#define DDRSS_PHY_43_DATA 0x00800180
+#define DDRSS_PHY_44_DATA 0x00000001
+#define DDRSS_PHY_45_DATA 0x00000000
+#define DDRSS_PHY_46_DATA 0x00000000
+#define DDRSS_PHY_47_DATA 0x00000000
+#define DDRSS_PHY_48_DATA 0x00000000
+#define DDRSS_PHY_49_DATA 0x00000000
+#define DDRSS_PHY_50_DATA 0x00000000
+#define DDRSS_PHY_51_DATA 0x00000000
+#define DDRSS_PHY_52_DATA 0x00000000
+#define DDRSS_PHY_53_DATA 0x00000000
+#define DDRSS_PHY_54_DATA 0x00000000
+#define DDRSS_PHY_55_DATA 0x00000000
+#define DDRSS_PHY_56_DATA 0x00000000
+#define DDRSS_PHY_57_DATA 0x00000000
+#define DDRSS_PHY_58_DATA 0x00000000
+#define DDRSS_PHY_59_DATA 0x00000000
+#define DDRSS_PHY_60_DATA 0x00000000
+#define DDRSS_PHY_61_DATA 0x00000000
+#define DDRSS_PHY_62_DATA 0x00000000
+#define DDRSS_PHY_63_DATA 0x00000000
+#define DDRSS_PHY_64_DATA 0x00000000
+#define DDRSS_PHY_65_DATA 0x00000004
+#define DDRSS_PHY_66_DATA 0x00000000
+#define DDRSS_PHY_67_DATA 0x00000000
+#define DDRSS_PHY_68_DATA 0x00000000
+#define DDRSS_PHY_69_DATA 0x00000000
+#define DDRSS_PHY_70_DATA 0x00000000
+#define DDRSS_PHY_71_DATA 0x00000000
+#define DDRSS_PHY_72_DATA 0x041F07FF
+#define DDRSS_PHY_73_DATA 0x00000000
+#define DDRSS_PHY_74_DATA 0x01CC0B01
+#define DDRSS_PHY_75_DATA 0x1003CC0B
+#define DDRSS_PHY_76_DATA 0x20000140
+#define DDRSS_PHY_77_DATA 0x07FF0200
+#define DDRSS_PHY_78_DATA 0x0000DD01
+#define DDRSS_PHY_79_DATA 0x00100303
+#define DDRSS_PHY_80_DATA 0x00000000
+#define DDRSS_PHY_81_DATA 0x00000000
+#define DDRSS_PHY_82_DATA 0x00021000
+#define DDRSS_PHY_83_DATA 0x00100010
+#define DDRSS_PHY_84_DATA 0x00100010
+#define DDRSS_PHY_85_DATA 0x00100010
+#define DDRSS_PHY_86_DATA 0x00100010
+#define DDRSS_PHY_87_DATA 0x02020010
+#define DDRSS_PHY_88_DATA 0x51516041
+#define DDRSS_PHY_89_DATA 0x31C06000
+#define DDRSS_PHY_90_DATA 0x07AB0340
+#define DDRSS_PHY_91_DATA 0x0000C0C0
+#define DDRSS_PHY_92_DATA 0x04050000
+#define DDRSS_PHY_93_DATA 0x00000504
+#define DDRSS_PHY_94_DATA 0x42100010
+#define DDRSS_PHY_95_DATA 0x010C053E
+#define DDRSS_PHY_96_DATA 0x000F0C1D
+#define DDRSS_PHY_97_DATA 0x01000140
+#define DDRSS_PHY_98_DATA 0x007A0120
+#define DDRSS_PHY_99_DATA 0x00000C00
+#define DDRSS_PHY_100_DATA 0x000001CC
+#define DDRSS_PHY_101_DATA 0x20100200
+#define DDRSS_PHY_102_DATA 0x00000005
+#define DDRSS_PHY_103_DATA 0x76543210
+#define DDRSS_PHY_104_DATA 0x00000008
+#define DDRSS_PHY_105_DATA 0x034C034C
+#define DDRSS_PHY_106_DATA 0x034C034C
+#define DDRSS_PHY_107_DATA 0x034C034C
+#define DDRSS_PHY_108_DATA 0x034C034C
+#define DDRSS_PHY_109_DATA 0x0000034C
+#define DDRSS_PHY_110_DATA 0x00008000
+#define DDRSS_PHY_111_DATA 0x00800080
+#define DDRSS_PHY_112_DATA 0x00800080
+#define DDRSS_PHY_113_DATA 0x00800080
+#define DDRSS_PHY_114_DATA 0x00800080
+#define DDRSS_PHY_115_DATA 0x00800080
+#define DDRSS_PHY_116_DATA 0x00800080
+#define DDRSS_PHY_117_DATA 0x00800080
+#define DDRSS_PHY_118_DATA 0x00800080
+#define DDRSS_PHY_119_DATA 0x01800080
+#define DDRSS_PHY_120_DATA 0x01000000
+#define DDRSS_PHY_121_DATA 0x00000000
+#define DDRSS_PHY_122_DATA 0x00000000
+#define DDRSS_PHY_123_DATA 0x00080200
+#define DDRSS_PHY_124_DATA 0x00000000
+#define DDRSS_PHY_125_DATA 0x0000F0F0
+#define DDRSS_PHY_126_DATA 0x00000000
+#define DDRSS_PHY_127_DATA 0x00000000
+#define DDRSS_PHY_128_DATA 0x00000000
+#define DDRSS_PHY_129_DATA 0x00000000
+#define DDRSS_PHY_130_DATA 0x00000000
+#define DDRSS_PHY_131_DATA 0x00000000
+#define DDRSS_PHY_132_DATA 0x00000000
+#define DDRSS_PHY_133_DATA 0x00000000
+#define DDRSS_PHY_134_DATA 0x00000000
+#define DDRSS_PHY_135_DATA 0x00000000
+#define DDRSS_PHY_136_DATA 0x00000000
+#define DDRSS_PHY_137_DATA 0x00000000
+#define DDRSS_PHY_138_DATA 0x00000000
+#define DDRSS_PHY_139_DATA 0x00000000
+#define DDRSS_PHY_140_DATA 0x00000000
+#define DDRSS_PHY_141_DATA 0x00000000
+#define DDRSS_PHY_142_DATA 0x00000000
+#define DDRSS_PHY_143_DATA 0x00000000
+#define DDRSS_PHY_144_DATA 0x00000000
+#define DDRSS_PHY_145_DATA 0x00000000
+#define DDRSS_PHY_146_DATA 0x00000000
+#define DDRSS_PHY_147_DATA 0x00000000
+#define DDRSS_PHY_148_DATA 0x00000000
+#define DDRSS_PHY_149_DATA 0x00000000
+#define DDRSS_PHY_150_DATA 0x00000000
+#define DDRSS_PHY_151_DATA 0x00000000
+#define DDRSS_PHY_152_DATA 0x00000000
+#define DDRSS_PHY_153_DATA 0x00000000
+#define DDRSS_PHY_154_DATA 0x00000000
+#define DDRSS_PHY_155_DATA 0x00000000
+#define DDRSS_PHY_156_DATA 0x00000000
+#define DDRSS_PHY_157_DATA 0x00000000
+#define DDRSS_PHY_158_DATA 0x00000000
+#define DDRSS_PHY_159_DATA 0x00000000
+#define DDRSS_PHY_160_DATA 0x00000000
+#define DDRSS_PHY_161_DATA 0x00000000
+#define DDRSS_PHY_162_DATA 0x00000000
+#define DDRSS_PHY_163_DATA 0x00000000
+#define DDRSS_PHY_164_DATA 0x00000000
+#define DDRSS_PHY_165_DATA 0x00000000
+#define DDRSS_PHY_166_DATA 0x00000000
+#define DDRSS_PHY_167_DATA 0x00000000
+#define DDRSS_PHY_168_DATA 0x00000000
+#define DDRSS_PHY_169_DATA 0x00000000
+#define DDRSS_PHY_170_DATA 0x00000000
+#define DDRSS_PHY_171_DATA 0x00000000
+#define DDRSS_PHY_172_DATA 0x00000000
+#define DDRSS_PHY_173_DATA 0x00000000
+#define DDRSS_PHY_174_DATA 0x00000000
+#define DDRSS_PHY_175_DATA 0x00000000
+#define DDRSS_PHY_176_DATA 0x00000000
+#define DDRSS_PHY_177_DATA 0x00000000
+#define DDRSS_PHY_178_DATA 0x00000000
+#define DDRSS_PHY_179_DATA 0x00000000
+#define DDRSS_PHY_180_DATA 0x00000000
+#define DDRSS_PHY_181_DATA 0x00000000
+#define DDRSS_PHY_182_DATA 0x00000000
+#define DDRSS_PHY_183_DATA 0x00000000
+#define DDRSS_PHY_184_DATA 0x00000000
+#define DDRSS_PHY_185_DATA 0x00000000
+#define DDRSS_PHY_186_DATA 0x00000000
+#define DDRSS_PHY_187_DATA 0x00000000
+#define DDRSS_PHY_188_DATA 0x00000000
+#define DDRSS_PHY_189_DATA 0x00000000
+#define DDRSS_PHY_190_DATA 0x00000000
+#define DDRSS_PHY_191_DATA 0x00000000
+#define DDRSS_PHY_192_DATA 0x00000000
+#define DDRSS_PHY_193_DATA 0x00000000
+#define DDRSS_PHY_194_DATA 0x00000000
+#define DDRSS_PHY_195_DATA 0x00000000
+#define DDRSS_PHY_196_DATA 0x00000000
+#define DDRSS_PHY_197_DATA 0x00000000
+#define DDRSS_PHY_198_DATA 0x00000000
+#define DDRSS_PHY_199_DATA 0x00000000
+#define DDRSS_PHY_200_DATA 0x00000000
+#define DDRSS_PHY_201_DATA 0x00000000
+#define DDRSS_PHY_202_DATA 0x00000000
+#define DDRSS_PHY_203_DATA 0x00000000
+#define DDRSS_PHY_204_DATA 0x00000000
+#define DDRSS_PHY_205_DATA 0x00000000
+#define DDRSS_PHY_206_DATA 0x00000000
+#define DDRSS_PHY_207_DATA 0x00000000
+#define DDRSS_PHY_208_DATA 0x00000000
+#define DDRSS_PHY_209_DATA 0x00000000
+#define DDRSS_PHY_210_DATA 0x00000000
+#define DDRSS_PHY_211_DATA 0x00000000
+#define DDRSS_PHY_212_DATA 0x00000000
+#define DDRSS_PHY_213_DATA 0x00000000
+#define DDRSS_PHY_214_DATA 0x00000000
+#define DDRSS_PHY_215_DATA 0x00000000
+#define DDRSS_PHY_216_DATA 0x00000000
+#define DDRSS_PHY_217_DATA 0x00000000
+#define DDRSS_PHY_218_DATA 0x00000000
+#define DDRSS_PHY_219_DATA 0x00000000
+#define DDRSS_PHY_220_DATA 0x00000000
+#define DDRSS_PHY_221_DATA 0x00000000
+#define DDRSS_PHY_222_DATA 0x00000000
+#define DDRSS_PHY_223_DATA 0x00000000
+#define DDRSS_PHY_224_DATA 0x00000000
+#define DDRSS_PHY_225_DATA 0x00000000
+#define DDRSS_PHY_226_DATA 0x00000000
+#define DDRSS_PHY_227_DATA 0x00000000
+#define DDRSS_PHY_228_DATA 0x00000000
+#define DDRSS_PHY_229_DATA 0x00000000
+#define DDRSS_PHY_230_DATA 0x00000000
+#define DDRSS_PHY_231_DATA 0x00000000
+#define DDRSS_PHY_232_DATA 0x00000000
+#define DDRSS_PHY_233_DATA 0x00000000
+#define DDRSS_PHY_234_DATA 0x00000000
+#define DDRSS_PHY_235_DATA 0x00000000
+#define DDRSS_PHY_236_DATA 0x00000000
+#define DDRSS_PHY_237_DATA 0x00000000
+#define DDRSS_PHY_238_DATA 0x00000000
+#define DDRSS_PHY_239_DATA 0x00000000
+#define DDRSS_PHY_240_DATA 0x00000000
+#define DDRSS_PHY_241_DATA 0x00000000
+#define DDRSS_PHY_242_DATA 0x00000000
+#define DDRSS_PHY_243_DATA 0x00000000
+#define DDRSS_PHY_244_DATA 0x00000000
+#define DDRSS_PHY_245_DATA 0x00000000
+#define DDRSS_PHY_246_DATA 0x00000000
+#define DDRSS_PHY_247_DATA 0x00000000
+#define DDRSS_PHY_248_DATA 0x00000000
+#define DDRSS_PHY_249_DATA 0x00000000
+#define DDRSS_PHY_250_DATA 0x00000000
+#define DDRSS_PHY_251_DATA 0x00000000
+#define DDRSS_PHY_252_DATA 0x00000000
+#define DDRSS_PHY_253_DATA 0x00000000
+#define DDRSS_PHY_254_DATA 0x00000000
+#define DDRSS_PHY_255_DATA 0x00000000
+#define DDRSS_PHY_256_DATA 0x04F00000
+#define DDRSS_PHY_257_DATA 0x00000000
+#define DDRSS_PHY_258_DATA 0x00030200
+#define DDRSS_PHY_259_DATA 0x00000000
+#define DDRSS_PHY_260_DATA 0x00000000
+#define DDRSS_PHY_261_DATA 0x01000000
+#define DDRSS_PHY_262_DATA 0x03000400
+#define DDRSS_PHY_263_DATA 0x00000001
+#define DDRSS_PHY_264_DATA 0x00000001
+#define DDRSS_PHY_265_DATA 0x00000000
+#define DDRSS_PHY_266_DATA 0x00000000
+#define DDRSS_PHY_267_DATA 0x01010000
+#define DDRSS_PHY_268_DATA 0x00010000
+#define DDRSS_PHY_269_DATA 0x00C00001
+#define DDRSS_PHY_270_DATA 0x00CC0008
+#define DDRSS_PHY_271_DATA 0x00660601
+#define DDRSS_PHY_272_DATA 0x00000003
+#define DDRSS_PHY_273_DATA 0x00000000
+#define DDRSS_PHY_274_DATA 0x00000000
+#define DDRSS_PHY_275_DATA 0x0000AAAA
+#define DDRSS_PHY_276_DATA 0x00005555
+#define DDRSS_PHY_277_DATA 0x0000B5B5
+#define DDRSS_PHY_278_DATA 0x00004A4A
+#define DDRSS_PHY_279_DATA 0x00005656
+#define DDRSS_PHY_280_DATA 0x0000A9A9
+#define DDRSS_PHY_281_DATA 0x0000B7B7
+#define DDRSS_PHY_282_DATA 0x00004848
+#define DDRSS_PHY_283_DATA 0x00000000
+#define DDRSS_PHY_284_DATA 0x00000000
+#define DDRSS_PHY_285_DATA 0x08000000
+#define DDRSS_PHY_286_DATA 0x0F000008
+#define DDRSS_PHY_287_DATA 0x00000F0F
+#define DDRSS_PHY_288_DATA 0x00E4E400
+#define DDRSS_PHY_289_DATA 0x00071020
+#define DDRSS_PHY_290_DATA 0x000C0020
+#define DDRSS_PHY_291_DATA 0x00062000
+#define DDRSS_PHY_292_DATA 0x00000000
+#define DDRSS_PHY_293_DATA 0x55555555
+#define DDRSS_PHY_294_DATA 0xAAAAAAAA
+#define DDRSS_PHY_295_DATA 0x55555555
+#define DDRSS_PHY_296_DATA 0xAAAAAAAA
+#define DDRSS_PHY_297_DATA 0x00005555
+#define DDRSS_PHY_298_DATA 0x01000100
+#define DDRSS_PHY_299_DATA 0x00800180
+#define DDRSS_PHY_300_DATA 0x00000000
+#define DDRSS_PHY_301_DATA 0x00000000
+#define DDRSS_PHY_302_DATA 0x00000000
+#define DDRSS_PHY_303_DATA 0x00000000
+#define DDRSS_PHY_304_DATA 0x00000000
+#define DDRSS_PHY_305_DATA 0x00000000
+#define DDRSS_PHY_306_DATA 0x00000000
+#define DDRSS_PHY_307_DATA 0x00000000
+#define DDRSS_PHY_308_DATA 0x00000000
+#define DDRSS_PHY_309_DATA 0x00000000
+#define DDRSS_PHY_310_DATA 0x00000000
+#define DDRSS_PHY_311_DATA 0x00000000
+#define DDRSS_PHY_312_DATA 0x00000000
+#define DDRSS_PHY_313_DATA 0x00000000
+#define DDRSS_PHY_314_DATA 0x00000000
+#define DDRSS_PHY_315_DATA 0x00000000
+#define DDRSS_PHY_316_DATA 0x00000000
+#define DDRSS_PHY_317_DATA 0x00000000
+#define DDRSS_PHY_318_DATA 0x00000000
+#define DDRSS_PHY_319_DATA 0x00000000
+#define DDRSS_PHY_320_DATA 0x00000000
+#define DDRSS_PHY_321_DATA 0x00000004
+#define DDRSS_PHY_322_DATA 0x00000000
+#define DDRSS_PHY_323_DATA 0x00000000
+#define DDRSS_PHY_324_DATA 0x00000000
+#define DDRSS_PHY_325_DATA 0x00000000
+#define DDRSS_PHY_326_DATA 0x00000000
+#define DDRSS_PHY_327_DATA 0x00000000
+#define DDRSS_PHY_328_DATA 0x041F07FF
+#define DDRSS_PHY_329_DATA 0x00000000
+#define DDRSS_PHY_330_DATA 0x01CC0B01
+#define DDRSS_PHY_331_DATA 0x1003CC0B
+#define DDRSS_PHY_332_DATA 0x20000140
+#define DDRSS_PHY_333_DATA 0x07FF0200
+#define DDRSS_PHY_334_DATA 0x0000DD01
+#define DDRSS_PHY_335_DATA 0x00100303
+#define DDRSS_PHY_336_DATA 0x00000000
+#define DDRSS_PHY_337_DATA 0x00000000
+#define DDRSS_PHY_338_DATA 0x00021000
+#define DDRSS_PHY_339_DATA 0x00100010
+#define DDRSS_PHY_340_DATA 0x00100010
+#define DDRSS_PHY_341_DATA 0x00100010
+#define DDRSS_PHY_342_DATA 0x00100010
+#define DDRSS_PHY_343_DATA 0x02020010
+#define DDRSS_PHY_344_DATA 0x51516041
+#define DDRSS_PHY_345_DATA 0x31C06000
+#define DDRSS_PHY_346_DATA 0x07AB0340
+#define DDRSS_PHY_347_DATA 0x0000C0C0
+#define DDRSS_PHY_348_DATA 0x04050000
+#define DDRSS_PHY_349_DATA 0x00000504
+#define DDRSS_PHY_350_DATA 0x42100010
+#define DDRSS_PHY_351_DATA 0x010C053E
+#define DDRSS_PHY_352_DATA 0x000F0C1D
+#define DDRSS_PHY_353_DATA 0x01000140
+#define DDRSS_PHY_354_DATA 0x007A0120
+#define DDRSS_PHY_355_DATA 0x00000C00
+#define DDRSS_PHY_356_DATA 0x000001CC
+#define DDRSS_PHY_357_DATA 0x20100200
+#define DDRSS_PHY_358_DATA 0x00000005
+#define DDRSS_PHY_359_DATA 0x76543210
+#define DDRSS_PHY_360_DATA 0x00000008
+#define DDRSS_PHY_361_DATA 0x034C034C
+#define DDRSS_PHY_362_DATA 0x034C034C
+#define DDRSS_PHY_363_DATA 0x034C034C
+#define DDRSS_PHY_364_DATA 0x034C034C
+#define DDRSS_PHY_365_DATA 0x0000034C
+#define DDRSS_PHY_366_DATA 0x00008000
+#define DDRSS_PHY_367_DATA 0x00800080
+#define DDRSS_PHY_368_DATA 0x00800080
+#define DDRSS_PHY_369_DATA 0x00800080
+#define DDRSS_PHY_370_DATA 0x00800080
+#define DDRSS_PHY_371_DATA 0x00800080
+#define DDRSS_PHY_372_DATA 0x00800080
+#define DDRSS_PHY_373_DATA 0x00800080
+#define DDRSS_PHY_374_DATA 0x00800080
+#define DDRSS_PHY_375_DATA 0x01800080
+#define DDRSS_PHY_376_DATA 0x01000000
+#define DDRSS_PHY_377_DATA 0x00000000
+#define DDRSS_PHY_378_DATA 0x00000000
+#define DDRSS_PHY_379_DATA 0x00080200
+#define DDRSS_PHY_380_DATA 0x00000000
+#define DDRSS_PHY_381_DATA 0x0000F0F0
+#define DDRSS_PHY_382_DATA 0x00000000
+#define DDRSS_PHY_383_DATA 0x00000000
+#define DDRSS_PHY_384_DATA 0x00000000
+#define DDRSS_PHY_385_DATA 0x00000000
+#define DDRSS_PHY_386_DATA 0x00000000
+#define DDRSS_PHY_387_DATA 0x00000000
+#define DDRSS_PHY_388_DATA 0x00000000
+#define DDRSS_PHY_389_DATA 0x00000000
+#define DDRSS_PHY_390_DATA 0x00000000
+#define DDRSS_PHY_391_DATA 0x00000000
+#define DDRSS_PHY_392_DATA 0x00000000
+#define DDRSS_PHY_393_DATA 0x00000000
+#define DDRSS_PHY_394_DATA 0x00000000
+#define DDRSS_PHY_395_DATA 0x00000000
+#define DDRSS_PHY_396_DATA 0x00000000
+#define DDRSS_PHY_397_DATA 0x00000000
+#define DDRSS_PHY_398_DATA 0x00000000
+#define DDRSS_PHY_399_DATA 0x00000000
+#define DDRSS_PHY_400_DATA 0x00000000
+#define DDRSS_PHY_401_DATA 0x00000000
+#define DDRSS_PHY_402_DATA 0x00000000
+#define DDRSS_PHY_403_DATA 0x00000000
+#define DDRSS_PHY_404_DATA 0x00000000
+#define DDRSS_PHY_405_DATA 0x00000000
+#define DDRSS_PHY_406_DATA 0x00000000
+#define DDRSS_PHY_407_DATA 0x00000000
+#define DDRSS_PHY_408_DATA 0x00000000
+#define DDRSS_PHY_409_DATA 0x00000000
+#define DDRSS_PHY_410_DATA 0x00000000
+#define DDRSS_PHY_411_DATA 0x00000000
+#define DDRSS_PHY_412_DATA 0x00000000
+#define DDRSS_PHY_413_DATA 0x00000000
+#define DDRSS_PHY_414_DATA 0x00000000
+#define DDRSS_PHY_415_DATA 0x00000000
+#define DDRSS_PHY_416_DATA 0x00000000
+#define DDRSS_PHY_417_DATA 0x00000000
+#define DDRSS_PHY_418_DATA 0x00000000
+#define DDRSS_PHY_419_DATA 0x00000000
+#define DDRSS_PHY_420_DATA 0x00000000
+#define DDRSS_PHY_421_DATA 0x00000000
+#define DDRSS_PHY_422_DATA 0x00000000
+#define DDRSS_PHY_423_DATA 0x00000000
+#define DDRSS_PHY_424_DATA 0x00000000
+#define DDRSS_PHY_425_DATA 0x00000000
+#define DDRSS_PHY_426_DATA 0x00000000
+#define DDRSS_PHY_427_DATA 0x00000000
+#define DDRSS_PHY_428_DATA 0x00000000
+#define DDRSS_PHY_429_DATA 0x00000000
+#define DDRSS_PHY_430_DATA 0x00000000
+#define DDRSS_PHY_431_DATA 0x00000000
+#define DDRSS_PHY_432_DATA 0x00000000
+#define DDRSS_PHY_433_DATA 0x00000000
+#define DDRSS_PHY_434_DATA 0x00000000
+#define DDRSS_PHY_435_DATA 0x00000000
+#define DDRSS_PHY_436_DATA 0x00000000
+#define DDRSS_PHY_437_DATA 0x00000000
+#define DDRSS_PHY_438_DATA 0x00000000
+#define DDRSS_PHY_439_DATA 0x00000000
+#define DDRSS_PHY_440_DATA 0x00000000
+#define DDRSS_PHY_441_DATA 0x00000000
+#define DDRSS_PHY_442_DATA 0x00000000
+#define DDRSS_PHY_443_DATA 0x00000000
+#define DDRSS_PHY_444_DATA 0x00000000
+#define DDRSS_PHY_445_DATA 0x00000000
+#define DDRSS_PHY_446_DATA 0x00000000
+#define DDRSS_PHY_447_DATA 0x00000000
+#define DDRSS_PHY_448_DATA 0x00000000
+#define DDRSS_PHY_449_DATA 0x00000000
+#define DDRSS_PHY_450_DATA 0x00000000
+#define DDRSS_PHY_451_DATA 0x00000000
+#define DDRSS_PHY_452_DATA 0x00000000
+#define DDRSS_PHY_453_DATA 0x00000000
+#define DDRSS_PHY_454_DATA 0x00000000
+#define DDRSS_PHY_455_DATA 0x00000000
+#define DDRSS_PHY_456_DATA 0x00000000
+#define DDRSS_PHY_457_DATA 0x00000000
+#define DDRSS_PHY_458_DATA 0x00000000
+#define DDRSS_PHY_459_DATA 0x00000000
+#define DDRSS_PHY_460_DATA 0x00000000
+#define DDRSS_PHY_461_DATA 0x00000000
+#define DDRSS_PHY_462_DATA 0x00000000
+#define DDRSS_PHY_463_DATA 0x00000000
+#define DDRSS_PHY_464_DATA 0x00000000
+#define DDRSS_PHY_465_DATA 0x00000000
+#define DDRSS_PHY_466_DATA 0x00000000
+#define DDRSS_PHY_467_DATA 0x00000000
+#define DDRSS_PHY_468_DATA 0x00000000
+#define DDRSS_PHY_469_DATA 0x00000000
+#define DDRSS_PHY_470_DATA 0x00000000
+#define DDRSS_PHY_471_DATA 0x00000000
+#define DDRSS_PHY_472_DATA 0x00000000
+#define DDRSS_PHY_473_DATA 0x00000000
+#define DDRSS_PHY_474_DATA 0x00000000
+#define DDRSS_PHY_475_DATA 0x00000000
+#define DDRSS_PHY_476_DATA 0x00000000
+#define DDRSS_PHY_477_DATA 0x00000000
+#define DDRSS_PHY_478_DATA 0x00000000
+#define DDRSS_PHY_479_DATA 0x00000000
+#define DDRSS_PHY_480_DATA 0x00000000
+#define DDRSS_PHY_481_DATA 0x00000000
+#define DDRSS_PHY_482_DATA 0x00000000
+#define DDRSS_PHY_483_DATA 0x00000000
+#define DDRSS_PHY_484_DATA 0x00000000
+#define DDRSS_PHY_485_DATA 0x00000000
+#define DDRSS_PHY_486_DATA 0x00000000
+#define DDRSS_PHY_487_DATA 0x00000000
+#define DDRSS_PHY_488_DATA 0x00000000
+#define DDRSS_PHY_489_DATA 0x00000000
+#define DDRSS_PHY_490_DATA 0x00000000
+#define DDRSS_PHY_491_DATA 0x00000000
+#define DDRSS_PHY_492_DATA 0x00000000
+#define DDRSS_PHY_493_DATA 0x00000000
+#define DDRSS_PHY_494_DATA 0x00000000
+#define DDRSS_PHY_495_DATA 0x00000000
+#define DDRSS_PHY_496_DATA 0x00000000
+#define DDRSS_PHY_497_DATA 0x00000000
+#define DDRSS_PHY_498_DATA 0x00000000
+#define DDRSS_PHY_499_DATA 0x00000000
+#define DDRSS_PHY_500_DATA 0x00000000
+#define DDRSS_PHY_501_DATA 0x00000000
+#define DDRSS_PHY_502_DATA 0x00000000
+#define DDRSS_PHY_503_DATA 0x00000000
+#define DDRSS_PHY_504_DATA 0x00000000
+#define DDRSS_PHY_505_DATA 0x00000000
+#define DDRSS_PHY_506_DATA 0x00000000
+#define DDRSS_PHY_507_DATA 0x00000000
+#define DDRSS_PHY_508_DATA 0x00000000
+#define DDRSS_PHY_509_DATA 0x00000000
+#define DDRSS_PHY_510_DATA 0x00000000
+#define DDRSS_PHY_511_DATA 0x00000000
+#define DDRSS_PHY_512_DATA 0x00000000
+#define DDRSS_PHY_513_DATA 0x00000000
+#define DDRSS_PHY_514_DATA 0x00000000
+#define DDRSS_PHY_515_DATA 0x00000000
+#define DDRSS_PHY_516_DATA 0x00000000
+#define DDRSS_PHY_517_DATA 0x00000100
+#define DDRSS_PHY_518_DATA 0x00000200
+#define DDRSS_PHY_519_DATA 0x00000000
+#define DDRSS_PHY_520_DATA 0x00000000
+#define DDRSS_PHY_521_DATA 0x00000000
+#define DDRSS_PHY_522_DATA 0x00000000
+#define DDRSS_PHY_523_DATA 0x00400000
+#define DDRSS_PHY_524_DATA 0x00000080
+#define DDRSS_PHY_525_DATA 0x00DCBA98
+#define DDRSS_PHY_526_DATA 0x03000000
+#define DDRSS_PHY_527_DATA 0x00200000
+#define DDRSS_PHY_528_DATA 0x00000000
+#define DDRSS_PHY_529_DATA 0x00000000
+#define DDRSS_PHY_530_DATA 0x00000000
+#define DDRSS_PHY_531_DATA 0x00000000
+#define DDRSS_PHY_532_DATA 0x0000002A
+#define DDRSS_PHY_533_DATA 0x00000015
+#define DDRSS_PHY_534_DATA 0x00000015
+#define DDRSS_PHY_535_DATA 0x0000002A
+#define DDRSS_PHY_536_DATA 0x00000033
+#define DDRSS_PHY_537_DATA 0x0000000C
+#define DDRSS_PHY_538_DATA 0x0000000C
+#define DDRSS_PHY_539_DATA 0x00000033
+#define DDRSS_PHY_540_DATA 0x0A418820
+#define DDRSS_PHY_541_DATA 0x003F0000
+#define DDRSS_PHY_542_DATA 0x000F013F
+#define DDRSS_PHY_543_DATA 0x0000000F
+#define DDRSS_PHY_544_DATA 0x020002CC
+#define DDRSS_PHY_545_DATA 0x00030000
+#define DDRSS_PHY_546_DATA 0x00000300
+#define DDRSS_PHY_547_DATA 0x00000300
+#define DDRSS_PHY_548_DATA 0x00000300
+#define DDRSS_PHY_549_DATA 0x00000300
+#define DDRSS_PHY_550_DATA 0x00000300
+#define DDRSS_PHY_551_DATA 0x42080010
+#define DDRSS_PHY_552_DATA 0x0000803E
+#define DDRSS_PHY_553_DATA 0x00000003
+#define DDRSS_PHY_554_DATA 0x00000002
+#define DDRSS_PHY_555_DATA 0x00000000
+#define DDRSS_PHY_556_DATA 0x00000000
+#define DDRSS_PHY_557_DATA 0x00000000
+#define DDRSS_PHY_558_DATA 0x00000000
+#define DDRSS_PHY_559_DATA 0x00000000
+#define DDRSS_PHY_560_DATA 0x00000000
+#define DDRSS_PHY_561_DATA 0x00000000
+#define DDRSS_PHY_562_DATA 0x00000000
+#define DDRSS_PHY_563_DATA 0x00000000
+#define DDRSS_PHY_564_DATA 0x00000000
+#define DDRSS_PHY_565_DATA 0x00000000
+#define DDRSS_PHY_566_DATA 0x00000000
+#define DDRSS_PHY_567_DATA 0x00000000
+#define DDRSS_PHY_568_DATA 0x00000000
+#define DDRSS_PHY_569_DATA 0x00000000
+#define DDRSS_PHY_570_DATA 0x00000000
+#define DDRSS_PHY_571_DATA 0x00000000
+#define DDRSS_PHY_572_DATA 0x00000000
+#define DDRSS_PHY_573_DATA 0x00000000
+#define DDRSS_PHY_574_DATA 0x00000000
+#define DDRSS_PHY_575_DATA 0x00000000
+#define DDRSS_PHY_576_DATA 0x00000000
+#define DDRSS_PHY_577_DATA 0x00000000
+#define DDRSS_PHY_578_DATA 0x00000000
+#define DDRSS_PHY_579_DATA 0x00000000
+#define DDRSS_PHY_580_DATA 0x00000000
+#define DDRSS_PHY_581_DATA 0x00000000
+#define DDRSS_PHY_582_DATA 0x00000000
+#define DDRSS_PHY_583_DATA 0x00000000
+#define DDRSS_PHY_584_DATA 0x00000000
+#define DDRSS_PHY_585_DATA 0x00000000
+#define DDRSS_PHY_586_DATA 0x00000000
+#define DDRSS_PHY_587_DATA 0x00000000
+#define DDRSS_PHY_588_DATA 0x00000000
+#define DDRSS_PHY_589_DATA 0x00000000
+#define DDRSS_PHY_590_DATA 0x00000000
+#define DDRSS_PHY_591_DATA 0x00000000
+#define DDRSS_PHY_592_DATA 0x00000000
+#define DDRSS_PHY_593_DATA 0x00000000
+#define DDRSS_PHY_594_DATA 0x00000000
+#define DDRSS_PHY_595_DATA 0x00000000
+#define DDRSS_PHY_596_DATA 0x00000000
+#define DDRSS_PHY_597_DATA 0x00000000
+#define DDRSS_PHY_598_DATA 0x00000000
+#define DDRSS_PHY_599_DATA 0x00000000
+#define DDRSS_PHY_600_DATA 0x00000000
+#define DDRSS_PHY_601_DATA 0x00000000
+#define DDRSS_PHY_602_DATA 0x00000000
+#define DDRSS_PHY_603_DATA 0x00000000
+#define DDRSS_PHY_604_DATA 0x00000000
+#define DDRSS_PHY_605_DATA 0x00000000
+#define DDRSS_PHY_606_DATA 0x00000000
+#define DDRSS_PHY_607_DATA 0x00000000
+#define DDRSS_PHY_608_DATA 0x00000000
+#define DDRSS_PHY_609_DATA 0x00000000
+#define DDRSS_PHY_610_DATA 0x00000000
+#define DDRSS_PHY_611_DATA 0x00000000
+#define DDRSS_PHY_612_DATA 0x00000000
+#define DDRSS_PHY_613_DATA 0x00000000
+#define DDRSS_PHY_614_DATA 0x00000000
+#define DDRSS_PHY_615_DATA 0x00000000
+#define DDRSS_PHY_616_DATA 0x00000000
+#define DDRSS_PHY_617_DATA 0x00000000
+#define DDRSS_PHY_618_DATA 0x00000000
+#define DDRSS_PHY_619_DATA 0x00000000
+#define DDRSS_PHY_620_DATA 0x00000000
+#define DDRSS_PHY_621_DATA 0x00000000
+#define DDRSS_PHY_622_DATA 0x00000000
+#define DDRSS_PHY_623_DATA 0x00000000
+#define DDRSS_PHY_624_DATA 0x00000000
+#define DDRSS_PHY_625_DATA 0x00000000
+#define DDRSS_PHY_626_DATA 0x00000000
+#define DDRSS_PHY_627_DATA 0x00000000
+#define DDRSS_PHY_628_DATA 0x00000000
+#define DDRSS_PHY_629_DATA 0x00000000
+#define DDRSS_PHY_630_DATA 0x00000000
+#define DDRSS_PHY_631_DATA 0x00000000
+#define DDRSS_PHY_632_DATA 0x00000000
+#define DDRSS_PHY_633_DATA 0x00000000
+#define DDRSS_PHY_634_DATA 0x00000000
+#define DDRSS_PHY_635_DATA 0x00000000
+#define DDRSS_PHY_636_DATA 0x00000000
+#define DDRSS_PHY_637_DATA 0x00000000
+#define DDRSS_PHY_638_DATA 0x00000000
+#define DDRSS_PHY_639_DATA 0x00000000
+#define DDRSS_PHY_640_DATA 0x00000000
+#define DDRSS_PHY_641_DATA 0x00000000
+#define DDRSS_PHY_642_DATA 0x00000000
+#define DDRSS_PHY_643_DATA 0x00000000
+#define DDRSS_PHY_644_DATA 0x00000000
+#define DDRSS_PHY_645_DATA 0x00000000
+#define DDRSS_PHY_646_DATA 0x00000000
+#define DDRSS_PHY_647_DATA 0x00000000
+#define DDRSS_PHY_648_DATA 0x00000000
+#define DDRSS_PHY_649_DATA 0x00000000
+#define DDRSS_PHY_650_DATA 0x00000000
+#define DDRSS_PHY_651_DATA 0x00000000
+#define DDRSS_PHY_652_DATA 0x00000000
+#define DDRSS_PHY_653_DATA 0x00000000
+#define DDRSS_PHY_654_DATA 0x00000000
+#define DDRSS_PHY_655_DATA 0x00000000
+#define DDRSS_PHY_656_DATA 0x00000000
+#define DDRSS_PHY_657_DATA 0x00000000
+#define DDRSS_PHY_658_DATA 0x00000000
+#define DDRSS_PHY_659_DATA 0x00000000
+#define DDRSS_PHY_660_DATA 0x00000000
+#define DDRSS_PHY_661_DATA 0x00000000
+#define DDRSS_PHY_662_DATA 0x00000000
+#define DDRSS_PHY_663_DATA 0x00000000
+#define DDRSS_PHY_664_DATA 0x00000000
+#define DDRSS_PHY_665_DATA 0x00000000
+#define DDRSS_PHY_666_DATA 0x00000000
+#define DDRSS_PHY_667_DATA 0x00000000
+#define DDRSS_PHY_668_DATA 0x00000000
+#define DDRSS_PHY_669_DATA 0x00000000
+#define DDRSS_PHY_670_DATA 0x00000000
+#define DDRSS_PHY_671_DATA 0x00000000
+#define DDRSS_PHY_672_DATA 0x00000000
+#define DDRSS_PHY_673_DATA 0x00000000
+#define DDRSS_PHY_674_DATA 0x00000000
+#define DDRSS_PHY_675_DATA 0x00000000
+#define DDRSS_PHY_676_DATA 0x00000000
+#define DDRSS_PHY_677_DATA 0x00000000
+#define DDRSS_PHY_678_DATA 0x00000000
+#define DDRSS_PHY_679_DATA 0x00000000
+#define DDRSS_PHY_680_DATA 0x00000000
+#define DDRSS_PHY_681_DATA 0x00000000
+#define DDRSS_PHY_682_DATA 0x00000000
+#define DDRSS_PHY_683_DATA 0x00000000
+#define DDRSS_PHY_684_DATA 0x00000000
+#define DDRSS_PHY_685_DATA 0x00000000
+#define DDRSS_PHY_686_DATA 0x00000000
+#define DDRSS_PHY_687_DATA 0x00000000
+#define DDRSS_PHY_688_DATA 0x00000000
+#define DDRSS_PHY_689_DATA 0x00000000
+#define DDRSS_PHY_690_DATA 0x00000000
+#define DDRSS_PHY_691_DATA 0x00000000
+#define DDRSS_PHY_692_DATA 0x00000000
+#define DDRSS_PHY_693_DATA 0x00000000
+#define DDRSS_PHY_694_DATA 0x00000000
+#define DDRSS_PHY_695_DATA 0x00000000
+#define DDRSS_PHY_696_DATA 0x00000000
+#define DDRSS_PHY_697_DATA 0x00000000
+#define DDRSS_PHY_698_DATA 0x00000000
+#define DDRSS_PHY_699_DATA 0x00000000
+#define DDRSS_PHY_700_DATA 0x00000000
+#define DDRSS_PHY_701_DATA 0x00000000
+#define DDRSS_PHY_702_DATA 0x00000000
+#define DDRSS_PHY_703_DATA 0x00000000
+#define DDRSS_PHY_704_DATA 0x00000000
+#define DDRSS_PHY_705_DATA 0x00000000
+#define DDRSS_PHY_706_DATA 0x00000000
+#define DDRSS_PHY_707_DATA 0x00000000
+#define DDRSS_PHY_708_DATA 0x00000000
+#define DDRSS_PHY_709_DATA 0x00000000
+#define DDRSS_PHY_710_DATA 0x00000000
+#define DDRSS_PHY_711_DATA 0x00000000
+#define DDRSS_PHY_712_DATA 0x00000000
+#define DDRSS_PHY_713_DATA 0x00000000
+#define DDRSS_PHY_714_DATA 0x00000000
+#define DDRSS_PHY_715_DATA 0x00000000
+#define DDRSS_PHY_716_DATA 0x00000000
+#define DDRSS_PHY_717_DATA 0x00000000
+#define DDRSS_PHY_718_DATA 0x00000000
+#define DDRSS_PHY_719_DATA 0x00000000
+#define DDRSS_PHY_720_DATA 0x00000000
+#define DDRSS_PHY_721_DATA 0x00000000
+#define DDRSS_PHY_722_DATA 0x00000000
+#define DDRSS_PHY_723_DATA 0x00000000
+#define DDRSS_PHY_724_DATA 0x00000000
+#define DDRSS_PHY_725_DATA 0x00000000
+#define DDRSS_PHY_726_DATA 0x00000000
+#define DDRSS_PHY_727_DATA 0x00000000
+#define DDRSS_PHY_728_DATA 0x00000000
+#define DDRSS_PHY_729_DATA 0x00000000
+#define DDRSS_PHY_730_DATA 0x00000000
+#define DDRSS_PHY_731_DATA 0x00000000
+#define DDRSS_PHY_732_DATA 0x00000000
+#define DDRSS_PHY_733_DATA 0x00000000
+#define DDRSS_PHY_734_DATA 0x00000000
+#define DDRSS_PHY_735_DATA 0x00000000
+#define DDRSS_PHY_736_DATA 0x00000000
+#define DDRSS_PHY_737_DATA 0x00000000
+#define DDRSS_PHY_738_DATA 0x00000000
+#define DDRSS_PHY_739_DATA 0x00000000
+#define DDRSS_PHY_740_DATA 0x00000000
+#define DDRSS_PHY_741_DATA 0x00000000
+#define DDRSS_PHY_742_DATA 0x00000000
+#define DDRSS_PHY_743_DATA 0x00000000
+#define DDRSS_PHY_744_DATA 0x00000000
+#define DDRSS_PHY_745_DATA 0x00000000
+#define DDRSS_PHY_746_DATA 0x00000000
+#define DDRSS_PHY_747_DATA 0x00000000
+#define DDRSS_PHY_748_DATA 0x00000000
+#define DDRSS_PHY_749_DATA 0x00000000
+#define DDRSS_PHY_750_DATA 0x00000000
+#define DDRSS_PHY_751_DATA 0x00000000
+#define DDRSS_PHY_752_DATA 0x00000000
+#define DDRSS_PHY_753_DATA 0x00000000
+#define DDRSS_PHY_754_DATA 0x00000000
+#define DDRSS_PHY_755_DATA 0x00000000
+#define DDRSS_PHY_756_DATA 0x00000000
+#define DDRSS_PHY_757_DATA 0x00000000
+#define DDRSS_PHY_758_DATA 0x00000000
+#define DDRSS_PHY_759_DATA 0x00000000
+#define DDRSS_PHY_760_DATA 0x00000000
+#define DDRSS_PHY_761_DATA 0x00000000
+#define DDRSS_PHY_762_DATA 0x00000000
+#define DDRSS_PHY_763_DATA 0x00000000
+#define DDRSS_PHY_764_DATA 0x00000000
+#define DDRSS_PHY_765_DATA 0x00000000
+#define DDRSS_PHY_766_DATA 0x00000000
+#define DDRSS_PHY_767_DATA 0x00000000
+#define DDRSS_PHY_768_DATA 0x00000000
+#define DDRSS_PHY_769_DATA 0x00000000
+#define DDRSS_PHY_770_DATA 0x00000000
+#define DDRSS_PHY_771_DATA 0x00000000
+#define DDRSS_PHY_772_DATA 0x00000000
+#define DDRSS_PHY_773_DATA 0x00000100
+#define DDRSS_PHY_774_DATA 0x00000200
+#define DDRSS_PHY_775_DATA 0x00000000
+#define DDRSS_PHY_776_DATA 0x00000000
+#define DDRSS_PHY_777_DATA 0x00000000
+#define DDRSS_PHY_778_DATA 0x00000000
+#define DDRSS_PHY_779_DATA 0x00400000
+#define DDRSS_PHY_780_DATA 0x00000080
+#define DDRSS_PHY_781_DATA 0x00DCBA98
+#define DDRSS_PHY_782_DATA 0x03000000
+#define DDRSS_PHY_783_DATA 0x00200000
+#define DDRSS_PHY_784_DATA 0x00000000
+#define DDRSS_PHY_785_DATA 0x00000000
+#define DDRSS_PHY_786_DATA 0x00000000
+#define DDRSS_PHY_787_DATA 0x00000000
+#define DDRSS_PHY_788_DATA 0x0000002A
+#define DDRSS_PHY_789_DATA 0x00000015
+#define DDRSS_PHY_790_DATA 0x00000015
+#define DDRSS_PHY_791_DATA 0x0000002A
+#define DDRSS_PHY_792_DATA 0x00000033
+#define DDRSS_PHY_793_DATA 0x0000000C
+#define DDRSS_PHY_794_DATA 0x0000000C
+#define DDRSS_PHY_795_DATA 0x00000033
+#define DDRSS_PHY_796_DATA 0x00000000
+#define DDRSS_PHY_797_DATA 0x00000000
+#define DDRSS_PHY_798_DATA 0x000F0000
+#define DDRSS_PHY_799_DATA 0x0000000F
+#define DDRSS_PHY_800_DATA 0x020002CC
+#define DDRSS_PHY_801_DATA 0x00030000
+#define DDRSS_PHY_802_DATA 0x00000300
+#define DDRSS_PHY_803_DATA 0x00000300
+#define DDRSS_PHY_804_DATA 0x00000300
+#define DDRSS_PHY_805_DATA 0x00000300
+#define DDRSS_PHY_806_DATA 0x00000300
+#define DDRSS_PHY_807_DATA 0x42080010
+#define DDRSS_PHY_808_DATA 0x0000803E
+#define DDRSS_PHY_809_DATA 0x00000003
+#define DDRSS_PHY_810_DATA 0x00000002
+#define DDRSS_PHY_811_DATA 0x00000000
+#define DDRSS_PHY_812_DATA 0x00000000
+#define DDRSS_PHY_813_DATA 0x00000000
+#define DDRSS_PHY_814_DATA 0x00000000
+#define DDRSS_PHY_815_DATA 0x00000000
+#define DDRSS_PHY_816_DATA 0x00000000
+#define DDRSS_PHY_817_DATA 0x00000000
+#define DDRSS_PHY_818_DATA 0x00000000
+#define DDRSS_PHY_819_DATA 0x00000000
+#define DDRSS_PHY_820_DATA 0x00000000
+#define DDRSS_PHY_821_DATA 0x00000000
+#define DDRSS_PHY_822_DATA 0x00000000
+#define DDRSS_PHY_823_DATA 0x00000000
+#define DDRSS_PHY_824_DATA 0x00000000
+#define DDRSS_PHY_825_DATA 0x00000000
+#define DDRSS_PHY_826_DATA 0x00000000
+#define DDRSS_PHY_827_DATA 0x00000000
+#define DDRSS_PHY_828_DATA 0x00000000
+#define DDRSS_PHY_829_DATA 0x00000000
+#define DDRSS_PHY_830_DATA 0x00000000
+#define DDRSS_PHY_831_DATA 0x00000000
+#define DDRSS_PHY_832_DATA 0x00000000
+#define DDRSS_PHY_833_DATA 0x00000000
+#define DDRSS_PHY_834_DATA 0x00000000
+#define DDRSS_PHY_835_DATA 0x00000000
+#define DDRSS_PHY_836_DATA 0x00000000
+#define DDRSS_PHY_837_DATA 0x00000000
+#define DDRSS_PHY_838_DATA 0x00000000
+#define DDRSS_PHY_839_DATA 0x00000000
+#define DDRSS_PHY_840_DATA 0x00000000
+#define DDRSS_PHY_841_DATA 0x00000000
+#define DDRSS_PHY_842_DATA 0x00000000
+#define DDRSS_PHY_843_DATA 0x00000000
+#define DDRSS_PHY_844_DATA 0x00000000
+#define DDRSS_PHY_845_DATA 0x00000000
+#define DDRSS_PHY_846_DATA 0x00000000
+#define DDRSS_PHY_847_DATA 0x00000000
+#define DDRSS_PHY_848_DATA 0x00000000
+#define DDRSS_PHY_849_DATA 0x00000000
+#define DDRSS_PHY_850_DATA 0x00000000
+#define DDRSS_PHY_851_DATA 0x00000000
+#define DDRSS_PHY_852_DATA 0x00000000
+#define DDRSS_PHY_853_DATA 0x00000000
+#define DDRSS_PHY_854_DATA 0x00000000
+#define DDRSS_PHY_855_DATA 0x00000000
+#define DDRSS_PHY_856_DATA 0x00000000
+#define DDRSS_PHY_857_DATA 0x00000000
+#define DDRSS_PHY_858_DATA 0x00000000
+#define DDRSS_PHY_859_DATA 0x00000000
+#define DDRSS_PHY_860_DATA 0x00000000
+#define DDRSS_PHY_861_DATA 0x00000000
+#define DDRSS_PHY_862_DATA 0x00000000
+#define DDRSS_PHY_863_DATA 0x00000000
+#define DDRSS_PHY_864_DATA 0x00000000
+#define DDRSS_PHY_865_DATA 0x00000000
+#define DDRSS_PHY_866_DATA 0x00000000
+#define DDRSS_PHY_867_DATA 0x00000000
+#define DDRSS_PHY_868_DATA 0x00000000
+#define DDRSS_PHY_869_DATA 0x00000000
+#define DDRSS_PHY_870_DATA 0x00000000
+#define DDRSS_PHY_871_DATA 0x00000000
+#define DDRSS_PHY_872_DATA 0x00000000
+#define DDRSS_PHY_873_DATA 0x00000000
+#define DDRSS_PHY_874_DATA 0x00000000
+#define DDRSS_PHY_875_DATA 0x00000000
+#define DDRSS_PHY_876_DATA 0x00000000
+#define DDRSS_PHY_877_DATA 0x00000000
+#define DDRSS_PHY_878_DATA 0x00000000
+#define DDRSS_PHY_879_DATA 0x00000000
+#define DDRSS_PHY_880_DATA 0x00000000
+#define DDRSS_PHY_881_DATA 0x00000000
+#define DDRSS_PHY_882_DATA 0x00000000
+#define DDRSS_PHY_883_DATA 0x00000000
+#define DDRSS_PHY_884_DATA 0x00000000
+#define DDRSS_PHY_885_DATA 0x00000000
+#define DDRSS_PHY_886_DATA 0x00000000
+#define DDRSS_PHY_887_DATA 0x00000000
+#define DDRSS_PHY_888_DATA 0x00000000
+#define DDRSS_PHY_889_DATA 0x00000000
+#define DDRSS_PHY_890_DATA 0x00000000
+#define DDRSS_PHY_891_DATA 0x00000000
+#define DDRSS_PHY_892_DATA 0x00000000
+#define DDRSS_PHY_893_DATA 0x00000000
+#define DDRSS_PHY_894_DATA 0x00000000
+#define DDRSS_PHY_895_DATA 0x00000000
+#define DDRSS_PHY_896_DATA 0x00000000
+#define DDRSS_PHY_897_DATA 0x00000000
+#define DDRSS_PHY_898_DATA 0x00000000
+#define DDRSS_PHY_899_DATA 0x00000000
+#define DDRSS_PHY_900_DATA 0x00000000
+#define DDRSS_PHY_901_DATA 0x00000000
+#define DDRSS_PHY_902_DATA 0x00000000
+#define DDRSS_PHY_903_DATA 0x00000000
+#define DDRSS_PHY_904_DATA 0x00000000
+#define DDRSS_PHY_905_DATA 0x00000000
+#define DDRSS_PHY_906_DATA 0x00000000
+#define DDRSS_PHY_907_DATA 0x00000000
+#define DDRSS_PHY_908_DATA 0x00000000
+#define DDRSS_PHY_909_DATA 0x00000000
+#define DDRSS_PHY_910_DATA 0x00000000
+#define DDRSS_PHY_911_DATA 0x00000000
+#define DDRSS_PHY_912_DATA 0x00000000
+#define DDRSS_PHY_913_DATA 0x00000000
+#define DDRSS_PHY_914_DATA 0x00000000
+#define DDRSS_PHY_915_DATA 0x00000000
+#define DDRSS_PHY_916_DATA 0x00000000
+#define DDRSS_PHY_917_DATA 0x00000000
+#define DDRSS_PHY_918_DATA 0x00000000
+#define DDRSS_PHY_919_DATA 0x00000000
+#define DDRSS_PHY_920_DATA 0x00000000
+#define DDRSS_PHY_921_DATA 0x00000000
+#define DDRSS_PHY_922_DATA 0x00000000
+#define DDRSS_PHY_923_DATA 0x00000000
+#define DDRSS_PHY_924_DATA 0x00000000
+#define DDRSS_PHY_925_DATA 0x00000000
+#define DDRSS_PHY_926_DATA 0x00000000
+#define DDRSS_PHY_927_DATA 0x00000000
+#define DDRSS_PHY_928_DATA 0x00000000
+#define DDRSS_PHY_929_DATA 0x00000000
+#define DDRSS_PHY_930_DATA 0x00000000
+#define DDRSS_PHY_931_DATA 0x00000000
+#define DDRSS_PHY_932_DATA 0x00000000
+#define DDRSS_PHY_933_DATA 0x00000000
+#define DDRSS_PHY_934_DATA 0x00000000
+#define DDRSS_PHY_935_DATA 0x00000000
+#define DDRSS_PHY_936_DATA 0x00000000
+#define DDRSS_PHY_937_DATA 0x00000000
+#define DDRSS_PHY_938_DATA 0x00000000
+#define DDRSS_PHY_939_DATA 0x00000000
+#define DDRSS_PHY_940_DATA 0x00000000
+#define DDRSS_PHY_941_DATA 0x00000000
+#define DDRSS_PHY_942_DATA 0x00000000
+#define DDRSS_PHY_943_DATA 0x00000000
+#define DDRSS_PHY_944_DATA 0x00000000
+#define DDRSS_PHY_945_DATA 0x00000000
+#define DDRSS_PHY_946_DATA 0x00000000
+#define DDRSS_PHY_947_DATA 0x00000000
+#define DDRSS_PHY_948_DATA 0x00000000
+#define DDRSS_PHY_949_DATA 0x00000000
+#define DDRSS_PHY_950_DATA 0x00000000
+#define DDRSS_PHY_951_DATA 0x00000000
+#define DDRSS_PHY_952_DATA 0x00000000
+#define DDRSS_PHY_953_DATA 0x00000000
+#define DDRSS_PHY_954_DATA 0x00000000
+#define DDRSS_PHY_955_DATA 0x00000000
+#define DDRSS_PHY_956_DATA 0x00000000
+#define DDRSS_PHY_957_DATA 0x00000000
+#define DDRSS_PHY_958_DATA 0x00000000
+#define DDRSS_PHY_959_DATA 0x00000000
+#define DDRSS_PHY_960_DATA 0x00000000
+#define DDRSS_PHY_961_DATA 0x00000000
+#define DDRSS_PHY_962_DATA 0x00000000
+#define DDRSS_PHY_963_DATA 0x00000000
+#define DDRSS_PHY_964_DATA 0x00000000
+#define DDRSS_PHY_965_DATA 0x00000000
+#define DDRSS_PHY_966_DATA 0x00000000
+#define DDRSS_PHY_967_DATA 0x00000000
+#define DDRSS_PHY_968_DATA 0x00000000
+#define DDRSS_PHY_969_DATA 0x00000000
+#define DDRSS_PHY_970_DATA 0x00000000
+#define DDRSS_PHY_971_DATA 0x00000000
+#define DDRSS_PHY_972_DATA 0x00000000
+#define DDRSS_PHY_973_DATA 0x00000000
+#define DDRSS_PHY_974_DATA 0x00000000
+#define DDRSS_PHY_975_DATA 0x00000000
+#define DDRSS_PHY_976_DATA 0x00000000
+#define DDRSS_PHY_977_DATA 0x00000000
+#define DDRSS_PHY_978_DATA 0x00000000
+#define DDRSS_PHY_979_DATA 0x00000000
+#define DDRSS_PHY_980_DATA 0x00000000
+#define DDRSS_PHY_981_DATA 0x00000000
+#define DDRSS_PHY_982_DATA 0x00000000
+#define DDRSS_PHY_983_DATA 0x00000000
+#define DDRSS_PHY_984_DATA 0x00000000
+#define DDRSS_PHY_985_DATA 0x00000000
+#define DDRSS_PHY_986_DATA 0x00000000
+#define DDRSS_PHY_987_DATA 0x00000000
+#define DDRSS_PHY_988_DATA 0x00000000
+#define DDRSS_PHY_989_DATA 0x00000000
+#define DDRSS_PHY_990_DATA 0x00000000
+#define DDRSS_PHY_991_DATA 0x00000000
+#define DDRSS_PHY_992_DATA 0x00000000
+#define DDRSS_PHY_993_DATA 0x00000000
+#define DDRSS_PHY_994_DATA 0x00000000
+#define DDRSS_PHY_995_DATA 0x00000000
+#define DDRSS_PHY_996_DATA 0x00000000
+#define DDRSS_PHY_997_DATA 0x00000000
+#define DDRSS_PHY_998_DATA 0x00000000
+#define DDRSS_PHY_999_DATA 0x00000000
+#define DDRSS_PHY_1000_DATA 0x00000000
+#define DDRSS_PHY_1001_DATA 0x00000000
+#define DDRSS_PHY_1002_DATA 0x00000000
+#define DDRSS_PHY_1003_DATA 0x00000000
+#define DDRSS_PHY_1004_DATA 0x00000000
+#define DDRSS_PHY_1005_DATA 0x00000000
+#define DDRSS_PHY_1006_DATA 0x00000000
+#define DDRSS_PHY_1007_DATA 0x00000000
+#define DDRSS_PHY_1008_DATA 0x00000000
+#define DDRSS_PHY_1009_DATA 0x00000000
+#define DDRSS_PHY_1010_DATA 0x00000000
+#define DDRSS_PHY_1011_DATA 0x00000000
+#define DDRSS_PHY_1012_DATA 0x00000000
+#define DDRSS_PHY_1013_DATA 0x00000000
+#define DDRSS_PHY_1014_DATA 0x00000000
+#define DDRSS_PHY_1015_DATA 0x00000000
+#define DDRSS_PHY_1016_DATA 0x00000000
+#define DDRSS_PHY_1017_DATA 0x00000000
+#define DDRSS_PHY_1018_DATA 0x00000000
+#define DDRSS_PHY_1019_DATA 0x00000000
+#define DDRSS_PHY_1020_DATA 0x00000000
+#define DDRSS_PHY_1021_DATA 0x00000000
+#define DDRSS_PHY_1022_DATA 0x00000000
+#define DDRSS_PHY_1023_DATA 0x00000000
+#define DDRSS_PHY_1024_DATA 0x00000000
+#define DDRSS_PHY_1025_DATA 0x00000000
+#define DDRSS_PHY_1026_DATA 0x00000000
+#define DDRSS_PHY_1027_DATA 0x00000000
+#define DDRSS_PHY_1028_DATA 0x00000000
+#define DDRSS_PHY_1029_DATA 0x00000100
+#define DDRSS_PHY_1030_DATA 0x00000200
+#define DDRSS_PHY_1031_DATA 0x00000000
+#define DDRSS_PHY_1032_DATA 0x00000000
+#define DDRSS_PHY_1033_DATA 0x00000000
+#define DDRSS_PHY_1034_DATA 0x00000000
+#define DDRSS_PHY_1035_DATA 0x00400000
+#define DDRSS_PHY_1036_DATA 0x00000080
+#define DDRSS_PHY_1037_DATA 0x00DCBA98
+#define DDRSS_PHY_1038_DATA 0x03000000
+#define DDRSS_PHY_1039_DATA 0x00200000
+#define DDRSS_PHY_1040_DATA 0x00000000
+#define DDRSS_PHY_1041_DATA 0x00000000
+#define DDRSS_PHY_1042_DATA 0x00000000
+#define DDRSS_PHY_1043_DATA 0x00000000
+#define DDRSS_PHY_1044_DATA 0x0000002A
+#define DDRSS_PHY_1045_DATA 0x00000015
+#define DDRSS_PHY_1046_DATA 0x00000015
+#define DDRSS_PHY_1047_DATA 0x0000002A
+#define DDRSS_PHY_1048_DATA 0x00000033
+#define DDRSS_PHY_1049_DATA 0x0000000C
+#define DDRSS_PHY_1050_DATA 0x0000000C
+#define DDRSS_PHY_1051_DATA 0x00000033
+#define DDRSS_PHY_1052_DATA 0x2307B9AC
+#define DDRSS_PHY_1053_DATA 0x10000000
+#define DDRSS_PHY_1054_DATA 0x000F0000
+#define DDRSS_PHY_1055_DATA 0x0000000F
+#define DDRSS_PHY_1056_DATA 0x020002CC
+#define DDRSS_PHY_1057_DATA 0x00030000
+#define DDRSS_PHY_1058_DATA 0x00000300
+#define DDRSS_PHY_1059_DATA 0x00000300
+#define DDRSS_PHY_1060_DATA 0x00000300
+#define DDRSS_PHY_1061_DATA 0x00000300
+#define DDRSS_PHY_1062_DATA 0x00000300
+#define DDRSS_PHY_1063_DATA 0x42080010
+#define DDRSS_PHY_1064_DATA 0x0000803E
+#define DDRSS_PHY_1065_DATA 0x00000003
+#define DDRSS_PHY_1066_DATA 0x00000002
+#define DDRSS_PHY_1067_DATA 0x00000000
+#define DDRSS_PHY_1068_DATA 0x00000000
+#define DDRSS_PHY_1069_DATA 0x00000000
+#define DDRSS_PHY_1070_DATA 0x00000000
+#define DDRSS_PHY_1071_DATA 0x00000000
+#define DDRSS_PHY_1072_DATA 0x00000000
+#define DDRSS_PHY_1073_DATA 0x00000000
+#define DDRSS_PHY_1074_DATA 0x00000000
+#define DDRSS_PHY_1075_DATA 0x00000000
+#define DDRSS_PHY_1076_DATA 0x00000000
+#define DDRSS_PHY_1077_DATA 0x00000000
+#define DDRSS_PHY_1078_DATA 0x00000000
+#define DDRSS_PHY_1079_DATA 0x00000000
+#define DDRSS_PHY_1080_DATA 0x00000000
+#define DDRSS_PHY_1081_DATA 0x00000000
+#define DDRSS_PHY_1082_DATA 0x00000000
+#define DDRSS_PHY_1083_DATA 0x00000000
+#define DDRSS_PHY_1084_DATA 0x00000000
+#define DDRSS_PHY_1085_DATA 0x00000000
+#define DDRSS_PHY_1086_DATA 0x00000000
+#define DDRSS_PHY_1087_DATA 0x00000000
+#define DDRSS_PHY_1088_DATA 0x00000000
+#define DDRSS_PHY_1089_DATA 0x00000000
+#define DDRSS_PHY_1090_DATA 0x00000000
+#define DDRSS_PHY_1091_DATA 0x00000000
+#define DDRSS_PHY_1092_DATA 0x00000000
+#define DDRSS_PHY_1093_DATA 0x00000000
+#define DDRSS_PHY_1094_DATA 0x00000000
+#define DDRSS_PHY_1095_DATA 0x00000000
+#define DDRSS_PHY_1096_DATA 0x00000000
+#define DDRSS_PHY_1097_DATA 0x00000000
+#define DDRSS_PHY_1098_DATA 0x00000000
+#define DDRSS_PHY_1099_DATA 0x00000000
+#define DDRSS_PHY_1100_DATA 0x00000000
+#define DDRSS_PHY_1101_DATA 0x00000000
+#define DDRSS_PHY_1102_DATA 0x00000000
+#define DDRSS_PHY_1103_DATA 0x00000000
+#define DDRSS_PHY_1104_DATA 0x00000000
+#define DDRSS_PHY_1105_DATA 0x00000000
+#define DDRSS_PHY_1106_DATA 0x00000000
+#define DDRSS_PHY_1107_DATA 0x00000000
+#define DDRSS_PHY_1108_DATA 0x00000000
+#define DDRSS_PHY_1109_DATA 0x00000000
+#define DDRSS_PHY_1110_DATA 0x00000000
+#define DDRSS_PHY_1111_DATA 0x00000000
+#define DDRSS_PHY_1112_DATA 0x00000000
+#define DDRSS_PHY_1113_DATA 0x00000000
+#define DDRSS_PHY_1114_DATA 0x00000000
+#define DDRSS_PHY_1115_DATA 0x00000000
+#define DDRSS_PHY_1116_DATA 0x00000000
+#define DDRSS_PHY_1117_DATA 0x00000000
+#define DDRSS_PHY_1118_DATA 0x00000000
+#define DDRSS_PHY_1119_DATA 0x00000000
+#define DDRSS_PHY_1120_DATA 0x00000000
+#define DDRSS_PHY_1121_DATA 0x00000000
+#define DDRSS_PHY_1122_DATA 0x00000000
+#define DDRSS_PHY_1123_DATA 0x00000000
+#define DDRSS_PHY_1124_DATA 0x00000000
+#define DDRSS_PHY_1125_DATA 0x00000000
+#define DDRSS_PHY_1126_DATA 0x00000000
+#define DDRSS_PHY_1127_DATA 0x00000000
+#define DDRSS_PHY_1128_DATA 0x00000000
+#define DDRSS_PHY_1129_DATA 0x00000000
+#define DDRSS_PHY_1130_DATA 0x00000000
+#define DDRSS_PHY_1131_DATA 0x00000000
+#define DDRSS_PHY_1132_DATA 0x00000000
+#define DDRSS_PHY_1133_DATA 0x00000000
+#define DDRSS_PHY_1134_DATA 0x00000000
+#define DDRSS_PHY_1135_DATA 0x00000000
+#define DDRSS_PHY_1136_DATA 0x00000000
+#define DDRSS_PHY_1137_DATA 0x00000000
+#define DDRSS_PHY_1138_DATA 0x00000000
+#define DDRSS_PHY_1139_DATA 0x00000000
+#define DDRSS_PHY_1140_DATA 0x00000000
+#define DDRSS_PHY_1141_DATA 0x00000000
+#define DDRSS_PHY_1142_DATA 0x00000000
+#define DDRSS_PHY_1143_DATA 0x00000000
+#define DDRSS_PHY_1144_DATA 0x00000000
+#define DDRSS_PHY_1145_DATA 0x00000000
+#define DDRSS_PHY_1146_DATA 0x00000000
+#define DDRSS_PHY_1147_DATA 0x00000000
+#define DDRSS_PHY_1148_DATA 0x00000000
+#define DDRSS_PHY_1149_DATA 0x00000000
+#define DDRSS_PHY_1150_DATA 0x00000000
+#define DDRSS_PHY_1151_DATA 0x00000000
+#define DDRSS_PHY_1152_DATA 0x00000000
+#define DDRSS_PHY_1153_DATA 0x00000000
+#define DDRSS_PHY_1154_DATA 0x00000000
+#define DDRSS_PHY_1155_DATA 0x00000000
+#define DDRSS_PHY_1156_DATA 0x00000000
+#define DDRSS_PHY_1157_DATA 0x00000000
+#define DDRSS_PHY_1158_DATA 0x00000000
+#define DDRSS_PHY_1159_DATA 0x00000000
+#define DDRSS_PHY_1160_DATA 0x00000000
+#define DDRSS_PHY_1161_DATA 0x00000000
+#define DDRSS_PHY_1162_DATA 0x00000000
+#define DDRSS_PHY_1163_DATA 0x00000000
+#define DDRSS_PHY_1164_DATA 0x00000000
+#define DDRSS_PHY_1165_DATA 0x00000000
+#define DDRSS_PHY_1166_DATA 0x00000000
+#define DDRSS_PHY_1167_DATA 0x00000000
+#define DDRSS_PHY_1168_DATA 0x00000000
+#define DDRSS_PHY_1169_DATA 0x00000000
+#define DDRSS_PHY_1170_DATA 0x00000000
+#define DDRSS_PHY_1171_DATA 0x00000000
+#define DDRSS_PHY_1172_DATA 0x00000000
+#define DDRSS_PHY_1173_DATA 0x00000000
+#define DDRSS_PHY_1174_DATA 0x00000000
+#define DDRSS_PHY_1175_DATA 0x00000000
+#define DDRSS_PHY_1176_DATA 0x00000000
+#define DDRSS_PHY_1177_DATA 0x00000000
+#define DDRSS_PHY_1178_DATA 0x00000000
+#define DDRSS_PHY_1179_DATA 0x00000000
+#define DDRSS_PHY_1180_DATA 0x00000000
+#define DDRSS_PHY_1181_DATA 0x00000000
+#define DDRSS_PHY_1182_DATA 0x00000000
+#define DDRSS_PHY_1183_DATA 0x00000000
+#define DDRSS_PHY_1184_DATA 0x00000000
+#define DDRSS_PHY_1185_DATA 0x00000000
+#define DDRSS_PHY_1186_DATA 0x00000000
+#define DDRSS_PHY_1187_DATA 0x00000000
+#define DDRSS_PHY_1188_DATA 0x00000000
+#define DDRSS_PHY_1189_DATA 0x00000000
+#define DDRSS_PHY_1190_DATA 0x00000000
+#define DDRSS_PHY_1191_DATA 0x00000000
+#define DDRSS_PHY_1192_DATA 0x00000000
+#define DDRSS_PHY_1193_DATA 0x00000000
+#define DDRSS_PHY_1194_DATA 0x00000000
+#define DDRSS_PHY_1195_DATA 0x00000000
+#define DDRSS_PHY_1196_DATA 0x00000000
+#define DDRSS_PHY_1197_DATA 0x00000000
+#define DDRSS_PHY_1198_DATA 0x00000000
+#define DDRSS_PHY_1199_DATA 0x00000000
+#define DDRSS_PHY_1200_DATA 0x00000000
+#define DDRSS_PHY_1201_DATA 0x00000000
+#define DDRSS_PHY_1202_DATA 0x00000000
+#define DDRSS_PHY_1203_DATA 0x00000000
+#define DDRSS_PHY_1204_DATA 0x00000000
+#define DDRSS_PHY_1205_DATA 0x00000000
+#define DDRSS_PHY_1206_DATA 0x00000000
+#define DDRSS_PHY_1207_DATA 0x00000000
+#define DDRSS_PHY_1208_DATA 0x00000000
+#define DDRSS_PHY_1209_DATA 0x00000000
+#define DDRSS_PHY_1210_DATA 0x00000000
+#define DDRSS_PHY_1211_DATA 0x00000000
+#define DDRSS_PHY_1212_DATA 0x00000000
+#define DDRSS_PHY_1213_DATA 0x00000000
+#define DDRSS_PHY_1214_DATA 0x00000000
+#define DDRSS_PHY_1215_DATA 0x00000000
+#define DDRSS_PHY_1216_DATA 0x00000000
+#define DDRSS_PHY_1217_DATA 0x00000000
+#define DDRSS_PHY_1218_DATA 0x00000000
+#define DDRSS_PHY_1219_DATA 0x00000000
+#define DDRSS_PHY_1220_DATA 0x00000000
+#define DDRSS_PHY_1221_DATA 0x00000000
+#define DDRSS_PHY_1222_DATA 0x00000000
+#define DDRSS_PHY_1223_DATA 0x00000000
+#define DDRSS_PHY_1224_DATA 0x00000000
+#define DDRSS_PHY_1225_DATA 0x00000000
+#define DDRSS_PHY_1226_DATA 0x00000000
+#define DDRSS_PHY_1227_DATA 0x00000000
+#define DDRSS_PHY_1228_DATA 0x00000000
+#define DDRSS_PHY_1229_DATA 0x00000000
+#define DDRSS_PHY_1230_DATA 0x00000000
+#define DDRSS_PHY_1231_DATA 0x00000000
+#define DDRSS_PHY_1232_DATA 0x00000000
+#define DDRSS_PHY_1233_DATA 0x00000000
+#define DDRSS_PHY_1234_DATA 0x00000000
+#define DDRSS_PHY_1235_DATA 0x00000000
+#define DDRSS_PHY_1236_DATA 0x00000000
+#define DDRSS_PHY_1237_DATA 0x00000000
+#define DDRSS_PHY_1238_DATA 0x00000000
+#define DDRSS_PHY_1239_DATA 0x00000000
+#define DDRSS_PHY_1240_DATA 0x00000000
+#define DDRSS_PHY_1241_DATA 0x00000000
+#define DDRSS_PHY_1242_DATA 0x00000000
+#define DDRSS_PHY_1243_DATA 0x00000000
+#define DDRSS_PHY_1244_DATA 0x00000000
+#define DDRSS_PHY_1245_DATA 0x00000000
+#define DDRSS_PHY_1246_DATA 0x00000000
+#define DDRSS_PHY_1247_DATA 0x00000000
+#define DDRSS_PHY_1248_DATA 0x00000000
+#define DDRSS_PHY_1249_DATA 0x00000000
+#define DDRSS_PHY_1250_DATA 0x00000000
+#define DDRSS_PHY_1251_DATA 0x00000000
+#define DDRSS_PHY_1252_DATA 0x00000000
+#define DDRSS_PHY_1253_DATA 0x00000000
+#define DDRSS_PHY_1254_DATA 0x00000000
+#define DDRSS_PHY_1255_DATA 0x00000000
+#define DDRSS_PHY_1256_DATA 0x00000000
+#define DDRSS_PHY_1257_DATA 0x00000000
+#define DDRSS_PHY_1258_DATA 0x00000000
+#define DDRSS_PHY_1259_DATA 0x00000000
+#define DDRSS_PHY_1260_DATA 0x00000000
+#define DDRSS_PHY_1261_DATA 0x00000000
+#define DDRSS_PHY_1262_DATA 0x00000000
+#define DDRSS_PHY_1263_DATA 0x00000000
+#define DDRSS_PHY_1264_DATA 0x00000000
+#define DDRSS_PHY_1265_DATA 0x00000000
+#define DDRSS_PHY_1266_DATA 0x00000000
+#define DDRSS_PHY_1267_DATA 0x00000000
+#define DDRSS_PHY_1268_DATA 0x00000000
+#define DDRSS_PHY_1269_DATA 0x00000000
+#define DDRSS_PHY_1270_DATA 0x00000000
+#define DDRSS_PHY_1271_DATA 0x00000000
+#define DDRSS_PHY_1272_DATA 0x00000000
+#define DDRSS_PHY_1273_DATA 0x00000000
+#define DDRSS_PHY_1274_DATA 0x00000000
+#define DDRSS_PHY_1275_DATA 0x00000000
+#define DDRSS_PHY_1276_DATA 0x00000000
+#define DDRSS_PHY_1277_DATA 0x00000000
+#define DDRSS_PHY_1278_DATA 0x00000000
+#define DDRSS_PHY_1279_DATA 0x00000000
+#define DDRSS_PHY_1280_DATA 0x00000000
+#define DDRSS_PHY_1281_DATA 0x00010100
+#define DDRSS_PHY_1282_DATA 0x00000000
+#define DDRSS_PHY_1283_DATA 0x00000000
+#define DDRSS_PHY_1284_DATA 0x00000000
+#define DDRSS_PHY_1285_DATA 0x00000000
+#define DDRSS_PHY_1286_DATA 0x00050000
+#define DDRSS_PHY_1287_DATA 0x04000000
+#define DDRSS_PHY_1288_DATA 0x00000055
+#define DDRSS_PHY_1289_DATA 0x00000000
+#define DDRSS_PHY_1290_DATA 0x00000000
+#define DDRSS_PHY_1291_DATA 0x00000000
+#define DDRSS_PHY_1292_DATA 0x00000000
+#define DDRSS_PHY_1293_DATA 0x00002001
+#define DDRSS_PHY_1294_DATA 0x00004001
+#define DDRSS_PHY_1295_DATA 0x00020028
+#define DDRSS_PHY_1296_DATA 0x01010100
+#define DDRSS_PHY_1297_DATA 0x00000000
+#define DDRSS_PHY_1298_DATA 0x00000000
+#define DDRSS_PHY_1299_DATA 0x0F0F0E06
+#define DDRSS_PHY_1300_DATA 0x00010101
+#define DDRSS_PHY_1301_DATA 0x010F0004
+#define DDRSS_PHY_1302_DATA 0x00000000
+#define DDRSS_PHY_1303_DATA 0x00000000
+#define DDRSS_PHY_1304_DATA 0x00000064
+#define DDRSS_PHY_1305_DATA 0x00000000
+#define DDRSS_PHY_1306_DATA 0x00000000
+#define DDRSS_PHY_1307_DATA 0x01020103
+#define DDRSS_PHY_1308_DATA 0x0F020102
+#define DDRSS_PHY_1309_DATA 0x03030303
+#define DDRSS_PHY_1310_DATA 0x03030303
+#define DDRSS_PHY_1311_DATA 0x00041B42
+#define DDRSS_PHY_1312_DATA 0x00005201
+#define DDRSS_PHY_1313_DATA 0x00000000
+#define DDRSS_PHY_1314_DATA 0x00000000
+#define DDRSS_PHY_1315_DATA 0x00000000
+#define DDRSS_PHY_1316_DATA 0x00000000
+#define DDRSS_PHY_1317_DATA 0x00000000
+#define DDRSS_PHY_1318_DATA 0x00000000
+#define DDRSS_PHY_1319_DATA 0x07030101
+#define DDRSS_PHY_1320_DATA 0x00005400
+#define DDRSS_PHY_1321_DATA 0x000040A2
+#define DDRSS_PHY_1322_DATA 0x00024410
+#define DDRSS_PHY_1323_DATA 0x00004410
+#define DDRSS_PHY_1324_DATA 0x00004410
+#define DDRSS_PHY_1325_DATA 0x00004410
+#define DDRSS_PHY_1326_DATA 0x00004410
+#define DDRSS_PHY_1327_DATA 0x00004410
+#define DDRSS_PHY_1328_DATA 0x00004410
+#define DDRSS_PHY_1329_DATA 0x00004410
+#define DDRSS_PHY_1330_DATA 0x00004410
+#define DDRSS_PHY_1331_DATA 0x00004410
+#define DDRSS_PHY_1332_DATA 0x00000000
+#define DDRSS_PHY_1333_DATA 0x00000076
+#define DDRSS_PHY_1334_DATA 0x00000400
+#define DDRSS_PHY_1335_DATA 0x00000008
+#define DDRSS_PHY_1336_DATA 0x00000000
+#define DDRSS_PHY_1337_DATA 0x00000000
+#define DDRSS_PHY_1338_DATA 0x00000000
+#define DDRSS_PHY_1339_DATA 0x00000000
+#define DDRSS_PHY_1340_DATA 0x00000000
+#define DDRSS_PHY_1341_DATA 0x03000000
+#define DDRSS_PHY_1342_DATA 0x00000000
+#define DDRSS_PHY_1343_DATA 0x00000000
+#define DDRSS_PHY_1344_DATA 0x00000000
+#define DDRSS_PHY_1345_DATA 0x04102006
+#define DDRSS_PHY_1346_DATA 0x00041020
+#define DDRSS_PHY_1347_DATA 0x01C98C98
+#define DDRSS_PHY_1348_DATA 0x3F400000
+#define DDRSS_PHY_1349_DATA 0x3F3F1F3F
+#define DDRSS_PHY_1350_DATA 0x0000001F
+#define DDRSS_PHY_1351_DATA 0x00000000
+#define DDRSS_PHY_1352_DATA 0x00000000
+#define DDRSS_PHY_1353_DATA 0x00000000
+#define DDRSS_PHY_1354_DATA 0x00000001
+#define DDRSS_PHY_1355_DATA 0x00000000
+#define DDRSS_PHY_1356_DATA 0x00000000
+#define DDRSS_PHY_1357_DATA 0x00000000
+#define DDRSS_PHY_1358_DATA 0x00000000
+#define DDRSS_PHY_1359_DATA 0x76543210
+#define DDRSS_PHY_1360_DATA 0x00040198
+#define DDRSS_PHY_1361_DATA 0x00000000
+#define DDRSS_PHY_1362_DATA 0x00000000
+#define DDRSS_PHY_1363_DATA 0x00000000
+#define DDRSS_PHY_1364_DATA 0x00040700
+#define DDRSS_PHY_1365_DATA 0x00000000
+#define DDRSS_PHY_1366_DATA 0x00000000
+#define DDRSS_PHY_1367_DATA 0x00000000
+#define DDRSS_PHY_1368_DATA 0x00000002
+#define DDRSS_PHY_1369_DATA 0x00000000
+#define DDRSS_PHY_1370_DATA 0x00000000
+#define DDRSS_PHY_1371_DATA 0x0001F7C2
+#define DDRSS_PHY_1372_DATA 0x00020002
+#define DDRSS_PHY_1373_DATA 0x00000000
+#define DDRSS_PHY_1374_DATA 0x00001142
+#define DDRSS_PHY_1375_DATA 0x03020000
+#define DDRSS_PHY_1376_DATA 0x00000080
+#define DDRSS_PHY_1377_DATA 0x03900390
+#define DDRSS_PHY_1378_DATA 0x03900390
+#define DDRSS_PHY_1379_DATA 0x03900390
+#define DDRSS_PHY_1380_DATA 0x03900390
+#define DDRSS_PHY_1381_DATA 0x03000300
+#define DDRSS_PHY_1382_DATA 0x03000300
+#define DDRSS_PHY_1383_DATA 0x00000300
+#define DDRSS_PHY_1384_DATA 0x00000300
+#define DDRSS_PHY_1385_DATA 0x00000300
+#define DDRSS_PHY_1386_DATA 0x00000300
+#define DDRSS_PHY_1387_DATA 0x3183BF77
+#define DDRSS_PHY_1388_DATA 0x00000000
+#define DDRSS_PHY_1389_DATA 0x0C000DFF
+#define DDRSS_PHY_1390_DATA 0x30000DFF
+#define DDRSS_PHY_1391_DATA 0x3F0DFF11
+#define DDRSS_PHY_1392_DATA 0x01990000
+#define DDRSS_PHY_1393_DATA 0x780DFFCC
+#define DDRSS_PHY_1394_DATA 0x00000C11
+#define DDRSS_PHY_1395_DATA 0x00018011
+#define DDRSS_PHY_1396_DATA 0x0089FF00
+#define DDRSS_PHY_1397_DATA 0x000C3F11
+#define DDRSS_PHY_1398_DATA 0x01990000
+#define DDRSS_PHY_1399_DATA 0x000C3F11
+#define DDRSS_PHY_1400_DATA 0x01990000
+#define DDRSS_PHY_1401_DATA 0x3F0DFF11
+#define DDRSS_PHY_1402_DATA 0x01990000
+#define DDRSS_PHY_1403_DATA 0x00018011
+#define DDRSS_PHY_1404_DATA 0x0089FF00
+#define DDRSS_PHY_1405_DATA 0x20040004
diff --git a/arch/arm/dts/k3-am62-main.dtsi b/arch/arm/dts/k3-am62-main.dtsi
deleted file mode 100644
index e9cffca..0000000
--- a/arch/arm/dts/k3-am62-main.dtsi
+++ /dev/null
@@ -1,1058 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-/*
- * Device Tree Source for AM625 SoC Family Main Domain peripherals
- *
- * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-&cbass_main {
- oc_sram: sram@70000000 {
- compatible = "mmio-sram";
- reg = <0x00 0x70000000 0x00 0x10000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x00 0x70000000 0x10000>;
- };
-
- gic500: interrupt-controller@1800000 {
- compatible = "arm,gic-v3";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
- <0x00 0x01880000 0x00 0xc0000>, /* GICR */
- <0x00 0x01880000 0x00 0xc0000>, /* GICR */
- <0x01 0x00000000 0x00 0x2000>, /* GICC */
- <0x01 0x00010000 0x00 0x1000>, /* GICH */
- <0x01 0x00020000 0x00 0x2000>; /* GICV */
- /*
- * vcpumntirq:
- * virtual CPU interface maintenance interrupt
- */
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
-
- gic_its: msi-controller@1820000 {
- compatible = "arm,gic-v3-its";
- reg = <0x00 0x01820000 0x00 0x10000>;
- socionext,synquacer-pre-its = <0x1000000 0x400000>;
- msi-controller;
- #msi-cells = <1>;
- };
- };
-
- main_conf: bus@100000 {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x00 0x00100000 0x20000>;
-
- phy_gmii_sel: phy@4044 {
- compatible = "ti,am654-phy-gmii-sel";
- reg = <0x4044 0x8>;
- #phy-cells = <1>;
- };
-
- epwm_tbclk: clock-controller@4130 {
- compatible = "ti,am62-epwm-tbclk";
- reg = <0x4130 0x4>;
- #clock-cells = <1>;
- };
-
- audio_refclk0: clock-controller@82e0 {
- compatible = "ti,am62-audio-refclk";
- reg = <0x82e0 0x4>;
- clocks = <&k3_clks 157 0>;
- assigned-clocks = <&k3_clks 157 0>;
- assigned-clock-parents = <&k3_clks 157 8>;
- #clock-cells = <0>;
- };
-
- audio_refclk1: clock-controller@82e4 {
- compatible = "ti,am62-audio-refclk";
- reg = <0x82e4 0x4>;
- clocks = <&k3_clks 157 10>;
- assigned-clocks = <&k3_clks 157 10>;
- assigned-clock-parents = <&k3_clks 157 18>;
- #clock-cells = <0>;
- };
- };
-
- dmss: bus@48000000 {
- bootph-all;
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- dma-ranges;
- ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
-
- ti,sci-dev-id = <25>;
-
- secure_proxy_main: mailbox@4d000000 {
- bootph-all;
- compatible = "ti,am654-secure-proxy";
- #mbox-cells = <1>;
- reg-names = "target_data", "rt", "scfg";
- reg = <0x00 0x4d000000 0x00 0x80000>,
- <0x00 0x4a600000 0x00 0x80000>,
- <0x00 0x4a400000 0x00 0x80000>;
- interrupt-names = "rx_012";
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- inta_main_dmss: interrupt-controller@48000000 {
- compatible = "ti,sci-inta";
- reg = <0x00 0x48000000 0x00 0x100000>;
- #interrupt-cells = <0>;
- interrupt-controller;
- interrupt-parent = <&gic500>;
- msi-controller;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <28>;
- ti,interrupt-ranges = <4 68 36>;
- ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
- };
-
- main_bcdma: dma-controller@485c0100 {
- compatible = "ti,am64-dmss-bcdma";
- reg = <0x00 0x485c0100 0x00 0x100>,
- <0x00 0x4c000000 0x00 0x20000>,
- <0x00 0x4a820000 0x00 0x20000>,
- <0x00 0x4aa40000 0x00 0x20000>,
- <0x00 0x4bc00000 0x00 0x100000>,
- <0x00 0x48600000 0x00 0x8000>,
- <0x00 0x484a4000 0x00 0x2000>,
- <0x00 0x484c2000 0x00 0x2000>,
- <0x00 0x48420000 0x00 0x2000>;
- reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
- "ring", "tchan", "rchan", "bchan";
- msi-parent = <&inta_main_dmss>;
- #dma-cells = <3>;
-
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <26>;
- ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
- ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
- ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
- };
-
- main_pktdma: dma-controller@485c0000 {
- compatible = "ti,am64-dmss-pktdma";
- reg = <0x00 0x485c0000 0x00 0x100>,
- <0x00 0x4a800000 0x00 0x20000>,
- <0x00 0x4aa00000 0x00 0x40000>,
- <0x00 0x4b800000 0x00 0x400000>,
- <0x00 0x485e0000 0x00 0x10000>,
- <0x00 0x484a0000 0x00 0x2000>,
- <0x00 0x484c0000 0x00 0x2000>,
- <0x00 0x48430000 0x00 0x1000>;
- reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
- "ring", "tchan", "rchan", "rflow";
- msi-parent = <&inta_main_dmss>;
- #dma-cells = <2>;
-
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <30>;
- ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
- <0x24>, /* CPSW_TX_CHAN */
- <0x25>, /* SAUL_TX_0_CHAN */
- <0x26>; /* SAUL_TX_1_CHAN */
- ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
- <0x11>, /* RING_CPSW_TX_CHAN */
- <0x12>, /* RING_SAUL_TX_0_CHAN */
- <0x13>; /* RING_SAUL_TX_1_CHAN */
- ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
- <0x2b>, /* CPSW_RX_CHAN */
- <0x2d>, /* SAUL_RX_0_CHAN */
- <0x2f>, /* SAUL_RX_1_CHAN */
- <0x31>, /* SAUL_RX_2_CHAN */
- <0x33>; /* SAUL_RX_3_CHAN */
- ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
- <0x2c>, /* FLOW_CPSW_RX_CHAN */
- <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
- <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
- };
- };
-
- dmsc: system-controller@44043000 {
- bootph-all;
- compatible = "ti,k2g-sci";
- ti,host-id = <12>;
- mbox-names = "rx", "tx";
- mboxes = <&secure_proxy_main 12>,
- <&secure_proxy_main 13>;
- reg-names = "debug_messages";
- reg = <0x00 0x44043000 0x00 0xfe0>;
-
- k3_pds: power-controller {
- bootph-all;
- compatible = "ti,sci-pm-domain";
- #power-domain-cells = <2>;
- };
-
- k3_clks: clock-controller {
- bootph-all;
- compatible = "ti,k2g-sci-clk";
- #clock-cells = <2>;
- };
-
- k3_reset: reset-controller {
- bootph-all;
- compatible = "ti,sci-reset";
- #reset-cells = <2>;
- };
- };
-
- crypto: crypto@40900000 {
- compatible = "ti,am62-sa3ul";
- reg = <0x00 0x40900000 0x00 0x1200>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
-
- dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>,
- <&main_pktdma 0x7507 0>;
- dma-names = "tx", "rx1", "rx2";
- };
-
- secure_proxy_sa3: mailbox@43600000 {
- bootph-pre-ram;
- compatible = "ti,am654-secure-proxy";
- #mbox-cells = <1>;
- reg-names = "target_data", "rt", "scfg";
- reg = <0x00 0x43600000 0x00 0x10000>,
- <0x00 0x44880000 0x00 0x20000>,
- <0x00 0x44860000 0x00 0x20000>;
- /*
- * Marked Disabled:
- * Node is incomplete as it is meant for bootloaders and
- * firmware on non-MPU processors
- */
- status = "disabled";
- };
-
- main_pmx0: pinctrl@f4000 {
- bootph-all;
- compatible = "pinctrl-single";
- reg = <0x00 0xf4000 0x00 0x2ac>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0xffffffff>;
- };
-
- main_esm: esm@420000 {
- bootph-pre-ram;
- compatible = "ti,j721e-esm";
- reg = <0x00 0x420000 0x00 0x1000>;
- ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>;
- };
-
- main_timer0: timer@2400000 {
- bootph-all;
- compatible = "ti,am654-timer";
- reg = <0x00 0x2400000 0x00 0x400>;
- interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 36 2>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 36 2>;
- assigned-clock-parents = <&k3_clks 36 3>;
- power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer1: timer@2410000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2410000 0x00 0x400>;
- interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 37 2>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 37 2>;
- assigned-clock-parents = <&k3_clks 37 3>;
- power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer2: timer@2420000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2420000 0x00 0x400>;
- interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 38 2>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 38 2>;
- assigned-clock-parents = <&k3_clks 38 3>;
- power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer3: timer@2430000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2430000 0x00 0x400>;
- interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 39 2>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 39 2>;
- assigned-clock-parents = <&k3_clks 39 3>;
- power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer4: timer@2440000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2440000 0x00 0x400>;
- interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 40 2>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 40 2>;
- assigned-clock-parents = <&k3_clks 40 3>;
- power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer5: timer@2450000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2450000 0x00 0x400>;
- interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 41 2>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 41 2>;
- assigned-clock-parents = <&k3_clks 41 3>;
- power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer6: timer@2460000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2460000 0x00 0x400>;
- interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 42 2>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 42 2>;
- assigned-clock-parents = <&k3_clks 42 3>;
- power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer7: timer@2470000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2470000 0x00 0x400>;
- interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 43 2>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 43 2>;
- assigned-clock-parents = <&k3_clks 43 3>;
- power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_uart0: serial@2800000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02800000 0x00 0x100>;
- interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 146 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart1: serial@2810000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02810000 0x00 0x100>;
- interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 152 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart2: serial@2820000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02820000 0x00 0x100>;
- interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 153 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart3: serial@2830000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02830000 0x00 0x100>;
- interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 154 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart4: serial@2840000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02840000 0x00 0x100>;
- interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 155 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart5: serial@2850000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02850000 0x00 0x100>;
- interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 156 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart6: serial@2860000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02860000 0x00 0x100>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 158 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_i2c0: i2c@20000000 {
- compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x20000000 0x00 0x100>;
- interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 102 2>;
- clock-names = "fck";
- status = "disabled";
- };
-
- main_i2c1: i2c@20010000 {
- compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x20010000 0x00 0x100>;
- interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 103 2>;
- clock-names = "fck";
- status = "disabled";
- };
-
- main_i2c2: i2c@20020000 {
- compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x20020000 0x00 0x100>;
- interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 104 2>;
- clock-names = "fck";
- status = "disabled";
- };
-
- main_i2c3: i2c@20030000 {
- compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x20030000 0x00 0x100>;
- interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 105 2>;
- clock-names = "fck";
- status = "disabled";
- };
-
- main_spi0: spi@20100000 {
- compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
- reg = <0x00 0x20100000 0x00 0x400>;
- interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 141 0>;
- status = "disabled";
- };
-
- main_spi1: spi@20110000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x20110000 0x00 0x400>;
- interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 142 0>;
- status = "disabled";
- };
-
- main_spi2: spi@20120000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x20120000 0x00 0x400>;
- interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 143 0>;
- status = "disabled";
- };
-
- main_gpio_intr: interrupt-controller@a00000 {
- compatible = "ti,sci-intr";
- reg = <0x00 0x00a00000 0x00 0x800>;
- ti,intr-trigger-type = <1>;
- interrupt-controller;
- interrupt-parent = <&gic500>;
- #interrupt-cells = <1>;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <3>;
- ti,interrupt-ranges = <0 32 16>;
- };
-
- main_gpio0: gpio@600000 {
- compatible = "ti,am64-gpio", "ti,keystone-gpio";
- reg = <0x0 0x00600000 0x0 0x100>;
- gpio-ranges = <&main_pmx0 0 0 32>,
- <&main_pmx0 32 33 38>,
- <&main_pmx0 70 72 22>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&main_gpio_intr>;
- interrupts = <190>, <191>, <192>,
- <193>, <194>, <195>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <92>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 77 0>;
- clock-names = "gpio";
- };
-
- main_gpio1: gpio@601000 {
- compatible = "ti,am64-gpio", "ti,keystone-gpio";
- reg = <0x0 0x00601000 0x0 0x100>;
- gpio-controller;
- gpio-ranges = <&main_pmx0 0 94 41>,
- <&main_pmx0 41 136 6>,
- <&main_pmx0 47 143 3>,
- <&main_pmx0 50 149 2>;
- #gpio-cells = <2>;
- interrupt-parent = <&main_gpio_intr>;
- interrupts = <180>, <181>, <182>,
- <183>, <184>, <185>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <52>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 78 0>;
- clock-names = "gpio";
- };
-
- sdhci0: mmc@fa10000 {
- compatible = "ti,am62-sdhci";
- reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>;
- interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 57 5>, <&k3_clks 57 6>;
- clock-names = "clk_ahb", "clk_xin";
- assigned-clocks = <&k3_clks 57 6>;
- assigned-clock-parents = <&k3_clks 57 8>;
- bus-width = <8>;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- ti,clkbuf-sel = <0x7>;
- ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-mmc-hs = <0x0>;
- ti,otap-del-sel-ddr52 = <0x5>;
- ti,otap-del-sel-hs200 = <0x5>;
- ti,itap-del-sel-legacy = <0xa>;
- ti,itap-del-sel-mmc-hs = <0x1>;
- status = "disabled";
- };
-
- sdhci1: mmc@fa00000 {
- compatible = "ti,am62-sdhci";
- reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>;
- interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 58 5>, <&k3_clks 58 6>;
- clock-names = "clk_ahb", "clk_xin";
- bus-width = <4>;
- ti,clkbuf-sel = <0x7>;
- ti,otap-del-sel-legacy = <0x8>;
- ti,otap-del-sel-sd-hs = <0x0>;
- ti,otap-del-sel-sdr12 = <0x0>;
- ti,otap-del-sel-sdr25 = <0x0>;
- ti,otap-del-sel-sdr50 = <0x8>;
- ti,otap-del-sel-sdr104 = <0x7>;
- ti,otap-del-sel-ddr50 = <0x4>;
- ti,itap-del-sel-legacy = <0xa>;
- ti,itap-del-sel-sd-hs = <0x1>;
- ti,itap-del-sel-sdr12 = <0xa>;
- ti,itap-del-sel-sdr25 = <0x1>;
- status = "disabled";
- };
-
- sdhci2: mmc@fa20000 {
- compatible = "ti,am62-sdhci";
- reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>;
- interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 184 5>, <&k3_clks 184 6>;
- clock-names = "clk_ahb", "clk_xin";
- bus-width = <4>;
- ti,clkbuf-sel = <0x7>;
- ti,otap-del-sel-legacy = <0x8>;
- ti,otap-del-sel-sd-hs = <0x0>;
- ti,otap-del-sel-sdr12 = <0x0>;
- ti,otap-del-sel-sdr25 = <0x0>;
- ti,otap-del-sel-sdr50 = <0x8>;
- ti,otap-del-sel-sdr104 = <0x7>;
- ti,otap-del-sel-ddr50 = <0x8>;
- ti,itap-del-sel-legacy = <0xa>;
- ti,itap-del-sel-sd-hs = <0xa>;
- ti,itap-del-sel-sdr12 = <0xa>;
- ti,itap-del-sel-sdr25 = <0x1>;
- status = "disabled";
- };
-
- usbss0: dwc3-usb@f900000 {
- compatible = "ti,am62-usb";
- reg = <0x00 0x0f900000 0x00 0x800>;
- clocks = <&k3_clks 161 3>;
- clock-names = "ref";
- ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>;
- #address-cells = <2>;
- #size-cells = <2>;
- power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
- ranges;
- status = "disabled";
-
- usb0: usb@31000000 {
- compatible = "snps,dwc3";
- reg = <0x00 0x31000000 0x00 0x50000>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
- <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
- interrupt-names = "host", "peripheral";
- maximum-speed = "high-speed";
- dr_mode = "otg";
- snps,usb2-gadget-lpm-disable;
- snps,usb2-lpm-disable;
- };
- };
-
- usbss1: dwc3-usb@f910000 {
- compatible = "ti,am62-usb";
- reg = <0x00 0x0f910000 0x00 0x800>;
- clocks = <&k3_clks 162 3>;
- clock-names = "ref";
- ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>;
- #address-cells = <2>;
- #size-cells = <2>;
- power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
- ranges;
- status = "disabled";
-
- usb1: usb@31100000 {
- compatible = "snps,dwc3";
- reg = <0x00 0x31100000 0x00 0x50000>;
- interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
- <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
- interrupt-names = "host", "peripheral";
- maximum-speed = "high-speed";
- dr_mode = "otg";
- snps,usb2-gadget-lpm-disable;
- snps,usb2-lpm-disable;
- };
- };
-
- fss: bus@fc00000 {
- compatible = "simple-bus";
- reg = <0x00 0x0fc00000 0x00 0x70000>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- ospi0: spi@fc40000 {
- compatible = "ti,am654-ospi", "cdns,qspi-nor";
- reg = <0x00 0x0fc40000 0x00 0x100>,
- <0x05 0x00000000 0x01 0x00000000>;
- interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
- cdns,fifo-depth = <256>;
- cdns,fifo-width = <4>;
- cdns,trigger-address = <0x0>;
- clocks = <&k3_clks 75 7>;
- assigned-clocks = <&k3_clks 75 7>;
- assigned-clock-parents = <&k3_clks 75 8>;
- assigned-clock-rates = <166666666>;
- power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
- };
-
- gpu: gpu@fd00000 {
- compatible = "ti,am62-gpu", "img,img-axe";
- reg = <0x00 0x0fd00000 0x00 0x20000>;
- clocks = <&k3_clks 187 0>;
- clock-names = "core";
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
- };
-
- cpsw3g: ethernet@8000000 {
- compatible = "ti,am642-cpsw-nuss";
- #address-cells = <2>;
- #size-cells = <2>;
- reg = <0x00 0x08000000 0x00 0x200000>;
- reg-names = "cpsw_nuss";
- ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>;
- clocks = <&k3_clks 13 0>;
- assigned-clocks = <&k3_clks 13 3>;
- assigned-clock-parents = <&k3_clks 13 11>;
- clock-names = "fck";
- power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
-
- dmas = <&main_pktdma 0xc600 15>,
- <&main_pktdma 0xc601 15>,
- <&main_pktdma 0xc602 15>,
- <&main_pktdma 0xc603 15>,
- <&main_pktdma 0xc604 15>,
- <&main_pktdma 0xc605 15>,
- <&main_pktdma 0xc606 15>,
- <&main_pktdma 0xc607 15>,
- <&main_pktdma 0x4600 15>;
- dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
- "tx7", "rx";
-
- ethernet-ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpsw_port1: port@1 {
- reg = <1>;
- ti,mac-only;
- label = "port1";
- phys = <&phy_gmii_sel 1>;
- mac-address = [00 00 00 00 00 00];
- ti,syscon-efuse = <&wkup_conf 0x200>;
- };
-
- cpsw_port2: port@2 {
- reg = <2>;
- ti,mac-only;
- label = "port2";
- phys = <&phy_gmii_sel 2>;
- mac-address = [00 00 00 00 00 00];
- };
- };
-
- cpsw3g_mdio: mdio@f00 {
- compatible = "ti,cpsw-mdio","ti,davinci_mdio";
- reg = <0x00 0xf00 0x00 0x100>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&k3_clks 13 0>;
- clock-names = "fck";
- bus_freq = <1000000>;
- status = "disabled";
- };
-
- cpts@3d000 {
- compatible = "ti,j721e-cpts";
- reg = <0x00 0x3d000 0x00 0x400>;
- clocks = <&k3_clks 13 3>;
- clock-names = "cpts";
- interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cpts";
- ti,cpts-ext-ts-inputs = <4>;
- ti,cpts-periodic-outputs = <2>;
- };
- };
-
- dss: dss@30200000 {
- compatible = "ti,am625-dss";
- reg = <0x00 0x30200000 0x00 0x1000>, /* common */
- <0x00 0x30202000 0x00 0x1000>, /* vidl1 */
- <0x00 0x30206000 0x00 0x1000>, /* vid */
- <0x00 0x30207000 0x00 0x1000>, /* ovr1 */
- <0x00 0x30208000 0x00 0x1000>, /* ovr2 */
- <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */
- <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */
- <0x00 0x30201000 0x00 0x1000>; /* common1 */
- reg-names = "common", "vidl1", "vid",
- "ovr1", "ovr2", "vp1", "vp2", "common1";
- power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 186 6>,
- <&dss_vp1_clk>,
- <&k3_clks 186 2>;
- clock-names = "fck", "vp1", "vp2";
- interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
-
- dss_ports: ports {
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-
- hwspinlock: spinlock@2a000000 {
- compatible = "ti,am64-hwspinlock";
- reg = <0x00 0x2a000000 0x00 0x1000>;
- #hwlock-cells = <1>;
- };
-
- mailbox0_cluster0: mailbox@29000000 {
- compatible = "ti,am64-mailbox";
- reg = <0x00 0x29000000 0x00 0x200>;
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- };
-
- ecap0: pwm@23100000 {
- compatible = "ti,am3352-ecap";
- #pwm-cells = <3>;
- reg = <0x00 0x23100000 0x00 0x100>;
- power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 51 0>;
- clock-names = "fck";
- status = "disabled";
- };
-
- ecap1: pwm@23110000 {
- compatible = "ti,am3352-ecap";
- #pwm-cells = <3>;
- reg = <0x00 0x23110000 0x00 0x100>;
- power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 52 0>;
- clock-names = "fck";
- status = "disabled";
- };
-
- ecap2: pwm@23120000 {
- compatible = "ti,am3352-ecap";
- #pwm-cells = <3>;
- reg = <0x00 0x23120000 0x00 0x100>;
- power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 53 0>;
- clock-names = "fck";
- status = "disabled";
- };
-
- main_mcan0: can@20701000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x20701000 0x00 0x200>,
- <0x00 0x20708000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 98 6>, <&k3_clks 98 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- main_rti0: watchdog@e000000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x0e000000 0x00 0x100>;
- clocks = <&k3_clks 125 0>;
- power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 125 0>;
- assigned-clock-parents = <&k3_clks 125 2>;
- };
-
- main_rti1: watchdog@e010000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x0e010000 0x00 0x100>;
- clocks = <&k3_clks 126 0>;
- power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 126 0>;
- assigned-clock-parents = <&k3_clks 126 2>;
- };
-
- main_rti2: watchdog@e020000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x0e020000 0x00 0x100>;
- clocks = <&k3_clks 127 0>;
- power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 127 0>;
- assigned-clock-parents = <&k3_clks 127 2>;
- };
-
- main_rti3: watchdog@e030000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x0e030000 0x00 0x100>;
- clocks = <&k3_clks 128 0>;
- power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 128 0>;
- assigned-clock-parents = <&k3_clks 128 2>;
- };
-
- main_rti15: watchdog@e0f0000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x0e0f0000 0x00 0x100>;
- clocks = <&k3_clks 130 0>;
- power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 130 0>;
- assigned-clock-parents = <&k3_clks 130 2>;
- };
-
- epwm0: pwm@23000000 {
- compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x00 0x23000000 0x00 0x100>;
- power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- epwm1: pwm@23010000 {
- compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x00 0x23010000 0x00 0x100>;
- power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- epwm2: pwm@23020000 {
- compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x00 0x23020000 0x00 0x100>;
- power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- mcasp0: audio-controller@2b00000 {
- compatible = "ti,am33xx-mcasp-audio";
- reg = <0x00 0x02b00000 0x00 0x2000>,
- <0x00 0x02b08000 0x00 0x400>;
- reg-names = "mpu", "dat";
- interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx", "rx";
-
- dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>;
- dma-names = "tx", "rx";
-
- clocks = <&k3_clks 190 0>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 190 0>;
- assigned-clock-parents = <&k3_clks 190 2>;
- power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- mcasp1: audio-controller@2b10000 {
- compatible = "ti,am33xx-mcasp-audio";
- reg = <0x00 0x02b10000 0x00 0x2000>,
- <0x00 0x02b18000 0x00 0x400>;
- reg-names = "mpu", "dat";
- interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx", "rx";
-
- dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>;
- dma-names = "tx", "rx";
-
- clocks = <&k3_clks 191 0>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 191 0>;
- assigned-clock-parents = <&k3_clks 191 2>;
- power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- mcasp2: audio-controller@2b20000 {
- compatible = "ti,am33xx-mcasp-audio";
- reg = <0x00 0x02b20000 0x00 0x2000>,
- <0x00 0x02b28000 0x00 0x400>;
- reg-names = "mpu", "dat";
- interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx", "rx";
-
- dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>;
- dma-names = "tx", "rx";
-
- clocks = <&k3_clks 192 0>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 192 0>;
- assigned-clock-parents = <&k3_clks 192 2>;
- power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- ti_csi2rx0: ticsi2rx@30102000 {
- compatible = "ti,j721e-csi2rx-shim";
- dmas = <&main_bcdma 0 0x4700 0>;
- dma-names = "rx0";
- reg = <0x00 0x30102000 0x00 0x1000>;
- power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- status = "disabled";
-
- cdns_csi2rx0: csi-bridge@30101000 {
- compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
- reg = <0x00 0x30101000 0x00 0x1000>;
- clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>,
- <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>;
- clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
- "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
- phys = <&dphy0>;
- phy-names = "dphy";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- csi0_port0: port@0 {
- reg = <0>;
- status = "disabled";
- };
-
- csi0_port1: port@1 {
- reg = <1>;
- status = "disabled";
- };
-
- csi0_port2: port@2 {
- reg = <2>;
- status = "disabled";
- };
-
- csi0_port3: port@3 {
- reg = <3>;
- status = "disabled";
- };
-
- csi0_port4: port@4 {
- reg = <4>;
- status = "disabled";
- };
- };
- };
- };
-
- dphy0: phy@30110000 {
- compatible = "cdns,dphy-rx";
- reg = <0x00 0x30110000 0x00 0x1100>;
- #phy-cells = <0>;
- power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
-};
diff --git a/arch/arm/dts/k3-am62-mcu.dtsi b/arch/arm/dts/k3-am62-mcu.dtsi
deleted file mode 100644
index e66d486..0000000
--- a/arch/arm/dts/k3-am62-mcu.dtsi
+++ /dev/null
@@ -1,176 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-/*
- * Device Tree Source for AM625 SoC Family MCU Domain peripherals
- *
- * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-&cbass_mcu {
- mcu_pmx0: pinctrl@4084000 {
- bootph-all;
- compatible = "pinctrl-single";
- reg = <0x00 0x04084000 0x00 0x88>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0xffffffff>;
- };
-
- mcu_esm: esm@4100000 {
- bootph-pre-ram;
- compatible = "ti,j721e-esm";
- reg = <0x00 0x4100000 0x00 0x1000>;
- ti,esm-pins = <0>, <1>, <2>, <85>;
- };
-
- /*
- * The MCU domain timer interrupts are routed only to the ESM module,
- * and not currently available for Linux. The MCU domain timers are
- * of limited use without interrupts, and likely reserved by the ESM.
- */
- mcu_timer0: timer@4800000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x4800000 0x00 0x400>;
- clocks = <&k3_clks 35 2>;
- clock-names = "fck";
- power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- status = "reserved";
- };
-
- mcu_timer1: timer@4810000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x4810000 0x00 0x400>;
- clocks = <&k3_clks 48 2>;
- clock-names = "fck";
- power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- status = "reserved";
- };
-
- mcu_timer2: timer@4820000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x4820000 0x00 0x400>;
- clocks = <&k3_clks 49 2>;
- clock-names = "fck";
- power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- status = "reserved";
- };
-
- mcu_timer3: timer@4830000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x4830000 0x00 0x400>;
- clocks = <&k3_clks 50 2>;
- clock-names = "fck";
- power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- status = "reserved";
- };
-
- mcu_uart0: serial@4a00000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x04a00000 0x00 0x100>;
- interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 149 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- mcu_i2c0: i2c@4900000 {
- compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x04900000 0x00 0x100>;
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 106 2>;
- clock-names = "fck";
- status = "disabled";
- };
-
- mcu_spi0: spi@4b00000 {
- compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
- reg = <0x00 0x04b00000 0x00 0x400>;
- interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 147 0>;
- status = "disabled";
- };
-
- mcu_spi1: spi@4b10000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x04b10000 0x00 0x400>;
- interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 148 0>;
- status = "disabled";
- };
-
- mcu_gpio_intr: interrupt-controller@4210000 {
- compatible = "ti,sci-intr";
- reg = <0x00 0x04210000 0x00 0x200>;
- ti,intr-trigger-type = <1>;
- interrupt-controller;
- interrupt-parent = <&gic500>;
- #interrupt-cells = <1>;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <5>;
- ti,interrupt-ranges = <0 104 4>;
- };
-
- mcu_gpio0: gpio@4201000 {
- compatible = "ti,am64-gpio", "ti,keystone-gpio";
- reg = <0x00 0x4201000 0x00 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&mcu_gpio_intr>;
- interrupts = <30>, <31>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <24>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 79 0>;
- clock-names = "gpio";
- };
-
- mcu_rti0: watchdog@4880000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x04880000 0x00 0x100>;
- clocks = <&k3_clks 131 0>;
- power-domains = <&k3_pds 131 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 131 0>;
- assigned-clock-parents = <&k3_clks 131 2>;
- /* Tightly coupled to M4F */
- status = "reserved";
- };
-
- mcu_mcan0: can@4e08000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x4e08000 0x00 0x200>,
- <0x00 0x4e00000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 188 6>, <&k3_clks 188 1>;
- clock-names = "hclk", "cclk";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- mcu_mcan1: can@4e18000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x4e18000 0x00 0x200>,
- <0x00 0x4e10000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 189 6>, <&k3_clks 189 1>;
- clock-names = "hclk", "cclk";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-};
diff --git a/arch/arm/dts/k3-am62-r5-lp-sk.dts b/arch/arm/dts/k3-am62-r5-lp-sk.dts
new file mode 100644
index 0000000..ec5d3f4
--- /dev/null
+++ b/arch/arm/dts/k3-am62-r5-lp-sk.dts
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * AM62x LP SK dts file for R5 SPL
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include "k3-am62-lp-sk.dts"
+#include "k3-am62-lp4-50-800-800.dtsi"
+#include "k3-am62-ddr.dtsi"
+
+#include "k3-am62-lp-sk-u-boot.dtsi"
+
+/ {
+ aliases {
+ remoteproc0 = &sysctrler;
+ remoteproc1 = &a53_0;
+ serial0 = &wkup_uart0;
+ serial3 = &main_uart1;
+ };
+
+ a53_0: a53@0 {
+ compatible = "ti,am654-rproc";
+ reg = <0x00 0x00a90000 0x00 0x10>;
+ power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+ <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
+ <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
+ resets = <&k3_reset 135 0>;
+ clocks = <&k3_clks 61 0>;
+ assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+ assigned-clock-parents = <&k3_clks 61 2>;
+ assigned-clock-rates = <200000000>, <1200000000>;
+ ti,sci = <&dmsc>;
+ ti,sci-proc-id = <32>;
+ ti,sci-host-id = <10>;
+ bootph-pre-ram;
+ };
+
+ dm_tifs: dm-tifs {
+ compatible = "ti,j721e-dm-sci";
+ ti,host-id = <36>;
+ ti,secure-host;
+ mbox-names = "rx", "tx";
+ mboxes= <&secure_proxy_main 22>,
+ <&secure_proxy_main 23>;
+ bootph-pre-ram;
+ };
+};
+
+&dmsc {
+ mboxes= <&secure_proxy_main 0>,
+ <&secure_proxy_main 1>,
+ <&secure_proxy_main 0>;
+ mbox-names = "rx", "tx", "notify";
+ ti,host-id = <35>;
+ ti,secure-host;
+};
+
+&secure_proxy_sa3 {
+ /* We require this for boot handshake */
+ status = "okay";
+};
+
+&cbass_main {
+ sysctrler: sysctrler {
+ compatible = "ti,am654-system-controller";
+ mboxes= <&secure_proxy_main 1>,
+ <&secure_proxy_main 0>,
+ <&secure_proxy_sa3 0>;
+ mbox-names = "tx", "rx", "boot_notify";
+ bootph-pre-ram;
+ };
+};
+
+/* WKUP UART0 is used for DM firmware logs */
+&wkup_uart0 {
+ status = "okay";
+};
+
+/* Main UART1 is used for TIFS firmware logs */
+&main_uart1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/k3-am62-thermal.dtsi b/arch/arm/dts/k3-am62-thermal.dtsi
deleted file mode 100644
index 12ba833..0000000
--- a/arch/arm/dts/k3-am62-thermal.dtsi
+++ /dev/null
@@ -1,36 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-/*
- * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#include <dt-bindings/thermal/thermal.h>
-
-thermal_zones: thermal-zones {
- main0_thermal: main0-thermal {
- polling-delay-passive = <250>; /* milliSeconds */
- polling-delay = <500>; /* milliSeconds */
- thermal-sensors = <&wkup_vtm0 0>;
-
- trips {
- main0_crit: main0-crit {
- temperature = <105000>; /* milliCelsius */
- hysteresis = <2000>; /* milliCelsius */
- type = "critical";
- };
- };
- };
-
- main1_thermal: main1-thermal {
- polling-delay-passive = <250>; /* milliSeconds */
- polling-delay = <500>; /* milliSeconds */
- thermal-sensors = <&wkup_vtm0 1>;
-
- trips {
- main1_crit: main1-crit {
- temperature = <105000>; /* milliCelsius */
- hysteresis = <2000>; /* milliCelsius */
- type = "critical";
- };
- };
- };
-};
diff --git a/arch/arm/dts/k3-am62-wakeup.dtsi b/arch/arm/dts/k3-am62-wakeup.dtsi
deleted file mode 100644
index 23ce1bf..0000000
--- a/arch/arm/dts/k3-am62-wakeup.dtsi
+++ /dev/null
@@ -1,96 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-/*
- * Device Tree Source for AM625 SoC Family Wakeup Domain peripherals
- *
- * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#include <dt-bindings/bus/ti-sysc.h>
-
-&cbass_wakeup {
- wkup_conf: syscon@43000000 {
- bootph-all;
- compatible = "syscon", "simple-mfd";
- reg = <0x00 0x43000000 0x00 0x20000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x00 0x43000000 0x20000>;
-
- chipid: chipid@14 {
- bootph-all;
- compatible = "ti,am654-chipid";
- reg = <0x14 0x4>;
- };
- };
-
- target-module@2b300050 {
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x00 0x2b300050 0x00 0x4>,
- <0x00 0x2b300054 0x00 0x4>,
- <0x00 0x2b300058 0x00 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- ti,no-reset-on-init;
- power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 114 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x00 0x2b300000 0x100000>;
-
- wkup_uart0: serial@0 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x0 0x100>;
- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
- };
-
- wkup_i2c0: i2c@2b200000 {
- compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x2b200000 0x00 0x100>;
- interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 107 4>;
- clock-names = "fck";
- status = "disabled";
- };
-
- wkup_rtc0: rtc@2b1f0000 {
- compatible = "ti,am62-rtc";
- reg = <0x00 0x2b1f0000 0x00 0x100>;
- interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 117 6> , <&k3_clks 117 0>;
- clock-names = "vbus", "osc32k";
- power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>;
- wakeup-source;
- };
-
- wkup_rti0: watchdog@2b000000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x2b000000 0x00 0x100>;
- clocks = <&k3_clks 132 0>;
- power-domains = <&k3_pds 132 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 132 0>;
- assigned-clock-parents = <&k3_clks 132 2>;
- /* Used by DM firmware */
- status = "reserved";
- };
-
- wkup_vtm0: temperature-sensor@b00000 {
- compatible = "ti,j7200-vtm";
- reg = <0x00 0xb00000 0x00 0x400>,
- <0x00 0xb01000 0x00 0x400>;
- power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>;
- #thermal-sensor-cells = <1>;
- };
-};
diff --git a/arch/arm/dts/k3-am62.dtsi b/arch/arm/dts/k3-am62.dtsi
deleted file mode 100644
index f0781f2..0000000
--- a/arch/arm/dts/k3-am62.dtsi
+++ /dev/null
@@ -1,122 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-/*
- * Device Tree Source for AM62 SoC Family
- *
- * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/soc/ti,sci_pm_domain.h>
-
-#include "k3-pinctrl.h"
-
-/ {
- model = "Texas Instruments K3 AM625 SoC";
- compatible = "ti,am625";
- interrupt-parent = <&gic500>;
- #address-cells = <2>;
- #size-cells = <2>;
-
- chosen { };
-
- firmware {
- optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- };
-
- psci: psci {
- compatible = "arm,psci-1.0";
- method = "smc";
- };
- };
-
- a53_timer0: timer-cl0-cpu0 {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
- <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
- <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
- };
-
- pmu: pmu {
- compatible = "arm,cortex-a53-pmu";
- interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- cbass_main: bus@f0000 {
- bootph-all;
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
-
- ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
- <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
- <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
- <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
- <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
- <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
- <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
- <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
- <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
- <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
- <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
- <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
- <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */
- <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
- <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
- <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
- <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
- <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
- <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
- <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
- <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */
- <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
- <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */
- <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
- <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
-
- /* MCU Domain Range */
- <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>,
-
- /* Wakeup Domain Range */
- <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
- <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>,
- <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>;
-
- cbass_mcu: bus@4000000 {
- bootph-all;
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */
- };
-
- cbass_wakeup: bus@b00000 {
- bootph-all;
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
- <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
- <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>;
- };
- };
-
- dss_vp1_clk: clock-divider-oldi {
- compatible = "fixed-factor-clock";
- clocks = <&k3_clks 186 0>;
- #clock-cells = <0>;
- clock-div = <7>;
- clock-mult = <1>;
- };
-
- #include "k3-am62-thermal.dtsi"
-};
-
-/* Now include the peripherals for each bus segments */
-#include "k3-am62-main.dtsi"
-#include "k3-am62-mcu.dtsi"
-#include "k3-am62-wakeup.dtsi"
diff --git a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
index 9ac4a82..467cac6 100644
--- a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
+++ b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
@@ -66,9 +66,9 @@
#ifdef CONFIG_TARGET_AM625_A53_BEAGLEPLAY
#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
-#define SPL_AM625_BEAGLEPLAY_DTB "spl/dts/k3-am625-beagleplay.dtb"
+#define SPL_AM625_BEAGLEPLAY_DTB "spl/dts/ti/k3-am625-beagleplay.dtb"
#define UBOOT_NODTB "u-boot-nodtb.bin"
-#define AM625_BEAGLEPLAY_DTB "arch/arm/dts/k3-am625-beagleplay.dtb"
+#define AM625_BEAGLEPLAY_DTB "dts/upstream/src/arm64/ti/k3-am625-beagleplay.dtb"
&binman {
ti-dm {
@@ -80,6 +80,7 @@
ti-spl_unsigned {
filename = "tispl.bin_unsigned";
+ symlink = "tispl.bin";
pad-byte = <0xff>;
fit {
@@ -214,6 +215,33 @@
};
};
};
+
+#include "k3-binman-capsule.dtsi"
+
+// Capsule update GUIDs in string form. See beagleplay.h
+#define BEAGLEPLAY_SPL_IMAGE_GUID_STR "b2e7cc49-1a5a-4036-ae01-3387c3bef657"
+#define BEAGLEPLAY_UBOOT_IMAGE_GUID_STR "92c92b11-a7ee-486f-aaa2-713d84425b0e"
+
+&capsule_tispl {
+ efi-capsule {
+ image-guid = BEAGLEPLAY_SPL_IMAGE_GUID_STR;
+
+ blob {
+ filename = "tispl.bin_unsigned";
+ };
+ };
+};
+
+&capsule_uboot {
+ efi-capsule {
+ image-guid = BEAGLEPLAY_UBOOT_IMAGE_GUID_STR;
+
+ blob {
+ filename = "u-boot.img_unsigned";
+ };
+ };
+};
+
#endif
&main_bcdma {
diff --git a/arch/arm/dts/k3-am625-beagleplay.dts b/arch/arm/dts/k3-am625-beagleplay.dts
deleted file mode 100644
index 8ab838f..0000000
--- a/arch/arm/dts/k3-am625-beagleplay.dts
+++ /dev/null
@@ -1,932 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-/*
- * https://beagleplay.org/
- *
- * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
- * Copyright (C) 2022-2024 Robert Nelson, BeagleBoard.org Foundation
- */
-
-/dts-v1/;
-
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include "k3-am625.dtsi"
-
-/ {
- compatible = "beagle,am625-beagleplay", "ti,am625";
- model = "BeagleBoard.org BeaglePlay";
-
- aliases {
- ethernet0 = &cpsw_port1;
- ethernet1 = &cpsw_port2;
- gpio0 = &main_gpio0;
- gpio1 = &main_gpio1;
- gpio2 = &mcu_gpio0;
- i2c0 = &main_i2c0;
- i2c1 = &main_i2c1;
- i2c2 = &main_i2c2;
- i2c3 = &main_i2c3;
- i2c4 = &wkup_i2c0;
- i2c5 = &mcu_i2c0;
- mmc0 = &sdhci0;
- mmc1 = &sdhci1;
- mmc2 = &sdhci2;
- rtc0 = &rtc;
- serial0 = &main_uart5;
- serial1 = &main_uart6;
- serial2 = &main_uart0;
- usb0 = &usb0;
- usb1 = &usb1;
- };
-
- chosen {
- stdout-path = "serial2:115200n8";
- };
-
- memory@80000000 {
- bootph-pre-ram;
- device_type = "memory";
- /* 2G RAM */
- reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- ramoops: ramoops@9ca00000 {
- compatible = "ramoops";
- reg = <0x00 0x9ca00000 0x00 0x00100000>;
- record-size = <0x8000>;
- console-size = <0x8000>;
- ftrace-size = <0x00>;
- pmsg-size = <0x8000>;
- };
-
- secure_tfa_ddr: tfa@9e780000 {
- reg = <0x00 0x9e780000 0x00 0x80000>;
- no-map;
- };
-
- secure_ddr: optee@9e800000 {
- reg = <0x00 0x9e800000 0x00 0x01800000>;
- no-map;
- };
-
- wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0x9db00000 0x00 0xc00000>;
- no-map;
- };
- };
-
- vsys_5v0: regulator-1 {
- bootph-all;
- compatible = "regulator-fixed";
- regulator-name = "vsys_5v0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vdd_3v3: regulator-2 {
- /* output of TLV62595DMQR-U12 */
- bootph-all;
- compatible = "regulator-fixed";
- regulator-name = "vdd_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vsys_5v0>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- wlan_en: regulator-3 {
- /* OUTPUT of SN74AVC2T244DQMR */
- compatible = "regulator-fixed";
- regulator-name = "wlan_en";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- enable-active-high;
- regulator-always-on;
- vin-supply = <&vdd_3v3>;
- gpio = <&main_gpio0 38 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_en_pins_default>;
- };
-
- vdd_3v3_sd: regulator-4 {
- /* output of TPS22918DBVR-U21 */
- bootph-all;
- pinctrl-names = "default";
- pinctrl-0 = <&vdd_3v3_sd_pins_default>;
-
- compatible = "regulator-fixed";
- regulator-name = "vdd_3v3_sd";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- enable-active-high;
- regulator-always-on;
- vin-supply = <&vdd_3v3>;
- gpio = <&main_gpio1 19 GPIO_ACTIVE_HIGH>;
- };
-
- vdd_sd_dv: regulator-5 {
- bootph-all;
- compatible = "regulator-gpio";
- regulator-name = "sd_hs200_switch";
- pinctrl-names = "default";
- pinctrl-0 = <&vdd_sd_dv_pins_default>;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- vin-supply = <&ldo1_reg>;
- gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>;
- states = <1800000 0x0>,
- <3300000 0x1>;
- };
-
- leds {
- bootph-all;
- compatible = "gpio-leds";
-
- led-0 {
- bootph-all;
- gpios = <&main_gpio0 3 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- function = LED_FUNCTION_HEARTBEAT;
- default-state = "off";
- };
-
- led-1 {
- bootph-all;
- gpios = <&main_gpio0 4 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "disk-activity";
- function = LED_FUNCTION_DISK_ACTIVITY;
- default-state = "keep";
- };
-
- led-2 {
- bootph-all;
- gpios = <&main_gpio0 5 GPIO_ACTIVE_HIGH>;
- function = LED_FUNCTION_CPU;
- };
-
- led-3 {
- bootph-all;
- gpios = <&main_gpio0 6 GPIO_ACTIVE_HIGH>;
- function = LED_FUNCTION_LAN;
- };
-
- led-4 {
- bootph-all;
- gpios = <&main_gpio0 9 GPIO_ACTIVE_HIGH>;
- function = LED_FUNCTION_WLAN;
- };
- };
-
- gpio_keys: gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
- pinctrl-names = "default";
- pinctrl-0 = <&usr_button_pins_default>;
-
- usr: button-usr {
- label = "User Key";
- linux,code = <BTN_0>;
- gpios = <&main_gpio0 18 GPIO_ACTIVE_LOW>;
- };
-
- };
-
- hdmi0: connector-hdmi {
- compatible = "hdmi-connector";
- label = "hdmi";
- type = "a";
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&it66121_out>;
- };
- };
- };
-
- sound {
- compatible = "simple-audio-card";
- simple-audio-card,name = "it66121 HDMI";
- simple-audio-card,format = "i2s";
- simple-audio-card,bitclock-master = <&hdmi_dailink_master>;
- simple-audio-card,frame-master = <&hdmi_dailink_master>;
-
- hdmi_dailink_master: simple-audio-card,cpu {
- sound-dai = <&mcasp1>;
- system-clock-direction-out;
- };
-
- simple-audio-card,codec {
- sound-dai = <&it66121>;
- };
- };
-
-};
-
-&main_pmx0 {
- gpio0_pins_default: gpio0-default-pins {
- bootph-all;
- pinctrl-single,pins = <
- AM62X_IOPAD(0x0004, PIN_INPUT, 7) /* (G25) OSPI0_LBCLKO.GPIO0_1 */
- AM62X_IOPAD(0x0008, PIN_INPUT, 7) /* (J24) OSPI0_DQS.GPIO0_2 */
- AM62X_IOPAD(0x000c, PIN_INPUT, 7) /* (E25) OSPI0_D0.GPIO0_3 */
- AM62X_IOPAD(0x0010, PIN_INPUT, 7) /* (G24) OSPI0_D1.GPIO0_4 */
- AM62X_IOPAD(0x0014, PIN_INPUT, 7) /* (F25) OSPI0_D2.GPIO0_5 */
- AM62X_IOPAD(0x0018, PIN_INPUT, 7) /* (F24) OSPI0_D3.GPIO0_6 */
- AM62X_IOPAD(0x0024, PIN_INPUT, 7) /* (H25) OSPI0_D6.GPIO0_9 */
- AM62X_IOPAD(0x0028, PIN_INPUT, 7) /* (J22) OSPI0_D7.GPIO0_10 */
- AM62X_IOPAD(0x002c, PIN_INPUT, 7) /* (F23) OSPI0_CSn0.GPIO0_11 */
- AM62X_IOPAD(0x0030, PIN_INPUT, 7) /* (G21) OSPI0_CSn1.GPIO0_12 */
- AM62X_IOPAD(0x0034, PIN_INPUT, 7) /* (H21) OSPI0_CSn2.GPIO0_13 */
- AM62X_IOPAD(0x0038, PIN_INPUT, 7) /* (E24) OSPI0_CSn3.GPIO0_14 */
- AM62X_IOPAD(0x00a4, PIN_INPUT, 7) /* (M22) GPMC0_DIR.GPIO0_40 */
- AM62X_IOPAD(0x00ac, PIN_INPUT, 7) /* (L21) GPMC0_CSn1.GPIO0_42 */
- >;
- };
-
- vdd_sd_dv_pins_default: vdd-sd-default-pins {
- bootph-all;
- pinctrl-single,pins = <
- AM62X_IOPAD(0x0244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */
- >;
- };
-
- usr_button_pins_default: usr-button-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x0048, PIN_INPUT, 7) /* (N25) GPMC0_AD3.GPIO0_18 */
- >;
- };
-
- grove_pins_default: grove-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
- AM62X_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */
- >;
- };
-
- local_i2c_pins_default: local-i2c-default-pins {
- bootph-all;
- pinctrl-single,pins = <
- AM62X_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
- AM62X_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
- >;
- };
-
- i2c2_1v8_pins_default: i2c2-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */
- AM62X_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */
- >;
- };
-
- mdio0_pins_default: mdio0-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x0160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */
- AM62X_IOPAD(0x015c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */
- AM62X_IOPAD(0x003c, PIN_INPUT, 7) /* (M25) GPMC0_AD0.GPIO0_15 */
- AM62X_IOPAD(0x018c, PIN_INPUT, 7) /* (AC21) RGMII2_RD2.GPIO1_5 */
- >;
- };
-
- rgmii1_pins_default: rgmii1-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x014c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */
- AM62X_IOPAD(0x0150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */
- AM62X_IOPAD(0x0154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */
- AM62X_IOPAD(0x0158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */
- AM62X_IOPAD(0x0148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */
- AM62X_IOPAD(0x0144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */
- AM62X_IOPAD(0x0134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */
- AM62X_IOPAD(0x0138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */
- AM62X_IOPAD(0x013c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */
- AM62X_IOPAD(0x0140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */
- AM62X_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */
- AM62X_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */
- >;
- };
-
- emmc_pins_default: emmc-default-pins {
- bootph-all;
- pinctrl-single,pins = <
- AM62X_IOPAD(0x0220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */
- AM62X_IOPAD(0x0218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */
- AM62X_IOPAD(0x0214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */
- AM62X_IOPAD(0x0210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */
- AM62X_IOPAD(0x020c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */
- AM62X_IOPAD(0x0208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */
- AM62X_IOPAD(0x0204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */
- AM62X_IOPAD(0x0200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */
- AM62X_IOPAD(0x01fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */
- AM62X_IOPAD(0x01f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */
- >;
- };
-
- vdd_3v3_sd_pins_default: vdd-3v3-sd-default-pins {
- bootph-all;
- pinctrl-single,pins = <
- AM62X_IOPAD(0x01c4, PIN_INPUT, 7) /* (B14) SPI0_D1_GPIO1_19 */
- >;
- };
-
- sd_pins_default: sd-default-pins {
- bootph-all;
- pinctrl-single,pins = <
- AM62X_IOPAD(0x023c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
- AM62X_IOPAD(0x0234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
- AM62X_IOPAD(0x0230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */
- AM62X_IOPAD(0x022c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */
- AM62X_IOPAD(0x0228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */
- AM62X_IOPAD(0x0224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */
- AM62X_IOPAD(0x0240, PIN_INPUT, 7) /* (D17) MMC1_SDCD.GPIO1_48 */
- >;
- };
-
- wifi_pins_default: wifi-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x0120, PIN_INPUT, 0) /* (C24) MMC2_CMD */
- AM62X_IOPAD(0x0118, PIN_INPUT, 0) /* (D25) MMC2_CLK */
- AM62X_IOPAD(0x0114, PIN_INPUT, 0) /* (B24) MMC2_DAT0 */
- AM62X_IOPAD(0x0110, PIN_INPUT, 0) /* (C25) MMC2_DAT1 */
- AM62X_IOPAD(0x010c, PIN_INPUT, 0) /* (E23) MMC2_DAT2 */
- AM62X_IOPAD(0x0108, PIN_INPUT, 0) /* (D24) MMC2_DAT3 */
- AM62X_IOPAD(0x0124, PIN_INPUT, 0) /* (A23) MMC2_SDCD */
- AM62X_IOPAD(0x11c, PIN_INPUT, 0) /* (#N/A) MMC2_CLKB */
- >;
- };
-
- wifi_en_pins_default: wifi-en-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x009c, PIN_OUTPUT, 7) /* (V25) GPMC0_WAIT1.GPIO0_38 */
- >;
- };
-
- wifi_wlirq_pins_default: wifi-wlirq-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x00a8, PIN_INPUT, 7) /* (M21) GPMC0_CSn0.GPIO0_41 */
- >;
- };
-
- spe_pins_default: spe-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x0168, PIN_INPUT, 1) /* (AE21) RGMII2_TXC.RMII2_CRS_DV */
- AM62X_IOPAD(0x0180, PIN_INPUT, 1) /* (AD23) RGMII2_RXC.RMII2_REF_CLK */
- AM62X_IOPAD(0x0184, PIN_INPUT, 1) /* (AE23) RGMII2_RD0.RMII2_RXD0 */
- AM62X_IOPAD(0x0188, PIN_INPUT, 1) /* (AB20) RGMII2_RD1.RMII2_RXD1 */
- AM62X_IOPAD(0x017c, PIN_INPUT, 1) /* (AD22) RGMII2_RX_CTL.RMII2_RX_ER */
- AM62X_IOPAD(0x016c, PIN_INPUT, 1) /* (Y18) RGMII2_TD0.RMII2_TXD0 */
- AM62X_IOPAD(0x0170, PIN_INPUT, 1) /* (AA18) RGMII2_TD1.RMII2_TXD1 */
- AM62X_IOPAD(0x0164, PIN_INPUT, 1) /* (AA19) RGMII2_TX_CTL.RMII2_TX_EN */
- AM62X_IOPAD(0x0190, PIN_INPUT, 7) /* (AE22) RGMII2_RD3.GPIO1_6 */
- AM62X_IOPAD(0x01f0, PIN_OUTPUT, 5) /* (A18) EXT_REFCLK1.CLKOUT0 */
- >;
- };
-
- mikrobus_i2c_pins_default: mikrobus-i2c-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x01d0, PIN_INPUT_PULLUP, 2) /* (A15) UART0_CTSn.I2C3_SCL */
- AM62X_IOPAD(0x01d4, PIN_INPUT_PULLUP, 2) /* (B15) UART0_RTSn.I2C3_SDA */
- >;
- };
-
- mikrobus_uart_pins_default: mikrobus-uart-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x01d8, PIN_INPUT, 1) /* (C15) MCAN0_TX.UART5_RXD */
- AM62X_IOPAD(0x01dc, PIN_OUTPUT, 1) /* (E15) MCAN0_RX.UART5_TXD */
- >;
- };
-
- mikrobus_spi_pins_default: mikrobus-spi-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x01b0, PIN_INPUT, 1) /* (A20) MCASP0_ACLKR.SPI2_CLK */
- AM62X_IOPAD(0x01ac, PIN_INPUT, 1) /* (E19) MCASP0_AFSR.SPI2_CS0 */
- AM62X_IOPAD(0x0194, PIN_INPUT, 1) /* (B19) MCASP0_AXR3.SPI2_D0 */
- AM62X_IOPAD(0x0198, PIN_INPUT, 1) /* (A19) MCASP0_AXR2.SPI2_D1 */
- >;
- };
-
- mikrobus_gpio_pins_default: mikrobus-gpio-default-pins {
- bootph-all;
- pinctrl-single,pins = <
- AM62X_IOPAD(0x019c, PIN_INPUT, 7) /* (B18) MCASP0_AXR1.GPIO1_9 */
- AM62X_IOPAD(0x01a0, PIN_INPUT, 7) /* (E18) MCASP0_AXR0.GPIO1_10 */
- AM62X_IOPAD(0x01a8, PIN_INPUT, 7) /* (D20) MCASP0_AFSX.GPIO1_12 */
- >;
- };
-
- main_uart0_pins_default: main-uart0-default-pins {
- bootph-all;
- pinctrl-single,pins = <
- AM62X_IOPAD(0x01c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
- AM62X_IOPAD(0x01cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
- >;
- };
-
- wifi_debug_uart_pins_default: wifi-debug-uart-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x001c, PIN_INPUT, 3) /* (J23) OSPI0_D4.UART6_RXD */
- AM62X_IOPAD(0x0020, PIN_OUTPUT, 3) /* (J25) OSPI0_D5.UART6_TXD */
- >;
- };
-
- usb1_pins_default: usb1-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x0258, PIN_INPUT, 0) /* (F18) USB1_DRVVBUS */
- >;
- };
-
- pmic_irq_pins_default: pmic-irq-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x01f4, PIN_INPUT_PULLUP, 0) /* (D16) EXTINTn */
- >;
- };
-
- hdmi_gpio_pins_default: hdmi-gpio-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x0094, PIN_INPUT_PULLUP | PIN_DEBOUNCE_CONF6, 7) /* (N20) GPMC0_BE1n.GPIO0_36 */
- AM62X_IOPAD(0x0054, PIN_OUTPUT_PULLUP, 7) /* (P21) GPMC0_AD6.GPIO0_21 */
- >;
- };
-
- mcasp_hdmi_pins_default: mcasp-hdmi-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x0090, PIN_INPUT, 2) /* (M24) GPMC0_BE0n_CLE.MCASP1_ACLKX */
- AM62X_IOPAD(0x0098, PIN_INPUT, 2) /* (U23) GPMC0_WAIT0.MCASP1_AFSX */
- AM62X_IOPAD(0x008c, PIN_OUTPUT, 2) /* (L25) GPMC0_WEn.MCASP1_AXR0 */
- AM62X_IOPAD(0x0088, PIN_INPUT, 2) /* (L24) GPMC0_OEn_REn.MCASP1_AXR1 */
- AM62X_IOPAD(0x0084, PIN_INPUT, 2) /* (L23) GPMC0_ADVn_ALE.MCASP1_AXR2 */
- AM62X_IOPAD(0x007c, PIN_INPUT, 2) /* (P25) GPMC0_CLK.MCASP1_AXR3 */
- >;
- };
-
- dss0_pins_default: dss0-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x0100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC */
- AM62X_IOPAD(0x00f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */
- AM62X_IOPAD(0x0104, PIN_OUTPUT, 0) /* (AC24) VOUT0_PCLK */
- AM62X_IOPAD(0x00fc, PIN_OUTPUT, 0) /* (Y20) VOUT0_DE */
- AM62X_IOPAD(0x00b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */
- AM62X_IOPAD(0x00bc, PIN_OUTPUT, 0) /* (V24) VOUT0_DATA1 */
- AM62X_IOPAD(0x00c0, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA2 */
- AM62X_IOPAD(0x00c4, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA3 */
- AM62X_IOPAD(0x00c8, PIN_OUTPUT, 0) /* (Y25) VOUT0_DATA4 */
- AM62X_IOPAD(0x00cc, PIN_OUTPUT, 0) /* (Y24) VOUT0_DATA5 */
- AM62X_IOPAD(0x00d0, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA6 */
- AM62X_IOPAD(0x00d4, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA7 */
- AM62X_IOPAD(0x00d8, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA8 */
- AM62X_IOPAD(0x00dc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA9 */
- AM62X_IOPAD(0x00e0, PIN_OUTPUT, 0) /* (V20) VOUT0_DATA10 */
- AM62X_IOPAD(0x00e4, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA11 */
- AM62X_IOPAD(0x00e8, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA12 */
- AM62X_IOPAD(0x00ec, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA13 */
- AM62X_IOPAD(0x00f0, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA14 */
- AM62X_IOPAD(0x00f4, PIN_OUTPUT, 0) /* (AA21) VOUT0_DATA15 */
- AM62X_IOPAD(0x005c, PIN_OUTPUT, 1) /* (R24) GPMC0_AD8.VOUT0_DATA16 */
- AM62X_IOPAD(0x0060, PIN_OUTPUT, 1) /* (R25) GPMC0_AD9.VOUT0_DATA17 */
- AM62X_IOPAD(0x0064, PIN_OUTPUT, 1) /* (T25) GPMC0_AD10.VOUT0_DATA18 */
- AM62X_IOPAD(0x0068, PIN_OUTPUT, 1) /* (R21) GPMC0_AD11.VOUT0_DATA19 */
- AM62X_IOPAD(0x006c, PIN_OUTPUT, 1) /* (T22) GPMC0_AD12.VOUT0_DATA20 */
- AM62X_IOPAD(0x0070, PIN_OUTPUT, 1) /* (T24) GPMC0_AD13.VOUT0_DATA21 */
- AM62X_IOPAD(0x0074, PIN_OUTPUT, 1) /* (U25) GPMC0_AD14.VOUT0_DATA22 */
- AM62X_IOPAD(0x0078, PIN_OUTPUT, 1) /* (U24) GPMC0_AD15.VOUT0_DATA23 */
- >;
- };
-};
-
-&mcu_pmx0 {
- i2c_qwiic_pins_default: i2c-qwiic-default-pins {
- pinctrl-single,pins = <
- AM62X_MCU_IOPAD(0x0044, PIN_INPUT, 0) /* (A8) MCU_I2C0_SCL */
- AM62X_MCU_IOPAD(0x0048, PIN_INPUT, 0) /* (D10) MCU_I2C0_SDA */
- >;
- };
-
- gbe_pmx_obsclk: gbe-pmx-obsclk-default-pins {
- pinctrl-single,pins = <
- AM62X_MCU_IOPAD(0x0004, PIN_OUTPUT, 1) /* (B8) MCU_SPI0_CS1.MCU_OBSCLK0 */
- >;
- };
-
- i2c_csi_pins_default: i2c-csi-default-pins {
- pinctrl-single,pins = <
- AM62X_MCU_IOPAD(0x004c, PIN_INPUT_PULLUP, 0) /* (B9) WKUP_I2C0_SCL */
- AM62X_MCU_IOPAD(0x0050, PIN_INPUT_PULLUP, 0) /* (A9) WKUP_I2C0_SDA */
- >;
- };
-
- wifi_32k_clk: mcu-clk-out-default-pins {
- pinctrl-single,pins = <
- AM62X_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (A12) WKUP_CLKOUT0 */
- >;
- };
-};
-
-&a53_opp_table {
- /* Requires VDD_CORE to be at 0.85V */
- opp-1400000000 {
- opp-hz = /bits/ 64 <1400000000>;
- opp-supported-hw = <0x01 0x0004>;
- };
-};
-
-&wkup_i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c_csi_pins_default>;
- clock-frequency = <400000>;
- /* Enable with overlay for camera sensor */
-};
-
-&mcu_i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c_qwiic_pins_default>;
- clock-frequency = <100000>;
- status = "okay";
-};
-
-&usbss0 {
- bootph-all;
- ti,vbus-divider;
- status = "okay";
-};
-
-&usb0 {
- bootph-all;
- dr_mode = "peripheral";
-};
-
-&usbss1 {
- ti,vbus-divider;
- status = "okay";
-};
-
-&usb1 {
- dr_mode = "host";
- pinctrl-names = "default";
- pinctrl-0 = <&usb1_pins_default>;
-};
-
-&cpsw3g {
- pinctrl-names = "default";
- pinctrl-0 = <&rgmii1_pins_default>, <&spe_pins_default>,
- <&gbe_pmx_obsclk>;
- assigned-clocks = <&k3_clks 157 70>, <&k3_clks 157 20>;
- assigned-clock-parents = <&k3_clks 157 72>, <&k3_clks 157 22>;
-};
-
-&cpsw_port1 {
- phy-mode = "rgmii-rxid";
- phy-handle = <&cpsw3g_phy0>;
-};
-
-&cpsw_port2 {
- phy-mode = "rmii";
- phy-handle = <&cpsw3g_phy1>;
-};
-
-&cpsw3g_mdio {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mdio0_pins_default>;
-
- cpsw3g_phy0: ethernet-phy@0 {
- reg = <0>;
- reset-gpios = <&main_gpio0 15 GPIO_ACTIVE_LOW>;
- reset-assert-us = <10000>;
- reset-deassert-us = <50000>;
- };
-
- cpsw3g_phy1: ethernet-phy@1 {
- reg = <1>;
- reset-gpios = <&main_gpio1 5 GPIO_ACTIVE_LOW>;
- reset-assert-us = <25>;
- reset-deassert-us = <60000>; /* T2 */
- };
-};
-
-&main_gpio0 {
- bootph-all;
- pinctrl-names = "default";
- pinctrl-0 = <&gpio0_pins_default>;
- gpio-line-names = "BL_EN_3V3", "SPE_PO_EN", "RTC_INT", /* 0-2 */
- "USR0", "USR1", "USR2", "USR3", "", "", "USR4", /* 3-9 */
- "EEPROM_WP", /* 10 */
- "CSI2_CAMERA_GPIO1", "CSI2_CAMERA_GPIO2", /* 11-12 */
- "CC1352P7_BOOT", "CC1352P7_RSTN", "GBE_RSTN", "", "", /* 13-17 */
- "USR_BUTTON", "", "", "", "", "", "", "", "", /* 18-26 */
- "", "", "", "", "", "", "", "", "", "HDMI_INT", /* 27-36 */
- "", "VDD_WLAN_EN", "", "", "WL_IRQ", "GBE_INTN",/* 37-42 */
- "", "", "", "", "", "", "", "", "", "", "", "", /* 43-54 */
- "", "", "", "", "", "", "", "", "", "", "", "", /* 55-66 */
- "", "", "", "", "", "", "", "", "", "", "", "", /* 67-78 */
- "", "", "", "", "", "", /* 79-84 */
- "BITBANG_MDIO_DATA", "BITBANG_MDIO_CLK", /* 85-86 */
- "", "", "", "", ""; /* 87-91 */
-};
-
-&main_gpio1 {
- bootph-all;
- pinctrl-names = "default";
- pinctrl-0 = <&mikrobus_gpio_pins_default>;
- gpio-line-names = "", "", "", "", "", /* 0-4 */
- "SPE_RSTN", "SPE_INTN", "MIKROBUS_GPIO1_7", /* 5-7 */
- "MIKROBUS_GPIO1_8", "MIKROBUS_GPIO1_9", /* 8-9 */
- "MIKROBUS_GPIO1_10", "MIKROBUS_GPIO1_11", /* 10-11 */
- "MIKROBUS_GPIO1_12", "MIKROBUS_W1_GPIO0", /* 12-13 */
- "MIKROBUS_GPIO1_14", /* 14 */
- "", "", "", "", "VDD_3V3_SD", "", "", /* 15-21 */
- "MIKROBUS_GPIO1_22", "MIKROBUS_GPIO1_23", /* 22-23 */
- "MIKROBUS_GPIO1_24", "MIKROBUS_GPIO1_25", /* 24-25 */
- "", "", "", "", "", "", "", "", "", "", "", "", /* 26-37 */
- "", "", "", "", "", "", "", "", "", "", /* 38-47 */
- "SD_CD", "SD_VOLT_SEL", "", ""; /* 48-51 */
-};
-
-&main_i2c0 {
- bootph-all;
- pinctrl-names = "default";
- pinctrl-0 = <&local_i2c_pins_default>;
- clock-frequency = <400000>;
- status = "okay";
-
- eeprom@50 {
- compatible = "atmel,24c32";
- reg = <0x50>;
- };
-
- rtc: rtc@68 {
- compatible = "ti,bq32000";
- reg = <0x68>;
- interrupt-parent = <&main_gpio0>;
- interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
- };
-
- tps65219: pmic@30 {
- bootph-all;
- compatible = "ti,tps65219";
- reg = <0x30>;
- buck1-supply = <&vsys_5v0>;
- buck2-supply = <&vsys_5v0>;
- buck3-supply = <&vsys_5v0>;
- ldo1-supply = <&vdd_3v3>;
- ldo2-supply = <&buck2_reg>;
- ldo3-supply = <&vdd_3v3>;
- ldo4-supply = <&vdd_3v3>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_irq_pins_default>;
- interrupt-parent = <&gic500>;
- interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #interrupt-cells = <1>;
-
- system-power-controller;
- ti,power-button;
-
- regulators {
- buck1_reg: buck1 {
- regulator-name = "VDD_CORE";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck2_reg: buck2 {
- regulator-name = "VDD_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck3_reg: buck3 {
- regulator-name = "VDD_1V2";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo1_reg: ldo1 {
- /*
- * Regulator is left as is unused, vdd_sd
- * is controlled via GPIO with bypass config
- * as per the NVM configuration
- */
- regulator-name = "VDD_SD_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-allow-bypass;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo2_reg: ldo2 {
- regulator-name = "VDDA_0V85";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo3_reg: ldo3 {
- regulator-name = "VDDA_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo4_reg: ldo4 {
- regulator-name = "VDD_2V5";
- regulator-min-microvolt = <2500000>;
- regulator-max-microvolt = <2500000>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
-};
-
-&main_i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&grove_pins_default>;
- clock-frequency = <100000>;
- status = "okay";
-};
-
-&main_i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_1v8_pins_default>;
- clock-frequency = <100000>;
- status = "okay";
-
- it66121: bridge-hdmi@4c {
- compatible = "ite,it66121";
- reg = <0x4c>;
- pinctrl-names = "default";
- pinctrl-0 = <&hdmi_gpio_pins_default>;
- vcn33-supply = <&vdd_3v3>;
- vcn18-supply = <&buck2_reg>;
- vrf12-supply = <&buck3_reg>;
- reset-gpios = <&main_gpio0 21 GPIO_ACTIVE_LOW>;
- interrupt-parent = <&main_gpio0>;
- interrupts = <36 IRQ_TYPE_EDGE_FALLING>;
- #sound-dai-cells = <0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- it66121_in: endpoint {
- bus-width = <24>;
- remote-endpoint = <&dpi1_out>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- it66121_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
- };
- };
- };
-};
-
-&main_i2c3 {
- pinctrl-names = "default";
- pinctrl-0 = <&mikrobus_i2c_pins_default>;
- clock-frequency = <400000>;
- status = "okay";
-};
-
-&main_spi2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mikrobus_spi_pins_default>;
- status = "okay";
-};
-
-&sdhci0 {
- bootph-all;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_pins_default>;
- disable-wp;
- status = "okay";
-};
-
-&sdhci1 {
- /* SD/MMC */
- bootph-all;
- pinctrl-names = "default";
- pinctrl-0 = <&sd_pins_default>;
-
- vmmc-supply = <&vdd_3v3_sd>;
- vqmmc-supply = <&vdd_sd_dv>;
- disable-wp;
- cd-gpios = <&main_gpio1 48 GPIO_ACTIVE_LOW>;
- cd-debounce-delay-ms = <100>;
- ti,fails-without-test-cd;
- status = "okay";
-};
-
-&sdhci2 {
- vmmc-supply = <&wlan_en>;
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_pins_default>, <&wifi_32k_clk>;
- non-removable;
- ti,fails-without-test-cd;
- cap-power-off-card;
- keep-power-in-suspend;
- assigned-clocks = <&k3_clks 157 158>;
- assigned-clock-parents = <&k3_clks 157 160>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- wlcore: wlcore@2 {
- compatible = "ti,wl1807";
- reg = <2>;
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_wlirq_pins_default>;
- interrupt-parent = <&main_gpio0>;
- interrupts = <41 IRQ_TYPE_EDGE_FALLING>;
- };
-};
-
-&main_uart0 {
- bootph-all;
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart0_pins_default>;
- status = "okay";
-};
-
-&main_uart1 {
- /* Main UART1 is used by TIFS firmware */
- status = "reserved";
-};
-
-&main_uart5 {
- pinctrl-names = "default";
- pinctrl-0 = <&mikrobus_uart_pins_default>;
- status = "okay";
-};
-
-&main_uart6 {
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_debug_uart_pins_default>;
- status = "okay";
-
- mcu {
- compatible = "ti,cc1352p7";
- reset-gpios = <&main_gpio0 72 GPIO_ACTIVE_LOW>;
- vdds-supply = <&vdd_3v3>;
- };
-};
-
-&dss {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&dss0_pins_default>;
-};
-
-&dss_ports {
- /* VP2: DPI Output */
- port@1 {
- reg = <1>;
-
- dpi1_out: endpoint {
- remote-endpoint = <&it66121_in>;
- };
- };
-};
-
-&mcasp1 {
- status = "okay";
- #sound-dai-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&mcasp_hdmi_pins_default>;
- auxclk-fs-ratio = <2177>;
- op-mode = <0>; /* MCASP_IIS_MODE */
- tdm-slots = <2>;
- serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
- 1 0 0 0
- 0 0 0 0
- 0 0 0 0
- 0 0 0 0
- >;
- tx-num-evt = <32>;
- rx-num-evt = <32>;
-};
diff --git a/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi b/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi
index 9416228..2bc5acb 100644
--- a/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi
@@ -127,6 +127,32 @@
flash@0 {
bootph-all;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "ospi.tiboot3";
+ reg = <0x00000 0x80000>;
+ };
+ partition@80000 {
+ label = "ospi.tispl";
+ reg = <0x080000 0x200000>;
+ };
+ partition@280000 {
+ label = "ospi.u-boot";
+ reg = <0x280000 0x400000>;
+ };
+ partition@680000 {
+ label = "ospi.env";
+ reg = <0x680000 0x40000>;
+ };
+ partition@6c0000 {
+ label = "ospi.env.backup";
+ reg = <0x6c0000 0x40000>;
+ };
+ };
};
};
@@ -142,6 +168,15 @@
bootph-all;
};
+&usbss0 {
+ bootph-all;
+};
+
+&usb0 {
+ dr_mode = "peripheral";
+ bootph-all;
+};
+
&vcc_3v3_mmc {
bootph-all;
};
diff --git a/arch/arm/dts/k3-am625-r5-beagleplay.dts b/arch/arm/dts/k3-am625-r5-beagleplay.dts
index 9db58f0..f0b66f0 100644
--- a/arch/arm/dts/k3-am625-r5-beagleplay.dts
+++ b/arch/arm/dts/k3-am625-r5-beagleplay.dts
@@ -79,6 +79,7 @@
&binman {
tiboot3-am62x-gp-evm.bin {
filename = "tiboot3-am62x-gp-evm.bin";
+ symlink = "tiboot3.bin";
ti-secure-rom {
content = <&u_boot_spl_unsigned>, <&ti_fs_gp>,
<&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>;
@@ -114,3 +115,18 @@
};
};
+
+#include "k3-binman-capsule-r5.dtsi"
+
+// Capsule update GUIDs in string form. See beagleplay.h
+#define BEAGLEPLAY_TIBOOT3_IMAGE_GUID_STR "0e225a09-f720-4d57-9120-e28f737f5a5e"
+
+&capsule_tiboot3 {
+ efi-capsule {
+ image-guid = BEAGLEPLAY_TIBOOT3_IMAGE_GUID_STR;
+
+ blob {
+ filename = "tiboot3-am62x-gp-evm.bin";
+ };
+ };
+};
diff --git a/arch/arm/dts/k3-am625-sk-binman.dtsi b/arch/arm/dts/k3-am625-sk-binman.dtsi
index dfd38d6..534eb14 100644
--- a/arch/arm/dts/k3-am625-sk-binman.dtsi
+++ b/arch/arm/dts/k3-am625-sk-binman.dtsi
@@ -137,11 +137,22 @@
};
};
+#include "k3-binman-capsule-r5.dtsi"
+
+// Capsule update GUIDs in string form. See am62x_evm.h
+#define AM62X_SK_TIBOOT3_IMAGE_GUID_STR "abcb83d2-9cb6-4351-b8f1-6494bbe3700a"
+
+&capsule_tiboot3 {
+ efi-capsule {
+ image-guid = AM62X_SK_TIBOOT3_IMAGE_GUID_STR;
+ };
+};
+
#endif
#ifdef CONFIG_TARGET_AM625_A53_EVM
-#define SPL_AM625_SK_DTB "spl/dts/k3-am625-sk.dtb"
+#define SPL_AM625_SK_DTB "spl/dts/ti/k3-am625-sk.dtb"
#define AM625_SK_DTB "u-boot.dtb"
&binman {
@@ -149,6 +160,7 @@
filename = "ti-dm.bin";
blob-ext {
filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+ optional;
};
};
@@ -452,4 +464,23 @@
};
};
};
+
+#include "k3-binman-capsule.dtsi"
+
+// Capsule update GUIDs in string form. See am62x_evm.h
+#define AM62X_SK_SPL_IMAGE_GUID_STR "aee355fc-bf97-4264-8c82-437255efdc1d"
+#define AM62X_SK_UBOOT_IMAGE_GUID_STR "28ab8c6c-fca8-41d3-8ea1-5f171b7d2929"
+
+&capsule_tispl {
+ efi-capsule {
+ image-guid = AM62X_SK_SPL_IMAGE_GUID_STR;
+ };
+};
+
+&capsule_uboot {
+ efi-capsule {
+ image-guid = AM62X_SK_UBOOT_IMAGE_GUID_STR;
+ };
+};
+
#endif
diff --git a/arch/arm/dts/k3-am625-sk.dts b/arch/arm/dts/k3-am625-sk.dts
deleted file mode 100644
index ae81ebb..0000000
--- a/arch/arm/dts/k3-am625-sk.dts
+++ /dev/null
@@ -1,299 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-/*
- * AM625 SK: https://www.ti.com/lit/zip/sprr448
- *
- * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-/dts-v1/;
-
-#include "k3-am62x-sk-common.dtsi"
-
-/ {
- compatible = "ti,am625-sk", "ti,am625";
- model = "Texas Instruments AM625 SK";
-
- opp-table {
- /* Add 1.4GHz OPP for am625-sk board. Requires VDD_CORE to be at 0.85V */
- opp-1400000000 {
- opp-hz = /bits/ 64 <1400000000>;
- opp-supported-hw = <0x01 0x0004>;
- clock-latency-ns = <6000000>;
- };
- };
-
- memory@80000000 {
- device_type = "memory";
- /* 2G RAM */
- reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
-
- };
-
- vmain_pd: regulator-0 {
- /* TPS65988 PD CONTROLLER OUTPUT */
- bootph-all;
- compatible = "regulator-fixed";
- regulator-name = "vmain_pd";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vcc_5v0: regulator-1 {
- /* Output of LM34936 */
- bootph-all;
- compatible = "regulator-fixed";
- regulator-name = "vcc_5v0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vmain_pd>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vcc_3v3_sys: regulator-2 {
- /* output of LM61460-Q1 */
- bootph-all;
- compatible = "regulator-fixed";
- regulator-name = "vcc_3v3_sys";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vmain_pd>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vdd_mmc1: regulator-3 {
- /* TPS22918DBVR */
- bootph-all;
- compatible = "regulator-fixed";
- regulator-name = "vdd_mmc1";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- enable-active-high;
- vin-supply = <&vcc_3v3_sys>;
- gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
- };
-
- vdd_sd_dv: regulator-4 {
- /* Output of TLV71033 */
- bootph-all;
- compatible = "regulator-gpio";
- regulator-name = "tlv71033";
- pinctrl-names = "default";
- pinctrl-0 = <&vdd_sd_dv_pins_default>;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- vin-supply = <&vcc_5v0>;
- gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>;
- states = <1800000 0x0>,
- <3300000 0x1>;
- };
-
- vcc_1v8: regulator-5 {
- /* output of TPS6282518DMQ */
- compatible = "regulator-fixed";
- regulator-name = "vcc_1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_3v3_sys>;
- regulator-always-on;
- regulator-boot-on;
- };
-};
-
-&main_pmx0 {
- main_rgmii2_pins_default: main-rgmii2-default-pins {
- bootph-all;
- pinctrl-single,pins = <
- AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */
- AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */
- AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */
- AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */
- AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */
- AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */
- AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */
- AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */
- AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */
- AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */
- AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */
- AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */
- >;
- };
-
- ospi0_pins_default: ospi0-default-pins {
- bootph-all;
- pinctrl-single,pins = <
- AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */
- AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */
- AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */
- AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */
- AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */
- AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */
- AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */
- AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */
- AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */
- AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */
- AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */
- >;
- };
-
- vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
- bootph-all;
- pinctrl-single,pins = <
- AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */
- >;
- };
-
- main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins {
- bootph-all;
- pinctrl-single,pins = <
- AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */
- >;
- };
-};
-
-&main_gpio0 {
- bootph-all;
-};
-
-&main_gpio1 {
- bootph-all;
-};
-
-&main_i2c1 {
- bootph-all;
- exp1: gpio@22 {
- bootph-all;
- compatible = "ti,tca6424";
- reg = <0x22>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
- "PRU_DETECT", "MMC1_SD_EN",
- "VPP_LDO_EN", "EXP_PS_3V3_En",
- "EXP_PS_5V0_En", "EXP_HAT_DETECT",
- "GPIO_AUD_RSTn", "GPIO_eMMC_RSTn",
- "UART1_FET_BUF_EN", "WL_LT_EN",
- "GPIO_HDMI_RSTn", "CSI_GPIO1",
- "CSI_GPIO2", "PRU_3V3_EN",
- "HDMI_INTn", "PD_I2C_IRQ",
- "MCASP1_FET_EN", "MCASP1_BUF_BT_EN",
- "MCASP1_FET_SEL", "UART1_FET_SEL",
- "TSINT#", "IO_EXP_TEST_LED";
-
- interrupt-parent = <&main_gpio1>;
- interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
- interrupt-controller;
- #interrupt-cells = <2>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>;
- };
-};
-
-&sdhci1 {
- vmmc-supply = <&vdd_mmc1>;
- vqmmc-supply = <&vdd_sd_dv>;
-};
-
-&cpsw3g {
- pinctrl-names = "default";
- pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>;
-};
-
-&cpsw_port2 {
- phy-mode = "rgmii-rxid";
- phy-handle = <&cpsw3g_phy1>;
-};
-
-&cpsw3g_mdio {
- cpsw3g_phy1: ethernet-phy@1 {
- reg = <1>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- ti,min-output-impedance;
- };
-};
-
-&mailbox0_cluster0 {
- mbox_m4_0: mbox-m4-0 {
- ti,mbox-rx = <0 0 0>;
- ti,mbox-tx = <1 0 0>;
- };
-};
-
-&fss {
- bootph-all;
-};
-
-&ospi0 {
- bootph-all;
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&ospi0_pins_default>;
-
- flash@0 {
- bootph-all;
- compatible = "jedec,spi-nor";
- reg = <0x0>;
- spi-tx-bus-width = <8>;
- spi-rx-bus-width = <8>;
- spi-max-frequency = <25000000>;
- cdns,tshsl-ns = <60>;
- cdns,tsd2d-ns = <60>;
- cdns,tchsh-ns = <60>;
- cdns,tslch-ns = <60>;
- cdns,read-delay = <4>;
-
- partitions {
- bootph-all;
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "ospi.tiboot3";
- reg = <0x0 0x80000>;
- };
-
- partition@80000 {
- label = "ospi.tispl";
- reg = <0x80000 0x200000>;
- };
-
- partition@280000 {
- label = "ospi.u-boot";
- reg = <0x280000 0x400000>;
- };
-
- partition@680000 {
- label = "ospi.env";
- reg = <0x680000 0x40000>;
- };
-
- partition@6c0000 {
- label = "ospi.env.backup";
- reg = <0x6c0000 0x40000>;
- };
-
- partition@800000 {
- label = "ospi.rootfs";
- reg = <0x800000 0x37c0000>;
- };
-
- partition@3fc0000 {
- bootph-pre-ram;
- label = "ospi.phypattern";
- reg = <0x3fc0000 0x40000>;
- };
- };
- };
-};
-
-&tlv320aic3106 {
- DVDD-supply = <&vcc_1v8>;
-};
diff --git a/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi b/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi
index 841541b..5062447 100644
--- a/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi
+++ b/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi
@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* This file was generated with the
- * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.10
- * Mon Dec 11 2023 17:07:35 GMT+0100 (Central European Standard Time)
+ * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.10.01
+ * Tue May 14 2024 12:55:28 GMT+0200 (Central European Summer Time)
* DDR Type: LPDDR4
* F0 = 50MHz F1 = NA F2 = 800MHz
* Density (per channel): 16Gb
@@ -10,9 +10,11 @@
* Number of Ranks: 1
*/
+
#define DDRSS_PLL_FHS_CNT 3
#define DDRSS_PLL_FREQUENCY_1 400000000
#define DDRSS_PLL_FREQUENCY_2 400000000
+#define DDRSS_SDRAM_IDX 15
#define DDRSS_CTL_0_DATA 0x00000B00
@@ -848,7 +850,7 @@
#define DDRSS_PHY_62_DATA 0x00000000
#define DDRSS_PHY_63_DATA 0x00000000
#define DDRSS_PHY_64_DATA 0x00000000
-#define DDRSS_PHY_65_DATA 0x00000004
+#define DDRSS_PHY_65_DATA 0x00000104
#define DDRSS_PHY_66_DATA 0x00000000
#define DDRSS_PHY_67_DATA 0x00000000
#define DDRSS_PHY_68_DATA 0x00000000
@@ -1104,7 +1106,7 @@
#define DDRSS_PHY_318_DATA 0x00000000
#define DDRSS_PHY_319_DATA 0x00000000
#define DDRSS_PHY_320_DATA 0x00000000
-#define DDRSS_PHY_321_DATA 0x00000004
+#define DDRSS_PHY_321_DATA 0x00000104
#define DDRSS_PHY_322_DATA 0x00000000
#define DDRSS_PHY_323_DATA 0x00000000
#define DDRSS_PHY_324_DATA 0x00000000
diff --git a/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi b/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi
index a9b86b6..0e61889 100644
--- a/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi
+++ b/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi
@@ -448,4 +448,72 @@
};
};
+&binman {
+ firmware-verdin-am62-gp.bin {
+ filename = "firmware-verdin-am62-gp.bin";
+
+ blob-ext@1 {
+ filename = "tiboot3-am62x-gp-verdin.bin";
+ };
+
+ blob-ext@2 {
+ filename = "tispl.bin_unsigned";
+ /*
+ * This value matches CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
+ * from R5 SPL config.
+ */
+ offset = <0x80000>;
+ };
+
+ blob-ext@3 {
+ filename = "u-boot.img_unsigned";
+ offset = <(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)>;
+ };
+ };
+
+ firmware-verdin-am62-hs.bin {
+ filename = "firmware-verdin-am62-hs.bin";
+
+ blob-ext@1 {
+ filename = "tiboot3-am62x-hs-verdin.bin";
+ };
+
+ blob-ext@2 {
+ filename = "tispl.bin";
+ /*
+ * This value matches CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
+ * from R5 SPL config.
+ */
+ offset = <0x80000>;
+ };
+
+ blob-ext@3 {
+ filename = "u-boot.img";
+ offset = <(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)>;
+ };
+ };
+
+ firmware-verdin-am62-hs-fs.bin {
+ filename = "firmware-verdin-am62-hs-fs.bin";
+
+ blob-ext@1 {
+ filename = "tiboot3-am62x-hs-fs-verdin.bin";
+ };
+
+ blob-ext@2 {
+ filename = "tispl.bin";
+ /*
+ * This value matches CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
+ * from R5 SPL config.
+ */
+ offset = <0x80000>;
+ };
+
+ blob-ext@3 {
+ filename = "u-boot.img";
+ offset = <(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)>;
+ };
+ };
+};
+
#endif /* CONFIG_TARGET_VERDIN_AM62_A53 */
diff --git a/arch/arm/dts/k3-am625.dtsi b/arch/arm/dts/k3-am625.dtsi
deleted file mode 100644
index 4014add..0000000
--- a/arch/arm/dts/k3-am625.dtsi
+++ /dev/null
@@ -1,155 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-/*
- * Device Tree Source for AM625 SoC family in Quad core configuration
- *
- * TRM: https://www.ti.com/lit/pdf/spruiv7
- *
- * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-/dts-v1/;
-
-#include "k3-am62.dtsi"
-
-/ {
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu-map {
- cluster0: cluster0 {
- core0 {
- cpu = <&cpu0>;
- };
-
- core1 {
- cpu = <&cpu1>;
- };
-
- core2 {
- cpu = <&cpu2>;
- };
-
- core3 {
- cpu = <&cpu3>;
- };
- };
- };
-
- cpu0: cpu@0 {
- compatible = "arm,cortex-a53";
- reg = <0x000>;
- device_type = "cpu";
- enable-method = "psci";
- i-cache-size = <0x8000>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <64>;
- d-cache-sets = <128>;
- next-level-cache = <&L2_0>;
- operating-points-v2 = <&a53_opp_table>;
- clocks = <&k3_clks 135 0>;
- };
-
- cpu1: cpu@1 {
- compatible = "arm,cortex-a53";
- reg = <0x001>;
- device_type = "cpu";
- enable-method = "psci";
- i-cache-size = <0x8000>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <64>;
- d-cache-sets = <128>;
- next-level-cache = <&L2_0>;
- operating-points-v2 = <&a53_opp_table>;
- clocks = <&k3_clks 136 0>;
- };
-
- cpu2: cpu@2 {
- compatible = "arm,cortex-a53";
- reg = <0x002>;
- device_type = "cpu";
- enable-method = "psci";
- i-cache-size = <0x8000>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <64>;
- d-cache-sets = <128>;
- next-level-cache = <&L2_0>;
- operating-points-v2 = <&a53_opp_table>;
- clocks = <&k3_clks 137 0>;
- };
-
- cpu3: cpu@3 {
- compatible = "arm,cortex-a53";
- reg = <0x003>;
- device_type = "cpu";
- enable-method = "psci";
- i-cache-size = <0x8000>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <64>;
- d-cache-sets = <128>;
- next-level-cache = <&L2_0>;
- operating-points-v2 = <&a53_opp_table>;
- clocks = <&k3_clks 138 0>;
- };
- };
-
- a53_opp_table: opp-table {
- compatible = "operating-points-v2-ti-cpu";
- opp-shared;
- syscon = <&wkup_conf>;
-
- opp-200000000 {
- opp-hz = /bits/ 64 <200000000>;
- opp-supported-hw = <0x01 0x0007>;
- clock-latency-ns = <6000000>;
- };
-
- opp-400000000 {
- opp-hz = /bits/ 64 <400000000>;
- opp-supported-hw = <0x01 0x0007>;
- clock-latency-ns = <6000000>;
- };
-
- opp-600000000 {
- opp-hz = /bits/ 64 <600000000>;
- opp-supported-hw = <0x01 0x0007>;
- clock-latency-ns = <6000000>;
- };
-
- opp-800000000 {
- opp-hz = /bits/ 64 <800000000>;
- opp-supported-hw = <0x01 0x0007>;
- clock-latency-ns = <6000000>;
- };
-
- opp-1000000000 {
- opp-hz = /bits/ 64 <1000000000>;
- opp-supported-hw = <0x01 0x0006>;
- clock-latency-ns = <6000000>;
- };
-
- opp-1250000000 {
- opp-hz = /bits/ 64 <1250000000>;
- opp-supported-hw = <0x01 0x0004>;
- clock-latency-ns = <6000000>;
- opp-suspend;
- };
- };
-
- L2_0: l2-cache0 {
- compatible = "cache";
- cache-unified;
- cache-level = <2>;
- cache-size = <0x80000>;
- cache-line-size = <64>;
- cache-sets = <512>;
- };
-};
diff --git a/arch/arm/dts/k3-am62a-main.dtsi b/arch/arm/dts/k3-am62a-main.dtsi
deleted file mode 100644
index aa1e057..0000000
--- a/arch/arm/dts/k3-am62a-main.dtsi
+++ /dev/null
@@ -1,1054 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-/*
- * Device Tree Source for AM62A SoC Family Main Domain peripherals
- *
- * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-&cbass_main {
- oc_sram: sram@70000000 {
- compatible = "mmio-sram";
- reg = <0x00 0x70000000 0x00 0x10000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x00 0x70000000 0x10000>;
- };
-
- gic500: interrupt-controller@1800000 {
- compatible = "arm,gic-v3";
- reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
- <0x00 0x01880000 0x00 0xc0000>, /* GICR */
- <0x00 0x01880000 0x00 0xc0000>, /* GICR */
- <0x01 0x00000000 0x00 0x2000>, /* GICC */
- <0x01 0x00010000 0x00 0x1000>, /* GICH */
- <0x01 0x00020000 0x00 0x2000>; /* GICV */
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- #interrupt-cells = <3>;
- interrupt-controller;
- /*
- * vcpumntirq:
- * virtual CPU interface maintenance interrupt
- */
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
-
- gic_its: msi-controller@1820000 {
- compatible = "arm,gic-v3-its";
- reg = <0x00 0x01820000 0x00 0x10000>;
- socionext,synquacer-pre-its = <0x1000000 0x400000>;
- msi-controller;
- #msi-cells = <1>;
- };
- };
-
- main_conf: bus@100000 {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00 0x00 0x00100000 0x20000>;
-
- phy_gmii_sel: phy@4044 {
- compatible = "ti,am654-phy-gmii-sel";
- reg = <0x4044 0x8>;
- #phy-cells = <1>;
- };
-
- epwm_tbclk: clock-controller@4130 {
- compatible = "ti,am62-epwm-tbclk";
- reg = <0x4130 0x4>;
- #clock-cells = <1>;
- };
- };
-
- dmss: bus@48000000 {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- dma-ranges;
- ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06000000>;
-
- ti,sci-dev-id = <25>;
-
- secure_proxy_main: mailbox@4d000000 {
- compatible = "ti,am654-secure-proxy";
- reg = <0x00 0x4d000000 0x00 0x80000>,
- <0x00 0x4a600000 0x00 0x80000>,
- <0x00 0x4a400000 0x00 0x80000>;
- reg-names = "target_data", "rt", "scfg";
- #mbox-cells = <1>;
- interrupt-names = "rx_012";
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- inta_main_dmss: interrupt-controller@48000000 {
- compatible = "ti,sci-inta";
- reg = <0x00 0x48000000 0x00 0x100000>;
- #interrupt-cells = <0>;
- interrupt-controller;
- interrupt-parent = <&gic500>;
- msi-controller;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <28>;
- ti,interrupt-ranges = <6 70 34>;
- ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
- };
-
- main_bcdma: dma-controller@485c0100 {
- compatible = "ti,am64-dmss-bcdma";
- reg = <0x00 0x485c0100 0x00 0x100>,
- <0x00 0x4c000000 0x00 0x20000>,
- <0x00 0x4a820000 0x00 0x20000>,
- <0x00 0x4aa40000 0x00 0x20000>,
- <0x00 0x4bc00000 0x00 0x100000>,
- <0x00 0x48600000 0x00 0x8000>,
- <0x00 0x484a4000 0x00 0x2000>,
- <0x00 0x484c2000 0x00 0x2000>,
- <0x00 0x48420000 0x00 0x2000>;
- reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
- "ring", "tchan", "rchan", "bchan";
- msi-parent = <&inta_main_dmss>;
- #dma-cells = <3>;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <26>;
- ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
- ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
- ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
- };
-
- main_pktdma: dma-controller@485c0000 {
- compatible = "ti,am64-dmss-pktdma";
- reg = <0x00 0x485c0000 0x00 0x100>,
- <0x00 0x4a800000 0x00 0x20000>,
- <0x00 0x4aa00000 0x00 0x40000>,
- <0x00 0x4b800000 0x00 0x400000>,
- <0x00 0x485e0000 0x00 0x10000>,
- <0x00 0x484a0000 0x00 0x2000>,
- <0x00 0x484c0000 0x00 0x2000>,
- <0x00 0x48430000 0x00 0x1000>;
- reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
- "ring", "tchan", "rchan", "rflow";
- msi-parent = <&inta_main_dmss>;
- #dma-cells = <2>;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <30>;
- ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
- <0x24>, /* CPSW_TX_CHAN */
- <0x25>, /* SAUL_TX_0_CHAN */
- <0x26>; /* SAUL_TX_1_CHAN */
- ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
- <0x11>, /* RING_CPSW_TX_CHAN */
- <0x12>, /* RING_SAUL_TX_0_CHAN */
- <0x13>; /* RING_SAUL_TX_1_CHAN */
- ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
- <0x2b>, /* CPSW_RX_CHAN */
- <0x2d>, /* SAUL_RX_0_CHAN */
- <0x2f>, /* SAUL_RX_1_CHAN */
- <0x31>, /* SAUL_RX_2_CHAN */
- <0x33>; /* SAUL_RX_3_CHAN */
- ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
- <0x2c>, /* FLOW_CPSW_RX_CHAN */
- <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
- <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
- };
- };
-
- dmss_csi: bus@4e000000 {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- dma-ranges;
- ranges = <0x00 0x4e000000 0x00 0x4e000000 0x00 0x300000>;
-
- ti,sci-dev-id = <198>;
-
- inta_main_dmss_csi: interrupt-controller@4e0a0000 {
- compatible = "ti,sci-inta";
- reg = <0x00 0x4e0a0000 0x00 0x8000>;
- #interrupt-cells = <0>;
- interrupt-controller;
- interrupt-parent = <&gic500>;
- msi-controller;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <200>;
- ti,interrupt-ranges = <0 237 8>;
- ti,unmapped-event-sources = <&main_bcdma_csi>;
- power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
- };
-
- main_bcdma_csi: dma-controller@4e230000 {
- compatible = "ti,am62a-dmss-bcdma-csirx";
- reg = <0x00 0x4e230000 0x00 0x100>,
- <0x00 0x4e180000 0x00 0x8000>,
- <0x00 0x4e100000 0x00 0x10000>;
- reg-names = "gcfg", "rchanrt", "ringrt";
- msi-parent = <&inta_main_dmss_csi>;
- #dma-cells = <3>;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <199>;
- ti,sci-rm-range-rchan = <0x21>;
- power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
- };
- };
-
- dmsc: system-controller@44043000 {
- compatible = "ti,k2g-sci";
- reg = <0x00 0x44043000 0x00 0xfe0>;
- reg-names = "debug_messages";
- ti,host-id = <12>;
- mbox-names = "rx", "tx";
- mboxes = <&secure_proxy_main 12>,
- <&secure_proxy_main 13>;
-
- k3_pds: power-controller {
- compatible = "ti,sci-pm-domain";
- #power-domain-cells = <2>;
- };
-
- k3_clks: clock-controller {
- compatible = "ti,k2g-sci-clk";
- #clock-cells = <2>;
- };
-
- k3_reset: reset-controller {
- compatible = "ti,sci-reset";
- #reset-cells = <2>;
- };
- };
-
- secure_proxy_sa3: mailbox@43600000 {
- compatible = "ti,am654-secure-proxy";
- #mbox-cells = <1>;
- reg-names = "target_data", "rt", "scfg";
- reg = <0x00 0x43600000 0x00 0x10000>,
- <0x00 0x44880000 0x00 0x20000>,
- <0x00 0x44860000 0x00 0x20000>;
- /*
- * Marked Disabled:
- * Node is incomplete as it is meant for bootloaders and
- * firmware on non-MPU processors
- */
- status = "disabled";
- };
-
- main_pmx0: pinctrl@f4000 {
- compatible = "pinctrl-single";
- reg = <0x00 0xf4000 0x00 0x2ac>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0xffffffff>;
- };
-
- main_timer0: timer@2400000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2400000 0x00 0x400>;
- interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 36 2>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 36 2>;
- assigned-clock-parents = <&k3_clks 36 3>;
- power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer1: timer@2410000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2410000 0x00 0x400>;
- interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 37 2>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 37 2>;
- assigned-clock-parents = <&k3_clks 37 3>;
- power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer2: timer@2420000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2420000 0x00 0x400>;
- interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 38 2>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 38 2>;
- assigned-clock-parents = <&k3_clks 38 3>;
- power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer3: timer@2430000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2430000 0x00 0x400>;
- interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 39 2>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 39 2>;
- assigned-clock-parents = <&k3_clks 39 3>;
- power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer4: timer@2440000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2440000 0x00 0x400>;
- interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 40 2>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 40 2>;
- assigned-clock-parents = <&k3_clks 40 3>;
- power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer5: timer@2450000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2450000 0x00 0x400>;
- interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 41 2>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 41 2>;
- assigned-clock-parents = <&k3_clks 41 3>;
- power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer6: timer@2460000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2460000 0x00 0x400>;
- interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 42 2>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 42 2>;
- assigned-clock-parents = <&k3_clks 42 3>;
- power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer7: timer@2470000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2470000 0x00 0x400>;
- interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 43 2>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 43 2>;
- assigned-clock-parents = <&k3_clks 43 3>;
- power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_uart0: serial@2800000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02800000 0x00 0x100>;
- interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 146 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart1: serial@2810000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02810000 0x00 0x100>;
- interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 152 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart2: serial@2820000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02820000 0x00 0x100>;
- interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 153 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart3: serial@2830000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02830000 0x00 0x100>;
- interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 154 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart4: serial@2840000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02840000 0x00 0x100>;
- interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 155 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart5: serial@2850000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02850000 0x00 0x100>;
- interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 156 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart6: serial@2860000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02860000 0x00 0x100>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 158 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_i2c0: i2c@20000000 {
- compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x20000000 0x00 0x100>;
- interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 102 2>;
- clock-names = "fck";
- status = "disabled";
- };
-
- main_i2c1: i2c@20010000 {
- compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x20010000 0x00 0x100>;
- interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 103 2>;
- clock-names = "fck";
- status = "disabled";
- };
-
- main_i2c2: i2c@20020000 {
- compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x20020000 0x00 0x100>;
- interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 104 2>;
- clock-names = "fck";
- status = "disabled";
- };
-
- main_i2c3: i2c@20030000 {
- compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x20030000 0x00 0x100>;
- interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 105 2>;
- clock-names = "fck";
- status = "disabled";
- };
-
- main_spi0: spi@20100000 {
- compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
- reg = <0x00 0x20100000 0x00 0x400>;
- interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 141 0>;
- status = "disabled";
- };
-
- main_spi1: spi@20110000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x20110000 0x00 0x400>;
- interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 142 0>;
- status = "disabled";
- };
-
- main_spi2: spi@20120000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x20120000 0x00 0x400>;
- interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 143 0>;
- status = "disabled";
- };
-
- main_gpio_intr: interrupt-controller@a00000 {
- compatible = "ti,sci-intr";
- reg = <0x00 0x00a00000 0x00 0x800>;
- ti,intr-trigger-type = <1>;
- interrupt-controller;
- interrupt-parent = <&gic500>;
- #interrupt-cells = <1>;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <3>;
- ti,interrupt-ranges = <0 32 16>;
- status = "disabled";
- };
-
- main_gpio0: gpio@600000 {
- compatible = "ti,am64-gpio", "ti,keystone-gpio";
- reg = <0x00 0x00600000 0x0 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&main_gpio_intr>;
- interrupts = <190>, <191>, <192>,
- <193>, <194>, <195>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <92>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 77 0>;
- clock-names = "gpio";
- status = "disabled";
- };
-
- main_gpio1: gpio@601000 {
- compatible = "ti,am64-gpio", "ti,keystone-gpio";
- reg = <0x00 0x00601000 0x0 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&main_gpio_intr>;
- interrupts = <180>, <181>, <182>,
- <183>, <184>, <185>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <52>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 78 0>;
- clock-names = "gpio";
- status = "disabled";
- };
-
- sdhci0: mmc@fa10000 {
- compatible = "ti,am62-sdhci";
- reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
- interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 57 5>, <&k3_clks 57 6>;
- clock-names = "clk_ahb", "clk_xin";
- assigned-clocks = <&k3_clks 57 6>;
- assigned-clock-parents = <&k3_clks 57 8>;
- bus-width = <8>;
- mmc-hs200-1_8v;
- ti,clkbuf-sel = <0x7>;
- ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-mmc-hs = <0x0>;
- ti,otap-del-sel-hs200 = <0x6>;
- status = "disabled";
- };
-
- sdhci1: mmc@fa00000 {
- compatible = "ti,am62-sdhci";
- reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
- interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 58 5>, <&k3_clks 58 6>;
- clock-names = "clk_ahb", "clk_xin";
- bus-width = <4>;
- ti,clkbuf-sel = <0x7>;
- ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-sd-hs = <0x0>;
- ti,otap-del-sel-sdr12 = <0xf>;
- ti,otap-del-sel-sdr25 = <0xf>;
- ti,otap-del-sel-sdr50 = <0xc>;
- ti,otap-del-sel-sdr104 = <0x6>;
- ti,otap-del-sel-ddr50 = <0x9>;
- ti,itap-del-sel-legacy = <0x0>;
- ti,itap-del-sel-sd-hs = <0x0>;
- ti,itap-del-sel-sdr12 = <0x0>;
- ti,itap-del-sel-sdr25 = <0x0>;
- no-1-8-v;
- status = "disabled";
- };
-
- sdhci2: mmc@fa20000 {
- compatible = "ti,am62-sdhci";
- reg = <0x00 0xfa20000 0x00 0x260>, <0x00 0xfa28000 0x00 0x134>;
- interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 184 5>, <&k3_clks 184 6>;
- clock-names = "clk_ahb", "clk_xin";
- bus-width = <4>;
- ti,clkbuf-sel = <0x7>;
- ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-sd-hs = <0x0>;
- ti,otap-del-sel-sdr12 = <0xf>;
- ti,otap-del-sel-sdr25 = <0xf>;
- ti,otap-del-sel-sdr50 = <0xc>;
- ti,otap-del-sel-sdr104 = <0x6>;
- ti,otap-del-sel-ddr50 = <0x9>;
- ti,itap-del-sel-legacy = <0x0>;
- ti,itap-del-sel-sd-hs = <0x0>;
- ti,itap-del-sel-sdr12 = <0x0>;
- ti,itap-del-sel-sdr25 = <0x0>;
- no-1-8-v;
- status = "disabled";
- };
-
- usbss0: dwc3-usb@f900000 {
- compatible = "ti,am62-usb";
- reg = <0x00 0x0f900000 0x00 0x800>;
- clocks = <&k3_clks 161 3>;
- clock-names = "ref";
- ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>;
- #address-cells = <2>;
- #size-cells = <2>;
- power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
- ranges;
- status = "disabled";
-
- usb0: usb@31000000 {
- compatible = "snps,dwc3";
- reg = <0x00 0x31000000 0x00 0x50000>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
- <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
- interrupt-names = "host", "peripheral";
- maximum-speed = "high-speed";
- dr_mode = "otg";
- };
- };
-
- usbss1: dwc3-usb@f910000 {
- compatible = "ti,am62-usb";
- reg = <0x00 0x0f910000 0x00 0x800>;
- clocks = <&k3_clks 162 3>;
- clock-names = "ref";
- ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>;
- #address-cells = <2>;
- #size-cells = <2>;
- power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
- ranges;
- status = "disabled";
-
- usb1: usb@31100000 {
- compatible = "snps,dwc3";
- reg = <0x00 0x31100000 0x00 0x50000>;
- interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
- <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
- interrupt-names = "host", "peripheral";
- maximum-speed = "high-speed";
- dr_mode = "otg";
- };
- };
-
- fss: bus@fc00000 {
- compatible = "simple-bus";
- reg = <0x00 0x0fc00000 0x00 0x70000>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- status = "disabled";
-
- ospi0: spi@fc40000 {
- compatible = "ti,am654-ospi", "cdns,qspi-nor";
- reg = <0x00 0x0fc40000 0x00 0x100>,
- <0x05 0x00000000 0x01 0x00000000>;
- interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
- cdns,fifo-depth = <256>;
- cdns,fifo-width = <4>;
- cdns,trigger-address = <0x0>;
- clocks = <&k3_clks 75 7>;
- assigned-clocks = <&k3_clks 75 7>;
- assigned-clock-parents = <&k3_clks 75 8>;
- assigned-clock-rates = <166666666>;
- power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-
- cpsw3g: ethernet@8000000 {
- compatible = "ti,am642-cpsw-nuss";
- #address-cells = <2>;
- #size-cells = <2>;
- reg = <0x0 0x8000000 0x0 0x200000>;
- reg-names = "cpsw_nuss";
- ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
- clocks = <&k3_clks 13 0>;
- assigned-clocks = <&k3_clks 13 3>;
- assigned-clock-parents = <&k3_clks 13 11>;
- clock-names = "fck";
- power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
-
- dmas = <&main_pktdma 0xc600 15>,
- <&main_pktdma 0xc601 15>,
- <&main_pktdma 0xc602 15>,
- <&main_pktdma 0xc603 15>,
- <&main_pktdma 0xc604 15>,
- <&main_pktdma 0xc605 15>,
- <&main_pktdma 0xc606 15>,
- <&main_pktdma 0xc607 15>,
- <&main_pktdma 0x4600 15>;
- dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
- "tx7", "rx";
-
- ethernet-ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpsw_port1: port@1 {
- reg = <1>;
- ti,mac-only;
- label = "port1";
- phys = <&phy_gmii_sel 1>;
- mac-address = [00 00 00 00 00 00];
- ti,syscon-efuse = <&wkup_conf 0x200>;
- };
-
- cpsw_port2: port@2 {
- reg = <2>;
- ti,mac-only;
- label = "port2";
- phys = <&phy_gmii_sel 2>;
- mac-address = [00 00 00 00 00 00];
- };
- };
-
- cpsw3g_mdio: mdio@f00 {
- compatible = "ti,cpsw-mdio","ti,davinci_mdio";
- reg = <0x0 0xf00 0x0 0x100>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&k3_clks 13 0>;
- clock-names = "fck";
- bus_freq = <1000000>;
- };
-
- cpts@3d000 {
- compatible = "ti,j721e-cpts";
- reg = <0x0 0x3d000 0x0 0x400>;
- clocks = <&k3_clks 13 3>;
- clock-names = "cpts";
- interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cpts";
- ti,cpts-ext-ts-inputs = <4>;
- ti,cpts-periodic-outputs = <2>;
- };
- };
-
- hwspinlock: spinlock@2a000000 {
- compatible = "ti,am64-hwspinlock";
- reg = <0x00 0x2a000000 0x00 0x1000>;
- #hwlock-cells = <1>;
- };
-
- mailbox0_cluster0: mailbox@29000000 {
- compatible = "ti,am64-mailbox";
- reg = <0x00 0x29000000 0x00 0x200>;
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- };
-
- mailbox0_cluster1: mailbox@29010000 {
- compatible = "ti,am64-mailbox";
- reg = <0x00 0x29010000 0x00 0x200>;
- interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- };
-
- mailbox0_cluster2: mailbox@29020000 {
- compatible = "ti,am64-mailbox";
- reg = <0x00 0x29020000 0x00 0x200>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- };
-
- mailbox0_cluster3: mailbox@29030000 {
- compatible = "ti,am64-mailbox";
- reg = <0x00 0x29030000 0x00 0x200>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- };
-
- main_mcan0: can@20701000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x20701000 0x00 0x200>,
- <0x00 0x20708000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 98 6>, <&k3_clks 98 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- main_rti0: watchdog@e000000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x0e000000 0x00 0x100>;
- clocks = <&k3_clks 125 0>;
- power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 125 0>;
- assigned-clock-parents = <&k3_clks 125 2>;
- };
-
- main_rti1: watchdog@e010000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x0e010000 0x00 0x100>;
- clocks = <&k3_clks 126 0>;
- power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 126 0>;
- assigned-clock-parents = <&k3_clks 126 2>;
- };
-
- main_rti2: watchdog@e020000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x0e020000 0x00 0x100>;
- clocks = <&k3_clks 127 0>;
- power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 127 0>;
- assigned-clock-parents = <&k3_clks 127 2>;
- };
-
- main_rti3: watchdog@e030000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x0e030000 0x00 0x100>;
- clocks = <&k3_clks 128 0>;
- power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 128 0>;
- assigned-clock-parents = <&k3_clks 128 2>;
- };
-
- main_rti4: watchdog@e040000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x0e040000 0x00 0x100>;
- clocks = <&k3_clks 205 0>;
- power-domains = <&k3_pds 205 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 205 0>;
- assigned-clock-parents = <&k3_clks 205 2>;
- };
-
- epwm0: pwm@23000000 {
- compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x00 0x23000000 0x00 0x100>;
- power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- epwm1: pwm@23010000 {
- compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x00 0x23010000 0x00 0x100>;
- power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- epwm2: pwm@23020000 {
- compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x00 0x23020000 0x00 0x100>;
- power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- ecap0: pwm@23100000 {
- compatible = "ti,am3352-ecap";
- #pwm-cells = <3>;
- reg = <0x00 0x23100000 0x00 0x100>;
- power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 51 0>;
- clock-names = "fck";
- status = "disabled";
- };
-
- ecap1: pwm@23110000 {
- compatible = "ti,am3352-ecap";
- #pwm-cells = <3>;
- reg = <0x00 0x23110000 0x00 0x100>;
- power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 52 0>;
- clock-names = "fck";
- status = "disabled";
- };
-
- ecap2: pwm@23120000 {
- compatible = "ti,am3352-ecap";
- #pwm-cells = <3>;
- reg = <0x00 0x23120000 0x00 0x100>;
- power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 53 0>;
- clock-names = "fck";
- status = "disabled";
- };
-
- mcasp0: audio-controller@2b00000 {
- compatible = "ti,am33xx-mcasp-audio";
- reg = <0x00 0x02b00000 0x00 0x2000>,
- <0x00 0x02b08000 0x00 0x400>;
- reg-names = "mpu", "dat";
- interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx", "rx";
-
- dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>;
- dma-names = "tx", "rx";
-
- clocks = <&k3_clks 190 0>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 190 0>;
- assigned-clock-parents = <&k3_clks 190 2>;
- power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- mcasp1: audio-controller@2b10000 {
- compatible = "ti,am33xx-mcasp-audio";
- reg = <0x00 0x02b10000 0x00 0x2000>,
- <0x00 0x02b18000 0x00 0x400>;
- reg-names = "mpu", "dat";
- interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx", "rx";
-
- dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>;
- dma-names = "tx", "rx";
-
- clocks = <&k3_clks 191 0>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 191 0>;
- assigned-clock-parents = <&k3_clks 191 2>;
- power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- mcasp2: audio-controller@2b20000 {
- compatible = "ti,am33xx-mcasp-audio";
- reg = <0x00 0x02b20000 0x00 0x2000>,
- <0x00 0x02b28000 0x00 0x400>;
- reg-names = "mpu", "dat";
- interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx", "rx";
-
- dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>;
- dma-names = "tx", "rx";
-
- clocks = <&k3_clks 192 0>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 192 0>;
- assigned-clock-parents = <&k3_clks 192 2>;
- power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- ti_csi2rx0: ticsi2rx@30102000 {
- compatible = "ti,j721e-csi2rx-shim";
- dmas = <&main_bcdma_csi 0 0x5000 0>;
- dma-names = "rx0";
- reg = <0x00 0x30102000 0x00 0x1000>;
- power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- status = "disabled";
-
- cdns_csi2rx0: csi-bridge@30101000 {
- compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
- reg = <0x00 0x30101000 0x00 0x1000>;
- clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>,
- <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>;
- clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
- "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
- phys = <&dphy0>;
- phy-names = "dphy";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- csi0_port0: port@0 {
- reg = <0>;
- status = "disabled";
- };
-
- csi0_port1: port@1 {
- reg = <1>;
- status = "disabled";
- };
-
- csi0_port2: port@2 {
- reg = <2>;
- status = "disabled";
- };
-
- csi0_port3: port@3 {
- reg = <3>;
- status = "disabled";
- };
-
- csi0_port4: port@4 {
- reg = <4>;
- status = "disabled";
- };
- };
- };
- };
-
- dphy0: phy@30110000 {
- compatible = "cdns,dphy-rx";
- reg = <0x00 0x30110000 0x00 0x1100>;
- #phy-cells = <0>;
- power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- dss: dss@30200000 {
- compatible = "ti,am62a7-dss";
- reg = <0x00 0x30200000 0x00 0x1000>, /* common */
- <0x00 0x30202000 0x00 0x1000>, /* vidl1 */
- <0x00 0x30206000 0x00 0x1000>, /* vid */
- <0x00 0x30207000 0x00 0x1000>, /* ovr1 */
- <0x00 0x30208000 0x00 0x1000>, /* ovr2 */
- <0x00 0x3020a000 0x00 0x1000>, /* vp1: Tied OFF in the SoC */
- <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */
- <0x00 0x30201000 0x00 0x1000>; /* common1 */
- reg-names = "common", "vidl1", "vid",
- "ovr1", "ovr2", "vp1", "vp2", "common1";
- power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 186 6>,
- <&k3_clks 186 0>,
- <&k3_clks 186 2>;
- clock-names = "fck", "vp1", "vp2";
- interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
-
- dss_ports: ports {
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-};
diff --git a/arch/arm/dts/k3-am62a-mcu.dtsi b/arch/arm/dts/k3-am62a-mcu.dtsi
deleted file mode 100644
index 8c36e56..0000000
--- a/arch/arm/dts/k3-am62a-mcu.dtsi
+++ /dev/null
@@ -1,170 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-/*
- * Device Tree Source for AM625 SoC Family MCU Domain peripherals
- *
- * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-&cbass_mcu {
- mcu_pmx0: pinctrl@4084000 {
- compatible = "pinctrl-single";
- reg = <0x00 0x04084000 0x00 0x88>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0xffffffff>;
- status = "disabled";
- };
-
- /*
- * The MCU domain timer interrupts are routed only to the ESM module,
- * and not currently available for Linux. The MCU domain timers are
- * of limited use without interrupts, and likely reserved by the ESM.
- */
- mcu_timer0: timer@4800000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x4800000 0x00 0x400>;
- clocks = <&k3_clks 35 2>;
- clock-names = "fck";
- power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- status = "reserved";
- };
-
- mcu_timer1: timer@4810000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x4810000 0x00 0x400>;
- clocks = <&k3_clks 48 2>;
- clock-names = "fck";
- power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- status = "reserved";
- };
-
- mcu_timer2: timer@4820000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x4820000 0x00 0x400>;
- clocks = <&k3_clks 49 2>;
- clock-names = "fck";
- power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- status = "reserved";
- };
-
- mcu_timer3: timer@4830000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x4830000 0x00 0x400>;
- clocks = <&k3_clks 50 2>;
- clock-names = "fck";
- power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- status = "reserved";
- };
-
- mcu_uart0: serial@4a00000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x04a00000 0x00 0x100>;
- interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 149 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- mcu_i2c0: i2c@4900000 {
- compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x04900000 0x00 0x100>;
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 106 2>;
- clock-names = "fck";
- status = "disabled";
- };
-
- mcu_spi0: spi@4b00000 {
- compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
- reg = <0x00 0x04b00000 0x00 0x400>;
- interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 147 0>;
- status = "disabled";
- };
-
- mcu_spi1: spi@4b10000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x04b10000 0x00 0x400>;
- interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 148 0>;
- status = "disabled";
- };
-
- mcu_gpio_intr: interrupt-controller@4210000 {
- compatible = "ti,sci-intr";
- reg = <0x00 0x04210000 0x00 0x200>;
- ti,intr-trigger-type = <1>;
- interrupt-controller;
- interrupt-parent = <&gic500>;
- #interrupt-cells = <1>;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <5>;
- ti,interrupt-ranges = <0 104 4>;
- };
-
- mcu_gpio0: gpio@4201000 {
- compatible = "ti,am64-gpio", "ti,keystone-gpio";
- reg = <0x00 0x04201000 0x00 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&mcu_gpio_intr>;
- interrupts = <30>, <31>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <24>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 79 0>;
- clock-names = "gpio";
- status = "disabled";
- };
-
- mcu_rti0: watchdog@4880000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x04880000 0x00 0x100>;
- clocks = <&k3_clks 131 0>;
- power-domains = <&k3_pds 131 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 131 0>;
- assigned-clock-parents = <&k3_clks 131 2>;
- /* Tightly coupled to M4F */
- status = "reserved";
- };
-
- mcu_mcan0: can@4e08000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x4e08000 0x00 0x200>,
- <0x00 0x4e00000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 188 6>, <&k3_clks 188 1>;
- clock-names = "hclk", "cclk";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- mcu_mcan1: can@4e18000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x4e18000 0x00 0x200>,
- <0x00 0x4e10000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 189 6>, <&k3_clks 189 1>;
- clock-names = "hclk", "cclk";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-};
diff --git a/arch/arm/dts/k3-am62a-sk-binman.dtsi b/arch/arm/dts/k3-am62a-sk-binman.dtsi
index ec3bf7c..2a8c260 100644
--- a/arch/arm/dts/k3-am62a-sk-binman.dtsi
+++ b/arch/arm/dts/k3-am62a-sk-binman.dtsi
@@ -144,7 +144,7 @@
#ifdef CONFIG_TARGET_AM62A7_A53_EVM
-#define SPL_AM62A7_SK_DTB "spl/dts/k3-am62a7-sk.dtb"
+#define SPL_AM62A7_SK_DTB "spl/dts/ti/k3-am62a7-sk.dtb"
#define AM62A7_SK_DTB "u-boot.dtb"
&binman {
@@ -152,13 +152,108 @@
filename = "ti-dm.bin";
blob-ext {
filename = "ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+ optional;
};
};
+
+ tifsstub-hs {
+ filename = "tifsstub.bin_hs";
+ ti-secure-rom {
+ content = <&tifsstub_hs_cert>;
+ core = "secure";
+ load = <0x60000>;
+ sw-rev = <CONFIG_K3_X509_SWRV>;
+ keyfile = "custMpk.pem";
+ countersign;
+ tifsstub;
+ };
+ tifsstub_hs_cert: tifsstub-hs-cert.bin {
+ filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-hs-cert.bin";
+ type = "blob-ext";
+ optional;
+ };
+ tifsstub_hs_enc: tifsstub-hs-enc.bin {
+ filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-hs-enc.bin";
+ type = "blob-ext";
+ optional;
+ };
+ };
+
+ tifsstub-fs {
+ filename = "tifsstub.bin_fs";
+ tifsstub_fs_cert: tifsstub-fs-cert.bin {
+ filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-hs-cert.bin";
+ type = "blob-ext";
+ optional;
+ };
+ tifsstub_fs_enc: tifsstub-fs-enc.bin {
+ filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-hs-enc.bin";
+ type = "blob-ext";
+ optional;
+ };
+
+ };
+
+ tifsstub-gp {
+ filename = "tifsstub.bin_gp";
+ ti-secure-rom {
+ content = <&tifsstub_gp>;
+ core = "secure";
+ load = <0x60000>;
+ sw-rev = <CONFIG_K3_X509_SWRV>;
+ keyfile = "ti-degenerate-key.pem";
+ tifsstub;
+ };
+ tifsstub_gp: tifsstub-gp.bin {
+ filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-gp.bin";
+ type = "blob-ext";
+ optional;
+ };
+ };
+
ti-spl {
insert-template = <&ti_spl_template>;
fit {
images {
+ tifsstub-hs {
+ description = "TIFSSTUB";
+ type = "firmware";
+ arch = "arm32";
+ compression = "none";
+ os = "tifsstub-hs";
+ load = <0x9ca00000>;
+ entry = <0x9ca00000>;
+ blob-ext {
+ filename = "tifsstub.bin_hs";
+ };
+ };
+
+ tifsstub-fs {
+ description = "TIFSSTUB";
+ type = "firmware";
+ arch = "arm32";
+ compression = "none";
+ os = "tifsstub-fs";
+ load = <0x9ca00000>;
+ entry = <0x9ca00000>;
+ blob-ext {
+ filename = "tifsstub.bin_fs";
+ };
+ };
+
+ tifsstub-gp {
+ description = "TIFSSTUB";
+ type = "firmware";
+ arch = "arm32";
+ compression = "none";
+ os = "tifsstub-gp";
+ load = <0x9ca00000>;
+ entry = <0x9ca00000>;
+ blob-ext {
+ filename = "tifsstub.bin_gp";
+ };
+ };
dm {
ti-secure {
content = <&dm>;
@@ -192,7 +287,8 @@
conf-0 {
description = "k3-am62a7-sk";
firmware = "atf";
- loadables = "tee", "dm", "spl";
+ loadables = "tee", "dm", "spl",
+ "tifsstub-hs", "tifsstub-fs", "tifsstub-gp";
fdt = "fdt-0";
};
};
@@ -249,6 +345,44 @@
fit {
images {
+ tifsstub-hs {
+ description = "tifsstub";
+ type = "firmware";
+ arch = "arm32";
+ compression = "none";
+ os = "tifsstub-hs";
+ load = <0x9ca00000>;
+ entry = <0x9ca00000>;
+ blob-ext {
+ filename = "tifsstub.bin_hs";
+ };
+ };
+
+ tifsstub-fs {
+ description = "tifsstub";
+ type = "firmware";
+ arch = "arm32";
+ compression = "none";
+ os = "tifsstub-fs";
+ load = <0x9ca00000>;
+ entry = <0x9ca00000>;
+ blob-ext {
+ filename = "tifsstub.bin_fs";
+ };
+ };
+
+ tifsstub-gp {
+ description = "tifsstub";
+ type = "firmware";
+ arch = "arm32";
+ compression = "none";
+ os = "tifsstub-gp";
+ load = <0x9ca00000>;
+ entry = <0x9ca00000>;
+ blob-ext {
+ filename = "tifsstub.bin_gp";
+ };
+ };
dm {
ti-dm {
filename = "ti-dm.bin";
@@ -272,7 +406,8 @@
conf-0 {
description = "k3-am62a7-sk";
firmware = "atf";
- loadables = "tee", "dm", "spl";
+ loadables = "tee", "dm", "spl",
+ "tifsstub-hs", "tifsstub-fs", "tifsstub-gp";
fdt = "fdt-0";
};
};
diff --git a/arch/arm/dts/k3-am62a-thermal.dtsi b/arch/arm/dts/k3-am62a-thermal.dtsi
deleted file mode 100644
index c7486fb..0000000
--- a/arch/arm/dts/k3-am62a-thermal.dtsi
+++ /dev/null
@@ -1,50 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-/*
- * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#include <dt-bindings/thermal/thermal.h>
-
-thermal_zones: thermal-zones {
- main0_thermal: main0-thermal {
- polling-delay-passive = <250>; /* milliSeconds */
- polling-delay = <500>; /* milliSeconds */
- thermal-sensors = <&wkup_vtm0 0>;
-
- trips {
- main0_crit: main0-crit {
- temperature = <125000>; /* milliCelsius */
- hysteresis = <2000>; /* milliCelsius */
- type = "critical";
- };
- };
- };
-
- main1_thermal: main1-thermal {
- polling-delay-passive = <250>; /* milliSeconds */
- polling-delay = <500>; /* milliSeconds */
- thermal-sensors = <&wkup_vtm0 1>;
-
- trips {
- main1_crit: main1-crit {
- temperature = <125000>; /* milliCelsius */
- hysteresis = <2000>; /* milliCelsius */
- type = "critical";
- };
- };
- };
-
- main2_thermal: main2-thermal {
- polling-delay-passive = <250>; /* milliSeconds */
- polling-delay = <500>; /* milliSeconds */
- thermal-sensors = <&wkup_vtm0 2>;
-
- trips {
- main2_crit: main2-crit {
- temperature = <125000>; /* milliCelsius */
- hysteresis = <2000>; /* milliCelsius */
- type = "critical";
- };
- };
- };
-};
diff --git a/arch/arm/dts/k3-am62a-wakeup.dtsi b/arch/arm/dts/k3-am62a-wakeup.dtsi
deleted file mode 100644
index f7bec48..0000000
--- a/arch/arm/dts/k3-am62a-wakeup.dtsi
+++ /dev/null
@@ -1,73 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-/*
- * Device Tree Source for AM62A SoC Family Wakeup Domain peripherals
- *
- * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-&cbass_wakeup {
- wkup_conf: syscon@43000000 {
- compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
- reg = <0x00 0x43000000 0x00 0x20000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00 0x00 0x43000000 0x20000>;
-
- chipid: chipid@14 {
- compatible = "ti,am654-chipid";
- reg = <0x14 0x4>;
- };
- };
-
- wkup_uart0: serial@2b300000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x2b300000 0x00 0x100>;
- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 114 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- wkup_i2c0: i2c@2b200000 {
- compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x2b200000 0x00 0x100>;
- interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 107 4>;
- clock-names = "fck";
- status = "disabled";
- };
-
- wkup_rtc0: rtc@2b1f0000 {
- compatible = "ti,am62-rtc";
- reg = <0x00 0x2b1f0000 0x00 0x100>;
- interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 117 6> , <&k3_clks 117 0>;
- clock-names = "vbus", "osc32k";
- power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>;
- wakeup-source;
- status = "disabled";
- };
-
- wkup_rti0: watchdog@2b000000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x2b000000 0x00 0x100>;
- clocks = <&k3_clks 132 0>;
- power-domains = <&k3_pds 132 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 132 0>;
- assigned-clock-parents = <&k3_clks 132 2>;
- /* Used by DM firmware */
- status = "reserved";
- };
-
- wkup_vtm0: temperature-sensor@b00000 {
- compatible = "ti,j7200-vtm";
- reg = <0x00 0xb00000 0x00 0x400>,
- <0x00 0xb01000 0x00 0x400>;
- power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>;
- #thermal-sensor-cells = <1>;
- };
-};
diff --git a/arch/arm/dts/k3-am62a.dtsi b/arch/arm/dts/k3-am62a.dtsi
deleted file mode 100644
index b1b8846..0000000
--- a/arch/arm/dts/k3-am62a.dtsi
+++ /dev/null
@@ -1,125 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-/*
- * Device Tree Source for AM62A SoC Family
- *
- * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/soc/ti,sci_pm_domain.h>
-
-#include "k3-pinctrl.h"
-
-/ {
- model = "Texas Instruments K3 AM62A SoC";
- compatible = "ti,am62a7";
- interrupt-parent = <&gic500>;
- #address-cells = <2>;
- #size-cells = <2>;
-
- chosen { };
-
- firmware {
- optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- };
-
- psci: psci {
- compatible = "arm,psci-1.0";
- method = "smc";
- };
- };
-
- a53_timer0: timer-cl0-cpu0 {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
- <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
- <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
- };
-
- pmu: pmu {
- compatible = "arm,cortex-a53-pmu";
- interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- cbass_main: bus@f0000 {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
-
- ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
- <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
- <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
- <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
- <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
- <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
- <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
- <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
- <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
- <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
- <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
- <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
- <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */
- <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
- <0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */
- <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
- <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
- <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
- <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
- <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
- <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
- <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */
- <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
- <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */
- <0x00 0x7e000000 0x00 0x7e000000 0x00 0x00100000>, /* C7x_0 */
- <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
- <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
-
- /* MCU Domain Range */
- <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>,
- <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */
- <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */
- <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU R5 IRAM0 */
- <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>, /* MCU R5 IRAM1 */
-
- /* Wakeup Domain Range */
- <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>,
- <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>,
- <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>,
- <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM */
- <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM */
-
- cbass_mcu: bus@4000000 {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Peripheral window */
- <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */
- <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */
- <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU IRAM0 */
- <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>; /* MCU IRAM1 */
- };
-
- cbass_wakeup: bus@b00000 {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
- <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
- <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* WKUP CTRL MMR */
- <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/
- <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/
- };
- };
-
- #include "k3-am62a-thermal.dtsi"
-};
-
-/* Now include the peripherals for each bus segments */
-#include "k3-am62a-main.dtsi"
-#include "k3-am62a-mcu.dtsi"
-#include "k3-am62a-wakeup.dtsi"
diff --git a/arch/arm/dts/k3-am62a7-sk.dts b/arch/arm/dts/k3-am62a7-sk.dts
deleted file mode 100644
index f241637..0000000
--- a/arch/arm/dts/k3-am62a7-sk.dts
+++ /dev/null
@@ -1,702 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-/*
- * AM62A SK: https://www.ti.com/lit/zip/sprr459
- *
- * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-/dts-v1/;
-
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/net/ti-dp83867.h>
-#include "k3-am62a7.dtsi"
-
-/ {
- compatible = "ti,am62a7-sk", "ti,am62a7";
- model = "Texas Instruments AM62A7 SK";
-
- aliases {
- serial0 = &wkup_uart0;
- serial2 = &main_uart0;
- serial3 = &main_uart1;
- mmc0 = &sdhci0;
- mmc1 = &sdhci1;
- };
-
- chosen {
- stdout-path = "serial2:115200n8";
- };
-
- memory@80000000 {
- device_type = "memory";
- /* 4G RAM */
- reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
- <0x00000008 0x80000000 0x00000000 0x80000000>;
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- secure_tfa_ddr: tfa@9e780000 {
- reg = <0x00 0x9e780000 0x00 0x80000>;
- alignment = <0x1000>;
- no-map;
- };
-
- secure_ddr: optee@9e800000 {
- reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
- alignment = <0x1000>;
- no-map;
- };
-
- wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0x9c900000 0x00 0x01e00000>;
- no-map;
- };
- };
-
- vmain_pd: regulator-0 {
- /* TPS25750 PD CONTROLLER OUTPUT */
- compatible = "regulator-fixed";
- regulator-name = "vmain_pd";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vcc_5v0: regulator-1 {
- /* Output of TPS63070 */
- compatible = "regulator-fixed";
- regulator-name = "vcc_5v0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vmain_pd>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vcc_3v3_main: regulator-2 {
- /* output of LM5141-Q1 */
- compatible = "regulator-fixed";
- regulator-name = "vcc_3v3_main";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vmain_pd>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vdd_mmc1: regulator-3 {
- /* TPS22918DBVR */
- compatible = "regulator-fixed";
- regulator-name = "vdd_mmc1";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- enable-active-high;
- gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
- };
-
- vcc_3v3_sys: regulator-4 {
- /* output of TPS222965DSGT */
- compatible = "regulator-fixed";
- regulator-name = "vcc_3v3_sys";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc_3v3_main>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&usr_led_pins_default>;
-
- led-0 {
- label = "am62a-sk:green:heartbeat";
- gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- function = LED_FUNCTION_HEARTBEAT;
- default-state = "off";
- };
- };
-
- tlv320_mclk: clk-0 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <12288000>;
- };
-
- hdmi0: connector-hdmi {
- compatible = "hdmi-connector";
- label = "hdmi";
- type = "a";
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&sii9022_out>;
- };
- };
- };
-
- codec_audio: sound {
- compatible = "simple-audio-card";
- simple-audio-card,name = "AM62Ax-SKEVM";
- simple-audio-card,widgets =
- "Headphone", "Headphone Jack",
- "Line", "Line In",
- "Microphone", "Microphone Jack";
- simple-audio-card,routing =
- "Headphone Jack", "HPLOUT",
- "Headphone Jack", "HPROUT",
- "LINE1L", "Line In",
- "LINE1R", "Line In",
- "MIC3R", "Microphone Jack",
- "Microphone Jack", "Mic Bias";
- simple-audio-card,format = "dsp_b";
- simple-audio-card,bitclock-master = <&sound_master>;
- simple-audio-card,frame-master = <&sound_master>;
- simple-audio-card,bitclock-inversion;
-
- simple-audio-card,cpu {
- sound-dai = <&mcasp1>;
- };
-
- sound_master: simple-audio-card,codec {
- sound-dai = <&tlv320aic3106>;
- clocks = <&tlv320_mclk>;
- };
- };
-};
-
-&mcu_pmx0 {
- wkup_uart0_pins_default: wkup-uart0-default-pins {
- pinctrl-single,pins = <
- AM62AX_MCU_IOPAD(0x0024, PIN_INPUT, 0) /* (C9) WKUP_UART0_RXD */
- AM62AX_MCU_IOPAD(0x0028, PIN_OUTPUT, 0) /* (E9) WKUP_UART0_TXD */
- AM62AX_MCU_IOPAD(0x002c, PIN_INPUT, 0) /* (C10) WKUP_UART0_CTSn */
- AM62AX_MCU_IOPAD(0x0030, PIN_OUTPUT, 0) /* (C8) WKUP_UART0_RTSn */
- >;
- };
-};
-
-/* WKUP UART0 is used for DM firmware logs */
-&wkup_uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_uart0_pins_default>;
- status = "reserved";
-};
-
-&main_pmx0 {
- main_dss0_pins_default: main-dss0-default-pins {
- pinctrl-single,pins = <
- AM62AX_IOPAD(0x100, PIN_OUTPUT, 0) /* (V17) VOUT0_VSYNC */
- AM62AX_IOPAD(0x0f8, PIN_OUTPUT, 0) /* (T18) VOUT0_HSYNC */
- AM62AX_IOPAD(0x104, PIN_OUTPUT, 0) /* (AA22) VOUT0_PCLK */
- AM62AX_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (U17) VOUT0_DE */
- AM62AX_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */
- AM62AX_IOPAD(0x0bc, PIN_OUTPUT, 0) /* (U21) VOUT0_DATA1 */
- AM62AX_IOPAD(0x0c0, PIN_OUTPUT, 0) /* (U20) VOUT0_DATA2 */
- AM62AX_IOPAD(0x0c4, PIN_OUTPUT, 0) /* (U19) VOUT0_DATA3 */
- AM62AX_IOPAD(0x0c8, PIN_OUTPUT, 0) /* (T19) VOUT0_DATA4 */
- AM62AX_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (U18) VOUT0_DATA5 */
- AM62AX_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (V22) VOUT0_DATA6 */
- AM62AX_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA7 */
- AM62AX_IOPAD(0x0d8, PIN_OUTPUT, 0) /* (V19) VOUT0_DATA8 */
- AM62AX_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (V18) VOUT0_DATA9 */
- AM62AX_IOPAD(0x0e0, PIN_OUTPUT, 0) /* (W22) VOUT0_DATA10 */
- AM62AX_IOPAD(0x0e4, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA11 */
- AM62AX_IOPAD(0x0e8, PIN_OUTPUT, 0) /* (W20) VOUT0_DATA12 */
- AM62AX_IOPAD(0x0ec, PIN_OUTPUT, 0) /* (W19) VOUT0_DATA13 */
- AM62AX_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (Y21) VOUT0_DATA14 */
- AM62AX_IOPAD(0x0f4, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA15 */
- AM62AX_IOPAD(0x05c, PIN_OUTPUT, 1) /* (P22) GPMC0_AD8.VOUT0_DATA16 */
- AM62AX_IOPAD(0x060, PIN_OUTPUT, 1) /* (R19) GPMC0_AD9.VOUT0_DATA17 */
- AM62AX_IOPAD(0x064, PIN_OUTPUT, 1) /* (R20) GPMC0_AD10.VOUT0_DATA18 */
- AM62AX_IOPAD(0x068, PIN_OUTPUT, 1) /* (R22) GPMC0_AD11.VOUT0_DATA19 */
- AM62AX_IOPAD(0x06c, PIN_OUTPUT, 1) /* (T22) GPMC0_AD12.VOUT0_DATA20 */
- AM62AX_IOPAD(0x070, PIN_OUTPUT, 1) /* (R21) GPMC0_AD13.VOUT0_DATA21 */
- AM62AX_IOPAD(0x074, PIN_OUTPUT, 1) /* (T20) GPMC0_AD14.VOUT0_DATA22 */
- AM62AX_IOPAD(0x078, PIN_OUTPUT, 1) /* (T21) GPMC0_AD15.VOUT0_DATA23 */
- >;
- };
-
- main_uart0_pins_default: main-uart0-default-pins {
- pinctrl-single,pins = <
- AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (E14) UART0_RXD */
- AM62AX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (D15) UART0_TXD */
- >;
- };
-
- main_uart1_pins_default: main-uart1-default-pins {
- pinctrl-single,pins = <
- AM62AX_IOPAD(0x01e8, PIN_INPUT, 1) /* (C17) I2C1_SCL.UART1_RXD */
- AM62AX_IOPAD(0x01ec, PIN_OUTPUT, 1) /* (E17) I2C1_SDA.UART1_TXD */
- AM62AX_IOPAD(0x0194, PIN_INPUT, 2) /* (C19) MCASP0_AXR3.UART1_CTSn */
- AM62AX_IOPAD(0x0198, PIN_OUTPUT, 2) /* (B19) MCASP0_AXR2.UART1_RTSn */
- >;
- };
-
- main_i2c0_pins_default: main-i2c0-default-pins {
- pinctrl-single,pins = <
- AM62AX_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
- AM62AX_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
- >;
- };
-
- main_i2c1_pins_default: main-i2c1-default-pins {
- pinctrl-single,pins = <
- AM62AX_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
- AM62AX_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */
- >;
- };
-
- main_i2c2_pins_default: main-i2c2-default-pins {
- pinctrl-single,pins = <
- AM62AX_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */
- AM62AX_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */
- >;
- };
-
- main_mmc0_pins_default: main-mmc0-default-pins {
- pinctrl-single,pins = <
- AM62AX_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */
- AM62AX_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLKLB */
- AM62AX_IOPAD(0x21c, PIN_INPUT, 0) /* (AB1) MMC0_CLK */
- AM62AX_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */
- AM62AX_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */
- AM62AX_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */
- AM62AX_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */
- AM62AX_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */
- AM62AX_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */
- AM62AX_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */
- AM62AX_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */
- >;
- };
-
- main_mmc1_pins_default: main-mmc1-default-pins {
- pinctrl-single,pins = <
- AM62AX_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
- AM62AX_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
- AM62AX_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */
- AM62AX_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */
- AM62AX_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */
- AM62AX_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */
- AM62AX_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */
- >;
- };
-
- usr_led_pins_default: usr-led-default-pins {
- pinctrl-single,pins = <
- AM62AX_IOPAD(0x244, PIN_OUTPUT, 7) /* (D18) MMC1_SDWP.GPIO1_49 */
- >;
- };
-
- main_usb1_pins_default: main-usb1-default-pins {
- pinctrl-single,pins = <
- AM62AX_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */
- >;
- };
-
- main_mdio1_pins_default: main-mdio1-default-pins {
- pinctrl-single,pins = <
- AM62AX_IOPAD(0x160, PIN_OUTPUT, 0) /* (V12) MDIO0_MDC */
- AM62AX_IOPAD(0x15c, PIN_INPUT, 0) /* (V13) MDIO0_MDIO */
- >;
- };
-
- main_rgmii1_pins_default: main-rgmii1-default-pins {
- pinctrl-single,pins = <
- AM62AX_IOPAD(0x14c, PIN_INPUT, 0) /* (AB16) RGMII1_RD0 */
- AM62AX_IOPAD(0x150, PIN_INPUT, 0) /* (V15) RGMII1_RD1 */
- AM62AX_IOPAD(0x154, PIN_INPUT, 0) /* (W15) RGMII1_RD2 */
- AM62AX_IOPAD(0x158, PIN_INPUT, 0) /* (V14) RGMII1_RD3 */
- AM62AX_IOPAD(0x148, PIN_INPUT, 0) /* (AA16) RGMII1_RXC */
- AM62AX_IOPAD(0x144, PIN_INPUT, 0) /* (AA15) RGMII1_RX_CTL */
- AM62AX_IOPAD(0x134, PIN_INPUT, 0) /* (Y17) RGMII1_TD0 */
- AM62AX_IOPAD(0x138, PIN_INPUT, 0) /* (V16) RGMII1_TD1 */
- AM62AX_IOPAD(0x13c, PIN_INPUT, 0) /* (Y16) RGMII1_TD2 */
- AM62AX_IOPAD(0x140, PIN_INPUT, 0) /* (AA17) RGMII1_TD3 */
- AM62AX_IOPAD(0x130, PIN_INPUT, 0) /* (AB17) RGMII1_TXC */
- AM62AX_IOPAD(0x12c, PIN_INPUT, 0) /* (W16) RGMII1_TX_CTL */
- >;
- };
-
- main_mcasp1_pins_default: main-mcasp1-default-pins {
- pinctrl-single,pins = <
- AM62AX_IOPAD(0x090, PIN_INPUT, 2) /* (L19) GPMC0_BE0n_CLE.MCASP1_ACLKX */
- AM62AX_IOPAD(0x098, PIN_INPUT, 2) /* (R18) GPMC0_WAIT0.MCASP1_AFSX */
- AM62AX_IOPAD(0x08c, PIN_OUTPUT, 2) /* (K19) GPMC0_WEn.MCASP1_AXR0 */
- AM62AX_IOPAD(0x084, PIN_INPUT, 2) /* (L18) GPMC0_ADVn_ALE.MCASP1_AXR2 */
- >;
- };
-
- main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins {
- pinctrl-single,pins = <
- AM62AX_IOPAD(0x01d4, PIN_INPUT, 7) /* (C15) UART0_RTSn.GPIO1_23 */
- >;
- };
-};
-
-&mcu_pmx0 {
- status = "okay";
-
- pmic_irq_pins_default: pmic-irq-default-pins {
- pinctrl-single,pins = <
- AM62AX_MCU_IOPAD(0x000, PIN_INPUT, 7) /* (E11) MCU_GPIO0_0 */
- >;
- };
-};
-
-&mcu_gpio0 {
- status = "okay";
-};
-
-&main_i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c0_pins_default>;
- clock-frequency = <400000>;
-
- typec_pd0: usb-power-controller@3f {
- compatible = "ti,tps6598x";
- reg = <0x3f>;
-
- connector {
- compatible = "usb-c-connector";
- label = "USB-C";
- self-powered;
- data-role = "dual";
- power-role = "sink";
- port {
- usb_con_hs: endpoint {
- remote-endpoint = <&usb0_hs_ep>;
- };
- };
- };
- };
-
- tps659312: pmic@48 {
- compatible = "ti,tps6593-q1";
- reg = <0x48>;
- ti,primary-pmic;
- system-power-controller;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_irq_pins_default>;
- interrupt-parent = <&mcu_gpio0>;
- interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
-
- buck123-supply = <&vcc_3v3_sys>;
- buck4-supply = <&vcc_3v3_sys>;
- buck5-supply = <&vcc_3v3_sys>;
- ldo1-supply = <&vcc_3v3_sys>;
- ldo2-supply = <&vcc_3v3_sys>;
- ldo3-supply = <&buck5>;
- ldo4-supply = <&vcc_3v3_sys>;
-
- regulators {
- buck123: buck123 {
- regulator-name = "vcc_core";
- regulator-min-microvolt = <715000>;
- regulator-max-microvolt = <895000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck4: buck4 {
- regulator-name = "vcc_1v1";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck5: buck5 {
- regulator-name = "vcc_1v8_sys";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo1: ldo1 {
- regulator-name = "vddshv5_sdio";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo2: ldo2 {
- regulator-name = "vpp_1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo3: ldo3 {
- regulator-name = "vcc_0v85";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo4: ldo4 {
- regulator-name = "vdda_1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
-};
-
-&main_i2c1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c1_pins_default>;
- clock-frequency = <100000>;
-
- exp1: gpio@22 {
- compatible = "ti,tca6424";
- reg = <0x22>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&main_gpio1>;
- interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
- interrupt-controller;
- #interrupt-cells = <2>;
- pinctrl-names = "default";
- pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>;
-
- gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
- "BT_EN_SOC", "MMC1_SD_EN",
- "VPP_EN", "EXP_PS_3V3_En",
- "EXP_PS_5V0_En", "EXP_HAT_DETECT",
- "GPIO_AUD_RSTn", "GPIO_eMMC_RSTn",
- "UART1_FET_BUF_EN", "BT_UART_WAKE_SOC",
- "GPIO_HDMI_RSTn", "CSI_GPIO0",
- "CSI_GPIO1", "WLAN_ALERTn",
- "HDMI_INTn", "TEST_GPIO2",
- "MCASP1_FET_EN", "MCASP1_BUF_BT_EN",
- "MCASP1_FET_SEL", "UART1_FET_SEL",
- "PD_I2C_IRQ", "IO_EXP_TEST_LED";
- };
-
- tlv320aic3106: audio-codec@1b {
- #sound-dai-cells = <0>;
- compatible = "ti,tlv320aic3106";
- reg = <0x1b>;
- ai3x-micbias-vg = <1>; /* 2.0V */
-
- /* Regulators */
- AVDD-supply = <&vcc_3v3_sys>;
- IOVDD-supply = <&vcc_3v3_sys>;
- DRVDD-supply = <&vcc_3v3_sys>;
- DVDD-supply = <&buck5>;
- };
-
- exp2: gpio@23 {
- compatible = "ti,tca6424";
- reg = <0x23>;
- gpio-controller;
- #gpio-cells = <2>;
-
- gpio-line-names = "", "",
- "", "",
- "", "",
- "", "",
- "WL_LT_EN", "CSI_RSTz",
- "", "",
- "", "",
- "", "",
- "SPI0_FET_SEL", "SPI0_FET_OE",
- "RGMII2_BRD_CONN_DET", "CSI_SEL2",
- "CSI_EN", "AUTO_100M_1000M_CONFIG",
- "CSI_VLDO_SEL", "SoC_WLAN_SDIO_RST";
- };
-
- sii9022: bridge-hdmi@3b {
- compatible = "sil,sii9022";
- reg = <0x3b>;
- interrupt-parent = <&exp1>;
- interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
- #sound-dai-cells = <0>;
- sil,i2s-data-lanes = < 0 >;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- sii9022_in: endpoint {
- remote-endpoint = <&dpi1_out>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- sii9022_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
- };
- };
- };
-};
-
-&main_i2c2 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c2_pins_default>;
- clock-frequency = <400000>;
-};
-
-&sdhci0 {
- /* eMMC */
- status = "okay";
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&main_mmc0_pins_default>;
- disable-wp;
-};
-
-&sdhci1 {
- /* SD/MMC */
- status = "okay";
- vmmc-supply = <&vdd_mmc1>;
- pinctrl-names = "default";
- pinctrl-0 = <&main_mmc1_pins_default>;
- disable-wp;
-};
-
-&main_gpio0 {
- status = "okay";
-};
-
-&main_gpio1 {
- status = "okay";
-};
-
-&main_gpio_intr {
- status = "okay";
-};
-
-&main_uart0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart0_pins_default>;
-};
-
-/* Main UART1 is used for TIFS firmware logs */
-&main_uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart1_pins_default>;
- status = "reserved";
-};
-
-&usbss0 {
- status = "okay";
- ti,vbus-divider;
-};
-
-&usb0 {
- usb-role-switch;
-
- port {
- usb0_hs_ep: endpoint {
- remote-endpoint = <&usb_con_hs>;
- };
- };
-};
-
-&usbss1 {
- status = "okay";
-};
-
-&usb1 {
- dr_mode = "host";
- pinctrl-names = "default";
- pinctrl-0 = <&main_usb1_pins_default>;
-};
-
-&cpsw3g {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_rgmii1_pins_default>;
-};
-
-&cpsw_port1 {
- status = "okay";
- phy-mode = "rgmii-rxid";
- phy-handle = <&cpsw3g_phy0>;
-};
-
-&cpsw_port2 {
- status = "disabled";
-};
-
-&cpsw3g_mdio {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_mdio1_pins_default>;
-
- cpsw3g_phy0: ethernet-phy@0 {
- reg = <0>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- ti,min-output-impedance;
- };
-};
-
-&mcasp1 {
- status = "okay";
- #sound-dai-cells = <0>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&main_mcasp1_pins_default>;
-
- op-mode = <0>; /* MCASP_IIS_MODE */
- tdm-slots = <2>;
-
- serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
- 1 0 2 0
- 0 0 0 0
- 0 0 0 0
- 0 0 0 0
- >;
- tx-num-evt = <32>;
- rx-num-evt = <32>;
-};
-
-&dss {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_dss0_pins_default>;
-};
-
-&dss_ports {
- /* VP2: DPI Output */
- port@1 {
- reg = <1>;
-
- dpi1_out: endpoint {
- remote-endpoint = <&sii9022_in>;
- };
- };
-};
diff --git a/arch/arm/dts/k3-am62p-sk-binman.dtsi b/arch/arm/dts/k3-am62p-sk-binman.dtsi
index dea1494..2177d54 100644
--- a/arch/arm/dts/k3-am62p-sk-binman.dtsi
+++ b/arch/arm/dts/k3-am62p-sk-binman.dtsi
@@ -59,6 +59,17 @@
};
};
+#include "k3-binman-capsule-r5.dtsi"
+
+// Capsule update GUIDs in string form. See am62px_evm.h
+#define AM62PX_SK_TIBOOT3_IMAGE_GUID_STR "b08471b7-be2d-4489-87a1-cab28a0cf743"
+
+&capsule_tiboot3 {
+ efi-capsule {
+ image-guid = AM62PX_SK_TIBOOT3_IMAGE_GUID_STR;
+ };
+};
+
#endif /* CONFIG_TARGET_AM62P5_R5_EVM */
#if IS_ENABLED(CONFIG_TARGET_AM62P5_A53_EVM)
@@ -72,14 +83,77 @@
blob-ext {
filename = "ti-dm/am62pxx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+ optional;
};
};
+ tifsstub-hs {
+ filename = "tifsstub.bin_hs";
+ ti-secure-rom {
+ content = <&tifsstub_hs_cert>;
+ core = "secure";
+ load = <0x60000>;
+ sw-rev = <CONFIG_K3_X509_SWRV>;
+ keyfile = "custMpk.pem";
+ countersign;
+ tifsstub;
+ };
+ tifsstub_hs_cert: tifsstub-hs-cert.bin {
+ filename = "ti-sysfw/ti-fs-stub-firmware-am62px-hs-cert.bin";
+ type = "blob-ext";
+ optional;
+ };
+ tifsstub_hs_enc: tifsstub-hs-enc.bin {
+ filename = "ti-sysfw/ti-fs-stub-firmware-am62px-hs-enc.bin";
+ type = "blob-ext";
+ optional;
+ };
+ };
+
+ tifsstub-fs {
+ filename = "tifsstub.bin_fs";
+ tifsstub_fs_cert: tifsstub-fs-cert.bin {
+ filename = "ti-sysfw/ti-fs-stub-firmware-am62px-hs-cert.bin";
+ type = "blob-ext";
+ optional;
+ };
+ tifsstub_fs_enc: tifsstub-fs-enc.bin {
+ filename = "ti-sysfw/ti-fs-stub-firmware-am62px-hs-enc.bin";
+ type = "blob-ext";
+ optional;
+ };
+
+ };
ti-spl {
insert-template = <&ti_spl_template>;
fit {
images {
+ tifsstub-hs {
+ description = "TIFSSTUB";
+ type = "firmware";
+ arch = "arm32";
+ compression = "none";
+ os = "tifsstub-hs";
+ load = <0x9ca00000>;
+ entry = <0x9ca00000>;
+ blob-ext {
+ filename = "tifsstub.bin_hs";
+ };
+ };
+
+ tifsstub-fs {
+ description = "TIFSSTUB";
+ type = "firmware";
+ arch = "arm32";
+ compression = "none";
+ os = "tifsstub-fs";
+ load = <0x9ca00000>;
+ entry = <0x9ca00000>;
+ blob-ext {
+ filename = "tifsstub.bin_fs";
+ };
+ };
dm {
ti-secure {
content = <&dm>;
@@ -116,7 +190,8 @@
conf-0 {
description = "k3-am62px-sk";
firmware = "atf";
- loadables = "tee", "dm", "spl";
+ loadables = "tee", "dm", "spl",
+ "tifsstub-hs", "tifsstub-fs";
fdt = "fdt-0";
};
};
@@ -170,4 +245,22 @@
};
};
+#include "k3-binman-capsule.dtsi"
+
+// Capsule update GUIDs in string form. See am62px_evm.h
+#define AM62PX_SK_SPL_IMAGE_GUID_STR "d02ed781-6d71-4c1a-a999-3c6a41c36324"
+#define AM62PX_SK_UBOOT_IMAGE_GUID_STR "7e6aea51-965c-44ab-b388-daeb03b54f66"
+
+&capsule_tispl {
+ efi-capsule {
+ image-guid = AM62PX_SK_SPL_IMAGE_GUID_STR;
+ };
+};
+
+&capsule_uboot {
+ efi-capsule {
+ image-guid = AM62PX_SK_UBOOT_IMAGE_GUID_STR;
+ };
+};
+
#endif /* CONFIG_TARGET_AM62P5_A53_EVM */
diff --git a/arch/arm/dts/k3-am62x-sk-common.dtsi b/arch/arm/dts/k3-am62x-sk-common.dtsi
deleted file mode 100644
index 3c45782..0000000
--- a/arch/arm/dts/k3-am62x-sk-common.dtsi
+++ /dev/null
@@ -1,535 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-/*
- * Common dtsi for AM62x SK and derivatives
- *
- * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/net/ti-dp83867.h>
-#include "k3-am625.dtsi"
-
-/ {
- aliases {
- serial2 = &main_uart0;
- mmc0 = &sdhci0;
- mmc1 = &sdhci1;
- mmc2 = &sdhci2;
- spi0 = &ospi0;
- ethernet0 = &cpsw_port1;
- ethernet1 = &cpsw_port2;
- usb0 = &usb0;
- usb1 = &usb1;
- };
-
- chosen {
- stdout-path = "serial2:115200n8";
- };
-
- memory@80000000 {
- bootph-pre-ram;
- device_type = "memory";
- /* 2G RAM */
- reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- ramoops@9ca00000 {
- compatible = "ramoops";
- reg = <0x00 0x9ca00000 0x00 0x00100000>;
- record-size = <0x8000>;
- console-size = <0x8000>;
- ftrace-size = <0x00>;
- pmsg-size = <0x8000>;
- };
-
- secure_tfa_ddr: tfa@9e780000 {
- reg = <0x00 0x9e780000 0x00 0x80000>;
- alignment = <0x1000>;
- no-map;
- };
-
- secure_ddr: optee@9e800000 {
- reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
- alignment = <0x1000>;
- no-map;
- };
-
- wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0x9db00000 0x00 0xc00000>;
- no-map;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&usr_led_pins_default>;
-
- led-0 {
- label = "am62-sk:green:heartbeat";
- gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- function = LED_FUNCTION_HEARTBEAT;
- default-state = "off";
- };
- };
-
- tlv320_mclk: clk-0 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <12288000>;
- };
-
- codec_audio: sound {
- compatible = "simple-audio-card";
- simple-audio-card,name = "AM62x-SKEVM";
- simple-audio-card,widgets =
- "Headphone", "Headphone Jack",
- "Line", "Line In",
- "Microphone", "Microphone Jack";
- simple-audio-card,routing =
- "Headphone Jack", "HPLOUT",
- "Headphone Jack", "HPROUT",
- "LINE1L", "Line In",
- "LINE1R", "Line In",
- "MIC3R", "Microphone Jack",
- "Microphone Jack", "Mic Bias";
- simple-audio-card,format = "dsp_b";
- simple-audio-card,bitclock-master = <&sound_master>;
- simple-audio-card,frame-master = <&sound_master>;
- simple-audio-card,bitclock-inversion;
-
- simple-audio-card,cpu {
- sound-dai = <&mcasp1>;
- };
-
- sound_master: simple-audio-card,codec {
- sound-dai = <&tlv320aic3106>;
- clocks = <&tlv320_mclk>;
- };
- };
-
- hdmi0: connector-hdmi {
- compatible = "hdmi-connector";
- label = "hdmi";
- type = "a";
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&sii9022_out>;
- };
- };
- };
-};
-
-&main_pmx0 {
- /* First pad number is ALW package and second is AMC package */
- main_uart0_pins_default: main-uart0-default-pins {
- bootph-all;
- pinctrl-single,pins = <
- AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14/A13) UART0_RXD */
- AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14/E11) UART0_TXD */
- >;
- };
-
- main_uart1_pins_default: main-uart1-default-pins {
- bootph-pre-ram;
- pinctrl-single,pins = <
- AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19/B18) MCASP0_AXR3.UART1_CTSn */
- AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19/B17) MCASP0_AXR2.UART1_RTSn */
- AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19/D15) MCASP0_AFSR.UART1_RXD */
- AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20/D16) MCASP0_ACLKR.UART1_TXD */
- >;
- };
-
- main_i2c0_pins_default: main-i2c0-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16/E12) I2C0_SCL */
- AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16/D14) I2C0_SDA */
- >;
- };
-
- main_i2c1_pins_default: main-i2c1-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17/A17) I2C1_SCL */
- AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17/A16) I2C1_SDA */
- >;
- };
-
- main_i2c2_pins_default: main-i2c2-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22/H18) GPMC0_CSn2.I2C2_SCL */
- AM62X_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24/H19) GPMC0_CSn3.I2C2_SDA */
- >;
- };
-
- main_mmc0_pins_default: main-mmc0-default-pins {
- bootph-all;
- pinctrl-single,pins = <
- AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3/V3) MMC0_CMD */
- AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1/Y1) MMC0_CLK */
- AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2/V2) MMC0_DAT0 */
- AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1/V1) MMC0_DAT1 */
- AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3/W2) MMC0_DAT2 */
- AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4/W1) MMC0_DAT3 */
- AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2/Y2) MMC0_DAT4 */
- AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1/W3) MMC0_DAT5 */
- AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2/W4) MMC0_DAT6 */
- AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2/V4) MMC0_DAT7 */
- >;
- };
-
- main_mmc1_pins_default: main-mmc1-default-pins {
- bootph-all;
- pinctrl-single,pins = <
- AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21/C18) MMC1_CMD */
- AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22/A20) MMC1_CLK */
- AM62X_IOPAD(0x230, PIN_INPUT, 0) /* (A22/A19) MMC1_DAT0 */
- AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21/B19) MMC1_DAT1 */
- AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21/B20) MMC1_DAT2 */
- AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22/C19) MMC1_DAT3 */
- AM62X_IOPAD(0x240, PIN_INPUT, 0) /* (D17/C15) MMC1_SDCD */
- >;
- };
-
- usr_led_pins_default: usr-led-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x244, PIN_OUTPUT, 7) /* (C17/B15) MMC1_SDWP.GPIO1_49 */
- >;
- };
-
- main_mdio1_pins_default: main-mdio1-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24/V17) MDIO0_MDC */
- AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22/U16) MDIO0_MDIO */
- >;
- };
-
- main_rgmii1_pins_default: main-rgmii1-default-pins {
- bootph-all;
- pinctrl-single,pins = <
- AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17/W15) RGMII1_RD0 */
- AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17/Y16) RGMII1_RD1 */
- AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16/AA17) RGMII1_RD2 */
- AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15/Y15) RGMII1_RD3 */
- AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17/AA16) RGMII1_RXC */
- AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17/W14) RGMII1_RX_CTL */
- AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20/U14) RGMII1_TD0 */
- AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20/AA19) RGMII1_TD1 */
- AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18/Y17) RGMII1_TD2 */
- AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18/AA18) RGMII1_TD3 */
- AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19/W16) RGMII1_TXC */
- AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19/V15) RGMII1_TX_CTL */
- >;
- };
-
- main_usb1_pins_default: main-usb1-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18/E16) USB1_DRVVBUS */
- >;
- };
-
- main_mcasp1_pins_default: main-mcasp1-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x090, PIN_INPUT, 2) /* (M24/K17) GPMC0_BE0N_CLE.MCASP1_ACLKX */
- AM62X_IOPAD(0x098, PIN_INPUT, 2) /* (U23/P21) GPMC0_WAIT0.MCASP1_AFSX */
- AM62X_IOPAD(0x08c, PIN_OUTPUT, 2) /* (L25/J17) GPMC0_WEN.MCASP1_AXR0 */
- AM62X_IOPAD(0x084, PIN_INPUT, 2) /* (L23/K20) GPMC0_ADVN_ALE.MCASP1_AXR2 */
- >;
- };
-
- main_dss0_pins_default: main-dss0-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC */
- AM62X_IOPAD(0x0f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */
- AM62X_IOPAD(0x104, PIN_OUTPUT, 0) /* (AC24) VOUT0_PCLK */
- AM62X_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (Y20) VOUT0_DE */
- AM62X_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */
- AM62X_IOPAD(0x0bc, PIN_OUTPUT, 0) /* (V24) VOUT0_DATA1 */
- AM62X_IOPAD(0x0c0, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA2 */
- AM62X_IOPAD(0x0c4, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA3 */
- AM62X_IOPAD(0x0c8, PIN_OUTPUT, 0) /* (Y25) VOUT0_DATA4 */
- AM62X_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (Y24) VOUT0_DATA5 */
- AM62X_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA6 */
- AM62X_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA7 */
- AM62X_IOPAD(0x0d8, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA8 */
- AM62X_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA9 */
- AM62X_IOPAD(0x0e0, PIN_OUTPUT, 0) /* (V20) VOUT0_DATA10 */
- AM62X_IOPAD(0x0e4, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA11 */
- AM62X_IOPAD(0x0e8, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA12 */
- AM62X_IOPAD(0x0ec, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA13 */
- AM62X_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA14 */
- AM62X_IOPAD(0x0f4, PIN_OUTPUT, 0) /* (AA21) VOUT0_DATA15 */
- AM62X_IOPAD(0x05c, PIN_OUTPUT, 1) /* (R24) GPMC0_AD8.VOUT0_DATA16 */
- AM62X_IOPAD(0x060, PIN_OUTPUT, 1) /* (R25) GPMC0_AD9.VOUT0_DATA17 */
- AM62X_IOPAD(0x064, PIN_OUTPUT, 1) /* (T25) GPMC0_AD10.VOUT0_DATA18 */
- AM62X_IOPAD(0x068, PIN_OUTPUT, 1) /* (R21) GPMC0_AD11.VOUT0_DATA19 */
- AM62X_IOPAD(0x06c, PIN_OUTPUT, 1) /* (T22) GPMC0_AD12.VOUT0_DATA20 */
- AM62X_IOPAD(0x070, PIN_OUTPUT, 1) /* (T24) GPMC0_AD13.VOUT0_DATA21 */
- AM62X_IOPAD(0x074, PIN_OUTPUT, 1) /* (U25) GPMC0_AD14.VOUT0_DATA22 */
- AM62X_IOPAD(0x078, PIN_OUTPUT, 1) /* (U24) GPMC0_AD15.VOUT0_DATA23 */
- >;
- };
-};
-
-&mcu_pmx0 {
- wkup_uart0_pins_default: wkup-uart0-default-pins {
- bootph-pre-ram;
- pinctrl-single,pins = <
- AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6/A7) WKUP_UART0_CTSn */
- AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4/B4) WKUP_UART0_RTSn */
- AM62X_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B4/B5) WKUP_UART0_RXD */
- AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C5/C6) WKUP_UART0_TXD */
- >;
- };
-};
-
-&wkup_uart0 {
- /* WKUP UART0 is used by DM firmware */
- bootph-pre-ram;
- status = "reserved";
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_uart0_pins_default>;
-};
-
-&main_uart0 {
- bootph-all;
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart0_pins_default>;
-};
-
-&main_uart1 {
- /* Main UART1 is used by TIFS firmware */
- bootph-pre-ram;
- status = "reserved";
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart1_pins_default>;
-};
-
-&main_i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c0_pins_default>;
- clock-frequency = <400000>;
-
- eeprom@51 {
- /* AT24C512C-MAHM-T or M24512-DFMC6TG */
- compatible = "atmel,24c512";
- reg = <0x51>;
- };
-
- typec_pd0: tps6598x@3f {
- compatible = "ti,tps6598x";
- reg = <0x3f>;
-
- connector {
- compatible = "usb-c-connector";
- label = "USB-C";
- self-powered;
- data-role = "dual";
- power-role = "sink";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- usb_con_hs: endpoint {
- remote-endpoint = <&usb0_hs_ep>;
- };
- };
- };
- };
- };
-};
-
-&main_i2c1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c1_pins_default>;
- clock-frequency = <100000>;
-
- tlv320aic3106: audio-codec@1b {
- #sound-dai-cells = <0>;
- compatible = "ti,tlv320aic3106";
- reg = <0x1b>;
- ai3x-micbias-vg = <1>; /* 2.0V */
-
- /* Regulators */
- AVDD-supply = <&vcc_3v3_sys>;
- IOVDD-supply = <&vcc_3v3_sys>;
- DRVDD-supply = <&vcc_3v3_sys>;
- };
-
- sii9022: bridge-hdmi@3b {
- compatible = "sil,sii9022";
- reg = <0x3b>;
- interrupt-parent = <&exp1>;
- interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
- #sound-dai-cells = <0>;
- sil,i2s-data-lanes = < 0 >;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- sii9022_in: endpoint {
- remote-endpoint = <&dpi1_out>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- sii9022_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
- };
- };
- };
-};
-
-&main_i2c2 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c2_pins_default>;
- clock-frequency = <400000>;
-};
-
-&sdhci0 {
- bootph-all;
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_mmc0_pins_default>;
- disable-wp;
-};
-
-&sdhci1 {
- /* SD/MMC */
- bootph-all;
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_mmc1_pins_default>;
- disable-wp;
-};
-
-&cpsw3g {
- bootph-all;
- pinctrl-names = "default";
- pinctrl-0 = <&main_rgmii1_pins_default>;
-};
-
-&cpsw_port1 {
- bootph-all;
- phy-mode = "rgmii-rxid";
- phy-handle = <&cpsw3g_phy0>;
-};
-
-&cpsw3g_mdio {
- bootph-all;
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_mdio1_pins_default>;
-
- cpsw3g_phy0: ethernet-phy@0 {
- bootph-all;
- reg = <0>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- ti,min-output-impedance;
- };
-};
-
-&mailbox0_cluster0 {
- mbox_m4_0: mbox-m4-0 {
- ti,mbox-rx = <0 0 0>;
- ti,mbox-tx = <1 0 0>;
- };
-};
-
-&usbss0 {
- bootph-all;
- status = "okay";
- ti,vbus-divider;
-};
-
-&usbss1 {
- status = "okay";
- ti,vbus-divider;
-};
-
-&usb0 {
- bootph-all;
- #address-cells = <1>;
- #size-cells = <0>;
- usb-role-switch;
-
- port@0 {
- reg = <0>;
- usb0_hs_ep: endpoint {
- remote-endpoint = <&usb_con_hs>;
- };
- };
-};
-
-&usb1 {
- dr_mode = "host";
- pinctrl-names = "default";
- pinctrl-0 = <&main_usb1_pins_default>;
-};
-
-&mcasp1 {
- status = "okay";
- #sound-dai-cells = <0>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&main_mcasp1_pins_default>;
-
- op-mode = <0>; /* MCASP_IIS_MODE */
- tdm-slots = <2>;
-
- serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
- 1 0 2 0
- 0 0 0 0
- 0 0 0 0
- 0 0 0 0
- >;
- tx-num-evt = <32>;
- rx-num-evt = <32>;
-};
-
-&dss {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_dss0_pins_default>;
-};
-
-&dss_ports {
- /* VP2: DPI Output */
- port@1 {
- reg = <1>;
-
- dpi1_out: endpoint {
- remote-endpoint = <&sii9022_in>;
- };
- };
-};
-
-/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */
-&mcu_gpio0 {
- status = "reserved";
-};
-
-&mcu_gpio_intr {
- status = "reserved";
-};
diff --git a/arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi b/arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi
index 4677c35..8f3c3a1 100644
--- a/arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi
@@ -115,6 +115,32 @@
bootph-all;
flash@0 {
bootph-all;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "ospi.tiboot3";
+ reg = <0x00000 0x80000>;
+ };
+ partition@80000 {
+ label = "ospi.tispl";
+ reg = <0x080000 0x200000>;
+ };
+ partition@280000 {
+ label = "ospi.u-boot";
+ reg = <0x280000 0x400000>;
+ };
+ partition@680000 {
+ label = "ospi.env";
+ reg = <0x680000 0x40000>;
+ };
+ partition@6c0000 {
+ label = "ospi.env.backup";
+ reg = <0x6c0000 0x40000>;
+ };
+ };
};
};
diff --git a/arch/arm/dts/k3-am64x-binman.dtsi b/arch/arm/dts/k3-am64x-binman.dtsi
index 37817ba..f768c4d 100644
--- a/arch/arm/dts/k3-am64x-binman.dtsi
+++ b/arch/arm/dts/k3-am64x-binman.dtsi
@@ -114,6 +114,17 @@
};
};
+#include "k3-binman-capsule-r5.dtsi"
+
+// Capsule update GUIDs in string form. See am64x_evm.h
+#define AM64X_SK_TIBOOT3_IMAGE_GUID_STR "ede0a0d5-9116-4bfb-aa54-09e97b5afe1a"
+
+&capsule_tiboot3 {
+ efi-capsule {
+ image-guid = AM64X_SK_TIBOOT3_IMAGE_GUID_STR;
+ };
+};
+
#endif
#ifdef CONFIG_TARGET_AM642_A53_EVM
@@ -373,4 +384,23 @@
};
};
};
+
+#include "k3-binman-capsule.dtsi"
+
+// Capsule update GUIDs in string form. See am64x_evm.h
+#define AM64X_SK_SPL_IMAGE_GUID_STR "77678f5c-64d4-4910-ad75-52c9d95cdb1d"
+#define AM64X_SK_UBOOT_IMAGE_GUID_STR "c6ad43a9-7d31-4f5d-83e9-b8efecae05bf"
+
+&capsule_tispl {
+ efi-capsule {
+ image-guid = AM64X_SK_SPL_IMAGE_GUID_STR;
+ };
+};
+
+&capsule_uboot {
+ efi-capsule {
+ image-guid = AM64X_SK_UBOOT_IMAGE_GUID_STR;
+ };
+};
+
#endif
diff --git a/arch/arm/dts/k3-binman-capsule-r5.dtsi b/arch/arm/dts/k3-binman-capsule-r5.dtsi
new file mode 100644
index 0000000..959ceb7
--- /dev/null
+++ b/arch/arm/dts/k3-binman-capsule-r5.dtsi
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&binman {
+ capsule_tiboot3: capsule-tiboot3 {
+ filename = "tiboot3-capsule.bin";
+ efi-capsule {
+ image-index = <0x1>;
+ image-guid = "00000000-0000-0000-0000-000000000000";
+ private-key = "arch/arm/mach-k3/keys/custMpk.pem";
+ public-key-cert = "arch/arm/mach-k3/keys/custMpk.crt";
+ monotonic-count = <0x1>;
+
+ blob {
+ filename = "tiboot3.bin";
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/k3-binman-capsule.dtsi b/arch/arm/dts/k3-binman-capsule.dtsi
new file mode 100644
index 0000000..17e83c9
--- /dev/null
+++ b/arch/arm/dts/k3-binman-capsule.dtsi
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&binman {
+ capsule_tispl: capsule-tispl {
+ filename = "tispl-capsule.bin";
+ efi-capsule {
+ image-index = <0x2>;
+ image-guid = "00000000-0000-0000-0000-000000000000";
+ private-key = "arch/arm/mach-k3/keys/custMpk.pem";
+ public-key-cert = "arch/arm/mach-k3/keys/custMpk.crt";
+ monotonic-count = <0x1>;
+
+ blob {
+ filename = "tispl.bin";
+ };
+ };
+ };
+};
+
+&binman {
+ capsule_uboot: capsule-uboot {
+ filename = "uboot-capsule.bin";
+ efi-capsule {
+ image-index = <0x3>;
+ image-guid = "00000000-0000-0000-0000-000000000000";
+ private-key = "arch/arm/mach-k3/keys/custMpk.pem";
+ public-key-cert = "arch/arm/mach-k3/keys/custMpk.crt";
+ monotonic-count = <0x1>;
+
+ blob {
+ filename = "u-boot.img";
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/k3-j7200-binman.dtsi b/arch/arm/dts/k3-j7200-binman.dtsi
index e8020fe..ef7d459 100644
--- a/arch/arm/dts/k3-j7200-binman.dtsi
+++ b/arch/arm/dts/k3-j7200-binman.dtsi
@@ -273,7 +273,7 @@
#ifdef CONFIG_TARGET_J7200_A72_EVM
-#define SPL_J7200_EVM_DTB "spl/dts/k3-j7200-common-proc-board.dtb"
+#define SPL_J7200_EVM_DTB "spl/dts/ti/k3-j7200-common-proc-board.dtb"
#define J7200_EVM_DTB "u-boot.dtb"
&binman {
@@ -281,6 +281,7 @@
filename = "ti-dm.bin";
blob-ext {
filename = "ti-dm/j7200/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+ optional;
};
};
ti-spl {
diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
index 485f17c..045ef17 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
@@ -26,8 +26,12 @@
&cbass_mcu_wakeup {
bootph-all;
- chipid@43000014 {
+ wkup_conf: bus@43000000 {
bootph-all;
+
+ chipid: chipid@14 {
+ bootph-all;
+ };
};
};
@@ -40,14 +44,6 @@
};
&mcu_udmap {
- reg = <0x0 0x285c0000 0x0 0x100>,
- <0x0 0x284c0000 0x0 0x4000>,
- <0x0 0x2a800000 0x0 0x40000>,
- <0x0 0x284a0000 0x0 0x4000>,
- <0x0 0x2aa00000 0x0 0x40000>,
- <0x0 0x28400000 0x0 0x2000>;
- reg-names = "gcfg", "rchan", "rchanrt", "tchan",
- "tchanrt", "rflow";
bootph-all;
};
diff --git a/arch/arm/dts/k3-j7200-common-proc-board.dts b/arch/arm/dts/k3-j7200-common-proc-board.dts
deleted file mode 100644
index cee2b4b..0000000
--- a/arch/arm/dts/k3-j7200-common-proc-board.dts
+++ /dev/null
@@ -1,396 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-/dts-v1/;
-
-#include "k3-j7200-som-p0.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/net/ti-dp83867.h>
-#include <dt-bindings/phy/phy.h>
-
-#include "k3-serdes.h"
-
-/ {
- compatible = "ti,j7200-evm", "ti,j7200";
- model = "Texas Instruments J7200 EVM";
-
- aliases {
- serial0 = &wkup_uart0;
- serial1 = &mcu_uart0;
- serial2 = &main_uart0;
- serial3 = &main_uart1;
- serial5 = &main_uart3;
- mmc0 = &main_sdhci0;
- mmc1 = &main_sdhci1;
- };
-
- chosen {
- stdout-path = "serial2:115200n8";
- };
-
- evm_12v0: fixedregulator-evm12v0 {
- /* main supply */
- compatible = "regulator-fixed";
- regulator-name = "evm_12v0";
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vsys_3v3: fixedregulator-vsys3v3 {
- /* Output of LM5140 */
- compatible = "regulator-fixed";
- regulator-name = "vsys_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&evm_12v0>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vsys_5v0: fixedregulator-vsys5v0 {
- /* Output of LM5140 */
- compatible = "regulator-fixed";
- regulator-name = "vsys_5v0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&evm_12v0>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vdd_mmc1: fixedregulator-sd {
- /* Output of TPS22918 */
- compatible = "regulator-fixed";
- regulator-name = "vdd_mmc1";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- enable-active-high;
- vin-supply = <&vsys_3v3>;
- gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
- };
-
- vdd_sd_dv: gpio-regulator-TLV71033 {
- /* Output of TLV71033 */
- compatible = "regulator-gpio";
- regulator-name = "tlv71033";
- pinctrl-names = "default";
- pinctrl-0 = <&vdd_sd_dv_pins_default>;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- vin-supply = <&vsys_5v0>;
- gpios = <&main_gpio0 55 GPIO_ACTIVE_HIGH>;
- states = <1800000 0x0>,
- <3300000 0x1>;
- };
-};
-
-&wkup_pmx0 {
- mcu_uart0_pins_default: mcu-uart0-default-pins {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */
- J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */
- J721E_WKUP_IOPAD(0xf8, PIN_INPUT, 0) /* (E20) MCU_UART0_CTSn */
- J721E_WKUP_IOPAD(0xfc, PIN_OUTPUT, 0) /* (E21) MCU_UART0_RTSn */
- >;
- };
-
- wkup_uart0_pins_default: wkup-uart0-default-pins {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */
- J721E_WKUP_IOPAD(0xb4, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */
- >;
- };
-};
-
-&wkup_pmx2 {
- mcu_cpsw_pins_default: mcu-cpsw-default-pins {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
- J721E_WKUP_IOPAD(0x0004, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
- J721E_WKUP_IOPAD(0x0008, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
- J721E_WKUP_IOPAD(0x000c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
- J721E_WKUP_IOPAD(0x0010, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
- J721E_WKUP_IOPAD(0x0014, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
- J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
- J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
- J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
- J721E_WKUP_IOPAD(0x002c, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
- J721E_WKUP_IOPAD(0x0018, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
- J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
- >;
- };
-
- wkup_gpio_pins_default: wkup-gpio-default-pins {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0x70, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */
- >;
- };
-
- mcu_mdio_pins_default: mcu-mdio1-default-pins {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0x0034, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
- J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
- >;
- };
-};
-
-&main_pmx0 {
- main_uart0_pins_default: main-uart0-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */
- J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */
- J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */
- J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */
- >;
- };
-
- main_uart1_pins_default: main-uart1-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0xb8, PIN_INPUT, 0) /* (T18) UART1_RXD */
- J721E_IOPAD(0xbc, PIN_INPUT, 0) /* (T20) UART1_TXD */
- >;
- };
-
- main_uart3_pins_default: main-uart3-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0x60, PIN_INPUT, 11) /* (T15) MCAN8_TX.UART3_CTSn */
- J721E_IOPAD(0x30, PIN_INPUT, 11) /* (Y18) MCAN2_TX.UART3_RXD */
- >;
- };
-
- main_i2c1_pins_default: main-i2c1-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */
- J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */
- >;
- };
-
- main_mmc1_pins_default: main-mmc1-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */
- J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */
- J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
- J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */
- J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */
- J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */
- J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
- J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */
- >;
- };
-
- vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */
- >;
- };
-};
-
-&main_pmx1 {
- main_usbss0_pins_default: main-usbss0-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
- >;
- };
-};
-
-&wkup_uart0 {
- /* Wakeup UART is used by System firmware */
- status = "reserved";
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_uart0_pins_default>;
-};
-
-&mcu_uart0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_uart0_pins_default>;
- clock-frequency = <96000000>;
-};
-
-&main_uart0 {
- status = "okay";
- /* Shared with ATF on this platform */
- power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart0_pins_default>;
-};
-
-&main_uart1 {
- status = "okay";
- /* Default pinmux */
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart1_pins_default>;
-};
-
-&main_uart2 {
- /* MAIN UART 2 is used by R5F firmware */
- status = "reserved";
-};
-
-&main_uart3 {
- /* Shared with MCAN Interface */
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart3_pins_default>;
-};
-
-&main_gpio0 {
- status = "okay";
-};
-
-&wkup_gpio0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_gpio_pins_default>;
-};
-
-&mcu_cpsw {
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
-};
-
-&davinci_mdio {
- phy0: ethernet-phy@0 {
- reg = <0>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- };
-};
-
-&cpsw_port1 {
- phy-mode = "rgmii-rxid";
- phy-handle = <&phy0>;
-};
-
-&main_i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c0_pins_default>;
- clock-frequency = <400000>;
-
- exp1: gpio@20 {
- compatible = "ti,tca6416";
- reg = <0x20>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- exp2: gpio@22 {
- compatible = "ti,tca6424";
- reg = <0x22>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-};
-
-/*
- * The j7200 CPB board is identical to the CPB used for J721E, the SOMs can be
- * swapped on the CPB.
- *
- * main_i2c1 of J7200 is connected to the CPB i2c bus labeled as i2c3.
- * The i2c1 of the CPB (as it is labeled) is not connected to j7200.
- */
-&main_i2c1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c1_pins_default>;
- clock-frequency = <400000>;
-
- exp3: gpio@20 {
- compatible = "ti,tca6408";
- reg = <0x20>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn",
- "UB926_LOCK", "UB926_PWR_SW_CNTRL",
- "UB926_TUNER_RESET", "UB926_GPIO_SPARE", "";
- };
-};
-
-&main_sdhci0 {
- /* eMMC */
- status = "okay";
- non-removable;
- ti,driver-strength-ohm = <50>;
- disable-wp;
-};
-
-&main_sdhci1 {
- /* SD card */
- status = "okay";
- pinctrl-0 = <&main_mmc1_pins_default>;
- pinctrl-names = "default";
- vmmc-supply = <&vdd_mmc1>;
- vqmmc-supply = <&vdd_sd_dv>;
- ti,driver-strength-ohm = <50>;
- disable-wp;
-};
-
-&serdes_ln_ctrl {
- idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>,
- <J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>;
-};
-
-&usb_serdes_mux {
- idle-states = <1>; /* USB0 to SERDES lane 3 */
-};
-
-&usbss0 {
- pinctrl-names = "default";
- pinctrl-0 = <&main_usbss0_pins_default>;
- ti,vbus-divider;
- ti,usb2-only;
-};
-
-&usb0 {
- dr_mode = "otg";
- maximum-speed = "high-speed";
-};
-
-&tscadc0 {
- adc {
- ti,adc-channels = <0 1 2 3 4 5 6 7>;
- };
-};
-
-&serdes_refclk {
- clock-frequency = <100000000>;
-};
-
-&serdes0 {
- serdes0_pcie_link: phy@0 {
- reg = <0>;
- cdns,num-lanes = <2>;
- #phy-cells = <0>;
- cdns,phy-type = <PHY_TYPE_PCIE>;
- resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
- };
-
- serdes0_qsgmii_link: phy@1 {
- reg = <2>;
- cdns,num-lanes = <1>;
- #phy-cells = <0>;
- cdns,phy-type = <PHY_TYPE_QSGMII>;
- resets = <&serdes_wiz0 3>;
- };
-};
-
-&pcie1_rc {
- reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
- phys = <&serdes0_pcie_link>;
- phy-names = "pcie-phy";
- num-lanes = <2>;
-};
-
-&pcie1_ep {
- phys = <&serdes0_pcie_link>;
- phy-names = "pcie-phy";
- num-lanes = <2>;
- status = "disabled";
-};
diff --git a/arch/arm/dts/k3-j7200-main.dtsi b/arch/arm/dts/k3-j7200-main.dtsi
deleted file mode 100644
index 264913f..0000000
--- a/arch/arm/dts/k3-j7200-main.dtsi
+++ /dev/null
@@ -1,1284 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for J7200 SoC Family Main Domain peripherals
- *
- * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-/ {
- serdes_refclk: serdes-refclk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- };
-};
-
-&cbass_main {
- msmc_ram: sram@70000000 {
- compatible = "mmio-sram";
- reg = <0x00 0x70000000 0x00 0x100000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00 0x00 0x70000000 0x100000>;
-
- atf-sram@0 {
- reg = <0x00 0x20000>;
- };
- };
-
- scm_conf: scm-conf@100000 {
- compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
- reg = <0x00 0x00100000 0x00 0x1c000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00 0x00 0x00100000 0x1c000>;
-
- serdes_ln_ctrl: mux-controller@4080 {
- compatible = "mmio-mux";
- #mux-control-cells = <1>;
- mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
- <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */
- };
-
- cpsw0_phy_gmii_sel: phy@4044 {
- compatible = "ti,j7200-cpsw5g-phy-gmii-sel";
- ti,qsgmii-main-ports = <1>;
- reg = <0x4044 0x10>;
- #phy-cells = <1>;
- };
-
- usb_serdes_mux: mux-controller@4000 {
- compatible = "mmio-mux";
- #mux-control-cells = <1>;
- mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
- };
- };
-
- gic500: interrupt-controller@1800000 {
- compatible = "arm,gic-v3";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
- <0x00 0x01900000 0x00 0x100000>, /* GICR */
- <0x00 0x6f000000 0x00 0x2000>, /* GICC */
- <0x00 0x6f010000 0x00 0x1000>, /* GICH */
- <0x00 0x6f020000 0x00 0x2000>; /* GICV */
-
- /* vcpumntirq: virtual CPU interface maintenance interrupt */
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
-
- gic_its: msi-controller@1820000 {
- compatible = "arm,gic-v3-its";
- reg = <0x00 0x01820000 0x00 0x10000>;
- socionext,synquacer-pre-its = <0x1000000 0x400000>;
- msi-controller;
- #msi-cells = <1>;
- };
- };
-
- main_gpio_intr: interrupt-controller@a00000 {
- compatible = "ti,sci-intr";
- reg = <0x00 0x00a00000 0x00 0x800>;
- ti,intr-trigger-type = <1>;
- interrupt-controller;
- interrupt-parent = <&gic500>;
- #interrupt-cells = <1>;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <131>;
- ti,interrupt-ranges = <8 392 56>;
- };
-
- main_navss: bus@30000000 {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
- ti,sci-dev-id = <199>;
- dma-coherent;
- dma-ranges;
-
- main_navss_intr: interrupt-controller@310e0000 {
- compatible = "ti,sci-intr";
- reg = <0x00 0x310e0000 0x00 0x4000>;
- ti,intr-trigger-type = <4>;
- interrupt-controller;
- interrupt-parent = <&gic500>;
- #interrupt-cells = <1>;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <213>;
- ti,interrupt-ranges = <0 64 64>,
- <64 448 64>,
- <128 672 64>;
- };
-
- main_udmass_inta: msi-controller@33d00000 {
- compatible = "ti,sci-inta";
- reg = <0x00 0x33d00000 0x00 0x100000>;
- interrupt-controller;
- #interrupt-cells = <0>;
- interrupt-parent = <&main_navss_intr>;
- msi-controller;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <209>;
- ti,interrupt-ranges = <0 0 256>;
- };
-
- secure_proxy_main: mailbox@32c00000 {
- compatible = "ti,am654-secure-proxy";
- #mbox-cells = <1>;
- reg-names = "target_data", "rt", "scfg";
- reg = <0x00 0x32c00000 0x00 0x100000>,
- <0x00 0x32400000 0x00 0x100000>,
- <0x00 0x32800000 0x00 0x100000>;
- interrupt-names = "rx_011";
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- hwspinlock: spinlock@30e00000 {
- compatible = "ti,am654-hwspinlock";
- reg = <0x00 0x30e00000 0x00 0x1000>;
- #hwlock-cells = <1>;
- };
-
- mailbox0_cluster0: mailbox@31f80000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f80000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox0_cluster1: mailbox@31f81000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f81000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox0_cluster2: mailbox@31f82000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f82000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox0_cluster3: mailbox@31f83000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f83000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox0_cluster4: mailbox@31f84000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f84000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox0_cluster5: mailbox@31f85000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f85000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox0_cluster6: mailbox@31f86000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f86000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox0_cluster7: mailbox@31f87000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f87000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox0_cluster8: mailbox@31f88000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f88000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox0_cluster9: mailbox@31f89000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f89000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox0_cluster10: mailbox@31f8a000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f8a000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox0_cluster11: mailbox@31f8b000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f8b000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- main_ringacc: ringacc@3c000000 {
- compatible = "ti,am654-navss-ringacc";
- reg = <0x00 0x3c000000 0x00 0x400000>,
- <0x00 0x38000000 0x00 0x400000>,
- <0x00 0x31120000 0x00 0x100>,
- <0x00 0x33000000 0x00 0x40000>,
- <0x00 0x31080000 0x00 0x40000>;
- reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
- ti,num-rings = <1024>;
- ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <211>;
- msi-parent = <&main_udmass_inta>;
- };
-
- main_udmap: dma-controller@31150000 {
- compatible = "ti,j721e-navss-main-udmap";
- reg = <0x00 0x31150000 0x00 0x100>,
- <0x00 0x34000000 0x00 0x100000>,
- <0x00 0x35000000 0x00 0x100000>;
- reg-names = "gcfg", "rchanrt", "tchanrt";
- msi-parent = <&main_udmass_inta>;
- #dma-cells = <1>;
-
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <212>;
- ti,ringacc = <&main_ringacc>;
-
- ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
- <0x0f>, /* TX_HCHAN */
- <0x10>; /* TX_UHCHAN */
- ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
- <0x0b>, /* RX_HCHAN */
- <0x0c>; /* RX_UHCHAN */
- ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
- };
-
- cpts@310d0000 {
- compatible = "ti,j721e-cpts";
- reg = <0x00 0x310d0000 0x00 0x400>;
- reg-names = "cpts";
- clocks = <&k3_clks 201 1>;
- clock-names = "cpts";
- interrupts-extended = <&main_navss_intr 391>;
- interrupt-names = "cpts";
- ti,cpts-periodic-outputs = <6>;
- ti,cpts-ext-ts-inputs = <8>;
- };
- };
-
- cpsw0: ethernet@c000000 {
- compatible = "ti,j7200-cpswxg-nuss";
- #address-cells = <2>;
- #size-cells = <2>;
- reg = <0x00 0xc000000 0x00 0x200000>;
- reg-names = "cpsw_nuss";
- ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>;
- clocks = <&k3_clks 19 33>;
- clock-names = "fck";
- power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>;
-
- dmas = <&main_udmap 0xca00>,
- <&main_udmap 0xca01>,
- <&main_udmap 0xca02>,
- <&main_udmap 0xca03>,
- <&main_udmap 0xca04>,
- <&main_udmap 0xca05>,
- <&main_udmap 0xca06>,
- <&main_udmap 0xca07>,
- <&main_udmap 0x4a00>;
- dma-names = "tx0", "tx1", "tx2", "tx3",
- "tx4", "tx5", "tx6", "tx7",
- "rx";
-
- status = "disabled";
-
- ethernet-ports {
- #address-cells = <1>;
- #size-cells = <0>;
- cpsw0_port1: port@1 {
- reg = <1>;
- ti,mac-only;
- label = "port1";
- status = "disabled";
- };
-
- cpsw0_port2: port@2 {
- reg = <2>;
- ti,mac-only;
- label = "port2";
- status = "disabled";
- };
-
- cpsw0_port3: port@3 {
- reg = <3>;
- ti,mac-only;
- label = "port3";
- status = "disabled";
- };
-
- cpsw0_port4: port@4 {
- reg = <4>;
- ti,mac-only;
- label = "port4";
- status = "disabled";
- };
- };
-
- cpsw5g_mdio: mdio@f00 {
- compatible = "ti,cpsw-mdio","ti,davinci_mdio";
- reg = <0x00 0xf00 0x00 0x100>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&k3_clks 19 33>;
- clock-names = "fck";
- bus_freq = <1000000>;
- status = "disabled";
- };
-
- cpts@3d000 {
- compatible = "ti,j721e-cpts";
- reg = <0x00 0x3d000 0x00 0x400>;
- clocks = <&k3_clks 19 16>;
- clock-names = "cpts";
- interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cpts";
- ti,cpts-ext-ts-inputs = <4>;
- ti,cpts-periodic-outputs = <2>;
- };
- };
-
- /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
- main_timerio_input: pinctrl@104200 {
- compatible = "pinctrl-single";
- reg = <0x0 0x104200 0x0 0x50>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x000001ff>;
- };
-
- /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
- main_timerio_output: pinctrl@104280 {
- compatible = "pinctrl-single";
- reg = <0x0 0x104280 0x0 0x20>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x0000001f>;
- };
-
- main_pmx0: pinctrl@11c000 {
- compatible = "pinctrl-single";
- /* Proxy 0 addressing */
- reg = <0x00 0x11c000 0x00 0x10c>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0xffffffff>;
- };
-
- main_pmx1: pinctrl@11c11c {
- compatible = "pinctrl-single";
- /* Proxy 0 addressing */
- reg = <0x00 0x11c11c 0x00 0xc>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0xffffffff>;
- };
-
- main_uart0: serial@2800000 {
- compatible = "ti,j721e-uart", "ti,am654-uart";
- reg = <0x00 0x02800000 0x00 0x100>;
- interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- current-speed = <115200>;
- power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 146 2>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart1: serial@2810000 {
- compatible = "ti,j721e-uart", "ti,am654-uart";
- reg = <0x00 0x02810000 0x00 0x100>;
- interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- current-speed = <115200>;
- power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 278 2>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart2: serial@2820000 {
- compatible = "ti,j721e-uart", "ti,am654-uart";
- reg = <0x00 0x02820000 0x00 0x100>;
- interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- current-speed = <115200>;
- power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 279 2>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart3: serial@2830000 {
- compatible = "ti,j721e-uart", "ti,am654-uart";
- reg = <0x00 0x02830000 0x00 0x100>;
- interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- current-speed = <115200>;
- power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 280 2>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart4: serial@2840000 {
- compatible = "ti,j721e-uart", "ti,am654-uart";
- reg = <0x00 0x02840000 0x00 0x100>;
- interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- current-speed = <115200>;
- power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 281 2>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart5: serial@2850000 {
- compatible = "ti,j721e-uart", "ti,am654-uart";
- reg = <0x00 0x02850000 0x00 0x100>;
- interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- current-speed = <115200>;
- power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 282 2>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart6: serial@2860000 {
- compatible = "ti,j721e-uart", "ti,am654-uart";
- reg = <0x00 0x02860000 0x00 0x100>;
- interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- current-speed = <115200>;
- power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 283 2>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart7: serial@2870000 {
- compatible = "ti,j721e-uart", "ti,am654-uart";
- reg = <0x00 0x02870000 0x00 0x100>;
- interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- current-speed = <115200>;
- power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 284 2>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart8: serial@2880000 {
- compatible = "ti,j721e-uart", "ti,am654-uart";
- reg = <0x00 0x02880000 0x00 0x100>;
- interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- current-speed = <115200>;
- power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 285 2>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart9: serial@2890000 {
- compatible = "ti,j721e-uart", "ti,am654-uart";
- reg = <0x00 0x02890000 0x00 0x100>;
- interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- current-speed = <115200>;
- power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 286 2>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_i2c0: i2c@2000000 {
- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x00 0x2000000 0x00 0x100>;
- interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "fck";
- clocks = <&k3_clks 187 1>;
- power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
- status = "disabled";
- };
-
- main_i2c1: i2c@2010000 {
- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x00 0x2010000 0x00 0x100>;
- interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "fck";
- clocks = <&k3_clks 188 1>;
- power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- main_i2c2: i2c@2020000 {
- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x00 0x2020000 0x00 0x100>;
- interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "fck";
- clocks = <&k3_clks 189 1>;
- power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- main_i2c3: i2c@2030000 {
- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x00 0x2030000 0x00 0x100>;
- interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "fck";
- clocks = <&k3_clks 190 1>;
- power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- main_i2c4: i2c@2040000 {
- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x00 0x2040000 0x00 0x100>;
- interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "fck";
- clocks = <&k3_clks 191 1>;
- power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- main_i2c5: i2c@2050000 {
- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x00 0x2050000 0x00 0x100>;
- interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "fck";
- clocks = <&k3_clks 192 1>;
- power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- main_i2c6: i2c@2060000 {
- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x00 0x2060000 0x00 0x100>;
- interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "fck";
- clocks = <&k3_clks 193 1>;
- power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- main_sdhci0: mmc@4f80000 {
- compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit";
- reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>;
- interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
- clock-names = "clk_ahb", "clk_xin";
- clocks = <&k3_clks 91 0>, <&k3_clks 91 3>;
- ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-mmc-hs = <0x0>;
- ti,otap-del-sel-ddr52 = <0x6>;
- ti,otap-del-sel-hs200 = <0x8>;
- ti,otap-del-sel-hs400 = <0x5>;
- ti,itap-del-sel-legacy = <0x10>;
- ti,itap-del-sel-mmc-hs = <0xa>;
- ti,strobe-sel = <0x77>;
- ti,clkbuf-sel = <0x7>;
- ti,trm-icp = <0x8>;
- bus-width = <8>;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- mmc-hs400-1_8v;
- dma-coherent;
- status = "disabled";
- };
-
- main_sdhci1: mmc@4fb0000 {
- compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit";
- reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
- clock-names = "clk_ahb", "clk_xin";
- clocks = <&k3_clks 92 1>, <&k3_clks 92 2>;
- ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-sd-hs = <0x0>;
- ti,otap-del-sel-sdr12 = <0xf>;
- ti,otap-del-sel-sdr25 = <0xf>;
- ti,otap-del-sel-sdr50 = <0xc>;
- ti,otap-del-sel-sdr104 = <0x5>;
- ti,otap-del-sel-ddr50 = <0xc>;
- ti,itap-del-sel-legacy = <0x0>;
- ti,itap-del-sel-sd-hs = <0x0>;
- ti,itap-del-sel-sdr12 = <0x0>;
- ti,itap-del-sel-sdr25 = <0x0>;
- ti,clkbuf-sel = <0x7>;
- ti,trm-icp = <0x8>;
- dma-coherent;
- status = "disabled";
- };
-
- serdes_wiz0: wiz@5060000 {
- compatible = "ti,j721e-wiz-10g";
- #address-cells = <1>;
- #size-cells = <1>;
- power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>;
- clock-names = "fck", "core_ref_clk", "ext_ref_clk";
- num-lanes = <4>;
- #reset-cells = <1>;
- ranges = <0x5060000 0x0 0x5060000 0x10000>;
-
- assigned-clocks = <&k3_clks 292 85>;
- assigned-clock-parents = <&k3_clks 292 89>;
-
- wiz0_pll0_refclk: pll0-refclk {
- clocks = <&k3_clks 292 85>, <&serdes_refclk>;
- clock-output-names = "wiz0_pll0_refclk";
- #clock-cells = <0>;
- assigned-clocks = <&wiz0_pll0_refclk>;
- assigned-clock-parents = <&k3_clks 292 85>;
- };
-
- wiz0_pll1_refclk: pll1-refclk {
- clocks = <&k3_clks 292 85>, <&serdes_refclk>;
- clock-output-names = "wiz0_pll1_refclk";
- #clock-cells = <0>;
- assigned-clocks = <&wiz0_pll1_refclk>;
- assigned-clock-parents = <&k3_clks 292 85>;
- };
-
- wiz0_refclk_dig: refclk-dig {
- clocks = <&k3_clks 292 85>, <&serdes_refclk>;
- clock-output-names = "wiz0_refclk_dig";
- #clock-cells = <0>;
- assigned-clocks = <&wiz0_refclk_dig>;
- assigned-clock-parents = <&k3_clks 292 85>;
- };
-
- wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
- clocks = <&wiz0_refclk_dig>;
- #clock-cells = <0>;
- };
-
- serdes0: serdes@5060000 {
- compatible = "ti,j721e-serdes-10g";
- reg = <0x05060000 0x00010000>;
- reg-names = "torrent_phy";
- resets = <&serdes_wiz0 0>;
- reset-names = "torrent_reset";
- clocks = <&wiz0_pll0_refclk>;
- clock-names = "refclk";
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-
- pcie1_rc: pcie@2910000 {
- compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
- reg = <0x00 0x02910000 0x00 0x1000>,
- <0x00 0x02917000 0x00 0x400>,
- <0x00 0x0d800000 0x00 0x00800000>,
- <0x00 0x18000000 0x00 0x00001000>;
- reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
- interrupt-names = "link_state";
- interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
- device_type = "pci";
- ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
- max-link-speed = <3>;
- num-lanes = <4>;
- power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 240 6>;
- clock-names = "fck";
- #address-cells = <3>;
- #size-cells = <2>;
- bus-range = <0x0 0xff>;
- cdns,no-bar-match-nbits = <64>;
- vendor-id = <0x104c>;
- device-id = <0xb00f>;
- msi-map = <0x0 &gic_its 0x0 0x10000>;
- dma-coherent;
- ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
- <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
- dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
- };
-
- pcie1_ep: pcie-ep@2910000 {
- compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep";
- reg = <0x00 0x02910000 0x00 0x1000>,
- <0x00 0x02917000 0x00 0x400>,
- <0x00 0x0d800000 0x00 0x00800000>,
- <0x00 0x18000000 0x00 0x08000000>;
- reg-names = "intd_cfg", "user_cfg", "reg", "mem";
- interrupt-names = "link_state";
- interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
- ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
- max-link-speed = <3>;
- num-lanes = <4>;
- power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 240 6>;
- clock-names = "fck";
- max-functions = /bits/ 8 <6>;
- max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
- dma-coherent;
- };
-
- usbss0: cdns-usb@4104000 {
- compatible = "ti,j721e-usb";
- reg = <0x00 0x4104000 0x00 0x100>;
- dma-coherent;
- power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 288 12>, <&k3_clks 288 3>;
- clock-names = "ref", "lpm";
- assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */
- assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- usb0: usb@6000000 {
- compatible = "cdns,usb3";
- reg = <0x00 0x6000000 0x00 0x10000>,
- <0x00 0x6010000 0x00 0x10000>,
- <0x00 0x6020000 0x00 0x10000>;
- reg-names = "otg", "xhci", "dev";
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
- <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
- <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
- interrupt-names = "host",
- "peripheral",
- "otg";
- maximum-speed = "super-speed";
- dr_mode = "otg";
- cdns,phyrst-a-enable;
- };
- };
-
- main_gpio0: gpio@600000 {
- compatible = "ti,j721e-gpio", "ti,keystone-gpio";
- reg = <0x00 0x00600000 0x00 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&main_gpio_intr>;
- interrupts = <145>, <146>, <147>, <148>,
- <149>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <69>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 105 0>;
- clock-names = "gpio";
- status = "disabled";
- };
-
- main_gpio2: gpio@610000 {
- compatible = "ti,j721e-gpio", "ti,keystone-gpio";
- reg = <0x00 0x00610000 0x00 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&main_gpio_intr>;
- interrupts = <154>, <155>, <156>, <157>,
- <158>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <69>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 107 0>;
- clock-names = "gpio";
- status = "disabled";
- };
-
- main_gpio4: gpio@620000 {
- compatible = "ti,j721e-gpio", "ti,keystone-gpio";
- reg = <0x00 0x00620000 0x00 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&main_gpio_intr>;
- interrupts = <163>, <164>, <165>, <166>,
- <167>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <69>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 109 0>;
- clock-names = "gpio";
- status = "disabled";
- };
-
- main_gpio6: gpio@630000 {
- compatible = "ti,j721e-gpio", "ti,keystone-gpio";
- reg = <0x00 0x00630000 0x00 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&main_gpio_intr>;
- interrupts = <172>, <173>, <174>, <175>,
- <176>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <69>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 111 0>;
- clock-names = "gpio";
- status = "disabled";
- };
-
- main_spi0: spi@2100000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x02100000 0x00 0x400>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 266 1>;
- status = "disabled";
- };
-
- main_spi1: spi@2110000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x02110000 0x00 0x400>;
- interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 267 1>;
- status = "disabled";
- };
-
- main_spi2: spi@2120000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x02120000 0x00 0x400>;
- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 268 1>;
- status = "disabled";
- };
-
- main_spi3: spi@2130000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x02130000 0x00 0x400>;
- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 269 1>;
- status = "disabled";
- };
-
- main_spi4: spi@2140000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x02140000 0x00 0x400>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 270 1>;
- status = "disabled";
- };
-
- main_spi5: spi@2150000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x02150000 0x00 0x400>;
- interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 271 1>;
- status = "disabled";
- };
-
- main_spi6: spi@2160000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x02160000 0x00 0x400>;
- interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 272 1>;
- status = "disabled";
- };
-
- main_spi7: spi@2170000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x02170000 0x00 0x400>;
- interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 273 1>;
- status = "disabled";
- };
-
- watchdog0: watchdog@2200000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x0 0x2200000 0x0 0x100>;
- clocks = <&k3_clks 252 1>;
- power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 252 1>;
- assigned-clock-parents = <&k3_clks 252 5>;
- };
-
- watchdog1: watchdog@2210000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x0 0x2210000 0x0 0x100>;
- clocks = <&k3_clks 253 1>;
- power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 253 1>;
- assigned-clock-parents = <&k3_clks 253 5>;
- };
-
- main_timer0: timer@2400000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2400000 0x00 0x400>;
- interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 49 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 49 1>;
- assigned-clock-parents = <&k3_clks 49 2>;
- power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer1: timer@2410000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2410000 0x00 0x400>;
- interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 50 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 50 1>, <&k3_clks 313 0>;
- assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 313 1>;
- power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer2: timer@2420000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2420000 0x00 0x400>;
- interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 51 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 51 1>;
- assigned-clock-parents = <&k3_clks 51 2>;
- power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer3: timer@2430000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2430000 0x00 0x400>;
- interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 52 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 52 1>, <&k3_clks 314 0>;
- assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 314 1>;
- power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer4: timer@2440000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2440000 0x00 0x400>;
- interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 53 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 53 1>;
- assigned-clock-parents = <&k3_clks 53 2>;
- power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer5: timer@2450000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2450000 0x00 0x400>;
- interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 54 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 54 1>, <&k3_clks 315 0>;
- assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 315 1>;
- power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer6: timer@2460000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2460000 0x00 0x400>;
- interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 55 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 55 1>;
- assigned-clock-parents = <&k3_clks 55 2>;
- power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer7: timer@2470000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2470000 0x00 0x400>;
- interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 57 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 57 1>, <&k3_clks 316 0>;
- assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 316 1>;
- power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer8: timer@2480000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2480000 0x00 0x400>;
- interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 58 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 58 1>;
- assigned-clock-parents = <&k3_clks 58 2>;
- power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer9: timer@2490000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2490000 0x00 0x400>;
- interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 59 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 59 1>, <&k3_clks 317 0>;
- assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 317 1>;
- power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer10: timer@24a0000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x24a0000 0x00 0x400>;
- interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 60 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 60 1>;
- assigned-clock-parents = <&k3_clks 60 2>;
- power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer11: timer@24b0000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x24b0000 0x00 0x400>;
- interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 62 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 62 1>, <&k3_clks 318 0>;
- assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 318 1>;
- power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer12: timer@24c0000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x24c0000 0x00 0x400>;
- interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 63 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 63 1>;
- assigned-clock-parents = <&k3_clks 63 2>;
- power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer13: timer@24d0000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x24d0000 0x00 0x400>;
- interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 64 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 64 1>, <&k3_clks 319 0>;
- assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 319 1>;
- power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer14: timer@24e0000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x24e0000 0x00 0x400>;
- interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 65 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 65 1>;
- assigned-clock-parents = <&k3_clks 65 2>;
- power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer15: timer@24f0000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x24f0000 0x00 0x400>;
- interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 66 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 66 1>, <&k3_clks 320 0>;
- assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 320 1>;
- power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer16: timer@2500000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2500000 0x00 0x400>;
- interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 67 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 67 1>;
- assigned-clock-parents = <&k3_clks 67 2>;
- power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer17: timer@2510000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2510000 0x00 0x400>;
- interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 68 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 68 1>, <&k3_clks 321 0>;
- assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 321 1>;
- power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer18: timer@2520000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2520000 0x00 0x400>;
- interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 69 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 69 1>;
- assigned-clock-parents = <&k3_clks 69 2>;
- power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer19: timer@2530000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2530000 0x00 0x400>;
- interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 70 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 70 1>, <&k3_clks 322 0>;
- assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 322 1>;
- power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_r5fss0: r5fss@5c00000 {
- compatible = "ti,j7200-r5fss";
- ti,cluster-mode = <1>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
- <0x5d00000 0x00 0x5d00000 0x20000>;
- power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
-
- main_r5fss0_core0: r5f@5c00000 {
- compatible = "ti,j7200-r5f";
- reg = <0x5c00000 0x00010000>,
- <0x5c10000 0x00010000>;
- reg-names = "atcm", "btcm";
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <245>;
- ti,sci-proc-ids = <0x06 0xff>;
- resets = <&k3_reset 245 1>;
- firmware-name = "j7200-main-r5f0_0-fw";
- ti,atcm-enable = <1>;
- ti,btcm-enable = <1>;
- ti,loczrama = <1>;
- };
-
- main_r5fss0_core1: r5f@5d00000 {
- compatible = "ti,j7200-r5f";
- reg = <0x5d00000 0x00008000>,
- <0x5d10000 0x00008000>;
- reg-names = "atcm", "btcm";
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <246>;
- ti,sci-proc-ids = <0x07 0xff>;
- resets = <&k3_reset 246 1>;
- firmware-name = "j7200-main-r5f0_1-fw";
- ti,atcm-enable = <1>;
- ti,btcm-enable = <1>;
- ti,loczrama = <1>;
- };
- };
-
- main_esm: esm@700000 {
- compatible = "ti,j721e-esm";
- reg = <0x0 0x700000 0x0 0x1000>;
- ti,esm-pins = <656>, <657>;
- };
-};
diff --git a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
deleted file mode 100644
index 3fc588b..0000000
--- a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
+++ /dev/null
@@ -1,647 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals
- *
- * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-&cbass_mcu_wakeup {
- dmsc: system-controller@44083000 {
- compatible = "ti,k2g-sci";
- ti,host-id = <12>;
-
- mbox-names = "rx", "tx";
-
- mboxes = <&secure_proxy_main 11>,
- <&secure_proxy_main 13>;
-
- reg-names = "debug_messages";
- reg = <0x00 0x44083000 0x00 0x1000>;
-
- k3_pds: power-controller {
- compatible = "ti,sci-pm-domain";
- #power-domain-cells = <2>;
- };
-
- k3_clks: clock-controller {
- compatible = "ti,k2g-sci-clk";
- #clock-cells = <2>;
- };
-
- k3_reset: reset-controller {
- compatible = "ti,sci-reset";
- #reset-cells = <2>;
- };
- };
-
- mcu_timer0: timer@40400000 {
- status = "reserved";
- compatible = "ti,am654-timer";
- reg = <0x00 0x40400000 0x00 0x400>;
- interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 35 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 35 1>;
- assigned-clock-parents = <&k3_clks 35 2>;
- power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- mcu_timer1: timer@40410000 {
- status = "reserved";
- compatible = "ti,am654-timer";
- reg = <0x00 0x40410000 0x00 0x400>;
- interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 71 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 71 1>, <&k3_clks 308 0>;
- assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 308 1>;
- power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- mcu_timer2: timer@40420000 {
- status = "reserved";
- compatible = "ti,am654-timer";
- reg = <0x00 0x40420000 0x00 0x400>;
- interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 72 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 72 1>;
- assigned-clock-parents = <&k3_clks 72 2>;
- power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- mcu_timer3: timer@40430000 {
- status = "reserved";
- compatible = "ti,am654-timer";
- reg = <0x00 0x40430000 0x00 0x400>;
- interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 73 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 73 1>, <&k3_clks 309 0>;
- assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 309 1>;
- power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- mcu_timer4: timer@40440000 {
- status = "reserved";
- compatible = "ti,am654-timer";
- reg = <0x00 0x40440000 0x00 0x400>;
- interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 74 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 74 1>;
- assigned-clock-parents = <&k3_clks 74 2>;
- power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- mcu_timer5: timer@40450000 {
- status = "reserved";
- compatible = "ti,am654-timer";
- reg = <0x00 0x40450000 0x00 0x400>;
- interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 75 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 75 1>, <&k3_clks 310 0>;
- assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 310 1>;
- power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- mcu_timer6: timer@40460000 {
- status = "reserved";
- compatible = "ti,am654-timer";
- reg = <0x00 0x40460000 0x00 0x400>;
- interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 76 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 76 1>;
- assigned-clock-parents = <&k3_clks 76 2>;
- power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- mcu_timer7: timer@40470000 {
- status = "reserved";
- compatible = "ti,am654-timer";
- reg = <0x00 0x40470000 0x00 0x400>;
- interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 77 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 77 1>, <&k3_clks 311 0>;
- assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 311 1>;
- power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- mcu_timer8: timer@40480000 {
- status = "reserved";
- compatible = "ti,am654-timer";
- reg = <0x00 0x40480000 0x00 0x400>;
- interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 78 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 78 1>;
- assigned-clock-parents = <&k3_clks 78 2>;
- power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- mcu_timer9: timer@40490000 {
- status = "reserved";
- compatible = "ti,am654-timer";
- reg = <0x00 0x40490000 0x00 0x400>;
- interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 79 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 79 1>, <&k3_clks 312 0>;
- assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 312 1>;
- power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- mcu_conf: syscon@40f00000 {
- compatible = "syscon", "simple-mfd";
- reg = <0x00 0x40f00000 0x00 0x20000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00 0x00 0x40f00000 0x20000>;
-
- phy_gmii_sel: phy@4040 {
- compatible = "ti,am654-phy-gmii-sel";
- reg = <0x4040 0x4>;
- #phy-cells = <1>;
- };
- };
-
- chipid@43000014 {
- compatible = "ti,am654-chipid";
- reg = <0x00 0x43000014 0x00 0x4>;
- };
-
- /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
- mcu_timerio_input: pinctrl@40f04200 {
- compatible = "pinctrl-single";
- reg = <0x0 0x40f04200 0x0 0x28>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x0000000F>;
- status = "reserved";
- };
-
- /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
- mcu_timerio_output: pinctrl@40f04280 {
- compatible = "pinctrl-single";
- reg = <0x0 0x40f04280 0x0 0x28>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x0000000F>;
- status = "reserved";
- };
-
- wkup_pmx0: pinctrl@4301c000 {
- compatible = "pinctrl-single";
- /* Proxy 0 addressing */
- reg = <0x00 0x4301c000 0x00 0x34>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0xffffffff>;
- };
-
- wkup_pmx1: pinctrl@4301c038 {
- compatible = "pinctrl-single";
- /* Proxy 0 addressing */
- reg = <0x00 0x4301c038 0x00 0x8>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0xffffffff>;
- };
-
- wkup_pmx2: pinctrl@4301c068 {
- compatible = "pinctrl-single";
- /* Proxy 0 addressing */
- reg = <0x00 0x4301c068 0x00 0xec>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0xffffffff>;
- };
-
- wkup_pmx3: pinctrl@4301c174 {
- compatible = "pinctrl-single";
- /* Proxy 0 addressing */
- reg = <0x00 0x4301c174 0x00 0x20>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0xffffffff>;
- };
-
- mcu_ram: sram@41c00000 {
- compatible = "mmio-sram";
- reg = <0x00 0x41c00000 0x00 0x100000>;
- ranges = <0x00 0x00 0x41c00000 0x100000>;
- #address-cells = <1>;
- #size-cells = <1>;
- };
-
- wkup_uart0: serial@42300000 {
- compatible = "ti,j721e-uart", "ti,am654-uart";
- reg = <0x00 0x42300000 0x00 0x100>;
- interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- current-speed = <115200>;
- power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 287 2>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- mcu_uart0: serial@40a00000 {
- compatible = "ti,j721e-uart", "ti,am654-uart";
- reg = <0x00 0x40a00000 0x00 0x100>;
- interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <96000000>;
- current-speed = <115200>;
- power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 149 2>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- wkup_gpio_intr: interrupt-controller@42200000 {
- compatible = "ti,sci-intr";
- reg = <0x00 0x42200000 0x00 0x400>;
- ti,intr-trigger-type = <1>;
- interrupt-controller;
- interrupt-parent = <&gic500>;
- #interrupt-cells = <1>;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <137>;
- ti,interrupt-ranges = <16 960 16>;
- };
-
- wkup_gpio0: gpio@42110000 {
- compatible = "ti,j721e-gpio", "ti,keystone-gpio";
- reg = <0x00 0x42110000 0x00 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&wkup_gpio_intr>;
- interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <85>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 113 0>;
- clock-names = "gpio";
- status = "disabled";
- };
-
- wkup_gpio1: gpio@42100000 {
- compatible = "ti,j721e-gpio", "ti,keystone-gpio";
- reg = <0x00 0x42100000 0x00 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&wkup_gpio_intr>;
- interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <85>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 114 0>;
- clock-names = "gpio";
- status = "disabled";
- };
-
- mcu_navss: bus@28380000 {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
- dma-coherent;
- dma-ranges;
- ti,sci-dev-id = <232>;
-
- mcu_ringacc: ringacc@2b800000 {
- compatible = "ti,am654-navss-ringacc";
- reg = <0x00 0x2b800000 0x00 0x400000>,
- <0x00 0x2b000000 0x00 0x400000>,
- <0x00 0x28590000 0x00 0x100>,
- <0x00 0x2a500000 0x00 0x40000>,
- <0x00 0x28440000 0x00 0x40000>;
- reg-names = "rt", "fifos", "proxy_gcfg",
- "proxy_target", "cfg";
- ti,num-rings = <286>;
- ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <235>;
- msi-parent = <&main_udmass_inta>;
- };
-
- mcu_udmap: dma-controller@285c0000 {
- compatible = "ti,j721e-navss-mcu-udmap";
- reg = <0x00 0x285c0000 0x00 0x100>,
- <0x00 0x2a800000 0x00 0x40000>,
- <0x00 0x2aa00000 0x00 0x40000>;
- reg-names = "gcfg", "rchanrt", "tchanrt";
- msi-parent = <&main_udmass_inta>;
- #dma-cells = <1>;
-
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <236>;
- ti,ringacc = <&mcu_ringacc>;
-
- ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
- <0x0f>; /* TX_HCHAN */
- ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
- <0x0b>; /* RX_HCHAN */
- ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
- };
- };
-
- secure_proxy_mcu: mailbox@2a480000 {
- compatible = "ti,am654-secure-proxy";
- #mbox-cells = <1>;
- reg-names = "target_data", "rt", "scfg";
- reg = <0x0 0x2a480000 0x0 0x80000>,
- <0x0 0x2a380000 0x0 0x80000>,
- <0x0 0x2a400000 0x0 0x80000>;
- /*
- * Marked Disabled:
- * Node is incomplete as it is meant for bootloaders and
- * firmware on non-MPU processors
- */
- status = "disabled";
- };
-
- mcu_cpsw: ethernet@46000000 {
- compatible = "ti,j721e-cpsw-nuss";
- #address-cells = <2>;
- #size-cells = <2>;
- reg = <0x00 0x46000000 0x00 0x200000>;
- reg-names = "cpsw_nuss";
- ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>;
- dma-coherent;
- clocks = <&k3_clks 18 21>;
- clock-names = "fck";
- power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
-
- dmas = <&mcu_udmap 0xf000>,
- <&mcu_udmap 0xf001>,
- <&mcu_udmap 0xf002>,
- <&mcu_udmap 0xf003>,
- <&mcu_udmap 0xf004>,
- <&mcu_udmap 0xf005>,
- <&mcu_udmap 0xf006>,
- <&mcu_udmap 0xf007>,
- <&mcu_udmap 0x7000>;
- dma-names = "tx0", "tx1", "tx2", "tx3",
- "tx4", "tx5", "tx6", "tx7",
- "rx";
-
- ethernet-ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpsw_port1: port@1 {
- reg = <1>;
- ti,mac-only;
- label = "port1";
- ti,syscon-efuse = <&mcu_conf 0x200>;
- phys = <&phy_gmii_sel 1>;
- };
- };
-
- davinci_mdio: mdio@f00 {
- compatible = "ti,cpsw-mdio","ti,davinci_mdio";
- reg = <0x00 0xf00 0x00 0x100>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&k3_clks 18 21>;
- clock-names = "fck";
- bus_freq = <1000000>;
- };
-
- cpts@3d000 {
- compatible = "ti,am65-cpts";
- reg = <0x00 0x3d000 0x00 0x400>;
- clocks = <&k3_clks 18 2>;
- clock-names = "cpts";
- interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cpts";
- ti,cpts-ext-ts-inputs = <4>;
- ti,cpts-periodic-outputs = <2>;
- };
- };
-
- mcu_i2c0: i2c@40b00000 {
- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x00 0x40b00000 0x00 0x100>;
- interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "fck";
- clocks = <&k3_clks 194 1>;
- power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- mcu_i2c1: i2c@40b10000 {
- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x00 0x40b10000 0x00 0x100>;
- interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "fck";
- clocks = <&k3_clks 195 1>;
- power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- wkup_i2c0: i2c@42120000 {
- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x00 0x42120000 0x00 0x100>;
- interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "fck";
- clocks = <&k3_clks 197 1>;
- power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
- status = "disabled";
- };
-
- mcu_spi0: spi@40300000 {
- compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
- reg = <0x00 0x040300000 0x00 0x400>;
- interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 274 0>;
- status = "disabled";
- };
-
- mcu_spi1: spi@40310000 {
- compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
- reg = <0x00 0x040310000 0x00 0x400>;
- interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 275 0>;
- status = "disabled";
- };
-
- mcu_spi2: spi@40320000 {
- compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
- reg = <0x00 0x040320000 0x00 0x400>;
- interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 276 0>;
- status = "disabled";
- };
-
- fss: syscon@47000000 {
- compatible = "syscon", "simple-mfd";
- reg = <0x00 0x47000000 0x00 0x100>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- hbmc_mux: hbmc-mux {
- compatible = "mmio-mux";
- #mux-control-cells = <1>;
- mux-reg-masks = <0x4 0x2>; /* HBMC select */
- };
-
- hbmc: hyperbus@47034000 {
- compatible = "ti,am654-hbmc";
- reg = <0x00 0x47034000 0x00 0x100>,
- <0x05 0x00000000 0x01 0x0000000>;
- power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 102 0>;
- assigned-clocks = <&k3_clks 102 5>;
- assigned-clock-rates = <333333333>;
- #address-cells = <2>;
- #size-cells = <1>;
- mux-controls = <&hbmc_mux 0>;
- };
-
- ospi0: spi@47040000 {
- compatible = "ti,am654-ospi", "cdns,qspi-nor";
- reg = <0x0 0x47040000 0x0 0x100>,
- <0x5 0x00000000 0x1 0x0000000>;
- interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
- cdns,fifo-depth = <256>;
- cdns,fifo-width = <4>;
- cdns,trigger-address = <0x0>;
- clocks = <&k3_clks 103 0>;
- assigned-clocks = <&k3_clks 103 0>;
- assigned-clock-parents = <&k3_clks 103 2>;
- assigned-clock-rates = <166666666>;
- power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
- };
-
- tscadc0: tscadc@40200000 {
- compatible = "ti,am3359-tscadc";
- reg = <0x00 0x40200000 0x00 0x1000>;
- interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 0 1>;
- assigned-clocks = <&k3_clks 0 3>;
- assigned-clock-rates = <60000000>;
- clock-names = "fck";
- dmas = <&main_udmap 0x7400>,
- <&main_udmap 0x7401>;
- dma-names = "fifo0", "fifo1";
-
- adc {
- #io-channel-cells = <1>;
- compatible = "ti,am3359-adc";
- };
- };
-
- mcu_r5fss0: r5fss@41000000 {
- compatible = "ti,j7200-r5fss";
- ti,cluster-mode = <1>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x41000000 0x00 0x41000000 0x20000>,
- <0x41400000 0x00 0x41400000 0x20000>;
- power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
-
- mcu_r5fss0_core0: r5f@41000000 {
- compatible = "ti,j7200-r5f";
- reg = <0x41000000 0x00010000>,
- <0x41010000 0x00010000>;
- reg-names = "atcm", "btcm";
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <250>;
- ti,sci-proc-ids = <0x01 0xff>;
- resets = <&k3_reset 250 1>;
- firmware-name = "j7200-mcu-r5f0_0-fw";
- ti,atcm-enable = <1>;
- ti,btcm-enable = <1>;
- ti,loczrama = <1>;
- };
-
- mcu_r5fss0_core1: r5f@41400000 {
- compatible = "ti,j7200-r5f";
- reg = <0x41400000 0x00008000>,
- <0x41410000 0x00008000>;
- reg-names = "atcm", "btcm";
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <251>;
- ti,sci-proc-ids = <0x02 0xff>;
- resets = <&k3_reset 251 1>;
- firmware-name = "j7200-mcu-r5f0_1-fw";
- ti,atcm-enable = <1>;
- ti,btcm-enable = <1>;
- ti,loczrama = <1>;
- };
- };
-
- mcu_crypto: crypto@40900000 {
- compatible = "ti,j721e-sa2ul";
- reg = <0x00 0x40900000 0x00 0x1200>;
- power-domains = <&k3_pds 265 TI_SCI_PD_SHARED>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
- dmas = <&mcu_udmap 0xf501>, <&mcu_udmap 0x7502>,
- <&mcu_udmap 0x7503>;
- dma-names = "tx", "rx1", "rx2";
-
- rng: rng@40910000 {
- compatible = "inside-secure,safexcel-eip76";
- reg = <0x00 0x40910000 0x00 0x7d>;
- interrupts = <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled"; /* Used by OP-TEE */
- };
- };
-
- wkup_vtm0: temperature-sensor@42040000 {
- compatible = "ti,j7200-vtm";
- reg = <0x00 0x42040000 0x00 0x350>,
- <0x00 0x42050000 0x00 0x350>;
- power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
- #thermal-sensor-cells = <1>;
- };
-
- mcu_esm: esm@40800000 {
- compatible = "ti,j721e-esm";
- reg = <0x00 0x40800000 0x00 0x1000>;
- ti,esm-pins = <95>;
- bootph-pre-ram;
- };
-};
diff --git a/arch/arm/dts/k3-j7200-som-p0.dtsi b/arch/arm/dts/k3-j7200-som-p0.dtsi
deleted file mode 100644
index 5a300d4..0000000
--- a/arch/arm/dts/k3-j7200-som-p0.dtsi
+++ /dev/null
@@ -1,327 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-/dts-v1/;
-
-#include "k3-j7200.dtsi"
-
-/ {
- memory@80000000 {
- device_type = "memory";
- /* 4G RAM */
- reg = <0x00 0x80000000 0x00 0x80000000>,
- <0x08 0x80000000 0x00 0x80000000>;
- };
-
- reserved_memory: reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- secure_ddr: optee@9e800000 {
- reg = <0x00 0x9e800000 0x00 0x01800000>;
- alignment = <0x1000>;
- no-map;
- };
-
- mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa0000000 0x00 0x100000>;
- no-map;
- };
-
- mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa0100000 0x00 0xf00000>;
- no-map;
- };
-
- mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa1000000 0x00 0x100000>;
- no-map;
- };
-
- mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa1100000 0x00 0xf00000>;
- no-map;
- };
-
- main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa2000000 0x00 0x100000>;
- no-map;
- };
-
- main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa2100000 0x00 0xf00000>;
- no-map;
- };
-
- main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa3000000 0x00 0x100000>;
- no-map;
- };
-
- main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa3100000 0x00 0xf00000>;
- no-map;
- };
-
- rtos_ipc_memory_region: ipc-memories@a4000000 {
- reg = <0x00 0xa4000000 0x00 0x00800000>;
- alignment = <0x1000>;
- no-map;
- };
- };
-};
-
-&wkup_pmx0 {
- mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
- J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
- J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (D6) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
- J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (D7) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
- J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (B7) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
- J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D8) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
- J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (C7) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
- J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (C5) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
- J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (A5) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
- J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (A6) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
- J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
- J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
- J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
- >;
- };
-
- mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
- J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
- J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */
- J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */
- J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */
- J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */
- J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */
- J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */
- J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */
- J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */
- J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */
- >;
- };
-};
-
-&wkup_pmx2 {
- wkup_i2c0_pins_default: wkup-i2c0-default-pins {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0x98, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */
- J721E_WKUP_IOPAD(0x9c, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */
- >;
- };
-};
-
-&main_pmx0 {
- main_i2c0_pins_default: main-i2c0-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
- J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
- >;
- };
-};
-
-&hbmc {
- /* OSPI and HBMC are muxed inside FSS, Bootloader will enable
- * appropriate node based on board detection
- */
- status = "disabled";
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
- ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */
- <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */
-
- flash@0,0 {
- compatible = "cypress,hyperflash", "cfi-flash";
- reg = <0x00 0x00 0x4000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "hbmc.tiboot3";
- reg = <0x0 0x100000>;
- };
-
- partition@100000 {
- label = "hbmc.tispl";
- reg = <0x100000 0x200000>;
- };
-
- partition@300000 {
- label = "hbmc.u-boot";
- reg = <0x300000 0x400000>;
- };
-
- partition@700000 {
- label = "hbmc.env";
- reg = <0x700000 0x40000>;
- };
-
- partition@800000 {
- label = "hbmc.rootfs";
- reg = <0x800000 0x3800000>;
- };
- };
- };
-};
-
-&mailbox0_cluster0 {
- status = "okay";
- interrupts = <436>;
-
- mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
- ti,mbox-rx = <0 0 0>;
- ti,mbox-tx = <1 0 0>;
- };
-
- mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
- ti,mbox-rx = <2 0 0>;
- ti,mbox-tx = <3 0 0>;
- };
-};
-
-&mailbox0_cluster1 {
- status = "okay";
- interrupts = <432>;
-
- mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
- ti,mbox-rx = <0 0 0>;
- ti,mbox-tx = <1 0 0>;
- };
-
- mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
- ti,mbox-rx = <2 0 0>;
- ti,mbox-tx = <3 0 0>;
- };
-};
-
-&mcu_r5fss0_core0 {
- mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
- memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
- <&mcu_r5fss0_core0_memory_region>;
-};
-
-&mcu_r5fss0_core1 {
- mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
- memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
- <&mcu_r5fss0_core1_memory_region>;
-};
-
-&main_r5fss0_core0 {
- mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
- memory-region = <&main_r5fss0_core0_dma_memory_region>,
- <&main_r5fss0_core0_memory_region>;
-};
-
-&main_r5fss0_core1 {
- mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
- memory-region = <&main_r5fss0_core1_dma_memory_region>,
- <&main_r5fss0_core1_memory_region>;
-};
-
-&main_i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c0_pins_default>;
- clock-frequency = <400000>;
-
- exp_som: gpio@21 {
- compatible = "ti,tca6408";
- reg = <0x21>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0",
- "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1",
- "UART/LIN_MUX_SEL", "TRC_D17/AUDIO_REFCLK_SEL",
- "GPIO_LIN_EN", "CAN_STB";
- };
-};
-
-&wkup_i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_i2c0_pins_default>;
- clock-frequency = <400000>;
-
- eeprom@50 {
- compatible = "atmel,24c256";
- reg = <0x50>;
- };
-};
-
-&ospi0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0x0>;
- spi-tx-bus-width = <8>;
- spi-rx-bus-width = <8>;
- spi-max-frequency = <25000000>;
- cdns,tshsl-ns = <60>;
- cdns,tsd2d-ns = <60>;
- cdns,tchsh-ns = <60>;
- cdns,tslch-ns = <60>;
- cdns,read-delay = <4>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "ospi.tiboot3";
- reg = <0x0 0x100000>;
- };
-
- partition@100000 {
- label = "ospi.tispl";
- reg = <0x100000 0x200000>;
- };
-
- partition@300000 {
- label = "ospi.u-boot";
- reg = <0x300000 0x400000>;
- };
-
- partition@700000 {
- label = "ospi.env";
- reg = <0x700000 0x40000>;
- };
-
- partition@740000 {
- label = "ospi.env.backup";
- reg = <0x740000 0x40000>;
- };
-
- partition@800000 {
- label = "ospi.rootfs";
- reg = <0x800000 0x37c0000>;
- };
-
- partition@3fc0000 {
- label = "ospi.phypattern";
- reg = <0x3fc0000 0x40000>;
- };
- };
- };
-};
diff --git a/arch/arm/dts/k3-j7200-thermal.dtsi b/arch/arm/dts/k3-j7200-thermal.dtsi
deleted file mode 100644
index e7e3a64..0000000
--- a/arch/arm/dts/k3-j7200-thermal.dtsi
+++ /dev/null
@@ -1,47 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-
-#include <dt-bindings/thermal/thermal.h>
-
-thermal_zones: thermal-zones {
- mcu_thermal: mcu-thermal {
- polling-delay-passive = <250>; /* milliseconds */
- polling-delay = <500>; /* milliseconds */
- thermal-sensors = <&wkup_vtm0 0>;
-
- trips {
- wkup_crit: wkup-crit {
- temperature = <125000>; /* milliCelsius */
- hysteresis = <2000>; /* milliCelsius */
- type = "critical";
- };
- };
- };
-
- mpu_thermal: mpu-thermal {
- polling-delay-passive = <250>; /* milliseconds */
- polling-delay = <500>; /* milliseconds */
- thermal-sensors = <&wkup_vtm0 1>;
-
- trips {
- mpu_crit: mpu-crit {
- temperature = <125000>; /* milliCelsius */
- hysteresis = <2000>; /* milliCelsius */
- type = "critical";
- };
- };
- };
-
- main_thermal: main-thermal {
- polling-delay-passive = <250>; /* milliseconds */
- polling-delay = <500>; /* milliseconds */
- thermal-sensors = <&wkup_vtm0 2>;
-
- trips {
- c7x_crit: c7x-crit {
- temperature = <125000>; /* milliCelsius */
- hysteresis = <2000>; /* milliCelsius */
- type = "critical";
- };
- };
- };
-};
diff --git a/arch/arm/dts/k3-j7200.dtsi b/arch/arm/dts/k3-j7200.dtsi
deleted file mode 100644
index ef73e6d..0000000
--- a/arch/arm/dts/k3-j7200.dtsi
+++ /dev/null
@@ -1,164 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for J7200 SoC Family
- *
- * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/soc/ti,sci_pm_domain.h>
-
-#include "k3-pinctrl.h"
-
-/ {
- model = "Texas Instruments K3 J7200 SoC";
- compatible = "ti,j7200";
- interrupt-parent = <&gic500>;
- #address-cells = <2>;
- #size-cells = <2>;
-
- chosen { };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- cpu-map {
- cluster0: cluster0 {
- core0 {
- cpu = <&cpu0>;
- };
-
- core1 {
- cpu = <&cpu1>;
- };
- };
-
- };
-
- cpu0: cpu@0 {
- compatible = "arm,cortex-a72";
- reg = <0x000>;
- device_type = "cpu";
- enable-method = "psci";
- i-cache-size = <0xc000>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <64>;
- d-cache-sets = <256>;
- next-level-cache = <&L2_0>;
- };
-
- cpu1: cpu@1 {
- compatible = "arm,cortex-a72";
- reg = <0x001>;
- device_type = "cpu";
- enable-method = "psci";
- i-cache-size = <0xc000>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <64>;
- d-cache-sets = <256>;
- next-level-cache = <&L2_0>;
- };
- };
-
- L2_0: l2-cache0 {
- compatible = "cache";
- cache-level = <2>;
- cache-unified;
- cache-size = <0x100000>;
- cache-line-size = <64>;
- cache-sets = <1024>;
- next-level-cache = <&msmc_l3>;
- };
-
- msmc_l3: l3-cache0 {
- compatible = "cache";
- cache-level = <3>;
- cache-unified;
- };
-
- firmware {
- optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- };
-
- psci: psci {
- compatible = "arm,psci-1.0";
- method = "smc";
- };
- };
-
- a72_timer0: timer-cl0-cpu0 {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
- <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
- <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
- };
-
- pmu: pmu {
- compatible = "arm,cortex-a72-pmu";
- interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- cbass_main: bus@100000 {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
- <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
- <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */
- <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */
- <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
- <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
- <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
- <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */
- <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
- <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
-
- /* MCUSS_WKUP Range */
- <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
- <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
- <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
- <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
- <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
- <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
- <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
- <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
- <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
- <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
- <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
- <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
- <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
-
- cbass_mcu_wakeup: bus@28380000 {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
- <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
- <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
- <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
- <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
- <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
- <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
- <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
- <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
- <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
- <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
- <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
- <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3 */
- };
- };
-
- #include "k3-j7200-thermal.dtsi"
-};
-
-/* Now include the peripherals for each bus segments */
-#include "k3-j7200-main.dtsi"
-#include "k3-j7200-mcu-wakeup.dtsi"
diff --git a/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi b/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi
index e202ae1..884f442 100644
--- a/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi
@@ -351,4 +351,27 @@
};
};
};
+
+#include "k3-binman-capsule.dtsi"
+
+// Capsule update GUIDs in string form. See beagleboneai64.h
+#define BEAGLEBONEAI64_SPL_IMAGE_GUID_STR "83447222-1e26-40cd-a395-b7de0957e875"
+#define BEAGLEBONEAI64_UBOOT_IMAGE_GUID_STR "4249ff77-c17d-4eb7-a1db-45aa9887d49e"
+
+&capsule_tispl {
+ efi-capsule {
+ image-guid = BEAGLEBONEAI64_SPL_IMAGE_GUID_STR;
+
+ blob {
+ filename = "tispl.bin_unsigned";
+ };
+ };
+};
+
+&capsule_uboot {
+ efi-capsule {
+ image-guid = BEAGLEBONEAI64_UBOOT_IMAGE_GUID_STR;
+ };
+};
+
#endif
diff --git a/arch/arm/dts/k3-j721e-binman.dtsi b/arch/arm/dts/k3-j721e-binman.dtsi
index 1514d89..0d60729 100644
--- a/arch/arm/dts/k3-j721e-binman.dtsi
+++ b/arch/arm/dts/k3-j721e-binman.dtsi
@@ -295,21 +295,49 @@
};
};
};
+
+#include "k3-binman-capsule-r5.dtsi"
+
+// Capsule update GUIDs in string form. See j721e_evm.h
+#define J721E_SK_TIBOOT3_IMAGE_GUID_STR "e672b518-7cd7-4014-bd8d-40724d0ad4dc"
+#define J721E_SK_SYSFW_IMAGE_GUID_STR "6fd10680-361b-431f-80aa-899455819e11"
+
+&capsule_tiboot3 {
+ efi-capsule {
+ image-guid = J721E_SK_TIBOOT3_IMAGE_GUID_STR;
+ };
+};
+
+&binman {
+ capsule-sysfw {
+ filename = "sysfw-capsule.bin";
+ efi-capsule {
+ image-index = <0x4>;
+ image-guid = J721E_SK_SYSFW_IMAGE_GUID_STR;
+ private-key = "arch/arm/mach-k3/keys/custMpk.pem";
+ public-key-cert = "arch/arm/mach-k3/keys/custMpk.crt";
+ monotonic-count = <0x1>;
+
+ blob {
+ filename = "sysfw.itb";
+ };
+ };
+ };
+};
+
#endif
#ifdef CONFIG_TARGET_J721E_A72_EVM
-#define SPL_J721E_EVM_DTB "spl/dts/k3-j721e-common-proc-board.dtb"
-#define SPL_J721E_SK_DTB "spl/dts/k3-j721e-sk.dtb"
-
+#define SPL_J721E_EVM_DTB "spl/dts/ti/k3-j721e-common-proc-board.dtb"
#define J721E_EVM_DTB "u-boot.dtb"
-#define J721E_SK_DTB "arch/arm/dts/k3-j721e-sk.dtb"
&binman {
ti-dm {
filename = "ti-dm.bin";
blob-ext {
filename = "ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+ optional;
};
};
ti-spl {
@@ -449,28 +477,13 @@
arch = "arm";
compression = "none";
ti-secure {
- content = <&spl_j721e_evm_dtb>;
+ content = <&spl_j721e_dtb>;
keyfile = "custMpk.pem";
};
- spl_j721e_evm_dtb: blob-ext {
+ spl_j721e_dtb: blob-ext {
filename = SPL_J721E_EVM_DTB;
};
};
-
- fdt-1 {
- description = "k3-j721e-sk";
- type = "flat_dt";
- arch = "arm";
- compression = "none";
- ti-secure {
- content = <&spl_j721e_sk_dtb>;
- keyfile = "custMpk.pem";
-
- };
- spl_j721e_sk_dtb: blob-ext {
- filename = SPL_J721E_SK_DTB;
- };
- };
};
configurations {
@@ -482,13 +495,6 @@
loadables = "tee", "dm", "spl";
fdt = "fdt-0";
};
-
- conf-1 {
- description = "k3-j721e-sk";
- firmware = "atf";
- loadables = "tee", "dm", "spl";
- fdt = "fdt-1";
- };
};
};
};
@@ -510,35 +516,17 @@
arch = "arm";
compression = "none";
ti-secure {
- content = <&j721e_evm_dtb>;
+ content = <&j721e_dtb>;
keyfile = "custMpk.pem";
};
- j721e_evm_dtb: blob-ext {
+ j721e_dtb: blob-ext {
filename = J721E_EVM_DTB;
};
hash {
algo = "crc32";
};
};
-
- fdt-1 {
- description = "k3-j721e-sk";
- type = "flat_dt";
- arch = "arm";
- compression = "none";
- ti-secure {
- content = <&j721e_sk_dtb>;
- keyfile = "custMpk.pem";
-
- };
- j721e_sk_dtb: blob-ext {
- filename = J721E_SK_DTB;
- };
- hash {
- algo = "crc32";
- };
- };
};
configurations {
@@ -550,13 +538,6 @@
loadables = "uboot";
fdt = "fdt-0";
};
-
- conf-1 {
- description = "k3-j721e-sk";
- firmware = "uboot";
- loadables = "uboot";
- fdt = "fdt-1";
- };
};
};
};
@@ -579,20 +560,10 @@
type = "flat_dt";
arch = "arm";
compression = "none";
- blob {
+ spl_j721e_dtb_unsigned: blob {
filename = SPL_J721E_EVM_DTB;
};
};
-
- fdt-1 {
- description = "k3-j721e-sk";
- type = "flat_dt";
- arch = "arm";
- compression = "none";
- blob {
- filename = SPL_J721E_SK_DTB;
- };
- };
};
configurations {
@@ -604,13 +575,6 @@
loadables = "tee", "dm", "spl";
fdt = "fdt-0";
};
-
- conf-1 {
- description = "k3-j721e-sk";
- firmware = "atf";
- loadables = "tee", "dm", "spl";
- fdt = "fdt-1";
- };
};
};
};
@@ -631,26 +595,13 @@
type = "flat_dt";
arch = "arm";
compression = "none";
- blob {
+ j721e_dtb_unsigned: blob {
filename = J721E_EVM_DTB;
};
hash {
algo = "crc32";
};
};
-
- fdt-1 {
- description = "k3-j721e-sk";
- type = "flat_dt";
- arch = "arm";
- compression = "none";
- blob {
- filename = J721E_SK_DTB;
- };
- hash {
- algo = "crc32";
- };
- };
};
configurations {
@@ -662,15 +613,27 @@
loadables = "uboot";
fdt = "fdt-0";
};
-
- conf-1 {
- description = "k3-j721e-sk";
- firmware = "uboot";
- loadables = "uboot";
- fdt = "fdt-1";
- };
};
};
};
};
+
+#include "k3-binman-capsule.dtsi"
+
+// Capsule update GUIDs in string form. See j721e_evm.h
+#define J721E_SK_SPL_IMAGE_GUID_STR "86f710ad-10cf-46ea-ac67-856ae06efad2"
+#define J721E_SK_UBOOT_IMAGE_GUID_STR "81b58fb0-3b00-4add-a20a-c185bbaca1ed"
+
+&capsule_tispl {
+ efi-capsule {
+ image-guid = J721E_SK_SPL_IMAGE_GUID_STR;
+ };
+};
+
+&capsule_uboot {
+ efi-capsule {
+ image-guid = J721E_SK_UBOOT_IMAGE_GUID_STR;
+ };
+};
+
#endif
diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
index aa919b4..1b119f2 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
@@ -15,10 +15,10 @@
&cbass_mcu_wakeup {
bootph-all;
+};
- chipid@43000014 {
- bootph-all;
- };
+&chipid {
+ bootph-all;
};
&mcu_navss {
@@ -30,14 +30,6 @@
};
&mcu_udmap {
- reg = <0x0 0x285c0000 0x0 0x100>,
- <0x0 0x284c0000 0x0 0x4000>,
- <0x0 0x2a800000 0x0 0x40000>,
- <0x0 0x284a0000 0x0 0x4000>,
- <0x0 0x2aa00000 0x0 0x40000>,
- <0x0 0x28400000 0x0 0x2000>;
- reg-names = "gcfg", "rchan", "rchanrt", "tchan",
- "tchanrt", "rflow";
bootph-all;
};
diff --git a/arch/arm/dts/k3-j721e-common-proc-board.dts b/arch/arm/dts/k3-j721e-common-proc-board.dts
deleted file mode 100644
index fe5207a..0000000
--- a/arch/arm/dts/k3-j721e-common-proc-board.dts
+++ /dev/null
@@ -1,976 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
- *
- * Product Link: https://www.ti.com/tool/J721EXCPXEVM
- */
-
-/dts-v1/;
-
-#include "k3-j721e-som-p0.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/net/ti-dp83867.h>
-#include <dt-bindings/phy/phy-cadence.h>
-
-/ {
- compatible = "ti,j721e-evm", "ti,j721e";
- model = "Texas Instruments J721e EVM";
-
- aliases {
- serial0 = &wkup_uart0;
- serial1 = &mcu_uart0;
- serial2 = &main_uart0;
- serial3 = &main_uart1;
- serial4 = &main_uart2;
- serial6 = &main_uart4;
- ethernet0 = &cpsw_port1;
- mmc0 = &main_sdhci0;
- mmc1 = &main_sdhci1;
- };
-
- chosen {
- stdout-path = "serial2:115200n8";
- };
-
- gpio_keys: gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
- pinctrl-names = "default";
- pinctrl-0 = <&sw10_button_pins_default>, <&sw11_button_pins_default>;
-
- sw10: switch-10 {
- label = "GPIO Key USER1";
- linux,code = <BTN_0>;
- gpios = <&main_gpio0 0 GPIO_ACTIVE_LOW>;
- };
-
- sw11: switch-11 {
- label = "GPIO Key USER2";
- linux,code = <BTN_1>;
- gpios = <&wkup_gpio0 7 GPIO_ACTIVE_LOW>;
- };
- };
-
- evm_12v0: fixedregulator-evm12v0 {
- /* main supply */
- compatible = "regulator-fixed";
- regulator-name = "evm_12v0";
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vsys_3v3: fixedregulator-vsys3v3 {
- /* Output of LMS140 */
- compatible = "regulator-fixed";
- regulator-name = "vsys_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&evm_12v0>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vsys_5v0: fixedregulator-vsys5v0 {
- /* Output of LM5140 */
- compatible = "regulator-fixed";
- regulator-name = "vsys_5v0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&evm_12v0>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vdd_mmc1: fixedregulator-sd {
- compatible = "regulator-fixed";
- regulator-name = "vdd_mmc1";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- enable-active-high;
- vin-supply = <&vsys_3v3>;
- gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
- };
-
- vdd_sd_dv_alt: gpio-regulator-TLV71033 {
- compatible = "regulator-gpio";
- pinctrl-names = "default";
- pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
- regulator-name = "tlv71033";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- vin-supply = <&vsys_5v0>;
- gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>;
- states = <1800000 0x0>,
- <3300000 0x1>;
- };
-
- sound0: sound-0 {
- compatible = "ti,j721e-cpb-audio";
- model = "j721e-cpb";
-
- ti,cpb-mcasp = <&mcasp10>;
- ti,cpb-codec = <&pcm3168a_1>;
-
- clocks = <&k3_clks 184 1>,
- <&k3_clks 184 2>, <&k3_clks 184 4>,
- <&k3_clks 157 371>,
- <&k3_clks 157 400>, <&k3_clks 157 401>;
- clock-names = "cpb-mcasp-auxclk",
- "cpb-mcasp-auxclk-48000", "cpb-mcasp-auxclk-44100",
- "cpb-codec-scki",
- "cpb-codec-scki-48000", "cpb-codec-scki-44100";
- };
-
- transceiver1: can-phy0 {
- compatible = "ti,tcan1043";
- #phy-cells = <0>;
- max-bitrate = <5000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
- standby-gpios = <&wkup_gpio0 54 GPIO_ACTIVE_LOW>;
- enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>;
- };
-
- transceiver2: can-phy1 {
- compatible = "ti,tcan1042";
- #phy-cells = <0>;
- max-bitrate = <5000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_mcan1_gpio_pins_default>;
- standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>;
- };
-
- transceiver3: can-phy2 {
- compatible = "ti,tcan1043";
- #phy-cells = <0>;
- max-bitrate = <5000000>;
- standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>;
- enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>;
- };
-
- transceiver4: can-phy3 {
- compatible = "ti,tcan1042";
- #phy-cells = <0>;
- max-bitrate = <5000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&main_mcan2_gpio_pins_default>;
- standby-gpios = <&main_gpio0 127 GPIO_ACTIVE_HIGH>;
- };
-
- dp_pwr_3v3: regulator-dp-pwr {
- compatible = "regulator-fixed";
- regulator-name = "dp-pwr";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&exp4 0 GPIO_ACTIVE_HIGH>; /* P0 - DP0_PWR_SW_EN */
- enable-active-high;
- };
-
- dp0: connector {
- compatible = "dp-connector";
- label = "DP0";
- type = "full-size";
- dp-pwr-supply = <&dp_pwr_3v3>;
-
- port {
- dp_connector_in: endpoint {
- remote-endpoint = <&dp0_out>;
- };
- };
- };
-};
-
-&main_pmx0 {
- main_uart0_pins_default: main-uart0-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0x1d4, PIN_INPUT, 1) /* (Y3) SPI1_CS0.UART0_CTSn */
- J721E_IOPAD(0x1c0, PIN_OUTPUT, 1) /* (AA2) SPI0_CS0.UART0_RTSn */
- J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
- J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
- >;
- };
-
- main_uart1_pins_default: main-uart1-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0x1f8, PIN_INPUT, 0) /* (AA4) UART1_RXD */
- J721E_IOPAD(0x1fc, PIN_OUTPUT, 0) /* (AB4) UART1_TXD */
- >;
- };
-
- main_uart2_pins_default: main-uart2-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0x1dc, PIN_INPUT, 3) /* (Y1) SPI1_CLK.UART2_RXD */
- J721E_IOPAD(0x1e0, PIN_OUTPUT, 3) /* (Y5) SPI1_D0.UART2_TXD */
- >;
- };
-
- main_uart4_pins_default: main-uart4-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0x190, PIN_INPUT, 1) /* (W23) RGMII6_TD3.UART4_RXD */
- J721E_IOPAD(0x194, PIN_OUTPUT, 1) /* (W28) RGMII6_TD2.UART4_TXD */
- >;
- };
-
- sw10_button_pins_default: sw10-button-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */
- >;
- };
-
- main_mmc1_pins_default: main-mmc1-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
- J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
- J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
- J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
- J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
- J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
- J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
- J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
- J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
- >;
- };
-
- vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */
- >;
- };
-
- main_usbss0_pins_default: main-usbss0-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
- J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
- >;
- };
-
- main_usbss1_pins_default: main-usbss1-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
- >;
- };
-
- dp0_pins_default: dp0-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */
- >;
- };
-
- main_i2c1_exp4_pins_default: main-i2c1-exp4-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */
- >;
- };
-
- main_i2c0_pins_default: main-i2c0-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
- J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
- >;
- };
-
- main_i2c1_pins_default: main-i2c1-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
- J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
- >;
- };
-
- main_i2c3_pins_default: main-i2c3-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
- J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
- >;
- };
-
- main_i2c6_pins_default: main-i2c6-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */
- J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */
- >;
- };
-
- mcasp10_pins_default: mcasp10-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */
- J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */
- J721E_IOPAD(0x160, PIN_OUTPUT_PULLDOWN, 12) /* (V28) RGMII5_TD3.MCASP10_AXR0 */
- J721E_IOPAD(0x164, PIN_OUTPUT_PULLDOWN, 12) /* (V29) RGMII5_TD2.MCASP10_AXR1 */
- J721E_IOPAD(0x170, PIN_OUTPUT_PULLDOWN, 12) /* (U29) RGMII5_TXC.MCASP10_AXR2 */
- J721E_IOPAD(0x174, PIN_OUTPUT_PULLDOWN, 12) /* (U25) RGMII5_RXC.MCASP10_AXR3 */
- J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 12) /* (V25) RGMII6_TD1.MCASP10_AXR4 */
- J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 12) /* (W27) RGMII6_TD0.MCASP10_AXR5 */
- J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 12) /* (W29) RGMII6_TXC.MCASP10_AXR6 */
- >;
- };
-
- audi_ext_refclk2_pins_default: audi-ext-refclk2-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */
- >;
- };
-
- main_mcan0_pins_default: main-mcan0-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0x208, PIN_INPUT, 0) /* (W5) MCAN0_RX */
- J721E_IOPAD(0x20c, PIN_OUTPUT, 0) /* (W6) MCAN0_TX */
- >;
- };
-
- main_mcan2_pins_default: main-mcan2-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0x01f0, PIN_INPUT, 3) /* (AC2) MCAN2_RX.GPIO0_123 */
- J721E_IOPAD(0x01f4, PIN_OUTPUT, 3) /* (AB1) MCAN2_TX.GPIO0_124 */
- >;
- };
-
- main_mcan2_gpio_pins_default: main-mcan2-gpio-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */
- >;
- };
-};
-
-&wkup_pmx0 {
- wkup_uart0_pins_default: wkup-uart0-default-pins {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
- J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
- >;
- };
-
- mcu_uart0_pins_default: mcu-uart0-default-pins {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0xe8, PIN_INPUT, 0) /* (H29) WKUP_GPIO0_14.MCU_UART0_CTSn */
- J721E_WKUP_IOPAD(0xec, PIN_OUTPUT, 0) /* (J27) WKUP_GPIO0_15.MCU_UART0_RTSn */
- J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */
- J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0) /* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
- >;
- };
-
- sw11_button_pins_default: sw11-button-default-pins {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */
- >;
- };
-
- mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */
- J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */
- J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */
- J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */
- J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */
- J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */
- J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */
- J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */
- >;
- };
-
- mcu_cpsw_pins_default: mcu-cpsw-default-pins {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
- J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
- J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
- J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
- J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
- J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
- J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
- J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
- J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
- J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
- J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
- J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
- >;
- };
-
- mcu_mdio_pins_default: mcu-mdio1-default-pins {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */
- J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */
- >;
- };
-
- mcu_mcan0_pins_default: mcu-mcan0-default-pins {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0xac, PIN_INPUT, 0) /* (C29) MCU_MCAN0_RX */
- J721E_WKUP_IOPAD(0xa8, PIN_OUTPUT, 0) /* (D29) MCU_MCAN0_TX */
- >;
- };
-
- mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* (F26) WKUP_GPIO0_0 */
- J721E_WKUP_IOPAD(0x98, PIN_INPUT, 7) /* (E28) MCU_SPI0_D1.WKUP_GPIO0_54 */
- >;
- };
-
- mcu_mcan1_pins_default: mcu-mcan1-default-pins {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0xc4, PIN_INPUT, 0) /* (G24) WKUP_GPIO0_5.MCU_MCAN1_RX */
- J721E_WKUP_IOPAD(0xc0, PIN_OUTPUT, 0) /* (G25) WKUP_GPIO0_4.MCU_MCAN1_TX */
- >;
- };
-
- mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* (F28) WKUP_GPIO0_2 */
- >;
- };
-
- wkup_gpio_pins_default: wkup-gpio-default-pins {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_8 */
- >;
- };
-};
-
-&wkup_uart0 {
- /* Wakeup UART is used by System firmware */
- status = "reserved";
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_uart0_pins_default>;
-};
-
-&mcu_uart0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_uart0_pins_default>;
-};
-
-&main_uart0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart0_pins_default>;
- /* Shared with ATF on this platform */
- power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
-};
-
-&main_uart1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart1_pins_default>;
-};
-
-&main_uart2 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart2_pins_default>;
-};
-
-&main_uart4 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart4_pins_default>;
-};
-
-&wkup_gpio0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_gpio_pins_default>;
-};
-
-&main_gpio0 {
- status = "okay";
-};
-
-&main_gpio1 {
- status = "okay";
-};
-
-&main_sdhci0 {
- /* eMMC */
- status = "okay";
- non-removable;
- ti,driver-strength-ohm = <50>;
- disable-wp;
-};
-
-&main_sdhci1 {
- /* SD/MMC */
- status = "okay";
- vmmc-supply = <&vdd_mmc1>;
- vqmmc-supply = <&vdd_sd_dv_alt>;
- pinctrl-names = "default";
- pinctrl-0 = <&main_mmc1_pins_default>;
- ti,driver-strength-ohm = <50>;
- disable-wp;
-};
-
-&usb_serdes_mux {
- idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */
-};
-
-&serdes_ln_ctrl {
- idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
- <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
- <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
- <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
- <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
- <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
-};
-
-&serdes_wiz3 {
- typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
- typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */
-};
-
-&serdes3 {
- serdes3_usb_link: phy@0 {
- reg = <0>;
- cdns,num-lanes = <2>;
- #phy-cells = <0>;
- cdns,phy-type = <PHY_TYPE_USB3>;
- resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
- };
-};
-
-&usbss0 {
- pinctrl-names = "default";
- pinctrl-0 = <&main_usbss0_pins_default>;
- ti,vbus-divider;
-};
-
-&usb0 {
- dr_mode = "otg";
- maximum-speed = "super-speed";
- phys = <&serdes3_usb_link>;
- phy-names = "cdns3,usb3-phy";
-};
-
-&usbss1 {
- pinctrl-names = "default";
- pinctrl-0 = <&main_usbss1_pins_default>;
- ti,usb2-only;
-};
-
-&usb1 {
- dr_mode = "host";
- maximum-speed = "high-speed";
-};
-
-&ospi1 {
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0x0>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <4>;
- spi-max-frequency = <40000000>;
- cdns,tshsl-ns = <60>;
- cdns,tsd2d-ns = <60>;
- cdns,tchsh-ns = <60>;
- cdns,tslch-ns = <60>;
- cdns,read-delay = <2>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "qspi.tiboot3";
- reg = <0x0 0x80000>;
- };
-
- partition@80000 {
- label = "qspi.tispl";
- reg = <0x80000 0x200000>;
- };
-
- partition@280000 {
- label = "qspi.u-boot";
- reg = <0x280000 0x400000>;
- };
-
- partition@680000 {
- label = "qspi.env";
- reg = <0x680000 0x20000>;
- };
-
- partition@6a0000 {
- label = "qspi.env.backup";
- reg = <0x6a0000 0x20000>;
- };
-
- partition@6c0000 {
- label = "qspi.sysfw";
- reg = <0x6c0000 0x100000>;
- };
-
- partition@800000 {
- label = "qspi.rootfs";
- reg = <0x800000 0x37c0000>;
- };
-
- partition@3fe0000 {
- label = "qspi.phypattern";
- reg = <0x3fe0000 0x20000>;
- };
- };
- };
-};
-
-&tscadc0 {
- status = "okay";
- adc {
- ti,adc-channels = <0 1 2 3 4 5 6 7>;
- };
-};
-
-&tscadc1 {
- status = "okay";
- adc {
- ti,adc-channels = <0 1 2 3 4 5 6 7>;
- };
-};
-
-&main_i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c0_pins_default>;
- clock-frequency = <400000>;
-
- exp1: gpio@20 {
- compatible = "ti,tca6416";
- reg = <0x20>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- exp2: gpio@22 {
- compatible = "ti,tca6424";
- reg = <0x22>;
- gpio-controller;
- #gpio-cells = <2>;
-
- p09-hog {
- /* P11 - MCASP/TRACE_MUX_S0 */
- gpio-hog;
- gpios = <9 GPIO_ACTIVE_HIGH>;
- output-low;
- line-name = "MCASP/TRACE_MUX_S0";
- };
-
- p10-hog {
- /* P12 - MCASP/TRACE_MUX_S1 */
- gpio-hog;
- gpios = <10 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "MCASP/TRACE_MUX_S1";
- };
- };
-};
-
-&main_i2c1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c1_pins_default>;
- clock-frequency = <400000>;
-
- exp4: gpio@20 {
- compatible = "ti,tca6408";
- reg = <0x20>;
- gpio-controller;
- #gpio-cells = <2>;
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c1_exp4_pins_default>;
- interrupt-parent = <&main_gpio1>;
- interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-};
-
-&k3_clks {
- /* Confiure AUDIO_EXT_REFCLK2 pin as output */
- pinctrl-names = "default";
- pinctrl-0 = <&audi_ext_refclk2_pins_default>;
-};
-
-&main_i2c3 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c3_pins_default>;
- clock-frequency = <400000>;
-
- exp3: gpio@20 {
- compatible = "ti,tca6408";
- reg = <0x20>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- pcm3168a_1: audio-codec@44 {
- compatible = "ti,pcm3168a";
- reg = <0x44>;
-
- #sound-dai-cells = <1>;
-
- reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>;
-
- /* C_AUDIO_REFCLK2 -> RGMII6_RXC (W26) */
- clocks = <&k3_clks 157 371>;
- clock-names = "scki";
-
- /* HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK -> REFCLK2 */
- assigned-clocks = <&k3_clks 157 371>;
- assigned-clock-parents = <&k3_clks 157 400>;
- assigned-clock-rates = <24576000>; /* for 48KHz */
-
- VDD1-supply = <&vsys_3v3>;
- VDD2-supply = <&vsys_3v3>;
- VCCAD1-supply = <&vsys_5v0>;
- VCCAD2-supply = <&vsys_5v0>;
- VCCDA1-supply = <&vsys_5v0>;
- VCCDA2-supply = <&vsys_5v0>;
- };
-};
-
-&main_i2c6 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c6_pins_default>;
- clock-frequency = <400000>;
-
- exp5: gpio@20 {
- compatible = "ti,tca6408";
- reg = <0x20>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-};
-
-&mcu_cpsw {
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
-};
-
-&davinci_mdio {
- phy0: ethernet-phy@0 {
- reg = <0>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- };
-};
-
-&cpsw_port1 {
- phy-mode = "rgmii-rxid";
- phy-handle = <&phy0>;
-};
-
-&dss {
- /*
- * These clock assignments are chosen to enable the following outputs:
- *
- * VP0 - DisplayPort SST
- * VP1 - DPI0
- * VP2 - DSI
- * VP3 - DPI1
- */
-
- assigned-clocks = <&k3_clks 152 1>,
- <&k3_clks 152 4>,
- <&k3_clks 152 9>,
- <&k3_clks 152 13>;
- assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */
- <&k3_clks 152 6>, /* PLL19_HSDIV0 */
- <&k3_clks 152 11>, /* PLL18_HSDIV0 */
- <&k3_clks 152 18>; /* PLL23_HSDIV0 */
-};
-
-&dss_ports {
- port {
- dpi0_out: endpoint {
- remote-endpoint = <&dp0_in>;
- };
- };
-};
-
-&dp0_ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- dp0_in: endpoint {
- remote-endpoint = <&dpi0_out>;
- };
- };
-
- port@4 {
- reg = <4>;
- dp0_out: endpoint {
- remote-endpoint = <&dp_connector_in>;
- };
- };
-};
-
-&mcasp10 {
- status = "okay";
- #sound-dai-cells = <0>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&mcasp10_pins_default>;
-
- op-mode = <0>; /* MCASP_IIS_MODE */
- tdm-slots = <2>;
- auxclk-fs-ratio = <256>;
-
- serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
- 1 1 1 1
- 2 2 2 0
- >;
- tx-num-evt = <0>;
- rx-num-evt = <0>;
-};
-
-&cmn_refclk1 {
- clock-frequency = <100000000>;
-};
-
-&wiz0_pll1_refclk {
- assigned-clocks = <&wiz0_pll1_refclk>;
- assigned-clock-parents = <&cmn_refclk1>;
-};
-
-&wiz0_refclk_dig {
- assigned-clocks = <&wiz0_refclk_dig>;
- assigned-clock-parents = <&cmn_refclk1>;
-};
-
-&wiz1_pll1_refclk {
- assigned-clocks = <&wiz1_pll1_refclk>;
- assigned-clock-parents = <&cmn_refclk1>;
-};
-
-&wiz1_refclk_dig {
- assigned-clocks = <&wiz1_refclk_dig>;
- assigned-clock-parents = <&cmn_refclk1>;
-};
-
-&wiz2_pll1_refclk {
- assigned-clocks = <&wiz2_pll1_refclk>;
- assigned-clock-parents = <&cmn_refclk1>;
-};
-
-&wiz2_refclk_dig {
- assigned-clocks = <&wiz2_refclk_dig>;
- assigned-clock-parents = <&cmn_refclk1>;
-};
-
-&serdes0 {
- assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
- assigned-clock-parents = <&wiz0_pll1_refclk>;
-
- serdes0_pcie_link: phy@0 {
- reg = <0>;
- cdns,num-lanes = <1>;
- #phy-cells = <0>;
- cdns,phy-type = <PHY_TYPE_PCIE>;
- resets = <&serdes_wiz0 1>;
- };
-};
-
-&serdes1 {
- assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>;
- assigned-clock-parents = <&wiz1_pll1_refclk>;
-
- serdes1_pcie_link: phy@0 {
- reg = <0>;
- cdns,num-lanes = <2>;
- #phy-cells = <0>;
- cdns,phy-type = <PHY_TYPE_PCIE>;
- resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
- };
-};
-
-&serdes2 {
- assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>;
- assigned-clock-parents = <&wiz2_pll1_refclk>;
-
- serdes2_pcie_link: phy@0 {
- reg = <0>;
- cdns,num-lanes = <2>;
- #phy-cells = <0>;
- cdns,phy-type = <PHY_TYPE_PCIE>;
- resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>;
- };
-};
-
-&serdes4 {
- torrent_phy_dp: phy@0 {
- reg = <0>;
- resets = <&serdes_wiz4 1>;
- cdns,phy-type = <PHY_TYPE_DP>;
- cdns,num-lanes = <4>;
- cdns,max-bit-rate = <5400>;
- #phy-cells = <0>;
- };
-};
-
-&mhdp {
- phys = <&torrent_phy_dp>;
- phy-names = "dpphy";
- pinctrl-names = "default";
- pinctrl-0 = <&dp0_pins_default>;
-};
-
-&pcie0_rc {
- status = "okay";
- reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
- phys = <&serdes0_pcie_link>;
- phy-names = "pcie-phy";
- num-lanes = <1>;
-};
-
-&pcie1_rc {
- status = "okay";
- reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
- phys = <&serdes1_pcie_link>;
- phy-names = "pcie-phy";
- num-lanes = <2>;
-};
-
-&pcie2_rc {
- status = "okay";
- reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>;
- phys = <&serdes2_pcie_link>;
- phy-names = "pcie-phy";
- num-lanes = <2>;
-};
-
-&mcu_mcan0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_mcan0_pins_default>;
- phys = <&transceiver1>;
-};
-
-&mcu_mcan1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_mcan1_pins_default>;
- phys = <&transceiver2>;
-};
-
-&main_mcan0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_mcan0_pins_default>;
- phys = <&transceiver3>;
-};
-
-&main_mcan2 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_mcan2_pins_default>;
- phys = <&transceiver4>;
-};
diff --git a/arch/arm/dts/k3-j721e-main.dtsi b/arch/arm/dts/k3-j721e-main.dtsi
deleted file mode 100644
index 746b9f8..0000000
--- a/arch/arm/dts/k3-j721e-main.dtsi
+++ /dev/null
@@ -1,2741 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for J721E SoC Family Main Domain peripherals
- *
- * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
- */
-#include <dt-bindings/phy/phy.h>
-#include <dt-bindings/phy/phy-ti.h>
-#include <dt-bindings/mux/mux.h>
-
-#include "k3-serdes.h"
-
-/ {
- cmn_refclk: clock-cmnrefclk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
-
- cmn_refclk1: clock-cmnrefclk1 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
-};
-
-&cbass_main {
- msmc_ram: sram@70000000 {
- compatible = "mmio-sram";
- reg = <0x0 0x70000000 0x0 0x800000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0x70000000 0x800000>;
-
- atf-sram@0 {
- reg = <0x0 0x20000>;
- };
- };
-
- scm_conf: scm-conf@100000 {
- compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
- reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0x00100000 0x1c000>;
-
- serdes_ln_ctrl: mux-controller@4080 {
- compatible = "mmio-mux";
- reg = <0x00004080 0x50>;
- #mux-control-cells = <1>;
- mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
- <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
- <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
- <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
- <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
- /* SERDES4 lane0/1/2/3 select */
- idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
- <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
- <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
- <MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>,
- <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
- <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
- };
-
- cpsw0_phy_gmii_sel: phy@4044 {
- compatible = "ti,j721e-cpsw9g-phy-gmii-sel";
- ti,qsgmii-main-ports = <2>, <2>;
- reg = <0x4044 0x20>;
- #phy-cells = <1>;
- };
-
- usb_serdes_mux: mux-controller@4000 {
- compatible = "mmio-mux";
- #mux-control-cells = <1>;
- mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
- <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */
- };
-
- ehrpwm_tbclk: clock-controller@4140 {
- compatible = "ti,am654-ehrpwm-tbclk";
- reg = <0x4140 0x18>;
- #clock-cells = <1>;
- };
- };
-
- main_ehrpwm0: pwm@3000000 {
- compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x00 0x3000000 0x00 0x100>;
- power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&ehrpwm_tbclk 0>, <&k3_clks 83 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- main_ehrpwm1: pwm@3010000 {
- compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x00 0x3010000 0x00 0x100>;
- power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&ehrpwm_tbclk 1>, <&k3_clks 84 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- main_ehrpwm2: pwm@3020000 {
- compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x00 0x3020000 0x00 0x100>;
- power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&ehrpwm_tbclk 2>, <&k3_clks 85 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- main_ehrpwm3: pwm@3030000 {
- compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x00 0x3030000 0x00 0x100>;
- power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&ehrpwm_tbclk 3>, <&k3_clks 86 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- main_ehrpwm4: pwm@3040000 {
- compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x00 0x3040000 0x00 0x100>;
- power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&ehrpwm_tbclk 4>, <&k3_clks 87 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- main_ehrpwm5: pwm@3050000 {
- compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x00 0x3050000 0x00 0x100>;
- power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&ehrpwm_tbclk 5>, <&k3_clks 88 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- gic500: interrupt-controller@1800000 {
- compatible = "arm,gic-v3";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
- <0x00 0x01900000 0x00 0x100000>, /* GICR */
- <0x00 0x6f000000 0x00 0x2000>, /* GICC */
- <0x00 0x6f010000 0x00 0x1000>, /* GICH */
- <0x00 0x6f020000 0x00 0x2000>; /* GICV */
-
- /* vcpumntirq: virtual CPU interface maintenance interrupt */
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
-
- gic_its: msi-controller@1820000 {
- compatible = "arm,gic-v3-its";
- reg = <0x00 0x01820000 0x00 0x10000>;
- socionext,synquacer-pre-its = <0x1000000 0x400000>;
- msi-controller;
- #msi-cells = <1>;
- };
- };
-
- main_gpio_intr: interrupt-controller@a00000 {
- compatible = "ti,sci-intr";
- reg = <0x00 0x00a00000 0x00 0x800>;
- ti,intr-trigger-type = <1>;
- interrupt-controller;
- interrupt-parent = <&gic500>;
- #interrupt-cells = <1>;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <131>;
- ti,interrupt-ranges = <8 392 56>;
- };
-
- main_navss: bus@30000000 {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
- dma-coherent;
- dma-ranges;
-
- ti,sci-dev-id = <199>;
-
- main_navss_intr: interrupt-controller@310e0000 {
- compatible = "ti,sci-intr";
- reg = <0x0 0x310e0000 0x0 0x4000>;
- ti,intr-trigger-type = <4>;
- interrupt-controller;
- interrupt-parent = <&gic500>;
- #interrupt-cells = <1>;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <213>;
- ti,interrupt-ranges = <0 64 64>,
- <64 448 64>,
- <128 672 64>;
- };
-
- main_udmass_inta: interrupt-controller@33d00000 {
- compatible = "ti,sci-inta";
- reg = <0x0 0x33d00000 0x0 0x100000>;
- interrupt-controller;
- interrupt-parent = <&main_navss_intr>;
- msi-controller;
- #interrupt-cells = <0>;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <209>;
- ti,interrupt-ranges = <0 0 256>;
- };
-
- secure_proxy_main: mailbox@32c00000 {
- compatible = "ti,am654-secure-proxy";
- #mbox-cells = <1>;
- reg-names = "target_data", "rt", "scfg";
- reg = <0x00 0x32c00000 0x00 0x100000>,
- <0x00 0x32400000 0x00 0x100000>,
- <0x00 0x32800000 0x00 0x100000>;
- interrupt-names = "rx_011";
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- smmu0: iommu@36600000 {
- compatible = "arm,smmu-v3";
- reg = <0x0 0x36600000 0x0 0x100000>;
- interrupt-parent = <&gic500>;
- interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "eventq", "gerror";
- #iommu-cells = <1>;
- };
-
- hwspinlock: spinlock@30e00000 {
- compatible = "ti,am654-hwspinlock";
- reg = <0x00 0x30e00000 0x00 0x1000>;
- #hwlock-cells = <1>;
- };
-
- mailbox0_cluster0: mailbox@31f80000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f80000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox0_cluster1: mailbox@31f81000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f81000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox0_cluster2: mailbox@31f82000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f82000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox0_cluster3: mailbox@31f83000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f83000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox0_cluster4: mailbox@31f84000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f84000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox0_cluster5: mailbox@31f85000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f85000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox0_cluster6: mailbox@31f86000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f86000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox0_cluster7: mailbox@31f87000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f87000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox0_cluster8: mailbox@31f88000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f88000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox0_cluster9: mailbox@31f89000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f89000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox0_cluster10: mailbox@31f8a000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f8a000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox0_cluster11: mailbox@31f8b000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f8b000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- main_ringacc: ringacc@3c000000 {
- compatible = "ti,am654-navss-ringacc";
- reg = <0x0 0x3c000000 0x0 0x400000>,
- <0x0 0x38000000 0x0 0x400000>,
- <0x0 0x31120000 0x0 0x100>,
- <0x0 0x33000000 0x0 0x40000>,
- <0x0 0x31080000 0x0 0x40000>;
- reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
- ti,num-rings = <1024>;
- ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <211>;
- msi-parent = <&main_udmass_inta>;
- };
-
- main_udmap: dma-controller@31150000 {
- compatible = "ti,j721e-navss-main-udmap";
- reg = <0x0 0x31150000 0x0 0x100>,
- <0x0 0x34000000 0x0 0x100000>,
- <0x0 0x35000000 0x0 0x100000>;
- reg-names = "gcfg", "rchanrt", "tchanrt";
- msi-parent = <&main_udmass_inta>;
- #dma-cells = <1>;
-
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <212>;
- ti,ringacc = <&main_ringacc>;
-
- ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
- <0x0f>, /* TX_HCHAN */
- <0x10>; /* TX_UHCHAN */
- ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
- <0x0b>, /* RX_HCHAN */
- <0x0c>; /* RX_UHCHAN */
- ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
- };
-
- cpts@310d0000 {
- compatible = "ti,j721e-cpts";
- reg = <0x0 0x310d0000 0x0 0x400>;
- reg-names = "cpts";
- clocks = <&k3_clks 201 1>;
- clock-names = "cpts";
- interrupts-extended = <&main_navss_intr 391>;
- interrupt-names = "cpts";
- ti,cpts-periodic-outputs = <6>;
- ti,cpts-ext-ts-inputs = <8>;
- };
- };
-
- cpsw0: ethernet@c000000 {
- compatible = "ti,j721e-cpswxg-nuss";
- #address-cells = <2>;
- #size-cells = <2>;
- reg = <0x0 0xc000000 0x0 0x200000>;
- reg-names = "cpsw_nuss";
- ranges = <0x0 0x0 0x0 0x0c000000 0x0 0x200000>;
- clocks = <&k3_clks 19 89>;
- clock-names = "fck";
- power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>;
-
- dmas = <&main_udmap 0xca00>,
- <&main_udmap 0xca01>,
- <&main_udmap 0xca02>,
- <&main_udmap 0xca03>,
- <&main_udmap 0xca04>,
- <&main_udmap 0xca05>,
- <&main_udmap 0xca06>,
- <&main_udmap 0xca07>,
- <&main_udmap 0x4a00>;
- dma-names = "tx0", "tx1", "tx2", "tx3",
- "tx4", "tx5", "tx6", "tx7",
- "rx";
-
- status = "disabled";
-
- ethernet-ports {
- #address-cells = <1>;
- #size-cells = <0>;
- cpsw0_port1: port@1 {
- reg = <1>;
- ti,mac-only;
- label = "port1";
- status = "disabled";
- };
-
- cpsw0_port2: port@2 {
- reg = <2>;
- ti,mac-only;
- label = "port2";
- status = "disabled";
- };
-
- cpsw0_port3: port@3 {
- reg = <3>;
- ti,mac-only;
- label = "port3";
- status = "disabled";
- };
-
- cpsw0_port4: port@4 {
- reg = <4>;
- ti,mac-only;
- label = "port4";
- status = "disabled";
- };
-
- cpsw0_port5: port@5 {
- reg = <5>;
- ti,mac-only;
- label = "port5";
- status = "disabled";
- };
-
- cpsw0_port6: port@6 {
- reg = <6>;
- ti,mac-only;
- label = "port6";
- status = "disabled";
- };
-
- cpsw0_port7: port@7 {
- reg = <7>;
- ti,mac-only;
- label = "port7";
- status = "disabled";
- };
-
- cpsw0_port8: port@8 {
- reg = <8>;
- ti,mac-only;
- label = "port8";
- status = "disabled";
- };
- };
-
- cpsw9g_mdio: mdio@f00 {
- compatible = "ti,cpsw-mdio","ti,davinci_mdio";
- reg = <0x0 0xf00 0x0 0x100>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&k3_clks 19 89>;
- clock-names = "fck";
- bus_freq = <1000000>;
- status = "disabled";
- };
-
- cpts@3d000 {
- compatible = "ti,j721e-cpts";
- reg = <0x0 0x3d000 0x0 0x400>;
- clocks = <&k3_clks 19 16>;
- clock-names = "cpts";
- interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cpts";
- ti,cpts-ext-ts-inputs = <4>;
- ti,cpts-periodic-outputs = <2>;
- };
- };
-
- main_crypto: crypto@4e00000 {
- compatible = "ti,j721e-sa2ul";
- reg = <0x0 0x4e00000 0x0 0x1200>;
- power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
-
- dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
- <&main_udmap 0x4001>;
- dma-names = "tx", "rx1", "rx2";
-
- rng: rng@4e10000 {
- compatible = "inside-secure,safexcel-eip76";
- reg = <0x0 0x4e10000 0x0 0x7d>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-
- main_pmx0: pinctrl@11c000 {
- compatible = "pinctrl-single";
- /* Proxy 0 addressing */
- reg = <0x0 0x11c000 0x0 0x2b4>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0xffffffff>;
- };
-
- /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
- main_timerio_input: pinctrl@104200 {
- compatible = "pinctrl-single";
- reg = <0x00 0x104200 0x00 0x50>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x00000007>;
- };
-
- /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
- main_timerio_output: pinctrl@104280 {
- compatible = "pinctrl-single";
- reg = <0x00 0x104280 0x00 0x20>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x0000001f>;
- };
-
- serdes_wiz0: wiz@5000000 {
- compatible = "ti,j721e-wiz-16g";
- #address-cells = <1>;
- #size-cells = <1>;
- power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>;
- clock-names = "fck", "core_ref_clk", "ext_ref_clk";
- assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
- assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
- num-lanes = <2>;
- #reset-cells = <1>;
- ranges = <0x5000000 0x0 0x5000000 0x10000>;
-
- wiz0_pll0_refclk: pll0-refclk {
- clocks = <&k3_clks 292 11>, <&cmn_refclk>;
- #clock-cells = <0>;
- assigned-clocks = <&wiz0_pll0_refclk>;
- assigned-clock-parents = <&k3_clks 292 11>;
- };
-
- wiz0_pll1_refclk: pll1-refclk {
- clocks = <&k3_clks 292 0>, <&cmn_refclk1>;
- #clock-cells = <0>;
- assigned-clocks = <&wiz0_pll1_refclk>;
- assigned-clock-parents = <&k3_clks 292 0>;
- };
-
- wiz0_refclk_dig: refclk-dig {
- clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>;
- #clock-cells = <0>;
- assigned-clocks = <&wiz0_refclk_dig>;
- assigned-clock-parents = <&k3_clks 292 11>;
- };
-
- wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
- clocks = <&wiz0_refclk_dig>;
- #clock-cells = <0>;
- };
-
- wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
- clocks = <&wiz0_pll1_refclk>;
- #clock-cells = <0>;
- };
-
- serdes0: serdes@5000000 {
- compatible = "ti,sierra-phy-t0";
- reg-names = "serdes";
- reg = <0x5000000 0x10000>;
- #address-cells = <1>;
- #size-cells = <0>;
- #clock-cells = <1>;
- resets = <&serdes_wiz0 0>;
- reset-names = "sierra_reset";
- clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>,
- <&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>;
- clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
- "pll0_refclk", "pll1_refclk";
- };
- };
-
- serdes_wiz1: wiz@5010000 {
- compatible = "ti,j721e-wiz-16g";
- #address-cells = <1>;
- #size-cells = <1>;
- power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>;
- clock-names = "fck", "core_ref_clk", "ext_ref_clk";
- assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
- assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
- num-lanes = <2>;
- #reset-cells = <1>;
- ranges = <0x5010000 0x0 0x5010000 0x10000>;
-
- wiz1_pll0_refclk: pll0-refclk {
- clocks = <&k3_clks 293 13>, <&cmn_refclk>;
- #clock-cells = <0>;
- assigned-clocks = <&wiz1_pll0_refclk>;
- assigned-clock-parents = <&k3_clks 293 13>;
- };
-
- wiz1_pll1_refclk: pll1-refclk {
- clocks = <&k3_clks 293 0>, <&cmn_refclk1>;
- #clock-cells = <0>;
- assigned-clocks = <&wiz1_pll1_refclk>;
- assigned-clock-parents = <&k3_clks 293 0>;
- };
-
- wiz1_refclk_dig: refclk-dig {
- clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>;
- #clock-cells = <0>;
- assigned-clocks = <&wiz1_refclk_dig>;
- assigned-clock-parents = <&k3_clks 293 13>;
- };
-
- wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div {
- clocks = <&wiz1_refclk_dig>;
- #clock-cells = <0>;
- };
-
- wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
- clocks = <&wiz1_pll1_refclk>;
- #clock-cells = <0>;
- };
-
- serdes1: serdes@5010000 {
- compatible = "ti,sierra-phy-t0";
- reg-names = "serdes";
- reg = <0x5010000 0x10000>;
- #address-cells = <1>;
- #size-cells = <0>;
- #clock-cells = <1>;
- resets = <&serdes_wiz1 0>;
- reset-names = "sierra_reset";
- clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>,
- <&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>;
- clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
- "pll0_refclk", "pll1_refclk";
- };
- };
-
- serdes_wiz2: wiz@5020000 {
- compatible = "ti,j721e-wiz-16g";
- #address-cells = <1>;
- #size-cells = <1>;
- power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>;
- clock-names = "fck", "core_ref_clk", "ext_ref_clk";
- assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
- assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>;
- num-lanes = <2>;
- #reset-cells = <1>;
- ranges = <0x5020000 0x0 0x5020000 0x10000>;
-
- wiz2_pll0_refclk: pll0-refclk {
- clocks = <&k3_clks 294 11>, <&cmn_refclk>;
- #clock-cells = <0>;
- assigned-clocks = <&wiz2_pll0_refclk>;
- assigned-clock-parents = <&k3_clks 294 11>;
- };
-
- wiz2_pll1_refclk: pll1-refclk {
- clocks = <&k3_clks 294 0>, <&cmn_refclk1>;
- #clock-cells = <0>;
- assigned-clocks = <&wiz2_pll1_refclk>;
- assigned-clock-parents = <&k3_clks 294 0>;
- };
-
- wiz2_refclk_dig: refclk-dig {
- clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>;
- #clock-cells = <0>;
- assigned-clocks = <&wiz2_refclk_dig>;
- assigned-clock-parents = <&k3_clks 294 11>;
- };
-
- wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div {
- clocks = <&wiz2_refclk_dig>;
- #clock-cells = <0>;
- };
-
- wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
- clocks = <&wiz2_pll1_refclk>;
- #clock-cells = <0>;
- };
-
- serdes2: serdes@5020000 {
- compatible = "ti,sierra-phy-t0";
- reg-names = "serdes";
- reg = <0x5020000 0x10000>;
- #address-cells = <1>;
- #size-cells = <0>;
- #clock-cells = <1>;
- resets = <&serdes_wiz2 0>;
- reset-names = "sierra_reset";
- clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>,
- <&wiz2_pll0_refclk>, <&wiz2_pll1_refclk>;
- clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
- "pll0_refclk", "pll1_refclk";
- };
- };
-
- serdes_wiz3: wiz@5030000 {
- compatible = "ti,j721e-wiz-16g";
- #address-cells = <1>;
- #size-cells = <1>;
- power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>;
- clock-names = "fck", "core_ref_clk", "ext_ref_clk";
- assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
- assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
- num-lanes = <2>;
- #reset-cells = <1>;
- ranges = <0x5030000 0x0 0x5030000 0x10000>;
-
- wiz3_pll0_refclk: pll0-refclk {
- clocks = <&k3_clks 295 9>, <&cmn_refclk>;
- #clock-cells = <0>;
- assigned-clocks = <&wiz3_pll0_refclk>;
- assigned-clock-parents = <&k3_clks 295 9>;
- };
-
- wiz3_pll1_refclk: pll1-refclk {
- clocks = <&k3_clks 295 0>, <&cmn_refclk1>;
- #clock-cells = <0>;
- assigned-clocks = <&wiz3_pll1_refclk>;
- assigned-clock-parents = <&k3_clks 295 0>;
- };
-
- wiz3_refclk_dig: refclk-dig {
- clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>;
- #clock-cells = <0>;
- assigned-clocks = <&wiz3_refclk_dig>;
- assigned-clock-parents = <&k3_clks 295 9>;
- };
-
- wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div {
- clocks = <&wiz3_refclk_dig>;
- #clock-cells = <0>;
- };
-
- wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
- clocks = <&wiz3_pll1_refclk>;
- #clock-cells = <0>;
- };
-
- serdes3: serdes@5030000 {
- compatible = "ti,sierra-phy-t0";
- reg-names = "serdes";
- reg = <0x5030000 0x10000>;
- #address-cells = <1>;
- #size-cells = <0>;
- #clock-cells = <1>;
- resets = <&serdes_wiz3 0>;
- reset-names = "sierra_reset";
- clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>,
- <&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>;
- clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
- "pll0_refclk", "pll1_refclk";
- };
- };
-
- pcie0_rc: pcie@2900000 {
- compatible = "ti,j721e-pcie-host";
- reg = <0x00 0x02900000 0x00 0x1000>,
- <0x00 0x02907000 0x00 0x400>,
- <0x00 0x0d000000 0x00 0x00800000>,
- <0x00 0x10000000 0x00 0x00001000>;
- reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
- interrupt-names = "link_state";
- interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
- device_type = "pci";
- ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
- max-link-speed = <3>;
- num-lanes = <2>;
- power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 239 1>;
- clock-names = "fck";
- #address-cells = <3>;
- #size-cells = <2>;
- bus-range = <0x0 0xff>;
- vendor-id = <0x104c>;
- device-id = <0xb00d>;
- msi-map = <0x0 &gic_its 0x0 0x10000>;
- dma-coherent;
- ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
- <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
- dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
- status = "disabled";
- };
-
- pcie1_rc: pcie@2910000 {
- compatible = "ti,j721e-pcie-host";
- reg = <0x00 0x02910000 0x00 0x1000>,
- <0x00 0x02917000 0x00 0x400>,
- <0x00 0x0d800000 0x00 0x00800000>,
- <0x00 0x18000000 0x00 0x00001000>;
- reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
- interrupt-names = "link_state";
- interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
- device_type = "pci";
- ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
- max-link-speed = <3>;
- num-lanes = <2>;
- power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 240 1>;
- clock-names = "fck";
- #address-cells = <3>;
- #size-cells = <2>;
- bus-range = <0x0 0xff>;
- vendor-id = <0x104c>;
- device-id = <0xb00d>;
- msi-map = <0x0 &gic_its 0x10000 0x10000>;
- dma-coherent;
- ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>,
- <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>;
- dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
- status = "disabled";
- };
-
- pcie2_rc: pcie@2920000 {
- compatible = "ti,j721e-pcie-host";
- reg = <0x00 0x02920000 0x00 0x1000>,
- <0x00 0x02927000 0x00 0x400>,
- <0x00 0x0e000000 0x00 0x00800000>,
- <0x44 0x00000000 0x00 0x00001000>;
- reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
- interrupt-names = "link_state";
- interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
- device_type = "pci";
- ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
- max-link-speed = <3>;
- num-lanes = <2>;
- power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 241 1>;
- clock-names = "fck";
- #address-cells = <3>;
- #size-cells = <2>;
- bus-range = <0x0 0xff>;
- vendor-id = <0x104c>;
- device-id = <0xb00d>;
- msi-map = <0x0 &gic_its 0x20000 0x10000>;
- dma-coherent;
- ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
- <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
- dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
- status = "disabled";
- };
-
- pcie3_rc: pcie@2930000 {
- compatible = "ti,j721e-pcie-host";
- reg = <0x00 0x02930000 0x00 0x1000>,
- <0x00 0x02937000 0x00 0x400>,
- <0x00 0x0e800000 0x00 0x00800000>,
- <0x44 0x10000000 0x00 0x00001000>;
- reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
- interrupt-names = "link_state";
- interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
- device_type = "pci";
- ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
- max-link-speed = <3>;
- num-lanes = <2>;
- power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 242 1>;
- clock-names = "fck";
- #address-cells = <3>;
- #size-cells = <2>;
- bus-range = <0x0 0xff>;
- vendor-id = <0x104c>;
- device-id = <0xb00d>;
- msi-map = <0x0 &gic_its 0x30000 0x10000>;
- dma-coherent;
- ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,
- <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;
- dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
- status = "disabled";
- };
-
- serdes_wiz4: wiz@5050000 {
- compatible = "ti,am64-wiz-10g";
- #address-cells = <1>;
- #size-cells = <1>;
- power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>;
- clock-names = "fck", "core_ref_clk", "ext_ref_clk";
- assigned-clocks = <&k3_clks 297 9>;
- assigned-clock-parents = <&k3_clks 297 10>;
- assigned-clock-rates = <19200000>;
- num-lanes = <4>;
- #reset-cells = <1>;
- #clock-cells = <1>;
- ranges = <0x05050000 0x00 0x05050000 0x010000>,
- <0x0a030a00 0x00 0x0a030a00 0x40>;
-
- serdes4: serdes@5050000 {
- /*
- * Note: we also map DPTX PHY registers as the Torrent
- * needs to manage those.
- */
- compatible = "ti,j721e-serdes-10g";
- reg = <0x05050000 0x010000>,
- <0x0a030a00 0x40>; /* DPTX PHY */
- reg-names = "torrent_phy", "dptx_phy";
-
- resets = <&serdes_wiz4 0>;
- reset-names = "torrent_reset";
- clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>;
- clock-names = "refclk";
- assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
- <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>,
- <&serdes_wiz4 TI_WIZ_REFCLK_DIG>;
- assigned-clock-parents = <&k3_clks 297 9>,
- <&k3_clks 297 9>,
- <&k3_clks 297 9>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-
- main_timer0: timer@2400000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2400000 0x00 0x400>;
- interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 49 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 49 1>;
- assigned-clock-parents = <&k3_clks 49 2>;
- power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer1: timer@2410000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2410000 0x00 0x400>;
- interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 50 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 50 1>, <&k3_clks 327 0>;
- assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 327 1>;
- power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer2: timer@2420000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2420000 0x00 0x400>;
- interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 51 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 51 1>;
- assigned-clock-parents = <&k3_clks 51 2>;
- power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer3: timer@2430000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2430000 0x00 0x400>;
- interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 52 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 52 1>, <&k3_clks 328 0>;
- assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 328 1>;
- power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer4: timer@2440000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2440000 0x00 0x400>;
- interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 53 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 53 1>;
- assigned-clock-parents = <&k3_clks 53 2>;
- power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer5: timer@2450000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2450000 0x00 0x400>;
- interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 54 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 54 1>, <&k3_clks 329 0>;
- assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 329 1>;
- power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer6: timer@2460000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2460000 0x00 0x400>;
- interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 55 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 55 1>;
- assigned-clock-parents = <&k3_clks 55 2>;
- power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer7: timer@2470000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2470000 0x00 0x400>;
- interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 57 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 57 1>, <&k3_clks 330 0>;
- assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 330 1>;
- power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer8: timer@2480000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2480000 0x00 0x400>;
- interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 58 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 58 1>;
- assigned-clock-parents = <&k3_clks 58 2>;
- power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer9: timer@2490000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2490000 0x00 0x400>;
- interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 59 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 59 1>, <&k3_clks 331 0>;
- assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 331 1>;
- power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer10: timer@24a0000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x24a0000 0x00 0x400>;
- interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 60 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 60 1>;
- assigned-clock-parents = <&k3_clks 60 2>;
- power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer11: timer@24b0000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x24b0000 0x00 0x400>;
- interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 62 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 62 1>, <&k3_clks 332 0>;
- assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 332 1>;
- power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer12: timer@24c0000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x24c0000 0x00 0x400>;
- interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 63 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 63 1>;
- assigned-clock-parents = <&k3_clks 63 2>;
- power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer13: timer@24d0000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x24d0000 0x00 0x400>;
- interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 64 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 64 1>, <&k3_clks 333 0>;
- assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 333 1>;
- power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer14: timer@24e0000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x24e0000 0x00 0x400>;
- interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 65 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 65 1>;
- assigned-clock-parents = <&k3_clks 65 2>;
- power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer15: timer@24f0000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x24f0000 0x00 0x400>;
- interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 66 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 66 1>, <&k3_clks 334 0>;
- assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 334 1>;
- power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer16: timer@2500000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2500000 0x00 0x400>;
- interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 67 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 67 1>;
- assigned-clock-parents = <&k3_clks 67 2>;
- power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer17: timer@2510000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2510000 0x00 0x400>;
- interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 68 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 68 1>, <&k3_clks 335 0>;
- assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 335 1>;
- power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer18: timer@2520000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2520000 0x00 0x400>;
- interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 69 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 69 1>;
- assigned-clock-parents = <&k3_clks 69 2>;
- power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer19: timer@2530000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2530000 0x00 0x400>;
- interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 70 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 70 1>, <&k3_clks 336 0>;
- assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 336 1>;
- power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_uart0: serial@2800000 {
- compatible = "ti,j721e-uart", "ti,am654-uart";
- reg = <0x00 0x02800000 0x00 0x100>;
- interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- current-speed = <115200>;
- power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 146 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart1: serial@2810000 {
- compatible = "ti,j721e-uart", "ti,am654-uart";
- reg = <0x00 0x02810000 0x00 0x100>;
- interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- current-speed = <115200>;
- power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 278 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart2: serial@2820000 {
- compatible = "ti,j721e-uart", "ti,am654-uart";
- reg = <0x00 0x02820000 0x00 0x100>;
- interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- current-speed = <115200>;
- power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 279 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart3: serial@2830000 {
- compatible = "ti,j721e-uart", "ti,am654-uart";
- reg = <0x00 0x02830000 0x00 0x100>;
- interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- current-speed = <115200>;
- power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 280 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart4: serial@2840000 {
- compatible = "ti,j721e-uart", "ti,am654-uart";
- reg = <0x00 0x02840000 0x00 0x100>;
- interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- current-speed = <115200>;
- power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 281 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart5: serial@2850000 {
- compatible = "ti,j721e-uart", "ti,am654-uart";
- reg = <0x00 0x02850000 0x00 0x100>;
- interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- current-speed = <115200>;
- power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 282 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart6: serial@2860000 {
- compatible = "ti,j721e-uart", "ti,am654-uart";
- reg = <0x00 0x02860000 0x00 0x100>;
- interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- current-speed = <115200>;
- power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 283 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart7: serial@2870000 {
- compatible = "ti,j721e-uart", "ti,am654-uart";
- reg = <0x00 0x02870000 0x00 0x100>;
- interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- current-speed = <115200>;
- power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 284 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart8: serial@2880000 {
- compatible = "ti,j721e-uart", "ti,am654-uart";
- reg = <0x00 0x02880000 0x00 0x100>;
- interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- current-speed = <115200>;
- power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 285 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart9: serial@2890000 {
- compatible = "ti,j721e-uart", "ti,am654-uart";
- reg = <0x00 0x02890000 0x00 0x100>;
- interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- current-speed = <115200>;
- power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 286 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_gpio0: gpio@600000 {
- compatible = "ti,j721e-gpio", "ti,keystone-gpio";
- reg = <0x0 0x00600000 0x0 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&main_gpio_intr>;
- interrupts = <256>, <257>, <258>, <259>,
- <260>, <261>, <262>, <263>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <128>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 105 0>;
- clock-names = "gpio";
- status = "disabled";
- };
-
- main_gpio1: gpio@601000 {
- compatible = "ti,j721e-gpio", "ti,keystone-gpio";
- reg = <0x0 0x00601000 0x0 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&main_gpio_intr>;
- interrupts = <288>, <289>, <290>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <36>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 106 0>;
- clock-names = "gpio";
- status = "disabled";
- };
-
- main_gpio2: gpio@610000 {
- compatible = "ti,j721e-gpio", "ti,keystone-gpio";
- reg = <0x0 0x00610000 0x0 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&main_gpio_intr>;
- interrupts = <264>, <265>, <266>, <267>,
- <268>, <269>, <270>, <271>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <128>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 107 0>;
- clock-names = "gpio";
- status = "disabled";
- };
-
- main_gpio3: gpio@611000 {
- compatible = "ti,j721e-gpio", "ti,keystone-gpio";
- reg = <0x0 0x00611000 0x0 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&main_gpio_intr>;
- interrupts = <292>, <293>, <294>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <36>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 108 0>;
- clock-names = "gpio";
- status = "disabled";
- };
-
- main_gpio4: gpio@620000 {
- compatible = "ti,j721e-gpio", "ti,keystone-gpio";
- reg = <0x0 0x00620000 0x0 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&main_gpio_intr>;
- interrupts = <272>, <273>, <274>, <275>,
- <276>, <277>, <278>, <279>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <128>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 109 0>;
- clock-names = "gpio";
- status = "disabled";
- };
-
- main_gpio5: gpio@621000 {
- compatible = "ti,j721e-gpio", "ti,keystone-gpio";
- reg = <0x0 0x00621000 0x0 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&main_gpio_intr>;
- interrupts = <296>, <297>, <298>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <36>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 110 0>;
- clock-names = "gpio";
- status = "disabled";
- };
-
- main_gpio6: gpio@630000 {
- compatible = "ti,j721e-gpio", "ti,keystone-gpio";
- reg = <0x0 0x00630000 0x0 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&main_gpio_intr>;
- interrupts = <280>, <281>, <282>, <283>,
- <284>, <285>, <286>, <287>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <128>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 111 0>;
- clock-names = "gpio";
- status = "disabled";
- };
-
- main_gpio7: gpio@631000 {
- compatible = "ti,j721e-gpio", "ti,keystone-gpio";
- reg = <0x0 0x00631000 0x0 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&main_gpio_intr>;
- interrupts = <300>, <301>, <302>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <36>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 112 0>;
- clock-names = "gpio";
- status = "disabled";
- };
-
- main_sdhci0: mmc@4f80000 {
- compatible = "ti,j721e-sdhci-8bit";
- reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
- interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
- clock-names = "clk_ahb", "clk_xin";
- clocks = <&k3_clks 91 0>, <&k3_clks 91 1>;
- assigned-clocks = <&k3_clks 91 1>;
- assigned-clock-parents = <&k3_clks 91 2>;
- bus-width = <8>;
- mmc-hs200-1_8v;
- mmc-ddr-1_8v;
- ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-mmc-hs = <0x0>;
- ti,otap-del-sel-ddr52 = <0x5>;
- ti,otap-del-sel-hs200 = <0x6>;
- ti,otap-del-sel-hs400 = <0x0>;
- ti,itap-del-sel-legacy = <0x10>;
- ti,itap-del-sel-mmc-hs = <0xa>;
- ti,itap-del-sel-ddr52 = <0x3>;
- ti,trm-icp = <0x8>;
- dma-coherent;
- status = "disabled";
- };
-
- main_sdhci1: mmc@4fb0000 {
- compatible = "ti,j721e-sdhci-4bit";
- reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
- clock-names = "clk_ahb", "clk_xin";
- clocks = <&k3_clks 92 5>, <&k3_clks 92 0>;
- assigned-clocks = <&k3_clks 92 0>;
- assigned-clock-parents = <&k3_clks 92 1>;
- ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-sd-hs = <0x0>;
- ti,otap-del-sel-sdr12 = <0xf>;
- ti,otap-del-sel-sdr25 = <0xf>;
- ti,otap-del-sel-sdr50 = <0xc>;
- ti,otap-del-sel-ddr50 = <0xc>;
- ti,otap-del-sel-sdr104 = <0x5>;
- ti,itap-del-sel-legacy = <0x0>;
- ti,itap-del-sel-sd-hs = <0x0>;
- ti,itap-del-sel-sdr12 = <0x0>;
- ti,itap-del-sel-sdr25 = <0x0>;
- ti,itap-del-sel-ddr50 = <0x2>;
- ti,trm-icp = <0x8>;
- ti,clkbuf-sel = <0x7>;
- dma-coherent;
- sdhci-caps-mask = <0x2 0x0>;
- status = "disabled";
- };
-
- main_sdhci2: mmc@4f98000 {
- compatible = "ti,j721e-sdhci-4bit";
- reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>;
- interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
- clock-names = "clk_ahb", "clk_xin";
- clocks = <&k3_clks 93 5>, <&k3_clks 93 0>;
- assigned-clocks = <&k3_clks 93 0>;
- assigned-clock-parents = <&k3_clks 93 1>;
- ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-sd-hs = <0x0>;
- ti,otap-del-sel-sdr12 = <0xf>;
- ti,otap-del-sel-sdr25 = <0xf>;
- ti,otap-del-sel-sdr50 = <0xc>;
- ti,otap-del-sel-ddr50 = <0xc>;
- ti,otap-del-sel-sdr104 = <0x5>;
- ti,itap-del-sel-legacy = <0x0>;
- ti,itap-del-sel-sd-hs = <0x0>;
- ti,itap-del-sel-sdr12 = <0x0>;
- ti,itap-del-sel-sdr25 = <0x0>;
- ti,itap-del-sel-ddr50 = <0x2>;
- ti,trm-icp = <0x8>;
- ti,clkbuf-sel = <0x7>;
- dma-coherent;
- sdhci-caps-mask = <0x2 0x0>;
- status = "disabled";
- };
-
- usbss0: cdns-usb@4104000 {
- compatible = "ti,j721e-usb";
- reg = <0x00 0x4104000 0x00 0x100>;
- dma-coherent;
- power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
- clock-names = "ref", "lpm";
- assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */
- assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- usb0: usb@6000000 {
- compatible = "cdns,usb3";
- reg = <0x00 0x6000000 0x00 0x10000>,
- <0x00 0x6010000 0x00 0x10000>,
- <0x00 0x6020000 0x00 0x10000>;
- reg-names = "otg", "xhci", "dev";
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
- <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
- <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
- interrupt-names = "host",
- "peripheral",
- "otg";
- maximum-speed = "super-speed";
- dr_mode = "otg";
- };
- };
-
- usbss1: cdns-usb@4114000 {
- compatible = "ti,j721e-usb";
- reg = <0x00 0x4114000 0x00 0x100>;
- dma-coherent;
- power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 289 15>, <&k3_clks 289 3>;
- clock-names = "ref", "lpm";
- assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */
- assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- usb1: usb@6400000 {
- compatible = "cdns,usb3";
- reg = <0x00 0x6400000 0x00 0x10000>,
- <0x00 0x6410000 0x00 0x10000>,
- <0x00 0x6420000 0x00 0x10000>;
- reg-names = "otg", "xhci", "dev";
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
- <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
- <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
- interrupt-names = "host",
- "peripheral",
- "otg";
- maximum-speed = "super-speed";
- dr_mode = "otg";
- };
- };
-
- main_i2c0: i2c@2000000 {
- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x0 0x2000000 0x0 0x100>;
- interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "fck";
- clocks = <&k3_clks 187 0>;
- power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
- status = "disabled";
- };
-
- main_i2c1: i2c@2010000 {
- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x0 0x2010000 0x0 0x100>;
- interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "fck";
- clocks = <&k3_clks 188 0>;
- power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- main_i2c2: i2c@2020000 {
- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x0 0x2020000 0x0 0x100>;
- interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "fck";
- clocks = <&k3_clks 189 0>;
- power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- main_i2c3: i2c@2030000 {
- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x0 0x2030000 0x0 0x100>;
- interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "fck";
- clocks = <&k3_clks 190 0>;
- power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- main_i2c4: i2c@2040000 {
- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x0 0x2040000 0x0 0x100>;
- interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "fck";
- clocks = <&k3_clks 191 0>;
- power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- main_i2c5: i2c@2050000 {
- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x0 0x2050000 0x0 0x100>;
- interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "fck";
- clocks = <&k3_clks 192 0>;
- power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- main_i2c6: i2c@2060000 {
- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x0 0x2060000 0x0 0x100>;
- interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "fck";
- clocks = <&k3_clks 193 0>;
- power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- ufs_wrapper: ufs-wrapper@4e80000 {
- compatible = "ti,j721e-ufs";
- reg = <0x0 0x4e80000 0x0 0x100>;
- power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 277 1>;
- assigned-clocks = <&k3_clks 277 1>;
- assigned-clock-parents = <&k3_clks 277 4>;
- ranges;
- #address-cells = <2>;
- #size-cells = <2>;
-
- ufs@4e84000 {
- compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
- reg = <0x0 0x4e84000 0x0 0x10000>;
- interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>;
- clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>;
- clock-names = "core_clk", "phy_clk", "ref_clk";
- dma-coherent;
- };
- };
-
- mhdp: dp-bridge@a000000 {
- compatible = "ti,j721e-mhdp8546";
- /*
- * Note: we do not map DPTX PHY area, as that is handled by
- * the PHY driver.
- */
- reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */
- <0x00 0x04f40000 0x00 0x20>; /* DSS_EDP0_INTG_CFG_VP */
- reg-names = "mhdptx", "j721e-intg";
-
- clocks = <&k3_clks 151 36>;
-
- interrupt-parent = <&gic500>;
- interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
-
- power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
-
- dp0_ports: ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- };
-
- port@4 {
- reg = <4>;
- };
- };
- };
-
- dss: dss@4a00000 {
- compatible = "ti,j721e-dss";
- reg =
- <0x00 0x04a00000 0x00 0x10000>, /* common_m */
- <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
- <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
- <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
-
- <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
- <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
- <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
- <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
-
- <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
- <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
- <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
- <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
-
- <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
- <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
- <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
- <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
- <0x00 0x04af0000 0x00 0x10000>; /* wb */
-
- reg-names = "common_m", "common_s0",
- "common_s1", "common_s2",
- "vidl1", "vidl2","vid1","vid2",
- "ovr1", "ovr2", "ovr3", "ovr4",
- "vp1", "vp2", "vp3", "vp4",
- "wb";
-
- clocks = <&k3_clks 152 0>,
- <&k3_clks 152 1>,
- <&k3_clks 152 4>,
- <&k3_clks 152 9>,
- <&k3_clks 152 13>;
- clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
-
- power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
-
- interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "common_m",
- "common_s0",
- "common_s1",
- "common_s2";
-
- dss_ports: ports {
- };
- };
-
- mcasp0: mcasp@2b00000 {
- compatible = "ti,am33xx-mcasp-audio";
- reg = <0x0 0x02b00000 0x0 0x2000>,
- <0x0 0x02b08000 0x0 0x1000>;
- reg-names = "mpu","dat";
- interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx", "rx";
-
- dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
- dma-names = "tx", "rx";
-
- clocks = <&k3_clks 174 1>;
- clock-names = "fck";
- power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- mcasp1: mcasp@2b10000 {
- compatible = "ti,am33xx-mcasp-audio";
- reg = <0x0 0x02b10000 0x0 0x2000>,
- <0x0 0x02b18000 0x0 0x1000>;
- reg-names = "mpu","dat";
- interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx", "rx";
-
- dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
- dma-names = "tx", "rx";
-
- clocks = <&k3_clks 175 1>;
- clock-names = "fck";
- power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- mcasp2: mcasp@2b20000 {
- compatible = "ti,am33xx-mcasp-audio";
- reg = <0x0 0x02b20000 0x0 0x2000>,
- <0x0 0x02b28000 0x0 0x1000>;
- reg-names = "mpu","dat";
- interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx", "rx";
-
- dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
- dma-names = "tx", "rx";
-
- clocks = <&k3_clks 176 1>;
- clock-names = "fck";
- power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- mcasp3: mcasp@2b30000 {
- compatible = "ti,am33xx-mcasp-audio";
- reg = <0x0 0x02b30000 0x0 0x2000>,
- <0x0 0x02b38000 0x0 0x1000>;
- reg-names = "mpu","dat";
- interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx", "rx";
-
- dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
- dma-names = "tx", "rx";
-
- clocks = <&k3_clks 177 1>;
- clock-names = "fck";
- power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- mcasp4: mcasp@2b40000 {
- compatible = "ti,am33xx-mcasp-audio";
- reg = <0x0 0x02b40000 0x0 0x2000>,
- <0x0 0x02b48000 0x0 0x1000>;
- reg-names = "mpu","dat";
- interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx", "rx";
-
- dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>;
- dma-names = "tx", "rx";
-
- clocks = <&k3_clks 178 1>;
- clock-names = "fck";
- power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- mcasp5: mcasp@2b50000 {
- compatible = "ti,am33xx-mcasp-audio";
- reg = <0x0 0x02b50000 0x0 0x2000>,
- <0x0 0x02b58000 0x0 0x1000>;
- reg-names = "mpu","dat";
- interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx", "rx";
-
- dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>;
- dma-names = "tx", "rx";
-
- clocks = <&k3_clks 179 1>;
- clock-names = "fck";
- power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- mcasp6: mcasp@2b60000 {
- compatible = "ti,am33xx-mcasp-audio";
- reg = <0x0 0x02b60000 0x0 0x2000>,
- <0x0 0x02b68000 0x0 0x1000>;
- reg-names = "mpu","dat";
- interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx", "rx";
-
- dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>;
- dma-names = "tx", "rx";
-
- clocks = <&k3_clks 180 1>;
- clock-names = "fck";
- power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- mcasp7: mcasp@2b70000 {
- compatible = "ti,am33xx-mcasp-audio";
- reg = <0x0 0x02b70000 0x0 0x2000>,
- <0x0 0x02b78000 0x0 0x1000>;
- reg-names = "mpu","dat";
- interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx", "rx";
-
- dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>;
- dma-names = "tx", "rx";
-
- clocks = <&k3_clks 181 1>;
- clock-names = "fck";
- power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- mcasp8: mcasp@2b80000 {
- compatible = "ti,am33xx-mcasp-audio";
- reg = <0x0 0x02b80000 0x0 0x2000>,
- <0x0 0x02b88000 0x0 0x1000>;
- reg-names = "mpu","dat";
- interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx", "rx";
-
- dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>;
- dma-names = "tx", "rx";
-
- clocks = <&k3_clks 182 1>;
- clock-names = "fck";
- power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- mcasp9: mcasp@2b90000 {
- compatible = "ti,am33xx-mcasp-audio";
- reg = <0x0 0x02b90000 0x0 0x2000>,
- <0x0 0x02b98000 0x0 0x1000>;
- reg-names = "mpu","dat";
- interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx", "rx";
-
- dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>;
- dma-names = "tx", "rx";
-
- clocks = <&k3_clks 183 1>;
- clock-names = "fck";
- power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- mcasp10: mcasp@2ba0000 {
- compatible = "ti,am33xx-mcasp-audio";
- reg = <0x0 0x02ba0000 0x0 0x2000>,
- <0x0 0x02ba8000 0x0 0x1000>;
- reg-names = "mpu","dat";
- interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx", "rx";
-
- dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>;
- dma-names = "tx", "rx";
-
- clocks = <&k3_clks 184 1>;
- clock-names = "fck";
- power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- mcasp11: mcasp@2bb0000 {
- compatible = "ti,am33xx-mcasp-audio";
- reg = <0x0 0x02bb0000 0x0 0x2000>,
- <0x0 0x02bb8000 0x0 0x1000>;
- reg-names = "mpu","dat";
- interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx", "rx";
-
- dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>;
- dma-names = "tx", "rx";
-
- clocks = <&k3_clks 185 1>;
- clock-names = "fck";
- power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- watchdog0: watchdog@2200000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x0 0x2200000 0x0 0x100>;
- clocks = <&k3_clks 252 1>;
- power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 252 1>;
- assigned-clock-parents = <&k3_clks 252 5>;
- };
-
- watchdog1: watchdog@2210000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x0 0x2210000 0x0 0x100>;
- clocks = <&k3_clks 253 1>;
- power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 253 1>;
- assigned-clock-parents = <&k3_clks 253 5>;
- };
-
- main_r5fss0: r5fss@5c00000 {
- compatible = "ti,j721e-r5fss";
- ti,cluster-mode = <1>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
- <0x5d00000 0x00 0x5d00000 0x20000>;
- power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
-
- main_r5fss0_core0: r5f@5c00000 {
- compatible = "ti,j721e-r5f";
- reg = <0x5c00000 0x00008000>,
- <0x5c10000 0x00008000>;
- reg-names = "atcm", "btcm";
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <245>;
- ti,sci-proc-ids = <0x06 0xff>;
- resets = <&k3_reset 245 1>;
- firmware-name = "j7-main-r5f0_0-fw";
- ti,atcm-enable = <1>;
- ti,btcm-enable = <1>;
- ti,loczrama = <1>;
- };
-
- main_r5fss0_core1: r5f@5d00000 {
- compatible = "ti,j721e-r5f";
- reg = <0x5d00000 0x00008000>,
- <0x5d10000 0x00008000>;
- reg-names = "atcm", "btcm";
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <246>;
- ti,sci-proc-ids = <0x07 0xff>;
- resets = <&k3_reset 246 1>;
- firmware-name = "j7-main-r5f0_1-fw";
- ti,atcm-enable = <1>;
- ti,btcm-enable = <1>;
- ti,loczrama = <1>;
- };
- };
-
- main_r5fss1: r5fss@5e00000 {
- compatible = "ti,j721e-r5fss";
- ti,cluster-mode = <1>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
- <0x5f00000 0x00 0x5f00000 0x20000>;
- power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>;
-
- main_r5fss1_core0: r5f@5e00000 {
- compatible = "ti,j721e-r5f";
- reg = <0x5e00000 0x00008000>,
- <0x5e10000 0x00008000>;
- reg-names = "atcm", "btcm";
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <247>;
- ti,sci-proc-ids = <0x08 0xff>;
- resets = <&k3_reset 247 1>;
- firmware-name = "j7-main-r5f1_0-fw";
- ti,atcm-enable = <1>;
- ti,btcm-enable = <1>;
- ti,loczrama = <1>;
- };
-
- main_r5fss1_core1: r5f@5f00000 {
- compatible = "ti,j721e-r5f";
- reg = <0x5f00000 0x00008000>,
- <0x5f10000 0x00008000>;
- reg-names = "atcm", "btcm";
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <248>;
- ti,sci-proc-ids = <0x09 0xff>;
- resets = <&k3_reset 248 1>;
- firmware-name = "j7-main-r5f1_1-fw";
- ti,atcm-enable = <1>;
- ti,btcm-enable = <1>;
- ti,loczrama = <1>;
- };
- };
-
- c66_0: dsp@4d80800000 {
- compatible = "ti,j721e-c66-dsp";
- reg = <0x4d 0x80800000 0x00 0x00048000>,
- <0x4d 0x80e00000 0x00 0x00008000>,
- <0x4d 0x80f00000 0x00 0x00008000>;
- reg-names = "l2sram", "l1pram", "l1dram";
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <142>;
- ti,sci-proc-ids = <0x03 0xff>;
- resets = <&k3_reset 142 1>;
- firmware-name = "j7-c66_0-fw";
- status = "disabled";
- };
-
- c66_1: dsp@4d81800000 {
- compatible = "ti,j721e-c66-dsp";
- reg = <0x4d 0x81800000 0x00 0x00048000>,
- <0x4d 0x81e00000 0x00 0x00008000>,
- <0x4d 0x81f00000 0x00 0x00008000>;
- reg-names = "l2sram", "l1pram", "l1dram";
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <143>;
- ti,sci-proc-ids = <0x04 0xff>;
- resets = <&k3_reset 143 1>;
- firmware-name = "j7-c66_1-fw";
- status = "disabled";
- };
-
- c71_0: dsp@64800000 {
- compatible = "ti,j721e-c71-dsp";
- reg = <0x00 0x64800000 0x00 0x00080000>,
- <0x00 0x64e00000 0x00 0x0000c000>;
- reg-names = "l2sram", "l1dram";
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <15>;
- ti,sci-proc-ids = <0x30 0xff>;
- resets = <&k3_reset 15 1>;
- firmware-name = "j7-c71_0-fw";
- status = "disabled";
- };
-
- icssg0: icssg@b000000 {
- compatible = "ti,j721e-icssg";
- reg = <0x00 0xb000000 0x00 0x80000>;
- power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x00 0x0b000000 0x100000>;
-
- icssg0_mem: memories@0 {
- reg = <0x0 0x2000>,
- <0x2000 0x2000>,
- <0x10000 0x10000>;
- reg-names = "dram0", "dram1",
- "shrdram2";
- };
-
- icssg0_cfg: cfg@26000 {
- compatible = "ti,pruss-cfg", "syscon";
- reg = <0x26000 0x200>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x26000 0x2000>;
-
- clocks {
- #address-cells = <1>;
- #size-cells = <0>;
-
- icssg0_coreclk_mux: coreclk-mux@3c {
- reg = <0x3c>;
- #clock-cells = <0>;
- clocks = <&k3_clks 119 24>, /* icssg0_core_clk */
- <&k3_clks 119 1>; /* icssg0_iclk */
- assigned-clocks = <&icssg0_coreclk_mux>;
- assigned-clock-parents = <&k3_clks 119 1>;
- };
-
- icssg0_iepclk_mux: iepclk-mux@30 {
- reg = <0x30>;
- #clock-cells = <0>;
- clocks = <&k3_clks 119 3>, /* icssg0_iep_clk */
- <&icssg0_coreclk_mux>; /* core_clk */
- assigned-clocks = <&icssg0_iepclk_mux>;
- assigned-clock-parents = <&icssg0_coreclk_mux>;
- };
- };
- };
-
- icssg0_mii_rt: mii-rt@32000 {
- compatible = "ti,pruss-mii", "syscon";
- reg = <0x32000 0x100>;
- };
-
- icssg0_mii_g_rt: mii-g-rt@33000 {
- compatible = "ti,pruss-mii-g", "syscon";
- reg = <0x33000 0x1000>;
- };
-
- icssg0_intc: interrupt-controller@20000 {
- compatible = "ti,icssg-intc";
- reg = <0x20000 0x2000>;
- interrupt-controller;
- #interrupt-cells = <3>;
- interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "host_intr0", "host_intr1",
- "host_intr2", "host_intr3",
- "host_intr4", "host_intr5",
- "host_intr6", "host_intr7";
- };
-
- pru0_0: pru@34000 {
- compatible = "ti,j721e-pru";
- reg = <0x34000 0x3000>,
- <0x22000 0x100>,
- <0x22400 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "j7-pru0_0-fw";
- };
-
- rtu0_0: rtu@4000 {
- compatible = "ti,j721e-rtu";
- reg = <0x4000 0x2000>,
- <0x23000 0x100>,
- <0x23400 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "j7-rtu0_0-fw";
- };
-
- tx_pru0_0: txpru@a000 {
- compatible = "ti,j721e-tx-pru";
- reg = <0xa000 0x1800>,
- <0x25000 0x100>,
- <0x25400 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "j7-txpru0_0-fw";
- };
-
- pru0_1: pru@38000 {
- compatible = "ti,j721e-pru";
- reg = <0x38000 0x3000>,
- <0x24000 0x100>,
- <0x24400 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "j7-pru0_1-fw";
- };
-
- rtu0_1: rtu@6000 {
- compatible = "ti,j721e-rtu";
- reg = <0x6000 0x2000>,
- <0x23800 0x100>,
- <0x23c00 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "j7-rtu0_1-fw";
- };
-
- tx_pru0_1: txpru@c000 {
- compatible = "ti,j721e-tx-pru";
- reg = <0xc000 0x1800>,
- <0x25800 0x100>,
- <0x25c00 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "j7-txpru0_1-fw";
- };
-
- icssg0_mdio: mdio@32400 {
- compatible = "ti,davinci_mdio";
- reg = <0x32400 0x100>;
- clocks = <&k3_clks 119 1>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <0>;
- bus_freq = <1000000>;
- status = "disabled";
- };
- };
-
- icssg1: icssg@b100000 {
- compatible = "ti,j721e-icssg";
- reg = <0x00 0xb100000 0x00 0x80000>;
- power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x00 0x0b100000 0x100000>;
-
- icssg1_mem: memories@b100000 {
- reg = <0x0 0x2000>,
- <0x2000 0x2000>,
- <0x10000 0x10000>;
- reg-names = "dram0", "dram1",
- "shrdram2";
- };
-
- icssg1_cfg: cfg@26000 {
- compatible = "ti,pruss-cfg", "syscon";
- reg = <0x26000 0x200>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x26000 0x2000>;
-
- clocks {
- #address-cells = <1>;
- #size-cells = <0>;
-
- icssg1_coreclk_mux: coreclk-mux@3c {
- reg = <0x3c>;
- #clock-cells = <0>;
- clocks = <&k3_clks 120 54>, /* icssg1_core_clk */
- <&k3_clks 120 4>; /* icssg1_iclk */
- assigned-clocks = <&icssg1_coreclk_mux>;
- assigned-clock-parents = <&k3_clks 120 4>;
- };
-
- icssg1_iepclk_mux: iepclk-mux@30 {
- reg = <0x30>;
- #clock-cells = <0>;
- clocks = <&k3_clks 120 9>, /* icssg1_iep_clk */
- <&icssg1_coreclk_mux>; /* core_clk */
- assigned-clocks = <&icssg1_iepclk_mux>;
- assigned-clock-parents = <&icssg1_coreclk_mux>;
- };
- };
- };
-
- icssg1_mii_rt: mii-rt@32000 {
- compatible = "ti,pruss-mii", "syscon";
- reg = <0x32000 0x100>;
- };
-
- icssg1_mii_g_rt: mii-g-rt@33000 {
- compatible = "ti,pruss-mii-g", "syscon";
- reg = <0x33000 0x1000>;
- };
-
- icssg1_intc: interrupt-controller@20000 {
- compatible = "ti,icssg-intc";
- reg = <0x20000 0x2000>;
- interrupt-controller;
- #interrupt-cells = <3>;
- interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "host_intr0", "host_intr1",
- "host_intr2", "host_intr3",
- "host_intr4", "host_intr5",
- "host_intr6", "host_intr7";
- };
-
- pru1_0: pru@34000 {
- compatible = "ti,j721e-pru";
- reg = <0x34000 0x4000>,
- <0x22000 0x100>,
- <0x22400 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "j7-pru1_0-fw";
- };
-
- rtu1_0: rtu@4000 {
- compatible = "ti,j721e-rtu";
- reg = <0x4000 0x2000>,
- <0x23000 0x100>,
- <0x23400 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "j7-rtu1_0-fw";
- };
-
- tx_pru1_0: txpru@a000 {
- compatible = "ti,j721e-tx-pru";
- reg = <0xa000 0x1800>,
- <0x25000 0x100>,
- <0x25400 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "j7-txpru1_0-fw";
- };
-
- pru1_1: pru@38000 {
- compatible = "ti,j721e-pru";
- reg = <0x38000 0x4000>,
- <0x24000 0x100>,
- <0x24400 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "j7-pru1_1-fw";
- };
-
- rtu1_1: rtu@6000 {
- compatible = "ti,j721e-rtu";
- reg = <0x6000 0x2000>,
- <0x23800 0x100>,
- <0x23c00 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "j7-rtu1_1-fw";
- };
-
- tx_pru1_1: txpru@c000 {
- compatible = "ti,j721e-tx-pru";
- reg = <0xc000 0x1800>,
- <0x25800 0x100>,
- <0x25c00 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "j7-txpru1_1-fw";
- };
-
- icssg1_mdio: mdio@32400 {
- compatible = "ti,davinci_mdio";
- reg = <0x32400 0x100>;
- clocks = <&k3_clks 120 4>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <0>;
- bus_freq = <1000000>;
- status = "disabled";
- };
- };
-
- main_mcan0: can@2701000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x02701000 0x00 0x200>,
- <0x00 0x02708000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 156 0>, <&k3_clks 156 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- main_mcan1: can@2711000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x02711000 0x00 0x200>,
- <0x00 0x02718000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 158 0>, <&k3_clks 158 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- main_mcan2: can@2721000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x02721000 0x00 0x200>,
- <0x00 0x02728000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 160 0>, <&k3_clks 160 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- main_mcan3: can@2731000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x02731000 0x00 0x200>,
- <0x00 0x02738000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 161 0>, <&k3_clks 161 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- main_mcan4: can@2741000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x02741000 0x00 0x200>,
- <0x00 0x02748000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 162 0>, <&k3_clks 162 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- main_mcan5: can@2751000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x02751000 0x00 0x200>,
- <0x00 0x02758000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 163 0>, <&k3_clks 163 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- main_mcan6: can@2761000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x02761000 0x00 0x200>,
- <0x00 0x02768000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 164 0>, <&k3_clks 164 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- main_mcan7: can@2771000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x02771000 0x00 0x200>,
- <0x00 0x02778000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 165 0>, <&k3_clks 165 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- main_mcan8: can@2781000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x02781000 0x00 0x200>,
- <0x00 0x02788000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 166 0>, <&k3_clks 166 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- main_mcan9: can@2791000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x02791000 0x00 0x200>,
- <0x00 0x02798000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 167 0>, <&k3_clks 167 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- main_mcan10: can@27a1000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x027a1000 0x00 0x200>,
- <0x00 0x027a8000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 168 0>, <&k3_clks 168 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- main_mcan11: can@27b1000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x027b1000 0x00 0x200>,
- <0x00 0x027b8000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 169 0>, <&k3_clks 169 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- main_mcan12: can@27c1000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x027c1000 0x00 0x200>,
- <0x00 0x027c8000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 170 0>, <&k3_clks 170 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- main_mcan13: can@27d1000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x027d1000 0x00 0x200>,
- <0x00 0x027d8000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 171 0>, <&k3_clks 171 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- main_spi0: spi@2100000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x02100000 0x00 0x400>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 266 1>;
- status = "disabled";
- };
-
- main_spi1: spi@2110000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x02110000 0x00 0x400>;
- interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 267 1>;
- status = "disabled";
- };
-
- main_spi2: spi@2120000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x02120000 0x00 0x400>;
- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 268 1>;
- status = "disabled";
- };
-
- main_spi3: spi@2130000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x02130000 0x00 0x400>;
- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 269 1>;
- status = "disabled";
- };
-
- main_spi4: spi@2140000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x02140000 0x00 0x400>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 270 1>;
- status = "disabled";
- };
-
- main_spi5: spi@2150000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x02150000 0x00 0x400>;
- interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 271 1>;
- status = "disabled";
- };
-
- main_spi6: spi@2160000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x02160000 0x00 0x400>;
- interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 272 1>;
- status = "disabled";
- };
-
- main_spi7: spi@2170000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x02170000 0x00 0x400>;
- interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 273 1>;
- status = "disabled";
- };
-
- main_esm: esm@700000 {
- compatible = "ti,j721e-esm";
- reg = <0x0 0x700000 0x0 0x1000>;
- ti,esm-pins = <344>, <345>;
- };
-};
diff --git a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
deleted file mode 100644
index f7ab771..0000000
--- a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
+++ /dev/null
@@ -1,681 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals
- *
- * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-&cbass_mcu_wakeup {
- dmsc: system-controller@44083000 {
- compatible = "ti,k2g-sci";
- ti,host-id = <12>;
-
- mbox-names = "rx", "tx";
-
- mboxes = <&secure_proxy_main 11>,
- <&secure_proxy_main 13>;
-
- reg-names = "debug_messages";
- reg = <0x00 0x44083000 0x0 0x1000>;
-
- k3_pds: power-controller {
- compatible = "ti,sci-pm-domain";
- #power-domain-cells = <2>;
- };
-
- k3_clks: clock-controller {
- compatible = "ti,k2g-sci-clk";
- #clock-cells = <2>;
- };
-
- k3_reset: reset-controller {
- compatible = "ti,sci-reset";
- #reset-cells = <2>;
- };
- };
-
- mcu_conf: syscon@40f00000 {
- compatible = "syscon", "simple-mfd";
- reg = <0x0 0x40f00000 0x0 0x20000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0x40f00000 0x20000>;
-
- phy_gmii_sel: phy@4040 {
- compatible = "ti,am654-phy-gmii-sel";
- reg = <0x4040 0x4>;
- #phy-cells = <1>;
- };
- };
-
- chipid@43000014 {
- compatible = "ti,am654-chipid";
- reg = <0x0 0x43000014 0x0 0x4>;
- };
-
- wkup_pmx0: pinctrl@4301c000 {
- compatible = "pinctrl-single";
- /* Proxy 0 addressing */
- reg = <0x00 0x4301c000 0x00 0x178>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0xffffffff>;
- };
-
- /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
- mcu_timerio_input: pinctrl@40f04200 {
- compatible = "pinctrl-single";
- reg = <0x00 0x40f04200 0x00 0x28>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x0000000f>;
- /* Non-MPU Firmware usage */
- status = "reserved";
- };
-
- /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
- mcu_timerio_output: pinctrl@40f04280 {
- compatible = "pinctrl-single";
- reg = <0x00 0x40f04280 0x00 0x28>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x0000000f>;
- /* Non-MPU Firmware usage */
- status = "reserved";
- };
-
- mcu_ram: sram@41c00000 {
- compatible = "mmio-sram";
- reg = <0x00 0x41c00000 0x00 0x100000>;
- ranges = <0x0 0x00 0x41c00000 0x100000>;
- #address-cells = <1>;
- #size-cells = <1>;
- };
-
- mcu_timer0: timer@40400000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x40400000 0x00 0x400>;
- interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 35 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 35 1>;
- assigned-clock-parents = <&k3_clks 35 2>;
- power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- /* Non-MPU Firmware usage */
- status = "reserved";
- };
-
- mcu_timer1: timer@40410000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x40410000 0x00 0x400>;
- interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 71 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 71 1>, <&k3_clks 322 0>;
- assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 322 1>;
- power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- /* Non-MPU Firmware usage */
- status = "reserved";
- };
-
- mcu_timer2: timer@40420000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x40420000 0x00 0x400>;
- interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 72 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 72 1>;
- assigned-clock-parents = <&k3_clks 72 2>;
- power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- /* Non-MPU Firmware usage */
- status = "reserved";
- };
-
- mcu_timer3: timer@40430000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x40430000 0x00 0x400>;
- interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 73 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 73 1>, <&k3_clks 323 0>;
- assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 323 1>;
- power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- /* Non-MPU Firmware usage */
- status = "reserved";
- };
-
- mcu_timer4: timer@40440000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x40440000 0x00 0x400>;
- interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 74 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 74 1>;
- assigned-clock-parents = <&k3_clks 74 2>;
- power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- /* Non-MPU Firmware usage */
- status = "reserved";
- };
-
- mcu_timer5: timer@40450000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x40450000 0x00 0x400>;
- interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 75 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 75 1>, <&k3_clks 324 0>;
- assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 324 1>;
- power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- /* Non-MPU Firmware usage */
- status = "reserved";
- };
-
- mcu_timer6: timer@40460000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x40460000 0x00 0x400>;
- interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 76 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 76 1>;
- assigned-clock-parents = <&k3_clks 76 2>;
- power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- /* Non-MPU Firmware usage */
- status = "reserved";
- };
-
- mcu_timer7: timer@40470000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x40470000 0x00 0x400>;
- interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 77 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 77 1>, <&k3_clks 325 0>;
- assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 325 1>;
- power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- /* Non-MPU Firmware usage */
- status = "reserved";
- };
-
- mcu_timer8: timer@40480000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x40480000 0x00 0x400>;
- interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 78 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 78 1>;
- assigned-clock-parents = <&k3_clks 78 2>;
- power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- /* Non-MPU Firmware usage */
- status = "reserved";
- };
-
- mcu_timer9: timer@40490000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x40490000 0x00 0x400>;
- interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 79 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 79 1>, <&k3_clks 326 0>;
- assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 326 1>;
- power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- /* Non-MPU Firmware usage */
- status = "reserved";
- };
- wkup_uart0: serial@42300000 {
- compatible = "ti,j721e-uart", "ti,am654-uart";
- reg = <0x00 0x42300000 0x00 0x100>;
- interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- current-speed = <115200>;
- power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 287 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- mcu_uart0: serial@40a00000 {
- compatible = "ti,j721e-uart", "ti,am654-uart";
- reg = <0x00 0x40a00000 0x00 0x100>;
- interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <96000000>;
- current-speed = <115200>;
- power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 149 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- wkup_gpio_intr: interrupt-controller@42200000 {
- compatible = "ti,sci-intr";
- reg = <0x00 0x42200000 0x00 0x400>;
- ti,intr-trigger-type = <1>;
- interrupt-controller;
- interrupt-parent = <&gic500>;
- #interrupt-cells = <1>;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <137>;
- ti,interrupt-ranges = <16 960 16>;
- };
-
- wkup_gpio0: gpio@42110000 {
- compatible = "ti,j721e-gpio", "ti,keystone-gpio";
- reg = <0x0 0x42110000 0x0 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&wkup_gpio_intr>;
- interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <84>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 113 0>;
- clock-names = "gpio";
- status = "disabled";
- };
-
- wkup_gpio1: gpio@42100000 {
- compatible = "ti,j721e-gpio", "ti,keystone-gpio";
- reg = <0x0 0x42100000 0x0 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&wkup_gpio_intr>;
- interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <84>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 114 0>;
- clock-names = "gpio";
- status = "disabled";
- };
-
- mcu_i2c0: i2c@40b00000 {
- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x0 0x40b00000 0x0 0x100>;
- interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "fck";
- clocks = <&k3_clks 194 0>;
- power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- mcu_i2c1: i2c@40b10000 {
- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x0 0x40b10000 0x0 0x100>;
- interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "fck";
- clocks = <&k3_clks 195 0>;
- power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- wkup_i2c0: i2c@42120000 {
- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x0 0x42120000 0x0 0x100>;
- interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "fck";
- clocks = <&k3_clks 197 0>;
- power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
- status = "disabled";
- };
-
- fss: bus@47000000 {
- compatible = "simple-bus";
- reg = <0x0 0x47000000 0x0 0x100>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- hbmc_mux: mux-controller@47000004 {
- compatible = "reg-mux";
- reg = <0x00 0x47000004 0x00 0x2>;
- #mux-control-cells = <1>;
- mux-reg-masks = <0x4 0x2>; /* HBMC select */
- };
-
- hbmc: hyperbus@47034000 {
- compatible = "ti,am654-hbmc";
- reg = <0x00 0x47034000 0x00 0x100>,
- <0x05 0x00000000 0x01 0x0000000>;
- power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 102 0>;
- assigned-clocks = <&k3_clks 102 5>;
- assigned-clock-rates = <333333333>;
- #address-cells = <2>;
- #size-cells = <1>;
- mux-controls = <&hbmc_mux 0>;
- status = "disabled";
- };
-
- ospi0: spi@47040000 {
- compatible = "ti,am654-ospi", "cdns,qspi-nor";
- reg = <0x0 0x47040000 0x0 0x100>,
- <0x5 0x00000000 0x1 0x0000000>;
- interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
- cdns,fifo-depth = <256>;
- cdns,fifo-width = <4>;
- cdns,trigger-address = <0x0>;
- clocks = <&k3_clks 103 0>;
- assigned-clocks = <&k3_clks 103 0>;
- assigned-clock-parents = <&k3_clks 103 2>;
- assigned-clock-rates = <166666666>;
- power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- ospi1: spi@47050000 {
- compatible = "ti,am654-ospi", "cdns,qspi-nor";
- reg = <0x0 0x47050000 0x0 0x100>,
- <0x7 0x00000000 0x1 0x00000000>;
- interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
- cdns,fifo-depth = <256>;
- cdns,fifo-width = <4>;
- cdns,trigger-address = <0x0>;
- clocks = <&k3_clks 104 0>;
- power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
- };
-
- tscadc0: tscadc@40200000 {
- compatible = "ti,am3359-tscadc";
- reg = <0x0 0x40200000 0x0 0x1000>;
- interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 0 1>;
- assigned-clocks = <&k3_clks 0 3>;
- assigned-clock-rates = <60000000>;
- clock-names = "fck";
- dmas = <&main_udmap 0x7400>,
- <&main_udmap 0x7401>;
- dma-names = "fifo0", "fifo1";
- status = "disabled";
-
- adc {
- #io-channel-cells = <1>;
- compatible = "ti,am3359-adc";
- };
- };
-
- tscadc1: tscadc@40210000 {
- compatible = "ti,am3359-tscadc";
- reg = <0x0 0x40210000 0x0 0x1000>;
- interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 1 1>;
- assigned-clocks = <&k3_clks 1 3>;
- assigned-clock-rates = <60000000>;
- clock-names = "fck";
- dmas = <&main_udmap 0x7402>,
- <&main_udmap 0x7403>;
- dma-names = "fifo0", "fifo1";
- status = "disabled";
-
- adc {
- #io-channel-cells = <1>;
- compatible = "ti,am3359-adc";
- };
- };
-
- mcu_navss: bus@28380000 {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
- dma-coherent;
- dma-ranges;
-
- ti,sci-dev-id = <232>;
-
- mcu_ringacc: ringacc@2b800000 {
- compatible = "ti,am654-navss-ringacc";
- reg = <0x0 0x2b800000 0x0 0x400000>,
- <0x0 0x2b000000 0x0 0x400000>,
- <0x0 0x28590000 0x0 0x100>,
- <0x0 0x2a500000 0x0 0x40000>,
- <0x0 0x28440000 0x0 0x40000>;
- reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
- ti,num-rings = <286>;
- ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <235>;
- msi-parent = <&main_udmass_inta>;
- };
-
- mcu_udmap: dma-controller@285c0000 {
- compatible = "ti,j721e-navss-mcu-udmap";
- reg = <0x0 0x285c0000 0x0 0x100>,
- <0x0 0x2a800000 0x0 0x40000>,
- <0x0 0x2aa00000 0x0 0x40000>;
- reg-names = "gcfg", "rchanrt", "tchanrt";
- msi-parent = <&main_udmass_inta>;
- #dma-cells = <1>;
-
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <236>;
- ti,ringacc = <&mcu_ringacc>;
-
- ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
- <0x0f>; /* TX_HCHAN */
- ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
- <0x0b>; /* RX_HCHAN */
- ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
- };
- };
-
- secure_proxy_mcu: mailbox@2a480000 {
- compatible = "ti,am654-secure-proxy";
- #mbox-cells = <1>;
- reg-names = "target_data", "rt", "scfg";
- reg = <0x0 0x2a480000 0x0 0x80000>,
- <0x0 0x2a380000 0x0 0x80000>,
- <0x0 0x2a400000 0x0 0x80000>;
- /*
- * Marked Disabled:
- * Node is incomplete as it is meant for bootloaders and
- * firmware on non-MPU processors
- */
- status = "disabled";
- };
-
- mcu_cpsw: ethernet@46000000 {
- compatible = "ti,j721e-cpsw-nuss";
- #address-cells = <2>;
- #size-cells = <2>;
- reg = <0x0 0x46000000 0x0 0x200000>;
- reg-names = "cpsw_nuss";
- ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
- dma-coherent;
- clocks = <&k3_clks 18 22>;
- clock-names = "fck";
- power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
-
- dmas = <&mcu_udmap 0xf000>,
- <&mcu_udmap 0xf001>,
- <&mcu_udmap 0xf002>,
- <&mcu_udmap 0xf003>,
- <&mcu_udmap 0xf004>,
- <&mcu_udmap 0xf005>,
- <&mcu_udmap 0xf006>,
- <&mcu_udmap 0xf007>,
- <&mcu_udmap 0x7000>;
- dma-names = "tx0", "tx1", "tx2", "tx3",
- "tx4", "tx5", "tx6", "tx7",
- "rx";
-
- ethernet-ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpsw_port1: port@1 {
- reg = <1>;
- ti,mac-only;
- label = "port1";
- ti,syscon-efuse = <&mcu_conf 0x200>;
- phys = <&phy_gmii_sel 1>;
- };
- };
-
- davinci_mdio: mdio@f00 {
- compatible = "ti,cpsw-mdio","ti,davinci_mdio";
- reg = <0x0 0xf00 0x0 0x100>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&k3_clks 18 22>;
- clock-names = "fck";
- bus_freq = <1000000>;
- };
-
- cpts@3d000 {
- compatible = "ti,am65-cpts";
- reg = <0x0 0x3d000 0x0 0x400>;
- clocks = <&k3_clks 18 2>;
- clock-names = "cpts";
- interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cpts";
- ti,cpts-ext-ts-inputs = <4>;
- ti,cpts-periodic-outputs = <2>;
- };
- };
-
- mcu_r5fss0: r5fss@41000000 {
- compatible = "ti,j721e-r5fss";
- ti,cluster-mode = <1>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x41000000 0x00 0x41000000 0x20000>,
- <0x41400000 0x00 0x41400000 0x20000>;
- power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
-
- mcu_r5fss0_core0: r5f@41000000 {
- compatible = "ti,j721e-r5f";
- reg = <0x41000000 0x00008000>,
- <0x41010000 0x00008000>;
- reg-names = "atcm", "btcm";
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <250>;
- ti,sci-proc-ids = <0x01 0xff>;
- resets = <&k3_reset 250 1>;
- firmware-name = "j7-mcu-r5f0_0-fw";
- ti,atcm-enable = <1>;
- ti,btcm-enable = <1>;
- ti,loczrama = <1>;
- };
-
- mcu_r5fss0_core1: r5f@41400000 {
- compatible = "ti,j721e-r5f";
- reg = <0x41400000 0x00008000>,
- <0x41410000 0x00008000>;
- reg-names = "atcm", "btcm";
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <251>;
- ti,sci-proc-ids = <0x02 0xff>;
- resets = <&k3_reset 251 1>;
- firmware-name = "j7-mcu-r5f0_1-fw";
- ti,atcm-enable = <1>;
- ti,btcm-enable = <1>;
- ti,loczrama = <1>;
- };
- };
-
- mcu_mcan0: can@40528000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x40528000 0x00 0x200>,
- <0x00 0x40500000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 172 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 172 0>, <&k3_clks 172 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- mcu_mcan1: can@40568000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x40568000 0x00 0x200>,
- <0x00 0x40540000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 173 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 173 0>, <&k3_clks 173 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- mcu_spi0: spi@40300000 {
- compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
- reg = <0x00 0x040300000 0x00 0x400>;
- interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 274 0>;
- status = "disabled";
- };
-
- mcu_spi1: spi@40310000 {
- compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
- reg = <0x00 0x040310000 0x00 0x400>;
- interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 275 0>;
- status = "disabled";
- };
-
- mcu_spi2: spi@40320000 {
- compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
- reg = <0x00 0x040320000 0x00 0x400>;
- interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 276 0>;
- status = "disabled";
- };
-
- wkup_vtm0: temperature-sensor@42040000 {
- compatible = "ti,j721e-vtm";
- reg = <0x00 0x42040000 0x00 0x350>,
- <0x00 0x42050000 0x00 0x350>,
- <0x00 0x43000300 0x00 0x10>;
- power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
- #thermal-sensor-cells = <1>;
- };
-
- mcu_esm: esm@40800000 {
- compatible = "ti,j721e-esm";
- reg = <0x00 0x40800000 0x00 0x1000>;
- ti,esm-pins = <95>;
- bootph-pre-ram;
- };
-};
diff --git a/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts b/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts
index 43da4da..586ddb6 100644
--- a/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts
+++ b/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts
@@ -12,84 +12,8 @@
#include "k3-j721e-ddr.dtsi"
#include "k3-j721e-beagleboneai64-u-boot.dtsi"
+#include "k3-j721e-r5.dtsi"
-/ {
- aliases {
- remoteproc0 = &sysctrler;
- remoteproc1 = &a72_0;
- };
-
- chosen {
- tick-timer = &mcu_timer0;
- };
-
- a72_0: a72@0 {
- compatible = "ti,am654-rproc";
- reg = <0x0 0x00a90000 0x0 0x10>;
- power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
- <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>,
- <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
- resets = <&k3_reset 202 0>;
- clocks = <&k3_clks 61 1>;
- assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;
- assigned-clock-rates = <2000000000>, <200000000>;
- ti,sci = <&dmsc>;
- ti,sci-proc-id = <32>;
- ti,sci-host-id = <10>;
- bootph-pre-ram;
- };
-
- dm_tifs: dm-tifs {
- compatible = "ti,j721e-dm-sci";
- ti,host-id = <3>;
- ti,secure-host;
- mbox-names = "rx", "tx";
- mboxes= <&secure_proxy_mcu 21>,
- <&secure_proxy_mcu 23>;
- bootph-pre-ram;
- };
-};
-
-&dmsc {
- mboxes= <&secure_proxy_mcu 6>,
- <&secure_proxy_mcu 8>,
- <&secure_proxy_mcu 5>;
- mbox-names = "rx", "tx", "notify";
- ti,host-id = <4>;
- ti,secure-host;
-};
-
-&mcu_timer0 {
- status = "okay";
- bootph-pre-ram;
-};
-
-&secure_proxy_mcu {
- bootph-pre-ram;
- /* We require this for boot handshake */
- status = "okay";
-};
-
-&cbass_mcu_wakeup {
- sysctrler: sysctrler {
- compatible = "ti,am654-system-controller";
- mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>;
- mbox-names = "tx", "rx";
- bootph-pre-ram;
- };
-};
-
-&mcu_ringacc {
- ti,sci = <&dm_tifs>;
-};
-
-&mcu_udmap {
- ti,sci = <&dm_tifs>;
-};
-
-&wkup_uart0_pins_default {
- bootph-pre-ram;
-};
&wkup_i2c0 {
bootph-pre-ram;
@@ -183,3 +107,32 @@
};
};
};
+
+#include "k3-binman-capsule-r5.dtsi"
+
+// Capsue update GUIDs. See beagleboneai64.h.
+#define BEAGLEBONEAI64_TIBOOT3_IMAGE_GUID_STR "772a4810-2194-4923-8754-0115870ef367"
+#define BEAGLEBONEAI64_SYSFW_IMAGE_GUID_STR "dfc9c683-49b7-46bd-b3c1-3a3b2fdb135b"
+
+&capsule_tiboot3 {
+ efi-capsule {
+ image-guid = BEAGLEBONEAI64_TIBOOT3_IMAGE_GUID_STR;
+ };
+};
+
+&binman {
+ capsule-sysfw {
+ filename = "sysfw-capsule.bin";
+ efi-capsule {
+ image-index = <0x4>;
+ image-guid = BEAGLEBONEAI64_SYSFW_IMAGE_GUID_STR;
+ private-key = "arch/arm/mach-k3/keys/custMpk.pem";
+ public-key-cert = "arch/arm/mach-k3/keys/custMpk.crt";
+ monotonic-count = <0x1>;
+
+ blob {
+ filename = "sysfw.itb";
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
index 9655ca2..c7e3443 100644
--- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
@@ -10,76 +10,7 @@
#include "k3-j721e-ddr.dtsi"
#include "k3-j721e-common-proc-board-u-boot.dtsi"
-/ {
- chosen {
- tick-timer = &mcu_timer0;
- };
-
- aliases {
- remoteproc0 = &sysctrler;
- remoteproc1 = &a72_0;
- };
-
- a72_0: a72@0 {
- compatible = "ti,am654-rproc";
- reg = <0x0 0x00a90000 0x0 0x10>;
- power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
- <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>,
- <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
- resets = <&k3_reset 202 0>;
- clocks = <&k3_clks 61 1>;
- assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;
- assigned-clock-rates = <2000000000>, <200000000>;
- ti,sci = <&dmsc>;
- ti,sci-proc-id = <32>;
- ti,sci-host-id = <10>;
- bootph-pre-ram;
- };
-
- dm_tifs: dm-tifs {
- compatible = "ti,j721e-dm-sci";
- ti,host-id = <3>;
- ti,secure-host;
- mbox-names = "rx", "tx";
- mboxes= <&secure_proxy_mcu 21>,
- <&secure_proxy_mcu 23>;
- bootph-pre-ram;
- };
-};
-
-&mcu_timer0 {
- status = "okay";
- bootph-pre-ram;
-};
-
-&dmsc {
- mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>;
- mbox-names = "tx", "rx", "notify";
- ti,host-id = <4>;
- ti,secure-host;
-};
-
-&secure_proxy_mcu {
- bootph-pre-ram;
- status = "okay";
-};
-
-&cbass_mcu_wakeup {
- sysctrler: sysctrler {
- bootph-pre-ram;
- compatible = "ti,am654-system-controller";
- mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>;
- mbox-names = "tx", "rx";
- };
-};
-
-&mcu_ringacc {
- ti,sci = <&dm_tifs>;
-};
-
-&mcu_udmap {
- ti,sci = <&dm_tifs>;
-};
+#include "k3-j721e-r5.dtsi"
&wkup_i2c0 {
bootph-pre-ram;
@@ -111,10 +42,6 @@
};
};
-&wkup_uart0_pins_default {
- bootph-pre-ram;
-};
-
&mcu_uart0_pins_default {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/k3-j721e-r5-sk.dts b/arch/arm/dts/k3-j721e-r5-sk.dts
index b0c108e..96a13b2 100644
--- a/arch/arm/dts/k3-j721e-r5-sk.dts
+++ b/arch/arm/dts/k3-j721e-r5-sk.dts
@@ -10,80 +10,7 @@
#include "k3-j721e-ddr.dtsi"
#include "k3-j721e-sk-u-boot.dtsi"
-/ {
- chosen {
- tick-timer = &mcu_timer0;
- };
-
- aliases {
- remoteproc0 = &sysctrler;
- remoteproc1 = &a72_0;
- };
-
- a72_0: a72@0 {
- compatible = "ti,am654-rproc";
- reg = <0x0 0x00a90000 0x0 0x10>;
- power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
- <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>,
- <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
- resets = <&k3_reset 202 0>;
- clocks = <&k3_clks 61 1>;
- assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;
- assigned-clock-rates = <2000000000>, <200000000>;
- ti,sci = <&dmsc>;
- ti,sci-proc-id = <32>;
- ti,sci-host-id = <10>;
- bootph-pre-ram;
- };
-
- dm_tifs: dm-tifs {
- compatible = "ti,j721e-dm-sci";
- ti,host-id = <3>;
- ti,secure-host;
- mbox-names = "rx", "tx";
- mboxes= <&secure_proxy_mcu 21>,
- <&secure_proxy_mcu 23>;
- bootph-pre-ram;
- };
-};
-
-&mcu_timer0 {
- status = "okay";
- bootph-pre-ram;
-};
-
-&secure_proxy_mcu {
- bootph-pre-ram;
- status = "okay";
-};
-
-&cbass_mcu_wakeup {
- sysctrler: sysctrler {
- bootph-pre-ram;
- compatible = "ti,am654-system-controller";
- mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>;
- mbox-names = "tx", "rx";
- };
-};
-
-&dmsc {
- mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>;
- mbox-names = "tx", "rx", "notify";
- ti,host-id = <4>;
- ti,secure-host;
-};
-
-&mcu_ringacc {
- ti,sci = <&dm_tifs>;
-};
-
-&mcu_udmap {
- ti,sci = <&dm_tifs>;
-};
-
-&wkup_uart0_pins_default {
- bootph-pre-ram;
-};
+#include "k3-j721e-r5.dtsi"
&mcu_uart0_pins_default {
bootph-pre-ram;
diff --git a/arch/arm/dts/k3-j721e-r5.dtsi b/arch/arm/dts/k3-j721e-r5.dtsi
new file mode 100644
index 0000000..fd0d921
--- /dev/null
+++ b/arch/arm/dts/k3-j721e-r5.dtsi
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/ {
+ chosen {
+ tick-timer = &mcu_timer0;
+ };
+
+ aliases {
+ remoteproc0 = &sysctrler;
+ remoteproc1 = &a72_0;
+ };
+
+ a72_0: a72@0 {
+ compatible = "ti,am654-rproc";
+ reg = <0x0 0x00a90000 0x0 0x10>;
+ power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+ <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>,
+ <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
+ resets = <&k3_reset 202 0>;
+ clocks = <&k3_clks 61 1>;
+ assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;
+ assigned-clock-rates = <2000000000>, <200000000>;
+ ti,sci = <&dmsc>;
+ ti,sci-proc-id = <32>;
+ ti,sci-host-id = <10>;
+ bootph-pre-ram;
+ };
+
+ dm_tifs: dm-tifs {
+ compatible = "ti,j721e-dm-sci";
+ ti,host-id = <3>;
+ ti,secure-host;
+ mbox-names = "rx", "tx";
+ mboxes= <&secure_proxy_mcu 21>,
+ <&secure_proxy_mcu 23>;
+ bootph-pre-ram;
+ };
+};
+
+&mcu_timer0 {
+ status = "okay";
+ bootph-pre-ram;
+};
+
+&dmsc {
+ mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>;
+ mbox-names = "tx", "rx", "notify";
+ ti,host-id = <4>;
+ ti,secure-host;
+};
+
+&secure_proxy_mcu {
+ bootph-pre-ram;
+ /* We require this for boot handshake */
+ status = "okay";
+};
+
+&cbass_mcu_wakeup {
+ sysctrler: sysctrler {
+ bootph-pre-ram;
+ compatible = "ti,am654-system-controller";
+ mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>;
+ mbox-names = "tx", "rx";
+ };
+};
+
+&mcu_ringacc {
+ ti,sci = <&dm_tifs>;
+};
+
+&mcu_udmap {
+ ti,sci = <&dm_tifs>;
+};
+
+&wkup_uart0_pins_default {
+ bootph-pre-ram;
+};
diff --git a/arch/arm/dts/k3-j721e-sk-u-boot.dtsi b/arch/arm/dts/k3-j721e-sk-u-boot.dtsi
index 8f4f944..07ed7b4 100644
--- a/arch/arm/dts/k3-j721e-sk-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-sk-u-boot.dtsi
@@ -15,10 +15,10 @@
&cbass_mcu_wakeup {
bootph-all;
+};
- chipid@43000014 {
- bootph-all;
- };
+&chipid {
+ bootph-all;
};
&mcu_navss {
@@ -26,19 +26,11 @@
};
&mcu_ringacc {
- bootph-all;
+ bootph-all;
};
&mcu_udmap {
- reg = <0x0 0x285c0000 0x0 0x100>,
- <0x0 0x284c0000 0x0 0x4000>,
- <0x0 0x2a800000 0x0 0x40000>,
- <0x0 0x284a0000 0x0 0x4000>,
- <0x0 0x2aa00000 0x0 0x40000>,
- <0x0 0x28400000 0x0 0x2000>;
- reg-names = "gcfg", "rchan", "rchanrt", "tchan",
- "tchanrt", "rflow";
- bootph-all;
+ bootph-all;
};
&secure_proxy_main {
@@ -155,3 +147,26 @@
bootph-all;
};
};
+
+#ifdef CONFIG_TARGET_J721E_A72_EVM
+
+#define SPL_J721E_SK_DTB "spl/dts/ti/k3-j721e-sk.dtb"
+#define J721E_SK_DTB "u-boot.dtb"
+
+&spl_j721e_dtb {
+ filename = SPL_J721E_SK_DTB;
+};
+
+&j721e_dtb {
+ filename = J721E_SK_DTB;
+};
+
+&spl_j721e_dtb_unsigned {
+ filename = SPL_J721E_SK_DTB;
+};
+
+&j721e_dtb_unsigned {
+ filename = J721E_SK_DTB;
+};
+
+#endif
diff --git a/arch/arm/dts/k3-j721e-sk.dts b/arch/arm/dts/k3-j721e-sk.dts
deleted file mode 100644
index 42fe8ee..0000000
--- a/arch/arm/dts/k3-j721e-sk.dts
+++ /dev/null
@@ -1,1074 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
- *
- * J721E SK URL: https://www.ti.com/tool/SK-TDA4VM
- */
-
-/dts-v1/;
-
-#include "k3-j721e.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/net/ti-dp83867.h>
-
-/ {
- compatible = "ti,j721e-sk", "ti,j721e";
- model = "Texas Instruments J721E SK";
-
- aliases {
- serial0 = &wkup_uart0;
- serial1 = &mcu_uart0;
- serial2 = &main_uart0;
- serial3 = &main_uart1;
- ethernet0 = &cpsw_port1;
- mmc1 = &main_sdhci1;
- };
-
- chosen {
- stdout-path = "serial2:115200n8";
- };
-
- memory@80000000 {
- device_type = "memory";
- /* 4G RAM */
- reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
- <0x00000008 0x80000000 0x00000000 0x80000000>;
- };
-
- reserved_memory: reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- secure_ddr: optee@9e800000 {
- reg = <0x00 0x9e800000 0x00 0x01800000>;
- alignment = <0x1000>;
- no-map;
- };
-
- mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa0000000 0x00 0x100000>;
- no-map;
- };
-
- mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa0100000 0x00 0xf00000>;
- no-map;
- };
-
- mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa1000000 0x00 0x100000>;
- no-map;
- };
-
- mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa1100000 0x00 0xf00000>;
- no-map;
- };
-
- main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa2000000 0x00 0x100000>;
- no-map;
- };
-
- main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa2100000 0x00 0xf00000>;
- no-map;
- };
-
- main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa3000000 0x00 0x100000>;
- no-map;
- };
-
- main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa3100000 0x00 0xf00000>;
- no-map;
- };
-
- main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa4000000 0x00 0x100000>;
- no-map;
- };
-
- main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa4100000 0x00 0xf00000>;
- no-map;
- };
-
- main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa5000000 0x00 0x100000>;
- no-map;
- };
-
- main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa5100000 0x00 0xf00000>;
- no-map;
- };
-
- c66_1_dma_memory_region: c66-dma-memory@a6000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa6000000 0x00 0x100000>;
- no-map;
- };
-
- c66_0_memory_region: c66-memory@a6100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa6100000 0x00 0xf00000>;
- no-map;
- };
-
- c66_0_dma_memory_region: c66-dma-memory@a7000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa7000000 0x00 0x100000>;
- no-map;
- };
-
- c66_1_memory_region: c66-memory@a7100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa7100000 0x00 0xf00000>;
- no-map;
- };
-
- c71_0_dma_memory_region: c71-dma-memory@a8000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa8000000 0x00 0x100000>;
- no-map;
- };
-
- c71_0_memory_region: c71-memory@a8100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa8100000 0x00 0xf00000>;
- no-map;
- };
-
- rtos_ipc_memory_region: ipc-memories@aa000000 {
- reg = <0x00 0xaa000000 0x00 0x01c00000>;
- alignment = <0x1000>;
- no-map;
- };
- };
-
- vusb_main: fixedregulator-vusb-main5v0 {
- /* USB MAIN INPUT 5V DC */
- compatible = "regulator-fixed";
- regulator-name = "vusb-main5v0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vsys_3v3: fixedregulator-vsys3v3 {
- /* Output of LM5141 */
- compatible = "regulator-fixed";
- regulator-name = "vsys_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vusb_main>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vdd_mmc1: fixedregulator-sd {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&vdd_mmc1_en_pins_default>;
- regulator-name = "vdd_mmc1";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- enable-active-high;
- vin-supply = <&vsys_3v3>;
- gpio = <&wkup_gpio0 8 GPIO_ACTIVE_HIGH>;
- };
-
- vdd_sd_dv_alt: gpio-regulator-tps659411 {
- compatible = "regulator-gpio";
- pinctrl-names = "default";
- pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
- regulator-name = "tps659411";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- vin-supply = <&vsys_3v3>;
- gpios = <&wkup_gpio0 9 GPIO_ACTIVE_HIGH>;
- states = <1800000 0x0>,
- <3300000 0x1>;
- };
-
- dp_pwr_3v3: fixedregulator-dp-prw {
- compatible = "regulator-fixed";
- regulator-name = "dp-pwr";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- pinctrl-names = "default";
- pinctrl-0 = <&dp_pwr_en_pins_default>;
- gpio = <&main_gpio0 111 0>; /* DP0_3V3 _EN */
- enable-active-high;
- };
-
- dp0: connector {
- compatible = "dp-connector";
- label = "DP0";
- type = "full-size";
- dp-pwr-supply = <&dp_pwr_3v3>;
-
- port {
- dp_connector_in: endpoint {
- remote-endpoint = <&dp0_out>;
- };
- };
- };
-
- hdmi-connector {
- compatible = "hdmi-connector";
- label = "hdmi";
- type = "a";
-
- pinctrl-names = "default";
- pinctrl-0 = <&hdmi_hpd_pins_default>;
-
- ddc-i2c-bus = <&main_i2c1>;
-
- /* HDMI_HPD */
- hpd-gpios = <&main_gpio1 0 GPIO_ACTIVE_HIGH>;
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&tfp410_out>;
- };
- };
- };
-
- dvi-bridge {
- compatible = "ti,tfp410";
-
- pinctrl-names = "default";
- pinctrl-0 = <&hdmi_pdn_pins_default>;
-
- powerdown-gpios = <&main_gpio0 127 GPIO_ACTIVE_LOW>;
- ti,deskew = <0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- tfp410_in: endpoint {
- remote-endpoint = <&dpi1_out>;
- pclk-sample = <1>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- tfp410_out: endpoint {
- remote-endpoint =
- <&hdmi_connector_in>;
- };
- };
- };
- };
-};
-
-&main_pmx0 {
- main_mmc1_pins_default: main-mmc1-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
- J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
- J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
- J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
- J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
- J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
- J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
- J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
- >;
- };
-
- main_uart0_pins_default: main-uart0-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */
- J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */
- J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
- J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
- >;
- };
-
- main_uart1_pins_default: main-uart1-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0x1f8, PIN_INPUT, 0) /* (AA4) UART1_RXD */
- J721E_IOPAD(0x1fc, PIN_OUTPUT, 0) /* (AB4) UART1_TXD */
- >;
- };
-
- main_i2c0_pins_default: main-i2c0-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
- J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
- >;
- };
-
- main_i2c1_pins_default: main-i2c1-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
- J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
- >;
- };
-
- main_i2c3_pins_default: main-i2c3-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
- J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
- >;
- };
-
- main_usbss0_pins_default: main-usbss0-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
- J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
- >;
- };
-
- main_usbss1_pins_default: main-usbss1-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
- >;
- };
-
- dp0_pins_default: dp0-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */
- >;
- };
-
- dp_pwr_en_pins_default: dp-pwr-en-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0x1c0, PIN_INPUT, 7) /* (AA2) SPI0_CS0.GPIO0_111 */
- >;
- };
-
- dss_vout0_pins_default: dss-vout0-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0x58, PIN_OUTPUT, 10) /* (AE22) PRG1_PRU1_GPO0.VOUT0_DATA0 */
- J721E_IOPAD(0x5c, PIN_OUTPUT, 10) /* (AG23) PRG1_PRU1_GPO1.VOUT0_DATA1 */
- J721E_IOPAD(0x60, PIN_OUTPUT, 10) /* (AF23) PRG1_PRU1_GPO2.VOUT0_DATA2 */
- J721E_IOPAD(0x64, PIN_OUTPUT, 10) /* (AD23) PRG1_PRU1_GPO3.VOUT0_DATA3 */
- J721E_IOPAD(0x68, PIN_OUTPUT, 10) /* (AH24) PRG1_PRU1_GPO4.VOUT0_DATA4 */
- J721E_IOPAD(0x6c, PIN_OUTPUT, 10) /* (AG21) PRG1_PRU1_GPO5.VOUT0_DATA5 */
- J721E_IOPAD(0x70, PIN_OUTPUT, 10) /* (AE23) PRG1_PRU1_GPO6.VOUT0_DATA6 */
- J721E_IOPAD(0x74, PIN_OUTPUT, 10) /* (AC21) PRG1_PRU1_GPO7.VOUT0_DATA7 */
- J721E_IOPAD(0x78, PIN_OUTPUT, 10) /* (Y23) PRG1_PRU1_GPO8.VOUT0_DATA8 */
- J721E_IOPAD(0x7c, PIN_OUTPUT, 10) /* (AF21) PRG1_PRU1_GPO9.VOUT0_DATA9 */
- J721E_IOPAD(0x80, PIN_OUTPUT, 10) /* (AB23) PRG1_PRU1_GPO10.VOUT0_DATA10 */
- J721E_IOPAD(0x84, PIN_OUTPUT, 10) /* (AJ25) PRG1_PRU1_GPO11.VOUT0_DATA11 */
- J721E_IOPAD(0x88, PIN_OUTPUT, 10) /* (AH25) PRG1_PRU1_GPO12.VOUT0_DATA12 */
- J721E_IOPAD(0x8c, PIN_OUTPUT, 10) /* (AG25) PRG1_PRU1_GPO13.VOUT0_DATA13 */
- J721E_IOPAD(0x90, PIN_OUTPUT, 10) /* (AH26) PRG1_PRU1_GPO14.VOUT0_DATA14 */
- J721E_IOPAD(0x94, PIN_OUTPUT, 10) /* (AJ27) PRG1_PRU1_GPO15.VOUT0_DATA15 */
- J721E_IOPAD(0x30, PIN_OUTPUT, 10) /* (AF24) PRG1_PRU0_GPO11.VOUT0_DATA16 */
- J721E_IOPAD(0x34, PIN_OUTPUT, 10) /* (AJ24) PRG1_PRU0_GPO12.VOUT0_DATA17 */
- J721E_IOPAD(0x38, PIN_OUTPUT, 10) /* (AG24) PRG1_PRU0_GPO13.VOUT0_DATA18 */
- J721E_IOPAD(0x3c, PIN_OUTPUT, 10) /* (AD24) PRG1_PRU0_GPO14.VOUT0_DATA19 */
- J721E_IOPAD(0x40, PIN_OUTPUT, 10) /* (AC24) PRG1_PRU0_GPO15.VOUT0_DATA20 */
- J721E_IOPAD(0x44, PIN_OUTPUT, 10) /* (AE24) PRG1_PRU0_GPO16.VOUT0_DATA21 */
- J721E_IOPAD(0x24, PIN_OUTPUT, 10) /* (AJ20) PRG1_PRU0_GPO8.VOUT0_DATA22 */
- J721E_IOPAD(0x28, PIN_OUTPUT, 10) /* (AG20) PRG1_PRU0_GPO9.VOUT0_DATA23 */
- J721E_IOPAD(0x9c, PIN_OUTPUT, 10) /* (AC22) PRG1_PRU1_GPO17.VOUT0_DE */
- J721E_IOPAD(0x98, PIN_OUTPUT, 10) /* (AJ26) PRG1_PRU1_GPO16.VOUT0_HSYNC */
- J721E_IOPAD(0xa4, PIN_OUTPUT, 10) /* (AH22) PRG1_PRU1_GPO19.VOUT0_PCLK */
- J721E_IOPAD(0xa0, PIN_OUTPUT, 10) /* (AJ22) PRG1_PRU1_GPO18.VOUT0_VSYNC */
- >;
- };
-
- hdmi_hpd_pins_default: hdmi-hpd-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0x204, PIN_INPUT, 7) /* (AD5) UART1_RTSn.GPIO1_0 */
- >;
- };
-
- hdmi_pdn_pins_default: hdmi-pdn-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */
- >;
- };
-
- /* Reset for M.2 E Key slot on PCIe0 */
- ekey_reset_pins_default: ekey-reset-pns-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0x124, PIN_INPUT, 7) /* (Y24) PRG0_PRU1_GPO9.GPIO0_72 */
- >;
- };
-
- main_i2c5_pins_default: main-i2c5-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */
- J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */
- >;
- };
-
- rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0x01C, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */
- J721E_IOPAD(0x120, PIN_INPUT, 7) /* (AA28) PRG0_PRU1_GPO8.GPIO0_71 */
- J721E_IOPAD(0x14C, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */
- J721E_IOPAD(0x02C, PIN_INPUT, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */
- J721E_IOPAD(0x198, PIN_INPUT, 7) /* (V25) RGMII6_TD1.GPIO0_101 */
- J721E_IOPAD(0x1B0, PIN_INPUT, 7) /* (W24) RGMII6_RD1.GPIO0_107 */
- J721E_IOPAD(0x1A0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */
- J721E_IOPAD(0x008, PIN_INPUT, 7) /* (AG22) PRG1_PRU0_GPO1.GPIO0_2 */
- J721E_IOPAD(0x1D0, PIN_INPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */
- J721E_IOPAD(0x11C, PIN_INPUT, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */
- J721E_IOPAD(0x148, PIN_INPUT, 7) /* (AA26) PRG0_PRU1_GPO18.GPIO0_81 */
- J721E_IOPAD(0x004, PIN_INPUT, 7) /* (AC23) PRG1_PRU0_GPO0.GPIO0_1 */
- J721E_IOPAD(0x014, PIN_INPUT, 7) /* (AH23) PRG1_PRU0_GPO4.GPIO0_5 */
- J721E_IOPAD(0x020, PIN_INPUT, 7) /* (AE20) PRG1_PRU0_GPO7.GPIO0_8 */
- J721E_IOPAD(0x19C, PIN_INPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */
- J721E_IOPAD(0x1B4, PIN_INPUT, 7) /* (W25) RGMII6_RD0.GPIO0_108 */
- J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */
- J721E_IOPAD(0x00C, PIN_INPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */
- J721E_IOPAD(0x010, PIN_INPUT, 7) /* (AJ23) PRG1_PRU0_GPO3.GPIO0_4 */
- J721E_IOPAD(0x178, PIN_INPUT, 7) /* (U27) RGMII5_RD3.GPIO0_93 */
- J721E_IOPAD(0x17C, PIN_INPUT, 7) /* (U24) RGMII5_RD2.GPIO0_94 */
- J721E_IOPAD(0x190, PIN_INPUT, 7) /* (W23) RGMII6_TD3.GPIO0_99 */
- J721E_IOPAD(0x18C, PIN_INPUT, 7) /* (V23) RGMII6_RX_CTL.GPIO0_98 */
- >;
- };
-
- rpi_header_gpio1_pins_default: rpi-header-gpio1-default-pins {
- pinctrl-single,pins = <
- J721E_IOPAD(0x234, PIN_INPUT, 7) /* (U3) EXT_REFCLK1.GPIO1_12 */
- >;
- };
-};
-
-&wkup_pmx0 {
- mcu_cpsw_pins_default: mcu-cpsw-default-pins {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */
- J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */
- J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */
- J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */
- J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */
- J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */
- J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */
- J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */
- J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */
- J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */
- J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */
- J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */
- >;
- };
-
- mcu_mdio_pins_default: mcu-mdio1-default-pins {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */
- J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */
- >;
- };
-
- mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */
- J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */
- J721E_WKUP_IOPAD(0xc, PIN_INPUT, 0) /* (D20) MCU_OSPI0_D0 */
- J721E_WKUP_IOPAD(0x10, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D1 */
- J721E_WKUP_IOPAD(0x14, PIN_INPUT, 0) /* (G20) MCU_OSPI0_D2 */
- J721E_WKUP_IOPAD(0x18, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D3 */
- J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 0) /* (F21) MCU_OSPI0_D4 */
- J721E_WKUP_IOPAD(0x20, PIN_INPUT, 0) /* (E21) MCU_OSPI0_D5 */
- J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */
- J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */
- J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */
- >;
- };
-
- vdd_mmc1_en_pins_default: vdd-mmc1-en-default-pins {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0xd0, PIN_OUTPUT, 7) /* (G27) WKUP_GPIO0_8 */
- >;
- };
-
- vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0xd4, PIN_OUTPUT, 7) /* (G26) WKUP_GPIO0_9 */
- >;
- };
-
- wkup_uart0_pins_default: wkup-uart0-default-pins {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
- J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
- >;
- };
-
- mcu_uart0_pins_default: mcu-uart0-default-pins {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 2) /* (D26) MCU_I3C0_SCL.MCU_UART0_CTSn */
- J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 2)/* (D25) MCU_I3C0_SDA.MCU_UART0_RTSn */
- J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */
- J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0)/* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
- >;
- };
-
- wkup_i2c0_pins_default: wkup-i2c0-default-pins {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
- J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
- >;
- };
-
- /* Reset for M.2 M Key slot on PCIe1 */
- mkey_reset_pins_default: mkey-reset-pns-default-pins {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* (H27) WKUP_GPIO0_11 */
- >;
- };
-};
-
-&wkup_uart0 {
- /* Wakeup UART is used by System firmware */
- status = "reserved";
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_uart0_pins_default>;
-};
-
-&wkup_i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_i2c0_pins_default>;
- clock-frequency = <400000>;
-
- eeprom@51 {
- /* AT24C512C-MAHM-T */
- compatible = "atmel,24c512";
- reg = <0x51>;
- };
-};
-
-&mcu_uart0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_uart0_pins_default>;
-};
-
-&main_uart0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart0_pins_default>;
- /* Shared with ATF on this platform */
- power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
-};
-
-&main_uart1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart1_pins_default>;
-};
-
-&main_sdhci1 {
- /* SD Card */
- status = "okay";
- vmmc-supply = <&vdd_mmc1>;
- vqmmc-supply = <&vdd_sd_dv_alt>;
- pinctrl-names = "default";
- pinctrl-0 = <&main_mmc1_pins_default>;
- ti,driver-strength-ohm = <50>;
- disable-wp;
-};
-
-&ospi0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0x0>;
- spi-tx-bus-width = <8>;
- spi-rx-bus-width = <8>;
- spi-max-frequency = <25000000>;
- cdns,tshsl-ns = <60>;
- cdns,tsd2d-ns = <60>;
- cdns,tchsh-ns = <60>;
- cdns,tslch-ns = <60>;
- cdns,read-delay = <4>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "ospi.tiboot3";
- reg = <0x0 0x80000>;
- };
-
- partition@80000 {
- label = "ospi.tispl";
- reg = <0x80000 0x200000>;
- };
-
- partition@280000 {
- label = "ospi.u-boot";
- reg = <0x280000 0x400000>;
- };
-
- partition@680000 {
- label = "ospi.env";
- reg = <0x680000 0x40000>;
- };
-
- partition@6c0000 {
- label = "ospi.sysfw";
- reg = <0x6c0000 0x100000>;
- };
-
- partition@7c0000 {
- label = "ospi.env.backup";
- reg = <0x7c0000 0x40000>;
- };
-
- partition@800000 {
- label = "ospi.rootfs";
- reg = <0x800000 0x37c0000>;
- };
-
- partition@3fc0000 {
- label = "ospi.phypattern";
- reg = <0x3fc0000 0x40000>;
- };
- };
- };
-};
-
-&main_i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c0_pins_default>;
- clock-frequency = <400000>;
-
- i2c-mux@71 {
- compatible = "nxp,pca9543";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x71>;
-
- /* PCIe1 M.2 M Key I2C */
- i2c@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
- };
-
- /* PCIe0 M.2 E Key I2C */
- i2c@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
- };
- };
-};
-
-&main_i2c1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c1_pins_default>;
- /* i2c1 is used for DVI DDC, so we need to use 100kHz */
- clock-frequency = <100000>;
-};
-
-&main_i2c3 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c3_pins_default>;
- clock-frequency = <400000>;
-
- i2c-mux@70 {
- compatible = "nxp,pca9543";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x70>;
-
- /* CSI0 I2C */
- i2c@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
- };
-
- /* CSI1 I2C */
- i2c@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
- };
- };
-};
-
-&main_i2c5 {
- /* Brought out on RPi Header */
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c5_pins_default>;
- clock-frequency = <400000>;
-};
-
-&main_gpio0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&rpi_header_gpio0_pins_default>;
-};
-
-&main_gpio1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&rpi_header_gpio1_pins_default>;
-};
-
-&wkup_gpio0 {
- status = "okay";
-};
-
-&usb_serdes_mux {
- idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */
-};
-
-&serdes_ln_ctrl {
- idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_IP4_UNUSED>,
- <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
- <J721E_SERDES2_LANE0_IP1_UNUSED>, <J721E_SERDES2_LANE1_USB3_1>,
- <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
- <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
- <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
-};
-
-&serdes_wiz3 {
- typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
- typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */
-};
-
-&serdes3 {
- serdes3_usb_link: phy@0 {
- reg = <0>;
- cdns,num-lanes = <2>;
- #phy-cells = <0>;
- cdns,phy-type = <PHY_TYPE_USB3>;
- resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
- };
-};
-
-&serdes4 {
- torrent_phy_dp: phy@0 {
- reg = <0>;
- resets = <&serdes_wiz4 1>;
- cdns,phy-type = <PHY_TYPE_DP>;
- cdns,num-lanes = <4>;
- cdns,max-bit-rate = <5400>;
- #phy-cells = <0>;
- };
-};
-
-&mhdp {
- phys = <&torrent_phy_dp>;
- phy-names = "dpphy";
- pinctrl-names = "default";
- pinctrl-0 = <&dp0_pins_default>;
-};
-
-&usbss0 {
- pinctrl-names = "default";
- pinctrl-0 = <&main_usbss0_pins_default>;
- ti,vbus-divider;
-};
-
-&usb0 {
- dr_mode = "otg";
- maximum-speed = "super-speed";
- phys = <&serdes3_usb_link>;
- phy-names = "cdns3,usb3-phy";
-};
-
-&serdes2 {
- serdes2_usb_link: phy@1 {
- reg = <1>;
- cdns,num-lanes = <1>;
- #phy-cells = <0>;
- cdns,phy-type = <PHY_TYPE_USB3>;
- resets = <&serdes_wiz2 2>;
- };
-};
-
-&usbss1 {
- pinctrl-names = "default";
- pinctrl-0 = <&main_usbss1_pins_default>;
- ti,vbus-divider;
-};
-
-&usb1 {
- dr_mode = "host";
- maximum-speed = "super-speed";
- phys = <&serdes2_usb_link>;
- phy-names = "cdns3,usb3-phy";
-};
-
-&mcu_cpsw {
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
-};
-
-&davinci_mdio {
- phy0: ethernet-phy@0 {
- reg = <0>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- };
-};
-
-&cpsw_port1 {
- phy-mode = "rgmii-rxid";
- phy-handle = <&phy0>;
-};
-
-&dss {
- pinctrl-names = "default";
- pinctrl-0 = <&dss_vout0_pins_default>;
-
- assigned-clocks = <&k3_clks 152 1>, /* VP 1 pixel clock */
- <&k3_clks 152 4>, /* VP 2 pixel clock */
- <&k3_clks 152 9>, /* VP 3 pixel clock */
- <&k3_clks 152 13>; /* VP 4 pixel clock */
- assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */
- <&k3_clks 152 6>, /* DPI0_EXT_CLKSEL_OUT0 */
- <&k3_clks 152 11>, /* PLL18_HSDIV0 */
- <&k3_clks 152 18>; /* DPI1_EXT_CLKSEL_OUT0 */
-};
-
-&dss_ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- dpi0_out: endpoint {
- remote-endpoint = <&dp0_in>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- dpi1_out: endpoint {
- remote-endpoint = <&tfp410_in>;
- };
- };
-};
-
-&dp0_ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- dp0_in: endpoint {
- remote-endpoint = <&dpi0_out>;
- };
- };
-
- port@4 {
- reg = <4>;
- dp0_out: endpoint {
- remote-endpoint = <&dp_connector_in>;
- };
- };
-};
-
-&serdes0 {
- serdes0_pcie_link: phy@0 {
- reg = <0>;
- cdns,num-lanes = <1>;
- #phy-cells = <0>;
- cdns,phy-type = <PHY_TYPE_PCIE>;
- resets = <&serdes_wiz0 1>;
- };
-};
-
-&serdes1 {
- serdes1_pcie_link: phy@0 {
- reg = <0>;
- cdns,num-lanes = <2>;
- #phy-cells = <0>;
- cdns,phy-type = <PHY_TYPE_PCIE>;
- resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
- };
-};
-
-&pcie0_rc {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&ekey_reset_pins_default>;
- reset-gpios = <&main_gpio0 72 GPIO_ACTIVE_HIGH>;
-
- phys = <&serdes0_pcie_link>;
- phy-names = "pcie-phy";
- num-lanes = <1>;
-};
-
-&pcie1_rc {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mkey_reset_pins_default>;
- reset-gpios = <&wkup_gpio0 11 GPIO_ACTIVE_HIGH>;
-
- phys = <&serdes1_pcie_link>;
- phy-names = "pcie-phy";
- num-lanes = <2>;
-};
-
-&ufs_wrapper {
- status = "disabled";
-};
-
-&mailbox0_cluster0 {
- status = "okay";
- interrupts = <436>;
-
- mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
- ti,mbox-rx = <0 0 0>;
- ti,mbox-tx = <1 0 0>;
- };
-
- mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
- ti,mbox-rx = <2 0 0>;
- ti,mbox-tx = <3 0 0>;
- };
-};
-
-&mailbox0_cluster1 {
- status = "okay";
- interrupts = <432>;
-
- mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
- ti,mbox-rx = <0 0 0>;
- ti,mbox-tx = <1 0 0>;
- };
-
- mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
- ti,mbox-rx = <2 0 0>;
- ti,mbox-tx = <3 0 0>;
- };
-};
-
-&mailbox0_cluster2 {
- status = "okay";
- interrupts = <428>;
-
- mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
- ti,mbox-rx = <0 0 0>;
- ti,mbox-tx = <1 0 0>;
- };
-
- mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
- ti,mbox-rx = <2 0 0>;
- ti,mbox-tx = <3 0 0>;
- };
-};
-
-&mailbox0_cluster3 {
- status = "okay";
- interrupts = <424>;
-
- mbox_c66_0: mbox-c66-0 {
- ti,mbox-rx = <0 0 0>;
- ti,mbox-tx = <1 0 0>;
- };
-
- mbox_c66_1: mbox-c66-1 {
- ti,mbox-rx = <2 0 0>;
- ti,mbox-tx = <3 0 0>;
- };
-};
-
-&mailbox0_cluster4 {
- status = "okay";
- interrupts = <420>;
-
- mbox_c71_0: mbox-c71-0 {
- ti,mbox-rx = <0 0 0>;
- ti,mbox-tx = <1 0 0>;
- };
-};
-
-&mcu_r5fss0_core0 {
- mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
- memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
- <&mcu_r5fss0_core0_memory_region>;
-};
-
-&mcu_r5fss0_core1 {
- mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
- memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
- <&mcu_r5fss0_core1_memory_region>;
-};
-
-&main_r5fss0_core0 {
- mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
- memory-region = <&main_r5fss0_core0_dma_memory_region>,
- <&main_r5fss0_core0_memory_region>;
-};
-
-&main_r5fss0_core1 {
- mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
- memory-region = <&main_r5fss0_core1_dma_memory_region>,
- <&main_r5fss0_core1_memory_region>;
-};
-
-&main_r5fss1_core0 {
- mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
- memory-region = <&main_r5fss1_core0_dma_memory_region>,
- <&main_r5fss1_core0_memory_region>;
-};
-
-&main_r5fss1_core1 {
- mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
- memory-region = <&main_r5fss1_core1_dma_memory_region>,
- <&main_r5fss1_core1_memory_region>;
-};
-
-&c66_0 {
- status = "okay";
- mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>;
- memory-region = <&c66_0_dma_memory_region>,
- <&c66_0_memory_region>;
-};
-
-&c66_1 {
- status = "okay";
- mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>;
- memory-region = <&c66_1_dma_memory_region>,
- <&c66_1_memory_region>;
-};
-
-&c71_0 {
- status = "okay";
- mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
- memory-region = <&c71_0_dma_memory_region>,
- <&c71_0_memory_region>;
-};
diff --git a/arch/arm/dts/k3-j721e-som-p0.dtsi b/arch/arm/dts/k3-j721e-som-p0.dtsi
deleted file mode 100644
index 7f0686c2..0000000
--- a/arch/arm/dts/k3-j721e-som-p0.dtsi
+++ /dev/null
@@ -1,446 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/
- *
- * Product Link: https://www.ti.com/tool/J721EXSOMXEVM
- */
-
-/dts-v1/;
-
-#include "k3-j721e.dtsi"
-
-/ {
- memory@80000000 {
- device_type = "memory";
- /* 4G RAM */
- reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
- <0x00000008 0x80000000 0x00000000 0x80000000>;
- };
-
- reserved_memory: reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- secure_ddr: optee@9e800000 {
- reg = <0x00 0x9e800000 0x00 0x01800000>;
- alignment = <0x1000>;
- no-map;
- };
-
- mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa0000000 0x00 0x100000>;
- no-map;
- };
-
- mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa0100000 0x00 0xf00000>;
- no-map;
- };
-
- mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa1000000 0x00 0x100000>;
- no-map;
- };
-
- mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa1100000 0x00 0xf00000>;
- no-map;
- };
-
- main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa2000000 0x00 0x100000>;
- no-map;
- };
-
- main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa2100000 0x00 0xf00000>;
- no-map;
- };
-
- main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa3000000 0x00 0x100000>;
- no-map;
- };
-
- main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa3100000 0x00 0xf00000>;
- no-map;
- };
-
- main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa4000000 0x00 0x100000>;
- no-map;
- };
-
- main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa4100000 0x00 0xf00000>;
- no-map;
- };
-
- main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa5000000 0x00 0x100000>;
- no-map;
- };
-
- main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa5100000 0x00 0xf00000>;
- no-map;
- };
-
- c66_1_dma_memory_region: c66-dma-memory@a6000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa6000000 0x00 0x100000>;
- no-map;
- };
-
- c66_0_memory_region: c66-memory@a6100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa6100000 0x00 0xf00000>;
- no-map;
- };
-
- c66_0_dma_memory_region: c66-dma-memory@a7000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa7000000 0x00 0x100000>;
- no-map;
- };
-
- c66_1_memory_region: c66-memory@a7100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa7100000 0x00 0xf00000>;
- no-map;
- };
-
- c71_0_dma_memory_region: c71-dma-memory@a8000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa8000000 0x00 0x100000>;
- no-map;
- };
-
- c71_0_memory_region: c71-memory@a8100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa8100000 0x00 0xf00000>;
- no-map;
- };
-
- rtos_ipc_memory_region: ipc-memories@aa000000 {
- reg = <0x00 0xaa000000 0x00 0x01c00000>;
- alignment = <0x1000>;
- no-map;
- };
- };
-};
-
-&wkup_pmx0 {
- wkup_i2c0_pins_default: wkup-i2c0-default-pins {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
- J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
- >;
- };
-
- mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
- J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */
- J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */
- J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */
- J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */
- J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */
- J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */
- J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */
- J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */
- J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */
- J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
- >;
- };
-
- mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CK */
- J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CKn */
- J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CSn0 */
- J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* MCU_HYPERBUS0_CSn1 */
- J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_RESETn */
- J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* MCU_HYPERBUS0_RWDS */
- J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ0 */
- J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ1 */
- J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ2 */
- J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ3 */
- J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ4 */
- J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ5 */
- J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ6 */
- J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ7 */
- >;
- };
-};
-
-&wkup_i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_i2c0_pins_default>;
- clock-frequency = <400000>;
-
- eeprom@50 {
- /* CAV24C256WE-GT3 */
- compatible = "atmel,24c256";
- reg = <0x50>;
- };
-};
-
-&ospi0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0x0>;
- spi-tx-bus-width = <8>;
- spi-rx-bus-width = <8>;
- spi-max-frequency = <25000000>;
- cdns,tshsl-ns = <60>;
- cdns,tsd2d-ns = <60>;
- cdns,tchsh-ns = <60>;
- cdns,tslch-ns = <60>;
- cdns,read-delay = <0>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "ospi.tiboot3";
- reg = <0x0 0x80000>;
- };
-
- partition@80000 {
- label = "ospi.tispl";
- reg = <0x80000 0x200000>;
- };
-
- partition@280000 {
- label = "ospi.u-boot";
- reg = <0x280000 0x400000>;
- };
-
- partition@680000 {
- label = "ospi.env";
- reg = <0x680000 0x20000>;
- };
-
- partition@6a0000 {
- label = "ospi.env.backup";
- reg = <0x6a0000 0x20000>;
- };
-
- partition@6c0000 {
- label = "ospi.sysfw";
- reg = <0x6c0000 0x100000>;
- };
-
- partition@800000 {
- label = "ospi.rootfs";
- reg = <0x800000 0x37c0000>;
- };
-
- partition@3fe0000 {
- label = "ospi.phypattern";
- reg = <0x3fe0000 0x20000>;
- };
- };
- };
-};
-
-&hbmc {
- /* OSPI and HBMC are muxed inside FSS, Bootloader will enable
- * appropriate node based on board detection
- */
- status = "disabled";
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
- ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */
- <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */
-
- flash@0,0 {
- compatible = "cypress,hyperflash", "cfi-flash";
- reg = <0x00 0x00 0x4000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "hbmc.tiboot3";
- reg = <0x0 0x80000>;
- };
-
- partition@80000 {
- label = "hbmc.tispl";
- reg = <0x80000 0x200000>;
- };
-
- partition@280000 {
- label = "hbmc.u-boot";
- reg = <0x280000 0x400000>;
- };
-
- partition@680000 {
- label = "hbmc.env";
- reg = <0x680000 0x40000>;
- };
-
- partition@6c0000 {
- label = "hbmc.sysfw";
- reg = <0x6c0000 0x100000>;
- };
-
- partition@800000 {
- label = "hbmc.rootfs";
- reg = <0x800000 0x3800000>;
- };
- };
- };
-};
-
-&mailbox0_cluster0 {
- status = "okay";
- interrupts = <436>;
-
- mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
- ti,mbox-rx = <0 0 0>;
- ti,mbox-tx = <1 0 0>;
- };
-
- mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
- ti,mbox-rx = <2 0 0>;
- ti,mbox-tx = <3 0 0>;
- };
-};
-
-&mailbox0_cluster1 {
- status = "okay";
- interrupts = <432>;
-
- mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
- ti,mbox-rx = <0 0 0>;
- ti,mbox-tx = <1 0 0>;
- };
-
- mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
- ti,mbox-rx = <2 0 0>;
- ti,mbox-tx = <3 0 0>;
- };
-};
-
-&mailbox0_cluster2 {
- status = "okay";
- interrupts = <428>;
-
- mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
- ti,mbox-rx = <0 0 0>;
- ti,mbox-tx = <1 0 0>;
- };
-
- mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
- ti,mbox-rx = <2 0 0>;
- ti,mbox-tx = <3 0 0>;
- };
-};
-
-&mailbox0_cluster3 {
- status = "okay";
- interrupts = <424>;
-
- mbox_c66_0: mbox-c66-0 {
- ti,mbox-rx = <0 0 0>;
- ti,mbox-tx = <1 0 0>;
- };
-
- mbox_c66_1: mbox-c66-1 {
- ti,mbox-rx = <2 0 0>;
- ti,mbox-tx = <3 0 0>;
- };
-};
-
-&mailbox0_cluster4 {
- status = "okay";
- interrupts = <420>;
-
- mbox_c71_0: mbox-c71-0 {
- ti,mbox-rx = <0 0 0>;
- ti,mbox-tx = <1 0 0>;
- };
-};
-
-&mcu_r5fss0_core0 {
- mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
- memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
- <&mcu_r5fss0_core0_memory_region>;
-};
-
-&mcu_r5fss0_core1 {
- mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
- memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
- <&mcu_r5fss0_core1_memory_region>;
-};
-
-&main_r5fss0_core0 {
- mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
- memory-region = <&main_r5fss0_core0_dma_memory_region>,
- <&main_r5fss0_core0_memory_region>;
-};
-
-&main_r5fss0_core1 {
- mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
- memory-region = <&main_r5fss0_core1_dma_memory_region>,
- <&main_r5fss0_core1_memory_region>;
-};
-
-&main_r5fss1_core0 {
- mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
- memory-region = <&main_r5fss1_core0_dma_memory_region>,
- <&main_r5fss1_core0_memory_region>;
-};
-
-&main_r5fss1_core1 {
- mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
- memory-region = <&main_r5fss1_core1_dma_memory_region>,
- <&main_r5fss1_core1_memory_region>;
-};
-
-&c66_0 {
- status = "okay";
- mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>;
- memory-region = <&c66_0_dma_memory_region>,
- <&c66_0_memory_region>;
-};
-
-&c66_1 {
- status = "okay";
- mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>;
- memory-region = <&c66_1_dma_memory_region>,
- <&c66_1_memory_region>;
-};
-
-&c71_0 {
- status = "okay";
- mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
- memory-region = <&c71_0_dma_memory_region>,
- <&c71_0_memory_region>;
-};
diff --git a/arch/arm/dts/k3-j721e-thermal.dtsi b/arch/arm/dts/k3-j721e-thermal.dtsi
deleted file mode 100644
index c252327..0000000
--- a/arch/arm/dts/k3-j721e-thermal.dtsi
+++ /dev/null
@@ -1,75 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-
-#include <dt-bindings/thermal/thermal.h>
-
-thermal_zones: thermal-zones {
- wkup_thermal: wkup-thermal {
- polling-delay-passive = <250>; /* milliseconds */
- polling-delay = <500>; /* milliseconds */
- thermal-sensors = <&wkup_vtm0 0>;
-
- trips {
- wkup_crit: wkup-crit {
- temperature = <125000>; /* milliCelsius */
- hysteresis = <2000>; /* milliCelsius */
- type = "critical";
- };
- };
- };
-
- mpu_thermal: mpu-thermal {
- polling-delay-passive = <250>; /* milliseconds */
- polling-delay = <500>; /* milliseconds */
- thermal-sensors = <&wkup_vtm0 1>;
-
- trips {
- mpu_crit: mpu-crit {
- temperature = <125000>; /* milliCelsius */
- hysteresis = <2000>; /* milliCelsius */
- type = "critical";
- };
- };
- };
-
- c7x_thermal: c7x-thermal {
- polling-delay-passive = <250>; /* milliseconds */
- polling-delay = <500>; /* milliseconds */
- thermal-sensors = <&wkup_vtm0 2>;
-
- trips {
- c7x_crit: c7x-crit {
- temperature = <125000>; /* milliCelsius */
- hysteresis = <2000>; /* milliCelsius */
- type = "critical";
- };
- };
- };
-
- gpu_thermal: gpu-thermal {
- polling-delay-passive = <250>; /* milliseconds */
- polling-delay = <500>; /* milliseconds */
- thermal-sensors = <&wkup_vtm0 3>;
-
- trips {
- gpu_crit: gpu-crit {
- temperature = <125000>; /* milliCelsius */
- hysteresis = <2000>; /* milliCelsius */
- type = "critical";
- };
- };
- };
-
- r5f_thermal: r5f-thermal {
- polling-delay-passive = <250>; /* milliseconds */
- polling-delay = <500>; /* milliseconds */
- thermal-sensors = <&wkup_vtm0 4>;
-
- trips {
- r5f_crit: r5f-crit {
- temperature = <125000>; /* milliCelsius */
- hysteresis = <2000>; /* milliCelsius */
- type = "critical";
- };
- };
- };
-};
diff --git a/arch/arm/dts/k3-j721e.dtsi b/arch/arm/dts/k3-j721e.dtsi
deleted file mode 100644
index a200810..0000000
--- a/arch/arm/dts/k3-j721e.dtsi
+++ /dev/null
@@ -1,176 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for J721E SoC Family
- *
- * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/soc/ti,sci_pm_domain.h>
-
-#include "k3-pinctrl.h"
-
-/ {
- model = "Texas Instruments K3 J721E SoC";
- compatible = "ti,j721e";
- interrupt-parent = <&gic500>;
- #address-cells = <2>;
- #size-cells = <2>;
-
- chosen { };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- cpu-map {
- cluster0: cluster0 {
- core0 {
- cpu = <&cpu0>;
- };
-
- core1 {
- cpu = <&cpu1>;
- };
- };
-
- };
-
- cpu0: cpu@0 {
- compatible = "arm,cortex-a72";
- reg = <0x000>;
- device_type = "cpu";
- enable-method = "psci";
- i-cache-size = <0xC000>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <64>;
- d-cache-sets = <256>;
- next-level-cache = <&L2_0>;
- };
-
- cpu1: cpu@1 {
- compatible = "arm,cortex-a72";
- reg = <0x001>;
- device_type = "cpu";
- enable-method = "psci";
- i-cache-size = <0xC000>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <64>;
- d-cache-sets = <256>;
- next-level-cache = <&L2_0>;
- };
- };
-
- L2_0: l2-cache0 {
- compatible = "cache";
- cache-level = <2>;
- cache-unified;
- cache-size = <0x100000>;
- cache-line-size = <64>;
- cache-sets = <1024>;
- next-level-cache = <&msmc_l3>;
- };
-
- msmc_l3: l3-cache0 {
- compatible = "cache";
- cache-level = <3>;
- cache-unified;
- };
-
- firmware {
- optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- };
-
- psci: psci {
- compatible = "arm,psci-1.0";
- method = "smc";
- };
- };
-
- a72_timer0: timer-cl0-cpu0 {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
- <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
- <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
- };
-
- pmu: pmu {
- compatible = "arm,cortex-a72-pmu";
- /* Recommendation from GIC500 TRM Table A.3 */
- interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- cbass_main: bus@100000 {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
- <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
- <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */
- <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
- <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */
- <0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */
- <0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */
- <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
- <0x00 0x0c000000 0x00 0x0c000000 0x00 0x0d000000>, /* CPSW9G */
- <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
- <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01800000>, /* PCIe Core*/
- <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /* PCIe Core*/
- <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
- <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */
- <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
- <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT */
- <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT */
- <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
- <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* C66_1 */
- <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
- <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */
-
- /* MCUSS_WKUP Range */
- <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
- <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
- <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
- <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
- <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
- <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
- <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
- <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
- <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
- <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
- <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
- <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
- <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
-
- cbass_mcu_wakeup: bus@28380000 {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
- <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
- <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
- <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
- <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
- <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
- <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
- <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
- <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
- <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
- <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
- <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
- <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/
- };
- };
-
- #include "k3-j721e-thermal.dtsi"
-};
-
-/* Now include the peripherals for each bus segments */
-#include "k3-j721e-main.dtsi"
-#include "k3-j721e-mcu-wakeup.dtsi"
diff --git a/arch/arm/dts/k3-j721s2-binman.dtsi b/arch/arm/dts/k3-j721s2-binman.dtsi
index 46297eb..d121d8c 100644
--- a/arch/arm/dts/k3-j721s2-binman.dtsi
+++ b/arch/arm/dts/k3-j721s2-binman.dtsi
@@ -149,6 +149,7 @@
filename = "ti-dm.bin";
blob-ext {
filename = "ti-dm/j721s2/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+ optional;
};
};
ti-spl {
diff --git a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
index 91a82b3..54eb9b4 100644
--- a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
@@ -102,7 +102,9 @@
};
&ospi0 {
- status = "disabled";
+ flash@0 {
+ bootph-all;
+ };
};
&ospi1 {
diff --git a/arch/arm/dts/k3-j721s2-r5.dtsi b/arch/arm/dts/k3-j721s2-r5.dtsi
index eb0df42..caf696c 100644
--- a/arch/arm/dts/k3-j721s2-r5.dtsi
+++ b/arch/arm/dts/k3-j721s2-r5.dtsi
@@ -22,7 +22,7 @@
resets = <&k3_reset 202 0>;
clocks = <&k3_clks 61 1>;
assigned-clocks = <&k3_clks 61 1>, <&k3_clks 202 0>;
- assigned-clock-parents = <&k3_clks 61 2>;
+ assigned-clock-parents = <&k3_clks 61 3>;
assigned-clock-rates = <200000000>, <2000000000>;
ti,sci = <&sms>;
ti,sci-proc-id = <32>;
@@ -79,3 +79,16 @@
&mcu_udmap {
ti,sci = <&dm_tifs>;
};
+
+&ospi0 {
+ reg = <0x0 0x47040000 0x0 0x100>,
+ <0x0 0x50000000 0x0 0x8000000>;
+};
+
+&fss {
+ /* fss node has 64 bit address regions mapped to it and since the ospi
+ * nodes is being override, override the fss node ranges as well
+ */
+ ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x00068400>,
+ <0x0 0x50000000 0x0 0x50000000 0x0 0x08000000>;
+};
diff --git a/arch/arm/dts/k3-j722s-binman.dtsi b/arch/arm/dts/k3-j722s-binman.dtsi
new file mode 100644
index 0000000..28087a3
--- /dev/null
+++ b/arch/arm/dts/k3-j722s-binman.dtsi
@@ -0,0 +1,172 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include "k3-binman.dtsi"
+
+#if IS_ENABLED(CONFIG_TARGET_J722S_R5_EVM)
+
+&binman {
+ tiboot3-j722s-hs-fs-evm.bin {
+ filename = "tiboot3-j722s-hs-fs-evm.bin";
+ symlink = "tiboot3.bin";
+
+ ti-secure-rom {
+ content = <&u_boot_spl_fs>, <&ti_fs_enc_fs>, <&combined_tifs_cfg_fs>,
+ <&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>;
+ combined;
+ dm-data;
+ sysfw-inner-cert;
+ keyfile = "custMpk.pem";
+ sw-rev = <1>;
+ content-sbl = <&u_boot_spl_fs>;
+ content-sysfw = <&ti_fs_enc_fs>;
+ content-sysfw-data = <&combined_tifs_cfg_fs>;
+ content-sysfw-inner-cert = <&sysfw_inner_cert_fs>;
+ content-dm-data = <&combined_dm_cfg_fs>;
+ load = <0x43c00000>;
+ load-sysfw = <0x40000>;
+ load-sysfw-data = <0x67000>;
+ load-dm-data = <0x43c7a800>;
+ };
+
+ u_boot_spl_fs: u-boot-spl {
+ no-expanded;
+ };
+
+ ti_fs_enc_fs: ti-fs-enc.bin {
+ filename = "ti-sysfw/ti-fs-firmware-j722s-hs-fs-enc.bin";
+ type = "blob-ext";
+ optional;
+ };
+
+ combined_tifs_cfg_fs: combined-tifs-cfg.bin {
+ filename = "combined-tifs-cfg.bin";
+ type = "blob-ext";
+ };
+
+ sysfw_inner_cert_fs: sysfw-inner-cert {
+ filename = "ti-sysfw/ti-fs-firmware-j722s-hs-fs-cert.bin";
+ type = "blob-ext";
+ optional;
+ };
+
+ combined_dm_cfg_fs: combined-dm-cfg.bin {
+ filename = "combined-dm-cfg.bin";
+ type = "blob-ext";
+ };
+ };
+};
+#endif /*CONFIG_TARGET_J722S_R5_EVM*/
+
+#if IS_ENABLED(CONFIG_TARGET_J722S_A53_EVM)
+
+#define SPL_J722S_EVM_DTB "spl/dts/ti/k3-j722s-evm.dtb"
+#define J722S_EVM_DTB "u-boot.dtb"
+
+&binman {
+ ti-dm {
+ filename = "ti-dm.bin";
+
+ blob-ext {
+ filename = "ti-dm/j722s/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+ optional;
+ };
+ };
+
+ ti-spl {
+ insert-template = <&ti_spl_template>;
+
+ fit {
+ images {
+ dm {
+ ti-secure {
+ content = <&dm>;
+ keyfile = "custMpk.pem";
+ };
+
+ dm: ti-dm {
+ filename = "ti-dm.bin";
+ };
+ };
+
+ fdt-0 {
+ description = "k3-j722s-evm";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+
+ ti-secure {
+ content = <&spl_j722s_evm_dtb>;
+ keyfile = "custMpk.pem";
+ };
+
+ spl_j722s_evm_dtb: blob-ext {
+ filename = SPL_J722S_EVM_DTB;
+ };
+
+ };
+
+ };
+
+ configurations {
+ default = "conf-0";
+
+ conf-0 {
+ description = "k3-j722s-evm";
+ firmware = "atf";
+ loadables = "tee", "dm", "spl";
+ fdt = "fdt-0";
+ };
+ };
+ };
+ };
+};
+
+&binman {
+ u-boot {
+ insert-template = <&u_boot_template>;
+
+ fit {
+ images {
+ uboot {
+ description = "U-Boot for J722S board";
+ };
+
+ fdt-0 {
+ description = "k3-j722s-evm";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+
+ ti-secure {
+ content = <&j722s_evm_dtb>;
+ keyfile = "custMpk.pem";
+ };
+
+ j722s_evm_dtb: blob-ext {
+ filename = J722S_EVM_DTB;
+ };
+
+ hash {
+ algo = "crc32";
+ };
+ };
+ };
+
+ configurations {
+ default = "conf-0";
+
+ conf-0 {
+ description = "k3-j722s-evm";
+ firmware = "uboot";
+ loadables = "uboot";
+ fdt = "fdt-0";
+ };
+
+ };
+ };
+ };
+};
+#endif /*CONFIG_TARGET_J722S_A53_EVM*/
diff --git a/arch/arm/dts/k3-j722s-ddr-lp4-50-3733.dtsi b/arch/arm/dts/k3-j722s-ddr-lp4-50-3733.dtsi
new file mode 100644
index 0000000..f11aa60
--- /dev/null
+++ b/arch/arm/dts/k3-j722s-ddr-lp4-50-3733.dtsi
@@ -0,0 +1,2795 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - http://www.ti.com/
+ * This file was generated with the Jacinto7_DDRSS_RegConfigTool, Revision: J722S - v0.0.0
+ * This file was generated on Fri Nov 17 2023 13:18:41 GMT-0600 (Central Standard Time)
+ */
+
+#define DDRSS_PLL_FHS_CNT 5
+#define DDRSS_PLL_FREQUENCY_0 25000000
+#define DDRSS_PLL_FREQUENCY_1 933000000
+#define DDRSS_PLL_FREQUENCY_2 933000000
+
+#define DDRSS_CTL_0_DATA 0x00000B00
+#define DDRSS_CTL_1_DATA 0x00000000
+#define DDRSS_CTL_2_DATA 0x00000000
+#define DDRSS_CTL_3_DATA 0x00000000
+#define DDRSS_CTL_4_DATA 0x00000000
+#define DDRSS_CTL_5_DATA 0x00000000
+#define DDRSS_CTL_6_DATA 0x00000000
+#define DDRSS_CTL_7_DATA 0x00002710
+#define DDRSS_CTL_8_DATA 0x000186A0
+#define DDRSS_CTL_9_DATA 0x00000005
+#define DDRSS_CTL_10_DATA 0x00000064
+#define DDRSS_CTL_11_DATA 0x0005B18F
+#define DDRSS_CTL_12_DATA 0x0038EF90
+#define DDRSS_CTL_13_DATA 0x00000005
+#define DDRSS_CTL_14_DATA 0x00000E94
+#define DDRSS_CTL_15_DATA 0x0005B18F
+#define DDRSS_CTL_16_DATA 0x0038EF90
+#define DDRSS_CTL_17_DATA 0x00000005
+#define DDRSS_CTL_18_DATA 0x00000E94
+#define DDRSS_CTL_19_DATA 0x01010100
+#define DDRSS_CTL_20_DATA 0x01010100
+#define DDRSS_CTL_21_DATA 0x01000110
+#define DDRSS_CTL_22_DATA 0x02010002
+#define DDRSS_CTL_23_DATA 0x0000000A
+#define DDRSS_CTL_24_DATA 0x000186A0
+#define DDRSS_CTL_25_DATA 0x00000000
+#define DDRSS_CTL_26_DATA 0x00000000
+#define DDRSS_CTL_27_DATA 0x00000000
+#define DDRSS_CTL_28_DATA 0x00000000
+#define DDRSS_CTL_29_DATA 0x00020200
+#define DDRSS_CTL_30_DATA 0x00000000
+#define DDRSS_CTL_31_DATA 0x00000000
+#define DDRSS_CTL_32_DATA 0x00000000
+#define DDRSS_CTL_33_DATA 0x00000000
+#define DDRSS_CTL_34_DATA 0x08000010
+#define DDRSS_CTL_35_DATA 0x00004B4B
+#define DDRSS_CTL_36_DATA 0x00000000
+#define DDRSS_CTL_37_DATA 0x00000000
+#define DDRSS_CTL_38_DATA 0x00000000
+#define DDRSS_CTL_39_DATA 0x00000000
+#define DDRSS_CTL_40_DATA 0x0000040C
+#define DDRSS_CTL_41_DATA 0x00000000
+#define DDRSS_CTL_42_DATA 0x00001040
+#define DDRSS_CTL_43_DATA 0x00000000
+#define DDRSS_CTL_44_DATA 0x00001040
+#define DDRSS_CTL_45_DATA 0x00000000
+#define DDRSS_CTL_46_DATA 0x05000804
+#define DDRSS_CTL_47_DATA 0x00000800
+#define DDRSS_CTL_48_DATA 0x09090004
+#define DDRSS_CTL_49_DATA 0x00000204
+#define DDRSS_CTL_50_DATA 0x007A0012
+#define DDRSS_CTL_51_DATA 0x09140054
+#define DDRSS_CTL_52_DATA 0x00003A26
+#define DDRSS_CTL_53_DATA 0x007A0012
+#define DDRSS_CTL_54_DATA 0x09140054
+#define DDRSS_CTL_55_DATA 0x09003A26
+#define DDRSS_CTL_56_DATA 0x000A0A09
+#define DDRSS_CTL_57_DATA 0x0400036D
+#define DDRSS_CTL_58_DATA 0x090F2005
+#define DDRSS_CTL_59_DATA 0x00001B13
+#define DDRSS_CTL_60_DATA 0x0E007FE6
+#define DDRSS_CTL_61_DATA 0x090F200F
+#define DDRSS_CTL_62_DATA 0x00001B13
+#define DDRSS_CTL_63_DATA 0x0E007FE6
+#define DDRSS_CTL_64_DATA 0x0304200F
+#define DDRSS_CTL_65_DATA 0x04050002
+#define DDRSS_CTL_66_DATA 0x24262426
+#define DDRSS_CTL_67_DATA 0x01010008
+#define DDRSS_CTL_68_DATA 0x044A4A08
+#define DDRSS_CTL_69_DATA 0x042B2B04
+#define DDRSS_CTL_70_DATA 0x00002B2B
+#define DDRSS_CTL_71_DATA 0x00000101
+#define DDRSS_CTL_72_DATA 0x00000000
+#define DDRSS_CTL_73_DATA 0x01000000
+#define DDRSS_CTL_74_DATA 0x00130803
+#define DDRSS_CTL_75_DATA 0x00000059
+#define DDRSS_CTL_76_DATA 0x000002C5
+#define DDRSS_CTL_77_DATA 0x00000E2E
+#define DDRSS_CTL_78_DATA 0x000002C5
+#define DDRSS_CTL_79_DATA 0x00000E2E
+#define DDRSS_CTL_80_DATA 0x00000005
+#define DDRSS_CTL_81_DATA 0x0000000A
+#define DDRSS_CTL_82_DATA 0x00000010
+#define DDRSS_CTL_83_DATA 0x00000163
+#define DDRSS_CTL_84_DATA 0x00000386
+#define DDRSS_CTL_85_DATA 0x00000163
+#define DDRSS_CTL_86_DATA 0x00000386
+#define DDRSS_CTL_87_DATA 0x03004000
+#define DDRSS_CTL_88_DATA 0x00001201
+#define DDRSS_CTL_89_DATA 0x000E0005
+#define DDRSS_CTL_90_DATA 0x2908000E
+#define DDRSS_CTL_91_DATA 0x0A050529
+#define DDRSS_CTL_92_DATA 0x1B0E0A03
+#define DDRSS_CTL_93_DATA 0x1B0E0A04
+#define DDRSS_CTL_94_DATA 0x04010104
+#define DDRSS_CTL_95_DATA 0x00010401
+#define DDRSS_CTL_96_DATA 0x00140014
+#define DDRSS_CTL_97_DATA 0x02D302D3
+#define DDRSS_CTL_98_DATA 0x02D302D3
+#define DDRSS_CTL_99_DATA 0x00000000
+#define DDRSS_CTL_100_DATA 0x03030000
+#define DDRSS_CTL_101_DATA 0x05050501
+#define DDRSS_CTL_102_DATA 0x04041C04
+#define DDRSS_CTL_103_DATA 0x0E0A0E0A
+#define DDRSS_CTL_104_DATA 0x0A04041C
+#define DDRSS_CTL_105_DATA 0x030E0A0E
+#define DDRSS_CTL_106_DATA 0x00000404
+#define DDRSS_CTL_107_DATA 0x00000301
+#define DDRSS_CTL_108_DATA 0x00000001
+#define DDRSS_CTL_109_DATA 0x00000000
+#define DDRSS_CTL_110_DATA 0x40020100
+#define DDRSS_CTL_111_DATA 0x00038010
+#define DDRSS_CTL_112_DATA 0x00050004
+#define DDRSS_CTL_113_DATA 0x00000004
+#define DDRSS_CTL_114_DATA 0x00040003
+#define DDRSS_CTL_115_DATA 0x00040005
+#define DDRSS_CTL_116_DATA 0x00030000
+#define DDRSS_CTL_117_DATA 0x00050004
+#define DDRSS_CTL_118_DATA 0x00000004
+#define DDRSS_CTL_119_DATA 0x00001640
+#define DDRSS_CTL_120_DATA 0x00001640
+#define DDRSS_CTL_121_DATA 0x00001640
+#define DDRSS_CTL_122_DATA 0x00001640
+#define DDRSS_CTL_123_DATA 0x00001640
+#define DDRSS_CTL_124_DATA 0x00000000
+#define DDRSS_CTL_125_DATA 0x0000026F
+#define DDRSS_CTL_126_DATA 0x00038B80
+#define DDRSS_CTL_127_DATA 0x00038B80
+#define DDRSS_CTL_128_DATA 0x00038B80
+#define DDRSS_CTL_129_DATA 0x00038B80
+#define DDRSS_CTL_130_DATA 0x00038B80
+#define DDRSS_CTL_131_DATA 0x00000000
+#define DDRSS_CTL_132_DATA 0x00006342
+#define DDRSS_CTL_133_DATA 0x00038B80
+#define DDRSS_CTL_134_DATA 0x00038B80
+#define DDRSS_CTL_135_DATA 0x00038B80
+#define DDRSS_CTL_136_DATA 0x00038B80
+#define DDRSS_CTL_137_DATA 0x00038B80
+#define DDRSS_CTL_138_DATA 0x00000000
+#define DDRSS_CTL_139_DATA 0x00006342
+#define DDRSS_CTL_140_DATA 0x00000000
+#define DDRSS_CTL_141_DATA 0x00000000
+#define DDRSS_CTL_142_DATA 0x00000000
+#define DDRSS_CTL_143_DATA 0x00000000
+#define DDRSS_CTL_144_DATA 0x00000000
+#define DDRSS_CTL_145_DATA 0x00000000
+#define DDRSS_CTL_146_DATA 0x00000000
+#define DDRSS_CTL_147_DATA 0x00000000
+#define DDRSS_CTL_148_DATA 0x00000000
+#define DDRSS_CTL_149_DATA 0x00000000
+#define DDRSS_CTL_150_DATA 0x00000000
+#define DDRSS_CTL_151_DATA 0x00000000
+#define DDRSS_CTL_152_DATA 0x00000000
+#define DDRSS_CTL_153_DATA 0x00000000
+#define DDRSS_CTL_154_DATA 0x00000000
+#define DDRSS_CTL_155_DATA 0x00000000
+#define DDRSS_CTL_156_DATA 0x00000000
+#define DDRSS_CTL_157_DATA 0x00000000
+#define DDRSS_CTL_158_DATA 0x03050000
+#define DDRSS_CTL_159_DATA 0x040A040A
+#define DDRSS_CTL_160_DATA 0x00000000
+#define DDRSS_CTL_161_DATA 0x07010A09
+#define DDRSS_CTL_162_DATA 0x000E0A09
+#define DDRSS_CTL_163_DATA 0x010A0900
+#define DDRSS_CTL_164_DATA 0x0E0A0907
+#define DDRSS_CTL_165_DATA 0x0A090000
+#define DDRSS_CTL_166_DATA 0x0A090701
+#define DDRSS_CTL_167_DATA 0x0000000E
+#define DDRSS_CTL_168_DATA 0x00040003
+#define DDRSS_CTL_169_DATA 0x00000007
+#define DDRSS_CTL_170_DATA 0x00000000
+#define DDRSS_CTL_171_DATA 0x00000000
+#define DDRSS_CTL_172_DATA 0x00000000
+#define DDRSS_CTL_173_DATA 0x00000000
+#define DDRSS_CTL_174_DATA 0x00000000
+#define DDRSS_CTL_175_DATA 0x00000000
+#define DDRSS_CTL_176_DATA 0x01000000
+#define DDRSS_CTL_177_DATA 0x00000000
+#define DDRSS_CTL_178_DATA 0x00001700
+#define DDRSS_CTL_179_DATA 0x0000100E
+#define DDRSS_CTL_180_DATA 0x00000002
+#define DDRSS_CTL_181_DATA 0x00000000
+#define DDRSS_CTL_182_DATA 0x00000001
+#define DDRSS_CTL_183_DATA 0x00000002
+#define DDRSS_CTL_184_DATA 0x00000C00
+#define DDRSS_CTL_185_DATA 0x00008000
+#define DDRSS_CTL_186_DATA 0x00000C00
+#define DDRSS_CTL_187_DATA 0x00008000
+#define DDRSS_CTL_188_DATA 0x00000C00
+#define DDRSS_CTL_189_DATA 0x00008000
+#define DDRSS_CTL_190_DATA 0x00000000
+#define DDRSS_CTL_191_DATA 0x00000000
+#define DDRSS_CTL_192_DATA 0x00000000
+#define DDRSS_CTL_193_DATA 0x00000000
+#define DDRSS_CTL_194_DATA 0x00000000
+#define DDRSS_CTL_195_DATA 0x0005000A
+#define DDRSS_CTL_196_DATA 0x0404000D
+#define DDRSS_CTL_197_DATA 0x0000000D
+#define DDRSS_CTL_198_DATA 0x00BB0176
+#define DDRSS_CTL_199_DATA 0x0E0E01D3
+#define DDRSS_CTL_200_DATA 0x000001D3
+#define DDRSS_CTL_201_DATA 0x00BB0176
+#define DDRSS_CTL_202_DATA 0x0E0E01D3
+#define DDRSS_CTL_203_DATA 0x000001D3
+#define DDRSS_CTL_204_DATA 0x00000000
+#define DDRSS_CTL_205_DATA 0x00000000
+#define DDRSS_CTL_206_DATA 0x00000000
+#define DDRSS_CTL_207_DATA 0x00000000
+#define DDRSS_CTL_208_DATA 0x00000084
+#define DDRSS_CTL_209_DATA 0x00000000
+#define DDRSS_CTL_210_DATA 0x00000000
+#define DDRSS_CTL_211_DATA 0x000000E4
+#define DDRSS_CTL_212_DATA 0x00000036
+#define DDRSS_CTL_213_DATA 0x00000000
+#define DDRSS_CTL_214_DATA 0x000000E4
+#define DDRSS_CTL_215_DATA 0x00000036
+#define DDRSS_CTL_216_DATA 0x00000000
+#define DDRSS_CTL_217_DATA 0x00000084
+#define DDRSS_CTL_218_DATA 0x00000000
+#define DDRSS_CTL_219_DATA 0x00000000
+#define DDRSS_CTL_220_DATA 0x000000E4
+#define DDRSS_CTL_221_DATA 0x00000036
+#define DDRSS_CTL_222_DATA 0x00000000
+#define DDRSS_CTL_223_DATA 0x000000E4
+#define DDRSS_CTL_224_DATA 0x00000036
+#define DDRSS_CTL_225_DATA 0x00000000
+#define DDRSS_CTL_226_DATA 0x00000000
+#define DDRSS_CTL_227_DATA 0x00000033
+#define DDRSS_CTL_228_DATA 0x00000033
+#define DDRSS_CTL_229_DATA 0x00000033
+#define DDRSS_CTL_230_DATA 0x00000033
+#define DDRSS_CTL_231_DATA 0x00000033
+#define DDRSS_CTL_232_DATA 0x00000033
+#define DDRSS_CTL_233_DATA 0x00000000
+#define DDRSS_CTL_234_DATA 0x00000000
+#define DDRSS_CTL_235_DATA 0x00000000
+#define DDRSS_CTL_236_DATA 0x00000000
+#define DDRSS_CTL_237_DATA 0x00000000
+#define DDRSS_CTL_238_DATA 0x00000000
+#define DDRSS_CTL_239_DATA 0x00000000
+#define DDRSS_CTL_240_DATA 0x00000000
+#define DDRSS_CTL_241_DATA 0x00000000
+#define DDRSS_CTL_242_DATA 0x00000000
+#define DDRSS_CTL_243_DATA 0x00000000
+#define DDRSS_CTL_244_DATA 0x00000000
+#define DDRSS_CTL_245_DATA 0x00000000
+#define DDRSS_CTL_246_DATA 0x00000000
+#define DDRSS_CTL_247_DATA 0x00000000
+#define DDRSS_CTL_248_DATA 0x00000000
+#define DDRSS_CTL_249_DATA 0x00000000
+#define DDRSS_CTL_250_DATA 0x00000000
+#define DDRSS_CTL_251_DATA 0x00000000
+#define DDRSS_CTL_252_DATA 0x00000000
+#define DDRSS_CTL_253_DATA 0x00000000
+#define DDRSS_CTL_254_DATA 0x00000000
+#define DDRSS_CTL_255_DATA 0x00000000
+#define DDRSS_CTL_256_DATA 0x35000000
+#define DDRSS_CTL_257_DATA 0x35353535
+#define DDRSS_CTL_258_DATA 0x00002735
+#define DDRSS_CTL_259_DATA 0x00000027
+#define DDRSS_CTL_260_DATA 0x00000027
+#define DDRSS_CTL_261_DATA 0x00000027
+#define DDRSS_CTL_262_DATA 0x00000027
+#define DDRSS_CTL_263_DATA 0x00000027
+#define DDRSS_CTL_264_DATA 0x00000000
+#define DDRSS_CTL_265_DATA 0x00000000
+#define DDRSS_CTL_266_DATA 0x0000000F
+#define DDRSS_CTL_267_DATA 0x0000000F
+#define DDRSS_CTL_268_DATA 0x0000000F
+#define DDRSS_CTL_269_DATA 0x0000000F
+#define DDRSS_CTL_270_DATA 0x0000000F
+#define DDRSS_CTL_271_DATA 0x0000000F
+#define DDRSS_CTL_272_DATA 0x00000000
+#define DDRSS_CTL_273_DATA 0x00001600
+#define DDRSS_CTL_274_DATA 0x00000016
+#define DDRSS_CTL_275_DATA 0x00000016
+#define DDRSS_CTL_276_DATA 0x00000016
+#define DDRSS_CTL_277_DATA 0x00000016
+#define DDRSS_CTL_278_DATA 0x00000016
+#define DDRSS_CTL_279_DATA 0x00000020
+#define DDRSS_CTL_280_DATA 0x00010000
+#define DDRSS_CTL_281_DATA 0x00000100
+#define DDRSS_CTL_282_DATA 0x00000000
+#define DDRSS_CTL_283_DATA 0x00000000
+#define DDRSS_CTL_284_DATA 0x00000101
+#define DDRSS_CTL_285_DATA 0x00000000
+#define DDRSS_CTL_286_DATA 0x00000000
+#define DDRSS_CTL_287_DATA 0x00000000
+#define DDRSS_CTL_288_DATA 0x00000000
+#define DDRSS_CTL_289_DATA 0x00000000
+#define DDRSS_CTL_290_DATA 0x00000000
+#define DDRSS_CTL_291_DATA 0x00000000
+#define DDRSS_CTL_292_DATA 0x00000000
+#define DDRSS_CTL_293_DATA 0x00000000
+#define DDRSS_CTL_294_DATA 0x00000000
+#define DDRSS_CTL_295_DATA 0x00000000
+#define DDRSS_CTL_296_DATA 0x0C181511
+#define DDRSS_CTL_297_DATA 0x00000304
+#define DDRSS_CTL_298_DATA 0x00000000
+#define DDRSS_CTL_299_DATA 0x00000000
+#define DDRSS_CTL_300_DATA 0x00000000
+#define DDRSS_CTL_301_DATA 0x00000000
+#define DDRSS_CTL_302_DATA 0x00000000
+#define DDRSS_CTL_303_DATA 0x00000000
+#define DDRSS_CTL_304_DATA 0x00000000
+#define DDRSS_CTL_305_DATA 0x00000000
+#define DDRSS_CTL_306_DATA 0x00000000
+#define DDRSS_CTL_307_DATA 0x00000000
+#define DDRSS_CTL_308_DATA 0x00000000
+#define DDRSS_CTL_309_DATA 0x00000000
+#define DDRSS_CTL_310_DATA 0x00000000
+#define DDRSS_CTL_311_DATA 0x00020000
+#define DDRSS_CTL_312_DATA 0x00400100
+#define DDRSS_CTL_313_DATA 0x00080032
+#define DDRSS_CTL_314_DATA 0x01000200
+#define DDRSS_CTL_315_DATA 0x074A0040
+#define DDRSS_CTL_316_DATA 0x00020038
+#define DDRSS_CTL_317_DATA 0x00400100
+#define DDRSS_CTL_318_DATA 0x0038074A
+#define DDRSS_CTL_319_DATA 0x00030000
+#define DDRSS_CTL_320_DATA 0x005E005E
+#define DDRSS_CTL_321_DATA 0x00000100
+#define DDRSS_CTL_322_DATA 0x01010000
+#define DDRSS_CTL_323_DATA 0x00000101
+#define DDRSS_CTL_324_DATA 0x1FFF0000
+#define DDRSS_CTL_325_DATA 0x000FFF00
+#define DDRSS_CTL_326_DATA 0x3FFF2000
+#define DDRSS_CTL_327_DATA 0x000FFF00
+#define DDRSS_CTL_328_DATA 0x0B000001
+#define DDRSS_CTL_329_DATA 0x0001FFFF
+#define DDRSS_CTL_330_DATA 0x01010101
+#define DDRSS_CTL_331_DATA 0x01010101
+#define DDRSS_CTL_332_DATA 0x00000118
+#define DDRSS_CTL_333_DATA 0x00000C03
+#define DDRSS_CTL_334_DATA 0x00040100
+#define DDRSS_CTL_335_DATA 0x00040100
+#define DDRSS_CTL_336_DATA 0x00000000
+#define DDRSS_CTL_337_DATA 0x00000000
+#define DDRSS_CTL_338_DATA 0x01030303
+#define DDRSS_CTL_339_DATA 0x00000000
+#define DDRSS_CTL_340_DATA 0x00000000
+#define DDRSS_CTL_341_DATA 0x00000000
+#define DDRSS_CTL_342_DATA 0x00000000
+#define DDRSS_CTL_343_DATA 0x00000000
+#define DDRSS_CTL_344_DATA 0x00000000
+#define DDRSS_CTL_345_DATA 0x00000000
+#define DDRSS_CTL_346_DATA 0x00000000
+#define DDRSS_CTL_347_DATA 0x00000000
+#define DDRSS_CTL_348_DATA 0x00000000
+#define DDRSS_CTL_349_DATA 0x00000000
+#define DDRSS_CTL_350_DATA 0x00000000
+#define DDRSS_CTL_351_DATA 0x00000000
+#define DDRSS_CTL_352_DATA 0x00000000
+#define DDRSS_CTL_353_DATA 0x00000000
+#define DDRSS_CTL_354_DATA 0x00000000
+#define DDRSS_CTL_355_DATA 0x00000000
+#define DDRSS_CTL_356_DATA 0x00000000
+#define DDRSS_CTL_357_DATA 0x00000000
+#define DDRSS_CTL_358_DATA 0x00000000
+#define DDRSS_CTL_359_DATA 0x00000000
+#define DDRSS_CTL_360_DATA 0x00000000
+#define DDRSS_CTL_361_DATA 0x00000000
+#define DDRSS_CTL_362_DATA 0x00000000
+#define DDRSS_CTL_363_DATA 0x00000000
+#define DDRSS_CTL_364_DATA 0x00000000
+#define DDRSS_CTL_365_DATA 0x00000000
+#define DDRSS_CTL_366_DATA 0x00000000
+#define DDRSS_CTL_367_DATA 0x00000000
+#define DDRSS_CTL_368_DATA 0x00000000
+#define DDRSS_CTL_369_DATA 0x00000000
+#define DDRSS_CTL_370_DATA 0x00000000
+#define DDRSS_CTL_371_DATA 0x00000000
+#define DDRSS_CTL_372_DATA 0x00000000
+#define DDRSS_CTL_373_DATA 0x00000000
+#define DDRSS_CTL_374_DATA 0x00000000
+#define DDRSS_CTL_375_DATA 0x00000000
+#define DDRSS_CTL_376_DATA 0x00000000
+#define DDRSS_CTL_377_DATA 0x00000000
+#define DDRSS_CTL_378_DATA 0x00000000
+#define DDRSS_CTL_379_DATA 0x00000000
+#define DDRSS_CTL_380_DATA 0x00000000
+#define DDRSS_CTL_381_DATA 0x00000000
+#define DDRSS_CTL_382_DATA 0x00000000
+#define DDRSS_CTL_383_DATA 0x01000101
+#define DDRSS_CTL_384_DATA 0x01010001
+#define DDRSS_CTL_385_DATA 0x00010101
+#define DDRSS_CTL_386_DATA 0x01090903
+#define DDRSS_CTL_387_DATA 0x05020201
+#define DDRSS_CTL_388_DATA 0x0E081B1B
+#define DDRSS_CTL_389_DATA 0x0009040E
+#define DDRSS_CTL_390_DATA 0x0B0D040F
+#define DDRSS_CTL_391_DATA 0x0B0D0406
+#define DDRSS_CTL_392_DATA 0x0D0D0906
+#define DDRSS_CTL_393_DATA 0x01000000
+#define DDRSS_CTL_394_DATA 0x07030701
+#define DDRSS_CTL_395_DATA 0x04000103
+#define DDRSS_CTL_396_DATA 0x1B000004
+#define DDRSS_CTL_397_DATA 0x000000B2
+#define DDRSS_CTL_398_DATA 0x00000200
+#define DDRSS_CTL_399_DATA 0x00000200
+#define DDRSS_CTL_400_DATA 0x00000200
+#define DDRSS_CTL_401_DATA 0x00000200
+#define DDRSS_CTL_402_DATA 0x00000321
+#define DDRSS_CTL_403_DATA 0x000006F4
+#define DDRSS_CTL_404_DATA 0x03000202
+#define DDRSS_CTL_405_DATA 0x37200201
+#define DDRSS_CTL_406_DATA 0x00001C5C
+#define DDRSS_CTL_407_DATA 0x00000200
+#define DDRSS_CTL_408_DATA 0x00000200
+#define DDRSS_CTL_409_DATA 0x00000200
+#define DDRSS_CTL_410_DATA 0x00000200
+#define DDRSS_CTL_411_DATA 0x00007F9E
+#define DDRSS_CTL_412_DATA 0x00011B98
+#define DDRSS_CTL_413_DATA 0x111A0402
+#define DDRSS_CTL_414_DATA 0x37200C09
+#define DDRSS_CTL_415_DATA 0x00001C5C
+#define DDRSS_CTL_416_DATA 0x00000200
+#define DDRSS_CTL_417_DATA 0x00000200
+#define DDRSS_CTL_418_DATA 0x00000200
+#define DDRSS_CTL_419_DATA 0x00000200
+#define DDRSS_CTL_420_DATA 0x00007F9E
+#define DDRSS_CTL_421_DATA 0x00011B98
+#define DDRSS_CTL_422_DATA 0x111A0402
+#define DDRSS_CTL_423_DATA 0x00200C09
+#define DDRSS_CTL_424_DATA 0x00000000
+#define DDRSS_CTL_425_DATA 0x02000A00
+#define DDRSS_CTL_426_DATA 0x00050003
+#define DDRSS_CTL_427_DATA 0x00010101
+#define DDRSS_CTL_428_DATA 0x00010101
+#define DDRSS_CTL_429_DATA 0x00010001
+#define DDRSS_CTL_430_DATA 0x00000101
+#define DDRSS_CTL_431_DATA 0x02000201
+#define DDRSS_CTL_432_DATA 0x02010000
+#define DDRSS_CTL_433_DATA 0x06000200
+#define DDRSS_CTL_434_DATA 0x00002222
+#define DDRSS_PI_0_DATA 0x00000B00
+#define DDRSS_PI_1_DATA 0x00000000
+#define DDRSS_PI_2_DATA 0x00000000
+#define DDRSS_PI_3_DATA 0x01000000
+#define DDRSS_PI_4_DATA 0x00000001
+#define DDRSS_PI_5_DATA 0x00010064
+#define DDRSS_PI_6_DATA 0x00000000
+#define DDRSS_PI_7_DATA 0x00000000
+#define DDRSS_PI_8_DATA 0x00000000
+#define DDRSS_PI_9_DATA 0x00000000
+#define DDRSS_PI_10_DATA 0x00000000
+#define DDRSS_PI_11_DATA 0x00000002
+#define DDRSS_PI_12_DATA 0x00000005
+#define DDRSS_PI_13_DATA 0x000F0001
+#define DDRSS_PI_14_DATA 0x08000000
+#define DDRSS_PI_15_DATA 0x00010300
+#define DDRSS_PI_16_DATA 0x00000005
+#define DDRSS_PI_17_DATA 0x00000000
+#define DDRSS_PI_18_DATA 0x00000000
+#define DDRSS_PI_19_DATA 0x00000000
+#define DDRSS_PI_20_DATA 0x00000000
+#define DDRSS_PI_21_DATA 0x00000000
+#define DDRSS_PI_22_DATA 0x00000000
+#define DDRSS_PI_23_DATA 0x00000000
+#define DDRSS_PI_24_DATA 0x00000000
+#define DDRSS_PI_25_DATA 0x00000000
+#define DDRSS_PI_26_DATA 0x01010000
+#define DDRSS_PI_27_DATA 0x0A000100
+#define DDRSS_PI_28_DATA 0x00000028
+#define DDRSS_PI_29_DATA 0x0F000000
+#define DDRSS_PI_30_DATA 0x00320000
+#define DDRSS_PI_31_DATA 0x00000000
+#define DDRSS_PI_32_DATA 0x00000000
+#define DDRSS_PI_33_DATA 0x01010102
+#define DDRSS_PI_34_DATA 0x00000000
+#define DDRSS_PI_35_DATA 0x00000000
+#define DDRSS_PI_36_DATA 0x00000000
+#define DDRSS_PI_37_DATA 0x00000001
+#define DDRSS_PI_38_DATA 0x000000AA
+#define DDRSS_PI_39_DATA 0x00000055
+#define DDRSS_PI_40_DATA 0x000000B5
+#define DDRSS_PI_41_DATA 0x0000004A
+#define DDRSS_PI_42_DATA 0x00000056
+#define DDRSS_PI_43_DATA 0x000000A9
+#define DDRSS_PI_44_DATA 0x000000A9
+#define DDRSS_PI_45_DATA 0x000000B5
+#define DDRSS_PI_46_DATA 0x00000000
+#define DDRSS_PI_47_DATA 0x00000000
+#define DDRSS_PI_48_DATA 0x000F0F00
+#define DDRSS_PI_49_DATA 0x0000001A
+#define DDRSS_PI_50_DATA 0x000007D0
+#define DDRSS_PI_51_DATA 0x00000300
+#define DDRSS_PI_52_DATA 0x00000000
+#define DDRSS_PI_53_DATA 0x00000000
+#define DDRSS_PI_54_DATA 0x01000000
+#define DDRSS_PI_55_DATA 0x00010101
+#define DDRSS_PI_56_DATA 0x01000000
+#define DDRSS_PI_57_DATA 0x03000000
+#define DDRSS_PI_58_DATA 0x00000000
+#define DDRSS_PI_59_DATA 0x0000170F
+#define DDRSS_PI_60_DATA 0x00000000
+#define DDRSS_PI_61_DATA 0x00000000
+#define DDRSS_PI_62_DATA 0x00000000
+#define DDRSS_PI_63_DATA 0x0A0A140A
+#define DDRSS_PI_64_DATA 0x10020101
+#define DDRSS_PI_65_DATA 0x01000210
+#define DDRSS_PI_66_DATA 0x05000404
+#define DDRSS_PI_67_DATA 0x00010001
+#define DDRSS_PI_68_DATA 0x0001000E
+#define DDRSS_PI_69_DATA 0x01010F00
+#define DDRSS_PI_70_DATA 0x00010000
+#define DDRSS_PI_71_DATA 0x00000034
+#define DDRSS_PI_72_DATA 0x00000000
+#define DDRSS_PI_73_DATA 0x00000000
+#define DDRSS_PI_74_DATA 0x0000FFFF
+#define DDRSS_PI_75_DATA 0x00000000
+#define DDRSS_PI_76_DATA 0x00000000
+#define DDRSS_PI_77_DATA 0x00000000
+#define DDRSS_PI_78_DATA 0x00000000
+#define DDRSS_PI_79_DATA 0x01000000
+#define DDRSS_PI_80_DATA 0x01010001
+#define DDRSS_PI_81_DATA 0x02000008
+#define DDRSS_PI_82_DATA 0x01000200
+#define DDRSS_PI_83_DATA 0x00000100
+#define DDRSS_PI_84_DATA 0x02000100
+#define DDRSS_PI_85_DATA 0x02000200
+#define DDRSS_PI_86_DATA 0x00000000
+#define DDRSS_PI_87_DATA 0x00000000
+#define DDRSS_PI_88_DATA 0x00000000
+#define DDRSS_PI_89_DATA 0x00000000
+#define DDRSS_PI_90_DATA 0x00000000
+#define DDRSS_PI_91_DATA 0x00000000
+#define DDRSS_PI_92_DATA 0x00000000
+#define DDRSS_PI_93_DATA 0x00000000
+#define DDRSS_PI_94_DATA 0x00000000
+#define DDRSS_PI_95_DATA 0x00000000
+#define DDRSS_PI_96_DATA 0x00000000
+#define DDRSS_PI_97_DATA 0x00000000
+#define DDRSS_PI_98_DATA 0x00000000
+#define DDRSS_PI_99_DATA 0x01000400
+#define DDRSS_PI_100_DATA 0x0E0D0F12
+#define DDRSS_PI_101_DATA 0x08111413
+#define DDRSS_PI_102_DATA 0x01000009
+#define DDRSS_PI_103_DATA 0x00000302
+#define DDRSS_PI_104_DATA 0x00000008
+#define DDRSS_PI_105_DATA 0x08000000
+#define DDRSS_PI_106_DATA 0x00000100
+#define DDRSS_PI_107_DATA 0x00000000
+#define DDRSS_PI_108_DATA 0x0000AA00
+#define DDRSS_PI_109_DATA 0x00000000
+#define DDRSS_PI_110_DATA 0x00000000
+#define DDRSS_PI_111_DATA 0x00010000
+#define DDRSS_PI_112_DATA 0x00000000
+#define DDRSS_PI_113_DATA 0x00000000
+#define DDRSS_PI_114_DATA 0x00000000
+#define DDRSS_PI_115_DATA 0x00000000
+#define DDRSS_PI_116_DATA 0x00000000
+#define DDRSS_PI_117_DATA 0x00000000
+#define DDRSS_PI_118_DATA 0x00000000
+#define DDRSS_PI_119_DATA 0x00000000
+#define DDRSS_PI_120_DATA 0x00000000
+#define DDRSS_PI_121_DATA 0x00000000
+#define DDRSS_PI_122_DATA 0x00000000
+#define DDRSS_PI_123_DATA 0x00000000
+#define DDRSS_PI_124_DATA 0x00000000
+#define DDRSS_PI_125_DATA 0x00000000
+#define DDRSS_PI_126_DATA 0x00000000
+#define DDRSS_PI_127_DATA 0x00000000
+#define DDRSS_PI_128_DATA 0x00000000
+#define DDRSS_PI_129_DATA 0x00000000
+#define DDRSS_PI_130_DATA 0x00000000
+#define DDRSS_PI_131_DATA 0x00000000
+#define DDRSS_PI_132_DATA 0x00000000
+#define DDRSS_PI_133_DATA 0x00000000
+#define DDRSS_PI_134_DATA 0x00000000
+#define DDRSS_PI_135_DATA 0x00000000
+#define DDRSS_PI_136_DATA 0x00000008
+#define DDRSS_PI_137_DATA 0x00000000
+#define DDRSS_PI_138_DATA 0x00000000
+#define DDRSS_PI_139_DATA 0x00000000
+#define DDRSS_PI_140_DATA 0x00000000
+#define DDRSS_PI_141_DATA 0x00000000
+#define DDRSS_PI_142_DATA 0x00000000
+#define DDRSS_PI_143_DATA 0x00000000
+#define DDRSS_PI_144_DATA 0x00000000
+#define DDRSS_PI_145_DATA 0x00010000
+#define DDRSS_PI_146_DATA 0x00000000
+#define DDRSS_PI_147_DATA 0x00000000
+#define DDRSS_PI_148_DATA 0x0000000A
+#define DDRSS_PI_149_DATA 0x000186A0
+#define DDRSS_PI_150_DATA 0x00000100
+#define DDRSS_PI_151_DATA 0x00000000
+#define DDRSS_PI_152_DATA 0x00000000
+#define DDRSS_PI_153_DATA 0x00000000
+#define DDRSS_PI_154_DATA 0x00000000
+#define DDRSS_PI_155_DATA 0x00000000
+#define DDRSS_PI_156_DATA 0x01000000
+#define DDRSS_PI_157_DATA 0x00010003
+#define DDRSS_PI_158_DATA 0x02000101
+#define DDRSS_PI_159_DATA 0x01030001
+#define DDRSS_PI_160_DATA 0x00010400
+#define DDRSS_PI_161_DATA 0x06000105
+#define DDRSS_PI_162_DATA 0x01070001
+#define DDRSS_PI_163_DATA 0x00000000
+#define DDRSS_PI_164_DATA 0x00000000
+#define DDRSS_PI_165_DATA 0x00000000
+#define DDRSS_PI_166_DATA 0x00010001
+#define DDRSS_PI_167_DATA 0x00000000
+#define DDRSS_PI_168_DATA 0x00000000
+#define DDRSS_PI_169_DATA 0x00000000
+#define DDRSS_PI_170_DATA 0x00000000
+#define DDRSS_PI_171_DATA 0x00010000
+#define DDRSS_PI_172_DATA 0x00000004
+#define DDRSS_PI_173_DATA 0x00000000
+#define DDRSS_PI_174_DATA 0x00010000
+#define DDRSS_PI_175_DATA 0x00000000
+#define DDRSS_PI_176_DATA 0x00080000
+#define DDRSS_PI_177_DATA 0x01180118
+#define DDRSS_PI_178_DATA 0x00262601
+#define DDRSS_PI_179_DATA 0x00000034
+#define DDRSS_PI_180_DATA 0x0000005E
+#define DDRSS_PI_181_DATA 0x0002005E
+#define DDRSS_PI_182_DATA 0x02000200
+#define DDRSS_PI_183_DATA 0x00000004
+#define DDRSS_PI_184_DATA 0x0000100C
+#define DDRSS_PI_185_DATA 0x00104000
+#define DDRSS_PI_186_DATA 0x00400000
+#define DDRSS_PI_187_DATA 0x00000013
+#define DDRSS_PI_188_DATA 0x00000059
+#define DDRSS_PI_189_DATA 0x000002C5
+#define DDRSS_PI_190_DATA 0x00000E2E
+#define DDRSS_PI_191_DATA 0x000002C5
+#define DDRSS_PI_192_DATA 0x04000E2E
+#define DDRSS_PI_193_DATA 0x01010404
+#define DDRSS_PI_194_DATA 0x00001501
+#define DDRSS_PI_195_DATA 0x00270027
+#define DDRSS_PI_196_DATA 0x01000100
+#define DDRSS_PI_197_DATA 0x00000100
+#define DDRSS_PI_198_DATA 0x00000000
+#define DDRSS_PI_199_DATA 0x05090903
+#define DDRSS_PI_200_DATA 0x01011B1B
+#define DDRSS_PI_201_DATA 0x01010101
+#define DDRSS_PI_202_DATA 0x000C0C0A
+#define DDRSS_PI_203_DATA 0x00000000
+#define DDRSS_PI_204_DATA 0x00000000
+#define DDRSS_PI_205_DATA 0x04000000
+#define DDRSS_PI_206_DATA 0x0C021212
+#define DDRSS_PI_207_DATA 0x0404020C
+#define DDRSS_PI_208_DATA 0x00090031
+#define DDRSS_PI_209_DATA 0x001B0043
+#define DDRSS_PI_210_DATA 0x001B0043
+#define DDRSS_PI_211_DATA 0x01010101
+#define DDRSS_PI_212_DATA 0x0003000D
+#define DDRSS_PI_213_DATA 0x000301D3
+#define DDRSS_PI_214_DATA 0x010001D3
+#define DDRSS_PI_215_DATA 0x000E000E
+#define DDRSS_PI_216_DATA 0x01D40100
+#define DDRSS_PI_217_DATA 0x010001D4
+#define DDRSS_PI_218_DATA 0x01D401D4
+#define DDRSS_PI_219_DATA 0x32103200
+#define DDRSS_PI_220_DATA 0x01013210
+#define DDRSS_PI_221_DATA 0x0A070601
+#define DDRSS_PI_222_DATA 0x1C11090D
+#define DDRSS_PI_223_DATA 0x1C110913
+#define DDRSS_PI_224_DATA 0x000C0013
+#define DDRSS_PI_225_DATA 0x00001000
+#define DDRSS_PI_226_DATA 0x00000C00
+#define DDRSS_PI_227_DATA 0x00001000
+#define DDRSS_PI_228_DATA 0x00000C00
+#define DDRSS_PI_229_DATA 0x02001000
+#define DDRSS_PI_230_DATA 0x0021000D
+#define DDRSS_PI_231_DATA 0x002101D3
+#define DDRSS_PI_232_DATA 0x000001D3
+#define DDRSS_PI_233_DATA 0x00001900
+#define DDRSS_PI_234_DATA 0x32000056
+#define DDRSS_PI_235_DATA 0x06000301
+#define DDRSS_PI_236_DATA 0x00300204
+#define DDRSS_PI_237_DATA 0x3212005A
+#define DDRSS_PI_238_DATA 0x17000301
+#define DDRSS_PI_239_DATA 0x00300C12
+#define DDRSS_PI_240_DATA 0x3212005A
+#define DDRSS_PI_241_DATA 0x17000301
+#define DDRSS_PI_242_DATA 0x00000C12
+#define DDRSS_PI_243_DATA 0x05040900
+#define DDRSS_PI_244_DATA 0x00040900
+#define DDRSS_PI_245_DATA 0x00000315
+#define DDRSS_PI_246_DATA 0x20010004
+#define DDRSS_PI_247_DATA 0x0A0A0A03
+#define DDRSS_PI_248_DATA 0x2B0F0000
+#define DDRSS_PI_249_DATA 0x24140026
+#define DDRSS_PI_250_DATA 0x0000731B
+#define DDRSS_PI_251_DATA 0x20070054
+#define DDRSS_PI_252_DATA 0x1B131B1C
+#define DDRSS_PI_253_DATA 0x2B0F0000
+#define DDRSS_PI_254_DATA 0x24140026
+#define DDRSS_PI_255_DATA 0x0000731B
+#define DDRSS_PI_256_DATA 0x20070054
+#define DDRSS_PI_257_DATA 0x1B131B1C
+#define DDRSS_PI_258_DATA 0x00000000
+#define DDRSS_PI_259_DATA 0x000000B2
+#define DDRSS_PI_260_DATA 0x000006F4
+#define DDRSS_PI_261_DATA 0x00001C5C
+#define DDRSS_PI_262_DATA 0x00011B98
+#define DDRSS_PI_263_DATA 0x00001C5C
+#define DDRSS_PI_264_DATA 0x00011B98
+#define DDRSS_PI_265_DATA 0x02D30014
+#define DDRSS_PI_266_DATA 0x030302D3
+#define DDRSS_PI_267_DATA 0x00000003
+#define DDRSS_PI_268_DATA 0x00000000
+#define DDRSS_PI_269_DATA 0x0A040503
+#define DDRSS_PI_270_DATA 0x00000A04
+#define DDRSS_PI_271_DATA 0x00002710
+#define DDRSS_PI_272_DATA 0x000186A0
+#define DDRSS_PI_273_DATA 0x00000005
+#define DDRSS_PI_274_DATA 0x00000064
+#define DDRSS_PI_275_DATA 0x00000014
+#define DDRSS_PI_276_DATA 0x0005B18F
+#define DDRSS_PI_277_DATA 0x000186A0
+#define DDRSS_PI_278_DATA 0x00000005
+#define DDRSS_PI_279_DATA 0x00000E94
+#define DDRSS_PI_280_DATA 0x000002D3
+#define DDRSS_PI_281_DATA 0x0005B18F
+#define DDRSS_PI_282_DATA 0x000186A0
+#define DDRSS_PI_283_DATA 0x00000005
+#define DDRSS_PI_284_DATA 0x00000E94
+#define DDRSS_PI_285_DATA 0x010002D3
+#define DDRSS_PI_286_DATA 0x00320040
+#define DDRSS_PI_287_DATA 0x00010008
+#define DDRSS_PI_288_DATA 0x074A0040
+#define DDRSS_PI_289_DATA 0x00010038
+#define DDRSS_PI_290_DATA 0x074A0040
+#define DDRSS_PI_291_DATA 0x00000338
+#define DDRSS_PI_292_DATA 0x0028005D
+#define DDRSS_PI_293_DATA 0x03040404
+#define DDRSS_PI_294_DATA 0x00000303
+#define DDRSS_PI_295_DATA 0x01010000
+#define DDRSS_PI_296_DATA 0x04040202
+#define DDRSS_PI_297_DATA 0x67670808
+#define DDRSS_PI_298_DATA 0x67676767
+#define DDRSS_PI_299_DATA 0x67676767
+#define DDRSS_PI_300_DATA 0x67676767
+#define DDRSS_PI_301_DATA 0x00006767
+#define DDRSS_PI_302_DATA 0x00000000
+#define DDRSS_PI_303_DATA 0x00000000
+#define DDRSS_PI_304_DATA 0x00000000
+#define DDRSS_PI_305_DATA 0x00000000
+#define DDRSS_PI_306_DATA 0x55000000
+#define DDRSS_PI_307_DATA 0x00000000
+#define DDRSS_PI_308_DATA 0x3C00005A
+#define DDRSS_PI_309_DATA 0x00005500
+#define DDRSS_PI_310_DATA 0x00005A00
+#define DDRSS_PI_311_DATA 0x0055003C
+#define DDRSS_PI_312_DATA 0x00000000
+#define DDRSS_PI_313_DATA 0x3C00005A
+#define DDRSS_PI_314_DATA 0x00005500
+#define DDRSS_PI_315_DATA 0x00005A00
+#define DDRSS_PI_316_DATA 0x1716153C
+#define DDRSS_PI_317_DATA 0x13100A18
+#define DDRSS_PI_318_DATA 0x06050414
+#define DDRSS_PI_319_DATA 0x02010007
+#define DDRSS_PI_320_DATA 0x00000003
+#define DDRSS_PI_321_DATA 0x00000000
+#define DDRSS_PI_322_DATA 0x00000000
+#define DDRSS_PI_323_DATA 0x01000000
+#define DDRSS_PI_324_DATA 0x04020201
+#define DDRSS_PI_325_DATA 0x00080804
+#define DDRSS_PI_326_DATA 0x00000000
+#define DDRSS_PI_327_DATA 0x00000000
+#define DDRSS_PI_328_DATA 0x00000000
+#define DDRSS_PI_329_DATA 0x00000084
+#define DDRSS_PI_330_DATA 0x00000000
+#define DDRSS_PI_331_DATA 0x00000033
+#define DDRSS_PI_332_DATA 0x00000000
+#define DDRSS_PI_333_DATA 0x00000000
+#define DDRSS_PI_334_DATA 0x35000000
+#define DDRSS_PI_335_DATA 0x20160F27
+#define DDRSS_PI_336_DATA 0x00000000
+#define DDRSS_PI_337_DATA 0x000000E4
+#define DDRSS_PI_338_DATA 0x00000036
+#define DDRSS_PI_339_DATA 0x00000033
+#define DDRSS_PI_340_DATA 0x00000000
+#define DDRSS_PI_341_DATA 0x00000000
+#define DDRSS_PI_342_DATA 0x35000000
+#define DDRSS_PI_343_DATA 0x20160F27
+#define DDRSS_PI_344_DATA 0x00000000
+#define DDRSS_PI_345_DATA 0x000000E4
+#define DDRSS_PI_346_DATA 0x00000036
+#define DDRSS_PI_347_DATA 0x00000033
+#define DDRSS_PI_348_DATA 0x00000000
+#define DDRSS_PI_349_DATA 0x00000000
+#define DDRSS_PI_350_DATA 0x35000000
+#define DDRSS_PI_351_DATA 0x20160F27
+#define DDRSS_PI_352_DATA 0x00000000
+#define DDRSS_PI_353_DATA 0x00000084
+#define DDRSS_PI_354_DATA 0x00000000
+#define DDRSS_PI_355_DATA 0x00000033
+#define DDRSS_PI_356_DATA 0x00000000
+#define DDRSS_PI_357_DATA 0x00000000
+#define DDRSS_PI_358_DATA 0x35000000
+#define DDRSS_PI_359_DATA 0x20160F27
+#define DDRSS_PI_360_DATA 0x00000000
+#define DDRSS_PI_361_DATA 0x000000E4
+#define DDRSS_PI_362_DATA 0x00000036
+#define DDRSS_PI_363_DATA 0x00000033
+#define DDRSS_PI_364_DATA 0x00000000
+#define DDRSS_PI_365_DATA 0x00000000
+#define DDRSS_PI_366_DATA 0x35000000
+#define DDRSS_PI_367_DATA 0x20160F27
+#define DDRSS_PI_368_DATA 0x00000000
+#define DDRSS_PI_369_DATA 0x000000E4
+#define DDRSS_PI_370_DATA 0x00000036
+#define DDRSS_PI_371_DATA 0x00000033
+#define DDRSS_PI_372_DATA 0x00000000
+#define DDRSS_PI_373_DATA 0x00000000
+#define DDRSS_PI_374_DATA 0x35000000
+#define DDRSS_PI_375_DATA 0x20160F27
+#define DDRSS_PI_376_DATA 0x00000000
+#define DDRSS_PI_377_DATA 0x00000084
+#define DDRSS_PI_378_DATA 0x00000000
+#define DDRSS_PI_379_DATA 0x00000033
+#define DDRSS_PI_380_DATA 0x00000000
+#define DDRSS_PI_381_DATA 0x00000000
+#define DDRSS_PI_382_DATA 0x35000000
+#define DDRSS_PI_383_DATA 0x20160F27
+#define DDRSS_PI_384_DATA 0x00000000
+#define DDRSS_PI_385_DATA 0x000000E4
+#define DDRSS_PI_386_DATA 0x00000036
+#define DDRSS_PI_387_DATA 0x00000033
+#define DDRSS_PI_388_DATA 0x00000000
+#define DDRSS_PI_389_DATA 0x00000000
+#define DDRSS_PI_390_DATA 0x35000000
+#define DDRSS_PI_391_DATA 0x20160F27
+#define DDRSS_PI_392_DATA 0x00000000
+#define DDRSS_PI_393_DATA 0x000000E4
+#define DDRSS_PI_394_DATA 0x00000036
+#define DDRSS_PI_395_DATA 0x00000033
+#define DDRSS_PI_396_DATA 0x00000000
+#define DDRSS_PI_397_DATA 0x00000000
+#define DDRSS_PI_398_DATA 0x35000000
+#define DDRSS_PI_399_DATA 0x20160F27
+#define DDRSS_PI_400_DATA 0x00000000
+#define DDRSS_PI_401_DATA 0x00000084
+#define DDRSS_PI_402_DATA 0x00000000
+#define DDRSS_PI_403_DATA 0x00000033
+#define DDRSS_PI_404_DATA 0x00000000
+#define DDRSS_PI_405_DATA 0x00000000
+#define DDRSS_PI_406_DATA 0x35000000
+#define DDRSS_PI_407_DATA 0x20160F27
+#define DDRSS_PI_408_DATA 0x00000000
+#define DDRSS_PI_409_DATA 0x000000E4
+#define DDRSS_PI_410_DATA 0x00000036
+#define DDRSS_PI_411_DATA 0x00000033
+#define DDRSS_PI_412_DATA 0x00000000
+#define DDRSS_PI_413_DATA 0x00000000
+#define DDRSS_PI_414_DATA 0x35000000
+#define DDRSS_PI_415_DATA 0x20160F27
+#define DDRSS_PI_416_DATA 0x00000000
+#define DDRSS_PI_417_DATA 0x000000E4
+#define DDRSS_PI_418_DATA 0x00000036
+#define DDRSS_PI_419_DATA 0x00000033
+#define DDRSS_PI_420_DATA 0x00000000
+#define DDRSS_PI_421_DATA 0x00000000
+#define DDRSS_PI_422_DATA 0x35000000
+#define DDRSS_PI_423_DATA 0x20160F27
+#define DDRSS_PHY_0_DATA 0x04F00000
+#define DDRSS_PHY_1_DATA 0x00000000
+#define DDRSS_PHY_2_DATA 0x00030200
+#define DDRSS_PHY_3_DATA 0x00000000
+#define DDRSS_PHY_4_DATA 0x00000000
+#define DDRSS_PHY_5_DATA 0x01030000
+#define DDRSS_PHY_6_DATA 0x00010000
+#define DDRSS_PHY_7_DATA 0x01030004
+#define DDRSS_PHY_8_DATA 0x01000000
+#define DDRSS_PHY_9_DATA 0x00000000
+#define DDRSS_PHY_10_DATA 0x00000000
+#define DDRSS_PHY_11_DATA 0x00000000
+#define DDRSS_PHY_12_DATA 0x01010000
+#define DDRSS_PHY_13_DATA 0x00010000
+#define DDRSS_PHY_14_DATA 0x00C00001
+#define DDRSS_PHY_15_DATA 0x00CC0008
+#define DDRSS_PHY_16_DATA 0x00660601
+#define DDRSS_PHY_17_DATA 0x00000003
+#define DDRSS_PHY_18_DATA 0x00000000
+#define DDRSS_PHY_19_DATA 0x00000301
+#define DDRSS_PHY_20_DATA 0x0000AAAA
+#define DDRSS_PHY_21_DATA 0x00005555
+#define DDRSS_PHY_22_DATA 0x0000B5B5
+#define DDRSS_PHY_23_DATA 0x00004A4A
+#define DDRSS_PHY_24_DATA 0x00005656
+#define DDRSS_PHY_25_DATA 0x0000A9A9
+#define DDRSS_PHY_26_DATA 0x0000B7B7
+#define DDRSS_PHY_27_DATA 0x00004848
+#define DDRSS_PHY_28_DATA 0x00000000
+#define DDRSS_PHY_29_DATA 0x00000000
+#define DDRSS_PHY_30_DATA 0x08000000
+#define DDRSS_PHY_31_DATA 0x0F000008
+#define DDRSS_PHY_32_DATA 0x00000F0F
+#define DDRSS_PHY_33_DATA 0x00E4E400
+#define DDRSS_PHY_34_DATA 0x00071040
+#define DDRSS_PHY_35_DATA 0x000C0020
+#define DDRSS_PHY_36_DATA 0x00062000
+#define DDRSS_PHY_37_DATA 0x00000000
+#define DDRSS_PHY_38_DATA 0x55555555
+#define DDRSS_PHY_39_DATA 0xAAAAAAAA
+#define DDRSS_PHY_40_DATA 0x55555555
+#define DDRSS_PHY_41_DATA 0xAAAAAAAA
+#define DDRSS_PHY_42_DATA 0x00005555
+#define DDRSS_PHY_43_DATA 0x01000100
+#define DDRSS_PHY_44_DATA 0x00800180
+#define DDRSS_PHY_45_DATA 0x00000001
+#define DDRSS_PHY_46_DATA 0x00000000
+#define DDRSS_PHY_47_DATA 0x00000000
+#define DDRSS_PHY_48_DATA 0x00000000
+#define DDRSS_PHY_49_DATA 0x00000000
+#define DDRSS_PHY_50_DATA 0x00000000
+#define DDRSS_PHY_51_DATA 0x00000000
+#define DDRSS_PHY_52_DATA 0x00000000
+#define DDRSS_PHY_53_DATA 0x00000000
+#define DDRSS_PHY_54_DATA 0x00000000
+#define DDRSS_PHY_55_DATA 0x00000000
+#define DDRSS_PHY_56_DATA 0x00000000
+#define DDRSS_PHY_57_DATA 0x00000000
+#define DDRSS_PHY_58_DATA 0x00000000
+#define DDRSS_PHY_59_DATA 0x00000000
+#define DDRSS_PHY_60_DATA 0x00000000
+#define DDRSS_PHY_61_DATA 0x00000000
+#define DDRSS_PHY_62_DATA 0x00000000
+#define DDRSS_PHY_63_DATA 0x00000000
+#define DDRSS_PHY_64_DATA 0x00000000
+#define DDRSS_PHY_65_DATA 0x00000000
+#define DDRSS_PHY_66_DATA 0x00000000
+#define DDRSS_PHY_67_DATA 0x00000004
+#define DDRSS_PHY_68_DATA 0x00000000
+#define DDRSS_PHY_69_DATA 0x00000000
+#define DDRSS_PHY_70_DATA 0x00000000
+#define DDRSS_PHY_71_DATA 0x00000000
+#define DDRSS_PHY_72_DATA 0x00000000
+#define DDRSS_PHY_73_DATA 0x00000000
+#define DDRSS_PHY_74_DATA 0x081F07FF
+#define DDRSS_PHY_75_DATA 0x10200080
+#define DDRSS_PHY_76_DATA 0x00000008
+#define DDRSS_PHY_77_DATA 0x00000401
+#define DDRSS_PHY_78_DATA 0x00000000
+#define DDRSS_PHY_79_DATA 0x01CC0C01
+#define DDRSS_PHY_80_DATA 0x1003CC0C
+#define DDRSS_PHY_81_DATA 0x20000140
+#define DDRSS_PHY_82_DATA 0x07FF0200
+#define DDRSS_PHY_83_DATA 0x0000DD01
+#define DDRSS_PHY_84_DATA 0x00100303
+#define DDRSS_PHY_85_DATA 0x00000000
+#define DDRSS_PHY_86_DATA 0x00000000
+#define DDRSS_PHY_87_DATA 0x00041000
+#define DDRSS_PHY_88_DATA 0x00100010
+#define DDRSS_PHY_89_DATA 0x00100010
+#define DDRSS_PHY_90_DATA 0x00100010
+#define DDRSS_PHY_91_DATA 0x00100010
+#define DDRSS_PHY_92_DATA 0x02000010
+#define DDRSS_PHY_93_DATA 0x00000005
+#define DDRSS_PHY_94_DATA 0x51516042
+#define DDRSS_PHY_95_DATA 0x31C06000
+#define DDRSS_PHY_96_DATA 0x07AB0340
+#define DDRSS_PHY_97_DATA 0x00C0C001
+#define DDRSS_PHY_98_DATA 0x0D000000
+#define DDRSS_PHY_99_DATA 0x000D0C0C
+#define DDRSS_PHY_100_DATA 0x42100010
+#define DDRSS_PHY_101_DATA 0x010C073E
+#define DDRSS_PHY_102_DATA 0x000F0C32
+#define DDRSS_PHY_103_DATA 0x01000140
+#define DDRSS_PHY_104_DATA 0x011E0120
+#define DDRSS_PHY_105_DATA 0x00000C00
+#define DDRSS_PHY_106_DATA 0x000002DD
+#define DDRSS_PHY_107_DATA 0x00030200
+#define DDRSS_PHY_108_DATA 0x02800000
+#define DDRSS_PHY_109_DATA 0x80800000
+#define DDRSS_PHY_110_DATA 0x000D2010
+#define DDRSS_PHY_111_DATA 0x76543210
+#define DDRSS_PHY_112_DATA 0x00000008
+#define DDRSS_PHY_113_DATA 0x045D045D
+#define DDRSS_PHY_114_DATA 0x045D045D
+#define DDRSS_PHY_115_DATA 0x045D045D
+#define DDRSS_PHY_116_DATA 0x045D045D
+#define DDRSS_PHY_117_DATA 0x0000045D
+#define DDRSS_PHY_118_DATA 0x0000A000
+#define DDRSS_PHY_119_DATA 0x00A000A0
+#define DDRSS_PHY_120_DATA 0x00A000A0
+#define DDRSS_PHY_121_DATA 0x00A000A0
+#define DDRSS_PHY_122_DATA 0x00A000A0
+#define DDRSS_PHY_123_DATA 0x00A000A0
+#define DDRSS_PHY_124_DATA 0x00A000A0
+#define DDRSS_PHY_125_DATA 0x00A000A0
+#define DDRSS_PHY_126_DATA 0x00A000A0
+#define DDRSS_PHY_127_DATA 0x00B200A0
+#define DDRSS_PHY_128_DATA 0x01000000
+#define DDRSS_PHY_129_DATA 0x00000000
+#define DDRSS_PHY_130_DATA 0x00000000
+#define DDRSS_PHY_131_DATA 0x00080200
+#define DDRSS_PHY_132_DATA 0x00000000
+#define DDRSS_PHY_133_DATA 0x20202020
+#define DDRSS_PHY_134_DATA 0x20202020
+#define DDRSS_PHY_135_DATA 0xF0F02020
+#define DDRSS_PHY_136_DATA 0x00000000
+#define DDRSS_PHY_137_DATA 0x00000000
+#define DDRSS_PHY_138_DATA 0x00000000
+#define DDRSS_PHY_139_DATA 0x00000000
+#define DDRSS_PHY_140_DATA 0x00000000
+#define DDRSS_PHY_141_DATA 0x00000000
+#define DDRSS_PHY_142_DATA 0x00000000
+#define DDRSS_PHY_143_DATA 0x00000000
+#define DDRSS_PHY_144_DATA 0x00000000
+#define DDRSS_PHY_145_DATA 0x00000000
+#define DDRSS_PHY_146_DATA 0x00000000
+#define DDRSS_PHY_147_DATA 0x00000000
+#define DDRSS_PHY_148_DATA 0x00000000
+#define DDRSS_PHY_149_DATA 0x00000000
+#define DDRSS_PHY_150_DATA 0x00000000
+#define DDRSS_PHY_151_DATA 0x00000000
+#define DDRSS_PHY_152_DATA 0x00000000
+#define DDRSS_PHY_153_DATA 0x00000000
+#define DDRSS_PHY_154_DATA 0x00000000
+#define DDRSS_PHY_155_DATA 0x00000000
+#define DDRSS_PHY_156_DATA 0x00000000
+#define DDRSS_PHY_157_DATA 0x00000000
+#define DDRSS_PHY_158_DATA 0x00000000
+#define DDRSS_PHY_159_DATA 0x00000000
+#define DDRSS_PHY_160_DATA 0x00000000
+#define DDRSS_PHY_161_DATA 0x00000000
+#define DDRSS_PHY_162_DATA 0x00000000
+#define DDRSS_PHY_163_DATA 0x00000000
+#define DDRSS_PHY_164_DATA 0x00000000
+#define DDRSS_PHY_165_DATA 0x00000000
+#define DDRSS_PHY_166_DATA 0x00000000
+#define DDRSS_PHY_167_DATA 0x00000000
+#define DDRSS_PHY_168_DATA 0x00000000
+#define DDRSS_PHY_169_DATA 0x00000000
+#define DDRSS_PHY_170_DATA 0x00000000
+#define DDRSS_PHY_171_DATA 0x00000000
+#define DDRSS_PHY_172_DATA 0x00000000
+#define DDRSS_PHY_173_DATA 0x00000000
+#define DDRSS_PHY_174_DATA 0x00000000
+#define DDRSS_PHY_175_DATA 0x00000000
+#define DDRSS_PHY_176_DATA 0x00000000
+#define DDRSS_PHY_177_DATA 0x00000000
+#define DDRSS_PHY_178_DATA 0x00000000
+#define DDRSS_PHY_179_DATA 0x00000000
+#define DDRSS_PHY_180_DATA 0x00000000
+#define DDRSS_PHY_181_DATA 0x00000000
+#define DDRSS_PHY_182_DATA 0x00000000
+#define DDRSS_PHY_183_DATA 0x00000000
+#define DDRSS_PHY_184_DATA 0x00000000
+#define DDRSS_PHY_185_DATA 0x00000000
+#define DDRSS_PHY_186_DATA 0x00000000
+#define DDRSS_PHY_187_DATA 0x00000000
+#define DDRSS_PHY_188_DATA 0x00000000
+#define DDRSS_PHY_189_DATA 0x00000000
+#define DDRSS_PHY_190_DATA 0x00000000
+#define DDRSS_PHY_191_DATA 0x00000000
+#define DDRSS_PHY_192_DATA 0x00000000
+#define DDRSS_PHY_193_DATA 0x00000000
+#define DDRSS_PHY_194_DATA 0x00000000
+#define DDRSS_PHY_195_DATA 0x00000000
+#define DDRSS_PHY_196_DATA 0x00000000
+#define DDRSS_PHY_197_DATA 0x00000000
+#define DDRSS_PHY_198_DATA 0x00000000
+#define DDRSS_PHY_199_DATA 0x00000000
+#define DDRSS_PHY_200_DATA 0x00000000
+#define DDRSS_PHY_201_DATA 0x00000000
+#define DDRSS_PHY_202_DATA 0x00000000
+#define DDRSS_PHY_203_DATA 0x00000000
+#define DDRSS_PHY_204_DATA 0x00000000
+#define DDRSS_PHY_205_DATA 0x00000000
+#define DDRSS_PHY_206_DATA 0x00000000
+#define DDRSS_PHY_207_DATA 0x00000000
+#define DDRSS_PHY_208_DATA 0x00000000
+#define DDRSS_PHY_209_DATA 0x00000000
+#define DDRSS_PHY_210_DATA 0x00000000
+#define DDRSS_PHY_211_DATA 0x00000000
+#define DDRSS_PHY_212_DATA 0x00000000
+#define DDRSS_PHY_213_DATA 0x00000000
+#define DDRSS_PHY_214_DATA 0x00000000
+#define DDRSS_PHY_215_DATA 0x00000000
+#define DDRSS_PHY_216_DATA 0x00000000
+#define DDRSS_PHY_217_DATA 0x00000000
+#define DDRSS_PHY_218_DATA 0x00000000
+#define DDRSS_PHY_219_DATA 0x00000000
+#define DDRSS_PHY_220_DATA 0x00000000
+#define DDRSS_PHY_221_DATA 0x00000000
+#define DDRSS_PHY_222_DATA 0x00000000
+#define DDRSS_PHY_223_DATA 0x00000000
+#define DDRSS_PHY_224_DATA 0x00000000
+#define DDRSS_PHY_225_DATA 0x00000000
+#define DDRSS_PHY_226_DATA 0x00000000
+#define DDRSS_PHY_227_DATA 0x00000000
+#define DDRSS_PHY_228_DATA 0x00000000
+#define DDRSS_PHY_229_DATA 0x00000000
+#define DDRSS_PHY_230_DATA 0x00000000
+#define DDRSS_PHY_231_DATA 0x00000000
+#define DDRSS_PHY_232_DATA 0x00000000
+#define DDRSS_PHY_233_DATA 0x00000000
+#define DDRSS_PHY_234_DATA 0x00000000
+#define DDRSS_PHY_235_DATA 0x00000000
+#define DDRSS_PHY_236_DATA 0x00000000
+#define DDRSS_PHY_237_DATA 0x00000000
+#define DDRSS_PHY_238_DATA 0x00000000
+#define DDRSS_PHY_239_DATA 0x00000000
+#define DDRSS_PHY_240_DATA 0x00000000
+#define DDRSS_PHY_241_DATA 0x00000000
+#define DDRSS_PHY_242_DATA 0x00000000
+#define DDRSS_PHY_243_DATA 0x00000000
+#define DDRSS_PHY_244_DATA 0x00000000
+#define DDRSS_PHY_245_DATA 0x00000000
+#define DDRSS_PHY_246_DATA 0x00000000
+#define DDRSS_PHY_247_DATA 0x00000000
+#define DDRSS_PHY_248_DATA 0x00000000
+#define DDRSS_PHY_249_DATA 0x00000000
+#define DDRSS_PHY_250_DATA 0x00000000
+#define DDRSS_PHY_251_DATA 0x00000000
+#define DDRSS_PHY_252_DATA 0x00000000
+#define DDRSS_PHY_253_DATA 0x00000000
+#define DDRSS_PHY_254_DATA 0x00000000
+#define DDRSS_PHY_255_DATA 0x00000000
+#define DDRSS_PHY_256_DATA 0x04F00000
+#define DDRSS_PHY_257_DATA 0x00000000
+#define DDRSS_PHY_258_DATA 0x00030200
+#define DDRSS_PHY_259_DATA 0x00000000
+#define DDRSS_PHY_260_DATA 0x00000000
+#define DDRSS_PHY_261_DATA 0x01030000
+#define DDRSS_PHY_262_DATA 0x00010000
+#define DDRSS_PHY_263_DATA 0x01030004
+#define DDRSS_PHY_264_DATA 0x01000000
+#define DDRSS_PHY_265_DATA 0x00000000
+#define DDRSS_PHY_266_DATA 0x00000000
+#define DDRSS_PHY_267_DATA 0x00000000
+#define DDRSS_PHY_268_DATA 0x01010000
+#define DDRSS_PHY_269_DATA 0x00010000
+#define DDRSS_PHY_270_DATA 0x00C00001
+#define DDRSS_PHY_271_DATA 0x00CC0008
+#define DDRSS_PHY_272_DATA 0x00660601
+#define DDRSS_PHY_273_DATA 0x00000003
+#define DDRSS_PHY_274_DATA 0x00000000
+#define DDRSS_PHY_275_DATA 0x00000301
+#define DDRSS_PHY_276_DATA 0x0000AAAA
+#define DDRSS_PHY_277_DATA 0x00005555
+#define DDRSS_PHY_278_DATA 0x0000B5B5
+#define DDRSS_PHY_279_DATA 0x00004A4A
+#define DDRSS_PHY_280_DATA 0x00005656
+#define DDRSS_PHY_281_DATA 0x0000A9A9
+#define DDRSS_PHY_282_DATA 0x0000B7B7
+#define DDRSS_PHY_283_DATA 0x00004848
+#define DDRSS_PHY_284_DATA 0x00000000
+#define DDRSS_PHY_285_DATA 0x00000000
+#define DDRSS_PHY_286_DATA 0x08000000
+#define DDRSS_PHY_287_DATA 0x0F000008
+#define DDRSS_PHY_288_DATA 0x00000F0F
+#define DDRSS_PHY_289_DATA 0x00E4E400
+#define DDRSS_PHY_290_DATA 0x00071040
+#define DDRSS_PHY_291_DATA 0x000C0020
+#define DDRSS_PHY_292_DATA 0x00062000
+#define DDRSS_PHY_293_DATA 0x00000000
+#define DDRSS_PHY_294_DATA 0x55555555
+#define DDRSS_PHY_295_DATA 0xAAAAAAAA
+#define DDRSS_PHY_296_DATA 0x55555555
+#define DDRSS_PHY_297_DATA 0xAAAAAAAA
+#define DDRSS_PHY_298_DATA 0x00005555
+#define DDRSS_PHY_299_DATA 0x01000100
+#define DDRSS_PHY_300_DATA 0x00800180
+#define DDRSS_PHY_301_DATA 0x00000000
+#define DDRSS_PHY_302_DATA 0x00000000
+#define DDRSS_PHY_303_DATA 0x00000000
+#define DDRSS_PHY_304_DATA 0x00000000
+#define DDRSS_PHY_305_DATA 0x00000000
+#define DDRSS_PHY_306_DATA 0x00000000
+#define DDRSS_PHY_307_DATA 0x00000000
+#define DDRSS_PHY_308_DATA 0x00000000
+#define DDRSS_PHY_309_DATA 0x00000000
+#define DDRSS_PHY_310_DATA 0x00000000
+#define DDRSS_PHY_311_DATA 0x00000000
+#define DDRSS_PHY_312_DATA 0x00000000
+#define DDRSS_PHY_313_DATA 0x00000000
+#define DDRSS_PHY_314_DATA 0x00000000
+#define DDRSS_PHY_315_DATA 0x00000000
+#define DDRSS_PHY_316_DATA 0x00000000
+#define DDRSS_PHY_317_DATA 0x00000000
+#define DDRSS_PHY_318_DATA 0x00000000
+#define DDRSS_PHY_319_DATA 0x00000000
+#define DDRSS_PHY_320_DATA 0x00000000
+#define DDRSS_PHY_321_DATA 0x00000000
+#define DDRSS_PHY_322_DATA 0x00000000
+#define DDRSS_PHY_323_DATA 0x00000004
+#define DDRSS_PHY_324_DATA 0x00000000
+#define DDRSS_PHY_325_DATA 0x00000000
+#define DDRSS_PHY_326_DATA 0x00000000
+#define DDRSS_PHY_327_DATA 0x00000000
+#define DDRSS_PHY_328_DATA 0x00000000
+#define DDRSS_PHY_329_DATA 0x00000000
+#define DDRSS_PHY_330_DATA 0x081F07FF
+#define DDRSS_PHY_331_DATA 0x10200080
+#define DDRSS_PHY_332_DATA 0x00000008
+#define DDRSS_PHY_333_DATA 0x00000401
+#define DDRSS_PHY_334_DATA 0x00000000
+#define DDRSS_PHY_335_DATA 0x01CC0C01
+#define DDRSS_PHY_336_DATA 0x1003CC0C
+#define DDRSS_PHY_337_DATA 0x20000140
+#define DDRSS_PHY_338_DATA 0x07FF0200
+#define DDRSS_PHY_339_DATA 0x0000DD01
+#define DDRSS_PHY_340_DATA 0x00100303
+#define DDRSS_PHY_341_DATA 0x00000000
+#define DDRSS_PHY_342_DATA 0x00000000
+#define DDRSS_PHY_343_DATA 0x00041000
+#define DDRSS_PHY_344_DATA 0x00100010
+#define DDRSS_PHY_345_DATA 0x00100010
+#define DDRSS_PHY_346_DATA 0x00100010
+#define DDRSS_PHY_347_DATA 0x00100010
+#define DDRSS_PHY_348_DATA 0x02000010
+#define DDRSS_PHY_349_DATA 0x00000005
+#define DDRSS_PHY_350_DATA 0x51516042
+#define DDRSS_PHY_351_DATA 0x31C06000
+#define DDRSS_PHY_352_DATA 0x07AB0340
+#define DDRSS_PHY_353_DATA 0x00C0C001
+#define DDRSS_PHY_354_DATA 0x0D000000
+#define DDRSS_PHY_355_DATA 0x000D0C0C
+#define DDRSS_PHY_356_DATA 0x42100010
+#define DDRSS_PHY_357_DATA 0x010C073E
+#define DDRSS_PHY_358_DATA 0x000F0C32
+#define DDRSS_PHY_359_DATA 0x01000140
+#define DDRSS_PHY_360_DATA 0x011E0120
+#define DDRSS_PHY_361_DATA 0x00000C00
+#define DDRSS_PHY_362_DATA 0x000002DD
+#define DDRSS_PHY_363_DATA 0x00030200
+#define DDRSS_PHY_364_DATA 0x02800000
+#define DDRSS_PHY_365_DATA 0x80800000
+#define DDRSS_PHY_366_DATA 0x000D2010
+#define DDRSS_PHY_367_DATA 0x76543210
+#define DDRSS_PHY_368_DATA 0x00000008
+#define DDRSS_PHY_369_DATA 0x045D045D
+#define DDRSS_PHY_370_DATA 0x045D045D
+#define DDRSS_PHY_371_DATA 0x045D045D
+#define DDRSS_PHY_372_DATA 0x045D045D
+#define DDRSS_PHY_373_DATA 0x0000045D
+#define DDRSS_PHY_374_DATA 0x0000A000
+#define DDRSS_PHY_375_DATA 0x00A000A0
+#define DDRSS_PHY_376_DATA 0x00A000A0
+#define DDRSS_PHY_377_DATA 0x00A000A0
+#define DDRSS_PHY_378_DATA 0x00A000A0
+#define DDRSS_PHY_379_DATA 0x00A000A0
+#define DDRSS_PHY_380_DATA 0x00A000A0
+#define DDRSS_PHY_381_DATA 0x00A000A0
+#define DDRSS_PHY_382_DATA 0x00A000A0
+#define DDRSS_PHY_383_DATA 0x00B200A0
+#define DDRSS_PHY_384_DATA 0x01000000
+#define DDRSS_PHY_385_DATA 0x00000000
+#define DDRSS_PHY_386_DATA 0x00000000
+#define DDRSS_PHY_387_DATA 0x00080200
+#define DDRSS_PHY_388_DATA 0x00000000
+#define DDRSS_PHY_389_DATA 0x20202020
+#define DDRSS_PHY_390_DATA 0x20202020
+#define DDRSS_PHY_391_DATA 0xF0F02020
+#define DDRSS_PHY_392_DATA 0x00000000
+#define DDRSS_PHY_393_DATA 0x00000000
+#define DDRSS_PHY_394_DATA 0x00000000
+#define DDRSS_PHY_395_DATA 0x00000000
+#define DDRSS_PHY_396_DATA 0x00000000
+#define DDRSS_PHY_397_DATA 0x00000000
+#define DDRSS_PHY_398_DATA 0x00000000
+#define DDRSS_PHY_399_DATA 0x00000000
+#define DDRSS_PHY_400_DATA 0x00000000
+#define DDRSS_PHY_401_DATA 0x00000000
+#define DDRSS_PHY_402_DATA 0x00000000
+#define DDRSS_PHY_403_DATA 0x00000000
+#define DDRSS_PHY_404_DATA 0x00000000
+#define DDRSS_PHY_405_DATA 0x00000000
+#define DDRSS_PHY_406_DATA 0x00000000
+#define DDRSS_PHY_407_DATA 0x00000000
+#define DDRSS_PHY_408_DATA 0x00000000
+#define DDRSS_PHY_409_DATA 0x00000000
+#define DDRSS_PHY_410_DATA 0x00000000
+#define DDRSS_PHY_411_DATA 0x00000000
+#define DDRSS_PHY_412_DATA 0x00000000
+#define DDRSS_PHY_413_DATA 0x00000000
+#define DDRSS_PHY_414_DATA 0x00000000
+#define DDRSS_PHY_415_DATA 0x00000000
+#define DDRSS_PHY_416_DATA 0x00000000
+#define DDRSS_PHY_417_DATA 0x00000000
+#define DDRSS_PHY_418_DATA 0x00000000
+#define DDRSS_PHY_419_DATA 0x00000000
+#define DDRSS_PHY_420_DATA 0x00000000
+#define DDRSS_PHY_421_DATA 0x00000000
+#define DDRSS_PHY_422_DATA 0x00000000
+#define DDRSS_PHY_423_DATA 0x00000000
+#define DDRSS_PHY_424_DATA 0x00000000
+#define DDRSS_PHY_425_DATA 0x00000000
+#define DDRSS_PHY_426_DATA 0x00000000
+#define DDRSS_PHY_427_DATA 0x00000000
+#define DDRSS_PHY_428_DATA 0x00000000
+#define DDRSS_PHY_429_DATA 0x00000000
+#define DDRSS_PHY_430_DATA 0x00000000
+#define DDRSS_PHY_431_DATA 0x00000000
+#define DDRSS_PHY_432_DATA 0x00000000
+#define DDRSS_PHY_433_DATA 0x00000000
+#define DDRSS_PHY_434_DATA 0x00000000
+#define DDRSS_PHY_435_DATA 0x00000000
+#define DDRSS_PHY_436_DATA 0x00000000
+#define DDRSS_PHY_437_DATA 0x00000000
+#define DDRSS_PHY_438_DATA 0x00000000
+#define DDRSS_PHY_439_DATA 0x00000000
+#define DDRSS_PHY_440_DATA 0x00000000
+#define DDRSS_PHY_441_DATA 0x00000000
+#define DDRSS_PHY_442_DATA 0x00000000
+#define DDRSS_PHY_443_DATA 0x00000000
+#define DDRSS_PHY_444_DATA 0x00000000
+#define DDRSS_PHY_445_DATA 0x00000000
+#define DDRSS_PHY_446_DATA 0x00000000
+#define DDRSS_PHY_447_DATA 0x00000000
+#define DDRSS_PHY_448_DATA 0x00000000
+#define DDRSS_PHY_449_DATA 0x00000000
+#define DDRSS_PHY_450_DATA 0x00000000
+#define DDRSS_PHY_451_DATA 0x00000000
+#define DDRSS_PHY_452_DATA 0x00000000
+#define DDRSS_PHY_453_DATA 0x00000000
+#define DDRSS_PHY_454_DATA 0x00000000
+#define DDRSS_PHY_455_DATA 0x00000000
+#define DDRSS_PHY_456_DATA 0x00000000
+#define DDRSS_PHY_457_DATA 0x00000000
+#define DDRSS_PHY_458_DATA 0x00000000
+#define DDRSS_PHY_459_DATA 0x00000000
+#define DDRSS_PHY_460_DATA 0x00000000
+#define DDRSS_PHY_461_DATA 0x00000000
+#define DDRSS_PHY_462_DATA 0x00000000
+#define DDRSS_PHY_463_DATA 0x00000000
+#define DDRSS_PHY_464_DATA 0x00000000
+#define DDRSS_PHY_465_DATA 0x00000000
+#define DDRSS_PHY_466_DATA 0x00000000
+#define DDRSS_PHY_467_DATA 0x00000000
+#define DDRSS_PHY_468_DATA 0x00000000
+#define DDRSS_PHY_469_DATA 0x00000000
+#define DDRSS_PHY_470_DATA 0x00000000
+#define DDRSS_PHY_471_DATA 0x00000000
+#define DDRSS_PHY_472_DATA 0x00000000
+#define DDRSS_PHY_473_DATA 0x00000000
+#define DDRSS_PHY_474_DATA 0x00000000
+#define DDRSS_PHY_475_DATA 0x00000000
+#define DDRSS_PHY_476_DATA 0x00000000
+#define DDRSS_PHY_477_DATA 0x00000000
+#define DDRSS_PHY_478_DATA 0x00000000
+#define DDRSS_PHY_479_DATA 0x00000000
+#define DDRSS_PHY_480_DATA 0x00000000
+#define DDRSS_PHY_481_DATA 0x00000000
+#define DDRSS_PHY_482_DATA 0x00000000
+#define DDRSS_PHY_483_DATA 0x00000000
+#define DDRSS_PHY_484_DATA 0x00000000
+#define DDRSS_PHY_485_DATA 0x00000000
+#define DDRSS_PHY_486_DATA 0x00000000
+#define DDRSS_PHY_487_DATA 0x00000000
+#define DDRSS_PHY_488_DATA 0x00000000
+#define DDRSS_PHY_489_DATA 0x00000000
+#define DDRSS_PHY_490_DATA 0x00000000
+#define DDRSS_PHY_491_DATA 0x00000000
+#define DDRSS_PHY_492_DATA 0x00000000
+#define DDRSS_PHY_493_DATA 0x00000000
+#define DDRSS_PHY_494_DATA 0x00000000
+#define DDRSS_PHY_495_DATA 0x00000000
+#define DDRSS_PHY_496_DATA 0x00000000
+#define DDRSS_PHY_497_DATA 0x00000000
+#define DDRSS_PHY_498_DATA 0x00000000
+#define DDRSS_PHY_499_DATA 0x00000000
+#define DDRSS_PHY_500_DATA 0x00000000
+#define DDRSS_PHY_501_DATA 0x00000000
+#define DDRSS_PHY_502_DATA 0x00000000
+#define DDRSS_PHY_503_DATA 0x00000000
+#define DDRSS_PHY_504_DATA 0x00000000
+#define DDRSS_PHY_505_DATA 0x00000000
+#define DDRSS_PHY_506_DATA 0x00000000
+#define DDRSS_PHY_507_DATA 0x00000000
+#define DDRSS_PHY_508_DATA 0x00000000
+#define DDRSS_PHY_509_DATA 0x00000000
+#define DDRSS_PHY_510_DATA 0x00000000
+#define DDRSS_PHY_511_DATA 0x00000000
+#define DDRSS_PHY_512_DATA 0x04F00000
+#define DDRSS_PHY_513_DATA 0x00000000
+#define DDRSS_PHY_514_DATA 0x00030200
+#define DDRSS_PHY_515_DATA 0x00000000
+#define DDRSS_PHY_516_DATA 0x00000000
+#define DDRSS_PHY_517_DATA 0x01030000
+#define DDRSS_PHY_518_DATA 0x00010000
+#define DDRSS_PHY_519_DATA 0x01030004
+#define DDRSS_PHY_520_DATA 0x01000000
+#define DDRSS_PHY_521_DATA 0x00000000
+#define DDRSS_PHY_522_DATA 0x00000000
+#define DDRSS_PHY_523_DATA 0x00000000
+#define DDRSS_PHY_524_DATA 0x01010000
+#define DDRSS_PHY_525_DATA 0x00010000
+#define DDRSS_PHY_526_DATA 0x00C00001
+#define DDRSS_PHY_527_DATA 0x00CC0008
+#define DDRSS_PHY_528_DATA 0x00660601
+#define DDRSS_PHY_529_DATA 0x00000003
+#define DDRSS_PHY_530_DATA 0x00000000
+#define DDRSS_PHY_531_DATA 0x00000301
+#define DDRSS_PHY_532_DATA 0x0000AAAA
+#define DDRSS_PHY_533_DATA 0x00005555
+#define DDRSS_PHY_534_DATA 0x0000B5B5
+#define DDRSS_PHY_535_DATA 0x00004A4A
+#define DDRSS_PHY_536_DATA 0x00005656
+#define DDRSS_PHY_537_DATA 0x0000A9A9
+#define DDRSS_PHY_538_DATA 0x0000B7B7
+#define DDRSS_PHY_539_DATA 0x00004848
+#define DDRSS_PHY_540_DATA 0x00000000
+#define DDRSS_PHY_541_DATA 0x00000000
+#define DDRSS_PHY_542_DATA 0x08000000
+#define DDRSS_PHY_543_DATA 0x0F000008
+#define DDRSS_PHY_544_DATA 0x00000F0F
+#define DDRSS_PHY_545_DATA 0x00E4E400
+#define DDRSS_PHY_546_DATA 0x00071040
+#define DDRSS_PHY_547_DATA 0x000C0020
+#define DDRSS_PHY_548_DATA 0x00062000
+#define DDRSS_PHY_549_DATA 0x00000000
+#define DDRSS_PHY_550_DATA 0x55555555
+#define DDRSS_PHY_551_DATA 0xAAAAAAAA
+#define DDRSS_PHY_552_DATA 0x55555555
+#define DDRSS_PHY_553_DATA 0xAAAAAAAA
+#define DDRSS_PHY_554_DATA 0x00005555
+#define DDRSS_PHY_555_DATA 0x01000100
+#define DDRSS_PHY_556_DATA 0x00800180
+#define DDRSS_PHY_557_DATA 0x00000001
+#define DDRSS_PHY_558_DATA 0x00000000
+#define DDRSS_PHY_559_DATA 0x00000000
+#define DDRSS_PHY_560_DATA 0x00000000
+#define DDRSS_PHY_561_DATA 0x00000000
+#define DDRSS_PHY_562_DATA 0x00000000
+#define DDRSS_PHY_563_DATA 0x00000000
+#define DDRSS_PHY_564_DATA 0x00000000
+#define DDRSS_PHY_565_DATA 0x00000000
+#define DDRSS_PHY_566_DATA 0x00000000
+#define DDRSS_PHY_567_DATA 0x00000000
+#define DDRSS_PHY_568_DATA 0x00000000
+#define DDRSS_PHY_569_DATA 0x00000000
+#define DDRSS_PHY_570_DATA 0x00000000
+#define DDRSS_PHY_571_DATA 0x00000000
+#define DDRSS_PHY_572_DATA 0x00000000
+#define DDRSS_PHY_573_DATA 0x00000000
+#define DDRSS_PHY_574_DATA 0x00000000
+#define DDRSS_PHY_575_DATA 0x00000000
+#define DDRSS_PHY_576_DATA 0x00000000
+#define DDRSS_PHY_577_DATA 0x00000000
+#define DDRSS_PHY_578_DATA 0x00000000
+#define DDRSS_PHY_579_DATA 0x00000004
+#define DDRSS_PHY_580_DATA 0x00000000
+#define DDRSS_PHY_581_DATA 0x00000000
+#define DDRSS_PHY_582_DATA 0x00000000
+#define DDRSS_PHY_583_DATA 0x00000000
+#define DDRSS_PHY_584_DATA 0x00000000
+#define DDRSS_PHY_585_DATA 0x00000000
+#define DDRSS_PHY_586_DATA 0x081F07FF
+#define DDRSS_PHY_587_DATA 0x10200080
+#define DDRSS_PHY_588_DATA 0x00000008
+#define DDRSS_PHY_589_DATA 0x00000401
+#define DDRSS_PHY_590_DATA 0x00000000
+#define DDRSS_PHY_591_DATA 0x01CC0C01
+#define DDRSS_PHY_592_DATA 0x1003CC0C
+#define DDRSS_PHY_593_DATA 0x20000140
+#define DDRSS_PHY_594_DATA 0x07FF0200
+#define DDRSS_PHY_595_DATA 0x0000DD01
+#define DDRSS_PHY_596_DATA 0x00100303
+#define DDRSS_PHY_597_DATA 0x00000000
+#define DDRSS_PHY_598_DATA 0x00000000
+#define DDRSS_PHY_599_DATA 0x00041000
+#define DDRSS_PHY_600_DATA 0x00100010
+#define DDRSS_PHY_601_DATA 0x00100010
+#define DDRSS_PHY_602_DATA 0x00100010
+#define DDRSS_PHY_603_DATA 0x00100010
+#define DDRSS_PHY_604_DATA 0x02000010
+#define DDRSS_PHY_605_DATA 0x00000005
+#define DDRSS_PHY_606_DATA 0x51516042
+#define DDRSS_PHY_607_DATA 0x31C06000
+#define DDRSS_PHY_608_DATA 0x07AB0340
+#define DDRSS_PHY_609_DATA 0x00C0C001
+#define DDRSS_PHY_610_DATA 0x0D000000
+#define DDRSS_PHY_611_DATA 0x000D0C0C
+#define DDRSS_PHY_612_DATA 0x42100010
+#define DDRSS_PHY_613_DATA 0x010C073E
+#define DDRSS_PHY_614_DATA 0x000F0C32
+#define DDRSS_PHY_615_DATA 0x01000140
+#define DDRSS_PHY_616_DATA 0x011E0120
+#define DDRSS_PHY_617_DATA 0x00000C00
+#define DDRSS_PHY_618_DATA 0x000002DD
+#define DDRSS_PHY_619_DATA 0x00030200
+#define DDRSS_PHY_620_DATA 0x02800000
+#define DDRSS_PHY_621_DATA 0x80800000
+#define DDRSS_PHY_622_DATA 0x000D2010
+#define DDRSS_PHY_623_DATA 0x76543210
+#define DDRSS_PHY_624_DATA 0x00000008
+#define DDRSS_PHY_625_DATA 0x045D045D
+#define DDRSS_PHY_626_DATA 0x045D045D
+#define DDRSS_PHY_627_DATA 0x045D045D
+#define DDRSS_PHY_628_DATA 0x045D045D
+#define DDRSS_PHY_629_DATA 0x0000045D
+#define DDRSS_PHY_630_DATA 0x0000A000
+#define DDRSS_PHY_631_DATA 0x00A000A0
+#define DDRSS_PHY_632_DATA 0x00A000A0
+#define DDRSS_PHY_633_DATA 0x00A000A0
+#define DDRSS_PHY_634_DATA 0x00A000A0
+#define DDRSS_PHY_635_DATA 0x00A000A0
+#define DDRSS_PHY_636_DATA 0x00A000A0
+#define DDRSS_PHY_637_DATA 0x00A000A0
+#define DDRSS_PHY_638_DATA 0x00A000A0
+#define DDRSS_PHY_639_DATA 0x00B200A0
+#define DDRSS_PHY_640_DATA 0x01000000
+#define DDRSS_PHY_641_DATA 0x00000000
+#define DDRSS_PHY_642_DATA 0x00000000
+#define DDRSS_PHY_643_DATA 0x00080200
+#define DDRSS_PHY_644_DATA 0x00000000
+#define DDRSS_PHY_645_DATA 0x20202020
+#define DDRSS_PHY_646_DATA 0x20202020
+#define DDRSS_PHY_647_DATA 0xF0F02020
+#define DDRSS_PHY_648_DATA 0x00000000
+#define DDRSS_PHY_649_DATA 0x00000000
+#define DDRSS_PHY_650_DATA 0x00000000
+#define DDRSS_PHY_651_DATA 0x00000000
+#define DDRSS_PHY_652_DATA 0x00000000
+#define DDRSS_PHY_653_DATA 0x00000000
+#define DDRSS_PHY_654_DATA 0x00000000
+#define DDRSS_PHY_655_DATA 0x00000000
+#define DDRSS_PHY_656_DATA 0x00000000
+#define DDRSS_PHY_657_DATA 0x00000000
+#define DDRSS_PHY_658_DATA 0x00000000
+#define DDRSS_PHY_659_DATA 0x00000000
+#define DDRSS_PHY_660_DATA 0x00000000
+#define DDRSS_PHY_661_DATA 0x00000000
+#define DDRSS_PHY_662_DATA 0x00000000
+#define DDRSS_PHY_663_DATA 0x00000000
+#define DDRSS_PHY_664_DATA 0x00000000
+#define DDRSS_PHY_665_DATA 0x00000000
+#define DDRSS_PHY_666_DATA 0x00000000
+#define DDRSS_PHY_667_DATA 0x00000000
+#define DDRSS_PHY_668_DATA 0x00000000
+#define DDRSS_PHY_669_DATA 0x00000000
+#define DDRSS_PHY_670_DATA 0x00000000
+#define DDRSS_PHY_671_DATA 0x00000000
+#define DDRSS_PHY_672_DATA 0x00000000
+#define DDRSS_PHY_673_DATA 0x00000000
+#define DDRSS_PHY_674_DATA 0x00000000
+#define DDRSS_PHY_675_DATA 0x00000000
+#define DDRSS_PHY_676_DATA 0x00000000
+#define DDRSS_PHY_677_DATA 0x00000000
+#define DDRSS_PHY_678_DATA 0x00000000
+#define DDRSS_PHY_679_DATA 0x00000000
+#define DDRSS_PHY_680_DATA 0x00000000
+#define DDRSS_PHY_681_DATA 0x00000000
+#define DDRSS_PHY_682_DATA 0x00000000
+#define DDRSS_PHY_683_DATA 0x00000000
+#define DDRSS_PHY_684_DATA 0x00000000
+#define DDRSS_PHY_685_DATA 0x00000000
+#define DDRSS_PHY_686_DATA 0x00000000
+#define DDRSS_PHY_687_DATA 0x00000000
+#define DDRSS_PHY_688_DATA 0x00000000
+#define DDRSS_PHY_689_DATA 0x00000000
+#define DDRSS_PHY_690_DATA 0x00000000
+#define DDRSS_PHY_691_DATA 0x00000000
+#define DDRSS_PHY_692_DATA 0x00000000
+#define DDRSS_PHY_693_DATA 0x00000000
+#define DDRSS_PHY_694_DATA 0x00000000
+#define DDRSS_PHY_695_DATA 0x00000000
+#define DDRSS_PHY_696_DATA 0x00000000
+#define DDRSS_PHY_697_DATA 0x00000000
+#define DDRSS_PHY_698_DATA 0x00000000
+#define DDRSS_PHY_699_DATA 0x00000000
+#define DDRSS_PHY_700_DATA 0x00000000
+#define DDRSS_PHY_701_DATA 0x00000000
+#define DDRSS_PHY_702_DATA 0x00000000
+#define DDRSS_PHY_703_DATA 0x00000000
+#define DDRSS_PHY_704_DATA 0x00000000
+#define DDRSS_PHY_705_DATA 0x00000000
+#define DDRSS_PHY_706_DATA 0x00000000
+#define DDRSS_PHY_707_DATA 0x00000000
+#define DDRSS_PHY_708_DATA 0x00000000
+#define DDRSS_PHY_709_DATA 0x00000000
+#define DDRSS_PHY_710_DATA 0x00000000
+#define DDRSS_PHY_711_DATA 0x00000000
+#define DDRSS_PHY_712_DATA 0x00000000
+#define DDRSS_PHY_713_DATA 0x00000000
+#define DDRSS_PHY_714_DATA 0x00000000
+#define DDRSS_PHY_715_DATA 0x00000000
+#define DDRSS_PHY_716_DATA 0x00000000
+#define DDRSS_PHY_717_DATA 0x00000000
+#define DDRSS_PHY_718_DATA 0x00000000
+#define DDRSS_PHY_719_DATA 0x00000000
+#define DDRSS_PHY_720_DATA 0x00000000
+#define DDRSS_PHY_721_DATA 0x00000000
+#define DDRSS_PHY_722_DATA 0x00000000
+#define DDRSS_PHY_723_DATA 0x00000000
+#define DDRSS_PHY_724_DATA 0x00000000
+#define DDRSS_PHY_725_DATA 0x00000000
+#define DDRSS_PHY_726_DATA 0x00000000
+#define DDRSS_PHY_727_DATA 0x00000000
+#define DDRSS_PHY_728_DATA 0x00000000
+#define DDRSS_PHY_729_DATA 0x00000000
+#define DDRSS_PHY_730_DATA 0x00000000
+#define DDRSS_PHY_731_DATA 0x00000000
+#define DDRSS_PHY_732_DATA 0x00000000
+#define DDRSS_PHY_733_DATA 0x00000000
+#define DDRSS_PHY_734_DATA 0x00000000
+#define DDRSS_PHY_735_DATA 0x00000000
+#define DDRSS_PHY_736_DATA 0x00000000
+#define DDRSS_PHY_737_DATA 0x00000000
+#define DDRSS_PHY_738_DATA 0x00000000
+#define DDRSS_PHY_739_DATA 0x00000000
+#define DDRSS_PHY_740_DATA 0x00000000
+#define DDRSS_PHY_741_DATA 0x00000000
+#define DDRSS_PHY_742_DATA 0x00000000
+#define DDRSS_PHY_743_DATA 0x00000000
+#define DDRSS_PHY_744_DATA 0x00000000
+#define DDRSS_PHY_745_DATA 0x00000000
+#define DDRSS_PHY_746_DATA 0x00000000
+#define DDRSS_PHY_747_DATA 0x00000000
+#define DDRSS_PHY_748_DATA 0x00000000
+#define DDRSS_PHY_749_DATA 0x00000000
+#define DDRSS_PHY_750_DATA 0x00000000
+#define DDRSS_PHY_751_DATA 0x00000000
+#define DDRSS_PHY_752_DATA 0x00000000
+#define DDRSS_PHY_753_DATA 0x00000000
+#define DDRSS_PHY_754_DATA 0x00000000
+#define DDRSS_PHY_755_DATA 0x00000000
+#define DDRSS_PHY_756_DATA 0x00000000
+#define DDRSS_PHY_757_DATA 0x00000000
+#define DDRSS_PHY_758_DATA 0x00000000
+#define DDRSS_PHY_759_DATA 0x00000000
+#define DDRSS_PHY_760_DATA 0x00000000
+#define DDRSS_PHY_761_DATA 0x00000000
+#define DDRSS_PHY_762_DATA 0x00000000
+#define DDRSS_PHY_763_DATA 0x00000000
+#define DDRSS_PHY_764_DATA 0x00000000
+#define DDRSS_PHY_765_DATA 0x00000000
+#define DDRSS_PHY_766_DATA 0x00000000
+#define DDRSS_PHY_767_DATA 0x00000000
+#define DDRSS_PHY_768_DATA 0x04F00000
+#define DDRSS_PHY_769_DATA 0x00000000
+#define DDRSS_PHY_770_DATA 0x00030200
+#define DDRSS_PHY_771_DATA 0x00000000
+#define DDRSS_PHY_772_DATA 0x00000000
+#define DDRSS_PHY_773_DATA 0x01030000
+#define DDRSS_PHY_774_DATA 0x00010000
+#define DDRSS_PHY_775_DATA 0x01030004
+#define DDRSS_PHY_776_DATA 0x01000000
+#define DDRSS_PHY_777_DATA 0x00000000
+#define DDRSS_PHY_778_DATA 0x00000000
+#define DDRSS_PHY_779_DATA 0x00000000
+#define DDRSS_PHY_780_DATA 0x01010000
+#define DDRSS_PHY_781_DATA 0x00010000
+#define DDRSS_PHY_782_DATA 0x00C00001
+#define DDRSS_PHY_783_DATA 0x00CC0008
+#define DDRSS_PHY_784_DATA 0x00660601
+#define DDRSS_PHY_785_DATA 0x00000003
+#define DDRSS_PHY_786_DATA 0x00000000
+#define DDRSS_PHY_787_DATA 0x00000301
+#define DDRSS_PHY_788_DATA 0x0000AAAA
+#define DDRSS_PHY_789_DATA 0x00005555
+#define DDRSS_PHY_790_DATA 0x0000B5B5
+#define DDRSS_PHY_791_DATA 0x00004A4A
+#define DDRSS_PHY_792_DATA 0x00005656
+#define DDRSS_PHY_793_DATA 0x0000A9A9
+#define DDRSS_PHY_794_DATA 0x0000B7B7
+#define DDRSS_PHY_795_DATA 0x00004848
+#define DDRSS_PHY_796_DATA 0x00000000
+#define DDRSS_PHY_797_DATA 0x00000000
+#define DDRSS_PHY_798_DATA 0x08000000
+#define DDRSS_PHY_799_DATA 0x0F000008
+#define DDRSS_PHY_800_DATA 0x00000F0F
+#define DDRSS_PHY_801_DATA 0x00E4E400
+#define DDRSS_PHY_802_DATA 0x00071040
+#define DDRSS_PHY_803_DATA 0x000C0020
+#define DDRSS_PHY_804_DATA 0x00062000
+#define DDRSS_PHY_805_DATA 0x00000000
+#define DDRSS_PHY_806_DATA 0x55555555
+#define DDRSS_PHY_807_DATA 0xAAAAAAAA
+#define DDRSS_PHY_808_DATA 0x55555555
+#define DDRSS_PHY_809_DATA 0xAAAAAAAA
+#define DDRSS_PHY_810_DATA 0x00005555
+#define DDRSS_PHY_811_DATA 0x01000100
+#define DDRSS_PHY_812_DATA 0x00800180
+#define DDRSS_PHY_813_DATA 0x00000000
+#define DDRSS_PHY_814_DATA 0x00000000
+#define DDRSS_PHY_815_DATA 0x00000000
+#define DDRSS_PHY_816_DATA 0x00000000
+#define DDRSS_PHY_817_DATA 0x00000000
+#define DDRSS_PHY_818_DATA 0x00000000
+#define DDRSS_PHY_819_DATA 0x00000000
+#define DDRSS_PHY_820_DATA 0x00000000
+#define DDRSS_PHY_821_DATA 0x00000000
+#define DDRSS_PHY_822_DATA 0x00000000
+#define DDRSS_PHY_823_DATA 0x00000000
+#define DDRSS_PHY_824_DATA 0x00000000
+#define DDRSS_PHY_825_DATA 0x00000000
+#define DDRSS_PHY_826_DATA 0x00000000
+#define DDRSS_PHY_827_DATA 0x00000000
+#define DDRSS_PHY_828_DATA 0x00000000
+#define DDRSS_PHY_829_DATA 0x00000000
+#define DDRSS_PHY_830_DATA 0x00000000
+#define DDRSS_PHY_831_DATA 0x00000000
+#define DDRSS_PHY_832_DATA 0x00000000
+#define DDRSS_PHY_833_DATA 0x00000000
+#define DDRSS_PHY_834_DATA 0x00000000
+#define DDRSS_PHY_835_DATA 0x00000004
+#define DDRSS_PHY_836_DATA 0x00000000
+#define DDRSS_PHY_837_DATA 0x00000000
+#define DDRSS_PHY_838_DATA 0x00000000
+#define DDRSS_PHY_839_DATA 0x00000000
+#define DDRSS_PHY_840_DATA 0x00000000
+#define DDRSS_PHY_841_DATA 0x00000000
+#define DDRSS_PHY_842_DATA 0x081F07FF
+#define DDRSS_PHY_843_DATA 0x10200080
+#define DDRSS_PHY_844_DATA 0x00000008
+#define DDRSS_PHY_845_DATA 0x00000401
+#define DDRSS_PHY_846_DATA 0x00000000
+#define DDRSS_PHY_847_DATA 0x01CC0C01
+#define DDRSS_PHY_848_DATA 0x1003CC0C
+#define DDRSS_PHY_849_DATA 0x20000140
+#define DDRSS_PHY_850_DATA 0x07FF0200
+#define DDRSS_PHY_851_DATA 0x0000DD01
+#define DDRSS_PHY_852_DATA 0x00100303
+#define DDRSS_PHY_853_DATA 0x00000000
+#define DDRSS_PHY_854_DATA 0x00000000
+#define DDRSS_PHY_855_DATA 0x00041000
+#define DDRSS_PHY_856_DATA 0x00100010
+#define DDRSS_PHY_857_DATA 0x00100010
+#define DDRSS_PHY_858_DATA 0x00100010
+#define DDRSS_PHY_859_DATA 0x00100010
+#define DDRSS_PHY_860_DATA 0x02000010
+#define DDRSS_PHY_861_DATA 0x00000005
+#define DDRSS_PHY_862_DATA 0x51516042
+#define DDRSS_PHY_863_DATA 0x31C06000
+#define DDRSS_PHY_864_DATA 0x07AB0340
+#define DDRSS_PHY_865_DATA 0x00C0C001
+#define DDRSS_PHY_866_DATA 0x0D000000
+#define DDRSS_PHY_867_DATA 0x000D0C0C
+#define DDRSS_PHY_868_DATA 0x42100010
+#define DDRSS_PHY_869_DATA 0x010C073E
+#define DDRSS_PHY_870_DATA 0x000F0C32
+#define DDRSS_PHY_871_DATA 0x01000140
+#define DDRSS_PHY_872_DATA 0x011E0120
+#define DDRSS_PHY_873_DATA 0x00000C00
+#define DDRSS_PHY_874_DATA 0x000002DD
+#define DDRSS_PHY_875_DATA 0x00030200
+#define DDRSS_PHY_876_DATA 0x02800000
+#define DDRSS_PHY_877_DATA 0x80800000
+#define DDRSS_PHY_878_DATA 0x000D2010
+#define DDRSS_PHY_879_DATA 0x76543210
+#define DDRSS_PHY_880_DATA 0x00000008
+#define DDRSS_PHY_881_DATA 0x045D045D
+#define DDRSS_PHY_882_DATA 0x045D045D
+#define DDRSS_PHY_883_DATA 0x045D045D
+#define DDRSS_PHY_884_DATA 0x045D045D
+#define DDRSS_PHY_885_DATA 0x0000045D
+#define DDRSS_PHY_886_DATA 0x0000A000
+#define DDRSS_PHY_887_DATA 0x00A000A0
+#define DDRSS_PHY_888_DATA 0x00A000A0
+#define DDRSS_PHY_889_DATA 0x00A000A0
+#define DDRSS_PHY_890_DATA 0x00A000A0
+#define DDRSS_PHY_891_DATA 0x00A000A0
+#define DDRSS_PHY_892_DATA 0x00A000A0
+#define DDRSS_PHY_893_DATA 0x00A000A0
+#define DDRSS_PHY_894_DATA 0x00A000A0
+#define DDRSS_PHY_895_DATA 0x00B200A0
+#define DDRSS_PHY_896_DATA 0x01000000
+#define DDRSS_PHY_897_DATA 0x00000000
+#define DDRSS_PHY_898_DATA 0x00000000
+#define DDRSS_PHY_899_DATA 0x00080200
+#define DDRSS_PHY_900_DATA 0x00000000
+#define DDRSS_PHY_901_DATA 0x20202020
+#define DDRSS_PHY_902_DATA 0x20202020
+#define DDRSS_PHY_903_DATA 0xF0F02020
+#define DDRSS_PHY_904_DATA 0x00000000
+#define DDRSS_PHY_905_DATA 0x00000000
+#define DDRSS_PHY_906_DATA 0x00000000
+#define DDRSS_PHY_907_DATA 0x00000000
+#define DDRSS_PHY_908_DATA 0x00000000
+#define DDRSS_PHY_909_DATA 0x00000000
+#define DDRSS_PHY_910_DATA 0x00000000
+#define DDRSS_PHY_911_DATA 0x00000000
+#define DDRSS_PHY_912_DATA 0x00000000
+#define DDRSS_PHY_913_DATA 0x00000000
+#define DDRSS_PHY_914_DATA 0x00000000
+#define DDRSS_PHY_915_DATA 0x00000000
+#define DDRSS_PHY_916_DATA 0x00000000
+#define DDRSS_PHY_917_DATA 0x00000000
+#define DDRSS_PHY_918_DATA 0x00000000
+#define DDRSS_PHY_919_DATA 0x00000000
+#define DDRSS_PHY_920_DATA 0x00000000
+#define DDRSS_PHY_921_DATA 0x00000000
+#define DDRSS_PHY_922_DATA 0x00000000
+#define DDRSS_PHY_923_DATA 0x00000000
+#define DDRSS_PHY_924_DATA 0x00000000
+#define DDRSS_PHY_925_DATA 0x00000000
+#define DDRSS_PHY_926_DATA 0x00000000
+#define DDRSS_PHY_927_DATA 0x00000000
+#define DDRSS_PHY_928_DATA 0x00000000
+#define DDRSS_PHY_929_DATA 0x00000000
+#define DDRSS_PHY_930_DATA 0x00000000
+#define DDRSS_PHY_931_DATA 0x00000000
+#define DDRSS_PHY_932_DATA 0x00000000
+#define DDRSS_PHY_933_DATA 0x00000000
+#define DDRSS_PHY_934_DATA 0x00000000
+#define DDRSS_PHY_935_DATA 0x00000000
+#define DDRSS_PHY_936_DATA 0x00000000
+#define DDRSS_PHY_937_DATA 0x00000000
+#define DDRSS_PHY_938_DATA 0x00000000
+#define DDRSS_PHY_939_DATA 0x00000000
+#define DDRSS_PHY_940_DATA 0x00000000
+#define DDRSS_PHY_941_DATA 0x00000000
+#define DDRSS_PHY_942_DATA 0x00000000
+#define DDRSS_PHY_943_DATA 0x00000000
+#define DDRSS_PHY_944_DATA 0x00000000
+#define DDRSS_PHY_945_DATA 0x00000000
+#define DDRSS_PHY_946_DATA 0x00000000
+#define DDRSS_PHY_947_DATA 0x00000000
+#define DDRSS_PHY_948_DATA 0x00000000
+#define DDRSS_PHY_949_DATA 0x00000000
+#define DDRSS_PHY_950_DATA 0x00000000
+#define DDRSS_PHY_951_DATA 0x00000000
+#define DDRSS_PHY_952_DATA 0x00000000
+#define DDRSS_PHY_953_DATA 0x00000000
+#define DDRSS_PHY_954_DATA 0x00000000
+#define DDRSS_PHY_955_DATA 0x00000000
+#define DDRSS_PHY_956_DATA 0x00000000
+#define DDRSS_PHY_957_DATA 0x00000000
+#define DDRSS_PHY_958_DATA 0x00000000
+#define DDRSS_PHY_959_DATA 0x00000000
+#define DDRSS_PHY_960_DATA 0x00000000
+#define DDRSS_PHY_961_DATA 0x00000000
+#define DDRSS_PHY_962_DATA 0x00000000
+#define DDRSS_PHY_963_DATA 0x00000000
+#define DDRSS_PHY_964_DATA 0x00000000
+#define DDRSS_PHY_965_DATA 0x00000000
+#define DDRSS_PHY_966_DATA 0x00000000
+#define DDRSS_PHY_967_DATA 0x00000000
+#define DDRSS_PHY_968_DATA 0x00000000
+#define DDRSS_PHY_969_DATA 0x00000000
+#define DDRSS_PHY_970_DATA 0x00000000
+#define DDRSS_PHY_971_DATA 0x00000000
+#define DDRSS_PHY_972_DATA 0x00000000
+#define DDRSS_PHY_973_DATA 0x00000000
+#define DDRSS_PHY_974_DATA 0x00000000
+#define DDRSS_PHY_975_DATA 0x00000000
+#define DDRSS_PHY_976_DATA 0x00000000
+#define DDRSS_PHY_977_DATA 0x00000000
+#define DDRSS_PHY_978_DATA 0x00000000
+#define DDRSS_PHY_979_DATA 0x00000000
+#define DDRSS_PHY_980_DATA 0x00000000
+#define DDRSS_PHY_981_DATA 0x00000000
+#define DDRSS_PHY_982_DATA 0x00000000
+#define DDRSS_PHY_983_DATA 0x00000000
+#define DDRSS_PHY_984_DATA 0x00000000
+#define DDRSS_PHY_985_DATA 0x00000000
+#define DDRSS_PHY_986_DATA 0x00000000
+#define DDRSS_PHY_987_DATA 0x00000000
+#define DDRSS_PHY_988_DATA 0x00000000
+#define DDRSS_PHY_989_DATA 0x00000000
+#define DDRSS_PHY_990_DATA 0x00000000
+#define DDRSS_PHY_991_DATA 0x00000000
+#define DDRSS_PHY_992_DATA 0x00000000
+#define DDRSS_PHY_993_DATA 0x00000000
+#define DDRSS_PHY_994_DATA 0x00000000
+#define DDRSS_PHY_995_DATA 0x00000000
+#define DDRSS_PHY_996_DATA 0x00000000
+#define DDRSS_PHY_997_DATA 0x00000000
+#define DDRSS_PHY_998_DATA 0x00000000
+#define DDRSS_PHY_999_DATA 0x00000000
+#define DDRSS_PHY_1000_DATA 0x00000000
+#define DDRSS_PHY_1001_DATA 0x00000000
+#define DDRSS_PHY_1002_DATA 0x00000000
+#define DDRSS_PHY_1003_DATA 0x00000000
+#define DDRSS_PHY_1004_DATA 0x00000000
+#define DDRSS_PHY_1005_DATA 0x00000000
+#define DDRSS_PHY_1006_DATA 0x00000000
+#define DDRSS_PHY_1007_DATA 0x00000000
+#define DDRSS_PHY_1008_DATA 0x00000000
+#define DDRSS_PHY_1009_DATA 0x00000000
+#define DDRSS_PHY_1010_DATA 0x00000000
+#define DDRSS_PHY_1011_DATA 0x00000000
+#define DDRSS_PHY_1012_DATA 0x00000000
+#define DDRSS_PHY_1013_DATA 0x00000000
+#define DDRSS_PHY_1014_DATA 0x00000000
+#define DDRSS_PHY_1015_DATA 0x00000000
+#define DDRSS_PHY_1016_DATA 0x00000000
+#define DDRSS_PHY_1017_DATA 0x00000000
+#define DDRSS_PHY_1018_DATA 0x00000000
+#define DDRSS_PHY_1019_DATA 0x00000000
+#define DDRSS_PHY_1020_DATA 0x00000000
+#define DDRSS_PHY_1021_DATA 0x00000000
+#define DDRSS_PHY_1022_DATA 0x00000000
+#define DDRSS_PHY_1023_DATA 0x00000000
+#define DDRSS_PHY_1024_DATA 0x00000000
+#define DDRSS_PHY_1025_DATA 0x00000000
+#define DDRSS_PHY_1026_DATA 0x00000000
+#define DDRSS_PHY_1027_DATA 0x00000000
+#define DDRSS_PHY_1028_DATA 0x00000000
+#define DDRSS_PHY_1029_DATA 0x00000100
+#define DDRSS_PHY_1030_DATA 0x00000200
+#define DDRSS_PHY_1031_DATA 0x00000000
+#define DDRSS_PHY_1032_DATA 0x00000000
+#define DDRSS_PHY_1033_DATA 0x00000000
+#define DDRSS_PHY_1034_DATA 0x00000000
+#define DDRSS_PHY_1035_DATA 0x00400000
+#define DDRSS_PHY_1036_DATA 0x00000080
+#define DDRSS_PHY_1037_DATA 0x00DCBA98
+#define DDRSS_PHY_1038_DATA 0x03000000
+#define DDRSS_PHY_1039_DATA 0x00200000
+#define DDRSS_PHY_1040_DATA 0x00000000
+#define DDRSS_PHY_1041_DATA 0x00000000
+#define DDRSS_PHY_1042_DATA 0x00000000
+#define DDRSS_PHY_1043_DATA 0x00000000
+#define DDRSS_PHY_1044_DATA 0x00000000
+#define DDRSS_PHY_1045_DATA 0x0000002A
+#define DDRSS_PHY_1046_DATA 0x00000015
+#define DDRSS_PHY_1047_DATA 0x00000015
+#define DDRSS_PHY_1048_DATA 0x0000002A
+#define DDRSS_PHY_1049_DATA 0x00000033
+#define DDRSS_PHY_1050_DATA 0x0000000C
+#define DDRSS_PHY_1051_DATA 0x0000000C
+#define DDRSS_PHY_1052_DATA 0x00000033
+#define DDRSS_PHY_1053_DATA 0x0A418820
+#define DDRSS_PHY_1054_DATA 0x003F0000
+#define DDRSS_PHY_1055_DATA 0x000F013F
+#define DDRSS_PHY_1056_DATA 0x20202003
+#define DDRSS_PHY_1057_DATA 0x00202020
+#define DDRSS_PHY_1058_DATA 0x20008008
+#define DDRSS_PHY_1059_DATA 0x00000810
+#define DDRSS_PHY_1060_DATA 0x00000F00
+#define DDRSS_PHY_1061_DATA 0x000405CC
+#define DDRSS_PHY_1062_DATA 0x03000004
+#define DDRSS_PHY_1063_DATA 0x00030000
+#define DDRSS_PHY_1064_DATA 0x00000300
+#define DDRSS_PHY_1065_DATA 0x00000300
+#define DDRSS_PHY_1066_DATA 0x00000300
+#define DDRSS_PHY_1067_DATA 0x00000300
+#define DDRSS_PHY_1068_DATA 0x42080010
+#define DDRSS_PHY_1069_DATA 0x0000803E
+#define DDRSS_PHY_1070_DATA 0x00000001
+#define DDRSS_PHY_1071_DATA 0x01000002
+#define DDRSS_PHY_1072_DATA 0x00008000
+#define DDRSS_PHY_1073_DATA 0x00000000
+#define DDRSS_PHY_1074_DATA 0x00000000
+#define DDRSS_PHY_1075_DATA 0x00000000
+#define DDRSS_PHY_1076_DATA 0x00000000
+#define DDRSS_PHY_1077_DATA 0x00000000
+#define DDRSS_PHY_1078_DATA 0x00000000
+#define DDRSS_PHY_1079_DATA 0x00000000
+#define DDRSS_PHY_1080_DATA 0x00000000
+#define DDRSS_PHY_1081_DATA 0x00000000
+#define DDRSS_PHY_1082_DATA 0x00000000
+#define DDRSS_PHY_1083_DATA 0x00000000
+#define DDRSS_PHY_1084_DATA 0x00000000
+#define DDRSS_PHY_1085_DATA 0x00000000
+#define DDRSS_PHY_1086_DATA 0x00000000
+#define DDRSS_PHY_1087_DATA 0x00000000
+#define DDRSS_PHY_1088_DATA 0x00000000
+#define DDRSS_PHY_1089_DATA 0x00000000
+#define DDRSS_PHY_1090_DATA 0x00000000
+#define DDRSS_PHY_1091_DATA 0x00000000
+#define DDRSS_PHY_1092_DATA 0x00000000
+#define DDRSS_PHY_1093_DATA 0x00000000
+#define DDRSS_PHY_1094_DATA 0x00000000
+#define DDRSS_PHY_1095_DATA 0x00000000
+#define DDRSS_PHY_1096_DATA 0x00000000
+#define DDRSS_PHY_1097_DATA 0x00000000
+#define DDRSS_PHY_1098_DATA 0x00000000
+#define DDRSS_PHY_1099_DATA 0x00000000
+#define DDRSS_PHY_1100_DATA 0x00000000
+#define DDRSS_PHY_1101_DATA 0x00000000
+#define DDRSS_PHY_1102_DATA 0x00000000
+#define DDRSS_PHY_1103_DATA 0x00000000
+#define DDRSS_PHY_1104_DATA 0x00000000
+#define DDRSS_PHY_1105_DATA 0x00000000
+#define DDRSS_PHY_1106_DATA 0x00000000
+#define DDRSS_PHY_1107_DATA 0x00000000
+#define DDRSS_PHY_1108_DATA 0x00000000
+#define DDRSS_PHY_1109_DATA 0x00000000
+#define DDRSS_PHY_1110_DATA 0x00000000
+#define DDRSS_PHY_1111_DATA 0x00000000
+#define DDRSS_PHY_1112_DATA 0x00000000
+#define DDRSS_PHY_1113_DATA 0x00000000
+#define DDRSS_PHY_1114_DATA 0x00000000
+#define DDRSS_PHY_1115_DATA 0x00000000
+#define DDRSS_PHY_1116_DATA 0x00000000
+#define DDRSS_PHY_1117_DATA 0x00000000
+#define DDRSS_PHY_1118_DATA 0x00000000
+#define DDRSS_PHY_1119_DATA 0x00000000
+#define DDRSS_PHY_1120_DATA 0x00000000
+#define DDRSS_PHY_1121_DATA 0x00000000
+#define DDRSS_PHY_1122_DATA 0x00000000
+#define DDRSS_PHY_1123_DATA 0x00000000
+#define DDRSS_PHY_1124_DATA 0x00000000
+#define DDRSS_PHY_1125_DATA 0x00000000
+#define DDRSS_PHY_1126_DATA 0x00000000
+#define DDRSS_PHY_1127_DATA 0x00000000
+#define DDRSS_PHY_1128_DATA 0x00000000
+#define DDRSS_PHY_1129_DATA 0x00000000
+#define DDRSS_PHY_1130_DATA 0x00000000
+#define DDRSS_PHY_1131_DATA 0x00000000
+#define DDRSS_PHY_1132_DATA 0x00000000
+#define DDRSS_PHY_1133_DATA 0x00000000
+#define DDRSS_PHY_1134_DATA 0x00000000
+#define DDRSS_PHY_1135_DATA 0x00000000
+#define DDRSS_PHY_1136_DATA 0x00000000
+#define DDRSS_PHY_1137_DATA 0x00000000
+#define DDRSS_PHY_1138_DATA 0x00000000
+#define DDRSS_PHY_1139_DATA 0x00000000
+#define DDRSS_PHY_1140_DATA 0x00000000
+#define DDRSS_PHY_1141_DATA 0x00000000
+#define DDRSS_PHY_1142_DATA 0x00000000
+#define DDRSS_PHY_1143_DATA 0x00000000
+#define DDRSS_PHY_1144_DATA 0x00000000
+#define DDRSS_PHY_1145_DATA 0x00000000
+#define DDRSS_PHY_1146_DATA 0x00000000
+#define DDRSS_PHY_1147_DATA 0x00000000
+#define DDRSS_PHY_1148_DATA 0x00000000
+#define DDRSS_PHY_1149_DATA 0x00000000
+#define DDRSS_PHY_1150_DATA 0x00000000
+#define DDRSS_PHY_1151_DATA 0x00000000
+#define DDRSS_PHY_1152_DATA 0x00000000
+#define DDRSS_PHY_1153_DATA 0x00000000
+#define DDRSS_PHY_1154_DATA 0x00000000
+#define DDRSS_PHY_1155_DATA 0x00000000
+#define DDRSS_PHY_1156_DATA 0x00000000
+#define DDRSS_PHY_1157_DATA 0x00000000
+#define DDRSS_PHY_1158_DATA 0x00000000
+#define DDRSS_PHY_1159_DATA 0x00000000
+#define DDRSS_PHY_1160_DATA 0x00000000
+#define DDRSS_PHY_1161_DATA 0x00000000
+#define DDRSS_PHY_1162_DATA 0x00000000
+#define DDRSS_PHY_1163_DATA 0x00000000
+#define DDRSS_PHY_1164_DATA 0x00000000
+#define DDRSS_PHY_1165_DATA 0x00000000
+#define DDRSS_PHY_1166_DATA 0x00000000
+#define DDRSS_PHY_1167_DATA 0x00000000
+#define DDRSS_PHY_1168_DATA 0x00000000
+#define DDRSS_PHY_1169_DATA 0x00000000
+#define DDRSS_PHY_1170_DATA 0x00000000
+#define DDRSS_PHY_1171_DATA 0x00000000
+#define DDRSS_PHY_1172_DATA 0x00000000
+#define DDRSS_PHY_1173_DATA 0x00000000
+#define DDRSS_PHY_1174_DATA 0x00000000
+#define DDRSS_PHY_1175_DATA 0x00000000
+#define DDRSS_PHY_1176_DATA 0x00000000
+#define DDRSS_PHY_1177_DATA 0x00000000
+#define DDRSS_PHY_1178_DATA 0x00000000
+#define DDRSS_PHY_1179_DATA 0x00000000
+#define DDRSS_PHY_1180_DATA 0x00000000
+#define DDRSS_PHY_1181_DATA 0x00000000
+#define DDRSS_PHY_1182_DATA 0x00000000
+#define DDRSS_PHY_1183_DATA 0x00000000
+#define DDRSS_PHY_1184_DATA 0x00000000
+#define DDRSS_PHY_1185_DATA 0x00000000
+#define DDRSS_PHY_1186_DATA 0x00000000
+#define DDRSS_PHY_1187_DATA 0x00000000
+#define DDRSS_PHY_1188_DATA 0x00000000
+#define DDRSS_PHY_1189_DATA 0x00000000
+#define DDRSS_PHY_1190_DATA 0x00000000
+#define DDRSS_PHY_1191_DATA 0x00000000
+#define DDRSS_PHY_1192_DATA 0x00000000
+#define DDRSS_PHY_1193_DATA 0x00000000
+#define DDRSS_PHY_1194_DATA 0x00000000
+#define DDRSS_PHY_1195_DATA 0x00000000
+#define DDRSS_PHY_1196_DATA 0x00000000
+#define DDRSS_PHY_1197_DATA 0x00000000
+#define DDRSS_PHY_1198_DATA 0x00000000
+#define DDRSS_PHY_1199_DATA 0x00000000
+#define DDRSS_PHY_1200_DATA 0x00000000
+#define DDRSS_PHY_1201_DATA 0x00000000
+#define DDRSS_PHY_1202_DATA 0x00000000
+#define DDRSS_PHY_1203_DATA 0x00000000
+#define DDRSS_PHY_1204_DATA 0x00000000
+#define DDRSS_PHY_1205_DATA 0x00000000
+#define DDRSS_PHY_1206_DATA 0x00000000
+#define DDRSS_PHY_1207_DATA 0x00000000
+#define DDRSS_PHY_1208_DATA 0x00000000
+#define DDRSS_PHY_1209_DATA 0x00000000
+#define DDRSS_PHY_1210_DATA 0x00000000
+#define DDRSS_PHY_1211_DATA 0x00000000
+#define DDRSS_PHY_1212_DATA 0x00000000
+#define DDRSS_PHY_1213_DATA 0x00000000
+#define DDRSS_PHY_1214_DATA 0x00000000
+#define DDRSS_PHY_1215_DATA 0x00000000
+#define DDRSS_PHY_1216_DATA 0x00000000
+#define DDRSS_PHY_1217_DATA 0x00000000
+#define DDRSS_PHY_1218_DATA 0x00000000
+#define DDRSS_PHY_1219_DATA 0x00000000
+#define DDRSS_PHY_1220_DATA 0x00000000
+#define DDRSS_PHY_1221_DATA 0x00000000
+#define DDRSS_PHY_1222_DATA 0x00000000
+#define DDRSS_PHY_1223_DATA 0x00000000
+#define DDRSS_PHY_1224_DATA 0x00000000
+#define DDRSS_PHY_1225_DATA 0x00000000
+#define DDRSS_PHY_1226_DATA 0x00000000
+#define DDRSS_PHY_1227_DATA 0x00000000
+#define DDRSS_PHY_1228_DATA 0x00000000
+#define DDRSS_PHY_1229_DATA 0x00000000
+#define DDRSS_PHY_1230_DATA 0x00000000
+#define DDRSS_PHY_1231_DATA 0x00000000
+#define DDRSS_PHY_1232_DATA 0x00000000
+#define DDRSS_PHY_1233_DATA 0x00000000
+#define DDRSS_PHY_1234_DATA 0x00000000
+#define DDRSS_PHY_1235_DATA 0x00000000
+#define DDRSS_PHY_1236_DATA 0x00000000
+#define DDRSS_PHY_1237_DATA 0x00000000
+#define DDRSS_PHY_1238_DATA 0x00000000
+#define DDRSS_PHY_1239_DATA 0x00000000
+#define DDRSS_PHY_1240_DATA 0x00000000
+#define DDRSS_PHY_1241_DATA 0x00000000
+#define DDRSS_PHY_1242_DATA 0x00000000
+#define DDRSS_PHY_1243_DATA 0x00000000
+#define DDRSS_PHY_1244_DATA 0x00000000
+#define DDRSS_PHY_1245_DATA 0x00000000
+#define DDRSS_PHY_1246_DATA 0x00000000
+#define DDRSS_PHY_1247_DATA 0x00000000
+#define DDRSS_PHY_1248_DATA 0x00000000
+#define DDRSS_PHY_1249_DATA 0x00000000
+#define DDRSS_PHY_1250_DATA 0x00000000
+#define DDRSS_PHY_1251_DATA 0x00000000
+#define DDRSS_PHY_1252_DATA 0x00000000
+#define DDRSS_PHY_1253_DATA 0x00000000
+#define DDRSS_PHY_1254_DATA 0x00000000
+#define DDRSS_PHY_1255_DATA 0x00000000
+#define DDRSS_PHY_1256_DATA 0x00000000
+#define DDRSS_PHY_1257_DATA 0x00000000
+#define DDRSS_PHY_1258_DATA 0x00000000
+#define DDRSS_PHY_1259_DATA 0x00000000
+#define DDRSS_PHY_1260_DATA 0x00000000
+#define DDRSS_PHY_1261_DATA 0x00000000
+#define DDRSS_PHY_1262_DATA 0x00000000
+#define DDRSS_PHY_1263_DATA 0x00000000
+#define DDRSS_PHY_1264_DATA 0x00000000
+#define DDRSS_PHY_1265_DATA 0x00000000
+#define DDRSS_PHY_1266_DATA 0x00000000
+#define DDRSS_PHY_1267_DATA 0x00000000
+#define DDRSS_PHY_1268_DATA 0x00000000
+#define DDRSS_PHY_1269_DATA 0x00000000
+#define DDRSS_PHY_1270_DATA 0x00000000
+#define DDRSS_PHY_1271_DATA 0x00000000
+#define DDRSS_PHY_1272_DATA 0x00000000
+#define DDRSS_PHY_1273_DATA 0x00000000
+#define DDRSS_PHY_1274_DATA 0x00000000
+#define DDRSS_PHY_1275_DATA 0x00000000
+#define DDRSS_PHY_1276_DATA 0x00000000
+#define DDRSS_PHY_1277_DATA 0x00000000
+#define DDRSS_PHY_1278_DATA 0x00000000
+#define DDRSS_PHY_1279_DATA 0x00000000
+#define DDRSS_PHY_1280_DATA 0x00000000
+#define DDRSS_PHY_1281_DATA 0x00000000
+#define DDRSS_PHY_1282_DATA 0x00000000
+#define DDRSS_PHY_1283_DATA 0x00000000
+#define DDRSS_PHY_1284_DATA 0x00000000
+#define DDRSS_PHY_1285_DATA 0x00000100
+#define DDRSS_PHY_1286_DATA 0x00000200
+#define DDRSS_PHY_1287_DATA 0x00000000
+#define DDRSS_PHY_1288_DATA 0x00000000
+#define DDRSS_PHY_1289_DATA 0x00000000
+#define DDRSS_PHY_1290_DATA 0x00000000
+#define DDRSS_PHY_1291_DATA 0x00400000
+#define DDRSS_PHY_1292_DATA 0x00000080
+#define DDRSS_PHY_1293_DATA 0x00DCBA98
+#define DDRSS_PHY_1294_DATA 0x03000000
+#define DDRSS_PHY_1295_DATA 0x00200000
+#define DDRSS_PHY_1296_DATA 0x00000000
+#define DDRSS_PHY_1297_DATA 0x00000000
+#define DDRSS_PHY_1298_DATA 0x00000000
+#define DDRSS_PHY_1299_DATA 0x00000000
+#define DDRSS_PHY_1300_DATA 0x00000000
+#define DDRSS_PHY_1301_DATA 0x0000002A
+#define DDRSS_PHY_1302_DATA 0x00000015
+#define DDRSS_PHY_1303_DATA 0x00000015
+#define DDRSS_PHY_1304_DATA 0x0000002A
+#define DDRSS_PHY_1305_DATA 0x00000033
+#define DDRSS_PHY_1306_DATA 0x0000000C
+#define DDRSS_PHY_1307_DATA 0x0000000C
+#define DDRSS_PHY_1308_DATA 0x00000033
+#define DDRSS_PHY_1309_DATA 0x0A418820
+#define DDRSS_PHY_1310_DATA 0x00000000
+#define DDRSS_PHY_1311_DATA 0x000F0000
+#define DDRSS_PHY_1312_DATA 0x20202003
+#define DDRSS_PHY_1313_DATA 0x00202020
+#define DDRSS_PHY_1314_DATA 0x20008008
+#define DDRSS_PHY_1315_DATA 0x00000810
+#define DDRSS_PHY_1316_DATA 0x00000F00
+#define DDRSS_PHY_1317_DATA 0x000405CC
+#define DDRSS_PHY_1318_DATA 0x03000004
+#define DDRSS_PHY_1319_DATA 0x00030000
+#define DDRSS_PHY_1320_DATA 0x00000300
+#define DDRSS_PHY_1321_DATA 0x00000300
+#define DDRSS_PHY_1322_DATA 0x00000300
+#define DDRSS_PHY_1323_DATA 0x00000300
+#define DDRSS_PHY_1324_DATA 0x42080010
+#define DDRSS_PHY_1325_DATA 0x0000803E
+#define DDRSS_PHY_1326_DATA 0x00000001
+#define DDRSS_PHY_1327_DATA 0x01000002
+#define DDRSS_PHY_1328_DATA 0x00008000
+#define DDRSS_PHY_1329_DATA 0x00000000
+#define DDRSS_PHY_1330_DATA 0x00000000
+#define DDRSS_PHY_1331_DATA 0x00000000
+#define DDRSS_PHY_1332_DATA 0x00000000
+#define DDRSS_PHY_1333_DATA 0x00000000
+#define DDRSS_PHY_1334_DATA 0x00000000
+#define DDRSS_PHY_1335_DATA 0x00000000
+#define DDRSS_PHY_1336_DATA 0x00000000
+#define DDRSS_PHY_1337_DATA 0x00000000
+#define DDRSS_PHY_1338_DATA 0x00000000
+#define DDRSS_PHY_1339_DATA 0x00000000
+#define DDRSS_PHY_1340_DATA 0x00000000
+#define DDRSS_PHY_1341_DATA 0x00000000
+#define DDRSS_PHY_1342_DATA 0x00000000
+#define DDRSS_PHY_1343_DATA 0x00000000
+#define DDRSS_PHY_1344_DATA 0x00000000
+#define DDRSS_PHY_1345_DATA 0x00000000
+#define DDRSS_PHY_1346_DATA 0x00000000
+#define DDRSS_PHY_1347_DATA 0x00000000
+#define DDRSS_PHY_1348_DATA 0x00000000
+#define DDRSS_PHY_1349_DATA 0x00000000
+#define DDRSS_PHY_1350_DATA 0x00000000
+#define DDRSS_PHY_1351_DATA 0x00000000
+#define DDRSS_PHY_1352_DATA 0x00000000
+#define DDRSS_PHY_1353_DATA 0x00000000
+#define DDRSS_PHY_1354_DATA 0x00000000
+#define DDRSS_PHY_1355_DATA 0x00000000
+#define DDRSS_PHY_1356_DATA 0x00000000
+#define DDRSS_PHY_1357_DATA 0x00000000
+#define DDRSS_PHY_1358_DATA 0x00000000
+#define DDRSS_PHY_1359_DATA 0x00000000
+#define DDRSS_PHY_1360_DATA 0x00000000
+#define DDRSS_PHY_1361_DATA 0x00000000
+#define DDRSS_PHY_1362_DATA 0x00000000
+#define DDRSS_PHY_1363_DATA 0x00000000
+#define DDRSS_PHY_1364_DATA 0x00000000
+#define DDRSS_PHY_1365_DATA 0x00000000
+#define DDRSS_PHY_1366_DATA 0x00000000
+#define DDRSS_PHY_1367_DATA 0x00000000
+#define DDRSS_PHY_1368_DATA 0x00000000
+#define DDRSS_PHY_1369_DATA 0x00000000
+#define DDRSS_PHY_1370_DATA 0x00000000
+#define DDRSS_PHY_1371_DATA 0x00000000
+#define DDRSS_PHY_1372_DATA 0x00000000
+#define DDRSS_PHY_1373_DATA 0x00000000
+#define DDRSS_PHY_1374_DATA 0x00000000
+#define DDRSS_PHY_1375_DATA 0x00000000
+#define DDRSS_PHY_1376_DATA 0x00000000
+#define DDRSS_PHY_1377_DATA 0x00000000
+#define DDRSS_PHY_1378_DATA 0x00000000
+#define DDRSS_PHY_1379_DATA 0x00000000
+#define DDRSS_PHY_1380_DATA 0x00000000
+#define DDRSS_PHY_1381_DATA 0x00000000
+#define DDRSS_PHY_1382_DATA 0x00000000
+#define DDRSS_PHY_1383_DATA 0x00000000
+#define DDRSS_PHY_1384_DATA 0x00000000
+#define DDRSS_PHY_1385_DATA 0x00000000
+#define DDRSS_PHY_1386_DATA 0x00000000
+#define DDRSS_PHY_1387_DATA 0x00000000
+#define DDRSS_PHY_1388_DATA 0x00000000
+#define DDRSS_PHY_1389_DATA 0x00000000
+#define DDRSS_PHY_1390_DATA 0x00000000
+#define DDRSS_PHY_1391_DATA 0x00000000
+#define DDRSS_PHY_1392_DATA 0x00000000
+#define DDRSS_PHY_1393_DATA 0x00000000
+#define DDRSS_PHY_1394_DATA 0x00000000
+#define DDRSS_PHY_1395_DATA 0x00000000
+#define DDRSS_PHY_1396_DATA 0x00000000
+#define DDRSS_PHY_1397_DATA 0x00000000
+#define DDRSS_PHY_1398_DATA 0x00000000
+#define DDRSS_PHY_1399_DATA 0x00000000
+#define DDRSS_PHY_1400_DATA 0x00000000
+#define DDRSS_PHY_1401_DATA 0x00000000
+#define DDRSS_PHY_1402_DATA 0x00000000
+#define DDRSS_PHY_1403_DATA 0x00000000
+#define DDRSS_PHY_1404_DATA 0x00000000
+#define DDRSS_PHY_1405_DATA 0x00000000
+#define DDRSS_PHY_1406_DATA 0x00000000
+#define DDRSS_PHY_1407_DATA 0x00000000
+#define DDRSS_PHY_1408_DATA 0x00000000
+#define DDRSS_PHY_1409_DATA 0x00000000
+#define DDRSS_PHY_1410_DATA 0x00000000
+#define DDRSS_PHY_1411_DATA 0x00000000
+#define DDRSS_PHY_1412_DATA 0x00000000
+#define DDRSS_PHY_1413_DATA 0x00000000
+#define DDRSS_PHY_1414_DATA 0x00000000
+#define DDRSS_PHY_1415_DATA 0x00000000
+#define DDRSS_PHY_1416_DATA 0x00000000
+#define DDRSS_PHY_1417_DATA 0x00000000
+#define DDRSS_PHY_1418_DATA 0x00000000
+#define DDRSS_PHY_1419_DATA 0x00000000
+#define DDRSS_PHY_1420_DATA 0x00000000
+#define DDRSS_PHY_1421_DATA 0x00000000
+#define DDRSS_PHY_1422_DATA 0x00000000
+#define DDRSS_PHY_1423_DATA 0x00000000
+#define DDRSS_PHY_1424_DATA 0x00000000
+#define DDRSS_PHY_1425_DATA 0x00000000
+#define DDRSS_PHY_1426_DATA 0x00000000
+#define DDRSS_PHY_1427_DATA 0x00000000
+#define DDRSS_PHY_1428_DATA 0x00000000
+#define DDRSS_PHY_1429_DATA 0x00000000
+#define DDRSS_PHY_1430_DATA 0x00000000
+#define DDRSS_PHY_1431_DATA 0x00000000
+#define DDRSS_PHY_1432_DATA 0x00000000
+#define DDRSS_PHY_1433_DATA 0x00000000
+#define DDRSS_PHY_1434_DATA 0x00000000
+#define DDRSS_PHY_1435_DATA 0x00000000
+#define DDRSS_PHY_1436_DATA 0x00000000
+#define DDRSS_PHY_1437_DATA 0x00000000
+#define DDRSS_PHY_1438_DATA 0x00000000
+#define DDRSS_PHY_1439_DATA 0x00000000
+#define DDRSS_PHY_1440_DATA 0x00000000
+#define DDRSS_PHY_1441_DATA 0x00000000
+#define DDRSS_PHY_1442_DATA 0x00000000
+#define DDRSS_PHY_1443_DATA 0x00000000
+#define DDRSS_PHY_1444_DATA 0x00000000
+#define DDRSS_PHY_1445_DATA 0x00000000
+#define DDRSS_PHY_1446_DATA 0x00000000
+#define DDRSS_PHY_1447_DATA 0x00000000
+#define DDRSS_PHY_1448_DATA 0x00000000
+#define DDRSS_PHY_1449_DATA 0x00000000
+#define DDRSS_PHY_1450_DATA 0x00000000
+#define DDRSS_PHY_1451_DATA 0x00000000
+#define DDRSS_PHY_1452_DATA 0x00000000
+#define DDRSS_PHY_1453_DATA 0x00000000
+#define DDRSS_PHY_1454_DATA 0x00000000
+#define DDRSS_PHY_1455_DATA 0x00000000
+#define DDRSS_PHY_1456_DATA 0x00000000
+#define DDRSS_PHY_1457_DATA 0x00000000
+#define DDRSS_PHY_1458_DATA 0x00000000
+#define DDRSS_PHY_1459_DATA 0x00000000
+#define DDRSS_PHY_1460_DATA 0x00000000
+#define DDRSS_PHY_1461_DATA 0x00000000
+#define DDRSS_PHY_1462_DATA 0x00000000
+#define DDRSS_PHY_1463_DATA 0x00000000
+#define DDRSS_PHY_1464_DATA 0x00000000
+#define DDRSS_PHY_1465_DATA 0x00000000
+#define DDRSS_PHY_1466_DATA 0x00000000
+#define DDRSS_PHY_1467_DATA 0x00000000
+#define DDRSS_PHY_1468_DATA 0x00000000
+#define DDRSS_PHY_1469_DATA 0x00000000
+#define DDRSS_PHY_1470_DATA 0x00000000
+#define DDRSS_PHY_1471_DATA 0x00000000
+#define DDRSS_PHY_1472_DATA 0x00000000
+#define DDRSS_PHY_1473_DATA 0x00000000
+#define DDRSS_PHY_1474_DATA 0x00000000
+#define DDRSS_PHY_1475_DATA 0x00000000
+#define DDRSS_PHY_1476_DATA 0x00000000
+#define DDRSS_PHY_1477_DATA 0x00000000
+#define DDRSS_PHY_1478_DATA 0x00000000
+#define DDRSS_PHY_1479_DATA 0x00000000
+#define DDRSS_PHY_1480_DATA 0x00000000
+#define DDRSS_PHY_1481_DATA 0x00000000
+#define DDRSS_PHY_1482_DATA 0x00000000
+#define DDRSS_PHY_1483_DATA 0x00000000
+#define DDRSS_PHY_1484_DATA 0x00000000
+#define DDRSS_PHY_1485_DATA 0x00000000
+#define DDRSS_PHY_1486_DATA 0x00000000
+#define DDRSS_PHY_1487_DATA 0x00000000
+#define DDRSS_PHY_1488_DATA 0x00000000
+#define DDRSS_PHY_1489_DATA 0x00000000
+#define DDRSS_PHY_1490_DATA 0x00000000
+#define DDRSS_PHY_1491_DATA 0x00000000
+#define DDRSS_PHY_1492_DATA 0x00000000
+#define DDRSS_PHY_1493_DATA 0x00000000
+#define DDRSS_PHY_1494_DATA 0x00000000
+#define DDRSS_PHY_1495_DATA 0x00000000
+#define DDRSS_PHY_1496_DATA 0x00000000
+#define DDRSS_PHY_1497_DATA 0x00000000
+#define DDRSS_PHY_1498_DATA 0x00000000
+#define DDRSS_PHY_1499_DATA 0x00000000
+#define DDRSS_PHY_1500_DATA 0x00000000
+#define DDRSS_PHY_1501_DATA 0x00000000
+#define DDRSS_PHY_1502_DATA 0x00000000
+#define DDRSS_PHY_1503_DATA 0x00000000
+#define DDRSS_PHY_1504_DATA 0x00000000
+#define DDRSS_PHY_1505_DATA 0x00000000
+#define DDRSS_PHY_1506_DATA 0x00000000
+#define DDRSS_PHY_1507_DATA 0x00000000
+#define DDRSS_PHY_1508_DATA 0x00000000
+#define DDRSS_PHY_1509_DATA 0x00000000
+#define DDRSS_PHY_1510_DATA 0x00000000
+#define DDRSS_PHY_1511_DATA 0x00000000
+#define DDRSS_PHY_1512_DATA 0x00000000
+#define DDRSS_PHY_1513_DATA 0x00000000
+#define DDRSS_PHY_1514_DATA 0x00000000
+#define DDRSS_PHY_1515_DATA 0x00000000
+#define DDRSS_PHY_1516_DATA 0x00000000
+#define DDRSS_PHY_1517_DATA 0x00000000
+#define DDRSS_PHY_1518_DATA 0x00000000
+#define DDRSS_PHY_1519_DATA 0x00000000
+#define DDRSS_PHY_1520_DATA 0x00000000
+#define DDRSS_PHY_1521_DATA 0x00000000
+#define DDRSS_PHY_1522_DATA 0x00000000
+#define DDRSS_PHY_1523_DATA 0x00000000
+#define DDRSS_PHY_1524_DATA 0x00000000
+#define DDRSS_PHY_1525_DATA 0x00000000
+#define DDRSS_PHY_1526_DATA 0x00000000
+#define DDRSS_PHY_1527_DATA 0x00000000
+#define DDRSS_PHY_1528_DATA 0x00000000
+#define DDRSS_PHY_1529_DATA 0x00000000
+#define DDRSS_PHY_1530_DATA 0x00000000
+#define DDRSS_PHY_1531_DATA 0x00000000
+#define DDRSS_PHY_1532_DATA 0x00000000
+#define DDRSS_PHY_1533_DATA 0x00000000
+#define DDRSS_PHY_1534_DATA 0x00000000
+#define DDRSS_PHY_1535_DATA 0x00000000
+#define DDRSS_PHY_1536_DATA 0x00000000
+#define DDRSS_PHY_1537_DATA 0x00000000
+#define DDRSS_PHY_1538_DATA 0x00000000
+#define DDRSS_PHY_1539_DATA 0x00000000
+#define DDRSS_PHY_1540_DATA 0x00000000
+#define DDRSS_PHY_1541_DATA 0x00000100
+#define DDRSS_PHY_1542_DATA 0x00000200
+#define DDRSS_PHY_1543_DATA 0x00000000
+#define DDRSS_PHY_1544_DATA 0x00000000
+#define DDRSS_PHY_1545_DATA 0x00000000
+#define DDRSS_PHY_1546_DATA 0x00000000
+#define DDRSS_PHY_1547_DATA 0x00400000
+#define DDRSS_PHY_1548_DATA 0x00000080
+#define DDRSS_PHY_1549_DATA 0x00DCBA98
+#define DDRSS_PHY_1550_DATA 0x03000000
+#define DDRSS_PHY_1551_DATA 0x00200000
+#define DDRSS_PHY_1552_DATA 0x00000000
+#define DDRSS_PHY_1553_DATA 0x00000000
+#define DDRSS_PHY_1554_DATA 0x00000000
+#define DDRSS_PHY_1555_DATA 0x00000000
+#define DDRSS_PHY_1556_DATA 0x00000000
+#define DDRSS_PHY_1557_DATA 0x0000002A
+#define DDRSS_PHY_1558_DATA 0x00000015
+#define DDRSS_PHY_1559_DATA 0x00000015
+#define DDRSS_PHY_1560_DATA 0x0000002A
+#define DDRSS_PHY_1561_DATA 0x00000033
+#define DDRSS_PHY_1562_DATA 0x0000000C
+#define DDRSS_PHY_1563_DATA 0x0000000C
+#define DDRSS_PHY_1564_DATA 0x00000033
+#define DDRSS_PHY_1565_DATA 0x0A418820
+#define DDRSS_PHY_1566_DATA 0x10000000
+#define DDRSS_PHY_1567_DATA 0x000F0000
+#define DDRSS_PHY_1568_DATA 0x20202003
+#define DDRSS_PHY_1569_DATA 0x00202020
+#define DDRSS_PHY_1570_DATA 0x20008008
+#define DDRSS_PHY_1571_DATA 0x00000810
+#define DDRSS_PHY_1572_DATA 0x00000F00
+#define DDRSS_PHY_1573_DATA 0x000405CC
+#define DDRSS_PHY_1574_DATA 0x03000004
+#define DDRSS_PHY_1575_DATA 0x00030000
+#define DDRSS_PHY_1576_DATA 0x00000300
+#define DDRSS_PHY_1577_DATA 0x00000300
+#define DDRSS_PHY_1578_DATA 0x00000300
+#define DDRSS_PHY_1579_DATA 0x00000300
+#define DDRSS_PHY_1580_DATA 0x42080010
+#define DDRSS_PHY_1581_DATA 0x0000803E
+#define DDRSS_PHY_1582_DATA 0x00000001
+#define DDRSS_PHY_1583_DATA 0x01000002
+#define DDRSS_PHY_1584_DATA 0x00008000
+#define DDRSS_PHY_1585_DATA 0x00000000
+#define DDRSS_PHY_1586_DATA 0x00000000
+#define DDRSS_PHY_1587_DATA 0x00000000
+#define DDRSS_PHY_1588_DATA 0x00000000
+#define DDRSS_PHY_1589_DATA 0x00000000
+#define DDRSS_PHY_1590_DATA 0x00000000
+#define DDRSS_PHY_1591_DATA 0x00000000
+#define DDRSS_PHY_1592_DATA 0x00000000
+#define DDRSS_PHY_1593_DATA 0x00000000
+#define DDRSS_PHY_1594_DATA 0x00000000
+#define DDRSS_PHY_1595_DATA 0x00000000
+#define DDRSS_PHY_1596_DATA 0x00000000
+#define DDRSS_PHY_1597_DATA 0x00000000
+#define DDRSS_PHY_1598_DATA 0x00000000
+#define DDRSS_PHY_1599_DATA 0x00000000
+#define DDRSS_PHY_1600_DATA 0x00000000
+#define DDRSS_PHY_1601_DATA 0x00000000
+#define DDRSS_PHY_1602_DATA 0x00000000
+#define DDRSS_PHY_1603_DATA 0x00000000
+#define DDRSS_PHY_1604_DATA 0x00000000
+#define DDRSS_PHY_1605_DATA 0x00000000
+#define DDRSS_PHY_1606_DATA 0x00000000
+#define DDRSS_PHY_1607_DATA 0x00000000
+#define DDRSS_PHY_1608_DATA 0x00000000
+#define DDRSS_PHY_1609_DATA 0x00000000
+#define DDRSS_PHY_1610_DATA 0x00000000
+#define DDRSS_PHY_1611_DATA 0x00000000
+#define DDRSS_PHY_1612_DATA 0x00000000
+#define DDRSS_PHY_1613_DATA 0x00000000
+#define DDRSS_PHY_1614_DATA 0x00000000
+#define DDRSS_PHY_1615_DATA 0x00000000
+#define DDRSS_PHY_1616_DATA 0x00000000
+#define DDRSS_PHY_1617_DATA 0x00000000
+#define DDRSS_PHY_1618_DATA 0x00000000
+#define DDRSS_PHY_1619_DATA 0x00000000
+#define DDRSS_PHY_1620_DATA 0x00000000
+#define DDRSS_PHY_1621_DATA 0x00000000
+#define DDRSS_PHY_1622_DATA 0x00000000
+#define DDRSS_PHY_1623_DATA 0x00000000
+#define DDRSS_PHY_1624_DATA 0x00000000
+#define DDRSS_PHY_1625_DATA 0x00000000
+#define DDRSS_PHY_1626_DATA 0x00000000
+#define DDRSS_PHY_1627_DATA 0x00000000
+#define DDRSS_PHY_1628_DATA 0x00000000
+#define DDRSS_PHY_1629_DATA 0x00000000
+#define DDRSS_PHY_1630_DATA 0x00000000
+#define DDRSS_PHY_1631_DATA 0x00000000
+#define DDRSS_PHY_1632_DATA 0x00000000
+#define DDRSS_PHY_1633_DATA 0x00000000
+#define DDRSS_PHY_1634_DATA 0x00000000
+#define DDRSS_PHY_1635_DATA 0x00000000
+#define DDRSS_PHY_1636_DATA 0x00000000
+#define DDRSS_PHY_1637_DATA 0x00000000
+#define DDRSS_PHY_1638_DATA 0x00000000
+#define DDRSS_PHY_1639_DATA 0x00000000
+#define DDRSS_PHY_1640_DATA 0x00000000
+#define DDRSS_PHY_1641_DATA 0x00000000
+#define DDRSS_PHY_1642_DATA 0x00000000
+#define DDRSS_PHY_1643_DATA 0x00000000
+#define DDRSS_PHY_1644_DATA 0x00000000
+#define DDRSS_PHY_1645_DATA 0x00000000
+#define DDRSS_PHY_1646_DATA 0x00000000
+#define DDRSS_PHY_1647_DATA 0x00000000
+#define DDRSS_PHY_1648_DATA 0x00000000
+#define DDRSS_PHY_1649_DATA 0x00000000
+#define DDRSS_PHY_1650_DATA 0x00000000
+#define DDRSS_PHY_1651_DATA 0x00000000
+#define DDRSS_PHY_1652_DATA 0x00000000
+#define DDRSS_PHY_1653_DATA 0x00000000
+#define DDRSS_PHY_1654_DATA 0x00000000
+#define DDRSS_PHY_1655_DATA 0x00000000
+#define DDRSS_PHY_1656_DATA 0x00000000
+#define DDRSS_PHY_1657_DATA 0x00000000
+#define DDRSS_PHY_1658_DATA 0x00000000
+#define DDRSS_PHY_1659_DATA 0x00000000
+#define DDRSS_PHY_1660_DATA 0x00000000
+#define DDRSS_PHY_1661_DATA 0x00000000
+#define DDRSS_PHY_1662_DATA 0x00000000
+#define DDRSS_PHY_1663_DATA 0x00000000
+#define DDRSS_PHY_1664_DATA 0x00000000
+#define DDRSS_PHY_1665_DATA 0x00000000
+#define DDRSS_PHY_1666_DATA 0x00000000
+#define DDRSS_PHY_1667_DATA 0x00000000
+#define DDRSS_PHY_1668_DATA 0x00000000
+#define DDRSS_PHY_1669_DATA 0x00000000
+#define DDRSS_PHY_1670_DATA 0x00000000
+#define DDRSS_PHY_1671_DATA 0x00000000
+#define DDRSS_PHY_1672_DATA 0x00000000
+#define DDRSS_PHY_1673_DATA 0x00000000
+#define DDRSS_PHY_1674_DATA 0x00000000
+#define DDRSS_PHY_1675_DATA 0x00000000
+#define DDRSS_PHY_1676_DATA 0x00000000
+#define DDRSS_PHY_1677_DATA 0x00000000
+#define DDRSS_PHY_1678_DATA 0x00000000
+#define DDRSS_PHY_1679_DATA 0x00000000
+#define DDRSS_PHY_1680_DATA 0x00000000
+#define DDRSS_PHY_1681_DATA 0x00000000
+#define DDRSS_PHY_1682_DATA 0x00000000
+#define DDRSS_PHY_1683_DATA 0x00000000
+#define DDRSS_PHY_1684_DATA 0x00000000
+#define DDRSS_PHY_1685_DATA 0x00000000
+#define DDRSS_PHY_1686_DATA 0x00000000
+#define DDRSS_PHY_1687_DATA 0x00000000
+#define DDRSS_PHY_1688_DATA 0x00000000
+#define DDRSS_PHY_1689_DATA 0x00000000
+#define DDRSS_PHY_1690_DATA 0x00000000
+#define DDRSS_PHY_1691_DATA 0x00000000
+#define DDRSS_PHY_1692_DATA 0x00000000
+#define DDRSS_PHY_1693_DATA 0x00000000
+#define DDRSS_PHY_1694_DATA 0x00000000
+#define DDRSS_PHY_1695_DATA 0x00000000
+#define DDRSS_PHY_1696_DATA 0x00000000
+#define DDRSS_PHY_1697_DATA 0x00000000
+#define DDRSS_PHY_1698_DATA 0x00000000
+#define DDRSS_PHY_1699_DATA 0x00000000
+#define DDRSS_PHY_1700_DATA 0x00000000
+#define DDRSS_PHY_1701_DATA 0x00000000
+#define DDRSS_PHY_1702_DATA 0x00000000
+#define DDRSS_PHY_1703_DATA 0x00000000
+#define DDRSS_PHY_1704_DATA 0x00000000
+#define DDRSS_PHY_1705_DATA 0x00000000
+#define DDRSS_PHY_1706_DATA 0x00000000
+#define DDRSS_PHY_1707_DATA 0x00000000
+#define DDRSS_PHY_1708_DATA 0x00000000
+#define DDRSS_PHY_1709_DATA 0x00000000
+#define DDRSS_PHY_1710_DATA 0x00000000
+#define DDRSS_PHY_1711_DATA 0x00000000
+#define DDRSS_PHY_1712_DATA 0x00000000
+#define DDRSS_PHY_1713_DATA 0x00000000
+#define DDRSS_PHY_1714_DATA 0x00000000
+#define DDRSS_PHY_1715_DATA 0x00000000
+#define DDRSS_PHY_1716_DATA 0x00000000
+#define DDRSS_PHY_1717_DATA 0x00000000
+#define DDRSS_PHY_1718_DATA 0x00000000
+#define DDRSS_PHY_1719_DATA 0x00000000
+#define DDRSS_PHY_1720_DATA 0x00000000
+#define DDRSS_PHY_1721_DATA 0x00000000
+#define DDRSS_PHY_1722_DATA 0x00000000
+#define DDRSS_PHY_1723_DATA 0x00000000
+#define DDRSS_PHY_1724_DATA 0x00000000
+#define DDRSS_PHY_1725_DATA 0x00000000
+#define DDRSS_PHY_1726_DATA 0x00000000
+#define DDRSS_PHY_1727_DATA 0x00000000
+#define DDRSS_PHY_1728_DATA 0x00000000
+#define DDRSS_PHY_1729_DATA 0x00000000
+#define DDRSS_PHY_1730_DATA 0x00000000
+#define DDRSS_PHY_1731_DATA 0x00000000
+#define DDRSS_PHY_1732_DATA 0x00000000
+#define DDRSS_PHY_1733_DATA 0x00000000
+#define DDRSS_PHY_1734_DATA 0x00000000
+#define DDRSS_PHY_1735_DATA 0x00000000
+#define DDRSS_PHY_1736_DATA 0x00000000
+#define DDRSS_PHY_1737_DATA 0x00000000
+#define DDRSS_PHY_1738_DATA 0x00000000
+#define DDRSS_PHY_1739_DATA 0x00000000
+#define DDRSS_PHY_1740_DATA 0x00000000
+#define DDRSS_PHY_1741_DATA 0x00000000
+#define DDRSS_PHY_1742_DATA 0x00000000
+#define DDRSS_PHY_1743_DATA 0x00000000
+#define DDRSS_PHY_1744_DATA 0x00000000
+#define DDRSS_PHY_1745_DATA 0x00000000
+#define DDRSS_PHY_1746_DATA 0x00000000
+#define DDRSS_PHY_1747_DATA 0x00000000
+#define DDRSS_PHY_1748_DATA 0x00000000
+#define DDRSS_PHY_1749_DATA 0x00000000
+#define DDRSS_PHY_1750_DATA 0x00000000
+#define DDRSS_PHY_1751_DATA 0x00000000
+#define DDRSS_PHY_1752_DATA 0x00000000
+#define DDRSS_PHY_1753_DATA 0x00000000
+#define DDRSS_PHY_1754_DATA 0x00000000
+#define DDRSS_PHY_1755_DATA 0x00000000
+#define DDRSS_PHY_1756_DATA 0x00000000
+#define DDRSS_PHY_1757_DATA 0x00000000
+#define DDRSS_PHY_1758_DATA 0x00000000
+#define DDRSS_PHY_1759_DATA 0x00000000
+#define DDRSS_PHY_1760_DATA 0x00000000
+#define DDRSS_PHY_1761_DATA 0x00000000
+#define DDRSS_PHY_1762_DATA 0x00000000
+#define DDRSS_PHY_1763_DATA 0x00000000
+#define DDRSS_PHY_1764_DATA 0x00000000
+#define DDRSS_PHY_1765_DATA 0x00000000
+#define DDRSS_PHY_1766_DATA 0x00000000
+#define DDRSS_PHY_1767_DATA 0x00000000
+#define DDRSS_PHY_1768_DATA 0x00000000
+#define DDRSS_PHY_1769_DATA 0x00000000
+#define DDRSS_PHY_1770_DATA 0x00000000
+#define DDRSS_PHY_1771_DATA 0x00000000
+#define DDRSS_PHY_1772_DATA 0x00000000
+#define DDRSS_PHY_1773_DATA 0x00000000
+#define DDRSS_PHY_1774_DATA 0x00000000
+#define DDRSS_PHY_1775_DATA 0x00000000
+#define DDRSS_PHY_1776_DATA 0x00000000
+#define DDRSS_PHY_1777_DATA 0x00000000
+#define DDRSS_PHY_1778_DATA 0x00000000
+#define DDRSS_PHY_1779_DATA 0x00000000
+#define DDRSS_PHY_1780_DATA 0x00000000
+#define DDRSS_PHY_1781_DATA 0x00000000
+#define DDRSS_PHY_1782_DATA 0x00000000
+#define DDRSS_PHY_1783_DATA 0x00000000
+#define DDRSS_PHY_1784_DATA 0x00000000
+#define DDRSS_PHY_1785_DATA 0x00000000
+#define DDRSS_PHY_1786_DATA 0x00000000
+#define DDRSS_PHY_1787_DATA 0x00000000
+#define DDRSS_PHY_1788_DATA 0x00000000
+#define DDRSS_PHY_1789_DATA 0x00000000
+#define DDRSS_PHY_1790_DATA 0x00000000
+#define DDRSS_PHY_1791_DATA 0x00000000
+#define DDRSS_PHY_1792_DATA 0x00000000
+#define DDRSS_PHY_1793_DATA 0x00010100
+#define DDRSS_PHY_1794_DATA 0x00000000
+#define DDRSS_PHY_1795_DATA 0x00000000
+#define DDRSS_PHY_1796_DATA 0x00000000
+#define DDRSS_PHY_1797_DATA 0x00000000
+#define DDRSS_PHY_1798_DATA 0x00050000
+#define DDRSS_PHY_1799_DATA 0x04000000
+#define DDRSS_PHY_1800_DATA 0x00000055
+#define DDRSS_PHY_1801_DATA 0x00000000
+#define DDRSS_PHY_1802_DATA 0x00000000
+#define DDRSS_PHY_1803_DATA 0x00000000
+#define DDRSS_PHY_1804_DATA 0x00000000
+#define DDRSS_PHY_1805_DATA 0x00002001
+#define DDRSS_PHY_1806_DATA 0x00004003
+#define DDRSS_PHY_1807_DATA 0x50020028
+#define DDRSS_PHY_1808_DATA 0x01010000
+#define DDRSS_PHY_1809_DATA 0x80080001
+#define DDRSS_PHY_1810_DATA 0x10200000
+#define DDRSS_PHY_1811_DATA 0x00000008
+#define DDRSS_PHY_1812_DATA 0x00000000
+#define DDRSS_PHY_1813_DATA 0x06000000
+#define DDRSS_PHY_1814_DATA 0x010F0F0E
+#define DDRSS_PHY_1815_DATA 0x00040101
+#define DDRSS_PHY_1816_DATA 0x0000010F
+#define DDRSS_PHY_1817_DATA 0x00000000
+#define DDRSS_PHY_1818_DATA 0x00000064
+#define DDRSS_PHY_1819_DATA 0x00000000
+#define DDRSS_PHY_1820_DATA 0x00000000
+#define DDRSS_PHY_1821_DATA 0x0F0F0F0F
+#define DDRSS_PHY_1822_DATA 0x0F0F0F0F
+#define DDRSS_PHY_1823_DATA 0x0F0F0F0F
+#define DDRSS_PHY_1824_DATA 0x02010804
+#define DDRSS_PHY_1825_DATA 0x00800120
+#define DDRSS_PHY_1826_DATA 0x00041B42
+#define DDRSS_PHY_1827_DATA 0x00004201
+#define DDRSS_PHY_1828_DATA 0x00000000
+#define DDRSS_PHY_1829_DATA 0x00000000
+#define DDRSS_PHY_1830_DATA 0x00000000
+#define DDRSS_PHY_1831_DATA 0x00000000
+#define DDRSS_PHY_1832_DATA 0x00000000
+#define DDRSS_PHY_1833_DATA 0x00000000
+#define DDRSS_PHY_1834_DATA 0x03010100
+#define DDRSS_PHY_1835_DATA 0x00540007
+#define DDRSS_PHY_1836_DATA 0x000040A2
+#define DDRSS_PHY_1837_DATA 0x00024410
+#define DDRSS_PHY_1838_DATA 0x00004410
+#define DDRSS_PHY_1839_DATA 0x00004410
+#define DDRSS_PHY_1840_DATA 0x00004410
+#define DDRSS_PHY_1841_DATA 0x00004410
+#define DDRSS_PHY_1842_DATA 0x00004410
+#define DDRSS_PHY_1843_DATA 0x00004410
+#define DDRSS_PHY_1844_DATA 0x00004410
+#define DDRSS_PHY_1845_DATA 0x00004410
+#define DDRSS_PHY_1846_DATA 0x00004410
+#define DDRSS_PHY_1847_DATA 0x00000000
+#define DDRSS_PHY_1848_DATA 0x00000076
+#define DDRSS_PHY_1849_DATA 0x00000400
+#define DDRSS_PHY_1850_DATA 0x00000008
+#define DDRSS_PHY_1851_DATA 0x00000000
+#define DDRSS_PHY_1852_DATA 0x00000000
+#define DDRSS_PHY_1853_DATA 0x00000000
+#define DDRSS_PHY_1854_DATA 0x00000000
+#define DDRSS_PHY_1855_DATA 0x00000000
+#define DDRSS_PHY_1856_DATA 0x03000000
+#define DDRSS_PHY_1857_DATA 0x00000000
+#define DDRSS_PHY_1858_DATA 0x00000000
+#define DDRSS_PHY_1859_DATA 0x00000000
+#define DDRSS_PHY_1860_DATA 0x04102006
+#define DDRSS_PHY_1861_DATA 0x00041020
+#define DDRSS_PHY_1862_DATA 0x01C98C98
+#define DDRSS_PHY_1863_DATA 0x3F400000
+#define DDRSS_PHY_1864_DATA 0x3F3F1F3F
+#define DDRSS_PHY_1865_DATA 0x0000001F
+#define DDRSS_PHY_1866_DATA 0x00000000
+#define DDRSS_PHY_1867_DATA 0x00000000
+#define DDRSS_PHY_1868_DATA 0x00000000
+#define DDRSS_PHY_1869_DATA 0x00000001
+#define DDRSS_PHY_1870_DATA 0x00000000
+#define DDRSS_PHY_1871_DATA 0x00000000
+#define DDRSS_PHY_1872_DATA 0x00000000
+#define DDRSS_PHY_1873_DATA 0x00000000
+#define DDRSS_PHY_1874_DATA 0x76543210
+#define DDRSS_PHY_1875_DATA 0x06010198
+#define DDRSS_PHY_1876_DATA 0x00000000
+#define DDRSS_PHY_1877_DATA 0x00000000
+#define DDRSS_PHY_1878_DATA 0x00000000
+#define DDRSS_PHY_1879_DATA 0x00040700
+#define DDRSS_PHY_1880_DATA 0x00000000
+#define DDRSS_PHY_1881_DATA 0x00000000
+#define DDRSS_PHY_1882_DATA 0x00000000
+#define DDRSS_PHY_1883_DATA 0x00000000
+#define DDRSS_PHY_1884_DATA 0x00000000
+#define DDRSS_PHY_1885_DATA 0x00000002
+#define DDRSS_PHY_1886_DATA 0x00000000
+#define DDRSS_PHY_1887_DATA 0x00000000
+#define DDRSS_PHY_1888_DATA 0x0001F7C4
+#define DDRSS_PHY_1889_DATA 0x04000004
+#define DDRSS_PHY_1890_DATA 0x00000000
+#define DDRSS_PHY_1891_DATA 0x00001142
+#define DDRSS_PHY_1892_DATA 0x01020000
+#define DDRSS_PHY_1893_DATA 0x00000080
+#define DDRSS_PHY_1894_DATA 0x03900390
+#define DDRSS_PHY_1895_DATA 0x03900390
+#define DDRSS_PHY_1896_DATA 0x03900390
+#define DDRSS_PHY_1897_DATA 0x03900390
+#define DDRSS_PHY_1898_DATA 0x03000300
+#define DDRSS_PHY_1899_DATA 0x03000300
+#define DDRSS_PHY_1900_DATA 0x00000300
+#define DDRSS_PHY_1901_DATA 0x00000300
+#define DDRSS_PHY_1902_DATA 0x00000300
+#define DDRSS_PHY_1903_DATA 0x00000300
+#define DDRSS_PHY_1904_DATA 0x00000005
+#define DDRSS_PHY_1905_DATA 0x3183BF77
+#define DDRSS_PHY_1906_DATA 0x00000000
+#define DDRSS_PHY_1907_DATA 0x0C000DFF
+#define DDRSS_PHY_1908_DATA 0x30000DFF
+#define DDRSS_PHY_1909_DATA 0x3F0DFF11
+#define DDRSS_PHY_1910_DATA 0x00EF0000
+#define DDRSS_PHY_1911_DATA 0x780DFFCC
+#define DDRSS_PHY_1912_DATA 0x00000C11
+#define DDRSS_PHY_1913_DATA 0x00018011
+#define DDRSS_PHY_1914_DATA 0x0089FF00
+#define DDRSS_PHY_1915_DATA 0x000C3F11
+#define DDRSS_PHY_1916_DATA 0x01990000
+#define DDRSS_PHY_1917_DATA 0x000C3F11
+#define DDRSS_PHY_1918_DATA 0x01990000
+#define DDRSS_PHY_1919_DATA 0x3F0DFF11
+#define DDRSS_PHY_1920_DATA 0x00EF0000
+#define DDRSS_PHY_1921_DATA 0x00018011
+#define DDRSS_PHY_1922_DATA 0x0089FF00
+#define DDRSS_PHY_1923_DATA 0x20040006
diff --git a/arch/arm/dts/k3-j722s-evm-u-boot.dtsi b/arch/arm/dts/k3-j722s-evm-u-boot.dtsi
new file mode 100644
index 0000000..88c4a72
--- /dev/null
+++ b/arch/arm/dts/k3-j722s-evm-u-boot.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Common J722S EVM dts file for SPLs
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include "k3-j722s-binman.dtsi"
+
+/ {
+ chosen {
+ stdout-path = "serial2:115200n8";
+ tick-timer = &main_timer0;
+ };
+};
+
+&dmsc {
+ bootph-pre-ram;
+};
diff --git a/arch/arm/dts/k3-j722s-r5-evm.dts b/arch/arm/dts/k3-j722s-r5-evm.dts
new file mode 100644
index 0000000..aff83cd
--- /dev/null
+++ b/arch/arm/dts/k3-j722s-r5-evm.dts
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * J722S EVM dts file for R5 SPL
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include "k3-j722s-evm.dts"
+#include "k3-j722s-evm-u-boot.dtsi"
+
+#include "k3-j722s-ddr-lp4-50-3733.dtsi"
+#include "k3-am62a-ddr.dtsi"
+
+/ {
+ aliases {
+ remoteproc0 = &sysctrler;
+ remoteproc1 = &a53_0;
+ serial0 = &wkup_uart0;
+ serial2 = &main_uart0;
+ };
+
+ a53_0: a53@0 {
+ compatible = "ti,am654-rproc";
+ reg = <0x00 0x00a90000 0x00 0x10>;
+ power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+ <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
+ <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
+ resets = <&k3_reset 135 0>;
+ clocks = <&k3_clks 61 0>;
+ assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+ assigned-clock-parents = <&k3_clks 61 2>;
+ assigned-clock-rates = <200000000>, <1200000000>;
+ ti,sci = <&dmsc>;
+ ti,sci-proc-id = <32>;
+ ti,sci-host-id = <10>;
+ bootph-all;
+ };
+
+ dm_tifs: dm-tifs {
+ compatible = "ti,j721e-dm-sci";
+ ti,host-id = <36>;
+ ti,secure-host;
+ mbox-names = "rx", "tx";
+ mboxes= <&secure_proxy_main 22>,
+ <&secure_proxy_main 23>;
+ bootph-all;
+ };
+};
+
+&dmsc {
+ mboxes= <&secure_proxy_main 0>,
+ <&secure_proxy_main 1>,
+ <&secure_proxy_main 0>;
+ mbox-names = "rx", "tx", "notify";
+ ti,host-id = <35>;
+ ti,secure-host;
+};
+
+&cbass_main {
+ sa3_secproxy: secproxy@44880000 {
+ compatible = "ti,am654-secure-proxy";
+ #mbox-cells = <1>;
+ reg = <0x00 0x44880000 0x00 0x20000>,
+ <0x00 0x44860000 0x00 0x20000>,
+ <0x00 0x43600000 0x00 0x10000>;
+ reg-names = "rt", "scfg", "target_data";
+ bootph-all;
+ };
+
+ sysctrler: sysctrler {
+ compatible = "ti,am654-system-controller";
+ mboxes= <&secure_proxy_main 1>,
+ <&secure_proxy_main 0>,
+ <&sa3_secproxy 0>;
+ mbox-names = "tx", "rx", "boot_notify";
+ bootph-all;
+ };
+};
+
+/* WKUP UART0 is used for DM firmware logs */
+&wkup_uart0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/k3-j784s4-binman.dtsi b/arch/arm/dts/k3-j784s4-binman.dtsi
index e4dd6e1..85bdd1f 100644
--- a/arch/arm/dts/k3-j784s4-binman.dtsi
+++ b/arch/arm/dts/k3-j784s4-binman.dtsi
@@ -157,6 +157,22 @@
};
};
+
+#include "k3-binman-capsule-r5.dtsi"
+
+// Capsule update GUIDs in string form. See j784s4_evm.h
+#define AM69_SK_TIBOOT3_IMAGE_GUID_STR "adf49ec5-61bb-4dbe-8b8d-39df4d7ebf46"
+
+&capsule_tiboot3 {
+ efi-capsule {
+ image-guid = AM69_SK_TIBOOT3_IMAGE_GUID_STR;
+
+ blob {
+ filename = "tiboot3-j784s4-hs-fs-evm.bin";
+ };
+ };
+};
+
#endif
#ifdef CONFIG_TARGET_J784S4_A72_EVM
@@ -170,6 +186,7 @@
blob-ext {
filename = "ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+ optional;
};
};
@@ -342,4 +359,23 @@
};
};
};
+
+#include "k3-binman-capsule.dtsi"
+
+// Capsule update GUIDs in string form. See j784s4_evm.h
+#define AM69_SK_SPL_IMAGE_GUID_STR "787f0059-63a1-461c-a18e-9d838345fe8e"
+#define AM69_SK_UBOOT_IMAGE_GUID_STR "9300505d-6ec5-4ff8-99e4-5459a04be617"
+
+&capsule_tispl {
+ efi-capsule {
+ image-guid = AM69_SK_SPL_IMAGE_GUID_STR;
+ };
+};
+
+&capsule_uboot {
+ efi-capsule {
+ image-guid = AM69_SK_UBOOT_IMAGE_GUID_STR;
+ };
+};
+
#endif
diff --git a/arch/arm/dts/omap3-igep.dtsi b/arch/arm/dts/omap3-igep.dtsi
deleted file mode 100644
index 2192026..0000000
--- a/arch/arm/dts/omap3-igep.dtsi
+++ /dev/null
@@ -1,247 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Common device tree for IGEP boards based on AM/DM37x
- *
- * Copyright (C) 2012 Javier Martinez Canillas <javier@dowhile0.org>
- * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
- */
-/dts-v1/;
-
-#include "omap36xx.dtsi"
-
-/ {
- memory@80000000 {
- device_type = "memory";
- reg = <0x80000000 0x20000000>; /* 512 MB */
- };
-
- chosen {
- stdout-path = &uart3;
- };
-
- sound {
- compatible = "ti,omap-twl4030";
- ti,model = "igep2";
- ti,mcbsp = <&mcbsp2>;
- };
-
- vdd33: regulator-vdd33 {
- compatible = "regulator-fixed";
- regulator-name = "vdd33";
- regulator-always-on;
- };
-
-};
-
-&omap3_pmx_core {
- gpmc_pins: pinmux_gpmc_pins {
- pinctrl-single,pins = <
- /* OneNAND seems to require PIN_INPUT on clock. */
- OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */
- >;
- };
-
- uart1_pins: pinmux_uart1_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */
- OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */
- >;
- };
-
- uart3_pins: pinmux_uart3_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */
- OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */
- >;
- };
-
- mcbsp2_pins: pinmux_mcbsp2_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */
- OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx.mcbsp2_clkx */
- OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr.mcbsp2.dr */
- OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx.mcbsp2_dx */
- >;
- };
-
- mmc1_pins: pinmux_mmc1_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
- OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
- OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
- OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
- OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
- OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
- >;
- };
-
- mmc2_pins: pinmux_mmc2_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
- OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
- OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
- OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
- OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
- OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
- >;
- };
-
- i2c1_pins: pinmux_i2c1_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
- OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
- >;
- };
-
- i2c3_pins: pinmux_i2c3_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */
- OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */
- >;
- };
-};
-
-&gpmc {
- pinctrl-names = "default";
- pinctrl-0 = <&gpmc_pins>;
-
- nand@0,0 {
- compatible = "ti,omap2-nand";
- reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
- interrupt-parent = <&gpmc>;
- interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
- <1 IRQ_TYPE_NONE>; /* termcount */
- linux,mtd-name = "micron,mt29c4g96maz";
- nand-bus-width = <16>;
- gpmc,device-width = <2>;
- ti,nand-ecc-opt = "bch8";
-
- gpmc,sync-clk-ps = <0>;
- gpmc,cs-on-ns = <0>;
- gpmc,cs-rd-off-ns = <44>;
- gpmc,cs-wr-off-ns = <44>;
- gpmc,adv-on-ns = <6>;
- gpmc,adv-rd-off-ns = <34>;
- gpmc,adv-wr-off-ns = <44>;
- gpmc,we-off-ns = <40>;
- gpmc,oe-off-ns = <54>;
- gpmc,access-ns = <64>;
- gpmc,rd-cycle-ns = <82>;
- gpmc,wr-cycle-ns = <82>;
- gpmc,wr-access-ns = <40>;
- gpmc,wr-data-mux-bus-ns = <0>;
-
- #address-cells = <1>;
- #size-cells = <1>;
-
- status = "okay";
- };
-
- onenand@0,0 {
- compatible = "ti,omap2-onenand";
- reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
-
- gpmc,sync-read;
- gpmc,sync-write;
- gpmc,burst-length = <16>;
- gpmc,burst-wrap;
- gpmc,burst-read;
- gpmc,burst-write;
- gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */
- gpmc,mux-add-data = <2>; /* GPMC_MUX_AD */
- gpmc,cs-on-ns = <0>;
- gpmc,cs-rd-off-ns = <96>;
- gpmc,cs-wr-off-ns = <96>;
- gpmc,adv-on-ns = <0>;
- gpmc,adv-rd-off-ns = <12>;
- gpmc,adv-wr-off-ns = <12>;
- gpmc,oe-on-ns = <18>;
- gpmc,oe-off-ns = <96>;
- gpmc,we-on-ns = <0>;
- gpmc,we-off-ns = <96>;
- gpmc,rd-cycle-ns = <114>;
- gpmc,wr-cycle-ns = <114>;
- gpmc,access-ns = <90>;
- gpmc,page-burst-access-ns = <12>;
- gpmc,bus-turnaround-ns = <0>;
- gpmc,cycle2cycle-delay-ns = <0>;
- gpmc,wait-monitoring-ns = <0>;
- gpmc,clk-activation-ns = <6>;
- gpmc,wr-data-mux-bus-ns = <30>;
- gpmc,wr-access-ns = <90>;
- gpmc,sync-clk-ps = <12000>;
-
- #address-cells = <1>;
- #size-cells = <1>;
-
- status = "disabled";
- };
-};
-
-&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins>;
- clock-frequency = <2600000>;
-
- twl: twl@48 {
- reg = <0x48>;
- interrupts = <7>; /* SYS_NIRQ cascaded to intc */
- interrupt-parent = <&intc>;
-
- twl_audio: audio {
- compatible = "ti,twl4030-audio";
- codec {
- };
- };
- };
-};
-
-#include "twl4030.dtsi"
-#include "twl4030_omap3.dtsi"
-
-&i2c3 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3_pins>;
-};
-
-&mcbsp2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mcbsp2_pins>;
- status = "okay";
-};
-
-&mmc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins>;
- vmmc-supply = <&vmmc1>;
- vmmc_aux-supply = <&vsim>;
- bus-width = <4>;
- cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>;
-};
-
-&mmc3 {
- status = "disabled";
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins>;
-};
-
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart3_pins>;
-};
-
-&twl_gpio {
- ti,use-leds;
-};
-
-&usb_otg_hs {
- interface-type = <0>;
- usb-phy = <&usb2_phy>;
- phys = <&usb2_phy>;
- phy-names = "usb2-phy";
- mode = <3>;
- power = <50>;
-};
diff --git a/arch/arm/dts/omap3-igep0020-common.dtsi b/arch/arm/dts/omap3-igep0020-common.dtsi
deleted file mode 100644
index 73d8f47..0000000
--- a/arch/arm/dts/omap3-igep0020-common.dtsi
+++ /dev/null
@@ -1,261 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Common Device Tree Source for IGEPv2
- *
- * Copyright (C) 2014 Javier Martinez Canillas <javier@dowhile0.org>
- * Copyright (C) 2014 Enric Balletbo i Serra <eballetbo@gmail.com>
- */
-
-#include "omap3-igep.dtsi"
-#include "omap-gpmc-smsc9221.dtsi"
-
-/ {
-
- leds {
- pinctrl-names = "default";
- pinctrl-0 = <&leds_pins>;
- compatible = "gpio-leds";
-
- boot {
- label = "omap3:green:boot";
- gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
-
- user0 {
- label = "omap3:red:user0";
- gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- user1 {
- label = "omap3:red:user1";
- gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- user2 {
- label = "omap3:green:user1";
- gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>;
- };
- };
-
- /* HS USB Port 1 Power */
- hsusb1_power: hsusb1_power_reg {
- compatible = "regulator-fixed";
- regulator-name = "hsusb1_vbus";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* GPIO LEDA */
- startup-delay-us = <70000>;
- };
-
- /* HS USB Host PHY on PORT 1 */
- hsusb1_phy: hsusb1_phy {
- compatible = "usb-nop-xceiv";
- reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */
- vcc-supply = <&hsusb1_power>;
- #phy-cells = <0>;
- };
-
- tfp410: encoder {
- compatible = "ti,tfp410";
- powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- tfp410_in: endpoint {
- remote-endpoint = <&dpi_out>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- tfp410_out: endpoint {
- remote-endpoint = <&dvi_connector_in>;
- };
- };
- };
- };
-
- dvi0: connector {
- compatible = "dvi-connector";
- label = "dvi";
-
- digital;
-
- ddc-i2c-bus = <&i2c3>;
-
- port {
- dvi_connector_in: endpoint {
- remote-endpoint = <&tfp410_out>;
- };
- };
- };
-};
-
-&omap3_pmx_core {
- pinctrl-names = "default";
- pinctrl-0 = <
- &tfp410_pins
- &dss_dpi_pins
- >;
-
- tfp410_pins: pinmux_tfp410_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */
- >;
- };
-
- dss_dpi_pins: pinmux_dss_dpi_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
- OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
- OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
- OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
- OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
- OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
- OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
- OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
- OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
- OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
- OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
- OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
- OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
- OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
- OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
- OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
- OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
- OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
- OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
- OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
- OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
- OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
- OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
- OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
- OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
- OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
- OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
- OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
- >;
- };
-
- uart2_pins: pinmux_uart2_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */
- OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/
- OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
- OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
- >;
- };
-
- smsc9221_pins: pinmux_smsc9221_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */
- >;
- };
-};
-
-&omap3_pmx_core2 {
- pinctrl-names = "default";
- pinctrl-0 = <
- &hsusbb1_pins
- >;
-
- hsusbb1_pins: pinmux_hsusbb1_pins {
- pinctrl-single,pins = <
- OMAP3630_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */
- OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */
- OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d8.hsusb1_dir */
- OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d9.hsusb1_nxt */
- OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d0.hsusb1_data0 */
- OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d1.hsusb1_data1 */
- OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d2.hsusb1_data2 */
- OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d3.hsusb1_data7 */
- OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d4.hsusb1_data4 */
- OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d5.hsusb1_data5 */
- OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d6.hsusb1_data6 */
- OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */
- >;
- };
-
- leds_pins: pinmux_leds_pins {
- pinctrl-single,pins = <
- OMAP3630_CORE2_IOPAD(0x25f4, PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */
- OMAP3630_CORE2_IOPAD(0x25f6, PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */
- OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */
- >;
- };
-
- mmc1_wp_pins: pinmux_mmc1_cd_pins {
- pinctrl-single,pins = <
- OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT | MUX_MODE4) /* etk_d15.gpio_29 */
- >;
- };
-};
-
-&i2c3 {
- clock-frequency = <100000>;
-
- /*
- * Display monitor features are burnt in the EEPROM
- * as EDID data.
- */
- eeprom@50 {
- compatible = "ti,eeprom";
- reg = <0x50>;
- };
-};
-
-&gpmc {
- ranges = <0 0 0x30000000 0x01000000>, /* CS0: 16MB for NAND */
- <5 0 0x2c000000 0x01000000>; /* CS5: 16MB for ethernet */
-
- ethernet@gpmc {
- pinctrl-names = "default";
- pinctrl-0 = <&smsc9221_pins>;
- reg = <5 0 0xff>;
- interrupt-parent = <&gpio6>;
- interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>;
-};
-
-&usbhshost {
- port1-mode = "ehci-phy";
-};
-
-&usbhsehci {
- phys = <&hsusb1_phy>;
-};
-
-&vpll2 {
- /* Needed for DSS */
- regulator-name = "vdds_dsi";
-};
-
-&dss {
- status = "okay";
-
- port {
- dpi_out: endpoint {
- remote-endpoint = <&tfp410_in>;
- data-lines = <24>;
- };
- };
-};
-
-&mmc1 {
- pinctrl-0 = <&mmc1_pins &mmc1_wp_pins>;
- wp-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; /* gpio_29 */
-};
diff --git a/arch/arm/dts/omap3-igep0020-u-boot.dtsi b/arch/arm/dts/omap3-igep0020-u-boot.dtsi
index 41beaf0..2c03701 100644
--- a/arch/arm/dts/omap3-igep0020-u-boot.dtsi
+++ b/arch/arm/dts/omap3-igep0020-u-boot.dtsi
@@ -5,20 +5,10 @@
* (C) Copyright 2017 Derald D. Woods <woods.technical@gmail.com>
*/
+#include "omap3-u-boot.dtsi"
+
/ {
chosen {
stdout-path = &uart3;
};
};
-
-&uart1 {
- reg-shift = <2>;
-};
-
-&uart2 {
- reg-shift = <2>;
-};
-
-&uart3 {
- reg-shift = <2>;
-};
diff --git a/arch/arm/dts/omap3-igep0020.dts b/arch/arm/dts/omap3-igep0020.dts
deleted file mode 100644
index cf3ac84..0000000
--- a/arch/arm/dts/omap3-igep0020.dts
+++ /dev/null
@@ -1,47 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Device Tree Source for IGEPv2 Rev. C (TI OMAP AM/DM37x)
- *
- * Copyright (C) 2012 Javier Martinez Canillas <javier@dowhile0.org>
- * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
- */
-
-#include "omap3-igep0020-common.dtsi"
-
-/ {
- model = "IGEPv2 Rev. C (TI OMAP AM/DM37x)";
- compatible = "isee,omap3-igep0020", "ti,omap36xx", "ti,omap3";
-
- vmmcsdio_fixed: fixedregulator-mmcsdio {
- compatible = "regulator-fixed";
- regulator-name = "vmmcsdio_fixed";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- mmc2_pwrseq: mmc2_pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>, /* gpio_139 - RESET_N_W */
- <&gpio5 10 GPIO_ACTIVE_LOW>; /* gpio_138 - WIFI_PDN */
- };
-};
-
-&omap3_pmx_core {
- lbee1usjyc_pins: pinmux_lbee1usjyc_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - RESET_N_W */
- OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 - WIFI_PDN */
- OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - RST_N_B */
- >;
- };
-};
-
-/* On board Wifi module */
-&mmc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_pins &lbee1usjyc_pins>;
- vmmc-supply = <&vmmcsdio_fixed>;
- mmc-pwrseq = <&mmc2_pwrseq>;
- bus-width = <4>;
- non-removable;
-};
diff --git a/arch/arm/dts/px30-engicam-common.dtsi b/arch/arm/dts/px30-engicam-common.dtsi
deleted file mode 100644
index 3429e12..0000000
--- a/arch/arm/dts/px30-engicam-common.dtsi
+++ /dev/null
@@ -1,129 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Engicam srl
- * Copyright (c) 2020 Amarula Solutions
- * Copyright (c) 2020 Amarula Solutions(India)
- */
-
-/ {
- aliases {
- mmc1 = &sdmmc;
- mmc2 = &sdio;
- };
-
- vcc5v0_sys: vcc5v0-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys"; /* +5V */
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- clocks = <&xin32k>;
- clock-names = "ext_clock";
- post-power-on-delay-ms = <80>;
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_enable_h>;
- };
-
- vcc3v3_btreg: vcc3v3-btreg {
- compatible = "regulator-gpio";
- enable-active-high;
- pinctrl-names = "default";
- pinctrl-0 = <&bt_enable_h>;
- regulator-name = "btreg-gpio-supply";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- states = <3300000 0x0>;
- };
-
- vcc3v3_rf_aux_mod: vcc3v3-rf-aux-mod {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_rf_aux_mod";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc5v0_sys>;
- };
-
- xin32k: xin32k {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- clock-output-names = "xin32k";
- };
-};
-
-&sdio {
- #address-cells = <1>;
- #size-cells = <0>;
- bus-width = <4>;
- clock-frequency = <50000000>;
- cap-sdio-irq;
- cap-sd-highspeed;
- keep-power-in-suspend;
- mmc-pwrseq = <&sdio_pwrseq>;
- non-removable;
- sd-uhs-sdr104;
- status = "okay";
-
- brcmf: wifi@1 {
- compatible = "brcm,bcm4329-fmac";
- reg = <1>;
- };
-};
-
-&gmac {
- clock_in_out = "output";
- phy-supply = <&vcc_3v3>; /* +3V3_SOM */
- snps,reset-active-low;
- snps,reset-delays-us = <0 50000 50000>;
- snps,reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
- status = "okay";
-};
-
-&pwm0 {
- status = "okay";
-};
-
-&sdmmc {
- cap-sd-highspeed;
- card-detect-delay = <800>;
- vmmc-supply = <&vcc_3v3>; /* +3V3_SOM */
- vqmmc-supply = <&vcc_3v3>;
- status = "okay";
-};
-
-&u2phy {
- status = "okay";
-
- u2phy_host: host-port {
- status = "okay";
- };
-
- u2phy_otg: otg-port {
- status = "okay";
- };
-};
-
-&uart2 {
- pinctrl-0 = <&uart2m1_xfer>;
- status = "okay";
-};
-
-&usb20_otg {
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
diff --git a/arch/arm/dts/px30-engicam-ctouch2.dtsi b/arch/arm/dts/px30-engicam-ctouch2.dtsi
deleted file mode 100644
index bf10a3d..0000000
--- a/arch/arm/dts/px30-engicam-ctouch2.dtsi
+++ /dev/null
@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Engicam srl
- * Copyright (c) 2020 Amarula Solutions
- * Copyright (c) 2020 Amarula Solutions(India)
- */
-
-#include "px30-engicam-common.dtsi"
-
-&pinctrl {
- bt {
- bt_enable_h: bt-enable-h {
- rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- sdio-pwrseq {
- wifi_enable_h: wifi-enable-h {
- rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&sdio_pwrseq {
- reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
-};
-
-&vcc3v3_btreg {
- enable-gpio = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>;
-};
diff --git a/arch/arm/dts/px30-engicam-edimm2.2.dtsi b/arch/arm/dts/px30-engicam-edimm2.2.dtsi
deleted file mode 100644
index 449b8eb..0000000
--- a/arch/arm/dts/px30-engicam-edimm2.2.dtsi
+++ /dev/null
@@ -1,66 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Engicam srl
- * Copyright (c) 2020 Amarula Solutions(India)
- */
-
-#include "px30-engicam-common.dtsi"
-
-/ {
- backlight: backlight {
- compatible = "pwm-backlight";
- pwms = <&pwm0 0 25000 0>;
- };
-
- panel {
- compatible = "yes-optoelectronics,ytc700tlag-05-201c";
- backlight = <&backlight>;
- data-mapping = "vesa-24";
- power-supply = <&vcc3v3_lcd>;
-
- port {
- panel_in_lvds: endpoint {
- remote-endpoint = <&lvds_out_panel>;
- };
- };
- };
-};
-
-&display_subsystem {
- status = "okay";
-};
-
-&dsi_dphy {
- status = "okay";
-};
-
-/* LVDS_B(secondary) */
-&lvds {
- status = "okay";
-
- ports {
- port@1 {
- reg = <1>;
-
- lvds_out_panel: endpoint {
- remote-endpoint = <&panel_in_lvds>;
- };
- };
- };
-};
-
-&vopb {
- status = "okay";
-};
-
-&vopb_mmu {
- status = "okay";
-};
-
-&vopl {
- status = "okay";
-};
-
-&vopl_mmu {
- status = "okay";
-};
diff --git a/arch/arm/dts/px30-engicam-px30-core-ctouch2-of10.dts b/arch/arm/dts/px30-engicam-px30-core-ctouch2-of10.dts
deleted file mode 100644
index 47aa305..0000000
--- a/arch/arm/dts/px30-engicam-px30-core-ctouch2-of10.dts
+++ /dev/null
@@ -1,77 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
- * Copyright (c) 2020 Engicam srl
- * Copyright (c) 2020 Amarula Solutions(India)
- */
-
-/dts-v1/;
-#include "px30.dtsi"
-#include "px30-engicam-ctouch2.dtsi"
-#include "px30-engicam-px30-core.dtsi"
-
-/ {
- model = "Engicam PX30.Core C.TOUCH 2.0 10.1\" Open Frame";
- compatible = "engicam,px30-core-ctouch2-of10", "engicam,px30-core",
- "rockchip,px30";
-
- backlight: backlight {
- compatible = "pwm-backlight";
- pwms = <&pwm0 0 25000 0>;
- };
-
- chosen {
- stdout-path = "serial2:115200n8";
- };
-
- panel {
- compatible = "ampire,am-1280800n3tzqw-t00h";
- backlight = <&backlight>;
- power-supply = <&vcc3v3_lcd>;
- data-mapping = "vesa-24";
-
- port {
- panel_in_lvds: endpoint {
- remote-endpoint = <&lvds_out_panel>;
- };
- };
- };
-};
-
-&display_subsystem {
- status = "okay";
-};
-
-&dsi_dphy {
- status = "okay";
-};
-
-&lvds {
- status = "okay";
-
- ports {
- port@1 {
- reg = <1>;
-
- lvds_out_panel: endpoint {
- remote-endpoint = <&panel_in_lvds>;
- };
- };
- };
-};
-
-&vopb {
- status = "okay";
-};
-
-&vopb_mmu {
- status = "okay";
-};
-
-&vopl {
- status = "okay";
-};
-
-&vopl_mmu {
- status = "okay";
-};
diff --git a/arch/arm/dts/px30-engicam-px30-core-ctouch2.dts b/arch/arm/dts/px30-engicam-px30-core-ctouch2.dts
deleted file mode 100644
index 5a0ecb8..0000000
--- a/arch/arm/dts/px30-engicam-px30-core-ctouch2.dts
+++ /dev/null
@@ -1,22 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
- * Copyright (c) 2020 Engicam srl
- * Copyright (c) 2020 Amarula Solutions
- * Copyright (c) 2020 Amarula Solutions(India)
- */
-
-/dts-v1/;
-#include "px30.dtsi"
-#include "px30-engicam-ctouch2.dtsi"
-#include "px30-engicam-px30-core.dtsi"
-
-/ {
- model = "Engicam PX30.Core C.TOUCH 2.0";
- compatible = "engicam,px30-core-ctouch2", "engicam,px30-core",
- "rockchip,px30";
-
- chosen {
- stdout-path = "serial2:115200n8";
- };
-};
diff --git a/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts b/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts
deleted file mode 100644
index d759478..0000000
--- a/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts
+++ /dev/null
@@ -1,43 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
- * Copyright (c) 2020 Engicam srl
- * Copyright (c) 2020 Amarula Solutions(India)
- */
-
-/dts-v1/;
-#include "px30.dtsi"
-#include "px30-engicam-edimm2.2.dtsi"
-#include "px30-engicam-px30-core.dtsi"
-
-/ {
- model = "Engicam PX30.Core EDIMM2.2 Starter Kit";
- compatible = "engicam,px30-core-edimm2.2", "engicam,px30-core",
- "rockchip,px30";
-
- chosen {
- stdout-path = "serial2:115200n8";
- };
-};
-
-&pinctrl {
- bt {
- bt_enable_h: bt-enable-h {
- rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- sdio-pwrseq {
- wifi_enable_h: wifi-enable-h {
- rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&sdio_pwrseq {
- reset-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>;
-};
-
-&vcc3v3_btreg {
- enable-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
-};
diff --git a/arch/arm/dts/px30-engicam-px30-core.dtsi b/arch/arm/dts/px30-engicam-px30-core.dtsi
deleted file mode 100644
index 7249871..0000000
--- a/arch/arm/dts/px30-engicam-px30-core.dtsi
+++ /dev/null
@@ -1,241 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
- * Copyright (c) 2020 Engicam srl
- * Copyright (c) 2020 Amarula Solutons
- * Copyright (c) 2020 Amarula Solutons(India)
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-
-/ {
- compatible = "engicam,px30-core", "rockchip,px30";
-
- aliases {
- mmc0 = &emmc;
- };
-};
-
-&cpu0 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu1 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu2 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu3 {
- cpu-supply = <&vdd_arm>;
-};
-
-&emmc {
- cap-mmc-highspeed;
- mmc-hs200-1_8v;
- non-removable;
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-
- rk809: pmic@20 {
- compatible = "rockchip,rk809";
- reg = <0x20>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int>;
- rockchip,system-power-controller;
- wakeup-source;
- #clock-cells = <1>;
- clock-output-names = "rk808-clkout1", "rk808-clkout2";
-
- vcc1-supply = <&vcc5v0_sys>;
- vcc2-supply = <&vcc5v0_sys>;
- vcc3-supply = <&vcc5v0_sys>;
- vcc4-supply = <&vcc5v0_sys>;
- vcc5-supply = <&vcc3v3_sys>;
- vcc6-supply = <&vcc3v3_sys>;
- vcc7-supply = <&vcc3v3_sys>;
- vcc8-supply = <&vcc3v3_sys>;
- vcc9-supply = <&vcc5v0_sys>;
-
- regulators {
- vdd_log: DCDC_REG1 {
- regulator-name = "vdd_log";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <950000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <950000>;
- };
- };
-
- vdd_arm: DCDC_REG2 {
- regulator-name = "vdd_arm";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <950000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <950000>;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_3v3: DCDC_REG4 {
- regulator-name = "vcc_3v3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc3v3_sys: DCDC_REG5 {
- regulator-name = "vcc3v3_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc_1v0: LDO_REG1 {
- regulator-name = "vcc_1v0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1000000>;
- };
- };
-
- vcc_1v8: LDO_REG2 {
- regulator-name = "vcc_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vdd_1v0: LDO_REG3 {
- regulator-name = "vdd_1v0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1000000>;
- };
- };
-
- vcc3v0_pmu: LDO_REG4 {
- regulator-name = "vcc3v0_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
-
- };
- };
-
- vccio_sd: LDO_REG5 {
- regulator-name = "vccio_sd";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc3v3_lcd: SWITCH_REG1 {
- regulator-boot-on;
- regulator-name = "vcc3v3_lcd";
- };
-
- vcc5v0_host: SWITCH_REG2 {
- regulator-name = "vcc5v0_host";
- regulator-always-on;
- regulator-boot-on;
- };
- };
- };
-};
-
-&io_domains {
- vccio1-supply = <&vcc_3v3>;
- vccio2-supply = <&vcc_3v3>;
- vccio3-supply = <&vcc_3v3>;
- vccio4-supply = <&vcc_3v3>;
- vccio5-supply = <&vcc_3v3>;
- vccio6-supply = <&vcc_1v8>;
- status = "okay";
-};
-
-&pinctrl {
- pmic {
- pmic_int: pmic_int {
- rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-};
-
-&pmu_io_domains {
- pmuio1-supply = <&vcc_3v3>;
- pmuio2-supply = <&vcc_3v3>;
- status = "okay";
-};
-
-&tsadc {
- rockchip,hw-tshut-mode = <1>;
- rockchip,hw-tshut-polarity = <1>;
- status = "okay";
-};
diff --git a/arch/arm/dts/px30-evb.dts b/arch/arm/dts/px30-evb.dts
deleted file mode 100644
index 848bc39..0000000
--- a/arch/arm/dts/px30-evb.dts
+++ /dev/null
@@ -1,634 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
- */
-
-/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include "px30.dtsi"
-
-/ {
- model = "Rockchip PX30 EVB";
- compatible = "rockchip,px30-evb", "rockchip,px30";
-
- aliases {
- mmc0 = &sdmmc;
- mmc1 = &sdio;
- mmc2 = &emmc;
- };
-
- chosen {
- stdout-path = "serial5:115200n8";
- };
-
- adc-keys {
- compatible = "adc-keys";
- io-channels = <&saradc 2>;
- io-channel-names = "buttons";
- keyup-threshold-microvolt = <1800000>;
- poll-interval = <100>;
-
- esc-key {
- label = "esc";
- linux,code = <KEY_ESC>;
- press-threshold-microvolt = <1310000>;
- };
-
- home-key {
- label = "home";
- linux,code = <KEY_HOME>;
- press-threshold-microvolt = <624000>;
- };
-
- menu-key {
- label = "menu";
- linux,code = <KEY_MENU>;
- press-threshold-microvolt = <987000>;
- };
-
- vol-down-key {
- label = "volume down";
- linux,code = <KEY_VOLUMEDOWN>;
- press-threshold-microvolt = <300000>;
- };
-
- vol-up-key {
- label = "volume up";
- linux,code = <KEY_VOLUMEUP>;
- press-threshold-microvolt = <17000>;
- };
- };
-
- backlight: backlight {
- compatible = "pwm-backlight";
- pwms = <&pwm1 0 25000 0>;
- power-supply = <&vcc3v3_lcd>;
- };
-
- emmc_pwrseq: emmc-pwrseq {
- compatible = "mmc-pwrseq-emmc";
- pinctrl-0 = <&emmc_reset>;
- pinctrl-names = "default";
- reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>;
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_enable_h>;
-
- /*
- * On the module itself this is one of these (depending
- * on the actual card populated):
- * - SDIO_RESET_L_WL_REG_ON
- * - PDN (power down when low)
- */
- reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */
- };
-
- vcc5v0_sys: vccsys {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-};
-
-&cpu0 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu1 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu2 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu3 {
- cpu-supply = <&vdd_arm>;
-};
-
-&csi_dphy {
- status = "okay";
-};
-
-&display_subsystem {
- status = "okay";
-};
-
-&dsi {
- status = "okay";
-
- ports {
- mipi_out: port@1 {
- reg = <1>;
-
- mipi_out_panel: endpoint {
- remote-endpoint = <&mipi_in_panel>;
- };
- };
- };
-
- panel@0 {
- compatible = "xinpeng,xpp055c272";
- reg = <0>;
- backlight = <&backlight>;
- iovcc-supply = <&vcc_1v8>;
- vci-supply = <&vcc3v3_lcd>;
-
- port {
- mipi_in_panel: endpoint {
- remote-endpoint = <&mipi_out_panel>;
- };
- };
- };
-};
-
-&dsi_dphy {
- status = "okay";
-};
-
-&emmc {
- cap-mmc-highspeed;
- mmc-hs200-1_8v;
- non-removable;
- mmc-pwrseq = <&emmc_pwrseq>;
- vmmc-supply = <&vcc_3v0>;
- vqmmc-supply = <&vccio_flash>;
- status = "okay";
-};
-
-&gmac {
- clock_in_out = "output";
- phy-supply = <&vcc_rmii>;
- snps,reset-gpio = <&gpio2 13 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 50000 50000>;
- status = "okay";
-};
-
-&gpu {
- mali-supply = <&vdd_log>;
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-
- rk809: pmic@20 {
- compatible = "rockchip,rk809";
- reg = <0x20>;
- interrupt-parent = <&gpio0>;
- interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int>;
- rockchip,system-power-controller;
- wakeup-source;
- #clock-cells = <0>;
- clock-output-names = "xin32k";
-
- vcc1-supply = <&vcc5v0_sys>;
- vcc2-supply = <&vcc5v0_sys>;
- vcc3-supply = <&vcc5v0_sys>;
- vcc4-supply = <&vcc5v0_sys>;
- vcc5-supply = <&vcc3v3_sys>;
- vcc6-supply = <&vcc3v3_sys>;
- vcc7-supply = <&vcc3v3_sys>;
- vcc8-supply = <&vcc3v3_sys>;
- vcc9-supply = <&vcc5v0_sys>;
-
- regulators {
- vdd_log: DCDC_REG1 {
- regulator-name = "vdd_log";
- regulator-min-microvolt = <950000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <950000>;
- };
- };
-
- vdd_arm: DCDC_REG2 {
- regulator-name = "vdd_arm";
- regulator-min-microvolt = <950000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <950000>;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_3v0: vcc_rmii: DCDC_REG4 {
- regulator-name = "vcc_3v0";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3000000>;
- };
- };
-
- vcc3v3_sys: DCDC_REG5 {
- regulator-name = "vcc3v3_sys";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc_1v0: LDO_REG1 {
- regulator-name = "vcc_1v0";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1000000>;
- };
- };
-
- vcc_1v8: vccio_flash: vccio_sdio: LDO_REG2 {
- regulator-name = "vcc_1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vdd_1v0: LDO_REG3 {
- regulator-name = "vdd_1v0";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1000000>;
- };
- };
-
- vcc3v0_pmu: LDO_REG4 {
- regulator-name = "vcc3v0_pmu";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3000000>;
- };
- };
-
- vccio_sd: LDO_REG5 {
- regulator-name = "vccio_sd";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc_sd: LDO_REG6 {
- regulator-name = "vcc_sd";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc2v8_dvp: LDO_REG7 {
- regulator-name = "vcc2v8_dvp";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <2800000>;
- };
- };
-
- vcc1v8_dvp: LDO_REG8 {
- regulator-name = "vcc1v8_dvp";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc1v5_dvp: LDO_REG9 {
- regulator-name = "vcc1v5_dvp";
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <1500000>;
- };
- };
-
- vcc3v3_lcd: SWITCH_REG1 {
- regulator-name = "vcc3v3_lcd";
- regulator-boot-on;
- };
-
- vcc5v0_host: SWITCH_REG2 {
- regulator-name = "vcc5v0_host";
- regulator-always-on;
- regulator-boot-on;
- };
- };
- };
-};
-
-&i2c1 {
- status = "okay";
-
- sensor@d {
- compatible = "asahi-kasei,ak8963";
- reg = <0x0d>;
- gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
- vdd-supply = <&vcc3v0_pmu>;
- mount-matrix = "1", /* x0 */
- "0", /* y0 */
- "0", /* z0 */
- "0", /* x1 */
- "1", /* y1 */
- "0", /* z1 */
- "0", /* x2 */
- "0", /* y2 */
- "1"; /* z2 */
- };
-
- touchscreen@14 {
- compatible = "goodix,gt1151";
- reg = <0x14>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PA5 IRQ_TYPE_LEVEL_LOW>;
- irq-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
- reset-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
- VDDIO-supply = <&vcc3v3_lcd>;
- };
-
- sensor@4c {
- compatible = "fsl,mma7660";
- reg = <0x4c>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PB7 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-&i2c2 {
- status = "okay";
-
- clock-frequency = <100000>;
-
- /* These are relatively safe rise/fall times; TODO: measure */
- i2c-scl-falling-time-ns = <50>;
- i2c-scl-rising-time-ns = <300>;
-
- ov5695: ov5695@36 {
- compatible = "ovti,ov5695";
- reg = <0x36>;
- avdd-supply = <&vcc2v8_dvp>;
- clocks = <&cru SCLK_CIF_OUT>;
- clock-names = "xvclk";
- dvdd-supply = <&vcc1v5_dvp>;
- dovdd-supply = <&vcc1v8_dvp>;
- pinctrl-names = "default";
- pinctrl-0 = <&cif_clkout_m0>;
- reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
-
- port {
- ucam_out: endpoint {
- remote-endpoint = <&mipi_in_ucam>;
- data-lanes = <1 2>;
- };
- };
- };
-};
-
-&i2s1_2ch {
- status = "okay";
-};
-
-&io_domains {
- status = "okay";
-
- vccio1-supply = <&vccio_sdio>;
- vccio2-supply = <&vccio_sd>;
- vccio3-supply = <&vcc_3v0>;
- vccio4-supply = <&vcc3v0_pmu>;
- vccio5-supply = <&vcc_3v0>;
- vccio6-supply = <&vccio_flash>;
-};
-
-&isp {
- status = "okay";
-
- ports {
- port@0 {
- mipi_in_ucam: endpoint@0 {
- reg = <0>;
- data-lanes = <1 2>;
- remote-endpoint = <&ucam_out>;
- };
- };
- };
-};
-
-&isp_mmu {
- status = "okay";
-};
-
-&pinctrl {
- headphone {
- hp_det: hp-det {
- rockchip,pins =
- <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
- };
- };
-
- emmc {
- emmc_reset: emmc-reset {
- rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pmic {
- pmic_int: pmic_int {
- rockchip,pins =
- <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
- };
-
- soc_slppin_gpio: soc_slppin_gpio {
- rockchip,pins =
- <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>;
- };
-
- soc_slppin_slp: soc_slppin_slp {
- rockchip,pins =
- <0 RK_PA4 1 &pcfg_pull_none>;
- };
-
- soc_slppin_rst: soc_slppin_rst {
- rockchip,pins =
- <0 RK_PA4 2 &pcfg_pull_none>;
- };
- };
-
- sdio-pwrseq {
- wifi_enable_h: wifi-enable-h {
- rockchip,pins =
- <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&pmu_io_domains {
- status = "okay";
-
- pmuio1-supply = <&vcc3v0_pmu>;
- pmuio2-supply = <&vcc3v0_pmu>;
-};
-
-&pwm1 {
- status = "okay";
-};
-
-&saradc {
- vref-supply = <&vcc_1v8>;
- status = "okay";
-};
-
-&sdmmc {
- cap-mmc-highspeed;
- cap-sd-highspeed;
- card-detect-delay = <800>;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc_sd>;
- vqmmc-supply = <&vccio_sd>;
- status = "okay";
-};
-
-&sdio {
- cap-sd-highspeed;
- keep-power-in-suspend;
- non-removable;
- mmc-pwrseq = <&sdio_pwrseq>;
- sd-uhs-sdr104;
- status = "okay";
-};
-
-&tsadc {
- rockchip,hw-tshut-mode = <1>;
- rockchip,hw-tshut-polarity = <1>;
- status = "okay";
-};
-
-&u2phy {
- status = "okay";
-
- u2phy_host: host-port {
- status = "okay";
- };
-
- u2phy_otg: otg-port {
- status = "okay";
- };
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_xfer &uart1_cts>;
- status = "okay";
-};
-
-&uart5 {
- status = "okay";
-};
-
-&usb20_otg {
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&vopb {
- status = "okay";
-};
-
-&vopb_mmu {
- status = "okay";
-};
-
-&vopl {
- status = "okay";
-};
-
-&vopl_mmu {
- status = "okay";
-};
diff --git a/arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi b/arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi
index e04766a..29ea276 100644
--- a/arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi
+++ b/arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi
@@ -15,14 +15,6 @@
};
};
-&binman {
- simple-bin {
- fit {
- offset = <((CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - 64) * 512)>;
- };
- };
-};
-
&emmc_clk {
bootph-all;
};
diff --git a/arch/arm/dts/px30-ringneck-haikou.dts b/arch/arm/dts/px30-ringneck-haikou.dts
deleted file mode 100644
index 08a3ad3..0000000
--- a/arch/arm/dts/px30-ringneck-haikou.dts
+++ /dev/null
@@ -1,232 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2022 Theobroma Systems Design und Consulting GmbH
- */
-
-/dts-v1/;
-#include "px30-ringneck.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "Theobroma Systems PX30-uQ7 SoM on Haikou devkit";
- compatible = "tsd,px30-ringneck-haikou", "rockchip,px30";
-
- aliases {
- mmc2 = &sdmmc;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&haikou_keys_pin>;
- pinctrl-names = "default";
-
- button-batlow-n {
- label = "BATLOW#";
- linux,code = <KEY_BATTERY>;
- gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;
- };
-
- button-slp-btn-n {
- label = "SLP_BTN#";
- linux,code = <KEY_SLEEP>;
- gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_LOW>;
- };
-
- button-wake-n {
- label = "WAKE#";
- linux,code = <KEY_WAKEUP>;
- gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>;
- wakeup-source;
- };
-
- switch-lid-btn-n {
- label = "LID_BTN#";
- linux,code = <SW_LID>;
- linux,input-type = <EV_SW>;
- gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>;
- };
- };
-
- leds {
- pinctrl-0 = <&module_led_pin>, <&sd_card_led_pin>;
-
- sd_card_led: led-1 {
- gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "mmc2";
- function = LED_FUNCTION_SD;
- color = <LED_COLOR_ID_BLUE>;
- };
- };
-
- i2s0-sound {
- compatible = "simple-audio-card";
- simple-audio-card,format = "i2s";
- simple-audio-card,name = "Haikou,I2S-codec";
- simple-audio-card,mclk-fs = <512>;
-
- simple-audio-card,codec {
- clocks = <&sgtl5000_clk>;
- sound-dai = <&sgtl5000>;
- };
-
- simple-audio-card,cpu {
- bitclock-master;
- frame-master;
- sound-dai = <&i2s0_8ch>;
- };
- };
-
- sgtl5000_clk: sgtl5000-oscillator {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24576000>;
- };
-
- dc_12v: dc-12v-regulator {
- compatible = "regulator-fixed";
- regulator-name = "dc_12v";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-
- vcc3v3_baseboard: vcc3v3-baseboard-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_baseboard";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&dc_12v>;
- };
-
- vcc5v0_baseboard: vcc5v0-baseboard-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_baseboard";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&dc_12v>;
- };
-
- vdda_codec: vdda-codec-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vdda_codec";
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc5v0_baseboard>;
- };
-
- vddd_codec: vddd-codec-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vddd_codec";
- regulator-boot-on;
- regulator-min-microvolt = <1600000>;
- regulator-max-microvolt = <1600000>;
- vin-supply = <&vcc5v0_baseboard>;
- };
-};
-
-&i2c2 {
- status = "okay";
- clock-frequency = <400000>;
-
- sgtl5000: codec@a {
- compatible = "fsl,sgtl5000";
- reg = <0x0a>;
- clocks = <&sgtl5000_clk>;
- #sound-dai-cells = <0>;
- VDDA-supply = <&vdda_codec>;
- VDDIO-supply = <&vcc3v3_baseboard>;
- VDDD-supply = <&vddd_codec>;
- };
-};
-
-&i2c3 {
- eeprom@50 {
- reg = <0x50>;
- compatible = "atmel,24c01";
- pagesize = <8>;
- size = <128>;
- vcc-supply = <&vcc3v3_baseboard>;
- };
-};
-
-&i2s0_8ch {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&pinctrl {
- haikou {
- haikou_keys_pin: haikou-keys-pin {
- rockchip,pins =
- /* WAKE# */
- <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>,
- /* SLP_BTN# */
- <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>,
- /* LID_BTN */
- <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
- /* BATLOW# */
- <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>,
- /* BIOS_DISABLE# */
- <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- leds {
- sd_card_led_pin: sd-card-led-pin {
- rockchip,pins =
- <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&pwm0 {
- status = "okay";
-};
-
-&sdmmc {
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>;
- disable-wp;
- vmmc-supply = <&vcc3v3_baseboard>;
- status = "okay";
-};
-
-&spi1 {
- status = "okay";
-};
-
-&u2phy_otg {
- status = "okay";
-};
-
-&uart0 {
- status = "okay";
-};
-
-&uart5 {
- pinctrl-0 = <&uart5_xfer>;
- status = "okay";
-};
-
-&usb20_otg {
- status = "okay";
-};
diff --git a/arch/arm/dts/px30-ringneck.dtsi b/arch/arm/dts/px30-ringneck.dtsi
deleted file mode 100644
index 1239775..0000000
--- a/arch/arm/dts/px30-ringneck.dtsi
+++ /dev/null
@@ -1,382 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2022 Theobroma Systems Design und Consulting GmbH
- */
-
-/dts-v1/;
-#include "px30.dtsi"
-#include <dt-bindings/leds/common.h>
-
-/ {
- aliases {
- mmc0 = &emmc;
- mmc1 = &sdio;
- rtc0 = &rtc_twi;
- rtc1 = &rk809;
- };
-
- emmc_pwrseq: emmc-pwrseq {
- compatible = "mmc-pwrseq-emmc";
- pinctrl-0 = <&emmc_reset>;
- pinctrl-names = "default";
- reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>;
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&module_led_pin>;
- status = "okay";
-
- module_led: led-0 {
- gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>;
- function = LED_FUNCTION_HEARTBEAT;
- linux,default-trigger = "heartbeat";
- color = <LED_COLOR_ID_AMBER>;
- };
- };
-
- vcc5v0_sys: vccsys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-};
-
-&cpu0 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu1 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu2 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu3 {
- cpu-supply = <&vdd_arm>;
-};
-
-&emmc {
- bus-width = <8>;
- cap-mmc-highspeed;
- mmc-hs200-1_8v;
- supports-emmc;
- mmc-pwrseq = <&emmc_pwrseq>;
- non-removable;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&vcc_emmc>;
-
- status = "okay";
-};
-
-/* On-module TI DP83825I PHY but no connector, enable in carrierboard */
-&gmac {
- snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 50000 50000>;
- phy-supply = <&vcc_3v3>;
- clock_in_out = "output";
-};
-
-&gpio2 {
- /*
- * The Qseven BIOS_DISABLE signal on the PX30-µQ7 keeps the on-module
- * eMMC powered-down initially (in fact it keeps the reset signal
- * asserted). BIOS_DISABLE_OVERRIDE pin allows to re-enable eMMC after
- * the SPL has been booted from SD Card.
- */
- bios-disable-override-hog {
- gpios = <RK_PB5 GPIO_ACTIVE_LOW>;
- output-high;
- line-name = "bios_disable_override";
- gpio-hog;
- };
-
- /*
- * The BIOS_DISABLE hog is a feedback pin for the actual status of the
- * signal, ignoring the BIOS_DISABLE_OVERRIDE logic. This usually
- * represents the state of a switch on the baseboard.
- */
- bios-disable-n-hog {
- gpios = <RK_PC2 GPIO_ACTIVE_LOW>;
- line-name = "bios_disable";
- input;
- gpio-hog;
- };
-};
-
-&gpu {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-
- rk809: pmic@20 {
- compatible = "rockchip,rk809";
- reg = <0x20>;
- interrupt-parent = <&gpio0>;
- interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-0 = <&pmic_int>;
- pinctrl-names = "default";
- #clock-cells = <0>;
- clock-output-names = "xin32k";
- rockchip,system-power-controller;
- wakeup-source;
-
- vcc1-supply = <&vcc5v0_sys>;
- vcc2-supply = <&vcc5v0_sys>;
- vcc3-supply = <&vcc5v0_sys>;
- vcc4-supply = <&vcc5v0_sys>;
- vcc5-supply = <&vcc_3v3>;
- vcc6-supply = <&vcc_3v3>;
- vcc7-supply = <&vcc_3v3>;
- vcc9-supply = <&vcc5v0_sys>;
-
- regulators {
- vdd_log: DCDC_REG1 {
- regulator-name = "vdd_log";
- regulator-min-microvolt = <950000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <950000>;
- };
- };
-
- vdd_arm: DCDC_REG2 {
- regulator-name = "vdd_arm";
- regulator-min-microvolt = <950000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <950000>;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_3v0_1v8: vcc_emmc: DCDC_REG4 {
- regulator-name = "vcc_3v0_1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3000000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3000000>;
- };
- };
-
- vcc_3v3: DCDC_REG5 {
- regulator-name = "vcc_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc_1v8: LDO_REG2 {
- regulator-name = "vcc_1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc_1v0: LDO_REG3 {
- regulator-name = "vcc_1v0";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1000000>;
- };
- };
-
- vccio_sd: LDO_REG5 {
- regulator-name = "vccio_sd";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc_lcd: LDO_REG7 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-name = "vcc_lcd";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <1000000>;
- };
- };
-
- vcc_1v8_lcd: LDO_REG8 {
- regulator-name = "vcc_1v8_lcd";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcca_1v8: LDO_REG9 {
- regulator-name = "vcca_1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
- };
- };
-};
-
-&i2c1 {
- status = "okay";
-
- /* SE05x is limited to Fast Mode */
- clock-frequency = <400000>;
-
- fan: fan@18 {
- compatible = "ti,amc6821";
- reg = <0x18>;
- #cooling-cells = <2>;
- };
-
- rtc_twi: rtc@6f {
- compatible = "isil,isl1208";
- reg = <0x6f>;
- };
-};
-
-&i2c3 {
- status = "okay";
-};
-
-&i2s0_8ch {
- rockchip,trcm-sync-tx-only;
-
- pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_lrcktx
- &i2s0_8ch_sdo0 &i2s0_8ch_sdi0>;
-};
-
-&io_domains {
- vccio1-supply = <&vcc_3v3>;
- vccio2-supply = <&vccio_sd>;
- vccio3-supply = <&vcc_3v3>;
- vccio4-supply = <&vcc_3v3>;
- vccio5-supply = <&vcc_3v3>;
- vccio6-supply = <&vcc_emmc>;
- vccio-oscgpi-supply = <&vcc_3v3>;
-
- status = "okay";
-};
-
-&pinctrl {
- emmc {
- emmc_reset: emmc-reset {
- rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- leds {
- module_led_pin: module-led-pin {
- rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pmic {
- pmic_int: pmic-int {
- rockchip,pins =
- <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-};
-
-&saradc {
- vref-supply = <&vcc_1v8>;
- status = "okay";
-};
-
-&sdmmc {
- vqmmc-supply = <&vccio_sd>;
-};
-
-&tsadc {
- status = "okay";
-};
-
-&u2phy {
- status = "okay";
-};
-
-&u2phy_host {
- status = "okay";
-};
-
-/* Mule UCAN */
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&wdt {
- status = "okay";
-};
diff --git a/arch/arm/dts/px30-u-boot.dtsi b/arch/arm/dts/px30-u-boot.dtsi
index 046da02..59fa9f4 100644
--- a/arch/arm/dts/px30-u-boot.dtsi
+++ b/arch/arm/dts/px30-u-boot.dtsi
@@ -33,11 +33,27 @@
bootph-all;
};
+&uart2m0_xfer {
+ bootph-all;
+};
+
&uart5 {
clock-frequency = <24000000>;
bootph-all;
};
+&uart5_cts {
+ bootph-all;
+};
+
+&uart5_rts {
+ bootph-all;
+};
+
+&uart5_xfer {
+ bootph-all;
+};
+
&sdmmc {
bootph-all;
diff --git a/arch/arm/dts/qcom-ipq4019.dtsi b/arch/arm/dts/qcom-ipq4019.dtsi
deleted file mode 100644
index f9489e4..0000000
--- a/arch/arm/dts/qcom-ipq4019.dtsi
+++ /dev/null
@@ -1,202 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2019 Sartura Ltd.
- *
- * Author: Robert Marko <robert.marko@sartura.hr>
- */
-
- /dts-v1/;
-
-#include "skeleton.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/clock/qcom,ipq4019-gcc.h>
-#include <dt-bindings/reset/qcom,ipq4019-reset.h>
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- model = "Qualcomm Technologies, Inc. IPQ4019";
- compatible = "qcom,ipq4019";
-
- aliases {
- serial0 = &blsp1_uart1;
- spi0 = &blsp1_spi1;
- };
-
- reserved-memory {
- #address-cells = <0x1>;
- #size-cells = <0x1>;
- ranges;
-
- smem_mem: smem_region: smem@87e00000 {
- reg = <0x87e00000 0x080000>;
- no-map;
- };
-
- tz@87e80000 {
- reg = <0x87e80000 0x180000>;
- no-map;
- };
- };
-
- smem {
- compatible = "qcom,smem";
- memory-region = <&smem_mem>;
- };
-
- soc: soc {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- compatible = "simple-bus";
-
- gcc: clock-controller@1800000 {
- compatible = "qcom,gcc-ipq4019";
- reg = <0x1800000 0x60000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- bootph-all;
- };
-
- rng: rng@22000 {
- compatible = "qcom,prng";
- reg = <0x22000 0x140>;
- clocks = <&gcc GCC_PRNG_AHB_CLK>;
- status = "disabled";
- };
-
- soc_gpios: pinctrl@1000000 {
- compatible = "qcom,ipq4019-pinctrl";
- reg = <0x1000000 0x300000>;
- gpio-controller;
- gpio-count = <100>;
- gpio-bank-name="soc";
- #gpio-cells = <2>;
- bootph-all;
- };
-
- blsp1_uart1: serial@78af000 {
- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
- reg = <0x78af000 0x200>;
- clock = <&gcc GCC_BLSP1_UART1_APPS_CLK>;
- bit-rate = <0xFF>;
- status = "disabled";
- bootph-all;
- };
-
- blsp1_spi1: spi@78b5000 {
- compatible = "qcom,spi-qup-v2.2.1";
- reg = <0x78b5000 0x600>;
- clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- bootph-all;
- };
-
- mdio: mdio@90000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "qcom,ipq4019-mdio";
- reg = <0x90000 0x64>;
- status = "disabled";
-
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
-
- ethphy1: ethernet-phy@1 {
- reg = <1>;
- };
-
- ethphy2: ethernet-phy@2 {
- reg = <2>;
- };
-
- ethphy3: ethernet-phy@3 {
- reg = <3>;
- };
-
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
- };
-
- usb3_ss_phy: ssphy@9a000 {
- compatible = "qcom,usb-ss-ipq4019-phy";
- #phy-cells = <0>;
- reg = <0x9a000 0x800>;
- reg-names = "phy_base";
- resets = <&gcc USB3_UNIPHY_PHY_ARES>;
- reset-names = "por_rst";
- status = "disabled";
- };
-
- usb3_hs_phy: hsphy@a6000 {
- compatible = "qcom,usb-hs-ipq4019-phy";
- #phy-cells = <0>;
- reg = <0xa6000 0x40>;
- reg-names = "phy_base";
- resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
- reset-names = "por_rst", "srif_rst";
- status = "disabled";
- };
-
- usb3: usb3@8af8800 {
- compatible = "qcom,dwc3";
- reg = <0x8af8800 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
- clocks = <&gcc GCC_USB3_MASTER_CLK>,
- <&gcc GCC_USB3_SLEEP_CLK>,
- <&gcc GCC_USB3_MOCK_UTMI_CLK>;
- clock-names = "master", "sleep", "mock_utmi";
- ranges;
- status = "disabled";
-
- dwc3@8a00000 {
- compatible = "snps,dwc3";
- reg = <0x8a00000 0xf8000>;
- phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
- phy-names = "usb2-phy", "usb3-phy";
- dr_mode = "host";
- maximum-speed = "super-speed";
- snps,dis_u2_susphy_quirk;
- };
- };
-
- usb2_hs_phy: hsphy@a8000 {
- compatible = "qcom,usb-hs-ipq4019-phy";
- #phy-cells = <0>;
- reg = <0xa8000 0x40>;
- reg-names = "phy_base";
- resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
- reset-names = "por_rst", "srif_rst";
- status = "disabled";
- };
-
- usb2: usb2@60f8800 {
- compatible = "qcom,dwc3";
- reg = <0x60f8800 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
- clocks = <&gcc GCC_USB2_MASTER_CLK>,
- <&gcc GCC_USB2_SLEEP_CLK>,
- <&gcc GCC_USB2_MOCK_UTMI_CLK>;
- clock-names = "master", "sleep", "mock_utmi";
- ranges;
- status = "disabled";
-
- dwc3@6000000 {
- compatible = "snps,dwc3";
- reg = <0x6000000 0xf8000>;
- phys = <&usb2_hs_phy>;
- phy-names = "usb2-phy";
- dr_mode = "host";
- maximum-speed = "high-speed";
- snps,dis_u2_susphy_quirk;
- };
- };
- };
-};
diff --git a/arch/arm/dts/r8a779h0-gray-hawk-cpu.dtsi b/arch/arm/dts/r8a779h0-gray-hawk-cpu.dtsi
deleted file mode 100644
index c8a4621..0000000
--- a/arch/arm/dts/r8a779h0-gray-hawk-cpu.dtsi
+++ /dev/null
@@ -1,166 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-/*
- * Device Tree Source for the Gray Hawk CPU board
- *
- * Copyright (C) 2023 Renesas Electronics Corp.
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-#include "r8a779h0.dtsi"
-
-/ {
- model = "Renesas Gray Hawk CPU board";
- compatible = "renesas,grayhawk-cpu", "renesas,r8a779h0";
-
- aliases {
- ethernet0 = &avb0;
- serial0 = &hscif0;
- };
-
- chosen {
- bootargs = "ignore_loglevel";
- stdout-path = "serial0:921600n8";
- };
-
- memory@48000000 {
- device_type = "memory";
- /* first 128MB is reserved for secure area. */
- reg = <0x0 0x48000000 0x0 0x78000000>;
- };
-
- memory@480000000 {
- device_type = "memory";
- reg = <0x4 0x80000000 0x1 0x80000000>;
- };
-
- reg_1p8v: regulator-1p8v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- reg_3p3v: regulator-3p3v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-};
-
-&avb0 {
- pinctrl-0 = <&avb0_pins>;
- pinctrl-names = "default";
- phy-handle = <&phy0>;
- tx-internal-delay-ps = <2000>;
- status = "okay";
-
- phy0: ethernet-phy@0 {
- compatible = "ethernet-phy-id0022.1622",
- "ethernet-phy-ieee802.3-c22";
- rxc-skew-ps = <1500>;
- reg = <0>;
- interrupt-parent = <&gpio7>;
- interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
- reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>;
- };
-};
-
-&extal_clk {
- clock-frequency = <16666666>;
-};
-
-&extalr_clk {
- clock-frequency = <32768>;
-};
-
-&hscif0 {
- uart-has-rtscts;
- status = "okay";
-};
-
-&i2c0 {
- pinctrl-0 = <&i2c0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
- clock-frequency = <400000>;
-
- eeprom@50 {
- compatible = "rohm,br24g01", "atmel,24c01";
- label = "cpu-board";
- reg = <0x50>;
- pagesize = <8>;
- };
-};
-
-&mmc0 {
- pinctrl-0 = <&mmc_pins>;
- pinctrl-1 = <&mmc_pins>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <®_3p3v>;
- vqmmc-supply = <®_1p8v>;
- mmc-hs200-1_8v;
- mmc-hs400-1_8v;
- bus-width = <8>;
- no-sd;
- no-sdio;
- non-removable;
- full-pwr-cycle-in-suspend;
- status = "okay";
-};
-
-&pfc {
- pinctrl-0 = <&scif_clk_pins>;
- pinctrl-names = "default";
-
- avb0_pins: avb0 {
- mux {
- groups = "avb0_link", "avb0_mdio", "avb0_rgmii",
- "avb0_txcrefclk";
- function = "avb0";
- };
-
- pins_mdio {
- groups = "avb0_mdio";
- drive-strength = <21>;
- };
-
- pins_mii {
- groups = "avb0_rgmii";
- drive-strength = <21>;
- };
- };
-
- hscif0_pins: hscif0 {
- groups = "hscif0_data", "hscif0_ctrl";
- function = "hscif0";
- };
-
- i2c0_pins: i2c0 {
- groups = "i2c0";
- function = "i2c0";
- };
-
- mmc_pins: mmc {
- groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
- function = "mmc";
- power-source = <1800>;
- };
-
- scif_clk_pins: scif_clk {
- groups = "scif_clk";
- function = "scif_clk";
- };
-};
-
-&scif_clk {
- clock-frequency = <24000000>;
-};
diff --git a/arch/arm/dts/r8a779h0-gray-hawk-csi-dsi.dtsi b/arch/arm/dts/r8a779h0-gray-hawk-csi-dsi.dtsi
deleted file mode 100644
index fcdd8eb..0000000
--- a/arch/arm/dts/r8a779h0-gray-hawk-csi-dsi.dtsi
+++ /dev/null
@@ -1,15 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-/*
- * Device Tree Source for the R-Car V4M Gray Hawk CSI/DSI sub-board
- *
- * Copyright (C) 2023 Renesas Electronics Corp.
- */
-
-&i2c0 {
- eeprom@52 {
- compatible = "rohm,br24g01", "atmel,24c01";
- label = "csi-dsi-sub-board-id";
- reg = <0x52>;
- pagesize = <8>;
- };
-};
diff --git a/arch/arm/dts/r8a779h0-gray-hawk-ethernet.dtsi b/arch/arm/dts/r8a779h0-gray-hawk-ethernet.dtsi
deleted file mode 100644
index 5a8e598..0000000
--- a/arch/arm/dts/r8a779h0-gray-hawk-ethernet.dtsi
+++ /dev/null
@@ -1,15 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-/*
- * Device Tree Source for the R-Car V4M Gray Hawk Ethernet sub-board
- *
- * Copyright (C) 2023 Renesas Electronics Corp.
- */
-
-&i2c0 {
- eeprom@53 {
- compatible = "rohm,br24g01", "atmel,24c01";
- label = "ethernet-sub-board-id";
- reg = <0x53>;
- pagesize = <8>;
- };
-};
diff --git a/arch/arm/dts/r8a779h0-gray-hawk-u-boot.dtsi b/arch/arm/dts/r8a779h0-gray-hawk-u-boot.dtsi
deleted file mode 100644
index 92c1315..0000000
--- a/arch/arm/dts/r8a779h0-gray-hawk-u-boot.dtsi
+++ /dev/null
@@ -1,41 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source extras for U-Boot for the Gray Hawk board
- *
- * Copyright (C) 2023 Renesas Electronics Corp.
- */
-
-#include "r8a779h0-u-boot.dtsi"
-
-/ {
- aliases {
- spi0 = &rpc;
- };
-};
-
-&pfc {
- qspi0_pins: qspi0 {
- groups = "qspi0_ctrl", "qspi0_data4";
- function = "qspi0";
- };
-};
-
-&rpc {
- pinctrl-0 = <&qspi0_pins>;
- pinctrl-names = "default";
-
- #address-cells = <1>;
- #size-cells = <0>;
- spi-max-frequency = <40000000>;
- status = "okay";
-
- flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "s25fs512s", "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <40000000>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <1>;
- };
-};
diff --git a/arch/arm/dts/r8a779h0-gray-hawk.dts b/arch/arm/dts/r8a779h0-gray-hawk.dts
deleted file mode 100644
index 59e5e49..0000000
--- a/arch/arm/dts/r8a779h0-gray-hawk.dts
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-/*
- * Device Tree Source for the Gray Hawk CPU and BreakOut boards
- *
- * Copyright (C) 2023 Renesas Electronics Corp.
- */
-
-/dts-v1/;
-#include "r8a779h0-gray-hawk-cpu.dtsi"
-#include "r8a779h0-gray-hawk-csi-dsi.dtsi"
-#include "r8a779h0-gray-hawk-ethernet.dtsi"
-
-/ {
- model = "Renesas Gray Hawk CPU and Breakout boards based on r8a779h0";
- compatible = "renesas,gray-hawk-breakout", "renesas,gray-hawk-cpu", "renesas,r8a779h0";
-};
-
-&i2c0 {
- eeprom@51 {
- compatible = "rohm,br24g01", "atmel,24c01";
- label = "breakout-board";
- reg = <0x51>;
- pagesize = <8>;
- };
-};
diff --git a/arch/arm/dts/r8a779h0-u-boot.dtsi b/arch/arm/dts/r8a779h0-u-boot.dtsi
deleted file mode 100644
index b2f7e05..0000000
--- a/arch/arm/dts/r8a779h0-u-boot.dtsi
+++ /dev/null
@@ -1,27 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source extras for U-Boot on R-Car R8A779H0 SoC
- *
- * Copyright (C) 2023 Renesas Electronics Corp.
- */
-
-#include "r8a779x-u-boot.dtsi"
-/ {
- soc {
- rpc: spi@ee200000 {
- compatible = "renesas,r8a779h0-rpc-if", "renesas,rcar-gen4-rpc-if";
- reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x04000000>;
- interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 629>;
- power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
- resets = <&cpg 629>;
- bank-width = <2>;
- num-cs = <1>;
- status = "disabled";
- };
- };
-};
-
-&extalr_clk {
- bootph-all;
-};
diff --git a/arch/arm/dts/r8a779h0.dtsi b/arch/arm/dts/r8a779h0.dtsi
deleted file mode 100644
index a896bc2..0000000
--- a/arch/arm/dts/r8a779h0.dtsi
+++ /dev/null
@@ -1,460 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-/*
- * Device Tree Source for the R-Car V4M (R8A779H0) SoC
- *
- * Copyright (C) 2023 Renesas Electronics Corp.
- */
-
-#include <dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/power/renesas,r8a779h0-sysc.h>
-
-/ {
- compatible = "renesas,r8a779h0";
- #address-cells = <2>;
- #size-cells = <2>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- a76_0: cpu@0 {
- compatible = "arm,cortex-a76";
- reg = <0>;
- device_type = "cpu";
- power-domains = <&sysc R8A779H0_PD_A1E0D0C0>;
- };
- };
-
- extal_clk: extal-clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board */
- clock-frequency = <0>;
- };
-
- extalr_clk: extalr-clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board */
- clock-frequency = <0>;
- };
-
- pmu-a76 {
- compatible = "arm,cortex-a76-pmu";
- interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
- };
-
- /* External SCIF clock - to be overridden by boards that provide it */
- scif_clk: scif-clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- soc: soc {
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- pfc: pinctrl@e6050000 {
- compatible = "renesas,pfc-r8a779h0";
- reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
- <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>,
- <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>,
- <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>;
- };
-
- gpio0: gpio@e6050180 {
- compatible = "renesas,gpio-r8a779h0",
- "renesas,rcar-gen4-gpio";
- reg = <0 0xe6050180 0 0x54>;
- interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 0 19>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 915>;
- power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
- resets = <&cpg 915>;
- };
-
- gpio1: gpio@e6050980 {
- compatible = "renesas,gpio-r8a779h0",
- "renesas,rcar-gen4-gpio";
- reg = <0 0xe6050980 0 0x54>;
- interrupts = <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 32 30>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 915>;
- power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
- resets = <&cpg 915>;
- };
-
- gpio2: gpio@e6058180 {
- compatible = "renesas,gpio-r8a779h0",
- "renesas,rcar-gen4-gpio";
- reg = <0 0xe6058180 0 0x54>;
- interrupts = <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 64 20>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 916>;
- power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
- resets = <&cpg 916>;
- };
-
- gpio3: gpio@e6058980 {
- compatible = "renesas,gpio-r8a779h0",
- "renesas,rcar-gen4-gpio";
- reg = <0 0xe6058980 0 0x54>;
- interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 96 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 916>;
- power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
- resets = <&cpg 916>;
- };
-
- gpio4: gpio@e6060180 {
- compatible = "renesas,gpio-r8a779h0",
- "renesas,rcar-gen4-gpio";
- reg = <0 0xe6060180 0 0x54>;
- interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 128 25>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 917>;
- power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
- resets = <&cpg 917>;
- };
-
- gpio5: gpio@e6060980 {
- compatible = "renesas,gpio-r8a779h0",
- "renesas,rcar-gen4-gpio";
- reg = <0 0xe6060980 0 0x54>;
- interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 160 21>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 917>;
- power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
- resets = <&cpg 917>;
- };
-
- gpio6: gpio@e6061180 {
- compatible = "renesas,gpio-r8a779h0",
- "renesas,rcar-gen4-gpio";
- reg = <0 0xe6061180 0 0x54>;
- interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 192 21>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 917>;
- power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
- resets = <&cpg 917>;
- };
-
- gpio7: gpio@e6061980 {
- compatible = "renesas,gpio-r8a779h0",
- "renesas,rcar-gen4-gpio";
- reg = <0 0xe6061980 0 0x54>;
- interrupts = <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 224 21>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 917>;
- power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
- resets = <&cpg 917>;
- };
-
- cpg: clock-controller@e6150000 {
- compatible = "renesas,r8a779h0-cpg-mssr";
- reg = <0 0xe6150000 0 0x4000>;
- clocks = <&extal_clk>, <&extalr_clk>;
- clock-names = "extal", "extalr";
- #clock-cells = <2>;
- #power-domain-cells = <0>;
- #reset-cells = <1>;
- };
-
- rst: reset-controller@e6160000 {
- compatible = "renesas,r8a779h0-rst";
- reg = <0 0xe6160000 0 0x4000>;
- };
-
- sysc: system-controller@e6180000 {
- compatible = "renesas,r8a779h0-sysc";
- reg = <0 0xe6180000 0 0x4000>;
- #power-domain-cells = <1>;
- };
-
- i2c0: i2c@e6500000 {
- compatible = "renesas,i2c-r8a779h0",
- "renesas,rcar-gen4-i2c";
- reg = <0 0xe6500000 0 0x40>;
- interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 518>;
- power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
- resets = <&cpg 518>;
- i2c-scl-internal-delay-ns = <110>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c1: i2c@e6508000 {
- compatible = "renesas,i2c-r8a779h0",
- "renesas,rcar-gen4-i2c";
- reg = <0 0xe6508000 0 0x40>;
- interrupts = <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 519>;
- power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
- resets = <&cpg 519>;
- i2c-scl-internal-delay-ns = <110>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c2: i2c@e6510000 {
- compatible = "renesas,i2c-r8a779h0",
- "renesas,rcar-gen4-i2c";
- reg = <0 0xe6510000 0 0x40>;
- interrupts = <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 520>;
- power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
- resets = <&cpg 520>;
- i2c-scl-internal-delay-ns = <110>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c3: i2c@e66d0000 {
- compatible = "renesas,i2c-r8a779h0",
- "renesas,rcar-gen4-i2c";
- reg = <0 0xe66d0000 0 0x40>;
- interrupts = <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 521>;
- power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
- resets = <&cpg 521>;
- i2c-scl-internal-delay-ns = <110>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- hscif0: serial@e6540000 {
- compatible = "renesas,hscif-r8a779h0",
- "renesas,rcar-gen4-hscif", "renesas,hscif";
- reg = <0 0xe6540000 0 0x60>;
- interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 514>,
- <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
- resets = <&cpg 514>;
- status = "disabled";
- };
-
- avb0: ethernet@e6800000 {
- compatible = "renesas,etheravb-r8a779h0",
- "renesas,etheravb-rcar-gen4";
- reg = <0 0xe6800000 0 0x800>;
- interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15",
- "ch16", "ch17", "ch18", "ch19",
- "ch20", "ch21", "ch22", "ch23",
- "ch24";
- clocks = <&cpg CPG_MOD 211>;
- power-domains = <&sysc R8A779H0_PD_C4>;
- resets = <&cpg 211>;
- phy-mode = "rgmii";
- rx-internal-delay-ps = <0>;
- tx-internal-delay-ps = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- avb1: ethernet@e6810000 {
- compatible = "renesas,etheravb-r8a779h0",
- "renesas,etheravb-rcar-gen4";
- reg = <0 0xe6810000 0 0x800>;
- interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15",
- "ch16", "ch17", "ch18", "ch19",
- "ch20", "ch21", "ch22", "ch23",
- "ch24";
- clocks = <&cpg CPG_MOD 212>;
- power-domains = <&sysc R8A779H0_PD_C4>;
- resets = <&cpg 212>;
- phy-mode = "rgmii";
- rx-internal-delay-ps = <0>;
- tx-internal-delay-ps = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- avb2: ethernet@e6820000 {
- compatible = "renesas,etheravb-r8a779h0",
- "renesas,etheravb-rcar-gen4";
- reg = <0 0xe6820000 0 0x1000>;
- interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15",
- "ch16", "ch17", "ch18", "ch19",
- "ch20", "ch21", "ch22", "ch23",
- "ch24";
- clocks = <&cpg CPG_MOD 213>;
- power-domains = <&sysc R8A779H0_PD_C4>;
- resets = <&cpg 213>;
- phy-mode = "rgmii";
- rx-internal-delay-ps = <0>;
- tx-internal-delay-ps = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- mmc0: mmc@ee140000 {
- compatible = "renesas,sdhi-r8a779h0",
- "renesas,rcar-gen4-sdhi";
- reg = <0 0xee140000 0 0x2000>;
- interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 706>,
- <&cpg CPG_CORE R8A779H0_CLK_SD0H>;
- clock-names = "core", "clkh";
- power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
- resets = <&cpg 706>;
- max-frequency = <200000000>;
- status = "disabled";
- };
-
- gic: interrupt-controller@f1000000 {
- compatible = "arm,gic-v3";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0x0 0xf1000000 0 0x20000>,
- <0x0 0xf1060000 0 0x110000>;
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- prr: chipid@fff00044 {
- compatible = "renesas,prr";
- reg = <0 0xfff00044 0 4>;
- };
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
- <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
- <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
- <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
- };
-};
diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
index 04028bf..a31dea8 100644
--- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
+++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
@@ -74,6 +74,21 @@
bootph-all;
};
+&rk817 {
+ regulators {
+ vcc_cam: LDO_REG9 {
+ regulator-name = "vcc_cam";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <3000000>;
+ };
+ };
+ };
+};
+
&saradc {
bootph-all;
status = "okay";
diff --git a/arch/arm/dts/rk3326-odroid-go2.dts b/arch/arm/dts/rk3326-odroid-go2.dts
deleted file mode 100644
index ea0695b..0000000
--- a/arch/arm/dts/rk3326-odroid-go2.dts
+++ /dev/null
@@ -1,642 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 Hardkernel Co., Ltd
- * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH
- */
-
-/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include "rk3326.dtsi"
-
-/ {
- model = "ODROID-GO Advance";
- compatible = "hardkernel,rk3326-odroid-go2", "rockchip,rk3326";
-
- aliases {
- mmc0 = &sdmmc;
- };
-
- chosen {
- stdout-path = "serial2:115200n8";
- };
-
- adc-joystick {
- compatible = "adc-joystick";
- io-channels = <&saradc 1>,
- <&saradc 2>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- axis@0 {
- reg = <0>;
- abs-flat = <10>;
- abs-fuzz = <10>;
- abs-range = <172 772>;
- linux,code = <ABS_X>;
- };
-
- axis@1 {
- reg = <1>;
- abs-flat = <10>;
- abs-fuzz = <10>;
- abs-range = <278 815>;
- linux,code = <ABS_Y>;
- };
- };
-
- backlight: backlight {
- compatible = "pwm-backlight";
- power-supply = <&vcc_bl>;
- pwms = <&pwm1 0 25000 0>;
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&btn_pins>;
-
- /*
- * *** ODROIDGO2-Advance Switch layout ***
- * |------------------------------------------------|
- * | sw15 sw16 |
- * |------------------------------------------------|
- * | sw1 |-------------------| sw8 |
- * | sw3 sw4 | | sw7 sw5 |
- * | sw2 | LCD Display | sw6 |
- * | | | |
- * | |-------------------| |
- * | sw9 sw10 sw11 sw12 sw13 sw14 |
- * |------------------------------------------------|
- */
-
- sw1 {
- gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>;
- label = "DPAD-UP";
- linux,code = <BTN_DPAD_UP>;
- };
- sw2 {
- gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_LOW>;
- label = "DPAD-DOWN";
- linux,code = <BTN_DPAD_DOWN>;
- };
- sw3 {
- gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>;
- label = "DPAD-LEFT";
- linux,code = <BTN_DPAD_LEFT>;
- };
- sw4 {
- gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_LOW>;
- label = "DPAD-RIGHT";
- linux,code = <BTN_DPAD_RIGHT>;
- };
- sw5 {
- gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>;
- label = "BTN-A";
- linux,code = <BTN_EAST>;
- };
- sw6 {
- gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>;
- label = "BTN-B";
- linux,code = <BTN_SOUTH>;
- };
- sw7 {
- gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>;
- label = "BTN-Y";
- linux,code = <BTN_WEST>;
- };
- sw8 {
- gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>;
- label = "BTN-X";
- linux,code = <BTN_NORTH>;
- };
- sw9 {
- gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>;
- label = "F1";
- linux,code = <BTN_TRIGGER_HAPPY1>;
- };
- sw10 {
- gpios = <&gpio2 RK_PA1 GPIO_ACTIVE_LOW>;
- label = "F2";
- linux,code = <BTN_TRIGGER_HAPPY2>;
- };
- sw11 {
- gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
- label = "F3";
- linux,code = <BTN_TRIGGER_HAPPY3>;
- };
- sw12 {
- gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_LOW>;
- label = "F4";
- linux,code = <BTN_TRIGGER_HAPPY4>;
- };
- sw13 {
- gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_LOW>;
- label = "F5";
- linux,code = <BTN_TRIGGER_HAPPY5>;
- };
- sw14 {
- gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_LOW>;
- label = "F6";
- linux,code = <BTN_TRIGGER_HAPPY6>;
- };
- sw15 {
- gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>;
- label = "TOP-LEFT";
- linux,code = <BTN_TL>;
- };
- sw16 {
- gpios = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>;
- label = "TOP-RIGHT";
- linux,code = <BTN_TR>;
- };
- };
-
- leds: gpio-leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&blue_led_pin>;
-
- blue_led: led-0 {
- label = "blue:heartbeat";
- gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- rk817-sound {
- compatible = "simple-audio-card";
- simple-audio-card,name = "Analog";
- simple-audio-card,format = "i2s";
- simple-audio-card,hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
- simple-audio-card,mclk-fs = <256>;
- simple-audio-card,widgets =
- "Microphone", "Mic Jack",
- "Headphone", "Headphones",
- "Speaker", "Speaker";
- simple-audio-card,routing =
- "MICL", "Mic Jack",
- "Headphones", "HPOL",
- "Headphones", "HPOR",
- "Speaker", "SPKO";
-
- simple-audio-card,codec {
- sound-dai = <&rk817>;
- };
-
- simple-audio-card,cpu {
- sound-dai = <&i2s1_2ch>;
- };
- };
-
- vccsys: vccsys {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v8_sys";
- regulator-always-on;
- regulator-min-microvolt = <3800000>;
- regulator-max-microvolt = <3800000>;
- };
-
- vcc_host: vcc_host {
- compatible = "regulator-fixed";
- regulator-name = "vcc_host";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
-
- gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&usb_midu>;
- };
-};
-
-&cpu0 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu1 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu2 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu3 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cru {
- assigned-clocks = <&cru PLL_NPLL>,
- <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
- <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
- <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>,
- <&cru PLL_CPLL>;
-
- assigned-clock-rates = <1188000000>,
- <200000000>, <200000000>,
- <150000000>, <150000000>,
- <100000000>, <200000000>,
- <17000000>;
-};
-
-&display_subsystem {
- status = "okay";
-};
-
-&dsi {
- status = "okay";
-
- ports {
- mipi_out: port@1 {
- reg = <1>;
-
- mipi_out_panel: endpoint {
- remote-endpoint = <&mipi_in_panel>;
- };
- };
- };
-
- panel@0 {
- compatible = "elida,kd35t133";
- reg = <0>;
- backlight = <&backlight>;
- iovcc-supply = <&vcc_lcd>;
- reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
- rotation = <270>;
- vdd-supply = <&vcc_lcd>;
-
- port {
- mipi_in_panel: endpoint {
- remote-endpoint = <&mipi_out_panel>;
- };
- };
- };
-};
-
-&dsi_dphy {
- status = "okay";
-};
-
-&gpu {
- mali-supply = <&vdd_logic>;
- status = "okay";
-};
-
-&i2c0 {
- clock-frequency = <400000>;
- i2c-scl-falling-time-ns = <16>;
- i2c-scl-rising-time-ns = <280>;
- status = "okay";
-
- rk817: pmic@20 {
- compatible = "rockchip,rk817";
- reg = <0x20>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
- clock-output-names = "rk808-clkout1", "xin32k";
- clock-names = "mclk";
- clocks = <&cru SCLK_I2S1_OUT>;
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int>, <&i2s1_2ch_mclk>;
- wakeup-source;
- #clock-cells = <1>;
- #sound-dai-cells = <0>;
-
- vcc1-supply = <&vccsys>;
- vcc2-supply = <&vccsys>;
- vcc3-supply = <&vccsys>;
- vcc4-supply = <&vccsys>;
- vcc5-supply = <&vccsys>;
- vcc6-supply = <&vccsys>;
- vcc7-supply = <&vccsys>;
- vcc8-supply = <&vccsys>;
-
- regulators {
- vdd_logic: DCDC_REG1 {
- regulator-name = "vdd_logic";
- regulator-min-microvolt = <950000>;
- regulator-max-microvolt = <1150000>;
- regulator-ramp-delay = <6001>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <950000>;
- };
- };
-
- vdd_arm: DCDC_REG2 {
- regulator-name = "vdd_arm";
- regulator-min-microvolt = <950000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <950000>;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_3v3: DCDC_REG4 {
- regulator-name = "vcc_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc_1v8: LDO_REG2 {
- regulator-name = "vcc_1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vdd_1v0: LDO_REG3 {
- regulator-name = "vdd_1v0";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1000000>;
- };
- };
-
- vcc3v3_pmu: LDO_REG4 {
- regulator-name = "vcc3v3_pmu";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vccio_sd: LDO_REG5 {
- regulator-name = "vccio_sd";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc_sd: LDO_REG6 {
- regulator-name = "vcc_sd";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc_bl: LDO_REG7 {
- regulator-name = "vcc_bl";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc_lcd: LDO_REG8 {
- regulator-name = "vcc_lcd";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <2800000>;
- };
- };
-
- vcc_cam: LDO_REG9 {
- regulator-name = "vcc_cam";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <3000000>;
- };
- };
-
- usb_midu: BOOST {
- regulator-name = "usb_midu";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5400000>;
- regulator-always-on;
- regulator-boot-on;
- };
- };
-
- rk817_codec: codec {
- rockchip,mic-in-differential;
- };
- };
-};
-
-/* EXT Header(P2): 7(SCL:GPIO0.C2), 8(SDA:GPIO0.C3) */
-&i2c1 {
- clock-frequency = <400000>;
- status = "okay";
-};
-
-/* I2S 1 Channel Used */
-&i2s1_2ch {
- status = "okay";
-};
-
-&io_domains {
- vccio1-supply = <&vcc_3v3>;
- vccio2-supply = <&vccio_sd>;
- vccio3-supply = <&vcc_3v3>;
- vccio4-supply = <&vcc_3v3>;
- vccio5-supply = <&vcc_3v3>;
- vccio6-supply = <&vcc_3v3>;
- status = "okay";
-};
-
-&pmu_io_domains {
- pmuio1-supply = <&vcc3v3_pmu>;
- pmuio2-supply = <&vcc3v3_pmu>;
- status = "okay";
-};
-
-&pwm1 {
- status = "okay";
-};
-
-&saradc {
- vref-supply = <&vcc_1v8>;
- status = "okay";
-};
-
-&sdmmc {
- cap-sd-highspeed;
- card-detect-delay = <200>;
- cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; /*[> CD GPIO <]*/
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc_sd>;
- vqmmc-supply = <&vccio_sd>;
- status = "okay";
-};
-
-&sfc {
- pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <108000000>;
- spi-rx-bus-width = <2>;
- spi-tx-bus-width = <1>;
- };
-};
-
-&tsadc {
- status = "okay";
-};
-
-&u2phy {
- status = "okay";
-
- u2phy_host: host-port {
- status = "okay";
- };
-
- u2phy_otg: otg-port {
- status = "disabled";
- };
-};
-
-&usb20_otg {
- status = "okay";
-};
-
-/* EXT Header(P2): 2(RXD:GPIO1.C0),3(TXD:.C1),4(CTS:.C2),5(RTS:.C3) */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_xfer &uart1_cts>;
- status = "okay";
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart2m1_xfer>;
- status = "okay";
-};
-
-&vopb {
- status = "okay";
-};
-
-&vopb_mmu {
- status = "okay";
-};
-
-&pinctrl {
- btns {
- btn_pins: btn-pins {
- rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
- <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
- <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
- <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>,
- <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>,
- <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>,
- <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>,
- <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>,
- <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>,
- <2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>,
- <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
- <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>,
- <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,
- <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
- <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
- <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- headphone {
- hp_det: hp-det {
- rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>;
- };
- };
-
- leds {
- blue_led_pin: blue-led-pin {
- rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pmic {
- dc_det: dc-det {
- rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- pmic_int: pmic-int {
- rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
- };
-
- soc_slppin_gpio: soc_slppin_gpio {
- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>;
- };
-
- soc_slppin_rst: soc_slppin_rst {
- rockchip,pins = <0 RK_PA4 2 &pcfg_pull_none>;
- };
-
- soc_slppin_slp: soc_slppin_slp {
- rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>;
- };
- };
-};
diff --git a/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi b/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi
index 5a9bd32..55895d0 100644
--- a/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi
@@ -33,12 +33,6 @@
};
&binman {
- simple-bin {
- fit {
- offset = <((CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - 64) * 512)>;
- };
- };
-
#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
simple-bin-spi {
fit {
diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
index 793ed4a..c7e8498 100644
--- a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
@@ -4,7 +4,7 @@
/ {
chosen {
- u-boot,spl-boot-order = "same-as-spl", &sdmmc1, &sdmmc0;
+ u-boot,spl-boot-order = &sdmmc0, &sdhci;
};
};
diff --git a/arch/arm/dts/rk3566-powkiddy-x55-u-boot.dtsi b/arch/arm/dts/rk3566-powkiddy-x55-u-boot.dtsi
new file mode 100644
index 0000000..eadd351
--- /dev/null
+++ b/arch/arm/dts/rk3566-powkiddy-x55-u-boot.dtsi
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk356x-u-boot.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = &sdmmc0, &sdhci;
+ };
+};
diff --git a/arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi b/arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi
new file mode 100644
index 0000000..af96d2f
--- /dev/null
+++ b/arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 ArmSoM Technology Co., Ltd.
+ */
+
+#include "rk3588-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi b/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi
new file mode 100644
index 0000000..275ae6f
--- /dev/null
+++ b/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Theobroma Systems Design und Consulting GmbH
+ */
+
+#include "rk3588-u-boot.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
+ };
+};
+
+&emmc_pwrseq {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&emmc_reset {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&gpio2 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sdhci {
+ /* U-Boot currently cannot handle anything below HS200 for eMMC on RK3588 */
+ /delete-property/ mmc-ddr-1_8v;
+ /delete-property/ cap-mmc-highspeed;
+};
+
+&uart2m2_xfer {
+ bootph-all;
+};
diff --git a/arch/arm/dts/rk3588-u-boot.dtsi b/arch/arm/dts/rk3588-u-boot.dtsi
index 4623580..bfe6645 100644
--- a/arch/arm/dts/rk3588-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-u-boot.dtsi
@@ -4,77 +4,3 @@
*/
#include "rk3588s-u-boot.dtsi"
-
-/ {
- usb_host1_xhci: usb@fc400000 {
- compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
- reg = <0x0 0xfc400000 0x0 0x400000>;
- interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
- <&cru ACLK_USB3OTG1>;
- clock-names = "ref_clk", "suspend_clk", "bus_clk";
- dr_mode = "otg";
- phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>;
- phy-names = "usb2-phy", "usb3-phy";
- phy_type = "utmi_wide";
- power-domains = <&power RK3588_PD_USB>;
- resets = <&cru SRST_A_USB3OTG1>;
- snps,dis_enblslpm_quirk;
- snps,dis-u2-freeclk-exists-quirk;
- snps,dis-del-phy-power-chg-quirk;
- snps,dis-tx-ipgap-linecheck-quirk;
- status = "disabled";
- };
-
- usbdpphy1_grf: syscon@fd5cc000 {
- compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
- reg = <0x0 0xfd5cc000 0x0 0x4000>;
- };
-
- usb2phy1_grf: syscon@fd5d4000 {
- compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
- reg = <0x0 0xfd5d4000 0x0 0x4000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- u2phy1: usb2phy@4000 {
- compatible = "rockchip,rk3588-usb2phy";
- reg = <0x4000 0x10>;
- #clock-cells = <0>;
- clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
- clock-names = "phyclk";
- clock-output-names = "usb480m_phy1";
- interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
- resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
- reset-names = "phy", "apb";
- status = "disabled";
-
- u2phy1_otg: otg-port {
- #phy-cells = <0>;
- status = "disabled";
- };
- };
- };
-
- usbdp_phy1: phy@fed90000 {
- compatible = "rockchip,rk3588-usbdp-phy";
- reg = <0x0 0xfed90000 0x0 0x10000>;
- #phy-cells = <1>;
- clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
- <&cru CLK_USBDP_PHY1_IMMORTAL>,
- <&cru PCLK_USBDPPHY1>,
- <&u2phy1>;
- clock-names = "refclk", "immortal", "pclk", "utmi";
- resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>,
- <&cru SRST_USBDP_COMBO_PHY1_CMN>,
- <&cru SRST_USBDP_COMBO_PHY1_LANE>,
- <&cru SRST_USBDP_COMBO_PHY1_PCS>,
- <&cru SRST_P_USBDPPHY1>;
- reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
- rockchip,u2phy-grf = <&usb2phy1_grf>;
- rockchip,usb-grf = <&usb_grf>;
- rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
- rockchip,vo-grf = <&vo0_grf>;
- status = "disabled";
- };
-};
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index e9d38d5..09d8b31 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -19,95 +19,10 @@
bootph-all;
};
- usb_host0_xhci: usb@fc000000 {
- compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
- reg = <0x0 0xfc000000 0x0 0x400000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
- <&cru ACLK_USB3OTG0>;
- clock-names = "ref_clk", "suspend_clk", "bus_clk";
- dr_mode = "otg";
- phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>;
- phy-names = "usb2-phy", "usb3-phy";
- phy_type = "utmi_wide";
- power-domains = <&power RK3588_PD_USB>;
- resets = <&cru SRST_A_USB3OTG0>;
- snps,dis_enblslpm_quirk;
- snps,dis-u1-entry-quirk;
- snps,dis-u2-entry-quirk;
- snps,dis-u2-freeclk-exists-quirk;
- snps,dis-del-phy-power-chg-quirk;
- snps,dis-tx-ipgap-linecheck-quirk;
- status = "disabled";
- };
-
- vo0_grf: syscon@fd5a6000 {
- compatible = "rockchip,rk3588-vo-grf", "syscon";
- reg = <0x0 0xfd5a6000 0x0 0x2000>;
- clocks = <&cru PCLK_VO0GRF>;
- };
-
- usb_grf: syscon@fd5ac000 {
- compatible = "rockchip,rk3588-usb-grf", "syscon";
- reg = <0x0 0xfd5ac000 0x0 0x4000>;
- };
-
- usbdpphy0_grf: syscon@fd5c8000 {
- compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
- reg = <0x0 0xfd5c8000 0x0 0x4000>;
- };
-
- usb2phy0_grf: syscon@fd5d0000 {
- compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
- reg = <0x0 0xfd5d0000 0x0 0x4000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- u2phy0: usb2phy@0 {
- compatible = "rockchip,rk3588-usb2phy";
- reg = <0x0 0x10>;
- #clock-cells = <0>;
- clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
- clock-names = "phyclk";
- clock-output-names = "usb480m_phy0";
- interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>;
- resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
- reset-names = "phy", "apb";
- status = "disabled";
-
- u2phy0_otg: otg-port {
- #phy-cells = <0>;
- status = "disabled";
- };
- };
- };
-
rng: rng@fe378000 {
compatible = "rockchip,trngv1";
reg = <0x0 0xfe378000 0x0 0x200>;
};
-
- usbdp_phy0: phy@fed80000 {
- compatible = "rockchip,rk3588-usbdp-phy";
- reg = <0x0 0xfed80000 0x0 0x10000>;
- #phy-cells = <1>;
- clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
- <&cru CLK_USBDP_PHY0_IMMORTAL>,
- <&cru PCLK_USBDPPHY0>,
- <&u2phy0>;
- clock-names = "refclk", "immortal", "pclk", "utmi";
- resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
- <&cru SRST_USBDP_COMBO_PHY0_CMN>,
- <&cru SRST_USBDP_COMBO_PHY0_LANE>,
- <&cru SRST_USBDP_COMBO_PHY0_PCS>,
- <&cru SRST_P_USBDPPHY0>;
- reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
- rockchip,u2phy-grf = <&usb2phy0_grf>;
- rockchip,usb-grf = <&usb_grf>;
- rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
- rockchip,vo-grf = <&vo0_grf>;
- status = "disabled";
- };
};
#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
diff --git a/arch/arm/dts/rv1126-edgeble-neu2-io.dts b/arch/arm/dts/rv1126-edgeble-neu2-io.dts
deleted file mode 100644
index 0c2396b..0000000
--- a/arch/arm/dts/rv1126-edgeble-neu2-io.dts
+++ /dev/null
@@ -1,112 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
- * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
- */
-
-/dts-v1/;
-#include "rv1126.dtsi"
-#include "rv1126-edgeble-neu2.dtsi"
-
-/ {
- model = "Edgeble Neu2 IO Board";
- compatible = "edgeble,neural-compute-module-2-io",
- "edgeble,neural-compute-module-2", "rockchip,rv1126";
-
- aliases {
- serial2 = &uart2;
- };
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- vcc12v_dcin: vcc12v-dcin-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc12v_dcin";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-
- vcc5v0_sys: vcc5v0-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc12v_dcin>;
- };
-
- v3v3_sys: v3v3-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "v3v3_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc5v0_sys>;
- };
-};
-
-&gmac {
- assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>,
- <&cru CLK_GMAC_ETHERNET_OUT>;
- assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>;
- assigned-clock-rates = <125000000>, <0>, <25000000>;
- clock_in_out = "input";
- phy-handle = <&phy>;
- phy-mode = "rgmii";
- phy-supply = <&vcc_3v3>;
- pinctrl-names = "default";
- pinctrl-0 = <&rgmiim1_miim &rgmiim1_bus2 &rgmiim1_bus4 &clk_out_ethernetm1_pins>;
- tx_delay = <0x2a>;
- rx_delay = <0x1a>;
- status = "okay";
-};
-
-&mdio {
- phy: ethernet-phy@0 {
- compatible = "ethernet-phy-id001c.c916",
- "ethernet-phy-ieee802.3-c22";
- reg = <0x0>;
- pinctrl-names = "default";
- pinctrl-0 = <ð_phy_rst>;
- reset-assert-us = <20000>;
- reset-deassert-us = <100000>;
- reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
- };
-};
-
-&pinctrl {
- ethernet {
- eth_phy_rst: eth-phy-rst {
- rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
- };
- };
-};
-
-&pwm11 {
- status = "okay";
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- card-detect-delay = <200>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_det>;
- rockchip,default-sample-phase = <90>;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr104;
- vqmmc-supply = <&vccio_sd>;
- status = "okay";
-};
-
-&uart2 {
- status = "okay";
-};
diff --git a/arch/arm/dts/rv1126-edgeble-neu2.dtsi b/arch/arm/dts/rv1126-edgeble-neu2.dtsi
deleted file mode 100644
index 7ea8d7d..0000000
--- a/arch/arm/dts/rv1126-edgeble-neu2.dtsi
+++ /dev/null
@@ -1,345 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
- * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
- */
-
-/ {
- compatible = "edgeble,neural-compute-module-2", "rockchip,rv1126";
-
- aliases {
- mmc0 = &emmc;
- };
-
- vccio_flash: vccio-flash-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&flash_vol_sel>;
- regulator-name = "vccio_flash";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_3v3>;
- };
-
- sdio_pwrseq: pwrseq-sdio {
- compatible = "mmc-pwrseq-simple";
- clocks = <&rk809 1>;
- clock-names = "ext_clock";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_enable_h>;
- reset-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>;
- };
-};
-
-&cpu0 {
- cpu-supply = <&vdd_arm>;
-};
-
-&emmc {
- bus-width = <8>;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk>;
- rockchip,default-sample-phase = <90>;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&vccio_flash>;
- status = "okay";
-};
-
-&i2c0 {
- clock-frequency = <400000>;
- status = "okay";
-
- rk809: pmic@20 {
- compatible = "rockchip,rk809";
- reg = <0x20>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PB1 IRQ_TYPE_LEVEL_LOW>;
- #clock-cells = <1>;
- clock-output-names = "rk808-clkout1", "rk808-clkout2";
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int_l>;
- rockchip,system-power-controller;
- wakeup-source;
-
- vcc1-supply = <&vcc5v0_sys>;
- vcc2-supply = <&vcc5v0_sys>;
- vcc3-supply = <&vcc5v0_sys>;
- vcc4-supply = <&vcc5v0_sys>;
- vcc5-supply = <&vcc_buck5>;
- vcc6-supply = <&vcc_buck5>;
- vcc7-supply = <&vcc5v0_sys>;
- vcc8-supply = <&vcc3v3_sys>;
- vcc9-supply = <&vcc5v0_sys>;
-
- regulators {
- vdd_npu_vepu: DCDC_REG1 {
- regulator-name = "vdd_npu_vepu";
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <650000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <6001>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_arm: DCDC_REG2 {
- regulator-name = "vdd_arm";
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <725000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc3v3_sys: DCDC_REG4 {
- regulator-name = "vcc3v3_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc_buck5: DCDC_REG5 {
- regulator-name = "vcc_buck5";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <2200000>;
- regulator-max-microvolt = <2200000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <2200000>;
- };
- };
-
- vcc_0v8: LDO_REG1 {
- regulator-name = "vcc_0v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <800000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc1v8_pmu: LDO_REG2 {
- regulator-name = "vcc1v8_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vdd0v8_pmu: LDO_REG3 {
- regulator-name = "vcc0v8_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <800000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <800000>;
- };
- };
-
- vcc_1v8: LDO_REG4 {
- regulator-name = "vcc_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc_dovdd: LDO_REG5 {
- regulator-name = "vcc_dovdd";
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_dvdd: LDO_REG6 {
- regulator-name = "vcc_dvdd";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_avdd: LDO_REG7 {
- regulator-name = "vcc_avdd";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vccio_sd: LDO_REG8 {
- regulator-name = "vccio_sd";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_sd: LDO_REG9 {
- regulator-name = "vcc3v3_sd";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_5v0: SWITCH_REG1 {
- regulator-name = "vcc_5v0";
- };
-
- vcc_3v3: SWITCH_REG2 {
- regulator-name = "vcc_3v3";
- regulator-always-on;
- regulator-boot-on;
- };
- };
- };
-};
-
-&pinctrl {
- bt {
- bt_enable: bt-enable {
- rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- flash {
- flash_vol_sel: flash-vol-sel {
- rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pmic {
- pmic_int_l: pmic-int-l {
- rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- wifi {
- wifi_enable_h: wifi-enable-h {
- rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&pmu_io_domains {
- pmuio0-supply = <&vcc1v8_pmu>;
- pmuio1-supply = <&vcc3v3_sys>;
- vccio1-supply = <&vccio_flash>;
- vccio2-supply = <&vccio_sd>;
- vccio3-supply = <&vcc_1v8>;
- vccio4-supply = <&vcc_dovdd>;
- vccio5-supply = <&vcc_1v8>;
- vccio6-supply = <&vcc_1v8>;
- vccio7-supply = <&vcc_dovdd>;
- status = "okay";
-};
-
-&saradc {
- vref-supply = <&vcc_1v8>;
- status = "okay";
-};
-
-&sfc {
- pinctrl-names = "default";
- pinctrl-0 = <&fspi_pins>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <50000000>;
- spi-rx-bus-width = <4>;
- spi-tx-bus-width = <1>;
- };
-};
-
-&sdio {
- bus-width = <4>;
- cap-sd-highspeed;
- cap-sdio-irq;
- keep-power-in-suspend;
- max-frequency = <100000000>;
- mmc-pwrseq = <&sdio_pwrseq>;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>;
- rockchip,default-sample-phase = <90>;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc3v3_sys>;
- vqmmc-supply = <&vcc_1v8>;
- status = "okay";
- #address-cells = <1>;
- #size-cells = <0>;
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer &uart0_ctsn &uart0_rtsn>;
- status = "okay";
-
- bluetooth {
- compatible = "qcom,qca9377-bt";
- clocks = <&rk809 1>;
- enable-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; /* BT_RST */
- max-speed = <2000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&bt_enable>;
- vddxo-supply = <&vcc3v3_sys>;
- vddio-supply = <&vcc_1v8>;
- };
-};
diff --git a/arch/arm/dts/rv1126-pinctrl.dtsi b/arch/arm/dts/rv1126-pinctrl.dtsi
deleted file mode 100644
index f84f5f2..0000000
--- a/arch/arm/dts/rv1126-pinctrl.dtsi
+++ /dev/null
@@ -1,341 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
- */
-
-#include <dt-bindings/pinctrl/rockchip.h>
-#include "rockchip-pinconf.dtsi"
-
-/*
- * This file is auto generated by pin2dts tool, please keep these code
- * by adding changes at end of this file.
- */
-&pinctrl {
- clk_out_ethernet {
- /omit-if-no-ref/
- clk_out_ethernetm1_pins: clk-out-ethernetm1-pins {
- rockchip,pins =
- /* clk_out_ethernet_m1 */
- <2 RK_PC5 2 &pcfg_pull_none>;
- };
- };
- emmc {
- /omit-if-no-ref/
- emmc_rstnout: emmc-rstnout {
- rockchip,pins =
- /* emmc_rstn */
- <1 RK_PA3 2 &pcfg_pull_none>;
- };
- /omit-if-no-ref/
- emmc_bus8: emmc-bus8 {
- rockchip,pins =
- /* emmc_d0 */
- <0 RK_PC4 2 &pcfg_pull_up_drv_level_2>,
- /* emmc_d1 */
- <0 RK_PC5 2 &pcfg_pull_up_drv_level_2>,
- /* emmc_d2 */
- <0 RK_PC6 2 &pcfg_pull_up_drv_level_2>,
- /* emmc_d3 */
- <0 RK_PC7 2 &pcfg_pull_up_drv_level_2>,
- /* emmc_d4 */
- <0 RK_PD0 2 &pcfg_pull_up_drv_level_2>,
- /* emmc_d5 */
- <0 RK_PD1 2 &pcfg_pull_up_drv_level_2>,
- /* emmc_d6 */
- <0 RK_PD2 2 &pcfg_pull_up_drv_level_2>,
- /* emmc_d7 */
- <0 RK_PD3 2 &pcfg_pull_up_drv_level_2>;
- };
- /omit-if-no-ref/
- emmc_clk: emmc-clk {
- rockchip,pins =
- /* emmc_clko */
- <0 RK_PD7 2 &pcfg_pull_up_drv_level_2>;
- };
- /omit-if-no-ref/
- emmc_cmd: emmc-cmd {
- rockchip,pins =
- /* emmc_cmd */
- <0 RK_PD5 2 &pcfg_pull_up_drv_level_2>;
- };
- };
- fspi {
- /omit-if-no-ref/
- fspi_pins: fspi-pins {
- rockchip,pins =
- /* fspi_clk */
- <1 RK_PA3 3 &pcfg_pull_down>,
- /* fspi_cs0n */
- <0 RK_PD4 3 &pcfg_pull_up>,
- /* fspi_d0 */
- <1 RK_PA0 3 &pcfg_pull_up>,
- /* fspi_d1 */
- <1 RK_PA1 3 &pcfg_pull_up>,
- /* fspi_d2 */
- <0 RK_PD6 3 &pcfg_pull_up>,
- /* fspi_d3 */
- <1 RK_PA2 3 &pcfg_pull_up>;
- };
- };
- i2c0 {
- /omit-if-no-ref/
- i2c0_xfer: i2c0-xfer {
- rockchip,pins =
- /* i2c0_scl */
- <0 RK_PB4 1 &pcfg_pull_none_drv_level_0_smt>,
- /* i2c0_sda */
- <0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>;
- };
- };
- i2c2 {
- /omit-if-no-ref/
- i2c2_xfer: i2c2-xfer {
- rockchip,pins =
- /* i2c2_scl */
- <0 RK_PC2 1 &pcfg_pull_none_drv_level_0_smt>,
- /* i2c2_sda */
- <0 RK_PC3 1 &pcfg_pull_none_drv_level_0_smt>;
- };
- };
- pwm2 {
- /omit-if-no-ref/
- pwm2m0_pins: pwm2m0-pins {
- rockchip,pins =
- /* pwm2_pin_m0 */
- <0 RK_PC0 3 &pcfg_pull_none>;
- };
- };
- pwm11 {
- /omit-if-no-ref/
- pwm11m0_pins: pwm11m0-pins {
- rockchip,pins =
- /* pwm11_pin_m0 */
- <3 RK_PA7 6 &pcfg_pull_none>;
- };
- };
- rgmii {
- /omit-if-no-ref/
- rgmiim1_miim: rgmiim1-miim {
- rockchip,pins =
- /* rgmii_mdc_m1 */
- <2 RK_PC2 2 &pcfg_pull_none>,
- /* rgmii_mdio_m1 */
- <2 RK_PC1 2 &pcfg_pull_none>;
- };
- /omit-if-no-ref/
- rgmiim1_rxer: rgmiim1-rxer {
- rockchip,pins =
- /* rgmii_rxer_m1 */
- <2 RK_PC0 2 &pcfg_pull_none>;
- };
- /omit-if-no-ref/
- rgmiim1_bus2: rgmiim1-bus2 {
- rockchip,pins =
- /* rgmii_rxd0_m1 */
- <2 RK_PB5 2 &pcfg_pull_none>,
- /* rgmii_rxd1_m1 */
- <2 RK_PB6 2 &pcfg_pull_none>,
- /* rgmii_rxdv_m1 */
- <2 RK_PB4 2 &pcfg_pull_none>,
- /* rgmii_txd0_m1 */
- <2 RK_PC3 2 &pcfg_pull_none_drv_level_3>,
- /* rgmii_txd1_m1 */
- <2 RK_PC4 2 &pcfg_pull_none_drv_level_3>,
- /* rgmii_txen_m1 */
- <2 RK_PC6 2 &pcfg_pull_none_drv_level_3>;
- };
- /omit-if-no-ref/
- rgmiim1_bus4: rgmiim1-bus4 {
- rockchip,pins =
- /* rgmii_rxclk_m1 */
- <2 RK_PD3 2 &pcfg_pull_none>,
- /* rgmii_rxd2_m1 */
- <2 RK_PC7 2 &pcfg_pull_none>,
- /* rgmii_rxd3_m1 */
- <2 RK_PD0 2 &pcfg_pull_none>,
- /* rgmii_txclk_m1 */
- <2 RK_PD2 2 &pcfg_pull_none_drv_level_3>,
- /* rgmii_txd2_m1 */
- <2 RK_PD1 2 &pcfg_pull_none_drv_level_3>,
- /* rgmii_txd3_m1 */
- <2 RK_PA4 2 &pcfg_pull_none_drv_level_3>;
- };
- /omit-if-no-ref/
- rgmiim1_mclkinout: rgmiim1-mclkinout {
- rockchip,pins =
- /* rgmii_clk_m1 */
- <2 RK_PB7 2 &pcfg_pull_none>;
- };
- };
- sdmmc0 {
- /omit-if-no-ref/
- sdmmc0_bus4: sdmmc0-bus4 {
- rockchip,pins =
- /* sdmmc0_d0 */
- <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
- /* sdmmc0_d1 */
- <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
- /* sdmmc0_d2 */
- <1 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
- /* sdmmc0_d3 */
- <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>;
- };
- /omit-if-no-ref/
- sdmmc0_clk: sdmmc0-clk {
- rockchip,pins =
- /* sdmmc0_clk */
- <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
- };
- /omit-if-no-ref/
- sdmmc0_cmd: sdmmc0-cmd {
- rockchip,pins =
- /* sdmmc0_cmd */
- <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
- };
- /omit-if-no-ref/
- sdmmc0_det: sdmmc0-det {
- rockchip,pins =
- <0 RK_PA3 1 &pcfg_pull_none>;
- };
- /omit-if-no-ref/
- sdmmc0_pwr: sdmmc0-pwr {
- rockchip,pins =
- <0 RK_PC0 1 &pcfg_pull_none>;
- };
- };
- sdmmc1 {
- /omit-if-no-ref/
- sdmmc1_bus4: sdmmc1-bus4 {
- rockchip,pins =
- /* sdmmc1_d0 */
- <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>,
- /* sdmmc1_d1 */
- <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>,
- /* sdmmc1_d2 */
- <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>,
- /* sdmmc1_d3 */
- <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>;
- };
- /omit-if-no-ref/
- sdmmc1_clk: sdmmc1-clk {
- rockchip,pins =
- /* sdmmc1_clk */
- <1 RK_PB2 1 &pcfg_pull_up_drv_level_2>;
- };
- /omit-if-no-ref/
- sdmmc1_cmd: sdmmc1-cmd {
- rockchip,pins =
- /* sdmmc1_cmd */
- <1 RK_PB3 1 &pcfg_pull_up_drv_level_2>;
- };
- /omit-if-no-ref/
- sdmmc1_det: sdmmc1-det {
- rockchip,pins =
- <1 RK_PD0 2 &pcfg_pull_none>;
- };
- /omit-if-no-ref/
- sdmmc1_pwr: sdmmc1-pwr {
- rockchip,pins =
- <1 RK_PD1 2 &pcfg_pull_none>;
- };
- };
- uart0 {
- /omit-if-no-ref/
- uart0_xfer: uart0-xfer {
- rockchip,pins =
- /* uart0_rx */
- <1 RK_PC2 1 &pcfg_pull_up>,
- /* uart0_tx */
- <1 RK_PC3 1 &pcfg_pull_up>;
- };
- /omit-if-no-ref/
- uart0_ctsn: uart0-ctsn {
- rockchip,pins =
- <1 RK_PC1 1 &pcfg_pull_none>;
- };
- /omit-if-no-ref/
- uart0_rtsn: uart0-rtsn {
- rockchip,pins =
- <1 RK_PC0 1 &pcfg_pull_none>;
- };
- /omit-if-no-ref/
- uart0_rtsn_gpio: uart0-rts-pin {
- rockchip,pins =
- <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
- uart1 {
- /omit-if-no-ref/
- uart1m0_xfer: uart1m0-xfer {
- rockchip,pins =
- /* uart1_rx_m0 */
- <0 RK_PB7 2 &pcfg_pull_up>,
- /* uart1_tx_m0 */
- <0 RK_PB6 2 &pcfg_pull_up>;
- };
- };
- uart2 {
- /omit-if-no-ref/
- uart2m1_xfer: uart2m1-xfer {
- rockchip,pins =
- /* uart2_rx_m1 */
- <3 RK_PA3 1 &pcfg_pull_up>,
- /* uart2_tx_m1 */
- <3 RK_PA2 1 &pcfg_pull_up>;
- };
- };
- uart3 {
- /omit-if-no-ref/
- uart3m0_xfer: uart3m0-xfer {
- rockchip,pins =
- /* uart3_rx_m0 */
- <3 RK_PC7 4 &pcfg_pull_up>,
- /* uart3_tx_m0 */
- <3 RK_PC6 4 &pcfg_pull_up>;
- };
- /omit-if-no-ref/
- uart3m2_xfer: uart3m2-xfer {
- rockchip,pins =
- /* uart3_rx_m2 */
- <3 RK_PA1 4 &pcfg_pull_up>,
- /* uart3_tx_m2 */
- <3 RK_PA0 4 &pcfg_pull_up>;
- };
- };
- uart4 {
- /omit-if-no-ref/
- uart4m0_xfer: uart4m0-xfer {
- rockchip,pins =
- /* uart4_rx_m0 */
- <3 RK_PA5 4 &pcfg_pull_up>,
- /* uart4_tx_m0 */
- <3 RK_PA4 4 &pcfg_pull_up>;
- };
- /omit-if-no-ref/
- uart4m2_xfer: uart4m2-xfer {
- rockchip,pins =
- /* uart4_rx_m2 */
- <1 RK_PD4 3 &pcfg_pull_up>,
- /* uart4_tx_m2 */
- <1 RK_PD5 3 &pcfg_pull_up>;
- };
- };
- uart5 {
- /omit-if-no-ref/
- uart5m0_xfer: uart5m0-xfer {
- rockchip,pins =
- /* uart5_rx_m0 */
- <3 RK_PA7 4 &pcfg_pull_up>,
- /* uart5_tx_m0 */
- <3 RK_PA6 4 &pcfg_pull_up>;
- };
- /omit-if-no-ref/
- uart5m2_xfer: uart5m2-xfer {
- rockchip,pins =
- /* uart5_rx_m2 */
- <2 RK_PA1 3 &pcfg_pull_up>,
- /* uart5_tx_m2 */
- <2 RK_PA0 3 &pcfg_pull_up>;
- };
- };
-};
diff --git a/arch/arm/dts/rv1126-sonoff-ihost.dts b/arch/arm/dts/rv1126-sonoff-ihost.dts
deleted file mode 100644
index 77386a4..0000000
--- a/arch/arm/dts/rv1126-sonoff-ihost.dts
+++ /dev/null
@@ -1,29 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
- */
-
-/dts-v1/;
-#include "rv1126.dtsi"
-#include "rv1126-sonoff-ihost.dtsi"
-
-/ {
- model = "Sonoff iHost 4G";
- compatible = "itead,sonoff-ihost", "rockchip,rv1126";
-};
-
-&cpu0 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu1 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu2 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu3 {
- cpu-supply = <&vdd_arm>;
-};
diff --git a/arch/arm/dts/rv1126-sonoff-ihost.dtsi b/arch/arm/dts/rv1126-sonoff-ihost.dtsi
deleted file mode 100644
index 32b329e..0000000
--- a/arch/arm/dts/rv1126-sonoff-ihost.dtsi
+++ /dev/null
@@ -1,404 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
- * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
- */
-
-/ {
- aliases {
- ethernet0 = &gmac;
- mmc0 = &emmc;
- };
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- vcc5v0_sys: regulator-vcc5v0-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- sdio_pwrseq: pwrseq-sdio {
- compatible = "mmc-pwrseq-simple";
- clocks = <&rk809 1>;
- clock-names = "ext_clock";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_enable_h>;
- reset-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>;
- };
-};
-
-&emmc {
- bus-width = <8>;
- cap-mmc-highspeed;
- mmc-hs200-1_8v;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_rstnout>;
- rockchip,default-sample-phase = <90>;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&vcc_1v8>;
- status = "okay";
-};
-
-&i2c0 {
- clock-frequency = <400000>;
- status = "okay";
-
- rk809: pmic@20 {
- compatible = "rockchip,rk809";
- reg = <0x20>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PB1 IRQ_TYPE_LEVEL_LOW>;
- #clock-cells = <1>;
- clock-output-names = "rk808-clkout1", "rk808-clkout2";
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int_l>;
- rockchip,system-power-controller;
- wakeup-source;
-
- vcc1-supply = <&vcc5v0_sys>;
- vcc2-supply = <&vcc5v0_sys>;
- vcc3-supply = <&vcc5v0_sys>;
- vcc4-supply = <&vcc5v0_sys>;
- vcc5-supply = <&vcc_buck5>;
- vcc6-supply = <&vcc_buck5>;
- vcc7-supply = <&vcc5v0_sys>;
- vcc8-supply = <&vcc3v3_sys>;
- vcc9-supply = <&vcc5v0_sys>;
-
- regulators {
- vdd_npu_vepu: DCDC_REG1 {
- regulator-name = "vdd_npu_vepu";
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <650000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <6001>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_arm: DCDC_REG2 {
- regulator-name = "vdd_arm";
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <725000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc3v3_sys: DCDC_REG4 {
- regulator-name = "vcc3v3_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc_buck5: DCDC_REG5 {
- regulator-name = "vcc_buck5";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <2200000>;
- regulator-max-microvolt = <2200000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <2200000>;
- };
- };
-
- vcc_0v8: LDO_REG1 {
- regulator-name = "vcc_0v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <800000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc1v8_pmu: LDO_REG2 {
- regulator-name = "vcc1v8_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vdd0v8_pmu: LDO_REG3 {
- regulator-name = "vcc0v8_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <800000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <800000>;
- };
- };
-
- vcc_1v8: LDO_REG4 {
- regulator-name = "vcc_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc_dovdd: LDO_REG5 {
- regulator-name = "vcc_dovdd";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_dvdd: LDO_REG6 {
- regulator-name = "vcc_dvdd";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_avdd: LDO_REG7 {
- regulator-name = "vcc_avdd";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vccio_sd: LDO_REG8 {
- regulator-name = "vccio_sd";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_sd: LDO_REG9 {
- regulator-name = "vcc3v3_sd";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_5v0: SWITCH_REG1 {
- regulator-name = "vcc_5v0";
- };
-
- vcc_3v3: SWITCH_REG2 {
- regulator-name = "vcc_3v3";
- regulator-always-on;
- regulator-boot-on;
- };
- };
- };
-};
-
-&i2c2 {
- status = "okay";
- clock-frequency = <400000>;
-
- pcf8563: rtc@51 {
- compatible = "nxp,pcf8563";
- reg = <0x51>;
- #clock-cells = <0>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
- clock-output-names = "xin32k";
- };
-};
-
-&gmac {
- assigned-clocks = <&cru CLK_GMAC_SRC_M1>, <&cru CLK_GMAC_SRC>,
- <&cru CLK_GMAC_TX_RX>;
- assigned-clock-parents = <&cru CLK_GMAC_RGMII_M1>, <&cru CLK_GMAC_SRC_M1>,
- <&cru RMII_MODE_CLK>;
- assigned-clock-rates = <0>, <50000000>;
- clock_in_out = "output";
- phy-handle = <&phy>;
- phy-mode = "rmii";
- phy-supply = <&vcc_3v3>;
- pinctrl-names = "default";
- pinctrl-0 = <&rgmiim1_miim &rgmiim1_rxer &rgmiim1_bus2 &rgmiim1_mclkinout>;
- status = "okay";
-};
-
-&mdio {
- phy: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0x0>;
- pinctrl-names = "default";
- pinctrl-0 = <ð_phy_rst>;
- reset-active-low;
- reset-assert-us = <50000>;
- reset-deassert-us = <10000>;
- reset-gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>;
- };
-};
-
-&pinctrl {
- ethernet {
- eth_phy_rst: eth-phy-rst {
- rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_down>;
- };
- };
- bt {
- bt_enable: bt-enable {
- rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_wake_dev: bt-wake-dev {
- rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_wake_host: bt-wake-host {
- rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pmic {
- pmic_int_l: pmic-int-l {
- rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- wifi {
- wifi_enable_h: wifi-enable-h {
- rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&pmu_io_domains {
- pmuio0-supply = <&vcc1v8_pmu>;
- pmuio1-supply = <&vcc3v3_sys>;
- vccio1-supply = <&vcc_1v8>;
- vccio2-supply = <&vccio_sd>;
- vccio3-supply = <&vcc_1v8>;
- vccio4-supply = <&vcc_dovdd>;
- vccio5-supply = <&vcc_1v8>;
- vccio6-supply = <&vcc_1v8>;
- vccio7-supply = <&vcc_dovdd>;
- status = "okay";
-};
-
-&saradc {
- vref-supply = <&vcc_1v8>;
- status = "okay";
-};
-
-&sdio {
- bus-width = <4>;
- cap-sd-highspeed;
- cap-sdio-irq;
- keep-power-in-suspend;
- max-frequency = <100000000>;
- mmc-pwrseq = <&sdio_pwrseq>;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>;
- rockchip,default-sample-phase = <90>;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc3v3_sys>;
- vqmmc-supply = <&vcc_1v8>;
- status = "okay";
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- card-detect-delay = <200>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_det>;
- rockchip,default-sample-phase = <90>;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr104;
- vqmmc-supply = <&vccio_sd>;
- status = "okay";
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer &uart0_ctsn &uart0_rtsn>;
- uart-has-rtscts;
- status = "okay";
-
- bluetooth {
- compatible = "realtek,rtl8723ds-bt";
- device-wake-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; /* BT_WAKE */
- enable-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; /* BT_RST */
- host-wake-gpios = <&gpio1 RK_PC5 GPIO_ACTIVE_HIGH>; /* BT_WAKE_HOST */
- max-speed = <2000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&bt_enable>, <&bt_wake_dev>, <&bt_wake_host>;
- };
-};
-
-&uart2 {
- status = "okay";
-};
-
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart3m2_xfer>;
- status = "okay";
-};
-
-&uart4 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart4m2_xfer>;
- status = "okay";
-};
diff --git a/arch/arm/dts/rv1126.dtsi b/arch/arm/dts/rv1126.dtsi
deleted file mode 100644
index bb603ca..0000000
--- a/arch/arm/dts/rv1126.dtsi
+++ /dev/null
@@ -1,623 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
- */
-
-#include <dt-bindings/clock/rockchip,rv1126-cru.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/power/rockchip,rv1126-power.h>
-#include <dt-bindings/soc/rockchip,boot-mode.h>
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- compatible = "rockchip,rv1126";
-
- interrupt-parent = <&gic>;
-
- aliases {
- i2c0 = &i2c0;
- i2c2 = &i2c2;
- serial0 = &uart0;
- serial1 = &uart1;
- serial2 = &uart2;
- serial3 = &uart3;
- serial4 = &uart4;
- serial5 = &uart5;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@f00 {
- device_type = "cpu";
- compatible = "arm,cortex-a7";
- reg = <0xf00>;
- enable-method = "psci";
- clocks = <&cru ARMCLK>;
- };
-
- cpu1: cpu@f01 {
- device_type = "cpu";
- compatible = "arm,cortex-a7";
- reg = <0xf01>;
- enable-method = "psci";
- clocks = <&cru ARMCLK>;
- };
-
- cpu2: cpu@f02 {
- device_type = "cpu";
- compatible = "arm,cortex-a7";
- reg = <0xf02>;
- enable-method = "psci";
- clocks = <&cru ARMCLK>;
- };
-
- cpu3: cpu@f03 {
- device_type = "cpu";
- compatible = "arm,cortex-a7";
- reg = <0xf03>;
- enable-method = "psci";
- clocks = <&cru ARMCLK>;
- };
- };
-
- arm-pmu {
- compatible = "arm,cortex-a7-pmu";
- interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
- };
-
- psci {
- compatible = "arm,psci-1.0";
- method = "smc";
- };
-
- timer {
- compatible = "arm,armv7-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
- clock-frequency = <24000000>;
- };
-
- display_subsystem {
- compatible = "rockchip,display-subsystem";
- ports = <&vop_out>;
- };
-
- xin24m: oscillator {
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- clock-output-names = "xin24m";
- #clock-cells = <0>;
- };
-
- grf: syscon@fe000000 {
- compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd";
- reg = <0xfe000000 0x20000>;
- };
-
- pmugrf: syscon@fe020000 {
- compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd";
- reg = <0xfe020000 0x1000>;
-
- pmu_io_domains: io-domains {
- compatible = "rockchip,rv1126-pmu-io-voltage-domain";
- status = "disabled";
- };
- };
-
- qos_emmc: qos@fe860000 {
- compatible = "rockchip,rv1126-qos", "syscon";
- reg = <0xfe860000 0x20>;
- };
-
- qos_nandc: qos@fe860080 {
- compatible = "rockchip,rv1126-qos", "syscon";
- reg = <0xfe860080 0x20>;
- };
-
- qos_sfc: qos@fe860200 {
- compatible = "rockchip,rv1126-qos", "syscon";
- reg = <0xfe860200 0x20>;
- };
-
- qos_sdio: qos@fe86c000 {
- compatible = "rockchip,rv1126-qos", "syscon";
- reg = <0xfe86c000 0x20>;
- };
-
- qos_iep: qos@fe8a0000 {
- compatible = "rockchip,rv1126-qos", "syscon";
- reg = <0xfe8a0000 0x20>;
- };
-
- qos_rga_rd: qos@fe8a0080 {
- compatible = "rockchip,rv1126-qos", "syscon";
- reg = <0xfe8a0080 0x20>;
- };
-
- qos_rga_wr: qos@fe8a0100 {
- compatible = "rockchip,rv1126-qos", "syscon";
- reg = <0xfe8a0100 0x20>;
- };
-
- qos_vop: qos@fe8a0180 {
- compatible = "rockchip,rv1126-qos", "syscon";
- reg = <0xfe8a0180 0x20>;
- };
-
- gic: interrupt-controller@feff0000 {
- compatible = "arm,gic-400";
- interrupt-controller;
- #interrupt-cells = <3>;
- #address-cells = <0>;
-
- reg = <0xfeff1000 0x1000>,
- <0xfeff2000 0x2000>,
- <0xfeff4000 0x2000>,
- <0xfeff6000 0x2000>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
- };
-
- pmu: power-management@ff3e0000 {
- compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd";
- reg = <0xff3e0000 0x1000>;
-
- power: power-controller {
- compatible = "rockchip,rv1126-power-controller";
- #power-domain-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- power-domain@RV1126_PD_NVM {
- reg = <RV1126_PD_NVM>;
- clocks = <&cru HCLK_EMMC>,
- <&cru CLK_EMMC>,
- <&cru HCLK_NANDC>,
- <&cru CLK_NANDC>,
- <&cru HCLK_SFC>,
- <&cru HCLK_SFCXIP>,
- <&cru SCLK_SFC>;
- pm_qos = <&qos_emmc>,
- <&qos_nandc>,
- <&qos_sfc>;
- #power-domain-cells = <0>;
- };
-
- power-domain@RV1126_PD_SDIO {
- reg = <RV1126_PD_SDIO>;
- clocks = <&cru HCLK_SDIO>,
- <&cru CLK_SDIO>;
- pm_qos = <&qos_sdio>;
- #power-domain-cells = <0>;
- };
-
- power-domain@RV1126_PD_VO {
- reg = <RV1126_PD_VO>;
- clocks = <&cru ACLK_RGA>,
- <&cru HCLK_RGA>,
- <&cru CLK_RGA_CORE>,
- <&cru ACLK_VOP>,
- <&cru HCLK_VOP>,
- <&cru DCLK_VOP>,
- <&cru PCLK_DSIHOST>,
- <&cru ACLK_IEP>,
- <&cru HCLK_IEP>,
- <&cru CLK_IEP_CORE>;
- pm_qos = <&qos_rga_rd>,
- <&qos_rga_wr>,
- <&qos_vop>,
- <&qos_iep>;
- #power-domain-cells = <0>;
- };
- };
- };
-
- i2c0: i2c@ff3f0000 {
- compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
- reg = <0xff3f0000 0x1000>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- rockchip,grf = <&pmugrf>;
- clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
- clock-names = "i2c", "pclk";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_xfer>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c2: i2c@ff400000 {
- compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
- reg = <0xff400000 0x1000>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- rockchip,grf = <&pmugrf>;
- clocks = <&pmucru CLK_I2C2>, <&pmucru PCLK_I2C2>;
- clock-names = "i2c", "pclk";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_xfer>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- uart1: serial@ff410000 {
- compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
- reg = <0xff410000 0x100>;
- interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <24000000>;
- clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac 7>, <&dmac 6>;
- dma-names = "tx", "rx";
- pinctrl-names = "default";
- pinctrl-0 = <&uart1m0_xfer>;
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
-
- pwm2: pwm@ff430020 {
- compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
- reg = <0xff430020 0x10>;
- clock-names = "pwm", "pclk";
- clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pwm2m0_pins>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pmucru: clock-controller@ff480000 {
- compatible = "rockchip,rv1126-pmucru";
- reg = <0xff480000 0x1000>;
- rockchip,grf = <&grf>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- cru: clock-controller@ff490000 {
- compatible = "rockchip,rv1126-cru";
- reg = <0xff490000 0x1000>;
- clocks = <&xin24m>;
- clock-names = "xin24m";
- rockchip,grf = <&grf>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- dmac: dma-controller@ff4e0000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0xff4e0000 0x4000>;
- interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
- #dma-cells = <1>;
- arm,pl330-periph-burst;
- clocks = <&cru ACLK_DMAC>;
- clock-names = "apb_pclk";
- };
-
- pwm11: pwm@ff550030 {
- compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
- reg = <0xff550030 0x10>;
- clock-names = "pwm", "pclk";
- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
- pinctrl-0 = <&pwm11m0_pins>;
- pinctrl-names = "default";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- uart0: serial@ff560000 {
- compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
- reg = <0xff560000 0x100>;
- interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <24000000>;
- clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac 5>, <&dmac 4>;
- dma-names = "tx", "rx";
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer>;
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
-
- uart2: serial@ff570000 {
- compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
- reg = <0xff570000 0x100>;
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <24000000>;
- clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac 9>, <&dmac 8>;
- dma-names = "tx", "rx";
- pinctrl-names = "default";
- pinctrl-0 = <&uart2m1_xfer>;
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
-
- uart3: serial@ff580000 {
- compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
- reg = <0xff580000 0x100>;
- interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <24000000>;
- clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac 11>, <&dmac 10>;
- dma-names = "tx", "rx";
- pinctrl-names = "default";
- pinctrl-0 = <&uart3m0_xfer>;
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
-
- uart4: serial@ff590000 {
- compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
- reg = <0xff590000 0x100>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <24000000>;
- clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac 13>, <&dmac 12>;
- dma-names = "tx", "rx";
- pinctrl-names = "default";
- pinctrl-0 = <&uart4m0_xfer>;
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
-
- uart5: serial@ff5a0000 {
- compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
- reg = <0xff5a0000 0x100>;
- interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <24000000>;
- clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac 15>, <&dmac 14>;
- dma-names = "tx", "rx";
- pinctrl-names = "default";
- pinctrl-0 = <&uart5m0_xfer>;
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
-
- saradc: adc@ff5e0000 {
- compatible = "rockchip,rv1126-saradc", "rockchip,rk3399-saradc";
- reg = <0xff5e0000 0x100>;
- interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
- #io-channel-cells = <1>;
- clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
- clock-names = "saradc", "apb_pclk";
- resets = <&cru SRST_SARADC_P>;
- reset-names = "saradc-apb";
- status = "disabled";
- };
-
- timer0: timer@ff660000 {
- compatible = "rockchip,rv1126-timer", "rockchip,rk3288-timer";
- reg = <0xff660000 0x20>;
- interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>;
- clock-names = "pclk", "timer";
- };
-
- vop: vop@ffb00000 {
- compatible = "rockchip,rv1126-vop";
- reg = <0xffb00000 0x200>, <0xffb00a00 0x400>;
- interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
- clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
- reset-names = "axi", "ahb", "dclk";
- resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
- iommus = <&vop_mmu>;
- power-domains = <&power RV1126_PD_VO>;
- status = "disabled";
-
- vop_out: port {
- #address-cells = <1>;
- #size-cells = <0>;
-
- vop_out_rgb: endpoint@0 {
- reg = <0>;
- };
-
- vop_out_dsi: endpoint@1 {
- reg = <1>;
- };
- };
- };
-
- vop_mmu: iommu@ffb00f00 {
- compatible = "rockchip,iommu";
- reg = <0xffb00f00 0x100>;
- interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "aclk", "iface";
- clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
- #iommu-cells = <0>;
- power-domains = <&power RV1126_PD_VO>;
- status = "disabled";
- };
-
- gmac: ethernet@ffc40000 {
- compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a";
- reg = <0xffc40000 0x4000>;
- interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq", "eth_wake_irq";
- rockchip,grf = <&grf>;
- clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>,
- <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_REF>,
- <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
- <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_PTPREF>;
- clock-names = "stmmaceth", "mac_clk_rx",
- "mac_clk_tx", "clk_mac_ref",
- "aclk_mac", "pclk_mac",
- "clk_mac_speed", "ptp_ref";
- resets = <&cru SRST_GMAC_A>;
- reset-names = "stmmaceth";
-
- snps,mixed-burst;
- snps,tso;
-
- snps,axi-config = <&stmmac_axi_setup>;
- snps,mtl-rx-config = <&mtl_rx_setup>;
- snps,mtl-tx-config = <&mtl_tx_setup>;
- status = "disabled";
-
- mdio: mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <0x1>;
- #size-cells = <0x0>;
- };
-
- stmmac_axi_setup: stmmac-axi-config {
- snps,wr_osr_lmt = <4>;
- snps,rd_osr_lmt = <8>;
- snps,blen = <0 0 0 0 16 8 4>;
- };
-
- mtl_rx_setup: rx-queues-config {
- snps,rx-queues-to-use = <1>;
- queue0 {};
- };
-
- mtl_tx_setup: tx-queues-config {
- snps,tx-queues-to-use = <1>;
- queue0 {};
- };
- };
-
- emmc: mmc@ffc50000 {
- compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
- reg = <0xffc50000 0x4000>;
- interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>,
- <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
- fifo-depth = <0x100>;
- max-frequency = <200000000>;
- power-domains = <&power RV1126_PD_NVM>;
- status = "disabled";
- };
-
- sdmmc: mmc@ffc60000 {
- compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
- reg = <0xffc60000 0x4000>;
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>,
- <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
- fifo-depth = <0x100>;
- max-frequency = <200000000>;
- status = "disabled";
- };
-
- sdio: mmc@ffc70000 {
- compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
- reg = <0xffc70000 0x4000>;
- interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>,
- <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
- fifo-depth = <0x100>;
- max-frequency = <200000000>;
- power-domains = <&power RV1126_PD_SDIO>;
- status = "disabled";
- };
-
- sfc: spi@ffc90000 {
- compatible = "rockchip,sfc";
- reg = <0xffc90000 0x4000>;
- interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
- assigned-clocks = <&cru SCLK_SFC>;
- assigned-clock-rates = <80000000>;
- clock-names = "clk_sfc", "hclk_sfc";
- clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
- power-domains = <&power RV1126_PD_NVM>;
- status = "disabled";
- };
-
- pinctrl: pinctrl {
- compatible = "rockchip,rv1126-pinctrl";
- rockchip,grf = <&grf>;
- rockchip,pmu = <&pmugrf>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- gpio0: gpio@ff460000 {
- compatible = "rockchip,gpio-bank";
- reg = <0xff460000 0x100>;
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio1: gpio@ff620000 {
- compatible = "rockchip,gpio-bank";
- reg = <0xff620000 0x100>;
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio2: gpio@ff630000 {
- compatible = "rockchip,gpio-bank";
- reg = <0xff630000 0x100>;
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio3: gpio@ff640000 {
- compatible = "rockchip,gpio-bank";
- reg = <0xff640000 0x100>;
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio4: gpio@ff650000 {
- compatible = "rockchip,gpio-bank";
- reg = <0xff650000 0x100>;
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
- };
-};
-
-#include "rv1126-pinctrl.dtsi"
diff --git a/arch/arm/dts/salvator-common.dtsi b/arch/arm/dts/salvator-common.dtsi
deleted file mode 100644
index 4a3d503..0000000
--- a/arch/arm/dts/salvator-common.dtsi
+++ /dev/null
@@ -1,1104 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for common parts of Salvator-X board variants
- *
- * Copyright (C) 2015-2016 Renesas Electronics Corp.
- */
-
-/*
- * SSI-AK4613
- *
- * This command is required when Playback/Capture
- *
- * amixer set "DVC Out" 100%
- * amixer set "DVC In" 100%
- *
- * You can use Mute
- *
- * amixer set "DVC Out Mute" on
- * amixer set "DVC In Mute" on
- *
- * You can use Volume Ramp
- *
- * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
- * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
- * amixer set "DVC Out Ramp" on
- * aplay xxx.wav &
- * amixer set "DVC Out" 80% // Volume Down
- * amixer set "DVC Out" 100% // Volume Up
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
- aliases {
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- i2c4 = &i2c4;
- i2c5 = &i2c5;
- i2c6 = &i2c6;
- i2c7 = &i2c_dvfs;
- serial0 = &scif2;
- serial1 = &hscif1;
- ethernet0 = &avb;
- mmc0 = &sdhi2;
- mmc1 = &sdhi0;
- mmc2 = &sdhi3;
- };
-
- chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
- stdout-path = "serial0:115200n8";
- };
-
- audio_clkout: audio-clkout {
- /*
- * This is same as <&rcar_sound 0>
- * but needed to avoid cs2000/rcar_sound probe dead-lock
- */
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <12288000>;
- };
-
- backlight: backlight {
- compatible = "pwm-backlight";
- pwms = <&pwm1 0 50000>;
-
- brightness-levels = <256 128 64 16 8 4 0>;
- default-brightness-level = <6>;
-
- power-supply = <®_12v>;
- enable-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
- };
-
- cvbs-in {
- compatible = "composite-video-connector";
- label = "CVBS IN";
-
- port {
- cvbs_con: endpoint {
- remote-endpoint = <&adv7482_ain7>;
- };
- };
- };
-
- hdmi-in {
- compatible = "hdmi-connector";
- label = "HDMI IN";
- type = "a";
-
- port {
- hdmi_in_con: endpoint {
- remote-endpoint = <&adv7482_hdmi>;
- };
- };
- };
-
- hdmi0-out {
- compatible = "hdmi-connector";
- label = "HDMI0 OUT";
- type = "a";
-
- port {
- hdmi0_con: endpoint {
- remote-endpoint = <&rcar_dw_hdmi0_out>;
- };
- };
- };
-
- hdmi1-out {
- compatible = "hdmi-connector";
- label = "HDMI1 OUT";
- type = "a";
-
- port {
- hdmi1_con: endpoint {
- };
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- pinctrl-0 = <&keys_pins>;
- pinctrl-names = "default";
-
- key-1 {
- gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_1>;
- label = "SW4-1";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-2 {
- gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_2>;
- label = "SW4-2";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-3 {
- gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_3>;
- label = "SW4-3";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-4 {
- gpios = <&gpio5 23 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_4>;
- label = "SW4-4";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-a {
- gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_A>;
- label = "TSW0";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-b {
- gpios = <&gpio6 12 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_B>;
- label = "TSW1";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-c {
- gpios = <&gpio6 13 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_C>;
- label = "TSW2";
- wakeup-source;
- debounce-interval = <20>;
- };
- };
-
- reg_1p8v: regulator-1p8v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- reg_3p3v: regulator-3p3v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- reg_12v: regulator-12v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-12V";
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- sound_card: sound {
- compatible = "audio-graph-card";
-
- label = "rcar-sound";
-
- dais = <&rsnd_port0 /* ak4613 */
- &rsnd_port1 /* HDMI0 */
-#ifdef SOC_HAS_HDMI1
- &rsnd_port2 /* HDMI1 */
-#endif
- >;
- };
-
- vbus0_usb2: regulator-vbus0-usb2 {
- compatible = "regulator-fixed";
-
- regulator-name = "USB20_VBUS0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
-
- gpio = <&gpio6 16 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vcc_sdhi0: regulator-vcc-sdhi0 {
- compatible = "regulator-fixed";
-
- regulator-name = "SDHI0 Vcc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vccq_sdhi0: regulator-vccq-sdhi0 {
- compatible = "regulator-gpio";
-
- regulator-name = "SDHI0 VccQ";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
- gpios-states = <1>;
- states = <3300000 1>, <1800000 0>;
- };
-
- vcc_sdhi3: regulator-vcc-sdhi3 {
- compatible = "regulator-fixed";
-
- regulator-name = "SDHI3 Vcc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vccq_sdhi3: regulator-vccq-sdhi3 {
- compatible = "regulator-gpio";
-
- regulator-name = "SDHI3 VccQ";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
- gpios-states = <1>;
- states = <3300000 1>, <1800000 0>;
- };
-
- vga {
- compatible = "vga-connector";
-
- port {
- vga_in: endpoint {
- remote-endpoint = <&adv7123_out>;
- };
- };
- };
-
- vga-encoder {
- compatible = "adi,adv7123";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- adv7123_in: endpoint {
- remote-endpoint = <&du_out_rgb>;
- };
- };
- port@1 {
- reg = <1>;
- adv7123_out: endpoint {
- remote-endpoint = <&vga_in>;
- };
- };
- };
- };
-
- x12_clk: x12 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24576000>;
- };
-
- /* External DU dot clocks */
- x21_clk: x21-clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <33000000>;
- };
-
- x22_clk: x22-clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <33000000>;
- };
-
- x23_clk: x23-clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <25000000>;
- };
-};
-
-&a57_0 {
- cpu-supply = <&dvfs>;
-};
-
-&audio_clk_a {
- clock-frequency = <22579200>;
-};
-
-&avb {
- pinctrl-0 = <&avb_pins>;
- pinctrl-names = "default";
- phy-handle = <&phy0>;
- tx-internal-delay-ps = <2000>;
- status = "okay";
-
- phy0: ethernet-phy@0 {
- compatible = "ethernet-phy-id0022.1622",
- "ethernet-phy-ieee802.3-c22";
- rxc-skew-ps = <1500>;
- reg = <0>;
- interrupt-parent = <&gpio2>;
- interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
- reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
- };
-};
-
-&csi20 {
- status = "okay";
-
- ports {
- port@0 {
- csi20_in: endpoint {
- clock-lanes = <0>;
- data-lanes = <1>;
- remote-endpoint = <&adv7482_txb>;
- };
- };
- };
-};
-
-&csi40 {
- status = "okay";
-
- ports {
- port@0 {
- csi40_in: endpoint {
- clock-lanes = <0>;
- data-lanes = <1 2 3 4>;
- remote-endpoint = <&adv7482_txa>;
- };
- };
- };
-};
-
-&du {
- pinctrl-0 = <&du_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- ports {
- port@0 {
- du_out_rgb: endpoint {
- remote-endpoint = <&adv7123_in>;
- };
- };
- };
-};
-
-&ehci0 {
- dr_mode = "otg";
- status = "okay";
-};
-
-&ehci1 {
- status = "okay";
-};
-
-&extalr_clk {
- clock-frequency = <32768>;
-};
-
-&hdmi0 {
- status = "okay";
-
- ports {
- port@1 {
- reg = <1>;
- rcar_dw_hdmi0_out: endpoint {
- remote-endpoint = <&hdmi0_con>;
- };
- };
- port@2 {
- reg = <2>;
- dw_hdmi0_snd_in: endpoint {
- remote-endpoint = <&rsnd_endpoint1>;
- };
- };
- };
-};
-
-#ifdef SOC_HAS_HDMI1
-&hdmi1 {
- status = "okay";
-
- ports {
- port@1 {
- reg = <1>;
- rcar_dw_hdmi1_out: endpoint {
- remote-endpoint = <&hdmi1_con>;
- };
- };
- port@2 {
- reg = <2>;
- dw_hdmi1_snd_in: endpoint {
- remote-endpoint = <&rsnd_endpoint2>;
- };
- };
- };
-};
-
-&hdmi1_con {
- remote-endpoint = <&rcar_dw_hdmi1_out>;
-};
-#endif /* SOC_HAS_HDMI1 */
-
-&hscif1 {
- pinctrl-0 = <&hscif1_pins>;
- pinctrl-names = "default";
-
- uart-has-rtscts;
- /* Please only enable hscif1 or scif1 */
- status = "okay";
-};
-
-&hsusb {
- dr_mode = "otg";
- status = "okay";
-};
-
-&i2c2 {
- pinctrl-0 = <&i2c2_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-
- clock-frequency = <100000>;
-
- ak4613: codec@10 {
- compatible = "asahi-kasei,ak4613";
- #sound-dai-cells = <0>;
- reg = <0x10>;
- clocks = <&rcar_sound 3>;
-
- asahi-kasei,in1-single-end;
- asahi-kasei,in2-single-end;
- asahi-kasei,out1-single-end;
- asahi-kasei,out2-single-end;
- asahi-kasei,out3-single-end;
- asahi-kasei,out4-single-end;
- asahi-kasei,out5-single-end;
- asahi-kasei,out6-single-end;
-
- port {
- ak4613_endpoint: endpoint {
- remote-endpoint = <&rsnd_endpoint0>;
- };
- };
- };
-
- cs2000: clk_multiplier@4f {
- #clock-cells = <0>;
- compatible = "cirrus,cs2000-cp";
- reg = <0x4f>;
- clocks = <&audio_clkout>, <&x12_clk>;
- clock-names = "clk_in", "ref_clk";
-
- assigned-clocks = <&cs2000>;
- assigned-clock-rates = <24576000>; /* 1/1 divide */
- };
-};
-
-&i2c4 {
- status = "okay";
-
- pca9654: gpio@20 {
- compatible = "onnn,pca9654";
- reg = <0x20>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- video-receiver@70 {
- compatible = "adi,adv7482";
- reg = <0x70 0x71 0x72 0x73 0x74 0x75
- 0x60 0x61 0x62 0x63 0x64 0x65>;
- reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater",
- "infoframe", "cbus", "cec", "sdp", "txa", "txb" ;
-
- interrupt-parent = <&gpio6>;
- interrupt-names = "intrq1", "intrq2";
- interrupts = <30 IRQ_TYPE_LEVEL_LOW>,
- <31 IRQ_TYPE_LEVEL_LOW>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@7 {
- reg = <7>;
-
- adv7482_ain7: endpoint {
- remote-endpoint = <&cvbs_con>;
- };
- };
-
- port@8 {
- reg = <8>;
-
- adv7482_hdmi: endpoint {
- remote-endpoint = <&hdmi_in_con>;
- };
- };
-
- port@a {
- reg = <10>;
-
- adv7482_txa: endpoint {
- clock-lanes = <0>;
- data-lanes = <1 2 3 4>;
- remote-endpoint = <&csi40_in>;
- };
- };
-
- port@b {
- reg = <11>;
-
- adv7482_txb: endpoint {
- clock-lanes = <0>;
- data-lanes = <1>;
- remote-endpoint = <&csi20_in>;
- };
- };
- };
- };
-
- csa_vdd: adc@7c {
- compatible = "maxim,max9611";
- reg = <0x7c>;
-
- shunt-resistor-micro-ohms = <5000>;
- };
-
- csa_dvfs: adc@7f {
- compatible = "maxim,max9611";
- reg = <0x7f>;
-
- shunt-resistor-micro-ohms = <5000>;
- };
-};
-
-&i2c_dvfs {
- status = "okay";
-
- clock-frequency = <400000>;
-
- pmic: pmic@30 {
- pinctrl-0 = <&irq0_pins>;
- pinctrl-names = "default";
-
- compatible = "rohm,bd9571mwv";
- reg = <0x30>;
- interrupt-parent = <&intc_ex>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-controller;
- #gpio-cells = <2>;
- rohm,ddr-backup-power = <0xf>;
- rohm,rstbmode-level;
-
- regulators {
- dvfs: dvfs {
- regulator-name = "dvfs";
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1030000>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
-
- eeprom@50 {
- compatible = "rohm,br24t01", "atmel,24c01";
- reg = <0x50>;
- pagesize = <8>;
- };
-};
-
-&ohci0 {
- dr_mode = "otg";
- status = "okay";
-};
-
-&ohci1 {
- status = "okay";
-};
-
-&pcie_bus_clk {
- clock-frequency = <100000000>;
-};
-
-&pciec0 {
- status = "okay";
-};
-
-&pciec1 {
- status = "okay";
-};
-
-&pfc {
- pinctrl-0 = <&scif_clk_pins>;
- pinctrl-names = "default";
-
- avb_pins: avb {
- mux {
- groups = "avb_link", "avb_mdio", "avb_mii";
- function = "avb";
- };
-
- pins_mdio {
- groups = "avb_mdio";
- drive-strength = <24>;
- };
-
- pins_mii_tx {
- pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
- "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
- drive-strength = <12>;
- };
- };
-
- du_pins: du {
- groups = "du_rgb888", "du_sync", "du_oddf", "du_clk_out_0";
- function = "du";
- };
-
- hscif1_pins: hscif1 {
- groups = "hscif1_data_a", "hscif1_ctrl_a";
- function = "hscif1";
- };
-
- i2c2_pins: i2c2 {
- groups = "i2c2_a";
- function = "i2c2";
- };
-
- irq0_pins: irq0 {
- groups = "intc_ex_irq0";
- function = "intc_ex";
- };
-
- keys_pins: keys {
- pins = "GP_5_17", "GP_5_20", "GP_5_22";
- bias-pull-up;
- };
-
- pwm1_pins: pwm1 {
- groups = "pwm1_a";
- function = "pwm1";
- };
-
- scif1_pins: scif1 {
- groups = "scif1_data_a", "scif1_ctrl";
- function = "scif1";
- };
-
- scif2_pins: scif2 {
- groups = "scif2_data_a";
- function = "scif2";
- };
-
- scif_clk_pins: scif_clk {
- groups = "scif_clk_a";
- function = "scif_clk";
- };
-
- sdhi0_pins: sd0 {
- groups = "sdhi0_data4", "sdhi0_ctrl";
- function = "sdhi0";
- power-source = <3300>;
- };
-
- sdhi0_pins_uhs: sd0_uhs {
- groups = "sdhi0_data4", "sdhi0_ctrl";
- function = "sdhi0";
- power-source = <1800>;
- };
-
- sdhi2_pins: sd2 {
- groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
- function = "sdhi2";
- power-source = <1800>;
- };
-
- sdhi3_pins: sd3 {
- groups = "sdhi3_data4", "sdhi3_ctrl";
- function = "sdhi3";
- power-source = <3300>;
- };
-
- sdhi3_pins_uhs: sd3_uhs {
- groups = "sdhi3_data4", "sdhi3_ctrl";
- function = "sdhi3";
- power-source = <1800>;
- };
-
- sound_pins: sound {
- groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
- function = "ssi";
- };
-
- sound_clk_pins: sound_clk {
- groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a",
- "audio_clkout_a", "audio_clkout3_a";
- function = "audio_clk";
- };
-
- usb0_pins: usb0 {
- groups = "usb0";
- function = "usb0";
- };
-
- usb1_pins: usb1 {
- mux {
- groups = "usb1";
- function = "usb1";
- };
-
- ovc {
- pins = "GP_6_27";
- bias-pull-up;
- };
-
- pwen {
- pins = "GP_6_26";
- bias-pull-down;
- };
- };
-
- usb30_pins: usb30 {
- groups = "usb30";
- function = "usb30";
- };
-};
-
-&pwm1 {
- pinctrl-0 = <&pwm1_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&rcar_sound {
- pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
- pinctrl-names = "default";
-
- /* audio_clkout0/1/2/3 */
- #clock-cells = <1>;
- clock-frequency = <12288000 11289600>;
-
- status = "okay";
-
- /* update <audio_clk_b> to <cs2000> */
- clocks = <&cpg CPG_MOD 1005>,
- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
- <&audio_clk_a>, <&cs2000>,
- <&audio_clk_c>,
- <&cpg CPG_CORE CPG_AUDIO_CLK_I>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- rsnd_port0: port@0 {
- reg = <0>;
- rsnd_endpoint0: endpoint {
- remote-endpoint = <&ak4613_endpoint>;
-
- dai-format = "left_j";
- bitclock-master = <&rsnd_endpoint0>;
- frame-master = <&rsnd_endpoint0>;
-
- playback = <&ssi0>, <&src0>, <&dvc0>;
- capture = <&ssi1>, <&src1>, <&dvc1>;
- };
- };
-
- rsnd_port1: port@1 {
- reg = <1>;
- rsnd_endpoint1: endpoint {
- remote-endpoint = <&dw_hdmi0_snd_in>;
-
- dai-format = "i2s";
- bitclock-master = <&rsnd_endpoint1>;
- frame-master = <&rsnd_endpoint1>;
-
- playback = <&ssi2>;
- };
- };
-
-#ifdef SOC_HAS_HDMI1
- rsnd_port2: port@2 {
- reg = <2>;
- rsnd_endpoint2: endpoint {
- remote-endpoint = <&dw_hdmi1_snd_in>;
-
- dai-format = "i2s";
- bitclock-master = <&rsnd_endpoint2>;
- frame-master = <&rsnd_endpoint2>;
-
- playback = <&ssi3>;
- };
- };
-#endif /* SOC_HAS_HDMI1 */
- };
-};
-
-&rpc {
- /* Left disabled. To be enabled by firmware when unlocked. */
-
- flash@0 {
- compatible = "cypress,hyperflash", "cfi-flash";
- reg = <0>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- bootparam@0 {
- reg = <0x00000000 0x040000>;
- read-only;
- };
- bl2@40000 {
- reg = <0x00040000 0x140000>;
- read-only;
- };
- cert_header_sa6@180000 {
- reg = <0x00180000 0x040000>;
- read-only;
- };
- bl31@1c0000 {
- reg = <0x001c0000 0x040000>;
- read-only;
- };
- tee@200000 {
- reg = <0x00200000 0x440000>;
- read-only;
- };
- uboot@640000 {
- reg = <0x00640000 0x100000>;
- read-only;
- };
- dtb@740000 {
- reg = <0x00740000 0x080000>;
- };
- kernel@7c0000 {
- reg = <0x007c0000 0x1400000>;
- };
- user@1bc0000 {
- reg = <0x01bc0000 0x2440000>;
- };
- };
- };
-};
-
-&rwdt {
- timeout-sec = <60>;
- status = "okay";
-};
-
-#ifdef SOC_HAS_SATA
-&sata {
- status = "okay";
-};
-#endif /* SOC_HAS_SATA */
-
-&scif1 {
- pinctrl-0 = <&scif1_pins>;
- pinctrl-names = "default";
-
- uart-has-rtscts;
- /* Please only enable hscif1 or scif1 */
- /* status = "okay"; */
-};
-
-&scif2 {
- pinctrl-0 = <&scif2_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&scif_clk {
- clock-frequency = <14745600>;
-};
-
-&sdhi0 {
- pinctrl-0 = <&sdhi0_pins>;
- pinctrl-1 = <&sdhi0_pins_uhs>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <&vcc_sdhi0>;
- vqmmc-supply = <&vccq_sdhi0>;
- cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
- wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
- bus-width = <4>;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
- status = "okay";
-};
-
-&sdhi2 {
- /* used for on-board 8bit eMMC */
- pinctrl-0 = <&sdhi2_pins>;
- pinctrl-1 = <&sdhi2_pins>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <®_3p3v>;
- vqmmc-supply = <®_1p8v>;
- bus-width = <8>;
- mmc-hs200-1_8v;
- mmc-hs400-1_8v;
- no-sd;
- no-sdio;
- non-removable;
- fixed-emmc-driver-type = <1>;
- full-pwr-cycle-in-suspend;
- status = "okay";
-};
-
-&sdhi3 {
- pinctrl-0 = <&sdhi3_pins>;
- pinctrl-1 = <&sdhi3_pins_uhs>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <&vcc_sdhi3>;
- vqmmc-supply = <&vccq_sdhi3>;
- cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
- wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
- bus-width = <4>;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
- status = "okay";
-};
-
-&ssi1 {
- shared-pin;
-};
-
-&usb_extal_clk {
- clock-frequency = <50000000>;
-};
-
-&usb2_phy0 {
- pinctrl-0 = <&usb0_pins>;
- pinctrl-names = "default";
-
- vbus-supply = <&vbus0_usb2>;
- status = "okay";
-};
-
-&usb2_phy1 {
- pinctrl-0 = <&usb1_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&usb3_peri0 {
- phys = <&usb3_phy0>;
- phy-names = "usb";
-
- companion = <&xhci0>;
-
- status = "okay";
-};
-
-&usb3_phy0 {
- status = "okay";
-};
-
-&usb3s0_clk {
- clock-frequency = <100000000>;
-};
-
-&vin0 {
- status = "okay";
-};
-
-&vin1 {
- status = "okay";
-};
-
-&vin2 {
- status = "okay";
-};
-
-&vin3 {
- status = "okay";
-};
-
-&vin4 {
- status = "okay";
-};
-
-&vin5 {
- status = "okay";
-};
-
-&vin6 {
- status = "okay";
-};
-
-&vin7 {
- status = "okay";
-};
-
-&xhci0 {
- pinctrl-0 = <&usb30_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-#ifdef SOC_HAS_USB2_CH2
-&ehci2 {
- status = "okay";
-};
-
-&ohci2 {
- status = "okay";
-};
-
-&pfc {
- usb2_pins: usb2 {
- groups = "usb2";
- function = "usb2";
- };
-};
-
-&usb2_phy2 {
- pinctrl-0 = <&usb2_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-#endif /* SOC_HAS_USB2_CH2 */
diff --git a/arch/arm/dts/salvator-x.dtsi b/arch/arm/dts/salvator-x.dtsi
deleted file mode 100644
index ddee50e..0000000
--- a/arch/arm/dts/salvator-x.dtsi
+++ /dev/null
@@ -1,29 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the Salvator-X board
- *
- * Copyright (C) 2015-2016 Renesas Electronics Corp.
- */
-
-#include "salvator-common.dtsi"
-
-/ {
- model = "Renesas Salvator-X board";
- compatible = "renesas,salvator-x";
-};
-
-&extal_clk {
- clock-frequency = <16666666>;
-};
-
-&i2c4 {
- clock-frequency = <400000>;
-
- versaclock5: clock-generator@6a {
- compatible = "idt,5p49v5923";
- reg = <0x6a>;
- #clock-cells = <1>;
- clocks = <&x23_clk>;
- clock-names = "xin";
- };
-};
diff --git a/arch/arm/dts/salvator-xs.dtsi b/arch/arm/dts/salvator-xs.dtsi
deleted file mode 100644
index 08b9256..0000000
--- a/arch/arm/dts/salvator-xs.dtsi
+++ /dev/null
@@ -1,85 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the Salvator-X 2nd version board
- *
- * Copyright (C) 2015-2017 Renesas Electronics Corp.
- */
-
-#include "salvator-common.dtsi"
-
-/ {
- model = "Renesas Salvator-X 2nd version board";
- compatible = "renesas,salvator-xs";
-};
-
-&extal_clk {
- clock-frequency = <16640000>;
-};
-
-&i2c4 {
- clock-frequency = <400000>;
-
- versaclock6: clock-generator@6a {
- compatible = "idt,5p49v6901";
- reg = <0x6a>;
- #clock-cells = <1>;
- clocks = <&x23_clk>;
- clock-names = "xin";
- };
-};
-
-#ifdef SOC_HAS_SATA
-&pca9654 {
- pcie-sata-switch-hog {
- gpio-hog;
- gpios = <7 GPIO_ACTIVE_HIGH>;
- output-low; /* enable SATA by default */
- line-name = "PCIE/SATA switch";
- };
-};
-
-/* SW12-7 must be set 'Off' (MD12 set to 1) which is not the default! */
-#endif /* SOC_HAS_SATA */
-
-#ifdef SOC_HAS_USB2_CH3
-&ehci3 {
- dr_mode = "otg";
- status = "okay";
-};
-
-&hsusb3 {
- dr_mode = "otg";
- status = "okay";
-};
-
-&ohci3 {
- dr_mode = "otg";
- status = "okay";
-};
-
-&pfc {
- /*
- * - On Salvator-X[S], GP6_3[01] are connected to ADV7482 as irq pins
- * (when SW31 is the default setting on Salvator-XS).
- * - If SW31 is the default setting, you cannot use USB2.0 ch3 on
- * r8a77951 with Salvator-XS.
- * Hence the SW31 setting must be changed like 2) below.
- * 1) Default setting of SW31: ON-ON-OFF-OFF-OFF-OFF:
- * - Connect GP6_3[01] to ADV7842.
- * 2) Changed setting of SW31: OFF-OFF-ON-ON-ON-ON:
- * - Connect GP6_3[01] to BD082065 (USB2.0 ch3's host power).
- * - Connect GP6_{04,21} to ADV7842.
- */
- usb2_ch3_pins: usb2_ch3 {
- groups = "usb2_ch3";
- function = "usb2_ch3";
- };
-};
-
-&usb2_phy3 {
- pinctrl-0 = <&usb2_ch3_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-#endif /* SOC_HAS_USB2_CH3 */
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index 27e0c38..c01d39f 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -6,6 +6,12 @@
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
&pinctrl {
+ adc1_pins_a: adc1-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1 in12 */
+ };
+ };
+
adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 {
pins {
pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
@@ -13,6 +19,104 @@
};
};
+ adc1_usb_cc_pins_b: adc1-usb-cc-pins-1 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 5, ANALOG)>, /* ADC1_INP2 */
+ <STM32_PINMUX('F', 13, ANALOG)>; /* ADC1_INP11 */
+ };
+ };
+
+ eth1_rgmii_pins_a: eth1-rgmii-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
+ <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
+ <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
+ <STM32_PINMUX('E', 5, AF10)>, /* ETH_RGMII_TXD3 */
+ <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
+ <STM32_PINMUX('C', 1, AF11)>, /* ETH_RGMII_GTX_CLK */
+ <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
+ <STM32_PINMUX('G', 2, AF11)>; /* ETH_MDC */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
+ <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
+ <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
+ <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
+ <STM32_PINMUX('A', 7, AF11)>, /* ETH_RGMII_RX_CTL */
+ <STM32_PINMUX('D', 7, AF10)>; /* ETH_RGMII_RX_CLK */
+ bias-disable;
+ };
+
+ };
+
+ eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
+ <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
+ <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
+ <STM32_PINMUX('E', 5, ANALOG)>, /* ETH_RGMII_TXD3 */
+ <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
+ <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_RGMII_GTX_CLK */
+ <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
+ <STM32_PINMUX('G', 2, ANALOG)>, /* ETH_MDC */
+ <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
+ <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
+ <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD1 */
+ <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD1 */
+ <STM32_PINMUX('A', 7, ANALOG)>, /* ETH_RGMII_RX_CTL */
+ <STM32_PINMUX('D', 7, ANALOG)>; /* ETH_RGMII_RX_CLK */
+ };
+ };
+
+ eth2_rgmii_pins_a: eth2-rgmii-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 7, AF11)>, /* ETH_RGMII_TXD0 */
+ <STM32_PINMUX('G', 11, AF10)>, /* ETH_RGMII_TXD1 */
+ <STM32_PINMUX('G', 1, AF10)>, /* ETH_RGMII_TXD2 */
+ <STM32_PINMUX('E', 6, AF11)>, /* ETH_RGMII_TXD3 */
+ <STM32_PINMUX('F', 6, AF11)>, /* ETH_RGMII_TX_CTL */
+ <STM32_PINMUX('G', 3, AF10)>, /* ETH_RGMII_GTX_CLK */
+ <STM32_PINMUX('B', 6, AF11)>, /* ETH_MDIO */
+ <STM32_PINMUX('G', 5, AF10)>; /* ETH_MDC */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('F', 4, AF11)>, /* ETH_RGMII_RXD0 */
+ <STM32_PINMUX('E', 2, AF10)>, /* ETH_RGMII_RXD1 */
+ <STM32_PINMUX('H', 6, AF12)>, /* ETH_RGMII_RXD2 */
+ <STM32_PINMUX('A', 8, AF11)>, /* ETH_RGMII_RXD3 */
+ <STM32_PINMUX('A', 12, AF11)>, /* ETH_RGMII_RX_CTL */
+ <STM32_PINMUX('H', 11, AF11)>; /* ETH_RGMII_RX_CLK */
+ bias-disable;
+ };
+ };
+
+ eth2_rgmii_sleep_pins_a: eth2-rgmii-sleep-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 7, ANALOG)>, /* ETH_RGMII_TXD0 */
+ <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TXD1 */
+ <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TXD2 */
+ <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TXD3 */
+ <STM32_PINMUX('G', 8, ANALOG)>, /* ETH_RGMII_TX_CTL */
+ <STM32_PINMUX('F', 6, ANALOG)>, /* ETH_RGMII_GTX_CLK */
+ <STM32_PINMUX('B', 2, ANALOG)>, /* ETH_MDIO */
+ <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_MDC */
+ <STM32_PINMUX('F', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
+ <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_RXD1 */
+ <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_RXD2 */
+ <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_RXD3 */
+ <STM32_PINMUX('A', 12, ANALOG)>, /* ETH_RGMII_RX_CTL */
+ <STM32_PINMUX('H', 11, ANALOG)>; /* ETH_RGMII_RX_CLK */
+ };
+ };
+
i2c1_pins_a: i2c1-0 {
pins {
pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
@@ -47,6 +151,63 @@
};
};
+ i2c5_pins_b: i2c5-1 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */
+ <STM32_PINMUX('E', 13, AF4)>; /* I2C5_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c5_sleep_pins_b: i2c5-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */
+ <STM32_PINMUX('E', 13, ANALOG)>; /* I2C5_SDA */
+ };
+ };
+
+ m_can1_pins_a: m-can1-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 10, AF9)>; /* CAN1_TX */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 0, AF9)>; /* CAN1_RX */
+ bias-disable;
+ };
+ };
+
+ m_can1_sleep_pins_a: m_can1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 10, ANALOG)>, /* CAN1_TX */
+ <STM32_PINMUX('D', 0, ANALOG)>; /* CAN1_RX */
+ };
+ };
+
+ m_can2_pins_a: m-can2-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 0, AF9)>; /* CAN2_TX */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 0, AF9)>; /* CAN2_RX */
+ bias-disable;
+ };
+ };
+
+ m_can2_sleep_pins_a: m_can2-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 0, ANALOG)>, /* CAN2_TX */
+ <STM32_PINMUX('E', 0, ANALOG)>; /* CAN2_RX */
+ };
+ };
+
mcp23017_pins_a: mcp23017-0 {
pins {
pinmux = <STM32_PINMUX('G', 12, GPIO)>;
@@ -84,6 +245,21 @@
};
};
+ pwm5_pins_a: pwm5-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 12, AF2)>; /* TIM5_CH3 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm5_sleep_pins_a: pwm5-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 12, ANALOG)>; /* TIM5_CH3 */
+ };
+ };
+
pwm8_pins_a: pwm8-0 {
pins {
pinmux = <STM32_PINMUX('E', 5, AF3)>; /* TIM8_CH3 */
@@ -99,6 +275,21 @@
};
};
+ pwm13_pins_a: pwm13-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 6, AF9)>; /* TIM13_CH1 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm13_sleep_pins_a: pwm13-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 6, ANALOG)>; /* TIM13_CH1 */
+ };
+ };
+
pwm14_pins_a: pwm14-0 {
pins {
pinmux = <STM32_PINMUX('F', 9, AF9)>; /* TIM14_CH1 */
@@ -114,6 +305,89 @@
};
};
+ qspi_clk_pins_a: qspi-clk-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <3>;
+ };
+ };
+
+ qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
+ };
+ };
+
+ qspi_bk1_pins_a: qspi-bk1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
+ <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
+ <STM32_PINMUX('D', 11, AF9)>, /* QSPI_BK1_IO2 */
+ <STM32_PINMUX('H', 7, AF13)>; /* QSPI_BK1_IO3 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
+ <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
+ <STM32_PINMUX('D', 11, ANALOG)>, /* QSPI_BK1_IO2 */
+ <STM32_PINMUX('H', 7, ANALOG)>; /* QSPI_BK1_IO3 */
+ };
+ };
+
+ qspi_cs1_pins_a: qspi-cs1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 2, AF9)>; /* QSPI_BK1_NCS */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 2, ANALOG)>; /* QSPI_BK1_NCS */
+ };
+ };
+
+ sai1a_pins_a: sai1a-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 4, AF12)>, /* SAI1_SCK_A */
+ <STM32_PINMUX('D', 6, AF6)>, /* SAI1_SD_A */
+ <STM32_PINMUX('E', 11, AF6)>; /* SAI1_FS_A */
+ slew-rate = <0>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ sai1a_sleep_pins_a: sai1a-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* SAI1_SCK_A */
+ <STM32_PINMUX('D', 6, ANALOG)>, /* SAI1_SD_A */
+ <STM32_PINMUX('E', 11, ANALOG)>; /* SAI1_FS_A */
+ };
+ };
+
+ sai1b_pins_a: sai1b-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 0, AF6)>; /* SAI1_SD_B */
+ bias-disable;
+ };
+ };
+
+ sai1b_sleep_pins_a: sai1b-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 0, ANALOG)>; /* SAI1_SD_B */
+ };
+ };
+
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
pins {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
@@ -216,6 +490,73 @@
};
};
+ sdmmc2_d47_pins_a: sdmmc2-d47-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 0, AF10)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('B', 9, AF10)>, /* SDMMC2_D5 */
+ <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
+ <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ };
+
+ sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC2_D5 */
+ <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
+ <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */
+ };
+ };
+
+ spi2_pins_a: spi2-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 10, AF6)>, /* SPI2_SCK */
+ <STM32_PINMUX('H', 10, AF6)>; /* SPI2_MOSI */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 5, AF5)>; /* SPI2_MISO */
+ bias-disable;
+ };
+ };
+
+ spi2_sleep_pins_a: spi2-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* SPI2_SCK */
+ <STM32_PINMUX('B', 5, ANALOG)>, /* SPI2_MISO */
+ <STM32_PINMUX('H', 10, ANALOG)>; /* SPI2_MOSI */
+ };
+ };
+
+ spi3_pins_a: spi3-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('H', 13, AF6)>, /* SPI3_SCK */
+ <STM32_PINMUX('F', 1, AF5)>; /* SPI3_MOSI */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 4, AF5)>; /* SPI3_MISO */
+ bias-disable;
+ };
+ };
+
+ spi3_sleep_pins_a: spi3-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* SPI3_SCK */
+ <STM32_PINMUX('D', 4, ANALOG)>, /* SPI3_MISO */
+ <STM32_PINMUX('F', 1, ANALOG)>; /* SPI3_MOSI */
+ };
+ };
+
spi5_pins_a: spi5-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 7, AF6)>, /* SPI5_SCK */
@@ -276,6 +617,77 @@
};
};
+ uart4_pins_b: uart4-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('A', 9, AF8)>; /* UART4_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
+ bias-pull-up;
+ };
+ };
+
+ uart4_idle_pins_b: uart4-idle-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('A', 9, ANALOG)>; /* UART4_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
+ bias-pull-up;
+ };
+ };
+
+ uart4_sleep_pins_b: uart4-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 9, ANALOG)>, /* UART4_TX */
+ <STM32_PINMUX('D', 8, ANALOG)>; /* UART4_RX */
+ };
+ };
+
+ uart7_pins_a: uart7-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('H', 2, AF8)>, /* UART7_TX */
+ <STM32_PINMUX('B', 12, AF7)>; /* UART7_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 10, AF7)>, /* UART7_RX */
+ <STM32_PINMUX('G', 7, AF8)>; /* UART7_CTS_NSS */
+ bias-disable;
+ };
+ };
+
+ uart7_idle_pins_a: uart7-idle-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* UART7_TX */
+ <STM32_PINMUX('G', 7, ANALOG)>; /* UART7_CTS_NSS */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 12, AF7)>; /* UART7_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('E', 10, AF7)>; /* UART7_RX */
+ bias-disable;
+ };
+ };
+
+ uart7_sleep_pins_a: uart7-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* UART7_TX */
+ <STM32_PINMUX('B', 12, ANALOG)>, /* UART7_RTS */
+ <STM32_PINMUX('E', 10, ANALOG)>, /* UART7_RX */
+ <STM32_PINMUX('G', 7, ANALOG)>; /* UART7_CTS_NSS */
+ };
+ };
+
uart8_pins_a: uart8-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
@@ -347,6 +759,36 @@
};
};
+ usart1_pins_b: usart1-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 0, AF7)>; /* USART1_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 14, AF7)>; /* USART1_RX */
+ bias-pull-up;
+ };
+ };
+
+ usart1_idle_pins_b: usart1-idle-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 0, ANALOG)>; /* USART1_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 14, AF7)>; /* USART1_RX */
+ bias-pull-up;
+ };
+ };
+
+ usart1_sleep_pins_b: usart1-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
+ <STM32_PINMUX('D', 14, ANALOG)>; /* USART1_RX */
+ };
+ };
+
usart2_pins_a: usart2-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 12, AF1)>, /* USART2_TX */
@@ -387,4 +829,45 @@
<STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */
};
};
+
+ usart2_pins_b: usart2-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 11, AF1)>, /* USART2_TX */
+ <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 15, AF1)>, /* USART2_RX */
+ <STM32_PINMUX('E', 15, AF3)>; /* USART2_CTS_NSS */
+ bias-disable;
+ };
+ };
+
+ usart2_idle_pins_b: usart2-idle-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* USART2_TX */
+ <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */
+ bias-disable;
+ };
+ };
+
+ usart2_sleep_pins_b: usart2-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* USART2_TX */
+ <STM32_PINMUX('A', 1, ANALOG)>, /* USART2_RTS */
+ <STM32_PINMUX('D', 15, ANALOG)>, /* USART2_RX */
+ <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */
+ };
+ };
};
diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi
index 215ad92..ad331b7 100644
--- a/arch/arm/dts/stm32mp131.dtsi
+++ b/arch/arm/dts/stm32mp131.dtsi
@@ -1092,6 +1092,30 @@
<&scmi_clk CK_SCMI_LSI>;
};
+ pwr_regulators: pwr@50001000 {
+ compatible = "st,stm32mp1,pwr-reg";
+ reg = <0x50001000 0x10>;
+ status = "disabled";
+
+ reg11: reg11 {
+ regulator-name = "reg11";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ };
+
+ reg18: reg18 {
+ regulator-name = "reg18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ usb33: usb33 {
+ regulator-name = "usb33";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+
exti: interrupt-controller@5000d000 {
compatible = "st,stm32mp13-exti", "syscon";
interrupt-controller;
@@ -1302,6 +1326,37 @@
cap-mmc-highspeed;
max-frequency = <130000000>;
status = "disabled";
+ };
+
+ eth1: eth1@5800a000 {
+ compatible = "snps,dwmac-4.20a", "st,stm32mp13-dwmac";
+ reg = <0x5800a000 0x2000>;
+ reg-names = "stmmaceth";
+ interrupts-extended = <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+ <&exti 68 1>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ clock-names = "stmmaceth",
+ "mac-clk-tx",
+ "mac-clk-rx",
+ "ethstp",
+ "eth-ck";
+ clocks = <&rcc ETH1MAC>,
+ <&rcc ETH1TX>,
+ <&rcc ETH1RX>,
+ <&rcc ETH1STP>,
+ <&rcc ETH1CK_K>;
+ st,syscon = <&syscfg 0x4 0xff0000>;
+ snps,mixed-burst;
+ snps,pbl = <2>;
+ snps,axi-config = <&stmmac_axi_config_1>;
+ snps,tso;
+ status = "disabled";
+
+ stmmac_axi_config_1: stmmac-axi-config {
+ snps,wr_osr_lmt = <0x7>;
+ snps,rd_osr_lmt = <0x7>;
+ snps,blen = <0 0 0 0 16 8 4>;
+ };
};
usbh_ohci: usb@5800c000 {
@@ -1380,6 +1435,12 @@
ts_cal2: calib@5e {
reg = <0x5e 0x2>;
};
+ ethernet_mac1_address: mac1@e4 {
+ reg = <0xe4 0x6>;
+ };
+ ethernet_mac2_address: mac2@ea {
+ reg = <0xea 0x6>;
+ };
};
/*
diff --git a/arch/arm/dts/stm32mp133.dtsi b/arch/arm/dts/stm32mp133.dtsi
index df451c3..5cd5bde 100644
--- a/arch/arm/dts/stm32mp133.dtsi
+++ b/arch/arm/dts/stm32mp133.dtsi
@@ -64,5 +64,35 @@
};
};
};
+
+ eth2: eth2@5800e000 {
+ compatible = "snps,dwmac-4.20a", "st,stm32mp13-dwmac";
+ reg = <0x5800e000 0x2000>;
+ reg-names = "stmmaceth";
+ interrupts-extended = <&intc GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clock-names = "stmmaceth",
+ "mac-clk-tx",
+ "mac-clk-rx",
+ "ethstp",
+ "eth-ck";
+ clocks = <&rcc ETH2MAC>,
+ <&rcc ETH2TX>,
+ <&rcc ETH2RX>,
+ <&rcc ETH2STP>,
+ <&rcc ETH2CK_K>;
+ st,syscon = <&syscfg 0x4 0xff000000>;
+ snps,mixed-burst;
+ snps,pbl = <2>;
+ snps,axi-config = <&stmmac_axi_config_2>;
+ snps,tso;
+ status = "disabled";
+
+ stmmac_axi_config_2: stmmac-axi-config {
+ snps,wr_osr_lmt = <0x7>;
+ snps,rd_osr_lmt = <0x7>;
+ snps,blen = <0 0 0 0 16 8 4>;
+ };
+ };
};
};
diff --git a/arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi b/arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi
new file mode 100644
index 0000000..d718aae
--- /dev/null
+++ b/arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2024 Marek Vasut <marex@denx.de>
+ */
+
+#include "stm32mp13xx-dhcor-u-boot.dtsi"
+
+&uart4 {
+ bootph-all;
+};
+
+&uart4_pins_b {
+ bootph-all;
+
+ pins1 {
+ bootph-all;
+ };
+ pins2 {
+ bootph-all;
+ };
+};
+
+&usbphyc {
+ bootph-all;
+};
diff --git a/arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts b/arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts
new file mode 100644
index 0000000..fc1c48a
--- /dev/null
+++ b/arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts
@@ -0,0 +1,383 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2024 Marek Vasut <marex@denx.de>
+ *
+ * DHCOR STM32MP13 variant:
+ * DHCR-STM32MP135F-C100-R051-EE-F0409-SPI4-RTC-WBT-I-01LG
+ * DHCOR PCB number: 718-100 or newer
+ * DHSBC PCB number: 719-100 or newer
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/regulator/st,stm32mp13-regulator.h>
+#include "stm32mp135.dtsi"
+#include "stm32mp13xf.dtsi"
+#include "stm32mp13xx-dhcor-som.dtsi"
+
+/ {
+ model = "DH electronics STM32MP135F DHCOR DHSBC";
+ compatible = "dh,stm32mp135f-dhcor-dhsbc",
+ "dh,stm32mp135f-dhcor-som",
+ "st,stm32mp135";
+
+ aliases {
+ ethernet0 = ð1;
+ ethernet1 = ð2;
+ serial2 = &usart1;
+ serial3 = &usart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&adc_1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&adc1_pins_a &adc1_usb_cc_pins_b>;
+ vdda-supply = <&vdd_adc>;
+ vref-supply = <&vdd_adc>;
+ status = "okay";
+
+ adc1: adc@0 {
+ status = "okay";
+
+ /*
+ * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in2 & in11.
+ * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
+ * 5 * (5.1 + 47kOhms) * 5pF => 1.3us.
+ * Use arbitrary margin here (e.g. 5us).
+ *
+ * The pinmux pins must be set as ANALOG, use datasheet
+ * DS13483 Table 7. STM32MP135C/F ball definitions to
+ * find out which 'pin name' maps to which 'additional
+ * functions', which lists the mapping between pin and
+ * ADC channel. In this case, PA5 maps to ADC1_INP2 and
+ * PF13 maps to ADC1_INP11 .
+ */
+ channel@2 {
+ reg = <2>;
+ st,min-sample-time-ns = <5000>;
+ };
+
+ channel@11 {
+ reg = <11>;
+ st,min-sample-time-ns = <5000>;
+ };
+
+ /* Expansion connector: INP12:pin29 */
+ channel@12 {
+ reg = <12>;
+ st,min-sample-time-ns = <5000>;
+ };
+ };
+};
+
+ð1 {
+ status = "okay";
+ pinctrl-0 = <ð1_rgmii_pins_a>;
+ pinctrl-1 = <ð1_rgmii_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy1>;
+ st,ext-phyclk;
+ nvmem-cells = <ðernet_mac1_address>;
+ nvmem-cell-names = "mac-address";
+
+ mdio1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ ethphy1: ethernet-phy@1 {
+ /* RTL8211F */
+ compatible = "ethernet-phy-id001c.c916",
+ "ethernet-phy-ieee802.3-c22";
+ interrupt-parent = <&gpiog>;
+ interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
+ reg = <1>;
+ reset-assert-us = <15000>;
+ reset-deassert-us = <55000>;
+ reset-gpios = <&gpioa 11 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+ð2 {
+ status = "okay";
+ pinctrl-0 = <ð2_rgmii_pins_a>;
+ pinctrl-1 = <ð2_rgmii_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy2>;
+ st,ext-phyclk;
+ nvmem-cells = <ðernet_mac2_address>;
+ nvmem-cell-names = "mac-address";
+
+ mdio1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ ethphy2: ethernet-phy@1 {
+ /* RTL8211F */
+ compatible = "ethernet-phy-id001c.c916",
+ "ethernet-phy-ieee802.3-c22";
+ interrupt-parent = <&gpiog>;
+ interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
+ reg = <1>;
+ reset-assert-us = <15000>;
+ reset-deassert-us = <55000>;
+ reset-gpios = <&gpiog 8 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&gpioa {
+ gpio-line-names = "", "", "", "",
+ "", "DHSBC_USB_PWR_CC1", "", "",
+ "", "", "", "DHSBC_nETH1_RST",
+ "", "DHCOR_HW-CODING_0", "", "";
+};
+
+&gpiob {
+ gpio-line-names = "", "", "", "",
+ "", "", "", "DHCOR_BT_HOST_WAKE",
+ "", "", "", "",
+ "", "DHSBC_nTPM_CS", "", "";
+};
+
+&gpioc {
+ gpio-line-names = "", "", "", "DHSBC_USB_5V_MEAS",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "";
+};
+
+&gpiod {
+ gpio-line-names = "", "", "", "",
+ "", "DHCOR_RAM-CODING_0", "", "",
+ "", "DHCOR_RAM-CODING_1", "", "",
+ "", "", "", "";
+};
+
+&gpioe {
+ gpio-line-names = "", "", "", "",
+ "", "", "", "",
+ "", "DHSBC_nTPM_RST", "", "",
+ "DHSBC_nTPM_PIRQ", "", "DHCOR_WL_HOST_WAKE", "";
+};
+
+&gpiof {
+ gpio-line-names = "", "", "DHSBC_USB_PWR_nFLT", "",
+ "", "", "", "",
+ "", "", "", "",
+ "DHCOR_WL_REG_ON", "DHSBC_USB_PWR_CC2", "", "";
+};
+
+&gpiog {
+ gpio-line-names = "", "", "", "",
+ "", "", "", "",
+ "DHSBC_nETH2_RST", "DHCOR_BT_DEV_WAKE", "", "",
+ "DHSBC_ETH1_INTB", "", "", "DHSBC_ETH2_INTB";
+};
+
+&gpioi {
+ gpio-line-names = "DHCOR_RTC_nINT", "DHCOR_HW-CODING_1",
+ "DHCOR_BT_REG_ON", "DHCOR_PMIC_nINT",
+ "DHSBC_BOOT0", "DHSBC_BOOT1",
+ "DHSBC_BOOT2", "DHSBC_USB-C_DATA_VBUS";
+};
+
+&i2c1 { /* Expansion connector: SDA:pin27 SCL:pin28 */
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c1_pins_a>;
+ pinctrl-1 = <&i2c1_sleep_pins_a>;
+ i2c-scl-rising-time-ns = <96>;
+ i2c-scl-falling-time-ns = <3>;
+ clock-frequency = <400000>;
+ status = "okay";
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+};
+
+&i2c5 { /* Expansion connector: SDA:pin3 SCL:pin5 */
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c5_pins_b>;
+ pinctrl-1 = <&i2c5_sleep_pins_b>;
+ i2c-scl-rising-time-ns = <96>;
+ i2c-scl-falling-time-ns = <3>;
+ clock-frequency = <400000>;
+ status = "okay";
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+};
+
+&m_can1 { /* Expansion connector: TX:pin16 RX:pin18 */
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&m_can1_pins_a>;
+ pinctrl-1 = <&m_can1_sleep_pins_a>;
+ status = "okay";
+};
+
+&m_can2 { /* Expansion connector: TX:pin22 RX:pin26 */
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&m_can2_pins_a>;
+ pinctrl-1 = <&m_can2_sleep_pins_a>;
+ status = "okay";
+};
+
+&pwr_regulators {
+ vdd-supply = <&vdd>;
+ vdd_3v3_usbfs-supply = <&vdd_usb>;
+ status = "okay";
+};
+
+&sai1 { /* Expansion connector: SCK-A:pin12 FS-A:pin35 SD-A:pin38 SD-B:pin40 */
+ clocks = <&rcc SAI1>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
+ clock-names = "pclk", "x8k", "x11k";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sai1a_pins_a &sai1b_pins_a>;
+ pinctrl-1 = <&sai1a_sleep_pins_a &sai1b_sleep_pins_a>;
+};
+
+&scmi_voltd {
+ status = "disabled";
+};
+
+&spi2 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&spi2_pins_a>;
+ pinctrl-1 = <&spi2_sleep_pins_a>;
+ cs-gpios = <&gpiob 13 0>;
+ status = "okay";
+
+ st33htph: tpm@0 {
+ compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi";
+ reg = <0>;
+ spi-max-frequency = <24000000>;
+ };
+};
+
+&spi3 { /* Expansion connector: MOSI:pin19 MISO:pin21 SCK:pin22 nCS:pin24 */
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&spi3_pins_a>;
+ pinctrl-1 = <&spi3_sleep_pins_a>;
+ cs-gpios = <&gpiof 3 0>;
+ status = "disabled";
+};
+
+&timers5 { /* Expansion connector: CH3:pin31 */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "okay";
+
+ pwm {
+ pinctrl-0 = <&pwm5_pins_a>;
+ pinctrl-1 = <&pwm5_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@4 {
+ status = "okay";
+ };
+};
+
+&timers13 { /* Expansion connector: CH1:pin32 */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "okay";
+
+ pwm {
+ pinctrl-0 = <&pwm13_pins_a>;
+ pinctrl-1 = <&pwm13_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@12 {
+ status = "okay";
+ };
+};
+
+&usart1 { /* Expansion connector: RX:pin33 TX:pin37 */
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&usart1_pins_b>;
+ pinctrl-1 = <&usart1_sleep_pins_b>;
+ pinctrl-2 = <&usart1_idle_pins_b>;
+ status = "okay";
+};
+
+&usart2 { /* Expansion connector: RX:pin10 TX:pin8 RTS:pin11 CTS:pin36 */
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&usart2_pins_b>;
+ pinctrl-1 = <&usart2_sleep_pins_b>;
+ pinctrl-2 = <&usart2_idle_pins_b>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&usbh_ehci {
+ phys = <&usbphyc_port0>;
+ status = "okay";
+};
+
+&usbh_ohci {
+ phys = <&usbphyc_port0>;
+ status = "okay";
+};
+
+&usbotg_hs {
+ dr_mode = "peripheral";
+ phys = <&usbphyc_port1 0>;
+ phy-names = "usb2-phy";
+ usb33d-supply = <&usb33>;
+ status = "okay";
+};
+
+&usbphyc {
+ status = "okay";
+ vdda1v1-supply = <®11>;
+ vdda1v8-supply = <®18>;
+};
+
+&usbphyc_port0 {
+ phy-supply = <&vdd_usb>;
+ st,current-boost-microamp = <1000>;
+ st,decrease-hs-slew-rate;
+ st,tune-hs-dc-level = <2>;
+ st,enable-hs-rftime-reduction;
+ st,trim-hs-current = <11>;
+ st,trim-hs-impedance = <2>;
+ st,tune-squelch-level = <1>;
+ st,enable-hs-rx-gain-eq;
+ st,no-hs-ftime-ctrl;
+ st,no-lsfs-sc;
+ connector {
+ compatible = "usb-a-connector";
+ vbus-supply = <&vbus_sw>;
+ };
+};
+
+&usbphyc_port1 {
+ phy-supply = <&vdd_usb>;
+ st,current-boost-microamp = <1000>;
+ st,decrease-hs-slew-rate;
+ st,tune-hs-dc-level = <2>;
+ st,enable-hs-rftime-reduction;
+ st,trim-hs-current = <11>;
+ st,trim-hs-impedance = <2>;
+ st,tune-squelch-level = <1>;
+ st,enable-hs-rx-gain-eq;
+ st,no-hs-ftime-ctrl;
+ st,no-lsfs-sc;
+ connector {
+ compatible = "gpio-usb-b-connector", "usb-b-connector";
+ vbus-gpios = <&gpioi 7 GPIO_ACTIVE_HIGH>;
+ label = "Type-C";
+ self-powered;
+ type = "micro";
+ };
+};
diff --git a/arch/arm/dts/stm32mp13xx-dhcor-som.dtsi b/arch/arm/dts/stm32mp13xx-dhcor-som.dtsi
new file mode 100644
index 0000000..ddad649
--- /dev/null
+++ b/arch/arm/dts/stm32mp13xx-dhcor-som.dtsi
@@ -0,0 +1,308 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2024 Marek Vasut <marex@denx.de>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/mfd/st,stpmic1.h>
+#include <dt-bindings/regulator/st,stm32mp13-regulator.h>
+#include "stm32mp13-pinctrl.dtsi"
+
+/ {
+ model = "DH electronics STM32MP13xx DHCOR SoM";
+ compatible = "dh,stm32mp131a-dhcor-som",
+ "st,stm32mp131";
+
+ aliases {
+ mmc0 = &sdmmc2;
+ mmc1 = &sdmmc1;
+ serial0 = &uart4;
+ serial1 = &uart7;
+ rtc0 = &rv3032;
+ spi0 = &qspi;
+ };
+
+ memory@c0000000 {
+ device_type = "memory";
+ reg = <0xc0000000 0x20000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ optee@dd000000 {
+ reg = <0xdd000000 0x3000000>;
+ no-map;
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpiof 12 GPIO_ACTIVE_LOW>;
+ };
+
+ vin: vin {
+ compatible = "regulator-fixed";
+ regulator-name = "vin";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+};
+
+&i2c3 {
+ i2c-scl-rising-time-ns = <96>;
+ i2c-scl-falling-time-ns = <3>;
+ clock-frequency = <400000>;
+ status = "okay";
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+
+ pmic: stpmic@33 {
+ compatible = "st,stpmic1";
+ reg = <0x33>;
+ interrupts-extended = <&gpioi 3 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "okay";
+
+ regulators {
+ compatible = "st,stpmic1-regulators";
+
+ ldo1-supply = <&vin>;
+ ldo2-supply = <&vin>;
+ ldo3-supply = <&vin>;
+ ldo4-supply = <&vin>;
+ ldo5-supply = <&vin>;
+ ldo6-supply = <&vin>;
+ pwr_sw1-supply = <&bst_out>;
+ pwr_sw2-supply = <&bst_out>;
+
+ vddcpu: buck1 { /* VDD_CPU_1V2 */
+ regulator-name = "vddcpu";
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ vdd_ddr: buck2 { /* VDD_DDR_1V35 */
+ regulator-name = "vdd_ddr";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ vdd: buck3 { /* VDD_3V3_1V8 */
+ regulator-name = "vdd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ vddcore: buck4 { /* VDD_CORE_1V2 */
+ regulator-name = "vddcore";
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ vdd_adc: ldo1 { /* VDD_ADC_1V8 */
+ regulator-name = "vdd_adc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ interrupts = <IT_CURLIM_LDO1 0>;
+ };
+
+ vdd_ldo2: ldo2 { /* LDO2_OUT_1V8 */
+ regulator-name = "vdd_ldo2";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ interrupts = <IT_CURLIM_LDO2 0>;
+ };
+
+ vdd_ldo3: ldo3 { /* LDO3_OUT */
+ regulator-name = "vdd_ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ interrupts = <IT_CURLIM_LDO3 0>;
+ };
+
+ vdd_usb: ldo4 { /* VDD_USB_3V3 */
+ regulator-name = "vdd_usb";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ interrupts = <IT_CURLIM_LDO4 0>;
+ };
+
+ vdd_sd: ldo5 { /* VDD_SD_3V3_1V8 */
+ regulator-name = "vdd_sd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ interrupts = <IT_CURLIM_LDO5 0>;
+ };
+
+ vdd_sd2: ldo6 { /* VDD_SD2_3V3_1V8 */
+ regulator-name = "vdd_sd2";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ interrupts = <IT_CURLIM_LDO6 0>;
+ };
+
+ vref_ddr: vref_ddr { /* VREF_DDR_0V675 */
+ regulator-name = "vref_ddr";
+ regulator-always-on;
+ };
+
+ bst_out: boost { /* BST_OUT_5V2 */
+ regulator-name = "bst_out";
+ };
+
+ vbus_otg: pwr_sw1 {
+ regulator-name = "vbus_otg";
+ interrupts = <IT_OCP_OTG 0>;
+ };
+
+ vbus_sw: pwr_sw2 {
+ regulator-name = "vbus_sw";
+ interrupts = <IT_OCP_SWOUT 0>;
+ regulator-active-discharge = <1>;
+ };
+ };
+
+ onkey {
+ compatible = "st,stpmic1-onkey";
+ interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>;
+ interrupt-names = "onkey-falling", "onkey-rising";
+ status = "okay";
+ };
+
+ watchdog {
+ compatible = "st,stpmic1-wdt";
+ status = "disabled";
+ };
+ };
+
+ eeprom0: eeprom@50 {
+ compatible = "atmel,24c256"; /* ST M24256 */
+ reg = <0x50>;
+ pagesize = <64>;
+ };
+
+ rv3032: rtc@51 {
+ compatible = "microcrystal,rv3032";
+ reg = <0x51>;
+ interrupts-extended = <&gpioi 0 IRQ_TYPE_EDGE_FALLING>;
+ };
+};
+
+&iwdg2 {
+ timeout-sec = <32>;
+ status = "okay";
+};
+
+&qspi {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qspi_clk_pins_a
+ &qspi_bk1_pins_a
+ &qspi_cs1_pins_a>;
+ pinctrl-1 = <&qspi_clk_sleep_pins_a
+ &qspi_bk1_sleep_pins_a
+ &qspi_cs1_sleep_pins_a>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash0: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <108000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
+
+/* Console UART */
+&uart4 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&uart4_pins_b>;
+ pinctrl-1 = <&uart4_sleep_pins_b>;
+ pinctrl-2 = <&uart4_idle_pins_b>;
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "okay";
+};
+
+/* Bluetooth */
+&uart7 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&uart7_pins_a>;
+ pinctrl-1 = <&uart7_sleep_pins_a>;
+ pinctrl-2 = <&uart7_idle_pins_a>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "infineon,cyw43439-bt", "brcm,bcm4329-bt";
+ max-speed = <3000000>;
+ device-wakeup-gpios = <&gpiog 9 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpioi 2 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+/* SDIO WiFi */
+&sdmmc1 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>;
+ pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>;
+ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
+ bus-width = <4>;
+ cap-power-off-card;
+ keep-power-in-suspend;
+ non-removable;
+ st,neg-edge;
+ vmmc-supply = <&vdd>;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ brcmf: bcrmf@1 { /* muRata 1YN */
+ reg = <1>;
+ compatible = "infineon,cyw43439-fmac", "brcm,bcm4329-fmac";
+ interrupt-parent = <&gpioe>;
+ interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "host-wake";
+ };
+};
+
+/* eMMC */
+&sdmmc2 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a &sdmmc2_clk_pins_a>;
+ pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a &sdmmc2_clk_pins_a>;
+ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
+ bus-width = <8>;
+ mmc-ddr-3_3v;
+ no-sd;
+ no-sdio;
+ non-removable;
+ st,neg-edge;
+ vmmc-supply = <&vdd>;
+ vqmmc-supply = <&vdd>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi
new file mode 100644
index 0000000..30e3b91
--- /dev/null
+++ b/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2024 Marek Vasut <marex@denx.de>
+ */
+
+#include "stm32mp13-u-boot.dtsi"
+
+/ {
+ aliases {
+ eeprom0 = &eeprom0;
+ };
+
+ config {
+ dh,ddr3-coding-gpios = <&gpiod 5 0>, <&gpiod 9 0>;
+ dh,som-coding-gpios = <&gpioa 13 0>, <&gpioi 1 0>;
+ };
+};
+
+&flash0 {
+ bootph-pre-ram;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "fsbl1";
+ reg = <0x00000000 0x00040000>;
+ };
+ partition@40000 {
+ label = "fsbl2";
+ reg = <0x00040000 0x00040000>;
+ };
+ partition@80000 {
+ label = "u-boot";
+ reg = <0x00080000 0x00360000>;
+ };
+ partition@3e0000 {
+ label = "u-boot-env-a";
+ reg = <0x003e0000 0x00010000>;
+ };
+ partition@3f0000 {
+ label = "u-boot-env-b";
+ reg = <0x003f0000 0x00010000>;
+ };
+ };
+};
+
+&sdmmc1 {
+ status = "disabled";
+};
+
+&usbotg_hs {
+ u-boot,force-b-session-valid;
+};
diff --git a/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi b/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi
index b780dbd..d07fdcf 100644
--- a/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi
@@ -115,11 +115,11 @@
bootph-all;
};
- /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
+ /* VCO = 750.0 MHz => P = 125, Q = 62.5, R = 62.5 */
pll4: st,pll@3 {
compatible = "st,stm32mp1-pll";
reg = <3>;
- cfg = < 3 98 5 7 7 PQR(1,1,1) >;
+ cfg = < 3 124 5 9 9 PQR(1,1,1) >;
bootph-all;
};
};
diff --git a/arch/arm/dts/stm32mp157c-odyssey.dts b/arch/arm/dts/stm32mp157c-odyssey.dts
index 17bcf56..4cc5e07 100644
--- a/arch/arm/dts/stm32mp157c-odyssey.dts
+++ b/arch/arm/dts/stm32mp157c-odyssey.dts
@@ -75,13 +75,15 @@
phy-mode = "rgmii-id";
max-speed = <1000>;
phy-handle = <&phy0>;
+ phy-reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>;
+ st,ext-phyclk;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
- phy0: ethernet-phy@0 {
- reg = <0>;
+ phy0: ethernet-phy@7 {
+ reg = <7>;
};
};
};
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts
index 1ef9ac2..90625bf 100644
--- a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts
+++ b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts
@@ -11,5 +11,7 @@
/ {
model = "DH Electronics STM32MP15xx DHCOM DRC02";
- compatible = "dh,stm32mp15xx-dhcom-drc02", "st,stm32mp1xx";
+ compatible = "dh,stm32mp15xx-dhcom-drc02",
+ "dh,stm32mp15xx-dhcom-som",
+ "st,stm32mp1xx";
};
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts
index e2e01e2..b2e450a 100644
--- a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts
+++ b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts
@@ -11,5 +11,7 @@
/ {
model = "STMicroelectronics STM32MP15xx DHCOM Premium Developer Kit (2)";
- compatible = "dh,stm32mp15xx-dhcom-pdk2", "st,stm32mp15x";
+ compatible = "dh,stm32mp15xx-dhcom-pdk2",
+ "dh,stm32mp15xx-dhcom-som",
+ "st,stm32mp15x";
};
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts b/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts
index 06770b4..3e90810 100644
--- a/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts
+++ b/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts
@@ -11,5 +11,7 @@
/ {
model = "DH Electronics STM32MP15xx DHCOM PicoITX";
- compatible = "dh,stm32mp15xx-dhcom-picoitx", "st,stm32mp1xx";
+ compatible = "dh,stm32mp15xx-dhcom-picoitx",
+ "dh,stm32mp15xx-dhcom-som",
+ "st,stm32mp1xx";
};
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
index 1b44561..d7b78cd 100644
--- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
@@ -26,6 +26,7 @@
u-boot,error-led = "error";
dh,som-coding-gpios = <&gpiof 12 0>, <&gpiof 13 0>, <&gpiof 15 0>;
dh,ddr3-coding-gpios = <&gpioz 6 0>, <&gpioz 7 0>;
+ dh,mac-coding-gpios = <&gpioc 3 0>;
};
};
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts
index 76ac5a8..dd8fcec 100644
--- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts
+++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts
@@ -14,5 +14,7 @@
/ {
model = "Arrow Electronics STM32MP15xx Avenger96 board";
- compatible = "arrow,stm32mp15xx-avenger96", "st,stm32mp15x";
+ compatible = "arrow,stm32mp15xx-avenger96",
+ "dh,stm32mp15xx-dhcor-som",
+ "st,stm32mp15x";
};
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dts b/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dts
index 77dd944..c1f99c1 100644
--- a/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dts
+++ b/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dts
@@ -12,5 +12,7 @@
/ {
model = "DH electronics STM32MP15xx DHCOR DRC Compact";
- compatible = "dh,stm32mp15xx-dhcor-drc-compact", "st,stm32mp1xx";
+ compatible = "dh,stm32mp15xx-dhcor-drc-compact",
+ "dh,stm32mp15xx-dhcor-som",
+ "st,stm32mp1xx";
};
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts b/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts
index c9163e1..5fdd762 100644
--- a/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts
+++ b/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts
@@ -9,7 +9,9 @@
/ {
model = "DH electronics STM32MP15xx DHCOR Testbench";
- compatible = "dh,stm32mp15xx-dhcor-testbench", "st,stm32mp1xx";
+ compatible = "dh,stm32mp15xx-dhcor-testbench",
+ "dh,stm32mp15xx-dhcor-som",
+ "st,stm32mp1xx";
aliases {
ethernet0 = ðernet0;
diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-boot.dtsi
index 0909a67..e1a9a7f 100644
--- a/arch/arm/dts/sunxi-u-boot.dtsi
+++ b/arch/arm/dts/sunxi-u-boot.dtsi
@@ -90,6 +90,7 @@
scp {
filename = "scp.bin";
missing-msg = "scp-sunxi";
+ optional;
};
};
#endif
diff --git a/arch/arm/dts/tegra20-asus-sl101.dts b/arch/arm/dts/tegra20-asus-sl101.dts
new file mode 100644
index 0000000..b4709c3
--- /dev/null
+++ b/arch/arm/dts/tegra20-asus-sl101.dts
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "tegra20-asus-transformer.dtsi"
+
+/ {
+ model = "ASUS EeePad Slider SL101";
+ compatible = "asus,sl101", "nvidia,tegra20";
+};
diff --git a/arch/arm/dts/tegra20-asus-tf101.dts b/arch/arm/dts/tegra20-asus-tf101.dts
new file mode 100644
index 0000000..7c734fb
--- /dev/null
+++ b/arch/arm/dts/tegra20-asus-tf101.dts
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "tegra20-asus-transformer.dtsi"
+
+/ {
+ model = "ASUS EeePad Transformer TF101";
+ compatible = "asus,tf101", "nvidia,tegra20";
+};
diff --git a/arch/arm/dts/tegra20-asus-tf101g.dts b/arch/arm/dts/tegra20-asus-tf101g.dts
new file mode 100644
index 0000000..f49a358
--- /dev/null
+++ b/arch/arm/dts/tegra20-asus-tf101g.dts
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "tegra20-asus-transformer.dtsi"
+
+/ {
+ model = "ASUS EeePad Transformer TF101G";
+ compatible = "asus,tf101g", "nvidia,tegra20";
+};
diff --git a/arch/arm/dts/tegra20-asus-transformer.dtsi b/arch/arm/dts/tegra20-asus-transformer.dtsi
new file mode 100644
index 0000000..49efabb
--- /dev/null
+++ b/arch/arm/dts/tegra20-asus-transformer.dtsi
@@ -0,0 +1,545 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/input/input.h>
+#include "tegra20.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uartd;
+ };
+
+ aliases {
+ i2c0 = &pwr_i2c;
+
+ mmc0 = &sdmmc4; /* eMMC */
+ mmc1 = &sdmmc3; /* MicroSD */
+
+ rtc0 = &pmic;
+ rtc1 = "/rtc@7000e000";
+
+ usb0 = &usb1;
+ usb1 = &usb3; /* Dock USB */
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x40000000>;
+ };
+
+ host1x@50000000 {
+ dc@54200000 {
+ rgb {
+ status = "okay";
+
+ nvidia,panel = <&panel>;
+ };
+ };
+ };
+
+ pinmux@70000014 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ ata {
+ nvidia,pins = "ata";
+ nvidia,function = "ide";
+ };
+
+ atb {
+ nvidia,pins = "atb", "gma", "gme";
+ nvidia,function = "sdio4";
+ };
+
+ atc {
+ nvidia,pins = "atc";
+ nvidia,function = "nand";
+ };
+
+ atd {
+ nvidia,pins = "atd", "ate", "gmb", "spia",
+ "spib", "spic";
+ nvidia,function = "gmi";
+ };
+
+ cdev1 {
+ nvidia,pins = "cdev1";
+ nvidia,function = "plla_out";
+ };
+
+ cdev2 {
+ nvidia,pins = "cdev2";
+ nvidia,function = "pllp_out4";
+ };
+
+ crtp {
+ nvidia,pins = "crtp";
+ nvidia,function = "crt";
+ };
+
+ lm1 {
+ nvidia,pins = "lm1";
+ nvidia,function = "rsvd3";
+ };
+
+ csus {
+ nvidia,pins = "csus";
+ nvidia,function = "vi_sensor_clk";
+ };
+
+ dap1 {
+ nvidia,pins = "dap1";
+ nvidia,function = "dap1";
+ };
+
+ dap2 {
+ nvidia,pins = "dap2";
+ nvidia,function = "dap2";
+ };
+
+ dap3 {
+ nvidia,pins = "dap3";
+ nvidia,function = "dap3";
+ };
+
+ dap4 {
+ nvidia,pins = "dap4";
+ nvidia,function = "dap4";
+ };
+
+ dta {
+ nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
+ nvidia,function = "vi";
+ };
+
+ dtf {
+ nvidia,pins = "dtf";
+ nvidia,function = "i2c3";
+ };
+
+ gmc {
+ nvidia,pins = "gmc";
+ nvidia,function = "uartd";
+ };
+
+ gmd {
+ nvidia,pins = "gmd";
+ nvidia,function = "sflash";
+ };
+
+ gpu {
+ nvidia,pins = "gpu";
+ nvidia,function = "pwm";
+ };
+
+ gpu7 {
+ nvidia,pins = "gpu7";
+ nvidia,function = "rtck";
+ };
+
+ gpv {
+ nvidia,pins = "gpv", "slxa";
+ nvidia,function = "pcie";
+ };
+
+ hdint {
+ nvidia,pins = "hdint";
+ nvidia,function = "hdmi";
+ };
+
+ i2cp {
+ nvidia,pins = "i2cp";
+ nvidia,function = "i2cp";
+ };
+
+ irrx {
+ nvidia,pins = "irrx", "irtx";
+ nvidia,function = "uartb";
+ };
+
+ kbca {
+ nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+ "kbce", "kbcf";
+ nvidia,function = "kbc";
+ };
+
+ lcsn {
+ nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
+ "lsdi", "lvp0";
+ nvidia,function = "rsvd4";
+ };
+
+ ld0 {
+ nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+ "ld5", "ld6", "ld7", "ld8", "ld9",
+ "ld10", "ld11", "ld12", "ld13", "ld14",
+ "ld15", "ld16", "ld17", "ldi", "lhp0",
+ "lhp1", "lhp2", "lhs", "lpp", "lpw0",
+ "lpw2", "lsc0", "lsc1", "lsck", "lsda",
+ "lspi", "lvp1", "lvs";
+ nvidia,function = "displaya";
+ };
+
+ owc {
+ nvidia,pins = "owc", "spdi", "spdo", "uac";
+ nvidia,function = "rsvd2";
+ };
+
+ pmc {
+ nvidia,pins = "pmc";
+ nvidia,function = "pwr_on";
+ };
+
+ rm {
+ nvidia,pins = "rm";
+ nvidia,function = "i2c1";
+ };
+
+ sdb {
+ nvidia,pins = "sdb", "sdc", "sdd", "slxc", "slxk";
+ nvidia,function = "sdio3";
+ };
+
+ sdio1 {
+ nvidia,pins = "sdio1";
+ nvidia,function = "sdio1";
+ };
+
+ slxd {
+ nvidia,pins = "slxd";
+ nvidia,function = "spdif";
+ };
+
+ spid {
+ nvidia,pins = "spid", "spie", "spif";
+ nvidia,function = "spi1";
+ };
+
+ spig {
+ nvidia,pins = "spig", "spih";
+ nvidia,function = "spi2_alt";
+ };
+
+ uaa {
+ nvidia,pins = "uaa", "uab", "uda";
+ nvidia,function = "ulpi";
+ };
+
+ uad {
+ nvidia,pins = "uad";
+ nvidia,function = "irda";
+ };
+
+ uca {
+ nvidia,pins = "uca", "ucb";
+ nvidia,function = "uartc";
+ };
+
+ conf_ata {
+ nvidia,pins = "ata", "atb", "atc", "atd",
+ "cdev1", "cdev2", "dap1", "dap4",
+ "dte", "ddc", "dtf", "gma", "gmc",
+ "gme", "gpu", "gpu7", "gpv", "i2cp",
+ "irrx", "irtx", "pta", "rm", "sdc",
+ "sdd", "slxc", "slxd", "slxk", "spdi",
+ "spdo", "uac", "uad",
+ "uda", "csus";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+
+ conf_ate {
+ nvidia,pins = "ate", "dap2", "dap3", "gmb", "gmd",
+ "owc", "spia", "spib", "spic",
+ "spid", "spie", "spig", "slxa";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ };
+
+ conf_ck32 {
+ nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+ "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ };
+
+ conf_crtp {
+ nvidia,pins = "crtp", "spih";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ };
+
+ conf_dta {
+ nvidia,pins = "dta", "dtb", "dtc", "dtd";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+
+ conf_spif {
+ nvidia,pins = "spif";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ };
+
+ conf_hdint {
+ nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
+ "lpw1", "lsck", "lsda", "lsdi", "lvp0";
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ };
+
+ conf_kbca {
+ nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+ "kbce", "kbcf", "sdio1", "uaa", "uab",
+ "uca", "ucb";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+
+ conf_lc {
+ nvidia,pins = "lc", "ls";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ };
+
+ conf_ld0 {
+ nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+ "ld5", "ld6", "ld7", "ld8", "ld9",
+ "ld10", "ld11", "ld12", "ld13", "ld14",
+ "ld15", "ld16", "ld17", "ldi", "lhp0",
+ "lhp1", "lhp2", "lhs", "lm0", "lpp",
+ "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
+ "lvp1", "lvs", "pmc", "sdb";
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+
+ conf_ld17_0 {
+ nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+ "ld23_22";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ };
+
+ drive_sdio1 {
+ nvidia,pins = "drive_sdio1", "drive_ddc", "drive_vi1";
+ nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+ nvidia,schmitt = <TEGRA_PIN_ENABLE>;
+ nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+ nvidia,pull-down-strength = <31>;
+ nvidia,pull-up-strength = <31>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+ };
+
+ drive_csus {
+ nvidia,pins = "drive_csus";
+ nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+ nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+ nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+ nvidia,pull-down-strength = <31>;
+ nvidia,pull-up-strength = <31>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+ };
+ };
+
+ state_i2cmux_ddc: pinmux-i2cmux-ddc {
+ ddc {
+ nvidia,pins = "ddc";
+ nvidia,function = "i2c2";
+ };
+
+ pta {
+ nvidia,pins = "pta";
+ nvidia,function = "rsvd4";
+ };
+ };
+
+ state_i2cmux_idle: pinmux-i2cmux-idle {
+ ddc {
+ nvidia,pins = "ddc";
+ nvidia,function = "rsvd4";
+ };
+
+ pta {
+ nvidia,pins = "pta";
+ nvidia,function = "rsvd4";
+ };
+ };
+
+ state_i2cmux_pta: pinmux-i2cmux-pta {
+ ddc {
+ nvidia,pins = "ddc";
+ nvidia,function = "rsvd4";
+ };
+
+ pta {
+ nvidia,pins = "pta";
+ nvidia,function = "i2c2";
+ };
+ };
+ };
+
+ uartd: serial@70006300 {
+ status = "okay";
+ clock-frequency = <216000000>;
+ };
+
+ pwm: pwm@7000a000 {
+ status = "okay";
+ };
+
+ pwr_i2c: i2c@7000d000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ pmic: tps6586x@34 {
+ compatible = "ti,tps6586x";
+ reg = <0x34>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+
+ ti,system-power-controller;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ regulators {
+ avdd_usb: ldo3 {
+ regulator-name = "vdd_ldo3,avdd_usb*";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcore_emmc: ldo5 {
+ regulator-name = "vdd_ldo5,vcore_mmc";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+ };
+ };
+ };
+
+ /* USB via ASUS connector */
+ usb1: usb@c5000000 {
+ status = "okay";
+ dr_mode = "otg";
+ };
+
+ usb-phy@c5000000 {
+ status = "okay";
+ nvidia,xcvr-setup-use-fuses;
+ };
+
+ /* Dock's USB port */
+ usb3: usb@c5008000 {
+ status = "okay";
+ };
+
+ sdmmc3: sdhci@c8000400 {
+ status = "okay";
+ bus-width = <4>;
+
+ cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+ power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
+
+ vmmc-supply = <&vdd_3v3_sys>;
+ vqmmc-supply = <&vdd_3v3_sys>;
+ };
+
+ sdmmc4: sdhci@c8000600 {
+ status = "okay";
+ bus-width = <8>;
+ non-removable;
+
+ vmmc-supply = <&vcore_emmc>;
+ vqmmc-supply = <&vdd_3v3_sys>;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+
+ enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
+ power-supply = <&vdd_3v3_sys>;
+ pwms = <&pwm 2 4000000>;
+
+ brightness-levels = <1 35 70 105 140 175 210 255>;
+ default-brightness-level = <5>;
+ };
+
+ /* PMIC has a built-in 32KHz oscillator which is used by PMC */
+ clk32k_in: clock-32k-in {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "pmic-oscillator";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ key-power {
+ label = "Power";
+ gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_ENTER>;
+ };
+
+ key-volume-down {
+ label = "Volume Down";
+ gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_DOWN>;
+ };
+
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_UP>;
+ };
+
+ switch-dock-hall-sensor {
+ label = "Lid sensor";
+ gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>;
+ linux,code = <SW_LID>;
+ };
+ };
+
+ panel: panel {
+ compatible = "simple-panel";
+
+ power-supply = <&vdd_pnl_reg>;
+ enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
+
+ backlight = <&backlight>;
+
+ display-timings {
+ timing@0 {
+ clock-frequency = <71200000>;
+
+ hactive = <1280>;
+ hfront-porch = <8>;
+ hback-porch = <18>;
+ hsync-len = <184>;
+
+ vactive = <800>;
+ vfront-porch = <4>;
+ vback-porch = <8>;
+ vsync-len = <3>;
+ };
+ };
+ };
+
+ vdd_3v3_sys: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_3v3_vs";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vdd_pnl_reg: regulator-pnl {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_panel";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
diff --git a/arch/arm/dts/tegra30-lenovo-ideapad-yoga-11.dts b/arch/arm/dts/tegra30-lenovo-ideapad-yoga-11.dts
new file mode 100644
index 0000000..9a1e8c0
--- /dev/null
+++ b/arch/arm/dts/tegra30-lenovo-ideapad-yoga-11.dts
@@ -0,0 +1,1266 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "tegra30.dtsi"
+
+/ {
+ model = "Lenovo Ideapad Yoga 11 Slate";
+ compatible = "lenovo,ideapad-yoga-11", "nvidia,tegra30";
+
+ chosen {
+ stdout-path = &uarta;
+ };
+
+ aliases {
+ i2c0 = &pwr_i2c;
+ i2c1 = &gen2_i2c;
+
+ mmc0 = &sdmmc4; /* eMMC */
+ mmc1 = &sdmmc1; /* uSD slot */
+
+ rtc0 = &pmic;
+ rtc1 = "/rtc@7000e000";
+
+ spi0 = &spi4;
+
+ usb0 = &usb1;
+ usb1 = &usb3;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
+
+ host1x@50000000 {
+ dc@54200000 {
+ rgb {
+ status = "okay";
+
+ nvidia,panel = <&bridge>;
+ };
+ };
+ };
+
+ pinmux@70000868 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ /* SDMMC1 pinmux */
+ sdmmc1-clk {
+ nvidia,pins = "sdmmc1_clk_pz0";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc1-cmd {
+ nvidia,pins = "sdmmc1_dat3_py4",
+ "sdmmc1_dat2_py5",
+ "sdmmc1_dat1_py6",
+ "sdmmc1_dat0_py7",
+ "sdmmc1_cmd_pz1";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* SDMMC3 pinmux */
+ sdmmc3-clk {
+ nvidia,pins = "sdmmc3_clk_pa6";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3-cmd {
+ nvidia,pins = "sdmmc3_cmd_pa7",
+ "sdmmc3_dat3_pb4",
+ "sdmmc3_dat2_pb5",
+ "sdmmc3_dat1_pb6",
+ "sdmmc3_dat0_pb7";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3-dat6 {
+ nvidia,pins = "sdmmc3_dat6_pd3";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3-dat7 {
+ nvidia,pins = "sdmmc3_dat7_pd4";
+ nvidia,function = "spdif";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* SDMMC4 pinmux */
+ sdmmc4-clk {
+ nvidia,pins = "sdmmc4_clk_pcc4";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <1>;
+ nvidia,io-reset = <1>;
+ };
+ sdmmc4-cmd {
+ nvidia,pins = "sdmmc4_cmd_pt7",
+ "sdmmc4_dat0_paa0",
+ "sdmmc4_dat1_paa1",
+ "sdmmc4_dat2_paa2",
+ "sdmmc4_dat3_paa3",
+ "sdmmc4_dat4_paa4",
+ "sdmmc4_dat5_paa5",
+ "sdmmc4_dat6_paa6",
+ "sdmmc4_dat7_paa7",
+ "sdmmc4_rst_n_pcc3";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <1>;
+ nvidia,io-reset = <1>;
+ };
+ cam-mclk {
+ nvidia,pins = "cam_mclk_pcc0";
+ nvidia,function = "vi_alt3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* I2C pinmux */
+ gen1-i2c {
+ nvidia,pins = "gen1_i2c_scl_pc4",
+ "gen1_i2c_sda_pc5";
+ nvidia,function = "i2c1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <1>;
+ };
+ gen2-i2c {
+ nvidia,pins = "gen2_i2c_scl_pt5",
+ "gen2_i2c_sda_pt6";
+ nvidia,function = "i2c2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <1>;
+ };
+ cam-i2c {
+ nvidia,pins = "cam_i2c_scl_pbb1",
+ "cam_i2c_sda_pbb2";
+ nvidia,function = "i2c3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <1>;
+ };
+ ddc-i2c {
+ nvidia,pins = "ddc_scl_pv4",
+ "ddc_sda_pv5";
+ nvidia,function = "i2c4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <1>;
+ };
+ pwr-i2c {
+ nvidia,pins = "pwr_i2c_scl_pz6",
+ "pwr_i2c_sda_pz7";
+ nvidia,function = "i2cpwr";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <1>;
+ };
+
+ /* HDMI pinmux */
+ hdmi-cec {
+ nvidia,pins = "hdmi_cec_pee3";
+ nvidia,function = "cec";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+ };
+ hdmi-int {
+ nvidia,pins = "hdmi_int_pn7";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* UART-A */
+ ulpi-data0 {
+ nvidia,pins = "ulpi_data0_po1";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi-data1 {
+ nvidia,pins = "ulpi_data1_po2";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ulpi-data2 {
+ nvidia,pins = "ulpi_data2_po3";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* UART-B */
+ uartb-txd-rxd {
+ nvidia,pins = "uart2_txd_pc2",
+ "uart2_rxd_pc3";
+ nvidia,function = "uartb";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uartb-cts-rts {
+ nvidia,pins = "uart2_cts_n_pj5",
+ "uart2_rts_n_pj6";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* UART-C */
+ uartc-rxd-cts {
+ nvidia,pins = "uart3_cts_n_pa1",
+ "uart3_rxd_pw7";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uartc-txd-rts {
+ nvidia,pins = "uart3_rts_n_pc0",
+ "uart3_txd_pw6";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* I2S pinmux */
+ dap1-fs {
+ nvidia,pins = "dap1_fs_pn0";
+ nvidia,function = "i2s0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap1-din {
+ nvidia,pins = "dap1_din_pn1",
+ "dap1_dout_pn2",
+ "dap1_sclk_pn3";
+ nvidia,function = "i2s0";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap2-fs-pa2 {
+ nvidia,pins = "dap2_fs_pa2",
+ "dap2_sclk_pa3",
+ "dap2_din_pa4",
+ "dap2_dout_pa5";
+ nvidia,function = "i2s1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap3-fs-pp0 {
+ nvidia,pins = "dap3_fs_pp0",
+ "dap3_din_pp1",
+ "dap3_dout_pp2";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap3-sclk-pp3 {
+ nvidia,pins = "dap3_sclk_pp3";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap4-fs-pp4 {
+ nvidia,pins = "dap4_fs_pp4",
+ "dap4_din_pp5",
+ "dap4_dout_pp6",
+ "dap4_sclk_pp7";
+ nvidia,function = "i2s3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pbb0 {
+ nvidia,pins = "pbb0", "pbb7";
+ nvidia,function = "i2s4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pcc1 {
+ nvidia,pins = "pcc1";
+ nvidia,function = "i2s4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pcc2 {
+ nvidia,pins = "pcc2";
+ nvidia,function = "i2s4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PCI-e pinmux */
+ pex-l2-rst-n {
+ nvidia,pins = "pex_l2_rst_n_pcc6",
+ "pex_l2_clkreq_n_pcc7",
+ "pex_l0_prsnt_n_pdd0",
+ "pex_l0_rst_n_pdd1",
+ "pex_l0_clkreq_n_pdd2",
+ "pex_wake_n_pdd3",
+ "pex_l1_prsnt_n_pdd4",
+ "pex_l1_rst_n_pdd5",
+ "pex_l1_clkreq_n_pdd6",
+ "pex_l2_prsnt_n_pdd7";
+ nvidia,function = "pcie";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* SPI pinmux */
+ spi1-miso-px7 {
+ nvidia,pins = "spi1_miso_px7";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ulpi-clk-py0 {
+ nvidia,pins = "ulpi_clk_py0",
+ "ulpi_dir_py1",
+ "ulpi_nxt_py2",
+ "ulpi_stp_py3";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ulpi-data7-po0 {
+ nvidia,pins = "ulpi_data7_po0",
+ "ulpi_data5_po6",
+ "ulpi_data6_po7",
+ "spi1_mosi_px4",
+ "spi1_sck_px5";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ulpi-data4-po5 {
+ nvidia,pins = "ulpi_data4_po5";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ spi1-cs0-n-px6 {
+ nvidia,pins = "spi1_cs0_n_px6";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi-data3-po4 {
+ nvidia,pins = "ulpi_data3_po4";
+ nvidia,function = "spi3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ spi2-cs1-n-pw2 {
+ nvidia,pins = "spi2_cs1_n_pw2",
+ "spi2_cs2_n_pw3";
+ nvidia,function = "spi3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi-a17-pb0 {
+ nvidia,pins = "gmi_a17_pb0",
+ "gmi_a18_pb1",
+ "gmi_a16_pj7",
+ "gmi_a19_pk7";
+ nvidia,function = "spi4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ spi2-mosi-px0 {
+ nvidia,pins = "spi2_mosi_px0";
+ nvidia,function = "spi6";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ spi2-miso-px1 {
+ nvidia,pins = "spi2_miso_px1";
+ nvidia,function = "spi6";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ spi2-sck-px2 {
+ nvidia,pins = "spi2_sck_px2";
+ nvidia,function = "spi6";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Display A pinmux */
+ lcd-pclk {
+ nvidia,pins = "lcd_pclk_pb3",
+ "lcd_dc1_pd2",
+ "lcd_d0_pe0",
+ "lcd_d1_pe1",
+ "lcd_d2_pe2",
+ "lcd_d3_pe3",
+ "lcd_d4_pe4",
+ "lcd_d5_pe5",
+ "lcd_d6_pe6",
+ "lcd_d7_pe7",
+ "lcd_d8_pf0",
+ "lcd_d9_pf1",
+ "lcd_d10_pf2",
+ "lcd_d11_pf3",
+ "lcd_d12_pf4",
+ "lcd_d13_pf5",
+ "lcd_d14_pf6",
+ "lcd_d15_pf7",
+ "lcd_de_pj1",
+ "lcd_d16_pm0",
+ "lcd_d17_pm1",
+ "lcd_d18_pm2",
+ "lcd_d19_pm3",
+ "lcd_d20_pm4",
+ "lcd_d21_pm5",
+ "lcd_d22_pm6",
+ "lcd_d23_pm7",
+ "lcd_sdout_pn5",
+ "lcd_dc0_pn6",
+ "lcd_m1_pw1",
+ "lcd_sdin_pz2",
+ "lcd_sck_pz4";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ lcd-pwr0 {
+ nvidia,pins = "lcd_pwr0_pb2",
+ "lcd_pwr2_pc6";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ lcd-pwr1 {
+ nvidia,pins = "lcd_pwr1_pc1";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ lcd-hsync {
+ nvidia,pins = "lcd_hsync_pj3",
+ "lcd_vsync_pj4",
+ "lcd_cs0_n_pn4",
+ "lcd_cs1_n_pw0",
+ "lcd_wr_n_pz3";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ crt-hsync-pv6 {
+ nvidia,pins = "crt_hsync_pv6",
+ "crt_vsync_pv7";
+ nvidia,function = "crt";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ blink {
+ nvidia,pins = "clk_32k_out_pa0";
+ nvidia,function = "blink";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* KBC keys */
+ kb-pins {
+ nvidia,pins = "kb_col0_pq0",
+ "kb_col1_pq1",
+ "kb_col2_pq2",
+ "kb_col3_pq3",
+ "kb_col4_pq4",
+ "kb_col5_pq5",
+ "kb_col6_pq6",
+ "kb_col7_pq7",
+ "kb_row0_pr0",
+ "kb_row1_pr1",
+ "kb_row2_pr2",
+ "kb_row3_pr3",
+ "kb_row4_pr4",
+ "kb_row5_pr5",
+ "kb_row6_pr6",
+ "kb_row7_pr7",
+ "kb_row8_ps0",
+ "kb_row9_ps1",
+ "kb_row10_ps2",
+ "kb_row11_ps3",
+ "kb_row12_ps4",
+ "kb_row13_ps5",
+ "kb_row14_ps6",
+ "kb_row15_ps7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* SPDIF pinmux */
+ spdif-pins {
+ nvidia,pins = "spdif_out_pk5",
+ "spdif_in_pk6";
+ nvidia,function = "spdif";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ jtag-rtck {
+ nvidia,pins = "jtag_rtck_pu7";
+ nvidia,function = "rtck";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* GMI pinmux */
+ gmi-wp-n-pc7 {
+ nvidia,pins = "gmi_wp_n_pc7";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3-dat5-pd0 {
+ nvidia,pins = "sdmmc3_dat5_pd0",
+ "gmi_ad8_ph0";
+ nvidia,function = "pwm0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ sdmmc3-dat4-pd1 {
+ nvidia,pins = "sdmmc3_dat4_pd1";
+ nvidia,function = "pwm1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi-ad12-ph4 {
+ nvidia,pins = "gmi_ad12_ph4",
+ "gmi_cs4_n_pk2",
+ "pv1";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi-dqs-pi2 {
+ nvidia,pins = "gmi_dqs_pi2";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi-ad13-ph5 {
+ nvidia,pins = "gmi_ad13_ph5",
+ "gmi_ad14_ph6",
+ "pu1",
+ "pu2",
+ "pv2",
+ "pv3";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi-ad0-pg0 {
+ nvidia,pins = "gmi_ad0_pg0",
+ "gmi_ad1_pg1",
+ "gmi_ad2_pg2",
+ "gmi_ad3_pg3",
+ "gmi_ad4_pg4",
+ "gmi_ad5_pg5",
+ "gmi_ad6_pg6",
+ "gmi_ad7_pg7",
+ "gmi_ad15_ph7";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi-ad9-ph1 {
+ nvidia,pins = "gmi_ad9_ph1";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi-ad10-ph2 {
+ nvidia,pins = "gmi_ad10_ph2";
+ nvidia,function = "pwm2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi-ad11-ph3 {
+ nvidia,pins = "gmi_ad11_ph3";
+ nvidia,function = "pwm3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi-wr-n-pi0 {
+ nvidia,pins = "gmi_wr_n_pi0",
+ "gmi_oe_n_pi1",
+ "gmi_adv_n_pk0",
+ "gmi_clk_pk1";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi-cs6-n-pi3 {
+ nvidia,pins = "gmi_cs6_n_pi3",
+ "gmi_cs7_n_pi6";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi-iordy-pi5 {
+ nvidia,pins = "gmi_iordy_pi5";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi-wait-pi7 {
+ nvidia,pins = "gmi_wait_pi7";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi-cs0-n-pj0 {
+ nvidia,pins = "gmi_cs0_n_pj0",
+ "gmi_cs1_n_pj2",
+ "gmi_cs2_n_pk3";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi-cs3-n-pk4 {
+ nvidia,pins = "gmi_cs3_n_pk4",
+ "pv0";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* VI pinmux */
+ vi-d1-pd5 {
+ nvidia,pins = "vi_d1_pd5";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <1>;
+ nvidia,io-reset = <1>;
+ };
+ vi-vsync-pd6 {
+ nvidia,pins = "vi_vsync_pd6",
+ "vi_d7_pl5",
+ "vi_d10_pt2",
+ "vi_d0_pt4";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <1>;
+ nvidia,io-reset = <2>;
+ };
+ vi-hsync-pd7 {
+ nvidia,pins = "vi_hsync_pd7",
+ "vi_d6_pl4",
+ "vi_d8_pl6",
+ "vi_d9_pl7",
+ "vi_pclk_pt0";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,lock = <1>;
+ nvidia,io-reset = <1>;
+ };
+ vi-d2-pl0 {
+ nvidia,pins = "vi_d2_pl0",
+ "vi_d3_pl1",
+ "vi_d4_pl2";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <1>;
+ nvidia,io-reset = <1>;
+ };
+ vi-mclk-pt1 {
+ nvidia,pins = "vi_mclk_pt1";
+ nvidia,function = "vi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <1>;
+ nvidia,io-reset = <2>;
+ };
+ vi-d11-pt3 {
+ nvidia,pins = "vi_d11_pt3";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <1>;
+ nvidia,io-reset = <1>;
+ };
+ vi-d5-pl3 {
+ nvidia,pins = "vi_d5_pl3";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <1>;
+ nvidia,io-reset = <1>;
+ };
+
+ /* PORT U */
+ pu0 {
+ nvidia,pins = "pu0";
+ nvidia,function = "owr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pu3 {
+ nvidia,pins = "pu3";
+ nvidia,function = "pwm0";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pu4 {
+ nvidia,pins = "pu4";
+ nvidia,function = "pwm1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pu5 {
+ nvidia,pins = "pu5";
+ nvidia,function = "pwm2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pu6 {
+ nvidia,pins = "pu6";
+ nvidia,function = "pwm3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PORT BB */
+ pbb3 {
+ nvidia,pins = "pbb3";
+ nvidia,function = "vgp3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pbb4 {
+ nvidia,pins = "pbb4";
+ nvidia,function = "vgp4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pbb5 {
+ nvidia,pins = "pbb5";
+ nvidia,function = "vgp5";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pbb6 {
+ nvidia,pins = "pbb6";
+ nvidia,function = "vgp6";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* CLK pinmux */
+ clk1-out {
+ nvidia,pins = "clk1_out_pw4";
+ nvidia,function = "extperiph1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ clk1-req {
+ nvidia,pins = "clk1_req_pee2";
+ nvidia,function = "dap";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ clk2-out {
+ nvidia,pins = "clk2_out_pw5";
+ nvidia,function = "extperiph2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ clk2-req {
+ nvidia,pins = "clk2_req_pcc5";
+ nvidia,function = "dap";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ clk3-out {
+ nvidia,pins = "clk3_out_pee0";
+ nvidia,function = "extperiph3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ clk3-req {
+ nvidia,pins = "clk3_req_pee1";
+ nvidia,function = "dev3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sys-clk-req {
+ nvidia,pins = "sys_clk_req_pz5";
+ nvidia,function = "sysclk";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ owr {
+ nvidia,pins = "owr";
+ nvidia,function = "owr";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* GPIO power/drive control */
+ drive-sdio1 {
+ nvidia,pins = "drive_sdio1",
+ "drive_sdio3";
+ nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+ nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+ nvidia,pull-down-strength = <46>;
+ nvidia,pull-up-strength = <42>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
+ };
+ };
+ };
+
+ uarta: serial@70006000 {
+ status = "okay";
+ };
+
+ pwm: pwm@7000a000 {
+ status = "okay";
+ };
+
+ gen2_i2c: i2c@7000c400 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ bridge: dp501@8 {
+ compatible = "parade,dp501";
+ reg = <0x08>;
+
+ enable-gpios = <&gpio TEGRA_GPIO(C, 1) GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_LOW>;
+
+ power-supply = <&vdd_edp_reg>;
+
+ panel = <&panel>;
+ };
+ };
+
+ pwr_i2c: i2c@7000d000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* Texas Instruments TPS659110 PMIC */
+ pmic: tps65911@2d {
+ compatible = "ti,tps65911";
+ reg = <0x2d>;
+
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
+ ti,system-power-controller;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ regulators {
+ vdd_1v8_vio: vddio {
+ regulator-name = "vdd_1v8_gen";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vddio_usd: ldo3 {
+ regulator-name = "vddio_usd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+ };
+
+ spi4: spi@7000da00 {
+ status = "okay";
+ spi-max-frequency = <25000000>;
+
+ spi-flash@1 {
+ compatible = "winbond,w25q32", "jedec,spi-nor";
+ reg = <1>;
+ spi-max-frequency = <20000000>;
+ };
+ };
+
+ kbc@7000e200 {
+ status = "okay";
+ nvidia,debounce-delay-ms = <2>;
+ nvidia,repeat-delay-ms = <160>;
+ nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
+ nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
+
+ linux,keymap = <
+ MATRIX_KEY(0x00, 0x01, KEY_TAB)
+ MATRIX_KEY(0x00, 0x02, KEY_GRAVE)
+ MATRIX_KEY(0x00, 0x03, KEY_1)
+ MATRIX_KEY(0x00, 0x04, KEY_Q)
+ MATRIX_KEY(0x00, 0x05, KEY_A)
+
+ MATRIX_KEY(0x01, 0x06, KEY_RIGHTALT)
+ MATRIX_KEY(0x01, 0x07, KEY_LEFTALT)
+
+ MATRIX_KEY(0x02, 0x00, KEY_F3)
+ MATRIX_KEY(0x02, 0x01, KEY_F4)
+ MATRIX_KEY(0x02, 0x02, KEY_CAPSLOCK)
+ MATRIX_KEY(0x02, 0x03, KEY_3)
+ MATRIX_KEY(0x02, 0x04, KEY_E)
+ MATRIX_KEY(0x02, 0x05, KEY_D)
+ MATRIX_KEY(0x02, 0x06, KEY_C)
+ MATRIX_KEY(0x02, 0x07, KEY_SPACE)
+
+ MATRIX_KEY(0x03, 0x00, KEY_F2)
+ MATRIX_KEY(0x03, 0x01, KEY_F1)
+ MATRIX_KEY(0x03, 0x02, KEY_ESC)
+ MATRIX_KEY(0x03, 0x03, KEY_2)
+ MATRIX_KEY(0x03, 0x04, KEY_W)
+ MATRIX_KEY(0x03, 0x05, KEY_S)
+ MATRIX_KEY(0x03, 0x06, KEY_X)
+ MATRIX_KEY(0x03, 0x07, KEY_Z)
+
+ MATRIX_KEY(0x04, 0x00, KEY_LEFTCTRL)
+
+ MATRIX_KEY(0x05, 0x00, KEY_G)
+ MATRIX_KEY(0x05, 0x01, KEY_T)
+ MATRIX_KEY(0x05, 0x02, KEY_5)
+ MATRIX_KEY(0x05, 0x03, KEY_4)
+ MATRIX_KEY(0x05, 0x04, KEY_R)
+ MATRIX_KEY(0x05, 0x05, KEY_F)
+ MATRIX_KEY(0x05, 0x06, KEY_V)
+ MATRIX_KEY(0x05, 0x07, KEY_B)
+
+ MATRIX_KEY(0x06, 0x00, KEY_H)
+ MATRIX_KEY(0x06, 0x01, KEY_Y)
+ MATRIX_KEY(0x06, 0x02, KEY_6)
+ MATRIX_KEY(0x06, 0x03, KEY_7)
+ MATRIX_KEY(0x06, 0x04, KEY_U)
+ MATRIX_KEY(0x06, 0x05, KEY_J)
+ MATRIX_KEY(0x06, 0x06, KEY_M)
+ MATRIX_KEY(0x06, 0x07, KEY_N)
+
+ MATRIX_KEY(0x07, 0x01, KEY_F11)
+ MATRIX_KEY(0x07, 0x02, KEY_F10)
+ MATRIX_KEY(0x07, 0x03, KEY_9)
+ MATRIX_KEY(0x07, 0x04, KEY_O)
+ MATRIX_KEY(0x07, 0x05, KEY_L)
+ MATRIX_KEY(0x07, 0x06, KEY_DOT)
+ MATRIX_KEY(0x07, 0x07, KEY_DOWN)
+
+ MATRIX_KEY(0x08, 0x04, KEY_RIGHTSHIFT)
+ MATRIX_KEY(0x08, 0x05, KEY_LEFTSHIFT)
+
+ MATRIX_KEY(0x09, 0x00, KEY_F7)
+ MATRIX_KEY(0x09, 0x01, KEY_F6)
+ MATRIX_KEY(0x09, 0x02, KEY_F5)
+ MATRIX_KEY(0x09, 0x03, KEY_8)
+ MATRIX_KEY(0x09, 0x04, KEY_I)
+ MATRIX_KEY(0x09, 0x05, KEY_K)
+ MATRIX_KEY(0x09, 0x06, KEY_COMMA)
+
+ MATRIX_KEY(0x0A, 0x00, KEY_F8)
+ MATRIX_KEY(0x0A, 0x01, KEY_F9)
+ MATRIX_KEY(0x0A, 0x02, KEY_BACKSLASH)
+ MATRIX_KEY(0x0A, 0x03, KEY_102ND)
+ MATRIX_KEY(0x0A, 0x04, KEY_COMPOSE)
+ MATRIX_KEY(0x0A, 0x05, KEY_LEFT)
+
+ MATRIX_KEY(0x0B, 0x00, KEY_RIGHTCTRL)
+ MATRIX_KEY(0x0B, 0x03, KEY_FN)
+
+ MATRIX_KEY(0x0C, 0x02, KEY_LEFTMETA)
+
+ MATRIX_KEY(0x0D, 0x00, KEY_MINUS)
+ MATRIX_KEY(0x0D, 0x02, KEY_0)
+ MATRIX_KEY(0x0D, 0x03, KEY_P)
+ MATRIX_KEY(0x0D, 0x04, KEY_LEFTBRACE)
+ MATRIX_KEY(0x0D, 0x05, KEY_SEMICOLON)
+ MATRIX_KEY(0x0D, 0x06, KEY_SLASH)
+ MATRIX_KEY(0x0D, 0x07, KEY_UP)
+
+ MATRIX_KEY(0x0E, 0x01, KEY_PRINT)
+ MATRIX_KEY(0x0E, 0x02, KEY_EQUAL)
+ MATRIX_KEY(0x0E, 0x03, KEY_BACKSPACE)
+ MATRIX_KEY(0x0E, 0x04, KEY_RIGHTBRACE)
+ MATRIX_KEY(0x0E, 0x06, KEY_APOSTROPHE)
+ MATRIX_KEY(0x0E, 0x07, KEY_ENTER)
+
+ MATRIX_KEY(0x0F, 0x02, KEY_DELETE)
+ MATRIX_KEY(0x0F, 0x03, KEY_PAGEUP)
+ MATRIX_KEY(0x0F, 0x04, KEY_INSERT)
+ MATRIX_KEY(0x0F, 0x05, KEY_F12)
+ MATRIX_KEY(0x0F, 0x06, KEY_PAGEDOWN)
+ MATRIX_KEY(0x0F, 0x07, KEY_RIGHT)
+ >;
+ };
+
+ sdmmc1: sdhci@78000000 {
+ status = "okay";
+ bus-width = <4>;
+
+ cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+
+ vmmc-supply = <&vdd_usd>;
+ vqmmc-supply = <&vddio_usd>;
+ };
+
+ sdmmc4: sdhci@78000600 {
+ status = "okay";
+ bus-width = <8>;
+ non-removable;
+
+ vmmc-supply = <&vcore_emmc>;
+ vqmmc-supply = <&vdd_1v8_vio>;
+ };
+
+ /* LEFT */
+ usb1: usb@7d000000 {
+ status = "okay";
+ dr_mode = "otg";
+ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
+ };
+
+ /* RIGHT */
+ usb3: usb@7d008000 {
+ status = "okay";
+ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+
+ enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+ pwms = <&pwm 0 4000000>;
+
+ brightness-levels = <1 35 70 105 140 175 210 255>;
+ default-brightness-level = <5>;
+ };
+
+ clk32k_in: clock-32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "ref-oscillator";
+ };
+
+ extcon-keys {
+ compatible = "gpio-keys";
+
+ switch-hall-sensor {
+ label = "Lid sensor";
+ gpios = <&gpio TEGRA_GPIO(J, 2) GPIO_ACTIVE_LOW>;
+ linux,code = <SW_LID>;
+ };
+
+ switch-rotation-lock {
+ label = "Rotation Lock";
+ gpios = <&gpio TEGRA_GPIO(K, 4) GPIO_ACTIVE_LOW>;
+ linux,code = <SW_ROTATE_LOCK>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ key-power {
+ label = "Power";
+ gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_ENTER>;
+ };
+
+ key-volume-down {
+ label = "Volume Down";
+ gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_DOWN>;
+ };
+
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&gpio TEGRA_GPIO(K, 5) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_UP>;
+ };
+
+ key-windows-button {
+ label = "Windows Button";
+ gpios = <&gpio TEGRA_GPIO(O, 5) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_ENTER>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-capslock {
+ label = "Capslock";
+ gpios = <&gpio TEGRA_GPIO(U, 2) GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "kbd-capslock";
+ default-state = "off";
+ };
+ };
+
+ panel: panel {
+ compatible = "simple-panel";
+
+ power-supply = <&vdd_pnl_reg>;
+ ddc-i2c-bus = <&gen2_i2c>;
+
+ backlight = <&backlight>;
+ };
+
+ vdd_edp_reg: regulator-edp {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_edp";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ gpio = <&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vcore_emmc: regulator-emmc {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_emmc_core";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vdd_pnl_reg: regulator-pnl {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_panel";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vdd_usd: regulator-usd {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_usd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
diff --git a/arch/arm/dts/tegra30-microsoft-surface-rt.dts b/arch/arm/dts/tegra30-microsoft-surface-rt.dts
new file mode 100644
index 0000000..6810350
--- /dev/null
+++ b/arch/arm/dts/tegra30-microsoft-surface-rt.dts
@@ -0,0 +1,1083 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "tegra30.dtsi"
+
+/ {
+ model = "Microsoft Surface RT Tablet";
+ compatible = "microsoft,surface-rt", "nvidia,tegra30";
+
+ chosen {
+ stdout-path = &uarta;
+ };
+
+ aliases {
+ i2c0 = &pwr_i2c;
+
+ mmc0 = &sdmmc4; /* eMMC */
+ mmc1 = &sdmmc1; /* uSD slot */
+
+ rtc0 = &pmic;
+ rtc1 = "/rtc@7000e000";
+
+ spi0 = &spi4;
+
+ usb0 = &usb1;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
+
+ host1x@50000000 {
+ dc@54200000 {
+ rgb {
+ status = "okay";
+
+ nvidia,panel = <&panel>;
+ };
+ };
+ };
+
+ gpio@6000d000 {
+ /* in case usb vbus is on for some reason */
+ usb-vbus-hog {
+ gpio-hog;
+ gpios = <TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>;
+ output-low;
+ };
+ };
+
+ pinmux@70000868 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ /* SDMMC1 pinmux */
+ sdmmc1-clk {
+ nvidia,pins = "sdmmc1_clk_pz0";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc1-cmd {
+ nvidia,pins = "sdmmc1_dat3_py4",
+ "sdmmc1_dat2_py5",
+ "sdmmc1_dat1_py6",
+ "sdmmc1_dat0_py7",
+ "sdmmc1_cmd_pz1";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* SDMMC3 pinmux */
+ sdmmc3-clk {
+ nvidia,pins = "sdmmc3_clk_pa6";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3-cmd {
+ nvidia,pins = "sdmmc3_cmd_pa7",
+ "sdmmc3_dat3_pb4",
+ "sdmmc3_dat2_pb5",
+ "sdmmc3_dat1_pb6",
+ "sdmmc3_dat0_pb7",
+ "sdmmc3_dat5_pd0";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* SDMMC4 pinmux */
+ sdmmc4-clk {
+ nvidia,pins = "sdmmc4_clk_pcc4";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <1>;
+ nvidia,io-reset = <1>;
+ };
+ sdmmc4-cmd {
+ nvidia,pins = "sdmmc4_cmd_pt7",
+ "sdmmc4_dat0_paa0",
+ "sdmmc4_dat1_paa1",
+ "sdmmc4_dat2_paa2",
+ "sdmmc4_dat3_paa3",
+ "sdmmc4_dat4_paa4",
+ "sdmmc4_dat5_paa5",
+ "sdmmc4_dat6_paa6",
+ "sdmmc4_dat7_paa7",
+ "sdmmc4_rst_n_pcc3";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <1>;
+ nvidia,io-reset = <1>;
+ };
+ cam-mclk {
+ nvidia,pins = "cam_mclk_pcc0";
+ nvidia,function = "vi_alt3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* I2C pinmux */
+ gen1-i2c {
+ nvidia,pins = "gen1_i2c_scl_pc4",
+ "gen1_i2c_sda_pc5";
+ nvidia,function = "i2c1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ };
+ gen2-i2c {
+ nvidia,pins = "gen2_i2c_scl_pt5",
+ "gen2_i2c_sda_pt6";
+ nvidia,function = "i2c2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ };
+ cam-i2c {
+ nvidia,pins = "cam_i2c_scl_pbb1",
+ "cam_i2c_sda_pbb2";
+ nvidia,function = "i2c3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ };
+ ddc-i2c {
+ nvidia,pins = "ddc_scl_pv4",
+ "ddc_sda_pv5";
+ nvidia,function = "i2c4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ };
+ pwr-i2c {
+ nvidia,pins = "pwr_i2c_scl_pz6",
+ "pwr_i2c_sda_pz7";
+ nvidia,function = "i2cpwr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ };
+
+ /* HDMI pinmux */
+ hdmi-cec {
+ nvidia,pins = "hdmi_cec_pee3";
+ nvidia,function = "cec";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ hdmi-hpd {
+ nvidia,pins = "hdmi_int_pn7";
+ nvidia,function = "hdmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* UART-A */
+ ulpi-data0-po1 {
+ nvidia,pins = "ulpi_data0_po1";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi-data1-po2 {
+ nvidia,pins = "ulpi_data1_po2";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ulpi-data2-po3 {
+ nvidia,pins = "ulpi_data2_po3",
+ "ulpi_data3_po4";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* UART-B */
+ uartb-txd-rxd {
+ nvidia,pins = "uart2_txd_pc2",
+ "uart2_rxd_pc3";
+ nvidia,function = "uartb";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uartb-cts-rts {
+ nvidia,pins = "uart2_cts_n_pj5",
+ "uart2_rts_n_pj6";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* UART-C */
+ uartc-rxd-cts {
+ nvidia,pins = "uart3_cts_n_pa1",
+ "uart3_rxd_pw7";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uartc-txd-rts {
+ nvidia,pins = "uart3_rts_n_pc0",
+ "uart3_txd_pw6";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* I2S pinmux */
+ dap-i2s0-out {
+ nvidia,pins = "dap1_fs_pn0",
+ "dap1_sclk_pn3";
+ nvidia,function = "i2s0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap-i2s0-in {
+ nvidia,pins = "dap1_din_pn1",
+ "dap1_dout_pn2";
+ nvidia,function = "i2s0";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap-i2s1 {
+ nvidia,pins = "dap2_fs_pa2",
+ "dap2_sclk_pa3",
+ "dap2_din_pa4",
+ "dap2_dout_pa5";
+ nvidia,function = "i2s1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap-i2s2 {
+ nvidia,pins = "dap3_fs_pp0",
+ "dap3_din_pp1",
+ "dap3_dout_pp2",
+ "dap3_sclk_pp3";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap-i2s3 {
+ nvidia,pins = "dap4_fs_pp4",
+ "dap4_din_pp5",
+ "dap4_dout_pp6",
+ "dap4_sclk_pp7";
+ nvidia,function = "i2s3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pbb0 {
+ nvidia,pins = "pbb0", "pbb7";
+ nvidia,function = "i2s4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pcc1 {
+ nvidia,pins = "pcc1";
+ nvidia,function = "i2s4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pcc2 {
+ nvidia,pins = "pcc2";
+ nvidia,function = "i2s4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PCI-e pinmux */
+ pex-l2-rst-n {
+ nvidia,pins = "pex_l2_rst_n_pcc6",
+ "pex_wake_n_pdd3",
+ "pex_l1_rst_n_pdd5";
+ nvidia,function = "pcie";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pex-l2-clkreq-n {
+ nvidia,pins = "pex_l2_clkreq_n_pcc7",
+ "pex_l0_prsnt_n_pdd0",
+ "pex_l0_rst_n_pdd1",
+ "pex_l0_clkreq_n_pdd2",
+ "pex_l1_prsnt_n_pdd4",
+ "pex_l1_clkreq_n_pdd6",
+ "pex_l2_prsnt_n_pdd7";
+ nvidia,function = "pcie";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* SPI pinmux */
+ spi1-miso {
+ nvidia,pins = "spi1_miso_px7";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ulpi-clk {
+ nvidia,pins = "ulpi_clk_py0",
+ "ulpi_dir_py1",
+ "ulpi_nxt_py2",
+ "ulpi_stp_py3";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ulpi-data7 {
+ nvidia,pins = "ulpi_data7_po0",
+ "ulpi_data4_po5",
+ "ulpi_data5_po6",
+ "ulpi_data6_po7",
+ "spi1_mosi_px4",
+ "spi1_sck_px5",
+ "spi1_cs0_n_px6";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ spi2-cs1-n {
+ nvidia,pins = "spi2_cs1_n_pw2";
+ nvidia,function = "spi3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ spi2-cs2-n {
+ nvidia,pins = "spi2_cs2_n_pw3";
+ nvidia,function = "spi3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi-a17 {
+ nvidia,pins = "gmi_a17_pb0",
+ "gmi_a18_pb1",
+ "gmi_a16_pj7",
+ "gmi_a19_pk7";
+ nvidia,function = "spi4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ spi2-sck {
+ nvidia,pins = "spi2_sck_px2";
+ nvidia,function = "spi6";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Display A pinmux */
+ lcd-pclk {
+ nvidia,pins = "lcd_pclk_pb3",
+ "lcd_dc1_pd2",
+ "lcd_d0_pe0",
+ "lcd_d1_pe1",
+ "lcd_d2_pe2",
+ "lcd_d3_pe3",
+ "lcd_d4_pe4",
+ "lcd_d5_pe5",
+ "lcd_d6_pe6",
+ "lcd_d7_pe7",
+ "lcd_d8_pf0",
+ "lcd_d9_pf1",
+ "lcd_d10_pf2",
+ "lcd_d11_pf3",
+ "lcd_d12_pf4",
+ "lcd_d13_pf5",
+ "lcd_d14_pf6",
+ "lcd_d15_pf7",
+ "lcd_de_pj1",
+ "lcd_d16_pm0",
+ "lcd_d17_pm1",
+ "lcd_d18_pm2",
+ "lcd_d19_pm3",
+ "lcd_d20_pm4",
+ "lcd_d21_pm5",
+ "lcd_d22_pm6",
+ "lcd_d23_pm7",
+ "lcd_sdout_pn5",
+ "lcd_dc0_pn6",
+ "lcd_m1_pw1",
+ "lcd_sdin_pz2",
+ "lcd_sck_pz4";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ lcd-pwr1 {
+ nvidia,pins = "lcd_pwr1_pc1",
+ "lcd_pwr2_pc6";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ lcd-hsync {
+ nvidia,pins = "lcd_hsync_pj3",
+ "lcd_vsync_pj4",
+ "lcd_cs0_n_pn4",
+ "lcd_cs1_n_pw0",
+ "lcd_wr_n_pz3";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ lcd-pwr0 {
+ nvidia,pins = "lcd_pwr0_pb2";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ crt-hsync-pv6 {
+ nvidia,pins = "crt_hsync_pv6",
+ "crt_vsync_pv7";
+ nvidia,function = "crt";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ blink {
+ nvidia,pins = "clk_32k_out_pa0";
+ nvidia,function = "blink";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* KBC keys */
+ kb-col0 {
+ nvidia,pins = "kb_col0_pq0",
+ "kb_col1_pq1",
+ "kb_col2_pq2",
+ "kb_col3_pq3",
+ "kb_col4_pq4",
+ "kb_col5_pq5",
+ "kb_col6_pq6",
+ "kb_col7_pq7",
+ "kb_row12_ps4";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb-row0 {
+ nvidia,pins = "kb_row0_pr0",
+ "kb_row1_pr1",
+ "kb_row5_pr5";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb-row2 {
+ nvidia,pins = "kb_row2_pr2",
+ "kb_row3_pr3",
+ "kb_row6_pr6",
+ "kb_row7_pr7",
+ "kb_row11_ps3";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb-row4 {
+ nvidia,pins = "kb_row4_pr4",
+ "kb_row9_ps1";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb-row8 {
+ nvidia,pins = "kb_row8_ps0",
+ "kb_row10_ps2";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb-row13 {
+ nvidia,pins = "kb_row13_ps5",
+ "kb_row14_ps6",
+ "kb_row15_ps7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* SPDIF pinmux */
+ spdif-pins {
+ nvidia,pins = "spdif_out_pk5",
+ "spdif_in_pk6";
+ nvidia,function = "spdif";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3-dat6 {
+ nvidia,pins = "sdmmc3_dat6_pd3",
+ "sdmmc3_dat7_pd4";
+ nvidia,function = "spdif";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ jtag-rtck {
+ nvidia,pins = "jtag_rtck_pu7";
+ nvidia,function = "rtck";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* GMI pinmux */
+ gmi-wp-n {
+ nvidia,pins = "gmi_wp_n_pc7",
+ "gmi_cs7_n_pi6";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3-dat4 {
+ nvidia,pins = "sdmmc3_dat4_pd1",
+ "gmi_ad9_ph1";
+ nvidia,function = "pwm1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi-ad0-pg0 {
+ nvidia,pins = "gmi_ad0_pg0",
+ "gmi_ad1_pg1",
+ "gmi_ad2_pg2",
+ "gmi_ad3_pg3",
+ "gmi_ad4_pg4",
+ "gmi_ad5_pg5",
+ "gmi_ad6_pg6",
+ "gmi_ad7_pg7",
+ "gmi_ad15_ph7";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi-ad8 {
+ nvidia,pins = "gmi_ad8_ph0";
+ nvidia,function = "pwm0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi-ad10 {
+ nvidia,pins = "gmi_ad10_ph2",
+ "gmi_ad11_ph3";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi-ad12 {
+ nvidia,pins = "gmi_ad12_ph4",
+ "gmi_ad13_ph5",
+ "gmi_iordy_pi5",
+ "gmi_cs0_n_pj0",
+ "pu1",
+ "pu2",
+ "pv1",
+ "pv2",
+ "pv3";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi-wr-n {
+ nvidia,pins = "gmi_wr_n_pi0",
+ "gmi_oe_n_pi1",
+ "gmi_adv_n_pk0",
+ "gmi_clk_pk1";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi-dqs {
+ nvidia,pins = "gmi_dqs_pi2";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi-wait {
+ nvidia,pins = "gmi_wait_pi7",
+ "gmi_cs2_n_pk3",
+ "gmi_cs3_n_pk4";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi-cs4-n {
+ nvidia,pins = "gmi_cs4_n_pk2";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi-ad14-ph6 {
+ nvidia,pins = "gmi_ad14_ph6";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* VI pinmux */
+ vi-d1-pd5 {
+ nvidia,pins = "vi_d1_pd5",
+ "vi_vsync_pd6",
+ "vi_d2_pl0",
+ "vi_d4_pl2",
+ "vi_d5_pl3",
+ "vi_d6_pl4",
+ "vi_pclk_pt0",
+ "vi_d10_pt2",
+ "vi_d0_pt4";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <1>;
+ nvidia,io-reset = <1>;
+ };
+ vi-d3-pl1 {
+ nvidia,pins = "vi_d3_pl1";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <1>;
+ nvidia,io-reset = <1>;
+ };
+ vi-hsync-pd7 {
+ nvidia,pins = "vi_hsync_pd7",
+ "vi_d7_pl5",
+ "vi_d8_pl6",
+ "vi_d9_pl7";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,lock = <1>;
+ nvidia,io-reset = <1>;
+ };
+ vi-mclk-pt1 {
+ nvidia,pins = "vi_mclk_pt1";
+ nvidia,function = "vi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <1>;
+ nvidia,io-reset = <1>;
+ };
+ vi-d11-pt3 {
+ nvidia,pins = "vi_d11_pt3";
+ nvidia,function = "ddr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,lock = <1>;
+ nvidia,io-reset = <1>;
+ };
+
+ /* PORT U */
+ pu0 {
+ nvidia,pins = "pu0";
+ nvidia,function = "owr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pu3 {
+ nvidia,pins = "pu3";
+ nvidia,function = "pwm0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pu4 {
+ nvidia,pins = "pu4";
+ nvidia,function = "pwm1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pu5 {
+ nvidia,pins = "pu5";
+ nvidia,function = "pwm2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pu6 {
+ nvidia,pins = "pu6";
+ nvidia,function = "pwm3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PORT V */
+ pv0 {
+ nvidia,pins = "pv0";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PORT BB */
+ pbb3 {
+ nvidia,pins = "pbb3";
+ nvidia,function = "vgp3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pbb4 {
+ nvidia,pins = "pbb4";
+ nvidia,function = "vgp4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pbb5 {
+ nvidia,pins = "pbb5";
+ nvidia,function = "vgp5";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pbb6 {
+ nvidia,pins = "pbb6";
+ nvidia,function = "vgp6";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* CLK pinmux */
+ clk1-out-pw4 {
+ nvidia,pins = "clk1_out_pw4";
+ nvidia,function = "extperiph1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ clk2-out-pw5 {
+ nvidia,pins = "clk2_out_pw5";
+ nvidia,function = "extperiph2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ clk2-req-pcc5 {
+ nvidia,pins = "clk2_req_pcc5",
+ "clk1_req_pee2";
+ nvidia,function = "dap";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ clk3-out-pee0 {
+ nvidia,pins = "clk3_out_pee0";
+ nvidia,function = "extperiph3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ clk3-req-pee1 {
+ nvidia,pins = "clk3_req_pee1";
+ nvidia,function = "dev3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sys-clk-req-pz5 {
+ nvidia,pins = "sys_clk_req_pz5";
+ nvidia,function = "sysclk";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ owr {
+ nvidia,pins = "owr";
+ nvidia,function = "owr";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* GPIO power/drive control */
+ drive-sdio1 {
+ nvidia,pins = "drive_sdio1",
+ "drive_sdio3";
+ nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+ nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+ nvidia,pull-down-strength = <46>;
+ nvidia,pull-up-strength = <42>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
+ };
+ };
+ };
+
+ uarta: serial@70006000 {
+ status = "okay";
+ };
+
+ pwm: pwm@7000a000 {
+ status = "okay";
+ };
+
+ pwr_i2c: i2c@7000d000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* Texas Instruments TPS659110 PMIC */
+ pmic: tps65911@2d {
+ compatible = "ti,tps65911";
+ reg = <0x2d>;
+
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
+ ti,system-power-controller;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ regulators {
+ vdd_1v8_vio: vddio {
+ regulator-name = "vdd_1v8_gen";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vddio_usd: ldo5 {
+ regulator-name = "vddio_usd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+ };
+
+ spi4: spi@7000da00 {
+ status = "okay";
+ spi-max-frequency = <25000000>;
+
+ spi-flash@1 {
+ compatible = "winbond,w25q32", "jedec,spi-nor";
+ reg = <1>;
+ spi-max-frequency = <20000000>;
+ };
+ };
+
+ sdmmc1: sdhci@78000000 {
+ status = "okay";
+ bus-width = <4>;
+
+ cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+
+ vmmc-supply = <&vdd_usd>;
+ vqmmc-supply = <&vddio_usd>;
+ };
+
+ sdmmc4: sdhci@78000600 {
+ status = "okay";
+ bus-width = <8>;
+ non-removable;
+
+ vmmc-supply = <&vdd_3v3_sys>;
+ vqmmc-supply = <&vdd_1v8_vio>;
+ };
+
+ /* Main USB port */
+ usb1: usb@7d000000 {
+ status = "okay";
+ dr_mode = "otg";
+ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+
+ enable-gpios = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>;
+ pwms = <&pwm 0 50000>;
+
+ brightness-levels = <1 35 70 105 140 175 210 255>;
+ default-brightness-level = <5>;
+ };
+
+ /* PMIC has a built-in 32KHz oscillator which is used by PMC */
+ clk32k_in: clock-32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "pmic-oscillator";
+ };
+
+ extcon-keys {
+ compatible = "gpio-keys";
+
+ switch-hall-sensor {
+ label = "Hall Sensor";
+ gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>;
+ linux,code = <SW_LID>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ key-power {
+ label = "Power";
+ gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_CANCEL>;
+ };
+
+ key-volume-down {
+ label = "Volume Down";
+ gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_DOWN>;
+ };
+
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&gpio TEGRA_GPIO(S, 7) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_UP>;
+ };
+
+ key-windows-button {
+ label = "Windows Button";
+ gpios = <&gpio TEGRA_GPIO(S, 5) GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_ENTER>;
+ };
+ };
+
+ panel: panel {
+ compatible = "simple-panel";
+
+ power-supply = <&vdd_pnl_reg>;
+ enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
+
+ backlight = <&backlight>;
+
+ display-timings {
+ timing@0 {
+ /* 1366x768@60Hz */
+ clock-frequency = <71980000>;
+
+ hactive = <1366>;
+ hfront-porch = <56>;
+ hback-porch = <106>;
+ hsync-len = <14>;
+
+ vactive = <768>;
+ vfront-porch = <3>;
+ vback-porch = <6>;
+ vsync-len = <1>;
+ };
+ };
+ };
+
+ vdd_3v3_sys: regulator-3v {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_3v3_sys";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_usd: regulator-usd {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_usd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vdd_pnl_reg: regulator-pnl {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_panel";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
diff --git a/arch/arm/dts/tegra30-wexler-qc750.dts b/arch/arm/dts/tegra30-wexler-qc750.dts
new file mode 100644
index 0000000..87c2a40
--- /dev/null
+++ b/arch/arm/dts/tegra30-wexler-qc750.dts
@@ -0,0 +1,1106 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+/* CPU Speedo ID 7, Soc Speedo ID 1, CPU Process: 4, Core Process: 0 */
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pmic/max77663.h>
+
+#include "tegra30.dtsi"
+
+/ {
+ model = "Wexler Tab 7t";
+ compatible = "wexler,qc750", "nvidia,tegra30";
+
+ chosen {
+ stdout-path = &uartd;
+ };
+
+ aliases {
+ i2c0 = &pwr_i2c;
+
+ mmc0 = &sdmmc4; /* eMMC */
+ mmc1 = &sdmmc1; /* uSD slot */
+
+ rtc0 = &pmic;
+ rtc1 = "/rtc@7000e000";
+
+ usb0 = µ_usb;
+ usb1 = &usb3; /* Full size USB */
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+
+ host1x@50000000 {
+ dc@54200000 {
+ rgb {
+ status = "okay";
+
+ nvidia,panel = <&panel>;
+ };
+ };
+ };
+
+ pinmux@70000868 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ /* SDMMC1 pinmux */
+ sdmmc1-clk {
+ nvidia,pins = "sdmmc1_clk_pz0";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc1-cmd {
+ nvidia,pins = "sdmmc1_dat3_py4",
+ "sdmmc1_dat2_py5",
+ "sdmmc1_dat1_py6",
+ "sdmmc1_dat0_py7",
+ "sdmmc1_cmd_pz1";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc1-cd {
+ nvidia,pins = "gmi_iordy_pi5";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* SDMMC3 pinmux */
+ sdmmc3-clk {
+ nvidia,pins = "sdmmc3_clk_pa6";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3-cmd {
+ nvidia,pins = "sdmmc3_cmd_pa7",
+ "sdmmc3_dat0_pb7",
+ "sdmmc3_dat1_pb6",
+ "sdmmc3_dat2_pb5",
+ "sdmmc3_dat3_pb4",
+ "sdmmc3_dat4_pd1",
+ "sdmmc3_dat5_pd0",
+ "sdmmc3_dat6_pd3",
+ "sdmmc3_dat7_pd4";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* SDMMC4 pinmux */
+ sdmmc4-clk {
+ nvidia,pins = "sdmmc4_clk_pcc4";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4-cmd {
+ nvidia,pins = "sdmmc4_cmd_pt7",
+ "sdmmc4_dat0_paa0",
+ "sdmmc4_dat1_paa1",
+ "sdmmc4_dat2_paa2",
+ "sdmmc4_dat3_paa3",
+ "sdmmc4_dat4_paa4",
+ "sdmmc4_dat5_paa5",
+ "sdmmc4_dat6_paa6",
+ "sdmmc4_dat7_paa7";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4-rst-n {
+ nvidia,pins = "sdmmc4_rst_n_pcc3";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ cam-mclk {
+ nvidia,pins = "cam_mclk_pcc0";
+ nvidia,function = "vi_alt3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ drive-sdmmc4 {
+ nvidia,pins = "drive_gma",
+ "drive_gmb",
+ "drive_gmc",
+ "drive_gmd";
+ nvidia,pull-down-strength = <9>;
+ nvidia,pull-up-strength = <9>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+ };
+
+ /* I2C pinmux */
+ gen1-i2c {
+ nvidia,pins = "gen1_i2c_scl_pc4",
+ "gen1_i2c_sda_pc5";
+ nvidia,function = "i2c1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ };
+ gen2-i2c {
+ nvidia,pins = "gen2_i2c_scl_pt5",
+ "gen2_i2c_sda_pt6";
+ nvidia,function = "i2c2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ };
+ cam-i2c {
+ nvidia,pins = "cam_i2c_scl_pbb1",
+ "cam_i2c_sda_pbb2";
+ nvidia,function = "i2c3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ };
+ ddc-i2c {
+ nvidia,pins = "ddc_scl_pv4",
+ "ddc_sda_pv5";
+ nvidia,function = "i2c4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ };
+ pwr-i2c {
+ nvidia,pins = "pwr_i2c_scl_pz6",
+ "pwr_i2c_sda_pz7";
+ nvidia,function = "i2cpwr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ };
+
+ /* HDMI pinmux */
+ hdmi-cec {
+ nvidia,pins = "hdmi_cec_pee3";
+ nvidia,function = "cec";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+ };
+ hdmi-int {
+ nvidia,pins = "hdmi_int_pn7";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* UART-B */
+ uartb-txd-rts {
+ nvidia,pins = "uart2_txd_pc2",
+ "uart2_rts_n_pj6";
+ nvidia,function = "uartb";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ uartb-rxd-cts {
+ nvidia,pins = "uart2_rxd_pc3",
+ "uart2_cts_n_pj5";
+ nvidia,function = "uartb";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* UART-C */
+ uartc-rxd-cts {
+ nvidia,pins = "uart3_cts_n_pa1",
+ "uart3_rxd_pw7";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uartc-txd-rts {
+ nvidia,pins = "uart3_rts_n_pc0",
+ "uart3_txd_pw6";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* UART-D */
+ uartd-rxd {
+ nvidia,pins = "gmi_a17_pb0";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uartd-txd {
+ nvidia,pins = "gmi_a16_pj7";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* I2S pinmux */
+ dap-i2s0 {
+ nvidia,pins = "dap1_fs_pn0",
+ "dap1_din_pn1",
+ "dap1_dout_pn2",
+ "dap1_sclk_pn3";
+ nvidia,function = "i2s0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap-i2s1 {
+ nvidia,pins = "dap2_fs_pa2",
+ "dap2_sclk_pa3",
+ "dap2_din_pa4",
+ "dap2_dout_pa5";
+ nvidia,function = "i2s1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap-i2s2 {
+ nvidia,pins = "dap3_fs_pp0",
+ "dap3_din_pp1",
+ "dap3_dout_pp2";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap3-sclk {
+ nvidia,pins = "dap3_sclk_pp3";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap-i2s3 {
+ nvidia,pins = "dap4_fs_pp4",
+ "dap4_din_pp5",
+ "dap4_dout_pp6",
+ "dap4_sclk_pp7";
+ nvidia,function = "i2s3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PCI-e pinmux */
+ pex-l2-rst-n {
+ nvidia,pins = "pex_l2_rst_n_pcc6",
+ "pex_l2_clkreq_n_pcc7";
+ nvidia,function = "pcie";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pex-l0-prsnt-n {
+ nvidia,pins = "pex_l0_prsnt_n_pdd0",
+ "pex_l0_rst_n_pdd1",
+ "pex_l0_clkreq_n_pdd2",
+ "pex_l1_prsnt_n_pdd4",
+ "pex_l1_rst_n_pdd5",
+ "pex_l1_clkreq_n_pdd6";
+ nvidia,function = "pcie";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pex-wake-n {
+ nvidia,pins = "pex_wake_n_pdd3",
+ "pex_l2_prsnt_n_pdd7";
+ nvidia,function = "pcie";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* SPI pinmux */
+ spi1-mosi {
+ nvidia,pins = "spi1_mosi_px4",
+ "spi1_sck_px5",
+ "spi1_cs0_n_px6",
+ "spi1_miso_px7";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ spi2-mosi {
+ nvidia,pins = "spi2_mosi_px0",
+ "spi2_miso_px1",
+ "spi2_cs1_n_pw2",
+ "spi2_cs2_n_pw3",
+ "ulpi_data7_po0",
+ "ulpi_data4_po5",
+ "ulpi_data5_po6",
+ "ulpi_data6_po7";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ spi2-sck {
+ nvidia,pins = "spi2_sck_px2";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Display A pinmux */
+ lcd-pwr0 {
+ nvidia,pins = "lcd_pwr0_pb2",
+ "lcd_pwr1_pc1",
+ "lcd_pwr2_pc6",
+ "lcd_m1_pw1",
+ "lcd_dc0_pn6";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ lcd-pclk {
+ nvidia,pins = "lcd_pclk_pb3",
+ "lcd_dc1_pd2",
+ "lcd_d0_pe0",
+ "lcd_d1_pe1",
+ "lcd_d2_pe2",
+ "lcd_d3_pe3",
+ "lcd_d4_pe4",
+ "lcd_d5_pe5",
+ "lcd_d6_pe6",
+ "lcd_d7_pe7",
+ "lcd_d8_pf0",
+ "lcd_d9_pf1",
+ "lcd_d10_pf2",
+ "lcd_d11_pf3",
+ "lcd_d12_pf4",
+ "lcd_d13_pf5",
+ "lcd_d14_pf6",
+ "lcd_d15_pf7",
+ "lcd_de_pj1",
+ "lcd_hsync_pj3",
+ "lcd_vsync_pj4",
+ "lcd_d16_pm0",
+ "lcd_d17_pm1",
+ "lcd_d18_pm2",
+ "lcd_d19_pm3",
+ "lcd_d20_pm4",
+ "lcd_d21_pm5",
+ "lcd_d22_pm6",
+ "lcd_d23_pm7",
+ "lcd_cs0_n_pn4",
+ "lcd_sdout_pn5",
+ "lcd_cs1_n_pw0",
+ "lcd_sdin_pz2",
+ "lcd_sck_pz4";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ lcd-wr-n {
+ nvidia,pins = "lcd_wr_n_pz3";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ clk-32k-out {
+ nvidia,pins = "clk_32k_out_pa0";
+ nvidia,function = "blink";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ sys-clk-req {
+ nvidia,pins = "sys_clk_req_pz5";
+ nvidia,function = "sysclk";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ owr {
+ nvidia,pins = "owr";
+ nvidia,function = "owr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* KBC pinmux */
+ kb-col0 {
+ nvidia,pins = "kb_col0_pq0",
+ "kb_col1_pq1",
+ "kb_col2_pq2",
+ "kb_col3_pq3",
+ "kb_row0_pr0",
+ "kb_row1_pr1",
+ "kb_row2_pr2";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb-col4 {
+ nvidia,pins = "kb_col4_pq4",
+ "kb_col5_pq5",
+ "kb_col6_pq6",
+ "kb_col7_pq7",
+ "kb_row12_ps4",
+ "kb_row13_ps5",
+ "kb_row14_ps6";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb-row3 {
+ nvidia,pins = "kb_row3_pr3",
+ "kb_row4_pr4",
+ "kb_row5_pr5",
+ "kb_row6_pr6",
+ "kb_row7_pr7",
+ "kb_row8_ps0",
+ "kb_row9_ps1",
+ "kb_row10_ps2",
+ "kb_row15_ps7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb-row11 {
+ nvidia,pins = "kb_row11_ps3";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* VI pinmux */
+ vi-d0 {
+ nvidia,pins = "vi_d0_pt4",
+ "vi_d1_pd5",
+ "vi_d10_pt2",
+ "vi_d11_pt3";
+ nvidia,function = "vi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ vi-d2 {
+ nvidia,pins = "vi_d2_pl0",
+ "vi_d3_pl1",
+ "vi_d4_pl2",
+ "vi_d5_pl3",
+ "vi_d6_pl4",
+ "vi_d7_pl5",
+ "vi_d8_pl6",
+ "vi_d9_pl7",
+ "vi_vsync_pd6",
+ "vi_hsync_pd7",
+ "vi_pclk_pt0",
+ "vi_mclk_pt1";
+ nvidia,function = "vi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ spdif-out {
+ nvidia,pins = "spdif_out_pk5";
+ nvidia,function = "spdif";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ spdif-in {
+ nvidia,pins = "spdif_in_pk6";
+ nvidia,function = "spdif";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* ULPI pinmux */
+ ulpi-clk {
+ nvidia,pins = "ulpi_clk_py0",
+ "ulpi_data0_po1",
+ "ulpi_data1_po2",
+ "ulpi_data2_po3",
+ "ulpi_data3_po4";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi-dir {
+ nvidia,pins = "ulpi_dir_py1",
+ "ulpi_nxt_py2",
+ "ulpi_stp_py3";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* PORT U */
+ pu0 {
+ nvidia,pins = "pu0";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pu1 {
+ nvidia,pins = "pu1";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pu2 {
+ nvidia,pins = "pu2";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pu3 {
+ nvidia,pins = "pu3";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pu4 {
+ nvidia,pins = "pu4";
+ nvidia,function = "pwm1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pu5 {
+ nvidia,pins = "pu5";
+ nvidia,function = "pwm2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pu6 {
+ nvidia,pins = "pu6";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ jtag-rtck-pu7 {
+ nvidia,pins = "jtag_rtck_pu7";
+ nvidia,function = "rtck";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PORT V */
+ pv0 {
+ nvidia,pins = "pv0";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pv1 {
+ nvidia,pins = "pv1";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pv2 {
+ nvidia,pins = "pv2";
+ nvidia,function = "owr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pv3 {
+ nvidia,pins = "pv3";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* PORT BB */
+ pbb0 {
+ nvidia,pins = "pbb0";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pbb3 {
+ nvidia,pins = "pbb3";
+ nvidia,function = "vgp3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pbb4 {
+ nvidia,pins = "pbb4";
+ nvidia,function = "vgp4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pbb5 {
+ nvidia,pins = "pbb5";
+ nvidia,function = "vgp5";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pbb6 {
+ nvidia,pins = "pbb6";
+ nvidia,function = "vgp6";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pbb7 {
+ nvidia,pins = "pbb7";
+ nvidia,function = "i2s4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PORT CC */
+ pcc1 {
+ nvidia,pins = "pcc1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pcc2 {
+ nvidia,pins = "pcc2";
+ nvidia,function = "i2s4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ crt-hsync-vsync {
+ nvidia,pins = "crt_hsync_pv6",
+ "crt_vsync_pv7";
+ nvidia,function = "crt";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ clk1-out {
+ nvidia,pins = "clk1_out_pw4";
+ nvidia,function = "extperiph1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ clk1-req {
+ nvidia,pins = "clk1_req_pee2";
+ nvidia,function = "dap";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ clk2-out {
+ nvidia,pins = "clk2_out_pw5";
+ nvidia,function = "extperiph2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ clk2-req {
+ nvidia,pins = "clk2_req_pcc5";
+ nvidia,function = "dap";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ clk3-out {
+ nvidia,pins = "clk3_out_pee0";
+ nvidia,function = "extperiph3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ clk3-req {
+ nvidia,pins = "clk3_req_pee1";
+ nvidia,function = "dev3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* GMI pinmux */
+ gmi-a18 {
+ nvidia,pins = "gmi_a18_pb1";
+ nvidia,function = "spi4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi-wp-n {
+ nvidia,pins = "gmi_wp_n_pc7",
+ "gmi_wait_pi7";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi-ad0 {
+ nvidia,pins = "gmi_ad0_pg0",
+ "gmi_ad1_pg1",
+ "gmi_cs3_n_pk4";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi-ad2 {
+ nvidia,pins = "gmi_ad2_pg2",
+ "gmi_ad3_pg3",
+ "gmi_ad6_pg6",
+ "gmi_ad7_pg7";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi-ad4 {
+ nvidia,pins = "gmi_ad4_pg4",
+ "gmi_ad5_pg5",
+ "gmi_ad12_ph4",
+ "gmi_ad13_ph5",
+ "gmi_ad14_ph6",
+ "gmi_ad15_ph7",
+ "gmi_dqs_pi2",
+ "gmi_cs0_n_pj0",
+ "gmi_cs4_n_pk2";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi-ad8 {
+ nvidia,pins = "gmi_ad8_ph0";
+ nvidia,function = "pwm0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi-ad9 {
+ nvidia,pins = "gmi_ad9_ph1";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi-ad10 {
+ nvidia,pins = "gmi_ad10_ph2";
+ nvidia,function = "pwm2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi-ad11 {
+ nvidia,pins = "gmi_ad11_ph3";
+ nvidia,function = "pwm3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi-wr-n {
+ nvidia,pins = "gmi_wr_n_pi0",
+ "gmi_oe_n_pi1",
+ "gmi_cs1_n_pj2",
+ "gmi_adv_n_pk0";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi-cs6-n {
+ nvidia,pins = "gmi_cs6_n_pi3",
+ "gmi_cs7_n_pi6",
+ "gmi_clk_pk1";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi-rst-n {
+ nvidia,pins = "gmi_rst_n_pi4";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi-cs2-n {
+ nvidia,pins = "gmi_cs2_n_pk3";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi-a19 {
+ nvidia,pins = "gmi_a19_pk7";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* GPIO power/drive control */
+ drive-dap2 {
+ nvidia,pins = "drive_dap2",
+ "drive_dbg",
+ "drive_at5",
+ "drive_gme",
+ "drive_ddc",
+ "drive_ao1",
+ "drive_uart3";
+ nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+ nvidia,schmitt = <TEGRA_PIN_ENABLE>;
+ nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+ nvidia,pull-down-strength = <31>;
+ nvidia,pull-up-strength = <31>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ };
+
+ drive-sdio1 {
+ nvidia,pins = "drive_sdio1",
+ "drive_sdio3";
+ nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+ nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+ nvidia,pull-down-strength = <46>;
+ nvidia,pull-up-strength = <42>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
+ };
+ };
+ };
+
+ uartd: serial@70006300 {
+ status = "okay";
+ };
+
+ pwm: pwm@7000a000 {
+ status = "okay";
+ };
+
+ pwr_i2c: i2c@7000d000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ pmic: max77663@3c {
+ compatible = "maxim,max77663";
+ reg = <0x3c>;
+
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ system-power-controller;
+
+ regulators {
+ vdd_1v8_vio: sd2 {
+ regulator-name = "vdd_1v8_gen";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcore_emmc: ldo3 {
+ regulator-name = "vcore_emmc";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <3100000>;
+ regulator-boot-on;
+ };
+
+ vddio_usd: ldo6 {
+ regulator-name = "vddio_usd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+ };
+
+ sdmmc1: sdhci@78000000 {
+ status = "okay";
+ bus-width = <4>;
+
+ cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+ power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
+
+ vmmc-supply = <&vdd_usd>;
+ vqmmc-supply = <&vddio_usd>;
+ };
+
+ sdmmc4: sdhci@78000600 {
+ status = "okay";
+ bus-width = <8>;
+ non-removable;
+
+ vmmc-supply = <&vcore_emmc>;
+ vqmmc-supply = <&vdd_1v8_vio>;
+ };
+
+ micro_usb: usb@7d000000 {
+ status = "okay";
+ dr_mode = "otg";
+ };
+
+ /* Full size USB */
+ usb3: usb@7d008000 {
+ status = "okay";
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+
+ enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+ power-supply = <&vdd_5v0_bl>;
+ pwms = <&pwm 0 5000000>;
+
+ brightness-levels = <1 35 70 105 140 175 210 255>;
+ default-brightness-level = <5>;
+ };
+
+ clk32k_in: clock-32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "ref-oscillator";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ key-power {
+ label = "Power";
+ gpios = <&pmic EN0 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_ENTER>;
+ };
+
+ key-volume-down {
+ label = "Volume Down";
+ gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_DOWN>;
+ };
+
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_UP>;
+ };
+ };
+
+ panel: panel {
+ compatible = "simple-panel";
+
+ power-supply = <&vdd_pnl_reg>;
+ enable-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_HIGH>;
+
+ backlight = <&backlight>;
+
+ display-timings {
+ timing@0 {
+ /* 1280x800@60Hz */
+ clock-frequency = <81750000>;
+
+ hactive = <800>;
+ hfront-porch = <64>;
+ hback-porch = <128>;
+ hsync-len = <64>;
+
+ vactive = <1280>;
+ vfront-porch = <5>;
+ vback-porch = <2>;
+ vsync-len = <1>;
+ };
+ };
+ };
+
+ vdd_5v0_bl: regulator-bl {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v0_bl";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vdd_usd: regulator-emmc {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_3v3_sdmmc1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vdd_pnl_reg: regulator-pnl {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_panel";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
diff --git a/arch/arm/dts/ulcb-audio-graph-card.dtsi b/arch/arm/dts/ulcb-audio-graph-card.dtsi
deleted file mode 100644
index 3be54df..0000000
--- a/arch/arm/dts/ulcb-audio-graph-card.dtsi
+++ /dev/null
@@ -1,85 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree for ULCB + Audio Graph Card
- *
- * Copyright (C) 2022 Renesas Electronics Corp.
- */
-
-/*
- * (A) CPU0 <-----> ak4613
- * (B) CPU1 -----> HDMI
- *
- * (A) aplay -D plughw:0,0 xxx.wav
- * (B) aplay -D plughw:0,1 xxx.wav
- *
- * (A) arecord -D plughw:0,0 xxx.wav
- */
-
-/ {
- sound_card: sound {
- compatible = "audio-graph-card";
- label = "rcar-sound";
-
- dais = <&rsnd_port0 /* (A) CPU0 <-> ak4613 */
- &rsnd_port1 /* (B) CPU1 -> HDMI */
- >;
- };
-};
-
-&ak4613 {
- #sound-dai-cells = <0>;
-
- port {
- /*
- * (A) CPU0 <-> ak4613
- */
- ak4613_endpoint: endpoint {
- remote-endpoint = <&rsnd_for_ak4613>;
- };
- };
-};
-
-&hdmi0 {
- ports {
- port@2 {
- /*
- * (B) CPU1 -> HDMI
- */
- dw_hdmi0_snd_in: endpoint {
- remote-endpoint = <&rsnd_for_hdmi>;
- };
- };
- };
-};
-
-&rcar_sound {
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- rsnd_port0: port@0 {
- /*
- * (A) CPU0 <-> ak4613
- */
- reg = <0>;
- rsnd_for_ak4613: endpoint {
- remote-endpoint = <&ak4613_endpoint>;
- bitclock-master;
- frame-master;
- playback = <&ssi0>, <&src0>, <&dvc0>;
- capture = <&ssi1>, <&src1>, <&dvc1>;
- };
- };
- rsnd_port1: port@1 {
- /*
- * (B) CPU1 -> HDMI
- */
- reg = <1>;
- rsnd_for_hdmi: endpoint {
- remote-endpoint = <&dw_hdmi0_snd_in>;
- bitclock-master;
- frame-master;
- playback = <&ssi2>;
- };
- };
- };
-};
diff --git a/arch/arm/dts/ulcb-audio-graph-card2.dtsi b/arch/arm/dts/ulcb-audio-graph-card2.dtsi
deleted file mode 100644
index 5ebec12..0000000
--- a/arch/arm/dts/ulcb-audio-graph-card2.dtsi
+++ /dev/null
@@ -1,26 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree for ULCB + Audio Graph Card2
- *
- * Copyright (C) 2022 Renesas Electronics Corp.
- */
-
-/*
- * (A) CPU0 <----> ak4613
- * (B) CPU1 ----> HDMI
- *
- * (A) aplay -D plughw:0,0 xxx.wav
- * (B) aplay -D plughw:0,1 xxx.wav
- *
- * (A) arecord -D plughw:0,0 xxx.wav
- */
-#include "ulcb-audio-graph-card.dtsi"
-
-&sound_card {
- compatible = "audio-graph-card2";
-
- /delete-property/ dais;
- links = <&rsnd_port0 /* (A) CPU0 <-> ak4613 */
- &rsnd_port1 /* (B) CPU1 -> HDMI */
- >;
-};
diff --git a/arch/arm/dts/ulcb.dtsi b/arch/arm/dts/ulcb.dtsi
deleted file mode 100644
index 0be2716..0000000
--- a/arch/arm/dts/ulcb.dtsi
+++ /dev/null
@@ -1,509 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the R-Car Gen3 ULCB board
- *
- * Copyright (C) 2016 Renesas Electronics Corp.
- * Copyright (C) 2016 Cogent Embedded, Inc.
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
- model = "Renesas R-Car Gen3 ULCB board";
-
- aliases {
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- i2c4 = &i2c4;
- i2c5 = &i2c5;
- i2c6 = &i2c6;
- i2c7 = &i2c_dvfs;
- serial0 = &scif2;
- ethernet0 = &avb;
- mmc0 = &sdhi2;
- mmc1 = &sdhi0;
- };
-
- chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
- stdout-path = "serial0:115200n8";
- };
-
- audio_clkout: audio-clkout {
- /*
- * This is same as <&rcar_sound 0>
- * but needed to avoid cs2000/rcar_sound probe dead-lock
- */
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <12288000>;
- };
-
- hdmi0-out {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi0_con: endpoint {
- remote-endpoint = <&rcar_dw_hdmi0_out>;
- };
- };
- };
-
- keyboard {
- compatible = "gpio-keys";
-
- key-1 {
- linux,code = <KEY_1>;
- label = "SW3";
- wakeup-source;
- debounce-interval = <20>;
- gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led5 {
- gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
- };
- led6 {
- gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
- };
- };
-
- reg_1p8v: regulator-1p8v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- reg_3p3v: regulator-3p3v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- vcc_sdhi0: regulator-vcc-sdhi0 {
- compatible = "regulator-fixed";
-
- regulator-name = "SDHI0 Vcc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vccq_sdhi0: regulator-vccq-sdhi0 {
- compatible = "regulator-gpio";
-
- regulator-name = "SDHI0 VccQ";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
- gpios-states = <1>;
- states = <3300000 1>, <1800000 0>;
- };
-
- x12_clk: x12 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24576000>;
- };
-
- x23_clk: x23-clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <25000000>;
- };
-};
-
-&a57_0 {
- cpu-supply = <&dvfs>;
-};
-
-&audio_clk_a {
- clock-frequency = <22579200>;
-};
-
-&avb {
- pinctrl-0 = <&avb_pins>;
- pinctrl-names = "default";
- phy-handle = <&phy0>;
- tx-internal-delay-ps = <2000>;
- status = "okay";
-
- phy0: ethernet-phy@0 {
- compatible = "ethernet-phy-id0022.1622",
- "ethernet-phy-ieee802.3-c22";
- rxc-skew-ps = <1500>;
- reg = <0>;
- interrupt-parent = <&gpio2>;
- interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
- reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
- };
-};
-
-&du {
- status = "okay";
-};
-
-&ehci1 {
- status = "okay";
-};
-
-&extal_clk {
- clock-frequency = <16666666>;
-};
-
-&extalr_clk {
- clock-frequency = <32768>;
-};
-
-&hdmi0 {
- status = "okay";
-
- ports {
- port@1 {
- reg = <1>;
- rcar_dw_hdmi0_out: endpoint {
- remote-endpoint = <&hdmi0_con>;
- };
- };
- port@2 {
- reg = <2>;
- };
- };
-};
-
-&i2c2 {
- pinctrl-0 = <&i2c2_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-
- clock-frequency = <100000>;
-
- ak4613: codec@10 {
- compatible = "asahi-kasei,ak4613";
- reg = <0x10>;
- clocks = <&rcar_sound 3>;
-
- asahi-kasei,in1-single-end;
- asahi-kasei,in2-single-end;
- asahi-kasei,out1-single-end;
- asahi-kasei,out2-single-end;
- asahi-kasei,out3-single-end;
- asahi-kasei,out4-single-end;
- asahi-kasei,out5-single-end;
- asahi-kasei,out6-single-end;
- };
-
- cs2000: clk-multiplier@4f {
- #clock-cells = <0>;
- compatible = "cirrus,cs2000-cp";
- reg = <0x4f>;
- clocks = <&audio_clkout>, <&x12_clk>;
- clock-names = "clk_in", "ref_clk";
-
- assigned-clocks = <&cs2000>;
- assigned-clock-rates = <24576000>; /* 1/1 divide */
- };
-};
-
-&i2c4 {
- status = "okay";
-
- clock-frequency = <400000>;
-
- versaclock5: clock-generator@6a {
- compatible = "idt,5p49v5925";
- reg = <0x6a>;
- #clock-cells = <1>;
- clocks = <&x23_clk>;
- clock-names = "xin";
- };
-};
-
-&i2c_dvfs {
- status = "okay";
-
- clock-frequency = <400000>;
-
- pmic: pmic@30 {
- pinctrl-0 = <&irq0_pins>;
- pinctrl-names = "default";
-
- compatible = "rohm,bd9571mwv";
- reg = <0x30>;
- interrupt-parent = <&intc_ex>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-controller;
- #gpio-cells = <2>;
- rohm,ddr-backup-power = <0xf>;
- rohm,rstbmode-pulse;
-
- regulators {
- dvfs: dvfs {
- regulator-name = "dvfs";
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1030000>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
-
- eeprom@50 {
- compatible = "rohm,br24t01", "atmel,24c01";
- reg = <0x50>;
- pagesize = <8>;
- };
-};
-
-&ohci1 {
- status = "okay";
-};
-
-&pfc {
- pinctrl-0 = <&scif_clk_pins>;
- pinctrl-names = "default";
-
- avb_pins: avb {
- mux {
- groups = "avb_link", "avb_mdio", "avb_mii";
- function = "avb";
- };
-
- pins_mdio {
- groups = "avb_mdio";
- drive-strength = <24>;
- };
-
- pins_mii_tx {
- pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
- "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
- drive-strength = <12>;
- };
- };
-
- i2c2_pins: i2c2 {
- groups = "i2c2_a";
- function = "i2c2";
- };
-
- irq0_pins: irq0 {
- groups = "intc_ex_irq0";
- function = "intc_ex";
- };
-
- scif2_pins: scif2 {
- groups = "scif2_data_a";
- function = "scif2";
- };
-
- scif_clk_pins: scif_clk {
- groups = "scif_clk_a";
- function = "scif_clk";
- };
-
- sdhi0_pins: sd0 {
- groups = "sdhi0_data4", "sdhi0_ctrl";
- function = "sdhi0";
- power-source = <3300>;
- };
-
- sdhi0_pins_uhs: sd0_uhs {
- groups = "sdhi0_data4", "sdhi0_ctrl";
- function = "sdhi0";
- power-source = <1800>;
- };
-
- sdhi2_pins: sd2 {
- groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
- function = "sdhi2";
- power-source = <1800>;
- };
-
- sound_pins: sound {
- groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
- function = "ssi";
- };
-
- sound_clk_pins: sound-clk {
- groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a",
- "audio_clkout_a", "audio_clkout3_a";
- function = "audio_clk";
- };
-
- usb1_pins: usb1 {
- groups = "usb1";
- function = "usb1";
- };
-};
-
-&rcar_sound {
- pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
- pinctrl-names = "default";
-
- /* audio_clkout0/1/2/3 */
- #clock-cells = <1>;
- clock-frequency = <12288000 11289600>;
-
- status = "okay";
-
- /* update <audio_clk_b> to <cs2000> */
- clocks = <&cpg CPG_MOD 1005>,
- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
- <&audio_clk_a>, <&cs2000>,
- <&audio_clk_c>,
- <&cpg CPG_CORE CPG_AUDIO_CLK_I>;
-};
-
-&rpc {
- /* Left disabled. To be enabled by firmware when unlocked. */
-
- flash@0 {
- compatible = "cypress,hyperflash", "cfi-flash";
- reg = <0>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- bootparam@0 {
- reg = <0x00000000 0x040000>;
- read-only;
- };
- bl2@40000 {
- reg = <0x00040000 0x140000>;
- read-only;
- };
- cert_header_sa6@180000 {
- reg = <0x00180000 0x040000>;
- read-only;
- };
- bl31@1c0000 {
- reg = <0x001c0000 0x040000>;
- read-only;
- };
- tee@200000 {
- reg = <0x00200000 0x440000>;
- read-only;
- };
- uboot@640000 {
- reg = <0x00640000 0x100000>;
- read-only;
- };
- dtb@740000 {
- reg = <0x00740000 0x080000>;
- };
- kernel@7c0000 {
- reg = <0x007c0000 0x1400000>;
- };
- user@1bc0000 {
- reg = <0x01bc0000 0x2440000>;
- };
- };
- };
-};
-
-&rwdt {
- timeout-sec = <60>;
- status = "okay";
-};
-
-&scif2 {
- pinctrl-0 = <&scif2_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&scif_clk {
- clock-frequency = <14745600>;
-};
-
-&sdhi0 {
- pinctrl-0 = <&sdhi0_pins>;
- pinctrl-1 = <&sdhi0_pins_uhs>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <&vcc_sdhi0>;
- vqmmc-supply = <&vccq_sdhi0>;
- cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
- bus-width = <4>;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
- status = "okay";
-};
-
-&sdhi2 {
- /* used for on-board 8bit eMMC */
- pinctrl-0 = <&sdhi2_pins>;
- pinctrl-1 = <&sdhi2_pins>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <®_3p3v>;
- vqmmc-supply = <®_1p8v>;
- bus-width = <8>;
- mmc-hs200-1_8v;
- mmc-hs400-1_8v;
- no-sd;
- no-sdio;
- non-removable;
- full-pwr-cycle-in-suspend;
- status = "okay";
-};
-
-&ssi1 {
- shared-pin;
-};
-
-&usb2_phy1 {
- pinctrl-0 = <&usb1_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-
-/*
- * For sound-test.
- *
- * We can switch Audio Card for testing
- *
- * #include "ulcb-simple-audio-card.dtsi"
- * #include "ulcb-simple-audio-card-mix+split.dtsi"
- * #include "ulcb-audio-graph-card.dtsi"
- * #include "ulcb-audio-graph-card-mix+split.dtsi"
- * #include "ulcb-audio-graph-card2-mix+split.dtsi"
- */
-#include "ulcb-audio-graph-card2.dtsi"
diff --git a/arch/arm/dts/zynqmp-mini-nand.dts b/arch/arm/dts/zynqmp-mini-nand.dts
index 5889d43..e08a784 100644
--- a/arch/arm/dts/zynqmp-mini-nand.dts
+++ b/arch/arm/dts/zynqmp-mini-nand.dts
@@ -46,8 +46,8 @@
status = "okay";
reg = <0x0 0xff100000 0x1000>;
clock-names = "clk_sys", "clk_flash";
- #address-cells = <2>;
- #size-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
arasan,has-mdma;
num-cs = <2>;
nand@0 {
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 53a606c..34f592c 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -314,19 +314,76 @@
ranges;
};
- remoteproc {
+ rproc_lockstep: remoteproc@ffe00000 {
compatible = "xlnx,zynqmp-r5fss";
xlnx,cluster-mode = <1>;
+ xlnx,tcm-mode = <1>;
- r5f-0 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>,
+ <0x0 0x20000 0x0 0xffe20000 0x0 0x10000>,
+ <0x0 0x10000 0x0 0xffe10000 0x0 0x10000>,
+ <0x0 0x30000 0x0 0xffe30000 0x0 0x10000>;
+
+ r5f@0 {
+ compatible = "xlnx,zynqmp-r5f";
+ reg = <0x0 0x0 0x0 0x10000>,
+ <0x0 0x20000 0x0 0x10000>,
+ <0x0 0x10000 0x0 0x10000>,
+ <0x0 0x30000 0x0 0x10000>;
+ reg-names = "atcm0", "btcm0", "atcm1", "btcm1";
+ power-domains = <&zynqmp_firmware PD_RPU_0>,
+ <&zynqmp_firmware PD_R5_0_ATCM>,
+ <&zynqmp_firmware PD_R5_0_BTCM>,
+ <&zynqmp_firmware PD_R5_1_ATCM>,
+ <&zynqmp_firmware PD_R5_1_BTCM>;
+ memory-region = <&rproc_0_fw_image>;
+ };
+
+ r5f@1 {
+ compatible = "xlnx,zynqmp-r5f";
+ reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>;
+ reg-names = "atcm0", "btcm0";
+ power-domains = <&zynqmp_firmware PD_RPU_1>,
+ <&zynqmp_firmware PD_R5_1_ATCM>,
+ <&zynqmp_firmware PD_R5_1_BTCM>;
+ memory-region = <&rproc_1_fw_image>;
+ };
+ };
+
+ rproc_split: remoteproc-split@ffe00000 {
+ status = "disabled";
+ compatible = "xlnx,zynqmp-r5fss";
+ xlnx,cluster-mode = <0>;
+ xlnx,tcm-mode = <0>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>,
+ <0x0 0x20000 0x0 0xffe20000 0x0 0x10000>,
+ <0x1 0x0 0x0 0xffe90000 0x0 0x10000>,
+ <0x1 0x20000 0x0 0xffeb0000 0x0 0x10000>;
+
+ r5f@0 {
compatible = "xlnx,zynqmp-r5f";
- power-domains = <&zynqmp_firmware PD_RPU_0>;
+ reg = <0x0 0x0 0x0 0x10000>, <0x0 0x20000 0x0 0x10000>;
+ reg-names = "atcm0", "btcm0";
+ power-domains = <&zynqmp_firmware PD_RPU_0>,
+ <&zynqmp_firmware PD_R5_0_ATCM>,
+ <&zynqmp_firmware PD_R5_0_BTCM>;
memory-region = <&rproc_0_fw_image>;
};
- r5f-1 {
+ r5f@1 {
compatible = "xlnx,zynqmp-r5f";
- power-domains = <&zynqmp_firmware PD_RPU_1>;
+ reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>;
+ reg-names = "atcm0", "btcm0";
+ power-domains = <&zynqmp_firmware PD_RPU_1>,
+ <&zynqmp_firmware PD_R5_1_ATCM>,
+ <&zynqmp_firmware PD_R5_1_BTCM>;
memory-region = <&rproc_1_fw_image>;
};
};
diff --git a/arch/arm/include/asm/arch-meson/usb-gx.h b/arch/arm/include/asm/arch-meson/usb-gx.h
deleted file mode 100644
index 61f1809..0000000
--- a/arch/arm/include/asm/arch-meson/usb-gx.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2019 BayLibre SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-#ifndef _ARCH_MESON_USB_GX_H_
-#define _ARCH_MESON_USB_GX_H_
-
-#include <generic-phy.h>
-#include <linux/usb/otg.h>
-
-/* TOFIX add set_mode to struct phy_ops */
-void phy_meson_gxl_usb2_set_mode(struct phy *phy, enum usb_dr_mode mode);
-
-int dwc3_meson_gxl_force_mode(struct udevice *dev, enum usb_dr_mode mode);
-
-#endif
diff --git a/arch/arm/include/asm/arch-meson/usb.h b/arch/arm/include/asm/arch-meson/usb.h
deleted file mode 100644
index b794b5c..0000000
--- a/arch/arm/include/asm/arch-meson/usb.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2019 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#ifndef __MESON_USB_H__
-#define __MESON_USB_H__
-
-int dwc3_meson_g12a_force_mode(struct udevice *dev, enum usb_dr_mode mode);
-
-#endif /* __MESON_USB_H__ */
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
index a4507e5..a0e54d3 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
@@ -29,6 +29,7 @@
V0PLL,
AUPLL,
PPLL,
+ SPLL,
PLL_COUNT,
};
@@ -150,6 +151,9 @@
#define RK3588_DSU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x800)
#define RK3588_DSU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0xa00)
+#define RK3588_SBUSCRU_SPLL_CON(x) ((x) * 0x4 + 0x220)
+#define RK3588_SBUSCRU_MODE_CON0 0x280
+
enum {
/* CRU_CLK_SEL8_CON */
ACLK_LOW_TOP_ROOT_SRC_SEL_SHIFT = 14,
diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index ce655ce..0ab681c 100644
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -51,7 +51,7 @@
#define PTE_TABLE_PXN (1UL << 59)
#define PTE_TABLE_XN (1UL << 60)
-#define PTE_TABLE_AP (1UL << 61)
+#define PTE_TABLE_AP (3UL << 61)
#define PTE_TABLE_NS (1UL << 63)
/*
@@ -129,6 +129,62 @@
asm volatile("isb");
}
+static inline void get_ttbr_tcr_mair(int el, u64 *table, u64 *tcr, u64 *attr)
+{
+ if (el == 1) {
+ asm volatile("mrs %0, ttbr0_el1" : "=r" (*table));
+ asm volatile("mrs %0, tcr_el1" : "=r" (*tcr));
+ asm volatile("mrs %0, mair_el1" : "=r" (*attr));
+ } else if (el == 2) {
+ asm volatile("mrs %0, ttbr0_el2" : "=r" (*table));
+ asm volatile("mrs %0, tcr_el2" : "=r" (*tcr));
+ asm volatile("mrs %0, mair_el2" : "=r" (*attr));
+ } else if (el == 3) {
+ asm volatile("mrs %0, ttbr0_el3" : "=r" (*table));
+ asm volatile("mrs %0, tcr_el3" : "=r" (*tcr));
+ asm volatile("mrs %0, mair_el3" : "=r" (*attr));
+ } else {
+ hang();
+ }
+}
+
+/**
+ * typedef pte_walker_cb_t - callback function for walk_pagetable.
+ *
+ * This function is called when the walker finds a table entry
+ * or after parsing a block or pages. For a table the @end address
+ * is 0, and @addr is the address of the table. Otherwise, they
+ * are the start and end physical addresses of the block or page.
+ *
+ * @addr: PTE start address (PA), or address of table. Includes attributes.
+ * @end: End address of the region (or 0 for a table)
+ * @va_bits: Number of bits in the virtual address
+ * @level: Table level
+ * @priv: Private data for the callback
+ *
+ * Return: true to stop walking, false to continue
+ */
+typedef bool (*pte_walker_cb_t)(u64 addr, u64 end, int va_bits, int level, void *priv);
+
+/**
+ * walk_pagetable() - Walk the pagetable at ttbr and call @cb for each region
+ *
+ * @ttbr: Address of the pagetable to dump
+ * @tcr: TCR value to use
+ * @cb: Callback function to call for each entry
+ * @priv: Private data for the callback
+ */
+void walk_pagetable(u64 ttbr, u64 tcr, pte_walker_cb_t cb, void *priv);
+
+/**
+ * dump_pagetable() - Dump the pagetable at ttbr, printing each region and
+ * level.
+ *
+ * @ttbr: Address of the pagetable to dump
+ * @tcr: TCR value to use
+ */
+void dump_pagetable(u64 ttbr, u64 tcr);
+
struct mm_region {
u64 virt;
u64 phys;
diff --git a/arch/arm/lib/sections.c b/arch/arm/lib/sections.c
index db5463b..07efaba 100644
--- a/arch/arm/lib/sections.c
+++ b/arch/arm/lib/sections.c
@@ -23,4 +23,3 @@
char __secure_end[0] __section(".__secure_end");
char __secure_stack_start[0] __section(".__secure_stack_start");
char __secure_stack_end[0] __section(".__secure_stack_end");
-char _end[0] __section(".__end");
diff --git a/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds b/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds
index ada6570..9502a73 100644
--- a/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds
+++ b/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds
@@ -61,11 +61,7 @@
__rel_dyn_end = .;
} > .nor
- .end :
- {
- *(.__end)
- } > .nor
-
+ _end = .;
_image_binary_end = .;
.bss : {
diff --git a/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
index 1a8bf94..09cf838 100644
--- a/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
+++ b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
@@ -33,12 +33,7 @@
. = ALIGN(4);
__image_copy_end = .;
-
- .end :
- {
- *(.__end)
- } >.sram
-
+ _end = .;
_image_binary_end = .;
.bss :
diff --git a/arch/arm/mach-at91/armv7/u-boot-spl.lds b/arch/arm/mach-at91/armv7/u-boot-spl.lds
index 6ca725f..460a91d 100644
--- a/arch/arm/mach-at91/armv7/u-boot-spl.lds
+++ b/arch/arm/mach-at91/armv7/u-boot-spl.lds
@@ -40,12 +40,7 @@
. = ALIGN(4);
__image_copy_end = .;
-
- .end :
- {
- *(.__end)
- } >.sram
-
+ _end = .;
_image_binary_end = .;
.bss :
diff --git a/arch/arm/mach-bcm283x/reset.c b/arch/arm/mach-bcm283x/reset.c
index 9199234..1dc7ce5 100644
--- a/arch/arm/mach-bcm283x/reset.c
+++ b/arch/arm/mach-bcm283x/reset.c
@@ -25,8 +25,6 @@
/* max ticks timeout */
#define BCM2835_WDOG_MAX_TIMEOUT 0x000fffff
-void hw_watchdog_disable(void) {}
-
__efi_runtime_data struct bcm2835_wdog_regs *wdog_regs;
static void __efi_runtime
@@ -34,10 +32,9 @@
{
uint32_t rstc, timeout;
- if (ticks == 0) {
- hw_watchdog_disable();
+ if (ticks == 0)
timeout = RESET_TIMEOUT;
- } else
+ else
timeout = ticks & BCM2835_WDOG_MAX_TIMEOUT;
rstc = readl(&wdog_regs->rstc);
diff --git a/arch/arm/mach-davinci/include/mach/timer_defs.h b/arch/arm/mach-davinci/include/mach/timer_defs.h
index 110e67e..a25f6d1 100644
--- a/arch/arm/mach-davinci/include/mach/timer_defs.h
+++ b/arch/arm/mach-davinci/include/mach/timer_defs.h
@@ -20,24 +20,4 @@
u_int32_t wdtcr;
};
-#define DV_TIMER_TCR_ENAMODE_MASK 3
-
-#define DV_TIMER_TCR_ENAMODE12_SHIFT 6
-#define DV_TIMER_TCR_CLKSRC12_SHIFT 8
-#define DV_TIMER_TCR_READRSTMODE12_SHIFT 10
-#define DV_TIMER_TCR_CAPMODE12_SHIFT 11
-#define DV_TIMER_TCR_CAPVTMODE12_SHIFT 12
-#define DV_TIMER_TCR_ENAMODE34_SHIFT 22
-#define DV_TIMER_TCR_CLKSRC34_SHIFT 24
-#define DV_TIMER_TCR_READRSTMODE34_SHIFT 26
-#define DV_TIMER_TCR_CAPMODE34_SHIFT 27
-#define DV_TIMER_TCR_CAPEVTMODE12_SHIFT 28
-
-#define DV_WDT_ENABLE_SYS_RESET 0x00020000
-#define DV_WDT_TRIGGER_SYS_RESET 0x00020002
-
-#ifdef CONFIG_HW_WATCHDOG
-void davinci_hw_watchdog_enable(void);
-void davinci_hw_watchdog_reset(void);
-#endif
#endif /* _TIMER_DEFS_H_ */
diff --git a/arch/arm/mach-davinci/timer.c b/arch/arm/mach-davinci/timer.c
index f2990f7..474dc6b 100644
--- a/arch/arm/mach-davinci/timer.c
+++ b/arch/arm/mach-davinci/timer.c
@@ -98,34 +98,3 @@
{
return gd->arch.timer_rate_hz;
}
-
-#ifdef CONFIG_HW_WATCHDOG
-static struct davinci_timer * const wdttimer =
- (struct davinci_timer *)CONFIG_SYS_WDTTIMERBASE;
-
-/*
- * See prufw2.pdf for using Timer as a WDT
- */
-void davinci_hw_watchdog_enable(void)
-{
- writel(0x0, &wdttimer->tcr);
- writel(0x0, &wdttimer->tgcr);
- /* TIMMODE = 2h */
- writel(0x08 | 0x03 | ((TIM_CLK_DIV - 1) << 8), &wdttimer->tgcr);
- writel(CONFIG_SYS_WDT_PERIOD_LOW, &wdttimer->prd12);
- writel(CONFIG_SYS_WDT_PERIOD_HIGH, &wdttimer->prd34);
- writel(2 << 22, &wdttimer->tcr);
- writel(0x0, &wdttimer->tim12);
- writel(0x0, &wdttimer->tim34);
- /* set WDEN bit, WDKEY 0xa5c6 */
- writel(0xa5c64000, &wdttimer->wdtcr);
- /* clear counter register */
- writel(0xda7e4000, &wdttimer->wdtcr);
-}
-
-void davinci_hw_watchdog_reset(void)
-{
- writel(0xa5c64000, &wdttimer->wdtcr);
- writel(0xda7e4000, &wdttimer->wdtcr);
-}
-#endif
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index af00ee1..cad8bb0 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -249,6 +249,7 @@
select OF_CONTROL
select PINCTRL
select PINCTRL_EXYNOS850
+ imply OF_UPSTREAM
endchoice
endif
diff --git a/arch/arm/mach-exynos/mmu-arm64.c b/arch/arm/mach-exynos/mmu-arm64.c
index e2f3254..fdaacc70 100644
--- a/arch/arm/mach-exynos/mmu-arm64.c
+++ b/arch/arm/mach-exynos/mmu-arm64.c
@@ -100,6 +100,14 @@
static struct mm_region exynos850_mem_map[] = {
{
+ /* iRAM */
+ .virt = 0x02000000UL,
+ .phys = 0x02000000UL,
+ .size = SZ_2M,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
/* Peripheral block */
.virt = 0x10000000UL,
.phys = 0x10000000UL,
diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c
index c7962ea..56e1a8f 100644
--- a/arch/arm/mach-imx/cmd_dek.c
+++ b/arch/arm/mach-imx/cmd_dek.c
@@ -395,10 +395,10 @@
}
/***************************************************/
-static char dek_blob_help_text[] =
+U_BOOT_LONGHELP(dek_blob,
"src dst len - Encapsulate and create blob of data\n"
" $len bits long at address $src and\n"
- " store the result at address $dst.\n";
+ " store the result at address $dst.\n");
U_BOOT_CMD(
dek_blob, 4, 1, do_dek_blob,
diff --git a/arch/arm/mach-imx/cmd_mfgprot.c b/arch/arm/mach-imx/cmd_mfgprot.c
index 9925c99..9f37e61 100644
--- a/arch/arm/mach-imx/cmd_mfgprot.c
+++ b/arch/arm/mach-imx/cmd_mfgprot.c
@@ -134,12 +134,12 @@
}
/***************************************************/
-static char mfgprot_help_text[] =
+U_BOOT_LONGHELP(mfgprot,
"Usage:\n"
"Print the public key for Manufacturing Protection\n"
"\tmfgprot pubk\n"
"Generates a Manufacturing Protection signature\n"
- "\tmfgprot sign <data_addr> <size>";
+ "\tmfgprot sign <data_addr> <size>\n");
U_BOOT_CMD(
mfgprot, 4, 1, do_mfgprot,
diff --git a/arch/arm/mach-imx/imx8/snvs_security_sc.c b/arch/arm/mach-imx/imx8/snvs_security_sc.c
index f13dfc1..df8c22b 100644
--- a/arch/arm/mach-imx/imx8/snvs_security_sc.c
+++ b/arch/arm/mach-imx/imx8/snvs_security_sc.c
@@ -597,7 +597,7 @@
}
#endif /* CONFIG_IMX_SNVS_SEC_SC_AUTO */
-static char snvs_cfg_help_text[] =
+U_BOOT_LONGHELP(snvs_cfg,
"snvs_cfg\n"
"\thp.lock\n"
"\thp.secvio_ctl\n"
@@ -618,7 +618,7 @@
"\tlp.act_tamper_routing_ctl1\n"
"\tlp.act_tamper_routing_ctl2\n"
"\n"
- "ALL values should be in hexadecimal format";
+ "ALL values should be in hexadecimal format\n");
#define NB_REGISTERS 18
static int do_snvs_cfg(struct cmd_tbl *cmdtp, int flag, int argc,
@@ -662,7 +662,7 @@
snvs_cfg_help_text
);
-static char snvs_dgo_cfg_help_text[] =
+U_BOOT_LONGHELP(snvs_dgo_cfg,
"snvs_dgo_cfg\n"
"\ttamper_offset_ctl\n"
"\ttamper_pull_ctl\n"
@@ -671,7 +671,7 @@
"\ttamper_misc_ctl\n"
"\ttamper_core_volt_mon_ctl\n"
"\n"
- "ALL values should be in hexadecimal format";
+ "ALL values should be in hexadecimal format\n");
static int do_snvs_dgo_cfg(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
@@ -702,12 +702,12 @@
snvs_dgo_cfg_help_text
);
-static char tamper_pin_cfg_help_text[] =
+U_BOOT_LONGHELP(tamper_pin_cfg,
"snvs_dgo_cfg\n"
"\tpad\n"
"\tvalue\n"
"\n"
- "ALL values should be in hexadecimal format";
+ "ALL values should be in hexadecimal format\n");
static int do_tamper_pin_cfg(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
@@ -734,7 +734,7 @@
tamper_pin_cfg_help_text
);
-static char snvs_clear_status_help_text[] =
+U_BOOT_LONGHELP(snvs_clear_status,
"snvs_clear_status\n"
"\tHPSR\n"
"\tHPSVSR\n"
@@ -742,7 +742,7 @@
"\tLPTDSR\n"
"\n"
"Write the status registers with the value provided,"
- " clearing the status";
+ " clearing the status\n");
static int do_snvs_clear_status(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
@@ -778,9 +778,9 @@
snvs_clear_status_help_text
);
-static char snvs_sec_status_help_text[] =
+U_BOOT_LONGHELP(snvs_sec_status,
"snvs_sec_status\n"
- "Display information about the security related to tamper and secvio";
+ "Display information about the security related to tamper and secvio\n");
static int do_snvs_sec_status(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 23d9217..d1fdaec 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -137,12 +137,14 @@
select IMX8MN
select SUPPORT_SPL
select IMX8M_DDR3L
+ imply OF_UPSTREAM
config TARGET_IMX8MN_BSH_SMM_S2PRO
bool "imx8mn-bsh-smm-s2pro"
select IMX8MN
select SUPPORT_SPL
select IMX8M_DDR3L
+ imply OF_UPSTREAM
config TARGET_IMX8MN_EVK
bool "imx8mn LPDDR4 EVK board"
@@ -296,12 +298,14 @@
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
+ imply OF_UPSTREAM
config TARGET_PHYCORE_IMX8MP
bool "PHYTEC PHYCORE i.MX8MP"
select IMX8MP
select SUPPORT_SPL
select IMX8M_LPDDR4
+ imply OF_UPSTREAM
config TARGET_IMX8MM_CL_IOT_GATE
bool "CompuLab iot-gate-imx8"
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 15ee2b9..7800553 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -481,6 +481,7 @@
select DM_MTD
select DM_THERMAL
select SUPPORT_SPL
+ imply OF_UPSTREAM
config TARGET_MYS_6ULX
bool "MYiR MYS-6ULX"
diff --git a/arch/arm/mach-ipq40xx/Makefile b/arch/arm/mach-ipq40xx/Makefile
new file mode 100644
index 0000000..d611de9
--- /dev/null
+++ b/arch/arm/mach-ipq40xx/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2024 Sartura Ltd.
+#
+# Author: Robert Marko <robert.marko@sartura.hr>
+
+obj-y += cpu.o
diff --git a/arch/arm/mach-ipq40xx/cpu.c b/arch/arm/mach-ipq40xx/cpu.c
new file mode 100644
index 0000000..92c34d6
--- /dev/null
+++ b/arch/arm/mach-ipq40xx/cpu.c
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * CPU code for Qualcomm IPQ40xx SoC
+ *
+ * Copyright (c) 2024 Sartura Ltd.
+ *
+ * Author: Robert Marko <robert.marko@sartura.hr>
+ */
+
+#include <cpu_func.h>
+#include <init.h>
+
+int dram_init(void)
+{
+ int ret;
+
+ ret = fdtdec_setup_memory_banksize();
+ if (ret)
+ return ret;
+ return fdtdec_setup_mem_size_base();
+}
+
+/*
+ * Enable/Disable D-cache.
+ * I-cache is already enabled in start.S
+ */
+void enable_caches(void)
+{
+ dcache_enable();
+}
+
+void disable_caches(void)
+{
+ dcache_disable();
+}
+
+/*
+ * In case boards need specific init code, they can override this stub.
+ */
+int __weak board_init(void)
+{
+ return 0;
+}
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index 2bb970c..f3f42b3 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -25,6 +25,9 @@
config SOC_K3_J721S2
bool "TI's K3 based J721S2 SoC Family Support"
+config SOC_K3_J722S
+ bool "TI's K3 based J722S SoC Family Support"
+
config SOC_K3_J784S4
bool "TI's K3 based J784S4 SoC Family Support"
@@ -84,6 +87,7 @@
default 0x43c3f290 if SOC_K3_AM62A7 && CPU_V7R
default 0x7000f290 if SOC_K3_AM62A7 && ARM64
default 0x43c4f290 if SOC_K3_AM62P5
+ default 0x43c7f290 if SOC_K3_J722S
help
Address at which ROM stores the value which determines if SPL
is booted up by primary boot media or secondary boot media.
@@ -122,7 +126,7 @@
config K3_ATF_LOAD_ADDR
hex "Load address of ATF image"
- default 0x80000000 if (SOC_K3_AM625 || SOC_K3_AM62A7 || SOC_K3_AM62P5)
+ default 0x80000000 if (SOC_K3_AM625 || SOC_K3_AM62A7 || SOC_K3_AM62P5 || SOC_K3_J722S)
default 0x70000000
help
The load address for the ATF image. This value is used to build the
@@ -163,6 +167,7 @@
source "arch/arm/mach-k3/am62px/Kconfig"
source "arch/arm/mach-k3/j721e/Kconfig"
source "arch/arm/mach-k3/j721s2/Kconfig"
+source "arch/arm/mach-k3/j722s/Kconfig"
source "arch/arm/mach-k3/j784s4/Kconfig"
endif
diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index 2b3ebd5..8c4f678 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -14,4 +14,5 @@
obj-$(CONFIG_SOC_K3_AM654) += am65x/
obj-$(CONFIG_SOC_K3_J721E) += j721e/
obj-$(CONFIG_SOC_K3_J721S2) += j721s2/
+obj-$(CONFIG_SOC_K3_J722S) += j722s/
obj-$(CONFIG_SOC_K3_J784S4) += j784s4/
diff --git a/arch/arm/mach-k3/am62px/Kconfig b/arch/arm/mach-k3/am62px/Kconfig
index 38a9e68..76ae86b 100644
--- a/arch/arm/mach-k3/am62px/Kconfig
+++ b/arch/arm/mach-k3/am62px/Kconfig
@@ -13,6 +13,7 @@
bool "TI K3 based AM62P5 EVM running on A53"
select ARM64
select BINMAN
+ select OF_SYSTEM_SETUP
config TARGET_AM62P5_R5_EVM
bool "TI K3 based AM62P5 EVM running on R5"
diff --git a/arch/arm/mach-k3/am62px/Makefile b/arch/arm/mach-k3/am62px/Makefile
index 5902862..eed91a0 100644
--- a/arch/arm/mach-k3/am62px/Makefile
+++ b/arch/arm/mach-k3/am62px/Makefile
@@ -3,4 +3,5 @@
# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
# Andrew Davis <afd@ti.com>
+obj-$(CONFIG_OF_SYSTEM_SETUP) += am62p5_fdt.o
obj-$(CONFIG_SPL_BUILD) += am62p5_init.o
diff --git a/arch/arm/mach-k3/am62px/am62p5_fdt.c b/arch/arm/mach-k3/am62px/am62p5_fdt.c
new file mode 100644
index 0000000..29c832d
--- /dev/null
+++ b/arch/arm/mach-k3/am62px/am62p5_fdt.c
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <asm/hardware.h>
+#include "../common_fdt.h"
+#include <fdt_support.h>
+
+int ft_system_setup(void *blob, struct bd_info *bd)
+{
+ fdt_fixup_reserved(blob, "tfa", CONFIG_K3_ATF_LOAD_ADDR, 0x80000);
+ fdt_fixup_reserved(blob, "optee", CONFIG_K3_OPTEE_LOAD_ADDR, 0x1800000);
+
+ return 0;
+}
diff --git a/arch/arm/mach-k3/am62x/am625_init.c b/arch/arm/mach-k3/am62x/am625_init.c
index ed8d24e..72a752d 100644
--- a/arch/arm/mach-k3/am62x/am625_init.c
+++ b/arch/arm/mach-k3/am62x/am625_init.c
@@ -213,6 +213,8 @@
preloader_console_init();
+ do_board_detect();
+
/*
* Allow establishing an early console as required for example when
* doing a UART-based boot. Note that this console may not "survive"
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index 1a269d6..eaa7d36 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -283,8 +283,10 @@
}
/* Default FIT boot on HS-SE devices */
- if (get_device_type() == K3_DEVICE_TYPE_HS_SE)
+ if (get_device_type() == K3_DEVICE_TYPE_HS_SE) {
env_set("boot_fit", "1");
+ env_set("secure_rprocs", "1");
+ }
return 0;
}
diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h
index 53aa186..7bd72da 100644
--- a/arch/arm/mach-k3/common.h
+++ b/arch/arm/mach-k3/common.h
@@ -2,12 +2,13 @@
/*
* K3: Architecture common definitions
*
- * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
#include <asm/armv7_mpu.h>
#include <asm/hardware.h>
+#include <mach/security.h>
#define K3_FIREWALL_BACKGROUND_BIT (8)
@@ -41,7 +42,6 @@
void mmr_unlock(uintptr_t base, u32 partition);
bool is_rom_loaded_sysfw(struct rom_extended_boot_data *data);
enum k3_device_type get_device_type(void);
-void ti_secure_image_post_process(void **p_image, size_t *p_size);
struct ti_sci_handle *get_ti_sci_handle(void);
void do_board_detect(void);
void ti_secure_image_check_binary(void **p_image, size_t *p_size);
diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h
index c724450..b191d53 100644
--- a/arch/arm/mach-k3/include/mach/hardware.h
+++ b/arch/arm/mach-k3/include/mach/hardware.h
@@ -8,37 +8,42 @@
#include <asm/io.h>
-#ifdef CONFIG_SOC_K3_AM654
-#include "am6_hardware.h"
+#ifdef CONFIG_SOC_K3_AM625
+#include "am62_hardware.h"
#endif
-#ifdef CONFIG_SOC_K3_J721E
-#include "j721e_hardware.h"
+#ifdef CONFIG_SOC_K3_AM62A7
+#include "am62a_hardware.h"
#endif
-#ifdef CONFIG_SOC_K3_J721S2
-#include "j721s2_hardware.h"
+#ifdef CONFIG_SOC_K3_AM62P5
+#include "am62p_hardware.h"
#endif
#ifdef CONFIG_SOC_K3_AM642
#include "am64_hardware.h"
#endif
-#ifdef CONFIG_SOC_K3_AM625
-#include "am62_hardware.h"
+#ifdef CONFIG_SOC_K3_AM654
+#include "am6_hardware.h"
#endif
-#ifdef CONFIG_SOC_K3_AM62A7
-#include "am62a_hardware.h"
+#ifdef CONFIG_SOC_K3_J721E
+#include "j721e_hardware.h"
#endif
+#ifdef CONFIG_SOC_K3_J721S2
+#include "j721s2_hardware.h"
+#endif
+
+#ifdef CONFIG_SOC_K3_J722S
+#include "j722s_hardware.h"
+#endif
+
#ifdef CONFIG_SOC_K3_J784S4
#include "j784s4_hardware.h"
#endif
-#ifdef CONFIG_SOC_K3_AM62P5
-#include "am62p_hardware.h"
-#endif
/* Assuming these addresses and definitions stay common across K3 devices */
#define CTRLMMR_WKUP_JTAG_ID (WKUP_CTRL_MMR0_BASE + 0x14)
@@ -54,6 +59,7 @@
#define JTAG_ID_PARTNO_J7200 0xbb6d
#define JTAG_ID_PARTNO_J721E 0xbb64
#define JTAG_ID_PARTNO_J721S2 0xbb75
+#define JTAG_ID_PARTNO_J722S 0xbba0
#define JTAG_ID_PARTNO_J784S4 0xbb80
#define K3_SOC_ID(id, ID) \
@@ -63,14 +69,15 @@
JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT; \
return soc == JTAG_ID_PARTNO_##ID; \
}
-K3_SOC_ID(am65x, AM65X)
-K3_SOC_ID(j721e, J721E)
-K3_SOC_ID(j7200, J7200)
-K3_SOC_ID(am64x, AM64X)
-K3_SOC_ID(j721s2, J721S2)
K3_SOC_ID(am62x, AM62X)
K3_SOC_ID(am62ax, AM62AX)
K3_SOC_ID(am62px, AM62PX)
+K3_SOC_ID(am64x, AM64X)
+K3_SOC_ID(am65x, AM65X)
+K3_SOC_ID(j7200, J7200)
+K3_SOC_ID(j721e, J721E)
+K3_SOC_ID(j721s2, J721S2)
+K3_SOC_ID(j722s, J722S)
#define K3_SEC_MGR_SYS_STATUS 0x44234100
#define SYS_STATUS_DEV_TYPE_SHIFT 0
diff --git a/arch/arm/mach-k3/include/mach/j722s_hardware.h b/arch/arm/mach-k3/include/mach/j722s_hardware.h
new file mode 100644
index 0000000..8d0bec2
--- /dev/null
+++ b/arch/arm/mach-k3/include/mach/j722s_hardware.h
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * K3: J722S SoC definitions, structures etc.
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef __ASM_ARCH_J722S_HARDWARE_H
+#define __ASM_ARCH_J722S_HARDWARE_H
+
+#include <config.h>
+#ifndef __ASSEMBLY__
+#include <linux/bitops.h>
+#endif
+
+#define PADCFG_MMR0_BASE 0x04080000
+#define PADCFG_MMR1_BASE 0x000f0000
+#define CTRL_MMR0_BASE 0x00100000
+#define MCU_CTRL_MMR0_BASE 0x04500000
+#define WKUP_CTRL_MMR0_BASE 0x43000000
+
+#define CTRLMMR_MAIN_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30)
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(6, 3)
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK GENMASK(9, 7)
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT 7
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK GENMASK(12, 10)
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT 10
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK BIT(13)
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT 13
+
+/* Primary Bootmode MMC Config macros */
+#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK 0x4
+#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT 2
+#define MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK 0x1
+#define MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_SHIFT 0
+
+/* Primary Bootmode USB Config macros */
+#define MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT 1
+#define MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK 0x02
+
+/* Backup Bootmode USB Config macros */
+#define MAIN_DEVSTAT_BACKUP_USB_MODE_MASK 0x01
+
+/*
+ * The CTRL_MMR0 memory space is divided into several equally-spaced
+ * partitions, so defining the partition size allows us to determine
+ * register addresses common to those partitions.
+ */
+#define CTRL_MMR0_PARTITION_SIZE 0x4000
+
+/*
+ * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTRL_MMR0 lock/kick-mechanism
+ * shared register definitions. The same registers are also used for
+ * PADCFG_MMR lock/kick-mechanism.
+ */
+#define CTRLMMR_LOCK_KICK0 0x1008
+#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490
+#define CTRLMMR_LOCK_KICK1 0x100c
+#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
+
+#define MCU_CTRL_LFXOSC_CTRL (MCU_CTRL_MMR0_BASE + 0x8038)
+#define MCU_CTRL_LFXOSC_TRIM (MCU_CTRL_MMR0_BASE + 0x803c)
+#define MCU_CTRL_LFXOSC_32K_DISABLE_VAL BIT(7)
+
+#define MCU_CTRL_DEVICE_CLKOUT_32K_CTRL (MCU_CTRL_MMR0_BASE + 0x8058)
+#define MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL (0x3)
+
+#define ROM_EXTENDED_BOOT_DATA_INFO 0x43c7f1e0
+
+#define K3_BOOT_PARAM_TABLE_INDEX_OCRAM 0x7000F290
+
+#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x43c30000
+
+#if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__)
+
+static const u32 put_device_ids[] = {};
+
+static const u32 put_core_ids[] = {};
+
+#endif
+
+#endif /* __ASM_ARCH_J722S_HARDWARE_H */
diff --git a/arch/arm/mach-k3/include/mach/j722s_spl.h b/arch/arm/mach-k3/include/mach/j722s_spl.h
new file mode 100644
index 0000000..eab8c51
--- /dev/null
+++ b/arch/arm/mach-k3/include/mach/j722s_spl.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef _ASM_ARCH_J722S_SPL_H_
+#define _ASM_ARCH_J722S_SPL_H_
+
+/* Primary BootMode devices */
+#define BOOT_DEVICE_SPI_NAND 0x00
+#define BOOT_DEVICE_RAM 0xFF
+#define BOOT_DEVICE_OSPI 0x01
+#define BOOT_DEVICE_QSPI 0x02
+#define BOOT_DEVICE_SPI 0x03
+#define BOOT_DEVICE_CPGMAC 0x04
+#define BOOT_DEVICE_ETHERNET_RGMII 0x04
+#define BOOT_DEVICE_ETHERNET_RMII 0x05
+#define BOOT_DEVICE_I2C 0x06
+#define BOOT_DEVICE_UART 0x07
+#define BOOT_DEVICE_MMC 0x08
+#define BOOT_DEVICE_EMMC 0x09
+
+#define BOOT_DEVICE_USB 0x2A
+#define BOOT_DEVICE_DFU 0x0A
+#define BOOT_DEVICE_GPMC_NAND 0x0B
+#define BOOT_DEVICE_GPMC_NOR 0x0C
+#define BOOT_DEVICE_XSPI 0x0E
+#define BOOT_DEVICE_NOBOOT 0x0F
+
+/* U-Boot used aliases */
+#define BOOT_DEVICE_ETHERNET 0x04
+#define BOOT_DEVICE_SPINAND 0x10
+#define BOOT_DEVICE_MMC2 0x08
+#define BOOT_DEVICE_MMC1 0x09
+/* Invalid */
+#define BOOT_DEVICE_MMC2_2 0x1F
+
+/* Backup BootMode devices */
+#define BACKUP_BOOT_DEVICE_DFU 0x01
+#define BACKUP_BOOT_DEVICE_UART 0x03
+#define BACKUP_BOOT_DEVICE_ETHERNET 0x04
+#define BACKUP_BOOT_DEVICE_MMC 0x05
+#define BACKUP_BOOT_DEVICE_SPI 0x06
+#define BACKUP_BOOT_DEVICE_I2C 0x07
+#define BACKUP_BOOT_DEVICE_USB 0x09
+
+#define K3_PRIMARY_BOOTMODE 0x0
+
+#endif /* _ASM_ARCH_J722S_SPL_H_ */
diff --git a/arch/arm/mach-k3/include/mach/k3-qos.h b/arch/arm/mach-k3/include/mach/k3-qos.h
index e00e1de..eb0f2a0 100644
--- a/arch/arm/mach-k3/include/mach/k3-qos.h
+++ b/arch/arm/mach-k3/include/mach/k3-qos.h
@@ -9,6 +9,26 @@
#include <linux/kernel.h>
+/* K3_QOS_REG: Registers to configure the channel for a given endpoint */
+
+#define K3_QOS_REG(base_reg, i) (base_reg + 0x100 + (i) * 4)
+
+#define K3_QOS_VAL(qos, orderid, asel, epriority, virtid, atype) \
+ (qos << 0 | \
+ orderid << 4 | \
+ asel << 8 | \
+ epriority << 12 | \
+ virtid << 16 | \
+ atype << 28)
+
+/*
+ * K3_QOS_GROUP_REG: Registers to set 1:1 mapping for orderID MAP1/MAP2
+ * remap registers.
+ */
+#define K3_QOS_GROUP_REG(base_reg, i) (base_reg + (i) * 4)
+
+#define K3_QOS_GROUP_DEFAULT_VAL_LOW 0x76543210
+#define K3_QOS_GROUP_DEFAULT_VAL_HIGH 0xfedcba98
struct k3_qos_data {
u32 reg;
u32 val;
diff --git a/arch/arm/mach-k3/include/mach/security.h b/arch/arm/mach-k3/include/mach/security.h
new file mode 100644
index 0000000..8502b57
--- /dev/null
+++ b/arch/arm/mach-k3/include/mach/security.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * K3: Security related definitions
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ * Manorit Chawdhry <m-chawdhry@ti.com>
+ */
+
+#include <linux/types.h>
+
+void ti_secure_image_post_process(void **p_image, size_t *p_size);
diff --git a/arch/arm/mach-k3/include/mach/spl.h b/arch/arm/mach-k3/include/mach/spl.h
index 8394277..ac1a345 100644
--- a/arch/arm/mach-k3/include/mach/spl.h
+++ b/arch/arm/mach-k3/include/mach/spl.h
@@ -38,4 +38,8 @@
#include "am62p_spl.h"
#endif
+#ifdef CONFIG_SOC_K3_J722S
+#include "j722s_spl.h"
+#endif
+
#endif /* _ASM_ARCH_SPL_H_ */
diff --git a/arch/arm/mach-k3/j721e/j721e_init.c b/arch/arm/mach-k3/j721e/j721e_init.c
index c2024f2..e9ed8cb 100644
--- a/arch/arm/mach-k3/j721e/j721e_init.c
+++ b/arch/arm/mach-k3/j721e/j721e_init.c
@@ -23,6 +23,22 @@
#include "../sysfw-loader.h"
#include "../common.h"
+/* NAVSS North Bridge (NB) registers */
+#define NAVSS0_NBSS_NB0_CFG_MMRS 0x03802000
+#define NAVSS0_NBSS_NB1_CFG_MMRS 0x03803000
+#define NAVSS0_NBSS_NB0_CFG_NB_THREADMAP (NAVSS0_NBSS_NB0_CFG_MMRS + 0x10)
+#define NAVSS0_NBSS_NB1_CFG_NB_THREADMAP (NAVSS0_NBSS_NB1_CFG_MMRS + 0x10)
+/*
+ * Thread Map for North Bridge Configuration
+ * Each bit is for each VBUSM source.
+ * Bit[0] maps orderID 0-7 to VBUSM.C thread number
+ * Bit[1] maps orderID 8-15 to VBUSM.C thread number
+ * When bit has value 0: VBUSM.C thread 0 (non-real time traffic)
+ * When bit has value 1: VBUSM.C thread 2 (real time traffic)
+ */
+#define NB_THREADMAP_BIT0 BIT(0)
+#define NB_THREADMAP_BIT1 BIT(1)
+
#ifdef CONFIG_K3_LOAD_SYSFW
struct fwl_data cbass_hc_cfg0_fwls[] = {
#if defined(CONFIG_TARGET_J721E_R5_EVM)
@@ -124,6 +140,13 @@
}
#endif
+/* Setup North Bridge registers to map ORDERID 8-15 to RT traffic */
+static void setup_navss_nb(void)
+{
+ writel(NB_THREADMAP_BIT1, (uintptr_t)NAVSS0_NBSS_NB0_CFG_NB_THREADMAP);
+ writel(NB_THREADMAP_BIT1, (uintptr_t)NAVSS0_NBSS_NB1_CFG_NB_THREADMAP);
+}
+
/*
* This uninitialized global variable would normal end up in the .bss section,
* but the .bss is cleared between writing and reading this variable, so move
@@ -288,6 +311,11 @@
panic("DRAM init failed: %d\n", ret);
#endif
spl_enable_cache();
+
+ if (IS_ENABLED(CONFIG_CPU_V7R))
+ setup_navss_nb();
+
+ setup_qos();
}
u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
diff --git a/arch/arm/mach-k3/j721s2/j721s2_init.c b/arch/arm/mach-k3/j721s2/j721s2_init.c
index fe9766e..05453fc 100644
--- a/arch/arm/mach-k3/j721s2/j721s2_init.c
+++ b/arch/arm/mach-k3/j721s2/j721s2_init.c
@@ -22,6 +22,24 @@
#include "../sysfw-loader.h"
#include "../common.h"
+/* NAVSS North Bridge (NB) */
+#define NAVSS0_NBSS_NB0_CFG_MMRS 0x03702000
+#define NAVSS0_NBSS_NB1_CFG_MMRS 0x03703000
+#define NAVSS0_NBSS_NB0_CFG_NB_THREADMAP (NAVSS0_NBSS_NB0_CFG_MMRS + 0x10)
+#define NAVSS0_NBSS_NB1_CFG_NB_THREADMAP (NAVSS0_NBSS_NB1_CFG_MMRS + 0x10)
+/*
+ * Thread Map for North Bridge Configuration
+ * Each bit is for each VBUSM source.
+ * Bit[0] maps orderID 0-3 to VBUSM.C thread number
+ * Bit[1] maps orderID 4-9 to VBUSM.C thread number
+ * Bit[2] maps orderID 10-15 to VBUSM.C thread number
+ * When bit has value 0: VBUSM.C thread 0 (non-real time traffic)
+ * When bit has value 1: VBUSM.C thread 2 (real time traffic)
+ */
+#define NB_THREADMAP_BIT0 BIT(0)
+#define NB_THREADMAP_BIT1 BIT(1)
+#define NB_THREADMAP_BIT2 BIT(2)
+
struct fwl_data cbass_hc_cfg0_fwls[] = {
{ "PCIE0_CFG", 2577, 7 },
{ "EMMC8SS0_CFG", 2579, 4 },
@@ -123,6 +141,13 @@
}
}
+/* Setup North Bridge registers to map ORDERID 10-15 to RT traffic */
+static void setup_navss_nb(void)
+{
+ writel(NB_THREADMAP_BIT1, (uintptr_t)NAVSS0_NBSS_NB0_CFG_NB_THREADMAP);
+ writel(NB_THREADMAP_BIT2, (uintptr_t)NAVSS0_NBSS_NB1_CFG_NB_THREADMAP);
+}
+
/*
* This uninitialized global variable would normal end up in the .bss section,
* but the .bss is cleared between writing and reading this variable, so move
@@ -295,6 +320,11 @@
do_dt_magic();
#endif
k3_mem_init();
+
+ if (IS_ENABLED(CONFIG_CPU_V7R))
+ setup_navss_nb();
+
+ setup_qos();
}
#endif
diff --git a/arch/arm/mach-k3/j722s/Kconfig b/arch/arm/mach-k3/j722s/Kconfig
new file mode 100644
index 0000000..39d38ea
--- /dev/null
+++ b/arch/arm/mach-k3/j722s/Kconfig
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+#
+
+if SOC_K3_J722S
+
+choice
+ prompt "TI K3 J722S based boards"
+ optional
+
+config TARGET_J722S_A53_EVM
+ bool "TI K3 based J722S EVM running on A53"
+ select ARM64
+ select BINMAN
+ select OF_SYSTEM_SETUP
+
+config TARGET_J722S_R5_EVM
+ bool "TI K3 based J722S EVM running on R5"
+ select CPU_V7R
+ select SYS_THUMB_BUILD
+ select K3_LOAD_SYSFW
+ select RAM
+ select SPL_RAM
+ select K3_DDRSS
+ select BINMAN
+ imply SYS_K3_SPL_ATF
+
+endchoice
+
+source "board/ti/j722s/Kconfig"
+
+endif
diff --git a/arch/arm/mach-k3/j722s/Makefile b/arch/arm/mach-k3/j722s/Makefile
new file mode 100644
index 0000000..2b1fec1
--- /dev/null
+++ b/arch/arm/mach-k3/j722s/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+# Jayesh Choudhary <j-choudhary@ti.com>
+
+obj-$(CONFIG_OF_SYSTEM_SETUP) += j722s_fdt.o
+obj-$(CONFIG_SPL_BUILD) += j722s_init.o
diff --git a/arch/arm/mach-k3/j722s/j722s_fdt.c b/arch/arm/mach-k3/j722s/j722s_fdt.c
new file mode 100644
index 0000000..29c832d
--- /dev/null
+++ b/arch/arm/mach-k3/j722s/j722s_fdt.c
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <asm/hardware.h>
+#include "../common_fdt.h"
+#include <fdt_support.h>
+
+int ft_system_setup(void *blob, struct bd_info *bd)
+{
+ fdt_fixup_reserved(blob, "tfa", CONFIG_K3_ATF_LOAD_ADDR, 0x80000);
+ fdt_fixup_reserved(blob, "optee", CONFIG_K3_OPTEE_LOAD_ADDR, 0x1800000);
+
+ return 0;
+}
diff --git a/arch/arm/mach-k3/j722s/j722s_init.c b/arch/arm/mach-k3/j722s/j722s_init.c
new file mode 100644
index 0000000..01b0068
--- /dev/null
+++ b/arch/arm/mach-k3/j722s/j722s_init.c
@@ -0,0 +1,287 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * J722S: SoC specific initialization
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <dm.h>
+#include <dm/uclass-internal.h>
+#include <dm/pinctrl.h>
+
+#include "../sysfw-loader.h"
+#include "../common.h"
+
+struct fwl_data cbass_main_fwls[] = {
+ { "FSS_DAT_REG3", 7, 8 },
+};
+
+/*
+ * This uninitialized global variable would normal end up in the .bss section,
+ * but the .bss is cleared between writing and reading this variable, so move
+ * it to the .data section.
+ */
+u32 bootindex __section(".data");
+static struct rom_extended_boot_data bootdata __section(".data");
+
+static void store_boot_info_from_rom(void)
+{
+ bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
+ memcpy(&bootdata, (uintptr_t *)ROM_EXTENDED_BOOT_DATA_INFO,
+ sizeof(struct rom_extended_boot_data));
+}
+
+static void ctrl_mmr_unlock(void)
+{
+ /* Unlock all WKUP_CTRL_MMR0 module registers */
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 4);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 5);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
+
+ /* Unlock all CTRL_MMR0 module registers */
+ mmr_unlock(CTRL_MMR0_BASE, 0);
+ mmr_unlock(CTRL_MMR0_BASE, 1);
+ mmr_unlock(CTRL_MMR0_BASE, 2);
+ mmr_unlock(CTRL_MMR0_BASE, 4);
+ mmr_unlock(CTRL_MMR0_BASE, 5);
+ mmr_unlock(CTRL_MMR0_BASE, 6);
+
+ /* Unlock all MCU_CTRL_MMR0 module registers */
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
+
+ /* Unlock PADCFG_CTRL_MMR padconf registers */
+ mmr_unlock(PADCFG_MMR0_BASE, 1);
+ mmr_unlock(PADCFG_MMR1_BASE, 1);
+}
+
+static void k3_spl_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ if (IS_ENABLED(CONFIG_CPU_V7R))
+ setup_k3_mpu_regions();
+
+ /*
+ * Cannot delay this further as there is a chance that
+ * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
+ */
+ store_boot_info_from_rom();
+
+ ctrl_mmr_unlock();
+
+ /* Init DM early */
+ ret = spl_early_init();
+ if (ret)
+ panic("spl_early_init() failed: %d\n", ret);
+
+ /*
+ * Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue
+ * regardless of the result of pinctrl. Do this without probing the
+ * device, but instead by searching the device that would request the
+ * given sequence number if probed. The UART will be used by the DM
+ * firmware image for various purposes and TIFS depends on us to
+ * initialize its pin settings.
+ */
+ ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev);
+ if (!ret)
+ pinctrl_select_state(dev, "default");
+
+ if (IS_ENABLED(CONFIG_K3_EARLY_CONS)) {
+ /*
+ * Allow establishing an early console as required for example
+ * when doing a UART-based boot. Note that this console may not
+ * "survive" through a SYSFW PM-init step and will need a re-init
+ * in some way due to changing module clock frequencies.
+ */
+ ret = early_console_init();
+ if (ret)
+ panic("early_console_init() failed: %d\n", ret);
+ }
+
+ if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW)) {
+ /*
+ * Configure and start up system controller firmware. Provide
+ * the U-Boot console init function to the SYSFW post-PM
+ * configuration callback hook, effectively switching on (or
+ * over) the console output.
+ */
+ ret = is_rom_loaded_sysfw(&bootdata);
+ if (!ret)
+ panic("ROM has not loaded TIFS firmware\n");
+
+ k3_sysfw_loader(true, NULL, NULL);
+ }
+
+ /*
+ * Force probe of clk_k3 driver here to ensure basic default clock
+ * configuration is always done.
+ */
+ if (IS_ENABLED(CONFIG_SPL_CLK_K3)) {
+ ret = uclass_get_device_by_driver(UCLASS_CLK,
+ DM_DRIVER_GET(ti_clk),
+ &dev);
+ if (ret)
+ printf("Failed to initialize clk-k3!\n");
+ }
+
+ preloader_console_init();
+
+ if (IS_ENABLED(CONFIG_CPU_V7R)) {
+ /* Disable ROM configured firewalls right after loading sysfw */
+ remove_fwl_configs(cbass_main_fwls, ARRAY_SIZE(cbass_main_fwls));
+ }
+
+ /* Output System Firmware version info */
+ k3_sysfw_print_ver();
+}
+
+static void k3_mem_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ if (IS_ENABLED(CONFIG_K3_AM62A_DDRSS)) {
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret)
+ panic("DRAM init failed: %d\n", ret);
+ }
+}
+
+void board_init_f(ulong dummy)
+{
+ k3_spl_init();
+ k3_mem_init();
+}
+
+static u32 __get_backup_bootmedia(u32 devstat)
+{
+ u32 bkup_bootmode = (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >>
+ MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT;
+ u32 bkup_bootmode_cfg =
+ (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >>
+ MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT;
+
+ switch (bkup_bootmode) {
+ case BACKUP_BOOT_DEVICE_UART:
+ return BOOT_DEVICE_UART;
+
+ case BACKUP_BOOT_DEVICE_USB:
+ return BOOT_DEVICE_USB;
+
+ case BACKUP_BOOT_DEVICE_ETHERNET:
+ return BOOT_DEVICE_ETHERNET;
+
+ case BACKUP_BOOT_DEVICE_MMC:
+ if (bkup_bootmode_cfg)
+ return BOOT_DEVICE_MMC2;
+ return BOOT_DEVICE_MMC1;
+
+ case BACKUP_BOOT_DEVICE_SPI:
+ return BOOT_DEVICE_SPI;
+
+ case BACKUP_BOOT_DEVICE_I2C:
+ return BOOT_DEVICE_I2C;
+
+ case BACKUP_BOOT_DEVICE_DFU:
+ if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK)
+ return BOOT_DEVICE_USB;
+ return BOOT_DEVICE_DFU;
+ };
+
+ return BOOT_DEVICE_RAM;
+}
+
+static u32 __get_primary_bootmedia(u32 devstat)
+{
+ u32 bootmode = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
+ MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
+ u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
+ MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
+
+ switch (bootmode) {
+ case BOOT_DEVICE_OSPI:
+ fallthrough;
+ case BOOT_DEVICE_QSPI:
+ fallthrough;
+ case BOOT_DEVICE_XSPI:
+ fallthrough;
+ case BOOT_DEVICE_SPI:
+ return BOOT_DEVICE_SPI;
+
+ case BOOT_DEVICE_ETHERNET_RGMII:
+ fallthrough;
+ case BOOT_DEVICE_ETHERNET_RMII:
+ return BOOT_DEVICE_ETHERNET;
+
+ case BOOT_DEVICE_EMMC:
+ return BOOT_DEVICE_MMC1;
+
+ case BOOT_DEVICE_SPI_NAND:
+ return BOOT_DEVICE_SPINAND;
+
+ case BOOT_DEVICE_MMC:
+ if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >>
+ MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT)
+ return BOOT_DEVICE_MMC2;
+ return BOOT_DEVICE_MMC1;
+
+ case BOOT_DEVICE_DFU:
+ if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >>
+ MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT)
+ return BOOT_DEVICE_USB;
+ return BOOT_DEVICE_DFU;
+
+ case BOOT_DEVICE_NOBOOT:
+ return BOOT_DEVICE_RAM;
+ }
+
+ return bootmode;
+}
+
+u32 spl_boot_device(void)
+{
+ u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
+ u32 bootmedia;
+
+ if (bootindex == K3_PRIMARY_BOOTMODE)
+ bootmedia = __get_primary_bootmedia(devstat);
+ else
+ bootmedia = __get_backup_bootmedia(devstat);
+
+ debug("j722s_init: %s: devstat = 0x%x bootmedia = 0x%x bootindex = %d\n",
+ __func__, devstat, bootmedia, bootindex);
+ return bootmedia;
+}
+
+u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
+{
+ u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
+ u32 bootmode = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
+ MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
+ u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
+ MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
+
+ switch (bootmode) {
+ case BOOT_DEVICE_EMMC:
+ return MMCSD_MODE_EMMCBOOT;
+ case BOOT_DEVICE_MMC:
+ if (bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK)
+ return MMCSD_MODE_RAW;
+ default:
+ return MMCSD_MODE_FS;
+ }
+}
diff --git a/arch/arm/mach-k3/j784s4/j784s4_init.c b/arch/arm/mach-k3/j784s4/j784s4_init.c
index 1ce13e0..07b5d7d 100644
--- a/arch/arm/mach-k3/j784s4/j784s4_init.c
+++ b/arch/arm/mach-k3/j784s4/j784s4_init.c
@@ -23,6 +23,24 @@
#define J784S4_MAX_DDR_CONTROLLERS 4
+/* NAVSS North Bridge (NB) */
+#define NAVSS0_NBSS_NB0_CFG_MMRS 0x03702000
+#define NAVSS0_NBSS_NB1_CFG_MMRS 0x03703000
+#define NAVSS0_NBSS_NB0_CFG_NB_THREADMAP (NAVSS0_NBSS_NB0_CFG_MMRS + 0x10)
+#define NAVSS0_NBSS_NB1_CFG_NB_THREADMAP (NAVSS0_NBSS_NB1_CFG_MMRS + 0x10)
+/*
+ * Thread Map for North Bridge Configuration
+ * Each bit is for each VBUSM source.
+ * Bit[0] maps orderID 0-3 to VBUSM.C thread number
+ * Bit[1] maps orderID 4-9 to VBUSM.C thread number
+ * Bit[2] maps orderID 10-15 to VBUSM.C thread number
+ * When bit has value 0: VBUSM.C thread 0 (non-real time traffic)
+ * When bit has value 1: VBUSM.C thread 2 (real time traffic)
+ */
+#define NB_THREADMAP_BIT0 BIT(0)
+#define NB_THREADMAP_BIT1 BIT(1)
+#define NB_THREADMAP_BIT2 BIT(2)
+
struct fwl_data infra_cbass0_fwls[] = {
{ "PSC0", 5, 1 },
{ "PLL_CTRL0", 6, 1 },
@@ -94,6 +112,13 @@
mmr_unlock(CTRL_MMR0_BASE, 7);
}
+/* Setup North Bridge registers to map ORDERID 10-15 to RT traffic */
+static void setup_navss_nb(void)
+{
+ writel(NB_THREADMAP_BIT1, (uintptr_t)NAVSS0_NBSS_NB0_CFG_NB_THREADMAP);
+ writel(NB_THREADMAP_BIT2, (uintptr_t)NAVSS0_NBSS_NB1_CFG_NB_THREADMAP);
+}
+
/*
* This uninitialized global variable would normal end up in the .bss section,
* but the .bss is cleared between writing and reading this variable, so move
@@ -210,6 +235,11 @@
{
k3_spl_init();
k3_mem_init();
+
+ if (IS_ENABLED(CONFIG_CPU_V7R))
+ setup_navss_nb();
+
+ setup_qos();
}
u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
diff --git a/arch/arm/mach-k3/r5/Makefile b/arch/arm/mach-k3/r5/Makefile
index 1cfc8e3..d3886ca 100644
--- a/arch/arm/mach-k3/r5/Makefile
+++ b/arch/arm/mach-k3/r5/Makefile
@@ -3,13 +3,14 @@
# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
# Andrew Davis <afd@ti.com>
+obj-$(CONFIG_SOC_K3_AM625) += am62x/
+obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/
+obj-$(CONFIG_SOC_K3_AM62P5) += am62px/
obj-$(CONFIG_SOC_K3_J721E) += j721e/
obj-$(CONFIG_SOC_K3_J721E) += j7200/
obj-$(CONFIG_SOC_K3_J721S2) += j721s2/
-obj-$(CONFIG_SOC_K3_AM625) += am62x/
-obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/
+obj-$(CONFIG_SOC_K3_J722S) += j722s/
obj-$(CONFIG_SOC_K3_J784S4) += j784s4/
-obj-$(CONFIG_SOC_K3_AM62P5) += am62px/
obj-y += common.o
obj-y += lowlevel_init.o
diff --git a/arch/arm/mach-k3/r5/am62ax/am62a_qos.h b/arch/arm/mach-k3/r5/am62ax/am62a_qos.h
index c74d69a..84a6dc7 100644
--- a/arch/arm/mach-k3/r5/am62ax/am62a_qos.h
+++ b/arch/arm/mach-k3/r5/am62ax/am62a_qos.h
@@ -6,80 +6,6 @@
* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
*/
-#define QOS_0 (0 << 0)
-#define QOS_1 (1 << 0)
-#define QOS_2 (2 << 0)
-#define QOS_3 (3 << 0)
-#define QOS_4 (4 << 0)
-#define QOS_5 (5 << 0)
-#define QOS_6 (6 << 0)
-#define QOS_7 (7 << 0)
-
-#define ORDERID_0 (0 << 4)
-#define ORDERID_1 (1 << 4)
-#define ORDERID_2 (2 << 4)
-#define ORDERID_3 (3 << 4)
-#define ORDERID_4 (4 << 4)
-#define ORDERID_5 (5 << 4)
-#define ORDERID_6 (6 << 4)
-#define ORDERID_7 (7 << 4)
-#define ORDERID_8 (8 << 4)
-#define ORDERID_9 (9 << 4)
-#define ORDERID_10 (10 << 4)
-#define ORDERID_11 (11 << 4)
-#define ORDERID_12 (12 << 4)
-#define ORDERID_13 (13 << 4)
-#define ORDERID_14 (14 << 4)
-#define ORDERID_15 (15 << 4)
-
-#define ASEL_0 (0 << 8)
-#define ASEL_1 (1 << 8)
-#define ASEL_2 (2 << 8)
-#define ASEL_3 (3 << 8)
-#define ASEL_4 (4 << 8)
-#define ASEL_5 (5 << 8)
-#define ASEL_6 (6 << 8)
-#define ASEL_7 (7 << 8)
-#define ASEL_8 (8 << 8)
-#define ASEL_9 (9 << 8)
-#define ASEL_10 (10 << 8)
-#define ASEL_11 (11 << 8)
-#define ASEL_12 (12 << 8)
-#define ASEL_13 (13 << 8)
-#define ASEL_14 (14 << 8)
-#define ASEL_15 (15 << 8)
-
-#define EPRIORITY_0 (0 << 12)
-#define EPRIORITY_1 (1 << 12)
-#define EPRIORITY_2 (2 << 12)
-#define EPRIORITY_3 (3 << 12)
-#define EPRIORITY_4 (4 << 12)
-#define EPRIORITY_5 (5 << 12)
-#define EPRIORITY_6 (6 << 12)
-#define EPRIORITY_7 (7 << 12)
-
-#define VIRTID_0 (0 << 16)
-#define VIRTID_1 (1 << 16)
-#define VIRTID_2 (2 << 16)
-#define VIRTID_3 (3 << 16)
-#define VIRTID_4 (4 << 16)
-#define VIRTID_5 (5 << 16)
-#define VIRTID_6 (6 << 16)
-#define VIRTID_7 (7 << 16)
-#define VIRTID_8 (8 << 16)
-#define VIRTID_9 (9 << 16)
-#define VIRTID_10 (10 << 16)
-#define VIRTID_11 (11 << 16)
-#define VIRTID_12 (12 << 16)
-#define VIRTID_13 (13 << 16)
-#define VIRTID_14 (14 << 16)
-#define VIRTID_15 (15 << 16)
-
-#define ATYPE_0 (0 << 28)
-#define ATYPE_1 (1 << 28)
-#define ATYPE_2 (2 << 28)
-#define ATYPE_3 (3 << 28)
-
#define PULSAR_UL_WKUP_0_CPU0_RMST 0x45D14000
#define PULSAR_UL_WKUP_0_CPU0_WMST 0x45D14400
#define PULSAR_UL_WKUP_0_CPU0_PMST 0x45D14800
diff --git a/arch/arm/mach-k3/r5/am62ax/am62a_qos_uboot.c b/arch/arm/mach-k3/r5/am62ax/am62a_qos_uboot.c
index 9a82944..1d588ac 100644
--- a/arch/arm/mach-k3/r5/am62ax/am62a_qos_uboot.c
+++ b/arch/arm/mach-k3/r5/am62ax/am62a_qos_uboot.c
@@ -12,20 +12,20 @@
struct k3_qos_data qos_data[] = {
/* modules_qosConfig0 - 1 endpoints, 4 channels */
{
- .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 0,
- .val = ORDERID_8,
+ .reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 0),
+ .val = K3_QOS_VAL(0, 8, 0, 0, 0, 0),
},
{
- .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 1,
- .val = ORDERID_8,
+ .reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 1),
+ .val = K3_QOS_VAL(0, 8, 0, 0, 0, 0),
},
{
- .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 2,
- .val = ORDERID_8,
+ .reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 2),
+ .val = K3_QOS_VAL(0, 8, 0, 0, 0, 0),
},
{
- .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 3,
- .val = ORDERID_8,
+ .reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 3),
+ .val = K3_QOS_VAL(0, 8, 0, 0, 0, 0),
},
/* Following registers set 1:1 mapping for orderID MAP1/MAP2
@@ -35,12 +35,12 @@
/* K3_DSS_UL_MAIN_0_VBUSM_DMA - 1 groups */
{
- .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0,
- .val = 0x76543210,
+ .reg = K3_QOS_GROUP_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 0),
+ .val = K3_QOS_GROUP_DEFAULT_VAL_LOW,
},
{
- .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 4,
- .val = 0xfedcba98,
+ .reg = K3_QOS_GROUP_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 1),
+ .val = K3_QOS_GROUP_DEFAULT_VAL_HIGH,
},
};
diff --git a/arch/arm/mach-k3/r5/j721e/Makefile b/arch/arm/mach-k3/r5/j721e/Makefile
index 78325db..07bfb0d 100644
--- a/arch/arm/mach-k3/r5/j721e/Makefile
+++ b/arch/arm/mach-k3/r5/j721e/Makefile
@@ -3,3 +3,4 @@
# Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
obj-y += clk-data.o
obj-y += dev-data.o
+obj-y += j721e_qos_uboot.o
diff --git a/arch/arm/mach-k3/r5/j721e/j721e_qos.h b/arch/arm/mach-k3/r5/j721e/j721e_qos.h
new file mode 100644
index 0000000..9ec0b7c
--- /dev/null
+++ b/arch/arm/mach-k3/r5/j721e/j721e_qos.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Keystone3 Quality of service endpoint definitions
+ * Auto generated by K3 Resource Partitioning Tool
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#define PULSAR_SL_MCU_0_MEMBDG_RMST0 0x45D10000
+#define PULSAR_SL_MCU_0_MEMBDG_WMST0 0x45D10400
+#define PULSAR_SL_MCU_0_CPU0_PMST 0x45D10800
+#define PULSAR_SL_MCU_0_MEMBDG_RMST1 0x45D11000
+#define PULSAR_SL_MCU_0_MEMBDG_WMST1 0x45D11400
+#define PULSAR_SL_MCU_0_CPU1_PMST 0x45D11800
+#define SA2_UL_MCU_0_CTXCACH_EXT_DMA 0x45D13000
+#define ICSS_G_MAIN_0_PR1_EXT_VBUSM 0x45D80000
+#define ICSS_G_MAIN_1_PR1_EXT_VBUSM 0x45D80400
+#define K3_C66_COREPAC_MAIN_0_C66_MDMA 0x45D81000
+#define K3_C66_COREPAC_MAIN_1_C66_MDMA 0x45D81400
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD 0x45D82000
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR 0x45D82400
+#define EMMCSD4SS_MAIN_1_EMMCSDSS_RD 0x45D82800
+#define EMMCSD4SS_MAIN_1_EMMCSDSS_WR 0x45D82C00
+#define PULSAR_SL_MAIN_0_MEMBDG_RMST0 0x45D84000
+#define PULSAR_SL_MAIN_0_MEMBDG_RMST1 0x45D84400
+#define PULSAR_SL_MAIN_0_MEMBDG_WMST0 0x45D84800
+#define PULSAR_SL_MAIN_0_MEMBDG_WMST1 0x45D84C00
+#define PULSAR_SL_MAIN_1_MEMBDG_RMST0 0x45D85000
+#define PULSAR_SL_MAIN_1_MEMBDG_RMST1 0x45D85400
+#define PULSAR_SL_MAIN_1_MEMBDG_WMST0 0x45D85800
+#define PULSAR_SL_MAIN_1_MEMBDG_WMST1 0x45D85C00
+#define COMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM 0x45D86000
+#define COMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM 0x45D86400
+#define K3_C66_COREPAC_MAIN_0_C66_CFG 0x45D87000
+#define K3_C66_COREPAC_MAIN_1_C66_CFG 0x45D87400
+#define SA2_UL_MAIN_0_CTXCACH_EXT_DMA 0x45D88800
+#define PULSAR_SL_MAIN_0_PBDG_RMST0 0x45D89800
+#define PULSAR_SL_MAIN_0_PBDG_RMST1 0x45D89C00
+#define PULSAR_SL_MAIN_0_PBDG_WMST0 0x45D8A000
+#define PULSAR_SL_MAIN_0_PBDG_WMST1 0x45D8A400
+#define PULSAR_SL_MAIN_1_PBDG_RMST0 0x45D8A800
+#define PULSAR_SL_MAIN_1_PBDG_RMST1 0x45D8AC00
+#define PULSAR_SL_MAIN_1_PBDG_WMST0 0x45D8B000
+#define PULSAR_SL_MAIN_1_PBDG_WMST1 0x45D8B400
+#define VPFE_MAIN_0_VBUSM_DMA 0x45D8C000
+#define VPE_MAIN_0_VPDMA_MST0 0x45D8C400
+#define VPE_MAIN_0_VPDMA_MST1 0x45D8C800
+#define PCIE_G4X2_MAIN_0_PCIE_MST_RD_HP 0x45D90000
+#define PCIE_G4X2_MAIN_0_PCIE_MST_RD_LP 0x45D90400
+#define PCIE_G4X2_MAIN_0_PCIE_MST_WR_HP 0x45D90800
+#define PCIE_G4X2_MAIN_0_PCIE_MST_WR_LP 0x45D90C00
+#define PCIE_G4X2_MAIN_1_PCIE_MST_RD_HP 0x45D91000
+#define PCIE_G4X2_MAIN_1_PCIE_MST_RD_LP 0x45D91400
+#define PCIE_G4X2_MAIN_1_PCIE_MST_WR_HP 0x45D91800
+#define PCIE_G4X2_MAIN_1_PCIE_MST_WR_LP 0x45D91C00
+#define PCIE_G4X2_MAIN_2_PCIE_MST_RD_HP 0x45D92000
+#define PCIE_G4X2_MAIN_2_PCIE_MST_RD_LP 0x45D92400
+#define PCIE_G4X2_MAIN_2_PCIE_MST_WR_HP 0x45D92800
+#define PCIE_G4X2_MAIN_2_PCIE_MST_WR_LP 0x45D92C00
+#define PCIE_G4X2_MAIN_3_PCIE_MST_RD_HP 0x45D93000
+#define PCIE_G4X2_MAIN_3_PCIE_MST_RD_LP 0x45D93400
+#define PCIE_G4X2_MAIN_3_PCIE_MST_WR_HP 0x45D93800
+#define PCIE_G4X2_MAIN_3_PCIE_MST_WR_LP 0x45D93C00
+#define USB3P0SS_16FFC_MAIN_0_MSTR0 0x45D98000
+#define USB3P0SS_16FFC_MAIN_0_MSTW0 0x45D98400
+#define USB3P0SS_16FFC_MAIN_1_MSTR0 0x45D98800
+#define USB3P0SS_16FFC_MAIN_1_MSTW0 0x45D98C00
+#define USB3P0SS_16FFC_MAIN_2_MSTR0 0x45D99000
+#define USB3P0SS_16FFC_MAIN_2_MSTW0 0x45D99400
+#define MLBSS2P0_MAIN_0_MLBSS_DMA_VBUSP 0x45D99C00
+#define EMMC8SS_16FFC_MAIN_0_EMMCSS_RD 0x45D9A000
+#define EMMC8SS_16FFC_MAIN_0_EMMCSS_WR 0x45D9A400
+#define UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_RD 0x45D9B000
+#define UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_WR 0x45D9B400
+#define UFSHCI2P1SS_16FFC_MAIN_1_UFSHCI_VBM_MST_RD 0x45D9B800
+#define UFSHCI2P1SS_16FFC_MAIN_1_UFSHCI_VBM_MST_WR 0x45D9BC00
+#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR 0x45DA0000
+#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW 0x45DA0400
+#define PULSAR_SL_MAIN_0_CPU0_PMST 0x45DA4000
+#define PULSAR_SL_MAIN_0_CPU1_PMST 0x45DA4400
+#define PULSAR_SL_MAIN_1_CPU0_PMST 0x45DA4800
+#define PULSAR_SL_MAIN_1_CPU1_PMST 0x45DA4C00
+#define DMPAC_TOP_MAIN_0_DATA_MST 0x45DC0000
+#define K3_D5520MP2_MAIN_0_M_VBUSM_R 0x45DC0400
+#define K3_D5520MP2_MAIN_0_M_VBUSM_W 0x45DC0800
+#define K3_VXE384MP2_MAIN_0_M_VBUSM_R 0x45DC0C00
+#define K3_VXE384MP2_MAIN_0_M_VBUSM_W 0x45DC1000
+#define VPAC_TOP_MAIN_0_DATA_MST_0 0x45DC1400
+#define VPAC_TOP_MAIN_0_DATA_MST_1 0x45DC1800
+#define VPAC_TOP_MAIN_0_LDC0_M_MST 0x45DC1C00
+#define K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA 0x45DC2000
+#define K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC 0x45DC2400
+#define J7_LASCAR_GPU_WRAP_MAIN_0_M0_VBUSM_R_ASYNC 0x45DC5000
+#define J7_LASCAR_GPU_WRAP_MAIN_0_M0_VBUSM_W_ASYNC 0x45DC5800
+#define J7_LASCAR_GPU_WRAP_MAIN_0_M1_VBUSM_R_ASYNC 0x45DC6000
+#define J7_LASCAR_GPU_WRAP_MAIN_0_M1_VBUSM_W_ASYNC 0x45DC6800
diff --git a/arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c b/arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c
new file mode 100644
index 0000000..713849a
--- /dev/null
+++ b/arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c
@@ -0,0 +1,126 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * j721e Quality of Service (QoS) Configuration Data
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <asm/arch/k3-qos.h>
+#include "j721e_qos.h"
+
+struct k3_qos_data qos_data[] = {
+ /* DSS_PIPE_VID1 - 2 endpoints, 2 channels */
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 0),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 1),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 0),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 1),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+
+ /* DSS_PIPE_VIDL1 - 2 endpoints, 2 channels */
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 2),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 3),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 2),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 3),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+
+ /* DSS_PIPE_VID2 - 2 endpoints, 2 channels */
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 4),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 5),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 4),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 5),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+
+ /* DSS_PIPE_VIDL2 - 2 endpoints, 2 channels */
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 6),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 7),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 6),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 7),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+
+ /* Following registers set 1:1 mapping for orderID MAP1/MAP2
+ * remap registers. orderID x is remapped to orderID x again
+ * This is to ensure orderID from MAP register is unchanged
+ */
+
+ /* K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA - 2 groups */
+ {
+ .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 0),
+ .val = K3_QOS_GROUP_DEFAULT_VAL_LOW,
+ },
+ {
+ .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 1),
+ .val = K3_QOS_GROUP_DEFAULT_VAL_HIGH,
+ },
+ {
+ .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 2),
+ .val = K3_QOS_GROUP_DEFAULT_VAL_LOW,
+ },
+ {
+ .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 3),
+ .val = K3_QOS_GROUP_DEFAULT_VAL_HIGH,
+ },
+
+ /* K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC - 2 groups */
+ {
+ .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 0),
+ .val = K3_QOS_GROUP_DEFAULT_VAL_LOW,
+ },
+ {
+ .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 1),
+ .val = K3_QOS_GROUP_DEFAULT_VAL_HIGH,
+ },
+ {
+ .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 2),
+ .val = K3_QOS_GROUP_DEFAULT_VAL_LOW,
+ },
+ {
+ .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 3),
+ .val = K3_QOS_GROUP_DEFAULT_VAL_HIGH,
+ },
+};
+
+u32 qos_count = ARRAY_SIZE(qos_data);
diff --git a/arch/arm/mach-k3/r5/j721s2/Makefile b/arch/arm/mach-k3/r5/j721s2/Makefile
index 8588c5e..89c0284 100644
--- a/arch/arm/mach-k3/r5/j721s2/Makefile
+++ b/arch/arm/mach-k3/r5/j721s2/Makefile
@@ -3,3 +3,4 @@
# Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
obj-y += clk-data.o
obj-y += dev-data.o
+obj-y += j721s2_qos_uboot.o
diff --git a/arch/arm/mach-k3/r5/j721s2/j721s2_qos.h b/arch/arm/mach-k3/r5/j721s2/j721s2_qos.h
new file mode 100644
index 0000000..ab3e477
--- /dev/null
+++ b/arch/arm/mach-k3/r5/j721s2/j721s2_qos.h
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Keystone3 Quality of service endpoint definitions
+ * Auto generated by K3 Resource Partitioning Tool
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#define SMS_WKUP_0_TIFS_VBUSP_M 0x45D00000
+#define SMS_WKUP_0_HSM_VBUSP_M 0x45D00400
+#define PULSAR_SL_MCU_0_CPU0_RMST 0x45D10000
+#define PULSAR_SL_MCU_0_CPU0_WMST 0x45D10400
+#define PULSAR_SL_MCU_0_CPU0_PMST 0x45D10800
+#define PULSAR_SL_MCU_0_CPU1_RMST 0x45D11000
+#define PULSAR_SL_MCU_0_CPU1_WMST 0x45D11400
+#define PULSAR_SL_MCU_0_CPU1_PMST 0x45D11800
+#define SA3SS_AM62_MCU_0_CTXCACH_EXT_DMA 0x45D13000
+#define PULSAR_SL_MAIN_0_PBDG_RMST0 0x45D78000
+#define PULSAR_SL_MAIN_0_PBDG_WMST0 0x45D78400
+#define PULSAR_SL_MAIN_0_PBDG_RMST1 0x45D78800
+#define PULSAR_SL_MAIN_0_PBDG_WMST1 0x45D78C00
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD 0x45D82800
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR 0x45D82C00
+#define COMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_RD_VBUSM 0x45D86000
+#define COMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_WR_VBUSM 0x45D86400
+#define PCIE_G3X4_128_MAIN_0_PCIE_MST_RD 0x45D98400
+#define PCIE_G3X4_128_MAIN_0_PCIE_MST_WR 0x45D98C00
+#define PCIE_G3X4_128_MAIN_1_PCIE_MST_RD 0x45D99400
+#define PCIE_G3X4_128_MAIN_1_PCIE_MST_WR 0x45D99C00
+#define USB3P0SS_16FFC_MAIN_0_MSTR0 0x45D9A000
+#define USB3P0SS_16FFC_MAIN_0_MSTW0 0x45D9A400
+#define UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_RD 0x45D9AC00
+#define UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_WR 0x45D9B000
+#define EMMC8SS_16FFC_MAIN_0_EMMCSS_WR 0x45D9B400
+#define EMMC8SS_16FFC_MAIN_0_EMMCSS_RD 0x45D9B800
+#define SA2_UL_MAIN_0_CTXCACH_EXT_DMA 0x45D9BC00
+#define VUSR_DUAL_MAIN_0_V0_M 0x45D9C000
+#define VUSR_DUAL_MAIN_0_V1_M 0x45D9C400
+#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR 0x45DA0000
+#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW 0x45DA0400
+#define PULSAR_SL_MAIN_1_CPU0_RMST 0x45DA8000
+#define PULSAR_SL_MAIN_1_CPU0_WMST 0x45DA8400
+#define PULSAR_SL_MAIN_1_CPU1_RMST 0x45DA8800
+#define PULSAR_SL_MAIN_1_CPU1_WMST 0x45DA8C00
+#define PULSAR_SL_MAIN_2_CPU0_RMST 0x45DA9000
+#define PULSAR_SL_MAIN_2_CPU0_WMST 0x45DA9400
+#define PULSAR_SL_MAIN_2_CPU1_RMST 0x45DA9800
+#define PULSAR_SL_MAIN_2_CPU1_WMST 0x45DA9C00
+#define DMPAC_TOP_MAIN_0_DATA_MST 0x45DC0000
+#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_R_ASYNC 0x45DC0C00
+#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_W_ASYNC 0x45DC1000
+#define VPAC_TOP_MAIN_0_DATA_MST_0 0x45DC1400
+#define VPAC_TOP_MAIN_0_DATA_MST_1 0x45DC1800
+#define VPAC_TOP_MAIN_0_LDC0_M_MST 0x45DC1C00
+#define K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA 0x45DC2000
+#define K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC 0x45DC2400
+#define VPAC_TOP_MAIN_1_LDC0_M_MST 0x45DC2800
+#define VPAC_TOP_MAIN_1_DATA_MST_0 0x45DC2C00
+#define VPAC_TOP_MAIN_1_DATA_MST_1 0x45DC3000
+#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_R_ASYNC 0x45DC3400
+#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_W_ASYNC 0x45DC3800
+#define K3_VPU_WAVE521CL_MAIN_1_SEC_M_VBUSM_R_ASYNC 0x45DC3C00
+#define K3_VPU_WAVE521CL_MAIN_1_SEC_M_VBUSM_W_ASYNC 0x45DC4000
+#define K3_VPU_WAVE521CL_MAIN_1_PRI_M_VBUSM_R_ASYNC 0x45DC4400
+#define K3_VPU_WAVE521CL_MAIN_1_PRI_M_VBUSM_W_ASYNC 0x45DC4800
+#define J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC 0x45DC5000
+#define J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC 0x45DC5800
+#define PULSAR_SL_MAIN_0_CPU0_RMST 0x45DC8000
+#define PULSAR_SL_MAIN_0_CPU0_WMST 0x45DC8400
+#define PULSAR_SL_MAIN_0_CPU1_RMST 0x45DC8800
+#define PULSAR_SL_MAIN_0_CPU1_WMST 0x45DC8C00
+#define PULSAR_SL_MAIN_1_PBDG_RMST0 0x45DCA000
+#define PULSAR_SL_MAIN_1_PBDG_WMST0 0x45DCA400
+#define PULSAR_SL_MAIN_1_PBDG_RMST1 0x45DCA800
+#define PULSAR_SL_MAIN_1_PBDG_WMST1 0x45DCAC00
+#define PULSAR_SL_MAIN_2_PBDG_RMST0 0x45DCB000
+#define PULSAR_SL_MAIN_2_PBDG_WMST0 0x45DCB400
+#define PULSAR_SL_MAIN_2_PBDG_RMST1 0x45DCB800
+#define PULSAR_SL_MAIN_2_PBDG_WMST1 0x45DCBC00
diff --git a/arch/arm/mach-k3/r5/j721s2/j721s2_qos_uboot.c b/arch/arm/mach-k3/r5/j721s2/j721s2_qos_uboot.c
new file mode 100644
index 0000000..54d81d9
--- /dev/null
+++ b/arch/arm/mach-k3/r5/j721s2/j721s2_qos_uboot.c
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * j721s2 Quality of Service (QoS) Configuration Data
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <asm/arch/k3-qos.h>
+#include "j721s2_qos.h"
+
+struct k3_qos_data qos_data[] = {
+ /* DSS_PIPE_VID1 - 2 endpoints, 2 channels */
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 0),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 1),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 0),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 1),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+
+ /* DSS_PIPE_VIDL1 - 2 endpoints, 2 channels */
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 2),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 3),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 2),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 3),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+
+ /* DSS_PIPE_VID2 - 2 endpoints, 2 channels */
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 4),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 5),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 4),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 5),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+
+ /* DSS_PIPE_VIDL2 - 2 endpoints, 2 channels */
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 6),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 7),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 6),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 7),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+
+ /* Following registers set 1:1 mapping for orderID MAP1/MAP2
+ * remap registers. orderID x is remapped to orderID x again
+ * This is to ensure orderID from MAP register is unchanged
+ */
+
+ /* K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA - 1 groups */
+ {
+ .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 0),
+ .val = K3_QOS_GROUP_DEFAULT_VAL_LOW,
+ },
+ {
+ .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 1),
+ .val = K3_QOS_GROUP_DEFAULT_VAL_HIGH,
+ },
+
+ /* K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC - 1 groups */
+ {
+ .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 0),
+ .val = K3_QOS_GROUP_DEFAULT_VAL_LOW,
+ },
+ {
+ .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 1),
+ .val = K3_QOS_GROUP_DEFAULT_VAL_HIGH,
+ },
+};
+
+u32 qos_count = ARRAY_SIZE(qos_data);
diff --git a/arch/arm/mach-k3/r5/j722s/Makefile b/arch/arm/mach-k3/r5/j722s/Makefile
new file mode 100644
index 0000000..2a0dbf5
--- /dev/null
+++ b/arch/arm/mach-k3/r5/j722s/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+
+obj-y += clk-data.o
+obj-y += dev-data.o
diff --git a/arch/arm/mach-k3/r5/j722s/clk-data.c b/arch/arm/mach-k3/r5/j722s/clk-data.c
new file mode 100644
index 0000000..b4f27af
--- /dev/null
+++ b/arch/arm/mach-k3/r5/j722s/clk-data.c
@@ -0,0 +1,312 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * J722S specific clock platform data
+ *
+ * This file is auto generated. Please do not hand edit and report any issues
+ * to Bryan Brattlof <bb@ti.com>.
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <linux/clk-provider.h>
+#include "k3-clk.h"
+
+static const char * const gluelogic_hfosc0_clkout_parents[] = {
+ NULL,
+ NULL,
+ "osc_24_mhz",
+ "osc_25_mhz",
+ "osc_26_mhz",
+ NULL,
+};
+
+static const char * const clk_32k_rc_sel_out0_parents[] = {
+ "gluelogic_rcosc_clk_1p0v_97p65k",
+ "gluelogic_hfosc0_clkout",
+ "gluelogic_rcosc_clk_1p0v_97p65k",
+ "gluelogic_lfosc0_clkout",
+};
+
+static const char * const main_emmcsd1_io_clklb_sel_out0_parents[] = {
+ "board_0_mmc1_clklb_out",
+ "board_0_mmc1_clk_out",
+};
+
+static const char * const main_ospi_loopback_clk_sel_out0_parents[] = {
+ "board_0_ospi0_dqs_out",
+ "board_0_ospi0_lbclko_out",
+};
+
+static const char * const main_usb0_refclk_sel_out0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "postdiv4_16ff_main_0_hsdivout8_clk",
+};
+
+static const char * const sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "hsdiv4_16fft_main_0_hsdivout0_clk",
+};
+
+static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "hsdiv4_16fft_mcu_0_hsdivout0_clk",
+};
+
+static const char * const clkout0_ctrl_out0_parents[] = {
+ "hsdiv4_16fft_main_2_hsdivout1_clk",
+ "hsdiv4_16fft_main_2_hsdivout1_clk",
+};
+
+static const char * const main_emmcsd0_refclk_sel_out0_parents[] = {
+ "postdiv4_16ff_main_0_hsdivout5_clk",
+ "hsdiv4_16fft_main_2_hsdivout2_clk",
+};
+
+static const char * const main_emmcsd1_refclk_sel_out0_parents[] = {
+ "postdiv4_16ff_main_0_hsdivout5_clk",
+ "hsdiv4_16fft_main_2_hsdivout2_clk",
+};
+
+static const char * const main_gtcclk_sel_out0_parents[] = {
+ "postdiv4_16ff_main_2_hsdivout5_clk",
+ "postdiv4_16ff_main_0_hsdivout6_clk",
+ "board_0_cp_gemac_cpts0_rft_clk_out",
+ NULL,
+ "board_0_mcu_ext_refclk0_out",
+ "board_0_ext_refclk1_out",
+ "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk",
+ "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
+};
+
+static const char * const main_ospi_ref_clk_sel_out0_parents[] = {
+ "hsdiv4_16fft_main_0_hsdivout1_clk",
+ "postdiv1_16fft_main_1_hsdivout5_clk",
+};
+
+static const char * const main_timerclkn_sel_out0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "clk_32k_rc_sel_out0",
+ "postdiv4_16ff_main_0_hsdivout7_clk",
+ "gluelogic_rcosc_clkout",
+ "board_0_mcu_ext_refclk0_out",
+ "board_0_ext_refclk1_out",
+ NULL,
+ "board_0_cp_gemac_cpts0_rft_clk_out",
+ "hsdiv4_16fft_main_1_hsdivout3_clk",
+ "postdiv4_16ff_main_2_hsdivout6_clk",
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+};
+
+static const char * const wkup_clkout_sel_out0_parents[] = {
+ NULL,
+ "gluelogic_lfosc0_clkout",
+ "hsdiv4_16fft_main_0_hsdivout2_clk",
+ "hsdiv4_16fft_main_1_hsdivout2_clk",
+ "postdiv4_16ff_main_2_hsdivout9_clk",
+ "clk_32k_rc_sel_out0",
+ "gluelogic_rcosc_clkout",
+ "gluelogic_hfosc0_clkout",
+};
+
+static const char * const wkup_clkout_sel_io_out0_parents[] = {
+ "wkup_clkout_sel_out0",
+ "gluelogic_hfosc0_clkout",
+};
+
+static const char * const wkup_clksel_out0_parents[] = {
+ "hsdiv3_16fft_main_15_hsdivout0_clk",
+ "hsdiv4_16fft_mcu_0_hsdivout0_clk",
+};
+
+static const char * const main_usart0_fclk_sel_out0_parents[] = {
+ "usart_programmable_clock_divider_out0",
+ "hsdiv4_16fft_main_1_hsdivout1_clk",
+};
+
+static const struct clk_data clk_list[] = {
+ CLK_FIXED_RATE("osc_26_mhz", 26000000, 0),
+ CLK_FIXED_RATE("osc_25_mhz", 25000000, 0),
+ CLK_FIXED_RATE("osc_24_mhz", 24000000, 0),
+ CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0),
+ CLK_FIXED_RATE("gluelogic_rcosc_clkout", 12500000, 0),
+ CLK_FIXED_RATE("gluelogic_rcosc_clk_1p0v_97p65k", 97656, 0),
+ CLK_FIXED_RATE("board_0_cp_gemac_cpts0_rft_clk_out", 0, 0),
+ CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0),
+ CLK_FIXED_RATE("board_0_i2c0_scl_out", 0, 0),
+ CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0),
+ CLK_FIXED_RATE("board_0_mmc1_clklb_out", 0, 0),
+ CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
+ CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0),
+ CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0),
+ CLK_FIXED_RATE("board_0_tck_out", 0, 0),
+ CLK_FIXED_RATE("dmtimer_dmc1ms_main_0_timer_pwm", 0, 0),
+ CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
+ CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0),
+ CLK_FIXED_RATE("mshsi2c_main_0_porscl", 0, 0),
+ CLK_PLL("pllfracf2_ssmod_16fft_main_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x680000, 0),
+ CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
+ CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
+ CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_main_1_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x681000, 0, 1920000000),
+ CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
+ CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
+ CLK_PLL("pllfracf2_ssmod_16fft_main_12_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68c000, 0),
+ CLK_PLL("pllfracf2_ssmod_16fft_main_15_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68f000, 0),
+ CLK_PLL("pllfracf2_ssmod_16fft_main_2_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x682000, 0),
+ CLK_DIV("pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
+ CLK_DIV("pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", 0x682038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
+ CLK_PLL("pllfracf2_ssmod_16fft_main_8_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x688000, 0),
+ CLK_PLL("pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x4040000, 0),
+ CLK_DIV("postdiv1_16fft_main_1_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0),
+ CLK_DIV("postdiv4_16ff_main_0_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680094, 0, 7, 0, 0),
+ CLK_DIV("postdiv4_16ff_main_0_hsdivout6_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0),
+ CLK_DIV("postdiv4_16ff_main_0_hsdivout7_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x68009c, 0, 7, 0, 0),
+ CLK_DIV("postdiv4_16ff_main_0_hsdivout8_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0),
+ CLK_DIV("postdiv4_16ff_main_2_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x682094, 0, 7, 0, 0),
+ CLK_DIV("postdiv4_16ff_main_2_hsdivout6_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x682098, 0, 7, 0, 0),
+ CLK_DIV("postdiv4_16ff_main_2_hsdivout8_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a0, 0, 7, 0, 0),
+ CLK_DIV("postdiv4_16ff_main_2_hsdivout9_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a4, 0, 7, 0, 0),
+ CLK_MUX("clk_32k_rc_sel_out0", clk_32k_rc_sel_out0_parents, 4, 0x4508058, 0, 2, 0),
+ CLK_MUX("main_emmcsd1_io_clklb_sel_out0", main_emmcsd1_io_clklb_sel_out0_parents, 2, 0x108168, 16, 1, 0),
+ CLK_MUX("main_ospi_loopback_clk_sel_out0", main_ospi_loopback_clk_sel_out0_parents, 2, 0x108500, 4, 1, 0),
+ CLK_MUX("main_usb0_refclk_sel_out0", main_usb0_refclk_sel_out0_parents, 2, 0x43008190, 0, 1, 0),
+ CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0),
+ CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0),
+ CLK_DIV("hsdiv3_16fft_main_15_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0),
+ CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000),
+ CLK_DIV("hsdiv4_16fft_main_1_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681084, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_main_1_hsdivout3_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x68108c, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0),
+ CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
+ CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0),
+ CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0),
+ CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0),
+ CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0),
+ CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0),
+ CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0),
+ CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0),
+ CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0),
+ CLK_MUX("main_timerclkn_sel_out0", main_timerclkn_sel_out0_parents, 16, 0x1081b0, 0, 4, 0),
+ CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x108240, 0, 2, 0, 0, 48000000),
+ CLK_MUX("wkup_clkout_sel_out0", wkup_clkout_sel_out0_parents, 8, 0x43008020, 0, 3, 0),
+ CLK_MUX("wkup_clkout_sel_io_out0", wkup_clkout_sel_io_out0_parents, 2, 0x43008020, 24, 1, 0),
+ CLK_MUX("wkup_clksel_out0", wkup_clksel_out0_parents, 2, 0x43008010, 0, 1, 0),
+ CLK_MUX("main_usart0_fclk_sel_out0", main_usart0_fclk_sel_out0_parents, 2, 0x108280, 0, 1, 0),
+ CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0),
+ CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x402011c, 0, 5, 0, 0),
+};
+
+static const struct dev_clk soc_dev_clk_data[] = {
+ DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"),
+ DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
+ DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
+ DEV_CLK(16, 3, "hsdiv4_16fft_main_0_hsdivout4_clk"),
+ DEV_CLK(16, 4, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(16, 5, "board_0_ext_refclk1_out"),
+ DEV_CLK(16, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(16, 7, "postdiv4_16ff_main_2_hsdivout8_clk"),
+ DEV_CLK(16, 8, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(16, 9, "board_0_ext_refclk1_out"),
+ DEV_CLK(16, 10, "gluelogic_rcosc_clkout"),
+ DEV_CLK(16, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(16, 12, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(36, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(36, 2, "main_timerclkn_sel_out0"),
+ DEV_CLK(36, 3, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(36, 4, "clk_32k_rc_sel_out0"),
+ DEV_CLK(36, 5, "postdiv4_16ff_main_0_hsdivout7_clk"),
+ DEV_CLK(36, 6, "gluelogic_rcosc_clkout"),
+ DEV_CLK(36, 7, "board_0_mcu_ext_refclk0_out"),
+ DEV_CLK(36, 8, "board_0_ext_refclk1_out"),
+ DEV_CLK(36, 10, "board_0_cp_gemac_cpts0_rft_clk_out"),
+ DEV_CLK(36, 11, "hsdiv4_16fft_main_1_hsdivout3_clk"),
+ DEV_CLK(36, 12, "postdiv4_16ff_main_2_hsdivout6_clk"),
+ DEV_CLK(57, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(57, 2, "main_emmcsd0_refclk_sel_out0"),
+ DEV_CLK(57, 3, "postdiv4_16ff_main_0_hsdivout5_clk"),
+ DEV_CLK(57, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"),
+ DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"),
+ DEV_CLK(58, 1, "board_0_mmc1_clklb_out"),
+ DEV_CLK(58, 2, "board_0_mmc1_clk_out"),
+ DEV_CLK(58, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(58, 6, "main_emmcsd1_refclk_sel_out0"),
+ DEV_CLK(58, 7, "postdiv4_16ff_main_0_hsdivout5_clk"),
+ DEV_CLK(58, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"),
+ DEV_CLK(61, 0, "main_gtcclk_sel_out0"),
+ DEV_CLK(61, 1, "postdiv4_16ff_main_2_hsdivout5_clk"),
+ DEV_CLK(61, 2, "postdiv4_16ff_main_0_hsdivout6_clk"),
+ DEV_CLK(61, 3, "board_0_cp_gemac_cpts0_rft_clk_out"),
+ DEV_CLK(61, 5, "board_0_mcu_ext_refclk0_out"),
+ DEV_CLK(61, 6, "board_0_ext_refclk1_out"),
+ DEV_CLK(61, 7, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
+ DEV_CLK(61, 8, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(61, 9, "wkup_clksel_out0"),
+ DEV_CLK(61, 10, "hsdiv3_16fft_main_15_hsdivout0_clk"),
+ DEV_CLK(61, 11, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
+ DEV_CLK(75, 0, "board_0_ospi0_dqs_out"),
+ DEV_CLK(75, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(75, 2, "main_ospi_loopback_clk_sel_out0"),
+ DEV_CLK(75, 3, "board_0_ospi0_dqs_out"),
+ DEV_CLK(75, 4, "board_0_ospi0_lbclko_out"),
+ DEV_CLK(75, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(75, 7, "main_ospi_ref_clk_sel_out0"),
+ DEV_CLK(75, 8, "hsdiv4_16fft_main_0_hsdivout1_clk"),
+ DEV_CLK(75, 9, "postdiv1_16fft_main_1_hsdivout5_clk"),
+ DEV_CLK(77, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(102, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(102, 1, "board_0_i2c0_scl_out"),
+ DEV_CLK(102, 2, "hsdiv4_16fft_main_1_hsdivout0_clk"),
+ DEV_CLK(135, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+ DEV_CLK(146, 0, "main_usart0_fclk_sel_out0"),
+ DEV_CLK(146, 1, "usart_programmable_clock_divider_out0"),
+ DEV_CLK(146, 2, "hsdiv4_16fft_main_1_hsdivout1_clk"),
+ DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(157, 54, "clkout0_ctrl_out0"),
+ DEV_CLK(157, 55, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(157, 56, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(157, 62, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(157, 74, "mshsi2c_main_0_porscl"),
+ DEV_CLK(157, 135, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"),
+ DEV_CLK(157, 143, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
+ DEV_CLK(157, 145, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
+ DEV_CLK(157, 157, "fss_ul_main_0_ospi_0_ospi_oclk_clk"),
+ DEV_CLK(157, 159, "fss_ul_main_0_ospi_0_ospi_oclk_clk"),
+ DEV_CLK(157, 173, "sam62_pll_ctrl_wrap_main_0_sysclkout_clk"),
+ DEV_CLK(157, 174, "wkup_clkout_sel_io_out0"),
+ DEV_CLK(157, 175, "wkup_clkout_sel_out0"),
+ DEV_CLK(157, 176, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(157, 178, "dmtimer_dmc1ms_main_0_timer_pwm"),
+ DEV_CLK(161, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(161, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(161, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(161, 3, "main_usb0_refclk_sel_out0"),
+ DEV_CLK(161, 4, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(161, 5, "postdiv4_16ff_main_0_hsdivout8_clk"),
+ DEV_CLK(161, 10, "board_0_tck_out"),
+ DEV_CLK(166, 3, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+ DEV_CLK(166, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(169, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(169, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(170, 1, "hsdiv0_16fft_main_12_hsdivout0_clk"),
+ DEV_CLK(170, 2, "board_0_tck_out"),
+ DEV_CLK(170, 3, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+};
+
+const struct ti_k3_clk_platdata j722s_clk_platdata = {
+ .clk_list = clk_list,
+ .clk_list_cnt = ARRAY_SIZE(clk_list),
+ .soc_dev_clk_data = soc_dev_clk_data,
+ .soc_dev_clk_data_cnt = ARRAY_SIZE(soc_dev_clk_data),
+};
diff --git a/arch/arm/mach-k3/r5/j722s/dev-data.c b/arch/arm/mach-k3/r5/j722s/dev-data.c
new file mode 100644
index 0000000..59176c9
--- /dev/null
+++ b/arch/arm/mach-k3/r5/j722s/dev-data.c
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * J722S specific device platform data
+ *
+ * This file is auto generated. Please do not hand edit and report any issues
+ * to Bryan Brattlof <bb@ti.com>.
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include "k3-dev.h"
+
+static struct ti_psc soc_psc_list[] = {
+ [0] = PSC(0, 0x00400000),
+};
+
+static struct ti_pd soc_pd_list[] = {
+ [0] = PSC_PD(0, &soc_psc_list[0], NULL),
+ [1] = PSC_PD(3, &soc_psc_list[0], &soc_pd_list[0]),
+ [2] = PSC_PD(4, &soc_psc_list[0], &soc_pd_list[1]),
+ [3] = PSC_PD(13, &soc_psc_list[0], &soc_pd_list[0]),
+};
+
+static struct ti_lpsc soc_lpsc_list[] = {
+ [0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL),
+ [1] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[5]),
+ [2] = PSC_LPSC(13, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[5]),
+ [3] = PSC_LPSC(20, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
+ [4] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
+ [5] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
+ [6] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
+ [7] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
+ [8] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[7]),
+ [9] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[8]),
+ [10] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[7]),
+ [11] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[10]),
+ [12] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[11]),
+};
+
+static struct ti_dev soc_dev_list[] = {
+ PSC_DEV(16, &soc_lpsc_list[0]),
+ PSC_DEV(77, &soc_lpsc_list[0]),
+ PSC_DEV(61, &soc_lpsc_list[0]),
+ PSC_DEV(178, &soc_lpsc_list[1]),
+ PSC_DEV(179, &soc_lpsc_list[2]),
+ PSC_DEV(57, &soc_lpsc_list[3]),
+ PSC_DEV(58, &soc_lpsc_list[4]),
+ PSC_DEV(161, &soc_lpsc_list[5]),
+ PSC_DEV(75, &soc_lpsc_list[6]),
+ PSC_DEV(36, &soc_lpsc_list[7]),
+ PSC_DEV(102, &soc_lpsc_list[7]),
+ PSC_DEV(146, &soc_lpsc_list[7]),
+ PSC_DEV(166, &soc_lpsc_list[8]),
+ PSC_DEV(135, &soc_lpsc_list[9]),
+ PSC_DEV(170, &soc_lpsc_list[10]),
+ PSC_DEV(177, &soc_lpsc_list[11]),
+ PSC_DEV(55, &soc_lpsc_list[12]),
+};
+
+const struct ti_k3_pd_platdata j722s_pd_platdata = {
+ .psc = soc_psc_list,
+ .pd = soc_pd_list,
+ .lpsc = soc_lpsc_list,
+ .devs = soc_dev_list,
+ .num_psc = ARRAY_SIZE(soc_psc_list),
+ .num_pd = ARRAY_SIZE(soc_pd_list),
+ .num_lpsc = ARRAY_SIZE(soc_lpsc_list),
+ .num_devs = ARRAY_SIZE(soc_dev_list),
+};
diff --git a/arch/arm/mach-k3/r5/j784s4/Makefile b/arch/arm/mach-k3/r5/j784s4/Makefile
index 9ce8830..0fd6cab 100644
--- a/arch/arm/mach-k3/r5/j784s4/Makefile
+++ b/arch/arm/mach-k3/r5/j784s4/Makefile
@@ -5,3 +5,4 @@
obj-y += clk-data.o
obj-y += dev-data.o
+obj-y += j784s4_qos_uboot.o
diff --git a/arch/arm/mach-k3/r5/j784s4/clk-data.c b/arch/arm/mach-k3/r5/j784s4/clk-data.c
index feaa13e..793bcac 100644
--- a/arch/arm/mach-k3/r5/j784s4/clk-data.c
+++ b/arch/arm/mach-k3/r5/j784s4/clk-data.c
@@ -134,7 +134,7 @@
static const char * const mcu_clkout_mux_out0_parents[] = {
"hsdiv4_16fft_mcu_2_hsdivout0_clk",
- "hsdiv4_16fft_mcu_2_hsdivout0_clk",
+ "hsdiv4_16fft_mcu_2_hsdivout1_clk",
};
static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = {
@@ -338,7 +338,7 @@
DEV_CLK(149, 5, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(157, 174, "mcu_clkout_mux_out0"),
DEV_CLK(157, 175, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
- DEV_CLK(157, 176, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+ DEV_CLK(157, 176, "hsdiv4_16fft_mcu_2_hsdivout1_clk"),
DEV_CLK(157, 179, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"),
DEV_CLK(157, 180, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"),
DEV_CLK(157, 224, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
diff --git a/arch/arm/mach-k3/r5/j784s4/j784s4_qos.h b/arch/arm/mach-k3/r5/j784s4/j784s4_qos.h
new file mode 100644
index 0000000..5851f88
--- /dev/null
+++ b/arch/arm/mach-k3/r5/j784s4/j784s4_qos.h
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Keystone3 Quality of service endpoint definitions
+ * Auto generated by K3 Resource Partitioning Tool
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#define SMS_WKUP_0_TIFS_VBUSP_M 0x45D00000
+#define SMS_WKUP_0_HSM_VBUSP_M 0x45D00400
+#define PULSAR_SL_MCU_0_CPU0_RMST 0x45D10000
+#define PULSAR_SL_MCU_0_CPU0_WMST 0x45D10400
+#define PULSAR_SL_MCU_0_CPU0_PMST 0x45D10800
+#define PULSAR_SL_MCU_0_CPU1_RMST 0x45D11000
+#define PULSAR_SL_MCU_0_CPU1_WMST 0x45D11400
+#define PULSAR_SL_MCU_0_CPU1_PMST 0x45D11800
+#define SA3SS_AM62_MCU_0_CTXCACH_EXT_DMA 0x45D13000
+#define PULSAR_SL_MAIN_0_PBDG_RMST0 0x45D78000
+#define PULSAR_SL_MAIN_0_PBDG_WMST0 0x45D78400
+#define PULSAR_SL_MAIN_0_PBDG_RMST1 0x45D78800
+#define PULSAR_SL_MAIN_0_PBDG_WMST1 0x45D78C00
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD 0x45D82800
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR 0x45D82C00
+#define COMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_RD_VBUSM 0x45D86000
+#define COMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_WR_VBUSM 0x45D86400
+#define PCIE_G3X4_128_MAIN_0_PCIE_MST_RD 0x45D98400
+#define PCIE_G3X4_128_MAIN_0_PCIE_MST_WR 0x45D98C00
+#define PCIE_G3X4_128_MAIN_1_PCIE_MST_RD 0x45D99400
+#define PCIE_G3X4_128_MAIN_1_PCIE_MST_WR 0x45D99C00
+#define USB3P0SS_16FFC_MAIN_0_MSTR0 0x45D9A000
+#define USB3P0SS_16FFC_MAIN_0_MSTW0 0x45D9A400
+#define UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_RD 0x45D9AC00
+#define UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_WR 0x45D9B000
+#define EMMC8SS_16FFC_MAIN_0_EMMCSS_WR 0x45D9B400
+#define EMMC8SS_16FFC_MAIN_0_EMMCSS_RD 0x45D9B800
+#define SA2_UL_MAIN_0_CTXCACH_EXT_DMA 0x45D9BC00
+#define VUSR_DUAL_MAIN_0_V0_M 0x45D9C000
+#define VUSR_DUAL_MAIN_0_V1_M 0x45D9C400
+#define PCIE_G3X4_128_MAIN_2_PCIE_MST_RD 0x45D9CC00
+#define PCIE_G3X4_128_MAIN_3_PCIE_MST_WR 0x45D9D400
+#define PCIE_G3X4_128_MAIN_2_PCIE_MST_WR 0x45D9D800
+#define PCIE_G3X4_128_MAIN_3_PCIE_MST_RD 0x45D9DC00
+#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR 0x45DA0000
+#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW 0x45DA0400
+#define PULSAR_SL_MAIN_1_CPU0_RMST 0x45DA8000
+#define PULSAR_SL_MAIN_1_CPU0_WMST 0x45DA8400
+#define PULSAR_SL_MAIN_1_CPU1_RMST 0x45DA8800
+#define PULSAR_SL_MAIN_1_CPU1_WMST 0x45DA8C00
+#define PULSAR_SL_MAIN_2_CPU0_RMST 0x45DA9000
+#define PULSAR_SL_MAIN_2_CPU0_WMST 0x45DA9400
+#define PULSAR_SL_MAIN_2_CPU1_RMST 0x45DA9800
+#define PULSAR_SL_MAIN_2_CPU1_WMST 0x45DA9C00
+#define DMPAC_TOP_MAIN_0_DATA_MST 0x45DC0000
+#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_R_ASYNC 0x45DC0C00
+#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_W_ASYNC 0x45DC1000
+#define VPAC_TOP_MAIN_0_DATA_MST_0 0x45DC1400
+#define VPAC_TOP_MAIN_0_DATA_MST_1 0x45DC1800
+#define VPAC_TOP_MAIN_0_LDC0_M_MST 0x45DC1C00
+#define K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA 0x45DC2000
+#define K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC 0x45DC2400
+#define VPAC_TOP_MAIN_1_LDC0_M_MST 0x45DC2800
+#define VPAC_TOP_MAIN_1_DATA_MST_0 0x45DC2C00
+#define VPAC_TOP_MAIN_1_DATA_MST_1 0x45DC3000
+#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_R_ASYNC 0x45DC3400
+#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_W_ASYNC 0x45DC3800
+#define K3_VPU_WAVE521CL_MAIN_1_SEC_M_VBUSM_R_ASYNC 0x45DC3C00
+#define K3_VPU_WAVE521CL_MAIN_1_SEC_M_VBUSM_W_ASYNC 0x45DC4000
+#define K3_VPU_WAVE521CL_MAIN_1_PRI_M_VBUSM_R_ASYNC 0x45DC4400
+#define K3_VPU_WAVE521CL_MAIN_1_PRI_M_VBUSM_W_ASYNC 0x45DC4800
+#define J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC 0x45DC5000
+#define J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC 0x45DC5800
+#define PULSAR_SL_MAIN_0_CPU0_RMST 0x45DC8000
+#define PULSAR_SL_MAIN_0_CPU0_WMST 0x45DC8400
+#define PULSAR_SL_MAIN_0_CPU1_RMST 0x45DC8800
+#define PULSAR_SL_MAIN_0_CPU1_WMST 0x45DC8C00
+#define PULSAR_SL_MAIN_1_PBDG_RMST0 0x45DCA000
+#define PULSAR_SL_MAIN_1_PBDG_WMST0 0x45DCA400
+#define PULSAR_SL_MAIN_1_PBDG_RMST1 0x45DCA800
+#define PULSAR_SL_MAIN_1_PBDG_WMST1 0x45DCAC00
+#define PULSAR_SL_MAIN_2_PBDG_RMST0 0x45DCB000
+#define PULSAR_SL_MAIN_2_PBDG_WMST0 0x45DCB400
+#define PULSAR_SL_MAIN_2_PBDG_RMST1 0x45DCB800
+#define PULSAR_SL_MAIN_2_PBDG_WMST1 0x45DCBC00
diff --git a/arch/arm/mach-k3/r5/j784s4/j784s4_qos_uboot.c b/arch/arm/mach-k3/r5/j784s4/j784s4_qos_uboot.c
new file mode 100644
index 0000000..8c96da6
--- /dev/null
+++ b/arch/arm/mach-k3/r5/j784s4/j784s4_qos_uboot.c
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * j784s4 Quality of Service (QoS) Configuration Data
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <asm/arch/k3-qos.h>
+#include "j784s4_qos.h"
+
+struct k3_qos_data qos_data[] = {
+ /* DSS_PIPE_VID1 - 2 endpoints, 2 channels */
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 0),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 1),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 0),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 1),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+
+ /* DSS_PIPE_VIDL1 - 2 endpoints, 2 channels */
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 2),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 3),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 2),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 3),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+
+ /* DSS_PIPE_VID2 - 2 endpoints, 2 channels */
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 4),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 5),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 4),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 5),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+
+ /* DSS_PIPE_VIDL2 - 2 endpoints, 2 channels */
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 6),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 7),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 6),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 7),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+
+ /* Following registers set 1:1 mapping for orderID MAP1/MAP2
+ * remap registers. orderID x is remapped to orderID x again
+ * This is to ensure orderID from MAP register is unchanged
+ */
+
+ /* K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA - 1 groups */
+ {
+ .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 0),
+ .val = K3_QOS_GROUP_DEFAULT_VAL_LOW,
+ },
+ {
+ .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 1),
+ .val = K3_QOS_GROUP_DEFAULT_VAL_HIGH,
+ },
+
+ /* K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC - 1 groups */
+ {
+ .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 0),
+ .val = K3_QOS_GROUP_DEFAULT_VAL_LOW,
+ },
+ {
+ .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 1),
+ .val = K3_QOS_GROUP_DEFAULT_VAL_HIGH,
+ },
+};
+
+u32 qos_count = ARRAY_SIZE(qos_data);
diff --git a/arch/arm/mach-mediatek/mt7622/init.c b/arch/arm/mach-mediatek/mt7622/init.c
index 6e970ac..368f291 100644
--- a/arch/arm/mach-mediatek/mt7622/init.c
+++ b/arch/arm/mach-mediatek/mt7622/init.c
@@ -27,7 +27,7 @@
if (ret)
return ret;
- gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_2G);
+ gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_1G);
return 0;
}
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index f15d3cc..4a83287 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -37,6 +37,10 @@
default 0x6
range 0x0 0x7
+config ARMADA_38X_SUPPORT_OLD_DDR3_TRAINING
+ bool
+ depends on ARMADA_38X
+
config ARMADA_XP
bool
select ARMADA_32BIT
@@ -145,6 +149,7 @@
select SPL_SYS_MALLOC_SIMPLE
select SYS_I2C_MVTWSI
select ATSHA204A
+ select ARMADA_38X_SUPPORT_OLD_DDR3_TRAINING
config TARGET_TURRIS_MOX
bool "Support CZ.NIC's Turris Mox / RIPE Atlas Probe"
@@ -250,6 +255,16 @@
At level 3, rovides the windows margin of each DQ as a results of
DQS centeralization.
+config DDR_IMMUTABLE_DEBUG_SETTINGS
+ bool "Immutable DDR debug level (always DEBUG_LEVEL_ERROR)"
+ depends on ARMADA_38X
+ help
+ Makes the DDR training code debug level settings immutable.
+ The debug level setting from board topology definition is ignored.
+ The debug level is always set to DEBUG_LEVEL_ERROR and register
+ dumps are disabled.
+ This can save around 10 KiB of space in SPL binary.
+
config DDR_RESET_ON_TRAINING_FAILURE
bool "Reset the board on DDR training failure instead of hanging"
depends on ARMADA_38X || ARMADA_XP
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index e603ab9..8a145a5 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -36,7 +36,7 @@
};
/* SPI0 CS0 Flash of size MBUS_SPI_SIZE is mapped to address MBUS_SPI_BASE */
-#if CONFIG_ENV_SPI_BUS == 0 && CONFIG_ENV_SPI_CS == 0 && \
+#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && CONFIG_ENV_SPI_BUS == 0 && CONFIG_ENV_SPI_CS == 0 && \
CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE <= MBUS_SPI_SIZE
void *env_sf_get_env_addr(void)
{
diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h
index 904e715..af6ce29 100644
--- a/arch/arm/mach-mvebu/include/mach/cpu.h
+++ b/arch/arm/mach-mvebu/include/mach/cpu.h
@@ -174,6 +174,7 @@
* drivers/ddr/marvell
*/
int ddr3_init(void);
+int old_ddr3_init(void);
/* Auto Voltage Scaling */
#if defined(CONFIG_ARMADA_38X)
diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c
index 4f4f7e0..cbef411 100644
--- a/arch/arm/mach-mvebu/spl.c
+++ b/arch/arm/mach-mvebu/spl.c
@@ -313,6 +313,33 @@
hang();
}
+#if !defined(CONFIG_ARMADA_375)
+__weak bool board_use_old_ddr3_training(void)
+{
+ return false;
+}
+
+static void ddr3_init_or_fail(void)
+{
+ int ret;
+
+ if (IS_ENABLED(CONFIG_ARMADA_38X_SUPPORT_OLD_DDR3_TRAINING) &&
+ board_use_old_ddr3_training())
+ ret = old_ddr3_init();
+ else
+ ret = ddr3_init();
+
+ if (ret) {
+ printf("ddr3 init failed: %d\n", ret);
+ if (IS_ENABLED(CONFIG_DDR_RESET_ON_TRAINING_FAILURE) &&
+ get_boot_device() != BOOT_DEVICE_UART)
+ reset_cpu();
+ else
+ hang();
+ }
+}
+#endif
+
void board_init_f(ulong dummy)
{
int ret;
@@ -347,15 +374,7 @@
serdes_phy_config();
/* Setup DDR */
- ret = ddr3_init();
- if (ret) {
- printf("ddr3_init() failed: %d\n", ret);
- if (IS_ENABLED(CONFIG_DDR_RESET_ON_TRAINING_FAILURE) &&
- get_boot_device() != BOOT_DEVICE_UART)
- reset_cpu();
- else
- hang();
- }
+ ddr3_init_or_fail();
#endif
/* Initialize Auto Voltage Scaling */
diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c
index 78c1e96..84a60de 100644
--- a/arch/arm/mach-omap2/am33xx/board.c
+++ b/arch/arm/mach-omap2/am33xx/board.c
@@ -490,9 +490,6 @@
*/
save_omap_boot_params();
#endif
-#ifdef CONFIG_DEBUG_UART_OMAP
- debug_uart_init();
-#endif
#ifdef CONFIG_SPL_BUILD
spl_early_init();
@@ -533,3 +530,18 @@
return 0;
}
EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, am33xx_dm_post_init);
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+ if (u_boot_first_phase()) {
+ hw_data_init();
+ set_uart_mux_conf();
+ setup_early_clocks();
+ uart_soft_reset();
+
+ /* avoid uart gibberish by allowing the clocks to settle */
+ mdelay(50);
+ }
+}
+#endif
diff --git a/arch/arm/mach-omap2/u-boot-spl.lds b/arch/arm/mach-omap2/u-boot-spl.lds
index 1d6e5d4..3bb759d 100644
--- a/arch/arm/mach-omap2/u-boot-spl.lds
+++ b/arch/arm/mach-omap2/u-boot-spl.lds
@@ -39,12 +39,7 @@
. = ALIGN(4);
__image_copy_end = .;
-
- .end :
- {
- *(.__end)
- }
-
+ _end = .;
_image_binary_end = .;
.bss :
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index ec3697f..14b3ab1 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -3,6 +3,7 @@
config ROCKCHIP_PX30
bool "Support Rockchip PX30"
select ARM64
+ imply OF_UPSTREAM
select SUPPORT_SPL
select SUPPORT_TPL
select SPL
@@ -427,6 +428,7 @@
imply SPL_ROCKCHIP_COMMON_BOARD
imply SPL_SERIAL
imply SPL_SYSCON
+ imply OF_UPSTREAM
config ROCKCHIP_USB_UART
bool "Route uart output to usb pins"
diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig
index 23f8f43..dcf9eb8 100644
--- a/arch/arm/mach-rockchip/px30/Kconfig
+++ b/arch/arm/mach-rockchip/px30/Kconfig
@@ -68,8 +68,11 @@
config SYS_SOC
default "px30"
+config ROCKCHIP_COMMON_STACK_ADDR
+ default y
+
config SYS_MALLOC_F_LEN
- default 0x400
+ default 0x400 if !SPL_SHARES_INIT_SP_ADDR
config SPL_SERIAL
default y
@@ -83,6 +86,9 @@
config TPL_STACK
default 0xff0e4fff
+config TPL_SYS_MALLOC_F_LEN
+ default 0x600
+
config DEBUG_UART_CHANNEL
int "Mux channel to use for debug UART2/UART3"
depends on DEBUG_UART_BOARD_INIT
diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig b/arch/arm/mach-rockchip/rk3568/Kconfig
index af537d9..014ebf9 100644
--- a/arch/arm/mach-rockchip/rk3568/Kconfig
+++ b/arch/arm/mach-rockchip/rk3568/Kconfig
@@ -22,6 +22,11 @@
help
Hardkernel ODROID-M1 single board computer with a RK3568B2 SoC.
+config TARGET_POWKIDDY_X55_RK3566
+ bool "Powkiddy X55"
+ help
+ Powkiddy X55 handheld gaming console with an RK3566 SoC.
+
config TARGET_QUARTZ64_RK3566
bool "Pine64 Quartz64"
help
@@ -48,5 +53,6 @@
source "board/anbernic/rgxx3_rk3566/Kconfig"
source "board/hardkernel/odroid_m1/Kconfig"
source "board/pine64/quartz64_rk3566/Kconfig"
+source "board/powkiddy/x55/Kconfig"
endif
diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig
index 39049ab..9a35c7d 100644
--- a/arch/arm/mach-rockchip/rk3588/Kconfig
+++ b/arch/arm/mach-rockchip/rk3588/Kconfig
@@ -78,6 +78,15 @@
Power: 5.5*2.1mm DC Jack, 12VDC input
Dimensions: 110x80x1.6mm (without case) / 86x114.5x30mm (with case)
+config TARGET_NOVA_RK3588
+ bool "Indiedroid Nova RK3588"
+ select BOARD_LATE_INIT
+ help
+ Indiedroid Nova is a Rockchip RK3588s based SBC by Indiedroid.
+ It comes in configurations from 4GB of RAM to 16GB of RAM,
+ includes socket for eMMC storage, an SDMMC slot, and a 40-pin
+ GPIO header for expansion.
+
config TARGET_RK3588_NEU6
bool "Edgeble Neural Compute Module 6(Neu6) SoM"
select BOARD_LATE_INIT
@@ -152,6 +161,31 @@
USB PD over USB Type-C
Size: 100mm x 72mm (Pico-ITX form factor)
+config TARGET_SIGE7_RK3588
+ bool "ArmSoM Sige7 RK3588 board"
+ select BOARD_LATE_INIT
+ help
+ ArmSoM Sige7 is a Rockchip RK3588 based SBC (Single Board Computer)
+ by ArmSoM.
+
+ There are two variants depending on the DRAM size : 8G and 16G.
+
+ Specification:
+
+ Rockchip Rk3588 SoC
+ 4x ARM Cortex-A76, 4x ARM Cortex-A55
+ 8/16GB memory LPDDR4x
+ Mali G610MC4 GPU
+ 2x MIPI CSI 2 multiple lanes connector
+ 64GB/128GB on board eMMC
+ uSD slot
+ 1x USB 2.0 Type-A, 1x USB 3.0 Type-A, 1x USB 3.0 Type-C
+ 1x HDMI 2.1 output
+ 2x 2.5 Gbps Ethernet port
+ 40-pin IO header including UART, SPI and I2C
+ USB PD over USB Type-C
+ Size: 92mm x 62mm
+
config TARGET_QUARTZPRO64_RK3588
bool "Pine64 QuartzPro64 RK3588 board"
select BOARD_LATE_INIT
@@ -159,6 +193,36 @@
Pine64 QuartzPro64 is a Rockchip RK3588 based SBC (Single Board
Computer) by Pine64.
+config TARGET_TIGER_RK3588
+ bool "Theobroma Systems SOM-RK3588-Q7 (Tiger)"
+ select BOARD_LATE_INIT
+ help
+ The RK3588-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230
+ connector) system-on-module from Theobroma Systems, featuring the
+ Rockchip RK3588.
+
+ It provides the following feature set:
+ * up to 16GB LPDDR4x
+ * on-module eMMC
+ * SD card (on a baseboard) via edge connector
+ * Gigabit Ethernet with on-module GbE PHY
+ * HDMI/eDP
+ * MIPI-DSI
+ * 4x MIPI-CSI (3x on FPC connectors, 1x over Q7)
+ * HDMI input over FPC connector
+ * CAN
+ * USB
+ - 1x USB 3.0 dual-role (direct connection)
+ - 2x USB 3.0 host + 1x USB 2.0 host
+ * PCIe
+ - 1x PCIe 2.1 Gen3, 4 lanes
+ - 2xSATA / 2x PCIe 2.1 Gen1, 2 lanes
+ * on-module ATtiny816 companion controller, implementing:
+ - low-power RTC functionality (ISL1208 emulation)
+ - fan controller (AMC6821 emulation)
+ * on-module Secure Element with Global Platform 2.2.1 compliant
+ JavaCard environment
+
config TARGET_TURINGRK1_RK3588
bool "Turing Machines RK1 RK3588 board"
select BOARD_LATE_INIT
@@ -221,8 +285,10 @@
config TEXT_BASE
default 0x00a00000
+source "board/armsom/sige7-rk3588/Kconfig"
source "board/edgeble/neural-compute-module-6/Kconfig"
source "board/friendlyelec/nanopc-t6-rk3588/Kconfig"
+source "board/indiedroid/nova/Kconfig"
source "board/pine64/quartzpro64-rk3588/Kconfig"
source "board/turing/turing-rk1-rk3588/Kconfig"
source "board/radxa/rock5a-rk3588s/Kconfig"
@@ -230,5 +296,6 @@
source "board/rockchip/evb_rk3588/Kconfig"
source "board/rockchip/toybrick_rk3588/Kconfig"
source "board/theobroma-systems/jaguar_rk3588/Kconfig"
+source "board/theobroma-systems/tiger_rk3588/Kconfig"
endif
diff --git a/arch/arm/mach-rockchip/u-boot-tpl-v8.lds b/arch/arm/mach-rockchip/u-boot-tpl-v8.lds
index ad32654..958a1b7 100644
--- a/arch/arm/mach-rockchip/u-boot-tpl-v8.lds
+++ b/arch/arm/mach-rockchip/u-boot-tpl-v8.lds
@@ -46,12 +46,7 @@
. = ALIGN(8);
__image_copy_end = .;
-
- .end : {
- . = ALIGN(8);
- *(.__end)
- }
-
+ _end = .;
_image_binary_end = .;
.bss ALIGN(8) : {
diff --git a/arch/arm/mach-snapdragon/include/mach/gpio.h b/arch/arm/mach-snapdragon/include/mach/gpio.h
index 53c6ae0..cc8f405 100644
--- a/arch/arm/mach-snapdragon/include/mach/gpio.h
+++ b/arch/arm/mach-snapdragon/include/mach/gpio.h
@@ -10,11 +10,25 @@
#include <asm/types.h>
#include <stdbool.h>
+struct msm_special_pin_data {
+ char *name;
+
+ u32 ctl_reg;
+ u32 io_reg;
+
+ unsigned pull_bit:5;
+ unsigned drv_bit:5;
+
+ unsigned oe_bit:5;
+ unsigned in_bit:5;
+ unsigned out_bit:5;
+};
+
struct msm_pin_data {
int pin_count;
const unsigned int *pin_offsets;
- /* Index of first special pin, these are ignored for now */
unsigned int special_pins_start;
+ const struct msm_special_pin_data *special_pins_data;
};
static inline u32 qcom_pin_offset(const unsigned int *offs, unsigned int selector)
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
index b9af03d..d5934a9 100644
--- a/arch/arm/mach-stm32mp/Kconfig
+++ b/arch/arm/mach-stm32mp/Kconfig
@@ -155,4 +155,21 @@
source "arch/arm/mach-stm32mp/Kconfig.15x"
source "arch/arm/mach-stm32mp/Kconfig.25x"
source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig"
+
+config STM32MP15_PWR
+ bool "Enable driver for STM32MP15x PWR"
+ depends on DM_REGULATOR && DM_PMIC && (STM32MP13X || STM32MP15X)
+ default y if STM32MP15X
+ help
+ This config enables implementation of driver-model pmic and
+ regulator uclass features for access to STM32MP15x PWR.
+
+config SPL_STM32MP15_PWR
+ bool "Enable driver for STM32MP15x PWR in SPL"
+ depends on SPL && SPL_DM_REGULATOR && SPL_DM_PMIC && (STM32MP13X || STM32MP15X)
+ default y if STM32MP15X
+ help
+ This config enables implementation of driver-model pmic and
+ regulator uclass features for access to STM32MP15x PWR in SPL.
+
endif
diff --git a/arch/arm/mach-stm32mp/Kconfig.15x b/arch/arm/mach-stm32mp/Kconfig.15x
index 71c14eb..d99aa9f 100644
--- a/arch/arm/mach-stm32mp/Kconfig.15x
+++ b/arch/arm/mach-stm32mp/Kconfig.15x
@@ -77,22 +77,6 @@
endchoice
-config STM32MP15_PWR
- bool "Enable driver for STM32MP15x PWR"
- depends on DM_REGULATOR && DM_PMIC
- default y
- help
- This config enables implementation of driver-model pmic and
- regulator uclass features for access to STM32MP15x PWR.
-
-config SPL_STM32MP15_PWR
- bool "Enable driver for STM32MP15x PWR in SPL"
- depends on SPL && SPL_DM_REGULATOR && SPL_DM_PMIC
- default y
- help
- This config enables implementation of driver-model pmic and
- regulator uclass features for access to STM32MP15x PWR in SPL.
-
config TEXT_BASE
default 0xC0100000
diff --git a/arch/arm/mach-stm32mp/cmd_stm32key.c b/arch/arm/mach-stm32mp/cmd_stm32key.c
index 0cb3c7a..040a70f 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32key.c
+++ b/arch/arm/mach-stm32mp/cmd_stm32key.c
@@ -419,12 +419,12 @@
return CMD_RET_SUCCESS;
}
-static char stm32key_help_text[] =
+U_BOOT_LONGHELP(stm32key,
"list : list the supported key with description\n"
"stm32key select [<key>] : Select the key identified by <key> or display the key used for read/fuse command\n"
"stm32key read [<addr> | -a ] : Read the curent key at <addr> or current / all (-a) key in OTP\n"
"stm32key fuse [-y] <addr> : Fuse the current key at addr in OTP\n"
- "stm32key close [-y] : Close the device\n";
+ "stm32key close [-y] : Close the device\n");
U_BOOT_CMD_WITH_SUBCMDS(stm32key, "Manage key on STM32", stm32key_help_text,
U_BOOT_SUBCMD_MKENT(list, 1, 0, do_stm32key_list),
diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c
index 78b12fc..6024959 100644
--- a/arch/arm/mach-stm32mp/dram_init.c
+++ b/arch/arm/mach-stm32mp/dram_init.c
@@ -6,6 +6,7 @@
#define LOG_CATEGORY LOGC_ARCH
#include <dm.h>
+#include <efi_loader.h>
#include <image.h>
#include <init.h>
#include <lmb.h>
@@ -74,3 +75,14 @@
return reg + size;
}
+
+void efi_add_known_memory(void)
+{
+ if (IS_ENABLED(CONFIG_EFI_LOADER))
+ /*
+ * Memory over ram_top is reserved to OPTEE.
+ * Declare to EFI only memory area below ram_top
+ */
+ efi_add_memory_map(gd->ram_base, gd->ram_top - gd->ram_base,
+ EFI_CONVENTIONAL_MEMORY);
+}
diff --git a/arch/arm/mach-stm32mp/stm32mp1/psci.c b/arch/arm/mach-stm32mp/stm32mp1/psci.c
index 7772546..bfbf420 100644
--- a/arch/arm/mach-stm32mp/stm32mp1/psci.c
+++ b/arch/arm/mach-stm32mp/stm32mp1/psci.c
@@ -809,6 +809,27 @@
clrbits_le32(STM32_SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
/*
+ * Make sure the OS would not get any spurious IWDG pretimeout IRQ
+ * right after the system wakes up. This may happen in case the SoC
+ * got woken up by another source than the IWDG pretimeout and the
+ * pretimeout IRQ arrived immediately afterward, but too late to be
+ * handled by the main loop above. In case either of the IWDG is
+ * enabled, ping it first and then return to the OS.
+ */
+
+ /* Ping IWDG1 and ACK pretimer IRQ */
+ if (gic_enabled[4] & BIT(22)) {
+ writel(IWDG_KR_RELOAD_KEY, STM32_IWDG1_BASE + IWDG_KR);
+ writel(IWDG_EWCR_EWIC, STM32_IWDG1_BASE + IWDG_EWCR);
+ }
+
+ /* Ping IWDG2 and ACK pretimer IRQ */
+ if (gic_enabled[4] & BIT(23)) {
+ writel(IWDG_KR_RELOAD_KEY, STM32_IWDG2_BASE + IWDG_KR);
+ writel(IWDG_EWCR_EWIC, STM32_IWDG2_BASE + IWDG_EWCR);
+ }
+
+ /*
* The system has resumed successfully. Rewrite LR register stored
* on stack with 'ep' value, so that on return from this PSCI call,
* the code would jump to that 'ep' resume entry point code path
diff --git a/arch/arm/mach-stm32mp/stm32mp1/spl.c b/arch/arm/mach-stm32mp/stm32mp1/spl.c
index 7a8fd31..6eae5c2 100644
--- a/arch/arm/mach-stm32mp/stm32mp1/spl.c
+++ b/arch/arm/mach-stm32mp/stm32mp1/spl.c
@@ -118,7 +118,7 @@
node = ofnode_path("/reserved-memory/optee");
if (!ofnode_valid(node))
- return 0;
+ return -ENOENT;
fdt_start = ofnode_get_addr_size(node, "reg", &fdt_mem_size);
*start = fdt_start;
@@ -134,7 +134,7 @@
{
const uint32_t dram_size = stm32mp_get_dram_size();
const uintptr_t dram_top = STM32_DDR_BASE + (dram_size - 1);
- uint32_t optee_base, optee_size, tee_shmem_base;
+ u32 optee_base = 0, optee_size = 0, tee_shmem_base;
const uintptr_t tzc = STM32_TZC_BASE;
int ret;
diff --git a/arch/arm/mach-tegra/tegra20/Kconfig b/arch/arm/mach-tegra/tegra20/Kconfig
index 57d1102..6458827 100644
--- a/arch/arm/mach-tegra/tegra20/Kconfig
+++ b/arch/arm/mach-tegra/tegra20/Kconfig
@@ -47,6 +47,10 @@
bool "Avionic Design Tamonten Evaluation Carrier"
select BOARD_LATE_INIT
+config TARGET_TRANSFORMER_T20
+ bool "Asus Tegra20 Transformer board"
+ select BOARD_LATE_INIT
+
config TARGET_TRIMSLICE
bool "Compulab TrimSlice board"
select BOARD_LATE_INIT
@@ -72,6 +76,7 @@
source "board/avionic-design/plutux/Kconfig"
source "board/nvidia/seaboard/Kconfig"
source "board/avionic-design/tec/Kconfig"
+source "board/asus/transformer-t20/Kconfig"
source "board/compulab/trimslice/Kconfig"
source "board/nvidia/ventana/Kconfig"
source "board/toradex/colibri_t20/Kconfig"
diff --git a/arch/arm/mach-tegra/tegra20/bct.c b/arch/arm/mach-tegra/tegra20/bct.c
index e155b98..b647b6b 100644
--- a/arch/arm/mach-tegra/tegra20/bct.c
+++ b/arch/arm/mach-tegra/tegra20/bct.c
@@ -6,6 +6,7 @@
#include <command.h>
#include <log.h>
+#include <vsprintf.h>
#include <asm/arch-tegra/crypto.h>
#include "bct.h"
#include "uboot_aes.h"
diff --git a/arch/arm/mach-tegra/tegra30/Kconfig b/arch/arm/mach-tegra/tegra30/Kconfig
index 3e478b3..e0f054a 100644
--- a/arch/arm/mach-tegra/tegra30/Kconfig
+++ b/arch/arm/mach-tegra/tegra30/Kconfig
@@ -28,6 +28,18 @@
bool "Asus and Google Grouper board"
select BOARD_LATE_INIT
+config TARGET_IDEAPAD_YOGA_11
+ bool "Lenovo Ideapad Yoga 11 board"
+ select BOARD_LATE_INIT
+
+config TARGET_QC750
+ bool "Wexler QC750 board"
+ select BOARD_LATE_INIT
+
+config TARGET_SURFACE_RT
+ bool "Microsoft Tegra30 Surface RT board"
+ select BOARD_LATE_INIT
+
config TARGET_TEC_NG
bool "Avionic Design TEC-NG board"
select BOARD_LATE_INIT
@@ -51,6 +63,9 @@
source "board/toradex/colibri_t30/Kconfig"
source "board/htc/endeavoru/Kconfig"
source "board/asus/grouper/Kconfig"
+source "board/lenovo/ideapad-yoga-11/Kconfig"
+source "board/wexler/qc750/Kconfig"
+source "board/microsoft/surface-rt/Kconfig"
source "board/avionic-design/tec-ng/Kconfig"
source "board/asus/transformer-t30/Kconfig"
source "board/lg/x3-t30/Kconfig"
diff --git a/arch/arm/mach-versal2/Kconfig b/arch/arm/mach-versal2/Kconfig
new file mode 100644
index 0000000..3f18e33
--- /dev/null
+++ b/arch/arm/mach-versal2/Kconfig
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: GPL-2.0
+
+if ARCH_VERSAL2
+
+config SYS_BOARD
+ string "Board name"
+ default "versal2"
+
+config SYS_VENDOR
+ string "Vendor name"
+ default "amd"
+
+config SYS_SOC
+ default "versal2"
+
+config SYS_CONFIG_NAME
+ string "Board configuration name"
+ default "amd_versal2"
+ help
+ This option contains information about board configuration name.
+ Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
+ will be used for board configuration.
+
+config COUNTER_FREQUENCY
+ int "Timer clock frequency"
+ default 0
+ help
+ Setup time clock frequency for certain platform
+
+config IOU_SWITCH_DIVISOR0
+ hex "IOU switch divisor0"
+ default 0x20
+ help
+ Setup time clock divisor for input clock.
+
+config SYS_MEM_RSVD_FOR_MMU
+ bool "Reserve memory for MMU Table"
+ help
+ If defined this option is used to setup different space for
+ MMU table than the one which will be allocated during
+ relocation.
+
+config GICV3
+ def_bool y
+
+config SYS_MALLOC_LEN
+ default 0x2000000
+
+config ZYNQ_SDHCI_MAX_FREQ
+ default 200000000
+
+source "board/xilinx/Kconfig"
+source "board/amd/versal2/Kconfig"
+
+endif
diff --git a/arch/arm/mach-versal2/Makefile b/arch/arm/mach-versal2/Makefile
new file mode 100644
index 0000000..96497b1
--- /dev/null
+++ b/arch/arm/mach-versal2/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (C) 2021 - 2022, Xilinx, Inc.
+# Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc.
+#
+# Michal Simek <michal.simek@amd.com>
+#
+
+obj-y += clk.o
+obj-y += cpu.o
diff --git a/arch/arm/mach-versal2/clk.c b/arch/arm/mach-versal2/clk.c
new file mode 100644
index 0000000..e73ae9a
--- /dev/null
+++ b/arch/arm/mach-versal2/clk.c
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016 - 2022, Xilinx, Inc.
+ * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include <init.h>
+#include <time.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_CLOCKS
+/**
+ * set_cpu_clk_info - Initialize clock framework
+ *
+ * Return: 0 always.
+ *
+ * This function is called from common code after relocation and sets up the
+ * clock framework. The framework must not be used before this function had been
+ * called.
+ */
+int set_cpu_clk_info(void)
+{
+ gd->cpu_clk = get_tbclk();
+
+ gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
+ gd->bd->bi_dsp_freq = 0;
+
+ return 0;
+}
+#endif
diff --git a/arch/arm/mach-versal2/cpu.c b/arch/arm/mach-versal2/cpu.c
new file mode 100644
index 0000000..2dfcadb
--- /dev/null
+++ b/arch/arm/mach-versal2/cpu.c
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 - 2022, Xilinx, Inc.
+ * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include <init.h>
+#include <asm/armv8/mmu.h>
+#include <asm/cache.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/cache.h>
+#include <dm/platdata.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define VERSAL2_MEM_MAP_USED 5
+
+#define DRAM_BANKS CONFIG_NR_DRAM_BANKS
+
+/* +1 is end of list which needs to be empty */
+#define VERSAL2_MEM_MAP_MAX (VERSAL2_MEM_MAP_USED + DRAM_BANKS + 1)
+
+static struct mm_region versal2_mem_map[VERSAL2_MEM_MAP_MAX] = {
+ {
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = 0x70000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .virt = 0xf0000000UL,
+ .phys = 0xf0000000UL,
+ .size = 0x0fe00000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .virt = 0x400000000UL,
+ .phys = 0x400000000UL,
+ .size = 0x200000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .virt = 0x600000000UL,
+ .phys = 0x600000000UL,
+ .size = 0x800000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xe00000000UL,
+ .phys = 0xe00000000UL,
+ .size = 0xf200000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }
+};
+
+void mem_map_fill(void)
+{
+ int banks = VERSAL2_MEM_MAP_USED;
+
+ for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ /* Zero size means no more DDR that's this is end */
+ if (!gd->bd->bi_dram[i].size)
+ break;
+
+ versal2_mem_map[banks].virt = gd->bd->bi_dram[i].start;
+ versal2_mem_map[banks].phys = gd->bd->bi_dram[i].start;
+ versal2_mem_map[banks].size = gd->bd->bi_dram[i].size;
+ versal2_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE;
+ banks = banks + 1;
+ }
+}
+
+struct mm_region *mem_map = versal2_mem_map;
+
+u64 get_page_table_size(void)
+{
+ return 0x14000;
+}
+
+U_BOOT_DRVINFO(soc_amd_versal2) = {
+ .name = "soc_amd_versal2",
+};
diff --git a/arch/arm/mach-versal2/include/mach/hardware.h b/arch/arm/mach-versal2/include/mach/hardware.h
new file mode 100644
index 0000000..42e3061
--- /dev/null
+++ b/arch/arm/mach-versal2/include/mach/hardware.h
@@ -0,0 +1,97 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 - 2022, Xilinx, Inc.
+ * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc.
+ */
+
+#ifndef __ASSEMBLY__
+#include <linux/bitops.h>
+#endif
+
+struct crlapb_regs {
+ u32 reserved0[67];
+ u32 cpu_r5_ctrl;
+ u32 reserved;
+ u32 iou_switch_ctrl; /* 0x114 */
+ u32 reserved1[13];
+ u32 timestamp_ref_ctrl; /* 0x14c */
+ u32 reserved3[108];
+ u32 rst_cpu_r5;
+ u32 reserved2[17];
+ u32 rst_timestamp; /* 0x348 */
+};
+
+struct iou_scntrs_regs {
+ u32 counter_control_register; /* 0x0 */
+ u32 reserved0[7];
+ u32 base_frequency_id_register; /* 0x20 */
+};
+
+struct crp_regs {
+ u32 reserved0[128];
+ u32 boot_mode_usr; /* 0x200 */
+};
+
+#define VERSAL2_CRL_APB_BASEADDR 0xEB5E0000
+#define VERSAL2_CRP_BASEADDR 0xF1260000
+#define VERSAL2_IOU_SCNTR_SECURE 0xEC920000
+
+#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT BIT(25)
+#define IOU_SWITCH_CTRL_CLKACT_BIT BIT(25)
+#define IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8
+#define IOU_SCNTRS_CONTROL_EN 1
+
+#define crlapb_base ((struct crlapb_regs *)VERSAL2_CRL_APB_BASEADDR)
+#define crp_base ((struct crp_regs *)VERSAL2_CRP_BASEADDR)
+#define iou_scntr_secure ((struct iou_scntrs_regs *)VERSAL2_IOU_SCNTR_SECURE)
+
+#define PMC_TAP 0xF11A0000
+
+#define PMC_TAP_IDCODE (PMC_TAP + 0)
+#define PMC_TAP_VERSION (PMC_TAP + 0x4)
+# define PMC_VERSION_MASK GENMASK(7, 0)
+# define PS_VERSION_MASK GENMASK(15, 8)
+# define PS_VERSION_PRODUCTION 0x20
+# define RTL_VERSION_MASK GENMASK(23, 16)
+# define PLATFORM_MASK GENMASK(27, 24)
+# define PLATFORM_VERSION_MASK GENMASK(31, 28)
+#define PMC_TAP_USERCODE (PMC_TAP + 0x8)
+
+/* Bootmode setting values */
+#define BOOT_MODES_MASK 0x0000000F
+#define QSPI_MODE_24BIT 0x00000001
+#define QSPI_MODE_32BIT 0x00000002
+#define SD_MODE 0x00000003 /* sd 0 */
+#define SD_MODE1 0x00000005 /* sd 1 */
+#define EMMC_MODE 0x00000006
+#define USB_MODE 0x00000007
+#define OSPI_MODE 0x00000008
+#define SELECTMAP_MODE 0x0000000A
+#define SD1_LSHFT_MODE 0x0000000E /* SD1 Level shifter */
+#define JTAG_MODE 0x00000000
+#define BOOT_MODE_USE_ALT 0x100
+#define BOOT_MODE_ALT_SHIFT 12
+
+enum versal2_platform {
+ VERSAL2_SILICON = 0,
+ VERSAL2_SPP = 1,
+ VERSAL2_EMU = 2,
+ VERSAL2_QEMU = 3,
+ VERSAL2_SPP_MMD = 5,
+ VERSAL2_EMU_MMD = 6,
+};
+
+#define VERSAL2_SLCR_BASEADDR 0xF1060000
+#define VERSAL_AXI_MUX_SEL (VERSAL2_SLCR_BASEADDR + 0x504)
+#define VERSAL_OSPI_LINEAR_MODE BIT(1)
+
+#define FLASH_RESET_GPIO 0xc
+#define WPROT_CRP 0xF126001C
+#define RST_GPIO 0xF1260318
+#define WPROT_LPD_MIO 0xFF080728
+#define WPROT_PMC_MIO 0xF1060828
+#define BOOT_MODE_DIR 0xF1020204
+#define BOOT_MODE_OUT 0xF1020208
+#define MIO_PIN_12 0xF1060030
+#define BANK0_OUTPUT 0xF1020040
+#define BANK0_TRI 0xF1060200
diff --git a/arch/arm/mach-versal2/include/mach/sys_proto.h b/arch/arm/mach-versal2/include/mach/sys_proto.h
new file mode 100644
index 0000000..7b1726a
--- /dev/null
+++ b/arch/arm/mach-versal2/include/mach/sys_proto.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 - 2022, Xilinx, Inc.
+ * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc.
+ */
+
+#include <linux/build_bug.h>
+
+void mem_map_fill(void);
diff --git a/arch/arm/mach-zynq/spl.c b/arch/arm/mach-zynq/spl.c
index 8ef12ed..dc964dc 100644
--- a/arch/arm/mach-zynq/spl.c
+++ b/arch/arm/mach-zynq/spl.c
@@ -31,8 +31,8 @@
arch_cpu_init();
}
-#ifdef CONFIG_SPL_BOARD_INIT
-void spl_board_init(void)
+#ifdef CONFIG_SPL_SOC_INIT
+void spl_soc_init(void)
{
preloader_console_init();
#if defined(CONFIG_ARCH_EARLY_INIT_R) && defined(CONFIG_SPL_FPGA)
diff --git a/arch/arm/mach-zynq/u-boot.lds b/arch/arm/mach-zynq/u-boot.lds
index 3e0c96c..f52523e 100644
--- a/arch/arm/mach-zynq/u-boot.lds
+++ b/arch/arm/mach-zynq/u-boot.lds
@@ -68,11 +68,7 @@
__rel_dyn_end = .;
}
- .end :
- {
- *(.__end)
- }
-
+ _end = .;
_image_binary_end = .;
/*
diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig
index 0d2238a..aea1362 100644
--- a/arch/arm/mach-zynqmp/Kconfig
+++ b/arch/arm/mach-zynqmp/Kconfig
@@ -189,7 +189,18 @@
endchoice
+config CMD_ZYNQMP
+ bool "Enable ZynqMP specific commands"
+ depends on ZYNQMP_FIRMWARE
+ default y
+ help
+ Enable ZynqMP specific commands like "zynqmp secure"
+ which is used for zynqmp secure image verification.
+ The secure image is a xilinx specific BOOT.BIN with
+ either authentication or encryption or both encryption
+ and authentication feature enabled while generating
+ BOOT.BIN using Xilinx bootgen tool.
+
source "board/xilinx/Kconfig"
-source "board/xilinx/zynqmp/Kconfig"
endif
diff --git a/arch/arm/mach-zynqmp/Makefile b/arch/arm/mach-zynqmp/Makefile
index 8f897a3..38be162 100644
--- a/arch/arm/mach-zynqmp/Makefile
+++ b/arch/arm/mach-zynqmp/Makefile
@@ -8,3 +8,7 @@
obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o psu_spl_init.o
obj-$(CONFIG_SPL_ZYNQMP_DRAM_ECC_INIT) += ecc_spl_init.o
obj-$(CONFIG_$(SPL_)ZYNQMP_PSU_INIT_ENABLED) += psu_spl_init.o
+
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_CMD_ZYNQMP) += zynqmp.o
+endif # !CONFIG_SPL_BUILD
diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c
index 6b67245..4a2d240 100644
--- a/arch/arm/mach-zynqmp/spl.c
+++ b/arch/arm/mach-zynqmp/spl.c
@@ -56,8 +56,8 @@
# define MODE_RESET PS_MODE1
#endif
-#ifdef CONFIG_SPL_BOARD_INIT
-void spl_board_init(void)
+#ifdef CONFIG_SPL_SOC_INIT
+void spl_soc_init(void)
{
preloader_console_init();
ps_mode_reset(MODE_RESET);
diff --git a/board/xilinx/zynqmp/cmds.c b/arch/arm/mach-zynqmp/zynqmp.c
similarity index 100%
rename from board/xilinx/zynqmp/cmds.c
rename to arch/arm/mach-zynqmp/zynqmp.c
diff --git a/arch/m68k/cpu/mcf52x2/cpu.c b/arch/m68k/cpu/mcf52x2/cpu.c
index 6bfde5e..d0a0a45 100644
--- a/arch/m68k/cpu/mcf52x2/cpu.c
+++ b/arch/m68k/cpu/mcf52x2/cpu.c
@@ -108,26 +108,6 @@
return 0;
};
-#if defined(CONFIG_WATCHDOG)
-void watchdog_reset(void)
-{
- mbar_writeShort(MCF_WTM_WSR, 0x5555);
- mbar_writeShort(MCF_WTM_WSR, 0xAAAA);
-}
-
-int watchdog_disable(void)
-{
- mbar_writeShort(MCF_WTM_WCR, 0);
- return (0);
-}
-
-int watchdog_init(void)
-{
- mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN);
- return (0);
-}
-#endif /* #ifdef CONFIG_WATCHDOG */
-
#endif
#ifdef CONFIG_M5272
@@ -174,49 +154,6 @@
};
#endif /* CONFIG_DISPLAY_CPUINFO */
-#if defined(CONFIG_WATCHDOG)
-/* Called by macro WATCHDOG_RESET */
-void watchdog_reset(void)
-{
- wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
-
- out_be16(&wdt->wdog_wcr, 0);
-}
-
-int watchdog_disable(void)
-{
- wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
-
- /* reset watchdog counter */
- out_be16(&wdt->wdog_wcr, 0);
- /* disable watchdog interrupt */
- out_be16(&wdt->wdog_wirr, 0);
- /* disable watchdog timer */
- out_be16(&wdt->wdog_wrrr, 0);
-
- puts("WATCHDOG:disabled\n");
- return (0);
-}
-
-int watchdog_init(void)
-{
- wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
-
- /* disable watchdog interrupt */
- out_be16(&wdt->wdog_wirr, 0);
-
- /* set timeout and enable watchdog */
- out_be16(&wdt->wdog_wrrr,
- (CONFIG_WATCHDOG_TIMEOUT_MSECS * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
-
- /* reset watchdog counter */
- out_be16(&wdt->wdog_wcr, 0);
-
- puts("WATCHDOG:enabled\n");
- return (0);
-}
-#endif /* #ifdef CONFIG_WATCHDOG */
-
#endif /* #ifdef CONFIG_M5272 */
#ifdef CONFIG_M5275
@@ -243,51 +180,6 @@
};
#endif /* CONFIG_DISPLAY_CPUINFO */
-#if defined(CONFIG_WATCHDOG)
-/* Called by macro WATCHDOG_RESET */
-void watchdog_reset(void)
-{
- wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
-
- out_be16(&wdt->wsr, 0x5555);
- out_be16(&wdt->wsr, 0xaaaa);
-}
-
-int watchdog_disable(void)
-{
- wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
-
- /* reset watchdog counter */
- out_be16(&wdt->wsr, 0x5555);
- out_be16(&wdt->wsr, 0xaaaa);
-
- /* disable watchdog timer */
- out_be16(&wdt->wcr, 0);
-
- puts("WATCHDOG:disabled\n");
- return (0);
-}
-
-int watchdog_init(void)
-{
- wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
-
- /* disable watchdog */
- out_be16(&wdt->wcr, 0);
-
- /* set timeout and enable watchdog */
- out_be16(&wdt->wmr,
- (CONFIG_WATCHDOG_TIMEOUT_MSECS * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
-
- /* reset watchdog counter */
- out_be16(&wdt->wsr, 0x5555);
- out_be16(&wdt->wsr, 0xaaaa);
-
- puts("WATCHDOG:enabled\n");
- return (0);
-}
-#endif /* #ifdef CONFIG_WATCHDOG */
-
#endif /* #ifdef CONFIG_M5275 */
#ifdef CONFIG_M5282
diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h
index 6ef7f7b..aa8d2ed 100644
--- a/arch/m68k/include/asm/cache.h
+++ b/arch/m68k/include/asm/cache.h
@@ -185,7 +185,6 @@
#ifndef __ASSEMBLY__ /* put C only stuff in this section */
-void icache_invalid(void);
void dcache_invalid(void);
#endif
diff --git a/arch/m68k/lib/cache.c b/arch/m68k/lib/cache.c
index de04124..370ad40 100644
--- a/arch/m68k/lib/cache.c
+++ b/arch/m68k/lib/cache.c
@@ -29,7 +29,7 @@
void icache_enable(void)
{
- icache_invalid();
+ invalidate_icache_all();
*cf_icache_status = 1;
@@ -53,7 +53,7 @@
u32 temp = 0;
*cf_icache_status = 0;
- icache_invalid();
+ invalidate_icache_all();
#if defined(CONFIG_CF_V4) || defined(CFG_CF_V4E)
__asm__ __volatile__("movec %0, %%acr2"::"r"(temp));
@@ -68,7 +68,7 @@
#endif
}
-void icache_invalid(void)
+void invalidate_icache_all(void)
{
u32 temp;
@@ -134,6 +134,15 @@
#endif
}
+/*
+ * Default implementation:
+ * do a range flush for the entire range
+ */
+__weak void flush_dcache_all(void)
+{
+ flush_dcache_range(0, ~0);
+}
+
__weak void invalidate_dcache_range(unsigned long start, unsigned long stop)
{
/* An empty stub, real implementation should be in platform code */
diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c
index e0be938..3c8cbd4 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu.c
@@ -164,21 +164,6 @@
}
#endif
-#if defined(CONFIG_WATCHDOG) && !defined(CONFIG_WDT)
-void watchdog_reset (void)
-{
- int re_enable = disable_interrupts();
-
- /* Reset the 83xx watchdog */
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- immr->wdt.swsrr = 0x556c;
- immr->wdt.swsrr = 0xaa39;
-
- if (re_enable)
- enable_interrupts();
-}
-#endif
-
/*
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 6356b02..ebce2fe 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -349,37 +349,6 @@
}
-#ifndef CONFIG_WDT
-#if defined(CONFIG_WATCHDOG)
-#define WATCHDOG_MASK (TCR_WP(63) | TCR_WRC(3) | TCR_WIE)
-void
-init_85xx_watchdog(void)
-{
- mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WATCHDOG_MASK) |
- TCR_WP(CFG_WATCHDOG_PRESC) | TCR_WRC(CFG_WATCHDOG_RC));
-}
-
-void
-reset_85xx_watchdog(void)
-{
- /*
- * Clear TSR(WIS) bit by writing 1
- */
- mtspr(SPRN_TSR, TSR_WIS);
-}
-
-void
-watchdog_reset(void)
-{
- int re_enable = disable_interrupts();
-
- reset_85xx_watchdog();
- if (re_enable)
- enable_interrupts();
-}
-#endif /* CONFIG_WATCHDOG */
-#endif
-
/*
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()
diff --git a/arch/powerpc/lib/cache.c b/arch/powerpc/lib/cache.c
index e480b26..a9cd7b8 100644
--- a/arch/powerpc/lib/cache.c
+++ b/arch/powerpc/lib/cache.c
@@ -5,6 +5,7 @@
*/
#include <cpu_func.h>
+#include <stdio.h>
#include <asm/cache.h>
#include <watchdog.h>
@@ -43,3 +44,17 @@
/* flush prefetch queue */
asm volatile("isync" : : : "memory");
}
+
+/*
+ * Default implementation:
+ * do a range flush for the entire range
+ */
+void flush_dcache_all(void)
+{
+ flush_dcache_range(0, ~0);
+}
+
+void invalidate_icache_all(void)
+{
+ puts("No arch specific invalidate_icache_all available!\n");
+}
diff --git a/arch/riscv/cpu/andes/cache.c b/arch/riscv/cpu/andes/cache.c
index 7d3df87..bb57498 100644
--- a/arch/riscv/cpu/andes/cache.c
+++ b/arch/riscv/cpu/andes/cache.c
@@ -43,9 +43,7 @@
void flush_dcache_all(void)
{
-#if CONFIG_IS_ENABLED(RISCV_MMODE)
- csr_write(CSR_MCCTLCOMMAND, CCTL_L1D_WBINVAL_ALL);
-#endif
+ csr_write(CSR_UCCTLCOMMAND, CCTL_L1D_WBINVAL_ALL);
}
void flush_dcache_range(unsigned long start, unsigned long end)
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index a9e1935..8e58f64 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -210,10 +210,6 @@
bnez s2, secondary_hart_loop
#endif
- /* Enable cache */
- jal icache_enable
- jal dcache_enable
-
#ifdef CONFIG_DEBUG_UART
jal debug_uart_init
#endif
diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h
index 028fd01..7d6104a 100644
--- a/arch/riscv/include/asm/arch-andes/csr.h
+++ b/arch/riscv/include/asm/arch-andes/csr.h
@@ -12,7 +12,7 @@
#define CSR_MCACHE_CTL 0x7ca
#define CSR_MMISC_CTL 0x7d0
-#define CSR_MCCTLCOMMAND 0x7cc
+#define CSR_UCCTLCOMMAND 0x80c
/* mcache_ctl register */
diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c
index 154a5d7..d7869b2e 100644
--- a/arch/sandbox/cpu/os.c
+++ b/arch/sandbox/cpu/os.c
@@ -109,7 +109,7 @@
*/
flags |= O_CLOEXEC;
- return open(pathname, flags, 0777);
+ return open(pathname, flags, 0644);
}
int os_close(int fd)
@@ -746,7 +746,7 @@
struct sandbox_state *state = state_get_current();
int fd, ret;
- fd = open(fname, O_CREAT | O_WRONLY, 0777);
+ fd = open(fname, O_CREAT | O_WRONLY, 0644);
if (fd < 0)
return -ENOENT;
ret = write(fd, state->ram_buf, state->ram_size);
@@ -791,7 +791,7 @@
if (write(fd, data, size) < 0)
return -EIO;
close(fd);
- if (chmod(fname, 0777))
+ if (chmod(fname, 0755))
return -ENOEXEC;
return 0;
diff --git a/arch/sandbox/cpu/u-boot.lds b/arch/sandbox/cpu/u-boot.lds
index 52f13af..6ee8095 100644
--- a/arch/sandbox/cpu/u-boot.lds
+++ b/arch/sandbox/cpu/u-boot.lds
@@ -19,30 +19,18 @@
*(_u_boot_sandbox_getopt_end)
}
- efi_runtime_start : {
- *(___efi_runtime_start)
- }
-
efi_runtime : {
+ __efi_runtime_start = .;
*(efi_runtime_text)
*(efi_runtime_data)
- }
-
- efi_runtime_stop : {
- *(___efi_runtime_stop)
+ __efi_runtime_stop = .;
}
- efi_runtime_rel_start : {
- *(___efi_runtime_rel_start)
- }
-
efi_runtime_rel : {
+ __efi_runtime_rel_start = .;
*(.relefi_runtime_text)
*(.relefi_runtime_data)
- }
-
- efi_runtime_rel_stop : {
- *(___efi_runtime_rel_stop)
+ __efi_runtime_rel_stop = .;
}
.dynsym :
diff --git a/arch/sandbox/lib/Makefile b/arch/sandbox/lib/Makefile
index a2bc5a7..d7d15a5 100644
--- a/arch/sandbox/lib/Makefile
+++ b/arch/sandbox/lib/Makefile
@@ -5,7 +5,7 @@
# (C) Copyright 2002-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-obj-y += fdt_fixup.o interrupts.o sections.o
+obj-y += fdt_fixup.o interrupts.o
obj-$(CONFIG_PCI) += pci_io.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-$(CONFIG_CMD_BOOTZ) += bootm.o
diff --git a/arch/sandbox/lib/sections.c b/arch/sandbox/lib/sections.c
deleted file mode 100644
index 2f2f3fb..0000000
--- a/arch/sandbox/lib/sections.c
+++ /dev/null
@@ -1,13 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
- *
- */
-#include <linux/compiler.h>
-
-char __efi_runtime_start[0] __section("___efi_runtime_start");
-char __efi_runtime_stop[0] __section("___efi_runtime_stop");
-char __efi_runtime_rel_start[0]
- __section("___efi_runtime_rel_start");
-char __efi_runtime_rel_stop[0]
- __section("___efi_runtime_rel_stop");
diff --git a/arch/sh/cpu/sh4/Makefile b/arch/sh/cpu/sh4/Makefile
index 7403a2c..6d7e05e 100644
--- a/arch/sh/cpu/sh4/Makefile
+++ b/arch/sh/cpu/sh4/Makefile
@@ -6,4 +6,4 @@
# (C) Copyright 2007
# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-obj-y = cpu.o interrupts.o watchdog.o cache.o
+obj-y = cpu.o interrupts.o cache.o
diff --git a/arch/sh/cpu/sh4/cache.c b/arch/sh/cpu/sh4/cache.c
index 8c18399..d3c480e 100644
--- a/arch/sh/cpu/sh4/cache.c
+++ b/arch/sh/cpu/sh4/cache.c
@@ -6,6 +6,7 @@
#include <command.h>
#include <cpu_func.h>
+#include <stdio.h>
#include <asm/cache.h>
#include <asm/io.h>
#include <asm/processor.h>
@@ -65,6 +66,15 @@
}
}
+/*
+ * Default implementation:
+ * do a range flush for the entire range
+ */
+void flush_dcache_all(void)
+{
+ flush_dcache_range(0, ~0);
+}
+
void invalidate_dcache_range(unsigned long start, unsigned long end)
{
u32 v;
@@ -91,6 +101,11 @@
cache_control(CACHE_DISABLE);
}
+void invalidate_icache_all(void)
+{
+ puts("No arch specific invalidate_icache_all available!\n");
+}
+
int icache_status(void)
{
return 0;
diff --git a/arch/sh/cpu/sh4/cpu.c b/arch/sh/cpu/sh4/cpu.c
index b0ad685..47a8549 100644
--- a/arch/sh/cpu/sh4/cpu.c
+++ b/arch/sh/cpu/sh4/cpu.c
@@ -10,6 +10,16 @@
#include <net.h>
#include <netdev.h>
#include <asm/processor.h>
+#include <asm/system.h>
+
+void reset_cpu(void)
+{
+ /* Address error with SR.BL=1 first. */
+ trigger_address_error();
+
+ while (1)
+ ;
+}
int checkcpu(void)
{
diff --git a/arch/sh/cpu/sh4/watchdog.c b/arch/sh/cpu/sh4/watchdog.c
deleted file mode 100644
index c597433..0000000
--- a/arch/sh/cpu/sh4/watchdog.c
+++ /dev/null
@@ -1,60 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-
-#include <cpu_func.h>
-#include <asm/processor.h>
-#include <asm/system.h>
-#include <asm/io.h>
-
-#define WDT_BASE WTCNT
-
-#define WDT_WD (1 << 6)
-#define WDT_RST_P (0)
-#define WDT_RST_M (1 << 5)
-#define WDT_ENABLE (1 << 7)
-
-#if defined(CONFIG_WATCHDOG)
-static unsigned char csr_read(void)
-{
- return inb(WDT_BASE + 0x04);
-}
-
-static void cnt_write(unsigned char value)
-{
- outl((unsigned short)value | 0x5A00, WDT_BASE + 0x00);
-}
-
-static void csr_write(unsigned char value)
-{
- outl((unsigned short)value | 0xA500, WDT_BASE + 0x04);
-}
-
-void watchdog_reset(void)
-{
- outl(0x55000000, WDT_BASE + 0x08);
-}
-
-int watchdog_init(void)
-{
- /* Set overflow time*/
- cnt_write(0);
- /* Power on reset */
- csr_write(WDT_WD|WDT_RST_P|WDT_ENABLE);
-
- return 0;
-}
-
-int watchdog_disable(void)
-{
- csr_write(csr_read() & ~WDT_ENABLE);
- return 0;
-}
-#endif
-
-void reset_cpu(void)
-{
- /* Address error with SR.BL=1 first. */
- trigger_address_error();
-
- while (1)
- ;
-}
diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index e0de331..fdd2897 100644
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@@ -24,9 +24,11 @@
#ifdef CONFIG_HAVE_INTEL_ME
intel-descriptor {
filename = CONFIG_FLASH_DESCRIPTOR_FILE;
+ assume-size = <0x1000>;
};
intel-me {
filename = CONFIG_INTEL_ME_FILE;
+ assume-size = <0x1ff000>;
};
#endif
#ifdef CONFIG_TPL
@@ -87,6 +89,7 @@
#ifdef CONFIG_HAVE_MRC
intel-mrc {
offset = <CFG_X86_MRC_ADDR>;
+ assume-size = <0x2fc94>;
};
#endif
#ifdef CONFIG_FSP_VERSION1
@@ -98,6 +101,7 @@
#ifdef CONFIG_FSP_VERSION2
intel-descriptor {
filename = CONFIG_FLASH_DESCRIPTOR_FILE;
+ assume-size = <4096>;
};
intel-ifwi {
filename = CONFIG_IFWI_INPUT_FILE;
@@ -139,6 +143,7 @@
intel-vga {
filename = CONFIG_VGA_BIOS_FILE;
offset = <CONFIG_VGA_BIOS_ADDR>;
+ assume-size = <0x10000>;
};
#endif
#ifdef CONFIG_HAVE_VBT
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index a42a7e6..e38ce19 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -478,7 +478,6 @@
/* Fill out header fields. */
acpi_fill_header(header, "HPET");
- header->creator_revision = ASL_REVISION;
header->length = sizeof(struct acpi_hpet);
header->revision = acpi_get_table_revision(ACPITAB_HPET);
@@ -569,7 +568,6 @@
memcpy(header->oem_id, OEM_ID, 6);
memcpy(header->oem_table_id, OEM_TABLE_ID, 8);
memcpy(header->creator_id, ASLC_ID, 4);
- header->creator_revision = 1;
fadt->x_firmware_ctrl = map_to_sysmem(facs);
fadt->x_dsdt = map_to_sysmem(dsdt);
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index 8f668cc..70eebb4 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -15,6 +15,10 @@
bool "Support XTFPGA"
select BOARD_POSTCLK_INIT
+config TARGET_QEMU_XTENSA
+ bool "Support QEMU Xtensa Virt Board"
+ select BOARD_LATE_INIT
+
endchoice
config SYS_ICACHE_OFF
@@ -41,6 +45,34 @@
help
Do not enable data cache in SPL.
+config XTENSA_SEMIHOSTING
+ bool "Support semihosting"
+ help
+ Enable Xtensa semihosting debugging support.
+
+choice
+ prompt "Semihosting interface"
+ default XTENSA_SIMCALL_ISS
+ depends on XTENSA_SEMIHOSTING
+ help
+ Choose semihosting interface that will be used for serial port,
+ block device and networking.
+
+config XTENSA_SIMCALL_ISS
+ bool "simcall"
+ help
+ Use simcall instruction. simcall is only available on simulators,
+ it does nothing on hardware.
+
+config XTENSA_SIMCALL_GDBIO
+ bool "GDBIO"
+ help
+ Use break instruction. It is available on real hardware when GDB
+ is attached to it via JTAG.
+
+endchoice
+
source "board/cadence/xtfpga/Kconfig"
+source "board/emulation/qemu-xtensa/Kconfig"
endmenu
diff --git a/arch/xtensa/config.mk b/arch/xtensa/config.mk
index b080999..200b66f 100644
--- a/arch/xtensa/config.mk
+++ b/arch/xtensa/config.mk
@@ -7,3 +7,9 @@
-ffunction-sections -fdata-sections
LDFLAGS_FINAL += --gc-sections
+
+ifeq ($(CONFIG_SYS_BIG_ENDIAN),y)
+PLATFORM_CPPFLAGS += -B xtensa -O elf32-xtensa-be
+else
+PLATFORM_ELFFLAGS += -B xtensa -O elf32-xtensa-le
+endif
diff --git a/arch/xtensa/cpu/cpu.c b/arch/xtensa/cpu/cpu.c
index abcd8f7..d226681 100644
--- a/arch/xtensa/cpu/cpu.c
+++ b/arch/xtensa/cpu/cpu.c
@@ -48,8 +48,3 @@
gd->ram_size = CFG_SYS_SDRAM_SIZE;
return 0;
}
-
-int dram_init(void)
-{
- return 0;
-}
diff --git a/arch/xtensa/cpu/u-boot.lds b/arch/xtensa/cpu/u-boot.lds
index 84ba32c..72e4b9a 100644
--- a/arch/xtensa/cpu/u-boot.lds
+++ b/arch/xtensa/cpu/u-boot.lds
@@ -82,6 +82,8 @@
__reloc_end = .;
__init_end = .;
+ /* Calculation to get end address in ROM */
+ _end = LOADADDR(.data) + (_data_end - _data_start);
SECTION_bss(__init_end (OVERLAY),)
diff --git a/arch/xtensa/dts/virt-u-boot.dtsi b/arch/xtensa/dts/virt-u-boot.dtsi
new file mode 100644
index 0000000..22b4683
--- /dev/null
+++ b/arch/xtensa/dts/virt-u-boot.dtsi
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Jiaxun Yang <jiaxun.yang@flygoat.com>
+ */
+
+#include <config.h>
+
+/ {
+ memory@0 {
+ device_type = "memory";
+#if XCHAL_HAVE_PTP_MMU
+ reg = <0x00000000 CFG_SYS_SDRAM_SIZE>;
+#else
+ reg = <CFG_SYS_MEMORY_BASE CFG_SYS_SDRAM_SIZE>;
+#endif
+ };
+};
diff --git a/arch/xtensa/include/asm/addrspace.h b/arch/xtensa/include/asm/addrspace.h
index 920b5fd..c8bed88 100644
--- a/arch/xtensa/include/asm/addrspace.h
+++ b/arch/xtensa/include/asm/addrspace.h
@@ -7,6 +7,8 @@
#ifndef _XTENSA_ADDRSPACE_H
#define _XTENSA_ADDRSPACE_H
+#include <config.h>
+
#include <asm/arch/core.h>
/*
diff --git a/arch/xtensa/include/asm/io.h b/arch/xtensa/include/asm/io.h
index 87ad9fa..ab2438b 100644
--- a/arch/xtensa/include/asm/io.h
+++ b/arch/xtensa/include/asm/io.h
@@ -12,6 +12,8 @@
#include <linux/types.h>
#include <asm/byteorder.h>
+#include <asm/addrspace.h>
+
/*
* swap functions to change byte order from little-endian to big-endian and
* vice versa.
@@ -125,8 +127,38 @@
*/
static inline void sync(void)
{
+}
+
+#if XCHAL_HAVE_PTP_MMU
+static inline void *phys_to_virt(phys_addr_t paddr)
+{
+ if (paddr >= CFG_SYS_IO_BASE)
+ return (void *)(unsigned long)paddr;
+
+ if (paddr < CFG_MAX_MEM_MAPPED)
+ return (void *)(unsigned long)MEMADDR(paddr);
+
+ return NULL;
+}
+
+#define phys_to_virt phys_to_virt
+
+static inline phys_addr_t virt_to_phys(void *vaddr)
+{
+ unsigned long addr = (unsigned long)vaddr;
+
+ if (addr >= CFG_SYS_IO_BASE)
+ return addr;
+
+ if (addr >= CFG_SYS_SDRAM_BASE && addr < MEMADDR(CFG_MAX_MEM_MAPPED))
+ return PHYSADDR(addr);
+
+ return 0;
}
+#define virt_to_phys virt_to_phys
+#endif /* XCHAL_HAVE_PTP_MMU */
+
#include <asm-generic/io.h>
#endif /* _XTENSA_IO_H */
diff --git a/arch/xtensa/include/asm/ldscript.h b/arch/xtensa/include/asm/ldscript.h
index 78a0b23..bcf0fd5 100644
--- a/arch/xtensa/include/asm/ldscript.h
+++ b/arch/xtensa/include/asm/ldscript.h
@@ -165,7 +165,6 @@
. = ALIGN(8); \
_bss_end = ABSOLUTE(.); \
__bss_end = ABSOLUTE(.); \
- _end = ALIGN(0x8); \
PROVIDE(end = ALIGN(0x8)); \
_stack_sentry = ALIGN(0x8); \
}
diff --git a/arch/xtensa/include/asm/platform/simcall-gdbio.h b/arch/xtensa/include/asm/platform/simcall-gdbio.h
new file mode 100644
index 0000000..e642860
--- /dev/null
+++ b/arch/xtensa/include/asm/platform/simcall-gdbio.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (C) 2021 Cadence Design Systems Inc. */
+
+#ifndef _XTENSA_PLATFORM_ISS_SIMCALL_GDBIO_H
+#define _XTENSA_PLATFORM_ISS_SIMCALL_GDBIO_H
+
+/*
+ * System call like services offered by the GDBIO host.
+ */
+
+#define SYS_open -2
+#define SYS_close -3
+#define SYS_read -4
+#define SYS_write -5
+#define SYS_lseek -6
+
+static int errno;
+
+static inline int __simc(int a, int b, int c, int d)
+{
+ register int a1 asm("a2") = a;
+ register int b1 asm("a6") = b;
+ register int c1 asm("a3") = c;
+ register int d1 asm("a4") = d;
+ __asm__ __volatile__ (
+ "break 1, 14\n"
+ : "+r"(a1), "+r"(c1)
+ : "r"(b1), "r"(d1)
+ : "memory");
+ errno = c1;
+ return a1;
+}
+
+#endif /* _XTENSA_PLATFORM_ISS_SIMCALL_GDBIO_H */
diff --git a/arch/xtensa/include/asm/platform/simcall-iss.h b/arch/xtensa/include/asm/platform/simcall-iss.h
new file mode 100644
index 0000000..5a1e7a1
--- /dev/null
+++ b/arch/xtensa/include/asm/platform/simcall-iss.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (C) 2021 Cadence Design Systems Inc. */
+
+#ifndef _XTENSA_PLATFORM_ISS_SIMCALL_ISS_H
+#define _XTENSA_PLATFORM_ISS_SIMCALL_ISS_H
+
+/*
+ * System call like services offered by the simulator host.
+ */
+
+#define SYS_nop 0 /* unused */
+#define SYS_exit 1 /*x*/
+#define SYS_fork 2
+#define SYS_read 3 /*x*/
+#define SYS_write 4 /*x*/
+#define SYS_open 5 /*x*/
+#define SYS_close 6 /*x*/
+#define SYS_rename 7 /*x 38 - waitpid */
+#define SYS_creat 8 /*x*/
+#define SYS_link 9 /*x (not implemented on WIN32) */
+#define SYS_unlink 10 /*x*/
+#define SYS_execv 11 /* n/a - execve */
+#define SYS_execve 12 /* 11 - chdir */
+#define SYS_pipe 13 /* 42 - time */
+#define SYS_stat 14 /* 106 - mknod */
+#define SYS_chmod 15
+#define SYS_chown 16 /* 202 - lchown */
+#define SYS_utime 17 /* 30 - break */
+#define SYS_wait 18 /* n/a - oldstat */
+#define SYS_lseek 19 /*x*/
+#define SYS_getpid 20
+#define SYS_isatty 21 /* n/a - mount */
+#define SYS_fstat 22 /* 108 - oldumount */
+#define SYS_time 23 /* 13 - setuid */
+#define SYS_gettimeofday 24 /*x 78 - getuid (not implemented on WIN32) */
+#define SYS_times 25 /*X 43 - stime (Xtensa-specific implementation) */
+#define SYS_socket 26
+#define SYS_sendto 27
+#define SYS_recvfrom 28
+#define SYS_select_one 29 /* not compatible select, one file descriptor at the time */
+#define SYS_bind 30
+#define SYS_ioctl 31
+
+#define SYS_iss_argc 1000 /* returns value of argc */
+#define SYS_iss_argv_size 1001 /* bytes needed for argv & arg strings */
+#define SYS_iss_set_argv 1002 /* saves argv & arg strings at given addr */
+
+/*
+ * SYS_select_one specifiers
+ */
+
+#define XTISS_SELECT_ONE_READ 1
+#define XTISS_SELECT_ONE_WRITE 2
+#define XTISS_SELECT_ONE_EXCEPT 3
+
+static int errno;
+
+static inline int __simc(int a, int b, int c, int d)
+{
+ register int a1 asm("a2") = a;
+ register int b1 asm("a3") = b;
+ register int c1 asm("a4") = c;
+ register int d1 asm("a5") = d;
+ __asm__ __volatile__ (
+ "simcall\n"
+ : "+r"(a1), "+r"(b1)
+ : "r"(c1), "r"(d1)
+ : "memory");
+ errno = b1;
+ return a1;
+}
+
+#endif /* _XTENSA_PLATFORM_ISS_SIMCALL_ISS_H */
diff --git a/arch/xtensa/include/asm/platform/simcall.h b/arch/xtensa/include/asm/platform/simcall.h
new file mode 100644
index 0000000..a1cb269
--- /dev/null
+++ b/arch/xtensa/include/asm/platform/simcall.h
@@ -0,0 +1,110 @@
+/*
+ * include/asm-xtensa/platform-iss/simcall.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 Tensilica Inc.
+ * Copyright (C) 2017 - 2021 Cadence Design Systems Inc.
+ */
+
+#ifndef _XTENSA_PLATFORM_ISS_SIMCALL_H
+#define _XTENSA_PLATFORM_ISS_SIMCALL_H
+
+#include <linux/bug.h>
+
+#ifdef CONFIG_XTENSA_SIMCALL_ISS
+#include <asm/platform/simcall-iss.h>
+#endif
+#ifdef CONFIG_XTENSA_SIMCALL_GDBIO
+#include <asm/platform/simcall-gdbio.h>
+#endif
+
+static inline int simc_exit(int exit_code)
+{
+#ifdef SYS_exit
+ return __simc(SYS_exit, exit_code, 0, 0);
+#else
+ WARN_ONCE(1, "%s: not implemented\n", __func__);
+ return -1;
+#endif
+}
+
+static inline int simc_open(const char *file, int flags, int mode)
+{
+ return __simc(SYS_open, (int) file, flags, mode);
+}
+
+static inline int simc_close(int fd)
+{
+ return __simc(SYS_close, fd, 0, 0);
+}
+
+static inline int simc_ioctl(int fd, int request, void *arg)
+{
+#ifdef SYS_ioctl
+ return __simc(SYS_ioctl, fd, request, (int) arg);
+#else
+ WARN_ONCE(1, "%s: not implemented\n", __func__);
+ return -1;
+#endif
+}
+
+static inline int simc_read(int fd, void *buf, size_t count)
+{
+ return __simc(SYS_read, fd, (int) buf, count);
+}
+
+static inline int simc_write(int fd, const void *buf, size_t count)
+{
+ return __simc(SYS_write, fd, (int) buf, count);
+}
+
+static inline int simc_poll(int fd)
+{
+#ifdef SYS_select_one
+ long timeval[2] = { 0, 0 };
+
+ return __simc(SYS_select_one, fd, XTISS_SELECT_ONE_READ, (int)&timeval);
+#else
+ WARN_ONCE(1, "%s: not implemented\n", __func__);
+ return -1;
+#endif
+}
+
+static inline int simc_lseek(int fd, uint32_t off, int whence)
+{
+ return __simc(SYS_lseek, fd, off, whence);
+}
+
+static inline int simc_argc(void)
+{
+#ifdef SYS_iss_argc
+ return __simc(SYS_iss_argc, 0, 0, 0);
+#else
+ WARN_ONCE(1, "%s: not implemented\n", __func__);
+ return 0;
+#endif
+}
+
+static inline int simc_argv_size(void)
+{
+#ifdef SYS_iss_argv_size
+ return __simc(SYS_iss_argv_size, 0, 0, 0);
+#else
+ WARN_ONCE(1, "%s: not implemented\n", __func__);
+ return 0;
+#endif
+}
+
+static inline void simc_argv(void *buf)
+{
+#ifdef SYS_iss_set_argv
+ __simc(SYS_iss_set_argv, (int)buf, 0, 0);
+#else
+ WARN_ONCE(1, "%s: not implemented\n", __func__);
+#endif
+}
+
+#endif /* _XTENSA_PLATFORM_ISS_SIMCALL_H */
diff --git a/board/CZ.NIC/turris_1x/Kconfig b/board/CZ.NIC/turris_1x/Kconfig
index f55dfa1..baea4d8 100644
--- a/board/CZ.NIC/turris_1x/Kconfig
+++ b/board/CZ.NIC/turris_1x/Kconfig
@@ -128,8 +128,6 @@
default y
config NAND_ECC_BCH
default y
-endif
-
config SYS_LOAD_ADDR
default 0x1000000
@@ -153,3 +151,5 @@
default y
endif
+
+endif
diff --git a/board/CZ.NIC/turris_omnia/Makefile b/board/CZ.NIC/turris_omnia/Makefile
index 341378b..d1ef5cb 100644
--- a/board/CZ.NIC/turris_omnia/Makefile
+++ b/board/CZ.NIC/turris_omnia/Makefile
@@ -3,3 +3,5 @@
# Copyright (C) 2017 Marek Behún <kabel@kernel.org>
obj-y := turris_omnia.o ../turris_atsha_otp.o ../turris_common.o
+obj-$(CONFIG_CMD_EEPROM_LAYOUT) += eeprom.o
+obj-$(CONFIG_SPL_BUILD) += old_ddr3_training.o
diff --git a/board/CZ.NIC/turris_omnia/eeprom.c b/board/CZ.NIC/turris_omnia/eeprom.c
new file mode 100644
index 0000000..6e2640a
--- /dev/null
+++ b/board/CZ.NIC/turris_omnia/eeprom.c
@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Marek Behún <kabel@kernel.org>
+ */
+
+#include <asm/unaligned.h>
+#include <ctype.h>
+#include <linux/compiler.h>
+#include <linux/kernel.h>
+#include <eeprom_field.h>
+#include <eeprom_layout.h>
+#include <u-boot/crc.h>
+
+#define _DEF_FIELD(_n, _s, _t) \
+ { _n, _s, NULL, eeprom_field_print_ ## _t, eeprom_field_update_ ## _t }
+
+static void eeprom_field_print_ramsz(const struct eeprom_field *field)
+{
+ printf(PRINT_FIELD_SEGMENT, field->name);
+ printf("%u\n", get_unaligned_le32(field->buf));
+}
+
+static int eeprom_field_update_ramsz(struct eeprom_field *field, char *value)
+{
+ u32 sz;
+
+ if (value[0] == '1' || value[0] == '2' || value[0] == '4')
+ sz = value[0] - '0';
+ else
+ return -1;
+
+ if (value[1] != '\0')
+ return -1;
+
+ put_unaligned_le32(sz, field->buf);
+
+ return 0;
+}
+
+static void eeprom_field_print_region(const struct eeprom_field *field)
+{
+ eeprom_field_print_ascii(field);
+}
+
+static int eeprom_field_update_region(struct eeprom_field *field, char *value)
+{
+ if (strlen(value) != 2) {
+ printf("%s: has to be 2 characters\n", field->name);
+ return -1;
+ }
+
+ memcpy(field->buf, value, 2);
+ memset(&field->buf[2], '\0', 2);
+
+ return 0;
+}
+
+static void eeprom_field_print_ddr_speed(const struct eeprom_field *field)
+{
+ printf(PRINT_FIELD_SEGMENT, field->name);
+
+ if (field->buf[0] == '\0' || field->buf[0] == 0xff)
+ puts("(empty, defaults to 1600K)\n");
+ else
+ printf("%.5s\n", field->buf);
+}
+
+bool omnia_valid_ddr_speed(const char *name);
+void omnia_print_ddr_speeds(void);
+
+static int eeprom_field_update_ddr_speed(struct eeprom_field *field,
+ char *value)
+{
+ if (value[0] == '\0') {
+ /* setting default value */
+ memset(field->buf, 0xff, field->size);
+
+ return 0;
+ }
+
+ if (!omnia_valid_ddr_speed(value)) {
+ printf("%s: invalid setting, supported values are:\n ",
+ field->name);
+ omnia_print_ddr_speeds();
+
+ return -1;
+ }
+
+ strncpy(field->buf, value, field->size);
+
+ return 0;
+}
+
+static void eeprom_field_print_bool(const struct eeprom_field *field)
+{
+ unsigned char val = field->buf[0];
+
+ printf(PRINT_FIELD_SEGMENT, field->name);
+
+ if (val == 0xff)
+ puts("(empty, defaults to 0)\n");
+ else
+ printf("%u\n", val);
+}
+
+static int eeprom_field_update_bool(struct eeprom_field *field, char *value)
+{
+ unsigned char *val = &field->buf[0];
+
+ if (value[0] == '\0') {
+ /* setting default value */
+ *val = 0xff;
+
+ return 0;
+ }
+
+ if (value[1] != '\0')
+ return -1;
+
+ if (value[0] == '1' || value[0] == '0')
+ *val = value[0] - '0';
+ else
+ return -1;
+
+ return 0;
+}
+
+static struct eeprom_field omnia_layout[] = {
+ _DEF_FIELD("Magic constant", 4, bin),
+ _DEF_FIELD("RAM size in GB", 4, ramsz),
+ _DEF_FIELD("Wi-Fi Region", 4, region),
+ _DEF_FIELD("CRC32 checksum", 4, bin),
+ _DEF_FIELD("DDR speed", 5, ddr_speed),
+ _DEF_FIELD("Use old DDR training", 1, bool),
+ _DEF_FIELD("Extended reserved fields", 38, reserved),
+ _DEF_FIELD("Extended CRC32 checksum", 4, bin),
+};
+
+static struct eeprom_field *crc_field = &omnia_layout[3];
+static struct eeprom_field *ext_crc_field =
+ &omnia_layout[ARRAY_SIZE(omnia_layout) - 1];
+
+static int omnia_update_field(struct eeprom_layout *layout, char *field_name,
+ char *new_data)
+{
+ struct eeprom_field *field;
+ int err;
+
+ if (!new_data)
+ return 0;
+
+ if (!field_name)
+ return -1;
+
+ field = eeprom_layout_find_field(layout, field_name, true);
+ if (!field)
+ return -1;
+
+ err = field->update(field, new_data);
+ if (err) {
+ printf("Invalid data for field %s\n", field_name);
+ return err;
+ }
+
+ if (field < crc_field) {
+ u32 crc = crc32(0, layout->data, 12);
+ put_unaligned_le32(crc, crc_field->buf);
+ }
+
+ if (field < ext_crc_field) {
+ u32 crc = crc32(0, layout->data, 60);
+ put_unaligned_le32(crc, ext_crc_field->buf);
+ }
+
+ return 0;
+}
+
+void eeprom_layout_assign(struct eeprom_layout *layout, int)
+{
+ layout->fields = omnia_layout;
+ layout->num_of_fields = ARRAY_SIZE(omnia_layout);
+ layout->update = omnia_update_field;
+ layout->data_size = 64;
+}
+
+int eeprom_layout_detect(unsigned char *)
+{
+ /* Turris Omnia has only one version of EEPROM layout */
+ return 0;
+}
diff --git a/board/CZ.NIC/turris_omnia/old_ddr3_training.c b/board/CZ.NIC/turris_omnia/old_ddr3_training.c
new file mode 100644
index 0000000..cdb3487
--- /dev/null
+++ b/board/CZ.NIC/turris_omnia/old_ddr3_training.c
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Marek Behún <kabel@kernel.org>
+ */
+
+#include <asm/arch/soc.h>
+#include <asm/io.h>
+
+#include "../drivers/ddr/marvell/a38x/old/ddr3_init.h"
+
+static struct hws_topology_map board_topology_map_1g = {
+ 0x1, /* active interfaces */
+ /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
+ { { { {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0} },
+ SPEED_BIN_DDR_1600K, /* speed_bin */
+ BUS_WIDTH_16, /* memory_width */
+ MEM_4G, /* mem_size */
+ DDR_FREQ_800, /* frequency */
+ 0, 0, /* cas_l cas_wl */
+ HWS_TEMP_NORMAL, /* temperature */
+ HWS_TIM_2T} }, /* timing (force 2t) */
+ 5, /* Num Of Bus Per Interface*/
+ BUS_MASK_32BIT /* Busses mask */
+};
+
+static struct hws_topology_map board_topology_map_2g = {
+ 0x1, /* active interfaces */
+ /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
+ { { { {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0} },
+ SPEED_BIN_DDR_1600K, /* speed_bin */
+ BUS_WIDTH_16, /* memory_width */
+ MEM_8G, /* mem_size */
+ DDR_FREQ_800, /* frequency */
+ 0, 0, /* cas_l cas_wl */
+ HWS_TEMP_NORMAL, /* temperature */
+ HWS_TIM_2T} }, /* timing (force 2t) */
+ 5, /* Num Of Bus Per Interface*/
+ BUS_MASK_32BIT /* Busses mask */
+};
+
+/* defined in turris_omnia.c */
+extern int omnia_get_ram_size_gb(void);
+
+struct hws_topology_map *ddr3_get_topology_map(void)
+{
+ if (omnia_get_ram_size_gb() == 2)
+ return &board_topology_map_2g;
+ else
+ return &board_topology_map_1g;
+}
+
+__weak u32 sys_env_get_topology_update_info(struct topology_update_info *tui)
+{
+ return MV_OK;
+}
diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c
index 4ee1a39..2f29d26 100644
--- a/board/CZ.NIC/turris_omnia/turris_omnia.c
+++ b/board/CZ.NIC/turris_omnia/turris_omnia.c
@@ -429,12 +429,42 @@
u32 ramsize;
char region[4];
u32 crc;
+
+ /* second part (only considered if crc2 is not all-ones) */
+ char ddr_speed[5];
+ u8 old_ddr_training;
+ u8 reserved[38];
+ u32 crc2;
};
+static bool is_omnia_eeprom_second_part_valid(const struct omnia_eeprom *oep)
+{
+ return oep->crc2 != 0xffffffff;
+}
+
+static void make_omnia_eeprom_second_part_invalid(struct omnia_eeprom *oep)
+{
+ oep->crc2 = 0xffffffff;
+}
+
+static bool check_eeprom_crc(const void *buf, size_t size, u32 expected,
+ const char *name)
+{
+ u32 crc;
+
+ crc = crc32(0, buf, size);
+ if (crc != expected) {
+ printf("bad %s EEPROM CRC (stored %08x, computed %08x)\n",
+ name, expected, crc);
+ return false;
+ }
+
+ return true;
+}
+
static bool omnia_read_eeprom(struct omnia_eeprom *oep)
{
struct udevice *chip;
- u32 crc;
int ret;
chip = omnia_get_i2c_chip("EEPROM", OMNIA_I2C_EEPROM_CHIP_ADDR,
@@ -455,17 +485,19 @@
return false;
}
- crc = crc32(0, (void *)oep, sizeof(*oep) - 4);
- if (crc != oep->crc) {
- printf("bad EEPROM CRC (stored %08x, computed %08x)\n",
- oep->crc, crc);
+ if (!check_eeprom_crc(oep, offsetof(struct omnia_eeprom, crc), oep->crc,
+ "first"))
return false;
- }
+
+ if (is_omnia_eeprom_second_part_valid(oep) &&
+ !check_eeprom_crc(oep, offsetof(struct omnia_eeprom, crc2),
+ oep->crc2, "second"))
+ make_omnia_eeprom_second_part_invalid(oep);
return true;
}
-static int omnia_get_ram_size_gb(void)
+int omnia_get_ram_size_gb(void)
{
static int ram_size;
struct omnia_eeprom oep;
@@ -490,6 +522,39 @@
return ram_size;
}
+bool board_use_old_ddr3_training(void)
+{
+ struct omnia_eeprom oep;
+
+ if (!omnia_read_eeprom(&oep))
+ return false;
+
+ if (!is_omnia_eeprom_second_part_valid(&oep))
+ return false;
+
+ return oep.old_ddr_training == 1;
+}
+
+static const char *omnia_get_ddr_speed(void)
+{
+ struct omnia_eeprom oep;
+ static char speed[sizeof(oep.ddr_speed) + 1];
+
+ if (!omnia_read_eeprom(&oep))
+ return NULL;
+
+ if (!is_omnia_eeprom_second_part_valid(&oep))
+ return NULL;
+
+ if (!oep.ddr_speed[0] || oep.ddr_speed[0] == 0xff)
+ return NULL;
+
+ memcpy(&speed, &oep.ddr_speed, sizeof(oep.ddr_speed));
+ speed[sizeof(speed) - 1] = '\0';
+
+ return speed;
+}
+
static const char * const omnia_get_mcu_type(void)
{
static char result[] = "xxxxxxx (with peripheral resets)";
@@ -604,12 +669,84 @@
{0} /* timing parameters */
};
+static const struct omnia_ddr_speed {
+ char name[5];
+ u8 speed_bin;
+ u8 freq;
+} omnia_ddr_speeds[] = {
+ { "1066F", SPEED_BIN_DDR_1066F, MV_DDR_FREQ_533 },
+ { "1333H", SPEED_BIN_DDR_1333H, MV_DDR_FREQ_667 },
+ { "1600K", SPEED_BIN_DDR_1600K, MV_DDR_FREQ_800 },
+};
+
+static const struct omnia_ddr_speed *find_ddr_speed_setting(const char *name)
+{
+ for (int i = 0; i < ARRAY_SIZE(omnia_ddr_speeds); ++i)
+ if (!strncmp(name, omnia_ddr_speeds[i].name, 5))
+ return &omnia_ddr_speeds[i];
+
+ return NULL;
+}
+
+bool omnia_valid_ddr_speed(const char *name)
+{
+ return find_ddr_speed_setting(name) != NULL;
+}
+
+void omnia_print_ddr_speeds(void)
+{
+ for (int i = 0; i < ARRAY_SIZE(omnia_ddr_speeds); ++i)
+ printf("%.5s%s", omnia_ddr_speeds[i].name,
+ i == ARRAY_SIZE(omnia_ddr_speeds) - 1 ? "\n" : ", ");
+}
+
+static void fixup_speed_in_ddr_topology(struct mv_ddr_topology_map *topology)
+{
+ typeof(topology->interface_params[0]) *params;
+ const struct omnia_ddr_speed *setting;
+ const char *speed;
+ static bool done;
+
+ if (done)
+ return;
+
+ done = true;
+
+ speed = omnia_get_ddr_speed();
+ if (!speed)
+ return;
+
+ setting = find_ddr_speed_setting(speed);
+ if (!setting) {
+ printf("Unsupported value %s for DDR3 speed in EEPROM!\n",
+ speed);
+ return;
+ }
+
+ params = &topology->interface_params[0];
+
+ /* don't inform if we are not changing the speed from the default one */
+ if (params->speed_bin_index == setting->speed_bin)
+ return;
+
+ printf("Fixing up DDR3 speed (EEPROM defines %s)\n", speed);
+
+ params->speed_bin_index = setting->speed_bin;
+ params->memory_freq = setting->freq;
+}
+
struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
{
+ struct mv_ddr_topology_map *topology;
+
if (omnia_get_ram_size_gb() == 2)
- return &board_topology_map_2g;
+ topology = &board_topology_map_2g;
else
- return &board_topology_map_1g;
+ topology = &board_topology_map_1g;
+
+ fixup_speed_in_ddr_topology(topology);
+
+ return topology;
}
static int set_regdomain(void)
@@ -978,11 +1115,21 @@
return 0;
}
-static int fixup_mcu_gpio_in_eth_wan_node(void *blob)
+static int get_phy_wan_node_offset(const void *blob)
+{
+ u32 phy_wan_phandle;
+
+ phy_wan_phandle = fdt_getprop_u32_default(blob, "ethernet2", "phy-handle", 0);
+ if (!phy_wan_phandle)
+ return -FDT_ERR_NOTFOUND;
+
+ return fdt_node_offset_by_phandle(blob, phy_wan_phandle);
+}
+
+static int fixup_mcu_gpio_in_phy_wan_node(void *blob)
{
unsigned int mcu_phandle;
- int eth_wan_node;
- int ret;
+ int phy_wan_node, ret;
ret = fdt_increase_size(blob, 64);
if (ret < 0) {
@@ -990,21 +1137,17 @@
return ret;
}
- eth_wan_node = fdt_path_offset(blob, "ethernet2");
- if (eth_wan_node < 0)
- return eth_wan_node;
+ phy_wan_node = get_phy_wan_node_offset(blob);
+ if (phy_wan_node < 0)
+ return phy_wan_node;
mcu_phandle = fdt_create_phandle_by_compatible(blob, "cznic,turris-omnia-mcu");
if (!mcu_phandle)
return -FDT_ERR_NOPHANDLES;
- /* insert: phy-reset-gpios = <&mcu 2 gpio GPIO_ACTIVE_LOW>; */
- ret = insert_mcu_gpio_prop(blob, eth_wan_node, "phy-reset-gpios",
- mcu_phandle, 2, ilog2(EXT_CTL_nRES_PHY), GPIO_ACTIVE_LOW);
- if (ret < 0)
- return ret;
-
- return 0;
+ /* insert: reset-gpios = <&mcu 2 gpio GPIO_ACTIVE_LOW>; */
+ return insert_mcu_gpio_prop(blob, phy_wan_node, "reset-gpios",
+ mcu_phandle, 2, ilog2(EXT_CTL_nRES_PHY), GPIO_ACTIVE_LOW);
}
static void fixup_atsha_node(void *blob)
@@ -1033,7 +1176,7 @@
{
if (omnia_mcu_has_feature(FEAT_PERIPH_MCU)) {
fixup_mcu_gpio_in_pcie_nodes(blob);
- fixup_mcu_gpio_in_eth_wan_node(blob);
+ fixup_mcu_gpio_in_phy_wan_node(blob);
}
fixup_msata_port_nodes(blob);
@@ -1218,14 +1361,14 @@
int node;
/*
- * U-Boot's FDT blob contains phy-reset-gpios in ethernet2
- * node when MCU controls all peripherals resets.
+ * U-Boot's FDT blob contains reset-gpios in ethernet2 PHY node when MCU
+ * controls all peripherals resets.
* Fixup MCU GPIO nodes in PCIe and eth wan nodes in this case.
*/
- node = fdt_path_offset(gd->fdt_blob, "ethernet2");
- if (node >= 0 && fdt_getprop(gd->fdt_blob, node, "phy-reset-gpios", NULL)) {
+ node = get_phy_wan_node_offset(gd->fdt_blob);
+ if (node >= 0 && fdt_getprop(gd->fdt_blob, node, "reset-gpios", NULL)) {
fixup_mcu_gpio_in_pcie_nodes(blob);
- fixup_mcu_gpio_in_eth_wan_node(blob);
+ fixup_mcu_gpio_in_phy_wan_node(blob);
}
fixup_spi_nor_partitions(blob);
diff --git a/board/Marvell/mvebu_armada-37xx/MAINTAINERS b/board/Marvell/mvebu_armada-37xx/MAINTAINERS
index 9b0afee..e96499e 100644
--- a/board/Marvell/mvebu_armada-37xx/MAINTAINERS
+++ b/board/Marvell/mvebu_armada-37xx/MAINTAINERS
@@ -9,3 +9,8 @@
M: Konstantin Porotchkin <kostap@marvell.com>
S: Maintained
F: configs/mvebu_espressobin-88f3720_defconfig
+
+ESPRESSOBin Ultra BOARD
+M: Ben Schneider <ben@bens.haus>
+S: Maintained
+F: configs/mvebu_espressobin_ultra-88f3720_defconfig
diff --git a/board/Marvell/octeon_nic23/board.c b/board/Marvell/octeon_nic23/board.c
index bc9332c..cf20c97 100644
--- a/board/Marvell/octeon_nic23/board.c
+++ b/board/Marvell/octeon_nic23/board.c
@@ -249,7 +249,7 @@
* read the incorrect device ID 0x9700 (reset value) instead of 0x9702
* (restored value).
*/
-static void octeon_board_restore_pf(void *ctx)
+static void octeon_board_restore_pf(struct cyclic_info *c)
{
union cvmx_spemx_flr_pf_stopreq stopreq;
static bool start_initialized[2] = {false, false};
@@ -357,10 +357,13 @@
board_configure_qlms();
/* Register cyclic function for PCIe FLR fixup */
- cyclic = cyclic_register(octeon_board_restore_pf, 100,
- "pcie_flr_fix", NULL);
- if (!cyclic)
+ cyclic = calloc(1, sizeof(*cyclic));
+ if (cyclic) {
+ cyclic_register(cyclic, octeon_board_restore_pf, 100,
+ "pcie_flr_fix");
+ } else {
printf("Registering of cyclic function failed\n");
+ }
return 0;
}
diff --git a/board/Synology/common/legacy.c b/board/Synology/common/legacy.c
index a0bace7..2e3aa66 100644
--- a/board/Synology/common/legacy.c
+++ b/board/Synology/common/legacy.c
@@ -6,6 +6,7 @@
*/
#include <config.h>
+#include <stdio.h>
#include <vsprintf.h>
#include <env.h>
#include <net.h>
diff --git a/board/amd/common b/board/amd/common
new file mode 120000
index 0000000..cd4d172
--- /dev/null
+++ b/board/amd/common
@@ -0,0 +1 @@
+../xilinx/common/
\ No newline at end of file
diff --git a/board/amd/versal2/Kconfig b/board/amd/versal2/Kconfig
new file mode 100644
index 0000000..ab46af6
--- /dev/null
+++ b/board/amd/versal2/Kconfig
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (C) 2020 - 2022, Xilinx, Inc.
+# Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc.
+#
+if ARCH_VERSAL2
+
+config CMD_VERSAL2
+ bool "Enable Versal Gen 2 specific commands"
+ default y
+ depends on ZYNQMP_FIRMWARE
+ help
+ Select this to enable AMD Versal Gen 2 specific commands.
+ Commands like versal2 loadpdi are enabled by this.
+
+endif
diff --git a/board/amd/versal2/MAINTAINERS b/board/amd/versal2/MAINTAINERS
new file mode 100644
index 0000000..af7913d
--- /dev/null
+++ b/board/amd/versal2/MAINTAINERS
@@ -0,0 +1,7 @@
+XILINX_VERSAL2 BOARDS
+M: Michal Simek <michal.simek@amd.com>
+S: Maintained
+T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git
+F: arch/arm/dts/versal2*
+F: board/amd/
+F: configs/amd*
diff --git a/board/amd/versal2/Makefile b/board/amd/versal2/Makefile
new file mode 100644
index 0000000..3a04451
--- /dev/null
+++ b/board/amd/versal2/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (C) 2021 - 2022, Xilinx, Inc.
+# Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc.
+#
+# Michal Simek <michal.simek@amd.com>
+#
+
+obj-y := board.o
+
+obj-$(CONFIG_CMD_VERSAL2) += cmds.o
diff --git a/board/amd/versal2/board.c b/board/amd/versal2/board.c
new file mode 100644
index 0000000..5651d51
--- /dev/null
+++ b/board/amd/versal2/board.c
@@ -0,0 +1,343 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 - 2022, Xilinx, Inc.
+ * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include <cpu_func.h>
+#include <fdtdec.h>
+#include <init.h>
+#include <env_internal.h>
+#include <log.h>
+#include <malloc.h>
+#include <time.h>
+#include <asm/cache.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+#include "../../xilinx/common/board.h"
+
+#include <linux/bitfield.h>
+#include <debug_uart.h>
+#include <generated/dt.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ printf("EL Level:\tEL%d\n", current_el());
+
+ return 0;
+}
+
+static u32 platform_id, platform_version;
+
+char *soc_name_decode(void)
+{
+ char *name, *platform_name;
+
+ switch (platform_id) {
+ case VERSAL2_SPP:
+ platform_name = "spp";
+ break;
+ case VERSAL2_EMU:
+ platform_name = "emu";
+ break;
+ case VERSAL2_SPP_MMD:
+ platform_name = "spp-mmd";
+ break;
+ case VERSAL2_EMU_MMD:
+ platform_name = "emu-mmd";
+ break;
+ case VERSAL2_QEMU:
+ platform_name = "qemu";
+ break;
+ default:
+ return NULL;
+ }
+
+ /*
+ * --rev. are 6 chars
+ * max platform name is qemu which is 4 chars
+ * platform version number are 1+1
+ * Plus 1 char for \n
+ */
+ name = calloc(1, strlen(CONFIG_SYS_BOARD) + 13);
+ if (!name)
+ return NULL;
+
+ sprintf(name, "%s-%s-rev%d.%d-el%d", CONFIG_SYS_BOARD,
+ platform_name, platform_version / 10,
+ platform_version % 10, current_el());
+
+ return name;
+}
+
+bool soc_detection(void)
+{
+ u32 version, ps_version;
+
+ version = readl(PMC_TAP_VERSION);
+ platform_id = FIELD_GET(PLATFORM_MASK, version);
+ ps_version = FIELD_GET(PS_VERSION_MASK, version);
+
+ debug("idcode %x, version %x, usercode %x\n",
+ readl(PMC_TAP_IDCODE), version,
+ readl(PMC_TAP_USERCODE));
+
+ debug("pmc_ver %lx, ps version %x, rtl version %lx\n",
+ FIELD_GET(PMC_VERSION_MASK, version),
+ ps_version,
+ FIELD_GET(RTL_VERSION_MASK, version));
+
+ platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version);
+
+ debug("Platform id: %d version: %d.%d\n", platform_id,
+ platform_version / 10, platform_version % 10);
+
+ return true;
+}
+
+int board_early_init_r(void)
+{
+ u32 val;
+
+ if (current_el() != 3)
+ return 0;
+
+ debug("iou_switch ctrl div0 %x\n",
+ readl(&crlapb_base->iou_switch_ctrl));
+
+ writel(IOU_SWITCH_CTRL_CLKACT_BIT |
+ (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
+ &crlapb_base->iou_switch_ctrl);
+
+ /* Global timer init - Program time stamp reference clk */
+ val = readl(&crlapb_base->timestamp_ref_ctrl);
+ val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
+ writel(val, &crlapb_base->timestamp_ref_ctrl);
+
+ debug("ref ctrl 0x%x\n",
+ readl(&crlapb_base->timestamp_ref_ctrl));
+
+ /* Clear reset of timestamp reg */
+ writel(0, &crlapb_base->rst_timestamp);
+
+ /*
+ * Program freq register in System counter and
+ * enable system counter.
+ */
+ writel(CONFIG_COUNTER_FREQUENCY,
+ &iou_scntr_secure->base_frequency_id_register);
+
+ debug("counter val 0x%x\n",
+ readl(&iou_scntr_secure->base_frequency_id_register));
+
+ writel(IOU_SCNTRS_CONTROL_EN,
+ &iou_scntr_secure->counter_control_register);
+
+ debug("scntrs control 0x%x\n",
+ readl(&iou_scntr_secure->counter_control_register));
+ debug("timer 0x%llx\n", get_ticks());
+ debug("timer 0x%llx\n", get_ticks());
+
+ return 0;
+}
+
+static u8 versal_net_get_bootmode(void)
+{
+ u8 bootmode;
+ u32 reg = 0;
+
+ reg = readl(&crp_base->boot_mode_usr);
+
+ if (reg >> BOOT_MODE_ALT_SHIFT)
+ reg >>= BOOT_MODE_ALT_SHIFT;
+
+ bootmode = reg & BOOT_MODES_MASK;
+
+ return bootmode;
+}
+
+static int boot_targets_setup(void)
+{
+ u8 bootmode;
+ struct udevice *dev;
+ int bootseq = -1;
+ int bootseq_len = 0;
+ int env_targets_len = 0;
+ const char *mode = NULL;
+ char *new_targets;
+ char *env_targets;
+
+ bootmode = versal_net_get_bootmode();
+
+ puts("Bootmode: ");
+ switch (bootmode) {
+ case USB_MODE:
+ puts("USB_MODE\n");
+ mode = "usb_dfu0 usb_dfu1";
+ break;
+ case JTAG_MODE:
+ puts("JTAG_MODE\n");
+ mode = "jtag pxe dhcp";
+ break;
+ case QSPI_MODE_24BIT:
+ puts("QSPI_MODE_24\n");
+ if (uclass_get_device_by_name(UCLASS_SPI,
+ "spi@f1030000", &dev)) {
+ debug("QSPI driver for QSPI device is not present\n");
+ break;
+ }
+ mode = "xspi";
+ bootseq = dev_seq(dev);
+ break;
+ case QSPI_MODE_32BIT:
+ puts("QSPI_MODE_32\n");
+ if (uclass_get_device_by_name(UCLASS_SPI,
+ "spi@f1030000", &dev)) {
+ debug("QSPI driver for QSPI device is not present\n");
+ break;
+ }
+ mode = "xspi";
+ bootseq = dev_seq(dev);
+ break;
+ case OSPI_MODE:
+ puts("OSPI_MODE\n");
+ if (uclass_get_device_by_name(UCLASS_SPI,
+ "spi@f1010000", &dev)) {
+ debug("OSPI driver for OSPI device is not present\n");
+ break;
+ }
+ mode = "xspi";
+ bootseq = dev_seq(dev);
+ break;
+ case EMMC_MODE:
+ puts("EMMC_MODE\n");
+ mode = "mmc";
+ bootseq = dev_seq(dev);
+ break;
+ case SELECTMAP_MODE:
+ puts("SELECTMAP_MODE\n");
+ break;
+ case SD_MODE:
+ puts("SD_MODE\n");
+ if (uclass_get_device_by_name(UCLASS_MMC,
+ "mmc@f1040000", &dev)) {
+ debug("SD0 driver for SD0 device is not present\n");
+ break;
+ }
+ debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
+
+ mode = "mmc";
+ bootseq = dev_seq(dev);
+ break;
+ case SD1_LSHFT_MODE:
+ puts("LVL_SHFT_");
+ fallthrough;
+ case SD_MODE1:
+ puts("SD_MODE1\n");
+ if (uclass_get_device_by_name(UCLASS_MMC,
+ "mmc@f1050000", &dev)) {
+ debug("SD1 driver for SD1 device is not present\n");
+ break;
+ }
+ debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
+
+ mode = "mmc";
+ bootseq = dev_seq(dev);
+ break;
+ default:
+ printf("Invalid Boot Mode:0x%x\n", bootmode);
+ break;
+ }
+
+ if (mode) {
+ if (bootseq >= 0) {
+ bootseq_len = snprintf(NULL, 0, "%i", bootseq);
+ debug("Bootseq len: %x\n", bootseq_len);
+ }
+
+ /*
+ * One terminating char + one byte for space between mode
+ * and default boot_targets
+ */
+ env_targets = env_get("boot_targets");
+ if (env_targets)
+ env_targets_len = strlen(env_targets);
+
+ new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
+ bootseq_len);
+ if (!new_targets)
+ return -ENOMEM;
+
+ if (bootseq >= 0)
+ sprintf(new_targets, "%s%x %s", mode, bootseq,
+ env_targets ? env_targets : "");
+ else
+ sprintf(new_targets, "%s %s", mode,
+ env_targets ? env_targets : "");
+
+ env_set("boot_targets", new_targets);
+ }
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ int ret;
+
+ if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
+ debug("Saved variables - Skipping\n");
+ return 0;
+ }
+
+ if (!IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG))
+ return 0;
+
+ if (IS_ENABLED(CONFIG_DISTRO_DEFAULTS)) {
+ ret = boot_targets_setup();
+ if (ret)
+ return ret;
+ }
+
+ return board_late_init_xilinx();
+}
+
+int dram_init_banksize(void)
+{
+ int ret;
+
+ ret = fdtdec_setup_memory_banksize();
+ if (ret)
+ return ret;
+
+ mem_map_fill();
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ int ret;
+
+ if (IS_ENABLED(CONFIG_SYS_MEM_RSVD_FOR_MMU))
+ ret = fdtdec_setup_mem_size_base();
+ else
+ ret = fdtdec_setup_mem_size_base_lowest();
+
+ if (ret)
+ return -EINVAL;
+
+ return 0;
+}
+
+void reset_cpu(void)
+{
+}
diff --git a/board/amd/versal2/cmds.c b/board/amd/versal2/cmds.c
new file mode 100644
index 0000000..56ae39b
--- /dev/null
+++ b/board/amd/versal2/cmds.c
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include <cpu_func.h>
+#include <command.h>
+#include <log.h>
+#include <memalign.h>
+#include <versalpl.h>
+#include <vsprintf.h>
+#include <zynqmp_firmware.h>
+
+/**
+ * do_versal2_load_pdi - Handle the "versal2 load pdi" command-line command
+ * @cmdtp: Command data struct pointer
+ * @flag: Command flag
+ * @argc: Command-line argument count
+ * @argv: Array of command-line arguments
+ *
+ * Processes the versal2 load pdi command
+ *
+ * Return: return 0 on success, Error value if command fails.
+ * CMD_RET_USAGE incase of incorrect/missing parameters.
+ */
+static int do_versal2_load_pdi(struct cmd_tbl *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ u32 buf_lo, buf_hi;
+ u32 ret_payload[PAYLOAD_ARG_CNT];
+ ulong addr, *pdi_buf;
+ size_t len;
+ int ret;
+
+ if (argc != cmdtp->maxargs) {
+ debug("pdi_load: incorrect parameters passed\n");
+ return CMD_RET_USAGE;
+ }
+
+ addr = simple_strtol(argv[1], NULL, 16);
+ if (!addr) {
+ debug("pdi_load: zero pdi_data address\n");
+ return CMD_RET_USAGE;
+ }
+
+ len = hextoul(argv[2], NULL);
+ if (!len) {
+ debug("pdi_load: zero size\n");
+ return CMD_RET_USAGE;
+ }
+
+ pdi_buf = (ulong *)ALIGN((ulong)addr, ARCH_DMA_MINALIGN);
+ if ((ulong)addr != (ulong)pdi_buf) {
+ memcpy((void *)pdi_buf, (void *)addr, len);
+ debug("Pdi addr:0x%lx aligned to 0x%lx\n",
+ addr, (ulong)pdi_buf);
+ }
+
+ flush_dcache_range((ulong)pdi_buf, (ulong)pdi_buf + len);
+
+ buf_lo = lower_32_bits((ulong)pdi_buf);
+ buf_hi = upper_32_bits((ulong)pdi_buf);
+
+ ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
+ buf_hi, 0, ret_payload);
+ if (ret)
+ printf("PDI load failed with err: 0x%08x\n", ret);
+
+ return cmd_process_error(cmdtp, ret);
+}
+
+U_BOOT_LONGHELP(versal2,
+ "loadpdi addr len - Load pdi image\n"
+ "load pdi image at ddr address 'addr' with pdi image size 'len'\n");
+
+U_BOOT_CMD_WITH_SUBCMDS(versal2, "Versal Gen 2 sub-system", versal2_help_text,
+ U_BOOT_SUBCMD_MKENT(loadpdi, 3, 1,
+ do_versal2_load_pdi));
diff --git a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
index 099eea6..5c57b90 100644
--- a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
+++ b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
@@ -6,14 +6,12 @@
#include <abuf.h>
#include <adc.h>
#include <asm/io.h>
-#include <command.h>
#include <display.h>
#include <dm.h>
#include <dm/lists.h>
#include <env.h>
#include <fdt_support.h>
#include <linux/delay.h>
-#include <linux/iopoll.h>
#include <mipi_dsi.h>
#include <mmc.h>
#include <panel.h>
@@ -21,8 +19,6 @@
#include <stdlib.h>
#include <video_bridge.h>
-#define BOOT_BROM_DOWNLOAD 0xef08a53c
-
#define GPIO0_BASE 0xfdd60000
#define GPIO4_BASE 0xfe770000
#define GPIO_SWPORT_DR_L 0x0000
@@ -36,14 +32,6 @@
#define GPIO_WRITEMASK(bits) ((bits) << 16)
-#define SARADC_BASE 0xfe720000
-#define SARADC_DATA 0x0000
-#define SARADC_STAS 0x0004
-#define SARADC_ADC_STATUS BIT(0)
-#define SARADC_CTRL 0x0008
-#define SARADC_INPUT_SRC_MSK 0x7
-#define SARADC_POWER_CTRL BIT(3)
-
#define DTB_DIR "rockchip/"
struct rg3xx_model {
@@ -170,63 +158,11 @@
};
/*
- * The device has internal eMMC, and while some devices have an exposed
- * clk pin you can ground to force a bypass not all devices do. As a
- * result it may be possible for some devices to become a perma-brick
- * if a corrupted TPL or SPL stage with a valid header is flashed to
- * the internal eMMC. Add functionality to read ADC channel 0 (the func
- * button) as early as possible in the boot process to provide some
- * protection against this. If we ever get an open TPL stage, we should
- * consider moving this function there.
- */
-void read_func_button(void)
-{
- int ret;
- u32 reg;
-
- /* Turn off SARADC to reset it. */
- writel(0, (SARADC_BASE + SARADC_CTRL));
-
- /* Enable channel 0 and power on SARADC. */
- writel(((0 & SARADC_INPUT_SRC_MSK) | SARADC_POWER_CTRL),
- (SARADC_BASE + SARADC_CTRL));
-
- /*
- * Wait for data to be ready. Use timeout of 20000us from
- * rockchip_saradc driver.
- */
- ret = readl_poll_timeout((SARADC_BASE + SARADC_STAS), reg,
- !(reg & SARADC_ADC_STATUS), 20000);
- if (ret) {
- printf("ADC Timeout");
- return;
- }
-
- /* Read the data from the SARADC. */
- reg = readl((SARADC_BASE + SARADC_DATA));
-
- /* Turn the SARADC back off so it's ready to be used again. */
- writel(0, (SARADC_BASE + SARADC_CTRL));
-
- /*
- * If the value is less than 30 the button is being pressed.
- * Reset the device back into Rockchip download mode.
- */
- if (reg <= 30) {
- printf("download key pressed, entering download mode...");
- writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG);
- do_reset(NULL, 0, 0, NULL);
- }
-};
-
-/*
* Start LED very early so user knows device is on. Set color
* to red.
*/
void spl_board_init(void)
{
- read_func_button();
-
/* Set GPIO0_C5, GPIO0_C6, and GPIO0_C7 to output. */
writel(GPIO_WRITEMASK(GPIO_C7 | GPIO_C6 | GPIO_C5) | \
(GPIO_C7 | GPIO_C6 | GPIO_C5),
diff --git a/board/armltd/vexpress/MAINTAINERS b/board/armltd/vexpress/MAINTAINERS
index 2b3e491..7a54c6b 100644
--- a/board/armltd/vexpress/MAINTAINERS
+++ b/board/armltd/vexpress/MAINTAINERS
@@ -1,5 +1,5 @@
VERSATILE EXPRESS BOARDS
-M: Kristian Amlie <kristian.amlie@northern.tech>
+M: Josef Holzmayr <josef.holzmayr@northern.tech>
S: Maintained
F: board/armltd/vexpress/
F: include/configs/vexpress_ca9x4.h
diff --git a/board/armsom/sige7-rk3588/Kconfig b/board/armsom/sige7-rk3588/Kconfig
new file mode 100644
index 0000000..793985f
--- /dev/null
+++ b/board/armsom/sige7-rk3588/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SIGE7_RK3588
+
+config SYS_BOARD
+ default "sige7-rk3588"
+
+config SYS_VENDOR
+ default "armsom"
+
+config SYS_CONFIG_NAME
+ default "sige7-rk3588"
+
+endif
diff --git a/board/armsom/sige7-rk3588/MAINTAINERS b/board/armsom/sige7-rk3588/MAINTAINERS
new file mode 100644
index 0000000..0fba39b
--- /dev/null
+++ b/board/armsom/sige7-rk3588/MAINTAINERS
@@ -0,0 +1,7 @@
+SIGE7-RK3588
+M: Jianfeng Liu <liujianfeng1994@gmail.com>
+S: Maintained
+F: board/armsom/sige7-rk3588
+F: include/configs/sige7-rk3588.h
+F: configs/sige7-rk3588_defconfig
+F: arch/arm/dts/rk3588-armsom-sige7*
diff --git a/board/asus/transformer-t20/Kconfig b/board/asus/transformer-t20/Kconfig
new file mode 100644
index 0000000..d5fe412
--- /dev/null
+++ b/board/asus/transformer-t20/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_TRANSFORMER_T20
+
+config SYS_BOARD
+ default "transformer-t20"
+
+config SYS_VENDOR
+ default "asus"
+
+config SYS_CONFIG_NAME
+ default "transformer-t20"
+
+endif
diff --git a/board/asus/transformer-t20/MAINTAINERS b/board/asus/transformer-t20/MAINTAINERS
new file mode 100644
index 0000000..7bf9357
--- /dev/null
+++ b/board/asus/transformer-t20/MAINTAINERS
@@ -0,0 +1,8 @@
+TRANSFORMER T20 BOARD
+M: Svyatoslav Ryhel <clamor95@gmail.com>
+S: Maintained
+F: arch/arm/dts/tegra20-asus-*
+F: board/asus/transformer-t20/
+F: configs/transformer_t20_defconfig
+F: doc/board/asus/transformer_t20.rst
+F: include/configs/transformer-t20.h
diff --git a/board/asus/transformer-t20/Makefile b/board/asus/transformer-t20/Makefile
new file mode 100644
index 0000000..8522f82
--- /dev/null
+++ b/board/asus/transformer-t20/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2010,2011
+# NVIDIA Corporation <www.nvidia.com>
+#
+# (C) Copyright 2021
+# Svyatoslav Ryhel <clamor95@gmail.com>
+
+obj-y += transformer-t20.o
diff --git a/board/asus/transformer-t20/configs/sl101.config b/board/asus/transformer-t20/configs/sl101.config
new file mode 100644
index 0000000..4f639e1
--- /dev/null
+++ b/board/asus/transformer-t20/configs/sl101.config
@@ -0,0 +1 @@
+CONFIG_DEFAULT_DEVICE_TREE="tegra20-asus-sl101"
diff --git a/board/asus/transformer-t20/configs/tf101.config b/board/asus/transformer-t20/configs/tf101.config
new file mode 100644
index 0000000..44a1d1a
--- /dev/null
+++ b/board/asus/transformer-t20/configs/tf101.config
@@ -0,0 +1 @@
+CONFIG_DEFAULT_DEVICE_TREE="tegra20-asus-tf101"
diff --git a/board/asus/transformer-t20/configs/tf101g.config b/board/asus/transformer-t20/configs/tf101g.config
new file mode 100644
index 0000000..0ccf249
--- /dev/null
+++ b/board/asus/transformer-t20/configs/tf101g.config
@@ -0,0 +1 @@
+CONFIG_DEFAULT_DEVICE_TREE="tegra20-asus-tf101g"
diff --git a/board/asus/transformer-t20/transformer-t20.c b/board/asus/transformer-t20/transformer-t20.c
new file mode 100644
index 0000000..42fc563
--- /dev/null
+++ b/board/asus/transformer-t20/transformer-t20.c
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * (C) Copyright 2021
+ * Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+/* T20 Transformers derive from Ventana board */
+
+#include <dm.h>
+#include <i2c.h>
+#include <log.h>
+#include <linux/delay.h>
+
+#define TPS6586X_I2C_ADDRESS 0x34
+#define TPS6586X_SUPPLYENE 0x14
+#define EXITSLREQ_BIT BIT(1)
+#define SLEEP_MODE_BIT BIT(3)
+
+#ifdef CONFIG_CMD_POWEROFF
+int do_poweroff(struct cmd_tbl *cmdtp,
+ int flag, int argc, char *const argv[])
+{
+ struct udevice *dev;
+ uchar data_buffer[1];
+ int ret;
+
+ ret = i2c_get_chip_for_busnum(0, TPS6586X_I2C_ADDRESS, 1, &dev);
+ if (ret) {
+ log_debug("cannot find PMIC I2C chip\n");
+ return 0;
+ }
+
+ ret = dm_i2c_read(dev, TPS6586X_SUPPLYENE, data_buffer, 1);
+ if (ret)
+ return ret;
+
+ data_buffer[0] &= ~EXITSLREQ_BIT;
+
+ ret = dm_i2c_write(dev, TPS6586X_SUPPLYENE, data_buffer, 1);
+ if (ret)
+ return ret;
+
+ data_buffer[0] |= SLEEP_MODE_BIT;
+
+ ret = dm_i2c_write(dev, TPS6586X_SUPPLYENE, data_buffer, 1);
+ if (ret)
+ return ret;
+
+ // wait some time and then print error
+ mdelay(5000);
+ printf("Failed to power off!!!\n");
+ return 1;
+}
+#endif
diff --git a/board/beacon/beacon-rzg2m/MAINTAINERS b/board/beacon/beacon-rzg2m/MAINTAINERS
index f8042bb..a4a920a 100644
--- a/board/beacon/beacon-rzg2m/MAINTAINERS
+++ b/board/beacon/beacon-rzg2m/MAINTAINERS
@@ -1,5 +1,6 @@
BEACON_RZG2M BOARD
M: Adam Ford <aford173@gmail.com>
+M: Marek Vasut <marek.vasut+renesas@mailbox.org>
S: Maintained
F: board/beacon/beacon-rzg2m/
F: include/configs/beacon-rzg2m.h
diff --git a/board/beagle/beagleboneai64/Kconfig b/board/beagle/beagleboneai64/Kconfig
index 7cfccf9..0f21582 100644
--- a/board/beagle/beagleboneai64/Kconfig
+++ b/board/beagle/beagleboneai64/Kconfig
@@ -37,7 +37,7 @@
default "beagle"
config SYS_CONFIG_NAME
- default "j721e_evm"
+ default "beagleboneai64"
source "board/ti/common/Kconfig"
@@ -52,7 +52,7 @@
default "beagle"
config SYS_CONFIG_NAME
- default "j721e_evm"
+ default "beagleboneai64"
source "board/ti/common/Kconfig"
diff --git a/board/beagle/beagleboneai64/beagleboneai64.c b/board/beagle/beagleboneai64/beagleboneai64.c
index c5b4ff7..1e43d1c 100644
--- a/board/beagle/beagleboneai64/beagleboneai64.c
+++ b/board/beagle/beagleboneai64/beagleboneai64.c
@@ -7,6 +7,7 @@
* Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
*/
+#include <efi_loader.h>
#include <cpu_func.h>
#include <env.h>
#include <fdt_support.h>
@@ -14,6 +15,44 @@
DECLARE_GLOBAL_DATA_PTR;
+struct efi_fw_image fw_images[] = {
+ {
+ .image_type_id = BEAGLEBONEAI64_TIBOOT3_IMAGE_GUID,
+ .fw_name = u"BEAGLEBONEAI64_TIBOOT3",
+ .image_index = 1,
+ },
+ {
+ .image_type_id = BEAGLEBONEAI64_SPL_IMAGE_GUID,
+ .fw_name = u"BEAGLEBONEAI64_SPL",
+ .image_index = 2,
+ },
+ {
+ .image_type_id = BEAGLEBONEAI64_UBOOT_IMAGE_GUID,
+ .fw_name = u"BEAGLEBONEAI64_UBOOT",
+ .image_index = 3,
+ },
+ {
+ .image_type_id = BEAGLEBONEAI64_SYSFW_IMAGE_GUID,
+ .fw_name = u"BEAGLEBONEAI64_SYSFW",
+ .image_index = 4,
+ }
+};
+
+struct efi_capsule_update_info update_info = {
+ .dfu_string = "mmc 0=tiboot3.bin raw 0 2000 mmcpart 1;"
+ "tispl.bin fat 0 1;u-boot.img fat 0 1; sysfw.itb fat 0 1",
+ .num_images = ARRAY_SIZE(fw_images),
+ .images = fw_images,
+};
+
+#if IS_ENABLED(CONFIG_SET_DFU_ALT_INFO)
+void set_dfu_alt_info(char *interface, char *devstr)
+{
+ if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT))
+ env_set("dfu_alt_info", update_info.dfu_string);
+}
+#endif
+
int board_init(void)
{
return 0;
diff --git a/board/beagle/beagleplay/Kconfig b/board/beagle/beagleplay/Kconfig
index 7dbd833..592b53e 100644
--- a/board/beagle/beagleplay/Kconfig
+++ b/board/beagle/beagleplay/Kconfig
@@ -12,6 +12,7 @@
bool "BeagleBoard.org AM625 BeaglePlay running on A53"
select ARM64
select BINMAN
+ select OF_SYSTEM_SETUP
config TARGET_AM625_R5_BEAGLEPLAY
bool "BeagleBoard.org AM625 BeaglePlay running on R5"
@@ -35,7 +36,7 @@
default "beagle"
config SYS_CONFIG_NAME
- default "am62x_evm"
+ default "beagleplay"
source "board/ti/common/Kconfig"
@@ -50,7 +51,7 @@
default "beagle"
config SYS_CONFIG_NAME
- default "am62x_evm"
+ default "beagleplay"
config SPL_LDSCRIPT
default "arch/arm/mach-omap2/u-boot-spl.lds"
diff --git a/board/beagle/beagleplay/beagleplay.c b/board/beagle/beagleplay/beagleplay.c
index af36439..a21f09e 100644
--- a/board/beagle/beagleplay/beagleplay.c
+++ b/board/beagle/beagleplay/beagleplay.c
@@ -6,6 +6,7 @@
* Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
*/
+#include <efi_loader.h>
#include <cpu_func.h>
#include <env.h>
#include <fdt_support.h>
@@ -15,6 +16,39 @@
DECLARE_GLOBAL_DATA_PTR;
+struct efi_fw_image fw_images[] = {
+ {
+ .image_type_id = BEAGLEPLAY_TIBOOT3_IMAGE_GUID,
+ .fw_name = u"BEAGLEPLAY_TIBOOT3",
+ .image_index = 1,
+ },
+ {
+ .image_type_id = BEAGLEPLAY_SPL_IMAGE_GUID,
+ .fw_name = u"BEAGLEPLAY_SPL",
+ .image_index = 2,
+ },
+ {
+ .image_type_id = BEAGLEPLAY_UBOOT_IMAGE_GUID,
+ .fw_name = u"BEAGLEPLAY_UBOOT",
+ .image_index = 3,
+ }
+};
+
+struct efi_capsule_update_info update_info = {
+ .dfu_string = "mmc 0=tiboot3.bin raw 0 2000 mmcpart 1;"
+ "tispl.bin fat 0 1;u-boot.img fat 0 1",
+ .num_images = ARRAY_SIZE(fw_images),
+ .images = fw_images,
+};
+
+#if IS_ENABLED(CONFIG_SET_DFU_ALT_INFO)
+void set_dfu_alt_info(char *interface, char *devstr)
+{
+ if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT))
+ env_set("dfu_alt_info", update_info.dfu_string);
+}
+#endif
+
int board_init(void)
{
return 0;
diff --git a/board/beagle/beagleplay/beagleplay.env b/board/beagle/beagleplay/beagleplay.env
index 8dbfc2f..354bc98 100644
--- a/board/beagle/beagleplay/beagleplay.env
+++ b/board/beagle/beagleplay/beagleplay.env
@@ -12,7 +12,7 @@
led led-2 on; led led-3 off; led led-4 on
boot=mmc
mmcdev=1
-bootpart=1:1
+bootpart=1:2
bootdir=/boot
boot_targets=mmc1 mmc0
bootmeths=script extlinux efi pxe
diff --git a/board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c b/board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c
index 0da6418..33452d2 100644
--- a/board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c
+++ b/board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c
@@ -18,15 +18,15 @@
{ 0x3d400304, 0x1 },
{ 0x3d400030, 0x20 },
{ 0x3d400000, 0xa1040001 },
- { 0x3d400064, 0x610040 },
+ { 0x3d400064, 0x300040 },
{ 0x3d4000d0, 0xc00200c5 },
{ 0x3d4000d4, 0x1000b },
{ 0x3d4000dc, 0x1d700004 },
- { 0x3d4000e0, 0x180000 },
+ { 0x3d4000e0, 0x580000 },
{ 0x3d4000e4, 0x90000 },
- { 0x3d4000f0, 0x0 },
+ { 0x3d4000f0, 0x2 },
{ 0x3d4000f4, 0xee5 },
- { 0x3d400100, 0xc101b0e },
+ { 0x3d400100, 0xc100d0e },
{ 0x3d400104, 0x30314 },
{ 0x3d400108, 0x4060509 },
{ 0x3d40010c, 0x2006 },
@@ -67,10 +67,10 @@
{ 0x3d400498, 0x7ff },
{ 0x3d40049c, 0xe00 },
{ 0x3d4004a0, 0x7ff },
- { 0x3d402064, 0x28001b },
+ { 0x3d402064, 0x14001b },
{ 0x3d4020dc, 0x12200004 },
- { 0x3d4020e0, 0x0 },
- { 0x3d402100, 0x7090b07 },
+ { 0x3d4020e0, 0x400000 },
+ { 0x3d402100, 0x7090507 },
{ 0x3d402104, 0x20209 },
{ 0x3d402108, 0x3030407 },
{ 0x3d40210c, 0x2006 },
@@ -680,12 +680,13 @@
{ 0x54006, 0x140 },
{ 0x54007, 0x1000 },
{ 0x54008, 0x101 },
+ { 0x54009, 0x200 },
{ 0x5400b, 0x31f },
{ 0x5400c, 0xc8 },
{ 0x54012, 0x1 },
{ 0x5402f, 0x1d70 },
{ 0x54030, 0x4 },
- { 0x54031, 0x18 },
+ { 0x54031, 0x58 },
{ 0x5403a, 0x1323 },
{ 0xd0000, 0x1 },
};
@@ -700,11 +701,13 @@
{ 0x54006, 0x140 },
{ 0x54007, 0x1000 },
{ 0x54008, 0x101 },
+ { 0x54009, 0x200 },
{ 0x5400b, 0x21f },
{ 0x5400c, 0xc8 },
{ 0x54012, 0x1 },
{ 0x5402f, 0x1220 },
{ 0x54030, 0x4 },
+ { 0x54031, 0x40 },
{ 0x5403a, 0x1323 },
{ 0xd0000, 0x1 },
};
@@ -886,11 +889,11 @@
{ 0xd00e7, 0x400 },
{ 0x90017, 0x0 },
{ 0x90026, 0x2b },
- { 0x2000b, 0x32 },
+ { 0x2000b, 0x1c2 },
{ 0x2000c, 0x64 },
{ 0x2000d, 0x3e8 },
{ 0x2000e, 0x2c },
- { 0x12000b, 0x14 },
+ { 0x12000b, 0xbb },
{ 0x12000c, 0x26 },
{ 0x12000d, 0x1a1 },
{ 0x12000e, 0x10 },
diff --git a/board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c b/board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c
index f845395..ca14a47 100644
--- a/board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c
+++ b/board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c
@@ -18,15 +18,15 @@
{ 0x3d400304, 0x1 },
{ 0x3d400030, 0x20 },
{ 0x3d400000, 0xa1040001 },
- { 0x3d400064, 0x610068 },
+ { 0x3d400064, 0x300068 },
{ 0x3d4000d0, 0xc00200c5 },
{ 0x3d4000d4, 0x1000b },
{ 0x3d4000dc, 0x1d700004 },
- { 0x3d4000e0, 0x180000 },
+ { 0x3d4000e0, 0x580000 },
{ 0x3d4000e4, 0x90000 },
- { 0x3d4000f0, 0x0 },
+ { 0x3d4000f0, 0x2 },
{ 0x3d4000f4, 0xee5 },
- { 0x3d400100, 0xc101b0e },
+ { 0x3d400100, 0xc100d0e },
{ 0x3d400104, 0x30314 },
{ 0x3d400108, 0x4060509 },
{ 0x3d40010c, 0x2006 },
@@ -700,11 +700,13 @@
{ 0x54006, 0x140 },
{ 0x54007, 0x1000 },
{ 0x54008, 0x101 },
+ { 0x54009, 0x200 },
{ 0x5400b, 0x21f },
{ 0x5400c, 0xc8 },
{ 0x54012, 0x1 },
{ 0x5402f, 0x1220 },
{ 0x54030, 0x4 },
+ { 0x54031, 0x40 },
{ 0x5403a, 0x1323 },
{ 0xd0000, 0x1 },
};
@@ -886,11 +888,11 @@
{ 0xd00e7, 0x400 },
{ 0x90017, 0x0 },
{ 0x90026, 0x2b },
- { 0x2000b, 0x32 },
+ { 0x2000b, 0x1c2 },
{ 0x2000c, 0x64 },
{ 0x2000d, 0x3e8 },
{ 0x2000e, 0x2c },
- { 0x12000b, 0x14 },
+ { 0x12000b, 0xbb },
{ 0x12000c, 0x26 },
{ 0x12000d, 0x1a1 },
{ 0x12000e, 0x10 },
diff --git a/board/cadence/xtfpga/xtfpga.c b/board/cadence/xtfpga/xtfpga.c
index 5110fed..6b92fe3 100644
--- a/board/cadence/xtfpga/xtfpga.c
+++ b/board/cadence/xtfpga/xtfpga.c
@@ -66,6 +66,11 @@
#endif
}
+int dram_init(void)
+{
+ return 0;
+}
+
int board_postclk_init(void)
{
gd->cpu_clk = get_board_sys_clk();
diff --git a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c
index 99d3bf3..6a3d816 100644
--- a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c
+++ b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c
@@ -46,7 +46,9 @@
static const struct lpddr4_desc lpddr4_array[] = {
{ .name = "Nanya", .id = 0x05000010, .subind = 0xff,
.size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010},
- { .name = "Samsung", .id = 0x01061010, .subind = 0xff,
+ { .name = "Samsung", .id = 0x01061010, .subind = 0x04,
+ .size = 4096, .count = 1, .timing = &ucm_dram_timing_ff000110},
+ { .name = "Samsung", .id = 0x01061010, .subind = 0x02,
.size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010},
{ .name = "Kingston", .id = 0xff000010, .subind = 0x04,
.size = 4096, .count = 1, .timing = &ucm_dram_timing_ff000110},
diff --git a/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c b/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c
index ba15873..bda7aac 100644
--- a/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c
+++ b/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c
@@ -8,6 +8,7 @@
#include <efi_loader.h>
#include <env.h>
#include <extension_board.h>
+#include <fdt_support.h>
#include <hang.h>
#include <i2c.h>
#include <init.h>
@@ -30,6 +31,8 @@
DECLARE_GLOBAL_DATA_PTR;
+static int fec_phyaddr = -1;
+
#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
struct efi_fw_image fw_images[] = {
#if defined(CONFIG_TARGET_IMX8MM_CL_IOT_GATE)
@@ -109,10 +112,72 @@
return 0;
}
+#define FDT_PHYADDR "/soc@0/bus@30800000/ethernet@30be0000/mdio/ethernet-phy@0"
+#define FLIP_32B(val) (((val >> 24) & 0xff) | ((val << 8) & 0xff0000) | ((val >> 8) & 0xff00) | ((val << 24) & 0xff000000))
+static int fdt_set_fec_phy_addr(void *blob)
+{
+ u32 val;
+
+ if (fec_phyaddr < 0)
+ return -EINVAL;
+
+ val = FLIP_32B(fec_phyaddr);
+ return fdt_find_and_setprop(blob, FDT_PHYADDR, "reg", (const void *)&val,
+ sizeof(val), 0);
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ fdt_set_fec_phy_addr(blob);
+ return 0;
+}
+
+/*
+ * These are specific ID, purposed to distiguish between PHY vendors.
+ * These values are not equal to real vendors' OUI (half of MAC address)
+ */
+#define OUI_PHY_ATHEROS 0x1374
+#define OUI_PHY_REALTEK 0x0732
+
int board_phy_config(struct phy_device *phydev)
{
- if (IS_ENABLED(CONFIG_FEC_MXC)) {
+ unsigned int model, rev, oui;
+ int phyid1, phyid2;
+ unsigned int reg;
+
+ if (!IS_ENABLED(CONFIG_FEC_MXC))
+ return 0;
+
+ phyid1 = phy_read(phydev, MDIO_DEVAD_NONE, MII_PHYSID1);
+ if (phyid1 < 0) {
+ printf("%s: PHYID1 registry read fail %i\n", __func__, phyid1);
+ return phyid1;
+ }
+
+ phyid2 = phy_read(phydev, MDIO_DEVAD_NONE, MII_PHYSID2);
+ if (phyid2 < 0) {
+ printf("%s: PHYID2 registry read fail %i\n", __func__, phyid2);
+ return phyid2;
+ }
+
+ reg = phyid2 | phyid1 << 16;
+ if (reg == 0xffff) {
+ printf("%s: There is no device @%i\n", __func__, phydev->addr);
+ return -ENODEV;
+ }
+
+ rev = reg & 0xf;
+ reg >>= 4;
+ model = reg & 0x3f;
+ reg >>= 6;
+ oui = reg;
+ debug("%s: PHY @0x%x OUI 0x%06x model 0x%x rev 0x%x\n",
+ __func__, phydev->addr, oui, model, rev);
+
+ switch (oui) {
+ case OUI_PHY_ATHEROS:
/* enable rgmii rxc skew and phy mode select to RGMII copper */
+ printf("phy: AR803x@%x\t", phydev->addr);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
@@ -120,10 +185,45 @@
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+ break;
+ case OUI_PHY_REALTEK:
+ printf("phy: RTL8211E@%x\t", phydev->addr);
+ /* RTL8211E-VB-CG - add TX and RX delay */
+ unsigned short val;
- if (phydev->drv->config)
- phydev->drv->config(phydev);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x07);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0xa4);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1c);
+ val |= (0x1 << 13) | (0x1 << 12) | (0x1 << 11);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1c, val);
+ /* LEDs: set to extension page */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x0007);
+ /* extension Page44 */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x002c);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1c, 0x0430);//LCR
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1a, 0x0010);//LACR
+ /*
+ * To disable EEE LED mode (blinking .4s/2s)
+ * Extension Page5
+ */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x0005);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x05, 0x8b82);//magic const
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x06, 0x052b);//magic const
+
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x00);// Back to Page0
+
+ break;
+ default:
+ printf("%s: ERROR: unknown PHY @0x%x OUI 0x%06x model 0x%x rev 0x%x\n",
+ __func__, phydev->addr, oui, model, rev);
+ return -ENOSYS;
}
+
+ fec_phyaddr = phydev->addr;
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
return 0;
}
diff --git a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
index 7e0f09f..56d6f4f 100644
--- a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
+++ b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
@@ -46,12 +46,7 @@
} >.sram
__image_copy_end = .;
-
- .end :
- {
- *(.__end)
- }
-
+ _end = .;
_image_binary_end = .;
.bss :
diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c
index 20c9d70..4f4f537 100644
--- a/board/dhelectronics/dh_stm32mp1/board.c
+++ b/board/dhelectronics/dh_stm32mp1/board.c
@@ -37,6 +37,7 @@
#include <power/regulator.h>
#include <remoteproc.h>
#include <reset.h>
+#include <spl.h>
#include <syscon.h>
#include <usb.h>
#include <usb/dwc2_udc.h>
@@ -75,16 +76,27 @@
static bool dh_stm32_mac_is_in_ks8851(void)
{
- ofnode node;
+ struct udevice *udev;
u32 reg, cider, ccr;
+ char path[256];
+ ofnode node;
+ int ret;
node = ofnode_path("ethernet1");
if (!ofnode_valid(node))
return false;
- if (ofnode_device_is_compatible(node, "micrel,ks8851-mll"))
+ ret = ofnode_get_path(node, path, sizeof(path));
+ if (ret)
return false;
+ ret = uclass_get_device_by_of_path(UCLASS_ETH, path, &udev);
+ if (ret)
+ return false;
+
+ if (!ofnode_device_is_compatible(node, "micrel,ks8851-mll"))
+ return false;
+
/*
* KS8851 with EEPROM may use custom MAC from EEPROM, read
* out the KS8851 CCR register to determine whether EEPROM
@@ -672,12 +684,69 @@
#endif
}
+static void dh_stm32_ks8851_fixup(void *blob)
+{
+ struct gpio_desc ks8851intrn;
+ bool compatible = false;
+ int ks8851intrn_value;
+ const char *prop;
+ ofnode node;
+ int idx = 0;
+ int offset;
+ int ret;
+
+ /* Do nothing if not STM32MP15xx DHCOM SoM */
+ while ((prop = fdt_stringlist_get(blob, 0, "compatible", idx++, NULL))) {
+ if (!strstr(prop, "dhcom-som"))
+ continue;
+ compatible = true;
+ break;
+ }
+
+ if (!compatible)
+ return;
+
+ /*
+ * Read state of INTRN pull up resistor, if this pull up is populated,
+ * KS8851-16MLL is populated as well and should be enabled, otherwise
+ * it should be disabled.
+ */
+ node = ofnode_path("/config");
+ if (!ofnode_valid(node))
+ return;
+
+ ret = gpio_request_by_name_nodev(node, "dh,mac-coding-gpios", 0,
+ &ks8851intrn, GPIOD_IS_IN);
+ if (ret)
+ return;
+
+ ks8851intrn_value = dm_gpio_get_value(&ks8851intrn);
+
+ dm_gpio_free(NULL, &ks8851intrn);
+
+ /* Set the 'status' property into KS8851-16MLL DT node. */
+ offset = fdt_path_offset(blob, "ethernet1");
+ ret = fdt_node_check_compatible(blob, offset, "micrel,ks8851-mll");
+ if (ret) /* Not compatible */
+ return;
+
+ /* Add a bit of extra space for new 'status' property */
+ ret = fdt_shrink_to_minimum(blob, 4096);
+ if (!ret)
+ return;
+
+ fdt_setprop_string(blob, offset, "status",
+ ks8851intrn_value ? "okay" : "disabled");
+}
+
#if defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
{
const char *buck3path = "/soc/i2c@5c002000/stpmic@33/regulators/buck3";
int buck3off, ret, uv;
+ dh_stm32_ks8851_fixup(blob);
+
ret = board_get_regulator_buck3_nvm_uv_av96(&uv);
if (ret) /* Not Avenger96 board, do not patch Buck3 in DT. */
return 0;
@@ -698,6 +767,13 @@
}
#endif
+#if defined(CONFIG_SPL_BUILD)
+void spl_perform_fixups(struct spl_image_info *spl_image)
+{
+ dh_stm32_ks8851_fixup(spl_image_fdt_addr(spl_image));
+}
+#endif
+
static void board_copro_image_process(ulong fw_image, size_t fw_size)
{
int ret, id = 0; /* Copro id fixed to 0 as only one coproc on mp1 */
diff --git a/board/emulation/qemu-xtensa/Kconfig b/board/emulation/qemu-xtensa/Kconfig
new file mode 100644
index 0000000..8767b6f
--- /dev/null
+++ b/board/emulation/qemu-xtensa/Kconfig
@@ -0,0 +1,43 @@
+if TARGET_QEMU_XTENSA
+
+config SYS_BOARD
+ default "qemu-xtensa"
+
+config SYS_VENDOR
+ default "emulation"
+
+config SYS_CONFIG_NAME
+ default "qemu-xtensa"
+
+config TEXT_BASE
+ default 0x50000000 if (SYS_CPU = de212)
+ default 0xfe000000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select BOARD_EARLY_INIT_F
+ select DM
+ select CPU
+ select CPU_XTENSA
+ select CLK
+ select DM_SERIAL
+ select XTENSA_SEMIHOSTING
+ select XTENSA_SEMIHOSTING_SERIAL
+ imply BLK
+ imply VIRTIO
+ imply VIRTIO_PCI
+ imply VIRTIO_NET
+ imply VIRTIO_BLK
+ imply E1000
+ imply PCI
+ imply PCI_INIT_R
+ imply NVME_PCI
+ imply PCIE_ECAM_GENERIC
+ imply SCSI
+ imply REMAKE_ELF
+ select OF_CONTROL
+ select OF_UPSTREAM
+ imply CMD_DM
+ imply CMD_PCI
+
+endif
diff --git a/board/emulation/qemu-xtensa/MAINTAINERS b/board/emulation/qemu-xtensa/MAINTAINERS
new file mode 100644
index 0000000..6ffdfe8
--- /dev/null
+++ b/board/emulation/qemu-xtensa/MAINTAINERS
@@ -0,0 +1,8 @@
+QEMU XTENSA 'VIRT' BOARD
+M: Jiaxun Yang <jiaxun.yang@flygoat.com>
+M: Max Filippov <jcmvbkbc@gmail.com>
+S: Maintained
+F: board/emulation/qemu-xtensa/
+F: board/emulation/common/
+F: include/configs/qemu-xtensa.h
+F: configs/qemu-xtensa-dc233c_defconfig
diff --git a/board/emulation/qemu-xtensa/Makefile b/board/emulation/qemu-xtensa/Makefile
new file mode 100644
index 0000000..0f33a65
--- /dev/null
+++ b/board/emulation/qemu-xtensa/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2024, Jiaxun Yang <jiaxun.yang@flygoat.com>
+
+obj-y += qemu-xtensa.o
diff --git a/board/emulation/qemu-xtensa/qemu-xtensa.c b/board/emulation/qemu-xtensa/qemu-xtensa.c
new file mode 100644
index 0000000..0ca8334
--- /dev/null
+++ b/board/emulation/qemu-xtensa/qemu-xtensa.c
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <dm.h>
+#include <cpu.h>
+#include <log.h>
+#include <init.h>
+#include <usb.h>
+#include <virtio_types.h>
+#include <virtio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ return gd->cpu_clk ? gd->cpu_clk : 40000000;
+}
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+int board_early_init_f(void)
+{
+ struct cpu_plat *cpu_plat;
+ struct udevice *cpu = cpu_get_current_dev();
+
+ if (!cpu)
+ return -ENODEV;
+
+ cpu_plat = dev_get_parent_plat(cpu);
+ if (!cpu_plat)
+ return -ENODEV;
+
+ gd->cpu_clk = cpu_plat->timebase_freq;
+ return 0;
+}
+
+int board_late_init(void)
+{
+ /* start usb so that usb keyboard can be used as input device */
+ if (CONFIG_IS_ENABLED(USB_KEYBOARD))
+ usb_init();
+
+ /*
+ * Make sure virtio bus is enumerated so that peripherals
+ * on the virtio bus can be discovered by their drivers
+ */
+ virtio_init();
+
+ return 0;
+}
diff --git a/board/freescale/common/cmd_esbc_validate.c b/board/freescale/common/cmd_esbc_validate.c
index d4192e5..3344653 100644
--- a/board/freescale/common/cmd_esbc_validate.c
+++ b/board/freescale/common/cmd_esbc_validate.c
@@ -63,14 +63,14 @@
}
/***************************************************/
-static char esbc_validate_help_text[] =
+U_BOOT_LONGHELP(esbc_validate,
"esbc_validate hdr_addr <hash_val> - Validates signature using\n"
" RSA verification\n"
" $hdr_addr Address of header of the image\n"
" to be validated.\n"
" $hash_val -Optional\n"
" It provides Hash of public/srk key to be\n"
- " used to verify signature.\n";
+ " used to verify signature.\n");
U_BOOT_CMD(
esbc_validate, 3, 0, do_esbc_validate,
diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c
index f10d310..e9cdede 100644
--- a/board/gateworks/venice/spl.c
+++ b/board/gateworks/venice/spl.c
@@ -118,13 +118,29 @@
return dm_i2c_write(dev, reg, &val, 1);
}
-static int power_init_board(void)
+static int power_init_board(struct udevice *gsc)
{
const char *model = eeprom_get_model();
struct udevice *bus;
struct udevice *dev;
int ret;
+ /* Enable GSC voltage supervisor for new board models */
+ if ((!strncmp(model, "GW7100", 6) && model[10] > 'D') ||
+ (!strncmp(model, "GW7101", 6) && model[10] > 'D') ||
+ (!strncmp(model, "GW7200", 6) && model[10] > 'E') ||
+ (!strncmp(model, "GW7201", 6) && model[10] > 'E') ||
+ (!strncmp(model, "GW7300", 6) && model[10] > 'E') ||
+ (!strncmp(model, "GW7301", 6) && model[10] > 'E') ||
+ (!strncmp(model, "GW740", 5) && model[7] > 'B')) {
+ u8 ver;
+
+ if (!dm_i2c_read(gsc, 14, &ver, 1) && ver > 62) {
+ printf("GSC : enabling voltage supervisor\n");
+ dm_i2c_clrsetbits(gsc, 25, 0, BIT(1));
+ }
+ }
+
if ((!strncmp(model, "GW71", 4)) ||
(!strncmp(model, "GW72", 4)) ||
(!strncmp(model, "GW73", 4)) ||
@@ -286,6 +302,7 @@
mdelay(10);
}
pinctrl_select_state(bus, "default");
+ mdelay(10);
}
}
/* Wait indefiniately until the GSC probes */
@@ -297,7 +314,7 @@
dram_sz = venice_eeprom_init(0);
/* PMIC */
- power_init_board();
+ power_init_board(dev);
/* DDR initialization */
spl_dram_init(dram_sz);
diff --git a/board/gateworks/venice/venice.c b/board/gateworks/venice/venice.c
index 5b105d7..d4c2212 100644
--- a/board/gateworks/venice/venice.c
+++ b/board/gateworks/venice/venice.c
@@ -45,22 +45,6 @@
return -1;
}
-static int __maybe_unused setup_fec(void)
-{
- struct iomuxc_gpr_base_regs *gpr =
- (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
-
-#ifndef CONFIG_IMX8MP
- /* Use 125M anatop REF_CLK1 for ENET1, not from external */
- clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
-#else
- /* Enable RGMII TX clk output */
- setbits_le32(&gpr->gpr[1], BIT(22));
-#endif
-
- return 0;
-}
-
#if (IS_ENABLED(CONFIG_NET))
int board_phy_config(struct phy_device *phydev)
{
@@ -75,6 +59,9 @@
val |= 0xb << 8; /* LED2(Green;Link/Act): blink for TX/RX act */
phy_write(phydev, MDIO_DEVAD_NONE, 24, val);
break;
+ case 0xd565a401: /* MaxLinear GPY111 */
+ puts("GPY111 ");
+ break;
}
if (phydev->drv->config)
@@ -88,9 +75,6 @@
{
venice_eeprom_init(1);
- if (IS_ENABLED(CONFIG_FEC_MXC))
- setup_fec();
-
return 0;
}
diff --git a/board/google/veyron/veyron.c b/board/google/veyron/veyron.c
index 53c3435..bd8ce63 100644
--- a/board/google/veyron/veyron.c
+++ b/board/google/veyron/veyron.c
@@ -28,44 +28,38 @@
int ret;
ret = regulator_get_by_platname("vdd_arm", &dev);
- if (ret) {
- debug("Cannot set regulator name\n");
- return ret;
- }
+ if (ret)
+ return log_msg_ret("vdd", ret);
/* Slowly raise to max CPU voltage to prevent overshoot */
ret = regulator_set_value(dev, 1200000);
if (ret)
- return ret;
+ return log_msg_ret("s12", ret);
udelay(175); /* Must wait for voltage to stabilize, 2mV/us */
ret = regulator_set_value(dev, 1400000);
if (ret)
- return ret;
+ return log_msg_ret("s14", ret);
udelay(100); /* Must wait for voltage to stabilize, 2mV/us */
ret = rockchip_get_clk(&clk.dev);
if (ret)
- return ret;
+ return log_msg_ret("clk", ret);
clk.id = PLL_APLL;
ret = clk_set_rate(&clk, 1800000000);
if (IS_ERR_VALUE(ret))
- return ret;
+ return log_msg_ret("s18", ret);
ret = regulator_get_by_platname("vcc33_sd", &dev);
- if (ret) {
- debug("Cannot get regulator name\n");
- return ret;
- }
+ if (ret)
+ return log_msg_ret("vcc", ret);
ret = regulator_set_value(dev, 3300000);
if (ret)
- return ret;
+ return log_msg_ret("s33", ret);
ret = regulators_enable_boot_on(false);
- if (ret) {
- debug("%s: Cannot enable boot on regulators\n", __func__);
- return ret;
- }
+ if (ret)
+ return log_msg_ret("boo", ret);
return 0;
}
@@ -80,7 +74,7 @@
if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) {
ret = veyron_init();
if (ret)
- return ret;
+ return log_msg_ret("vey", ret);
}
#endif
/*
diff --git a/board/hardkernel/odroid_go2/MAINTAINERS b/board/hardkernel/odroid_go2/MAINTAINERS
index 4d4c6e8..9e83bc9 100644
--- a/board/hardkernel/odroid_go2/MAINTAINERS
+++ b/board/hardkernel/odroid_go2/MAINTAINERS
@@ -1,5 +1,5 @@
GO2
-M: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
+M: Heiko Stuebner <heiko.stuebner@cherry.de>
S: Maintained
F: board/hardkernel/odroid_go2/
F: include/configs/odroid_go2.h
diff --git a/board/indiedroid/nova/Kconfig b/board/indiedroid/nova/Kconfig
new file mode 100644
index 0000000..271d15a
--- /dev/null
+++ b/board/indiedroid/nova/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_NOVA_RK3588
+
+config SYS_BOARD
+ default "nova-rk3588s"
+
+config SYS_VENDOR
+ default "indiedroid"
+
+config SYS_CONFIG_NAME
+ default "nova-rk3588s"
+
+endif
diff --git a/board/indiedroid/nova/MAINTAINERS b/board/indiedroid/nova/MAINTAINERS
new file mode 100644
index 0000000..db1f115
--- /dev/null
+++ b/board/indiedroid/nova/MAINTAINERS
@@ -0,0 +1,6 @@
+INDIEDROID-NOVA-RK3588
+M: Chris Morgan <macromorgan@hotmail.com>
+S: Maintained
+F: board/indiedroid/nova
+F: configs/nova-rk3588s_defconfig
+F: include/configs/nova-rk3588s.h
diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c
index 8a3f290..a35a7cd 100644
--- a/board/isee/igep00x0/igep00x0.c
+++ b/board/isee/igep00x0/igep00x0.c
@@ -29,18 +29,6 @@
#include <fdt_support.h>
#include "igep00x0.h"
-static const struct ns16550_plat igep_serial = {
- .base = OMAP34XX_UART3,
- .reg_shift = 2,
- .clock = V_NS16550_CLK,
- .fcr = UART_FCR_DEFVAL,
-};
-
-U_BOOT_DRVINFO(igep_uart) = {
- "ns16550_serial",
- &igep_serial
-};
-
/*
* Routine: get_board_revision
* Description: GPIO_28 and GPIO_129 are used to read board and revision from
diff --git a/board/kontron/sl28/cmds.c b/board/kontron/sl28/cmds.c
index 7851361..0751477 100644
--- a/board/kontron/sl28/cmds.c
+++ b/board/kontron/sl28/cmds.c
@@ -172,8 +172,8 @@
return CMD_RET_FAILURE;
}
-static char sl28_help_text[] =
- "nvm [<hex>] - display/set the 16 non-volatile bits\n";
+U_BOOT_LONGHELP(sl28,
+ "nvm [<hex>] - display/set the 16 non-volatile bits\n");
U_BOOT_CMD_WITH_SUBCMDS(sl28, "SMARC-sAL28 specific", sl28_help_text,
U_BOOT_SUBCMD_MKENT(nvm, 2, 1, do_sl28_nvm));
diff --git a/board/lenovo/ideapad-yoga-11/Kconfig b/board/lenovo/ideapad-yoga-11/Kconfig
new file mode 100644
index 0000000..6764440
--- /dev/null
+++ b/board/lenovo/ideapad-yoga-11/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_IDEAPAD_YOGA_11
+
+config SYS_BOARD
+ default "ideapad-yoga-11"
+
+config SYS_VENDOR
+ default "lenovo"
+
+config SYS_CONFIG_NAME
+ default "ideapad-yoga-11"
+
+endif
diff --git a/board/lenovo/ideapad-yoga-11/MAINTAINERS b/board/lenovo/ideapad-yoga-11/MAINTAINERS
new file mode 100644
index 0000000..77e8253
--- /dev/null
+++ b/board/lenovo/ideapad-yoga-11/MAINTAINERS
@@ -0,0 +1,7 @@
+Lenovo Ideapad Yoga 11
+M: Jonas Schwöbel <jonasschwoebel@yahoo.de>
+S: Maintained
+F: board/lenovo/ideapad-yoga-11/
+F: configs/ideapad-yoga-11_defconfig
+F: doc/board/lenovo/ideapad-yoga-11.rst
+F: include/configs/ideapad-yoga-11.h
diff --git a/board/lenovo/ideapad-yoga-11/Makefile b/board/lenovo/ideapad-yoga-11/Makefile
new file mode 100644
index 0000000..186f1cb
--- /dev/null
+++ b/board/lenovo/ideapad-yoga-11/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022
+# Open Surface RT
+
+obj-$(CONFIG_SPL_BUILD) += ideapad-yoga-11-spl.o
diff --git a/board/lenovo/ideapad-yoga-11/ideapad-yoga-11-spl.c b/board/lenovo/ideapad-yoga-11/ideapad-yoga-11-spl.c
new file mode 100644
index 0000000..b8b3964
--- /dev/null
+++ b/board/lenovo/ideapad-yoga-11/ideapad-yoga-11-spl.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Ideapad Yoga 11 SPL stage configuration
+ *
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * (C) Copyright 2021
+ * Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include <linux/delay.h>
+
+#define TPS65911_I2C_ADDR (0x2D << 1)
+#define TPS65911_VDDCTRL_OP_REG 0x28
+#define TPS65911_VDDCTRL_SR_REG 0x27
+#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG)
+#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG)
+
+#define TPS62361B_I2C_ADDR (0x60 << 1)
+#define TPS62361B_SET2_REG 0x02
+#define TPS62361B_SET2_DATA (0x4600 | TPS62361B_SET2_REG)
+
+void pmic_enable_cpu_vdd(void)
+{
+ /* Set VDD_CORE to 1.200V. */
+ tegra_i2c_ll_write(TPS62361B_I2C_ADDR, TPS62361B_SET2_DATA);
+
+ udelay(1000);
+
+ /*
+ * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
+ * First set VDD to 1.0125V, then enable the VDD regulator.
+ */
+ tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_OP_DATA);
+ udelay(1000);
+ tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_SR_DATA);
+ udelay(10 * 1000);
+}
diff --git a/board/microchip/mpfs_icicle/MAINTAINERS b/board/microchip/mpfs_icicle/MAINTAINERS
index 22f3b97..d092b5a 100644
--- a/board/microchip/mpfs_icicle/MAINTAINERS
+++ b/board/microchip/mpfs_icicle/MAINTAINERS
@@ -1,5 +1,5 @@
Microchip MPFS icicle
-M: Padmarao Begari <padmarao.begari@microchip.com>
+M: Conor Dooley <conor.dooley@microchip.com>
M: Cyril Jean <cyril.jean@microchip.com>
S: Maintained
F: board/microchip/mpfs_icicle/
diff --git a/board/microchip/mpfs_icicle/mpfs_icicle.c b/board/microchip/mpfs_icicle/mpfs_icicle.c
index 7beac33..4d7d843 100644
--- a/board/microchip/mpfs_icicle/mpfs_icicle.c
+++ b/board/microchip/mpfs_icicle/mpfs_icicle.c
@@ -72,25 +72,13 @@
int board_late_init(void)
{
u32 ret;
- u32 node;
+ int node;
u8 idx;
u8 device_serial_number[16] = { 0 };
unsigned char mac_addr[6];
char icicle_mac_addr[20];
void *blob = (void *)gd->fdt_blob;
- node = fdt_path_offset(blob, "/soc/ethernet@20112000");
- if (node < 0) {
- printf("No ethernet0 path offset\n");
- return -ENODEV;
- }
-
- ret = fdtdec_get_byte_array(blob, node, "local-mac-address", mac_addr, 6);
- if (ret) {
- printf("No local-mac-address property for ethernet@20112000\n");
- return -EINVAL;
- }
-
read_device_serial_number(device_serial_number, 16);
/* Update MAC address with device serial number */
@@ -101,10 +89,13 @@
mac_addr[4] = device_serial_number[1];
mac_addr[5] = device_serial_number[0];
- ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6);
- if (ret) {
- printf("Error setting local-mac-address property for ethernet@20112000\n");
- return -ENODEV;
+ node = fdt_path_offset(blob, "/soc/ethernet@20112000");
+ if (node >= 0) {
+ ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6);
+ if (ret) {
+ printf("Error setting local-mac-address property for ethernet@20112000\n");
+ return -ENODEV;
+ }
}
icicle_mac_addr[0] = '[';
diff --git a/board/microsoft/surface-rt/Kconfig b/board/microsoft/surface-rt/Kconfig
new file mode 100644
index 0000000..9e66897
--- /dev/null
+++ b/board/microsoft/surface-rt/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SURFACE_RT
+
+config SYS_BOARD
+ default "surface-rt"
+
+config SYS_VENDOR
+ default "microsoft"
+
+config SYS_CONFIG_NAME
+ default "surface-rt"
+
+endif
diff --git a/board/microsoft/surface-rt/MAINTAINERS b/board/microsoft/surface-rt/MAINTAINERS
new file mode 100644
index 0000000..1bbd896
--- /dev/null
+++ b/board/microsoft/surface-rt/MAINTAINERS
@@ -0,0 +1,7 @@
+Microsoft Surface RT
+M: Jonas Schwöbel <jonasschwoebel@yahoo.de>
+S: Maintained
+F: board/microsoft/surface-rt/
+F: configs/surface-rt_defconfig
+F: doc/board/microsoft/surface-rt.rst
+F: include/configs/surface-rt.h
diff --git a/board/microsoft/surface-rt/Makefile b/board/microsoft/surface-rt/Makefile
new file mode 100644
index 0000000..da4094a
--- /dev/null
+++ b/board/microsoft/surface-rt/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2021
+# Open Surface RT
+
+obj-$(CONFIG_SPL_BUILD) += surface-rt-spl.o
diff --git a/board/microsoft/surface-rt/surface-rt-spl.c b/board/microsoft/surface-rt/surface-rt-spl.c
new file mode 100644
index 0000000..f327a80
--- /dev/null
+++ b/board/microsoft/surface-rt/surface-rt-spl.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Surface RT SPL stage configuration
+ *
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * (C) Copyright 2021
+ * Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include <linux/delay.h>
+
+#define TPS65911_I2C_ADDR (0x2D << 1)
+#define TPS65911_VDDCTRL_OP_REG 0x28
+#define TPS65911_VDDCTRL_SR_REG 0x27
+#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG)
+#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG)
+
+#define TPS62361B_I2C_ADDR (0x60 << 1)
+#define TPS62361B_SET3_REG 0x03
+#define TPS62361B_SET3_DATA (0x4600 | TPS62361B_SET3_REG)
+
+void pmic_enable_cpu_vdd(void)
+{
+ /* Set VDD_CORE to 1.200V. */
+ tegra_i2c_ll_write(TPS62361B_I2C_ADDR, TPS62361B_SET3_DATA);
+
+ udelay(1000);
+
+ /*
+ * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
+ * First set VDD to 1.0125V, then enable the VDD regulator.
+ */
+ tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_OP_DATA);
+ udelay(1000);
+ tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_SR_DATA);
+ udelay(10 * 1000);
+}
diff --git a/board/phytec/common/Kconfig b/board/phytec/common/Kconfig
index 1077f0f..f394ace 100644
--- a/board/phytec/common/Kconfig
+++ b/board/phytec/common/Kconfig
@@ -4,6 +4,13 @@
help
Support of I2C EEPROM based SoM detection.
+config PHYTEC_SOM_DETECTION_BLOCKS
+ bool "Extend SoM detection with block support"
+ depends on PHYTEC_SOM_DETECTION
+ help
+ Extend the I2C EEPROM based SoM detection with API v3. This API
+ introduces blocks with different payloads.
+
config PHYTEC_IMX8M_SOM_DETECTION
bool "Support SoM detection for i.MX8M PHYTEC platforms"
depends on ARCH_IMX8M && PHYTEC_SOM_DETECTION
@@ -16,6 +23,8 @@
bool "Support SoM detection for AM62x PHYTEC platforms"
depends on (TARGET_PHYCORE_AM62X_A53 || TARGET_PHYCORE_AM62X_R5) && \
PHYTEC_SOM_DETECTION
+ select PHYTEC_SOM_DETECTION_BLOCKS
+ depends on SPL_I2C && DM_I2C
default y
help
Support of I2C EEPROM based SoM detection. Supported
@@ -25,6 +34,8 @@
bool "Support SoM detection for AM64x PHYTEC platforms"
depends on (TARGET_PHYCORE_AM64X_A53 || TARGET_PHYCORE_AM64X_R5) && \
PHYTEC_SOM_DETECTION
+ select PHYTEC_SOM_DETECTION_BLOCKS
+ depends on SPL_I2C && DM_I2C
default y
help
Support of I2C EEPROM based SoM detection. Supported
diff --git a/board/phytec/common/Makefile b/board/phytec/common/Makefile
index c34fc50..04469d0 100644
--- a/board/phytec/common/Makefile
+++ b/board/phytec/common/Makefile
@@ -5,10 +5,8 @@
ifdef CONFIG_SPL_BUILD
# necessary to create built-in.o
obj- := __dummy__.o
-else
-obj-$(CONFIG_ARCH_K3) += k3/
endif
-obj-y += phytec_som_detection.o
-obj-$(CONFIG_ARCH_K3) += am6_som_detection.o
+obj-y += phytec_som_detection.o phytec_som_detection_blocks.o
+obj-$(CONFIG_ARCH_K3) += am6_som_detection.o k3/
obj-$(CONFIG_ARCH_IMX8M) += imx8m_som_detection.o
diff --git a/board/phytec/common/am6_som_detection.c b/board/phytec/common/am6_som_detection.c
index 2e9884d..7930ab4 100644
--- a/board/phytec/common/am6_som_detection.c
+++ b/board/phytec/common/am6_som_detection.c
@@ -73,7 +73,7 @@
* - The size
* - PHYTEC_EEPROM_INVAL when the data is invalid.
*/
-u8 __maybe_unused phytec_get_am62_ddr_size(struct phytec_eeprom_data *data)
+u8 __maybe_unused phytec_get_am6_ddr_size(struct phytec_eeprom_data *data)
{
u8 ddr_id = phytec_check_opt(data, 3);
@@ -89,7 +89,7 @@
* - Otherwise a board depended code for the size.
* - PHYTEC_EEPROM_INVAL when the data is invalid.
*/
-u8 __maybe_unused phytec_get_am62_spi(struct phytec_eeprom_data *data)
+u8 __maybe_unused phytec_get_am6_spi(struct phytec_eeprom_data *data)
{
u8 spi = phytec_check_opt(data, 5);
@@ -105,7 +105,7 @@
* - 0x1 if 10/100/1000 MBit Phy is populated.
* - PHYTEC_EEPROM_INVAL when the data is invalid.
*/
-u8 __maybe_unused phytec_get_am62_eth(struct phytec_eeprom_data *data)
+u8 __maybe_unused phytec_get_am6_eth(struct phytec_eeprom_data *data)
{
u8 eth = phytec_check_opt(data, 6);
@@ -121,7 +121,7 @@
* - 1 if it is populated.
* - PHYTEC_EEPROM_INVAL when the data is invalid.
*/
-u8 __maybe_unused phytec_get_am62_rtc(struct phytec_eeprom_data *data)
+u8 __maybe_unused phytec_get_am6_rtc(struct phytec_eeprom_data *data)
{
u8 rtc = phytec_check_opt(data, 7);
@@ -131,28 +131,28 @@
#else
-inline int __maybe_unused phytec_am62_detect(struct phytec_eeprom_data *data)
+inline int __maybe_unused phytec_am6_detect(struct phytec_eeprom_data *data)
{
return -1;
}
inline u8 __maybe_unused
-phytec_get_am62_ddr_size(struct phytec_eeprom_data *data)
+phytec_get_am6_ddr_size(struct phytec_eeprom_data *data)
{
return PHYTEC_EEPROM_INVAL;
}
-inline u8 __maybe_unused phytec_get_am62_spi(struct phytec_eeprom_data *data)
+inline u8 __maybe_unused phytec_get_am6_spi(struct phytec_eeprom_data *data)
{
return PHYTEC_EEPROM_INVAL;
}
-inline u8 __maybe_unused phytec_get_am62_eth(struct phytec_eeprom_data *data)
+inline u8 __maybe_unused phytec_get_am6_eth(struct phytec_eeprom_data *data)
{
return PHYTEC_EEPROM_INVAL;
}
-inline u8 __maybe_unused phytec_get_am62_rtc(struct phytec_eeprom_data *data)
+inline u8 __maybe_unused phytec_get_am6_rtc(struct phytec_eeprom_data *data)
{
return PHYTEC_EEPROM_INVAL;
}
diff --git a/board/phytec/common/am6_som_detection.h b/board/phytec/common/am6_som_detection.h
index 032f9da..c5c6e17 100644
--- a/board/phytec/common/am6_som_detection.h
+++ b/board/phytec/common/am6_som_detection.h
@@ -9,11 +9,19 @@
#include "phytec_som_detection.h"
+#define EEPROM_ADDR 0x50
#define PHYTEC_AM62X_SOM 71
#define PHYTEC_AM64X_SOM 72
#define PHYTEC_EEPROM_VALUE_X 0x21
#define PHYTEC_EEPROM_NOR_FLASH_64MB_QSPI 0xC
+enum {
+ EEPROM_RAM_SIZE_512MB = 0,
+ EEPROM_RAM_SIZE_1GB = 1,
+ EEPROM_RAM_SIZE_2GB = 2,
+ EEPROM_RAM_SIZE_4GB = 4
+};
+
int __maybe_unused phytec_am6_detect(struct phytec_eeprom_data *data);
u8 __maybe_unused phytec_get_am6_ddr_size(struct phytec_eeprom_data *data);
u8 __maybe_unused phytec_get_am6_spi(struct phytec_eeprom_data *data);
diff --git a/board/phytec/common/k3/Makefile b/board/phytec/common/k3/Makefile
index bcca1a9..40e91a4 100644
--- a/board/phytec/common/k3/Makefile
+++ b/board/phytec/common/k3/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y += board.o
+obj-$(CONFIG_K3_DDRSS) += k3_ddrss_patch.o
diff --git a/board/phytec/common/k3/board.c b/board/phytec/common/k3/board.c
index 9cb168c..3d7e090 100644
--- a/board/phytec/common/k3/board.c
+++ b/board/phytec/common/k3/board.c
@@ -5,9 +5,12 @@
*/
#include <env_internal.h>
+#include <fdt_support.h>
#include <spl.h>
#include <asm/arch/hardware.h>
+#include "../am6_som_detection.h"
+
#if IS_ENABLED(CONFIG_ENV_IS_IN_FAT) || IS_ENABLED(CONFIG_ENV_IS_IN_MMC)
int mmc_get_env_dev(void)
{
@@ -68,6 +71,36 @@
break;
};
+ if (IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION_BLOCKS)) {
+ struct phytec_api3_element *block_element;
+ struct phytec_eeprom_data data;
+ int ret;
+
+ ret = phytec_eeprom_data_setup(&data, 0, EEPROM_ADDR);
+ if (ret || !data.valid)
+ return 0;
+
+ PHYTEC_API3_FOREACH_BLOCK(block_element, &data) {
+ switch (block_element->block_type) {
+ case PHYTEC_API3_BLOCK_MAC:
+ phytec_blocks_add_mac_to_env(block_element);
+ break;
+ default:
+ debug("%s: Unknown block type %i\n", __func__,
+ block_element->block_type);
+ }
+ }
+ }
+
+ return 0;
+}
+#endif
+
+#if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ fdt_copy_fixed_partitions(blob);
+
return 0;
}
#endif
diff --git a/board/phytec/common/k3/k3_ddrss_patch.c b/board/phytec/common/k3/k3_ddrss_patch.c
new file mode 100644
index 0000000..5afe5a2
--- /dev/null
+++ b/board/phytec/common/k3/k3_ddrss_patch.c
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
+ * Author: Wadim Egorov <w.egorov@phytec.de>
+ */
+
+#include "k3_ddrss_patch.h"
+
+#include <fdt_support.h>
+#include <linux/errno.h>
+
+#ifdef CONFIG_K3_AM64_DDRSS
+#define LPDDR4_INTR_CTL_REG_COUNT (423U)
+#define LPDDR4_INTR_PHY_INDEP_REG_COUNT (345U)
+#define LPDDR4_INTR_PHY_REG_COUNT (1406U)
+#endif
+
+static int fdt_setprop_inplace_idx_u32(void *fdt, int nodeoffset,
+ const char *name, uint32_t idx, u32 val)
+{
+ val = cpu_to_be32(val);
+ return fdt_setprop_inplace_namelen_partial(fdt, nodeoffset, name,
+ strlen(name),
+ idx * sizeof(val), &val,
+ sizeof(val));
+}
+
+int fdt_apply_ddrss_timings_patch(void *fdt, struct ddrss *ddrss)
+{
+ int i, j;
+ int ret;
+ int mem_offset;
+
+ mem_offset = fdt_path_offset(fdt, "/memorycontroller@f300000");
+ if (mem_offset < 0)
+ return -ENODEV;
+
+ for (i = 0; i < LPDDR4_INTR_CTL_REG_COUNT; i++)
+ for (j = 0; j < ddrss->ctl_regs_num; j++)
+ if (i == ddrss->ctl_regs[j].off) {
+ ret = fdt_setprop_inplace_idx_u32(fdt,
+ mem_offset, "ti,ctl-data", i,
+ ddrss->ctl_regs[j].val);
+ if (ret)
+ return ret;
+ }
+
+ for (i = 0; i < LPDDR4_INTR_PHY_INDEP_REG_COUNT; i++)
+ for (j = 0; j < ddrss->pi_regs_num; j++)
+ if (i == ddrss->pi_regs[j].off) {
+ ret = fdt_setprop_inplace_idx_u32(fdt,
+ mem_offset, "ti,pi-data", i,
+ ddrss->pi_regs[j].val);
+ if (ret)
+ return ret;
+ }
+
+ for (i = 0; i < LPDDR4_INTR_PHY_REG_COUNT; i++)
+ for (j = 0; j < ddrss->phy_regs_num; j++)
+ if (i == ddrss->phy_regs[j].off) {
+ ret = fdt_setprop_inplace_idx_u32(fdt,
+ mem_offset, "ti,phy-data", i,
+ ddrss->phy_regs[j].val);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
diff --git a/board/phytec/common/k3/k3_ddrss_patch.h b/board/phytec/common/k3/k3_ddrss_patch.h
new file mode 100644
index 0000000..0a47c85
--- /dev/null
+++ b/board/phytec/common/k3/k3_ddrss_patch.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
+ * Author: Wadim Egorov <w.egorov@phytec.de>
+ */
+
+#ifndef K3_DDRSS_PATCH
+#define K3_DDRSS_PATCH
+
+#include <linux/types.h>
+
+struct ddr_reg {
+ u32 off;
+ u32 val;
+};
+
+struct ddrss {
+ struct ddr_reg *ctl_regs;
+ u32 ctl_regs_num;
+ struct ddr_reg *pi_regs;
+ u32 pi_regs_num;
+ struct ddr_reg *phy_regs;
+ u32 phy_regs_num;
+};
+
+int fdt_apply_ddrss_timings_patch(void *fdt, struct ddrss *ddrss);
+
+#endif /* K3_DDRSS_PATCH */
diff --git a/board/phytec/common/phytec_som_detection.c b/board/phytec/common/phytec_som_detection.c
index b14bb3d..166c3ea 100644
--- a/board/phytec/common/phytec_som_detection.c
+++ b/board/phytec/common/phytec_som_detection.c
@@ -47,16 +47,9 @@
return ret;
}
-int phytec_eeprom_data_init(struct phytec_eeprom_data *data,
- int bus_num, int addr)
+int phytec_eeprom_read(u8 *data, int bus_num, int addr, int size, int offset)
{
- int ret, i;
- unsigned int crc;
- u8 *ptr;
- const unsigned int payload_size = sizeof(struct phytec_eeprom_payload);
-
- if (!data)
- data = &eeprom_data;
+ int ret;
#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
@@ -64,20 +57,183 @@
ret = i2c_get_chip_for_busnum(bus_num, addr, 2, &dev);
if (ret) {
pr_err("%s: i2c EEPROM not found: %i.\n", __func__, ret);
- goto err;
+ return ret;
}
- ret = dm_i2c_read(dev, 0, (uint8_t *)data, payload_size);
+ ret = dm_i2c_read(dev, offset, (uint8_t *)data, size);
if (ret) {
pr_err("%s: Unable to read EEPROM data: %i\n", __func__, ret);
- goto err;
+ return ret;
}
#else
i2c_set_bus_num(bus_num);
- ret = i2c_read(addr, 0, 2, (uint8_t *)data,
- sizeof(struct phytec_eeprom_data));
+ ret = i2c_read(addr, offset, 2, (uint8_t *)data, size);
+#endif
+ return ret;
+}
+
+int phytec_eeprom_data_init_v2(struct phytec_eeprom_data *data)
+{
+ unsigned int crc;
+
+ if (!data)
+ return -1;
+
+ crc = crc8(0, (const unsigned char *)&data->payload, PHYTEC_API2_DATA_LEN);
+ debug("%s: crc: %x\n", __func__, crc);
+
+ if (crc) {
+ pr_err("%s: CRC mismatch. EEPROM data is not usable.\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+#if IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION_BLOCKS)
+
+int phytec_eeprom_data_init_v3_block(struct phytec_eeprom_data *data,
+ struct phytec_api3_block_header *header,
+ u8 *payload)
+{
+ struct phytec_api3_element *element = NULL;
+ struct phytec_api3_element *list_iterator;
+
+ if (!header)
+ return -1;
+ if (!payload)
+ return -1;
+
+ debug("%s: block type: %i\n", __func__, header->block_type);
+ switch (header->block_type) {
+ case PHYTEC_API3_BLOCK_MAC:
+ element = phytec_blocks_init_mac(header, payload);
+ break;
+ default:
+ debug("%s: Unknown block type %i\n", __func__,
+ header->block_type);
+ }
+ if (!element)
+ return -1;
+
+ if (!data->payload.block_head) {
+ data->payload.block_head = element;
+ return 0;
+ }
+
+ list_iterator = data->payload.block_head;
+ while (list_iterator && list_iterator->next)
+ list_iterator = list_iterator->next;
+ list_iterator->next = element;
+
+ return 0;
+}
+
+int phytec_eeprom_data_init_v3(struct phytec_eeprom_data *data,
+ int bus_num, int addr)
+{
+ int ret, i;
+ struct phytec_api3_header header;
+ unsigned int crc;
+ u8 *payload;
+ int block_addr;
+ struct phytec_api3_block_header *block_header;
+
+ if (!data)
+ return -1;
+
+ ret = phytec_eeprom_read((uint8_t *)&header, bus_num, addr,
+ PHYTEC_API3_DATA_HEADER_LEN,
+ PHYTEC_API2_DATA_LEN);
+ if (ret) {
+ pr_err("%s: Failed to read API v3 data header.\n", __func__);
+ goto err;
+ }
+
+ crc = crc8(0, (const unsigned char *)&header,
+ PHYTEC_API3_DATA_HEADER_LEN);
+ debug("%s: crc: %x\n", __func__, crc);
+ if (crc) {
+ pr_err("%s: CRC mismatch. API3 header is unusable.\n",
+ __func__);
+ goto err;
+ }
+
+ debug("%s: data length: %i\n", __func__, header.data_length);
+ payload = malloc(header.data_length);
+ if (!payload) {
+ pr_err("%s: Unable to allocate memory\n", __func__);
+ goto err_payload;
+ }
+
+ ret = phytec_eeprom_read(payload, bus_num, addr, header.data_length,
+ PHYTEC_API3_DATA_HEADER_LEN +
+ PHYTEC_API2_DATA_LEN);
+ if (ret) {
+ pr_err("%s: Failed to read API v3 data payload.\n", __func__);
+ goto err_payload;
+ }
+
+ block_addr = 0;
+ debug("%s: block count: %i\n", __func__, header.block_count);
+ for (i = 0; i < header.block_count; i++) {
+ debug("%s: block_addr: %i\n", __func__, block_addr);
+ block_header = (struct phytec_api3_block_header *)
+ &payload[block_addr];
+ crc = crc8(0, (const unsigned char *)block_header,
+ PHYTEC_API3_BLOCK_HEADER_LEN);
+
+ debug("%s: crc: %x\n", __func__, crc);
+ if (crc) {
+ pr_err("%s: CRC mismatch. API3 block header is unusable\n",
+ __func__);
+ goto err_payload;
+ }
+
+ ret = phytec_eeprom_data_init_v3_block(data, block_header,
+ &payload[block_addr + PHYTEC_API3_BLOCK_HEADER_LEN]);
+ /* Ignore failed block initialization and continue. */
+ if (ret)
+ debug("%s: Unable to create block with index %i.\n",
+ __func__, i);
+
+ block_addr = block_header->next_block;
+ }
+
+ free(payload);
+ return 0;
+err_payload:
+ free(payload);
+err:
+ return -1;
+}
+
+#else
+
+inline int phytec_eeprom_data_init_v3(struct phytec_eeprom_data *data,
+ int bus_num, int addr)
+{
+ return 0;
+}
+
#endif
+int phytec_eeprom_data_init(struct phytec_eeprom_data *data,
+ int bus_num, int addr)
+{
+ int ret, i;
+ u8 *ptr;
+
+ if (!data)
+ data = &eeprom_data;
+
+ ret = phytec_eeprom_read((u8 *)data, bus_num, addr,
+ PHYTEC_API2_DATA_LEN, 0);
+ if (ret)
+ goto err;
+ data->payload.block_head = NULL;
+
if (data->payload.api_rev == 0xff) {
pr_err("%s: EEPROM is not flashed. Prototype?\n", __func__);
ret = -EINVAL;
@@ -85,31 +241,28 @@
}
ptr = (u8 *)data;
- for (i = 0; i < payload_size; ++i)
+ for (i = 0; i < PHYTEC_API2_DATA_LEN; ++i)
if (ptr[i] != 0x0)
break;
- if (i == payload_size) {
+ if (i == PHYTEC_API2_DATA_LEN) {
pr_err("%s: EEPROM data is all zero. Erased?\n", __func__);
ret = -EINVAL;
goto err;
}
- /* We are done here for early revisions */
- if (data->payload.api_rev <= PHYTEC_API_REV1) {
- data->valid = true;
- return 0;
+ if (data->payload.api_rev >= PHYTEC_API_REV2) {
+ ret = phytec_eeprom_data_init_v2(data);
+ if (ret)
+ goto err;
}
- crc = crc8(0, (const unsigned char *)&data->payload, payload_size);
- debug("%s: crc: %x\n", __func__, crc);
-
- if (crc) {
- pr_err("%s: CRC mismatch. EEPROM data is not usable.\n",
- __func__);
- ret = -EINVAL;
- goto err;
- }
+ if (IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION_BLOCKS))
+ if (data->payload.api_rev >= PHYTEC_API_REV3) {
+ ret = phytec_eeprom_data_init_v3(data, bus_num, addr);
+ if (ret)
+ goto err;
+ }
data->valid = true;
return 0;
@@ -248,6 +401,17 @@
}
#endif /* IS_ENABLED(CONFIG_CMD_EXTENSION) */
+struct phytec_api3_element *
+ __maybe_unused phytec_get_block_head(struct phytec_eeprom_data *data)
+{
+ if (!data)
+ data = &eeprom_data;
+ if (!data->valid)
+ return NULL;
+
+ return data->payload.block_head;
+}
+
#else
inline int phytec_eeprom_data_setup(struct phytec_eeprom_data *data,
@@ -288,6 +452,12 @@
return PHYTEC_EEPROM_INVAL;
}
+inline struct phytec_api3_element * __maybe_unused
+ phytec_get_block_head(struct phytec_eeprom_data *data)
+{
+ return NULL;
+}
+
#if IS_ENABLED(CONFIG_CMD_EXTENSION)
inline struct extension *phytec_add_extension(const char *name,
const char *overlay,
diff --git a/board/phytec/common/phytec_som_detection.h b/board/phytec/common/phytec_som_detection.h
index 0ad5c14..5e35a13 100644
--- a/board/phytec/common/phytec_som_detection.h
+++ b/board/phytec/common/phytec_som_detection.h
@@ -7,9 +7,13 @@
#ifndef _PHYTEC_SOM_DETECTION_H
#define _PHYTEC_SOM_DETECTION_H
+#include "phytec_som_detection_blocks.h"
+
#define PHYTEC_MAX_OPTIONS 17
#define PHYTEC_EEPROM_INVAL 0xff
+#define PHYTEC_API2_DATA_LEN 32
+
#define PHYTEC_GET_OPTION(option) \
(((option) > '9') ? (option) - 'A' + 10 : (option) - '0')
@@ -17,6 +21,7 @@
PHYTEC_API_REV0 = 0,
PHYTEC_API_REV1,
PHYTEC_API_REV2,
+ PHYTEC_API_REV3,
};
enum phytec_som_type_str {
@@ -61,6 +66,7 @@
struct phytec_api0_data data_api0;
struct phytec_api2_data data_api2;
} data;
+ struct phytec_api3_element *block_head;
} __packed;
struct phytec_eeprom_data {
@@ -86,4 +92,7 @@
const char *other);
#endif /* IS_ENABLED(CONFIG_CMD_EXTENSION) */
+struct phytec_api3_element *
+ __maybe_unused phytec_get_block_head(struct phytec_eeprom_data *data);
+
#endif /* _PHYTEC_SOM_DETECTION_H */
diff --git a/board/phytec/common/phytec_som_detection_blocks.c b/board/phytec/common/phytec_som_detection_blocks.c
new file mode 100644
index 0000000..5f3c27e
--- /dev/null
+++ b/board/phytec/common/phytec_som_detection_blocks.c
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
+ * Author: Daniel Schultz <d.schultz@phytec.de>
+ */
+
+#include <malloc.h>
+#include <u-boot/crc.h>
+#include <net.h>
+#include <vsprintf.h>
+
+#include "phytec_som_detection_blocks.h"
+
+#if IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION_BLOCKS)
+
+struct phytec_api3_element *
+ phytec_blocks_init_mac(struct phytec_api3_block_header *header,
+ uint8_t *payload)
+{
+ struct phytec_api3_element *element;
+ struct phytec_api3_block_mac *mac;
+ unsigned int crc;
+ unsigned int len = sizeof(struct phytec_api3_block_mac);
+
+ if (!header)
+ return NULL;
+ if (!payload)
+ return NULL;
+
+ element = (struct phytec_api3_element *)
+ calloc(8, PHYTEC_API3_ELEMENT_HEADER_SIZE + len);
+ if (!element) {
+ pr_err("%s: Unable to allocate memory\n", __func__);
+ return NULL;
+ }
+ element->block_type = header->block_type;
+ memcpy(&element->block.mac, payload, len);
+ mac = &element->block.mac;
+
+ debug("%s: interface: %i\n", __func__, mac->interface);
+ debug("%s: MAC %pM\n", __func__, mac->address);
+
+ crc = crc8(0, (const unsigned char *)mac, len);
+ debug("%s: crc: %x\n", __func__, crc);
+ if (crc) {
+ pr_err("%s: CRC mismatch. API3 block payload is unusable\n",
+ __func__);
+ return NULL;
+ }
+
+ return element;
+}
+
+int __maybe_unused
+ phytec_blocks_add_mac_to_env(struct phytec_api3_element *element)
+{
+ char enetenv[9] = "ethaddr";
+ char buf[ARP_HLEN_ASCII + 1];
+ struct phytec_api3_block_mac *block = &element->block.mac;
+ int ret;
+
+ if (!is_valid_ethaddr(block->address)) {
+ pr_err("%s: Invalid MAC address in block.\n", __func__);
+ return -1;
+ }
+
+ if (block->interface > 0) {
+ ret = sprintf(enetenv, "eth%iaddr", block->interface);
+ if (ret != 8) {
+ pr_err("%s: Unable to create env string\n", __func__);
+ return -1;
+ }
+ }
+
+ ret = sprintf(buf, "%pM", block->address);
+ if (ret != ARP_HLEN_ASCII) {
+ pr_err("%s: Unable to convert MAC address\n", __func__);
+ return -1;
+ }
+ ret = env_set(enetenv, buf);
+ if (ret) {
+ pr_err("%s: Failed to set MAC address to env.\n", __func__);
+ return -1;
+ }
+
+ debug("%s: Added %s to %s\n", __func__, buf, enetenv);
+ return 0;
+}
+
+#else
+
+inline struct phytec_api3_element *
+ phytec_api3_init_mac_block(struct phytec_api3_block_header *header,
+ uint8_t *payload)
+{
+ return NULL;
+}
+
+inline int __maybe_unused
+ phytec_blocks_add_mac_to_env(struct phytec_api3_element *element)
+{
+ return -1;
+}
+
+#endif
diff --git a/board/phytec/common/phytec_som_detection_blocks.h b/board/phytec/common/phytec_som_detection_blocks.h
new file mode 100644
index 0000000..2a5a83c
--- /dev/null
+++ b/board/phytec/common/phytec_som_detection_blocks.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
+ * Author: Daniel Schultz <d.schultz@phytec.de>
+ */
+
+#ifndef _PHYTEC_SOM_DETECTION_BLOCKS_H
+#define _PHYTEC_SOM_DETECTION_BLOCKS_H
+
+#define PHYTEC_API3_DATA_HEADER_LEN 8
+#define PHYTEC_API3_BLOCK_HEADER_LEN 4
+#define PHYTEC_API3_PAYLOAD_START \
+ (PHYTEC_API2_DATA_LEN + PHYTEC_API3_DATA_HEADER_LEN)
+
+#define PHYTEC_API3_ELEMENT_HEADER_SIZE \
+ (sizeof(struct phytec_api3_element *) + \
+ sizeof(enum phytec_api3_block_types))
+
+#define PHYTEC_API3_FOREACH_BLOCK(elem, data) \
+ for (elem = phytec_get_block_head(data); elem; elem = elem->next)
+
+struct phytec_api3_header {
+ u16 data_length; /* Total length in Bytes of all blocks */
+ u8 block_count; /* Number of blocks */
+ u8 sub_version; /* Block specification version */
+ u8 reserved[3]; /* Reserved */
+ u8 crc8; /* checksum */
+} __packed;
+
+struct phytec_api3_block_header {
+ u8 block_type; /* Block payload identifier */
+ u16 next_block; /* Address of the next block */
+ u8 crc8; /* checksum */
+} __packed;
+
+enum phytec_api3_block_types {
+ PHYTEC_API3_BLOCK_MAC = 0,
+};
+
+struct phytec_api3_block_mac {
+ u8 interface; /* Ethernet interface number */
+ u8 address[6]; /* MAC-Address */
+ u8 crc8; /* checksum */
+} __packed;
+
+struct phytec_api3_element {
+ struct phytec_api3_element *next;
+ enum phytec_api3_block_types block_type;
+ union {
+ struct phytec_api3_block_mac mac;
+ } block;
+} __packed;
+
+struct phytec_api3_element *
+ phytec_blocks_init_mac(struct phytec_api3_block_header *header,
+ uint8_t *payload);
+
+int __maybe_unused
+phytec_blocks_add_mac_to_env(struct phytec_api3_element *element);
+
+#endif /* _PHYTEC_SOM_DETECTION_BLOCKS_H */
diff --git a/board/phytec/phycore_am62x/Kconfig b/board/phytec/phycore_am62x/Kconfig
index 1de8850..7c179ef 100644
--- a/board/phytec/phycore_am62x/Kconfig
+++ b/board/phytec/phycore_am62x/Kconfig
@@ -35,3 +35,33 @@
source "board/phytec/common/Kconfig"
endif
+
+config PHYCORE_AM62X_RAM_SIZE_FIX
+ bool "Set phyCORE-AM62x RAM size fix instead of detecting"
+ default false
+ help
+ RAM size is automatic being detected with the help of
+ the EEPROM introspection data. Set RAM size to a fix value
+ instead.
+
+choice
+ prompt "phyCORE-AM62x RAM size"
+ depends on PHYCORE_AM62X_RAM_SIZE_FIX
+ default PHYCORE_AM62X_RAM_SIZE_2GB
+
+config PHYCORE_AM62X_RAM_SIZE_1GB
+ bool "1GB RAM"
+ help
+ Set RAM size fix to 1GB for phyCORE-AM62x.
+
+config PHYCORE_AM62X_RAM_SIZE_2GB
+ bool "2GB RAM"
+ help
+ Set RAM size fix to 2GB for phyCORE-AM62x.
+
+config PHYCORE_AM62X_RAM_SIZE_4GB
+ bool "4GB RAM"
+ help
+ Set RAM size fix to 4GB for phyCORE-AM62x.
+
+endchoice
diff --git a/board/phytec/phycore_am62x/MAINTAINERS b/board/phytec/phycore_am62x/MAINTAINERS
index 02ac88e..42463ad 100644
--- a/board/phytec/phycore_am62x/MAINTAINERS
+++ b/board/phytec/phycore_am62x/MAINTAINERS
@@ -11,3 +11,4 @@
F: configs/phycore_am62x_r5_defconfig
F: include/configs/phycore_am62x.h
F: doc/board/phytec/phycore-am62x.rst
+F: board/phytec/common/k3
diff --git a/board/phytec/phycore_am62x/phycore-am62x.c b/board/phytec/phycore_am62x/phycore-am62x.c
index a082b88..9f6bc73 100644
--- a/board/phytec/phycore_am62x/phycore-am62x.c
+++ b/board/phytec/phycore_am62x/phycore-am62x.c
@@ -4,10 +4,18 @@
* Author: Wadim Egorov <w.egorov@phytec.de>
*/
+#include <asm/arch/hardware.h>
#include <asm/io.h>
#include <spl.h>
#include <fdt_support.h>
+#include "phycore-ddr-data.h"
+#include "../common/k3/k3_ddrss_patch.h"
+#include "../common/am6_som_detection.h"
+
+#define AM64_DDRSS_SS_BASE 0x0F300000
+#define DDRSS_V2A_CTL_REG 0x0020
+
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
@@ -15,15 +23,184 @@
return 0;
}
+static u8 phytec_get_am62_ddr_size_default(void)
+{
+ int ret;
+ struct phytec_eeprom_data data;
+
+ if (IS_ENABLED(CONFIG_PHYCORE_AM62X_RAM_SIZE_FIX)) {
+ if (IS_ENABLED(CONFIG_PHYCORE_AM62X_RAM_SIZE_1GB))
+ return EEPROM_RAM_SIZE_1GB;
+ else if (IS_ENABLED(CONFIG_PHYCORE_AM62X_RAM_SIZE_2GB))
+ return EEPROM_RAM_SIZE_2GB;
+ else if (IS_ENABLED(CONFIG_PHYCORE_AM62X_RAM_SIZE_4GB))
+ return EEPROM_RAM_SIZE_4GB;
+ }
+
+ ret = phytec_eeprom_data_setup(&data, 0, EEPROM_ADDR);
+ if (!ret && data.valid)
+ return phytec_get_am6_ddr_size(&data);
+
+ /* Default DDR size is 2GB */
+ return EEPROM_RAM_SIZE_2GB;
+}
+
int dram_init(void)
{
- return fdtdec_setup_mem_size_base();
+ u8 ram_size;
+
+ if (!IS_ENABLED(CONFIG_CPU_V7R))
+ return fdtdec_setup_mem_size_base();
+
+ ram_size = phytec_get_am62_ddr_size_default();
+
+ /*
+ * HACK: ddrss driver support 2GB RAM by default
+ * V2A_CTL_REG should be updated to support other RAM size
+ */
+ if (IS_ENABLED(CONFIG_K3_AM64_DDRSS))
+ if (ram_size == EEPROM_RAM_SIZE_4GB)
+ writel(0x00000210, AM64_DDRSS_SS_BASE + DDRSS_V2A_CTL_REG);
+
+ switch (ram_size) {
+ case EEPROM_RAM_SIZE_1GB:
+ gd->ram_size = 0x40000000;
+ break;
+ case EEPROM_RAM_SIZE_2GB:
+ gd->ram_size = 0x80000000;
+ break;
+ case EEPROM_RAM_SIZE_4GB:
+#ifdef CONFIG_PHYS_64BIT
+ gd->ram_size = 0x100000000;
+#else
+ gd->ram_size = 0x80000000;
+#endif
+ break;
+ default:
+ gd->ram_size = 0x80000000;
+ }
+
+ return 0;
+}
+
+phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+{
+#ifdef CONFIG_PHYS_64BIT
+ /* Limit RAM used by U-Boot to the DDR low region */
+ if (gd->ram_top > 0x100000000)
+ return 0x100000000;
+#endif
+ return gd->ram_top;
}
int dram_init_banksize(void)
{
+ u8 ram_size;
+
+ if (!IS_ENABLED(CONFIG_CPU_V7R))
+ return fdtdec_setup_memory_banksize();
+
+ ram_size = phytec_get_am62_ddr_size_default();
+ switch (ram_size) {
+ case EEPROM_RAM_SIZE_1GB:
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = 0x40000000;
+ gd->ram_size = 0x40000000;
+ break;
+
+ case EEPROM_RAM_SIZE_2GB:
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = 0x80000000;
+ gd->ram_size = 0x80000000;
+ break;
+
+ case EEPROM_RAM_SIZE_4GB:
+ /* Bank 0 declares the memory available in the DDR low region */
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = 0x80000000;
+ gd->ram_size = 0x80000000;
+
+#ifdef CONFIG_PHYS_64BIT
+ /* Bank 1 declares the memory available in the DDR upper region */
+ gd->bd->bi_dram[1].start = 0x880000000;
+ gd->bd->bi_dram[1].size = 0x80000000;
+ gd->ram_size = 0x100000000;
+#endif
+ break;
+ default:
+ /* Continue with default 2GB setup */
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = 0x80000000;
+ gd->ram_size = 0x80000000;
+ printf("DDR size %d is not supported\n", ram_size);
+ }
+
+ return 0;
+}
+
+#if defined(CONFIG_K3_DDRSS)
+int update_ddrss_timings(void)
+{
- return fdtdec_setup_memory_banksize();
+ int ret;
+ u8 ram_size;
+ struct ddrss *ddr_patch = NULL;
+ void *fdt = (void *)gd->fdt_blob;
+
+ ram_size = phytec_get_am62_ddr_size_default();
+ switch (ram_size) {
+ case EEPROM_RAM_SIZE_1GB:
+ ddr_patch = &phycore_ddrss_data[PHYCORE_1GB];
+ break;
+ case EEPROM_RAM_SIZE_2GB:
+ ddr_patch = NULL;
+ break;
+ case EEPROM_RAM_SIZE_4GB:
+ ddr_patch = &phycore_ddrss_data[PHYCORE_4GB];
+ break;
+ default:
+ break;
+ }
+
+ /* Nothing to patch */
+ if (!ddr_patch)
+ return 0;
+
+ debug("Applying DDRSS timings patch for ram_size %d\n", ram_size);
+
+ ret = fdt_apply_ddrss_timings_patch(fdt, ddr_patch);
+ if (ret < 0) {
+ printf("Failed to apply ddrs timings patch %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+int do_board_detect(void)
+{
+ return update_ddrss_timings();
+}
+#endif
+
+#if IS_ENABLED(CONFIG_SPL_BUILD)
+void spl_perform_fixups(struct spl_image_info *spl_image)
+{
+ u64 start[CONFIG_NR_DRAM_BANKS];
+ u64 size[CONFIG_NR_DRAM_BANKS];
+ int bank;
+ int ret;
+
+ dram_init();
+ dram_init_banksize();
+
+ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+ start[bank] = gd->bd->bi_dram[bank].start;
+ size[bank] = gd->bd->bi_dram[bank].size;
+ }
+
+ ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size, CONFIG_NR_DRAM_BANKS);
}
+#endif
#define CTRLMMR_USB0_PHY_CTRL 0x43004008
#define CTRLMMR_USB1_PHY_CTRL 0x43004018
diff --git a/board/phytec/phycore_am62x/phycore-ddr-data.h b/board/phytec/phycore_am62x/phycore-ddr-data.h
new file mode 100644
index 0000000..fe6eccd
--- /dev/null
+++ b/board/phytec/phycore_am62x/phycore-ddr-data.h
@@ -0,0 +1,206 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
+ * Author: Wadim Egorov <w.egorov@phytec.de>
+ */
+
+#ifndef PHYCORE_DDR_DATA
+#define PHYCORE_DDR_DATA
+
+#include "../common/k3/k3_ddrss_patch.h"
+
+/* 1 GB variant delta */
+struct ddr_reg ddr_1gb_ctl_regs[] = {
+ { 55, 0x0400DB60 },
+ { 58, 0x0400DB60 },
+ { 61, 0x0400DB60 },
+ { 73, 0x00001860 },
+ { 75, 0x00001860 },
+ { 77, 0x00001860 },
+ { 119, 0x00061800 },
+ { 120, 0x00061800 },
+ { 121, 0x00061800 },
+ { 122, 0x00061800 },
+ { 123, 0x00061800 },
+ { 125, 0x0000AAA0 },
+ { 126, 0x00061800 },
+ { 127, 0x00061800 },
+ { 128, 0x00061800 },
+ { 129, 0x00061800 },
+ { 130, 0x00061800 },
+ { 132, 0x0000AAA0 },
+ { 133, 0x00061800 },
+ { 134, 0x00061800 },
+ { 135, 0x00061800 },
+ { 136, 0x00061800 },
+ { 137, 0x00061800 },
+ { 139, 0x0000AAA0 },
+ { 206, 0x00000000 },
+ { 209, 0x00000000 },
+ { 212, 0x00000000 },
+ { 215, 0x00000000 },
+ { 218, 0x00000000 },
+ { 221, 0x00000000 },
+ { 230, 0x00000000 },
+ { 231, 0x00000000 },
+ { 232, 0x00000000 },
+ { 233, 0x00000000 },
+ { 234, 0x00000000 },
+ { 235, 0x00000000 },
+ { 316, 0x01010000 },
+ { 318, 0x3FFF0000 },
+ { 327, 0x00000C01 },
+ { 328, 0x00000000 },
+ { 385, 0x000030C0 },
+ { 390, 0x0000DB60 },
+ { 391, 0x0001E780 },
+ { 394, 0x000030C0 },
+ { 399, 0x0000DB60 },
+ { 400, 0x0001E780 },
+ { 403, 0x000030C0 },
+ { 408, 0x0000DB60 },
+ { 409, 0x0001E780 }
+};
+
+struct ddr_reg ddr_1gb_pi_regs[] = {
+ { 77, 0x04000100 },
+ { 176, 0x00001860 },
+ { 178, 0x00001860 },
+ { 180, 0x04001860 },
+ { 233, 0x0000C570 },
+ { 238, 0x0000C570 },
+ { 243, 0x0000C570 },
+ { 247, 0x000030C0 },
+ { 248, 0x0001E780 },
+ { 249, 0x000030C0 },
+ { 250, 0x0001E780 },
+ { 251, 0x000030C0 },
+ { 252, 0x0001E780 },
+ { 299, 0x00000000 },
+ { 301, 0x00000000 },
+ { 307, 0x00000000 },
+ { 309, 0x00000000 },
+ { 315, 0x00000000 },
+ { 317, 0x00000000 },
+ { 323, 0x00000000 },
+ { 325, 0x00000000 },
+ { 331, 0x00000000 },
+ { 333, 0x00000000 },
+ { 339, 0x00000000 },
+ { 341, 0x00000000 }
+};
+
+struct ddr_reg ddr_1gb_phy_regs[] = {
+ { 1371, 0x0001F7C2 },
+};
+
+/* 4 GB variant delta */
+struct ddr_reg ddr_4gb_ctl_regs[] = {
+ { 55, 0x0400DB60 },
+ { 58, 0x0400DB60 },
+ { 61, 0x0400DB60 },
+ { 73, 0x00001860 },
+ { 75, 0x00001860 },
+ { 77, 0x00001860 },
+ { 119, 0x00061800 },
+ { 120, 0x00061800 },
+ { 121, 0x00061800 },
+ { 122, 0x00061800 },
+ { 123, 0x00061800 },
+ { 125, 0x0000AAA0 },
+ { 126, 0x00061800 },
+ { 127, 0x00061800 },
+ { 128, 0x00061800 },
+ { 129, 0x00061800 },
+ { 130, 0x00061800 },
+ { 132, 0x0000AAA0 },
+ { 133, 0x00061800 },
+ { 134, 0x00061800 },
+ { 135, 0x00061800 },
+ { 136, 0x00061800 },
+ { 137, 0x00061800 },
+ { 139, 0x0000AAA0 },
+ { 206, 0x00000000 },
+ { 209, 0x00000000 },
+ { 212, 0x00000000 },
+ { 215, 0x00000000 },
+ { 218, 0x00000000 },
+ { 221, 0x00000000 },
+ { 230, 0x00000000 },
+ { 231, 0x00000000 },
+ { 232, 0x00000000 },
+ { 233, 0x00000000 },
+ { 234, 0x00000000 },
+ { 235, 0x00000000 },
+ { 316, 0x00000000 },
+ { 318, 0x7FFF0000 },
+ { 327, 0x01000C01 },
+ { 328, 0x00000001 },
+ { 385, 0x000030C0 },
+ { 390, 0x0000DB60 },
+ { 391, 0x0001E780 },
+ { 394, 0x000030C0 },
+ { 399, 0x0000DB60 },
+ { 400, 0x0001E780 },
+ { 403, 0x000030C0 },
+ { 408, 0x0000DB60 },
+ { 409, 0x0001E780 }
+};
+
+struct ddr_reg ddr_4gb_pi_regs[] = {
+ { 77, 0x04000000 },
+ { 176, 0x00001860 },
+ { 178, 0x00001860 },
+ { 180, 0x04001860 },
+ { 233, 0x0000C570 },
+ { 238, 0x0000C570 },
+ { 243, 0x0000C570 },
+ { 247, 0x000030C0 },
+ { 248, 0x0001E780 },
+ { 249, 0x000030C0 },
+ { 250, 0x0001E780 },
+ { 251, 0x000030C0 },
+ { 252, 0x0001E780 },
+ { 299, 0x00000000 },
+ { 301, 0x00000000 },
+ { 307, 0x00000000 },
+ { 309, 0x00000000 },
+ { 315, 0x00000000 },
+ { 317, 0x00000000 },
+ { 323, 0x00000000 },
+ { 325, 0x00000000 },
+ { 331, 0x00000000 },
+ { 333, 0x00000000 },
+ { 339, 0x00000000 },
+ { 341, 0x00000000 }
+};
+
+struct ddr_reg ddr_4gb_phy_regs[] = {
+ { 1371, 0x0001F7C2 },
+};
+
+enum {
+ PHYCORE_1GB,
+ PHYCORE_4GB,
+};
+
+struct ddrss phycore_ddrss_data[] = {
+ [PHYCORE_1GB] = {
+ .ctl_regs = &ddr_1gb_ctl_regs[0],
+ .ctl_regs_num = ARRAY_SIZE(ddr_1gb_ctl_regs),
+ .pi_regs = &ddr_1gb_pi_regs[0],
+ .pi_regs_num = ARRAY_SIZE(ddr_1gb_pi_regs),
+ .phy_regs = &ddr_1gb_phy_regs[0],
+ .phy_regs_num = ARRAY_SIZE(ddr_1gb_phy_regs),
+ },
+ [PHYCORE_4GB] = {
+ .ctl_regs = &ddr_4gb_ctl_regs[0],
+ .ctl_regs_num = ARRAY_SIZE(ddr_4gb_ctl_regs),
+ .pi_regs = &ddr_4gb_pi_regs[0],
+ .pi_regs_num = ARRAY_SIZE(ddr_4gb_pi_regs),
+ .phy_regs = &ddr_4gb_phy_regs[0],
+ .phy_regs_num = ARRAY_SIZE(ddr_4gb_phy_regs),
+ },
+};
+
+#endif /* PHYCORE_DDR_DATA */
diff --git a/board/phytec/phycore_am62x/phycore_am62x.env b/board/phytec/phycore_am62x/phycore_am62x.env
index ada3a92..42db26a 100644
--- a/board/phytec/phycore_am62x/phycore_am62x.env
+++ b/board/phytec/phycore_am62x/phycore_am62x.env
@@ -1,3 +1,5 @@
+#include <env/ti/k3_dfu.env>
+
fdtaddr=0x88000000
loadaddr=0x82000000
scriptaddr=0x80000000
diff --git a/board/phytec/phycore_imx8mm/MAINTAINERS b/board/phytec/phycore_imx8mm/MAINTAINERS
index e46e369..58c5e2d 100644
--- a/board/phytec/phycore_imx8mm/MAINTAINERS
+++ b/board/phytec/phycore_imx8mm/MAINTAINERS
@@ -2,10 +2,7 @@
M: Teresa Remmet <t.remmet@phytec.de>
W: https://www.phytec.eu/product-eu/system-on-modules/phycore-imx-8m-mini-nano/
S: Maintained
-F: arch/arm/dts/imx8mm-phyboard-polis-rdk.dts
-F: arch/arm/dts/imx8mm-phycore-som.dtsi
F: arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi
-F: arch/arm/dts/imx8mm-phygate-tauri-l.dts
F: arch/arm/dts/imx8mm-phygate-tauri-l-u-boot.dtsi
F: board/phytec/phycore_imx8mm/
F: configs/imx8mm-phygate-tauri-l_defconfig
diff --git a/board/phytec/phycore_imx8mp/Kconfig b/board/phytec/phycore_imx8mp/Kconfig
index f846d10..bdf9e97 100644
--- a/board/phytec/phycore_imx8mp/Kconfig
+++ b/board/phytec/phycore_imx8mp/Kconfig
@@ -12,5 +12,72 @@
config IMX_CONFIG
default "board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg"
+config PHYCORE_IMX8MP_RAM_SIZE_FIX
+ bool "Set phyCORE-i.MX8MP RAM size fix instead of detecting"
+ default false
+ help
+ RAM size is automatic being detected with the help of
+ the EEPROM introspection data. Set RAM size to a fix value
+ instead.
+
+choice
+ prompt "phyCORE-i.MX8MP RAM size"
+ depends on PHYCORE_IMX8MP_RAM_SIZE_FIX
+ default PHYCORE_IMX8MP_RAM_SIZE_2GB
+
+config PHYCORE_IMX8MP_RAM_SIZE_1GB
+ bool "1GB RAM"
+ help
+ Set RAM size fix to 1GB for phyCORE-i.MX8MP.
+ RAM frequency is configured independent.
+
+config PHYCORE_IMX8MP_RAM_SIZE_2GB
+ bool "2GB RAM"
+ help
+ Set RAM size fix to 2GB for phyCORE-i.MX8MP.
+ RAM frequency is configured independent.
+
+config PHYCORE_IMX8MP_RAM_SIZE_4GB
+ bool "4GB RAM"
+ help
+ Set RAM size fix to 4GB for phyCORE-i.MX8MP.
+ RAM frequency is configured independent.
+
+config PHYCORE_IMX8MP_RAM_SIZE_8GB
+ bool "8GB RAM"
+ select PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS
+ help
+ Set RAM size fix to 8GB for phyCORE-i.MX8MP.
+ Only 2GHz RAMs are supported.
+
+endchoice
+
+config PHYCORE_IMX8MP_RAM_FREQ_FIX
+ bool "Set phyCORE-i.MX8MP RAM frequency fix instead of detecting"
+ default false
+ help
+ RAM frequency is automatic being detected with the help of
+ the EEPROM introspection data. Set RAM frequency to a fix value
+ instead.
+
+choice
+ prompt "phyCORE-i.MX8MP RAM frequency"
+ depends on PHYCORE_IMX8MP_RAM_FREQ_FIX
+ default PHYCORE_IMX8MP_USE_1_5GHZ_RAM_TIMINGS
+
+config PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS
+ bool "Use 2GHz RAM timings"
+ help
+ Use fix 2GHz RAM timings for phyCORE-i.MX8MP instead of
+ 1.5GHz timings.
+
+config PHYCORE_IMX8MP_USE_1_5GHZ_RAM_TIMINGS
+ depends on !PHYCORE_IMX8MP_RAM_SIZE_8GB
+ bool "Use 1.5GHz RAM timings"
+ help
+ Use fix 1.5GHz RAM timings for phyCORE-i.MX8MP instead of
+ 2GHz timings.
+endchoice
+
source "board/phytec/common/Kconfig"
endif
diff --git a/board/phytec/phycore_imx8mp/MAINTAINERS b/board/phytec/phycore_imx8mp/MAINTAINERS
index d3beb97..645476a 100644
--- a/board/phytec/phycore_imx8mp/MAINTAINERS
+++ b/board/phytec/phycore_imx8mp/MAINTAINERS
@@ -2,7 +2,6 @@
M: Teresa Remmet <t.remmet@phytec.de>
W: https://www.phytec.eu/product-eu/system-on-modules/phycore-imx-8m-plus/
S: Maintained
-F: arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts
F: arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi
F: board/phytec/phycore_imx8mp/
F: configs/phycore-imx8mp_defconfig
diff --git a/board/phytec/phycore_imx8mp/lpddr4_timing.c b/board/phytec/phycore_imx8mp/lpddr4_timing.c
index f2707b8..9984b6c 100644
--- a/board/phytec/phycore_imx8mp/lpddr4_timing.c
+++ b/board/phytec/phycore_imx8mp/lpddr4_timing.c
@@ -1839,3 +1839,156 @@
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
.fsp_table = { 3000, 400, 100, },
};
+
+void set_dram_timings_2ghz_2gb(void)
+{
+ dram_timing.ddrc_cfg[3].val = 0x1323;
+ dram_timing.ddrc_cfg[4].val = 0x1e84800;
+ dram_timing.ddrc_cfg[5].val = 0x7a0118;
+ dram_timing.ddrc_cfg[8].val = 0xc00307a3;
+ dram_timing.ddrc_cfg[9].val = 0xc50000;
+ dram_timing.ddrc_cfg[10].val = 0xf4003f;
+ dram_timing.ddrc_cfg[11].val = 0xf30000;
+ dram_timing.ddrc_cfg[14].val = 0x2028222a;
+ dram_timing.ddrc_cfg[15].val = 0x8083f;
+ dram_timing.ddrc_cfg[16].val = 0xe0e000;
+ dram_timing.ddrc_cfg[17].val = 0x12040a12;
+ dram_timing.ddrc_cfg[18].val = 0x2050f0f;
+ dram_timing.ddrc_cfg[19].val = 0x1010009;
+ dram_timing.ddrc_cfg[20].val = 0x502;
+ dram_timing.ddrc_cfg[21].val = 0x20800;
+ dram_timing.ddrc_cfg[22].val = 0xe100002;
+ dram_timing.ddrc_cfg[23].val = 0x120;
+ dram_timing.ddrc_cfg[24].val = 0xc80064;
+ dram_timing.ddrc_cfg[25].val = 0x3e8001e;
+ dram_timing.ddrc_cfg[26].val = 0x3207a12;
+ dram_timing.ddrc_cfg[28].val = 0x4a3820e;
+ dram_timing.ddrc_cfg[30].val = 0x230e;
+ dram_timing.ddrc_cfg[37].val = 0x799;
+ dram_timing.ddrc_cfg[38].val = 0x9141d1c;
+ dram_timing.ddrc_cfg[74].val = 0x302;
+ dram_timing.ddrc_cfg[83].val = 0x599;
+ dram_timing.ddrc_cfg[99].val = 0x302;
+ dram_timing.ddrc_cfg[108].val = 0x599;
+ dram_timing.ddrphy_cfg[66].val = 0x18;
+ dram_timing.ddrphy_cfg[75].val = 0x1e3;
+ dram_timing.ddrphy_cfg[77].val = 0x1e3;
+ dram_timing.ddrphy_cfg[79].val = 0x1e3;
+ dram_timing.ddrphy_cfg[145].val = 0x3e8;
+ dram_timing.fsp_msg[0].drate = 4000;
+ dram_timing.fsp_msg[0].fsp_cfg[1].val = 0xfa0;
+ dram_timing.fsp_msg[0].fsp_cfg[10].val = 0x3ff4;
+ dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xf3;
+ dram_timing.fsp_msg[0].fsp_cfg[15].val = 0x3ff4;
+ dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xf3;
+ dram_timing.fsp_msg[0].fsp_cfg[22].val = 0xf400;
+ dram_timing.fsp_msg[0].fsp_cfg[23].val = 0xf33f;
+ dram_timing.fsp_msg[0].fsp_cfg[28].val = 0xf400;
+ dram_timing.fsp_msg[0].fsp_cfg[29].val = 0xf33f;
+ dram_timing.fsp_msg[3].drate = 4000;
+ dram_timing.fsp_msg[3].fsp_cfg[1].val = 0xfa0;
+ dram_timing.fsp_msg[3].fsp_cfg[11].val = 0x3ff4;
+ dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xf3;
+ dram_timing.fsp_msg[3].fsp_cfg[16].val = 0x3ff4;
+ dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xf3;
+ dram_timing.fsp_msg[3].fsp_cfg[23].val = 0xf400;
+ dram_timing.fsp_msg[3].fsp_cfg[24].val = 0xf33f;
+ dram_timing.fsp_msg[3].fsp_cfg[29].val = 0xf400;
+ dram_timing.fsp_msg[3].fsp_cfg[30].val = 0xf33f;
+ dram_timing.ddrphy_pie[480].val = 0x465;
+ dram_timing.ddrphy_pie[481].val = 0xfa;
+ dram_timing.ddrphy_pie[482].val = 0x9c4;
+ dram_timing.fsp_table[0] = 4000;
+}
+
+void set_dram_timings_1_5ghz_1gb(void)
+{
+ dram_timing.ddrc_cfg[3].val = 0x1233;
+ dram_timing.ddrc_cfg[5].val = 0x5b0087;
+ dram_timing.ddrc_cfg[6].val = 0x61027f10;
+ dram_timing.ddrc_cfg[7].val = 0x7b0;
+ dram_timing.ddrc_cfg[11].val = 0xf30000;
+ dram_timing.ddrc_cfg[23].val = 0x8d;
+ dram_timing.ddrc_cfg[45].val = 0xf070707;
+ dram_timing.ddrc_cfg[59].val = 0x1031;
+ dram_timing.ddrc_cfg[62].val = 0xc0012;
+ dram_timing.ddrc_cfg[77].val = 0x13;
+ dram_timing.ddrc_cfg[84].val = 0x1031;
+ dram_timing.ddrc_cfg[87].val = 0x30005;
+ dram_timing.ddrc_cfg[102].val = 0x5;
+ dram_timing.ddrphy_cfg[75].val = 0x1e3;
+ dram_timing.ddrphy_cfg[77].val = 0x1e3;
+ dram_timing.ddrphy_cfg[79].val = 0x1e3;
+ dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xf3;
+ dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xf3;
+ dram_timing.fsp_msg[0].fsp_cfg[23].val = 0xf32d;
+ dram_timing.fsp_msg[0].fsp_cfg[29].val = 0xf32d;
+ dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xf3;
+ dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xf3;
+ dram_timing.fsp_msg[3].fsp_cfg[24].val = 0xf32d;
+ dram_timing.fsp_msg[3].fsp_cfg[30].val = 0xf32d;
+}
+
+void set_dram_timings_2ghz_1gb(void)
+{
+ set_dram_timings_2ghz_2gb();
+ dram_timing.ddrc_cfg[5].val = 0x7a00b4;
+ dram_timing.ddrc_cfg[23].val = 0xbc;
+ dram_timing.ddrc_cfg[45].val = 0xf070707;
+ dram_timing.ddrc_cfg[62].val = 0xc0012;
+ dram_timing.ddrc_cfg[77].val = 0x13;
+ dram_timing.ddrc_cfg[87].val = 0x30005;
+ dram_timing.ddrc_cfg[102].val = 0x5;
+}
+
+void set_dram_timings_1_5ghz_4gb(void)
+{
+ dram_timing.ddrc_cfg[2].val = 0xa3080020;
+ dram_timing.ddrc_cfg[39].val = 0x17;
+ dram_timing.fsp_msg[0].fsp_cfg[9].val = 0x310;
+ dram_timing.fsp_msg[0].fsp_cfg[21].val = 0x3;
+ dram_timing.fsp_msg[1].fsp_cfg[10].val = 0x310;
+ dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x3;
+ dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x310;
+ dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x3;
+ dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x310;
+ dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x3;
+}
+
+void set_dram_timings_2ghz_4gb(void)
+{
+ set_dram_timings_2ghz_2gb();
+ dram_timing.ddrc_cfg[2].val = 0xa3080020;
+ dram_timing.ddrc_cfg[39].val = 0x17;
+ dram_timing.fsp_msg[0].fsp_cfg[9].val = 0x310;
+ dram_timing.fsp_msg[0].fsp_cfg[21].val = 0x3;
+ dram_timing.fsp_msg[1].fsp_cfg[10].val = 0x310;
+ dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x3;
+ dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x310;
+ dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x3;
+ dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x310;
+ dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x3;
+}
+
+void set_dram_timings_2ghz_8gb(void)
+{
+ set_dram_timings_2ghz_2gb();
+ dram_timing.ddrc_cfg[2].val = 0xa3080020;
+ dram_timing.ddrc_cfg[5].val = 0x7a017c;
+ dram_timing.ddrc_cfg[23].val = 0x184;
+ dram_timing.ddrc_cfg[39].val = 0x18;
+ dram_timing.ddrc_cfg[46].val = 0xf07;
+ dram_timing.ddrc_cfg[62].val = 0xc0026;
+ dram_timing.ddrc_cfg[77].val = 0x27;
+ dram_timing.ddrc_cfg[87].val = 0x3000a;
+ dram_timing.ddrc_cfg[102].val = 0xa;
+
+ dram_timing.fsp_msg[0].fsp_cfg[9].val = 0x310;
+ dram_timing.fsp_msg[0].fsp_cfg[21].val = 0x3;
+ dram_timing.fsp_msg[1].fsp_cfg[10].val = 0x310;
+ dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x3;
+ dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x310;
+ dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x3;
+ dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x310;
+ dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x3;
+}
diff --git a/board/phytec/phycore_imx8mp/lpddr4_timing.h b/board/phytec/phycore_imx8mp/lpddr4_timing.h
new file mode 100644
index 0000000..1c10e08
--- /dev/null
+++ b/board/phytec/phycore_imx8mp/lpddr4_timing.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
+ */
+
+#ifndef __LPDDR4_TIMING_H__
+#define __LPDDR4_TIMING_H__
+
+void set_dram_timings_2ghz_2gb(void);
+void set_dram_timings_2ghz_1gb(void);
+void set_dram_timings_2ghz_4gb(void);
+void set_dram_timings_1_5ghz_1gb(void);
+void set_dram_timings_1_5ghz_4gb(void);
+void set_dram_timings_2ghz_8gb(void);
+
+#endif /* __LPDDR4_TIMING_H__ */
diff --git a/board/phytec/phycore_imx8mp/phycore-imx8mp.c b/board/phytec/phycore_imx8mp/phycore-imx8mp.c
index 3568359..ef95136 100644
--- a/board/phytec/phycore_imx8mp/phycore-imx8mp.c
+++ b/board/phytec/phycore_imx8mp/phycore-imx8mp.c
@@ -9,6 +9,7 @@
#include <asm/io.h>
#include <asm/mach-imx/boot_mode.h>
#include <env.h>
+#include <init.h>
#include <miiphy.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -55,3 +56,13 @@
return 0;
}
+
+int board_phys_sdram_size(phys_size_t *size)
+{
+ if (!size)
+ return -EINVAL;
+
+ *size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE);
+
+ return 0;
+}
diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c
index 352f803..0610d8b 100644
--- a/board/phytec/phycore_imx8mp/spl.c
+++ b/board/phytec/phycore_imx8mp/spl.c
@@ -20,95 +20,103 @@
#include <power/pca9450.h>
#include <spl.h>
+#include "lpddr4_timing.h"
#include "../common/imx8m_som_detection.h"
DECLARE_GLOBAL_DATA_PTR;
-#define EEPROM_ADDR 0x51
-#define EEPROM_ADDR_FALLBACK 0x59
+#define EEPROM_ADDR 0x51
+#define EEPROM_ADDR_FALLBACK 0x59
int spl_board_boot_device(enum boot_device boot_dev_spl)
{
return BOOT_DEVICE_BOOTROM;
}
+enum phytec_imx8mp_ddr_eeprom_code {
+ PHYTEC_IMX8MP_DDR_1GB = 2,
+ PHYTEC_IMX8MP_DDR_2GB = 3,
+ PHYTEC_IMX8MP_DDR_4GB = 5,
+ PHYTEC_IMX8MP_DDR_8GB = 7,
+ PHYTEC_IMX8MP_DDR_4GB_2GHZ = 8,
+};
+
void spl_dram_init(void)
{
int ret;
+ bool use_2ghz_timings = false;
+ enum phytec_imx8mp_ddr_eeprom_code size = PHYTEC_EEPROM_INVAL;
ret = phytec_eeprom_data_setup_fallback(NULL, 0, EEPROM_ADDR,
EEPROM_ADDR_FALLBACK);
- if (ret)
+ if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_FIX))
goto out;
ret = phytec_imx8m_detect(NULL);
if (!ret)
phytec_print_som_info(NULL);
+ if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_FIX)) {
+ if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_1GB))
+ size = PHYTEC_IMX8MP_DDR_1GB;
+ else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_2GB))
+ size = PHYTEC_IMX8MP_DDR_2GB;
+ else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_4GB))
+ size = PHYTEC_IMX8MP_DDR_4GB;
+ else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_8GB))
+ size = PHYTEC_IMX8MP_DDR_8GB;
+ } else {
+ size = phytec_get_imx8m_ddr_size(NULL);
+ }
+
- u8 rev = phytec_get_rev(NULL);
- u8 somtype = phytec_get_som_type(NULL);
+ if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_FREQ_FIX)) {
+ if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS)) {
+ if (size == PHYTEC_IMX8MP_DDR_4GB)
+ size = PHYTEC_IMX8MP_DDR_4GB_2GHZ;
+ else
+ use_2ghz_timings = true;
+ } else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_USE_1_5GHZ_RAM_TIMINGS)) {
+ if (size == PHYTEC_IMX8MP_DDR_4GB_2GHZ)
+ size = PHYTEC_IMX8MP_DDR_4GB;
+ else
+ use_2ghz_timings = false;
+ }
+ } else {
+ u8 rev = phytec_get_rev(NULL);
+ u8 somtype = phytec_get_som_type(NULL);
- if (rev != PHYTEC_EEPROM_INVAL && (rev >= 3 || (somtype == SOM_TYPE_PCL && rev >= 1))) {
- dram_timing.ddrc_cfg[3].val = 0x1323;
- dram_timing.ddrc_cfg[4].val = 0x1e84800;
- dram_timing.ddrc_cfg[5].val = 0x7a0118;
- dram_timing.ddrc_cfg[8].val = 0xc00307a3;
- dram_timing.ddrc_cfg[9].val = 0xc50000;
- dram_timing.ddrc_cfg[10].val = 0xf4003f;
- dram_timing.ddrc_cfg[11].val = 0xf30000;
- dram_timing.ddrc_cfg[14].val = 0x2028222a;
- dram_timing.ddrc_cfg[15].val = 0x8083f;
- dram_timing.ddrc_cfg[16].val = 0xe0e000;
- dram_timing.ddrc_cfg[17].val = 0x12040a12;
- dram_timing.ddrc_cfg[18].val = 0x2050f0f;
- dram_timing.ddrc_cfg[19].val = 0x1010009;
- dram_timing.ddrc_cfg[20].val = 0x502;
- dram_timing.ddrc_cfg[21].val = 0x20800;
- dram_timing.ddrc_cfg[22].val = 0xe100002;
- dram_timing.ddrc_cfg[23].val = 0x120;
- dram_timing.ddrc_cfg[24].val = 0xc80064;
- dram_timing.ddrc_cfg[25].val = 0x3e8001e;
- dram_timing.ddrc_cfg[26].val = 0x3207a12;
- dram_timing.ddrc_cfg[28].val = 0x4a3820e;
- dram_timing.ddrc_cfg[30].val = 0x230e;
- dram_timing.ddrc_cfg[37].val = 0x799;
- dram_timing.ddrc_cfg[38].val = 0x9141d1c;
- dram_timing.ddrc_cfg[74].val = 0x302;
- dram_timing.ddrc_cfg[83].val = 0x599;
- dram_timing.ddrc_cfg[99].val = 0x302;
- dram_timing.ddrc_cfg[108].val = 0x599;
- dram_timing.ddrphy_cfg[66].val = 0x18;
- dram_timing.ddrphy_cfg[75].val = 0x1e3;
- dram_timing.ddrphy_cfg[77].val = 0x1e3;
- dram_timing.ddrphy_cfg[79].val = 0x1e3;
- dram_timing.ddrphy_cfg[145].val = 0x3e8;
- dram_timing.fsp_msg[0].drate = 4000;
- dram_timing.fsp_msg[0].fsp_cfg[1].val = 0xfa0;
- dram_timing.fsp_msg[0].fsp_cfg[10].val = 0x3ff4;
- dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xf3;
- dram_timing.fsp_msg[0].fsp_cfg[15].val = 0x3ff4;
- dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xf3;
- dram_timing.fsp_msg[0].fsp_cfg[22].val = 0xf400;
- dram_timing.fsp_msg[0].fsp_cfg[23].val = 0xf33f;
- dram_timing.fsp_msg[0].fsp_cfg[28].val = 0xf400;
- dram_timing.fsp_msg[0].fsp_cfg[29].val = 0xf33f;
- dram_timing.fsp_msg[3].drate = 4000;
- dram_timing.fsp_msg[3].fsp_cfg[1].val = 0xfa0;
- dram_timing.fsp_msg[3].fsp_cfg[11].val = 0x3ff4;
- dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xf3;
- dram_timing.fsp_msg[3].fsp_cfg[16].val = 0x3ff4;
- dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xf3;
- dram_timing.fsp_msg[3].fsp_cfg[23].val = 0xf400;
- dram_timing.fsp_msg[3].fsp_cfg[24].val = 0xf33f;
- dram_timing.fsp_msg[3].fsp_cfg[29].val = 0xf400;
- dram_timing.fsp_msg[3].fsp_cfg[30].val = 0xf33f;
- dram_timing.ddrphy_pie[480].val = 0x465;
- dram_timing.ddrphy_pie[481].val = 0xfa;
- dram_timing.ddrphy_pie[482].val = 0x9c4;
- dram_timing.fsp_table[0] = 4000;
+ if (rev != PHYTEC_EEPROM_INVAL &&
+ (rev >= 3 || (somtype == SOM_TYPE_PCL && rev >= 1)))
+ use_2ghz_timings = true;
}
+ switch (size) {
+ case PHYTEC_IMX8MP_DDR_1GB:
+ if (use_2ghz_timings)
+ set_dram_timings_2ghz_1gb();
+ else
+ set_dram_timings_1_5ghz_1gb();
+ break;
+ case PHYTEC_IMX8MP_DDR_2GB:
+ if (use_2ghz_timings)
+ set_dram_timings_2ghz_2gb();
+ break;
+ case PHYTEC_IMX8MP_DDR_4GB:
+ set_dram_timings_1_5ghz_4gb();
+ break;
+ case PHYTEC_IMX8MP_DDR_4GB_2GHZ:
+ set_dram_timings_2ghz_4gb();
+ break;
+ case PHYTEC_IMX8MP_DDR_8GB:
+ set_dram_timings_2ghz_8gb();
+ break;
+ default:
+ goto out;
+ }
+ ddr_init(&dram_timing);
+ return;
out:
+ printf("Could not detect correct RAM size. Fallback to default.\n");
ddr_init(&dram_timing);
}
diff --git a/board/powkiddy/x55/Kconfig b/board/powkiddy/x55/Kconfig
new file mode 100644
index 0000000..a7b3ed4
--- /dev/null
+++ b/board/powkiddy/x55/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_POWKIDDY_X55_RK3566
+
+config SYS_BOARD
+ default "x55"
+
+config SYS_VENDOR
+ default "powkiddy"
+
+config SYS_CONFIG_NAME
+ default "powkiddy-x55-rk3566"
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+
+endif
diff --git a/board/powkiddy/x55/MAINTAINERS b/board/powkiddy/x55/MAINTAINERS
new file mode 100644
index 0000000..01ae8da
--- /dev/null
+++ b/board/powkiddy/x55/MAINTAINERS
@@ -0,0 +1,7 @@
+X55
+M: Chris Morgan <macromorgan@hotmail.com>
+S: Maintained
+F: board/powkiddy/x55
+F: include/configs/powkiddy-x55-rk3566.h
+F: configs/powkiddy-x55-rk3566_defconfig
+F: arch/arm/dts/rk3566-powkiddy-x55-u-boot.dtsi
diff --git a/board/powkiddy/x55/Makefile b/board/powkiddy/x55/Makefile
new file mode 100644
index 0000000..55c8c16
--- /dev/null
+++ b/board/powkiddy/x55/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2023 Chris Morgan <macromorgan@hotmail.com>
+#
+
+obj-y += x55.o
diff --git a/board/powkiddy/x55/x55.c b/board/powkiddy/x55/x55.c
new file mode 100644
index 0000000..b2703e6
--- /dev/null
+++ b/board/powkiddy/x55/x55.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023 Chris Morgan <macromorgan@hotmail.com>
+ */
+
+#include <asm/io.h>
+
+#define GPIO4_BASE 0xfe770000
+#define GPIO_SWPORT_DR_L 0x0000
+#define GPIO_SWPORT_DDR_L 0x0008
+#define GPIO_B4 BIT(12)
+#define GPIO_B5 BIT(13)
+#define GPIO_B6 BIT(14)
+
+#define GPIO_WRITEMASK(bits) ((bits) << 16)
+
+/*
+ * Start LED very early so user knows device is on. Set color
+ * to red.
+ */
+void spl_board_init(void)
+{
+ /* Set GPIO4_B4, GPIO4_B5, and GPIO4_B6 to output. */
+ writel(GPIO_WRITEMASK(GPIO_B6 | GPIO_B5 | GPIO_B4) | \
+ (GPIO_B6 | GPIO_B5 | GPIO_B4),
+ (GPIO4_BASE + GPIO_SWPORT_DDR_L));
+ /* Set GPIO4_B5 and GPIO4_B6 to 0 and GPIO4_B4 to 1. */
+ writel(GPIO_WRITEMASK(GPIO_B6 | GPIO_B5 | GPIO_B4) | GPIO_B4,
+ (GPIO4_BASE + GPIO_SWPORT_DR_L));
+}
+
+int rk_board_late_init(void)
+{
+ /* Turn off red LED and turn on orange LED. */
+ writel(GPIO_WRITEMASK(GPIO_B6 | GPIO_B5 | GPIO_B4) | GPIO_B6,
+ (GPIO4_BASE + GPIO_SWPORT_DR_L));
+
+ return 0;
+}
diff --git a/board/qualcomm/default.env b/board/qualcomm/default.env
new file mode 100644
index 0000000..dbf6f4e
--- /dev/null
+++ b/board/qualcomm/default.env
@@ -0,0 +1,11 @@
+stdin=serial,button-kbd
+stdout=serial,vidconsole
+stderr=serial,vidconsole
+preboot=scsi scan; usb start
+fastboot=fastboot -l $fastboot_addr_r usb 0
+do_boot=bootefi bootmgr
+bootmenu_0=Boot first available device=run do_boot
+bootmenu_1=Enable fastboot mode=run fastboot
+bootmenu_2=Reset device=reset
+menucmd=bootmenu
+bootcmd=run do_boot
diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
index d996eb0..ab5ea85 100644
--- a/board/raspberrypi/rpi/rpi.c
+++ b/board/raspberrypi/rpi/rpi.c
@@ -381,7 +381,7 @@
snprintf(s, sizeof(s), "0x%X", revision);
env_set("board_revision", s);
- snprintf(s, sizeof(s), "%d", rev_scheme);
+ snprintf(s, sizeof(s), "%u", rev_scheme);
env_set("board_rev_scheme", s);
/* Can't rename this to board_rev_type since it's an ABI for scripts */
snprintf(s, sizeof(s), "0x%X", rev_type);
@@ -493,10 +493,6 @@
int board_init(void)
{
-#ifdef CONFIG_HW_WATCHDOG
- hw_watchdog_init();
-#endif
-
get_board_revision();
gd->bd->bi_boot_params = 0x100;
diff --git a/board/samsung/common/exynos-uboot-spl.lds b/board/samsung/common/exynos-uboot-spl.lds
index 73cd97a..9d3b57e 100644
--- a/board/samsung/common/exynos-uboot-spl.lds
+++ b/board/samsung/common/exynos-uboot-spl.lds
@@ -41,11 +41,7 @@
. = ALIGN(4);
__image_copy_end = .;
-
- .end :
- {
- *(.__end)
- } >.sram
+ _end = .;
.bss :
{
diff --git a/board/samsung/e850-96/MAINTAINERS b/board/samsung/e850-96/MAINTAINERS
index e8b9365..b098794 100644
--- a/board/samsung/e850-96/MAINTAINERS
+++ b/board/samsung/e850-96/MAINTAINERS
@@ -2,7 +2,6 @@
M: Sam Protsenko <semen.protsenko@linaro.org>
S: Maintained
F: arch/arm/dts/exynos850-e850-96-u-boot.dtsi
-F: arch/arm/dts/exynos850-e850-96.dts
F: board/samsung/e850-96/
F: configs/e850-96_defconfig
F: doc/board/samsung/e850-96.rst
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
index b555189..b794b73 100644
--- a/board/starfive/visionfive2/spl.c
+++ b/board/starfive/visionfive2/spl.c
@@ -86,6 +86,43 @@
"tx-internal-delay-ps", "0"},
};
+static const struct starfive_vf2_pro star64_pine64[] = {
+ {"/soc/ethernet@16030000", "starfive,tx-use-rgmii-clk", NULL},
+ {"/soc/ethernet@16040000", "starfive,tx-use-rgmii-clk", NULL},
+
+ {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
+ "motorcomm,tx-clk-adj-enabled", NULL},
+ {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
+ "motorcomm,tx-clk-10-inverted", NULL},
+ {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
+ "motorcomm,tx-clk-100-inverted", NULL},
+ {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
+ "motorcomm,tx-clk-1000-inverted", NULL},
+ {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
+ "motorcomm,rx-clk-drv-microamp", "2910"},
+ {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
+ "motorcomm,rx-data-drv-microamp", "2910"},
+ {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
+ "rx-internal-delay-ps", "1900"},
+ {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
+ "tx-internal-delay-ps", "1500"},
+
+ {"/soc/ethernet@16040000/mdio/ethernet-phy@1",
+ "motorcomm,tx-clk-adj-enabled", NULL},
+ {"/soc/ethernet@16040000/mdio/ethernet-phy@1",
+ "motorcomm,tx-clk-10-inverted", NULL},
+ {"/soc/ethernet@16040000/mdio/ethernet-phy@1",
+ "motorcomm,tx-clk-100-inverted", NULL},
+ {"/soc/ethernet@16040000/mdio/ethernet-phy@1",
+ "motorcomm,rx-clk-drv-microamp", "2910"},
+ {"/soc/ethernet@16040000/mdio/ethernet-phy@1",
+ "motorcomm,rx-data-drv-microamp", "2910"},
+ {"/soc/ethernet@16040000/mdio/ethernet-phy@1",
+ "rx-internal-delay-ps", "0"},
+ {"/soc/ethernet@16040000/mdio/ethernet-phy@1",
+ "tx-internal-delay-ps", "300"},
+};
+
void spl_fdt_fixup_mars(void *fdt)
{
static const char compat[] = "milkv,mars\0starfive,jh7110";
@@ -250,6 +287,56 @@
}
}
+void spl_fdt_fixup_star64(void *fdt)
+{
+ static const char compat[] = "pine64,star64\0starfive,jh7110";
+ u32 phandle;
+ u8 i;
+ int offset;
+ int ret;
+
+ fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat));
+ fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model",
+ "Pine64 Star64");
+
+ /* gmac0 */
+ offset = fdt_path_offset(fdt, "/soc/clock-controller@17000000");
+ phandle = fdt_get_phandle(fdt, offset);
+ offset = fdt_path_offset(fdt, "/soc/ethernet@16030000");
+
+ fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle);
+ fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_AONCLK_GMAC0_TX);
+ fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle);
+ fdt_appendprop_u32(fdt, offset, "assigned-clock-parents",
+ JH7110_AONCLK_GMAC0_RMII_RTX);
+
+ /* gmac1 */
+ offset = fdt_path_offset(fdt, "/soc/clock-controller@13020000");
+ phandle = fdt_get_phandle(fdt, offset);
+ offset = fdt_path_offset(fdt, "/soc/ethernet@16040000");
+
+ fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle);
+ fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_TX);
+ fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle);
+ fdt_appendprop_u32(fdt, offset, "assigned-clock-parents",
+ JH7110_SYSCLK_GMAC1_RMII_RTX);
+
+ for (i = 0; i < ARRAY_SIZE(star64_pine64); i++) {
+ offset = fdt_path_offset(fdt, star64_pine64[i].path);
+
+ if (star64_pine64[i].value)
+ ret = fdt_setprop_u32(fdt, offset, star64_pine64[i].name,
+ dectoul(star64_pine64[i].value, NULL));
+ else
+ ret = fdt_setprop_empty(fdt, offset, star64_pine64[i].name);
+
+ if (ret) {
+ pr_err("%s set prop %s fail.\n", __func__, star64_pine64[i].name);
+ break;
+ }
+ }
+}
+
void spl_perform_fixups(struct spl_image_info *spl_image)
{
u8 version;
@@ -278,6 +365,8 @@
spl_fdt_fixup_version_b(spl_image->fdt_addr);
break;
};
+ } else if (!strncmp(product_id, "STAR64", 6)) {
+ spl_fdt_fixup_star64(spl_image->fdt_addr);
} else {
pr_err("Unknown product %s\n", product_id);
};
diff --git a/board/starfive/visionfive2/starfive_visionfive2.c b/board/starfive/visionfive2/starfive_visionfive2.c
index 6be5348..f611460 100644
--- a/board/starfive/visionfive2/starfive_visionfive2.c
+++ b/board/starfive/visionfive2/starfive_visionfive2.c
@@ -27,6 +27,8 @@
"starfive/jh7110-starfive-visionfive-2-v1.2a.dtb"
#define FDTFILE_VISIONFIVE2_1_3B \
"starfive/jh7110-starfive-visionfive-2-v1.3b.dtb"
+#define FDTFILE_PINE64_STAR64 \
+ "starfive/jh7110-pine64-star64.dtb"
/* enable U74-mc hart1~hart4 prefetcher */
static void enable_prefetcher(void)
@@ -87,6 +89,8 @@
fdtfile = FDTFILE_VISIONFIVE2_1_3B;
break;
}
+ } else if (!strncmp(product_id, "STAR64", 6)) {
+ fdtfile = FDTFILE_PINE64_STAR64;
} else {
log_err("Unknown product\n");
return;
diff --git a/board/theobroma-systems/jaguar_rk3588/MAINTAINERS b/board/theobroma-systems/jaguar_rk3588/MAINTAINERS
index 28fae4b..ab7051b 100644
--- a/board/theobroma-systems/jaguar_rk3588/MAINTAINERS
+++ b/board/theobroma-systems/jaguar_rk3588/MAINTAINERS
@@ -1,6 +1,6 @@
JAGUAR-RK3588 (SBC-RK3588-AMR Single Board Computer)
-M: Klaus Goger <klaus.goger@theobroma-systems.com>
-M: Quentin Schulz <quentin.schulz@theobroma-systems.com>
+M: Klaus Goger <klaus.goger@cherry.de>
+M: Quentin Schulz <quentin.schulz@cherry.de>
M: Heiko Stuebner <heiko.stuebner@cherry.de>
S: Maintained
F: board/theobroma-systems/jaguar_rk3588
@@ -9,5 +9,5 @@
F: include/configs/jaguar_rk3588.h
F: arch/arm/dts/rk3588-jaguar*
F: configs/jaguar-rk3588_defconfig
-W: https://theobroma-systems.com/product/jaguar-sbc-rk3588/
-T: git git://git.theobroma-systems.com/jaguar-u-boot.git
+W: https://embedded.cherry.de/product/jaguar-sbc-rk3588/
+T: git git://git.embedded.cherry.de/jaguar-u-boot.git
diff --git a/board/theobroma-systems/lion_rk3368/MAINTAINERS b/board/theobroma-systems/lion_rk3368/MAINTAINERS
index a5b4cb3..ed35fee 100644
--- a/board/theobroma-systems/lion_rk3368/MAINTAINERS
+++ b/board/theobroma-systems/lion_rk3368/MAINTAINERS
@@ -1,6 +1,6 @@
LION-RK3368 (RK3368-uQ7 system-on-module)
-M: Quentin Schulz <quentin.schulz@theobroma-systems.com>
-M: Klaus Goger <klaus.goger@theobroma-systems.com>
+M: Quentin Schulz <quentin.schulz@cherry.de>
+M: Klaus Goger <klaus.goger@cherry.de>
S: Maintained
F: board/theobroma-systems/lion_rk3368
F: include/configs/lion_rk3368.h
diff --git a/board/theobroma-systems/puma_rk3399/MAINTAINERS b/board/theobroma-systems/puma_rk3399/MAINTAINERS
index 7e84a5b..2536e34 100644
--- a/board/theobroma-systems/puma_rk3399/MAINTAINERS
+++ b/board/theobroma-systems/puma_rk3399/MAINTAINERS
@@ -1,6 +1,6 @@
PUMA-RK3399
-M: Quentin Schulz <quentin.schulz@theobroma-systems.com>
-M: Klaus Goger <klaus.goger@theobroma-systems.com>
+M: Quentin Schulz <quentin.schulz@cherry.de>
+M: Klaus Goger <klaus.goger@cherry.de>
S: Maintained
F: board/theobroma-systems/puma_rk3399
F: board/theobroma-systems/common
@@ -8,5 +8,5 @@
F: include/configs/puma_rk3399.h
F: arch/arm/dts/rk3399-puma*
F: configs/puma-rk3399_defconfig
-W: https://www.theobroma-systems.com/rk3399-q7/tech-specs
-T: git git://git.theobroma-systems.com/puma-u-boot.git
+W: https://embedded.cherry.de/product/puma-som-rk3399-q7/
+T: git git://git.embedded.cherry.de/puma-u-boot.git
diff --git a/board/theobroma-systems/ringneck_px30/MAINTAINERS b/board/theobroma-systems/ringneck_px30/MAINTAINERS
index 97baf334..2aff91f 100644
--- a/board/theobroma-systems/ringneck_px30/MAINTAINERS
+++ b/board/theobroma-systems/ringneck_px30/MAINTAINERS
@@ -1,6 +1,6 @@
RINGNECK-PX30
-M: Quentin Schulz <quentin.schulz@theobroma-systems.com>
-M: Klaus Goger <klaus.goger@theobroma-systems.com>
+M: Quentin Schulz <quentin.schulz@cherry.de>
+M: Klaus Goger <klaus.goger@cherry.de>
S: Maintained
F: board/theobroma-systems/ringneck_px30
F: board/theobroma-systems/common
@@ -8,4 +8,5 @@
F: include/configs/ringneck_px30.h
F: arch/arm/dts/px30-ringneck*
F: configs/ringneck-px30_defconfig
-W: https://theobroma-systems.com/product/ringneck-som-px30-uq7/
+W: https://embedded.cherry.de/product/ringneck-som-px30-uq7/
+T: git git://git.embedded.cherry.de/ringneck-u-boot.git
diff --git a/board/theobroma-systems/tiger_rk3588/Kconfig b/board/theobroma-systems/tiger_rk3588/Kconfig
new file mode 100644
index 0000000..2c6ac6a
--- /dev/null
+++ b/board/theobroma-systems/tiger_rk3588/Kconfig
@@ -0,0 +1,16 @@
+if TARGET_TIGER_RK3588
+
+config SYS_BOARD
+ default "tiger_rk3588"
+
+config SYS_VENDOR
+ default "theobroma-systems"
+
+config SYS_CONFIG_NAME
+ default "tiger_rk3588"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ENV_IS_NOWHERE
+
+endif
diff --git a/board/theobroma-systems/tiger_rk3588/MAINTAINERS b/board/theobroma-systems/tiger_rk3588/MAINTAINERS
new file mode 100644
index 0000000..e5aab4b
--- /dev/null
+++ b/board/theobroma-systems/tiger_rk3588/MAINTAINERS
@@ -0,0 +1,13 @@
+TIGER-RK3588 (SOM-RK3588-Q7)
+M: Klaus Goger <klaus.goger@cherry.de>
+M: Quentin Schulz <quentin.schulz@cherry.de>
+M: Heiko Stuebner <heiko.stuebner@cherry.de>
+S: Maintained
+F: board/theobroma-systems/tiger_rk3588
+F: board/theobroma-systems/common
+F: doc/board/theobroma-systems/
+F: include/configs/tiger_rk3588.h
+F: arch/arm/dts/rk3588-tiger*
+F: configs/tiger-rk3588_defconfig
+W: https://embedded.cherry.de/product/tiger-som-rk3588-q7/
+T: git git://git.embedded.cherry.de/tiger-u-boot.git
diff --git a/board/theobroma-systems/tiger_rk3588/Makefile b/board/theobroma-systems/tiger_rk3588/Makefile
new file mode 100644
index 0000000..5c4c484
--- /dev/null
+++ b/board/theobroma-systems/tiger_rk3588/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (c) 2024 Theobroma Systems Design und Consulting GmbH
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += tiger_rk3588.o
+ifneq ($(CONFIG_SPL_BUILD),y)
+obj-y += ../common/common.o
+endif
diff --git a/board/theobroma-systems/tiger_rk3588/tiger_rk3588.c b/board/theobroma-systems/tiger_rk3588/tiger_rk3588.c
new file mode 100644
index 0000000..a6d44f1
--- /dev/null
+++ b/board/theobroma-systems/tiger_rk3588/tiger_rk3588.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2023 Theobroma Systems Design und Consulting GmbH
+ */
+
+#include <phy.h>
+#include <eth_phy.h>
+
+#include <asm/types.h>
+#include <asm/arch-rockchip/cru_rk3588.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/ioc_rk3588.h>
+#include <asm-generic/u-boot.h>
+#include <dm/device.h>
+#include <dm/uclass-id.h>
+#include <linux/bitfield.h>
+
+#include "../common/common.h"
+
+#define GPIO2C3_SEL_MASK GENMASK(15, 12)
+#define GPIO2C3_ETH0_REFCLKO_25M FIELD_PREP(GPIO2C3_SEL_MASK, 1)
+
+#define REFCLKO25M_ETH0_OUT_SEL_MASK BIT(15)
+#define REFCLKO25M_ETH0_OUT_SEL_CPLL FIELD_PREP(REFCLKO25M_ETH0_OUT_SEL_MASK, 1)
+#define REFCLKO25M_ETH0_OUT_DIV_MASK GENMASK(14, 8)
+#define REFCLKO25M_ETH0_OUT_DIV(x) FIELD_PREP(REFCLKO25M_ETH0_OUT_DIV_MASK, (x) - 1)
+
+#define REFCLKO25M_ETH0_OUT_EN BIT(4)
+
+void setup_eth0refclko(void)
+{
+ /* Configure and enable ETH0_REFCLKO_25MHz */
+ static struct rk3588_bus_ioc * const bus_ioc = (void *)BUS_IOC_BASE;
+ static struct rk3588_cru * const cru = (void *)CRU_BASE;
+
+ /* 1. Pinmux */
+ rk_clrsetreg(&bus_ioc->gpio2c_iomux_sel_l, GPIO2C3_SEL_MASK, GPIO2C3_ETH0_REFCLKO_25M);
+ /* 2. Parent clock selection + divider => CPLL (1.5GHz) / 60 => 25MHz */
+ rk_clrsetreg(&cru->clksel_con[15],
+ REFCLKO25M_ETH0_OUT_SEL_MASK | REFCLKO25M_ETH0_OUT_DIV_MASK,
+ REFCLKO25M_ETH0_OUT_SEL_CPLL | REFCLKO25M_ETH0_OUT_DIV(60));
+ /* 3. Enable clock */
+ rk_clrreg(&cru->clkgate_con[5], REFCLKO25M_ETH0_OUT_EN);
+}
+
+int rockchip_early_misc_init_r(void)
+{
+ setup_boottargets();
+
+ setup_eth0refclko();
+
+ return 0;
+}
diff --git a/board/ti/am335x/MAINTAINERS b/board/ti/am335x/MAINTAINERS
index 219c871..ed8800a 100644
--- a/board/ti/am335x/MAINTAINERS
+++ b/board/ti/am335x/MAINTAINERS
@@ -3,6 +3,5 @@
S: Maintained
F: board/ti/am335x/
F: include/configs/am335x_evm.h
-F: configs/am335x_boneblack_vboot_defconfig
F: configs/am335x_evm_defconfig
F: configs/am335x_evm_spiboot_defconfig
diff --git a/board/ti/am62px/evm.c b/board/ti/am62px/evm.c
index 97a95ce..1a2c46c 100644
--- a/board/ti/am62px/evm.c
+++ b/board/ti/am62px/evm.c
@@ -6,6 +6,7 @@
*
*/
+#include <efi_loader.h>
#include <asm/arch/hardware.h>
#include <asm/io.h>
#include <dm/uclass.h>
@@ -13,6 +14,39 @@
#include <fdt_support.h>
#include <spl.h>
+struct efi_fw_image fw_images[] = {
+ {
+ .image_type_id = AM62PX_SK_TIBOOT3_IMAGE_GUID,
+ .fw_name = u"AM62PX_SK_TIBOOT3",
+ .image_index = 1,
+ },
+ {
+ .image_type_id = AM62PX_SK_SPL_IMAGE_GUID,
+ .fw_name = u"AM62PX_SK_SPL",
+ .image_index = 2,
+ },
+ {
+ .image_type_id = AM62PX_SK_UBOOT_IMAGE_GUID,
+ .fw_name = u"AM62PX_SK_UBOOT",
+ .image_index = 3,
+ }
+};
+
+struct efi_capsule_update_info update_info = {
+ .dfu_string = "sf 0:0=tiboot3.bin raw 0 80000;"
+ "tispl.bin raw 80000 200000;u-boot.img raw 280000 400000",
+ .num_images = ARRAY_SIZE(fw_images),
+ .images = fw_images,
+};
+
+#if IS_ENABLED(CONFIG_SET_DFU_ALT_INFO)
+void set_dfu_alt_info(char *interface, char *devstr)
+{
+ if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT))
+ env_set("dfu_alt_info", update_info.dfu_string);
+}
+#endif
+
int board_init(void)
{
return 0;
diff --git a/board/ti/am62x/MAINTAINERS b/board/ti/am62x/MAINTAINERS
index 105e741..562a5c6 100644
--- a/board/ti/am62x/MAINTAINERS
+++ b/board/ti/am62x/MAINTAINERS
@@ -1,8 +1,10 @@
AM62x BOARD
-M: Dave Gerlach <d-gerlach@ti.com>
+M: Bryan Brattlof <bb@ti.com>
M: Tom Rini <trini@konsulko.com>
S: Maintained
F: board/ti/am62x/
F: include/configs/am62x_evm.h
F: configs/am62x_evm_r5_defconfig
F: configs/am62x_evm_a53_defconfig
+F: configs/am62x_lpsk_r5_defconfig
+F: configs/am62x_lpsk_a53_defconfig
diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c
index b3e8680..9bdd022 100644
--- a/board/ti/am62x/evm.c
+++ b/board/ti/am62x/evm.c
@@ -7,6 +7,7 @@
*
*/
+#include <efi_loader.h>
#include <env.h>
#include <spl.h>
#include <init.h>
@@ -46,6 +47,39 @@
}
#endif
+struct efi_fw_image fw_images[] = {
+ {
+ .image_type_id = AM62X_SK_TIBOOT3_IMAGE_GUID,
+ .fw_name = u"AM62X_SK_TIBOOT3",
+ .image_index = 1,
+ },
+ {
+ .image_type_id = AM62X_SK_SPL_IMAGE_GUID,
+ .fw_name = u"AM62X_SK_SPL",
+ .image_index = 2,
+ },
+ {
+ .image_type_id = AM62X_SK_UBOOT_IMAGE_GUID,
+ .fw_name = u"AM62X_SK_UBOOT",
+ .image_index = 3,
+ }
+};
+
+struct efi_capsule_update_info update_info = {
+ .dfu_string = "sf 0:0=tiboot3.bin raw 0 80000;"
+ "tispl.bin raw 80000 200000;u-boot.img raw 280000 400000",
+ .num_images = ARRAY_SIZE(fw_images),
+ .images = fw_images,
+};
+
+#if IS_ENABLED(CONFIG_SET_DFU_ALT_INFO)
+void set_dfu_alt_info(char *interface, char *devstr)
+{
+ if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT))
+ env_set("dfu_alt_info", update_info.dfu_string);
+}
+#endif
+
int board_init(void)
{
return 0;
diff --git a/board/ti/am64x/am64x.env b/board/ti/am64x/am64x.env
index 9a8812d..8ad805a 100644
--- a/board/ti/am64x/am64x.env
+++ b/board/ti/am64x/am64x.env
@@ -39,3 +39,8 @@
run get_kern_usb;
run get_fdt_usb;
run run_kern;
+
+#if CONFIG_TI_ICSSG_PRUETH
+storage_interface=mmc
+fw_dev_part=1:2
+#endif
diff --git a/board/ti/am64x/evm.c b/board/ti/am64x/evm.c
index b8de69d..609e5cf 100644
--- a/board/ti/am64x/evm.c
+++ b/board/ti/am64x/evm.c
@@ -7,6 +7,7 @@
*
*/
+#include <efi_loader.h>
#include <asm/io.h>
#include <dm/uclass.h>
#include <k3-ddrss.h>
@@ -27,6 +28,39 @@
DECLARE_GLOBAL_DATA_PTR;
+struct efi_fw_image fw_images[] = {
+ {
+ .image_type_id = AM64X_SK_TIBOOT3_IMAGE_GUID,
+ .fw_name = u"AM64X_SK_TIBOOT3",
+ .image_index = 1,
+ },
+ {
+ .image_type_id = AM64X_SK_SPL_IMAGE_GUID,
+ .fw_name = u"AM64X_SK_SPL",
+ .image_index = 2,
+ },
+ {
+ .image_type_id = AM64X_SK_UBOOT_IMAGE_GUID,
+ .fw_name = u"AM64X_SK_UBOOT",
+ .image_index = 3,
+ }
+};
+
+struct efi_capsule_update_info update_info = {
+ .dfu_string = "sf 0:0=tiboot3.bin raw 0 100000;"
+ "tispl.bin raw 100000 200000;u-boot.img raw 300000 400000",
+ .num_images = ARRAY_SIZE(fw_images),
+ .images = fw_images,
+};
+
+#if IS_ENABLED(CONFIG_SET_DFU_ALT_INFO)
+void set_dfu_alt_info(char *interface, char *devstr)
+{
+ if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT))
+ env_set("dfu_alt_info", update_info.dfu_string);
+}
+#endif
+
int board_init(void)
{
return 0;
diff --git a/board/ti/common/fdt_ops.c b/board/ti/common/fdt_ops.c
index eb917be..8a33009 100644
--- a/board/ti/common/fdt_ops.c
+++ b/board/ti/common/fdt_ops.c
@@ -6,7 +6,7 @@
*/
#include <env.h>
-#include <vsprintf.h>
+#include <stdio.h>
#include "fdt_ops.h"
void ti_set_fdt_env(const char *board_name, struct ti_fdt_map *fdt_map)
diff --git a/board/ti/j721e/MAINTAINERS b/board/ti/j721e/MAINTAINERS
index f5ca7d0..06aba53 100644
--- a/board/ti/j721e/MAINTAINERS
+++ b/board/ti/j721e/MAINTAINERS
@@ -5,5 +5,7 @@
F: include/configs/j721e_evm.h
F: configs/j721e_evm_r5_defconfig
F: configs/j721e_evm_a72_defconfig
+F: configs/j721e_sk_r5_defconfig
+F: configs/j721e_sk_a72_defconfig
F: configs/j7200_evm_r5_defconfig
F: configs/j7200_evm_a72_defconfig
diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index 539eaf4..f3452ff 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -7,6 +7,7 @@
*
*/
+#include <efi_loader.h>
#include <generic-phy.h>
#include <image.h>
#include <net.h>
@@ -32,6 +33,45 @@
DECLARE_GLOBAL_DATA_PTR;
+struct efi_fw_image fw_images[] = {
+ {
+ .image_type_id = J721E_SK_TIBOOT3_IMAGE_GUID,
+ .fw_name = u"J721E_SK_TIBOOT3",
+ .image_index = 1,
+ },
+ {
+ .image_type_id = J721E_SK_SPL_IMAGE_GUID,
+ .fw_name = u"J721E_SK_SPL",
+ .image_index = 2,
+ },
+ {
+ .image_type_id = J721E_SK_UBOOT_IMAGE_GUID,
+ .fw_name = u"J721E_SK_UBOOT",
+ .image_index = 3,
+ },
+ {
+ .image_type_id = J721E_SK_SYSFW_IMAGE_GUID,
+ .fw_name = u"J721E_SK_SYSFW",
+ .image_index = 4,
+ }
+};
+
+struct efi_capsule_update_info update_info = {
+ .dfu_string = "sf 0:0=tiboot3.bin raw 0 80000;"
+ "tispl.bin raw 80000 200000;u-boot.img raw 280000 400000;"
+ "sysfw.itb raw 6C0000 100000",
+ .num_images = ARRAY_SIZE(fw_images),
+ .images = fw_images,
+};
+
+#if IS_ENABLED(CONFIG_SET_DFU_ALT_INFO)
+void set_dfu_alt_info(char *interface, char *devstr)
+{
+ if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT))
+ env_set("dfu_alt_info", update_info.dfu_string);
+}
+#endif
+
int board_init(void)
{
return 0;
diff --git a/board/ti/j722s/Kconfig b/board/ti/j722s/Kconfig
new file mode 100644
index 0000000..68c214e
--- /dev/null
+++ b/board/ti/j722s/Kconfig
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+#
+
+if TARGET_J722S_R5_EVM || TARGET_J722S_A53_EVM
+
+config SYS_BOARD
+ default "j722s"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_CONFIG_NAME
+ default "j722s_evm"
+
+source "board/ti/common/Kconfig"
+
+endif
+
+if TARGET_J722S_R5_EVM
+
+config SPL_LDSCRIPT
+ default "arch/arm/mach-omap2/u-boot-spl.lds"
+
+endif
diff --git a/board/ti/j722s/MAINTAINERS b/board/ti/j722s/MAINTAINERS
new file mode 100644
index 0000000..7908c30
--- /dev/null
+++ b/board/ti/j722s/MAINTAINERS
@@ -0,0 +1,9 @@
+J722S BOARD
+M: Vaishnav Achath <vaishnav.a@ti.com>
+M: Jayesh Choudhary <j-choudhary@ti.com>
+M: Tom Rini <trini@konsulko.com>
+S: Maintained
+F: board/ti/j722s/
+F: include/configs/j722s_evm.h
+F: configs/j722s_evm_r5_defconfig
+F: configs/j722s_evm_a53_defconfig
diff --git a/board/ti/j722s/Makefile b/board/ti/j722s/Makefile
new file mode 100644
index 0000000..20d2ec9
--- /dev/null
+++ b/board/ti/j722s/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += evm.o
diff --git a/board/ti/j722s/board-cfg.yaml b/board/ti/j722s/board-cfg.yaml
new file mode 100644
index 0000000..f9a4c43
--- /dev/null
+++ b/board/ti/j722s/board-cfg.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Board configuration for J722S
+#
+
+---
+
+board-cfg:
+ rev:
+ boardcfg_abi_maj: 0x0
+ boardcfg_abi_min: 0x1
+ control:
+ subhdr:
+ magic: 0xC1D3
+ size: 7
+ main_isolation_enable: 0x5A
+ main_isolation_hostid: 0x2
+ secproxy:
+ subhdr:
+ magic: 0x1207
+ size: 7
+ scaling_factor: 0x1
+ scaling_profile: 0x1
+ disable_main_nav_secure_proxy: 0
+ msmc:
+ subhdr:
+ magic: 0xA5C3
+ size: 5
+ msmc_cache_size: 0x0
+ debug_cfg:
+ subhdr:
+ magic: 0x020C
+ size: 8
+ trace_dst_enables: 0x00
+ trace_src_enables: 0x00
diff --git a/board/ti/j722s/evm.c b/board/ti/j722s/evm.c
new file mode 100644
index 0000000..515aaa8
--- /dev/null
+++ b/board/ti/j722s/evm.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board specific initialization for J722S platforms
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ */
+
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include <dm/uclass.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <spl.h>
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
diff --git a/board/ti/j722s/j722s.env b/board/ti/j722s/j722s.env
new file mode 100644
index 0000000..f8b6aff
--- /dev/null
+++ b/board/ti/j722s/j722s.env
@@ -0,0 +1,15 @@
+#include <env/ti/ti_common.env>
+#include <env/ti/mmc.env>
+
+name_kern=Image
+console=ttyS2,115200n8
+args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x02800000
+ ${mtdparts}
+run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
+
+boot_targets=mmc1 mmc0 pxe dhcp
+boot=mmc
+mmcdev=1
+bootpart=1:2
+bootdir=/boot
+rd_spec=-
diff --git a/board/ti/j722s/pm-cfg.yaml b/board/ti/j722s/pm-cfg.yaml
new file mode 100644
index 0000000..46b3ad2
--- /dev/null
+++ b/board/ti/j722s/pm-cfg.yaml
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Power management configuration for J722S
+#
+
+---
+
+pm-cfg:
+ rev:
+ boardcfg_abi_maj: 0x0
+ boardcfg_abi_min: 0x1
diff --git a/board/ti/j722s/rm-cfg.yaml b/board/ti/j722s/rm-cfg.yaml
new file mode 100644
index 0000000..21ca301
--- /dev/null
+++ b/board/ti/j722s/rm-cfg.yaml
@@ -0,0 +1,1119 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Resource management configuration for J722S
+#
+
+---
+
+rm-cfg:
+ rm_boardcfg:
+ rev:
+ boardcfg_abi_maj: 0x0
+ boardcfg_abi_min: 0x1
+ host_cfg:
+ subhdr:
+ magic: 0x4C41
+ size: 356
+ host_cfg_entries:
+ -
+ host_id: 12
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ -
+ host_id: 20
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ -
+ host_id: 22
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ -
+ host_id: 30
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ -
+ host_id: 36
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ -
+ host_id: 38
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ resasg:
+ subhdr:
+ magic: 0x7B25
+ size: 8
+ resasg_entries_size: 1160
+ reserved: 0
+ resasg_entries:
+ -
+ start_resource: 0
+ num_resource: 16
+ type: 192
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 6
+ type: 192
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 34
+ num_resource: 2
+ type: 192
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 4
+ type: 320
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 4
+ num_resource: 4
+ type: 320
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 12
+ num_resource: 4
+ type: 320
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 26
+ type: 384
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 50176
+ num_resource: 164
+ type: 1666
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 1667
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 16
+ type: 1677
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 6
+ type: 1677
+ host_id: 20
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 6
+ type: 1677
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 22
+ num_resource: 2
+ type: 1677
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 24
+ num_resource: 4
+ type: 1677
+ host_id: 22
+ reserved: 0
+ -
+ start_resource: 28
+ num_resource: 4
+ type: 1677
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 57
+ num_resource: 16
+ type: 1678
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 73
+ num_resource: 5
+ type: 1678
+ host_id: 20
+ reserved: 0
+ -
+ start_resource: 73
+ num_resource: 5
+ type: 1678
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 78
+ num_resource: 2
+ type: 1678
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 80
+ num_resource: 2
+ type: 1678
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 32
+ num_resource: 12
+ type: 1679
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 44
+ num_resource: 6
+ type: 1679
+ host_id: 20
+ reserved: 0
+ -
+ start_resource: 44
+ num_resource: 6
+ type: 1679
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 50
+ num_resource: 2
+ type: 1679
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 52
+ num_resource: 2
+ type: 1679
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 54
+ num_resource: 3
+ type: 1679
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 16
+ type: 1696
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 6
+ type: 1696
+ host_id: 20
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 6
+ type: 1696
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 22
+ num_resource: 2
+ type: 1696
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 24
+ num_resource: 4
+ type: 1696
+ host_id: 22
+ reserved: 0
+ -
+ start_resource: 28
+ num_resource: 4
+ type: 1696
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 16
+ type: 1697
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 5
+ type: 1697
+ host_id: 20
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 5
+ type: 1697
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 21
+ num_resource: 2
+ type: 1697
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 23
+ num_resource: 2
+ type: 1697
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 12
+ type: 1698
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 12
+ num_resource: 6
+ type: 1698
+ host_id: 20
+ reserved: 0
+ -
+ start_resource: 12
+ num_resource: 6
+ type: 1698
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 18
+ num_resource: 2
+ type: 1698
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 20
+ num_resource: 2
+ type: 1698
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 22
+ num_resource: 3
+ type: 1698
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 7
+ num_resource: 21
+ type: 1802
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 44
+ num_resource: 36
+ type: 1802
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 44
+ num_resource: 36
+ type: 1802
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 84
+ num_resource: 16
+ type: 1802
+ host_id: 20
+ reserved: 0
+ -
+ start_resource: 100
+ num_resource: 16
+ type: 1802
+ host_id: 22
+ reserved: 0
+ -
+ start_resource: 154
+ num_resource: 14
+ type: 1802
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 168
+ num_resource: 16
+ type: 1802
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 17
+ num_resource: 512
+ type: 1805
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 529
+ num_resource: 256
+ type: 1805
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 529
+ num_resource: 256
+ type: 1805
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 785
+ num_resource: 128
+ type: 1805
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 913
+ num_resource: 128
+ type: 1805
+ host_id: 20
+ reserved: 0
+ -
+ start_resource: 1041
+ num_resource: 128
+ type: 1805
+ host_id: 22
+ reserved: 0
+ -
+ start_resource: 1169
+ num_resource: 128
+ type: 1805
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 1297
+ num_resource: 239
+ type: 1805
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 4096
+ num_resource: 29
+ type: 1807
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 4608
+ num_resource: 99
+ type: 1808
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 5120
+ num_resource: 24
+ type: 1809
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 5632
+ num_resource: 51
+ type: 1810
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 6144
+ num_resource: 51
+ type: 1811
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 8192
+ num_resource: 32
+ type: 1812
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 8704
+ num_resource: 32
+ type: 1813
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 9216
+ num_resource: 32
+ type: 1814
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 9728
+ num_resource: 25
+ type: 1815
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 10240
+ num_resource: 25
+ type: 1816
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 10752
+ num_resource: 25
+ type: 1817
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 11264
+ num_resource: 25
+ type: 1818
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 11776
+ num_resource: 25
+ type: 1819
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 12288
+ num_resource: 25
+ type: 1820
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 1923
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 10
+ type: 1936
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1936
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1936
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 13
+ num_resource: 3
+ type: 1936
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 3
+ type: 1936
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 64
+ type: 1937
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 64
+ type: 1937
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 83
+ num_resource: 8
+ type: 1938
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 91
+ num_resource: 8
+ type: 1939
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 99
+ num_resource: 10
+ type: 1942
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 109
+ num_resource: 3
+ type: 1942
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 109
+ num_resource: 3
+ type: 1942
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 112
+ num_resource: 3
+ type: 1942
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 115
+ num_resource: 3
+ type: 1942
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 118
+ num_resource: 16
+ type: 1943
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 118
+ num_resource: 16
+ type: 1943
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 134
+ num_resource: 8
+ type: 1944
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 134
+ num_resource: 8
+ type: 1945
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 142
+ num_resource: 8
+ type: 1946
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 142
+ num_resource: 8
+ type: 1947
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 10
+ type: 1955
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1955
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1955
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 13
+ num_resource: 3
+ type: 1955
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 3
+ type: 1955
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 8
+ type: 1956
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 8
+ type: 1956
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 27
+ num_resource: 1
+ type: 1957
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 28
+ num_resource: 1
+ type: 1958
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 10
+ type: 1961
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1961
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1961
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 13
+ num_resource: 3
+ type: 1961
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 3
+ type: 1961
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 10
+ type: 1962
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1962
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1962
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 13
+ num_resource: 3
+ type: 1962
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 3
+ type: 1962
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 1
+ type: 1963
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 1
+ type: 1963
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 16
+ type: 1964
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 16
+ type: 1964
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 20
+ num_resource: 1
+ type: 1965
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 35
+ num_resource: 8
+ type: 1966
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 21
+ num_resource: 1
+ type: 1967
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 35
+ num_resource: 8
+ type: 1968
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 22
+ num_resource: 1
+ type: 1969
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 43
+ num_resource: 8
+ type: 1970
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 23
+ num_resource: 1
+ type: 1971
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 43
+ num_resource: 8
+ type: 1972
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 2112
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 2
+ num_resource: 2
+ type: 2122
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 51200
+ num_resource: 80
+ type: 12738
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 12739
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 8
+ num_resource: 12
+ type: 12750
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 20
+ num_resource: 20
+ type: 12750
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 8
+ type: 12751
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 12
+ type: 12769
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 12
+ num_resource: 20
+ type: 12769
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 8
+ type: 12770
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 8
+ type: 12810
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 22
+ num_resource: 18
+ type: 12810
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 12288
+ num_resource: 64
+ type: 12813
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 12352
+ num_resource: 64
+ type: 12813
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 12416
+ num_resource: 88
+ type: 12813
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 1536
+ num_resource: 8
+ type: 12823
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 2048
+ num_resource: 8
+ type: 12824
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 2560
+ num_resource: 8
+ type: 12825
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 3072
+ num_resource: 32
+ type: 12826
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 3584
+ num_resource: 32
+ type: 12827
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 4096
+ num_resource: 32
+ type: 12828
+ host_id: 128
+ reserved: 0
diff --git a/board/ti/j722s/sec-cfg.yaml b/board/ti/j722s/sec-cfg.yaml
new file mode 100644
index 0000000..a41374b3
--- /dev/null
+++ b/board/ti/j722s/sec-cfg.yaml
@@ -0,0 +1,379 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Security management configuration for J722S
+#
+
+---
+
+sec-cfg:
+ rev:
+ boardcfg_abi_maj: 0x0
+ boardcfg_abi_min: 0x1
+ processor_acl_list:
+ subhdr:
+ magic: 0xF1EA
+ size: 164
+ proc_acl_entries:
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ host_hierarchy:
+ subhdr:
+ magic: 0x8D27
+ size: 68
+ host_hierarchy_entries:
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ otp_config:
+ subhdr:
+ magic: 0x4081
+ size: 69
+ write_host_id: 0
+ otp_entry:
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ dkek_config:
+ subhdr:
+ magic: 0x5170
+ size: 12
+ allowed_hosts: [128, 0, 0, 0]
+ allow_dkek_export_tisci: 0x5A
+ rsvd: [0, 0, 0]
+ sa2ul_cfg:
+ subhdr:
+ magic: 0x23BE
+ size: 0
+ auth_resource_owner: 0
+ enable_saul_psil_global_config_writes: 0x5A
+ rsvd: [0, 0]
+ sec_dbg_config:
+ subhdr:
+ magic: 0x42AF
+ size: 16
+ allow_jtag_unlock: 0x5A
+ allow_wildcard_unlock: 0x5A
+ allowed_debug_level_rsvd: 0
+ rsvd: 0
+ min_cert_rev: 0x0
+ jtag_unlock_hosts: [0, 0, 0, 0]
+ sec_handover_cfg:
+ subhdr:
+ magic: 0x608F
+ size: 10
+ handover_msg_sender: 0
+ handover_to_host_id: 0
+ rsvd: [0, 0, 0, 0]
diff --git a/board/ti/j722s/tifs-rm-cfg.yaml b/board/ti/j722s/tifs-rm-cfg.yaml
new file mode 100644
index 0000000..5e8d7e0
--- /dev/null
+++ b/board/ti/j722s/tifs-rm-cfg.yaml
@@ -0,0 +1,981 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Resource management configuration for J722S
+#
+
+---
+
+tifs-rm-cfg:
+ rm_boardcfg:
+ rev:
+ boardcfg_abi_maj: 0x0
+ boardcfg_abi_min: 0x1
+ host_cfg:
+ subhdr:
+ magic: 0x4C41
+ size: 356
+ host_cfg_entries:
+ - #1
+ host_id: 12
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - #2
+ host_id: 20
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - #3
+ host_id: 22
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - #4
+ host_id: 30
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - #5
+ host_id: 36
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - #6
+ host_id: 38
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - #7
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #8
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #9
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #10
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #11
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #12
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #13
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #14
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #15
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #16
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #17
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #18
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #19
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #20
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #21
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #22
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #23
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #24
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #25
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #26
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #27
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #28
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #29
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #30
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #31
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #32
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ resasg:
+ subhdr:
+ magic: 0x7B25
+ size: 8
+ resasg_entries_size: 976
+ reserved: 0
+ resasg_entries:
+ -
+ start_resource: 0
+ num_resource: 16
+ type: 1677
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 6
+ type: 1677
+ host_id: 20
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 6
+ type: 1677
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 22
+ num_resource: 2
+ type: 1677
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 24
+ num_resource: 4
+ type: 1677
+ host_id: 22
+ reserved: 0
+ -
+ start_resource: 28
+ num_resource: 4
+ type: 1677
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 57
+ num_resource: 16
+ type: 1678
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 73
+ num_resource: 5
+ type: 1678
+ host_id: 20
+ reserved: 0
+ -
+ start_resource: 73
+ num_resource: 5
+ type: 1678
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 78
+ num_resource: 2
+ type: 1678
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 80
+ num_resource: 2
+ type: 1678
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 32
+ num_resource: 12
+ type: 1679
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 44
+ num_resource: 6
+ type: 1679
+ host_id: 20
+ reserved: 0
+ -
+ start_resource: 44
+ num_resource: 6
+ type: 1679
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 50
+ num_resource: 2
+ type: 1679
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 52
+ num_resource: 2
+ type: 1679
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 54
+ num_resource: 3
+ type: 1679
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 16
+ type: 1696
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 6
+ type: 1696
+ host_id: 20
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 6
+ type: 1696
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 22
+ num_resource: 2
+ type: 1696
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 24
+ num_resource: 4
+ type: 1696
+ host_id: 22
+ reserved: 0
+ -
+ start_resource: 28
+ num_resource: 4
+ type: 1696
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 16
+ type: 1697
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 5
+ type: 1697
+ host_id: 20
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 5
+ type: 1697
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 21
+ num_resource: 2
+ type: 1697
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 23
+ num_resource: 2
+ type: 1697
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 12
+ type: 1698
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 12
+ num_resource: 6
+ type: 1698
+ host_id: 20
+ reserved: 0
+ -
+ start_resource: 12
+ num_resource: 6
+ type: 1698
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 18
+ num_resource: 2
+ type: 1698
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 20
+ num_resource: 2
+ type: 1698
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 22
+ num_resource: 3
+ type: 1698
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 7
+ num_resource: 21
+ type: 1802
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 44
+ num_resource: 36
+ type: 1802
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 44
+ num_resource: 36
+ type: 1802
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 84
+ num_resource: 16
+ type: 1802
+ host_id: 20
+ reserved: 0
+ -
+ start_resource: 100
+ num_resource: 16
+ type: 1802
+ host_id: 22
+ reserved: 0
+ -
+ start_resource: 154
+ num_resource: 14
+ type: 1802
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 168
+ num_resource: 16
+ type: 1802
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 4096
+ num_resource: 29
+ type: 1807
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 4608
+ num_resource: 99
+ type: 1808
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 5120
+ num_resource: 24
+ type: 1809
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 5632
+ num_resource: 51
+ type: 1810
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 6144
+ num_resource: 51
+ type: 1811
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 8192
+ num_resource: 32
+ type: 1812
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 8704
+ num_resource: 32
+ type: 1813
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 9216
+ num_resource: 32
+ type: 1814
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 9728
+ num_resource: 25
+ type: 1815
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 10240
+ num_resource: 25
+ type: 1816
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 10752
+ num_resource: 25
+ type: 1817
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 11264
+ num_resource: 25
+ type: 1818
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 11776
+ num_resource: 25
+ type: 1819
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 12288
+ num_resource: 25
+ type: 1820
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 10
+ type: 1936
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1936
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1936
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 13
+ num_resource: 3
+ type: 1936
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 3
+ type: 1936
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 64
+ type: 1937
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 64
+ type: 1937
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 83
+ num_resource: 8
+ type: 1938
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 91
+ num_resource: 8
+ type: 1939
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 99
+ num_resource: 10
+ type: 1942
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 109
+ num_resource: 3
+ type: 1942
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 109
+ num_resource: 3
+ type: 1942
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 112
+ num_resource: 3
+ type: 1942
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 115
+ num_resource: 3
+ type: 1942
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 118
+ num_resource: 16
+ type: 1943
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 118
+ num_resource: 16
+ type: 1943
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 134
+ num_resource: 8
+ type: 1944
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 134
+ num_resource: 8
+ type: 1945
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 142
+ num_resource: 8
+ type: 1946
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 142
+ num_resource: 8
+ type: 1947
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 10
+ type: 1955
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1955
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1955
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 13
+ num_resource: 3
+ type: 1955
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 3
+ type: 1955
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 8
+ type: 1956
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 8
+ type: 1956
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 27
+ num_resource: 1
+ type: 1957
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 28
+ num_resource: 1
+ type: 1958
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 10
+ type: 1961
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1961
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1961
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 13
+ num_resource: 3
+ type: 1961
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 3
+ type: 1961
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 10
+ type: 1962
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1962
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1962
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 13
+ num_resource: 3
+ type: 1962
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 3
+ type: 1962
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 1
+ type: 1963
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 1
+ type: 1963
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 16
+ type: 1964
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 16
+ type: 1964
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 20
+ num_resource: 1
+ type: 1965
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 35
+ num_resource: 8
+ type: 1966
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 21
+ num_resource: 1
+ type: 1967
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 35
+ num_resource: 8
+ type: 1968
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 22
+ num_resource: 1
+ type: 1969
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 43
+ num_resource: 8
+ type: 1970
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 23
+ num_resource: 1
+ type: 1971
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 43
+ num_resource: 8
+ type: 1972
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 2112
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 2
+ num_resource: 2
+ type: 2122
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 8
+ num_resource: 12
+ type: 12750
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 20
+ num_resource: 20
+ type: 12750
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 8
+ type: 12751
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 12
+ type: 12769
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 12
+ num_resource: 20
+ type: 12769
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 8
+ type: 12770
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 8
+ type: 12810
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 22
+ num_resource: 18
+ type: 12810
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 1536
+ num_resource: 8
+ type: 12823
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 2048
+ num_resource: 8
+ type: 12824
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 2560
+ num_resource: 8
+ type: 12825
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 3072
+ num_resource: 32
+ type: 12826
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 3584
+ num_resource: 32
+ type: 12827
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 4096
+ num_resource: 32
+ type: 12828
+ host_id: 128
+ reserved: 0
diff --git a/board/ti/j784s4/evm.c b/board/ti/j784s4/evm.c
index aed0ea5..548dbd5 100644
--- a/board/ti/j784s4/evm.c
+++ b/board/ti/j784s4/evm.c
@@ -7,12 +7,46 @@
*
*/
+#include <efi_loader.h>
#include <init.h>
#include <spl.h>
#include "../common/fdt_ops.h"
DECLARE_GLOBAL_DATA_PTR;
+struct efi_fw_image fw_images[] = {
+ {
+ .image_type_id = AM69_SK_TIBOOT3_IMAGE_GUID,
+ .fw_name = u"AM69_SK_TIBOOT3",
+ .image_index = 1,
+ },
+ {
+ .image_type_id = AM69_SK_SPL_IMAGE_GUID,
+ .fw_name = u"AM69_SK_SPL",
+ .image_index = 2,
+ },
+ {
+ .image_type_id = AM69_SK_UBOOT_IMAGE_GUID,
+ .fw_name = u"AM69_SK_UBOOT",
+ .image_index = 3,
+ }
+};
+
+struct efi_capsule_update_info update_info = {
+ .dfu_string = "sf 0:0=tiboot3.bin raw 0 80000;"
+ "tispl.bin raw 80000 200000;u-boot.img raw 280000 400000",
+ .num_images = ARRAY_SIZE(fw_images),
+ .images = fw_images,
+};
+
+#if IS_ENABLED(CONFIG_SET_DFU_ALT_INFO)
+void set_dfu_alt_info(char *interface, char *devstr)
+{
+ if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT))
+ env_set("dfu_alt_info", update_info.dfu_string);
+}
+#endif
+
int board_init(void)
{
return 0;
diff --git a/board/ti/j784s4/j784s4.env b/board/ti/j784s4/j784s4.env
index 7e54ca0..f5b72c7 100644
--- a/board/ti/j784s4/j784s4.env
+++ b/board/ti/j784s4/j784s4.env
@@ -3,6 +3,10 @@
#include <env/ti/ufs.env>
#include <env/ti/k3_dfu.env>
+#if CONFIG_CMD_REMOTEPROC
+#include <env/ti/k3_rproc.env>
+#endif
+
name_kern=Image
console=ttyS2,115200n8
args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x02880000
@@ -15,3 +19,5 @@
bootpart=1:2
bootdir=/boot
rd_spec=-
+
+rproc_fw_binaries= 2 /lib/firmware/j784s4-main-r5f0_0-fw 3 /lib/firmware/j784s4-main-r5f0_1-fw 4 /lib/firmware/j784s4-main-r5f1_0-fw 5 /lib/firmware/j784s4-main-r5f1_1-fw 6 /lib/firmware/j784s4-main-r5f2_0-fw 7 /lib/firmware/j784s4-main-r5f2_1-fw 8 /lib/firmware/j784s4-c71_0-fw 9 /lib/firmware/j784s4-c71_1-fw 10 /lib/firmware/j784s4-c71_2-fw 11 /lib/firmware/j784s4-c71_3-fw
diff --git a/board/toradex/apalis-imx8/MAINTAINERS b/board/toradex/apalis-imx8/MAINTAINERS
index 198399c..761034a 100644
--- a/board/toradex/apalis-imx8/MAINTAINERS
+++ b/board/toradex/apalis-imx8/MAINTAINERS
@@ -1,5 +1,5 @@
Apalis iMX8
-M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+M: Francesco Dolcini <francesco.dolcini@toradex.com>
W: http://developer.toradex.com/software/linux/linux-software
S: Maintained
F: arch/arm/dts/fsl-imx8qm-apalis.dts
diff --git a/board/toradex/apalis-tk1/MAINTAINERS b/board/toradex/apalis-tk1/MAINTAINERS
index e2c6f63..393c8dc 100644
--- a/board/toradex/apalis-tk1/MAINTAINERS
+++ b/board/toradex/apalis-tk1/MAINTAINERS
@@ -1,5 +1,5 @@
Apalis TK1
-M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+M: Francesco Dolcini <francesco.dolcini@toradex.com>
S: Maintained
F: board/toradex/apalis-tk1/
F: board/toradex/common/
diff --git a/board/toradex/apalis_imx6/MAINTAINERS b/board/toradex/apalis_imx6/MAINTAINERS
index 0b2907b..d84527c 100644
--- a/board/toradex/apalis_imx6/MAINTAINERS
+++ b/board/toradex/apalis_imx6/MAINTAINERS
@@ -1,5 +1,5 @@
Apalis iMX6
-M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+M: Francesco Dolcini <francesco.dolcini@toradex.com>
W: http://developer.toradex.com/software/linux/linux-software
W: https://www.toradex.com/community
S: Maintained
diff --git a/board/toradex/apalis_t30/MAINTAINERS b/board/toradex/apalis_t30/MAINTAINERS
index 097db7d..368decf 100644
--- a/board/toradex/apalis_t30/MAINTAINERS
+++ b/board/toradex/apalis_t30/MAINTAINERS
@@ -1,5 +1,5 @@
Apalis T30
-M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+M: Francesco Dolcini <francesco.dolcini@toradex.com>
S: Maintained
F: board/toradex/apalis_t30/
F: board/toradex/common/
diff --git a/board/toradex/colibri-imx6ull/MAINTAINERS b/board/toradex/colibri-imx6ull/MAINTAINERS
index ee6fe6c..6c93e35 100644
--- a/board/toradex/colibri-imx6ull/MAINTAINERS
+++ b/board/toradex/colibri-imx6ull/MAINTAINERS
@@ -1,5 +1,5 @@
Colibri iMX6ULL
-M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+M: Francesco Dolcini <francesco.dolcini@toradex.com>
W: http://developer.toradex.com/software/linux/linux-software
W: https://www.toradex.com/community
S: Maintained
diff --git a/board/toradex/colibri-imx8x/MAINTAINERS b/board/toradex/colibri-imx8x/MAINTAINERS
index 8c9bf1f..938c2ca 100644
--- a/board/toradex/colibri-imx8x/MAINTAINERS
+++ b/board/toradex/colibri-imx8x/MAINTAINERS
@@ -1,5 +1,5 @@
Colibri iMX8X
-M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+M: Francesco Dolcini <francesco.dolcini@toradex.com>
W: http://developer.toradex.com/software/linux/linux-software
S: Maintained
F: arch/arm/dts/fsl-imx8x-colibri.dts
diff --git a/board/toradex/colibri_imx6/MAINTAINERS b/board/toradex/colibri_imx6/MAINTAINERS
index 25d3a06..c106750 100644
--- a/board/toradex/colibri_imx6/MAINTAINERS
+++ b/board/toradex/colibri_imx6/MAINTAINERS
@@ -1,5 +1,5 @@
Colibri iMX6
-M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+M: Francesco Dolcini <francesco.dolcini@toradex.com>
W: http://developer.toradex.com/software/linux/linux-software
W: https://www.toradex.com/community
S: Maintained
diff --git a/board/toradex/colibri_imx7/MAINTAINERS b/board/toradex/colibri_imx7/MAINTAINERS
index e4583d5..80770cc 100644
--- a/board/toradex/colibri_imx7/MAINTAINERS
+++ b/board/toradex/colibri_imx7/MAINTAINERS
@@ -1,5 +1,5 @@
Colibri iMX7
-M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+M: Francesco Dolcini <francesco.dolcini@toradex.com>
W: http://developer.toradex.com/software/linux/linux-software
W: https://www.toradex.com/community
S: Maintained
diff --git a/board/toradex/colibri_t20/MAINTAINERS b/board/toradex/colibri_t20/MAINTAINERS
index d0c5b11..5884243 100644
--- a/board/toradex/colibri_t20/MAINTAINERS
+++ b/board/toradex/colibri_t20/MAINTAINERS
@@ -1,5 +1,5 @@
COLIBRI_T20
-M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+M: Francesco Dolcini <francesco.dolcini@toradex.com>
S: Maintained
F: board/toradex/colibri_t20/
F: board/toradex/common/
diff --git a/board/toradex/colibri_t30/MAINTAINERS b/board/toradex/colibri_t30/MAINTAINERS
index 006a0e5..73859fd 100644
--- a/board/toradex/colibri_t30/MAINTAINERS
+++ b/board/toradex/colibri_t30/MAINTAINERS
@@ -1,5 +1,5 @@
Colibri T30
-M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+M: Francesco Dolcini <francesco.dolcini@toradex.com>
S: Maintained
F: board/toradex/colibri_t30/
F: board/toradex/common/
diff --git a/board/toradex/colibri_vf/MAINTAINERS b/board/toradex/colibri_vf/MAINTAINERS
index 2e1a74c..a41bd16 100644
--- a/board/toradex/colibri_vf/MAINTAINERS
+++ b/board/toradex/colibri_vf/MAINTAINERS
@@ -1,5 +1,5 @@
Colibri VFxx
-M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+M: Francesco Dolcini <francesco.dolcini@toradex.com>
W: http://developer.toradex.com/software/linux/linux-software
W: https://www.toradex.com/community
S: Maintained
diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c
index 2225cef..a6e3c6a 100644
--- a/board/toradex/common/tdx-cfg-block.c
+++ b/board/toradex/common/tdx-cfg-block.c
@@ -158,6 +158,9 @@
[85] = { "Apalis iMX6Q 2GB IT", TARGET_IS_ENABLED(APALIS_IMX6) },
[86] = { "Verdin iMX8M Mini DualLite 2GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) },
[87] = { "Verdin iMX8M Mini Quad 2GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) },
+ [88] = { "Aquila AM69 Octa 32GB WB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) },
+ [89] = { "Verdin iMX95 Hexa 16GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX95) },
+ [90] = { "Verdin iMX8M Mini Quad 4GB WB ET", TARGET_IS_ENABLED(VERDIN_IMX8MM) },
};
struct pid4list {
diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h
index 183ee0f..0d6dd1c 100644
--- a/board/toradex/common/tdx-cfg-block.h
+++ b/board/toradex/common/tdx-cfg-block.h
@@ -113,6 +113,9 @@
APALIS_IMX6Q_IT_NOWINCE, /* 85 */
VERDIN_IMX8MMDL_2G_IT,
VERDIN_IMX8MMQ_2G_IT_NO_CAN,
+ AQUILA_AM69O_32G_WIFI_BT_IT,
+ VERDIN_IMX95H_16G_WIFI_BT_IT,
+ VERDIN_IMX8MMQ_4G_WIFI_BT_ET, /* 90 */
};
enum {
diff --git a/board/toradex/verdin-am62/MAINTAINERS b/board/toradex/verdin-am62/MAINTAINERS
index 3e30d1d..3f69ea8 100644
--- a/board/toradex/verdin-am62/MAINTAINERS
+++ b/board/toradex/verdin-am62/MAINTAINERS
@@ -8,6 +8,6 @@
F: configs/verdin-am62_r5_defconfig
F: doc/board/toradex/verdin-am62.rst
F: include/configs/verdin-am62.h
-M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+M: Francesco Dolcini <francesco.dolcini@toradex.com>
S: Maintained
W: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am-62
diff --git a/board/toradex/verdin-imx8mm/MAINTAINERS b/board/toradex/verdin-imx8mm/MAINTAINERS
index d567f0e..0d58a73 100644
--- a/board/toradex/verdin-imx8mm/MAINTAINERS
+++ b/board/toradex/verdin-imx8mm/MAINTAINERS
@@ -1,5 +1,5 @@
Verdin iMX8M Mini
-M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+M: Francesco Dolcini <francesco.dolcini@toradex.com>
W: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-mini
S: Maintained
F: arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi
diff --git a/board/toradex/verdin-imx8mm/lpddr4_timing.c b/board/toradex/verdin-imx8mm/lpddr4_timing.c
index 4dfec67..eece226 100644
--- a/board/toradex/verdin-imx8mm/lpddr4_timing.c
+++ b/board/toradex/verdin-imx8mm/lpddr4_timing.c
@@ -18,7 +18,7 @@
{0x3d400000, 0xa1080020},
{0x3d400020, 0x202},
{0x3d400024, 0x3a980},
- {0x3d400064, 0x2d00d2},
+ {0x3d400064, 0x2d011d},
{0x3d4000d0, 0xc00305ba},
{0x3d4000d4, 0x940000},
{0x3d4000dc, 0xd4002d},
@@ -34,7 +34,7 @@
{0x3d40011c, 0x402},
{0x3d400130, 0x20600},
{0x3d400134, 0xc100002},
- {0x3d400138, 0xd8},
+ {0x3d400138, 0x123},
{0x3d400144, 0x96004b},
{0x3d400180, 0x2ee0017},
{0x3d400184, 0x2605b8e},
@@ -56,7 +56,7 @@
{0x3d400204, 0x80808},
{0x3d400214, 0x7070707},
{0x3d400218, 0x7070707},
- {0x3d40021c, 0xf0f},
+ {0x3d40021c, 0xf07},
{0x3d400250, 0x29001701},
{0x3d400254, 0x2c},
{0x3d40025c, 0x4000030},
@@ -71,7 +71,7 @@
{0x3d402020, 0x0},
{0x3d402024, 0x7d00},
{0x3d402050, 0x20d040},
- {0x3d402064, 0x6001c},
+ {0x3d402064, 0x60026},
{0x3d4020dc, 0x840000},
{0x3d4020e0, 0x310000},
{0x3d4020e8, 0x66004d},
@@ -86,7 +86,7 @@
{0x3d40211c, 0x302},
{0x3d402130, 0x20300},
{0x3d402134, 0xa100002},
- {0x3d402138, 0x1d},
+ {0x3d402138, 0x27},
{0x3d402144, 0x14000a},
{0x3d402180, 0x640004},
{0x3d402190, 0x3818200},
@@ -96,7 +96,7 @@
{0x3d403020, 0x0},
{0x3d403024, 0x1f40},
{0x3d403050, 0x20d040},
- {0x3d403064, 0x30007},
+ {0x3d403064, 0x3000A},
{0x3d4030dc, 0x840000},
{0x3d4030e0, 0x310000},
{0x3d4030e8, 0x66004d},
@@ -111,7 +111,7 @@
{0x3d40311c, 0x302},
{0x3d403130, 0x20300},
{0x3d403134, 0xa100002},
- {0x3d403138, 0x8},
+ {0x3d403138, 0xA},
{0x3d403144, 0x50003},
{0x3d403180, 0x190004},
{0x3d403190, 0x3818200},
diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c
index 020ee67..9359e0a 100644
--- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c
+++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c
@@ -84,7 +84,8 @@
*/
is_wifi = (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT) ||
(tdx_hw_tag.prodid == VERDIN_IMX8MMDL_WIFI_BT_IT) ||
- (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT_NO_CAN);
+ (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT_NO_CAN) ||
+ (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_4G_WIFI_BT_ET);
}
switch (get_pcb_revision()) {
@@ -117,7 +118,7 @@
if (!size)
return -EINVAL;
- *size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+ *size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE);
return 0;
}
@@ -125,6 +126,35 @@
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
{
+ const char *canoscpath = "/oscillator";
+ int freq = 40000000; /* 40 MHz is used on most variants */
+ int canoscoff, ret;
+
+ canoscoff = fdt_path_offset(blob, canoscpath);
+ if (canoscoff < 0) /* No CAN oscillator found. */
+ goto exit;
+
+ /*
+ * The following "prodid" (PID4 in Toradex naming) use
+ * a 20MHz CAN oscillator:
+ * - 0055, V1.1A, V1.1B, V1.1C and V1.1D
+ * - 0059, V1.1A and V1.1B
+ */
+ if ((tdx_hw_tag.ver_major == 1 && tdx_hw_tag.ver_minor == 1) &&
+ ((tdx_hw_tag.prodid == VERDIN_IMX8MMQ_IT &&
+ tdx_hw_tag.ver_assembly <= 1) || /* 0059 rev. A or B */
+ (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT &&
+ tdx_hw_tag.ver_assembly <= 3))) { /* 0055 rev. A/B/C/D */
+ freq = 20000000;
+ }
+
+ ret = fdt_setprop_u32(blob, canoscoff, "clock-frequency", freq);
+ if (ret < 0) {
+ printf("Failed to set CAN oscillator clock-frequency, ret=%d\n",
+ ret);
+ }
+
+exit:
return ft_common_board_setup(blob, bd);
}
#endif
diff --git a/board/toradex/verdin-imx8mp/MAINTAINERS b/board/toradex/verdin-imx8mp/MAINTAINERS
index 9fe76d8..a683448 100644
--- a/board/toradex/verdin-imx8mp/MAINTAINERS
+++ b/board/toradex/verdin-imx8mp/MAINTAINERS
@@ -5,6 +5,6 @@
F: configs/verdin-imx8mp_defconfig
F: doc/board/toradex/verdin-imx8mp.rst
F: include/configs/verdin-imx8mp.h
-M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+M: Francesco Dolcini <francesco.dolcini@toradex.com>
S: Maintained
W: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-plus
diff --git a/board/wexler/qc750/Kconfig b/board/wexler/qc750/Kconfig
new file mode 100644
index 0000000..45a1e5e
--- /dev/null
+++ b/board/wexler/qc750/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_QC750
+
+config SYS_BOARD
+ default "qc750"
+
+config SYS_VENDOR
+ default "wexler"
+
+config SYS_CONFIG_NAME
+ default "qc750"
+
+endif
diff --git a/board/wexler/qc750/MAINTAINERS b/board/wexler/qc750/MAINTAINERS
new file mode 100644
index 0000000..017f6f2
--- /dev/null
+++ b/board/wexler/qc750/MAINTAINERS
@@ -0,0 +1,7 @@
+QC750 BOARD
+M: Svyatoslav Ryhel <clamor95@gmail.com>
+S: Maintained
+F: board/wexler/qc750/
+F: configs/qc750_defconfig
+F: doc/board/wexler/qc750.rst
+F: include/configs/qc750.h
diff --git a/board/wexler/qc750/Makefile b/board/wexler/qc750/Makefile
new file mode 100644
index 0000000..4daefc4
--- /dev/null
+++ b/board/wexler/qc750/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2010-2012
+# NVIDIA Corporation <www.nvidia.com>
+#
+# (C) Copyright 2023
+# Svyatoslav Ryhel <clamor95@gmail.com>
+
+obj-$(CONFIG_SPL_BUILD) += qc750-spl.o
+
+obj-y += qc750.o
diff --git a/board/wexler/qc750/qc750-spl.c b/board/wexler/qc750/qc750-spl.c
new file mode 100644
index 0000000..707be77
--- /dev/null
+++ b/board/wexler/qc750/qc750-spl.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * T30 QC750 SPL stage configuration
+ *
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * (C) Copyright 2023
+ * Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include <linux/delay.h>
+
+#define MAX77663_I2C_ADDR (0x3c << 1)
+
+#define MAX77663_REG_SD0 0x16
+#define MAX77663_REG_SD0_DATA (0x2100 | MAX77663_REG_SD0)
+#define MAX77663_REG_SD1 0x17
+#define MAX77663_REG_SD1_DATA (0x3000 | MAX77663_REG_SD1)
+#define MAX77663_REG_LDO4 0x2b
+#define MAX77663_REG_LDO4_DATA (0xE000 | MAX77663_REG_LDO4)
+
+#define MAX77663_REG_GPIO4 0x3a
+#define MAX77663_REG_GPIO4_DATA (0x0100 | MAX77663_REG_GPIO4)
+
+void pmic_enable_cpu_vdd(void)
+{
+ /* Set VDD_CORE to 1.200V. */
+ tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_SD1_DATA);
+
+ udelay(1000);
+
+ /* Bring up VDD_CPU to 1.0125V. */
+ tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_SD0_DATA);
+ udelay(1000);
+
+ /* Bring up VDD_RTC to 1.200V. */
+ tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_LDO4_DATA);
+ udelay(10 * 1000);
+
+ /* Set 32k-out gpio state */
+ tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_GPIO4_DATA);
+}
diff --git a/board/wexler/qc750/qc750.c b/board/wexler/qc750/qc750.c
new file mode 100644
index 0000000..5234211
--- /dev/null
+++ b/board/wexler/qc750/qc750.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * (C) Copyright 2023
+ * Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <fdt_support.h>
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ /* Remove TrustZone nodes */
+ fdt_del_node_and_alias(blob, "/firmware");
+ fdt_del_node_and_alias(blob, "/reserved-memory/trustzone@bfe00000");
+
+ return 0;
+}
+#endif
diff --git a/board/xilinx/Kconfig b/board/xilinx/Kconfig
index 5c4ad8f..c7df4ab 100644
--- a/board/xilinx/Kconfig
+++ b/board/xilinx/Kconfig
@@ -42,7 +42,7 @@
config XILINX_OF_BOARD_DTB_ADDR
hex "Default DTB pickup address"
- default 0x1000 if ARCH_VERSAL || ARCH_VERSAL_NET
+ default 0x1000 if ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2
default 0x8000 if MICROBLAZE
default 0x100000 if ARCH_ZYNQ || ARCH_ZYNQMP
default 0x23000000 if TARGET_XILINX_MBV
@@ -52,10 +52,10 @@
config BOOT_SCRIPT_OFFSET
hex "Boot script offset"
- depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || MICROBLAZE || TARGET_XILINX_MBV
+ depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2 || MICROBLAZE || TARGET_XILINX_MBV
default 0xFC0000 if ARCH_ZYNQ || MICROBLAZE
default 0x3E80000 if ARCH_ZYNQMP
- default 0x7F80000 if ARCH_VERSAL || ARCH_VERSAL_NET
+ default 0x7F80000 if ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2
default 0 if TARGET_XILINX_MBV
help
Specifies distro boot script offset in NAND/QSPI/NOR flash.
diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
index 30a8137..0b43407 100644
--- a/board/xilinx/common/board.c
+++ b/board/xilinx/common/board.c
@@ -701,11 +701,6 @@
#define MAX_RAND_SIZE 8
int ft_board_setup(void *blob, struct bd_info *bd)
{
- size_t n = MAX_RAND_SIZE;
- struct udevice *dev;
- u8 buf[MAX_RAND_SIZE];
- int nodeoffset, ret;
-
static const struct node_info nodes[] = {
{ "arm,pl353-nand-r2p1", MTD_DEV_TYPE_NAND, },
};
@@ -713,41 +708,6 @@
if (IS_ENABLED(CONFIG_FDT_FIXUP_PARTITIONS) && IS_ENABLED(CONFIG_NAND_ZYNQ))
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
- if (uclass_get_device(UCLASS_RNG, 0, &dev) || !dev) {
- debug("No RNG device\n");
- return 0;
- }
-
- if (dm_rng_read(dev, buf, n)) {
- debug("Reading RNG failed\n");
- return 0;
- }
-
- if (!blob) {
- debug("No FDT memory address configured. Please configure\n"
- "the FDT address via \"fdt addr <address>\" command.\n"
- "Aborting!\n");
- return 0;
- }
-
- ret = fdt_check_header(blob);
- if (ret < 0) {
- debug("fdt_chosen: %s\n", fdt_strerror(ret));
- return ret;
- }
-
- nodeoffset = fdt_find_or_add_subnode(blob, 0, "chosen");
- if (nodeoffset < 0) {
- debug("Reading chosen node failed\n");
- return nodeoffset;
- }
-
- ret = fdt_setprop(blob, nodeoffset, "kaslr-seed", buf, sizeof(buf));
- if (ret < 0) {
- debug("Unable to set kaslr-seed on chosen node: %s\n", fdt_strerror(ret));
- return ret;
- }
-
return 0;
}
#endif
diff --git a/board/xilinx/versal-net/cmds.c b/board/xilinx/versal-net/cmds.c
index 4d52084..e8b669f 100644
--- a/board/xilinx/versal-net/cmds.c
+++ b/board/xilinx/versal-net/cmds.c
@@ -71,10 +71,9 @@
return cmd_process_error(cmdtp, ret);
}
-static char versalnet_help_text[] =
+U_BOOT_LONGHELP(versalnet,
"loadpdi addr len - Load pdi image\n"
- "load pdi image at ddr address 'addr' with pdi image size 'len'\n"
-;
+ "load pdi image at ddr address 'addr' with pdi image size 'len'\n");
U_BOOT_CMD_WITH_SUBCMDS(versalnet, "Versal NET sub-system", versalnet_help_text,
U_BOOT_SUBCMD_MKENT(loadpdi, 3, 1,
diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c
index 77ba783..3947467 100644
--- a/board/xilinx/versal/board.c
+++ b/board/xilinx/versal/board.c
@@ -150,14 +150,29 @@
break;
case QSPI_MODE_24BIT:
puts("QSPI_MODE_24\n");
+ if (uclass_get_device_by_name(UCLASS_SPI,
+ "spi@f1030000", &dev)) {
+ debug("QSPI driver for QSPI device is not present\n");
+ break;
+ }
mode = "xspi0";
break;
case QSPI_MODE_32BIT:
puts("QSPI_MODE_32\n");
+ if (uclass_get_device_by_name(UCLASS_SPI,
+ "spi@f1030000", &dev)) {
+ debug("QSPI driver for QSPI device is not present\n");
+ break;
+ }
mode = "xspi0";
break;
case OSPI_MODE:
puts("OSPI_MODE\n");
+ if (uclass_get_device_by_name(UCLASS_SPI,
+ "spi@f1010000", &dev)) {
+ debug("OSPI driver for OSPI device is not present\n");
+ break;
+ }
mode = "xspi0";
break;
case EMMC_MODE:
diff --git a/board/xilinx/zynqmp/Kconfig b/board/xilinx/zynqmp/Kconfig
deleted file mode 100644
index ffa2f02..0000000
--- a/board/xilinx/zynqmp/Kconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-# Copyright (c) 2018, Xilinx, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0
-
-if ARCH_ZYNQMP
-
-config CMD_ZYNQMP
- bool "Enable ZynqMP specific commands"
- depends on ZYNQMP_FIRMWARE
- default y
- help
- Enable ZynqMP specific commands like "zynqmp secure"
- which is used for zynqmp secure image verification.
- The secure image is a xilinx specific BOOT.BIN with
- either authentication or encryption or both encryption
- and authentication feature enabled while generating
- BOOT.BIN using Xilinx bootgen tool.
-
-endif
diff --git a/board/xilinx/zynqmp/Makefile b/board/xilinx/zynqmp/Makefile
index 204e4fa..9ab50ec 100644
--- a/board/xilinx/zynqmp/Makefile
+++ b/board/xilinx/zynqmp/Makefile
@@ -40,10 +40,6 @@
endif
endif
-ifndef CONFIG_SPL_BUILD
-obj-$(CONFIG_CMD_ZYNQMP) += cmds.o
-endif
-
# Suppress "warning: function declaration isn't a prototype"
CFLAGS_REMOVE_psu_init_gpl.o := -Wstrict-prototypes
diff --git a/board/xilinx/zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c
index 166e614..274203f 100644
--- a/board/xilinx/zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c
@@ -528,8 +528,8 @@
psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U);
psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U);
psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
- psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
- psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180130, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180134, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x50000000U);
psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02020U);
psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
@@ -569,21 +569,16 @@
psu_mask_write(0xFD1A0100, 0x0001807CU, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
- psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0230, 0x00000002U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
- psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U);
- psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U);
- psu_mask_write(0xFF180320, 0x33840000U, 0x02840000U);
- psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
- psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
- psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000080U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00000400U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00000010U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
- psu_mask_write(0xFF5E0238, 0x00000004U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
@@ -591,13 +586,15 @@
psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U);
psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
- psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+ psu_mask_write(0xFF0A0284, 0x03FFFFFFU, 0x01000000U);
+ psu_mask_write(0xFF0A0288, 0x03FFFFFFU, 0x01000000U);
+ psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x02FF0100U);
mask_delay(1);
- psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U);
+ psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x02FF0000U);
mask_delay(5);
- psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+ psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x02FF0100U);
return 1;
}
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index c4050af..b4c15b0 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -285,6 +285,18 @@
#if !CONFIG_IS_ENABLED(SYSRESET)
void reset_cpu(void)
{
+ if (!IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE)) {
+ log_warning("reset failed: ZYNQMP_FIRMWARE disabled");
+ return;
+ }
+
+ /* In case of !CONFIG_ZYNQMP_FIRMWARE the call to 'xilinx_pm_request()'
+ * will be removed by the compiler due to the early return.
+ * If CONFIG_ZYNQMP_FIRMWARE is defined in SPL 'xilinx_pm_request()'
+ * will send command over IPI and requires pmufw to be present.
+ */
+ xilinx_pm_request(PM_RESET_ASSERT, ZYNQMP_PM_RESET_SOFT,
+ PM_RESET_ACTION_ASSERT, 0, 0, NULL);
}
#endif
@@ -519,6 +531,10 @@
usb_ether_init();
#endif
+ multiboot = multi_boot();
+ if (multiboot >= 0)
+ env_set_hex("multiboot", multiboot);
+
if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
debug("Saved variables - Skipping\n");
return 0;
@@ -531,10 +547,6 @@
if (ret)
return ret;
- multiboot = multi_boot();
- if (multiboot >= 0)
- env_set_hex("multiboot", multiboot);
-
if (IS_ENABLED(CONFIG_DISTRO_DEFAULTS)) {
ret = boot_targets_setup();
if (ret)
diff --git a/board/xilinx/zynqmp/zynqmp_kria.env b/board/xilinx/zynqmp/zynqmp_kria.env
index 846eceb..69e333c 100644
--- a/board/xilinx/zynqmp/zynqmp_kria.env
+++ b/board/xilinx/zynqmp/zynqmp_kria.env
@@ -65,6 +65,7 @@
tpm_setup=tpm autostart;
board_setup=\
+zynqmp mmio_write 0xFFCA0010 0xfff 0; \
if test ${card1_name} = SCK-KV-G; then run kv260_setup; fi;\
if test ${card1_name} = SCK-KR-G; then run kr260_setup; fi;\
if test ${card1_name} = SCK-KD-G; then run kd240_setup; fi;\
diff --git a/boot/Kconfig b/boot/Kconfig
index 8099af4..95300b0 100644
--- a/boot/Kconfig
+++ b/boot/Kconfig
@@ -85,7 +85,7 @@
using a hash signed and verified using RSA. If
CONFIG_SHA_PROG_HW_ACCEL is defined, i.e support for progressive
hashing is available using hardware, then the RSA library will use
- it. See doc/uImage.FIT/signature.txt for more details.
+ it. See doc/usage/fit/signature.rst for more details.
WARNING: When relying on signed FIT images with a required signature
check the legacy image format is disabled by default, so that
@@ -150,10 +150,10 @@
processed before being added to the FIT image).
config FIT_PRINT
- bool "Support FIT printing"
- default y
- help
- Support printing the content of the fitImage in a verbose manner.
+ bool "Support FIT printing"
+ default y
+ help
+ Support printing the content of the fitImage in a verbose manner.
config SPL_FIT
bool "Support Flattened Image Tree within SPL"
@@ -223,8 +223,8 @@
1. "loadables" images, other than FDTs, which do not have a "load"
property will not be loaded. This limitation also applies to FPGA
images with the correct "compatible" string.
- 2. For FPGA images, the supported "compatible" list is in the
- doc/uImage.FIT/source_file_format.txt.
+ 2. For FPGA images, the supported "compatible" list may be found in
+ https://fitspec.osfw.foundation/.
3. FDTs are only loaded for images with an "os" property of "u-boot".
"linux" images are also supported with Falcon boot mode.
@@ -423,7 +423,7 @@
depends on SPL && SPL_DM && SPL_OF_CONTROL && SPL_BLK
default y if VPL
help
- This enables standard boot in SPL. This is neeeded so that VBE
+ This enables standard boot in SPL. This is needed so that VBE
(Verified Boot for Embedded) can be used, since it depends on standard
boot. It is enabled by default since the main purpose of VPL is to
handle the firmware part of VBE.
@@ -433,7 +433,7 @@
depends on VPL && VPL_DM && VPL_OF_CONTROL && VPL_BLK
default y
help
- This enables standard boot in SPL. This is neeeded so that VBE
+ This enables standard boot in SPL. This is needed so that VBE
(Verified Boot for Embedded) can be used, since it depends on standard
boot. It is enabled by default since the main purpose of VPL is to
handle the firmware part of VBE.
@@ -449,7 +449,7 @@
- bootdev, bootmeth commands
- extra features in the bootflow command
- support for selecting the ordering of bootmeths ("bootmeth order")
- - support for selecting the ordering of bootdevs using the devicetree
+ - support for selecting the ordering of bootdevs using the Device Tree
as well as the "boot_targets" environment variable
config BOOTSTD_DEFAULTS
@@ -481,7 +481,7 @@
default y
help
Enable this to provide a board_run_command() function which can boot
- a systen without using commands. If the boot fails, then U-Boot will
+ a system without using commands. If the boot fails, then U-Boot will
panic.
Note: This currently has many limitations and is not a useful booting
@@ -517,7 +517,7 @@
bootdevs look for a 'extlinux/extlinux.conf' on each filesystem
they scan.
- The specification for this filed is here:
+ The specification for this file is here:
https://uapi-group.org/specifications/specs/boot_loader_specification/
@@ -576,7 +576,7 @@
select EVENT
help
Enables support for VBE boot. This is a standard boot method which
- supports selection of various firmware components, seleciton of an OS to
+ supports selection of various firmware components, selection of an OS to
boot as well as updating these using fwupd.
config BOOTMETH_DISTRO
@@ -593,7 +593,7 @@
default y if VPL
help
Enables support for VBE boot. This is a standard boot method which
- supports selection of various firmware components, seleciton of an OS to
+ supports selection of various firmware components, selection of an OS to
boot as well as updating these using fwupd.
config VPL_BOOTMETH_VBE
@@ -603,7 +603,7 @@
default y
help
Enables support for VBE boot. This is a standard boot method which
- supports selection of various firmware components, seleciton of an OS to
+ supports selection of various firmware components, selection of an OS to
boot as well as updating these using fwupd.
if BOOTMETH_VBE
@@ -734,6 +734,10 @@
config MEASURED_BOOT
bool "Measure boot images and configuration when booting without EFI"
depends on HASH && TPM_V2
+ select SHA1
+ select SHA256
+ select SHA384
+ select SHA512
help
This option enables measurement of the boot process when booting
without UEFI . Measurement involves creating cryptographic hashes
@@ -748,7 +752,7 @@
bool "Measure the devicetree image"
default y if MEASURED_BOOT
help
- On some platforms, the devicetree is not static as it may contain
+ On some platforms, the Device Tree is not static as it may contain
random MAC addresses or other such data that changes each boot.
Therefore, it should not be measured into the TPM. In that case,
disable the measurement here.
@@ -1303,7 +1307,7 @@
Note that this define is used as the (only) argument to a
printf() call, so it may contain '%' format specifications,
- provided that it also includes, sepearated by commas exactly
+ provided that it also includes, separated by commas exactly
like in a printf statement, the required arguments. It is
the responsibility of the user to select only such arguments
that are valid in the given context.
@@ -1402,7 +1406,7 @@
help
This option adds the feature to only stop the autobooting,
and therefore boot into the U-Boot prompt, when the input
- string / password matches a values that is encypted via
+ string / password matches a values that is encrypted via
a SHA256 hash and saved in the environment variable
"bootstopkeysha256". If the value in that variable
includes a ":", the portion prior to the ":" will be treated
diff --git a/boot/bootflow_menu.c b/boot/bootflow_menu.c
index 143ef84..9d0dc35 100644
--- a/boot/bootflow_menu.c
+++ b/boot/bootflow_menu.c
@@ -9,6 +9,7 @@
#define LOG_CATEGORY UCLASS_BOOTSTD
#include <bootflow.h>
+#include <bootmeth.h>
#include <bootstd.h>
#include <cli.h>
#include <dm.h>
@@ -76,6 +77,7 @@
last_bootdev = NULL;
for (ret = bootflow_first_glob(&bflow), i = 0; !ret && i < 36;
ret = bootflow_next_glob(&bflow), i++) {
+ struct bootmeth_uc_plat *ucp;
char str[2], *label, *key;
uint preview_id;
bool add_gap;
@@ -83,6 +85,11 @@
if (bflow->state != BOOTFLOWST_READY)
continue;
+ /* No media to show for BOOTMETHF_GLOBAL bootmeths */
+ ucp = dev_get_uclass_plat(bflow->method);
+ if (ucp->flags & BOOTMETHF_GLOBAL)
+ continue;
+
*str = i < 10 ? '0' + i : 'A' + i - 10;
str[1] = '\0';
key = strdup(str);
diff --git a/boot/bootm.c b/boot/bootm.c
index 6fa8eda..376d63a 100644
--- a/boot/bootm.c
+++ b/boot/bootm.c
@@ -24,6 +24,7 @@
#include <asm/io.h>
#include <linux/sizes.h>
#include <tpm-v2.h>
+#include <tpm_tcg2.h>
#if defined(CONFIG_CMD_USB)
#include <usb.h>
#endif
@@ -963,7 +964,7 @@
goto unmap_initrd;
if (IS_ENABLED(CONFIG_MEASURE_DEVICETREE)) {
- ret = tcg2_measure_data(dev, &elog, 0, images->ft_len,
+ ret = tcg2_measure_data(dev, &elog, 1, images->ft_len,
(u8 *)images->ft_addr,
EV_TABLE_OF_DEVICES,
strlen("dts") + 1,
diff --git a/boot/bootm_os.c b/boot/bootm_os.c
index 15297dd..6a66217 100644
--- a/boot/bootm_os.c
+++ b/boot/bootm_os.c
@@ -8,6 +8,7 @@
#include <bootstage.h>
#include <cpu_func.h>
#include <efi_loader.h>
+#include <elf.h>
#include <env.h>
#include <fdt_support.h>
#include <image.h>
@@ -394,6 +395,20 @@
}
#endif
+#if defined(CONFIG_BOOTM_ELF)
+static int do_bootm_elf(int flag, struct bootm_info *bmi)
+{
+ Bootelf_flags flags = { .autostart = 1 };
+
+ if (flag != BOOTM_STATE_OS_GO)
+ return 0;
+
+ bootelf(bmi->images->ep, flags, 0, NULL);
+
+ return 1;
+}
+#endif
+
#ifdef CONFIG_INTEGRITY
static int do_bootm_integrity(int flag, struct bootm_info *bmi)
{
@@ -535,6 +550,9 @@
#ifdef CONFIG_BOOTM_EFI
[IH_OS_EFI] = do_bootm_efi,
#endif
+#if defined(CONFIG_BOOTM_ELF)
+ [IH_OS_ELF] = do_bootm_elf,
+#endif
};
/* Allow for arch specific config before we boot */
diff --git a/boot/bootmeth_cros.c b/boot/bootmeth_cros.c
index 645b8be..1d5fd8b 100644
--- a/boot/bootmeth_cros.c
+++ b/boot/bootmeth_cros.c
@@ -147,7 +147,7 @@
{
struct blk_desc *desc = dev_get_uclass_plat(blk);
struct vb2_keyblock *hdr;
- struct uuid type;
+ efi_guid_t type;
ulong num_blks;
int ret;
@@ -160,7 +160,7 @@
/* Check for kernel partition type */
log_debug("part %x: type=%s\n", partnum, info->type_guid);
- if (uuid_str_to_bin(info->type_guid, (u8 *)&type, UUID_STR_FORMAT_GUID))
+ if (uuid_str_to_bin(info->type_guid, type.b, UUID_STR_FORMAT_GUID))
return log_msg_ret("typ", -EINVAL);
if (memcmp(&cros_kern_type, &type, sizeof(type)))
diff --git a/boot/bootmeth_efi.c b/boot/bootmeth_efi.c
index c7035c0..5a4c125 100644
--- a/boot/bootmeth_efi.c
+++ b/boot/bootmeth_efi.c
@@ -143,62 +143,6 @@
return 0;
}
-/**
- * distro_efi_get_fdt_name() - Get the filename for reading the .dtb file
- *
- * @fname: Place to put filename
- * @size: Max size of filename
- * @seq: Sequence number, to cycle through options (0=first)
- * Returns: 0 on success, -ENOENT if the "fdtfile" env var does not exist,
- * -EINVAL if there are no more options, -EALREADY if the control FDT should be
- * used
- */
-static int distro_efi_get_fdt_name(char *fname, int size, int seq)
-{
- const char *fdt_fname;
- const char *prefix;
-
- /* select the prefix */
- switch (seq) {
- case 0:
- /* this is the default */
- prefix = "/dtb";
- break;
- case 1:
- prefix = "";
- break;
- case 2:
- prefix = "/dtb/current";
- break;
- default:
- return log_msg_ret("pref", -EINVAL);
- }
-
- fdt_fname = env_get("fdtfile");
- if (fdt_fname) {
- snprintf(fname, size, "%s/%s", prefix, fdt_fname);
- log_debug("Using device tree: %s\n", fname);
- } else if (IS_ENABLED(CONFIG_OF_HAS_PRIOR_STAGE)) {
- strcpy(fname, "<prior>");
- return log_msg_ret("pref", -EALREADY);
- /* Use this fallback only for 32-bit ARM */
- } else if (IS_ENABLED(CONFIG_ARM) && !IS_ENABLED(CONFIG_ARM64)) {
- const char *soc = env_get("soc");
- const char *board = env_get("board");
- const char *boardver = env_get("boardver");
-
- /* cf the code in label_boot() which seems very complex */
- snprintf(fname, size, "%s/%s%s%s%s.dtb", prefix,
- soc ? soc : "", soc ? "-" : "", board ? board : "",
- boardver ? boardver : "");
- log_debug("Using default device tree: %s\n", fname);
- } else {
- return log_msg_ret("env", -ENOENT);
- }
-
- return 0;
-}
-
/*
* distro_efi_try_bootflow_files() - Check that files are present
*
@@ -240,7 +184,7 @@
ret = -ENOENT;
*fname = '\0';
for (seq = 0; ret == -ENOENT; seq++) {
- ret = distro_efi_get_fdt_name(fname, sizeof(fname), seq);
+ ret = efi_get_distro_fdt_name(fname, sizeof(fname), seq);
if (ret == -EALREADY)
bflow->flags = BOOTFLOWF_USE_PRIOR_FDT;
if (!ret) {
@@ -339,7 +283,7 @@
sprintf(file_addr, "%lx", fdt_addr);
/* We only allow the first prefix with PXE */
- ret = distro_efi_get_fdt_name(fname, sizeof(fname), 0);
+ ret = efi_get_distro_fdt_name(fname, sizeof(fname), 0);
if (ret)
return log_msg_ret("nam", ret);
diff --git a/boot/fdt_support.c b/boot/fdt_support.c
index 874ca4d..2392027 100644
--- a/boot/fdt_support.c
+++ b/boot/fdt_support.c
@@ -6,12 +6,15 @@
* Copyright 2010-2011 Freescale Semiconductor, Inc.
*/
+#include <dm.h>
#include <abuf.h>
#include <env.h>
#include <log.h>
#include <mapmem.h>
#include <net.h>
+#include <rng.h>
#include <stdio_dev.h>
+#include <dm/device_compat.h>
#include <dm/ofnode.h>
#include <linux/ctype.h>
#include <linux/types.h>
@@ -273,6 +276,47 @@
return 0;
}
+int fdt_kaslrseed(void *fdt, bool overwrite)
+{
+ int len, err, nodeoffset;
+ struct udevice *dev;
+ const u64 *orig;
+ u64 data = 0;
+
+ err = fdt_check_header(fdt);
+ if (err < 0)
+ return err;
+
+ /* find or create "/chosen" node. */
+ nodeoffset = fdt_find_or_add_subnode(fdt, 0, "chosen");
+ if (nodeoffset < 0)
+ return nodeoffset;
+
+ /* return without error if we are not overwriting and existing non-zero node */
+ orig = fdt_getprop(fdt, nodeoffset, "kaslr-seed", &len);
+ if (orig && len == sizeof(*orig))
+ data = fdt64_to_cpu(*orig);
+ if (data && !overwrite) {
+ debug("not overwriting existing kaslr-seed\n");
+ return 0;
+ }
+ err = uclass_get_device(UCLASS_RNG, 0, &dev);
+ if (err) {
+ printf("No RNG device\n");
+ return err;
+ }
+ err = dm_rng_read(dev, &data, sizeof(data));
+ if (err) {
+ dev_err(dev, "dm_rng_read failed: %d\n", err);
+ return err;
+ }
+ err = fdt_setprop(fdt, nodeoffset, "kaslr-seed", &data, sizeof(data));
+ if (err < 0)
+ printf("WARNING: could not set kaslr-seed %s.\n", fdt_strerror(err));
+
+ return err;
+}
+
/**
* board_fdt_chosen_bootargs - boards may override this function to use
* alternative kernel command line arguments
@@ -300,6 +344,15 @@
if (nodeoffset < 0)
return nodeoffset;
+ /* if DM_RNG enabled automatically inject kaslr-seed node unless:
+ * CONFIG_MEASURED_BOOT enabled: as dt modifications break measured boot
+ * CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT enabled: as that implementation does not use dm yet
+ */
+ if (IS_ENABLED(CONFIG_DM_RNG) &&
+ !IS_ENABLED(CONFIG_MEASURED_BOOT) &&
+ !IS_ENABLED(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT))
+ fdt_kaslrseed(fdt, false);
+
if (IS_ENABLED(CONFIG_BOARD_RNG_SEED) && !board_rng_seed(&buf)) {
err = fdt_setprop(fdt, nodeoffset, "rng-seed",
abuf_data(&buf), abuf_size(&buf));
diff --git a/boot/image-android.c b/boot/image-android.c
index ddd8ffd..ee62697 100644
--- a/boot/image-android.c
+++ b/boot/image-android.c
@@ -63,7 +63,6 @@
data->kcmdline = hdr->cmdline;
data->header_version = hdr->header_version;
- data->ramdisk_ptr = env_get_ulong("ramdisk_addr_r", 16, 0);
/*
* The header takes a full page, the remaining components are aligned
@@ -74,6 +73,7 @@
data->kernel_ptr = end;
data->kernel_size = hdr->kernel_size;
end += ALIGN(hdr->kernel_size, ANDR_GKI_PAGE_SIZE);
+ data->ramdisk_ptr = end;
data->ramdisk_size = hdr->ramdisk_size;
data->boot_ramdisk_size = hdr->ramdisk_size;
end += ALIGN(hdr->ramdisk_size, ANDR_GKI_PAGE_SIZE);
@@ -393,25 +393,24 @@
return -1;
}
if (img_data.header_version > 2) {
- ramdisk_ptr = img_data.ramdisk_ptr;
+ ramdisk_ptr = img_data.ramdisk_addr;
memcpy((void *)(ramdisk_ptr), (void *)img_data.vendor_ramdisk_ptr,
img_data.vendor_ramdisk_size);
- memcpy((void *)(ramdisk_ptr + img_data.vendor_ramdisk_size),
- (void *)img_data.ramdisk_ptr,
+ ramdisk_ptr += img_data.vendor_ramdisk_size;
+ memcpy((void *)(ramdisk_ptr), (void *)img_data.ramdisk_ptr,
img_data.boot_ramdisk_size);
+ ramdisk_ptr += img_data.boot_ramdisk_size;
if (img_data.bootconfig_size) {
memcpy((void *)
- (ramdisk_ptr + img_data.vendor_ramdisk_size +
- img_data.boot_ramdisk_size),
- (void *)img_data.bootconfig_addr,
+ (ramdisk_ptr), (void *)img_data.bootconfig_addr,
img_data.bootconfig_size);
}
}
printf("RAM disk load addr 0x%08lx size %u KiB\n",
- img_data.ramdisk_ptr, DIV_ROUND_UP(img_data.ramdisk_size, 1024));
+ img_data.ramdisk_addr, DIV_ROUND_UP(img_data.ramdisk_size, 1024));
- *rd_data = img_data.ramdisk_ptr;
+ *rd_data = img_data.ramdisk_addr;
*rd_len = img_data.ramdisk_size;
return 0;
diff --git a/boot/image-board.c b/boot/image-board.c
index b7884b8..f212401 100644
--- a/boot/image-board.c
+++ b/boot/image-board.c
@@ -406,13 +406,20 @@
if (IS_ENABLED(CONFIG_ANDROID_BOOT_IMAGE)) {
int ret;
if (IS_ENABLED(CONFIG_CMD_ABOOTIMG)) {
- void *boot_img = map_sysmem(get_abootimg_addr(), 0);
+ ulong boot_img = get_abootimg_addr();
+ ulong init_boot_img = get_ainit_bootimg_addr();
void *vendor_boot_img = map_sysmem(get_avendor_bootimg_addr(), 0);
+ void *ramdisk_img;
- ret = android_image_get_ramdisk(boot_img, vendor_boot_img,
+ if (init_boot_img == -1)
+ ramdisk_img = map_sysmem(boot_img, 0);
+ else
+ ramdisk_img = map_sysmem(init_boot_img, 0);
+
+ ret = android_image_get_ramdisk(ramdisk_img, vendor_boot_img,
rd_datap, rd_lenp);
unmap_sysmem(vendor_boot_img);
- unmap_sysmem(boot_img);
+ unmap_sysmem(ramdisk_img);
} else {
void *ptr = map_sysmem(images->os.start, 0);
diff --git a/boot/image-fit.c b/boot/image-fit.c
index fb03cab..9253f81 100644
--- a/boot/image-fit.c
+++ b/boot/image-fit.c
@@ -37,10 +37,6 @@
#include <image.h>
#include <bootstage.h>
#include <u-boot/crc.h>
-#include <u-boot/md5.h>
-#include <u-boot/sha1.h>
-#include <u-boot/sha256.h>
-#include <u-boot/sha512.h>
/*****************************************************************************/
/* New uImage format routines */
@@ -2179,7 +2175,8 @@
fit_image_check_os(fit, noffset, IH_OS_TEE) ||
fit_image_check_os(fit, noffset, IH_OS_OPENRTOS) ||
fit_image_check_os(fit, noffset, IH_OS_EFI) ||
- fit_image_check_os(fit, noffset, IH_OS_VXWORKS);
+ fit_image_check_os(fit, noffset, IH_OS_VXWORKS) ||
+ fit_image_check_os(fit, noffset, IH_OS_ELF);
/*
* If either of the checks fail, we should report an error, but
diff --git a/boot/image.c b/boot/image.c
index eb12e4b..abac254 100644
--- a/boot/image.c
+++ b/boot/image.c
@@ -25,8 +25,6 @@
#endif
#include <asm/global_data.h>
-#include <u-boot/md5.h>
-#include <u-boot/sha1.h>
#include <linux/errno.h>
#include <asm/io.h>
@@ -132,7 +130,10 @@
{ IH_OS_OPENRTOS, "openrtos", "OpenRTOS", },
#endif
{ IH_OS_OPENSBI, "opensbi", "RISC-V OpenSBI", },
- { IH_OS_EFI, "efi", "EFI Firmware" },
+ { IH_OS_EFI, "efi", "EFI Firmware" },
+#ifdef CONFIG_BOOTM_ELF
+ { IH_OS_ELF, "elf", "ELF Image" },
+#endif
{ -1, "", "", },
};
@@ -530,10 +531,10 @@
printf("Unimplemented compression type %d\n", comp);
return ret;
}
- if (ret)
- return ret;
*load_end = load + image_len;
+ if (ret)
+ return ret;
return 0;
}
diff --git a/boot/pxe_utils.c b/boot/pxe_utils.c
index 4b22bb6..53d6cf7 100644
--- a/boot/pxe_utils.c
+++ b/boot/pxe_utils.c
@@ -4,6 +4,8 @@
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
*/
+#define LOG_CATEGORY LOGC_BOOT
+
#include <command.h>
#include <dm.h>
#include <env.h>
@@ -323,10 +325,6 @@
#if CONFIG_IS_ENABLED(DM_RNG)
ulong fdt_addr;
struct fdt_header *working_fdt;
- size_t n = 0x8;
- struct udevice *dev;
- u64 *buf;
- int nodeoffset;
int err;
/* Get the main fdt and map it */
@@ -341,36 +339,8 @@
err = fdt_shrink_to_minimum(working_fdt, 512);
if (err <= 0)
return;
-
- if (uclass_get_device(UCLASS_RNG, 0, &dev) || !dev) {
- printf("No RNG device\n");
- return;
- }
-
- nodeoffset = fdt_find_or_add_subnode(working_fdt, 0, "chosen");
- if (nodeoffset < 0) {
- printf("Reading chosen node failed\n");
- return;
- }
-
- buf = malloc(n);
- if (!buf) {
- printf("Out of memory\n");
- return;
- }
- if (dm_rng_read(dev, buf, n)) {
- printf("Reading RNG failed\n");
- goto err;
- }
-
- err = fdt_setprop(working_fdt, nodeoffset, "kaslr-seed", buf, sizeof(buf));
- if (err < 0) {
- printf("Unable to set kaslr-seed on chosen node: %s\n", fdt_strerror(err));
- goto err;
- }
-err:
- free(buf);
+ fdt_kaslrseed(working_fdt, true);
#endif
return;
}
@@ -762,17 +732,22 @@
/* Try bootm for legacy and FIT format image */
if (genimg_get_format(buf) != IMAGE_FORMAT_INVALID &&
- IS_ENABLED(CONFIG_CMD_BOOTM))
+ IS_ENABLED(CONFIG_CMD_BOOTM)) {
+ log_debug("using bootm\n");
do_bootm(ctx->cmdtp, 0, bootm_argc, bootm_argv);
/* Try booting an AArch64 Linux kernel image */
- else if (IS_ENABLED(CONFIG_CMD_BOOTI))
+ } else if (IS_ENABLED(CONFIG_CMD_BOOTI)) {
+ log_debug("using booti\n");
do_booti(ctx->cmdtp, 0, bootm_argc, bootm_argv);
/* Try booting a Image */
- else if (IS_ENABLED(CONFIG_CMD_BOOTZ))
+ } else if (IS_ENABLED(CONFIG_CMD_BOOTZ)) {
+ log_debug("using bootz\n");
do_bootz(ctx->cmdtp, 0, bootm_argc, bootm_argv);
/* Try booting an x86_64 Linux kernel image */
- else if (IS_ENABLED(CONFIG_CMD_ZBOOT))
+ } else if (IS_ENABLED(CONFIG_CMD_ZBOOT)) {
+ log_debug("using zboot\n");
do_zboot_parent(ctx->cmdtp, 0, zboot_argc, zboot_argv, NULL);
+ }
unmap_sysmem(buf);
diff --git a/cmd/Kconfig b/cmd/Kconfig
index c06fec3..0cf0d8a 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -271,7 +271,7 @@
depends on CMD_BOOTM
depends on IMAGE_PRE_LOAD
help
- Enable support of stage pre-load for the bootm command.
+ Enable support of stage pre-load for the bootm command.
This stage allow to check or modify the image provided
to the bootm command.
@@ -308,7 +308,7 @@
depends on BOOTSTD
default y if BOOTSTD_FULL
help
- Support listing available bootmethds (methods used to boot an
+ Support listing available bootmeths (methods used to boot an
Operating System), as well as selecting the order that the bootmeths
are used.
@@ -321,6 +321,13 @@
help
Support booting UEFI FIT images via the bootm command.
+config BOOTM_ELF
+ bool "Support booting ELF images"
+ depends on CMD_BOOTM && LIB_ELF
+ default n
+ help
+ Support booting ELF images via the bootm command.
+
config CMD_BOOTZ
bool "bootz"
help
@@ -622,7 +629,7 @@
Consider using FIT in preference to this since it supports directly
booting both 32- and 64-bit kernels, as well as secure boot.
- Documentation is available in doc/uImage.FIT/x86-fit-boot.txt
+ Documentation is available in doc/usage/fit/x86-fit-boot.rst.
endmenu
@@ -804,9 +811,16 @@
types of eeprom fields. Can be used for defining
custom layouts.
+config EEPROM_LAYOUT_VERSIONS
+ bool "Support specifying eeprom layout version"
+ depends on CMD_EEPROM_LAYOUT
+ help
+ Support specifying eeprom layout version in the 'eeprom' command
+ via the -l option.
+
config EEPROM_LAYOUT_HELP_STRING
string "Tells user what layout names are supported"
- depends on CMD_EEPROM_LAYOUT
+ depends on EEPROM_LAYOUT_VERSIONS
default "<not defined>"
help
Help printed with the LAYOUT VERSIONS part of the 'eeprom'
@@ -898,9 +912,9 @@
bool "Enable cyclic md/mw commands"
depends on CMD_MEMORY
help
- Add the "mdc" and "mwc" memory commands. These are cyclic
- "md/mw" commands.
- Examples:
+ Add the "mdc" and "mwc" memory commands. These are cyclic
+ "md/mw" commands.
+ Examples:
=> mdc.b 10 4 500
This command will print 4 bytes (10,11,12,13) each 500 ms.
@@ -2154,12 +2168,12 @@
Example use-cases:
- Treat a region of RAM as a block device, i.e. a RAM disk. This let's
- you extract files from filesystem images stored in RAM (perhaps as a
- result of a TFTP transfer).
+ you extract files from filesystem images stored in RAM (perhaps as a
+ result of a TFTP transfer).
- Create a virtual partition on an existing device. This let's you
- access filesystems that aren't stored at an exact partition
- boundary. A common example is a filesystem image embedded in an FIT
- image.
+ access filesystems that aren't stored at an exact partition
+ boundary. A common example is a filesystem image embedded in an FIT
+ image.
config CMD_BUTTON
bool "button"
@@ -2938,7 +2952,7 @@
bool "Enable rename"
depends on CMD_UBI
help
- Enable a "ubi" command to rename ubi volume:
+ Enable a "ubi" command to rename ubi volume:
ubi rename <oldname> <newname>
config CMD_UBIFS
diff --git a/cmd/abootimg.c b/cmd/abootimg.c
index 88c77d9..327712a 100644
--- a/cmd/abootimg.c
+++ b/cmd/abootimg.c
@@ -14,6 +14,7 @@
/* Please use abootimg_addr() macro to obtain the boot image address */
static ulong _abootimg_addr = -1;
+static ulong _ainit_bootimg_addr = -1;
static ulong _avendor_bootimg_addr = -1;
ulong get_abootimg_addr(void)
@@ -21,6 +22,11 @@
return (_abootimg_addr == -1 ? image_load_addr : _abootimg_addr);
}
+ulong get_ainit_bootimg_addr(void)
+{
+ return _ainit_bootimg_addr;
+}
+
ulong get_avendor_bootimg_addr(void)
{
return _avendor_bootimg_addr;
@@ -179,7 +185,7 @@
char *endp;
ulong img_addr;
- if (argc < 2 || argc > 3)
+ if (argc < 2 || argc > 4)
return CMD_RET_USAGE;
img_addr = hextoul(argv[1], &endp);
@@ -190,16 +196,26 @@
_abootimg_addr = img_addr;
- if (argc == 3) {
+ if (argc > 2) {
img_addr = simple_strtoul(argv[2], &endp, 16);
if (*endp != '\0') {
- printf("Error: Wrong vendor image address\n");
+ printf("Error: Wrong vendor_boot image address\n");
return CMD_RET_FAILURE;
}
_avendor_bootimg_addr = img_addr;
}
+ if (argc == 4) {
+ img_addr = simple_strtoul(argv[3], &endp, 16);
+ if (*endp != '\0') {
+ printf("Error: Wrong init_boot image address\n");
+ return CMD_RET_FAILURE;
+ }
+
+ _ainit_bootimg_addr = img_addr;
+ }
+
return CMD_RET_SUCCESS;
}
@@ -243,7 +259,7 @@
}
static struct cmd_tbl cmd_abootimg_sub[] = {
- U_BOOT_CMD_MKENT(addr, 3, 1, do_abootimg_addr, "", ""),
+ U_BOOT_CMD_MKENT(addr, 4, 1, do_abootimg_addr, "", ""),
U_BOOT_CMD_MKENT(dump, 2, 1, do_abootimg_dump, "", ""),
U_BOOT_CMD_MKENT(get, 5, 1, do_abootimg_get, "", ""),
};
@@ -271,7 +287,7 @@
U_BOOT_CMD(
abootimg, CONFIG_SYS_MAXARGS, 0, do_abootimg,
"manipulate Android Boot Image",
- "addr <boot_img_addr> [<vendor_boot_img_addr>]>\n"
+ "addr <boot_img_addr> [<vendor_boot_img_addr> [<init_boot_img_addr>]]\n"
" - set the address in RAM where boot image is located\n"
" ($loadaddr is used by default)\n"
"abootimg dump dtb\n"
diff --git a/cmd/adc.c b/cmd/adc.c
index f87f978..4d3b5b6 100644
--- a/cmd/adc.c
+++ b/cmd/adc.c
@@ -152,11 +152,11 @@
return CMD_RET_SUCCESS;
}
-static char adc_help_text[] =
+U_BOOT_LONGHELP(adc,
"list - list ADC devices\n"
"adc info <name> - Get ADC device info\n"
"adc single <name> <channel> [varname] - Get Single data of ADC device channel\n"
- "adc scan <name> [channel mask] - Scan all [or masked] ADC channels";
+ "adc scan <name> [channel mask] - Scan all [or masked] ADC channels\n");
U_BOOT_CMD_WITH_SUBCMDS(adc, "ADC sub-system", adc_help_text,
U_BOOT_SUBCMD_MKENT(list, 1, 1, do_adc_list),
diff --git a/cmd/arm/exception.c b/cmd/arm/exception.c
index 98a9795..8857f12 100644
--- a/cmd/arm/exception.c
+++ b/cmd/arm/exception.c
@@ -49,12 +49,11 @@
"", ""),
};
-static char exception_help_text[] =
+U_BOOT_LONGHELP(exception,
"<ex>\n"
" The following exceptions are available:\n"
" breakpoint - prefetch abort\n"
" unaligned - data abort\n"
- " undefined - undefined instruction\n"
- ;
+ " undefined - undefined instruction\n");
#include <exception.h>
diff --git a/cmd/arm/exception64.c b/cmd/arm/exception64.c
index 73d6c20..4c5b953 100644
--- a/cmd/arm/exception64.c
+++ b/cmd/arm/exception64.c
@@ -77,12 +77,11 @@
"", ""),
};
-static char exception_help_text[] =
+U_BOOT_LONGHELP(exception,
"<ex>\n"
" The following exceptions are available:\n"
" breakpoint - breakpoint instruction exception\n"
" unaligned - unaligned LDAR data abort\n"
- " undefined - undefined instruction exception\n"
- ;
+ " undefined - undefined instruction exception\n");
#include <exception.h>
diff --git a/cmd/blob.c b/cmd/blob.c
index a3c1dc4..b1c72e3 100644
--- a/cmd/blob.c
+++ b/cmd/blob.c
@@ -99,7 +99,7 @@
}
/***************************************************/
-static char blob_help_text[] =
+U_BOOT_LONGHELP(blob,
"enc src dst len km - Encapsulate and create blob of data\n"
" $len bytes long at address $src and\n"
" store the result at address $dst.\n"
@@ -115,7 +115,7 @@
" modifier is stored.\n"
" The modifier is required for generation\n"
" /use as key for cryptographic operation.\n"
- " Key modifier should be 16 byte long.\n";
+ " Key modifier should be 16 byte long.\n");
U_BOOT_CMD(
blob, 6, 1, do_blob,
diff --git a/cmd/cache.c b/cmd/cache.c
index 0254ff1..7a20682 100644
--- a/cmd/cache.c
+++ b/cmd/cache.c
@@ -13,16 +13,6 @@
static int parse_argv(const char *);
-void __weak invalidate_icache_all(void)
-{
- /* please define arch specific invalidate_icache_all */
- puts("No arch specific invalidate_icache_all available!\n");
-}
-
-__weak void noncached_set_region(void)
-{
-}
-
static int do_icache(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
@@ -52,12 +42,6 @@
return 0;
}
-void __weak flush_dcache_all(void)
-{
- puts("No arch specific flush_dcache_all available!\n");
- /* please define arch specific flush_dcache_all */
-}
-
static int do_dcache(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
@@ -69,7 +53,9 @@
break;
case 1:
dcache_enable();
+#ifdef CONFIG_SYS_NONCACHED_MEMORY
noncached_set_region();
+#endif
break;
case 2:
flush_dcache_all();
diff --git a/cmd/cli.c b/cmd/cli.c
index be3bf7d..e0ddd0a 100644
--- a/cmd/cli.c
+++ b/cmd/cli.c
@@ -118,16 +118,11 @@
return CMD_RET_USAGE;
}
-#if CONFIG_IS_ENABLED(SYS_LONGHELP)
-static char cli_help_text[] =
+U_BOOT_LONGHELP(cli,
"get - print current cli\n"
- "set - set the current cli, possible value are: old, modern"
- ;
-#endif
+ "set - set the current cli, possible value are: old, modern\n");
U_BOOT_CMD(cli, 3, 1, do_cli,
"cli",
-#if CONFIG_IS_ENABLED(SYS_LONGHELP)
cli_help_text
-#endif
);
diff --git a/cmd/cyclic.c b/cmd/cyclic.c
index 40e966d..339dd4a 100644
--- a/cmd/cyclic.c
+++ b/cmd/cyclic.c
@@ -15,14 +15,16 @@
#include <time.h>
#include <vsprintf.h>
#include <linux/delay.h>
+#include <linux/kernel.h>
struct cyclic_demo_info {
+ struct cyclic_info cyclic;
uint delay_us;
};
-static void cyclic_demo(void *ctx)
+static void cyclic_demo(struct cyclic_info *c)
{
- struct cyclic_demo_info *info = ctx;
+ struct cyclic_demo_info *info = container_of(c, struct cyclic_demo_info, cyclic);
/* Just a small dummy delay here */
udelay(info->delay_us);
@@ -32,7 +34,6 @@
char *const argv[])
{
struct cyclic_demo_info *info;
- struct cyclic_info *cyclic;
uint time_ms;
if (argc < 3)
@@ -48,10 +49,7 @@
info->delay_us = simple_strtoul(argv[2], NULL, 0);
/* Register demo cyclic function */
- cyclic = cyclic_register(cyclic_demo, time_ms * 1000, "cyclic_demo",
- info);
- if (!cyclic)
- printf("Registering of cyclic_demo failed\n");
+ cyclic_register(&info->cyclic, cyclic_demo, time_ms * 1000, "cyclic_demo");
printf("Registered function \"%s\" to be executed all %dms\n",
"cyclic_demo", time_ms);
diff --git a/cmd/eeprom.c b/cmd/eeprom.c
index 26f3750..cf89cfc 100644
--- a/cmd/eeprom.c
+++ b/cmd/eeprom.c
@@ -21,8 +21,10 @@
#include <config.h>
#include <command.h>
+#include <dm.h>
#include <eeprom.h>
#include <i2c.h>
+#include <i2c_eeprom.h>
#include <eeprom_layout.h>
#include <vsprintf.h>
#include <linux/delay.h>
@@ -208,41 +210,95 @@
return (*endptr != '\0') ? -1 : value;
}
+struct eeprom_dev_spec {
+#if CONFIG_IS_ENABLED(I2C_EEPROM)
+ struct udevice *dev;
+#endif
+ int i2c_bus;
+ ulong i2c_addr;
+};
+
+static void eeprom_dev_spec_init(struct eeprom_dev_spec *dev)
+{
+#if CONFIG_IS_ENABLED(I2C_EEPROM)
+ if (!dev->dev)
+#endif
+ eeprom_init(dev->i2c_bus);
+}
+
+static int eeprom_dev_spec_read(struct eeprom_dev_spec *dev,
+ unsigned offset, uchar *buffer, unsigned cnt)
+{
+#if CONFIG_IS_ENABLED(I2C_EEPROM)
+ if (dev->dev)
+ return i2c_eeprom_read(dev->dev, offset, buffer, cnt);
+#endif
+ return eeprom_read(dev->i2c_addr, offset, buffer, cnt);
+}
+
+static int eeprom_dev_spec_write(struct eeprom_dev_spec *dev,
+ unsigned offset, uchar *buffer, unsigned cnt)
+{
+#if CONFIG_IS_ENABLED(I2C_EEPROM)
+ if (dev->dev)
+ return i2c_eeprom_write(dev->dev, offset, buffer, cnt);
+#endif
+ return eeprom_write(dev->i2c_addr, offset, buffer, cnt);
+}
+
/**
- * parse_i2c_bus_addr - parse the i2c bus and i2c devaddr parameters
+ * parse_eeprom_dev_spec - parse the eeprom device specifier
*
- * @i2c_bus: address to store the i2c bus
- * @i2c_addr: address to store the device i2c address
- * @argc: count of command line arguments left to parse
+ * @dev: pointer to eeprom device specifier
+ * @argc: count of command line arguments that can be used to parse
+ * the device specifier
* @argv: command line arguments left to parse
- * @argc_no_bus_addr: argc value we expect to see when bus & addr aren't given
*
* @returns: number of arguments parsed or CMD_RET_USAGE if error
*/
-static int parse_i2c_bus_addr(int *i2c_bus, ulong *i2c_addr, int argc,
- char *const argv[], int argc_no_bus_addr)
+static int parse_eeprom_dev_spec(struct eeprom_dev_spec *dev, int argc,
+ char *const argv[])
{
- int argc_no_bus = argc_no_bus_addr + 1;
- int argc_bus_addr = argc_no_bus_addr + 2;
+#if CONFIG_IS_ENABLED(I2C_EEPROM)
+ if (argc == 0) {
+ if (!uclass_first_device_err(UCLASS_I2C_EEPROM, &dev->dev))
+ return 0;
+ }
+
+ if (argc == 1) {
+ if (!uclass_get_device_by_name(UCLASS_I2C_EEPROM, argv[0],
+ &dev->dev))
+ return 1;
+
+ /*
+ * If we could not find the device by name and the parameter is
+ * not numeric (and so won't be handled later), fail.
+ */
+ if (parse_numeric_param(argv[0]) == -1) {
+ printf("Can't get eeprom device: %s\n", argv[0]);
+ return CMD_RET_USAGE;
+ }
+ }
+#endif
#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
- if (argc == argc_no_bus_addr) {
- *i2c_bus = -1;
- *i2c_addr = CONFIG_SYS_I2C_EEPROM_ADDR;
+ if (argc == 0) {
+ dev->i2c_bus = -1;
+ dev->i2c_addr = CONFIG_SYS_I2C_EEPROM_ADDR;
return 0;
}
#endif
- if (argc == argc_no_bus) {
- *i2c_bus = -1;
- *i2c_addr = parse_numeric_param(argv[0]);
+ if (argc == 1) {
+ dev->i2c_bus = -1;
+ dev->i2c_addr = parse_numeric_param(argv[0]);
return 1;
}
- if (argc == argc_bus_addr) {
- *i2c_bus = parse_numeric_param(argv[0]);
- *i2c_addr = parse_numeric_param(argv[1]);
+ if (argc == 2) {
+ dev->i2c_bus = parse_numeric_param(argv[0]);
+ dev->i2c_addr = parse_numeric_param(argv[1]);
return 2;
}
@@ -252,16 +308,19 @@
#ifdef CONFIG_CMD_EEPROM_LAYOUT
+#ifdef CONFIG_EEPROM_LAYOUT_VERSIONS
__weak int eeprom_parse_layout_version(char *str)
{
return LAYOUT_VERSION_UNRECOGNIZED;
}
+#endif
static unsigned char eeprom_buf[CONFIG_SYS_EEPROM_SIZE];
#endif
enum eeprom_action {
+ EEPROM_LIST,
EEPROM_READ,
EEPROM_WRITE,
EEPROM_PRINT,
@@ -271,6 +330,10 @@
static enum eeprom_action parse_action(char *cmd)
{
+#if CONFIG_IS_ENABLED(I2C_EEPROM)
+ if (!strncmp(cmd, "list", 4))
+ return EEPROM_LIST;
+#endif
if (!strncmp(cmd, "read", 4))
return EEPROM_READ;
if (!strncmp(cmd, "write", 5))
@@ -285,68 +348,115 @@
return EEPROM_ACTION_INVALID;
}
-static int eeprom_execute_command(enum eeprom_action action, int i2c_bus,
- ulong i2c_addr, int layout_ver, char *key,
- char *value, ulong addr, ulong off, ulong cnt)
+#if CONFIG_IS_ENABLED(I2C_EEPROM)
+static int do_eeprom_list(void)
{
- int rcode = 0;
+ struct udevice *dev;
+ struct uclass *uc;
+ int err;
+
+ err = uclass_get(UCLASS_I2C_EEPROM, &uc);
+ if (err)
+ return CMD_RET_FAILURE;
+
+ uclass_foreach_dev(dev, uc)
+ printf("%s (%s)\n", dev->name, dev->driver->name);
+
+ return CMD_RET_SUCCESS;
+}
+#endif
+
+static int do_eeprom_rw(struct eeprom_dev_spec *dev, bool read,
+ ulong addr, ulong off, ulong cnt)
+{
const char *const fmt =
"\nEEPROM @0x%lX %s: addr 0x%08lx off 0x%04lx count %ld ... ";
+ uchar *memloc = (uchar *)addr;
+ int ret;
+
+ printf(fmt, dev->i2c_addr, read ? "read" : "write", addr, off, cnt);
+ if (read)
+ ret = eeprom_dev_spec_read(dev, off, memloc, cnt);
+ else
+ ret = eeprom_dev_spec_write(dev, off, memloc, cnt);
+ puts("done\n");
+
+ return ret;
+}
+
#ifdef CONFIG_CMD_EEPROM_LAYOUT
- struct eeprom_layout layout;
-#endif
- if (action == EEPROM_ACTION_INVALID)
- return CMD_RET_USAGE;
+static int do_eeprom_layout(struct eeprom_dev_spec *dev, int layout_ver,
+ struct eeprom_layout *layout)
+{
+ eeprom_layout_setup(layout, eeprom_buf, CONFIG_SYS_EEPROM_SIZE,
+ layout_ver);
- eeprom_init(i2c_bus);
- if (action == EEPROM_READ) {
- printf(fmt, i2c_addr, "read", addr, off, cnt);
+ return eeprom_dev_spec_read(dev, 0, eeprom_buf, layout->data_size);
+}
- rcode = eeprom_read(i2c_addr, off, (uchar *)addr, cnt);
+static int do_eeprom_print(struct eeprom_dev_spec *dev, int layout_ver)
+{
+ struct eeprom_layout layout;
+ int ret;
- puts("done\n");
- return rcode;
- } else if (action == EEPROM_WRITE) {
- printf(fmt, i2c_addr, "write", addr, off, cnt);
+ ret = do_eeprom_layout(dev, layout_ver, &layout);
+ if (ret)
+ return ret;
- rcode = eeprom_write(i2c_addr, off, (uchar *)addr, cnt);
+ layout.print(&layout);
- puts("done\n");
- return rcode;
- }
+ return 0;
+}
-#ifdef CONFIG_CMD_EEPROM_LAYOUT
- rcode = eeprom_read(i2c_addr, 0, eeprom_buf, CONFIG_SYS_EEPROM_SIZE);
- if (rcode < 0)
- return rcode;
+static int do_eeprom_update(struct eeprom_dev_spec *dev, int layout_ver,
+ char *key, char *value)
+{
+ struct eeprom_layout layout;
+ int ret;
- eeprom_layout_setup(&layout, eeprom_buf, CONFIG_SYS_EEPROM_SIZE,
- layout_ver);
+ ret = do_eeprom_layout(dev, layout_ver, &layout);
+ if (ret)
+ return ret;
- if (action == EEPROM_PRINT) {
- layout.print(&layout);
- return 0;
- }
+ ret = layout.update(&layout, key, value);
+ if (ret)
+ return CMD_RET_FAILURE;
- layout.update(&layout, key, value);
+ return eeprom_dev_spec_write(dev, 0, layout.data, layout.data_size);
+}
- rcode = eeprom_write(i2c_addr, 0, layout.data, CONFIG_SYS_EEPROM_SIZE);
#endif
- return rcode;
+static int eeprom_action_expected_argc(enum eeprom_action action)
+{
+ switch (action) {
+ case EEPROM_LIST:
+ return 0;
+ case EEPROM_READ:
+ case EEPROM_WRITE:
+ return 3;
+ case EEPROM_PRINT:
+ return 0;
+ case EEPROM_UPDATE:
+ return 2;
+ default:
+ return CMD_RET_USAGE;
+ }
}
#define NEXT_PARAM(argc, index) { (argc)--; (index)++; }
int do_eeprom(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
- int layout_ver = LAYOUT_VERSION_AUTODETECT;
enum eeprom_action action = EEPROM_ACTION_INVALID;
- int i2c_bus = -1, index = 0;
- ulong i2c_addr = -1, addr = 0, cnt = 0, off = 0;
- int ret;
+ struct eeprom_dev_spec dev;
+ ulong addr = 0, cnt = 0, off = 0;
+ int ret, index = 0;
+#ifdef CONFIG_CMD_EEPROM_LAYOUT
char *field_name = "";
char *field_value = "";
+ int layout_ver = LAYOUT_VERSION_AUTODETECT;
+#endif
if (argc <= 1)
return CMD_RET_USAGE;
@@ -359,7 +469,12 @@
if (action == EEPROM_ACTION_INVALID)
return CMD_RET_USAGE;
-#ifdef CONFIG_CMD_EEPROM_LAYOUT
+#if CONFIG_IS_ENABLED(I2C_EEPROM)
+ if (action == EEPROM_LIST)
+ return do_eeprom_list();
+#endif
+
+#ifdef CONFIG_EEPROM_LAYOUT_VERSIONS
if (action == EEPROM_PRINT || action == EEPROM_UPDATE) {
if (!strcmp(argv[index], "-l")) {
NEXT_PARAM(argc, index);
@@ -369,25 +484,9 @@
}
#endif
- switch (action) {
- case EEPROM_READ:
- case EEPROM_WRITE:
- ret = parse_i2c_bus_addr(&i2c_bus, &i2c_addr, argc,
- argv + index, 3);
- break;
- case EEPROM_PRINT:
- ret = parse_i2c_bus_addr(&i2c_bus, &i2c_addr, argc,
- argv + index, 0);
- break;
- case EEPROM_UPDATE:
- ret = parse_i2c_bus_addr(&i2c_bus, &i2c_addr, argc,
- argv + index, 2);
- break;
- default:
- /* Get compiler to stop whining */
- return CMD_RET_USAGE;
- }
-
+ ret = parse_eeprom_dev_spec(&dev,
+ argc - eeprom_action_expected_argc(action),
+ argv + index);
if (ret == CMD_RET_USAGE)
return ret;
@@ -411,24 +510,64 @@
}
#endif
+ eeprom_dev_spec_init(&dev);
+
- return eeprom_execute_command(action, i2c_bus, i2c_addr, layout_ver,
- field_name, field_value, addr, off, cnt);
+ switch (action) {
+ case EEPROM_READ:
+ case EEPROM_WRITE:
+ return do_eeprom_rw(&dev, action == EEPROM_READ,
+ addr, off, cnt);
+#ifdef CONFIG_CMD_EEPROM_LAYOUT
+ case EEPROM_PRINT:
+ return do_eeprom_print(&dev, layout_ver);
+ case EEPROM_UPDATE:
+ return do_eeprom_update(&dev, layout_ver,
+ field_name, field_value);
+#endif
+ default:
+ return CMD_RET_USAGE;
+ }
}
+#ifdef CONFIG_EEPROM_LAYOUT_VERSIONS
+#define EEPROM_LAYOUT_SPEC "[-l <layout_version>] "
+#else
+#define EEPROM_LAYOUT_SPEC ""
+#endif
+
+#if CONFIG_IS_ENABLED(I2C_EEPROM)
+# define EEPROM_DEV_SPEC "[device_specifier]"
+#else
+# define EEPROM_DEV_SPEC "[[bus] devaddr]"
+#endif
+
U_BOOT_CMD(
eeprom, 8, 1, do_eeprom,
"EEPROM sub-system",
- "read <bus> <devaddr> addr off cnt\n"
- "eeprom write <bus> <devaddr> addr off cnt\n"
+#if CONFIG_IS_ENABLED(I2C_EEPROM)
+ "list\n"
+ "eeprom "
+#endif
+ "read " EEPROM_DEV_SPEC " addr off cnt\n"
+ "eeprom write " EEPROM_DEV_SPEC " addr off cnt\n"
" - read/write `cnt' bytes from `devaddr` EEPROM at offset `off'"
#ifdef CONFIG_CMD_EEPROM_LAYOUT
"\n"
- "eeprom print [-l <layout_version>] <bus> <devaddr>\n"
+ "eeprom print " EEPROM_LAYOUT_SPEC EEPROM_DEV_SPEC "\n"
" - Print layout fields and their data in human readable format\n"
- "eeprom update [-l <layout_version>] <bus> <devaddr> field_name field_value\n"
+ "eeprom update " EEPROM_LAYOUT_SPEC EEPROM_DEV_SPEC " field_name field_value\n"
" - Update a specific eeprom field with new data.\n"
- " The new data must be written in the same human readable format as shown by the print command.\n"
- "\n"
+ " The new data must be written in the same human readable format as shown by the print command."
+#endif
+#if CONFIG_IS_ENABLED(I2C_EEPROM)
+ "\n\n"
+ "DEVICE SPECIFIER - the eeprom device can be specified\n"
+ " [dev_name] - by device name (devices can listed with the eeprom list command)\n"
+ " [[bus] devaddr] - or by I2C bus and I2C device address\n"
+ "If no device specifier is given, the first driver-model found device is used."
+#endif
+#ifdef CONFIG_EEPROM_LAYOUT_VERSIONS
+ "\n\n"
"LAYOUT VERSIONS\n"
"The -l option can be used to force the command to interpret the EEPROM data using the chosen layout.\n"
"If the -l option is omitted, the command will auto detect the layout based on the data in the EEPROM.\n"
diff --git a/cmd/eficonfig.c b/cmd/eficonfig.c
index 4164cb4..bea09e4 100644
--- a/cmd/eficonfig.c
+++ b/cmd/eficonfig.c
@@ -61,6 +61,7 @@
struct eficonfig_boot_option {
struct eficonfig_select_file_info file_info;
struct eficonfig_select_file_info initrd_info;
+ struct eficonfig_select_file_info fdt_info;
unsigned int boot_index;
u16 *description;
u16 *optional_data;
@@ -530,7 +531,7 @@
dp = efi_dp_shorten(dp_volume);
if (!dp)
dp = dp_volume;
- dp = efi_dp_concat(dp, &fp->dp, false);
+ dp = efi_dp_concat(dp, &fp->dp, 0);
free(buf);
return dp;
@@ -1307,6 +1308,10 @@
if (ret != EFI_SUCCESS)
goto out;
+ ret = prepare_file_selection_entry(efi_menu, "Fdt File: ", &bo->fdt_info);
+ if (ret != EFI_SUCCESS)
+ goto out;
+
ret = create_boot_option_entry(efi_menu, "Optional Data: ", bo->optional_data,
eficonfig_boot_add_optional_data, bo);
if (ret != EFI_SUCCESS)
@@ -1387,30 +1392,47 @@
efi_status_t ret;
char *tmp = NULL, *p;
struct efi_load_option lo = {0};
- efi_uintn_t final_dp_size;
+ efi_uintn_t dp_size;
struct efi_device_path *dp = NULL;
efi_uintn_t size = load_option_size;
- struct efi_device_path *final_dp = NULL;
struct efi_device_path *device_dp = NULL;
struct efi_device_path *initrd_dp = NULL;
+ struct efi_device_path *fdt_dp = NULL;
struct efi_device_path *initrd_device_dp = NULL;
+ struct efi_device_path *fdt_device_dp = NULL;
- const struct efi_initrd_dp id_dp = {
+ const struct efi_lo_dp_prefix initrd_prefix = {
.vendor = {
{
DEVICE_PATH_TYPE_MEDIA_DEVICE,
DEVICE_PATH_SUB_TYPE_VENDOR_PATH,
- sizeof(id_dp.vendor),
+ sizeof(initrd_prefix.vendor),
},
EFI_INITRD_MEDIA_GUID,
},
.end = {
DEVICE_PATH_TYPE_END,
DEVICE_PATH_SUB_TYPE_END,
- sizeof(id_dp.end),
+ sizeof(initrd_prefix.end),
}
};
+ const struct efi_lo_dp_prefix fdt_prefix = {
+ .vendor = {
+ {
+ DEVICE_PATH_TYPE_MEDIA_DEVICE,
+ DEVICE_PATH_SUB_TYPE_VENDOR_PATH,
+ sizeof(fdt_prefix.vendor),
+ },
+ EFI_FDT_GUID,
+ },
+ .end = {
+ DEVICE_PATH_TYPE_END,
+ DEVICE_PATH_SUB_TYPE_END,
+ sizeof(initrd_prefix.end),
+ }
+ };
+
bo->file_info.current_path = calloc(1, EFICONFIG_FILE_PATH_BUF_SIZE);
if (!bo->file_info.current_path) {
ret = EFI_OUT_OF_RESOURCES;
@@ -1423,6 +1445,12 @@
goto out;
}
+ bo->fdt_info.current_path = calloc(1, EFICONFIG_FILE_PATH_BUF_SIZE);
+ if (!bo->fdt_info.current_path) {
+ ret = EFI_OUT_OF_RESOURCES;
+ goto out;
+ }
+
bo->description = calloc(1, EFICONFIG_DESCRIPTION_MAX * sizeof(u16));
if (!bo->description) {
ret = EFI_OUT_OF_RESOURCES;
@@ -1455,13 +1483,20 @@
if (lo.file_path)
fill_file_info(lo.file_path, &bo->file_info, device_dp);
- /* Initrd file path(optional) is placed at second instance. */
+ /* Initrd file path (optional) is placed at second instance. */
initrd_dp = efi_dp_from_lo(&lo, &efi_lf2_initrd_guid);
if (initrd_dp) {
fill_file_info(initrd_dp, &bo->initrd_info, initrd_device_dp);
efi_free_pool(initrd_dp);
}
+ /* Fdt file path (optional) is placed as third instance. */
+ fdt_dp = efi_dp_from_lo(&lo, &efi_guid_fdt);
+ if (fdt_dp) {
+ fill_file_info(fdt_dp, &bo->fdt_info, fdt_device_dp);
+ efi_free_pool(fdt_dp);
+ }
+
if (size > 0)
memcpy(bo->optional_data, lo.optional_data, size);
}
@@ -1483,8 +1518,20 @@
ret = EFI_OUT_OF_RESOURCES;
goto out;
}
+ initrd_dp = efi_dp_concat((const struct efi_device_path *)&initrd_prefix,
+ dp, 0);
+ efi_free_pool(dp);
+ }
+
+ if (bo->fdt_info.dp_volume) {
+ dp = eficonfig_create_device_path(bo->fdt_info.dp_volume,
+ bo->fdt_info.current_path);
+ if (!dp) {
+ ret = EFI_OUT_OF_RESOURCES;
+ goto out;
+ }
- initrd_dp = efi_dp_concat((const struct efi_device_path *)&id_dp,
- dp, false);
+ fdt_dp = efi_dp_concat((const struct efi_device_path *)&fdt_prefix,
+ dp, 0);
efi_free_pool(dp);
}
@@ -1493,16 +1540,9 @@
ret = EFI_OUT_OF_RESOURCES;
goto out;
}
- final_dp_size = efi_dp_size(dp) + sizeof(END);
- if (initrd_dp) {
- final_dp = efi_dp_concat(dp, initrd_dp, true);
- final_dp_size += efi_dp_size(initrd_dp) + sizeof(END);
- } else {
- final_dp = efi_dp_dup(dp);
- }
- efi_free_pool(dp);
- if (!final_dp)
+ ret = efi_load_option_dp_join(&dp, &dp_size, initrd_dp, fdt_dp);
+ if (ret != EFI_SUCCESS)
goto out;
if (utf16_utf8_strlen(bo->optional_data)) {
@@ -1514,17 +1554,20 @@
utf16_utf8_strncpy(&p, bo->optional_data, u16_strlen(bo->optional_data));
}
- ret = eficonfig_set_boot_option(varname, final_dp, final_dp_size, bo->description, tmp);
+ ret = eficonfig_set_boot_option(varname, dp, dp_size, bo->description, tmp);
out:
free(tmp);
free(bo->optional_data);
free(bo->description);
free(bo->file_info.current_path);
free(bo->initrd_info.current_path);
+ free(bo->fdt_info.current_path);
efi_free_pool(device_dp);
efi_free_pool(initrd_device_dp);
efi_free_pool(initrd_dp);
- efi_free_pool(final_dp);
+ efi_free_pool(fdt_device_dp);
+ efi_free_pool(fdt_dp);
+ efi_free_pool(dp);
return ret;
}
diff --git a/cmd/efidebug.c b/cmd/efidebug.c
index e978e74..1a191eb 100644
--- a/cmd/efidebug.c
+++ b/cmd/efidebug.c
@@ -653,38 +653,80 @@
}
/**
- * create_initrd_dp() - create a special device for our Boot### option
+ * enum efi_lo_dp_part - part of device path in load option
+ */
+enum efi_lo_dp_part {
+ /** @EFI_LO_DP_PART_BINARY: binary */
+ EFI_LO_DP_PART_BINARY,
+ /** @EFI_LO_DP_PART_INITRD: initial RAM disk */
+ EFI_LO_DP_PART_INITRD,
+ /** @EFI_LP_DP_PART_FDT: device-tree */
+ EFI_LP_DP_PART_FDT,
+};
+
+/**
+ * create_lo_dp() - create a special device path for our Boot### option
*
* @dev: device
* @part: disk partition
* @file: filename
* @shortform: create short form device path
+ * @type: part of device path to be created
* Return: pointer to the device path or ERR_PTR
*/
static
-struct efi_device_path *create_initrd_dp(const char *dev, const char *part,
- const char *file, int shortform)
+struct efi_device_path *create_lo_dp_part(const char *dev, const char *part,
+ const char *file, bool shortform,
+ enum efi_lo_dp_part type)
{
struct efi_device_path *tmp_dp = NULL, *tmp_fp = NULL, *short_fp = NULL;
- struct efi_device_path *initrd_dp = NULL;
+ struct efi_device_path *dp = NULL;
+ const struct efi_device_path *dp_prefix;
efi_status_t ret;
- const struct efi_initrd_dp id_dp = {
+ const struct efi_lo_dp_prefix fdt_dp = {
.vendor = {
{
DEVICE_PATH_TYPE_MEDIA_DEVICE,
DEVICE_PATH_SUB_TYPE_VENDOR_PATH,
- sizeof(id_dp.vendor),
+ sizeof(fdt_dp.vendor),
+ },
+ EFI_FDT_GUID,
+ },
+ .end = {
+ DEVICE_PATH_TYPE_END,
+ DEVICE_PATH_SUB_TYPE_END,
+ sizeof(fdt_dp.end),
+ }
+ };
+ const struct efi_lo_dp_prefix initrd_dp = {
+ .vendor = {
+ {
+ DEVICE_PATH_TYPE_MEDIA_DEVICE,
+ DEVICE_PATH_SUB_TYPE_VENDOR_PATH,
+ sizeof(initrd_dp.vendor),
},
EFI_INITRD_MEDIA_GUID,
},
.end = {
DEVICE_PATH_TYPE_END,
DEVICE_PATH_SUB_TYPE_END,
- sizeof(id_dp.end),
+ sizeof(initrd_dp.end),
}
};
+ switch (type) {
+ case EFI_LO_DP_PART_INITRD:
+ dp_prefix = &initrd_dp.vendor.dp;
+ break;
+ case EFI_LP_DP_PART_FDT:
+ dp_prefix = &fdt_dp.vendor.dp;
+ break;
+ default:
+ dp_prefix = NULL;
+ break;
+ }
+
ret = efi_dp_from_name(dev, part, file, &tmp_dp, &tmp_fp);
if (ret != EFI_SUCCESS) {
printf("Cannot create device path for \"%s %s\"\n", part, file);
@@ -695,13 +737,12 @@
if (!short_fp)
short_fp = tmp_fp;
- initrd_dp = efi_dp_concat((const struct efi_device_path *)&id_dp,
- short_fp, false);
+ dp = efi_dp_concat(dp_prefix, short_fp, 0);
out:
efi_free_pool(tmp_dp);
efi_free_pool(tmp_fp);
- return initrd_dp;
+ return dp;
}
/**
@@ -792,9 +833,8 @@
efi_guid_t guid;
u16 *label;
struct efi_device_path *file_path = NULL;
- struct efi_device_path *fp_free = NULL;
- struct efi_device_path *final_fp = NULL;
struct efi_device_path *initrd_dp = NULL;
+ struct efi_device_path *fdt_dp = NULL;
struct efi_load_option lo;
void *data = NULL;
efi_uintn_t size;
@@ -842,22 +882,31 @@
lo.label = label; /* label will be changed below */
/* file path */
- ret = efi_dp_from_name(argv[3], argv[4], argv[5],
- NULL, &fp_free);
- if (ret != EFI_SUCCESS) {
- printf("Cannot create device path for \"%s %s\"\n",
- argv[3], argv[4]);
+ file_path = create_lo_dp_part(argv[3], argv[4], argv[5],
+ shortform,
+ EFI_LO_DP_PART_BINARY);
+ argc -= 5;
+ argv += 5;
+ break;
+ case 'd':
+ shortform = 1;
+ fallthrough;
+ case 'D':
+ if (argc < 3 || fdt_dp) {
+ r = CMD_RET_USAGE;
+ goto out;
+ }
+
+ fdt_dp = create_lo_dp_part(argv[1], argv[2], argv[3],
+ shortform,
+ EFI_LP_DP_PART_FDT);
+ if (!fdt_dp) {
+ printf("Cannot add a device-tree\n");
r = CMD_RET_FAILURE;
goto out;
}
- if (shortform)
- file_path = efi_dp_shorten(fp_free);
- if (!file_path)
- file_path = fp_free;
- fp_size += efi_dp_size(file_path) +
- sizeof(struct efi_device_path);
- argc -= 5;
- argv += 5;
+ argc -= 3;
+ argv += 3;
break;
case 'i':
shortform = 1;
@@ -868,8 +917,9 @@
goto out;
}
- initrd_dp = create_initrd_dp(argv[1], argv[2], argv[3],
- shortform);
+ initrd_dp = create_lo_dp_part(argv[1], argv[2], argv[3],
+ shortform,
+ EFI_LO_DP_PART_INITRD);
if (!initrd_dp) {
printf("Cannot add an initrd\n");
r = CMD_RET_FAILURE;
@@ -877,8 +927,6 @@
}
argc -= 3;
argv += 3;
- fp_size += efi_dp_size(initrd_dp) +
- sizeof(struct efi_device_path);
break;
case 's':
if (argc < 1 || lo.optional_data) {
@@ -896,7 +944,6 @@
&file_path, &fp_size);
if (r != CMD_RET_SUCCESS)
goto out;
- fp_free = file_path;
argc -= 3;
argv += 3;
} else{
@@ -916,14 +963,14 @@
goto out;
}
- final_fp = efi_dp_concat(file_path, initrd_dp, true);
- if (!final_fp) {
+ ret = efi_load_option_dp_join(&file_path, &fp_size, initrd_dp, fdt_dp);
+ if (ret != EFI_SUCCESS) {
printf("Cannot create final device path\n");
r = CMD_RET_FAILURE;
goto out;
}
- lo.file_path = final_fp;
+ lo.file_path = file_path;
lo.file_path_length = fp_size;
size = efi_serialize_load_option(&lo, (u8 **)&data);
@@ -944,9 +991,9 @@
out:
free(data);
- efi_free_pool(final_fp);
efi_free_pool(initrd_dp);
- efi_free_pool(fp_free);
+ efi_free_pool(fdt_dp);
+ efi_free_pool(file_path);
free(lo.label);
return r;
@@ -1008,7 +1055,8 @@
*/
static void show_efi_boot_opt_data(u16 *varname16, void *data, size_t *size)
{
- struct efi_device_path *initrd_path = NULL;
+ struct efi_device_path *fdt_path;
+ struct efi_device_path *initrd_path;
struct efi_load_option lo;
efi_status_t ret;
@@ -1037,6 +1085,12 @@
efi_free_pool(initrd_path);
}
+ fdt_path = efi_dp_from_lo(&lo, &efi_guid_fdt);
+ if (fdt_path) {
+ printf(" device-tree path: %pD\n", fdt_path);
+ efi_free_pool(fdt_path);
+ }
+
printf(" data:\n");
print_hex_dump(" ", DUMP_PREFIX_OFFSET, 16, 1,
lo.optional_data, *size, true);
@@ -1564,8 +1618,9 @@
"\n"
"efidebug boot add - set UEFI BootXXXX variable\n"
" -b|-B <bootid> <label> <interface> <devnum>[:<part>] <file path>\n"
+ " -d|-D <interface> <devnum>[:<part>] <device-tree file path>\n"
" -i|-I <interface> <devnum>[:<part>] <initrd file path>\n"
- " (-b, -i for short form device path)\n"
+ " (-b, -d, -i for short form device path)\n"
#if (IS_ENABLED(CONFIG_EFI_HTTP_BOOT))
" -u <bootid> <label> <uri>\n"
#endif
diff --git a/cmd/elf.c b/cmd/elf.c
index a02361f..673c6c3 100644
--- a/cmd/elf.c
+++ b/cmd/elf.c
@@ -19,21 +19,6 @@
#include <linux/linkage.h>
#endif
-/* Allow ports to override the default behavior */
-static unsigned long do_bootelf_exec(ulong (*entry)(int, char * const[]),
- int argc, char *const argv[])
-{
- unsigned long ret;
-
- /*
- * pass address parameter as argv[0] (aka command name),
- * and all remaining args
- */
- ret = entry(argc, argv);
-
- return ret;
-}
-
/* Interpreter command to boot an arbitrary ELF image from memory */
int do_bootelf(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
@@ -43,8 +28,8 @@
#endif
unsigned long addr; /* Address of the ELF image */
unsigned long rc; /* Return value from user code */
- char *sload = NULL;
- int rcode = 0;
+ int rcode = CMD_RET_SUCCESS;
+ Bootelf_flags flags = {0};
/* Consume 'bootelf' */
argc--; argv++;
@@ -52,7 +37,10 @@
/* Check for [-p|-s] flag. */
if (argc >= 1 && (argv[0][0] == '-' && \
(argv[0][1] == 'p' || argv[0][1] == 's'))) {
- sload = argv[0];
+ if (argv[0][1] == 'p')
+ flags.phdr = 1;
+ log_debug("Using ELF header format %s\n",
+ flags.phdr ? "phdr" : "shdr");
/* Consume flag. */
argc--; argv++;
}
@@ -75,39 +63,39 @@
} else
addr = image_load_addr;
- if (!valid_elf_image(addr))
- return 1;
-
- if (sload && sload[1] == 'p')
- addr = load_elf_image_phdr(addr);
- else
- addr = load_elf_image_shdr(addr);
-
#if CONFIG_IS_ENABLED(CMD_ELF_FDT_SETUP)
if (fdt_addr) {
- printf("## Setting up FDT at 0x%08lx ...\n", fdt_addr);
+ log_debug("Setting up FDT at 0x%08lx ...\n", fdt_addr);
flush();
+ fdt_set_totalsize((void *)fdt_addr,
+ fdt_totalsize(fdt_addr) + CONFIG_SYS_FDT_PAD);
if (image_setup_libfdt(&img, (void *)fdt_addr, NULL))
return 1;
}
#endif
- if (!env_get_autostart())
- return rcode;
-
- printf("## Starting application at 0x%08lx ...\n", addr);
- flush();
+ if (env_get_autostart()) {
+ flags.autostart = 1;
+ log_debug("Starting application at 0x%08lx ...\n", addr);
+ flush();
+ }
/*
* pass address parameter as argv[0] (aka command name),
- * and all remaining args
+ * and all remaining arguments
*/
- rc = do_bootelf_exec((void *)addr, argc, argv);
+ rc = bootelf(addr, flags, argc, argv);
if (rc != 0)
- rcode = 1;
+ rcode = CMD_RET_FAILURE;
- printf("## Application terminated, rc = 0x%lx\n", rc);
+ if (flags.autostart)
+ {
+ if (ENOEXEC == errno)
+ log_err("Invalid ELF image\n");
+ else
+ log_debug("## Application terminated, rc = 0x%lx\n", rc);
+ }
return rcode;
}
diff --git a/cmd/fwu_mdata.c b/cmd/fwu_mdata.c
index 5ecda45..9c048d6 100644
--- a/cmd/fwu_mdata.c
+++ b/cmd/fwu_mdata.c
@@ -13,27 +13,34 @@
#include <linux/types.h>
-static void print_mdata(struct fwu_mdata *mdata)
+static void print_mdata(struct fwu_data *data)
{
int i, j;
struct fwu_image_entry *img_entry;
struct fwu_image_bank_info *img_info;
printf("\tFWU Metadata\n");
- printf("crc32: %#x\n", mdata->crc32);
- printf("version: %#x\n", mdata->version);
- printf("active_index: %#x\n", mdata->active_index);
- printf("previous_active_index: %#x\n", mdata->previous_active_index);
+ printf("crc32: %#x\n", data->crc32);
+ printf("version: %#x\n", data->version);
+ printf("size: %#x\n", data->metadata_size);
+ printf("active_index: %#x\n", data->active_index);
+ printf("previous_active_index: %#x\n", data->previous_active_index);
+
+ if (data->version == 2) {
+ for (i = 0; i < 4; i++)
+ printf("bank_state[%d]: %#x\n",
+ i, data->bank_state[i]);
+ }
printf("\tImage Info\n");
for (i = 0; i < CONFIG_FWU_NUM_IMAGES_PER_BANK; i++) {
- img_entry = &mdata->img_entry[i];
+ img_entry = &data->fwu_images[i];
printf("\nImage Type Guid: %pUL\n",
- &img_entry->image_type_uuid);
- printf("Location Guid: %pUL\n", &img_entry->location_uuid);
+ &img_entry->image_type_guid);
+ printf("Location Guid: %pUL\n", &img_entry->location_guid);
for (j = 0; j < CONFIG_FWU_NUM_BANKS; j++) {
img_info = &img_entry->img_bank_info[j];
- printf("Image Guid: %pUL\n", &img_info->image_uuid);
+ printf("Image Guid: %pUL\n", &img_info->image_guid);
printf("Image Acceptance: %s\n",
img_info->accepted == 0x1 ? "yes" : "no");
}
@@ -43,20 +50,11 @@
int do_fwu_mdata_read(struct cmd_tbl *cmdtp, int flag,
int argc, char * const argv[])
{
- int ret = CMD_RET_SUCCESS, res;
- struct fwu_mdata mdata;
+ struct fwu_data *data = fwu_get_data();
- res = fwu_get_mdata(&mdata);
- if (res < 0) {
- log_err("Unable to get valid FWU metadata\n");
- ret = CMD_RET_FAILURE;
- goto out;
- }
-
- print_mdata(&mdata);
+ print_mdata(data);
-out:
- return ret;
+ return CMD_RET_SUCCESS;
}
U_BOOT_CMD(
diff --git a/cmd/gpt.c b/cmd/gpt.c
index 36b112d..86b7701 100644
--- a/cmd/gpt.c
+++ b/cmd/gpt.c
@@ -116,6 +116,7 @@
k = strsep(&v, "=");
if (!k)
break;
+ k += strspn(k, " \t");
if (strcmp(k, key) == 0) {
new = strdup(v);
break;
@@ -150,6 +151,7 @@
k = strsep(&s, ",");
if (!k)
break;
+ k += strspn(k, " \t");
if (strcmp(k, key) == 0) {
result = true;
break;
@@ -682,7 +684,8 @@
free(str_disk_guid);
free(partitions);
out:
- free(gpt_pte);
+ if (!ret)
+ free(gpt_pte);
return ret;
}
diff --git a/cmd/kaslrseed.c b/cmd/kaslrseed.c
index e0d3c7f..2ad983a 100644
--- a/cmd/kaslrseed.c
+++ b/cmd/kaslrseed.c
@@ -15,60 +15,25 @@
static int do_kaslr_seed(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
- size_t n = 0x8;
- struct udevice *dev;
- u64 *buf;
- int nodeoffset;
- int ret = CMD_RET_SUCCESS;
+ int err = CMD_RET_SUCCESS;
- if (uclass_get_device(UCLASS_RNG, 0, &dev) || !dev) {
- printf("No RNG device\n");
- return CMD_RET_FAILURE;
- }
-
- buf = malloc(n);
- if (!buf) {
- printf("Out of memory\n");
- return CMD_RET_FAILURE;
- }
-
- if (dm_rng_read(dev, buf, n)) {
- printf("Reading RNG failed\n");
- return CMD_RET_FAILURE;
- }
+ printf("Notice: a /chosen/kaslr-seed is automatically added to the device-tree when booted via booti/bootm/bootz therefore using this command is likely no longer needed\n");
if (!working_fdt) {
printf("No FDT memory address configured. Please configure\n"
"the FDT address via \"fdt addr <address>\" command.\n"
"Aborting!\n");
- return CMD_RET_FAILURE;
- }
-
- ret = fdt_check_header(working_fdt);
- if (ret < 0) {
- printf("fdt_chosen: %s\n", fdt_strerror(ret));
- return CMD_RET_FAILURE;
- }
-
- nodeoffset = fdt_find_or_add_subnode(working_fdt, 0, "chosen");
- if (nodeoffset < 0) {
- printf("Reading chosen node failed\n");
- return CMD_RET_FAILURE;
+ err = CMD_RET_FAILURE;
+ } else {
+ if (fdt_kaslrseed(working_fdt, true) < 0)
+ err = CMD_RET_FAILURE;
}
- ret = fdt_setprop(working_fdt, nodeoffset, "kaslr-seed", buf, sizeof(buf));
- if (ret < 0) {
- printf("Unable to set kaslr-seed on chosen node: %s\n", fdt_strerror(ret));
- return CMD_RET_FAILURE;
- }
-
- free(buf);
-
- return ret;
+ return cmd_process_error(cmdtp, err);
}
U_BOOT_LONGHELP(kaslrseed,
- "[n]\n"
+ "\n"
" - append random bytes to chosen kaslr-seed node\n");
U_BOOT_CMD(
diff --git a/cmd/part.c b/cmd/part.c
index d140a1e..db7bc58 100644
--- a/cmd/part.c
+++ b/cmd/part.c
@@ -19,6 +19,7 @@
#include <command.h>
#include <env.h>
#include <part.h>
+#include <stdio.h>
#include <vsprintf.h>
enum cmd_part_info {
diff --git a/cmd/riscv/exception.c b/cmd/riscv/exception.c
index 14ad6c4..2b58b1c 100644
--- a/cmd/riscv/exception.c
+++ b/cmd/riscv/exception.c
@@ -68,14 +68,13 @@
"", ""),
};
-static char exception_help_text[] =
+U_BOOT_LONGHELP(exception,
"<ex>\n"
" The following exceptions are available:\n"
" compressed - compressed instruction\n"
" ebreak - breakpoint\n"
" ialign16 - 16 bit aligned instruction\n"
" undefined - illegal instruction\n"
- " unaligned - load address misaligned\n"
- ;
+ " unaligned - load address misaligned\n");
#include <exception.h>
diff --git a/cmd/scmi.c b/cmd/scmi.c
index 664062c..cfbca63 100644
--- a/cmd/scmi.c
+++ b/cmd/scmi.c
@@ -369,7 +369,7 @@
return cp->cmd(cmdtp, flag, argc, argv);
}
-static char scmi_help_text[] =
+U_BOOT_LONGHELP(scmi,
" - SCMI utility\n"
" info - get the info of SCMI services\n"
" perm_dev <agent-id in hex> <device-id in hex> <flags in hex>\n"
@@ -377,8 +377,7 @@
" perm_proto <agent-id in hex> <device-id in hex> <protocol-id in hex> <flags in hex>\n"
" - set protocol permission to device\n"
" reset <agent-id in hex> <flags in hex>\n"
- " - reset platform resource settings\n"
- "";
+ " - reset platform resource settings\n");
U_BOOT_CMD(scmi, CONFIG_SYS_MAXARGS, 0, do_scmi, "SCMI utility",
scmi_help_text);
diff --git a/cmd/sound.c b/cmd/sound.c
index 08bf741..8f67cbd 100644
--- a/cmd/sound.c
+++ b/cmd/sound.c
@@ -98,7 +98,7 @@
sound, INT_MAX, 1, do_sound,
"sound sub-system",
"init - initialise the sound driver\n"
- "sound play [[[-q|-s] len [freq]] ...] - play sounds\n"
+ "sound play [len [freq [len [freq ...]]]] - play sounds\n"
" len - duration in ms\n"
" freq - frequency in Hz\n"
);
diff --git a/cmd/tpm-v2.c b/cmd/tpm-v2.c
index 99c540b..8517833 100644
--- a/cmd/tpm-v2.c
+++ b/cmd/tpm-v2.c
@@ -98,11 +98,19 @@
struct tpm_chip_priv *priv;
u32 index = simple_strtoul(argv[1], NULL, 0);
void *digest = map_sysmem(simple_strtoul(argv[2], NULL, 0), 0);
+ int algo = TPM2_ALG_SHA256;
+ int algo_len;
int ret;
u32 rc;
- if (argc != 3)
+ if (argc < 3 || argc > 4)
return CMD_RET_USAGE;
+ if (argc == 4) {
+ algo = tpm2_name_to_algorithm(argv[3]);
+ if (algo < 0)
+ return CMD_RET_FAILURE;
+ }
+ algo_len = tpm2_algorithm_to_len(algo);
ret = get_tpm(&dev);
if (ret)
@@ -115,8 +123,12 @@
if (index >= priv->pcr_count)
return -EINVAL;
- rc = tpm2_pcr_extend(dev, index, TPM2_ALG_SHA256, digest,
- TPM2_DIGEST_LEN);
+ rc = tpm2_pcr_extend(dev, index, algo, digest, algo_len);
+ if (!rc) {
+ printf("PCR #%u extended with %d byte %s digest\n", index,
+ algo_len, tpm2_algorithm_name(algo));
+ print_byte_string(digest, algo_len);
+ }
unmap_sysmem(digest);
@@ -126,15 +138,23 @@
static int do_tpm_pcr_read(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
+ enum tpm2_algorithms algo = TPM2_ALG_SHA256;
struct udevice *dev;
struct tpm_chip_priv *priv;
u32 index, rc;
+ int algo_len;
unsigned int updates;
void *data;
int ret;
- if (argc != 3)
+ if (argc < 3 || argc > 4)
return CMD_RET_USAGE;
+ if (argc == 4) {
+ algo = tpm2_name_to_algorithm(argv[3]);
+ if (algo < 0)
+ return CMD_RET_FAILURE;
+ }
+ algo_len = tpm2_algorithm_to_len(algo);
ret = get_tpm(&dev);
if (ret)
@@ -150,11 +170,12 @@
data = map_sysmem(simple_strtoul(argv[2], NULL, 0), 0);
- rc = tpm2_pcr_read(dev, index, priv->pcr_select_min, TPM2_ALG_SHA256,
- data, TPM2_DIGEST_LEN, &updates);
+ rc = tpm2_pcr_read(dev, index, priv->pcr_select_min, algo,
+ data, algo_len, &updates);
if (!rc) {
- printf("PCR #%u content (%u known updates):\n", index, updates);
- print_byte_string(data, TPM2_DIGEST_LEN);
+ printf("PCR #%u %s %d byte content (%u known updates):\n", index,
+ tpm2_algorithm_name(algo), algo_len, updates);
+ print_byte_string(data, algo_len);
}
unmap_sysmem(data);
@@ -414,14 +435,14 @@
" <hierarchy> is one of:\n"
" * TPM2_RH_LOCKOUT\n"
" * TPM2_RH_PLATFORM\n"
-"pcr_extend <pcr> <digest_addr>\n"
-" Extend PCR #<pcr> with digest at <digest_addr>.\n"
+"pcr_extend <pcr> <digest_addr> [<digest_algo>]\n"
+" Extend PCR #<pcr> with digest at <digest_addr> with digest_algo.\n"
" <pcr>: index of the PCR\n"
-" <digest_addr>: address of a 32-byte SHA256 digest\n"
-"pcr_read <pcr> <digest_addr>\n"
-" Read PCR #<pcr> to memory address <digest_addr>.\n"
+" <digest_addr>: address of digest of digest_algo type (defaults to SHA256)\n"
+"pcr_read <pcr> <digest_addr> [<digest_algo>]\n"
+" Read PCR #<pcr> to memory address <digest_addr> with <digest_algo>.\n"
" <pcr>: index of the PCR\n"
-" <digest_addr>: address to store the a 32-byte SHA256 digest\n"
+" <digest_addr>: address of digest of digest_algo type (defaults to SHA256)\n"
"get_capability <capability> <property> <addr> <count>\n"
" Read and display <count> entries indexed by <capability>/<property>.\n"
" Values are 4 bytes long and are written at <addr>.\n"
diff --git a/cmd/ubi.c b/cmd/ubi.c
index 8c1b5df..92998af 100644
--- a/cmd/ubi.c
+++ b/cmd/ubi.c
@@ -248,7 +248,7 @@
static struct ubi_volume *ubi_find_volume(char *volume)
{
- struct ubi_volume *vol = NULL;
+ struct ubi_volume *vol;
int i;
for (i = 0; i < ubi->vtbl_slots; i++) {
@@ -355,13 +355,18 @@
static int ubi_volume_continue_write(char *volume, void *buf, size_t size)
{
- int err = 1;
+ int err;
struct ubi_volume *vol;
vol = ubi_find_volume(volume);
if (vol == NULL)
return ENODEV;
+ if (!vol->updating) {
+ printf("UBI volume update was not initiated\n");
+ return EINVAL;
+ }
+
err = ubi_more_update_data(ubi, vol, buf, size);
if (err < 0) {
printf("Couldnt or partially wrote data\n");
@@ -391,8 +396,8 @@
int ubi_volume_begin_write(char *volume, void *buf, size_t size,
size_t full_size)
{
- int err = 1;
- int rsvd_bytes = 0;
+ int err;
+ int rsvd_bytes;
struct ubi_volume *vol;
vol = ubi_find_volume(volume);
@@ -411,6 +416,10 @@
return -err;
}
+ /* The volume is just wiped out */
+ if (!full_size)
+ return 0;
+
return ubi_volume_continue_write(volume, buf, size);
}
@@ -573,7 +582,7 @@
int ubi_part(char *part_name, const char *vid_header_offset)
{
struct mtd_info *mtd;
- int err = 0;
+ int err;
if (ubi && ubi->mtd && !strcmp(ubi->mtd->name, part_name)) {
printf("UBI partition '%s' already selected\n", part_name);
@@ -604,7 +613,7 @@
static int do_ubi(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
- int64_t size = 0;
+ int64_t size;
ulong addr = 0;
bool skipcheck = false;
diff --git a/cmd/unlz4.c b/cmd/unlz4.c
index fc52001..2eadc75 100644
--- a/cmd/unlz4.c
+++ b/cmd/unlz4.c
@@ -6,6 +6,7 @@
#include <command.h>
#include <env.h>
+#include <mapmem.h>
#include <vsprintf.h>
#include <u-boot/lz4.h>
@@ -26,7 +27,8 @@
return CMD_RET_USAGE;
}
- ret = ulz4fn((void *)src, src_len, (void *)dst, &dst_len);
+ ret = ulz4fn(map_sysmem(src, 0), src_len, map_sysmem(dst, dst_len),
+ &dst_len);
if (ret) {
printf("Uncompressed err :%d\n", ret);
return 1;
diff --git a/cmd/usb.c b/cmd/usb.c
index 3a3764a..225d929 100644
--- a/cmd/usb.c
+++ b/cmd/usb.c
@@ -25,9 +25,6 @@
#ifdef CONFIG_USB_STORAGE
static int usb_stor_curr_dev = -1; /* current device */
#endif
-#if defined(CONFIG_USB_HOST_ETHER) && !defined(CONFIG_DM_ETH)
-static int __maybe_unused usb_ether_curr_dev = -1; /* current ethernet device */
-#endif
/* some display routines (info command) */
static char *usb_get_class_desc(unsigned char dclass)
diff --git a/cmd/x86/exception.c b/cmd/x86/exception.c
index 14b6bd6..0273549 100644
--- a/cmd/x86/exception.c
+++ b/cmd/x86/exception.c
@@ -19,10 +19,9 @@
"", ""),
};
-static char exception_help_text[] =
+U_BOOT_LONGHELP(exception,
"<ex>\n"
" The following exceptions are available:\n"
- " undefined - undefined instruction\n"
- ;
+ " undefined - undefined instruction\n");
#include <exception.h>
diff --git a/cmd/x86/zboot.c b/cmd/x86/zboot.c
index addf28c..94e602b8 100644
--- a/cmd/x86/zboot.c
+++ b/cmd/x86/zboot.c
@@ -5,6 +5,8 @@
* Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
*/
+#define LOG_CATEGORY LOGC_BOOT
+
#include <command.h>
#include <mapmem.h>
#include <vsprintf.h>
@@ -14,8 +16,14 @@
char *const argv[])
{
ulong bzimage_addr = 0, bzimage_size, initrd_addr, initrd_size;
- ulong base_addr;
const char *s, *cmdline;
+ ulong base_addr;
+ int i;
+
+ log_debug("argc %d:", argc);
+ for (i = 0; i < argc; i++)
+ log_debug(" %s", argv[i]);
+ log_debug("\n");
/* argv[1] holds the address of the bzImage */
s = cmd_arg1(argc, argv) ? : env_get("fileaddr");
@@ -114,17 +122,18 @@
int do_zboot_states(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[], int state_mask)
{
- int ret;
+ int ret = 0;
- if (flag & ZBOOT_STATE_START)
+ log_debug("state_mask %x\n", state_mask);
+ if (state_mask & ZBOOT_STATE_START)
ret = do_zboot_start(cmdtp, flag, argc, argv);
- if (!ret && (flag & ZBOOT_STATE_LOAD))
+ if (!ret && (state_mask & ZBOOT_STATE_LOAD))
ret = do_zboot_load(cmdtp, flag, argc, argv);
- if (!ret && (flag & ZBOOT_STATE_SETUP))
+ if (!ret && (state_mask & ZBOOT_STATE_SETUP))
ret = do_zboot_setup(cmdtp, flag, argc, argv);
- if (!ret && (flag & ZBOOT_STATE_INFO))
+ if (!ret && (state_mask & ZBOOT_STATE_INFO))
ret = do_zboot_info(cmdtp, flag, argc, argv);
- if (!ret && (flag & ZBOOT_STATE_GO))
+ if (!ret && (state_mask & ZBOOT_STATE_GO))
ret = do_zboot_go(cmdtp, flag, argc, argv);
if (ret)
return ret;
diff --git a/cmd/ximg.c b/cmd/ximg.c
index 1467484..c79e8a0 100644
--- a/cmd/ximg.c
+++ b/cmd/ximg.c
@@ -15,6 +15,9 @@
#include <cpu_func.h>
#include <env.h>
#include <gzip.h>
+#if IS_ENABLED(CONFIG_ZSTD)
+#include <linux/zstd.h>
+#endif
#include <image.h>
#include <malloc.h>
#include <mapmem.h>
@@ -237,6 +240,26 @@
}
break;
#endif /* CONFIG_BZIP2 */
+#if IS_ENABLED(CONFIG_ZSTD)
+ case IH_COMP_ZSTD:
+ {
+ int ret;
+ struct abuf in, out;
+
+ printf(" Uncompressing part %d ... ", part);
+
+ abuf_init_set(&in, (void *)data, len);
+ abuf_init_set(&out, (void *)dest, unc_len);
+ ret = zstd_decompress(&in, &out);
+ if (ret < 0) {
+ printf("ZSTD ERROR %d - "
+ "image not loaded\n", ret);
+ return 1;
+ }
+ len = ret;
+ }
+ break;
+#endif
default:
printf("Unimplemented compression type %d\n", comp);
return 1;
diff --git a/common/Kconfig b/common/Kconfig
index 5e3070e..4bb9f08 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -628,7 +628,7 @@
config CYCLIC_MAX_CPU_TIME_US
int "Sets the max allowed time for a cyclic function in us"
- default 1000
+ default 5000
help
The max allowed time for a cyclic function in us. If a functions
takes longer than this duration this function will get unregistered
diff --git a/common/board_r.c b/common/board_r.c
index c823cd2..d4ba245 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -230,8 +230,7 @@
oftree_reset();
- /* Save the pre-reloc driver model and start a new one */
- gd->dm_root_f = gd->dm_root;
+ /* Drop the pre-reloc driver model and start a new one */
gd->dm_root = NULL;
#ifdef CONFIG_TIMER
gd->timer = NULL;
diff --git a/common/button_cmd.c b/common/button_cmd.c
index 8642c26..72dac1f 100644
--- a/common/button_cmd.c
+++ b/common/button_cmd.c
@@ -8,7 +8,7 @@
#include <command.h>
#include <env.h>
#include <log.h>
-#include <vsprintf.h>
+#include <stdio.h>
/* Some sane limit "just in case" */
#define MAX_BTN_CMDS 32
diff --git a/common/cyclic.c b/common/cyclic.c
index a49bfc8..ec38fad 100644
--- a/common/cyclic.c
+++ b/common/cyclic.c
@@ -26,34 +26,22 @@
return (struct hlist_head *)&gd->cyclic_list;
}
-struct cyclic_info *cyclic_register(cyclic_func_t func, uint64_t delay_us,
- const char *name, void *ctx)
+void cyclic_register(struct cyclic_info *cyclic, cyclic_func_t func,
+ uint64_t delay_us, const char *name)
{
- struct cyclic_info *cyclic;
-
- cyclic = calloc(1, sizeof(struct cyclic_info));
- if (!cyclic) {
- pr_debug("Memory allocation error\n");
- return NULL;
- }
+ memset(cyclic, 0, sizeof(*cyclic));
/* Store values in struct */
cyclic->func = func;
- cyclic->ctx = ctx;
- cyclic->name = strdup(name);
+ cyclic->name = name;
cyclic->delay_us = delay_us;
cyclic->start_time_us = timer_get_us();
hlist_add_head(&cyclic->list, cyclic_get_list());
-
- return cyclic;
}
-int cyclic_unregister(struct cyclic_info *cyclic)
+void cyclic_unregister(struct cyclic_info *cyclic)
{
hlist_del(&cyclic->list);
- free(cyclic);
-
- return 0;
}
void cyclic_run(void)
@@ -76,7 +64,7 @@
if (time_after_eq64(now, cyclic->next_call)) {
/* Call cyclic function and account it's cpu-time */
cyclic->next_call = now + cyclic->delay_us;
- cyclic->func(cyclic->ctx);
+ cyclic->func(cyclic);
cyclic->run_cnt++;
cpu_time = timer_get_us() - now;
cyclic->cpu_time_us += cpu_time;
diff --git a/common/eeprom/eeprom_field.c b/common/eeprom/eeprom_field.c
index 3bacb1a..64b9db1 100644
--- a/common/eeprom/eeprom_field.c
+++ b/common/eeprom/eeprom_field.c
@@ -56,8 +56,8 @@
tmp[k] = value[reverse ? i - 1 + k : i + k];
}
- byte = simple_strtoul(tmp, &endptr, 0);
- if (*endptr != '\0' || byte < 0)
+ byte = simple_strtoul(tmp, &endptr, 16);
+ if (*endptr != '\0')
return -1;
field->buf[j] = byte;
diff --git a/common/eeprom/eeprom_layout.c b/common/eeprom/eeprom_layout.c
index 1a425c1..8c0b7e0 100644
--- a/common/eeprom/eeprom_layout.c
+++ b/common/eeprom/eeprom_layout.c
@@ -57,6 +57,28 @@
}
/*
+ * eeprom_layout_find_field() - finds a layout field by name
+ * @layout: A pointer to an existing struct layout.
+ * @field_name: The name of the field to update.
+ * @warn: Whether to print a warning if the field is not found.
+ *
+ * Returns: a pointer to the found field or NULL on failure.
+ */
+struct eeprom_field *eeprom_layout_find_field(struct eeprom_layout *layout,
+ char *field_name, bool warn)
+{
+ for (int i = 0; i < layout->num_of_fields; i++)
+ if (layout->fields[i].name != RESERVED_FIELDS &&
+ !strcmp(layout->fields[i].name, field_name))
+ return &layout->fields[i];
+
+ if (warn)
+ printf("No such field '%s'\n", field_name);
+
+ return NULL;
+}
+
+/*
* eeprom_layout_update_field() - update a single field in the layout data.
* @layout: A pointer to an existing struct layout.
* @field_name: The name of the field to update.
@@ -67,8 +89,8 @@
static int eeprom_layout_update_field(struct eeprom_layout *layout,
char *field_name, char *new_data)
{
- int i, err;
- struct eeprom_field *fields = layout->fields;
+ struct eeprom_field *field;
+ int err;
if (new_data == NULL)
return 0;
@@ -76,21 +98,15 @@
if (field_name == NULL)
return -1;
- for (i = 0; i < layout->num_of_fields; i++) {
- if (fields[i].name == RESERVED_FIELDS ||
- strcmp(fields[i].name, field_name))
- continue;
-
- err = fields[i].update(&fields[i], new_data);
- if (err)
- printf("Invalid data for field %s\n", field_name);
-
- return err;
- }
+ field = eeprom_layout_find_field(layout, field_name, true);
+ if (field == NULL)
+ return -1;
- printf("No such field '%s'\n", field_name);
+ err = field->update(field, new_data);
+ if (err)
+ printf("Invalid data for field %s\n", field_name);
- return -1;
+ return err;
}
/*
@@ -111,14 +127,14 @@
else
layout->layout_version = layout_version;
+ layout->data_size = buf_size;
+ layout->print = eeprom_layout_print;
+ layout->update = eeprom_layout_update_field;
+
eeprom_layout_assign(layout, layout_version);
layout->data = buf;
for (i = 0; i < layout->num_of_fields; i++) {
layout->fields[i].buf = buf;
buf += layout->fields[i].size;
}
-
- layout->data_size = buf_size;
- layout->print = eeprom_layout_print;
- layout->update = eeprom_layout_update_field;
}
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 6405374..af43b5f 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -272,6 +272,13 @@
help
The address in memory that SPL will be running from.
+config SPL_SOC_INIT
+ bool "Call SoC-specific initialization in SPL"
+ help
+ If this option is enabled, U-Boot will call the function
+ spl_soc_init() from board_init_r(). This function should be
+ provided by the SoC vendor.
+
config SPL_BOARD_INIT
bool "Call board-specific initialization in SPL"
help
@@ -409,6 +416,7 @@
depends on SPL_STACK_R && SPL_SYS_MALLOC_SIMPLE
hex "Size of malloc_simple heap after switching to DRAM SPL stack"
default 0x400000 if ARCH_K3 && ARM64
+ default 0x200000 if ARCH_K3 && CPU_V7R
default 0x100000
help
Specify the amount of the stack to use as memory pool for
@@ -1293,7 +1301,7 @@
config SPL_NVME
bool "NVM Express device support"
- depends on BLK
+ depends on SPL_BLK
select FS_LOADER
select SPL_BLK_FS
help
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 9a879e9..7794ddc 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -710,6 +710,9 @@
}
}
+ if (CONFIG_IS_ENABLED(SOC_INIT))
+ spl_soc_init();
+
if (CONFIG_IS_ENABLED(BOARD_INIT))
spl_board_init();
diff --git a/common/spl/spl_atf.c b/common/spl/spl_atf.c
index 0b1c981..0397b86 100644
--- a/common/spl/spl_atf.c
+++ b/common/spl/spl_atf.c
@@ -203,7 +203,8 @@
fdt_addr);
raw_write_daif(SPSR_EXCEPTION_MASK);
- dcache_disable();
+ if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+ dcache_disable();
atf_entry(bl31_params, (void *)fdt_addr);
}
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 988125b..2a097f4 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -587,7 +587,7 @@
static void warn_deprecated(const char *msg)
{
printf("DEPRECATED: %s\n", msg);
- printf("\tSee doc/uImage.FIT/source_file_format.txt\n");
+ printf("\tSee https://fitspec.osfw.foundation/\n");
}
static int spl_fit_upload_fpga(struct spl_fit_info *ctx, int node,
diff --git a/common/usb.c b/common/usb.c
index 84b10f5..f5b21c8 100644
--- a/common/usb.c
+++ b/common/usb.c
@@ -214,8 +214,9 @@
* clear keyboards LEDs). For data transfers, (storage transfers) we don't
* allow control messages with 0 timeout, by previousely resetting the flag
* asynch_allowed (usb_disable_asynch(1)).
- * returns the transferred length if OK or -1 if error. The transferred length
- * and the current status are stored in the dev->act_len and dev->status.
+ * returns the transferred length if OK, otherwise a negative error code. The
+ * transferred length and the current status are stored in the dev->act_len and
+ * dev->status.
*/
int usb_control_msg(struct usb_device *dev, unsigned int pipe,
unsigned char request, unsigned char requesttype,
@@ -257,11 +258,14 @@
break;
mdelay(1);
}
+
+ if (timeout == 0)
+ return -ETIMEDOUT;
+
if (dev->status)
return -1;
return dev->act_len;
-
}
/*-------------------------------------------------------------------
@@ -562,10 +566,29 @@
static int usb_get_descriptor(struct usb_device *dev, unsigned char type,
unsigned char index, void *buf, int size)
{
- return usb_control_msg(dev, usb_rcvctrlpipe(dev, 0),
- USB_REQ_GET_DESCRIPTOR, USB_DIR_IN,
- (type << 8) + index, 0, buf, size,
- USB_CNTL_TIMEOUT);
+ int i;
+ int result;
+
+ if (size <= 0) /* No point in asking for no data */
+ return -EINVAL;
+
+ memset(buf, 0, size); /* Make sure we parse really received data */
+
+ for (i = 0; i < 3; ++i) {
+ /* retry on length 0 or error; some devices are flakey */
+ result = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0),
+ USB_REQ_GET_DESCRIPTOR, USB_DIR_IN,
+ (type << 8) + index, 0, buf, size,
+ USB_CNTL_TIMEOUT);
+ if (result <= 0 && result != -ETIMEDOUT)
+ continue;
+ if (result > 1 && ((u8 *)buf)[1] != type) {
+ result = -ENODATA;
+ continue;
+ }
+ break;
+ }
+ return result;
}
/**********************************************************************
diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig
deleted file mode 100644
index d473a1a..0000000
--- a/configs/am335x_boneblack_vboot_defconfig
+++ /dev/null
@@ -1,94 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_CPU_INIT=y
-# CONFIG_SPL_USE_ARCH_MEMCPY is not set
-# CONFIG_SPL_USE_ARCH_MEMSET is not set
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
-CONFIG_SF_DEFAULT_SPEED=24000000
-CONFIG_DEFAULT_DEVICE_TREE="am335x-boneblack"
-CONFIG_AM33XX=y
-CONFIG_CLOCK_SYNTHESIZER=y
-CONFIG_SPL=y
-CONFIG_ENV_OFFSET_REDUND=0x280000
-CONFIG_TIMESTAMP=y
-CONFIG_FIT_SIGNATURE=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SYS_BOOTM_LEN=0x1000000
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
-CONFIG_AUTOBOOT_DELAY_STR="d"
-CONFIG_AUTOBOOT_STOP_STR=" "
-CONFIG_BOOTCOMMAND="run findfdt; run init_console; run finduuid; run distro_bootcmd"
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL_SYS_MALLOC=y
-CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
-CONFIG_SPL_MUSB_NEW=y
-# CONFIG_SPL_NAND_SUPPORT is not set
-CONFIG_SPL_NET=y
-CONFIG_SPL_NET_VCI_STRING="AM33xx U-Boot SPL"
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_FALCON_BOOT_MMCSD=y
-CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700
-CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500
-CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200
-CONFIG_CMD_SPL=y
-CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_BOOTP_DNS2=y
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SYS_MMC_ENV_DEV=1
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_NET_RETRY_COUNT=10
-CONFIG_BOOTP_SEND_HOSTNAME=y
-# CONFIG_SPL_BLK is not set
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_SYS_BOOTCOUNT_BE=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_RAM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_DM_I2C=y
-CONFIG_MISC=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x50
-# CONFIG_SPL_DM_MMC is not set
-CONFIG_MMC_OMAP_HS=y
-CONFIG_MTD=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_GIGE=y
-CONFIG_MII=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_DM_PMIC=y
-# CONFIG_SPL_DM_PMIC is not set
-CONFIG_PMIC_TPS65217=y
-CONFIG_SPL_POWER_TPS65910=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_TIMER=y
-CONFIG_OMAP_TIMER=y
-CONFIG_USB=y
-CONFIG_DM_USB_GADGET=y
-CONFIG_SPL_DM_USB_GADGET=y
-CONFIG_USB_MUSB_HOST=y
-CONFIG_USB_MUSB_GADGET=y
-CONFIG_USB_MUSB_TI=y
-CONFIG_USB_GADGET=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0451
-CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
-CONFIG_USB_ETHER=y
-CONFIG_SPL_USB_ETHER=y
-CONFIG_LZO=y
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index d243cb1..cabc181 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -13,6 +13,8 @@
CONFIG_AM335X_USB1=y
CONFIG_SPL=y
CONFIG_TIMESTAMP=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_DISTRO_DEFAULTS=y
@@ -119,5 +121,4 @@
CONFIG_WDT=y
# CONFIG_SPL_WDT is not set
CONFIG_DYNAMIC_CRC_TABLE=y
-CONFIG_RSA=y
CONFIG_LZO=y
diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index e1f0ab4..d73b1cb 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -74,6 +74,7 @@
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x180000
CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig
index ea5b69f..89e2125 100644
--- a/configs/am43xx_evm_qspiboot_defconfig
+++ b/configs/am43xx_evm_qspiboot_defconfig
@@ -50,6 +50,7 @@
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_POWER_TPS65218=y
diff --git a/configs/am43xx_evm_rtconly_defconfig b/configs/am43xx_evm_rtconly_defconfig
index 8941132..2ff0119 100644
--- a/configs/am43xx_evm_rtconly_defconfig
+++ b/configs/am43xx_evm_rtconly_defconfig
@@ -64,6 +64,7 @@
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x180000
CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index bf8cdba..845b686 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -77,6 +77,7 @@
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x180000
CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig
index 8a7a3df..ff5073c 100644
--- a/configs/am43xx_hs_evm_defconfig
+++ b/configs/am43xx_hs_evm_defconfig
@@ -70,6 +70,7 @@
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x180000
CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
diff --git a/configs/am43xx_hs_evm_qspi_defconfig b/configs/am43xx_hs_evm_qspi_defconfig
index ebfad6a..5ef59d8 100644
--- a/configs/am43xx_hs_evm_qspi_defconfig
+++ b/configs/am43xx_hs_evm_qspi_defconfig
@@ -51,6 +51,7 @@
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_POWER_TPS65218=y
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index bfa78f0..7c3ceeb 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -94,6 +94,7 @@
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_MII=y
diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index 7be94ae..1f7eca4 100644
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -90,6 +90,7 @@
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_MII=y
diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig
index 055e29b..807e1d6 100644
--- a/configs/am57xx_hs_evm_usb_defconfig
+++ b/configs/am57xx_hs_evm_usb_defconfig
@@ -88,6 +88,7 @@
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_MII=y
diff --git a/configs/am62ax_evm_a53_defconfig b/configs/am62ax_evm_a53_defconfig
index 6b29a4b..2a71b06 100644
--- a/configs/am62ax_evm_a53_defconfig
+++ b/configs/am62ax_evm_a53_defconfig
@@ -8,7 +8,7 @@
CONFIG_TARGET_AM62A7_A53_EVM=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
-CONFIG_DEFAULT_DEVICE_TREE="k3-am62a7-sk"
+CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am62a7-sk"
CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
@@ -39,6 +39,7 @@
CONFIG_CMD_MMC=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
CONFIG_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
diff --git a/configs/am62px_evm_a53_defconfig b/configs/am62px_evm_a53_defconfig
index 9f40c9a..e1c9c85 100644
--- a/configs/am62px_evm_a53_defconfig
+++ b/configs/am62px_evm_a53_defconfig
@@ -179,3 +179,5 @@
CONFIG_SPL_DFU=y
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
CONFIG_EFI_SET_TIME=y
+
+#include <configs/k3_efi_capsule.config>
diff --git a/configs/am62px_evm_r5_defconfig b/configs/am62px_evm_r5_defconfig
index b365c7e..ace5569 100644
--- a/configs/am62px_evm_r5_defconfig
+++ b/configs/am62px_evm_r5_defconfig
@@ -23,7 +23,6 @@
CONFIG_SPL_BSS_START_ADDR=0x43c4b000
CONFIG_SPL_BSS_MAX_SIZE=0x3000
CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000
CONFIG_SPL_SIZE_LIMIT=0x3C000
CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x5000
CONFIG_SPL_FS_FAT=y
diff --git a/configs/am62x_beagleplay_a53_defconfig b/configs/am62x_beagleplay_a53_defconfig
index ec62670..79c82d1 100644
--- a/configs/am62x_beagleplay_a53_defconfig
+++ b/configs/am62x_beagleplay_a53_defconfig
@@ -10,7 +10,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80b80000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="k3-am625-beagleplay"
+CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am625-beagleplay"
CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
@@ -58,6 +58,7 @@
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
CONFIG_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
@@ -70,6 +71,9 @@
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CLK_TI_SCI=y
+CONFIG_DFU_MMC=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x180000
CONFIG_DMA_CHANNELS=y
CONFIG_TI_K3_NAVSS_UDMA=y
CONFIG_TI_SCI_PROTOCOL=y
@@ -122,4 +126,5 @@
CONFIG_LZO=y
CONFIG_EFI_SET_TIME=y
+#include <configs/k3_efi_capsule.config>
#include <configs/am62x_a53_usbdfu.config>
diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig
index 16294a6..ca993b4 100644
--- a/configs/am62x_evm_a53_defconfig
+++ b/configs/am62x_evm_a53_defconfig
@@ -10,7 +10,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80b80000
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="k3-am625-sk"
+CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am625-sk"
CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
@@ -56,6 +56,7 @@
CONFIG_MMC_SPEED_MODE_SET=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
CONFIG_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
@@ -113,4 +114,5 @@
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
CONFIG_EFI_SET_TIME=y
+#include <configs/k3_efi_capsule.config>
#include <configs/am62x_a53_usbdfu.config>
diff --git a/configs/am62x_evm_r5_defconfig b/configs/am62x_evm_r5_defconfig
index 6482414..4b2e57b 100644
--- a/configs/am62x_evm_r5_defconfig
+++ b/configs/am62x_evm_r5_defconfig
@@ -26,7 +26,6 @@
CONFIG_SPL_BSS_START_ADDR=0x43c3b000
CONFIG_SPL_BSS_MAX_SIZE=0x3000
CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000
CONFIG_SPL_SIZE_LIMIT=0x3A7F0
CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x3500
CONFIG_SPL_FS_FAT=y
diff --git a/configs/am62x_lpsk_a53_defconfig b/configs/am62x_lpsk_a53_defconfig
new file mode 100644
index 0000000..a86bfb5
--- /dev/null
+++ b/configs/am62x_lpsk_a53_defconfig
@@ -0,0 +1,8 @@
+#include <configs/am62x_evm_a53_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am62-lp-sk"
+CONFIG_OF_UPSTREAM=y
+CONFIG_SOC_K3_AM625=y
+CONFIG_TARGET_AM625_A53_EVM=y
diff --git a/configs/am62x_lpsk_r5_defconfig b/configs/am62x_lpsk_r5_defconfig
new file mode 100644
index 0000000..9112bc2
--- /dev/null
+++ b/configs/am62x_lpsk_r5_defconfig
@@ -0,0 +1,7 @@
+#include <configs/am62x_evm_r5_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-am62-r5-lp-sk"
+CONFIG_SOC_K3_AM625=y
+CONFIG_TARGET_AM625_R5_EVM=y
diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig
index e000549..5b01002 100644
--- a/configs/am64x_evm_a53_defconfig
+++ b/configs/am64x_evm_a53_defconfig
@@ -103,7 +103,11 @@
CONFIG_DMA_CHANNELS=y
CONFIG_TI_K3_NAVSS_UDMA=y
CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DM_PCA953X=y
+CONFIG_SPL_DM_PCA953X=y
CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_DM_I2C_GPIO=y
CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
@@ -126,8 +130,10 @@
CONFIG_MULTIPLEXER=y
CONFIG_MUX_MMIO=y
CONFIG_PHY_TI_DP83867=y
+CONFIG_PHY_TI_DP83869=y
CONFIG_PHY_FIXED=y
CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_TI_ICSSG_PRUETH=y
CONFIG_PHY=y
CONFIG_SPL_PHY=y
CONFIG_PHY_CADENCE_TORRENT=y
@@ -143,6 +149,8 @@
CONFIG_DM_REGULATOR_TPS65219=y
CONFIG_K3_SYSTEM_CONTROLLER=y
CONFIG_REMOTEPROC_TI_K3_ARM64=y
+CONFIG_REMOTEPROC_TI_PRU=y
+CONFIG_CMD_REMOTEPROC=y
CONFIG_RESET_TI_SCI=y
CONFIG_DM_RTC=y
CONFIG_RTC_EMULATION=y
@@ -150,6 +158,7 @@
CONFIG_SOC_DEVICE=y
CONFIG_SOC_DEVICE_TI_K3=y
CONFIG_SOC_TI=y
+CONFIG_TI_PRUSS=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
@@ -178,3 +187,5 @@
CONFIG_SPL_DFU=y
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
CONFIG_EFI_SET_TIME=y
+
+#include <configs/k3_efi_capsule.config>
diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig
index ee79ade..925a88e 100644
--- a/configs/am65x_evm_a53_defconfig
+++ b/configs/am65x_evm_a53_defconfig
@@ -16,7 +16,6 @@
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am654-base-board"
CONFIG_SPL_TEXT_BASE=0x80080000
-CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
@@ -36,6 +35,7 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
+CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run boot_rprocs; if test ${boot_fit} -eq 1; then run get_fit_${boot}; run get_overlaystring; run run_fit; else; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern; fi;"
@@ -68,7 +68,6 @@
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_REMOTEPROC=y
-CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY=y
CONFIG_CMD_USB=y
CONFIG_CMD_TIME=y
CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0"
diff --git a/configs/amd_versal2_virt_defconfig b/configs/amd_versal2_virt_defconfig
new file mode 100644
index 0000000..2d611f8
--- /dev/null
+++ b/configs/amd_versal2_virt_defconfig
@@ -0,0 +1,151 @@
+CONFIG_ARM=y
+CONFIG_COUNTER_FREQUENCY=375000
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_SYS_INIT_SP_BSS_OFFSET=1572864
+CONFIG_ARCH_VERSAL2=y
+CONFIG_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_F_LEN=0x100000
+CONFIG_DEFAULT_DEVICE_TREE="amd-versal2-virt"
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_BASE=0xf1920000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_CMD_FRU=y
+CONFIG_SYS_LOAD_ADDR=0x8000000
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_MEMTEST_START=0x00000000
+CONFIG_SYS_MEMTEST_END=0x00001000
+CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_BOOTM_LEN=0x6400000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTDELAY=5
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=2073
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_CLOCKS=y
+CONFIG_SYS_PROMPT="versal2> "
+CONFIG_CMD_BOOTMENU=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_SHA1SUM=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_UFS=y
+CONFIG_CMD_USB=y
+CONFIG_BOOTP_MAY_FAIL=y
+CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_RNG=y
+CONFIG_CMD_KASLRSEED=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_SMC=y
+CONFIG_CMD_TPM=y
+CONFIG_CMD_SCMI=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SQUASHFS=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_UBI=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_BOARD=y
+CONFIG_DTB_RESELECT=y
+CONFIG_MULTI_DTB_FIT=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+CONFIG_IP_DEFRAG=y
+CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
+CONFIG_TFTP_BLOCKSIZE=4096
+CONFIG_CLK_CCF=y
+CONFIG_CLK_SCMI=y
+CONFIG_DFU_RAM=y
+CONFIG_ARM_FFA_TRANSPORT=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_DM_MAILBOX=y
+CONFIG_ZYNQMP_IPI=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_ZYNQ_SDHCI_MIN_FREQ=100000
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TI_DP83867=y
+CONFIG_PHY_VITESSE=y
+CONFIG_PHY_FIXED=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_XILINX_AXIEMAC=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_RESET_SCMI=y
+CONFIG_SCSI=y
+CONFIG_DEBUG_UART_PL011=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_ARM_DCC=y
+CONFIG_PL01X_SERIAL=y
+CONFIG_XILINX_UARTLITE=y
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_AMD_VERSAL2=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_CADENCE_OSPI_VERSAL=y
+CONFIG_ZYNQ_SPI=y
+CONFIG_ZYNQMP_GQSPI=y
+CONFIG_TPM2_TIS_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
+CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_THOR=y
+CONFIG_UFS=y
+CONFIG_CADENCE_UFS=y
+CONFIG_VIRTIO_MMIO=y
+CONFIG_VIRTIO_NET=y
+CONFIG_VIRTIO_BLK=y
+CONFIG_TPM=y
diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig
index e8dc60c..6d70cc2 100644
--- a/configs/apalis_imx6_defconfig
+++ b/configs/apalis_imx6_defconfig
@@ -99,6 +99,7 @@
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
+CONFIG_PHY_ANEG_TIMEOUT=15000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_FEC_MXC=y
diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig
index acfe393..b2ecfa6 100644
--- a/configs/chromebook_bob_defconfig
+++ b/configs/chromebook_bob_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00200000
diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig
index 95fdb41..0fba591 100644
--- a/configs/chromebook_kevin_defconfig
+++ b/configs/chromebook_kevin_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00200000
diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig
index 7cf23b2..9583f87 100644
--- a/configs/chromebook_link64_defconfig
+++ b/configs/chromebook_link64_defconfig
@@ -80,6 +80,7 @@
CONFIG_SYS_NS16550_PORT_MAPPED=y
CONFIG_SPI=y
CONFIG_TPM_TIS_LPC=y
+# CONFIG_TPM_V2 is not set
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig
index a9f91dd..637b888 100644
--- a/configs/chromebook_link_defconfig
+++ b/configs/chromebook_link_defconfig
@@ -15,6 +15,8 @@
CONFIG_HAVE_MRC=y
CONFIG_SMP=y
CONFIG_HAVE_VGA_BIOS=y
+CONFIG_HAS_BOARD_SIZE_LIMIT=y
+CONFIG_BOARD_SIZE_LIMIT=630000
CONFIG_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
@@ -70,6 +72,7 @@
CONFIG_SOUND=y
CONFIG_SPI=y
CONFIG_TPM_TIS_LPC=y
+# CONFIG_TPM_V2 is not set
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_VIDEO_COPY=y
@@ -78,5 +81,6 @@
CONFIG_VIDEO_IVYBRIDGE_IGD=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_TPM=y
+# CONFIG_SHA256 is not set
# CONFIG_GZIP is not set
# CONFIG_EFI_LOADER is not set
diff --git a/configs/chromebook_samus_defconfig b/configs/chromebook_samus_defconfig
index 40cc449..8cdad8d 100644
--- a/configs/chromebook_samus_defconfig
+++ b/configs/chromebook_samus_defconfig
@@ -74,6 +74,7 @@
CONFIG_SOUND_RT5677=y
CONFIG_SPI=y
CONFIG_TPM_TIS_LPC=y
+# CONFIG_TPM_V2 is not set
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_VIDEO_COPY=y
diff --git a/configs/chromebook_samus_tpl_defconfig b/configs/chromebook_samus_tpl_defconfig
index 3e7298f..1be5756 100644
--- a/configs/chromebook_samus_tpl_defconfig
+++ b/configs/chromebook_samus_tpl_defconfig
@@ -96,6 +96,7 @@
CONFIG_SPI=y
CONFIG_TPL_SYSRESET=y
CONFIG_TPM_TIS_LPC=y
+# CONFIG_TPM_V2 is not set
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig
index 9bbc723..62dbf2a 100644
--- a/configs/clearfog_defconfig
+++ b/configs/clearfog_defconfig
@@ -64,6 +64,7 @@
CONFIG_SF_DEFAULT_BUS=1
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
diff --git a/configs/clearfog_sata_defconfig b/configs/clearfog_sata_defconfig
index 9ddd5d2..41382f9 100644
--- a/configs/clearfog_sata_defconfig
+++ b/configs/clearfog_sata_defconfig
@@ -65,6 +65,7 @@
CONFIG_SF_DEFAULT_BUS=1
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
diff --git a/configs/clearfog_spi_defconfig b/configs/clearfog_spi_defconfig
index 4175fdb17..f345b12 100644
--- a/configs/clearfog_spi_defconfig
+++ b/configs/clearfog_spi_defconfig
@@ -65,6 +65,7 @@
CONFIG_SF_DEFAULT_BUS=1
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig
index a4d5f91..386616c 100644
--- a/configs/cm_fx6_defconfig
+++ b/configs/cm_fx6_defconfig
@@ -46,6 +46,7 @@
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_EEPROM_LAYOUT=y
+CONFIG_EEPROM_LAYOUT_VERSIONS=y
CONFIG_EEPROM_LAYOUT_HELP_STRING="v2, v3"
CONFIG_SYS_I2C_EEPROM_BUS=2
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig
index 93e6672..32f126a 100644
--- a/configs/cm_t43_defconfig
+++ b/configs/cm_t43_defconfig
@@ -50,6 +50,7 @@
CONFIG_CMD_ASKENV=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_EEPROM_LAYOUT=y
+CONFIG_EEPROM_LAYOUT_VERSIONS=y
CONFIG_EEPROM_LAYOUT_HELP_STRING="v2, v3"
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
diff --git a/configs/controlcenterdc_defconfig b/configs/controlcenterdc_defconfig
index cf7499b..6fe9750 100644
--- a/configs/controlcenterdc_defconfig
+++ b/configs/controlcenterdc_defconfig
@@ -85,6 +85,7 @@
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig
index 8b2f77f..ab4e0fe 100644
--- a/configs/corstone1000_defconfig
+++ b/configs/corstone1000_defconfig
@@ -68,3 +68,4 @@
CONFIG_EFI_CAPSULE_ON_DISK=y
CONFIG_EFI_IGNORE_OSINDICATIONS=y
CONFIG_FWU_MULTI_BANK_UPDATE=y
+CONFIG_FWU_MDATA_V1=y
diff --git a/configs/cortina_presidio-asic-base_defconfig b/configs/cortina_presidio-asic-base_defconfig
index 8f20f65..eb5743d 100644
--- a/configs/cortina_presidio-asic-base_defconfig
+++ b/configs/cortina_presidio-asic-base_defconfig
@@ -38,3 +38,4 @@
CONFIG_CORTINA_UART=y
CONFIG_WDT=y
CONFIG_WDT_CORTINA=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/cortina_presidio-asic-pnand_defconfig b/configs/cortina_presidio-asic-pnand_defconfig
index 94dc3e1..c7367d4 100644
--- a/configs/cortina_presidio-asic-pnand_defconfig
+++ b/configs/cortina_presidio-asic-pnand_defconfig
@@ -43,3 +43,4 @@
CONFIG_CORTINA_UART=y
CONFIG_WDT=y
CONFIG_WDT_CORTINA=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/crs305-1g-4s-bit_defconfig b/configs/crs305-1g-4s-bit_defconfig
index a8f1757..c3d4594 100644
--- a/configs/crs305-1g-4s-bit_defconfig
+++ b/configs/crs305-1g-4s-bit_defconfig
@@ -47,3 +47,4 @@
CONFIG_PCI_MVEBU=y
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD_SPI=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/crs305-1g-4s_defconfig b/configs/crs305-1g-4s_defconfig
index c66d291..1919e8c 100644
--- a/configs/crs305-1g-4s_defconfig
+++ b/configs/crs305-1g-4s_defconfig
@@ -48,3 +48,4 @@
CONFIG_PCI_MVEBU=y
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD_SPI=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/crs326-24g-2s-bit_defconfig b/configs/crs326-24g-2s-bit_defconfig
index b754dac..a584c26 100644
--- a/configs/crs326-24g-2s-bit_defconfig
+++ b/configs/crs326-24g-2s-bit_defconfig
@@ -47,3 +47,4 @@
CONFIG_PCI_MVEBU=y
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD_SPI=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/crs326-24g-2s_defconfig b/configs/crs326-24g-2s_defconfig
index 870127d..43f7455 100644
--- a/configs/crs326-24g-2s_defconfig
+++ b/configs/crs326-24g-2s_defconfig
@@ -47,3 +47,4 @@
CONFIG_PCI_MVEBU=y
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD_SPI=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/crs328-4c-20s-4s-bit_defconfig b/configs/crs328-4c-20s-4s-bit_defconfig
index 2373775..7bf6716 100644
--- a/configs/crs328-4c-20s-4s-bit_defconfig
+++ b/configs/crs328-4c-20s-4s-bit_defconfig
@@ -47,3 +47,4 @@
CONFIG_PCI_MVEBU=y
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD_SPI=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/crs328-4c-20s-4s_defconfig b/configs/crs328-4c-20s-4s_defconfig
index 9bac122..2f50bda 100644
--- a/configs/crs328-4c-20s-4s_defconfig
+++ b/configs/crs328-4c-20s-4s_defconfig
@@ -47,3 +47,4 @@
CONFIG_PCI_MVEBU=y
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD_SPI=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/db-88f6720_defconfig b/configs/db-88f6720_defconfig
index 33b8b80..22a1e83 100644
--- a/configs/db-88f6720_defconfig
+++ b/configs/db-88f6720_defconfig
@@ -64,6 +64,7 @@
# CONFIG_MMC is not set
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVPP2=y
diff --git a/configs/db-88f6820-amc_defconfig b/configs/db-88f6820-amc_defconfig
index 540a348..a6c8622 100644
--- a/configs/db-88f6820-amc_defconfig
+++ b/configs/db-88f6820-amc_defconfig
@@ -71,6 +71,7 @@
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
diff --git a/configs/db-88f6820-amc_nand_defconfig b/configs/db-88f6820-amc_nand_defconfig
index 4d4cf36..5445782 100644
--- a/configs/db-88f6820-amc_nand_defconfig
+++ b/configs/db-88f6820-amc_nand_defconfig
@@ -75,6 +75,7 @@
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig
index 4f98ee4..ee8cb8a 100644
--- a/configs/db-88f6820-gp_defconfig
+++ b/configs/db-88f6820-gp_defconfig
@@ -68,6 +68,7 @@
CONFIG_MMC_SDHCI_MV=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
diff --git a/configs/db-mv784mp-gp_defconfig b/configs/db-mv784mp-gp_defconfig
index d776693..f10a6fb 100644
--- a/configs/db-mv784mp-gp_defconfig
+++ b/configs/db-mv784mp-gp_defconfig
@@ -70,6 +70,7 @@
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
diff --git a/configs/ds116_defconfig b/configs/ds116_defconfig
index 1fc7380..56bd56b 100644
--- a/configs/ds116_defconfig
+++ b/configs/ds116_defconfig
@@ -71,6 +71,7 @@
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
diff --git a/configs/ds414_defconfig b/configs/ds414_defconfig
index ecf9501..18c741d 100644
--- a/configs/ds414_defconfig
+++ b/configs/ds414_defconfig
@@ -68,6 +68,7 @@
# CONFIG_MMC is not set
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ANEG_TIMEOUT=16000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
diff --git a/configs/e850-96_defconfig b/configs/e850-96_defconfig
index bb41635..38b9968 100644
--- a/configs/e850-96_defconfig
+++ b/configs/e850-96_defconfig
@@ -7,7 +7,7 @@
CONFIG_ARCH_EXYNOS9=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xf8c00000
-CONFIG_DEFAULT_DEVICE_TREE="exynos850-e850-96"
+CONFIG_DEFAULT_DEVICE_TREE="exynos/exynos850-e850-96"
CONFIG_SYS_LOAD_ADDR=0x80000000
# CONFIG_AUTOBOOT is not set
# CONFIG_DISPLAY_CPUINFO is not set
diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig
index 07c56a4..488a259 100644
--- a/configs/evb-px30_defconfig
+++ b/configs/evb-px30_defconfig
@@ -2,28 +2,15 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000
-CONFIG_DEFAULT_DEVICE_TREE="px30-evb"
-CONFIG_SPL_TEXT_BASE=0x00000000
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/px30-evb"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_PX30=y
+# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set
CONFIG_TARGET_EVB_PX30=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
+# CONFIG_TPL_LIBCOMMON_SUPPORT is not set
CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
-CONFIG_SPL_STACK_R_ADDR=0x600000
-CONFIG_SPL_STACK=0x400000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
-CONFIG_SPL_STACK_R=y
-CONFIG_DEBUG_UART_BASE=0xFF160000
+CONFIG_DEBUG_UART_BASE=0xff178000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
@@ -40,9 +27,9 @@
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_ATF=y
# CONFIG_TPL_FRAMEWORK is not set
+# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set
# CONFIG_TPL_BANNER_PRINT is not set
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_ELF is not set
@@ -64,7 +51,7 @@
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_REGMAP=y
diff --git a/configs/firefly-px30_defconfig b/configs/firefly-px30_defconfig
index e5377dc..3fe1dc3 100644
--- a/configs/firefly-px30_defconfig
+++ b/configs/firefly-px30_defconfig
@@ -2,28 +2,15 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000
CONFIG_DEFAULT_DEVICE_TREE="px30-firefly"
-CONFIG_SPL_TEXT_BASE=0x00000000
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_PX30=y
+# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set
CONFIG_TARGET_EVB_PX30=y
CONFIG_DEBUG_UART_CHANNEL=1
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
+# CONFIG_TPL_LIBCOMMON_SUPPORT is not set
CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
-CONFIG_SPL_STACK_R_ADDR=0x600000
-CONFIG_SPL_STACK=0x400000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
-CONFIG_SPL_STACK_R=y
CONFIG_DEBUG_UART_BASE=0xFF160000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
@@ -41,9 +28,9 @@
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_ATF=y
# CONFIG_TPL_FRAMEWORK is not set
+# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set
# CONFIG_TPL_BANNER_PRINT is not set
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_ELF is not set
@@ -65,6 +52,7 @@
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
+# CONFIG_OF_UPSTREAM is not set
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
diff --git a/configs/gxp_defconfig b/configs/gxp_defconfig
index 00a9211..d37749b 100644
--- a/configs/gxp_defconfig
+++ b/configs/gxp_defconfig
@@ -59,3 +59,4 @@
CONFIG_GXP_TIMER=y
# CONFIG_RANDOM_UUID is not set
CONFIG_SHA512=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/helios4_defconfig b/configs/helios4_defconfig
index c4c5d48..29b6230 100644
--- a/configs/helios4_defconfig
+++ b/configs/helios4_defconfig
@@ -64,6 +64,7 @@
CONFIG_SF_DEFAULT_BUS=1
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
diff --git a/configs/hihope_rzg2_defconfig b/configs/hihope_rzg2_defconfig
index 149ce0b..fc412d0 100644
--- a/configs/hihope_rzg2_defconfig
+++ b/configs/hihope_rzg2_defconfig
@@ -68,6 +68,7 @@
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_REALTEK=y
CONFIG_RENESAS_RAVB=y
CONFIG_DM_REGULATOR=y
diff --git a/configs/hmibsc_defconfig b/configs/hmibsc_defconfig
index a076898..86ca4f8 100644
--- a/configs/hmibsc_defconfig
+++ b/configs/hmibsc_defconfig
@@ -10,44 +10,42 @@
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x0
CONFIG_DEFAULT_DEVICE_TREE="apq8016-schneider-hmibsc"
-# CONFIG_OF_UPSTREAM is not set
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_IDENT_STRING="\nSchneider Electric-HMIBSC"
CONFIG_SYS_LOAD_ADDR=0x80080000
CONFIG_REMAKE_ELF=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_CBSIZE=2048
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="hmibsc => "
-CONFIG_SYS_MAXARGS=64
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_FS_GENERIC=y
# CONFIG_CMD_IMI is not set
+CONFIG_CMD_ENV_FLAGS=y
+CONFIG_CMD_NVEDIT_INFO=y
CONFIG_CMD_MD5SUM=y
CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIMER=y
-CONFIG_CMD_ENV_FLAGS=y
-CONFIG_CMD_ENV_EXISTS=y
-CONFIG_CMD_NVEDIT_INFO=y
-CONFIG_ENV_WRITEABLE_LIST=y
-CONFIG_ENV_ACCESS_IGNORE_FORCE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+# CONFIG_OF_UPSTREAM is not set
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=2
+CONFIG_ENV_WRITEABLE_LIST=y
+CONFIG_ENV_ACCESS_IGNORE_FORCE=y
CONFIG_BUTTON_QCOM_PMIC=y
CONFIG_CLK=y
CONFIG_CLK_QCOM_APQ8016=y
@@ -61,6 +59,8 @@
CONFIG_LED_GPIO=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_MSM=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
@@ -77,10 +77,9 @@
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_LAN75XX=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_PHYLIB=y
-CONFIG_USB_ETHER_LAN75XX=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_VENDOR_NUM=0x18d1
CONFIG_USB_GADGET_PRODUCT_NUM=0xd00d
diff --git a/configs/ideapad-yoga-11_defconfig b/configs/ideapad-yoga-11_defconfig
new file mode 100644
index 0000000..25624c6
--- /dev/null
+++ b/configs/ideapad-yoga-11_defconfig
@@ -0,0 +1,84 @@
+CONFIG_ARM=y
+CONFIG_ARCH_TEGRA=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_CMDLINE_TAG=y
+CONFIG_INITRD_TAG=y
+CONFIG_TEXT_BASE=0x80110000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SIZE=0x3000
+CONFIG_ENV_OFFSET=0xFFFFD000
+CONFIG_DEFAULT_DEVICE_TREE="tegra30-lenovo-ideapad-yoga-11"
+CONFIG_SPL_TEXT_BASE=0x80108000
+CONFIG_SPL_STACK=0x800ffffc
+CONFIG_TEGRA30=y
+CONFIG_TARGET_IDEAPAD_YOGA_11=y
+CONFIG_CMD_EBTUPDATE=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_BUTTON_CMD=y
+CONFIG_BOOTDELAY=0
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_KEYED_CTRLC=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_PBSIZE=2084
+CONFIG_SPL_FOOTPRINT_LIMIT=y
+CONFIG_SPL_MAX_FOOTPRINT=0x8000
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
+CONFIG_SYS_PROMPT="Tegra30 (Ideapad Yoga 11) # "
+# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
+CONFIG_CMD_BOOTMENU=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_UMS_ABORT_KEYED=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PAUSE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_PART=2
+CONFIG_BUTTON=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x91000000
+CONFIG_FASTBOOT_BUF_SIZE=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_SYS_I2C_TEGRA=y
+CONFIG_BUTTON_KEYBOARD=y
+CONFIG_TEGRA_KEYBOARD=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_TPS65910=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_TPS65911=y
+CONFIG_PWM_TEGRA=y
+CONFIG_SYS_NS16550=y
+CONFIG_TEGRA20_SLINK=y
+CONFIG_SYSRESET_TPS65910=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_LOGO is not set
+CONFIG_VIDEO_BRIDGE_PARADE_DP501=y
+CONFIG_VIDEO_TEGRA20=y
diff --git a/configs/igep00x0_defconfig b/configs/igep00x0_defconfig
index 261f71a..4738916 100644
--- a/configs/igep00x0_defconfig
+++ b/configs/igep00x0_defconfig
@@ -1,15 +1,18 @@
CONFIG_ARM=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SYS_MALLOC_F_LEN=0x400
+CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00
CONFIG_ENV_SIZE=0x8000
-CONFIG_DEFAULT_DEVICE_TREE="omap3-igep0020"
+CONFIG_DEFAULT_DEVICE_TREE="ti/omap/omap3-igep0020"
CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_TARGET_OMAP3_IGEP00X0=y
CONFIG_SYS_MONITOR_LEN=262144
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
@@ -39,16 +42,7 @@
CONFIG_SPL_UBI_INFO_ADDR=0x88080000
CONFIG_SPL_UBI_VOL_IDS=8
CONFIG_SPL_UBI_LOAD_MONITOR_ID=0
-CONFIG_SPL_UBI_LOAD_KERNEL_ID=3
-CONFIG_SPL_UBI_LOAD_ARGS_ID=4
CONFIG_SPL_ONENAND_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x84000000
-CONFIG_SYS_NAND_SPL_KERNEL_OFFS=0x280000
-CONFIG_SPL_FALCON_BOOT_MMCSD=y
-CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700
-CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500
-CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200
CONFIG_CMD_SPL=y
CONFIG_CMD_NAND=y
CONFIG_CMD_ONENAND=y
@@ -58,7 +52,12 @@
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_UBI=y
# CONFIG_CMD_UBIFS is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SPL_PARTITION_UUIDS=y
CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
+CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent"
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_UBI=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
@@ -68,8 +67,9 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_NET is not set
-CONFIG_SYS_I2C_LEGACY=y
-CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SPL_DM=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_SYS_MTDPARTS_RUNTIME=y
@@ -80,8 +80,6 @@
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_CONS_INDEX=3
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_OMAP3_SPI=y
CONFIG_BCH=y
diff --git a/configs/imx6ulz_smm_m2_defconfig b/configs/imx6ulz_smm_m2_defconfig
index 064758c..93ead4c 100644
--- a/configs/imx6ulz_smm_m2_defconfig
+++ b/configs/imx6ulz_smm_m2_defconfig
@@ -11,7 +11,7 @@
CONFIG_ENV_OFFSET=0x400000
CONFIG_MX6ULL=y
CONFIG_TARGET_MX6ULZ_SMM_M2=y
-CONFIG_DEFAULT_DEVICE_TREE="imx6ulz-bsh-smm-m2"
+CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6ulz-bsh-smm-m2"
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_SERIAL=y
CONFIG_SPL_BSS_START_ADDR=0x84100000
diff --git a/configs/imx8mm-mx8menlo_defconfig b/configs/imx8mm-mx8menlo_defconfig
index e9b18ac..5e6bbb3 100644
--- a/configs/imx8mm-mx8menlo_defconfig
+++ b/configs/imx8mm-mx8menlo_defconfig
@@ -25,15 +25,19 @@
CONFIG_SPL=y
CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
CONFIG_ENV_OFFSET_REDUND=0xFFFFDE00
+CONFIG_IMX_BOOTAUX=y
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_SYS_MEMTEST_START=0x40000000
CONFIG_SYS_MEMTEST_END=0x80000000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTDELAY=1
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTCOMMAND="mmc partconf 0 distro_bootpart && load ${devtype} ${devnum}:${distro_bootpart} ${loadaddr} boot/fitImage && source ${loadaddr}:bootscr-boot.cmd ; reset"
+CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="imx8mm-mx8menlo.dtb"
CONFIG_SYS_CBSIZE=2048
CONFIG_SYS_PBSIZE=2081
@@ -57,19 +61,26 @@
# CONFIG_BOOTM_NETBSD is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_EXPORTENV is not set
-# CONFIG_CMD_CRC32 is not set
+CONFIG_CRC32_VERIFY=y
+CONFIG_CMD_MD5SUM=y
+CONFIG_MD5SUM_VERIFY=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_READ=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_SDP=y
CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_CAT=y
+CONFIG_CMD_XXD=y
CONFIG_CMD_BOOTCOUNT=y
CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
CONFIG_CMD_UUID=y
+CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_BTRFS=y
CONFIG_CMD_EXT4_WRITE=y
@@ -84,8 +95,9 @@
CONFIG_SYS_MMC_ENV_PART=1
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="FEC"
+CONFIG_ETHPRIME="eth0"
CONFIG_VERSION_VARIABLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_BLOCKSIZE=4096
CONFIG_SPL_DM=y
@@ -96,16 +108,27 @@
CONFIG_SPL_CLK_IMX8MM=y
CONFIG_CLK_IMX8MM=y
CONFIG_GPIO_HOG=y
+CONFIG_SPL_GPIO_HOG=y
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_SPL_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_SPL_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_PHY_FIXED=y
+CONFIG_DM_MDIO=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_SPL_PHY=y
@@ -128,6 +151,7 @@
CONFIG_SYSRESET_PSCI=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
CONFIG_USB=y
CONFIG_SPL_USB_HOST=y
CONFIG_USB_EHCI_HCD=y
@@ -143,3 +167,4 @@
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_IMX_WATCHDOG=y
+CONFIG_HEXDUMP=y
diff --git a/configs/imx8mm-phygate-tauri-l_defconfig b/configs/imx8mm-phygate-tauri-l_defconfig
index cb292dd..41765f1 100644
--- a/configs/imx8mm-phygate-tauri-l_defconfig
+++ b/configs/imx8mm-phygate-tauri-l_defconfig
@@ -8,7 +8,7 @@
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x3C0000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mm-phygate-tauri-l"
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-phygate-tauri-l"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_PHYCORE_IMX8MM=y
CONFIG_SYS_MONITOR_LEN=524288
diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig b/configs/imx8mm_data_modul_edm_sbc_defconfig
index 53249f4..f26a879 100644
--- a/configs/imx8mm_data_modul_edm_sbc_defconfig
+++ b/configs/imx8mm_data_modul_edm_sbc_defconfig
@@ -193,6 +193,7 @@
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHYLIB=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_DM_MDIO=y
diff --git a/configs/imx8mn_bsh_smm_s2_defconfig b/configs/imx8mn_bsh_smm_s2_defconfig
index 0e0a548..b4351a3 100644
--- a/configs/imx8mn_bsh_smm_s2_defconfig
+++ b/configs/imx8mn_bsh_smm_s2_defconfig
@@ -8,7 +8,7 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mn-bsh-smm-s2"
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mn-bsh-smm-s2"
CONFIG_SPL_TEXT_BASE=0x912000
CONFIG_TARGET_IMX8MN_BSH_SMM_S2=y
CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/imx8mn_bsh_smm_s2pro_defconfig b/configs/imx8mn_bsh_smm_s2pro_defconfig
index f739569..0faa337 100644
--- a/configs/imx8mn_bsh_smm_s2pro_defconfig
+++ b/configs/imx8mn_bsh_smm_s2pro_defconfig
@@ -8,7 +8,7 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mn-bsh-smm-s2pro"
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mn-bsh-smm-s2pro"
CONFIG_SPL_TEXT_BASE=0x912000
CONFIG_TARGET_IMX8MN_BSH_SMM_S2PRO=y
CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig b/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig
index 3a62272..05f68c7 100644
--- a/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig
+++ b/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig
@@ -87,6 +87,7 @@
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DWC_ETH_QOS=y
diff --git a/configs/imx8mp_beacon_defconfig b/configs/imx8mp_beacon_defconfig
index b0dcbc7..3c337d4 100644
--- a/configs/imx8mp_beacon_defconfig
+++ b/configs/imx8mp_beacon_defconfig
@@ -113,6 +113,7 @@
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y
diff --git a/configs/imx8mp_data_modul_edm_sbc_defconfig b/configs/imx8mp_data_modul_edm_sbc_defconfig
index 209d896..fe3e757 100644
--- a/configs/imx8mp_data_modul_edm_sbc_defconfig
+++ b/configs/imx8mp_data_modul_edm_sbc_defconfig
@@ -206,6 +206,7 @@
# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_MICREL=y
diff --git a/configs/imx8mp_debix_model_a_defconfig b/configs/imx8mp_debix_model_a_defconfig
index 70126c9..aa1de6d 100644
--- a/configs/imx8mp_debix_model_a_defconfig
+++ b/configs/imx8mp_debix_model_a_defconfig
@@ -76,6 +76,7 @@
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH_PHY=y
CONFIG_PHY_GIGE=y
diff --git a/configs/imx8mp_dhcom_pdk2_defconfig b/configs/imx8mp_dhcom_pdk2_defconfig
index 76f2fe8..79b3e96 100644
--- a/configs/imx8mp_dhcom_pdk2_defconfig
+++ b/configs/imx8mp_dhcom_pdk2_defconfig
@@ -15,7 +15,6 @@
CONFIG_DEFAULT_DEVICE_TREE="imx8mp-dhcom-pdk2"
CONFIG_SPL_TEXT_BASE=0x920000
CONFIG_TARGET_IMX8MP_DH_DHCOM_PDK2=y
-CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_SPL_MMC=y
@@ -41,6 +40,7 @@
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000
+CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY=y
CONFIG_SYS_BOOTM_LEN=0x8000000
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_SYSTEM_SETUP=y
@@ -66,6 +66,7 @@
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+# CONFIG_SPL_FIT_IMAGE_TINY is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
@@ -107,6 +108,8 @@
CONFIG_CMD_USB=y
CONFIG_CMD_USB_SDP=y
CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_CAT=y
+CONFIG_CMD_XXD=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_DHCP6=y
CONFIG_CMD_TFTPPUT=y
@@ -179,6 +182,7 @@
CONFIG_GPIO_HOG=y
CONFIG_SPL_GPIO_HOG=y
CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
# CONFIG_INPUT is not set
CONFIG_LED=y
@@ -201,6 +205,7 @@
# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_PHY_SMSC=y
diff --git a/configs/imx8mp_dhcom_pdk3_defconfig b/configs/imx8mp_dhcom_pdk3_defconfig
index 5b338f2..8ef8bf4 100644
--- a/configs/imx8mp_dhcom_pdk3_defconfig
+++ b/configs/imx8mp_dhcom_pdk3_defconfig
@@ -111,6 +111,8 @@
CONFIG_CMD_USB=y
CONFIG_CMD_USB_SDP=y
CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_CAT=y
+CONFIG_CMD_XXD=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_DHCP6=y
CONFIG_CMD_TFTPPUT=y
@@ -160,8 +162,6 @@
CONFIG_PROT_TCP_SACK=y
CONFIG_IPV6=y
CONFIG_SPL_DM=y
-CONFIG_REGMAP=y
-CONFIG_SYSCON=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000
CONFIG_SPL_CLK_COMPOSITE_CCF=y
@@ -208,6 +208,7 @@
# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_PHY_SMSC=y
@@ -231,7 +232,6 @@
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_PCA9450=y
CONFIG_SPL_DM_PMIC_PCA9450=y
-CONFIG_DM_REGULATOR=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PCA9450=y
CONFIG_SPL_DM_REGULATOR_PCA9450=y
diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig
index d907aed..f5ba022 100644
--- a/configs/imx8mp_evk_defconfig
+++ b/configs/imx8mp_evk_defconfig
@@ -93,6 +93,7 @@
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH_PHY=y
CONFIG_PHY_GIGE=y
diff --git a/configs/imx8mp_rsb3720a1_4G_defconfig b/configs/imx8mp_rsb3720a1_4G_defconfig
index 393a131..5478936 100644
--- a/configs/imx8mp_rsb3720a1_4G_defconfig
+++ b/configs/imx8mp_rsb3720a1_4G_defconfig
@@ -126,6 +126,7 @@
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH_PHY=y
CONFIG_PHY_GIGE=y
diff --git a/configs/imx8mp_rsb3720a1_6G_defconfig b/configs/imx8mp_rsb3720a1_6G_defconfig
index 6dd51a3..4b0b71d 100644
--- a/configs/imx8mp_rsb3720a1_6G_defconfig
+++ b/configs/imx8mp_rsb3720a1_6G_defconfig
@@ -127,6 +127,7 @@
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH_PHY=y
CONFIG_PHY_GIGE=y
diff --git a/configs/imx8ulp_evk_defconfig b/configs/imx8ulp_evk_defconfig
index 721c4cb..b302df1 100644
--- a/configs/imx8ulp_evk_defconfig
+++ b/configs/imx8ulp_evk_defconfig
@@ -74,6 +74,7 @@
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_PHYLIB=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_FEC_MXC=y
diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig
index 5ad770f..2246715 100644
--- a/configs/imx93_11x11_evk_defconfig
+++ b/configs/imx93_11x11_evk_defconfig
@@ -98,6 +98,7 @@
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH_PHY=y
CONFIG_PHY_GIGE=y
diff --git a/configs/imx93_11x11_evk_ld_defconfig b/configs/imx93_11x11_evk_ld_defconfig
index abda6d1..deed068 100644
--- a/configs/imx93_11x11_evk_ld_defconfig
+++ b/configs/imx93_11x11_evk_ld_defconfig
@@ -95,6 +95,7 @@
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH_PHY=y
CONFIG_PHY_GIGE=y
diff --git a/configs/imx93_var_som_defconfig b/configs/imx93_var_som_defconfig
index e39d7dc..94ce213 100644
--- a/configs/imx93_var_som_defconfig
+++ b/configs/imx93_var_som_defconfig
@@ -112,6 +112,7 @@
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_ADIN=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_REALTEK=y
diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig
index fe8e84c..4db5654 100644
--- a/configs/j7200_evm_a72_defconfig
+++ b/configs/j7200_evm_a72_defconfig
@@ -15,7 +15,7 @@
CONFIG_ENV_SIZE=0x20000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="k3-j7200-common-proc-board"
+CONFIG_DEFAULT_DEVICE_TREE="ti/k3-j7200-common-proc-board"
CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
@@ -96,6 +96,7 @@
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_OF_UPSTREAM=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CLK_CCF=y
diff --git a/configs/j721e_beagleboneai64_a72_defconfig b/configs/j721e_beagleboneai64_a72_defconfig
index a354876..86c565a 100644
--- a/configs/j721e_beagleboneai64_a72_defconfig
+++ b/configs/j721e_beagleboneai64_a72_defconfig
@@ -172,3 +172,5 @@
CONFIG_SPL_DFU=y
CONFIG_LZO=y
CONFIG_EFI_SET_TIME=y
+
+#include <configs/k3_efi_capsule.config>
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index 3d8e939..f993157 100644
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -14,7 +14,7 @@
CONFIG_ENV_SIZE=0x20000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-common-proc-board"
+CONFIG_DEFAULT_DEVICE_TREE="ti/k3-j721e-common-proc-board"
CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
@@ -88,7 +88,7 @@
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_LIST="k3-j721e-common-proc-board k3-j721e-sk"
+CONFIG_OF_LIST="ti/k3-j721e-common-proc-board"
CONFIG_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
@@ -101,6 +101,7 @@
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_OF_UPSTREAM=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CLK_TI_SCI=y
@@ -210,3 +211,5 @@
CONFIG_CADENCE_UFS=y
CONFIG_TI_J721E_UFS=y
CONFIG_EFI_SET_TIME=y
+
+#include <configs/k3_efi_capsule.config>
diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig
index cea48b2..ffaf21d 100644
--- a/configs/j721e_evm_r5_defconfig
+++ b/configs/j721e_evm_r5_defconfig
@@ -7,6 +7,7 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SOC_K3_J721E=y
CONFIG_K3_EARLY_CONS=y
+CONFIG_K3_QOS=y
CONFIG_TARGET_J721E_R5_EVM=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41cf59f0
@@ -81,7 +82,7 @@
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_SPL_MULTI_DTB_FIT=y
-CONFIG_SPL_OF_LIST="k3-j721e-r5-common-proc-board k3-j721e-r5-sk"
+CONFIG_SPL_OF_LIST="k3-j721e-r5-common-proc-board"
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
diff --git a/configs/j721e_sk_a72_defconfig b/configs/j721e_sk_a72_defconfig
new file mode 100644
index 0000000..80e3e90
--- /dev/null
+++ b/configs/j721e_sk_a72_defconfig
@@ -0,0 +1,9 @@
+#include <configs/j721e_evm_a72_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SOC_K3_J721E=y
+CONFIG_TARGET_J721E_A72_EVM=y
+
+CONFIG_DEFAULT_DEVICE_TREE="ti/k3-j721e-sk"
+CONFIG_OF_LIST="ti/k3-j721e-sk"
diff --git a/configs/j721e_sk_r5_defconfig b/configs/j721e_sk_r5_defconfig
new file mode 100644
index 0000000..b361c69
--- /dev/null
+++ b/configs/j721e_sk_r5_defconfig
@@ -0,0 +1,10 @@
+#include <configs/j721e_evm_r5_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SOC_K3_J721E=y
+CONFIG_TARGET_J721E_R5_EVM=y
+
+CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-r5-sk"
+CONFIG_SPL_OF_LIST="k3-j721e-r5-sk"
+CONFIG_OF_LIST="k3-j721e-r5-sk"
diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig
index 5ed8d00..5c3b52ba 100644
--- a/configs/j721s2_evm_a72_defconfig
+++ b/configs/j721s2_evm_a72_defconfig
@@ -10,6 +10,7 @@
CONFIG_TARGET_J721S2_A72_EVM=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
+CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_ENV_SIZE=0x20000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig
index 3c958ca..6404b1c 100644
--- a/configs/j721s2_evm_r5_defconfig
+++ b/configs/j721s2_evm_r5_defconfig
@@ -7,9 +7,11 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SOC_K3_J721S2=y
CONFIG_K3_EARLY_CONS=y
+CONFIG_K3_QOS=y
CONFIG_TARGET_J721S2_R5_EVM=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41c76000
+CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_ENV_SIZE=0x20000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
@@ -24,7 +26,6 @@
CONFIG_SPL_BSS_START_ADDR=0x41c76000
CONFIG_SPL_BSS_MAX_SIZE=0xa000
CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x140000
CONFIG_SPL_SIZE_LIMIT=0x80000
CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000
CONFIG_SPL_FS_FAT=y
diff --git a/configs/j722s_evm_a53_defconfig b/configs/j722s_evm_a53_defconfig
new file mode 100644
index 0000000..da0e9f4
--- /dev/null
+++ b/configs/j722s_evm_a53_defconfig
@@ -0,0 +1,172 @@
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SOC_K3_J722S=y
+CONFIG_TARGET_J722S_A53_EVM=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
+CONFIG_SF_DEFAULT_SPEED=25000000
+CONFIG_ENV_SIZE=0x40000
+CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="ti/k3-j722s-evm"
+CONFIG_SPL_TEXT_BASE=0x80080000
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x80a00000
+CONFIG_SPL_BSS_MAX_SIZE=0x80000
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
+CONFIG_BOOTSTD_FULL=y
+CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb"
+CONFIG_SPL_MAX_SIZE=0x58000
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
+CONFIG_SPL_I2C=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+# CONFIG_SPL_SPI_FLASH_TINY is not set
+CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
+CONFIG_SPL_THERMAL=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_REMOTEPROC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_UBI=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
+CONFIG_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_DEVICE_REMOVE=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_TI_SCI=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_MTD=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0xC0000000
+CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_SPL_DM_GPIO_LOOKUP_LABEL=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_SPL_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SPL_I2C_EEPROM=y
+CONFIG_FS_LOADER=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_SPL_MMC_IO_VOLTAGE=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_SOFT_RESET=y
+CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_S28HX_T=y
+CONFIG_PHY_TI_DP83867=y
+CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_GPIO=y
+CONFIG_K3_SYSTEM_CONTROLLER=y
+CONFIG_REMOTEPROC_TI_K3_ARM64=y
+CONFIG_REMOTEPROC_TI_K3_DSP=y
+CONFIG_REMOTEPROC_TI_K3_R5F=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_SOC_TI=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_TI_SCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_SPL_USB_HOST=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_SPL_USB_DWC3_GENERIC=y
+CONFIG_SPL_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0451
+CONFIG_USB_GADGET_PRODUCT_NUM=0x6165
+CONFIG_SPL_DFU=y
+CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
diff --git a/configs/j722s_evm_r5_defconfig b/configs/j722s_evm_r5_defconfig
new file mode 100644
index 0000000..d7b99cb
--- /dev/null
+++ b/configs/j722s_evm_r5_defconfig
@@ -0,0 +1,131 @@
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SYS_MALLOC_F_LEN=0x9000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SOC_K3_J722S=y
+CONFIG_TARGET_J722S_R5_EVM=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x43c4a7f0
+CONFIG_SF_DEFAULT_SPEED=25000000
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0x680000
+CONFIG_SPL_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-j722s-r5-evm"
+CONFIG_SPL_TEXT_BASE=0x43c00000
+CONFIG_DM_RESET=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x43c7b000
+CONFIG_SPL_BSS_MAX_SIZE=0x3000
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000
+CONFIG_SPL_SIZE_LIMIT=0x3C000
+CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x5000
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
+CONFIG_SPL_MAX_SIZE=0x6ce00
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_EARLY_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
+CONFIG_SPL_DMA=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_REMOTEPROC=y
+# CONFIG_SPL_SPI_FLASH_TINY is not set
+CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
+CONFIG_SPL_THERMAL=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_REMOTEPROC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_PART=1
+# CONFIG_NET is not set
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_DEVICE_REMOVE=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_SPL_CLK_CCF=y
+CONFIG_SPL_CLK_K3_PLL=y
+CONFIG_SPL_CLK_K3=y
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_TI_SCI_PROTOCOL=y
+# CONFIG_GPIO is not set
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_SOFT_RESET=y
+CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_S28HX_T=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_GENERIC is not set
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_GENERIC is not set
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_POWER_DOMAIN=y
+CONFIG_K3_SYSTEM_CONTROLLER=y
+CONFIG_REMOTEPROC_TI_K3_ARM64=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_SOC_TI=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_LIB_RATIONAL=y
+CONFIG_SPL_LIB_RATIONAL=y
diff --git a/configs/j784s4_evm_a72_defconfig b/configs/j784s4_evm_a72_defconfig
index bb9603b..3cfa006 100644
--- a/configs/j784s4_evm_a72_defconfig
+++ b/configs/j784s4_evm_a72_defconfig
@@ -49,16 +49,22 @@
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
+# CONFIG_SPL_SPI_FLASH_TINY is not set
+CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
CONFIG_SPL_THERMAL=y
CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
+CONFIG_CMD_REMOTEPROC=y
+CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
@@ -79,6 +85,9 @@
CONFIG_SPL_CLK=y
CONFIG_CLK_CCF=y
CONFIG_CLK_TI_SCI=y
+CONFIG_DFU_SF=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
CONFIG_DMA_CHANNELS=y
CONFIG_TI_K3_NAVSS_UDMA=y
CONFIG_TI_SCI_PROTOCOL=y
@@ -134,7 +143,11 @@
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
+CONFIG_REMOTEPROC_TI_K3_DSP=y
+CONFIG_REMOTEPROC_TI_K3_R5F=y
CONFIG_RESET_TI_SCI=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
CONFIG_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SOC_DEVICE=y
@@ -147,3 +160,6 @@
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
CONFIG_DM_THERMAL=y
+CONFIG_EFI_SET_TIME=y
+
+#include <configs/k3_efi_capsule.config>
diff --git a/configs/j784s4_evm_r5_defconfig b/configs/j784s4_evm_r5_defconfig
index f5fe743..7ace661 100644
--- a/configs/j784s4_evm_r5_defconfig
+++ b/configs/j784s4_evm_r5_defconfig
@@ -6,6 +6,7 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SOC_K3_J784S4=y
CONFIG_K3_EARLY_CONS=y
+CONFIG_K3_QOS=y
CONFIG_TARGET_J784S4_R5_EVM=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41c76000
@@ -24,7 +25,6 @@
CONFIG_SPL_BSS_START_ADDR=0x41c76000
CONFIG_SPL_BSS_MAX_SIZE=0xa000
CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x140000
CONFIG_SPL_SIZE_LIMIT=0x80000
CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000
CONFIG_SPL_FS_FAT=y
@@ -56,6 +56,8 @@
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_REMOTEPROC=y
+# CONFIG_SPL_SPI_FLASH_TINY is not set
+CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
CONFIG_SPL_THERMAL=y
diff --git a/configs/jaguar-rk3588_defconfig b/configs/jaguar-rk3588_defconfig
index b69cf4c..36bf34d 100644
--- a/configs/jaguar-rk3588_defconfig
+++ b/configs/jaguar-rk3588_defconfig
@@ -5,7 +5,6 @@
CONFIG_SPL_GPIO=y
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x2000
-CONFIG_ENV_SIZE=0x1f000
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-jaguar"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_ROCKCHIP_BOOT_MODE_REG=0x0
diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
index 88965e2..5d54d75 100644
--- a/configs/k2g_evm_defconfig
+++ b/configs/k2g_evm_defconfig
@@ -81,6 +81,7 @@
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
+CONFIG_PHY_ANEG_TIMEOUT=10000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
diff --git a/configs/k2g_hs_evm_defconfig b/configs/k2g_hs_evm_defconfig
index 3a45c41..9adab3a 100644
--- a/configs/k2g_hs_evm_defconfig
+++ b/configs/k2g_hs_evm_defconfig
@@ -57,6 +57,7 @@
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
+CONFIG_PHY_ANEG_TIMEOUT=10000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
diff --git a/configs/k3_efi_capsule.config b/configs/k3_efi_capsule.config
new file mode 100644
index 0000000..e31cea3
--- /dev/null
+++ b/configs/k3_efi_capsule.config
@@ -0,0 +1,2 @@
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
diff --git a/configs/kontron_pitx_imx8m_defconfig b/configs/kontron_pitx_imx8m_defconfig
index e2a87c4..c213347 100644
--- a/configs/kontron_pitx_imx8m_defconfig
+++ b/configs/kontron_pitx_imx8m_defconfig
@@ -83,6 +83,7 @@
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_TI=y
CONFIG_PHY_GIGE=y
CONFIG_FEC_MXC=y
diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig
index a4a7f1a..868eeaf 100644
--- a/configs/lion-rk3368_defconfig
+++ b/configs/lion-rk3368_defconfig
@@ -77,6 +77,7 @@
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MSCC=y
CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig
index 0ebda79..db3a5b9 100644
--- a/configs/m53menlo_defconfig
+++ b/configs/m53menlo_defconfig
@@ -22,6 +22,7 @@
CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
CONFIG_ENV_OFFSET_REDUND=0x180000
CONFIG_SYS_LOAD_ADDR=0x70800000
+CONFIG_CMD_BMODE=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=1
CONFIG_OF_BOARD_SETUP=y
@@ -71,7 +72,7 @@
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
-CONFIG_BOOTFILE="boot/fitImage"
+CONFIG_BOOTFILE="fitImage"
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="FEC0"
CONFIG_USE_HOSTNAME=y
diff --git a/configs/maxbcm_defconfig b/configs/maxbcm_defconfig
index 9906099..c5c3a69 100644
--- a/configs/maxbcm_defconfig
+++ b/configs/maxbcm_defconfig
@@ -53,6 +53,7 @@
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
@@ -62,3 +63,4 @@
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD_SPI=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/milkv_duo_defconfig b/configs/milkv_duo_defconfig
index 0cb2922..d350ec1 100644
--- a/configs/milkv_duo_defconfig
+++ b/configs/milkv_duo_defconfig
@@ -32,11 +32,11 @@
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_CV1800B=y
+CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SYS_NS16550=y
CONFIG_SYS_NS16550_MEM32=y
-CONFIG_SYSRESET=y
-CONFIG_SYSRESET_CV1800B=y
-CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI=y
CONFIG_CV1800B_SPIF=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_CV1800B=y
diff --git a/configs/msc_sm2s_imx8mp_defconfig b/configs/msc_sm2s_imx8mp_defconfig
index dc5a45f..2e1d112 100644
--- a/configs/msc_sm2s_imx8mp_defconfig
+++ b/configs/msc_sm2s_imx8mp_defconfig
@@ -85,6 +85,7 @@
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_TI=y
CONFIG_DM_ETH_PHY=y
CONFIG_PHY_GIGE=y
diff --git a/configs/mt7981_rfb_defconfig b/configs/mt7981_rfb_defconfig
index 817e4b3..3989c79 100644
--- a/configs/mt7981_rfb_defconfig
+++ b/configs/mt7981_rfb_defconfig
@@ -64,4 +64,5 @@
CONFIG_DM_SPI=y
CONFIG_MTK_SPIM=y
CONFIG_HEXDUMP=y
+# CONFIG_EFI_LOADER is not set
CONFIG_LMB_MAX_REGIONS=64
diff --git a/configs/mt7986_rfb_defconfig b/configs/mt7986_rfb_defconfig
index 35227eb..4d0cc85 100644
--- a/configs/mt7986_rfb_defconfig
+++ b/configs/mt7986_rfb_defconfig
@@ -64,4 +64,5 @@
CONFIG_DM_SPI=y
CONFIG_MTK_SPIM=y
CONFIG_HEXDUMP=y
+# CONFIG_EFI_LOADER is not set
CONFIG_LMB_MAX_REGIONS=64
diff --git a/configs/mvebu_espressobin_ultra-88f3720_defconfig b/configs/mvebu_espressobin_ultra-88f3720_defconfig
new file mode 100644
index 0000000..c6ffaaa
--- /dev/null
+++ b/configs/mvebu_espressobin_ultra-88f3720_defconfig
@@ -0,0 +1,106 @@
+CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_TEXT_BASE=0x00000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000
+CONFIG_TARGET_MVEBU_ARMADA_37XX=y
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x3F0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_OF_UPSTREAM=y
+CONFIG_DEFAULT_DEVICE_TREE="marvell/armada-3720-espressobin-ultra"
+CONFIG_SYS_LOAD_ADDR=0x6000000
+CONFIG_PCI=y
+CONFIG_AHCI=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SYS_MAXARGS=32
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SATA=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_BTRFS=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SQUASHFS=y
+CONFIG_CMD_FS_UUID=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ARP_TIMEOUT=200
+CONFIG_NET_RETRY_COUNT=50
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_AHCI_PCI=y
+CONFIG_AHCI_MVEBU=y
+CONFIG_LBA48=y
+CONFIG_SYS_64BIT_LBA=y
+CONFIG_CLK=y
+CONFIG_CLK_MVEBU=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MV=y
+CONFIG_MISC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_XENON=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_FIXED=y
+CONFIG_PHY_GIGE=y
+CONFIG_DM_DSA=y
+CONFIG_MV88E6XXX=y
+CONFIG_MVNETA=y
+CONFIG_MVMDIO=y
+CONFIG_NVME_PCI=y
+CONFIG_PCI_AARDVARK=y
+CONFIG_PHY=y
+CONFIG_MVEBU_COMPHY_SUPPORT=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_ARMADA_37XX=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DEFAULT_ENV_IS_RW=y
+CONFIG_MVEBU_A3700_UART=y
+CONFIG_MVEBU_A3700_SPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_WATCHDOG_AUTOSTART is not set
+CONFIG_WDT=y
+CONFIG_WDT_ARMADA_37XX=y
+CONFIG_SHA1=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_PCF8563=y
+# CONFIG_DEBUG_UART=y
+# CONFIG_DEBUG_UART_BASE=0xd0012000
+# CONFIG_DEBUG_UART_CLOCK=25804800
+# CONFIG_DEBUG_UART_SHIFT=2
+# CONFIG_DEBUG_UART_ANNOUNCE=y
diff --git a/configs/mx6memcal_defconfig b/configs/mx6memcal_defconfig
index 7f11e6f..4c8a596 100644
--- a/configs/mx6memcal_defconfig
+++ b/configs/mx6memcal_defconfig
@@ -44,3 +44,4 @@
CONFIG_FSL_USDHC=y
CONFIG_MXC_UART=y
CONFIG_OF_LIBFDT=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/n2350_defconfig b/configs/n2350_defconfig
index 5e13d2c..e7d7dea 100644
--- a/configs/n2350_defconfig
+++ b/configs/n2350_defconfig
@@ -75,6 +75,7 @@
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
diff --git a/configs/neu2-io-rv1126_defconfig b/configs/neu2-io-rv1126_defconfig
index dc27b9e..2a4c9b4 100644
--- a/configs/neu2-io-rv1126_defconfig
+++ b/configs/neu2-io-rv1126_defconfig
@@ -5,7 +5,7 @@
CONFIG_SYS_ARCH_TIMER=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_DEFAULT_DEVICE_TREE="rv1126-edgeble-neu2-io"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rv1126-edgeble-neu2-io"
CONFIG_SYS_MONITOR_LEN=614400
CONFIG_ROCKCHIP_RV1126=y
CONFIG_TARGET_RV1126_NEU2=y
diff --git a/configs/nova-rk3588s_defconfig b/configs/nova-rk3588s_defconfig
new file mode 100644
index 0000000..a2e2440
--- /dev/null
+++ b/configs/nova-rk3588s_defconfig
@@ -0,0 +1,69 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588s-indiedroid-nova"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_SPL_SERIAL=y
+CONFIG_TARGET_NOVA_RK3588=y
+CONFIG_DEBUG_UART_BASE=0xFEB50000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-indiedroid-nova.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig
index 1483d17..78fb758 100644
--- a/configs/nyan-big_defconfig
+++ b/configs/nyan-big_defconfig
@@ -11,13 +11,10 @@
CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_SPL_STACK=0x800ffffc
CONFIG_BOOTSTAGE_STASH_ADDR=0x83000000
-CONFIG_DEBUG_UART_BASE=0x70006000
-CONFIG_DEBUG_UART_CLOCK=408000000
CONFIG_TEGRA124=y
CONFIG_TARGET_NYAN_BIG=y
CONFIG_TEGRA_GPU=y
CONFIG_SYS_LOAD_ADDR=0x82408000
-CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_BOOTSTAGE=y
@@ -76,7 +73,6 @@
CONFIG_REGULATOR_AS3722=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_PWM_TEGRA=y
-CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_SOUND=y
CONFIG_I2S=y
@@ -84,6 +80,7 @@
CONFIG_SOUND_MAX98090=y
CONFIG_TEGRA114_SPI=y
CONFIG_TPM_TIS_INFINEON=y
+# CONFIG_TPM_V2 is not set
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_TEGRA=y
diff --git a/configs/octeon_ebb7304_defconfig b/configs/octeon_ebb7304_defconfig
index 00fcd57..cb711f0 100644
--- a/configs/octeon_ebb7304_defconfig
+++ b/configs/octeon_ebb7304_defconfig
@@ -63,6 +63,7 @@
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_DM_MDIO=y
CONFIG_DM_ETH_PHY=y
diff --git a/configs/octeon_nic23_defconfig b/configs/octeon_nic23_defconfig
index f7c3553..5a8db5a 100644
--- a/configs/octeon_nic23_defconfig
+++ b/configs/octeon_nic23_defconfig
@@ -25,7 +25,6 @@
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
# CONFIG_SYS_DEVICE_NULLDEV is not set
CONFIG_CYCLIC=y
-CONFIG_CYCLIC_MAX_CPU_TIME_US=5000
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_LATE_INIT=y
diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig
index 99d7149..a9af415 100644
--- a/configs/odroid-go2_defconfig
+++ b/configs/odroid-go2_defconfig
@@ -2,30 +2,17 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x4000
-CONFIG_DEFAULT_DEVICE_TREE="rk3326-odroid-go2"
-CONFIG_SPL_TEXT_BASE=0x00000000
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3326-odroid-go2"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_PX30=y
+# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set
CONFIG_TARGET_ODROID_GO2=y
CONFIG_DEBUG_UART_CHANNEL=1
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
+# CONFIG_TPL_LIBCOMMON_SUPPORT is not set
CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
-CONFIG_SPL_STACK_R_ADDR=0x600000
-CONFIG_SPL_STACK=0x400000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
-CONFIG_SPL_STACK_R=y
CONFIG_DEBUG_UART_BASE=0xFF160000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
@@ -45,11 +32,11 @@
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_ATF=y
# CONFIG_TPL_FRAMEWORK is not set
+# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set
# CONFIG_TPL_BANNER_PRINT is not set
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_ELF is not set
diff --git a/configs/paz00_defconfig b/configs/paz00_defconfig
index 4f0725f..97c7977 100644
--- a/configs/paz00_defconfig
+++ b/configs/paz00_defconfig
@@ -51,5 +51,6 @@
CONFIG_USB_ETHER_ASIX=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_BPP8 is not set
+CONFIG_I2C_EDID=y
CONFIG_VIDEO_TEGRA20=y
CONFIG_CONSOLE_SCROLL_LINES=10
diff --git a/configs/pg_wcom_expu1_defconfig b/configs/pg_wcom_expu1_defconfig
index 2be9e24..61513c9 100644
--- a/configs/pg_wcom_expu1_defconfig
+++ b/configs/pg_wcom_expu1_defconfig
@@ -104,5 +104,6 @@
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_LZO=y
+# CONFIG_EFI_LOADER is not set
CONFIG_POST=y
CONFIG_HUSH_OLD_PARSER=y
diff --git a/configs/pg_wcom_expu1_update_defconfig b/configs/pg_wcom_expu1_update_defconfig
index 9245a56..ec0f975 100644
--- a/configs/pg_wcom_expu1_update_defconfig
+++ b/configs/pg_wcom_expu1_update_defconfig
@@ -102,5 +102,6 @@
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_LZO=y
+# CONFIG_EFI_LOADER is not set
CONFIG_POST=y
CONFIG_HUSH_OLD_PARSER=y
diff --git a/configs/pg_wcom_seli8_defconfig b/configs/pg_wcom_seli8_defconfig
index 033dd82..82923d3 100644
--- a/configs/pg_wcom_seli8_defconfig
+++ b/configs/pg_wcom_seli8_defconfig
@@ -104,5 +104,6 @@
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_LZO=y
+# CONFIG_EFI_LOADER is not set
CONFIG_POST=y
CONFIG_HUSH_OLD_PARSER=y
diff --git a/configs/pg_wcom_seli8_update_defconfig b/configs/pg_wcom_seli8_update_defconfig
index 4d34ef6..41931e2 100644
--- a/configs/pg_wcom_seli8_update_defconfig
+++ b/configs/pg_wcom_seli8_update_defconfig
@@ -102,5 +102,6 @@
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_LZO=y
+# CONFIG_EFI_LOADER is not set
CONFIG_POST=y
CONFIG_HUSH_OLD_PARSER=y
diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig
index 22d4190..f9fd725 100644
--- a/configs/phycore-imx8mm_defconfig
+++ b/configs/phycore-imx8mm_defconfig
@@ -9,7 +9,7 @@
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x3C0000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mm-phyboard-polis-rdk"
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-phyboard-polis-rdk"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_PHYCORE_IMX8MM=y
CONFIG_SYS_MONITOR_LEN=524288
diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig
index 9f42edd..8dd4963 100644
--- a/configs/phycore-imx8mp_defconfig
+++ b/configs/phycore-imx8mp_defconfig
@@ -5,14 +5,14 @@
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_PHYTEC_SOM_DETECTION=y
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x3C0000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mp-phyboard-pollux-rdk"
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-phyboard-pollux-rdk"
CONFIG_SPL_TEXT_BASE=0x920000
CONFIG_TARGET_PHYCORE_IMX8MP=y
-CONFIG_PHYTEC_SOM_DETECTION=y
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
@@ -32,6 +32,7 @@
CONFIG_DEFAULT_FDT_FILE="oftree"
CONFIG_SYS_CBSIZE=2048
CONFIG_SYS_PBSIZE=2074
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x26000
CONFIG_SPL_BOARD_INIT=y
@@ -44,6 +45,7 @@
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+# CONFIG_SPL_CRYPTO is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
@@ -86,6 +88,7 @@
CONFIG_SPL_DM=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_CLK_IMX8MP=y
+CONFIG_FSL_CAAM=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x42800000
CONFIG_FASTBOOT_BUF_SIZE=0x13000000
@@ -101,7 +104,6 @@
CONFIG_DM_I2C=y
# CONFIG_SPL_DM_I2C is not set
CONFIG_SPL_SYS_I2C_LEGACY=y
-CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x51
CONFIG_SUPPORT_EMMC_BOOT=y
@@ -151,3 +153,4 @@
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_IMX_WATCHDOG=y
+# CONFIG_SPL_SHA_HW_ACCEL is not set
diff --git a/configs/phycore_am62x_a53_defconfig b/configs/phycore_am62x_a53_defconfig
index fd36edc..95a48aa 100644
--- a/configs/phycore_am62x_a53_defconfig
+++ b/configs/phycore_am62x_a53_defconfig
@@ -1,16 +1,18 @@
CONFIG_ARM=y
CONFIG_ARCH_K3=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_AM625=y
+CONFIG_PHYTEC_SOM_DETECTION=y
CONFIG_TARGET_PHYCORE_AM62X_A53=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80b80000
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0xFFFFD000
+CONFIG_ENV_OFFSET=0x680000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am625-phyboard-lyra-rdk"
CONFIG_SPL_TEXT_BASE=0x80080000
@@ -25,6 +27,7 @@
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SIZE_LIMIT=0x40000
CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x800
+CONFIG_ENV_OFFSET_REDUND=0x6c0000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -35,44 +38,62 @@
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
CONFIG_BOOTSTD_FULL=y
CONFIG_SYS_BOOTM_LEN=0x800000
+CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="run mmcboot; bootflow scan -lb"
CONFIG_DEFAULT_FDT_FILE="oftree"
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x58000
CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
+CONFIG_SPL_I2C=y
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
# CONFIG_SPL_SPI_FLASH_TINY is not set
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_CMD_DFU=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_USB=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CLK_TI_SCI=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
CONFIG_DMA_CHANNELS=y
CONFIG_TI_K3_NAVSS_UDMA=y
CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_SUPPORT_EMMC_BOOT=y
@@ -86,10 +107,9 @@
# CONFIG_SPI_FLASH_SMART_HWCAPS is not set
CONFIG_SPI_FLASH_SOFT_RESET=y
CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_S28HX_T=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_MT35XU=y
+CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_TI_DP83867=y
CONFIG_PHY_FIXED=y
CONFIG_TI_AM65_CPSW_NUSS=y
@@ -112,4 +132,21 @@
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_SPL_USB_DWC3_GENERIC=y
+CONFIG_SPL_USB_DWC3_AM62=y
+CONFIG_USB_DWC3_AM62=y
+CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Phytec"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0451
+CONFIG_USB_GADGET_PRODUCT_NUM=0x6165
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_DFU=y
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
diff --git a/configs/phycore_am62x_r5_defconfig b/configs/phycore_am62x_r5_defconfig
index 389672d..c1664c4 100644
--- a/configs/phycore_am62x_r5_defconfig
+++ b/configs/phycore_am62x_r5_defconfig
@@ -6,6 +6,7 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_AM625=y
+CONFIG_PHYTEC_SOM_DETECTION=y
CONFIG_TARGET_PHYCORE_AM62X_R5=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x43c3a7f0
@@ -26,7 +27,6 @@
CONFIG_SPL_BSS_START_ADDR=0x43c3b000
CONFIG_SPL_BSS_MAX_SIZE=0x3000
CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000
CONFIG_SPL_SIZE_LIMIT=0x3A7F0
CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x3500
CONFIG_SPL_FS_FAT=y
@@ -50,6 +50,7 @@
CONFIG_SPL_EARLY_BSS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
+CONFIG_SPL_I2C=y
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_DM_RESET=y
@@ -88,6 +89,7 @@
CONFIG_SPL_CLK_K3=y
CONFIG_TI_SCI_PROTOCOL=y
CONFIG_DA8XX_GPIO=y
+CONFIG_DM_I2C=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_SPL_MISC=y
@@ -103,7 +105,6 @@
# CONFIG_SPI_FLASH_SMART_HWCAPS is not set
CONFIG_SPI_FLASH_SOFT_RESET=y
CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
-CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_MT35XU=y
CONFIG_PINCTRL=y
@@ -129,3 +130,4 @@
CONFIG_OMAP_TIMER=y
CONFIG_LIB_RATIONAL=y
CONFIG_SPL_LIB_RATIONAL=y
+CONFIG_SYS_I2C_OMAP24XX=y
diff --git a/configs/phycore_am64x_a53_defconfig b/configs/phycore_am64x_a53_defconfig
index 76bb0e5..cf04e14 100644
--- a/configs/phycore_am64x_a53_defconfig
+++ b/configs/phycore_am64x_a53_defconfig
@@ -13,7 +13,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0xFFFFD000
+CONFIG_ENV_OFFSET=0x680000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am642-phyboard-electra-rdk"
@@ -28,6 +28,7 @@
CONFIG_SPL_BSS_START_ADDR=0x80a00000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
CONFIG_SPL_STACK_R=y
+CONFIG_ENV_OFFSET_REDUND=0x6c0000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -68,6 +69,7 @@
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
CONFIG_CMD_USB=y
CONFIG_CMD_TIME=y
CONFIG_OF_CONTROL=y
@@ -76,6 +78,7 @@
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
@@ -118,10 +121,9 @@
# CONFIG_SPI_FLASH_SMART_HWCAPS is not set
CONFIG_SPI_FLASH_SOFT_RESET=y
CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_S28HX_T=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_MT35XU=y
+CONFIG_SPI_FLASH_MTD=y
CONFIG_MULTIPLEXER=y
CONFIG_MUX_MMIO=y
CONFIG_PHY_TI_DP83867=y
diff --git a/configs/phycore_am64x_r5_defconfig b/configs/phycore_am64x_r5_defconfig
index 15a7e70..a0d7824 100644
--- a/configs/phycore_am64x_r5_defconfig
+++ b/configs/phycore_am64x_r5_defconfig
@@ -121,7 +121,6 @@
# CONFIG_SPI_FLASH_SMART_HWCAPS is not set
CONFIG_SPI_FLASH_SOFT_RESET=y
CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
-CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_MT35XU=y
CONFIG_PHY_TI_DP83867=y
diff --git a/configs/powkiddy-x55-rk3566_defconfig b/configs/powkiddy-x55-rk3566_defconfig
new file mode 100644
index 0000000..2360bdb
--- /dev/null
+++ b/configs/powkiddy-x55-rk3566_defconfig
@@ -0,0 +1,58 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-powkiddy-x55"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_SERIAL=y
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-powkiddy-x55.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig
index 34a0b57..5319239 100644
--- a/configs/puma-rk3399_defconfig
+++ b/configs/puma-rk3399_defconfig
@@ -6,7 +6,6 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_SIZE=0x3000
-CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-puma-haikou"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
@@ -29,7 +28,12 @@
CONFIG_SPL_POWER=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_TPL=y
-CONFIG_CMD_BOOTZ=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_CMD_VBE is not set
+# CONFIG_BOOTM_VXWORKS is not set
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
@@ -41,6 +45,8 @@
CONFIG_CMD_TIME=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EROFS=y
+CONFIG_CMD_SQUASHFS=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_OVERWRITE=y
diff --git a/configs/px30-core-ctouch2-of10-px30_defconfig b/configs/px30-core-ctouch2-of10-px30_defconfig
index a2801ec..fdcbd8a 100644
--- a/configs/px30-core-ctouch2-of10-px30_defconfig
+++ b/configs/px30-core-ctouch2-of10-px30_defconfig
@@ -2,28 +2,15 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000
-CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-ctouch2-of10"
-CONFIG_SPL_TEXT_BASE=0x00000000
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/px30-engicam-px30-core-ctouch2-of10"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_PX30=y
+# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set
CONFIG_TARGET_PX30_CORE=y
CONFIG_DEBUG_UART_CHANNEL=1
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
+# CONFIG_TPL_LIBCOMMON_SUPPORT is not set
CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
-CONFIG_SPL_STACK_R_ADDR=0x600000
-CONFIG_SPL_STACK=0x400000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
-CONFIG_SPL_STACK_R=y
CONFIG_DEBUG_UART_BASE=0xFF160000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
@@ -41,9 +28,9 @@
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_ATF=y
# CONFIG_TPL_FRAMEWORK is not set
+# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set
# CONFIG_TPL_BANNER_PRINT is not set
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_ELF is not set
diff --git a/configs/px30-core-ctouch2-px30_defconfig b/configs/px30-core-ctouch2-px30_defconfig
index cc33e27..343fd0b 100644
--- a/configs/px30-core-ctouch2-px30_defconfig
+++ b/configs/px30-core-ctouch2-px30_defconfig
@@ -2,28 +2,15 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000
-CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-ctouch2"
-CONFIG_SPL_TEXT_BASE=0x00000000
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/px30-engicam-px30-core-ctouch2"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_PX30=y
+# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set
CONFIG_TARGET_PX30_CORE=y
CONFIG_DEBUG_UART_CHANNEL=1
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
+# CONFIG_TPL_LIBCOMMON_SUPPORT is not set
CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
-CONFIG_SPL_STACK_R_ADDR=0x600000
-CONFIG_SPL_STACK=0x400000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
-CONFIG_SPL_STACK_R=y
CONFIG_DEBUG_UART_BASE=0xFF160000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
@@ -41,9 +28,9 @@
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_ATF=y
# CONFIG_TPL_FRAMEWORK is not set
+# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set
# CONFIG_TPL_BANNER_PRINT is not set
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_ELF is not set
diff --git a/configs/px30-core-edimm2.2-px30_defconfig b/configs/px30-core-edimm2.2-px30_defconfig
index 99e1b2f..aa0bff4 100644
--- a/configs/px30-core-edimm2.2-px30_defconfig
+++ b/configs/px30-core-edimm2.2-px30_defconfig
@@ -2,28 +2,15 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000
-CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-edimm2.2"
-CONFIG_SPL_TEXT_BASE=0x00000000
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/px30-engicam-px30-core-edimm2.2"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_PX30=y
+# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set
CONFIG_TARGET_PX30_CORE=y
CONFIG_DEBUG_UART_CHANNEL=1
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
+# CONFIG_TPL_LIBCOMMON_SUPPORT is not set
CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
-CONFIG_SPL_STACK_R_ADDR=0x600000
-CONFIG_SPL_STACK=0x400000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
-CONFIG_SPL_STACK_R=y
CONFIG_DEBUG_UART_BASE=0xFF160000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
@@ -41,9 +28,9 @@
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_ATF=y
# CONFIG_TPL_FRAMEWORK is not set
+# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set
# CONFIG_TPL_BANNER_PRINT is not set
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_ELF is not set
diff --git a/configs/qc750_defconfig b/configs/qc750_defconfig
new file mode 100644
index 0000000..17b5ec8
--- /dev/null
+++ b/configs/qc750_defconfig
@@ -0,0 +1,81 @@
+CONFIG_ARM=y
+CONFIG_ARCH_TEGRA=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_CMDLINE_TAG=y
+CONFIG_INITRD_TAG=y
+CONFIG_TEXT_BASE=0x80110000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SIZE=0x3000
+CONFIG_ENV_OFFSET=0xFFFFD000
+CONFIG_DEFAULT_DEVICE_TREE="tegra30-wexler-qc750"
+CONFIG_SPL_TEXT_BASE=0x80108000
+CONFIG_SPL_STACK=0x800ffffc
+CONFIG_TEGRA30=y
+CONFIG_TARGET_QC750=y
+CONFIG_TEGRA_ENABLE_UARTD=y
+CONFIG_CMD_EBTUPDATE=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_BUTTON_CMD=y
+CONFIG_BOOTDELAY=0
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_KEYED_CTRLC=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTCOMMAND="bootflow scan; poweroff"
+CONFIG_SYS_PBSIZE=2084
+CONFIG_SPL_FOOTPRINT_LIMIT=y
+CONFIG_SPL_MAX_FOOTPRINT=0x8000
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
+CONFIG_SYS_PROMPT="Tegra30 (QC750) # "
+# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
+CONFIG_CMD_BOOTMENU=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_UMS_ABORT_KEYED=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PAUSE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_PART=2
+CONFIG_BUTTON=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x91000000
+CONFIG_FASTBOOT_BUF_SIZE=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_MAX77663_GPIO=y
+CONFIG_SYS_I2C_TEGRA=y
+CONFIG_BUTTON_KEYBOARD=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_MAX77663=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_MAX77663=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_PWM_TEGRA=y
+CONFIG_SYS_NS16550=y
+CONFIG_SYSRESET_MAX77663=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_LOGO is not set
+CONFIG_VIDEO_TEGRA20=y
diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig
index 80ad3b3..4942237 100644
--- a/configs/qcom_defconfig
+++ b/configs/qcom_defconfig
@@ -1,16 +1,17 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_POSITION_INDEPENDENT=y
+CONFIG_SYS_INIT_SP_BSS_OFFSET=1572864
CONFIG_ARCH_SNAPDRAGON=y
CONFIG_DEFAULT_DEVICE_TREE="qcom/sdm845-db845c"
CONFIG_SYS_LOAD_ADDR=0xA0000000
-CONFIG_SYS_INIT_SP_BSS_OFFSET=1572864
CONFIG_BUTTON_CMD=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTSTD_FULL=y
# CONFIG_BOOTMETH_VBE is not set
CONFIG_BOOTDELAY=1
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y
CONFIG_SYS_CBSIZE=512
@@ -34,9 +35,12 @@
CONFIG_CMD_BMP=y
CONFIG_CMD_LOG=y
CONFIG_OF_LIVE=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_BUTTON_QCOM_PMIC=y
+CONFIG_USE_DEFAULT_ENV_FILE=y
+CONFIG_DEFAULT_ENV_FILE="board/qualcomm/default.env"
CONFIG_CLK=y
+CONFIG_CLK_QCOM_APQ8016=y
+CONFIG_CLK_QCOM_APQ8096=y
CONFIG_CLK_QCOM_QCM2290=y
CONFIG_CLK_QCOM_QCS404=y
CONFIG_CLK_QCOM_SDM845=y
@@ -73,6 +77,8 @@
CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=y
CONFIG_PHY_QCOM_SNPS_EUSB2=y
CONFIG_PINCTRL=y
+CONFIG_PINCTRL_QCOM_APQ8016=y
+CONFIG_PINCTRL_QCOM_APQ8096=y
CONFIG_PINCTRL_QCOM_QCM2290=y
CONFIG_PINCTRL_QCOM_QCS404=y
CONFIG_PINCTRL_QCOM_SDM845=y
@@ -106,5 +112,4 @@
CONFIG_NO_FB_CLEAR=y
CONFIG_VIDEO_SIMPLE=y
CONFIG_HEXDUMP=y
-CONFIG_GENERATE_SMBIOS_TABLE=y
CONFIG_LMB_MAX_REGIONS=64
diff --git a/configs/qemu-xtensa-dc233c_defconfig b/configs/qemu-xtensa-dc233c_defconfig
new file mode 100644
index 0000000..e6f40b3
--- /dev/null
+++ b/configs/qemu-xtensa-dc233c_defconfig
@@ -0,0 +1,32 @@
+CONFIG_XTENSA=y
+CONFIG_SYS_CPU="dc233c"
+CONFIG_SYS_MALLOC_LEN=0x40000
+CONFIG_SYS_MALLOC_F_LEN=0x400
+CONFIG_ENV_SIZE=0x20000
+CONFIG_DEFAULT_DEVICE_TREE="virt"
+CONFIG_SYS_MONITOR_LEN=262144
+CONFIG_SYS_LOAD_ADDR=0x02000000
+CONFIG_TARGET_QEMU_XTENSA=y
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_BASE=0xF6000000
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
+CONFIG_SHOW_BOOT_PROGRESS=y
+CONFIG_BOOTDELAY=10
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press <SPACE> to stop\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_SYS_PBSIZE=1049
+CONFIG_SYS_MALLOC_BOOTPARAMS=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="U-Boot> "
+CONFIG_CMD_ASKENV=y
+CONFIG_CRC32_VERIFY=y
+CONFIG_CMD_MX_CYCLIC=y
+CONFIG_CMD_SAVES=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DIAG=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="uImage"
+CONFIG_VERSION_VARIABLE=y
+CONFIG_SYSRESET=y
diff --git a/configs/r8a77970_eagle_defconfig b/configs/r8a77970_eagle_defconfig
index 09ea1c5..9983dbd 100644
--- a/configs/r8a77970_eagle_defconfig
+++ b/configs/r8a77970_eagle_defconfig
@@ -67,6 +67,7 @@
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y
@@ -80,3 +81,4 @@
CONFIG_RENESAS_RPC_SPI=y
CONFIG_TEE=y
CONFIG_OPTEE=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/r8a77970_v3msk_defconfig b/configs/r8a77970_v3msk_defconfig
index 089c754..ab49d54 100644
--- a/configs/r8a77970_v3msk_defconfig
+++ b/configs/r8a77970_v3msk_defconfig
@@ -72,6 +72,7 @@
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y
diff --git a/configs/r8a77980_condor_defconfig b/configs/r8a77980_condor_defconfig
index 9f5212f..1e7e430 100644
--- a/configs/r8a77980_condor_defconfig
+++ b/configs/r8a77980_condor_defconfig
@@ -75,6 +75,7 @@
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y
diff --git a/configs/r8a77980_v3hsk_defconfig b/configs/r8a77980_v3hsk_defconfig
index 8c85f42..e942acd 100644
--- a/configs/r8a77980_v3hsk_defconfig
+++ b/configs/r8a77980_v3hsk_defconfig
@@ -68,6 +68,7 @@
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y
diff --git a/configs/r8a77990_ebisu_defconfig b/configs/r8a77990_ebisu_defconfig
index 3960a25..7418d39 100644
--- a/configs/r8a77990_ebisu_defconfig
+++ b/configs/r8a77990_ebisu_defconfig
@@ -89,6 +89,7 @@
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y
diff --git a/configs/r8a77995_draak_defconfig b/configs/r8a77995_draak_defconfig
index 01f5b13..29d921d 100644
--- a/configs/r8a77995_draak_defconfig
+++ b/configs/r8a77995_draak_defconfig
@@ -86,6 +86,7 @@
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y
diff --git a/configs/r8a779a0_falcon_defconfig b/configs/r8a779a0_falcon_defconfig
index 40097f9..7dbd145 100644
--- a/configs/r8a779a0_falcon_defconfig
+++ b/configs/r8a779a0_falcon_defconfig
@@ -61,6 +61,7 @@
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y
diff --git a/configs/r8a779f0_spider_defconfig b/configs/r8a779f0_spider_defconfig
index 9ab46a4..e822e95 100644
--- a/configs/r8a779f0_spider_defconfig
+++ b/configs/r8a779f0_spider_defconfig
@@ -64,6 +64,7 @@
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHYLIB_10G=y
CONFIG_PHY_MARVELL_10G=y
CONFIG_DM_ETH_PHY=y
diff --git a/configs/r8a779g0_whitehawk_defconfig b/configs/r8a779g0_whitehawk_defconfig
index abc9a3b..a0abc45 100644
--- a/configs/r8a779g0_whitehawk_defconfig
+++ b/configs/r8a779g0_whitehawk_defconfig
@@ -60,6 +60,7 @@
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y
diff --git a/configs/r8a779h0_grayhawk_defconfig b/configs/r8a779h0_grayhawk_defconfig
index 6bd872f..6cbe27a 100644
--- a/configs/r8a779h0_grayhawk_defconfig
+++ b/configs/r8a779h0_grayhawk_defconfig
@@ -5,7 +5,7 @@
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xFFFE0000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="r8a779h0-gray-hawk"
+CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a779h0-gray-hawk-single"
CONFIG_RCAR_GEN4=y
CONFIG_TARGET_GRAYHAWK=y
CONFIG_SYS_MONITOR_LEN=1048576
@@ -39,7 +39,6 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
-# CONFIG_OF_UPSTREAM is not set
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=2
@@ -61,6 +60,7 @@
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y
diff --git a/configs/rcar3_salvator-x_defconfig b/configs/rcar3_salvator-x_defconfig
index 45d2446..318a9ab 100644
--- a/configs/rcar3_salvator-x_defconfig
+++ b/configs/rcar3_salvator-x_defconfig
@@ -92,6 +92,7 @@
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y
diff --git a/configs/rcar3_ulcb_defconfig b/configs/rcar3_ulcb_defconfig
index b5d8121..f8e8c92 100644
--- a/configs/rcar3_ulcb_defconfig
+++ b/configs/rcar3_ulcb_defconfig
@@ -90,6 +90,7 @@
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y
diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig
index 67a44ed..2320479 100644
--- a/configs/ringneck-px30_defconfig
+++ b/configs/ringneck-px30_defconfig
@@ -2,57 +2,47 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_GPIO=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000
-CONFIG_DEFAULT_DEVICE_TREE="px30-ringneck-haikou"
-CONFIG_SPL_TEXT_BASE=0x00000000
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/px30-ringneck-haikou"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_PX30=y
+# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set
CONFIG_TARGET_RINGNECK_PX30=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
+# CONFIG_TPL_LIBCOMMON_SUPPORT is not set
CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
-CONFIG_SPL_STACK_R_ADDR=0x600000
-CONFIG_SPL_STACK=0x400000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
-CONFIG_SPL_STACK_R=y
CONFIG_DEBUG_UART_BASE=0xFF030000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
-CONFIG_TPL_MAX_SIZE=0x20000
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_BOOTSTD_FULL=y
CONFIG_DEFAULT_FDT_FILE="rockchip/px30-ringneck-haikou.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x20000
-CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_PAD_TO=0x38000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
CONFIG_SPL_ATF=y
# CONFIG_TPL_FRAMEWORK is not set
-# CONFIG_CMD_BOOTD is not set
+# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_CMD_VBE is not set
+# CONFIG_BOOTM_VXWORKS is not set
# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_LZMADEC is not set
# CONFIG_CMD_UNZIP is not set
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADB is not set
@@ -60,9 +50,11 @@
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
-# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_SLEEP is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EROFS=y
+CONFIG_CMD_SQUASHFS=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
diff --git a/configs/rzg2_beacon_defconfig b/configs/rzg2_beacon_defconfig
index 4aabb1f..eebbaa9 100644
--- a/configs/rzg2_beacon_defconfig
+++ b/configs/rzg2_beacon_defconfig
@@ -3,7 +3,8 @@
CONFIG_TEXT_BASE=0x50000000
CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_ENV_OFFSET=0x0
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xFFFFE000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a774a1-beacon-rzg2m-kit"
CONFIG_RCAR_GEN3=y
@@ -65,6 +66,7 @@
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig
index 2bd4eea..dd0582d 100644
--- a/configs/sandbox64_defconfig
+++ b/configs/sandbox64_defconfig
@@ -267,6 +267,7 @@
CONFIG_TPM=y
CONFIG_ERRNO_STR=y
CONFIG_GETOPT=y
+CONFIG_EFI_RT_VOLATILE_STORE=y
CONFIG_EFI_SECURE_BOOT=y
CONFIG_TEST_FDTDEC=y
CONFIG_UNIT_TEST=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 93b52f2..da8c197 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -348,6 +348,7 @@
CONFIG_TPM=y
CONFIG_ERRNO_STR=y
CONFIG_GETOPT=y
+CONFIG_EFI_RT_VOLATILE_STORE=y
CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
CONFIG_EFI_CAPSULE_ON_DISK=y
CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
diff --git a/configs/sige7-rk3588_defconfig b/configs/sige7-rk3588_defconfig
new file mode 100644
index 0000000..d15fc09
--- /dev/null
+++ b/configs/sige7-rk3588_defconfig
@@ -0,0 +1,93 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-armsom-sige7"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_SPL_SERIAL=y
+CONFIG_TARGET_SIGE7_RK3588=y
+CONFIG_DEBUG_UART_BASE=0xFEB50000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-armsom-sige7.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_AHCI_PCI=y
+CONFIG_DWC_AHCI=y
+CONFIG_SPL_CLK=y
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHYLIB=y
+CONFIG_RTL8169=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_SCSI=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_SPL_USB_DWC3_GENERIC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_LAN75XX=y
+CONFIG_USB_ETHER_LAN78XX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/silinux_ek874_defconfig b/configs/silinux_ek874_defconfig
index 4c6009d..d1b1c03 100644
--- a/configs/silinux_ek874_defconfig
+++ b/configs/silinux_ek874_defconfig
@@ -68,6 +68,7 @@
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_REALTEK=y
CONFIG_RENESAS_RAVB=y
CONFIG_DM_REGULATOR=y
diff --git a/configs/smdkc100_defconfig b/configs/smdkc100_defconfig
index 54a0379..256190d 100644
--- a/configs/smdkc100_defconfig
+++ b/configs/smdkc100_defconfig
@@ -39,3 +39,4 @@
CONFIG_MTD=y
CONFIG_SAMSUNG_ONENAND=y
CONFIG_SMC911X=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/snow_defconfig b/configs/snow_defconfig
index 3a617c6..2c07571 100644
--- a/configs/snow_defconfig
+++ b/configs/snow_defconfig
@@ -88,6 +88,7 @@
CONFIG_SOUND_WM8994=y
CONFIG_EXYNOS_SPI=y
CONFIG_TPM_TIS_INFINEON=y
+# CONFIG_TPM_V2 is not set
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig
index f0a364a..0fff908 100644
--- a/configs/socfpga_is1_defconfig
+++ b/configs/socfpga_is1_defconfig
@@ -68,3 +68,4 @@
CONFIG_CADENCE_QSPI=y
# CONFIG_SPL_WDT is not set
CONFIG_SYS_TIMER_COUNTS_DOWN=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index 603b744..c415248 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -67,6 +67,7 @@
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/sonoff-ihost-rv1126_defconfig b/configs/sonoff-ihost-rv1126_defconfig
index dfc71b1..4890644 100644
--- a/configs/sonoff-ihost-rv1126_defconfig
+++ b/configs/sonoff-ihost-rv1126_defconfig
@@ -5,7 +5,7 @@
CONFIG_SYS_ARCH_TIMER=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_NR_DRAM_BANKS=2
-CONFIG_DEFAULT_DEVICE_TREE="rv1126-sonoff-ihost"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rv1126-sonoff-ihost"
CONFIG_SYS_MONITOR_LEN=614400
CONFIG_ROCKCHIP_RV1126=y
CONFIG_TARGET_RV1126_SONOFF_IHOST=y
diff --git a/configs/stm32mp13_dhcor_defconfig b/configs/stm32mp13_dhcor_defconfig
new file mode 100644
index 0000000..fb3d86d
--- /dev/null
+++ b/configs/stm32mp13_dhcor_defconfig
@@ -0,0 +1,148 @@
+CONFIG_ARM=y
+CONFIG_ARCH_STM32MP=y
+CONFIG_TFABOOT=y
+CONFIG_SYS_MALLOC_F_LEN=0x1c0000
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0400000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x3E0000
+CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_DEFAULT_DEVICE_TREE="stm32mp135f-dhcor-dhsbc"
+CONFIG_STM32MP13X=y
+CONFIG_DDR_CACHEABLE_SIZE=0x8000000
+CONFIG_CMD_STM32KEY=y
+CONFIG_TARGET_ST_STM32MP13X=y
+CONFIG_ENV_OFFSET_REDUND=0x3F0000
+CONFIG_CMD_STM32PROG=y
+CONFIG_STM32MP15_PWR=y
+# CONFIG_ARMV7_NONSEC is not set
+CONFIG_SYS_LOAD_ADDR=0xc2000000
+CONFIG_SYS_MEMTEST_START=0xc0000000
+CONFIG_SYS_MEMTEST_END=0xc4000000
+CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTSTAGE_RECORD_COUNT=100
+CONFIG_BOOTDELAY=3
+CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_PROMPT="STM32MP> "
+# CONFIG_CMD_ELF is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_EXPORTENV is not set
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_UNZIP=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_LSBLK=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_CAT=y
+CONFIG_CMD_SETEXPR_FMT=y
+CONFIG_CMD_XXD=y
+CONFIG_CMD_DHCP6=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_SYS_DISABLE_AUTOLOAD=y
+CONFIG_CMD_WGET=y
+CONFIG_CMD_BOOTCOUNT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_RNG=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_BTRFS=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_LOG=y
+CONFIG_CMD_UBI=y
+# CONFIG_ISO_PARTITION is not set
+CONFIG_OF_LIVE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_SPI_MAX_HZ=50000000
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_IP_DEFRAG=y
+CONFIG_TFTP_TSIZE=y
+CONFIG_PROT_TCP_SACK=y
+CONFIG_IPV6=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000
+CONFIG_CLK_SCMI=y
+CONFIG_SET_DFU_ALT_INFO=y
+CONFIG_GPIO_HOG=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_STM32F7=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_STM32_FMC2_EBI=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_STM32_SDMMC2=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_PHY=y
+CONFIG_PHY_STM32_USBPHYC=y
+CONFIG_PINCONF=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_STPMIC1=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_REGULATOR_STPMIC1=y
+CONFIG_DM_REGULATOR_SCMI=y
+CONFIG_RESET_SCMI=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_STM32=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_STM32=y
+CONFIG_SERIAL_RX_BUFFER=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_STM32_QSPI=y
+CONFIG_STM32_SPI=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+# CONFIG_OPTEE_TA_AVB is not set
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_ONBOARD_HUB=y
+CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=2000
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="dh"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0483
+CONFIG_USB_GADGET_PRODUCT_NUM=0x5720
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_WDT=y
+CONFIG_WDT_STM32MP=y
+CONFIG_FAT_WRITE=y
+CONFIG_ERRNO_STR=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig
index 8442f0b..c3e6b09 100644
--- a/configs/stm32mp15_dhcom_basic_defconfig
+++ b/configs/stm32mp15_dhcom_basic_defconfig
@@ -133,6 +133,7 @@
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_DWC_ETH_QOS=y
CONFIG_KS8851_MLL=y
CONFIG_PHY=y
diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig
index 91b64f7..1eac11b 100644
--- a/configs/stm32mp15_dhcor_basic_defconfig
+++ b/configs/stm32mp15_dhcor_basic_defconfig
@@ -131,6 +131,7 @@
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DWC_ETH_QOS=y
diff --git a/configs/stm32mp25_defconfig b/configs/stm32mp25_defconfig
index 9fbd7eb..87038cc 100644
--- a/configs/stm32mp25_defconfig
+++ b/configs/stm32mp25_defconfig
@@ -48,6 +48,7 @@
CONFIG_WDT_STM32MP=y
CONFIG_WDT_ARM_SMC=y
CONFIG_ERRNO_STR=y
+# CONFIG_EFI_LOADER is not set
# CONFIG_LMB_USE_MAX_REGIONS is not set
CONFIG_LMB_MEMORY_REGIONS=2
CONFIG_LMB_RESERVED_REGIONS=32
diff --git a/configs/surface-rt_defconfig b/configs/surface-rt_defconfig
new file mode 100644
index 0000000..2326d24
--- /dev/null
+++ b/configs/surface-rt_defconfig
@@ -0,0 +1,80 @@
+CONFIG_ARM=y
+CONFIG_ARCH_TEGRA=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_CMDLINE_TAG=y
+CONFIG_INITRD_TAG=y
+CONFIG_TEXT_BASE=0x80110000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SIZE=0x3000
+CONFIG_ENV_OFFSET=0xFFFFD000
+CONFIG_DEFAULT_DEVICE_TREE="tegra30-microsoft-surface-rt"
+CONFIG_SPL_TEXT_BASE=0x80108000
+CONFIG_SPL_STACK=0x800ffffc
+CONFIG_TEGRA30=y
+CONFIG_TARGET_SURFACE_RT=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_BUTTON_CMD=y
+CONFIG_BOOTDELAY=0
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_KEYED_CTRLC=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_PBSIZE=2084
+CONFIG_SPL_FOOTPRINT_LIMIT=y
+CONFIG_SPL_MAX_FOOTPRINT=0x8000
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
+CONFIG_SYS_PROMPT="Tegra30 (Surface RT) # "
+# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
+CONFIG_CMD_BOOTMENU=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_UMS_ABORT_KEYED=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PAUSE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_PART=1
+CONFIG_BUTTON=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x91000000
+CONFIG_FASTBOOT_BUF_SIZE=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_GPIO_HOG=y
+CONFIG_SYS_I2C_TEGRA=y
+CONFIG_BUTTON_KEYBOARD=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_TPS65910=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_TPS65911=y
+CONFIG_PWM_TEGRA=y
+CONFIG_SYS_NS16550=y
+CONFIG_TEGRA20_SLINK=y
+CONFIG_SYSRESET_TPS65910=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_LOGO is not set
+CONFIG_VIDEO_TEGRA20=y
diff --git a/configs/synquacer_developerbox_defconfig b/configs/synquacer_developerbox_defconfig
index 2a0407d..7e1aeac 100644
--- a/configs/synquacer_developerbox_defconfig
+++ b/configs/synquacer_developerbox_defconfig
@@ -11,7 +11,6 @@
CONFIG_DEFAULT_DEVICE_TREE="synquacer-sc2a11-developerbox"
CONFIG_SYS_LOAD_ADDR=0x80000000
CONFIG_TARGET_DEVELOPERBOX=y
-CONFIG_FWU_NUM_IMAGES_PER_BANK=1
CONFIG_AHCI=y
CONFIG_FIT=y
CONFIG_SYS_BOOTM_LEN=0x800000
@@ -97,3 +96,4 @@
CONFIG_EFI_IGNORE_OSINDICATIONS=y
CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
CONFIG_FWU_MULTI_BANK_UPDATE=y
+CONFIG_FWU_MDATA_V2=y
diff --git a/configs/theadorable_debug_defconfig b/configs/theadorable_debug_defconfig
index ed468b8..d237092 100644
--- a/configs/theadorable_debug_defconfig
+++ b/configs/theadorable_debug_defconfig
@@ -78,6 +78,7 @@
# CONFIG_MMC is not set
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
diff --git a/configs/thunderx_88xx_defconfig b/configs/thunderx_88xx_defconfig
index 247e32d..b754cc0 100644
--- a/configs/thunderx_88xx_defconfig
+++ b/configs/thunderx_88xx_defconfig
@@ -36,3 +36,4 @@
# CONFIG_MMC is not set
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_SKIP_INIT=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/tiger-rk3588_defconfig b/configs/tiger-rk3588_defconfig
new file mode 100644
index 0000000..8fcdd06
--- /dev/null
+++ b/configs/tiger-rk3588_defconfig
@@ -0,0 +1,113 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SPL_GPIO=y
+CONFIG_SF_DEFAULT_SPEED=24000000
+CONFIG_SF_DEFAULT_MODE=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-tiger-haikou"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_ROCKCHIP_BOOT_MODE_REG=0x0
+CONFIG_SPL_SERIAL=y
+CONFIG_TARGET_TIGER_RK3588=y
+CONFIG_DEBUG_UART_BASE=0xfeb50000
+CONFIG_DEBUG_UART_CLOCK=24000000
+# CONFIG_DEBUG_UART_BOARD_INIT is not set
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_BOOTMETH_VBE is not set
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-tiger-haikou.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_CYCLIC=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_ATF=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+# CONFIG_CMD_ELF is not set
+CONFIG_CMD_ADC=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SF is not set
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MII is not set
+# CONFIG_CMD_BLOCK_CACHE is not set
+# CONFIG_CMD_EFICONFIG is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EROFS=y
+CONFIG_CMD_SQUASHFS=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+# CONFIG_OF_TAG_MIGRATE is not set
+CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_GPIO=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_GPIO=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_SPL_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_SPL_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_SPL_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+# CONFIG_SPI_FLASH is not set
+CONFIG_SF_DEFAULT_BUS=5
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_SPL_RAM=y
+CONFIG_SCSI=y
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/transformer_t20_defconfig b/configs/transformer_t20_defconfig
new file mode 100644
index 0000000..13bb269
--- /dev/null
+++ b/configs/transformer_t20_defconfig
@@ -0,0 +1,82 @@
+CONFIG_ARM=y
+CONFIG_ARCH_TEGRA=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_CMDLINE_TAG=y
+CONFIG_INITRD_TAG=y
+CONFIG_TEXT_BASE=0x00110000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SIZE=0x3000
+CONFIG_ENV_OFFSET=0xFFFFD000
+CONFIG_DEFAULT_DEVICE_TREE="tegra20-asus-tf101"
+CONFIG_SPL_TEXT_BASE=0x00108000
+CONFIG_SPL_STACK=0xffffc
+CONFIG_TEGRA20=y
+CONFIG_TARGET_TRANSFORMER_T20=y
+CONFIG_TEGRA_ENABLE_UARTD=y
+CONFIG_CMD_EBTUPDATE=y
+CONFIG_SYS_LOAD_ADDR=0x2000000
+CONFIG_BUTTON_CMD=y
+CONFIG_BOOTDELAY=0
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_KEYED_CTRLC=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTCOMMAND="bootflow scan; poweroff"
+CONFIG_SYS_PBSIZE=2085
+CONFIG_SPL_FOOTPRINT_LIMIT=y
+CONFIG_SPL_MAX_FOOTPRINT=0x8000
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x90000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
+CONFIG_SYS_PROMPT="Tegra20 (Transformer) # "
+# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
+CONFIG_CMD_BOOTMENU=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_UMS_ABORT_KEYED=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PAUSE=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_PART=2
+CONFIG_BUTTON=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x11000000
+CONFIG_FASTBOOT_BUF_SIZE=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_SYS_I2C_TEGRA=y
+CONFIG_BUTTON_KEYBOARD=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_PWM_TEGRA=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="ASUS"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0b05
+CONFIG_USB_GADGET_PRODUCT_NUM=0x4e0f
+CONFIG_CI_UDC=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_LOGO is not set
+# CONFIG_VIDEO_BPP8 is not set
+CONFIG_VIDEO_TEGRA20=y
diff --git a/configs/transformer_t30_defconfig b/configs/transformer_t30_defconfig
index 11a552d..1ebdb31 100644
--- a/configs/transformer_t30_defconfig
+++ b/configs/transformer_t30_defconfig
@@ -20,7 +20,7 @@
CONFIG_AUTOBOOT_KEYED_CTRLC=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_BOOTCOMMAND="setenv boot_targets usb mmc1 mmc0; bootflow scan; poweroff"
+CONFIG_BOOTCOMMAND="bootflow scan; poweroff"
CONFIG_SYS_PBSIZE=2084
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x8000
diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig
index 9753e27..c8756a3 100644
--- a/configs/turris_omnia_defconfig
+++ b/configs/turris_omnia_defconfig
@@ -10,6 +10,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000
CONFIG_TARGET_TURRIS_OMNIA=y
+CONFIG_DDR_IMMUTABLE_DEBUG_SETTINGS=y
CONFIG_DDR_RESET_ON_TRAINING_FAILURE=y
CONFIG_MVEBU_EFUSE_VHV_GPIO="mcu_56"
CONFIG_MVEBU_EFUSE_VHV_GPIO_ACTIVE_LOW=y
@@ -54,6 +55,8 @@
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
CONFIG_SYS_MAXARGS=32
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_EEPROM_LAYOUT=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_SHA1SUM=y
@@ -89,6 +92,7 @@
CONFIG_AHCI_PCI=y
CONFIG_AHCI_MVEBU=y
CONFIG_DM_PCA953X=y
+CONFIG_I2C_EEPROM=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_MV=y
CONFIG_DM_MTD=y
@@ -96,9 +100,11 @@
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_FIXED=y
CONFIG_DM_DSA=y
+CONFIG_DM_ETH_PHY=y
CONFIG_PHY_GIGE=y
CONFIG_MV88E6XXX=y
CONFIG_MVNETA=y
@@ -123,4 +129,3 @@
CONFIG_USB_EHCI_HCD=y
CONFIG_WDT=y
CONFIG_WDT_ORION=y
-CONFIG_EXT4_WRITE=y
diff --git a/configs/verdin-am62_r5_defconfig b/configs/verdin-am62_r5_defconfig
index 06c63fa..8266a7f 100644
--- a/configs/verdin-am62_r5_defconfig
+++ b/configs/verdin-am62_r5_defconfig
@@ -23,7 +23,6 @@
CONFIG_SPL_BSS_START_ADDR=0x43c3b000
CONFIG_SPL_BSS_MAX_SIZE=0x3000
CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000
CONFIG_SPL_SIZE_LIMIT=0x3A7F0
CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x3500
CONFIG_SPL_LIBDISK_SUPPORT=y
diff --git a/configs/xilinx_versal_mini_defconfig b/configs/xilinx_versal_mini_defconfig
index 9d3924c..b97bf5e 100644
--- a/configs/xilinx_versal_mini_defconfig
+++ b/configs/xilinx_versal_mini_defconfig
@@ -62,4 +62,5 @@
# CONFIG_MMC is not set
CONFIG_ARM_DCC=y
# CONFIG_GZIP is not set
+# CONFIG_EFI_LOADER is not set
# CONFIG_LMB is not set
diff --git a/configs/xilinx_versal_mini_ospi_defconfig b/configs/xilinx_versal_mini_ospi_defconfig
index 7a11035..8f16259 100644
--- a/configs/xilinx_versal_mini_ospi_defconfig
+++ b/configs/xilinx_versal_mini_ospi_defconfig
@@ -72,4 +72,5 @@
CONFIG_HAS_CQSPI_REF_CLK=y
CONFIG_CQSPI_REF_CLK=200000000
CONFIG_CADENCE_OSPI_VERSAL=y
+# CONFIG_EFI_LOADER is not set
# CONFIG_LMB is not set
diff --git a/configs/xilinx_versal_mini_qspi_defconfig b/configs/xilinx_versal_mini_qspi_defconfig
index 58945a1..8fbde1c 100644
--- a/configs/xilinx_versal_mini_qspi_defconfig
+++ b/configs/xilinx_versal_mini_qspi_defconfig
@@ -76,4 +76,5 @@
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_ZYNQMP_GQSPI=y
+# CONFIG_EFI_LOADER is not set
# CONFIG_LMB is not set
diff --git a/configs/xilinx_versal_net_mini_defconfig b/configs/xilinx_versal_net_mini_defconfig
index 7dac1ec..d6ebd08 100644
--- a/configs/xilinx_versal_net_mini_defconfig
+++ b/configs/xilinx_versal_net_mini_defconfig
@@ -71,4 +71,5 @@
CONFIG_ARM_DCC=y
CONFIG_PL01X_SERIAL=y
# CONFIG_GZIP is not set
+# CONFIG_EFI_LOADER is not set
# CONFIG_LMB is not set
diff --git a/configs/xilinx_versal_net_mini_ospi_defconfig b/configs/xilinx_versal_net_mini_ospi_defconfig
index d78c9f8..872a4a5 100644
--- a/configs/xilinx_versal_net_mini_ospi_defconfig
+++ b/configs/xilinx_versal_net_mini_ospi_defconfig
@@ -70,4 +70,5 @@
CONFIG_HAS_CQSPI_REF_CLK=y
CONFIG_CQSPI_REF_CLK=200000000
CONFIG_CADENCE_OSPI_VERSAL=y
+# CONFIG_EFI_LOADER is not set
# CONFIG_LMB is not set
diff --git a/configs/xilinx_versal_net_mini_qspi_defconfig b/configs/xilinx_versal_net_mini_qspi_defconfig
index b0567f8..00319e0 100644
--- a/configs/xilinx_versal_net_mini_qspi_defconfig
+++ b/configs/xilinx_versal_net_mini_qspi_defconfig
@@ -74,4 +74,5 @@
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_ZYNQMP_GQSPI=y
+# CONFIG_EFI_LOADER is not set
# CONFIG_LMB is not set
diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig
index 40c6a29..53ef81e 100644
--- a/configs/xilinx_versal_net_virt_defconfig
+++ b/configs/xilinx_versal_net_virt_defconfig
@@ -8,6 +8,7 @@
CONFIG_DEFAULT_DEVICE_TREE="xilinx-versal-net-virt"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
+CONFIG_ENV_OFFSET_REDUND=0x7F00000
CONFIG_CMD_FRU=y
CONFIG_SYS_LOAD_ADDR=0x8000000
CONFIG_SYS_MEMTEST_START=0x00000000
@@ -26,6 +27,7 @@
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_CLOCKS=y
CONFIG_SYS_PROMPT="Versal NET> "
+CONFIG_CMD_SMBIOS=y
CONFIG_CMD_BOOTMENU=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_NVEDIT_EFI=y
@@ -72,6 +74,7 @@
CONFIG_TFTP_BLOCKSIZE=4096
CONFIG_CLK_VERSAL=y
CONFIG_DFU_RAM=y
+CONFIG_ARM_FFA_TRANSPORT=y
CONFIG_ZYNQ_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
@@ -80,6 +83,7 @@
CONFIG_DM_MAILBOX=y
CONFIG_ZYNQMP_IPI=y
CONFIG_MISC=y
+CONFIG_NVMEM=y
CONFIG_I2C_EEPROM=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
@@ -101,6 +105,7 @@
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig
index c9b8a6d..915f0b9 100644
--- a/configs/xilinx_versal_virt_defconfig
+++ b/configs/xilinx_versal_virt_defconfig
@@ -28,6 +28,7 @@
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_CLOCKS=y
CONFIG_SYS_PROMPT="Versal> "
+CONFIG_CMD_SMBIOS=y
CONFIG_CMD_BOOTMENU=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_NVEDIT_EFI=y
@@ -74,6 +75,7 @@
CONFIG_DFU_TIMEOUT=y
CONFIG_DFU_RAM=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1800000
+CONFIG_ARM_FFA_TRANSPORT=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_VERSALPL=y
CONFIG_DM_I2C=y
@@ -83,6 +85,7 @@
CONFIG_DM_MAILBOX=y
CONFIG_ZYNQMP_IPI=y
CONFIG_MISC=y
+CONFIG_NVMEM=y
CONFIG_I2C_EEPROM=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
@@ -102,6 +105,7 @@
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_ADIN=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig
index f30fbdf..9be904f 100644
--- a/configs/xilinx_zynq_virt_defconfig
+++ b/configs/xilinx_zynq_virt_defconfig
@@ -107,6 +107,7 @@
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_MISC=y
+CONFIG_NVMEM=y
CONFIG_I2C_EEPROM=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig
index ba42f0c..58e88b2 100644
--- a/configs/xilinx_zynqmp_kria_defconfig
+++ b/configs/xilinx_zynqmp_kria_defconfig
@@ -54,6 +54,7 @@
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_CMD_SMBIOS=y
CONFIG_CMD_BOOTMENU=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_NVEDIT_EFI=y
@@ -134,6 +135,7 @@
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_ARM_FFA_TRANSPORT=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
CONFIG_GPIO_HOG=y
@@ -158,6 +160,7 @@
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_ADIN=y
CONFIG_PHY_TI_DP83867=y
CONFIG_PHY_XILINX_GMII2RGMII=y
diff --git a/configs/xilinx_zynqmp_mini_defconfig b/configs/xilinx_zynqmp_mini_defconfig
index 7fdd2ee..4b45074 100644
--- a/configs/xilinx_zynqmp_mini_defconfig
+++ b/configs/xilinx_zynqmp_mini_defconfig
@@ -60,4 +60,5 @@
CONFIG_ARM_DCC=y
CONFIG_PANIC_HANG=y
# CONFIG_GZIP is not set
+# CONFIG_EFI_LOADER is not set
# CONFIG_LMB is not set
diff --git a/configs/xilinx_zynqmp_mini_nand_defconfig b/configs/xilinx_zynqmp_mini_nand_defconfig
index d2e920f..b471953 100644
--- a/configs/xilinx_zynqmp_mini_nand_defconfig
+++ b/configs/xilinx_zynqmp_mini_nand_defconfig
@@ -60,4 +60,5 @@
CONFIG_ARM_DCC=y
CONFIG_PANIC_HANG=y
# CONFIG_GZIP is not set
+# CONFIG_EFI_LOADER is not set
# CONFIG_LMB is not set
diff --git a/configs/xilinx_zynqmp_mini_nand_single_defconfig b/configs/xilinx_zynqmp_mini_nand_single_defconfig
index 31f6473..7ede176 100644
--- a/configs/xilinx_zynqmp_mini_nand_single_defconfig
+++ b/configs/xilinx_zynqmp_mini_nand_single_defconfig
@@ -59,4 +59,5 @@
CONFIG_ARM_DCC=y
CONFIG_PANIC_HANG=y
# CONFIG_GZIP is not set
+# CONFIG_EFI_LOADER is not set
# CONFIG_LMB is not set
diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig
index 957ae07..0d79ece 100644
--- a/configs/xilinx_zynqmp_mini_qspi_defconfig
+++ b/configs/xilinx_zynqmp_mini_qspi_defconfig
@@ -92,4 +92,5 @@
CONFIG_ZYNQMP_GQSPI=y
CONFIG_PANIC_HANG=y
# CONFIG_GZIP is not set
+# CONFIG_EFI_LOADER is not set
# CONFIG_LMB is not set
diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig
index ee87beb..fa912ae 100644
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -52,6 +52,7 @@
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_CMD_SMBIOS=y
CONFIG_CMD_BOOTMENU=y
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_THOR_RESET_OFF=y
@@ -134,6 +135,7 @@
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_ARM_FFA_TRANSPORT=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
CONFIG_GPIO_HOG=y
@@ -147,6 +149,7 @@
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_MISC=y
+CONFIG_NVMEM=y
CONFIG_I2C_EEPROM=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
@@ -169,6 +172,7 @@
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_ADIN=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_MICREL=y
diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig
index 48473d7..750ea0d 100644
--- a/configs/zynq_cse_nand_defconfig
+++ b/configs/zynq_cse_nand_defconfig
@@ -79,4 +79,5 @@
CONFIG_ARM_DCC=y
CONFIG_SYS_TIMER_COUNTS_DOWN=y
# CONFIG_GZIP is not set
+# CONFIG_EFI_LOADER is not set
# CONFIG_LMB is not set
diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig
index 9f2b738..3155fe0 100644
--- a/configs/zynq_cse_nor_defconfig
+++ b/configs/zynq_cse_nor_defconfig
@@ -83,4 +83,5 @@
CONFIG_ARM_DCC=y
CONFIG_SYS_TIMER_COUNTS_DOWN=y
# CONFIG_GZIP is not set
+# CONFIG_EFI_LOADER is not set
# CONFIG_LMB is not set
diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig
index 5b861bd..f2e1aa6 100644
--- a/configs/zynq_cse_qspi_defconfig
+++ b/configs/zynq_cse_qspi_defconfig
@@ -93,4 +93,5 @@
CONFIG_ZYNQ_QSPI=y
CONFIG_SYS_TIMER_COUNTS_DOWN=y
# CONFIG_GZIP is not set
+# CONFIG_EFI_LOADER is not set
# CONFIG_LMB is not set
diff --git a/disk/Kconfig b/disk/Kconfig
index 8549695..ffa835e 100644
--- a/disk/Kconfig
+++ b/disk/Kconfig
@@ -116,7 +116,7 @@
number.
config EFI_PARTITION_ENTRIES_OFF
- int "Offset (in bytes) of the EFI partition entries"
+ int "Offset (in bytes) of the EFI partition entries"
depends on EFI_PARTITION
default 0
help
diff --git a/doc/arch/arm64.rst b/doc/arch/arm64.rst
index 7c07135..19662be 100644
--- a/doc/arch/arm64.rst
+++ b/doc/arch/arm64.rst
@@ -48,6 +48,55 @@
6. CONFIG_ARM64 instead of CONFIG_ARMV8 is used to distinguish aarch64 and
aarch32 specific codes.
+MMU
+---
+
+U-Boot uses a simple page table for MMU setup. It uses the smallest number of bits
+possible for the virtual address based on the maximum memory address (see the logic
+in ``get_tcr()``). If this is less than 39 bits, the MMU will use only 3 levels for
+address translation.
+
+As with all platforms, U-Boot on ARM64 uses a 1:1 mapping of virtual to physical addresses.
+In general, the memory map is expected to remain static once the MMU is enabled.
+
+Software pagetable walker
+^^^^^^^^^^^^^^^^^^^^^^^^^
+
+It is possible to debug the pagetable generated by U-Boot with the built in
+``dump_pagetable()`` and ``walk_pagetable()`` functions (the former being a simple
+wrapper for the latter). For example the following can be added to ``setup_all_pgtables()``
+after the first call to ``setup_pgtables()``:
+
+.. code-block:: c
+
+ dump_pagetable(gd->arch.tlb_addr, get_tcr(NULL, NULL));
+
+.. kernel-doc:: arch/arm/cpu/armv8/cache_v8.c
+ :identifiers: __pagetable_walk pagetable_print_entry
+
+The pagetable walker can be used as follows:
+
+.. kernel-doc:: arch/arm/include/asm/armv8/mmu.h
+ :identifiers: pte_walker_cb_t walk_pagetable dump_pagetable
+
+This will result in a print like the following:
+
+.. code-block:: text
+
+ Walking pagetable at 000000017df90000, va_bits: 36. Using 3 levels
+ [0x17df91000] | Table | |
+ [0x17df92000] | Table | |
+ [0x000001000 - 0x000200000] | Pages | Device-nGnRnE | Non-shareable
+ [0x000200000 - 0x040000000] | Block | Device-nGnRnE | Non-shareable
+ [0x040000000 - 0x080000000] | Block | Device-nGnRnE | Non-shareable
+ [0x080000000 - 0x140000000] | Block | Normal | Inner-shareable
+ [0x17df93000] | Table | |
+ [0x140000000 - 0x17de00000] | Block | Normal | Inner-shareable
+ [0x17df94000] | Table | |
+ [0x17de00000 - 0x17dfa0000] | Pages | Normal | Inner-shareable
+
+For more information, please refer to the additional function documentation in
+``arch/arm/include/asm/armv8/mmu.h``.
Contributors
------------
diff --git a/doc/board/asus/index.rst b/doc/board/asus/index.rst
index 87e535f..2b10328 100644
--- a/doc/board/asus/index.rst
+++ b/doc/board/asus/index.rst
@@ -7,4 +7,5 @@
:maxdepth: 2
grouper_common
+ transformer_t20
transformer_t30
diff --git a/doc/board/asus/transformer_t20.rst b/doc/board/asus/transformer_t20.rst
new file mode 100644
index 0000000..d4bc12d
--- /dev/null
+++ b/doc/board/asus/transformer_t20.rst
@@ -0,0 +1,129 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for the ASUS Eee Pad Transformer device family
+=====================================================
+
+``DISCLAMER!`` Moving your ASUS Eee Pad Transformer/Slider to use U-Boot
+assumes replacement of the vendor ASUS bootloader. Vendor Android firmwares
+will no longer be able to run on the device. This replacement IS reversible.
+
+Quick Start
+-----------
+
+- Build U-Boot
+- Process U-Boot
+- Flashing U-Boot into the eMMC
+- Boot
+- Self Upgrading
+
+Build U-Boot
+------------
+
+Device support is implemented by applying config fragment to a generic board
+defconfig. Valid fragments are ``tf101.config``, ``tf101g.config`` and
+``sl101.config``.
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=arm-linux-gnueabi-
+ $ make transformer_t20_defconfig tf101.config # For TF101
+ $ make
+
+After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin``
+image, ready for further processing.
+
+Process U-Boot
+--------------
+
+``DISCLAMER!`` All questions related to the re-crypt work should be asked
+in re-crypt repo issues. NOT HERE!
+
+re-crypt is a tool that processes the ``u-boot-dtb-tegra.bin`` binary into form
+usable by device. This process is required only on the first installation or
+to recover the device in case of a failed update.
+
+Permanent installation can be performed either by using the nv3p protocol or by
+pre-loading just built U-Boot into RAM.
+
+Processing for the NV3P protocol
+********************************
+
+.. code-block:: bash
+
+ $ git clone https://gitlab.com/grate-driver/re-crypt.git
+ $ cd re-crypt # place your u-boot-dtb-tegra.bin here
+ $ ./re-crypt.py --dev tf101
+
+The script will produce a ``repart-block.bin`` ready to flash.
+
+Processing for pre-loaded U-Boot
+********************************
+
+The procedure is the same, but the ``--split`` argument is used with the
+``re-crypt.py``. The script will produce ``bct.img`` and ``ebt.img`` ready
+to flash.
+
+Flashing U-Boot into the eMMC
+-----------------------------
+
+``DISCLAMER!`` All questions related to NvFlash should be asked in the proper
+place. NOT HERE! Flashing U-Boot will erase all eMMC, so make a backup before!
+
+Permanent installation can be performed either by using the nv3p protocol or by
+pre-loading just built U-Boot into RAM.
+
+Flashing with the NV3P protocol
+*******************************
+
+Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can
+enter it either by using ``wheelie`` with the correct ``blob.bin`` file or by
+pre-loading vendor bootloader with the Fusée Gelée.
+
+With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in
+encrypted state in form, which can just be written RAW at the start of eMMC.
+
+.. code-block:: bash
+
+ $ wheelie --blob blob.bin
+ $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin
+
+When flashing is done, reboot the device.
+
+Flashing with a pre-loaded U-Boot
+*********************************
+
+U-Boot pre-loaded into RAM acts the same as when it was booted "cold". Currently
+U-Boot supports bootmenu entry fastboot, which allows to write a processed copy
+of U-Boot permanently into eMMC.
+
+While pre-loading U-Boot, hold the ``volume down`` button which will trigger
+the bootmenu. There, select ``fastboot`` using the volume and power buttons.
+After, on host PC, do:
+
+.. code-block:: bash
+
+ $ fastboot flash 0.1 bct.img
+ $ fastboot flash 0.2 ebt.img
+ $ fastboot reboot
+
+Device will reboot.
+
+Boot
+----
+
+To boot Linux, U-Boot will look for an ``extlinux.conf`` on MicroSD and then on
+eMMC. Additionally, if the Volume Down button is pressed while booting, the
+device will enter bootmenu. Bootmenu contains entries to mount MicroSD and eMMC
+as mass storage, fastboot, reboot, reboot RCM, poweroff, enter U-Boot console
+and update bootloader (check the next chapter).
+
+Flashing ``repart-block.bin`` eliminates vendor restrictions on eMMC and allows
+the user to use/partition it in any way the user desires.
+
+Self Upgrading
+--------------
+
+Place your ``u-boot-dtb-tegra.bin`` on the first partition of the MicroSD card
+and insert it into the tablet. Enter bootmenu, choose update the bootloader
+option with the Power button and U-Boot should update itself. Once the process
+is completed, U-Boot will ask to press any button to reboot.
diff --git a/doc/board/beagle/am62x_beagleplay.rst b/doc/board/beagle/am62x_beagleplay.rst
index cdc6102..01f04be 100644
--- a/doc/board/beagle/am62x_beagleplay.rst
+++ b/doc/board/beagle/am62x_beagleplay.rst
@@ -71,11 +71,10 @@
Target Images
-------------
-Copy the below images to an SD card and boot:
+Copy these images to an SD card and boot:
-* tiboot3-am62x-gp-evm.bin from R5 build as tiboot3.bin
-* tispl.bin_unsigned from Cortex-A build as tispl.bin
-* u-boot.img_unsigned from Cortex-A build as u-boot.img
+* tiboot3.bin from Cortex-R5 build.
+* tispl.bin and u-boot.img from Cortex-A build
Image formats
-------------
diff --git a/doc/board/emulation/index.rst b/doc/board/emulation/index.rst
index d3d6b8f..98a0b26 100644
--- a/doc/board/emulation/index.rst
+++ b/doc/board/emulation/index.rst
@@ -14,3 +14,4 @@
qemu-ppce500
qemu-riscv
qemu-x86
+ qemu-xtensa
diff --git a/doc/board/emulation/qemu-xtensa.rst b/doc/board/emulation/qemu-xtensa.rst
new file mode 100644
index 0000000..fff23c1
--- /dev/null
+++ b/doc/board/emulation/qemu-xtensa.rst
@@ -0,0 +1,33 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (C) 2024 Jiaxun Yang <jiaxun.yang@flygoat.com>
+
+QEMU Xtensa
+===========
+
+QEMU for Xtensa supports a special 'virt' machine designed for emulation and
+virtualization purposes. This document describes how to run U-Boot under it.
+
+The QEMU virt machine models a generic Xtensa virtual machine with PCI Bus
+and Xtensa ISS simcall semihosting support. It supports many different Xtensa
+CPU configuration. Currently, only dc233c variant is tested against U-Boot.
+
+Building U-Boot
+---------------
+Set the CROSS_COMPILE environment variable as usual, and run:
+
+ make qemu-xtensa-dc233c_defconfig
+ make
+
+Note that Xtensa's toolchain is bounded to CPU configuration, you must use
+the toolchain built for exactly the same CPU configuration as you selected
+in U-Boot.
+
+Running U-Boot
+--------------
+The minimal QEMU command line to get U-Boot up and running is:
+
+ qemu-system-xtensa -nographic -machine virt -cpu dc233c -semihosting -kernel ./u-boot.elf
+
+You many change cpu option to match your U-Boot CPU type configuration.
+semihosting option is mandatory because this is the only way to interact
+with U-Boot in command line.
diff --git a/doc/board/index.rst b/doc/board/index.rst
index 2340eeb..417c128 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -31,9 +31,11 @@
htc/index
intel/index
kontron/index
+ lenovo/index
lg/index
mediatek/index
microchip/index
+ microsoft/index
nxp/index
openpiton/index
phytec/index
@@ -58,5 +60,6 @@
ti/index
toradex/index
variscite/index
+ wexler/index
xen/index
xilinx/index
diff --git a/doc/board/lenovo/ideapad-yoga-11.rst b/doc/board/lenovo/ideapad-yoga-11.rst
new file mode 100644
index 0000000..94bf171
--- /dev/null
+++ b/doc/board/lenovo/ideapad-yoga-11.rst
@@ -0,0 +1,41 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for the Lenovo Ideapad Yoga 11 tablet
+============================================
+
+Quick Start
+-----------
+
+- Build U-Boot
+- Boot
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=arm-linux-gnueabi-
+ $ make ideapad-yoga-11_defconfig
+ $ make
+
+After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin``
+image, ready for loading.
+
+Boot
+----
+
+Currently, U-Boot can be preloaded into RAM via the Fusée Gelée. To enter
+RCM protocol use ``power`` and ``volume up`` key combination from powered
+off device. The host PC should recognize an APX device.
+
+Built U-Boot ``u-boot-dtb-tegra.bin`` can be loaded from fusee-tools
+directory with
+
+.. code-block:: bash
+
+ $ ./run_bootloader.sh -s T30 -t ./bct/ideapad-yoga-11.bct
+
+To boot Linux, U-Boot will look for an ``extlinux.conf`` on MicroSD and then on
+eMMC. Additionally, if the Volume Down button is pressed while loading, the
+device will enter bootmenu. Bootmenu contains entries to mount MicroSD and eMMC
+as mass storage, fastboot, reboot, reboot RCM, poweroffand enter U-Boot console.
diff --git a/doc/board/lenovo/index.rst b/doc/board/lenovo/index.rst
new file mode 100644
index 0000000..2ce457a
--- /dev/null
+++ b/doc/board/lenovo/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Lenovo
+=========
+
+.. toctree::
+ :maxdepth: 2
+
+ ideapad-yoga-11
diff --git a/doc/board/microsoft/index.rst b/doc/board/microsoft/index.rst
new file mode 100644
index 0000000..107f352
--- /dev/null
+++ b/doc/board/microsoft/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Microsoft
+=========
+
+.. toctree::
+ :maxdepth: 2
+
+ surface-rt
diff --git a/doc/board/microsoft/surface-rt.rst b/doc/board/microsoft/surface-rt.rst
new file mode 100644
index 0000000..b5645e7
--- /dev/null
+++ b/doc/board/microsoft/surface-rt.rst
@@ -0,0 +1,41 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for the Microsoft Surface RT tablet
+==========================================
+
+Quick Start
+-----------
+
+- Build U-Boot
+- Boot
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=arm-linux-gnueabi-
+ $ make surface-rt_defconfig
+ $ make
+
+After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin``
+image, ready for loading.
+
+Boot
+----
+
+Currently, U-Boot can be preloaded into RAM via the Fusée Gelée. To enter
+RCM protocol use ``power`` and ``volume up`` key combination from powered
+off device. The host PC should recognize an APX device.
+
+Built U-Boot ``u-boot-dtb-tegra.bin`` can be loaded from fusee-tools
+directory with
+
+.. code-block:: bash
+
+ $ ./run_bootloader.sh -s T30 -t ./bct/surface-rt.bct
+
+To boot Linux, U-Boot will look for an ``extlinux.conf`` on MicroSD and then on
+eMMC. Additionally, if the Volume Down button is pressed while loading, the
+device will enter bootmenu. Bootmenu contains entries to mount MicroSD and eMMC
+as mass storage, fastboot, reboot, reboot RCM, poweroffand enter U-Boot console.
diff --git a/doc/board/phytec/phycore-am62x.rst b/doc/board/phytec/phycore-am62x.rst
index bc6d524..a7ce2c5 100644
--- a/doc/board/phytec/phycore-am62x.rst
+++ b/doc/board/phytec/phycore-am62x.rst
@@ -110,14 +110,31 @@
.. code-block:: bash
- sf probe
+ mtd list
fatload mmc 1 ${loadaddr} tiboot3.bin
- sf update $loadaddr 0x0 $filesize
+ mtd write ospi.tiboot3 ${loadaddr} 0 ${filesize}
fatload mmc 1 ${loadaddr} tispl.bin
- sf update $loadaddr 0x80000 $filesize
+ mtd write ospi.tispl ${loadaddr} 0 ${filesize}
fatload mmc 1 ${loadaddr} u-boot.img
- sf update $loadaddr 0x280000 $filesize
+ mtd write ospi.u-boot ${loadaddr} 0 ${filesize}
+UART based boot
+---------------
+
+To boot the board via UART, set the switches to UART mode and connect to the
+micro USB port labeled as "Debug UART". After power-on the build artifacts
+needs to be uploaded one by one with a tool like sz.
+
+Example bash script sequence for running on a Linux host PC feeding all boot
+artifacts needed to the device. Assuming the host uses /dev/ttyUSB0 as
+the main domain serial port:
+
+.. prompt:: bash $
+
+ stty -F /dev/ttyUSB0 115200
+ sb --xmodem tiboot3.bin > /dev/ttyUSB0 < /dev/ttyUSB0
+ sb --ymodem tispl.bin > /dev/ttyUSB0 < /dev/ttyUSB0
+ sb --ymodem u-boot.img > /dev/ttyUSB0 < /dev/ttyUSB0
Boot Modes
----------
@@ -151,8 +168,12 @@
- 11011100
- 00000000
+ * - USB DFU
+ - 11001010
+ - 00100000
+
Further Information
-------------------
Please see :doc:`../ti/am62x_sk` chapter for further AM62 SoC related documentation
-and https://docs.phytec.com/phycore-am62x for vendor documentation.
+and https://docs.phytec.com/projects/yocto-phycore-am62x/en/latest/ for vendor documentation.
diff --git a/doc/board/phytec/phycore-am64x.rst b/doc/board/phytec/phycore-am64x.rst
index a27ad01..68d78ad 100644
--- a/doc/board/phytec/phycore-am64x.rst
+++ b/doc/board/phytec/phycore-am64x.rst
@@ -9,7 +9,7 @@
with different carrier boards. This module can come with different sizes and
models for DDR, eMMC, SPI NOR Flash and various SoCs from the AM64x family.
-A development Kit, called `phyBOARD-Lyra <https://www.phytec.com/product/phyboard-am64x>`_
+A development Kit, called `phyBOARD-Electra <https://www.phytec.com/product/phyboard-am64x>`_
is used as a carrier board reference design around the AM64x SoM.
Quickstart
@@ -111,14 +111,33 @@
.. code-block:: bash
- sf probe
+ mtd list
fatload mmc 1 ${loadaddr} tiboot3.bin
- sf update $loadaddr 0x0 $filesize
+ mtd write ospi.tiboot3 ${loadaddr} 0 ${filesize}
fatload mmc 1 ${loadaddr} tispl.bin
- sf update $loadaddr 0x80000 $filesize
+ mtd write ospi.tispl ${loadaddr} 0 ${filesize}
fatload mmc 1 ${loadaddr} u-boot.img
- sf update $loadaddr 0x280000 $filesize
+ mtd write ospi.u-boot ${loadaddr} 0 ${filesize}
+UART based boot
+---------------
+
+To boot the board via UART, set the switches to UART mode and connect to the
+micro USB port labeled as "Debug UART". After power-on the build artifacts
+needs to be uploaded one by one with a tool like sz.
+
+Example bash script sequence for running on a Linux host PC feeding all boot
+artifacts needed to the device. Assuming the host uses /dev/ttyUSB0 as
+the main domain serial port:
+
+.. prompt:: bash $
+
+ stty -F /dev/ttyUSB0 115200
+ sb --xmodem tiboot3.bin > /dev/ttyUSB0 < /dev/ttyUSB0
+ # Resend tiboot3.bin a 2nd time due to ErrataID:i2331
+ sb --xmodem tiboot3.bin > /dev/ttyUSB0 < /dev/ttyUSB0
+ sb --ymodem tispl.bin > /dev/ttyUSB0 < /dev/ttyUSB0
+ sb --ymodem u-boot.img > /dev/ttyUSB0 < /dev/ttyUSB0
Boot Modes
----------
@@ -156,4 +175,4 @@
-------------------
Please see :doc:`../ti/am64x_evm` chapter for further AM64 SoC related documentation
-and https://docs.phytec.com/phycore-am64x for vendor documentation.
+and https://docs.phytec.com/projects/yocto-phycore-am64x/en/latest/ for vendor documentation.
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index 9a726e9..eaf7167 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -104,6 +104,7 @@
- Pine64 SOQuartz on Blade (soquartz-blade-rk3566)
- Pine64 SOQuartz on CM4-IO (soquartz-cm4-rk3566)
- Pine64 SOQuartz on Model A (soquartz-model-a-rk3566)
+ - Powkiddy X55 (powkiddy-x55-rk3566)
- Radxa CM3 IO Board (radxa-cm3-io-rk3566)
* rk3568
@@ -118,16 +119,19 @@
- Radxa ROCK 3 Model A (rock-3a-rk3568)
* rk3588
+ - ArmSoM Sige7 (sige7-rk3588)
- Rockchip EVB (evb-rk3588)
- Edgeble Neural Compute Module 6A SoM - Neu6a (neu6a-io-rk3588)
- Edgeble Neural Compute Module 6B SoM - Neu6b (neu6b-io-rk3588)
- FriendlyElec NanoPC-T6 (nanopc-t6-rk3588)
- Generic RK3588S/RK3588 (generic-rk3588)
+ - Indiedroid Nova (nova-rk3588s)
- Pine64 QuartzPro64 (quartzpro64-rk3588)
- Radxa ROCK 5A (rock5a-rk3588s)
- Radxa ROCK 5B (rock5b-rk3588)
- Rockchip Toybrick TB-RK3588X (toybrick-rk3588)
- Theobroma Systems RK3588-SBC Jaguar (jaguar-rk3588)
+ - Theobroma Systems SOM-RK3588-Q7 - Tiger (tiger-rk3588)
- Turing Machines RK1 (turing-rk1-rk3588)
- Xunlong Orange Pi 5 (orangepi-5-rk3588s)
- Xunlong Orange Pi 5 Plus (orangepi-5-plus-rk3588)
diff --git a/doc/board/socionext/developerbox.rst b/doc/board/socionext/developerbox.rst
index 46712c3..863761c 100644
--- a/doc/board/socionext/developerbox.rst
+++ b/doc/board/socionext/developerbox.rst
@@ -116,6 +116,7 @@
CONFIG_FWU_NUM_BANKS=2
CONFIG_FWU_NUM_IMAGES_PER_BANK=1
CONFIG_CMD_FWU_METADATA=y
+ CONFIG_FWU_MDATA_V2=y
And build it::
@@ -129,7 +130,9 @@
By default, the CONFIG_FWU_NUM_BANKS and CONFIG_FWU_NUM_IMAGES_PER_BANKS are
set to 2 and 1 respectively. This uses FIP (Firmware Image Package) type image
which contains TF-A, U-Boot and OP-TEE (the OP-TEE is optional).
-You can use fiptool to compose the FIP image from those firmware images.
+You can use fiptool to compose the FIP image from those firmware
+images. There are two versions of the FWU metadata, of which the
+platform enables version 2 by default.
Rebuild SCP firmware
--------------------
@@ -194,7 +197,7 @@
These UUIDs are used for making a FWU metadata image.
-u-boot$ ./tools/mkfwumdata -i 1 -b 2 \
+u-boot$ ./tools/mkfwumdata -v 2 -i 1 -b 2 \
17e86d77-41f9-4fd7-87ec-a55df9842de5,10c36d7d-ca52-b843-b7b9-f9d6c501d108,5a66a702-99fd-4fef-a392-c26e261a2828,a8f868a1-6e5c-4757-878d-ce63375ef2c0 \
../devbox-fwu-mdata.img
diff --git a/doc/board/starfive/index.rst b/doc/board/starfive/index.rst
index d369b98..72ab6dd 100644
--- a/doc/board/starfive/index.rst
+++ b/doc/board/starfive/index.rst
@@ -8,4 +8,5 @@
milk-v_mars
milk-v_mars_cm
+ pine64_star64
visionfive2
diff --git a/doc/board/starfive/pine64_star64.rst b/doc/board/starfive/pine64_star64.rst
new file mode 100644
index 0000000..52e9a90
--- /dev/null
+++ b/doc/board/starfive/pine64_star64.rst
@@ -0,0 +1,201 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Pine64 Star64
+=============
+
+U-Boot for the Star64 uses the same U-Boot binaries as the VisionFive 2 board.
+In U-Boot SPL the actual board is detected and the device-tree patched
+accordingly.
+
+Building
+~~~~~~~~
+
+1. Add the RISC-V toolchain to your PATH.
+2. Setup ARCH & cross compilation environment variable:
+
+.. code-block:: none
+
+ export CROSS_COMPILE=<riscv64 toolchain prefix>
+
+The M-mode software OpenSBI provides the supervisor binary interface (SBI) and
+is responsible for the switch to S-Mode. It is a prerequisite to build U-Boot.
+Support for the JH7110 was introduced in OpenSBI 1.2. It is recommended to use
+a current release.
+
+.. code-block:: console
+
+ git clone https://github.com/riscv/opensbi.git
+ cd opensbi
+ make PLATFORM=generic FW_TEXT_START=0x40000000
+
+Now build the U-Boot SPL and U-Boot proper.
+
+.. code-block:: console
+
+ cd <U-Boot-dir>
+ make starfive_visionfive2_defconfig
+ make OPENSBI=$(opensbi_dir)/build/platform/generic/firmware/fw_dynamic.bin
+
+This will generate the U-Boot SPL image (spl/u-boot-spl.bin.normal.out) as well
+as the FIT image (u-boot.itb) with OpenSBI and U-Boot.
+
+Device-tree selection
+~~~~~~~~~~~~~~~~~~~~~
+
+U-Boot will set variable $fdtfile to starfive/jh7110-pine64-star64.dtb.
+
+To overrule this selection the variable can be set manually and saved in the
+environment
+
+::
+
+ env set fdtfile my_device-tree.dtb
+ env save
+
+or the configuration variable CONFIG_DEFAULT_FDT_FILE can be used to set to
+provide a default value.
+
+Boot source selection
+~~~~~~~~~~~~~~~~~~~~~
+
+Boot mode is selected by an MSEL-DIP marked S1804 and GPIO_0 position adjacent
+to the 40pin GPIO header. ON/ONKE and number markings of the MSEL-DIP are
+misleading; Instead refer to the ``L`` (0) and ``H`` (1) silkscreen for
+accurate selection.
+
++ (QSPI) Flash: 00
++ SD: 01
++ EMMC: 10
++ UART: 11
+
+Preparing the SD-Card
+~~~~~~~~~~~~~~~~~~~~~
+
+The device firmware loads U-Boot SPL (u-boot-spl.bin.normal.out) from the
+partition with type GUID 2E54B353-1271-4842-806F-E436D6AF6985. You are free
+to choose any partition number.
+
+With the default configuration U-Boot SPL loads the U-Boot FIT image
+(u-boot.itb) from partition 2 (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2).
+When formatting it is recommended to use GUID
+BC13C2FF-59E6-4262-A352-B275FD6F7172 for this partition.
+
+The FIT image (u-boot.itb) is a combination of OpenSBI's fw_dynamic.bin,
+u-boot-nodtb.bin and the device tree blob.
+
+Format the SD card (make sure the disk has GPT, otherwise use gdisk to switch)
+
+.. code-block:: bash
+
+ sudo sgdisk --clear \
+ --set-alignment=2 \
+ --new=1:4096:8191 --change-name=1:spl --typecode=1:2E54B353-1271-4842-806F-E436D6AF6985\
+ --new=2:8192:16383 --change-name=2:uboot --typecode=2:BC13C2FF-59E6-4262-A352-B275FD6F7172 \
+ --new=3:16384:1654784 --change-name=3:system --typecode=3:EBD0A0A2-B9E5-4433-87C0-68B6B72699C7 \
+ /dev/sdb
+
+Copy U-Boot to the SD card
+
+.. code-block:: bash
+
+ sudo dd if=u-boot-spl.bin.normal.out of=/dev/sdb1
+ sudo dd if=u-boot.itb of=/dev/sdb2
+
+ sudo mount /dev/sdb3 /mnt/
+ sudo cp u-boot-spl.bin.normal.out /mnt/
+ sudo cp u-boot.itb /mnt/
+ sudo cp Image.gz /mnt/
+ sudo cp initramfs.cpio.gz /mnt/
+ sudo cp jh7110-starfive-visionfive-2.dtb /mnt/
+ sudo umount /mnt
+
+Booting
+~~~~~~~
+
+Once you plugin the sdcard and power up, you should see the U-Boot prompt.
+
+Serial Number and MAC address issues
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+U-Boot requires valid EEPROM data to determine which board-specific fix-up to
+apply at runtime. This affects the size of memory initialized, network mac
+address numbering, and tuning of the network PHYs.
+
+The Star64 does not currently ship with unique serial numbers per-device.
+Devices follow a pattern where the last mac address bytes are a sum of 0x7558
+and the serial number (lower port mac0), or a sum of 0x7559 and the serial
+number (upper port mac1).
+
+As tested there are several 4gb model units where the serial number and network
+mac addresses collide with other devices (serial
+``STAR64V1-2310-D004E000-00000005``, MACs ``6c:cf:39:00:75:61``,
+``6c:cf:39:00:75:62``)
+
+Some early Star64 boards shipped with an uninitialized EEPROM and no write
+protect pull-up resistor in place. Later units of all 4gb and 8gb models
+sharing the same serial number in EEPROM data will have this problem that the
+network mac addresses are alike between different models and this may be
+corrected by defeating the write protect resistor to write new values. As an
+alternative to this, it may be worked around by overriding the mac addresses
+via U-Boot environment variables.
+
+It is required for any unit having uninitialized EEPROM and recommended for
+all later Star64 4gb model units (not properly serialized) to have decided on a
+new 6-byte serial number. This serial number should be high enough to
+avoid collision with other JH7110 boards and low enough not to overflow i.e.
+between ``cafe00`` and ``f00d00``.
+
+Update EEPROM values
+^^^^^^^^^^^^^^^^^^^^
+
+1. Prepare EEPROM data in memory
+
+::
+
+ ## When there is no error to load existing data:
+ mac read_eeprom
+
+ ## When there is an error to load non-existing data:
+ # "DRAM: Not a StarFive EEPROM data format - magic error"
+ mac initialize
+
+2. Set Star64 values
+
+::
+
+ ## Common values
+ mac vendor PINE64
+ mac pcb_revision c1
+ mac bom_revision A
+
+ ## Device-specific values
+ # Year 2023 week 10 production date, 8GB DRAM, optional eMMC, serial cdef01
+ mac product_id STAR64V1-2310-D008E000-00cdef01
+
+ # Last three bytes mac0: 0x7558 + serial number 0xcdef01
+ mac mac0_address 6c:cf:39:ce:64:59
+
+ # Last three bytes mac1: 0x7559 + serial number 0xcdef01
+ mac mac1_address 6c:cf:39:ce:64:5a
+
+3. Defeat write-protect pull-up resistor (if installed) and write to EEPROM
+
+::
+
+ mac write_eeprom
+
+Set Variables in U-Boot
+^^^^^^^^^^^^^^^^^^^^^^^
+
+.. note:: Changing just the serial number will not alter your MAC address
+
+The MAC addresses may be "set" as follows by writing as a custom config to SPI
+(Change the last 3 bytes of MAC addreses as appropriate):
+
+::
+
+ env set serial# STAR64V1-2310-D008E000-00cdef01
+ env set ethaddr 6c:cf:39:ce:64:59
+ env set eth1addr 6c:cf:39:ce:64:5a
+ env save
+ reset
diff --git a/doc/board/theobroma-systems/index.rst b/doc/board/theobroma-systems/index.rst
index b4da261..73e07f7 100644
--- a/doc/board/theobroma-systems/index.rst
+++ b/doc/board/theobroma-systems/index.rst
@@ -9,3 +9,4 @@
jaguar_rk3588
puma_rk3399
ringneck_px30
+ tiger_rk3588
diff --git a/doc/board/theobroma-systems/tiger_rk3588.rst b/doc/board/theobroma-systems/tiger_rk3588.rst
new file mode 100644
index 0000000..a73eec7
--- /dev/null
+++ b/doc/board/theobroma-systems/tiger_rk3588.rst
@@ -0,0 +1,102 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+SOM-RK3588-Q7 Tiger
+===================
+
+The RK3588-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230
+connector) system-on-module from Theobroma Systems, featuring the
+Rockchip RK3588.
+
+It provides the following feature set:
+ * up to 16GB LPDDR4x
+ * on-module eMMC
+ * SD card (on a baseboard) via edge connector
+ * Gigabit Ethernet with on-module GbE PHY
+ * HDMI/eDP
+ * MIPI-DSI
+ * 4x MIPI-CSI (3x on FPC connectors, 1x over Q7)
+ * HDMI input over FPC connector
+ * CAN
+ * USB
+ - 1x USB 3.0 dual-role (direct connection)
+ - 2x USB 3.0 host + 1x USB 2.0 host
+ * PCIe
+ - 1x PCIe 2.1 Gen3, 4 lanes
+ - 2xSATA / 2x PCIe 2.1 Gen1, 2 lanes
+ * on-module ATtiny816 companion controller, implementing:
+ - low-power RTC functionality (ISL1208 emulation)
+ - fan controller (AMC6821 emulation)
+ * on-module Secure Element with Global Platform 2.2.1 compliant
+ JavaCard environment
+
+Here is the step-by-step to boot to U-Boot on SOM-RK3588-Q7 Tiger from Theobroma
+Systems.
+
+Get the TF-A and DDR init (TPL) binaries
+----------------------------------------
+
+.. prompt:: bash
+
+ git clone https://github.com/rockchip-linux/rkbin
+ cd rkbin
+ export RKBIN=$(pwd)
+ export BL31=$RKBIN/bin/rk35/rk3588_bl31_v1.38.elf
+ export ROCKCHIP_TPL=$RKBIN/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2736MHz_v1.11.bin
+ sed -i 's/^uart baudrate=.*$/uart baudrate=115200/' tools/ddrbin_param.txt
+ sed -i 's/^uart iomux=.*$/uart iomux=2/' tools/ddrbin_param.txt
+ ./tools/ddrbin_tool tools/ddrbin_param.txt "$ROCKCHIP_TPL"
+ ./tools/boot_merger RKBOOT/RK3588MINIALL.ini
+ export RKDB=$RKBIN/rk3588_spl_loader_v1.11.112.bin
+
+This will setup all required external dependencies for compiling U-Boot. This will
+be updated in the future once upstream Trusted-Firmware-A supports RK3588 or U-Boot
+gains support for open-source DRAM initialization in TPL.
+
+Build U-Boot
+------------
+
+.. prompt:: bash
+
+ cd ../u-boot
+ make CROSS_COMPILE=aarch64-linux-gnu- tiger-rk3588_defconfig all
+
+This will build ``u-boot-rockchip.bin`` which can be written to an MMC device
+(eMMC or SD card).
+
+Flash the image
+---------------
+
+Copy ``u-boot-rockchip.bin`` to offset 32k for SD/eMMC.
+
+SD-Card
+~~~~~~~
+
+.. prompt:: bash
+
+ dd if=u-boot-rockchip.bin of=/dev/sdX seek=64
+
+.. note::
+
+ Replace ``/dev/sdX`` to match your SD card kernel device.
+
+eMMC
+~~~~
+
+``rkdeveloptool`` allows to flash the on-board eMMC via the USB OTG interface
+with help of the Rockchip loader binary.
+
+To enter the USB flashing mode on Haikou baseboard, remove any SD card, insert a
+micro-USB cable in the ``Q7 USB P1`` connector (P8), move ``SW5`` switch into
+``BIOS Disable`` mode, power cycle or reset the board and move ``SW5`` switch
+back to ``Normal Boot`` mode. A new USB device should have appeared on your PC
+(check with ``lsusb -d 2207:350b``).
+
+To flash U-Boot on the eMMC with ``rkdeveloptool``:
+
+.. prompt:: bash
+
+ git clone https://github.com/rockchip-linux/rkdeveloptool
+ cd rkdeveloptool
+ autoreconf -i && CPPFLAGS=-Wno-format-truncation ./configure && make
+ ./rkdeveloptool db "$RKDB"
+ ./rkdeveloptool wl 64 ../u-boot-rockchip.bin
diff --git a/doc/board/ti/am62px_sk.rst b/doc/board/ti/am62px_sk.rst
index 1f2982c..c80b506 100644
--- a/doc/board/ti/am62px_sk.rst
+++ b/doc/board/ti/am62px_sk.rst
@@ -156,6 +156,30 @@
.. image:: img/dm_tispl.bin.svg
:alt: tispl.bin image format
+OSPI:
+-----
+ROM supports booting from OSPI from offset 0x0.
+
+Flashing images to OSPI:
+
+Below commands can be used to download tiboot3.bin, tispl.bin, and u-boot.img,
+over tftp and then flash those to OSPI at their respective addresses.
+
+.. prompt:: bash =>
+
+ sf probe
+ tftp ${loadaddr} tiboot3.bin
+ sf update $loadaddr 0x0 $filesize
+ tftp ${loadaddr} tispl.bin
+ sf update $loadaddr 0x80000 $filesize
+ tftp ${loadaddr} u-boot.img
+ sf update $loadaddr 0x280000 $filesize
+
+Flash layout for OSPI:
+
+.. image:: img/ospi_sysfw2.svg
+ :alt: OSPI flash partition layout
+
A53 SPL DDR Memory Layout
-------------------------
diff --git a/doc/board/ti/am62x_sk.rst b/doc/board/ti/am62x_sk.rst
index d5f7fe3..2a25e84 100644
--- a/doc/board/ti/am62x_sk.rst
+++ b/doc/board/ti/am62x_sk.rst
@@ -164,6 +164,30 @@
.. image:: img/dm_tispl.bin.svg
:alt: tispl.bin image format
+OSPI:
+-----
+ROM supports booting from OSPI from offset 0x0.
+
+Flashing images to OSPI:
+
+Below commands can be used to download tiboot3.bin, tispl.bin, and u-boot.img,
+over tftp and then flash those to OSPI at their respective addresses.
+
+.. prompt:: bash =>
+
+ sf probe
+ tftp ${loadaddr} tiboot3.bin
+ sf update $loadaddr 0x0 $filesize
+ tftp ${loadaddr} tispl.bin
+ sf update $loadaddr 0x80000 $filesize
+ tftp ${loadaddr} u-boot.img
+ sf update $loadaddr 0x280000 $filesize
+
+Flash layout for OSPI:
+
+.. image:: img/ospi_sysfw2.svg
+ :alt: OSPI flash partition layout
+
A53 SPL DDR Memory Layout
-------------------------
diff --git a/doc/board/ti/am64x_evm.rst b/doc/board/ti/am64x_evm.rst
index 6ae35b3..88997b6 100644
--- a/doc/board/ti/am64x_evm.rst
+++ b/doc/board/ti/am64x_evm.rst
@@ -140,6 +140,30 @@
.. image:: img/nodm_tispl.bin.svg
:alt: tispl.bin image format
+OSPI:
+-----
+ROM supports booting from OSPI from offset 0x0.
+
+Flashing images to OSPI:
+
+Below commands can be used to download tiboot3.bin, tispl.bin, and u-boot.img,
+over tftp and then flash those to OSPI at their respective addresses.
+
+.. prompt:: bash =>
+
+ sf probe
+ tftp ${loadaddr} tiboot3.bin
+ sf update $loadaddr 0x0 $filesize
+ tftp ${loadaddr} tispl.bin
+ sf update $loadaddr 0x100000 $filesize
+ tftp ${loadaddr} u-boot.img
+ sf update $loadaddr 0x300000 $filesize
+
+Flash layout for OSPI:
+
+.. image:: img/ospi_sysfw-am64.svg
+ :alt: OSPI flash partition layout
+
Switch Setting for Boot Mode
----------------------------
diff --git a/doc/board/ti/img/ospi_sysfw-am64.svg b/doc/board/ti/img/ospi_sysfw-am64.svg
new file mode 100644
index 0000000..f6244dc
--- /dev/null
+++ b/doc/board/ti/img/ospi_sysfw-am64.svg
@@ -0,0 +1,802 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<!--SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause-->
+
+<!--Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/-->
+
+<svg
+ version="1.1"
+ width="321px"
+ height="336px"
+ viewBox="-0.5 -0.5 321 336"
+ id="svg28701"
+ sodipodi:docname="ospi_sysfw-am64.svg"
+ inkscape:version="1.1.2 (0a00cf5339, 2022-02-04)"
+ xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape"
+ xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
+ xmlns="http://www.w3.org/2000/svg"
+ xmlns:svg="http://www.w3.org/2000/svg"
+ xmlns:xhtml="http://www.w3.org/1999/xhtml">
+ <sodipodi:namedview
+ id="namedview28703"
+ pagecolor="#505050"
+ bordercolor="#eeeeee"
+ borderopacity="1"
+ inkscape:pageshadow="0"
+ inkscape:pageopacity="0"
+ inkscape:pagecheckerboard="0"
+ showgrid="false"
+ inkscape:zoom="2.5982143"
+ inkscape:cx="160.49485"
+ inkscape:cy="168"
+ inkscape:window-width="3370"
+ inkscape:window-height="1376"
+ inkscape:window-x="70"
+ inkscape:window-y="27"
+ inkscape:window-maximized="1"
+ inkscape:current-layer="g28699" />
+ <defs
+ id="defs28505" />
+ <g
+ id="g28699">
+ <g
+ id="g28509">
+ <rect
+ x="120"
+ y="15"
+ width="200"
+ height="40"
+ fill="none"
+ stroke="rgb(0, 0, 0)"
+ pointer-events="all"
+ id="rect28507" />
+ </g>
+ <g
+ id="g28517">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g28515">
+ <switch
+ id="switch28513">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 35px; margin-left: 121px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ospi.tiboot3(1M)</xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="220"
+ y="39"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="middle"
+ id="text28511">ospi.tiboot3(1M)</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g28521">
+ <rect
+ x="60"
+ y="5"
+ width="60"
+ height="30"
+ fill="none"
+ stroke="none"
+ pointer-events="all"
+ id="rect28519" />
+ </g>
+ <g
+ id="g28529">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g28527">
+ <switch
+ id="switch28525">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 58px; height: 1px; padding-top: 20px; margin-left: 60px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
+ <xhtml:pre
+ style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x0</xhtml:pre>
+ </xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="118"
+ y="24"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="end"
+ id="text28523">0x0</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g28533">
+ <rect
+ x="120"
+ y="55"
+ width="200"
+ height="40"
+ fill="none"
+ stroke="rgb(0, 0, 0)"
+ pointer-events="all"
+ id="rect28531" />
+ </g>
+ <g
+ id="g28541">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g28539">
+ <switch
+ id="switch28537">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 75px; margin-left: 121px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ospi.tispl(2M)</xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="220"
+ y="79"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="middle"
+ id="text28535">ospi.tispl(2M)</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g28545">
+ <rect
+ x="0"
+ y="45"
+ width="120"
+ height="30"
+ fill="none"
+ stroke="none"
+ pointer-events="all"
+ id="rect28543" />
+ </g>
+ <g
+ id="g28553">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g28551">
+ <switch
+ id="switch28549">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 118px; height: 1px; padding-top: 60px; margin-left: 0px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
+ <xhtml:pre
+ style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x100000</xhtml:pre>
+ </xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="118"
+ y="64"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="end"
+ id="text28547">0x100000</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g28557">
+ <rect
+ x="120"
+ y="95"
+ width="200"
+ height="40"
+ fill="none"
+ stroke="rgb(0, 0, 0)"
+ pointer-events="all"
+ id="rect28555" />
+ </g>
+ <g
+ id="g28565">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g28563">
+ <switch
+ id="switch28561">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 115px; margin-left: 121px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ospi.u-boot(4M)</xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="220"
+ y="119"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="middle"
+ id="text28559">ospi.u-boot(4M)</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g28569">
+ <rect
+ x="0"
+ y="85"
+ width="120"
+ height="30"
+ fill="none"
+ stroke="none"
+ pointer-events="all"
+ id="rect28567" />
+ </g>
+ <g
+ id="g28577">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g28575">
+ <switch
+ id="switch28573">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 118px; height: 1px; padding-top: 100px; margin-left: 0px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
+ <xhtml:pre
+ style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x300000</xhtml:pre>
+ </xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="118"
+ y="104"
+ fill="#000000"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="end"
+ id="text28571">0x300000</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g28581">
+ <rect
+ x="120"
+ y="135"
+ width="200"
+ height="40"
+ fill="none"
+ stroke="rgb(0, 0, 0)"
+ pointer-events="all"
+ id="rect28579" />
+ </g>
+ <g
+ id="g28589">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g28587">
+ <switch
+ id="switch28585">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 155px; margin-left: 121px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ospi.env(128K)</xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="220"
+ y="159"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="middle"
+ id="text28583">ospi.env(128K)</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g28593">
+ <rect
+ x="0"
+ y="125"
+ width="120"
+ height="30"
+ fill="none"
+ stroke="none"
+ pointer-events="all"
+ id="rect28591" />
+ </g>
+ <g
+ id="g28601">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g28599">
+ <switch
+ id="switch28597">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 118px; height: 1px; padding-top: 140px; margin-left: 0px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
+ <xhtml:pre
+ style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x700000</xhtml:pre>
+ </xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="118"
+ y="144"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="end"
+ id="text28595">0x700000</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g28605">
+ <rect
+ x="120"
+ y="175"
+ width="200"
+ height="40"
+ fill="none"
+ stroke="rgb(0, 0, 0)"
+ pointer-events="all"
+ id="rect28603" />
+ </g>
+ <g
+ id="g28613">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g28611">
+ <switch
+ id="switch28609">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 195px; margin-left: 121px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ospi.env.backup(128K)</xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="220"
+ y="199"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="middle"
+ id="text28607">ospi.env.backup(128K)</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g28617">
+ <rect
+ x="0"
+ y="165"
+ width="120"
+ height="30"
+ fill="none"
+ stroke="none"
+ pointer-events="all"
+ id="rect28615" />
+ </g>
+ <g
+ id="g28625">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g28623">
+ <switch
+ id="switch28621">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 118px; height: 1px; padding-top: 180px; margin-left: 0px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
+ <xhtml:pre
+ style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x720000</xhtml:pre>
+ </xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="118"
+ y="184"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="end"
+ id="text28619">0x720000</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g28629">
+ <rect
+ x="120"
+ y="215"
+ width="200"
+ height="40"
+ fill="none"
+ stroke="rgb(0, 0, 0)"
+ pointer-events="all"
+ id="rect28627" />
+ </g>
+ <g
+ id="g28637">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g28635">
+ <switch
+ id="switch28633">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 235px; margin-left: 121px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">padding(768K)</xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="220"
+ y="239"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="middle"
+ id="text28631">padding(768K)</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g28641">
+ <rect
+ x="0"
+ y="205"
+ width="120"
+ height="30"
+ fill="none"
+ stroke="none"
+ pointer-events="all"
+ id="rect28639" />
+ </g>
+ <g
+ id="g28649">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g28647">
+ <switch
+ id="switch28645">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 118px; height: 1px; padding-top: 220px; margin-left: 0px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
+ <xhtml:pre
+ style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x740000</xhtml:pre>
+ </xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="118"
+ y="224"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="end"
+ id="text28643">0x740000</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g28653">
+ <rect
+ x="120"
+ y="255"
+ width="200"
+ height="40"
+ fill="none"
+ stroke="rgb(0, 0, 0)"
+ pointer-events="all"
+ id="rect28651" />
+ </g>
+ <g
+ id="g28661">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g28659">
+ <switch
+ id="switch28657">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 275px; margin-left: 121px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ospi.rootfs(UBIFS)</xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="220"
+ y="279"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="middle"
+ id="text28655">ospi.rootfs(UBIFS)</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g28665">
+ <rect
+ x="0"
+ y="245"
+ width="120"
+ height="30"
+ fill="none"
+ stroke="none"
+ pointer-events="all"
+ id="rect28663" />
+ </g>
+ <g
+ id="g28673">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g28671">
+ <switch
+ id="switch28669">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 118px; height: 1px; padding-top: 260px; margin-left: 0px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
+ <xhtml:pre
+ style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x800000</xhtml:pre>
+ </xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="118"
+ y="264"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="end"
+ id="text28667">0x800000</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g28677">
+ <rect
+ x="120"
+ y="295"
+ width="200"
+ height="40"
+ fill="none"
+ stroke="rgb(0, 0, 0)"
+ pointer-events="all"
+ id="rect28675" />
+ </g>
+ <g
+ id="g28685">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g28683">
+ <switch
+ id="switch28681">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 315px; margin-left: 121px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ospi.phypattern(256k)</xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="220"
+ y="319"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="middle"
+ id="text28679">ospi.phypattern(256k)</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g28689">
+ <rect
+ x="0"
+ y="285"
+ width="120"
+ height="30"
+ fill="none"
+ stroke="none"
+ pointer-events="all"
+ id="rect28687" />
+ </g>
+ <g
+ id="g28697">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g28695">
+ <switch
+ id="switch28693">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 118px; height: 1px; padding-top: 300px; margin-left: 0px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
+ <xhtml:pre
+ style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x3FC0000</xhtml:pre>
+ </xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="118"
+ y="304"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="end"
+ id="text28691">0x3FC0000</text>
+ </switch>
+ </g>
+ </g>
+ </g>
+</svg>
diff --git a/doc/board/ti/img/ospi_sysfw.svg b/doc/board/ti/img/ospi_sysfw.svg
index 648f6fd..2a2fd3f 100644
--- a/doc/board/ti/img/ospi_sysfw.svg
+++ b/doc/board/ti/img/ospi_sysfw.svg
@@ -1,725 +1,897 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<!--SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause-->
-<!--Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/-->
+<!--Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/-->
<svg
version="1.1"
width="321px"
- height="336px"
- viewBox="-0.5 -0.5 321 336"
- id="svg142"
+ height="376px"
+ viewBox="-0.5 -0.5 321 376"
+ id="svg19243"
sodipodi:docname="ospi_sysfw.svg"
inkscape:version="1.1.2 (0a00cf5339, 2022-02-04)"
xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape"
xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
- xmlns:xlink="http://www.w3.org/1999/xlink"
xmlns="http://www.w3.org/2000/svg"
xmlns:svg="http://www.w3.org/2000/svg"
xmlns:xhtml="http://www.w3.org/1999/xhtml">
<sodipodi:namedview
- id="namedview144"
- pagecolor="#ffffff"
- bordercolor="#666666"
- borderopacity="1.0"
- inkscape:pageshadow="2"
- inkscape:pageopacity="0.0"
+ id="namedview19245"
+ pagecolor="#505050"
+ bordercolor="#eeeeee"
+ borderopacity="1"
+ inkscape:pageshadow="0"
+ inkscape:pageopacity="0"
inkscape:pagecheckerboard="0"
showgrid="false"
- inkscape:zoom="2.0297619"
- inkscape:cx="156.66862"
- inkscape:cy="168"
- inkscape:window-width="3440"
- inkscape:window-height="1416"
- inkscape:window-x="0"
- inkscape:window-y="0"
+ inkscape:zoom="2.3218085"
+ inkscape:cx="160.65063"
+ inkscape:cy="188"
+ inkscape:window-width="3370"
+ inkscape:window-height="1376"
+ inkscape:window-x="70"
+ inkscape:window-y="27"
inkscape:window-maximized="1"
- inkscape:current-layer="svg142" />
+ inkscape:current-layer="g19241" />
<defs
- id="defs2" />
+ id="defs19023" />
<g
- id="g132">
- <rect
- x="120"
- y="15"
- width="200"
- height="40"
- fill="rgb(255, 255, 255)"
- stroke="rgb(0, 0, 0)"
- pointer-events="all"
- id="rect4" />
+ id="g19241">
<g
- transform="translate(-0.5 -0.5)"
- id="g10">
- <switch
- id="switch8">
- <foreignObject
- pointer-events="none"
- width="100%"
- height="100%"
- requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
- style="overflow: visible; text-align: left;">
- <xhtml:div
- style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 35px; margin-left: 121px;">
+ id="g19027">
+ <rect
+ x="120"
+ y="15"
+ width="200"
+ height="40"
+ fill="none"
+ stroke="rgb(0, 0, 0)"
+ pointer-events="all"
+ id="rect19025" />
+ </g>
+ <g
+ id="g19035">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g19033">
+ <switch
+ id="switch19031">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
<xhtml:div
- data-drawio-colors="color: rgb(0, 0, 0); "
- style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 35px; margin-left: 121px;">
<xhtml:div
- style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ospi.tiboot3(512k)</xhtml:div>
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ospi.tiboot3(512k)</xhtml:div>
+ </xhtml:div>
</xhtml:div>
- </xhtml:div>
- </foreignObject>
- <text
- x="220"
- y="39"
- fill="#000000"
- font-family="Helvetica"
- font-size="12px"
- text-anchor="middle"
- id="text6">ospi.tiboot3(512k)</text>
- </switch>
+ </foreignObject>
+ <text
+ x="220"
+ y="39"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="middle"
+ id="text19029">ospi.tiboot3(512k)</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g19039">
+ <rect
+ x="60"
+ y="5"
+ width="60"
+ height="30"
+ fill="none"
+ stroke="none"
+ pointer-events="all"
+ id="rect19037" />
</g>
- <rect
- x="60"
- y="5"
- width="60"
- height="30"
- fill="none"
- stroke="none"
- pointer-events="all"
- id="rect12" />
<g
- transform="translate(-0.5 -0.5)"
- id="g18">
- <switch
- id="switch16">
- <foreignObject
- pointer-events="none"
- width="100%"
- height="100%"
- requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
- style="overflow: visible; text-align: left;">
- <xhtml:div
- style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 58px; height: 1px; padding-top: 20px; margin-left: 60px;">
+ id="g19047">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g19045">
+ <switch
+ id="switch19043">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
<xhtml:div
- data-drawio-colors="color: rgb(0, 0, 0); "
- style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 58px; height: 1px; padding-top: 20px; margin-left: 60px;">
<xhtml:div
- style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
- <xhtml:pre
- style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x0</xhtml:pre>
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
+ <xhtml:pre
+ style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x0</xhtml:pre>
+ </xhtml:div>
</xhtml:div>
</xhtml:div>
- </xhtml:div>
- </foreignObject>
- <text
- x="118"
- y="24"
- fill="rgb(0, 0, 0)"
- font-family="Helvetica"
- font-size="12px"
- text-anchor="end"
- id="text14">0x0</text>
- </switch>
+ </foreignObject>
+ <text
+ x="118"
+ y="24"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="end"
+ id="text19041">0x0</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g19051">
+ <rect
+ x="120"
+ y="55"
+ width="200"
+ height="40"
+ fill="none"
+ stroke="rgb(0, 0, 0)"
+ pointer-events="all"
+ id="rect19049" />
</g>
- <rect
- x="120"
- y="55"
- width="200"
- height="40"
- fill="rgb(255, 255, 255)"
- stroke="rgb(0, 0, 0)"
- pointer-events="all"
- id="rect20" />
<g
- transform="translate(-0.5 -0.5)"
- id="g26">
- <switch
- id="switch24">
- <foreignObject
- pointer-events="none"
- width="100%"
- height="100%"
- requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
- style="overflow: visible; text-align: left;">
- <xhtml:div
- style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 75px; margin-left: 121px;">
+ id="g19059">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g19057">
+ <switch
+ id="switch19055">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
<xhtml:div
- data-drawio-colors="color: rgb(0, 0, 0); "
- style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 75px; margin-left: 121px;">
<xhtml:div
- style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ospi.tispl(2M)</xhtml:div>
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ospi.tispl(2M)</xhtml:div>
+ </xhtml:div>
</xhtml:div>
- </xhtml:div>
- </foreignObject>
- <text
- x="220"
- y="79"
- fill="rgb(0, 0, 0)"
- font-family="Helvetica"
- font-size="12px"
- text-anchor="middle"
- id="text22">ospi.tispl(2M)</text>
- </switch>
+ </foreignObject>
+ <text
+ x="220"
+ y="79"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="middle"
+ id="text19053">ospi.tispl(2M)</text>
+ </switch>
+ </g>
</g>
- <rect
- x="0"
- y="45"
- width="120"
- height="30"
- fill="none"
- stroke="none"
- pointer-events="all"
- id="rect28" />
<g
- transform="translate(-0.5 -0.5)"
- id="g34">
- <switch
- id="switch32">
- <foreignObject
- pointer-events="none"
- width="100%"
- height="100%"
- requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
- style="overflow: visible; text-align: left;">
- <xhtml:div
- style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 118px; height: 1px; padding-top: 60px; margin-left: 0px;">
+ id="g19063">
+ <rect
+ x="0"
+ y="45"
+ width="120"
+ height="30"
+ fill="none"
+ stroke="none"
+ pointer-events="all"
+ id="rect19061" />
+ </g>
+ <g
+ id="g19071">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g19069">
+ <switch
+ id="switch19067">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
<xhtml:div
- data-drawio-colors="color: rgb(0, 0, 0); "
- style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 118px; height: 1px; padding-top: 60px; margin-left: 0px;">
<xhtml:div
- style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
- <xhtml:pre
- style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x80000</xhtml:pre>
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
+ <xhtml:pre
+ style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x80000</xhtml:pre>
+ </xhtml:div>
</xhtml:div>
</xhtml:div>
- </xhtml:div>
- </foreignObject>
- <text
- x="118"
- y="64"
- fill="rgb(0, 0, 0)"
- font-family="Helvetica"
- font-size="12px"
- text-anchor="end"
- id="text30">0x80000</text>
- </switch>
+ </foreignObject>
+ <text
+ x="118"
+ y="64"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="end"
+ id="text19065">0x80000</text>
+ </switch>
+ </g>
</g>
- <rect
- x="120"
- y="95"
- width="200"
- height="40"
- fill="rgb(255, 255, 255)"
- stroke="rgb(0, 0, 0)"
- pointer-events="all"
- id="rect36" />
<g
- transform="translate(-0.5 -0.5)"
- id="g42">
- <switch
- id="switch40">
- <foreignObject
- pointer-events="none"
- width="100%"
- height="100%"
- requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
- style="overflow: visible; text-align: left;">
- <xhtml:div
- style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 115px; margin-left: 121px;">
+ id="g19075">
+ <rect
+ x="120"
+ y="95"
+ width="200"
+ height="40"
+ fill="none"
+ stroke="rgb(0, 0, 0)"
+ pointer-events="all"
+ id="rect19073" />
+ </g>
+ <g
+ id="g19083">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g19081">
+ <switch
+ id="switch19079">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
<xhtml:div
- data-drawio-colors="color: rgb(0, 0, 0); "
- style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 115px; margin-left: 121px;">
<xhtml:div
- style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ospi.u-boot(4M)</xhtml:div>
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ospi.u-boot(4M)</xhtml:div>
+ </xhtml:div>
</xhtml:div>
- </xhtml:div>
- </foreignObject>
- <text
- x="220"
- y="119"
- fill="rgb(0, 0, 0)"
- font-family="Helvetica"
- font-size="12px"
- text-anchor="middle"
- id="text38">ospi.u-boot(4M)</text>
- </switch>
+ </foreignObject>
+ <text
+ x="220"
+ y="119"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="middle"
+ id="text19077">ospi.u-boot(4M)</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g19087">
+ <rect
+ x="0"
+ y="85"
+ width="120"
+ height="30"
+ fill="none"
+ stroke="none"
+ pointer-events="all"
+ id="rect19085" />
</g>
- <rect
- x="0"
- y="85"
- width="120"
- height="30"
- fill="none"
- stroke="none"
- pointer-events="all"
- id="rect44" />
<g
- transform="translate(-0.5 -0.5)"
- id="g50">
- <switch
- id="switch48">
- <foreignObject
- pointer-events="none"
- width="100%"
- height="100%"
- requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
- style="overflow: visible; text-align: left;">
- <xhtml:div
- style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 118px; height: 1px; padding-top: 100px; margin-left: 0px;">
+ id="g19095">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g19093">
+ <switch
+ id="switch19091">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
<xhtml:div
- data-drawio-colors="color: rgb(0, 0, 0); "
- style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 118px; height: 1px; padding-top: 100px; margin-left: 0px;">
<xhtml:div
- style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
- <xhtml:pre
- style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x280000</xhtml:pre>
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
+ <xhtml:pre
+ style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x280000</xhtml:pre>
+ </xhtml:div>
</xhtml:div>
</xhtml:div>
- </xhtml:div>
- </foreignObject>
- <text
- x="118"
- y="104"
- fill="rgb(0, 0, 0)"
- font-family="Helvetica"
- font-size="12px"
- text-anchor="end"
- id="text46">0x280000</text>
- </switch>
+ </foreignObject>
+ <text
+ x="118"
+ y="104"
+ fill="#000000"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="end"
+ id="text19089">0x280000</text>
+ </switch>
+ </g>
</g>
- <rect
- x="120"
- y="135"
- width="200"
- height="40"
- fill="rgb(255, 255, 255)"
- stroke="rgb(0, 0, 0)"
- pointer-events="all"
- id="rect52" />
<g
- transform="translate(-0.5 -0.5)"
- id="g58">
- <switch
- id="switch56">
- <foreignObject
- pointer-events="none"
- width="100%"
- height="100%"
- requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
- style="overflow: visible; text-align: left;">
- <xhtml:div
- style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 155px; margin-left: 121px;">
+ id="g19099">
+ <rect
+ x="120"
+ y="135"
+ width="200"
+ height="40"
+ fill="none"
+ stroke="rgb(0, 0, 0)"
+ pointer-events="all"
+ id="rect19097" />
+ </g>
+ <g
+ id="g19107">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g19105">
+ <switch
+ id="switch19103">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
<xhtml:div
- data-drawio-colors="color: rgb(0, 0, 0); "
- style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 155px; margin-left: 121px;">
<xhtml:div
- style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ospi.env(128K)</xhtml:div>
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ospi.env(128K)</xhtml:div>
+ </xhtml:div>
</xhtml:div>
- </xhtml:div>
- </foreignObject>
- <text
- x="220"
- y="159"
- fill="rgb(0, 0, 0)"
- font-family="Helvetica"
- font-size="12px"
- text-anchor="middle"
- id="text54">ospi.env(128K)</text>
- </switch>
+ </foreignObject>
+ <text
+ x="220"
+ y="159"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="middle"
+ id="text19101">ospi.env(128K)</text>
+ </switch>
+ </g>
</g>
- <rect
- x="0"
- y="125"
- width="120"
- height="30"
- fill="none"
- stroke="none"
- pointer-events="all"
- id="rect60" />
<g
- transform="translate(-0.5 -0.5)"
- id="g66">
- <switch
- id="switch64">
- <foreignObject
- pointer-events="none"
- width="100%"
- height="100%"
- requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
- style="overflow: visible; text-align: left;">
- <xhtml:div
- style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 118px; height: 1px; padding-top: 140px; margin-left: 0px;">
+ id="g19111">
+ <rect
+ x="0"
+ y="125"
+ width="120"
+ height="30"
+ fill="none"
+ stroke="none"
+ pointer-events="all"
+ id="rect19109" />
+ </g>
+ <g
+ id="g19119">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g19117">
+ <switch
+ id="switch19115">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
<xhtml:div
- data-drawio-colors="color: rgb(0, 0, 0); "
- style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 118px; height: 1px; padding-top: 140px; margin-left: 0px;">
<xhtml:div
- style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
- <xhtml:pre
- style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x680000</xhtml:pre>
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
+ <xhtml:pre
+ style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x680000</xhtml:pre>
+ </xhtml:div>
</xhtml:div>
</xhtml:div>
- </xhtml:div>
- </foreignObject>
- <text
- x="118"
- y="144"
- fill="rgb(0, 0, 0)"
- font-family="Helvetica"
- font-size="12px"
- text-anchor="end"
- id="text62">0x680000</text>
- </switch>
+ </foreignObject>
+ <text
+ x="118"
+ y="144"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="end"
+ id="text19113">0x680000</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g19123">
+ <rect
+ x="120"
+ y="175"
+ width="200"
+ height="40"
+ fill="none"
+ stroke="rgb(0, 0, 0)"
+ pointer-events="all"
+ id="rect19121" />
</g>
- <rect
- x="120"
- y="175"
- width="200"
- height="40"
- fill="rgb(255, 255, 255)"
- stroke="rgb(0, 0, 0)"
- pointer-events="all"
- id="rect68" />
<g
- transform="translate(-0.5 -0.5)"
- id="g74">
- <switch
- id="switch72">
- <foreignObject
- pointer-events="none"
- width="100%"
- height="100%"
- requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
- style="overflow: visible; text-align: left;">
- <xhtml:div
- style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 195px; margin-left: 121px;">
+ id="g19131">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g19129">
+ <switch
+ id="switch19127">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
<xhtml:div
- data-drawio-colors="color: rgb(0, 0, 0); "
- style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 195px; margin-left: 121px;">
<xhtml:div
- style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ospi.env.backup(128K)</xhtml:div>
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ospi.env.backup(128K)</xhtml:div>
+ </xhtml:div>
</xhtml:div>
- </xhtml:div>
- </foreignObject>
- <text
- x="220"
- y="199"
- fill="rgb(0, 0, 0)"
- font-family="Helvetica"
- font-size="12px"
- text-anchor="middle"
- id="text70">ospi.env.backup(128K)</text>
- </switch>
+ </foreignObject>
+ <text
+ x="220"
+ y="199"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="middle"
+ id="text19125">ospi.env.backup(128K)</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g19135">
+ <rect
+ x="0"
+ y="165"
+ width="120"
+ height="30"
+ fill="none"
+ stroke="none"
+ pointer-events="all"
+ id="rect19133" />
</g>
- <rect
- x="0"
- y="165"
- width="120"
- height="30"
- fill="none"
- stroke="none"
- pointer-events="all"
- id="rect76" />
<g
- transform="translate(-0.5 -0.5)"
- id="g82">
- <switch
- id="switch80">
- <foreignObject
- pointer-events="none"
- width="100%"
- height="100%"
- requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
- style="overflow: visible; text-align: left;">
- <xhtml:div
- style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 118px; height: 1px; padding-top: 180px; margin-left: 0px;">
+ id="g19143">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g19141">
+ <switch
+ id="switch19139">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
<xhtml:div
- data-drawio-colors="color: rgb(0, 0, 0); "
- style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 118px; height: 1px; padding-top: 180px; margin-left: 0px;">
<xhtml:div
- style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
- <xhtml:pre
- style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x6A0000</xhtml:pre>
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
+ <xhtml:pre
+ style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x6A0000</xhtml:pre>
+ </xhtml:div>
</xhtml:div>
</xhtml:div>
- </xhtml:div>
- </foreignObject>
- <text
- x="118"
- y="184"
- fill="rgb(0, 0, 0)"
- font-family="Helvetica"
- font-size="12px"
- text-anchor="end"
- id="text78">0x6A0000</text>
- </switch>
+ </foreignObject>
+ <text
+ x="118"
+ y="184"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="end"
+ id="text19137">0x6A0000</text>
+ </switch>
+ </g>
</g>
- <rect
- x="120"
- y="215"
- width="200"
- height="40"
- fill="rgb(255, 255, 255)"
- stroke="rgb(0, 0, 0)"
- pointer-events="all"
- id="rect84" />
<g
- transform="translate(-0.5 -0.5)"
- id="g90">
- <switch
- id="switch88">
- <foreignObject
- pointer-events="none"
- width="100%"
- height="100%"
- requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
- style="overflow: visible; text-align: left;">
- <xhtml:div
- style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 235px; margin-left: 121px;">
+ id="g19147">
+ <rect
+ x="120"
+ y="215"
+ width="200"
+ height="40"
+ fill="none"
+ stroke="rgb(0, 0, 0)"
+ pointer-events="all"
+ id="rect19145" />
+ </g>
+ <g
+ id="g19155">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g19153">
+ <switch
+ id="switch19151">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
<xhtml:div
- data-drawio-colors="color: rgb(0, 0, 0); "
- style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 235px; margin-left: 121px;">
<xhtml:div
- style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ospi.sysfw(1M)</xhtml:div>
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ospi.sysfw(1M)</xhtml:div>
+ </xhtml:div>
</xhtml:div>
- </xhtml:div>
- </foreignObject>
- <text
- x="220"
- y="239"
- fill="rgb(0, 0, 0)"
- font-family="Helvetica"
- font-size="12px"
- text-anchor="middle"
- id="text86">ospi.sysfw(1M)</text>
- </switch>
+ </foreignObject>
+ <text
+ x="220"
+ y="239"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="middle"
+ id="text19149">ospi.sysfw(1M)</text>
+ </switch>
+ </g>
</g>
- <rect
- x="0"
- y="205"
- width="120"
- height="30"
- fill="none"
- stroke="none"
- pointer-events="all"
- id="rect92" />
<g
- transform="translate(-0.5 -0.5)"
- id="g98">
- <switch
- id="switch96">
- <foreignObject
- pointer-events="none"
- width="100%"
- height="100%"
- requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
- style="overflow: visible; text-align: left;">
- <xhtml:div
- style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 118px; height: 1px; padding-top: 220px; margin-left: 0px;">
+ id="g19159">
+ <rect
+ x="0"
+ y="205"
+ width="120"
+ height="30"
+ fill="none"
+ stroke="none"
+ pointer-events="all"
+ id="rect19157" />
+ </g>
+ <g
+ id="g19167">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g19165">
+ <switch
+ id="switch19163">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
<xhtml:div
- data-drawio-colors="color: rgb(0, 0, 0); "
- style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 118px; height: 1px; padding-top: 220px; margin-left: 0px;">
<xhtml:div
- style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
- <xhtml:pre
- style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x6C0000</xhtml:pre>
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
+ <xhtml:pre
+ style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x6C0000</xhtml:pre>
+ </xhtml:div>
</xhtml:div>
</xhtml:div>
- </xhtml:div>
- </foreignObject>
- <text
- x="118"
- y="224"
- fill="rgb(0, 0, 0)"
- font-family="Helvetica"
- font-size="12px"
- text-anchor="end"
- id="text94">0x6C0000</text>
- </switch>
+ </foreignObject>
+ <text
+ x="118"
+ y="224"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="end"
+ id="text19161">0x6C0000</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g19171">
+ <rect
+ x="120"
+ y="255"
+ width="200"
+ height="40"
+ fill="none"
+ stroke="rgb(0, 0, 0)"
+ pointer-events="all"
+ id="rect19169" />
</g>
- <rect
- x="120"
- y="255"
- width="200"
- height="40"
- fill="rgb(255, 255, 255)"
- stroke="rgb(0, 0, 0)"
- pointer-events="all"
- id="rect100" />
<g
- transform="translate(-0.5 -0.5)"
- id="g106">
- <switch
- id="switch104">
- <foreignObject
- pointer-events="none"
- width="100%"
- height="100%"
- requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
- style="overflow: visible; text-align: left;">
- <xhtml:div
- style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 275px; margin-left: 121px;">
+ id="g19179">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g19177">
+ <switch
+ id="switch19175">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
<xhtml:div
- data-drawio-colors="color: rgb(0, 0, 0); "
- style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 275px; margin-left: 121px;">
<xhtml:div
- style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">padding(256K)</xhtml:div>
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">padding(256K)</xhtml:div>
+ </xhtml:div>
</xhtml:div>
- </xhtml:div>
- </foreignObject>
- <text
- x="220"
- y="279"
- fill="rgb(0, 0, 0)"
- font-family="Helvetica"
- font-size="12px"
- text-anchor="middle"
- id="text102">padding(256K)</text>
- </switch>
+ </foreignObject>
+ <text
+ x="220"
+ y="279"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="middle"
+ id="text19173">padding(256K)</text>
+ </switch>
+ </g>
</g>
- <rect
- x="0"
- y="245"
- width="120"
- height="30"
- fill="none"
- stroke="none"
- pointer-events="all"
- id="rect108" />
<g
- transform="translate(-0.5 -0.5)"
- id="g114">
- <switch
- id="switch112">
- <foreignObject
- pointer-events="none"
- width="100%"
- height="100%"
- requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
- style="overflow: visible; text-align: left;">
- <xhtml:div
- style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 118px; height: 1px; padding-top: 260px; margin-left: 0px;">
+ id="g19183">
+ <rect
+ x="0"
+ y="245"
+ width="120"
+ height="30"
+ fill="none"
+ stroke="none"
+ pointer-events="all"
+ id="rect19181" />
+ </g>
+ <g
+ id="g19191">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g19189">
+ <switch
+ id="switch19187">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
<xhtml:div
- data-drawio-colors="color: rgb(0, 0, 0); "
- style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 118px; height: 1px; padding-top: 260px; margin-left: 0px;">
<xhtml:div
- style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
- <xhtml:pre
- style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x7C0000</xhtml:pre>
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
+ <xhtml:pre
+ style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x7C0000</xhtml:pre>
+ </xhtml:div>
</xhtml:div>
</xhtml:div>
- </xhtml:div>
- </foreignObject>
- <text
- x="118"
- y="264"
- fill="rgb(0, 0, 0)"
- font-family="Helvetica"
- font-size="12px"
- text-anchor="end"
- id="text110">0x7C0000</text>
- </switch>
+ </foreignObject>
+ <text
+ x="118"
+ y="264"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="end"
+ id="text19185">0x7C0000</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g19195">
+ <rect
+ x="120"
+ y="295"
+ width="200"
+ height="40"
+ fill="none"
+ stroke="rgb(0, 0, 0)"
+ pointer-events="all"
+ id="rect19193" />
</g>
- <rect
- x="120"
- y="295"
- width="200"
- height="40"
- fill="rgb(255, 255, 255)"
- stroke="rgb(0, 0, 0)"
- pointer-events="all"
- id="rect116" />
<g
- transform="translate(-0.5 -0.5)"
- id="g122">
- <switch
- id="switch120">
- <foreignObject
- pointer-events="none"
- width="100%"
- height="100%"
- requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
- style="overflow: visible; text-align: left;">
- <xhtml:div
- style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 315px; margin-left: 121px;">
+ id="g19203">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g19201">
+ <switch
+ id="switch19199">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
<xhtml:div
- data-drawio-colors="color: rgb(0, 0, 0); "
- style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 315px; margin-left: 121px;">
<xhtml:div
- style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ospi.rootfs(UBIFS)</xhtml:div>
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ospi.rootfs(UBIFS)</xhtml:div>
+ </xhtml:div>
</xhtml:div>
- </xhtml:div>
- </foreignObject>
- <text
- x="220"
- y="319"
- fill="rgb(0, 0, 0)"
- font-family="Helvetica"
- font-size="12px"
- text-anchor="middle"
- id="text118">ospi.rootfs(UBIFS)</text>
- </switch>
+ </foreignObject>
+ <text
+ x="220"
+ y="319"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="middle"
+ id="text19197">ospi.rootfs(UBIFS)</text>
+ </switch>
+ </g>
</g>
- <rect
- x="0"
- y="285"
- width="120"
- height="30"
- fill="none"
- stroke="none"
- pointer-events="all"
- id="rect124" />
<g
- transform="translate(-0.5 -0.5)"
- id="g130">
- <switch
- id="switch128">
- <foreignObject
- pointer-events="none"
- width="100%"
- height="100%"
- requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
- style="overflow: visible; text-align: left;">
- <xhtml:div
- style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 118px; height: 1px; padding-top: 300px; margin-left: 0px;">
+ id="g19207">
+ <rect
+ x="0"
+ y="285"
+ width="120"
+ height="30"
+ fill="none"
+ stroke="none"
+ pointer-events="all"
+ id="rect19205" />
+ </g>
+ <g
+ id="g19215">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g19213">
+ <switch
+ id="switch19211">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
<xhtml:div
- data-drawio-colors="color: rgb(0, 0, 0); "
- style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 118px; height: 1px; padding-top: 300px; margin-left: 0px;">
<xhtml:div
- style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
- <xhtml:pre
- style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x800000</xhtml:pre>
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
+ <xhtml:pre
+ style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x800000</xhtml:pre>
+ </xhtml:div>
</xhtml:div>
</xhtml:div>
- </xhtml:div>
- </foreignObject>
- <text
- x="118"
- y="304"
- fill="rgb(0, 0, 0)"
- font-family="Helvetica"
- font-size="12px"
- text-anchor="end"
- id="text126">0x800000</text>
- </switch>
+ </foreignObject>
+ <text
+ x="118"
+ y="304"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="end"
+ id="text19209">0x800000</text>
+ </switch>
+ </g>
</g>
- </g>
- <switch
- id="switch140">
+ <g
+ id="g19219">
+ <rect
+ x="120"
+ y="335"
+ width="200"
+ height="40"
+ fill="none"
+ stroke="rgb(0, 0, 0)"
+ pointer-events="all"
+ id="rect19217" />
+ </g>
<g
- requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
- id="g134" />
- <a
- transform="translate(0,-5)"
- xlink:href="https://www.diagrams.net/doc/faq/svg-export-text-problems"
- target="_blank"
- id="a138">
- <text
- text-anchor="middle"
- font-size="10px"
- x="50%"
- y="100%"
- id="text136">Text is not SVG - cannot display</text>
- </a>
- </switch>
+ id="g19227">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g19225">
+ <switch
+ id="switch19223">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 355px; margin-left: 121px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ospi.phypattern(128k)</xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="220"
+ y="359"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="middle"
+ id="text19221">ospi.phypattern(128k)</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g19231">
+ <rect
+ x="0"
+ y="325"
+ width="120"
+ height="30"
+ fill="none"
+ stroke="none"
+ pointer-events="all"
+ id="rect19229" />
+ </g>
+ <g
+ id="g19239">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g19237">
+ <switch
+ id="switch19235">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 118px; height: 1px; padding-top: 340px; margin-left: 0px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
+ <xhtml:pre
+ style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x3FE0000</xhtml:pre>
+ </xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="118"
+ y="344"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="end"
+ id="text19233">0x3FE0000</text>
+ </switch>
+ </g>
+ </g>
+ </g>
</svg>
diff --git a/doc/board/ti/img/ospi_sysfw2.svg b/doc/board/ti/img/ospi_sysfw2.svg
new file mode 100644
index 0000000..06711df
--- /dev/null
+++ b/doc/board/ti/img/ospi_sysfw2.svg
@@ -0,0 +1,802 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<!--SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause-->
+
+<!--Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/-->
+
+<svg
+ version="1.1"
+ width="321px"
+ height="336px"
+ viewBox="-0.5 -0.5 321 336"
+ id="svg24863"
+ sodipodi:docname="ospi_sysfw2.svg"
+ inkscape:version="1.1.2 (0a00cf5339, 2022-02-04)"
+ xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape"
+ xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
+ xmlns="http://www.w3.org/2000/svg"
+ xmlns:svg="http://www.w3.org/2000/svg"
+ xmlns:xhtml="http://www.w3.org/1999/xhtml">
+ <sodipodi:namedview
+ id="namedview24865"
+ pagecolor="#505050"
+ bordercolor="#eeeeee"
+ borderopacity="1"
+ inkscape:pageshadow="0"
+ inkscape:pageopacity="0"
+ inkscape:pagecheckerboard="0"
+ showgrid="false"
+ inkscape:zoom="2.5982143"
+ inkscape:cx="160.49485"
+ inkscape:cy="168"
+ inkscape:window-width="3370"
+ inkscape:window-height="1376"
+ inkscape:window-x="70"
+ inkscape:window-y="27"
+ inkscape:window-maximized="1"
+ inkscape:current-layer="g24861" />
+ <defs
+ id="defs24667" />
+ <g
+ id="g24861">
+ <g
+ id="g24671">
+ <rect
+ x="120"
+ y="15"
+ width="200"
+ height="40"
+ fill="none"
+ stroke="rgb(0, 0, 0)"
+ pointer-events="all"
+ id="rect24669" />
+ </g>
+ <g
+ id="g24679">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g24677">
+ <switch
+ id="switch24675">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 35px; margin-left: 121px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ospi.tiboot3(512k)</xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="220"
+ y="39"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="middle"
+ id="text24673">ospi.tiboot3(512k)</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g24683">
+ <rect
+ x="60"
+ y="5"
+ width="60"
+ height="30"
+ fill="none"
+ stroke="none"
+ pointer-events="all"
+ id="rect24681" />
+ </g>
+ <g
+ id="g24691">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g24689">
+ <switch
+ id="switch24687">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 58px; height: 1px; padding-top: 20px; margin-left: 60px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
+ <xhtml:pre
+ style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x0</xhtml:pre>
+ </xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="118"
+ y="24"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="end"
+ id="text24685">0x0</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g24695">
+ <rect
+ x="120"
+ y="55"
+ width="200"
+ height="40"
+ fill="none"
+ stroke="rgb(0, 0, 0)"
+ pointer-events="all"
+ id="rect24693" />
+ </g>
+ <g
+ id="g24703">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g24701">
+ <switch
+ id="switch24699">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 75px; margin-left: 121px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ospi.tispl(2M)</xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="220"
+ y="79"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="middle"
+ id="text24697">ospi.tispl(2M)</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g24707">
+ <rect
+ x="0"
+ y="45"
+ width="120"
+ height="30"
+ fill="none"
+ stroke="none"
+ pointer-events="all"
+ id="rect24705" />
+ </g>
+ <g
+ id="g24715">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g24713">
+ <switch
+ id="switch24711">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 118px; height: 1px; padding-top: 60px; margin-left: 0px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
+ <xhtml:pre
+ style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x80000</xhtml:pre>
+ </xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="118"
+ y="64"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="end"
+ id="text24709">0x80000</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g24719">
+ <rect
+ x="120"
+ y="95"
+ width="200"
+ height="40"
+ fill="none"
+ stroke="rgb(0, 0, 0)"
+ pointer-events="all"
+ id="rect24717" />
+ </g>
+ <g
+ id="g24727">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g24725">
+ <switch
+ id="switch24723">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 115px; margin-left: 121px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ospi.u-boot(4M)</xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="220"
+ y="119"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="middle"
+ id="text24721">ospi.u-boot(4M)</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g24731">
+ <rect
+ x="0"
+ y="85"
+ width="120"
+ height="30"
+ fill="none"
+ stroke="none"
+ pointer-events="all"
+ id="rect24729" />
+ </g>
+ <g
+ id="g24739">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g24737">
+ <switch
+ id="switch24735">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 118px; height: 1px; padding-top: 100px; margin-left: 0px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
+ <xhtml:pre
+ style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x280000</xhtml:pre>
+ </xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="118"
+ y="104"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="end"
+ id="text24733">0x280000</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g24743">
+ <rect
+ x="120"
+ y="135"
+ width="200"
+ height="40"
+ fill="none"
+ stroke="rgb(0, 0, 0)"
+ pointer-events="all"
+ id="rect24741" />
+ </g>
+ <g
+ id="g24751">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g24749">
+ <switch
+ id="switch24747">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 155px; margin-left: 121px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ospi.env(128K)</xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="220"
+ y="159"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="middle"
+ id="text24745">ospi.env(128K)</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g24755">
+ <rect
+ x="0"
+ y="125"
+ width="120"
+ height="30"
+ fill="none"
+ stroke="none"
+ pointer-events="all"
+ id="rect24753" />
+ </g>
+ <g
+ id="g24763">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g24761">
+ <switch
+ id="switch24759">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 118px; height: 1px; padding-top: 140px; margin-left: 0px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
+ <xhtml:pre
+ style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x680000</xhtml:pre>
+ </xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="118"
+ y="144"
+ fill="#000000"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="end"
+ id="text24757">0x680000</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g24767">
+ <rect
+ x="120"
+ y="175"
+ width="200"
+ height="40"
+ fill="none"
+ stroke="rgb(0, 0, 0)"
+ pointer-events="all"
+ id="rect24765" />
+ </g>
+ <g
+ id="g24775">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g24773">
+ <switch
+ id="switch24771">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 195px; margin-left: 121px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ospi.env.backup(128K)</xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="220"
+ y="199"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="middle"
+ id="text24769">ospi.env.backup(128K)</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g24779">
+ <rect
+ x="0"
+ y="165"
+ width="120"
+ height="30"
+ fill="none"
+ stroke="none"
+ pointer-events="all"
+ id="rect24777" />
+ </g>
+ <g
+ id="g24787">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g24785">
+ <switch
+ id="switch24783">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 118px; height: 1px; padding-top: 180px; margin-left: 0px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
+ <xhtml:pre
+ style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x6C0000</xhtml:pre>
+ </xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="118"
+ y="184"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="end"
+ id="text24781">0x6C0000</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g24791">
+ <rect
+ x="120"
+ y="215"
+ width="200"
+ height="40"
+ fill="none"
+ stroke="rgb(0, 0, 0)"
+ pointer-events="all"
+ id="rect24789" />
+ </g>
+ <g
+ id="g24799">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g24797">
+ <switch
+ id="switch24795">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 235px; margin-left: 121px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">padding(768K)</xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="220"
+ y="239"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="middle"
+ id="text24793">padding(768K)</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g24803">
+ <rect
+ x="0"
+ y="205"
+ width="120"
+ height="30"
+ fill="none"
+ stroke="none"
+ pointer-events="all"
+ id="rect24801" />
+ </g>
+ <g
+ id="g24811">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g24809">
+ <switch
+ id="switch24807">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 118px; height: 1px; padding-top: 220px; margin-left: 0px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
+ <xhtml:pre
+ style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x740000</xhtml:pre>
+ </xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="118"
+ y="224"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="end"
+ id="text24805">0x740000</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g24815">
+ <rect
+ x="120"
+ y="255"
+ width="200"
+ height="40"
+ fill="none"
+ stroke="rgb(0, 0, 0)"
+ pointer-events="all"
+ id="rect24813" />
+ </g>
+ <g
+ id="g24823">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g24821">
+ <switch
+ id="switch24819">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 275px; margin-left: 121px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ospi.rootfs(UBIFS)</xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="220"
+ y="279"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="middle"
+ id="text24817">ospi.rootfs(UBIFS)</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g24827">
+ <rect
+ x="0"
+ y="245"
+ width="120"
+ height="30"
+ fill="none"
+ stroke="none"
+ pointer-events="all"
+ id="rect24825" />
+ </g>
+ <g
+ id="g24835">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g24833">
+ <switch
+ id="switch24831">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 118px; height: 1px; padding-top: 260px; margin-left: 0px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
+ <xhtml:pre
+ style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x800000</xhtml:pre>
+ </xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="118"
+ y="264"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="end"
+ id="text24829">0x800000</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g24839">
+ <rect
+ x="120"
+ y="295"
+ width="200"
+ height="40"
+ fill="none"
+ stroke="rgb(0, 0, 0)"
+ pointer-events="all"
+ id="rect24837" />
+ </g>
+ <g
+ id="g24847">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g24845">
+ <switch
+ id="switch24843">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 315px; margin-left: 121px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ospi.phypattern(256k)</xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="220"
+ y="319"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="middle"
+ id="text24841">ospi.phypattern(256k)</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g24851">
+ <rect
+ x="0"
+ y="285"
+ width="120"
+ height="30"
+ fill="none"
+ stroke="none"
+ pointer-events="all"
+ id="rect24849" />
+ </g>
+ <g
+ id="g24859">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g24857">
+ <switch
+ id="switch24855">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 118px; height: 1px; padding-top: 300px; margin-left: 0px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
+ <xhtml:pre
+ style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x3FC0000</xhtml:pre>
+ </xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="118"
+ y="304"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="end"
+ id="text24853">0x3FC0000</text>
+ </switch>
+ </g>
+ </g>
+ </g>
+</svg>
diff --git a/doc/board/ti/img/ospi_sysfw3.svg b/doc/board/ti/img/ospi_sysfw3.svg
new file mode 100644
index 0000000..382867c
--- /dev/null
+++ b/doc/board/ti/img/ospi_sysfw3.svg
@@ -0,0 +1,802 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<!--SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause-->
+
+<!--Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/-->
+
+<svg
+ version="1.1"
+ width="321px"
+ height="336px"
+ viewBox="-0.5 -0.5 321 336"
+ id="svg205"
+ sodipodi:docname="ospi_sysfw3.svg"
+ inkscape:version="1.1.2 (0a00cf5339, 2022-02-04)"
+ xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape"
+ xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
+ xmlns="http://www.w3.org/2000/svg"
+ xmlns:svg="http://www.w3.org/2000/svg"
+ xmlns:xhtml="http://www.w3.org/1999/xhtml">
+ <sodipodi:namedview
+ id="namedview207"
+ pagecolor="#505050"
+ bordercolor="#eeeeee"
+ borderopacity="1"
+ inkscape:pageshadow="0"
+ inkscape:pageopacity="0"
+ inkscape:pagecheckerboard="0"
+ showgrid="false"
+ inkscape:zoom="3.4732143"
+ inkscape:cx="160.37018"
+ inkscape:cy="168"
+ inkscape:window-width="3370"
+ inkscape:window-height="1376"
+ inkscape:window-x="70"
+ inkscape:window-y="27"
+ inkscape:window-maximized="1"
+ inkscape:current-layer="g203" />
+ <defs
+ id="defs9" />
+ <g
+ id="g203">
+ <g
+ id="g13">
+ <rect
+ x="120"
+ y="15"
+ width="200"
+ height="40"
+ fill="none"
+ stroke="rgb(0, 0, 0)"
+ pointer-events="all"
+ id="rect11" />
+ </g>
+ <g
+ id="g21">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g19">
+ <switch
+ id="switch17">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 35px; margin-left: 121px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ospi.tiboot3(512k)</xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="220"
+ y="39"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="middle"
+ id="text15">ospi.tiboot3(512k)</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g25">
+ <rect
+ x="60"
+ y="5"
+ width="60"
+ height="30"
+ fill="none"
+ stroke="none"
+ pointer-events="all"
+ id="rect23" />
+ </g>
+ <g
+ id="g33">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g31">
+ <switch
+ id="switch29">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 58px; height: 1px; padding-top: 20px; margin-left: 60px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
+ <xhtml:pre
+ style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x0</xhtml:pre>
+ </xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="118"
+ y="24"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="end"
+ id="text27">0x0</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g37">
+ <rect
+ x="120"
+ y="55"
+ width="200"
+ height="40"
+ fill="none"
+ stroke="rgb(0, 0, 0)"
+ pointer-events="all"
+ id="rect35" />
+ </g>
+ <g
+ id="g45">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g43">
+ <switch
+ id="switch41">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 75px; margin-left: 121px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ospi.tispl(2M)</xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="220"
+ y="79"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="middle"
+ id="text39">ospi.tispl(2M)</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g49">
+ <rect
+ x="0"
+ y="45"
+ width="120"
+ height="30"
+ fill="none"
+ stroke="none"
+ pointer-events="all"
+ id="rect47" />
+ </g>
+ <g
+ id="g57">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g55">
+ <switch
+ id="switch53">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 118px; height: 1px; padding-top: 60px; margin-left: 0px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
+ <xhtml:pre
+ style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x80000</xhtml:pre>
+ </xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="118"
+ y="64"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="end"
+ id="text51">0x80000</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g61">
+ <rect
+ x="120"
+ y="95"
+ width="200"
+ height="40"
+ fill="none"
+ stroke="rgb(0, 0, 0)"
+ pointer-events="all"
+ id="rect59" />
+ </g>
+ <g
+ id="g69">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g67">
+ <switch
+ id="switch65">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 115px; margin-left: 121px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ospi.u-boot(4M)</xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="220"
+ y="119"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="middle"
+ id="text63">ospi.u-boot(4M)</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g73">
+ <rect
+ x="0"
+ y="85"
+ width="120"
+ height="30"
+ fill="none"
+ stroke="none"
+ pointer-events="all"
+ id="rect71" />
+ </g>
+ <g
+ id="g81">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g79">
+ <switch
+ id="switch77">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 118px; height: 1px; padding-top: 100px; margin-left: 0px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
+ <xhtml:pre
+ style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x280000</xhtml:pre>
+ </xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="118"
+ y="104"
+ fill="#000000"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="end"
+ id="text75">0x280000</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g85">
+ <rect
+ x="120"
+ y="135"
+ width="200"
+ height="40"
+ fill="none"
+ stroke="rgb(0, 0, 0)"
+ pointer-events="all"
+ id="rect83" />
+ </g>
+ <g
+ id="g93">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g91">
+ <switch
+ id="switch89">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 155px; margin-left: 121px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ospi.env(128K)</xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="220"
+ y="159"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="middle"
+ id="text87">ospi.env(128K)</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g97">
+ <rect
+ x="0"
+ y="125"
+ width="120"
+ height="30"
+ fill="none"
+ stroke="none"
+ pointer-events="all"
+ id="rect95" />
+ </g>
+ <g
+ id="g105">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g103">
+ <switch
+ id="switch101">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 118px; height: 1px; padding-top: 140px; margin-left: 0px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
+ <xhtml:pre
+ style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x680000</xhtml:pre>
+ </xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="118"
+ y="144"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="end"
+ id="text99">0x680000</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g109">
+ <rect
+ x="120"
+ y="175"
+ width="200"
+ height="40"
+ fill="none"
+ stroke="rgb(0, 0, 0)"
+ pointer-events="all"
+ id="rect107" />
+ </g>
+ <g
+ id="g117">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g115">
+ <switch
+ id="switch113">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 195px; margin-left: 121px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ospi.env.backup(128K)</xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="220"
+ y="199"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="middle"
+ id="text111">ospi.env.backup(128K)</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g121">
+ <rect
+ x="0"
+ y="165"
+ width="120"
+ height="30"
+ fill="none"
+ stroke="none"
+ pointer-events="all"
+ id="rect119" />
+ </g>
+ <g
+ id="g129">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g127">
+ <switch
+ id="switch125">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 118px; height: 1px; padding-top: 180px; margin-left: 0px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
+ <xhtml:pre
+ style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x6A0000</xhtml:pre>
+ </xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="118"
+ y="184"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="end"
+ id="text123">0x6A0000</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g133">
+ <rect
+ x="120"
+ y="215"
+ width="200"
+ height="40"
+ fill="none"
+ stroke="rgb(0, 0, 0)"
+ pointer-events="all"
+ id="rect131" />
+ </g>
+ <g
+ id="g141">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g139">
+ <switch
+ id="switch137">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 235px; margin-left: 121px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">padding(1280K)</xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="220"
+ y="239"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="middle"
+ id="text135">padding(1280K)</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g145">
+ <rect
+ x="0"
+ y="205"
+ width="120"
+ height="30"
+ fill="none"
+ stroke="none"
+ pointer-events="all"
+ id="rect143" />
+ </g>
+ <g
+ id="g153">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g151">
+ <switch
+ id="switch149">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 118px; height: 1px; padding-top: 220px; margin-left: 0px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
+ <xhtml:pre
+ style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x6C0000</xhtml:pre>
+ </xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="118"
+ y="224"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="end"
+ id="text147">0x6C0000</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g157">
+ <rect
+ x="120"
+ y="255"
+ width="200"
+ height="40"
+ fill="none"
+ stroke="rgb(0, 0, 0)"
+ pointer-events="all"
+ id="rect155" />
+ </g>
+ <g
+ id="g165">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g163">
+ <switch
+ id="switch161">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 275px; margin-left: 121px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ospi.rootfs(UBIFS)</xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="220"
+ y="279"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="middle"
+ id="text159">ospi.rootfs(UBIFS)</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g169">
+ <rect
+ x="0"
+ y="245"
+ width="120"
+ height="30"
+ fill="none"
+ stroke="none"
+ pointer-events="all"
+ id="rect167" />
+ </g>
+ <g
+ id="g177">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g175">
+ <switch
+ id="switch173">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 118px; height: 1px; padding-top: 260px; margin-left: 0px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
+ <xhtml:pre
+ style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x800000</xhtml:pre>
+ </xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="118"
+ y="264"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="end"
+ id="text171">0x800000</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g181">
+ <rect
+ x="120"
+ y="295"
+ width="200"
+ height="40"
+ fill="none"
+ stroke="rgb(0, 0, 0)"
+ pointer-events="all"
+ id="rect179" />
+ </g>
+ <g
+ id="g189">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g187">
+ <switch
+ id="switch185">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 198px; height: 1px; padding-top: 315px; margin-left: 121px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: center;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ospi.phypattern(256k)</xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="220"
+ y="319"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="middle"
+ id="text183">ospi.phypattern(256k)</text>
+ </switch>
+ </g>
+ </g>
+ <g
+ id="g193">
+ <rect
+ x="0"
+ y="285"
+ width="120"
+ height="30"
+ fill="none"
+ stroke="none"
+ pointer-events="all"
+ id="rect191" />
+ </g>
+ <g
+ id="g201">
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g199">
+ <switch
+ id="switch197">
+ <foreignObject
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ style="overflow: visible; text-align: left;">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 118px; height: 1px; padding-top: 300px; margin-left: 0px;">
+ <xhtml:div
+ data-drawio-colors="color: rgb(0, 0, 0); "
+ style="box-sizing: border-box; font-size: 0px; text-align: right;">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">
+ <xhtml:pre
+ style="box-sizing: border-box; font-family: SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", Courier, monospace; line-height: 1.4; margin-top: 0px; margin-bottom: 0px; padding: 12px; overflow: auto; color: rgb(64, 64, 64); text-align: start;">0x3FC0000</xhtml:pre>
+ </xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="118"
+ y="304"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="end"
+ id="text195">0x3FC0000</text>
+ </switch>
+ </g>
+ </g>
+ </g>
+</svg>
diff --git a/doc/board/ti/j721e_evm.rst b/doc/board/ti/j721e_evm.rst
index a422a9b..80d91ca 100644
--- a/doc/board/ti/j721e_evm.rst
+++ b/doc/board/ti/j721e_evm.rst
@@ -150,6 +150,33 @@
.. image:: img/sysfw.itb.svg
:alt: sysfw.itb image format
+OSPI:
+-----
+ROM supports booting from OSPI from offset 0x0.
+
+Flashing images to OSPI:
+
+Below commands can be used to download tiboot3.bin, tispl.bin, u-boot.img,
+and sysfw.itb over tftp and then flash those to OSPI at their respective
+addresses.
+
+.. prompt:: bash =>
+
+ sf probe
+ tftp ${loadaddr} tiboot3.bin
+ sf update $loadaddr 0x0 $filesize
+ tftp ${loadaddr} tispl.bin
+ sf update $loadaddr 0x80000 $filesize
+ tftp ${loadaddr} u-boot.img
+ sf update $loadaddr 0x280000 $filesize
+ tftp ${loadaddr} sysfw.itb
+ sf update $loadaddr 0x6C0000 $filesize
+
+Flash layout for OSPI:
+
+.. image:: img/ospi_sysfw.svg
+ :alt: OSPI flash partition layout
+
R5 Memory Map:
--------------
@@ -193,35 +220,8 @@
- 0x41cffbfc
- 0x41cfffff
-OSPI:
------
-ROM supports booting from OSPI from offset 0x0.
-
-Flashing images to OSPI:
-
-Below commands can be used to download tiboot3.bin, tispl.bin, u-boot.img,
-and sysfw.itb over tftp and then flash those to OSPI at their respective
-addresses.
-
-.. prompt:: bash =>
-
- sf probe
- tftp ${loadaddr} tiboot3.bin
- sf update $loadaddr 0x0 $filesize
- tftp ${loadaddr} tispl.bin
- sf update $loadaddr 0x80000 $filesize
- tftp ${loadaddr} u-boot.img
- sf update $loadaddr 0x280000 $filesize
- tftp ${loadaddr} sysfw.itb
- sf update $loadaddr 0x6C0000 $filesize
-
-Flash layout for OSPI:
-
-.. image:: img/ospi_sysfw.svg
- :alt: OSPI flash partition layout
-
-Firmwares:
-----------
+Firmware:
+---------
The J721e u-boot allows firmware to be loaded for the Cortex-R5 subsystem.
The CPSW5G in J7200 and CPSW9G in J721E present in MAIN domain is configured
diff --git a/doc/board/ti/j722s_evm.rst b/doc/board/ti/j722s_evm.rst
new file mode 100644
index 0000000..10b2439
--- /dev/null
+++ b/doc/board/ti/j722s_evm.rst
@@ -0,0 +1,260 @@
+.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+.. sectionauthor:: Jayesh Choudhary <j-choudhary@ti.com>
+
+J722S-EVM Platform
+==================
+
+The J722S is a family of application processors built for Automotive and
+Linux Application development. J722S family of SoCs is a superset of the
+AM62P SoC family and shares similar memory map, thus the nodes are being
+reused from AM62P includes instead of duplicating the definitions.
+
+Some highlights of J722S SoC (in addition to AM62P SoC features) are:
+
+* Two Cortex-R5F for Functional Safety or general-purpose usage and
+ two C7x floating point vector DSP with Matrix Multiply Accelerator
+ for deep learning.
+
+* Vision Processing Accelerator (VPAC) with image signal processor
+ and Depth and Motion Processing Accelerator (DMPAC).
+
+* 7xUARTs, 3xSPI, 5xI2C, 2xUSB2, 2xCAN-FD, 3xMMC and SD, GPMC for
+ NAND/FPGA connection, OSPI memory controller, 5xMcASP for audio,
+ 4xCSI-RX for Camera, 1 PCIe Gen3 controller, USB3.0 eCAP/eQEP,
+ ePWM, among other peripherals.
+
+For those interested, more details about this SoC can be found in the
+Technical Reference Manual here: https://www.ti.com/lit/zip/sprujb3
+
+Boot Flow:
+----------
+
+The bootflow is exactly the same as all SoCs in the am62xxx extended SoC
+family. Below is the pictorial representation:
+
+.. image:: img/boot_diagram_k3_current.svg
+ :alt: Boot flow diagram
+
+- Here TIFS acts as master and provides all the critical services. R5/A53
+ requests TIFS to get these services done as shown in the above diagram.
+
+Sources:
+--------
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_boot_sources
+ :end-before: .. k3_rst_include_end_boot_sources
+
+Build procedure:
+----------------
+
+0. Setup the environment variables:
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_common_env_vars_desc
+ :end-before: .. k3_rst_include_end_common_env_vars_desc
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_board_env_vars_desc
+ :end-before: .. k3_rst_include_end_board_env_vars_desc
+
+Set the variables corresponding to this platform:
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_common_env_vars_defn
+ :end-before: .. k3_rst_include_end_common_env_vars_defn
+
+.. code-block:: bash
+
+ $ export UBOOT_CFG_CORTEXR=j722s_evm_r5_defconfig
+ $ export UBOOT_CFG_CORTEXA=j722s_evm_a53_defconfig
+ $ export TFA_BOARD=lite
+ $ export OPTEE_PLATFORM=k3-am62x
+ $ export OPTEE_EXTRA_ARGS="CFG_WITH_SOFTWARE_PRNG=y"
+
+.. j722s_evm_rst_include_start_build_steps
+
+1. Trusted Firmware-A:
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_build_steps_tfa
+ :end-before: .. k3_rst_include_end_build_steps_tfa
+
+
+2. OP-TEE:
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_build_steps_optee
+ :end-before: .. k3_rst_include_end_build_steps_optee
+
+3. U-Boot:
+
+* 3.1 R5:
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_build_steps_spl_r5
+ :end-before: .. k3_rst_include_end_build_steps_spl_r5
+
+* 3.2 A53:
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_build_steps_uboot
+ :end-before: .. k3_rst_include_end_build_steps_uboot
+.. j722s_evm_rst_include_end_build_steps
+
+Target Images
+--------------
+
+In order to boot we need tiboot3.bin, tispl.bin and u-boot.img. Each SoC
+variant (HS-FS, HS-SE) requires a different source for these files.
+
+ - HS-FS
+
+ * tiboot3-j722s-hs-fs-evm.bin from step 3.1
+ * tispl.bin, u-boot.img from step 3.2
+
+ - HS-SE
+
+ * tiboot3-j722s-hs-evm.bin from step 3.1
+ * tispl.bin, u-boot.img from step 3.2
+
+Image formats:
+--------------
+
+- tiboot3.bin
+
+.. image:: img/multi_cert_tiboot3.bin.svg
+ :alt: tiboot3.bin image format
+
+- tispl.bin
+
+.. image:: img/dm_tispl.bin.svg
+ :alt: tispl.bin image format
+
+A53 SPL DDR Memory Layout
+-------------------------
+
+.. j722s_evm_rst_include_start_ddr_mem_layout
+
+This provides an overview memory usage in A53 SPL stage.
+
+.. list-table::
+ :widths: 16 16 16
+ :header-rows: 1
+
+ * - Region
+ - Start Address
+ - End Address
+
+ * - EMPTY
+ - 0x80000000
+ - 0x80080000
+
+ * - TEXT BASE
+ - 0x80080000
+ - 0x800d8000
+
+ * - EMPTY
+ - 0x800d8000
+ - 0x80477660
+
+ * - STACK
+ - 0x80477660
+ - 0x80477e60
+
+ * - GD
+ - 0x80477e60
+ - 0x80478000
+
+ * - MALLOC
+ - 0x80478000
+ - 0x80480000
+
+ * - EMPTY
+ - 0x80480000
+ - 0x80a00000
+
+ * - BSS
+ - 0x80a00000
+ - 0x80a80000
+
+ * - BLOBS
+ - 0x80a80000
+ - 0x80d00400
+
+ * - EMPTY
+ - 0x80d00400
+ - 0x81000000
+.. j722s_evm_rst_include_end_ddr_mem_layout
+
+Switch Setting for Boot Mode
+----------------------------
+
+Boot Mode pins provide means to select the boot mode and options before the
+device is powered up. After every POR, they are the main source to populate
+the Boot Parameter Tables.
+
+The following table shows some common boot modes used on J722S-EVM
+platform. More details can be found in the Technical Reference Manual:
+https://www.ti.com/lit/zip/sprujb3 under the `Boot Mode Pins` section.
+
+.. note::
+
+ This device is very new. Currently only UART boot is available while
+ we continue to add support for the other bootmodes.
+
+.. list-table:: Boot Modes
+ :widths: 16 16 16
+ :header-rows: 1
+
+ * - Switch Label
+ - SW3: 12345678
+ - SW4: 12345678
+
+ * - SD
+ - 11000010
+ - 01000000
+
+ * - OSPI
+ - 11001110
+ - 00000000
+
+ * - EMMC
+ - 11010010
+ - 00000000
+
+ * - UART
+ - 11011100
+ - 00000000
+
+ * - USB DFU
+ - 11001010
+ - 00000000
+
+For SW2 and SW1, the switch state in the "ON" position = 1.
+
+Debugging U-Boot
+----------------
+
+See :ref:`Common Debugging environment - OpenOCD<k3_rst_refer_openocd>`: for
+detailed setup information.
+
+.. warning::
+
+ **OpenOCD support after**: v0.12.0
+
+ While support for the entire K3 generation including the am62xxx
+ extended family was added before v0.12.0, the tcl scripts for the
+ am62px have been accepted and will be available in the next release of
+ OpenOCD. It may be necessary to build OpenOCD from source depending on
+ the version your distribution has packaged.
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_openocd_connect_XDS110
+ :end-before: .. k3_rst_include_end_openocd_connect_XDS110
+
+To start OpenOCD and connect to the board
+
+.. code-block:: bash
+
+ openocd -f board/ti_j722sevm.cfg
diff --git a/doc/board/ti/j784s4_evm.rst b/doc/board/ti/j784s4_evm.rst
index 5c4bd2c..2ffec3d 100644
--- a/doc/board/ti/j784s4_evm.rst
+++ b/doc/board/ti/j784s4_evm.rst
@@ -153,6 +153,31 @@
.. image:: img/dm_tispl.bin.svg
:alt: tispl.bin format
+OSPI:
+-----
+ROM supports booting from OSPI from offset 0x0.
+
+Flashing images to OSPI NOR:
+
+Below commands can be used to download tiboot3.bin, tispl.bin, and
+u-boot.img over tftp and then flash those to OSPI at their respective
+addresses.
+
+.. prompt:: bash =>
+
+ sf probe
+ tftp ${loadaddr} tiboot3.bin
+ sf update $loadaddr 0x0 $filesize
+ tftp ${loadaddr} tispl.bin
+ sf update $loadaddr 0x80000 $filesize
+ tftp ${loadaddr} u-boot.img
+ sf update $loadaddr 0x280000 $filesize
+
+Flash layout for OSPI NOR:
+
+.. image:: img/ospi_sysfw3.svg
+ :alt: OSPI NOR flash partition layout
+
R5 Memory Map
-------------
@@ -262,6 +287,9 @@
* - SD
- 0000
+ * - OSPI
+ - 0010
+
* - EMMC
- 0110
diff --git a/doc/board/ti/k3.rst b/doc/board/ti/k3.rst
index a1c01d1..67b066a 100644
--- a/doc/board/ti/k3.rst
+++ b/doc/board/ti/k3.rst
@@ -42,6 +42,7 @@
../beagle/j721e_beagleboneai64
j721e_evm
j721s2_evm
+ j722s_evm
j784s4_evm
Boot Flow Overview
@@ -51,14 +52,14 @@
Management Subsystem (SMS) which will secure the device and start a core
in the wakeup domain to run the ROM code. ROM will then initialize the
boot media needed to load the binaries packaged inside `tiboot3.bin`,
-including a 32bit U-Boot SPL, (called the wakup SPL) that ROM will jump
+including a 32bit U-Boot SPL, (called the wakeup SPL) that ROM will jump
to after it has finished loading everything into internal SRAM.
.. image:: img/boot_flow_01.svg
:alt: Boot flow up to wakeup domain SPL
The wakeup SPL, running on a wakeup domain core, will initialize DDR and
-any peripherals needed load the larger binaries inside the `tispl.bin`
+any peripherals needed to load the larger binaries inside the `tispl.bin`
into DDR. Once loaded the wakeup SPL will start one of the 'big'
application cores inside the main domain to initialize the main domain,
starting with Trusted Firmware-A (TF-A), before moving on to start
@@ -94,7 +95,7 @@
* Combined binary with a split firmware: (eg: AM62)
For devices that utilize the split binary approach, ROM is not capable
-of loading the firmware into the SoC requiring the wakeup domain's
+of loading the firmware into the SoC, requiring the wakeup domain's
U-Boot SPL to load the firmware.
Devices with a split firmware will have two firmwares loaded into the
@@ -114,8 +115,8 @@
authenticated boot flow for secure boot. HS-FS (High Security - Field
Securable) is the state of a K3 device before it has been eFused with
customer security keys. In the HS-FS state the authentication still can
-function as in HS-SE but as there are no customer keys to verify the
-signatures against the authentication will pass for certificates signed
+function as in HS-SE, but as there are no customer keys to verify the
+signatures against, the authentication will pass for certificates signed
with any key.
Chain of trust
@@ -203,6 +204,11 @@
Build Procedure
---------------
+.. note ::
+
+ Make sure you have installed all necessary host package dependencies
+ before proceeding. See :ref:`build/gcc:Building with GCC`.
+
Depending on the specifics of your device, you will need three or more
binaries to boot your SoC.
@@ -387,6 +393,30 @@
| `tispl.bin` for HS devices or `tispl.bin_unsigned` for GP devices
| `u-boot.img` for HS devices or `u-boot.img_unsigned` for GP devices
+Capsules
+--------
+
+Most K3 boards have support for UEFI capsule update via capsule-on-disk
+functionality. Check the ``CONFIG_EFI_CAPSULE_ON_DISK`` config option for
+the board under question to verify. If configured, capsules for each of the
+binaries above are automatically generated as part of the binary's build.
+They are named `<binary>-capsule.bin`. For example, the capsule for
+`u-boot.img` would be called `uboot-capsule.bin`.
+
+See :ref:`uefi_capsule_update_ref` for more information on U-Boot's support
+for capsule update and how they are applied.
+
+Each board defines the capsules generated, including where those capsules
+are applied. See the ``update_info`` definition for a board, typically
+found at `board/ti/<board>/evm.c`. For example, `board/ti/am62x/evm.c`.
+Usually, if the board has OSPI flash, the capsules will be applied there,
+else the boot partition of the eMMC device.
+
+Once applied, the board will have U-Boot binaries in on-board non-volatile
+storage. To start booting from that storage, set the bootmode pins
+accordingly. Future updates can be performed by using the capsules
+generated from the corresponding U-Boot builds.
+
FIT signature signing
---------------------
diff --git a/doc/board/wexler/index.rst b/doc/board/wexler/index.rst
new file mode 100644
index 0000000..308aad7
--- /dev/null
+++ b/doc/board/wexler/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+WEXLER
+======
+
+.. toctree::
+ :maxdepth: 2
+
+ qc750
diff --git a/doc/board/wexler/qc750.rst b/doc/board/wexler/qc750.rst
new file mode 100644
index 0000000..b61e401
--- /dev/null
+++ b/doc/board/wexler/qc750.rst
@@ -0,0 +1,125 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for the WEXLER QC750 tablet
+==================================
+
+``DISCLAMER!`` Moving your WEXLER QC750 to use U-Boot assumes replacement
+of the vendor bootloader. Vendor Android firmwares will no longer be able
+to run on the device. This replacement IS reversible.
+
+Quick Start
+-----------
+
+- Build U-Boot
+- Process U-Boot
+- Flashing U-Boot into the eMMC
+- Boot
+- Self Upgrading
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=arm-linux-gnueabi-
+ $ make qc750_defconfig
+ $ make
+
+After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin``
+image, ready for further processing.
+
+Process U-Boot
+--------------
+
+``DISCLAMER!`` All questions related to the re-crypt work should be asked
+in re-crypt repo issues. NOT HERE!
+
+re-crypt is a tool that processes the ``u-boot-dtb-tegra.bin`` binary into form
+usable by device. This process is required only on the first installation or
+to recover the device in case of a failed update.
+
+Permanent installation can be performed either by using the tegrarcm or by
+pre-loading just built U-Boot into RAM.
+
+Processing for the NV3P protocol
+********************************
+
+.. code-block:: bash
+
+ $ git clone https://gitlab.com/grate-driver/re-crypt.git
+ $ cd re-crypt # place your u-boot-dtb-tegra.bin here
+ $ ./re-crypt.py --dev qc750
+
+The script will produce a ``repart-block.bin`` ready to flash.
+
+Processing for pre-loaded U-Boot
+********************************
+
+The procedure is the same, but the ``--split`` argument is used with the
+``re-crypt.py``. The script will produce ``bct.img`` and ``ebt.img`` ready
+to flash.
+
+Flashing U-Boot into the eMMC
+-----------------------------
+
+``DISCLAMER!`` All questions related to tegrarcm should be asked in the proper
+place. NOT HERE! Flashing U-Boot will erase all eMMC, so make a backup before!
+
+Permanent installation can be performed either by using the nv3p protocol or by
+pre-loading just built U-Boot into RAM.
+
+Flashing with the NV3P protocol
+*******************************
+
+Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can
+enter it either by using ``wheelie`` with the correct ``blob.bin`` file or by
+pre-loading vendor bootloader with the Fusée Gelée.
+
+With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in
+encrypted state in form, which can just be written RAW at the start of eMMC.
+
+.. code-block:: bash
+
+ $ wheelie --bct qc750.bct --bl bootloader.bin
+ $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin
+
+When flashing is done, reboot the device.
+
+Flashing with a pre-loaded U-Boot
+*********************************
+
+U-Boot pre-loaded into RAM acts the same as when it was booted "cold". Currently
+U-Boot supports bootmenu entry fastboot, which allows to write a processed copy
+of U-Boot permanently into eMMC.
+
+While pre-loading U-Boot, hold the ``volume down`` button which will trigger
+the bootmenu. There, select ``fastboot`` using the volume and power buttons.
+After, on host PC, do:
+
+.. code-block:: bash
+
+ $ fastboot flash 0.1 bct.img
+ $ fastboot flash 0.2 ebt.img
+ $ fastboot reboot
+
+Device will reboot.
+
+Boot
+----
+
+To boot Linux, U-Boot will look for an ``extlinux.conf`` on MicroSD and then on
+eMMC. Additionally, if the Volume Down button is pressed while booting, the
+device will enter bootmenu. Bootmenu contains entries to mount MicroSD and eMMC
+as mass storage, fastboot, reboot, reboot RCM, poweroff, enter U-Boot console
+and update bootloader (check the next chapter).
+
+Flashing ``repart-block.bin`` eliminates vendor restrictions on eMMC and allows
+the user to use/partition it in any way the user desires.
+
+Self Upgrading
+--------------
+
+Place your ``u-boot-dtb-tegra.bin`` on the first partition of the MicroSD card
+and insert it into the tablet. Enter bootmenu, choose update the bootloader
+option with the Power button and U-Boot should update itself. Once the process
+is completed, U-Boot will ask to press any button to reboot.
diff --git a/doc/develop/bootstd.rst b/doc/develop/bootstd.rst
index a07a725..3463108 100644
--- a/doc/develop/bootstd.rst
+++ b/doc/develop/bootstd.rst
@@ -39,7 +39,7 @@
A bootflow is a file that describes how to boot a distro. Conceptually there can
be different formats for that file but at present U-Boot only supports the
-BootLoaderSpec_ format. which looks something like this::
+BootLoaderSpec_ format which looks something like this::
menu autoboot Welcome to Fedora-Workstation-armhfp-31-1.9. Automatic boot in # second{,s}. Press a key for options.
menu title Fedora-Workstation-armhfp-31-1.9 Boot Options.
@@ -52,7 +52,7 @@
initrd /initramfs-5.3.7-301.fc31.armv7hl.img
As you can see it specifies a kernel, a ramdisk (initrd) and a directory from
-which to load devicetree files. The details are described in distro_bootcmd_.
+which to load Device Tree files. The details are described in distro_bootcmd_.
The bootflow is provided by the distro. It is not part of U-Boot. U-Boot's job
is simply to interpret the file and carry out the instructions. This allows
@@ -85,7 +85,7 @@
--------
Once the list of filesystems is provided, how does U-Boot find the bootflow
-files in these filesystems. That is the job of bootmeth. Each boot method has
+files in these filesystems? That is the job of bootmeth. Each boot method has
its own way of doing this.
For example, the distro bootmeth simply looks through the provided filesystem
@@ -106,7 +106,7 @@
Boot process
------------
-U-Boot tries to use the 'lazy init' approach whereever possible and distro boot
+U-Boot tries to use the 'lazy init' approach wherever possible and distro boot
is no exception. The algorithm is::
while (get next bootdev)
@@ -174,13 +174,13 @@
Bootdev uclass
--------------
-The bootdev uclass provides an simple API call to obtain a bootflows from a
+The bootdev uclass provides a simple API call to obtain a bootflow from a
device::
int bootdev_get_bootflow(struct udevice *dev, struct bootflow_iter *iter,
struct bootflow *bflow);
-This takes a iterator which indicates the bootdev, partition and bootmeth to
+This takes an iterator which indicates the bootdev, partition and bootmeth to
use. It returns a bootflow. This is the core of the bootdev implementation. The
bootdev drivers that implement this differ depending on the media they are
reading from, but each is responsible for returning a valid bootflow if
@@ -188,7 +188,7 @@
A helper called `bootdev_find_in_blk()` makes it fairly easy to implement this
function for each media device uclass, in a few lines of code. For many types
-ot bootdevs, the `get_bootflow` member can be NULL, indicating that the default
+of bootdevs, the `get_bootflow` member can be NULL, indicating that the default
handler is used. This is called `default_get_bootflow()` and it only works with
block devices.
@@ -196,7 +196,7 @@
Bootdev drivers
---------------
-A bootdev driver is typically fairly simple. Here is one for mmc::
+A bootdev driver is typically fairly simple. Here is one for MMC::
static int mmc_bootdev_bind(struct udevice *dev)
{
@@ -328,7 +328,7 @@
Here, `eth_bootdev` is the name of the Ethernet bootdev driver and `dev`
-is the ethernet device. This function is safe to call even if standard boot is
+is the Ethernet device. This function is safe to call even if standard boot is
not enabled, since it does nothing in that case. It can be added to all uclasses
which implement suitable media.
@@ -340,7 +340,7 @@
work. This includes global information about the state of standard boot. See
`struct bootstd_priv` for this structure, accessed with `bootstd_get_priv()`.
-Within the devicetree, if you add bootmeth devices, they should be children of
+Within the Device Tree, if you add bootmeth devices, they should be children of
the bootstd device. See `arch/sandbox/dts/test.dts` for an example of this.
@@ -349,12 +349,12 @@
Automatic devices
-----------------
-It is possible to define all the required devices in the devicetree manually,
+It is possible to define all the required devices in the Device Tree manually,
but it is not necessary. The bootstd uclass includes a `dm_scan_other()`
function which creates the bootstd device if not found. If no bootmeth devices
are found at all, it creates one for each available bootmeth driver.
-If your devicetree has any bootmeth device it must have all of them that you
+If your Device Tree has any bootmeth device it must have all of them that you
want to use, since no bootmeth devices will be created automatically in that
case.
@@ -363,8 +363,8 @@
----------------
If a bootdev is complicated or needs configuration information, it can be
-added to the devicetree as a child of the media device. For example, imagine a
-bootdev which reads a bootflow from SPI flash. The devicetree fragment might
+added to the Device Tree as a child of the media device. For example, imagine a
+bootdev which reads a bootflow from SPI flash. The Device Tree fragment might
look like this::
spi@0 {
@@ -398,7 +398,7 @@
option also. For example, `CONFIG_BOOTMETH_EXTLINUX` enables support for
booting from a disk using an `extlinux.conf` file.
-To enable all feature sof standard boot, use `CONFIG_BOOTSTD_FULL`. This
+To enable all features of standard boot, use `CONFIG_BOOTSTD_FULL`. This
includes the full set of commands, more error messages when things go wrong and
bootmeth ordering with the bootmeths environment variable.
@@ -492,9 +492,9 @@
This describes how standard boot progresses through to booting an operating
system.
-To start. all the necessary devices must be bound, including bootstd, which
+To start, all the necessary devices must be bound, including bootstd, which
provides the top-level `struct bootstd_priv` containing optional configuration
-information. The bootstd device is also holds the various lists used while
+information. The bootstd device also holds the various lists used while
scanning. This step is normally handled automatically by driver model, as
described in `Automatic Devices`_.
@@ -504,7 +504,7 @@
devices and one or more bootmeth devices.
Once these are ready, typically a `bootflow scan` command is issued. This kicks
-of the iteration process, which involves hunting for bootdevs and looking
+off the iteration process, which involves hunting for bootdevs and looking
through the bootdevs and their partitions one by one to find bootflows.
Iteration is kicked off using `bootflow_scan_first()`.
@@ -526,7 +526,7 @@
- If `label` indicates a numeric bootdev number (e.g. "2") then
`BOOTFLOW_METHF_SINGLE_DEV` is set. In this case, moving to the next bootdev
- simple stops, since there is only one. No hunters are used.
+ simply stops, since there is only one. No hunters are used.
- If `label` indicates a particular media device (e.g. "mmc1") then
`BOOTFLOWIF_SINGLE_MEDIA` is set. In this case, moving to the next bootdev
processes just the children of the media device. Hunters are used, in this
@@ -554,7 +554,7 @@
Next, the ordering of bootmeths is determined, by `bootmeth_setup_iter_order()`.
By default the ordering is again by sequence number, i.e. the `/aliases` node,
-or failing that the order in the devicetree. But the `bootmeth order` command
+or failing that the order in the Device Tree. But the `bootmeth order` command
or `bootmeths` environment variable can be used to set up an ordering. If that
has been done, the ordering is in `struct bootstd_priv`, so that ordering is
simply copied into the iterator. Either way, the `method_order` array it set up,
@@ -652,12 +652,12 @@
bootflow to be immediately booted. Assuming it is successful, the iteration never
completes.
-Also note that the iterator hold the **current** combination being considered.
+Also note that the iterator holds the **current** combination being considered.
So when `iter_incr()` is called, it increments to the next one and returns it,
the new **current** combination.
Note also the `err` field in `struct bootflow_iter`. This is normally 0 and has
-thus has no effect on `iter_inc()`. But if it is non-zero, signalling an error,
+thus no effect on `iter_inc()`. But if it is non-zero, signalling an error,
it indicates to the iterator what it should do when called. It can force moving
to the next partition, or bootdev, for example. The special values
`BF_NO_MORE_PARTS` and `BF_NO_MORE_DEVICES` handle this. When `iter_incr` sees
@@ -675,7 +675,7 @@
method `bootdev_get_bootflow()` to ask the bootdev to return a bootflow. It
passes the iterator to the bootdev method, so that function knows what we are
talking about. At first, the bootflow is set up in the state `BOOTFLOWST_BASE`,
-with just the `method` and `dev` intiialised. But the bootdev may fill in more,
+with just the `method` and `dev` initialised. But the bootdev may fill in more,
e.g. updating the state, depending on what it finds. For global bootmeths the
`bootmeth_get_bootflow()` function is called instead of
`bootdev_get_bootflow()`.
@@ -733,12 +733,12 @@
extlinux boot, this parses and processes the `extlinux.conf` file that was read.
See `extlinux_boot()` for how that works. The processing may involve reading
additional files, which is handled by the `read_file()` method, which is
-`extlinux_read_file()` in this case. All bootmethds should support reading
+`extlinux_read_file()` in this case. All bootmeths should support reading
files, since the bootflow is typically only the basic instructions and does not
include the operating system itself, ramdisk, device tree, etc.
The vast majority of the bootstd code is concerned with iterating through
-partitions on bootdevs and using bootmethds to find bootflows.
+partitions on bootdevs and using bootmeths to find bootflows.
How about bootdevs which are not block devices? They are handled by the same
methods as above, but with a different implementation. For example, the bootmeth
diff --git a/doc/develop/cyclic.rst b/doc/develop/cyclic.rst
index 6783149..893c269 100644
--- a/doc/develop/cyclic.rst
+++ b/doc/develop/cyclic.rst
@@ -19,20 +19,26 @@
To register a cyclic function, use something like this::
- static void cyclic_demo(void *ctx)
+ struct donkey {
+ struct cyclic_info cyclic;
+ void (*say)(const char *s);
+ };
+
+ static void cyclic_demo(struct cyclic_info *c)
{
- /* Just a small dummy delay here */
- udelay(10);
+ struct donkey *donkey = container_of(c, struct donkey, cyclic);
+
+ donkey->say("Are we there yet?");
}
-
- int board_init(void)
+
+ int donkey_init(void)
{
- struct cyclic_info *cyclic;
-
+ struct donkey *donkey;
+
+ /* Initialize donkey ... */
+
/* Register demo cyclic function */
- cyclic = cyclic_register(cyclic_demo, 10 * 1000, "cyclic_demo", NULL);
- if (!cyclic)
- printf("Registering of cyclic_demo failed\n");
+ cyclic_register(&donkey->cyclic, cyclic_demo, 10 * 1000, "cyclic_demo");
return 0;
}
diff --git a/doc/develop/devicetree/control.rst b/doc/develop/devicetree/control.rst
index 4cc1457..ca4fb0b 100644
--- a/doc/develop/devicetree/control.rst
+++ b/doc/develop/devicetree/control.rst
@@ -113,9 +113,12 @@
prompted by Kconfig.
However, if `dts/upstream/` hasn't yet received devicetree source file for your
-newly added board support then you can add corresponding devicetree source file
-as `arch/<arch>/dts/<name>.dts`. To select that add `# CONFIG_OF_UPSTREAM is not
-set` and set `DEFAULT_DEVICE_TREE=<name>` when prompted by Kconfig.
+newly added board support then one option is that you can add the corresponding
+devicetree source file as `arch/<arch>/dts/<name>.dts`. To select that add `#
+CONFIG_OF_UPSTREAM is not set` and set `DEFAULT_DEVICE_TREE=<name>` when
+prompted by Kconfig. Another option is that you can use use the "pick" option of
+`dts/update-dts-subtree.sh` mentioned above to bring in the commits that you
+need.
This should include your CPU or SoC's devicetree file. On top of that any U-Boot
specific tweaks (see: :ref:`dttweaks`) can be made for your board.
diff --git a/doc/develop/gdb.rst b/doc/develop/gdb.rst
new file mode 100644
index 0000000..4e359c7
--- /dev/null
+++ b/doc/develop/gdb.rst
@@ -0,0 +1,171 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (c) 2024 Alexander Dahl
+
+Debugging U-Boot with GDB
+=========================
+
+Using a JTAG adapter it is possible to debug a running U-Boot with GDB.
+A common way is to connect a debug adapter to the JTAG connector of your
+board, run a GDB server, connect GDB to the GDB server, and use GDB as usual.
+
+Similarly QEMU can provide a GDB server.
+
+Preparing build
+---------------
+
+Building U-Boot with with reduced optimization (-Og) and without link time
+optimization is recommended for easier debugging::
+
+ CONFIG_CC_OPTIMIZE_FOR_DEBUG=y
+ CONFIG_LTO=n
+
+Otherwise build, install, and run U-Boot as usual.
+
+Using OpenOCD as GDB server
+---------------------------
+
+`OpenOCD <https://openocd.org/>`_ is an open source tool supporting hardware
+debug probes, and providing a GDB server. It is readily available in major Linux
+distributions or you can build it from source.
+
+Here is example of starting OpenOCD on Debian using a J-Link adapter and a
+board with an AT91 SAMA5D2 SoC:
+
+.. code-block:: console
+
+ $ openocd -f interface/jlink.cfg -f target/at91sama5d2.cfg -c 'adapter speed 4000'
+ Open On-Chip Debugger 0.12.0
+ Licensed under GNU GPL v2
+ For bug reports, read
+ http://openocd.org/doc/doxygen/bugs.html
+ Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
+ adapter speed: 4000 kHz
+
+ Info : Listening on port 6666 for tcl connections
+ Info : Listening on port 4444 for telnet connections
+ Info : J-Link V10 compiled Jan 30 2023 11:28:07
+ Info : Hardware version: 10.10
+ Info : VTarget = 3.244 V
+ Info : clock speed 4000 kHz
+ Info : JTAG tap: at91sama5d2.cpu tap/device found: 0x5ba00477 (mfg: 0x23b (ARM Ltd), part: 0xba00, ver: 0x5)
+ Info : at91sama5d2.cpu_a5.0: hardware has 3 breakpoints, 2 watchpoints
+ Info : at91sama5d2.cpu_a5.0: MPIDR level2 0, cluster 0, core 0, mono core, no SMT
+ Info : starting gdb server for at91sama5d2.cpu_a5.0 on 3333
+ Info : Listening on port 3333 for gdb connections
+
+Notice that OpenOCD is listening on port 3333 for GDB connections.
+
+Using QEMU as GDB server
+------------------------
+
+When running U-Boot on QEMU you can used the '-gdb' parameter to provide a
+GDB server:
+
+ qemu-system-riscv64 -M virt -nographic -gdb tcp::3333 -kernel u-boot
+
+Running a GDB session
+----------------------
+
+You need a GDB suited for your target. This can be the GDB coming with your
+toolchain or *gdb-multiarch* available in your Linux distribution.
+
+.. prompt:: bash $
+
+ gdb-multiarch u-boot
+
+In the above command-line *u-boot* is the U-boot binary in your build
+directory. You may need to adjust the path when calling GDB.
+
+Connect to the GDB server like this:
+
+.. code-block:: console
+
+ (gdb) target extended-remote :3333
+ Remote debugging using :3333
+ 0x27fa9ac6 in ?? ()
+ (gdb)
+
+This is fine for debugging before U-Boot relocates itself.
+
+For debugging U-Boot after relocation you need to indicate the relocation
+address to GDB. You can retrieve the relocation address from the U-Boot shell
+with the command *bdinfo*:
+
+.. code-block:: console
+
+ U-Boot> bdinfo
+ boot_params = 0x20000100
+ DRAM bank = 0x00000000
+ -> start = 0x20000000
+ -> size = 0x08000000
+ flashstart = 0x00000000
+ flashsize = 0x00000000
+ flashoffset = 0x00000000
+ baudrate = 115200 bps
+ relocaddr = 0x27f7a000
+ reloc off = 0x0607a000
+ Build = 32-bit
+ current eth = ethernet@f8008000
+ ethaddr = 00:50:c2:31:58:d4
+ IP addr = <NULL>
+ fdt_blob = 0x27b36060
+ new_fdt = 0x27b36060
+ fdt_size = 0x00003e40
+ lmb_dump_all:
+ memory.cnt = 0x1 / max = 0x10
+ memory[0] [0x20000000-0x27ffffff], 0x08000000 bytes flags: 0
+ reserved.cnt = 0x1 / max = 0x10
+ reserved[0] [0x27b31d00-0x27ffffff], 0x004ce300 bytes flags: 0
+ devicetree = separate
+ arch_number = 0x00000000
+ TLB addr = 0x27ff0000
+ irq_sp = 0x27b36050
+ sp start = 0x27b36040
+ Early malloc usage: cd8 / 2000
+
+Look out for the line starting with *relocaddr* which has the address
+you need, ``0x27f7a000`` in this case.
+
+On most architectures (not sandbox, x86, Xtensa) the global data pointer is
+stored in a fixed register:
+
+============ ========
+Architecture Register
+============ ========
+arc r25
+arm r9
+arm64 x18
+m68k d7
+microblaze r31
+mips k0
+nios2 gp
+powerpc r2
+riscv gp
+sh r13
+============ ========
+
+On these architecture the relocation address cat be determined by
+dereferencing the global data pointer stored in register, *r9* in the example:
+
+.. code-block:: console
+
+ (gdb) p/x (*(struct global_data*)$r9)->relocaddr
+ $1 = 0x27f7a000
+
+In the GDB shell discard the previously loaded symbol file and add it once
+again with the relocation address like this:
+
+.. code-block:: console
+
+ (gdb) symbol-file
+ Discard symbol table from `/home/adahl/build/u-boot/v2024.04.x/u-boot'? (y or n) y
+ No symbol file now.
+ (gdb) add-symbol-file u-boot 0x27f7a000
+ add symbol table from file "u-boot" at
+ .text_addr = 0x27f7a000
+ (y or n) y
+ Reading symbols from u-boot...
+ (gdb)
+
+You can now use GDB as usual, setting breakpoints, printing backtraces,
+inspecting variables, stepping through the code, etc.
diff --git a/doc/develop/index.rst b/doc/develop/index.rst
index f82e148..f9c4bf8 100644
--- a/doc/develop/index.rst
+++ b/doc/develop/index.rst
@@ -60,6 +60,7 @@
:maxdepth: 1
crash_dumps
+ gdb
trace
Packaging
diff --git a/doc/develop/process.rst b/doc/develop/process.rst
index 92477d0..0542b3f 100644
--- a/doc/develop/process.rst
+++ b/doc/develop/process.rst
@@ -34,7 +34,7 @@
The end of a Release Cycle is marked by the release of a new U-Boot version.
Merge Window
-------------
+^^^^^^^^^^^^
The Merge Window is the period when new patches get submitted (and hopefully
accepted) for inclusion into U-Boot mainline. This period lasts for 21 days (3
@@ -44,7 +44,7 @@
boards, or other new features or reorganization of code) is accepted.
Twilight Time
--------------
+^^^^^^^^^^^^^
Usually patches do not get accepted as they are - the peer review that takes
place will usually require changes and resubmissions of the patches before they
@@ -65,13 +65,13 @@
merged for the upcoming release.
Stabilization Period
---------------------
+^^^^^^^^^^^^^^^^^^^^
During the Stabilization Period only patches containing bug fixes get
applied.
Corner Cases
-------------
+^^^^^^^^^^^^
Sometimes it is not clear if a patch contains a bug fix or not.
For example, changes that remove dead code, unused macros etc. or
@@ -108,6 +108,19 @@
In U-Boot, ``"-rc1"`` will only be released after all (or at least most of
the) patches that were submitted during the merge window have been applied.
+Resyncing of the device tree subtree
+------------------------------------
+
+As explained in :doc:`devicetree/control` some platforms make use of device tree
+files which come from a git subtree that mirrors the Linux Kernel sources
+itself. For our purposes, we only track releases and not release candidates for
+merging in our tree. These merges follow the normal merge window rules.
+
+In the case of specific changes, such as bug fixes or new platform support,
+these can be "cherry-picked" and are subject to the normal merge rules. For
+example, a bug fix can come in later in the window but a full re-sync only
+happens within the merge window itself.
+
.. _custodians:
Custodians
diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst
index 383f448..541ab0a 100644
--- a/doc/develop/release_cycle.rst
+++ b/doc/develop/release_cycle.rst
@@ -51,13 +51,14 @@
Current Status
--------------
-* U-Boot v2024.04 was released on Tue 02 April 2024.
+* U-Boot v2024.07 was released on Mon 01 July 2024.
-* The Merge Window for the next release (v2024.07) is **closed**.
+* The Merge Window for the next release (v2024.10) is **open** until the -rc1
+ release on Mon 22 July 2024.
-* The next branch is now **open**.
+* The next branch is now **closed**.
-* Release "v2024.07" is scheduled for 01 July 2024.
+* Release "v2024.10" is scheduled for 07 October 2024.
Future Releases
---------------
@@ -65,29 +66,31 @@
.. The following commented out dates are for when release candidates are
planned to be tagged.
-For the next scheduled release, release candidates were made on::
+.. For the next scheduled release, release candidates were made on::
-* U-Boot v2024.07-rc1 was released on Mon 22 April 2024.
+.. * U-Boot v2024.10-rc1 was released on Mon 22 July 2024.
-* U-Boot v2024.07-rc2 was released on Mon 06 May 2024.
+.. * U-Boot v2024.10-rc2 was released on Mon 05 August 2024.
-* U-Boot v2024.07-rc3 was released on Mon 20 May 2024.
+.. * U-Boot v2024.10-rc3 was released on Mon 19 August 2024.
-.. * U-Boot v2024.07-rc4 was released on Mon 03 June 2024.
+.. * U-Boot v2024.10-rc4 was released on Mon 02 September 2024.
-.. * U-Boot v2024.07-rc5 was released on Mon 17 June 2024.
+.. * U-Boot v2024.10-rc5 was released on Mon 16 September 2024.
+
+.. * U-Boot v2024.10-rc6 was released on Mon 30 September 2024.
Please note that the following dates are planned only and may be deviated from
as needed.
-* "v2024.07": end of MW = Mon, Apr 22, 2024; release = Mon, Jul 01, 2024
-
* "v2024.10": end of MW = Mon, Jul 22, 2024; release = Mon, Oct 07, 2024
* "v2025.01": end of MW = Mon, Oct 21, 2024; release = Mon, Jan 06, 2025
* "v2025.04": end of MW = Mon, Jan 27, 2025; release = Mon, Apr 07, 2025
+* "v2025.07": end of MW = Mon, Apr 21, 2025; release = Mon, Jul 07, 2025
+
Previous Releases
-----------------
@@ -95,6 +98,8 @@
<https://source.denx.de/u-boot/gitdm>`_, which was originally created by
Jonathan Corbet.
+* :doc:`statistics/u-boot-stats-v2024.07` which was released on 01 July 2024.
+
* :doc:`statistics/u-boot-stats-v2024.04` which was released on 02 April 2024.
* :doc:`statistics/u-boot-stats-v2024.01` which was released on 08 January 2024.
diff --git a/doc/develop/statistics/u-boot-stats-v2024.07.rst b/doc/develop/statistics/u-boot-stats-v2024.07.rst
new file mode 100644
index 0000000..b437e92
--- /dev/null
+++ b/doc/develop/statistics/u-boot-stats-v2024.07.rst
@@ -0,0 +1,890 @@
+:orphan:
+
+Release Statistics for U-Boot v2024.07
+======================================
+
+* Processed 1624 changesets from 191 developers
+
+* 28 employers found
+
+* A total of 2308875 lines added, 242831 removed (delta 2066044)
+
+.. table:: Developers with the most changesets
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ Tom Rini 324 (20.0%)
+ Jonas Karlman 155 (9.5%)
+ Caleb Connolly 98 (6.0%)
+ Heinrich Schuchardt 84 (5.2%)
+ Quentin Schulz 59 (3.6%)
+ Marek Vasut 52 (3.2%)
+ Simon Glass 44 (2.7%)
+ Patrice Chotard 32 (2.0%)
+ Sumit Garg 31 (1.9%)
+ Svyatoslav Ryhel 31 (1.9%)
+ Michal Simek 26 (1.6%)
+ Ilias Apalodimas 23 (1.4%)
+ Neil Armstrong 23 (1.4%)
+ Jonathan Humphreys 22 (1.4%)
+ Andrew Davis 18 (1.1%)
+ Marek Behún 18 (1.1%)
+ Jagan Teki 17 (1.0%)
+ MD Danish Anwar 15 (0.9%)
+ Kongyang Liu 15 (0.9%)
+ Bryan Brattlof 14 (0.9%)
+ Janne Grunau 14 (0.9%)
+ Christophe Leroy 13 (0.8%)
+ Tim Harvey 13 (0.8%)
+ Apurva Nandan 12 (0.7%)
+ Wadim Egorov 11 (0.7%)
+ Andre Przywara 11 (0.7%)
+ Peng Fan 11 (0.7%)
+ Adam Ford 10 (0.6%)
+ Sam Protsenko 10 (0.6%)
+ Roger Quadros 10 (0.6%)
+ Igor Opaniuk 9 (0.6%)
+ Robert Marko 9 (0.6%)
+ Jonas Schwöbel 9 (0.6%)
+ Yang Xiwen 9 (0.6%)
+ Eugene Uriev 9 (0.6%)
+ Chris Morgan 8 (0.5%)
+ Judith Mendez 8 (0.5%)
+ Raymond Mao 8 (0.5%)
+ Alexander Dahl 7 (0.4%)
+ Fabio Estevam 7 (0.4%)
+ Jim Liu 7 (0.4%)
+ Venkatesh Yadav Abbarapu 7 (0.4%)
+ Mattijs Korpershoek 6 (0.4%)
+ Daniel Schultz 6 (0.4%)
+ Weizhao Ouyang 6 (0.4%)
+ Ye Li 6 (0.4%)
+ Conor Dooley 5 (0.3%)
+ Nishanth Menon 5 (0.3%)
+ Leo Yu-Chi Liang 5 (0.3%)
+ Bhargav Raviprakash 5 (0.3%)
+ Masahisa Kojima 5 (0.3%)
+ mwleeds@mailtundra.com 5 (0.3%)
+ Michał Barnaś 5 (0.3%)
+ Leonard Anderweit 5 (0.3%)
+ Chen-Yu Tsai 5 (0.3%)
+ Javier Martinez Canillas 4 (0.2%)
+ Francesco Dolcini 4 (0.2%)
+ Felipe Balbi 4 (0.2%)
+ Aniket Limaye 4 (0.2%)
+ Christopher Obbard 4 (0.2%)
+ Mathieu Othacehe 4 (0.2%)
+ Joao Paulo Goncalves 4 (0.2%)
+ Sughosh Ganu 4 (0.2%)
+ Volodymyr Babchuk 4 (0.2%)
+ Lukasz Majewski 4 (0.2%)
+ Jacky Chou 4 (0.2%)
+ Dan Carpenter 4 (0.2%)
+ Mihai Sain 4 (0.2%)
+ Arseniy Krasnov 3 (0.2%)
+ Fiona Klute 3 (0.2%)
+ Hanyuan Zhao 3 (0.2%)
+ Greg Malysa 3 (0.2%)
+ Nathan Barrett-Morrison 3 (0.2%)
+ Peter Robinson 3 (0.2%)
+ Lukas Funke 3 (0.2%)
+ Yannic Moog 3 (0.2%)
+ Udit Kumar 3 (0.2%)
+ Michael Walle 3 (0.2%)
+ Devarsh Thakkar 3 (0.2%)
+ Christophe Kerello 3 (0.2%)
+ Viacheslav Bocharov 3 (0.2%)
+ Emanuele Ghidoli 3 (0.2%)
+ Hari Nagalla 3 (0.2%)
+ Love Kumar 3 (0.2%)
+ Thomas Weißschuh 3 (0.2%)
+ Weijie Gao 3 (0.2%)
+ Dragan Simic 2 (0.1%)
+ Michael Trimarchi 2 (0.1%)
+ Patrick Delaunay 2 (0.1%)
+ Tony Dinh 2 (0.1%)
+ Sam Povilus 2 (0.1%)
+ H Bell 2 (0.1%)
+ Thinh Nguyen 2 (0.1%)
+ Benjamin Hahn 2 (0.1%)
+ Neha Malcom Francis 2 (0.1%)
+ Ian Roberts 2 (0.1%)
+ Sean Anderson 2 (0.1%)
+ Kamlesh Gurudasani 2 (0.1%)
+ Stefan Eichenberger 2 (0.1%)
+ Parth Pancholi 2 (0.1%)
+ Maksim Kiselev 2 (0.1%)
+ Christophe Roullier 2 (0.1%)
+ Hugo Dubois 2 (0.1%)
+ CASAUBON Jean Michel 2 (0.1%)
+ Ahelenia Ziemiańska 2 (0.1%)
+ Yasuharu Shibata 2 (0.1%)
+ Wan Yee Lau 2 (0.1%)
+ Vincent Stehlé 2 (0.1%)
+ Marcel Ziswiler 2 (0.1%)
+ Maxim Moskalets 2 (0.1%)
+ Sébastien Szymanski 2 (0.1%)
+ Tejas Bhumkar 2 (0.1%)
+ Bhupesh Sharma 2 (0.1%)
+ Colin McAllister 2 (0.1%)
+ Andy Yan 2 (0.1%)
+ Dasnavis Sabiya 2 (0.1%)
+ Stefan Bosch 2 (0.1%)
+ Frank Wunderlich 1 (0.1%)
+ Jiaxun Yang 1 (0.1%)
+ Ravi Minnikanti 1 (0.1%)
+ John Watts 1 (0.1%)
+ Heiko Schocher 1 (0.1%)
+ Thomas Perl 1 (0.1%)
+ Kristian Amlie 1 (0.1%)
+ Heiko Stuebner 1 (0.1%)
+ Anand Moon 1 (0.1%)
+ Alexander Sverdlin 1 (0.1%)
+ Aswath Govindraju 1 (0.1%)
+ Sam Day 1 (0.1%)
+ Boon Khai Ng 1 (0.1%)
+ William Zhang 1 (0.1%)
+ Jaehoon Chung 1 (0.1%)
+ Sam Edwards 1 (0.1%)
+ Linus Walleij 1 (0.1%)
+ Kishan Dudhatra 1 (0.1%)
+ Yu Chien Peter Lin 1 (0.1%)
+ Nitin Yadav 1 (0.1%)
+ Andrea Calabrese 1 (0.1%)
+ Lukasz Czechowski 1 (0.1%)
+ Finley Xiao 1 (0.1%)
+ Jason Zhu 1 (0.1%)
+ Maximilian Brune 1 (0.1%)
+ cmachida 1 (0.1%)
+ Hector Martin 1 (0.1%)
+ Anton Bambura 1 (0.1%)
+ Khem Raj 1 (0.1%)
+ Jianan Huang 1 (0.1%)
+ Charles Hardin 1 (0.1%)
+ Gireesh Hiremath 1 (0.1%)
+ Alexey Romanov 1 (0.1%)
+ Eugeniu Rosca 1 (0.1%)
+ Bruce Suen 1 (0.1%)
+ Kunihiko Hayashi 1 (0.1%)
+ Hugo Cornelis 1 (0.1%)
+ Vitor Soares 1 (0.1%)
+ Martyn Welch 1 (0.1%)
+ Manorit Chawdhry 1 (0.1%)
+ Jixiong Hu 1 (0.1%)
+ Pierre-Clément Tosi 1 (0.1%)
+ Hiago De Franco 1 (0.1%)
+ Petr Zejdl 1 (0.1%)
+ Łukasz Stelmach 1 (0.1%)
+ Ben Dooks 1 (0.1%)
+ Javier Viguera 1 (0.1%)
+ Josua Mayer 1 (0.1%)
+ James Hilliard 1 (0.1%)
+ Marjolaine Amate 1 (0.1%)
+ Vishal Sagar 1 (0.1%)
+ Manikanta Guntupalli 1 (0.1%)
+ Shubhangi Shrikrushna Mahalle 1 (0.1%)
+ Piotr Wojtaszczyk 1 (0.1%)
+ Kelly Hung 1 (0.1%)
+ Leon M. Busch-George 1 (0.1%)
+ Lukasz Wiecaszek 1 (0.1%)
+ Jit Loon Lim 1 (0.1%)
+ William Wu 1 (0.1%)
+ Ben Wolsieffer 1 (0.1%)
+ Elon Zhang 1 (0.1%)
+ Vignesh Raghavendra 1 (0.1%)
+ Maks Mishin 1 (0.1%)
+ Bob Wolff 1 (0.1%)
+ Romain Naour 1 (0.1%)
+ Dmitry Baryshkov 1 (0.1%)
+ Vishal Mahaveer 1 (0.1%)
+ Siddharth Vadapalli 1 (0.1%)
+ Ivan Orlov 1 (0.1%)
+ Nam Cao 1 (0.1%)
+ Massimiliano Minella 1 (0.1%)
+ BELOUARGA Mohamed 1 (0.1%)
+ Alexander Gendin 1 (0.1%)
+ Ivan Mikhaylov 1 (0.1%)
+ ==================================== =====
+
+
+.. table:: Developers with the most changed lines
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ Tom Rini 2187616 (86.6%)
+ Jonas Karlman 69460 (2.8%)
+ Marek Vasut 53285 (2.1%)
+ Caleb Connolly 47393 (1.9%)
+ Apurva Nandan 26241 (1.0%)
+ Neil Armstrong 23816 (0.9%)
+ Tim Harvey 10971 (0.4%)
+ Christophe Leroy 10210 (0.4%)
+ Wadim Egorov 8248 (0.3%)
+ Bryan Brattlof 7039 (0.3%)
+ Tony Dinh 5540 (0.2%)
+ Marcel Ziswiler 5068 (0.2%)
+ Nathan Barrett-Morrison 4872 (0.2%)
+ Adam Ford 4867 (0.2%)
+ Sumit Garg 4743 (0.2%)
+ Andrew Davis 4066 (0.2%)
+ Quentin Schulz 3449 (0.1%)
+ Peng Fan 3071 (0.1%)
+ Sam Protsenko 3021 (0.1%)
+ Jit Loon Lim 2717 (0.1%)
+ MD Danish Anwar 2686 (0.1%)
+ Anand Moon 2526 (0.1%)
+ Svyatoslav Ryhel 2445 (0.1%)
+ Andy Yan 1978 (0.1%)
+ Peter Robinson 1907 (0.1%)
+ Boon Khai Ng 1709 (0.1%)
+ Arseniy Krasnov 1669 (0.1%)
+ Heinrich Schuchardt 1350 (0.1%)
+ Jagan Teki 1347 (0.1%)
+ Fabio Estevam 1209 (0.0%)
+ Ilias Apalodimas 1189 (0.0%)
+ Simon Glass 1137 (0.0%)
+ Roger Quadros 955 (0.0%)
+ Marek Behún 939 (0.0%)
+ Elon Zhang 889 (0.0%)
+ Kongyang Liu 846 (0.0%)
+ Mihai Sain 789 (0.0%)
+ Bhupesh Sharma 662 (0.0%)
+ Jonas Schwöbel 620 (0.0%)
+ Javier Martinez Canillas 597 (0.0%)
+ Michael Walle 505 (0.0%)
+ Eugene Uriev 501 (0.0%)
+ Christophe Kerello 479 (0.0%)
+ Chris Morgan 452 (0.0%)
+ Michal Simek 449 (0.0%)
+ Bhargav Raviprakash 388 (0.0%)
+ Janne Grunau 386 (0.0%)
+ Robert Marko 332 (0.0%)
+ Vignesh Raghavendra 332 (0.0%)
+ H Bell 291 (0.0%)
+ Yang Xiwen 278 (0.0%)
+ Bruce Suen 269 (0.0%)
+ Daniel Schultz 265 (0.0%)
+ Love Kumar 258 (0.0%)
+ Igor Opaniuk 219 (0.0%)
+ Raymond Mao 208 (0.0%)
+ Wan Yee Lau 206 (0.0%)
+ Sughosh Ganu 201 (0.0%)
+ Greg Malysa 200 (0.0%)
+ Patrice Chotard 199 (0.0%)
+ Masahisa Kojima 193 (0.0%)
+ Dasnavis Sabiya 189 (0.0%)
+ Neha Malcom Francis 183 (0.0%)
+ Jonathan Humphreys 173 (0.0%)
+ Anton Bambura 167 (0.0%)
+ Kelly Hung 164 (0.0%)
+ Andre Przywara 163 (0.0%)
+ Kamlesh Gurudasani 163 (0.0%)
+ Volodymyr Babchuk 147 (0.0%)
+ Parth Pancholi 146 (0.0%)
+ Piotr Wojtaszczyk 144 (0.0%)
+ Judith Mendez 131 (0.0%)
+ Joao Paulo Goncalves 131 (0.0%)
+ Leonard Anderweit 117 (0.0%)
+ BELOUARGA Mohamed 114 (0.0%)
+ Finley Xiao 109 (0.0%)
+ Jianan Huang 99 (0.0%)
+ Venkatesh Yadav Abbarapu 95 (0.0%)
+ Chen-Yu Tsai 92 (0.0%)
+ Mathieu Othacehe 92 (0.0%)
+ Michał Barnaś 86 (0.0%)
+ Lukasz Majewski 74 (0.0%)
+ Alexander Dahl 67 (0.0%)
+ Nishanth Menon 66 (0.0%)
+ Conor Dooley 64 (0.0%)
+ Francesco Dolcini 64 (0.0%)
+ Maksim Kiselev 64 (0.0%)
+ Linus Walleij 64 (0.0%)
+ Weizhao Ouyang 63 (0.0%)
+ Yannic Moog 61 (0.0%)
+ Weijie Gao 60 (0.0%)
+ Ben Dooks 60 (0.0%)
+ Leo Yu-Chi Liang 59 (0.0%)
+ Fiona Klute 56 (0.0%)
+ Alexey Romanov 56 (0.0%)
+ Jim Liu 55 (0.0%)
+ Devarsh Thakkar 53 (0.0%)
+ Colin McAllister 53 (0.0%)
+ Maxim Moskalets 51 (0.0%)
+ Josua Mayer 50 (0.0%)
+ Ivan Mikhaylov 50 (0.0%)
+ Ian Roberts 47 (0.0%)
+ Christophe Roullier 44 (0.0%)
+ Vincent Stehlé 44 (0.0%)
+ Nam Cao 43 (0.0%)
+ Ben Wolsieffer 42 (0.0%)
+ Felipe Balbi 41 (0.0%)
+ Vishal Sagar 40 (0.0%)
+ Hanyuan Zhao 38 (0.0%)
+ Hugo Dubois 37 (0.0%)
+ Christopher Obbard 34 (0.0%)
+ Aniket Limaye 33 (0.0%)
+ Romain Naour 33 (0.0%)
+ Heiko Stuebner 31 (0.0%)
+ Emanuele Ghidoli 30 (0.0%)
+ Stefan Bosch 30 (0.0%)
+ mwleeds@mailtundra.com 28 (0.0%)
+ Michael Trimarchi 23 (0.0%)
+ Thomas Weißschuh 22 (0.0%)
+ Thinh Nguyen 21 (0.0%)
+ Nitin Yadav 19 (0.0%)
+ Jixiong Hu 18 (0.0%)
+ Marjolaine Amate 18 (0.0%)
+ Dan Carpenter 17 (0.0%)
+ Stefan Eichenberger 17 (0.0%)
+ Sam Povilus 15 (0.0%)
+ Sébastien Szymanski 15 (0.0%)
+ Massimiliano Minella 15 (0.0%)
+ Mattijs Korpershoek 14 (0.0%)
+ Sean Anderson 14 (0.0%)
+ Lukas Funke 13 (0.0%)
+ Yasuharu Shibata 13 (0.0%)
+ Sam Edwards 13 (0.0%)
+ Kunihiko Hayashi 13 (0.0%)
+ Jacky Chou 12 (0.0%)
+ Vitor Soares 12 (0.0%)
+ Ye Li 11 (0.0%)
+ Udit Kumar 11 (0.0%)
+ Hiago De Franco 11 (0.0%)
+ Hari Nagalla 10 (0.0%)
+ Maximilian Brune 10 (0.0%)
+ Leon M. Busch-George 10 (0.0%)
+ Viacheslav Bocharov 9 (0.0%)
+ Benjamin Hahn 9 (0.0%)
+ cmachida 9 (0.0%)
+ James Hilliard 9 (0.0%)
+ Lukasz Wiecaszek 9 (0.0%)
+ Charles Hardin 8 (0.0%)
+ Petr Zejdl 8 (0.0%)
+ Vishal Mahaveer 8 (0.0%)
+ Sam Day 7 (0.0%)
+ Manorit Chawdhry 7 (0.0%)
+ Łukasz Stelmach 7 (0.0%)
+ Andrea Calabrese 6 (0.0%)
+ Siddharth Vadapalli 6 (0.0%)
+ CASAUBON Jean Michel 5 (0.0%)
+ Ahelenia Ziemiańska 5 (0.0%)
+ Ravi Minnikanti 5 (0.0%)
+ Hugo Cornelis 5 (0.0%)
+ Bob Wolff 5 (0.0%)
+ Alexander Gendin 5 (0.0%)
+ Dragan Simic 4 (0.0%)
+ Aswath Govindraju 4 (0.0%)
+ Kishan Dudhatra 4 (0.0%)
+ Khem Raj 4 (0.0%)
+ Tejas Bhumkar 3 (0.0%)
+ Heiko Schocher 3 (0.0%)
+ Lukasz Czechowski 3 (0.0%)
+ Jason Zhu 3 (0.0%)
+ Maks Mishin 3 (0.0%)
+ Patrick Delaunay 2 (0.0%)
+ Jiaxun Yang 2 (0.0%)
+ William Zhang 2 (0.0%)
+ Eugeniu Rosca 2 (0.0%)
+ Pierre-Clément Tosi 2 (0.0%)
+ Javier Viguera 2 (0.0%)
+ Manikanta Guntupalli 2 (0.0%)
+ Dmitry Baryshkov 2 (0.0%)
+ Frank Wunderlich 1 (0.0%)
+ John Watts 1 (0.0%)
+ Thomas Perl 1 (0.0%)
+ Kristian Amlie 1 (0.0%)
+ Alexander Sverdlin 1 (0.0%)
+ Jaehoon Chung 1 (0.0%)
+ Yu Chien Peter Lin 1 (0.0%)
+ Hector Martin 1 (0.0%)
+ Gireesh Hiremath 1 (0.0%)
+ Martyn Welch 1 (0.0%)
+ Shubhangi Shrikrushna Mahalle 1 (0.0%)
+ William Wu 1 (0.0%)
+ Ivan Orlov 1 (0.0%)
+ ==================================== =====
+
+
+.. table:: Developers with the most lines removed
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ Jonas Karlman 59892 (24.7%)
+ Marek Vasut 51731 (21.3%)
+ Neil Armstrong 19240 (7.9%)
+ Tim Harvey 10397 (4.3%)
+ Tony Dinh 5465 (2.3%)
+ Marcel Ziswiler 5061 (2.1%)
+ Adam Ford 4818 (2.0%)
+ Andrew Davis 3493 (1.4%)
+ Peng Fan 2778 (1.1%)
+ Anand Moon 2523 (1.0%)
+ Sam Protsenko 2273 (0.9%)
+ Peter Robinson 1907 (0.8%)
+ Fabio Estevam 1185 (0.5%)
+ Sumit Garg 845 (0.3%)
+ Javier Martinez Canillas 582 (0.2%)
+ Michael Walle 494 (0.2%)
+ Chen-Yu Tsai 80 (0.0%)
+ Igor Opaniuk 72 (0.0%)
+ Linus Walleij 61 (0.0%)
+ Francesco Dolcini 36 (0.0%)
+ Sam Edwards 12 (0.0%)
+ Ben Wolsieffer 11 (0.0%)
+ Hiago De Franco 11 (0.0%)
+ Kunihiko Hayashi 10 (0.0%)
+ Colin McAllister 7 (0.0%)
+ Heiko Schocher 3 (0.0%)
+ Dan Carpenter 2 (0.0%)
+ Dragan Simic 2 (0.0%)
+ Jiaxun Yang 1 (0.0%)
+ William Zhang 1 (0.0%)
+ ==================================== =====
+
+
+.. table:: Developers with the most signoffs (total 231)
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ Caleb Connolly 41 (17.7%)
+ Mattijs Korpershoek 19 (8.2%)
+ Michal Simek 15 (6.5%)
+ Dario Binacchi 11 (4.8%)
+ Chris Morgan 10 (4.3%)
+ Ilias Apalodimas 10 (4.3%)
+ Svyatoslav Ryhel 10 (4.3%)
+ Hari Nagalla 8 (3.5%)
+ Minkyu Kang 7 (3.0%)
+ Alexander Sverdlin 6 (2.6%)
+ Ian Roberts 6 (2.6%)
+ Greg Malysa 5 (2.2%)
+ Nathan Barrett-Morrison 5 (2.2%)
+ Manorit Chawdhry 4 (1.7%)
+ Dasnavis Sabiya 4 (1.7%)
+ Christophe Leroy 4 (1.7%)
+ Apurva Nandan 4 (1.7%)
+ Neil Armstrong 3 (1.3%)
+ Francesco Dolcini 3 (1.3%)
+ Vasileios Bimpikas 3 (1.3%)
+ Utsav Agarwal 3 (1.3%)
+ Arturs Artamonovs 3 (1.3%)
+ Neha Malcom Francis 3 (1.3%)
+ Janne Grunau 3 (1.3%)
+ Heinrich Schuchardt 3 (1.3%)
+ Jonas Karlman 2 (0.9%)
+ Marek Vasut 2 (0.9%)
+ Sumit Garg 2 (0.9%)
+ Dhruva Gole 2 (0.9%)
+ Kever Yang 2 (0.9%)
+ Ravi Gunasekaran 2 (0.9%)
+ Parvathi Bhogaraju 2 (0.9%)
+ Jayesh Choudhary 2 (0.9%)
+ Bo-Cun Chen 2 (0.9%)
+ Daniel Schultz 2 (0.9%)
+ Jonas Schwöbel 2 (0.9%)
+ Bryan Brattlof 2 (0.9%)
+ Peng Fan 1 (0.4%)
+ Fabio Estevam 1 (0.4%)
+ Stefan Roese 1 (0.4%)
+ Greg Kroah-Hartman 1 (0.4%)
+ Angelo Dureghello 1 (0.4%)
+ Anatolij Gustschin 1 (0.4%)
+ Vaishnav Achath 1 (0.4%)
+ Ashok Reddy Soma 1 (0.4%)
+ Dong Huang 1 (0.4%)
+ Shubhangi Shrikrushna Mahalle 1 (0.4%)
+ Felipe Balbi 1 (0.4%)
+ Judith Mendez 1 (0.4%)
+ Patrice Chotard 1 (0.4%)
+ Quentin Schulz 1 (0.4%)
+ ==================================== =====
+
+
+.. table:: Developers with the most reviews (total 1025)
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ Kever Yang 223 (21.8%)
+ Neil Armstrong 71 (6.9%)
+ Sumit Garg 70 (6.8%)
+ Dragan Simic 45 (4.4%)
+ Ilias Apalodimas 42 (4.1%)
+ Heinrich Schuchardt 35 (3.4%)
+ Patrick Delaunay 33 (3.2%)
+ Quentin Schulz 32 (3.1%)
+ Mattijs Korpershoek 31 (3.0%)
+ Leo Yu-Chi Liang 31 (3.0%)
+ Marek Vasut 28 (2.7%)
+ Jaehoon Chung 28 (2.7%)
+ Patrice Chotard 22 (2.1%)
+ Caleb Connolly 21 (2.0%)
+ Tom Rini 21 (2.0%)
+ Stefan Roese 20 (2.0%)
+ Neha Malcom Francis 17 (1.7%)
+ Simon Glass 16 (1.6%)
+ Peter Robinson 13 (1.3%)
+ Igor Opaniuk 13 (1.3%)
+ Thierry Reding 12 (1.2%)
+ Neal Gompa 11 (1.1%)
+ Heiko Schocher 9 (0.9%)
+ Michael Trimarchi 9 (0.9%)
+ Roger Quadros 9 (0.9%)
+ Tony Dinh 8 (0.8%)
+ Christopher Obbard 8 (0.8%)
+ Jonas Karlman 6 (0.6%)
+ Dhruva Gole 6 (0.6%)
+ E Shattow 6 (0.6%)
+ Christophe ROULLIER 6 (0.6%)
+ Richard Henderson 6 (0.6%)
+ Nishanth Menon 6 (0.6%)
+ Ravi Gunasekaran 5 (0.5%)
+ Teresa Remmet 5 (0.5%)
+ Mark Kettenis 5 (0.5%)
+ Paul Barker 5 (0.5%)
+ Udit Kumar 5 (0.5%)
+ Sean Anderson 5 (0.5%)
+ Fabio Estevam 4 (0.4%)
+ Sam Protsenko 4 (0.4%)
+ Enric Balletbo i Serra 4 (0.4%)
+ Laurent Pinchart 4 (0.4%)
+ Bryan Brattlof 3 (0.3%)
+ Andrew Davis 3 (0.3%)
+ Sam Edwards 3 (0.3%)
+ Dan Carpenter 3 (0.3%)
+ William Zhang 3 (0.3%)
+ Chris Packham 3 (0.3%)
+ Nikhil M Jain 3 (0.3%)
+ Tianling Shen 3 (0.3%)
+ Anatolij Gustschin 2 (0.2%)
+ CASAUBON Jean Michel 2 (0.2%)
+ Ian Ray 2 (0.2%)
+ Oleksandr Suvorov 2 (0.2%)
+ Bin Meng 2 (0.2%)
+ Tien Fong Chee 2 (0.2%)
+ Minkyu Kang 1 (0.1%)
+ Tim Harvey 1 (0.1%)
+ Adam Ford 1 (0.1%)
+ Linus Walleij 1 (0.1%)
+ Eddie James 1 (0.1%)
+ Guillaume La Roque 1 (0.1%)
+ Julien Masson 1 (0.1%)
+ Miquel Raynal 1 (0.1%)
+ Tim Lunn 1 (0.1%)
+ Cédric Le Goater 1 (0.1%)
+ Biju Das 1 (0.1%)
+ Holger Brunck 1 (0.1%)
+ Otavio Salvador 1 (0.1%)
+ Chia-Wei Wang 1 (0.1%)
+ Keerthy 1 (0.1%)
+ Philipp Tomsich 1 (0.1%)
+ Gao Xiang 1 (0.1%)
+ Frieder Schrempf 1 (0.1%)
+ Dmitrii Merkurev 1 (0.1%)
+ Marc Zyngier 1 (0.1%)
+ Ramon Fried 1 (0.1%)
+ Jai Luthra 1 (0.1%)
+ Alexander Dahl 1 (0.1%)
+ Heiko Stuebner 1 (0.1%)
+ Hugo Dubois 1 (0.1%)
+ Weizhao Ouyang 1 (0.1%)
+ Andre Przywara 1 (0.1%)
+ Mathieu Othacehe 1 (0.1%)
+ Wadim Egorov 1 (0.1%)
+ ==================================== =====
+
+
+.. table:: Developers with the most test credits (total 166)
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ Sumit Garg 19 (11.4%)
+ Marcel Ziswiler 15 (9.0%)
+ Svyatoslav Ryhel 10 (6.0%)
+ Mattijs Korpershoek 9 (5.4%)
+ Ion Agorria 9 (5.4%)
+ Tim Harvey 7 (4.2%)
+ Adam Ford 7 (4.2%)
+ Andreas Westman Dorcsak 7 (4.2%)
+ Sam Edwards 6 (3.6%)
+ Agneli 6 (3.6%)
+ Robert Eckelmann 6 (3.6%)
+ Simon Glass 5 (3.0%)
+ Teresa Remmet 5 (3.0%)
+ Fabio Estevam 5 (3.0%)
+ Ilias Apalodimas 4 (2.4%)
+ Jonathan Humphreys 4 (2.4%)
+ Neil Armstrong 3 (1.8%)
+ Paul Barker 3 (1.8%)
+ Heiko Stuebner 3 (1.8%)
+ Christian Gmeiner 3 (1.8%)
+ Heinrich Schuchardt 2 (1.2%)
+ Caleb Connolly 2 (1.2%)
+ Tony Dinh 2 (1.2%)
+ Hiago De Franco 2 (1.2%)
+ Robert Nelson 2 (1.2%)
+ Leo Yu-Chi Liang 1 (0.6%)
+ Jaehoon Chung 1 (0.6%)
+ Patrice Chotard 1 (0.6%)
+ Dhruva Gole 1 (0.6%)
+ E Shattow 1 (0.6%)
+ Ravi Gunasekaran 1 (0.6%)
+ Bryan Brattlof 1 (0.6%)
+ Andrew Davis 1 (0.6%)
+ Tim Lunn 1 (0.6%)
+ Otavio Salvador 1 (0.6%)
+ Wadim Egorov 1 (0.6%)
+ Michal Simek 1 (0.6%)
+ Alexander Sverdlin 1 (0.6%)
+ Jonas Schwöbel 1 (0.6%)
+ Judith Mendez 1 (0.6%)
+ Michael Walle 1 (0.6%)
+ Patrick Bruenn 1 (0.6%)
+ Jethro Bull 1 (0.6%)
+ Kamlesh Gurudasani 1 (0.6%)
+ Robert Marko 1 (0.6%)
+ ==================================== =====
+
+
+.. table:: Developers who gave the most tested-by credits (total 166)
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ Svyatoslav Ryhel 36 (21.7%)
+ Caleb Connolly 23 (13.9%)
+ Sumit Garg 15 (9.0%)
+ Apurva Nandan 12 (7.2%)
+ Marek Vasut 10 (6.0%)
+ Ilias Apalodimas 6 (3.6%)
+ Quentin Schulz 6 (3.6%)
+ Tom Rini 6 (3.6%)
+ Neil Armstrong 5 (3.0%)
+ Andrew Davis 5 (3.0%)
+ Leonard Anderweit 5 (3.0%)
+ Jonas Schwöbel 4 (2.4%)
+ Fabio Estevam 3 (1.8%)
+ Heinrich Schuchardt 3 (1.8%)
+ Bryan Brattlof 3 (1.8%)
+ Alexander Sverdlin 2 (1.2%)
+ Dasnavis Sabiya 2 (1.2%)
+ Pierre-Clément Tosi 2 (1.2%)
+ Yasuharu Shibata 2 (1.2%)
+ Josua Mayer 2 (1.2%)
+ Masahisa Kojima 2 (1.2%)
+ Tim Harvey 1 (0.6%)
+ Simon Glass 1 (0.6%)
+ Tony Dinh 1 (0.6%)
+ Judith Mendez 1 (0.6%)
+ Igor Opaniuk 1 (0.6%)
+ Roger Quadros 1 (0.6%)
+ Nishanth Menon 1 (0.6%)
+ Anand Moon 1 (0.6%)
+ Sébastien Szymanski 1 (0.6%)
+ Maksim Kiselev 1 (0.6%)
+ Ben Dooks 1 (0.6%)
+ Yang Xiwen 1 (0.6%)
+ ==================================== =====
+
+
+.. table:: Developers with the most report credits (total 27)
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ E Shattow 4 (14.8%)
+ Sumit Garg 2 (7.4%)
+ Jonas Karlman 2 (7.4%)
+ Laurent Pinchart 2 (7.4%)
+ Suman Anna 2 (7.4%)
+ Marek Vasut 1 (3.7%)
+ Andrew Davis 1 (3.7%)
+ Heinrich Schuchardt 1 (3.7%)
+ Tim Harvey 1 (3.7%)
+ Simon Glass 1 (3.7%)
+ Jonathan Humphreys 1 (3.7%)
+ Patrice Chotard 1 (3.7%)
+ Dhruva Gole 1 (3.7%)
+ Dan Carpenter 1 (3.7%)
+ Christophe Leroy 1 (3.7%)
+ Eugeniu Rosca 1 (3.7%)
+ Janusz Dziedzic 1 (3.7%)
+ David Virag 1 (3.7%)
+ Jan Kiszka 1 (3.7%)
+ Aniket Limaye 1 (3.7%)
+ ==================================== =====
+
+
+.. table:: Developers who gave the most report credits (total 27)
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ Heinrich Schuchardt 6 (22.2%)
+ Neha Malcom Francis 3 (11.1%)
+ Marek Vasut 2 (7.4%)
+ Caleb Connolly 2 (7.4%)
+ Tom Rini 2 (7.4%)
+ Fabio Estevam 2 (7.4%)
+ Bryan Brattlof 2 (7.4%)
+ Andrew Davis 1 (3.7%)
+ Ilias Apalodimas 1 (3.7%)
+ Quentin Schulz 1 (3.7%)
+ Yasuharu Shibata 1 (3.7%)
+ Nishanth Menon 1 (3.7%)
+ Sam Protsenko 1 (3.7%)
+ Felipe Balbi 1 (3.7%)
+ Alexander Gendin 1 (3.7%)
+ ==================================== =====
+
+
+.. table:: Top changeset contributors by employer
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ (Unknown) 645 (39.7%)
+ Konsulko Group 324 (20.0%)
+ Linaro 201 (12.4%)
+ Texas Instruments 119 (7.3%)
+ Google LLC 50 (3.1%)
+ AMD 43 (2.6%)
+ ST Microelectronics 39 (2.4%)
+ DENX Software Engineering 34 (2.1%)
+ Phytec 27 (1.7%)
+ Renesas Electronics 25 (1.5%)
+ Toradex 19 (1.2%)
+ NXP 17 (1.0%)
+ Edgeble AI Technologies Pvt. Ltd. 14 (0.9%)
+ ARM 13 (0.8%)
+ Intel 9 (0.6%)
+ Amarula Solutions 7 (0.4%)
+ BayLibre SAS 6 (0.4%)
+ Socionext Inc. 6 (0.4%)
+ Collabora Ltd. 5 (0.3%)
+ Red Hat 4 (0.2%)
+ linutronix 4 (0.2%)
+ Rockchip 4 (0.2%)
+ Weidmüller Interface GmbH & Co. KG 3 (0.2%)
+ Samsung 2 (0.1%)
+ Broadcom 1 (0.1%)
+ Digi International 1 (0.1%)
+ Marvell 1 (0.1%)
+ Siemens 1 (0.1%)
+ ==================================== =====
+
+
+.. table:: Top lines changed by employer
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ Konsulko Group 2187616 (86.6%)
+ (Unknown) 130949 (5.2%)
+ Linaro 80577 (3.2%)
+ Renesas Electronics 52143 (2.1%)
+ Texas Instruments 41420 (1.6%)
+ Phytec 8700 (0.3%)
+ Toradex 5479 (0.2%)
+ Intel 4682 (0.2%)
+ Edgeble AI Technologies Pvt. Ltd. 3856 (0.2%)
+ NXP 3082 (0.1%)
+ DENX Software Engineering 1283 (0.1%)
+ Google LLC 1225 (0.0%)
+ Rockchip 1002 (0.0%)
+ AMD 863 (0.0%)
+ ST Microelectronics 724 (0.0%)
+ Red Hat 597 (0.0%)
+ ARM 207 (0.0%)
+ Socionext Inc. 206 (0.0%)
+ linutronix 65 (0.0%)
+ Amarula Solutions 46 (0.0%)
+ Collabora Ltd. 35 (0.0%)
+ BayLibre SAS 14 (0.0%)
+ Weidmüller Interface GmbH & Co. KG 13 (0.0%)
+ Samsung 8 (0.0%)
+ Marvell 5 (0.0%)
+ Broadcom 2 (0.0%)
+ Digi International 2 (0.0%)
+ Siemens 1 (0.0%)
+ ==================================== =====
+
+
+.. table:: Employers with the most signoffs (total 231)
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ (Unknown) 56 (24.2%)
+ Linaro 56 (24.2%)
+ Texas Instruments 33 (14.3%)
+ BayLibre SAS 19 (8.2%)
+ AMD 17 (7.4%)
+ Amarula Solutions 11 (4.8%)
+ Analog Devices 9 (3.9%)
+ Samsung 7 (3.0%)
+ Siemens 6 (2.6%)
+ DENX Software Engineering 4 (1.7%)
+ Toradex 3 (1.3%)
+ Canonical 3 (1.3%)
+ Phytec 2 (0.9%)
+ Rockchip 2 (0.9%)
+ Intel 1 (0.4%)
+ NXP 1 (0.4%)
+ ST Microelectronics 1 (0.4%)
+ ==================================== =====
+
+
+.. table:: Employers with the most hackers (total 195)
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ (Unknown) 98 (50.3%)
+ Texas Instruments 20 (10.3%)
+ Linaro 10 (5.1%)
+ AMD 8 (4.1%)
+ Toradex 8 (4.1%)
+ Phytec 5 (2.6%)
+ Intel 5 (2.6%)
+ DENX Software Engineering 4 (2.1%)
+ Rockchip 4 (2.1%)
+ ST Microelectronics 4 (2.1%)
+ Amarula Solutions 3 (1.5%)
+ Google LLC 3 (1.5%)
+ Samsung 2 (1.0%)
+ NXP 2 (1.0%)
+ Edgeble AI Technologies Pvt. Ltd. 2 (1.0%)
+ ARM 2 (1.0%)
+ Socionext Inc. 2 (1.0%)
+ linutronix 2 (1.0%)
+ Collabora Ltd. 2 (1.0%)
+ BayLibre SAS 1 (0.5%)
+ Siemens 1 (0.5%)
+ Konsulko Group 1 (0.5%)
+ Renesas Electronics 1 (0.5%)
+ Red Hat 1 (0.5%)
+ Weidmüller Interface GmbH & Co. KG 1 (0.5%)
+ Marvell 1 (0.5%)
+ Broadcom 1 (0.5%)
+ Digi International 1 (0.5%)
+ ==================================== =====
+
diff --git a/doc/develop/testing.rst b/doc/develop/testing.rst
index 5afeb42..9114d11 100644
--- a/doc/develop/testing.rst
+++ b/doc/develop/testing.rst
@@ -69,7 +69,7 @@
./test/py/test.py --bd sandbox_spl --build -k test_spl
-See test/py/README.md for more information about the pytest suite.
+See :doc:`py_testing` for more information about the pytest suite.
See :doc:`tests_sandbox` for how to run tests directly (not through pytest).
@@ -123,7 +123,7 @@
is much easier to add onto a test - writing a new large test can seem
daunting to most contributors.
-See doc:`tests_writing` for how to write tests.
+See :doc:`tests_writing` for how to write tests.
Future work
diff --git a/doc/develop/uefi/fwu_updates.rst b/doc/develop/uefi/fwu_updates.rst
index e4709d8..51e8a28 100644
--- a/doc/develop/uefi/fwu_updates.rst
+++ b/doc/develop/uefi/fwu_updates.rst
@@ -46,6 +46,8 @@
CONFIG_FWU_NUM_BANKS=<val>
CONFIG_FWU_NUM_IMAGES_PER_BANK=<val>
+ CONFIG_FWU_MDATA_V1=y or CONFIG_FWU_MDATA_V2=y
+
in the .config file
By enabling the CONFIG_CMD_FWU_METADATA config option, the
@@ -58,6 +60,14 @@
section :ref:`uefi_capsule_update_ref` for more details on generation
of the UEFI capsule.
+FWU Metadata
+------------
+
+U-Boot supports both versions(1 and 2) of the FWU metadata defined in
+the two revisions of the specification. Support can be enabled for
+either of the two versions through a config flag. The mkfwumdata tool
+can generate metadata for both the supported versions.
+
Setting up the device for GPT partitioned storage
-------------------------------------------------
@@ -94,12 +104,12 @@
* UniquePartitionGUID
The PartitionTypeGUID value should correspond to the
-``image_type_uuid`` field of the FWU metadata. This field is used to
+``image_type_guid`` field of the FWU metadata. This field is used to
identify a given type of updatable firmware image, e.g. U-Boot,
OP-TEE, FIP etc. This GUID should also be used for specifying the
`--guid` parameter when generating the capsule.
-The UniquePartitionGUID value should correspond to the ``image_uuid``
+The UniquePartitionGUID value should correspond to the ``image_guid``
field in the FWU metadata. This GUID is used to identify images of a
given image type in different banks.
@@ -108,8 +118,8 @@
metadata partitions. Similarly, the UEFI specification defines the ESP
GUID to be be used.
-When generating the metadata, the ``image_type_uuid`` and the
-``image_uuid`` values should match the *PartitionTypeGUID* and the
+When generating the metadata, the ``image_type_guid`` and the
+``image_guid`` values should match the *PartitionTypeGUID* and the
*UniquePartitionGUID* values respectively.
Performing the Update
@@ -181,5 +191,5 @@
Links
-----
-* [1] https://developer.arm.com/documentation/den0118/a/ - FWU Specification
+* [1] https://developer.arm.com/documentation/den0118/ - FWU Specification
* [2] https://git.codelinaro.org/linaro/dependable-boot/mbfw/uploads/6f7ddfe3be24e18d4319e108a758d02e/mbfw.pdf - Dependable Boot Specification
diff --git a/doc/develop/uefi/uefi.rst b/doc/develop/uefi/uefi.rst
index 0389b26..88596f3 100644
--- a/doc/develop/uefi/uefi.rst
+++ b/doc/develop/uefi/uefi.rst
@@ -72,7 +72,7 @@
CONFIG_BOOTM_EFI=y
-A sample configuration is provided as file doc/uImage.FIT/uefi.its.
+A sample configuration is provided in :doc:`../../usage/fit/uefi`.
Below you find the output of an example session starting GRUB::
@@ -96,7 +96,7 @@
## Transferring control to EFI (at address 404000d0) ...
Welcome to GRUB!
-See doc/uImage.FIT/howto.txt for an introduction to FIT images.
+See :doc:`../../usage/fit/howto` for an introduction to FIT images.
Configuring UEFI secure boot
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -631,6 +631,18 @@
The properties of image-type-id and image-index must match the value
defined in the efi_fw_image array as image_type_id and image_index.
+Porting Capsule Updates to new boards
+*************************************
+
+It is important, when using a reference board as a starting point for a custom
+board, that certain steps are taken to properly support Capsule Updates.
+
+Capsule GUIDs need to be unique for each firmware and board. That is, if two
+firmwares are built from the same source but result in different binaries
+because they are built for different boards, they should have different GUIDs.
+Therefore it is important when creating support for a new board, new GUIDs are
+defined in the board's header file. *DO NOT* reuse capsule GUIDs.
+
Executing the boot manager
~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/doc/device-tree-bindings/clock/samsung,exynos850-clock.yaml b/doc/device-tree-bindings/clock/samsung,exynos850-clock.yaml
deleted file mode 100644
index a0906ef..0000000
--- a/doc/device-tree-bindings/clock/samsung,exynos850-clock.yaml
+++ /dev/null
@@ -1,307 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/clock/samsung,exynos850-clock.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Samsung Exynos850 SoC clock controller
-
-maintainers:
- - Sam Protsenko <semen.protsenko@linaro.org>
-
-description: |
- Exynos850 clock controller is comprised of several CMU units, generating
- clocks for different domains. Those CMU units are modeled as separate device
- tree nodes, and might depend on each other. Root clocks in that clock tree are
- two external clocks:: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external
- clocks must be defined as fixed-rate clocks in dts.
-
- CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
- dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
-
- Each clock is assigned an identifier and client nodes can use this identifier
- to specify the clock which they consume. All clocks available for usage
- in clock consumer nodes are defined as preprocessor macros in
- 'dt-bindings/clock/exynos850.h' header.
-
-properties:
- compatible:
- enum:
- - samsung,exynos850-cmu-top
- - samsung,exynos850-cmu-apm
- - samsung,exynos850-cmu-aud
- - samsung,exynos850-cmu-cmgp
- - samsung,exynos850-cmu-core
- - samsung,exynos850-cmu-dpu
- - samsung,exynos850-cmu-g3d
- - samsung,exynos850-cmu-hsi
- - samsung,exynos850-cmu-is
- - samsung,exynos850-cmu-mfcmscl
- - samsung,exynos850-cmu-peri
-
- clocks:
- minItems: 1
- maxItems: 5
-
- clock-names:
- minItems: 1
- maxItems: 5
-
- "#clock-cells":
- const: 1
-
- reg:
- maxItems: 1
-
-allOf:
- - if:
- properties:
- compatible:
- contains:
- const: samsung,exynos850-cmu-top
-
- then:
- properties:
- clocks:
- items:
- - description: External reference clock (26 MHz)
-
- clock-names:
- items:
- - const: oscclk
-
- - if:
- properties:
- compatible:
- contains:
- const: samsung,exynos850-cmu-apm
-
- then:
- properties:
- clocks:
- items:
- - description: External reference clock (26 MHz)
- - description: CMU_APM bus clock (from CMU_TOP)
-
- clock-names:
- items:
- - const: oscclk
- - const: dout_clkcmu_apm_bus
-
- - if:
- properties:
- compatible:
- contains:
- const: samsung,exynos850-cmu-aud
-
- then:
- properties:
- clocks:
- items:
- - description: External reference clock (26 MHz)
- - description: AUD clock (from CMU_TOP)
-
- clock-names:
- items:
- - const: oscclk
- - const: dout_aud
-
- - if:
- properties:
- compatible:
- contains:
- const: samsung,exynos850-cmu-cmgp
-
- then:
- properties:
- clocks:
- items:
- - description: External reference clock (26 MHz)
- - description: CMU_CMGP bus clock (from CMU_APM)
-
- clock-names:
- items:
- - const: oscclk
- - const: gout_clkcmu_cmgp_bus
-
- - if:
- properties:
- compatible:
- contains:
- const: samsung,exynos850-cmu-core
-
- then:
- properties:
- clocks:
- items:
- - description: External reference clock (26 MHz)
- - description: CMU_CORE bus clock (from CMU_TOP)
- - description: CCI clock (from CMU_TOP)
- - description: eMMC clock (from CMU_TOP)
- - description: SSS clock (from CMU_TOP)
-
- clock-names:
- items:
- - const: oscclk
- - const: dout_core_bus
- - const: dout_core_cci
- - const: dout_core_mmc_embd
- - const: dout_core_sss
-
- - if:
- properties:
- compatible:
- contains:
- const: samsung,exynos850-cmu-dpu
-
- then:
- properties:
- clocks:
- items:
- - description: External reference clock (26 MHz)
- - description: DPU clock (from CMU_TOP)
-
- clock-names:
- items:
- - const: oscclk
- - const: dout_dpu
-
- - if:
- properties:
- compatible:
- contains:
- const: samsung,exynos850-cmu-g3d
-
- then:
- properties:
- clocks:
- items:
- - description: External reference clock (26 MHz)
- - description: G3D clock (from CMU_TOP)
-
- clock-names:
- items:
- - const: oscclk
- - const: dout_g3d_switch
-
- - if:
- properties:
- compatible:
- contains:
- const: samsung,exynos850-cmu-hsi
-
- then:
- properties:
- clocks:
- items:
- - description: External reference clock (26 MHz)
- - description: External RTC clock (32768 Hz)
- - description: CMU_HSI bus clock (from CMU_TOP)
- - description: SD card clock (from CMU_TOP)
- - description: USB 2.0 DRD clock (from CMU_TOP)
-
- clock-names:
- items:
- - const: oscclk
- - const: rtcclk
- - const: dout_hsi_bus
- - const: dout_hsi_mmc_card
- - const: dout_hsi_usb20drd
-
- - if:
- properties:
- compatible:
- contains:
- const: samsung,exynos850-cmu-is
-
- then:
- properties:
- clocks:
- items:
- - description: External reference clock (26 MHz)
- - description: CMU_IS bus clock (from CMU_TOP)
- - description: Image Texture Processing core clock (from CMU_TOP)
- - description: Visual Recognition Accelerator clock (from CMU_TOP)
- - description: Geometric Distortion Correction clock (from CMU_TOP)
-
- clock-names:
- items:
- - const: oscclk
- - const: dout_is_bus
- - const: dout_is_itp
- - const: dout_is_vra
- - const: dout_is_gdc
-
- - if:
- properties:
- compatible:
- contains:
- const: samsung,exynos850-cmu-mfcmscl
-
- then:
- properties:
- clocks:
- items:
- - description: External reference clock (26 MHz)
- - description: Multi-Format Codec clock (from CMU_TOP)
- - description: Memory to Memory Scaler clock (from CMU_TOP)
- - description: Multi-Channel Scaler clock (from CMU_TOP)
- - description: JPEG codec clock (from CMU_TOP)
-
- clock-names:
- items:
- - const: oscclk
- - const: dout_mfcmscl_mfc
- - const: dout_mfcmscl_m2m
- - const: dout_mfcmscl_mcsc
- - const: dout_mfcmscl_jpeg
-
- - if:
- properties:
- compatible:
- contains:
- const: samsung,exynos850-cmu-peri
-
- then:
- properties:
- clocks:
- items:
- - description: External reference clock (26 MHz)
- - description: CMU_PERI bus clock (from CMU_TOP)
- - description: UART clock (from CMU_TOP)
- - description: Parent clock for HSI2C and SPI (from CMU_TOP)
-
- clock-names:
- items:
- - const: oscclk
- - const: dout_peri_bus
- - const: dout_peri_uart
- - const: dout_peri_ip
-
-required:
- - compatible
- - "#clock-cells"
- - clocks
- - clock-names
- - reg
-
-additionalProperties: false
-
-examples:
- # Clock controller node for CMU_PERI
- - |
- #include <dt-bindings/clock/exynos850.h>
-
- cmu_peri: clock-controller@10030000 {
- compatible = "samsung,exynos850-cmu-peri";
- reg = <0x10030000 0x8000>;
- #clock-cells = <1>;
-
- clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>,
- <&cmu_top CLK_DOUT_PERI_UART>,
- <&cmu_top CLK_DOUT_PERI_IP>;
- clock-names = "oscclk", "dout_peri_bus",
- "dout_peri_uart", "dout_peri_ip";
- };
-
-...
diff --git a/doc/device-tree-bindings/soc/samsung/exynos-usi.yaml b/doc/device-tree-bindings/soc/samsung/exynos-usi.yaml
deleted file mode 100644
index 8e6423f..0000000
--- a/doc/device-tree-bindings/soc/samsung/exynos-usi.yaml
+++ /dev/null
@@ -1,162 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/soc/samsung/exynos-usi.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Samsung's Exynos USI (Universal Serial Interface)
-
-maintainers:
- - Sam Protsenko <semen.protsenko@linaro.org>
-
-description: |
- USI IP-core provides selectable serial protocol (UART, SPI or High-Speed I2C).
- USI shares almost all internal circuits within each protocol, so only one
- protocol can be chosen at a time. USI is modeled as a node with zero or more
- child nodes, each representing a serial sub-node device. The mode setting
- selects which particular function will be used.
-
-properties:
- $nodename:
- pattern: "^usi@[0-9a-f]+$"
-
- compatible:
- enum:
- - samsung,exynos850-usi
-
- reg: true
-
- clocks: true
-
- clock-names: true
-
- ranges: true
-
- "#address-cells":
- const: 1
-
- "#size-cells":
- const: 1
-
- samsung,sysreg:
- $ref: /schemas/types.yaml#/definitions/phandle-array
- items:
- - items:
- - description: phandle to System Register syscon node
- - description: offset of SW_CONF register for this USI controller
- description:
- Should be phandle/offset pair. The phandle to System Register syscon node
- (for the same domain where this USI controller resides) and the offset
- of SW_CONF register for this USI controller.
-
- samsung,mode:
- $ref: /schemas/types.yaml#/definitions/uint32
- description:
- Selects USI function (which serial protocol to use). Refer to
- <include/dt-bindings/soc/samsung,exynos-usi.h> for valid USI mode values.
-
- samsung,clkreq-on:
- type: boolean
- description:
- Enable this property if underlying protocol requires the clock to be
- continuously provided without automatic gating. As suggested by SoC
- manual, it should be set in case of SPI/I2C slave, UART Rx and I2C
- multi-master mode. Usually this property is needed if USI mode is set
- to "UART".
-
- This property is optional.
-
-patternProperties:
- "^i2c@[0-9a-f]+$":
- $ref: /schemas/i2c/i2c-exynos5.yaml
- description: Child node describing underlying I2C
-
- "^serial@[0-9a-f]+$":
- $ref: /schemas/serial/samsung_uart.yaml
- description: Child node describing underlying UART/serial
-
- "^spi@[0-9a-f]+$":
- $ref: /schemas/spi/samsung,spi.yaml
- description: Child node describing underlying SPI
-
-required:
- - compatible
- - ranges
- - "#address-cells"
- - "#size-cells"
- - samsung,sysreg
- - samsung,mode
-
-if:
- properties:
- compatible:
- contains:
- enum:
- - samsung,exynos850-usi
-
-then:
- properties:
- reg:
- maxItems: 1
-
- clocks:
- items:
- - description: Bus (APB) clock
- - description: Operating clock for UART/SPI/I2C protocol
-
- clock-names:
- items:
- - const: pclk
- - const: ipclk
-
- required:
- - reg
- - clocks
- - clock-names
-
-else:
- properties:
- reg: false
- clocks: false
- clock-names: false
- samsung,clkreq-on: false
-
-additionalProperties: false
-
-examples:
- - |
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/soc/samsung,exynos-usi.h>
-
- usi0: usi@138200c0 {
- compatible = "samsung,exynos850-usi";
- reg = <0x138200c0 0x20>;
- samsung,sysreg = <&sysreg_peri 0x1010>;
- samsung,mode = <USI_V2_UART>;
- samsung,clkreq-on; /* needed for UART mode */
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- clocks = <&cmu_peri 32>, <&cmu_peri 31>;
- clock-names = "pclk", "ipclk";
-
- serial_0: serial@13820000 {
- compatible = "samsung,exynos850-uart";
- reg = <0x13820000 0xc0>;
- interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cmu_peri 32>, <&cmu_peri 31>;
- clock-names = "uart", "clk_uart_baud0";
- status = "disabled";
- };
-
- hsi2c_0: i2c@13820000 {
- compatible = "samsung,exynosautov9-hsi2c";
- reg = <0x13820000 0xc0>;
- interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cmu_peri 31>, <&cmu_peri 32>;
- clock-names = "hsi2c", "hsi2c_pclk";
- status = "disabled";
- };
- };
diff --git a/doc/imx/habv4/csf_examples/mx8m/csf.sh b/doc/imx/habv4/csf_examples/mx8m/csf.sh
deleted file mode 100644
index cd3b261..0000000
--- a/doc/imx/habv4/csf_examples/mx8m/csf.sh
+++ /dev/null
@@ -1,92 +0,0 @@
-#!/bin/sh
-
-# 0) Generate keys
-#
-# WARNING: ECDSA keys are only supported by HAB 4.5 and newer (i.e. i.MX8M Plus)
-#
-# cd /path/to/cst-3.3.1/keys/
-# ./hab4_pki_tree.sh -existing-ca n -use-ecc n -kl 4096 -duration 10 -num-srk 4 -srk-ca y
-# cd /path/to/cst-3.3.1/crts/
-# ../linux64/bin/srktool -h 4 -t SRK_1_2_3_4_table.bin -e SRK_1_2_3_4_fuse.bin -d sha256 -c ./SRK1_sha256_4096_65537_v3_ca_crt.pem,./SRK2_sha256_4096_65537_v3_ca_crt.pem,./SRK3_sha256_4096_65537_v3_ca_crt.pem,./SRK4_sha256_4096_65537_v3_ca_crt.pem -f 1
-
-# 1) Build U-Boot (e.g. for i.MX8MM)
-#
-# cp -Lv /path/to/arm-trusted-firmware/build/imx8mm/release/bl31.bin .
-# cp -Lv /path/to/firmware-imx-8.14/firmware/ddr/synopsys/ddr3* .
-# make -j imx8mm_board_defconfig
-# make -j`nproc` flash.bin
-
-# 2) Sign SPL and DRAM blobs
-
-cp doc/imx/habv4/csf_examples/mx8m/csf_spl.txt csf_spl.tmp
-cp doc/imx/habv4/csf_examples/mx8m/csf_fit.txt csf_fit.tmp
-
-# update File Paths from env vars
-if ! [ -r $CSF_KEY ]; then
- echo "Error: \$CSF_KEY not found"
- exit 1
-fi
-if ! [ -r $IMG_KEY ]; then
- echo "Error: \$IMG_KEY not found"
- exit 1
-fi
-if ! [ -r $SRK_TABLE ]; then
- echo "Error: \$SRK_TABLE not found"
- exit 1
-fi
-sed -i "s:\$CSF_KEY:$CSF_KEY:" csf_spl.tmp
-sed -i "s:\$IMG_KEY:$IMG_KEY:" csf_spl.tmp
-sed -i "s:\$SRK_TABLE:$SRK_TABLE:" csf_spl.tmp
-sed -i "s:\$CSF_KEY:$CSF_KEY:" csf_fit.tmp
-sed -i "s:\$IMG_KEY:$IMG_KEY:" csf_fit.tmp
-sed -i "s:\$SRK_TABLE:$SRK_TABLE:" csf_fit.tmp
-
-# update SPL Blocks
-spl_block_base=$(printf "0x%x" $(( $(sed -n "/CONFIG_SPL_TEXT_BASE=/ s@.*=@@p" .config) - 0x40)) )
-spl_block_size=$(printf "0x%x" $(stat -tc %s u-boot-spl-ddr.bin))
-sed -i "/Blocks = / s@.*@ Blocks = $spl_block_base 0x0 $spl_block_size \"flash.bin\"@" csf_spl.tmp
-
-# Generate CSF blob
-cst -i csf_spl.tmp -o csf_spl.bin
-
-# Patch CSF blob into flash.bin
-spl_csf_offset=$(xxd -s 24 -l 4 -e flash.bin | cut -d " " -f 2 | sed "s@^@0x@")
-spl_bin_offset=$(xxd -s 4 -l 4 -e flash.bin | cut -d " " -f 2 | sed "s@^@0x@")
-spl_dd_offset=$((${spl_csf_offset} - ${spl_bin_offset} + 0x40))
-dd if=csf_spl.bin of=flash.bin bs=1 seek=${spl_dd_offset} conv=notrunc
-
-# 3) Sign u-boot.itb
-
-# fitImage
-fit_block_base=$(printf "0x%x" $(sed -n "/CONFIG_SPL_LOAD_FIT_ADDRESS=/ s@.*=@@p" .config) )
-fit_block_offset=$(printf "0x%s" $(fdtget -t x u-boot.dtb /binman/imx-boot/uboot offset))
-fit_block_size=$(printf "0x%x" $(( ( ( $(stat -tc %s u-boot.itb) + 0x1000 - 0x1 ) & ~(0x1000 - 0x1)) + 0x20 )) )
-sed -i "/Blocks = / s@.*@ Blocks = $fit_block_base $fit_block_offset $fit_block_size \"flash.bin\"@" csf_fit.tmp
-
-# IVT
-ivt_ptr_base=$(printf "%08x" ${fit_block_base} | sed "s@\(..\)\(..\)\(..\)\(..\)@0x\4\3\2\1@")
-ivt_block_base=$(printf "%08x" $(( ${fit_block_base} + ${fit_block_size} - 0x20 )) | sed "s@\(..\)\(..\)\(..\)\(..\)@0x\4\3\2\1@")
-csf_block_base=$(printf "%08x" $(( ${fit_block_base} + ${fit_block_size} )) | sed "s@\(..\)\(..\)\(..\)\(..\)@0x\4\3\2\1@")
-ivt_block_offset=$((${fit_block_offset} + ${fit_block_size} - 0x20))
-csf_block_offset=$((${ivt_block_offset} + 0x20))
-
-echo "0xd1002041 ${ivt_block_base} 0x00000000 0x00000000 0x00000000 ${ivt_block_base} ${csf_block_base} 0x00000000" | xxd -r -p > ivt.bin
-dd if=ivt.bin of=flash.bin bs=1 seek=${ivt_block_offset} conv=notrunc
-
-# Generate CSF blob
-cst -i csf_fit.tmp -o csf_fit.bin
-
-# When loading flash.bin via USB, we must ensure that the file being
-# served is as large as the target expects (see
-# board_spl_fit_size_align()), otherwise the target will hang in
-# rom_api_download_image() waiting for the remaining bytes.
-#
-# Note that in order for dd to actually extend the file, one must not
-# pass conv=notrunc here. With a non-zero seek= argument, dd is
-# documented to preserve the contents of the file seeked past; in
-# particular, dd does not open the file with O_TRUNC.
-CSF_SIZE=$(sed -n "/CONFIG_CSF_SIZE=/ s@.*=@@p" .config)
-dd if=/dev/null of=csf_fit.bin bs=1 seek=$((CSF_SIZE - 0x20)) count=0
-
-# Patch CSF blob into flash.bin
-dd if=csf_fit.bin of=flash.bin bs=1 seek=${csf_block_offset} conv=notrunc
diff --git a/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt b/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt
deleted file mode 100644
index 97f3eea..0000000
--- a/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt
+++ /dev/null
@@ -1,30 +0,0 @@
-[Header]
- Version = 4.3
- Hash Algorithm = sha256
- Engine = CAAM
- Engine Configuration = 0
- Certificate Format = X509
- Signature Format = CMS
-
-[Install SRK]
- # SRK_TABLE is full path to SRK_1_2_3_4_table.bin
- File = "$SRK_TABLE"
- Source index = 0
-
-[Install CSFK]
- # CSF_KEY is full path to CSF1_1_sha256_4096_65537_v3_usr_crt.pem
- File = "$CSF_KEY"
-
-[Authenticate CSF]
-
-[Install Key]
- Verification index = 0
- Target Index = 2
- # IMG_KEY is full path to IMG1_1_sha256_4096_65537_v3_usr_crt.pem
- File = "$IMG_KEY"
-
-[Authenticate Data]
- Verification index = 2
- # FIXME:
- # Line 1 -- fitImage
- Blocks = CONFIG_SPL_LOAD_FIT_ADDRESS 0x57c00 0xffff "flash.bin"
diff --git a/doc/imx/habv4/csf_examples/mx8m/csf_spl.txt b/doc/imx/habv4/csf_examples/mx8m/csf_spl.txt
deleted file mode 100644
index 88fa420..0000000
--- a/doc/imx/habv4/csf_examples/mx8m/csf_spl.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-[Header]
- Version = 4.3
- Hash Algorithm = sha256
- Engine = CAAM
- Engine Configuration = 0
- Certificate Format = X509
- Signature Format = CMS
-
-[Install SRK]
- # SRK_TABLE is full path to SRK_1_2_3_4_table.bin
- File = "$SRK_TABLE"
- Source index = 0
-
-[Install CSFK]
- # CSF_KEY is full path to CSF1_1_sha256_4096_65537_v3_usr_crt.pem
- File = "$CSF_KEY"
-
-[Authenticate CSF]
-
-[Unlock]
- Engine = CAAM
- Features = MID
-
-[Install Key]
- Verification index = 0
- Target Index = 2
- # IMG_KEY is full path to IMG1_1_sha256_4096_65537_v3_usr_crt.pem
- File = "$IMG_KEY"
-
-[Authenticate Data]
- Verification index = 2
- # FIXME: Adjust start (first column) and size (third column) here
- Blocks = 0x7e0fc0 0x0 0x306f0 "flash.bin"
diff --git a/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt b/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt
index e16e541..1bea091 100644
--- a/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt
+++ b/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt
@@ -121,6 +121,9 @@
- Defconfig:
CONFIG_IMX_HAB=y
+ CONFIG_FSL_CAAM=y
+ CONFIG_ARCH_MISC_INIT=y
+ CONFIG_SPL_CRYPTO=y
- Kconfig:
@@ -131,91 +134,59 @@
The CSF contains all the commands that the HAB executes during the secure
boot. These commands instruct the HAB code on which memory areas of the image
-to authenticate, which keys to install, use and etc.
+to authenticate, which keys to install, use and etc. The CSF is generated
+using the CST Code Signing Tool based on input configuration file. This tool
+input configuration file is generated using binman, and the tool is invoked
+from binman as well.
-CSF examples are available under doc/imx/habv4/csf_examples/ directory.
+The SPL and fitImage sections of the generated image are signed separately.
+The signing is activated by wrapping SPL and fitImage sections into nxp-imx8mcst
+etype, which is done automatically in arch/arm/dts/imx8m{m,n,p,q}-u-boot.dtsi
+in case CONFIG_IMX_HAB Kconfig symbol is enabled.
-CSF "Blocks" line for csf_spl.txt can be generated as follows:
+Per default the HAB keys and certificates need to be located in the build
+directory, this means creating a symbolic link or copying the following files
+from the HAB keys directory flat (e.g. removing the `keys` and `cert`
+subdirectory) into the u-boot build directory for the CST Code Signing Tool to
+locate them:
-```
-spl_block_base=$(printf "0x%x" $(( $(sed -n "/CONFIG_SPL_TEXT_BASE=/ s@.*=@@p" .config) - 0x40)) )
-spl_block_size=$(printf "0x%x" $(stat -tc %s u-boot-spl-ddr.bin))
-sed -i "/Blocks = / s@.*@ Blocks = $spl_block_base 0x0 $spl_block_size \"flash.bin\"@" csf_spl.txt
-```
+- `crts/SRK_1_2_3_4_table.bin`
+- `crts/CSF1_1_sha256_4096_65537_v3_usr_crt.pem`
+- `keys/CSF1_1_sha256_4096_65537_v3_usr_key.pem`
+- `crts/IMG1_1_sha256_4096_65537_v3_usr_crt.pem`
+- `keys/IMG1_1_sha256_4096_65537_v3_usr_key.pem`
+- `keys/key_pass.txt`
-The resulting line looks as follows:
-```
- Blocks = 0x7e0fc0 0x0 0x306f0 "flash.bin"
-```
+The paths to the SRK table and the certificates can be modified via changes to
+the nxp_imx8mcst device tree node(s), however the other files are required by
+the CST tools as well, and will be searched for in relation to them.
-The columns mean:
- - CONFIG_SPL_TEXT_BASE - 0x40 -- Start address of signed data, in DRAM
- - 0x0 -- Start address of signed data, in "flash.bin"
- - 0x306f0 -- Length of signed data, in "flash.bin"
- - Filename -- "flash.bin"
+Build of flash.bin target then produces a signed flash.bin automatically.
-To generate signature for the SPL part of flash.bin container, use CST:
-```
-cst -i csf_spl.tmp -o csf_spl.bin
-```
+The nxp-imx8mcst etype is configurable using either DT properties or environment
+variables. The following DT properties and environment variables are supported.
+Note that environment variables override DT properties.
-The newly generated CST blob has to be patched into existing flash.bin
-container. Conveniently, flash.bin IVT contains physical address of the
-CSF blob. Remember, the SPL part of flash.bin container is loaded by the
-BootROM at CONFIG_SPL_TEXT_BASE - 0x40 , so the offset of CSF blob in
-the fitImage can be calculated and inserted into the flash.bin in the
-correct location as follows:
-```
-# offset = IVT_HEADER[6 = CSF address] - CONFIG_SPL_TEXT_BASE - 0x40
-spl_csf_offset=$(xxd -s 24 -l 4 -e flash.bin | cut -d " " -f 2 | sed "s@^@0x@")
-spl_bin_offset=$(xxd -s 4 -l 4 -e flash.bin | cut -d " " -f 2 | sed "s@^@0x@")
-spl_dd_offset=$((${spl_csf_offset} - ${spl_bin_offset} + 0x40))
-dd if=csf_spl.bin of=flash.bin bs=1 seek=${spl_dd_offset} conv=notrunc
-```
-
-CSF "Blocks" line for csf_fit.txt can be generated as follows:
-```
-# fitImage
-fit_block_base=$(printf "0x%x" $(sed -n "/CONFIG_SPL_LOAD_FIT_ADDRESS=/ s@.*=@@p" .config) )
-fit_block_offset=$(printf "0x%s" $(fdtget -t x u-boot.dtb /binman/imx-boot/uboot offset))
-fit_block_size=$(printf "0x%x" $(( ( ( $(stat -tc %s u-boot.itb) + 0x1000 - 0x1 ) & ~(0x1000 - 0x1)) + 0x20 )) )
-sed -i "/Blocks = / s@.*@ Blocks = $fit_block_base $fit_block_offset $fit_block_size \"flash.bin\"@" csf_fit.tmp
-```
++--------------------+-----------+------------------------------------------------------------------+
+| DT property | Variable | Description |
++====================+===========+==================================================================+
+| nxp,loader-address | | SPL base address |
++--------------------+-----------+------------------------------------------------------------------+
+| nxp,srk-table | SRK_TABLE | full path to SRK_1_2_3_4_table.bin |
++--------------------+-----------+------------------------------------------------------------------+
+| nxp,csf-crt | CSF_KEY | full path to the CSF Key CSF1_1_sha256_4096_65537_v3_usr_crt.pem |
++--------------------+-----------+------------------------------------------------------------------+
+| nxp,img-crt | IMG_KEY | full path to the IMG Key IMG1_1_sha256_4096_65537_v3_usr_crt.pem |
++--------------------+-----------+------------------------------------------------------------------+
-The fitImage part of flash.bin requires separate IVT. Generate the IVT and
-patch it into the correct aligned location of flash.bin as follows:
-```
-# IVT
-ivt_ptr_base=$(printf "%08x" ${fit_block_base} | sed "s@\(..\)\(..\)\(..\)\(..\)@0x\4\3\2\1@")
-ivt_block_base=$(printf "%08x" $(( ${fit_block_base} + ${fit_block_size} - 0x20 )) | sed "s@\(..\)\(..\)\(..\)\(..\)@0x\4\3\2\1@")
-csf_block_base=$(printf "%08x" $(( ${fit_block_base} + ${fit_block_size} )) | sed "s@\(..\)\(..\)\(..\)\(..\)@0x\4\3\2\1@")
-ivt_block_offset=$((${fit_block_offset} + ${fit_block_size} - 0x20))
-csf_block_offset=$((${ivt_block_offset} + 0x20))
-
-echo "0xd1002041 ${ivt_block_base} 0x00000000 0x00000000 0x00000000 ${ivt_block_base} ${csf_block_base} 0x00000000" | xxd -r -p > ivt.bin
-dd if=ivt.bin of=flash.bin bs=1 seek=${ivt_block_offset} conv=notrunc
-```
-
-To generate CSF signature for the fitImage part of flash.bin container, use CST:
-```
-cst -i csf_fit.tmp -o csf_fit.bin
-```
-
-Finally, patch the CSF signature into the fitImage right past the IVT:
-```
-dd if=csf_fit.bin of=flash.bin bs=1 seek=${csf_block_offset} conv=notrunc
-```
-
-The entire script is available in doc/imx/habv4/csf_examples/mx8m/csf.sh
-and can be used as follows to modify flash.bin to be signed
-(adjust paths as needed):
+Environment variables can be set as follows to point the build process
+to external key material:
```
export CST_DIR=/usr/src/cst-3.3.1/
export CSF_KEY=$CST_DIR/crts/CSF1_1_sha256_4096_65537_v3_usr_crt.pem
export IMG_KEY=$CST_DIR/crts/IMG1_1_sha256_4096_65537_v3_usr_crt.pem
export SRK_TABLE=$CST_DIR/crts/SRK_1_2_3_4_table.bin
-export PATH=$CST_DIR/linux64/bin:$PATH
-/bin/sh doc/imx/habv4/csf_examples/mx8m/csf.sh
+make flash.bin
```
1.4 Closing the device
diff --git a/doc/mkfwumdata.1 b/doc/mkfwumdata.1
index 7dd718b..2ed0fb1 100644
--- a/doc/mkfwumdata.1
+++ b/doc/mkfwumdata.1
@@ -6,9 +6,11 @@
.
.SH SYNOPSIS
.SY mkfwumdata
+.OP \-v version
.OP \-a activeidx
.OP \-p previousidx
.OP \-g
+.OP \-V vendor-file
.BI \-i\~ imagecount
.BI \-b\~ bankcount
.I UUIDs
@@ -28,6 +30,12 @@
Print usage information and exit.
.
.TP
+.B \-v
+Set
+.IR version
+as the metadata version to generate. Valid values 1 or 2.
+.
+.TP
.B \-a
Set
.IR activeidx
@@ -50,6 +58,12 @@
as GUIDs before use.
.
.TP
+.B \-V
+Pass
+.IR vendor-file
+for appending vendor data to the metadata. Supported only with version 2.
+.
+.TP
.B \-i
Specify there are
.IR imagecount
@@ -81,7 +95,7 @@
.EX
.in +4
$ \c
-.B mkfwumdata \-a 0 \-p 1 \-b 2 \-i 1 \\\\\&
+.B mkfwumdata \-v 2 \-a 0 \-p 1 \-b 2 \-i 1 \\\\\&
.in +6
.B 17e86d77-41f9-4fd7-87ec-a55df9842de5,\\\\\&
.B 10c36d7d-ca52-b843-b7b9-f9d6c501d108,\\\\\&
diff --git a/doc/sphinx/requirements.txt b/doc/sphinx/requirements.txt
index 426f41e..306b05a 100644
--- a/doc/sphinx/requirements.txt
+++ b/doc/sphinx/requirements.txt
@@ -1,18 +1,18 @@
alabaster==0.7.16
-Babel==2.14.0
-certifi==2023.11.17
+Babel==2.15.0
+certifi==2024.6.2
charset-normalizer==3.3.2
docutils==0.20.1
idna==3.7
imagesize==1.4.1
Jinja2==3.1.4
-MarkupSafe==2.1.3
-packaging==23.2
-Pygments==2.17.2
-requests==2.31.0
+MarkupSafe==2.1.5
+packaging==24.1
+Pygments==2.18.0
+requests==2.32.3
six==1.16.0
snowballstemmer==2.2.0
-Sphinx==7.2.6
+Sphinx==7.3.7
sphinx-prompt==1.8.0
sphinx-rtd-theme==2.0.0
sphinxcontrib-applehelp==1.0.8
@@ -22,4 +22,4 @@
sphinxcontrib-jsmath==1.0.1
sphinxcontrib-qthelp==1.0.7
sphinxcontrib-serializinghtml==1.1.10
-urllib3==2.1.0
+urllib3==2.2.1
diff --git a/doc/usage/cmd/bootmeth.rst b/doc/usage/cmd/bootmeth.rst
index 2903977..bac9fdf 100644
--- a/doc/usage/cmd/bootmeth.rst
+++ b/doc/usage/cmd/bootmeth.rst
@@ -48,7 +48,7 @@
===== === ================== =================================
Order Seq Name Description
===== === ================== =================================
- 0 0 extlinunx Extlinux boot from a block device
+ 0 0 extlinux Extlinux boot from a block device
1 1 efi EFI boot from an .efi file
2 2 pxe PXE boot from a network device
3 3 sandbox Sandbox boot for testing
diff --git a/doc/usage/fit/beaglebone_vboot.rst b/doc/usage/fit/beaglebone_vboot.rst
index cd6bb14..1298ba1 100644
--- a/doc/usage/fit/beaglebone_vboot.rst
+++ b/doc/usage/fit/beaglebone_vboot.rst
@@ -67,18 +67,20 @@
export CROSS_COMPILE=arm-linux-gnueabi-
-b. Configure and build U-Boot with verified boot enabled::
+b. Configure and build U-Boot with verified boot enabled. Note that we use the
+am335x_evm target since it covers all boards based on the AM335x evaluation
+board::
export UBOOT=/path/to/u-boot
cd $UBOOT
# You can add -j10 if you have 10 CPUs to make it faster
- make O=b/am335x_boneblack_vboot am335x_boneblack_vboot_config all
- export UOUT=$UBOOT/b/am335x_boneblack_vboot
+ make O=b/am335x_evm am335x_evm_config all
+ export UOUT=$UBOOT/b/am335x_evm
c. You will now have a U-Boot image::
- file b/am335x_boneblack_vboot/u-boot-dtb.img
- b/am335x_boneblack_vboot/u-boot-dtb.img: u-boot legacy uImage,
+ file b/am335x_evm/u-boot-dtb.img
+ b/am335x_evm/u-boot-dtb.img: u-boot legacy uImage,
U-Boot 2014.07-rc2-00065-g2f69f8, Firmware/ARM, Firmware Image
(Not compressed), 395375 bytes, Sat May 31 16:19:04 2014,
Load Address: 0x80800000, Entry Point: 0x00000000,
@@ -466,7 +468,7 @@
you sign::
cd $UBOOT
- make O=b/am335x_boneblack_vboot EXT_DTB=${WORK}/am335x-boneblack-pubkey.dtb
+ make O=b/am335x_evm EXT_DTB=${WORK}/am335x-boneblack-pubkey.dtb
Here we are overriding the normal device tree file with our one, which
contains the public key.
@@ -597,14 +599,11 @@
Several of the steps here can be easily automated. In particular it would be
capital if signing and packaging a kernel were easy, perhaps a simple make
-target in the kernel.
+target in the kernel. A starting point for this is the 'make image.fit' target
+for ARM64 in Linux from v6.9 onwards.
Some mention of how to use multiple .dtb files in a FIT might be useful.
-U-Boot's verified boot mechanism has not had a robust and independent security
-review. Such a review should look at the implementation and its resistance to
-attacks.
-
Perhaps the verified boot feature could be integrated into the Amstrom
distribution.
diff --git a/doc/usage/fit/signature.rst b/doc/usage/fit/signature.rst
index 03a71b5..b868dcb 100644
--- a/doc/usage/fit/signature.rst
+++ b/doc/usage/fit/signature.rst
@@ -15,7 +15,7 @@
key is kept secret and the public key is stored in a non-volatile place,
any image can be verified in this way.
-See verified-boot.txt for more general information on verified boot.
+See :doc:`verified-boot` for more general information on verified boot.
Concepts
diff --git a/doc/usage/fit/source_file_format.rst b/doc/usage/fit/source_file_format.rst
index b2b1e42..15990e3 100644
--- a/doc/usage/fit/source_file_format.rst
+++ b/doc/usage/fit/source_file_format.rst
@@ -192,13 +192,13 @@
invalid Invalid Image
aisimage Davinci AIS image
atmelimage ATMEL ROM-Boot Image
- copro Coprocessor Image}
+ copro Coprocessor Image
fdt_legacy legacy Image with Flat Device Tree
filesystem Filesystem Image
firmware Firmware
- firmware_ivt Firmware with HABv4 IVT }
+ firmware_ivt Firmware with HABv4 IVT
flat_dt Flat Device Tree
- fpga FPGA Image }
+ fpga FPGA Device Image (bitstream file, vendor specific)
gpimage TI Keystone SPL Image
imx8image NXP i.MX8 Boot Image
imx8mimage NXP i.MX8M Boot Image
@@ -207,31 +207,31 @@
kernel_noload Kernel Image (no loading done)
kwbimage Kirkwood Boot Image
lpc32xximage LPC32XX Boot Image
- mtk_image MediaTek BootROM loadable Image }
+ mtk_image MediaTek BootROM loadable Image
multi Multi-File Image
mxsimage Freescale MXS Boot Image
omapimage TI OMAP SPL With GP CH
pblimage Freescale PBL Boot Image
pmmc TI Power Management Micro-Controller Firmware
ramdisk RAMDisk Image
- rkimage Rockchip Boot Image }
- rksd Rockchip SD Boot Image }
- rkspi Rockchip SPI Boot Image }
+ rkimage Rockchip Boot Image
+ rksd Rockchip SD Boot Image
+ rkspi Rockchip SPI Boot Image
script Script
socfpgaimage Altera SoCFPGA CV/AV preloader
socfpgaimage_v1 Altera SoCFPGA A10 preloader
- spkgimage Renesas SPKG Image }
+ spkgimage Renesas SPKG Image
standalone Standalone Program
- stm32image STMicroelectronics STM32 Image }
- sunxi_egon Allwinner eGON Boot Image }
- sunxi_toc0 Allwinner TOC0 Boot Image }
+ stm32image STMicroelectronics STM32 Image
+ sunxi_egon Allwinner eGON Boot Image
+ sunxi_toc0 Allwinner TOC0 Boot Image
tee Trusted Execution Environment Image
ublimage Davinci UBL image
vybridimage Vybrid Boot Image
x86_setup x86 setup.bin
- zynqimage Xilinx Zynq Boot Image }
- zynqmpbif Xilinx ZynqMP Boot Image (bif) }
- zynqmpimage Xilinx ZynqMP Boot Image }
+ zynqimage Xilinx Zynq Boot Image
+ zynqmpbif Xilinx ZynqMP Boot Image (bif)
+ zynqmpimage Xilinx ZynqMP Boot Image
==================== ==================
compression
@@ -254,9 +254,6 @@
zstd zstd compressed
==================== ==================
-data-size
- size of the data in bytes
-
Conditionally mandatory property
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -276,6 +273,9 @@
not relative to the loading of the FIT. This is mandatory if external data
used with a fixed address.
+data-size
+ Size of the data in bytes. This is mandatory if external data is used.
+
os
OS name, mandatory for types "kernel". Valid OS names are:
diff --git a/doc/usage/measured_boot.rst b/doc/usage/measured_boot.rst
index 9691904..05c439e 100644
--- a/doc/usage/measured_boot.rst
+++ b/doc/usage/measured_boot.rst
@@ -7,19 +7,46 @@
of the boot process, extending the results in the TPM and logging the
component's measurement in memory for the operating system to consume.
+The functionality is available when booting via the EFI subsystem or 'bootm'
+command.
+
+UEFI measured boot
+------------------
+
+The EFI subsystem implements the `EFI TCG protocol
+<https://trustedcomputinggroup.org/resource/tcg-efi-protocol-specification/>`_
+and the `TCG PC Client Specific Platform Firmware Profile Specification
+<https://trustedcomputinggroup.org/resource/pc-client-specific-platform-firmware-profile-specification/>`_
+which defines the binaries to be measured and the corresponding PCRs to be used.
+
+Requirements
+~~~~~~~~~~~~
+
+* A hardware TPM 2.0 supported by an enabled U-Boot driver
+* CONFIG_EFI_TCG2_PROTOCOL=y
+* CONFIG_EFI_TCG2_PROTOCOL_EVENTLOG_SIZE=y
+* optional CONFIG_EFI_TCG2_PROTOCOL_MEASURE_DTB=y will measure the loaded DTB
+ in PCR 1
+
+Legacy measured boot
+--------------------
+
+The commands booti, bootm, and bootz can be used for measured boot
+using the legacy entry point of the Linux kernel.
+
By default, U-Boot will measure the operating system (linux) image, the
initrd image, and the "bootargs" environment variable. By enabling
-CONFIG_MEASURE_DEVICETREE, U-Boot will also measure the devicetree image.
+CONFIG_MEASURE_DEVICETREE, U-Boot will also measure the devicetree image in PCR1.
The operating system typically would verify that the hashes found in the
TPM PCRs match the contents of the event log. This can further be checked
against the hash results of previous boots.
Requirements
-------------
+~~~~~~~~~~~~
-* A hardware TPM 2.0 supported by the U-Boot drivers
-* CONFIG_TPM=y
+* A hardware TPM 2.0 supported by an enabled U-Boot driver
+* CONFIG_TPMv2=y
* CONFIG_MEASURED_BOOT=y
* Device-tree configuration of the TPM device to specify the memory area
for event logging. The TPM device node must either contain a phandle to
diff --git a/doc/usage/netconsole.rst b/doc/usage/netconsole.rst
index 2aa3b9c..df27b78 100644
--- a/doc/usage/netconsole.rst
+++ b/doc/usage/netconsole.rst
@@ -3,10 +3,10 @@
In U-Boot, we implemented the networked console via the standard
"devices" mechanism, which means that you can switch between the
-serial and network input/output devices by adjusting the 'stdin' and
-'stdout' environment variables. To switch to the networked console,
-set either of these variables to "nc". Input and output can be
-switched independently.
+serial and network input/output devices by adjusting the 'stdin',
+'stdout', and 'stderr' environment variables. To switch to the
+networked console, set either of these variables to "nc". Input and
+output can be switched independently.
The default buffer size can be overridden by setting
CFG_NETCONSOLE_BUFFER_SIZE.
@@ -18,14 +18,18 @@
address of 0 (or 0.0.0.0) then no messages are sent to the network.
The source / listening port can be configured separately by setting
the 'ncinport' environment variable and the destination port can be
-configured by setting the 'ncoutport' environment variable.
+configured by setting the 'ncoutport' environment variable. Note that
+you need to set up the network interface (e.g. using DHCP) before it
+can be used for network console.
-For example, if your server IP is 192.168.1.1, you could use::
+For example, if your server IP is 192.168.1.1, you could use:
- => setenv nc 'setenv stdout nc;setenv stdin nc'
- => setenv ncip 192.168.1.1
- => saveenv
- => run nc
+.. prompt:: bash =>
+
+ env set nc 'env set stdout nc; env set stderr nc; env set stdin nc'
+ env set ncip '192.168.1.1'
+ env save
+ run nc
On the host side, please use this script to access the console
@@ -107,3 +111,34 @@
Note that unlike the U-Boot implementation the Linux netconsole is
unidirectional, i. e. you have console output only in Linux.
+
+Setup via environment
+---------------------
+
+If persistent environment is enabled in your U-Boot configuration, you
+can configure the network console using the environment. For example:
+
+.. prompt:: bash =>
+
+ env set autoload no
+ env set hostname "u-boot"
+ env set bootdelay 5
+ env set nc 'dhcp; env set stdout nc; env set stderr nc; env set stdin nc'
+ env set ncip '192.168.1.1'
+ env set preboot "${preboot}; run nc;"
+ env save
+ reset
+
+``autoload no`` tells the ``dhcp`` command to configure the network
+interface without trying to load an image. ``hostname "u-boot"`` sets
+the hostname to be sent in DHCP requests, so they are easy to
+recognize in the DHCP server log. The command in ``nc`` calls ``dhcp``
+to make sure the network interface is set up before enabling
+netconsole.
+
+Adding ``nc`` to ``preboot`` tells U-Boot to activate netconsole
+before trying to find any boot options, so you can interact with it if
+desired.
+
+``env save`` stores the settings persistently, and ``reset`` then
+triggers a fresh start that will use the changed settings.
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 9bc5283..6cca561 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -61,7 +61,6 @@
config DWC_AHSATA
bool "Enable DWC AHSATA driver support"
select LIBATA
- depends on BLK
help
Enable this driver to support the DWC AHSATA SATA controller found
in i.MX5 and i.MX6 SoCs.
diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig
index 6ad1888..48529a6 100644
--- a/drivers/block/Kconfig
+++ b/drivers/block/Kconfig
@@ -1,8 +1,8 @@
config BLK
bool # "Support block devices"
depends on DM
- default y if MMC || USB || SCSI || NVME || IDE || AHCI || SATA
- default y if EFI_MEDIA || VIRTIO_BLK || PVBLOCK
+ def_bool y if MMC || USB || SCSI || NVME || IDE || AHCI || SATA
+ def_bool y if EFI_MEDIA || VIRTIO_BLK || PVBLOCK
help
Enable support for block devices, such as SCSI, MMC and USB
flash sticks. These provide a block-level interface which permits
diff --git a/drivers/cache/cache-andes-l2.c b/drivers/cache/cache-andes-l2.c
index 7de8f16..45a4f21 100644
--- a/drivers/cache/cache-andes-l2.c
+++ b/drivers/cache/cache-andes-l2.c
@@ -29,7 +29,7 @@
volatile u64 cctl_command2;
volatile u64 cctl_access_line2;
volatile u64 cctl_command3;
- volatile u64 cctl_access_line4;
+ volatile u64 cctl_access_line3;
volatile u64 cctl_status;
};
@@ -96,13 +96,15 @@
struct andes_l2_plat *plat = dev_get_plat(dev);
volatile struct l2cache *regs = plat->regs;
u8 hart = gd->arch.boot_hart;
+
void __iomem *cctlcmd = (void __iomem *)CCTL_CMD_REG(regs, hart);
+ void __iomem *cctlstatus = (void __iomem *)CCTL_STATUS_REG(regs, hart);
if ((regs) && (readl(®s->control) & L2_ENABLE)) {
writel(L2_WBINVAL_ALL, cctlcmd);
- while ((readl(®s->cctl_status) & CCTL_STATUS_MSK(hart))) {
- if ((readl(®s->cctl_status) & CCTL_STATUS_ILLEGAL(hart))) {
+ while ((readl(cctlstatus) & CCTL_STATUS_MSK(hart))) {
+ if ((readl(cctlstatus) & CCTL_STATUS_ILLEGAL(hart))) {
printf("L2 flush illegal! hanging...");
hang();
}
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 39e01c3..62477e1 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -101,8 +101,7 @@
return clk_mux_val_to_index(clk, mux->table, mux->flags, val);
}
-static int clk_fetch_parent_index(struct clk *clk,
- struct clk *parent)
+int clk_mux_fetch_parent_index(struct clk *clk, struct clk *parent)
{
struct clk_mux *mux = to_clk_mux(clk);
@@ -126,7 +125,7 @@
u32 val;
u32 reg;
- index = clk_fetch_parent_index(clk, parent);
+ index = clk_mux_fetch_parent_index(clk, parent);
if (index < 0) {
log_err("Could not fetch index\n");
return index;
diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c
index 45f1bca..64bffa3 100644
--- a/drivers/clk/imx/clk-composite-8m.c
+++ b/drivers/clk/imx/clk-composite-8m.c
@@ -116,6 +116,41 @@
.set_rate = imx8m_clk_composite_divider_set_rate,
};
+static int imx8m_clk_mux_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct clk_mux *mux = to_clk_mux(clk);
+ int index;
+ u32 val;
+ u32 reg;
+
+ index = clk_mux_fetch_parent_index(clk, parent);
+ if (index < 0) {
+ log_err("Could not fetch index\n");
+ return index;
+ }
+
+ val = clk_mux_index_to_val(mux->table, mux->flags, index);
+
+ reg = readl(mux->reg);
+ reg &= ~(mux->mask << mux->shift);
+ val = val << mux->shift;
+ reg |= val;
+
+ /*
+ * write twice to make sure non-target interface
+ * SEL_A/B point the same clk input.
+ */
+ writel(reg, mux->reg);
+ writel(reg, mux->reg);
+
+ return 0;
+}
+
+const struct clk_ops imx8m_clk_mux_ops = {
+ .get_rate = clk_generic_get_rate,
+ .set_parent = imx8m_clk_mux_set_parent,
+};
+
struct clk *imx8m_clk_composite_flags(const char *name,
const char * const *parent_names,
int num_parents, void __iomem *reg,
@@ -134,7 +169,6 @@
mux->shift = PCG_PCS_SHIFT;
mux->mask = PCG_PCS_MASK;
mux->num_parents = num_parents;
- mux->flags = flags;
mux->parent_names = parent_names;
div = kzalloc(sizeof(*div), GFP_KERNEL);
@@ -144,7 +178,7 @@
div->reg = reg;
div->shift = PCG_PREDIV_SHIFT;
div->width = PCG_PREDIV_WIDTH;
- div->flags = CLK_DIVIDER_ROUND_CLOSEST | flags;
+ div->flags = CLK_DIVIDER_ROUND_CLOSEST;
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
if (!gate)
@@ -152,11 +186,10 @@
gate->reg = reg;
gate->bit_idx = PCG_CGC_SHIFT;
- gate->flags = flags;
clk = clk_register_composite(NULL, name,
parent_names, num_parents,
- &mux->clk, &clk_mux_ops, &div->clk,
+ &mux->clk, &imx8m_clk_mux_ops, &div->clk,
&imx8m_clk_composite_divider_ops,
&gate->clk, &clk_gate_ops, flags);
if (IS_ERR(clk))
diff --git a/drivers/clk/imx/clk-composite-93.c b/drivers/clk/imx/clk-composite-93.c
index 2cf20be..61692d3 100644
--- a/drivers/clk/imx/clk-composite-93.c
+++ b/drivers/clk/imx/clk-composite-93.c
@@ -102,7 +102,6 @@
mux->mask = CCM_MUX_MASK;
mux->num_parents = num_parents;
mux->parent_names = parent_names;
- mux->flags = flags;
div = kzalloc(sizeof(*div), GFP_KERNEL);
if (!div)
@@ -119,7 +118,6 @@
gate->reg = reg;
gate->bit_idx = CCM_OFF_SHIFT;
- gate->flags = flags;
clk = clk_register_composite(NULL, name,
parent_names, num_parents,
diff --git a/drivers/clk/mediatek/clk-mt7981.c b/drivers/clk/mediatek/clk-mt7981.c
index 7fcb814..13dc3df 100644
--- a/drivers/clk/mediatek/clk-mt7981.c
+++ b/drivers/clk/mediatek/clk-mt7981.c
@@ -543,6 +543,7 @@
static const struct udevice_id mt7981_fixed_pll_compat[] = {
{ .compatible = "mediatek,mt7981-fixed-plls" },
+ { .compatible = "mediatek,mt7981-apmixedsys" },
{}
};
diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c
index b3fa63f..efc3d41 100644
--- a/drivers/clk/mediatek/clk-mt7986.c
+++ b/drivers/clk/mediatek/clk-mt7986.c
@@ -533,6 +533,7 @@
static const struct udevice_id mt7986_fixed_pll_compat[] = {
{ .compatible = "mediatek,mt7986-fixed-plls" },
+ { .compatible = "mediatek,mt7986-apmixedsys" },
{}
};
diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c
index 34e7b2d..32b0451 100644
--- a/drivers/clk/mediatek/clk-mt7988.c
+++ b/drivers/clk/mediatek/clk-mt7988.c
@@ -833,6 +833,7 @@
static const struct udevice_id mt7988_fixed_pll_compat[] = {
{ .compatible = "mediatek,mt7988-fixed-plls" },
+ { .compatible = "mediatek,mt7988-apmixedsys" },
{}
};
diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c
index 41fe4d8..b5def55 100644
--- a/drivers/clk/qcom/clock-apq8016.c
+++ b/drivers/clk/qcom/clock-apq8016.c
@@ -16,6 +16,8 @@
#include "clock-qcom.h"
+#define USB_HS_SYSTEM_CLK_CMD_RCGR 0x41010
+
/* Clocks: (from CLK_CTL_BASE) */
#define GPLL0_STATUS (0x2101C)
#define APCS_GPLL_ENA_VOTE (0x45000)
@@ -51,6 +53,11 @@
.vote_bit = BIT(10),
};
+static const struct gate_clk apq8016_clks[] = {
+ GATE_CLK(GCC_USB_HS_AHB_CLK, 0x41008, 0x00000001),
+ GATE_CLK(GCC_USB_HS_SYSTEM_CLK, 0x41004, 0x00000001),
+};
+
/* SDHCI */
static int apq8016_clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate)
{
@@ -116,13 +123,38 @@
case GCC_BLSP1_UART2_APPS_CLK: /* UART2 */
apq8016_clk_init_uart(priv->base, clk->id);
return 7372800;
+ case GCC_USB_HS_SYSTEM_CLK:
+ if (rate != 80000000)
+ log_warning("Unexpected rate %ld requested for USB_HS_SYSTEM_CLK\n",
+ rate);
+ clk_rcg_set_rate_mnd(priv->base, USB_HS_SYSTEM_CLK_CMD_RCGR,
+ 10, 0, 0, CFG_CLK_SRC_GPLL0, 0);
+ return rate;
default:
return 0;
}
}
+static int apq8016_clk_enable(struct clk *clk)
+{
+ struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+
+ if (priv->data->num_clks < clk->id) {
+ log_warning("%s: unknown clk id %lu\n", __func__, clk->id);
+ return 0;
+ }
+
+ debug("%s: clk %s\n", __func__, apq8016_clks[clk->id].name);
+ qcom_gate_clk_en(priv, clk->id);
+
+ return 0;
+}
+
static struct msm_clk_data apq8016_clk_data = {
.set_rate = apq8016_clk_set_rate,
+ .clks = apq8016_clks,
+ .num_clks = ARRAY_SIZE(apq8016_clks),
+ .enable = apq8016_clk_enable,
};
static const struct udevice_id gcc_apq8016_of_match[] = {
diff --git a/drivers/clk/qcom/clock-ipq4019.c b/drivers/clk/qcom/clock-ipq4019.c
index 0e6d93b..9352ff4 100644
--- a/drivers/clk/qcom/clock-ipq4019.c
+++ b/drivers/clk/qcom/clock-ipq4019.c
@@ -15,6 +15,12 @@
#include "clock-qcom.h"
+/* I2C controller clock control registerss */
+#define BLSP1_QUP1_I2C_APPS_CBCR (0x2008)
+#define BLSP1_QUP1_I2C_APPS_CMD_RCGR (0x200C)
+#define BLSP1_QUP2_I2C_APPS_CBCR (0x3010)
+#define BLSP1_QUP2_I2C_APPS_CMD_RCGR (0x3000)
+
static ulong ipq4019_clk_set_rate(struct clk *clk, ulong rate)
{
switch (clk->id) {
@@ -28,7 +34,22 @@
static int ipq4019_clk_enable(struct clk *clk)
{
+ struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+
switch (clk->id) {
+ case GCC_BLSP1_AHB_CLK:
+ /* This clock is already initialized by SBL1 */
+ return 0;
+ case GCC_BLSP1_QUP1_I2C_APPS_CLK:
+ clk_enable_cbc(priv->base + BLSP1_QUP1_I2C_APPS_CBCR);
+ clk_rcg_set_rate(priv->base, BLSP1_QUP1_I2C_APPS_CMD_RCGR, 0,
+ CFG_CLK_SRC_CXO);
+ return 0;
+ case GCC_BLSP1_QUP2_I2C_APPS_CLK:
+ clk_enable_cbc(priv->base + BLSP1_QUP2_I2C_APPS_CBCR);
+ clk_rcg_set_rate(priv->base, BLSP1_QUP2_I2C_APPS_CMD_RCGR, 0,
+ CFG_CLK_SRC_CXO);
+ return 0;
case GCC_BLSP1_QUP1_SPI_APPS_CLK: /*SPI1*/
/* This clock is already initialized by SBL1 */
return 0;
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index e511f74..4225036 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -77,6 +77,7 @@
/* Core Clock Outputs */
DEF_GEN3_Z("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
DEF_GEN3_Z("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
+ DEF_GEN3_Z("zg", R8A7795_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24),
DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@@ -126,6 +127,7 @@
};
static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
+ DEF_MOD("3dge", 112, R8A7795_CLK_ZG),
DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1),
DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1),
DEF_MOD("tmu4", 121, R8A7795_CLK_S0D6),
@@ -249,6 +251,7 @@
DEF_MOD("rpc-if", 917, R8A7795_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A7795_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A7795_CLK_S0D6),
+ DEF_MOD("adg", 922, R8A7795_CLK_S0D4),
DEF_MOD("i2c-dvfs", 926, R8A7795_CLK_CP),
DEF_MOD("i2c4", 927, R8A7795_CLK_S0D6),
DEF_MOD("i2c3", 928, R8A7795_CLK_S0D6),
diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
index ba086be..b44d560 100644
--- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -133,7 +133,7 @@
DEF_MOD("avb3", 214, R8A779A0_CLK_S3D2),
DEF_MOD("avb4", 215, R8A779A0_CLK_S3D2),
DEF_MOD("avb5", 216, R8A779A0_CLK_S3D2),
- DEF_MOD("canfd0", 328, R8A779A0_CLK_CANFD),
+ DEF_MOD("canfd0", 328, R8A779A0_CLK_S3D2),
DEF_MOD("csi40", 331, R8A779A0_CLK_CSI0),
DEF_MOD("csi41", 400, R8A779A0_CLK_CSI0),
DEF_MOD("csi42", 401, R8A779A0_CLK_CSI0),
diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
index 108655f..ea98bc6 100644
--- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
@@ -156,7 +156,7 @@
DEF_MOD("cmt1", 911, R8A779F0_CLK_R),
DEF_MOD("cmt2", 912, R8A779F0_CLK_R),
DEF_MOD("cmt3", 913, R8A779F0_CLK_R),
- DEF_MOD("pfc0", 915, R8A779F0_CLK_CL16M),
+ DEF_MOD("pfc0", 915, R8A779F0_CLK_CPEX),
DEF_MOD("tsc", 919, R8A779F0_CLK_CL16M),
DEF_MOD("rswitch2", 1505, R8A779F0_CLK_RSW2),
DEF_MOD("ether-serdes", 1506, R8A779F0_CLK_S0D2_HSC),
diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
index 781806e..4df0a69 100644
--- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -17,7 +17,7 @@
enum clk_ids {
/* Core Clock Outputs exported to DT */
- LAST_DT_CORE_CLK = R8A779G0_CLK_R,
+ LAST_DT_CORE_CLK = R8A779G0_CLK_CP,
/* External Input Clocks */
CLK_EXTAL,
@@ -136,6 +136,7 @@
DEF_FIXED("svd2_vip", R8A779G0_CLK_SVD2_VIP, CLK_SV_VIP, 2, 1),
DEF_FIXED("cbfusa", R8A779G0_CLK_CBFUSA, CLK_EXTAL, 2, 1),
DEF_FIXED("cpex", R8A779G0_CLK_CPEX, CLK_EXTAL, 2, 1),
+ DEF_FIXED("cp", R8A779G0_CLK_CP, CLK_EXTAL, 2, 1),
DEF_FIXED("viobus", R8A779G0_CLK_VIOBUS, CLK_VIO, 1, 1),
DEF_FIXED("viobusd2", R8A779G0_CLK_VIOBUSD2, CLK_VIO, 2, 1),
DEF_FIXED("vcbus", R8A779G0_CLK_VCBUS, CLK_VC, 1, 1),
@@ -187,6 +188,8 @@
DEF_MOD("msi3", 621, R8A779G0_CLK_MSO),
DEF_MOD("msi4", 622, R8A779G0_CLK_MSO),
DEF_MOD("msi5", 623, R8A779G0_CLK_MSO),
+ DEF_MOD("pciec0", 624, R8A779G0_CLK_S0D2_HSC),
+ DEF_MOD("pciec1", 625, R8A779G0_CLK_S0D2_HSC),
DEF_MOD("pwm", 628, R8A779G0_CLK_SASYNCPERD4),
DEF_MOD("rpc-if", 629, R8A779G0_CLK_RPCD2),
DEF_MOD("scif0", 702, R8A779G0_CLK_SASYNCPERD4),
@@ -225,11 +228,12 @@
DEF_MOD("cmt1", 911, R8A779G0_CLK_R),
DEF_MOD("cmt2", 912, R8A779G0_CLK_R),
DEF_MOD("cmt3", 913, R8A779G0_CLK_R),
- DEF_MOD("pfc0", 915, R8A779G0_CLK_CL16M),
- DEF_MOD("pfc1", 916, R8A779G0_CLK_CL16M),
- DEF_MOD("pfc2", 917, R8A779G0_CLK_CL16M),
- DEF_MOD("pfc3", 918, R8A779G0_CLK_CL16M),
+ DEF_MOD("pfc0", 915, R8A779G0_CLK_CP),
+ DEF_MOD("pfc1", 916, R8A779G0_CLK_CP),
+ DEF_MOD("pfc2", 917, R8A779G0_CLK_CP),
+ DEF_MOD("pfc3", 918, R8A779G0_CLK_CP),
DEF_MOD("tsc", 919, R8A779G0_CLK_CL16M),
+ DEF_MOD("tsn", 2723, R8A779G0_CLK_S0D4_HSC),
DEF_MOD("ssiu", 2926, R8A779G0_CLK_S0D6_PER),
DEF_MOD("ssi", 2927, R8A779G0_CLK_S0D6_PER),
};
diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
index 502b20b..b20d559 100644
--- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
@@ -172,9 +172,9 @@
};
static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
- DEF_MOD("avb0-rgmii0", 211, R8A779H0_CLK_S0D8_HSC),
- DEF_MOD("avb1-rgmii1", 212, R8A779H0_CLK_S0D8_HSC),
- DEF_MOD("avb2-rgmii2", 213, R8A779H0_CLK_S0D8_HSC),
+ DEF_MOD("avb0:rgmii0", 211, R8A779H0_CLK_S0D8_HSC),
+ DEF_MOD("avb1:rgmii1", 212, R8A779H0_CLK_S0D8_HSC),
+ DEF_MOD("avb2:rgmii2", 213, R8A779H0_CLK_S0D8_HSC),
DEF_MOD("hscif0", 514, R8A779H0_CLK_SASYNCPERD1),
DEF_MOD("hscif1", 515, R8A779H0_CLK_SASYNCPERD1),
DEF_MOD("hscif2", 516, R8A779H0_CLK_SASYNCPERD1),
@@ -185,9 +185,12 @@
DEF_MOD("i2c3", 521, R8A779H0_CLK_S0D6_PER),
DEF_MOD("rpc-if", 629, R8A779H0_CLK_RPCD2),
DEF_MOD("sdhi0", 706, R8A779H0_CLK_SD0),
- DEF_MOD("pfc0", 915, R8A779H0_CLK_CL16M),
- DEF_MOD("pfc1", 916, R8A779H0_CLK_CL16M),
- DEF_MOD("pfc2", 917, R8A779H0_CLK_CL16M),
+ DEF_MOD("sydm1", 709, R8A779H0_CLK_S0D6_PER),
+ DEF_MOD("sydm2", 710, R8A779H0_CLK_S0D6_PER),
+ DEF_MOD("wdt1:wdt0", 907, R8A779H0_CLK_R),
+ DEF_MOD("pfc0", 915, R8A779H0_CLK_CP),
+ DEF_MOD("pfc1", 916, R8A779H0_CLK_CP),
+ DEF_MOD("pfc2", 917, R8A779H0_CLK_CP),
};
/*
diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c
index ceae08a..db1384d 100644
--- a/drivers/clk/rockchip/clk_rk3588.c
+++ b/drivers/clk/rockchip/clk_rk3588.c
@@ -36,6 +36,7 @@
RK3588_PLL_RATE(786000000, 1, 131, 2, 0),
RK3588_PLL_RATE(742500000, 4, 495, 2, 0),
RK3588_PLL_RATE(722534400, 8, 963, 2, 24850),
+ RK3588_PLL_RATE(702000000, 3, 351, 2, 0),
RK3588_PLL_RATE(600000000, 2, 200, 2, 0),
RK3588_PLL_RATE(594000000, 2, 198, 2, 0),
RK3588_PLL_RATE(200000000, 3, 400, 4, 0),
@@ -64,6 +65,15 @@
RK3588_MODE_CON0, 0, 15, 0, rk3588_pll_rates),
[PPLL] = PLL(pll_rk3588, PLL_PPLL, RK3588_PMU_PLL_CON(128),
RK3588_MODE_CON0, 10, 15, 0, rk3588_pll_rates),
+#ifdef CONFIG_SPL_BUILD
+ /*
+ * The SPLL is part of the SBUSCRU, not the main CRU and as
+ * such only directly accessible during the SPL stage.
+ */
+ [SPLL] = PLL(pll_rk3588, 0, RK3588_SBUSCRU_SPLL_CON(0),
+ RK3588_SBUSCRU_MODE_CON0, 0, 15, 0, rk3588_pll_rates),
+#endif
+
};
#ifndef CONFIG_SPL_BUILD
@@ -2043,6 +2053,7 @@
#ifdef CONFIG_SPL_BUILD
#define SCRU_BASE 0xfd7d0000
+#define SBUSCRU_BASE 0xfd7d8000
static ulong rk3588_scru_clk_get_rate(struct clk *clk)
{
@@ -2117,15 +2128,28 @@
return rk3588_scru_clk_get_rate(clk);
}
+static int rk3588_scru_clk_probe(struct udevice *dev)
+{
+ int ret;
+
+ ret = rockchip_pll_set_rate(&rk3588_pll_clks[SPLL],
+ (void *)SBUSCRU_BASE, SPLL, SPLL_HZ);
+ if (ret)
+ debug("%s setting spll rate failed %d\n", __func__, ret);
+
+ return 0;
+}
+
static const struct clk_ops rk3588_scru_clk_ops = {
.get_rate = rk3588_scru_clk_get_rate,
.set_rate = rk3588_scru_clk_set_rate,
};
U_BOOT_DRIVER(rockchip_rk3588_scru) = {
- .name = "rockchip_rk3588_scru",
- .id = UCLASS_CLK,
- .ops = &rk3588_scru_clk_ops,
+ .name = "rockchip_rk3588_scru",
+ .id = UCLASS_CLK,
+ .ops = &rk3588_scru_clk_ops,
+ .probe = rk3588_scru_clk_probe,
};
static int rk3588_scmi_spl_glue_bind(struct udevice *dev)
diff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c
index 41e5022..bf65f57 100644
--- a/drivers/clk/ti/clk-k3.c
+++ b/drivers/clk/ti/clk-k3.c
@@ -59,6 +59,24 @@
}
static const struct soc_attr ti_k3_soc_clk_data[] = {
+#if IS_ENABLED(CONFIG_SOC_K3_AM625)
+ {
+ .family = "AM62X",
+ .data = &am62x_clk_platdata,
+ },
+#endif
+#if IS_ENABLED(CONFIG_SOC_K3_AM62A7)
+ {
+ .family = "AM62AX",
+ .data = &am62ax_clk_platdata,
+ },
+#endif
+#if IS_ENABLED(CONFIG_SOC_K3_AM62P5)
+ {
+ .family = "AM62PX",
+ .data = &am62px_clk_platdata,
+ },
+#endif
#if IS_ENABLED(CONFIG_SOC_K3_J721E)
{
.family = "J721E",
@@ -68,36 +86,25 @@
.family = "J7200",
.data = &j7200_clk_platdata,
},
-#elif CONFIG_SOC_K3_J721S2
+#endif
+#if IS_ENABLED(CONFIG_SOC_K3_J721S2)
{
.family = "J721S2",
.data = &j721s2_clk_platdata,
},
#endif
-#ifdef CONFIG_SOC_K3_AM625
- {
- .family = "AM62X",
- .data = &am62x_clk_platdata,
- },
-#endif
-#ifdef CONFIG_SOC_K3_AM62A7
+#if IS_ENABLED(CONFIG_SOC_K3_J722S)
{
- .family = "AM62AX",
- .data = &am62ax_clk_platdata,
+ .family = "J722S",
+ .data = &j722s_clk_platdata,
},
#endif
-#ifdef CONFIG_SOC_K3_J784S4
+#if IS_ENABLED(CONFIG_SOC_K3_J784S4)
{
.family = "J784S4",
.data = &j784s4_clk_platdata,
},
#endif
-#ifdef CONFIG_SOC_K3_AM62P5
- {
- .family = "AM62PX",
- .data = &am62px_clk_platdata,
- },
-#endif
{ /* sentinel */ }
};
diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index 1081d61..1a7be4d 100644
--- a/drivers/core/Kconfig
+++ b/drivers/core/Kconfig
@@ -56,7 +56,7 @@
out - it will do nothing when called.
config SPL_DM_WARN
- bool "Enable warnings in driver model wuth SPL"
+ bool "Enable warnings in driver model in SPL"
depends on SPL_DM
help
Enable this to see warnings related to driver model in SPL
@@ -113,7 +113,7 @@
select EVENT
help
This enables support for generating events related to driver model
- operations, such as prbing or removing a device. Subsystems can
+ operations, such as probing or removing a device. Subsystems can
register a 'spy' function that is called when the event occurs. Such
subsystems must select this option.
diff --git a/drivers/core/device.c b/drivers/core/device.c
index 18e2bd0..779f371 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -58,7 +58,7 @@
ret = uclass_get(drv->id, &uc);
if (ret) {
- debug("Missing uclass for driver %s\n", drv->name);
+ dm_warn("Missing uclass for driver %s\n", drv->name);
return ret;
}
diff --git a/drivers/core/fdtaddr.c b/drivers/core/fdtaddr.c
index 6be8ea0..9e59968 100644
--- a/drivers/core/fdtaddr.c
+++ b/drivers/core/fdtaddr.c
@@ -15,6 +15,7 @@
#include <asm/global_data.h>
#include <asm/io.h>
#include <dm/device-internal.h>
+#include <dm/util.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -32,19 +33,19 @@
na = fdt_address_cells(gd->fdt_blob, parent);
if (na < 1) {
- debug("bad #address-cells\n");
+ dm_warn("bad #address-cells\n");
return FDT_ADDR_T_NONE;
}
ns = fdt_size_cells(gd->fdt_blob, parent);
if (ns < 0) {
- debug("bad #size-cells\n");
+ dm_warn("bad #size-cells\n");
return FDT_ADDR_T_NONE;
}
reg = fdt_getprop(gd->fdt_blob, offset, "reg", &len);
if (!reg || (len <= (index * sizeof(fdt32_t) * (na + ns)))) {
- debug("Req index out of range\n");
+ dm_warn("Req index out of range\n");
return FDT_ADDR_T_NONE;
}
diff --git a/drivers/core/lists.c b/drivers/core/lists.c
index 2839a9b..c7be504 100644
--- a/drivers/core/lists.c
+++ b/drivers/core/lists.c
@@ -8,6 +8,7 @@
#define LOG_CATEGORY LOGC_DM
+#include <debug_uart.h>
#include <errno.h>
#include <log.h>
#include <dm/device.h>
@@ -50,6 +51,21 @@
return NULL;
}
+/**
+ * bind_drivers_pass() - Perform a pass of driver binding
+ *
+ * Work through the driver_info records binding a driver for each one. If the
+ * binding fails, continue binding others, but return the error.
+ *
+ * For OF_PLATDATA we must bind parent devices before their children. So only
+ * children of bound parents are bound on each call to this function. When a
+ * child is left unbound, -EAGAIN is returned, indicating that this function
+ * should be called again
+ *
+ * @parent: Parent device to use when binding each child device
+ * Return: 0 if OK, -EAGAIN if unbound children exist, -ENOENT if there is no
+ * driver for one of the devices, other -ve on other error
+ */
static int bind_drivers_pass(struct udevice *parent, bool pre_reloc_only)
{
struct driver_info *info =
@@ -144,7 +160,7 @@
drv = lists_driver_lookup_name(drv_name);
if (!drv) {
- debug("Cannot find driver '%s'\n", drv_name);
+ dm_warn("Cannot find driver '%s'\n", drv_name);
return -ENOENT;
}
ret = device_bind_with_driver_data(parent, drv, dev_name, 0 /* data */,
@@ -246,9 +262,8 @@
}
if (entry->of_match)
- log_debug(" - found match at '%s': '%s' matches '%s'\n",
- entry->name, entry->of_match->compatible,
- id->compatible);
+ log_debug(" - found match at driver '%s' for '%s'\n",
+ entry->name, id->compatible);
ret = device_bind_with_driver_data(parent, entry, name,
id ? id->data : 0, node,
&dev);
diff --git a/drivers/core/of_access.c b/drivers/core/of_access.c
index 41f2e09..d05be27 100644
--- a/drivers/core/of_access.c
+++ b/drivers/core/of_access.c
@@ -25,6 +25,7 @@
#include <linux/bug.h>
#include <linux/libfdt.h>
#include <dm/of_access.h>
+#include <dm/util.h>
#include <linux/ctype.h>
#include <linux/err.h>
#include <linux/ioport.h>
@@ -489,17 +490,17 @@
{
const u8 *val;
- debug("%s: %s: ", __func__, propname);
+ dm_warn("%s: %s: ", __func__, propname);
if (!np)
return -EINVAL;
val = of_find_property_value_of_size(np, propname, sizeof(*outp));
if (IS_ERR(val)) {
- debug("(not found)\n");
+ dm_warn("(not found)\n");
return PTR_ERR(val);
}
*outp = *val;
- debug("%#x (%d)\n", *outp, *outp);
+ dm_warn("%#x (%d)\n", *outp, *outp);
return 0;
}
@@ -508,17 +509,17 @@
{
const __be16 *val;
- debug("%s: %s: ", __func__, propname);
+ dm_warn("%s: %s: ", __func__, propname);
if (!np)
return -EINVAL;
val = of_find_property_value_of_size(np, propname, sizeof(*outp));
if (IS_ERR(val)) {
- debug("(not found)\n");
+ dm_warn("(not found)\n");
return PTR_ERR(val);
}
*outp = be16_to_cpup(val);
- debug("%#x (%d)\n", *outp, *outp);
+ dm_warn("%#x (%d)\n", *outp, *outp);
return 0;
}
@@ -533,14 +534,14 @@
{
const __be32 *val;
- debug("%s: %s: ", __func__, propname);
+ dm_warn("%s: %s: ", __func__, propname);
val = of_find_property_value_of_size(np, propname,
sz * sizeof(*out_values));
if (IS_ERR(val))
return PTR_ERR(val);
- debug("size %zd\n", sz);
+ dm_warn("size %zd\n", sz);
while (sz--)
*out_values++ = be32_to_cpup(val++);
@@ -552,19 +553,19 @@
{
const __be32 *val;
- debug("%s: %s: ", __func__, propname);
+ dm_warn("%s: %s: ", __func__, propname);
if (!np)
return -EINVAL;
val = of_find_property_value_of_size(np, propname,
sizeof(*outp) * (index + 1));
if (IS_ERR(val)) {
- debug("(not found)\n");
+ dm_warn("(not found)\n");
return PTR_ERR(val);
}
*outp = be32_to_cpup(val + index);
- debug("%#x (%d)\n", *outp, *outp);
+ dm_warn("%#x (%d)\n", *outp, *outp);
return 0;
}
@@ -574,20 +575,20 @@
{
const __be64 *val;
- debug("%s: %s: ", __func__, propname);
+ dm_warn("%s: %s: ", __func__, propname);
if (!np)
return -EINVAL;
val = of_find_property_value_of_size(np, propname,
sizeof(*outp) * (index + 1));
if (IS_ERR(val)) {
- debug("(not found)\n");
+ dm_warn("(not found)\n");
return PTR_ERR(val);
}
*outp = be64_to_cpup(val + index);
- debug("%#llx (%lld)\n", (unsigned long long)*outp,
- (unsigned long long)*outp);
+ dm_warn("%#llx (%lld)\n", (unsigned long long)*outp,
+ (unsigned long long)*outp);
return 0;
}
@@ -620,7 +621,7 @@
l = strnlen(p, end - p) + 1;
if (p + l > end)
return -EILSEQ;
- debug("comparing %s with %s\n", string, p);
+ dm_warn("comparing %s with %s\n", string, p);
if (strcmp(string, p) == 0)
return i; /* Found it; return index */
}
@@ -707,17 +708,17 @@
if (cells_name || cur_index == index) {
node = of_find_node_by_phandle(NULL, phandle);
if (!node) {
- debug("%s: could not find phandle\n",
- np->full_name);
+ dm_warn("%s: could not find phandle\n",
+ np->full_name);
goto err;
}
}
if (cells_name) {
if (of_read_u32(node, cells_name, &count)) {
- debug("%s: could not get %s for %s\n",
- np->full_name, cells_name,
- node->full_name);
+ dm_warn("%s: could not get %s for %s\n",
+ np->full_name, cells_name,
+ node->full_name);
goto err;
}
} else {
@@ -729,8 +730,8 @@
* remaining property data length
*/
if (list + count > list_end) {
- debug("%s: arguments longer than property\n",
- np->full_name);
+ dm_warn("%s: arguments longer than property\n",
+ np->full_name);
goto err;
}
}
@@ -825,8 +826,8 @@
strncpy(ap->stem, stem, stem_len);
ap->stem[stem_len] = 0;
list_add_tail(&ap->link, &aliases_lookup);
- debug("adding DT alias:%s: stem=%s id=%i node=%s\n",
- ap->alias, ap->stem, ap->id, of_node_full_name(np));
+ dm_warn("adding DT alias:%s: stem=%s id=%i node=%s\n",
+ ap->alias, ap->stem, ap->id, of_node_full_name(np));
}
int of_alias_scan(void)
diff --git a/drivers/core/of_addr.c b/drivers/core/of_addr.c
index d7913ab..c893447 100644
--- a/drivers/core/of_addr.c
+++ b/drivers/core/of_addr.c
@@ -11,6 +11,7 @@
#include <linux/libfdt.h>
#include <dm/of_access.h>
#include <dm/of_addr.h>
+#include <dm/util.h>
#include <linux/err.h>
#include <linux/ioport.h>
#include <linux/printk.h>
@@ -26,7 +27,7 @@
#ifdef DEBUG
static void of_dump_addr(const char *s, const __be32 *addr, int na)
{
- debug("%s", s);
+ dm_warn("%s", s);
while (na--)
pr_cont(" %08x", be32_to_cpu(*(addr++)));
pr_cont("\n");
@@ -65,9 +66,9 @@
s = of_read_number(range + na + pna, ns);
da = of_read_number(addr, na);
- debug("default map, cp=%llx, s=%llx, da=%llx\n",
- (unsigned long long)cp, (unsigned long long)s,
- (unsigned long long)da);
+ dm_warn("default map, cp=%llx, s=%llx, da=%llx\n",
+ (unsigned long long)cp, (unsigned long long)s,
+ (unsigned long long)da);
if (da < cp || da >= (cp + s))
return OF_BAD_ADDR;
@@ -193,17 +194,17 @@
ranges = of_get_property(parent, rprop, &rlen);
if (ranges == NULL && !of_empty_ranges_quirk(parent) &&
strcmp(rprop, "dma-ranges")) {
- debug("no ranges; cannot translate\n");
+ dm_warn("no ranges; cannot translate\n");
return 1;
}
if (ranges == NULL || rlen == 0) {
offset = of_read_number(addr, na);
memset(addr, 0, pna * 4);
- debug("empty ranges; 1:1 translation\n");
+ dm_warn("empty ranges; 1:1 translation\n");
goto finish;
}
- debug("walking ranges...\n");
+ dm_warn("walking ranges...\n");
/* Now walk through the ranges */
rlen /= 4;
@@ -214,14 +215,14 @@
break;
}
if (offset == OF_BAD_ADDR) {
- debug("not found !\n");
+ dm_warn("not found !\n");
return 1;
}
memcpy(addr, ranges + na, 4 * pna);
finish:
of_dump_addr("parent translation for:", addr, pna);
- debug("with offset: %llx\n", (unsigned long long)offset);
+ dm_warn("with offset: %llx\n", (unsigned long long)offset);
/* Translate it into parent bus space */
return pbus->translate(addr, offset, pna);
@@ -246,7 +247,7 @@
int na, ns, pna, pns;
u64 result = OF_BAD_ADDR;
- debug("** translation for device %s **\n", of_node_full_name(dev));
+ dm_warn("** translation for device %s **\n", of_node_full_name(dev));
/* Increase refcount at current level */
(void)of_node_get(dev);
@@ -260,13 +261,13 @@
/* Count address cells & copy address locally */
bus->count_cells(dev, &na, &ns);
if (!OF_CHECK_COUNTS(na, ns)) {
- debug("Bad cell count for %s\n", of_node_full_name(dev));
+ dm_warn("Bad cell count for %s\n", of_node_full_name(dev));
goto bail;
}
memcpy(addr, in_addr, na * 4);
- debug("bus is %s (na=%d, ns=%d) on %s\n", bus->name, na, ns,
- of_node_full_name(parent));
+ dm_warn("bus is %s (na=%d, ns=%d) on %s\n", bus->name, na, ns,
+ of_node_full_name(parent));
of_dump_addr("translating address:", addr, na);
/* Translate */
@@ -278,7 +279,7 @@
/* If root, we have finished */
if (parent == NULL) {
- debug("reached root node\n");
+ dm_warn("reached root node\n");
result = of_read_number(addr, na);
break;
}
@@ -287,13 +288,13 @@
pbus = of_match_bus(parent);
pbus->count_cells(dev, &pna, &pns);
if (!OF_CHECK_COUNTS(pna, pns)) {
- debug("Bad cell count for %s\n",
- of_node_full_name(dev));
+ dm_warn("Bad cell count for %s\n",
+ of_node_full_name(dev));
break;
}
- debug("parent bus is %s (na=%d, ns=%d) on %s\n", pbus->name,
- pna, pns, of_node_full_name(parent));
+ dm_warn("parent bus is %s (na=%d, ns=%d) on %s\n", pbus->name,
+ pna, pns, of_node_full_name(parent));
/* Apply bus translation */
if (of_translate_one(dev, bus, pbus, addr, na, ns, pna, rprop))
@@ -358,8 +359,8 @@
}
if (!dev || !ranges) {
- debug("no dma-ranges found for node %s\n",
- of_node_full_name(dev));
+ dm_warn("no dma-ranges found for node %s\n",
+ of_node_full_name(dev));
ret = -ENOENT;
goto out;
}
diff --git a/drivers/core/of_extra.c b/drivers/core/of_extra.c
index a3ebe9e..bfc1e34 100644
--- a/drivers/core/of_extra.c
+++ b/drivers/core/of_extra.c
@@ -9,6 +9,7 @@
#include <dm/of_access.h>
#include <dm/of_extra.h>
#include <dm/ofnode.h>
+#include <dm/util.h>
int ofnode_read_fmap_entry(ofnode node, struct fmap_entry *entry)
{
@@ -16,13 +17,13 @@
ofnode subnode;
if (ofnode_read_u32(node, "image-pos", &entry->offset)) {
- debug("Node '%s' has bad/missing 'image-pos' property\n",
- ofnode_get_name(node));
+ dm_warn("Node '%s' has bad/missing 'image-pos' property\n",
+ ofnode_get_name(node));
return log_msg_ret("image-pos", -ENOENT);
}
if (ofnode_read_u32(node, "size", &entry->length)) {
- debug("Node '%s' has bad/missing 'size' property\n",
- ofnode_get_name(node));
+ dm_warn("Node '%s' has bad/missing 'size' property\n",
+ ofnode_get_name(node));
return log_msg_ret("size", -ENOENT);
}
entry->used = ofnode_read_s32_default(node, "used", entry->length);
@@ -57,17 +58,17 @@
const fdt_addr_t *cell;
int len;
- debug("%s: %s: %s\n", __func__, ofnode_get_name(node), prop_name);
+ dm_warn("%s: %s: %s\n", __func__, ofnode_get_name(node), prop_name);
cell = ofnode_get_property(node, prop_name, &len);
if (!cell || (len < sizeof(fdt_addr_t) * 2)) {
- debug("cell=%p, len=%d\n", cell, len);
+ dm_warn("cell=%p, len=%d\n", cell, len);
return -1;
}
*basep = fdt_addr_to_cpu(*cell);
*sizep = fdt_size_to_cpu(cell[1]);
- debug("%s: base=%08lx, size=%lx\n", __func__, (ulong)*basep,
- (ulong)*sizep);
+ dm_warn("%s: base=%08lx, size=%lx\n", __func__, (ulong)*basep,
+ (ulong)*sizep);
return 0;
}
@@ -85,7 +86,7 @@
if (!ofnode_valid(config_node)) {
config_node = ofnode_path("/config");
if (!ofnode_valid(config_node)) {
- debug("%s: Cannot find /config node\n", __func__);
+ dm_warn("%s: Cannot find /config node\n", __func__);
return -ENOENT;
}
}
@@ -96,14 +97,14 @@
suffix);
mem = ofnode_read_string(config_node, prop_name);
if (!mem) {
- debug("%s: No memory type for '%s', using /memory\n", __func__,
- prop_name);
+ dm_warn("%s: No memory type for '%s', using /memory\n", __func__,
+ prop_name);
mem = "/memory";
}
node = ofnode_path(mem);
if (!ofnode_valid(node)) {
- debug("%s: Failed to find node '%s'\n", __func__, mem);
+ dm_warn("%s: Failed to find node '%s'\n", __func__, mem);
return -ENOENT;
}
@@ -112,8 +113,8 @@
* use the first
*/
if (ofnode_decode_region(node, "reg", &base, &size)) {
- debug("%s: Failed to decode memory region %s\n", __func__,
- mem);
+ dm_warn("%s: Failed to decode memory region %s\n", __func__,
+ mem);
return -EINVAL;
}
@@ -121,8 +122,8 @@
suffix);
if (ofnode_decode_region(config_node, prop_name, &offset,
&offset_size)) {
- debug("%s: Failed to decode memory region '%s'\n", __func__,
- prop_name);
+ dm_warn("%s: Failed to decode memory region '%s'\n", __func__,
+ prop_name);
return -EINVAL;
}
diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c
index 9a5eaaa..4d563b4 100644
--- a/drivers/core/ofnode.c
+++ b/drivers/core/ofnode.c
@@ -16,6 +16,7 @@
#include <dm/of_access.h>
#include <dm/of_addr.h>
#include <dm/ofnode.h>
+#include <dm/util.h>
#include <linux/err.h>
#include <linux/ioport.h>
#include <asm/global_data.h>
@@ -314,7 +315,7 @@
int len;
assert(ofnode_valid(node));
- debug("%s: %s: ", __func__, propname);
+ dm_warn("%s: %s: ", __func__, propname);
if (ofnode_is_np(node))
return of_read_u8(ofnode_to_np(node), propname, outp);
@@ -322,11 +323,11 @@
cell = fdt_getprop(gd->fdt_blob, ofnode_to_offset(node), propname,
&len);
if (!cell || len < sizeof(*cell)) {
- debug("(not found)\n");
+ dm_warn("(not found)\n");
return -EINVAL;
}
*outp = *cell;
- debug("%#x (%d)\n", *outp, *outp);
+ dm_warn("%#x (%u)\n", *outp, *outp);
return 0;
}
@@ -345,7 +346,7 @@
int len;
assert(ofnode_valid(node));
- debug("%s: %s: ", __func__, propname);
+ dm_warn("%s: %s: ", __func__, propname);
if (ofnode_is_np(node))
return of_read_u16(ofnode_to_np(node), propname, outp);
@@ -353,11 +354,11 @@
cell = fdt_getprop(gd->fdt_blob, ofnode_to_offset(node), propname,
&len);
if (!cell || len < sizeof(*cell)) {
- debug("(not found)\n");
+ dm_warn("(not found)\n");
return -EINVAL;
}
*outp = be16_to_cpup(cell);
- debug("%#x (%d)\n", *outp, *outp);
+ dm_warn("%#x (%u)\n", *outp, *outp);
return 0;
}
@@ -390,7 +391,7 @@
int len;
assert(ofnode_valid(node));
- debug("%s: %s: ", __func__, propname);
+ dm_warn("%s: %s: ", __func__, propname);
if (ofnode_is_np(node))
return of_read_u32_index(ofnode_to_np(node), propname, index,
@@ -399,17 +400,17 @@
cell = fdt_getprop(ofnode_to_fdt(node), ofnode_to_offset(node),
propname, &len);
if (!cell) {
- debug("(not found)\n");
+ dm_warn("(not found)\n");
return -EINVAL;
}
if (len < (sizeof(int) * (index + 1))) {
- debug("(not large enough)\n");
+ dm_warn("(not large enough)\n");
return -EOVERFLOW;
}
*outp = fdt32_to_cpu(cell[index]);
- debug("%#x (%d)\n", *outp, *outp);
+ dm_warn("%#x (%u)\n", *outp, *outp);
return 0;
}
@@ -429,17 +430,17 @@
cell = fdt_getprop(ofnode_to_fdt(node), ofnode_to_offset(node),
propname, &len);
if (!cell) {
- debug("(not found)\n");
+ dm_warn("(not found)\n");
return -EINVAL;
}
if (len < (sizeof(u64) * (index + 1))) {
- debug("(not large enough)\n");
+ dm_warn("(not large enough)\n");
return -EOVERFLOW;
}
*outp = fdt64_to_cpu(cell[index]);
- debug("%#llx (%lld)\n", *outp, *outp);
+ dm_warn("%#llx (%llu)\n", *outp, *outp);
return 0;
}
@@ -467,7 +468,7 @@
int len;
assert(ofnode_valid(node));
- debug("%s: %s: ", __func__, propname);
+ dm_warn("%s: %s: ", __func__, propname);
if (ofnode_is_np(node))
return of_read_u64(ofnode_to_np(node), propname, outp);
@@ -475,12 +476,12 @@
cell = fdt_getprop(ofnode_to_fdt(node), ofnode_to_offset(node),
propname, &len);
if (!cell || len < sizeof(*cell)) {
- debug("(not found)\n");
+ dm_warn("(not found)\n");
return -EINVAL;
}
*outp = fdt64_to_cpu(cell[0]);
- debug("%#llx (%lld)\n", (unsigned long long)*outp,
- (unsigned long long)*outp);
+ dm_warn("%#llx (%llu)\n", (unsigned long long)*outp,
+ (unsigned long long)*outp);
return 0;
}
@@ -498,11 +499,11 @@
bool prop;
assert(ofnode_valid(node));
- debug("%s: %s: ", __func__, propname);
+ dm_warn("%s: %s: ", __func__, propname);
prop = ofnode_has_property(node, propname);
- debug("%s\n", prop ? "true" : "false");
+ dm_warn("%s\n", prop ? "true" : "false");
return prop ? true : false;
}
@@ -513,7 +514,7 @@
int len;
assert(ofnode_valid(node));
- debug("%s: %s: ", __func__, propname);
+ dm_warn("%s: %s: ", __func__, propname);
if (ofnode_is_np(node)) {
struct property *prop = of_find_property(
@@ -528,7 +529,7 @@
propname, &len);
}
if (!val) {
- debug("<not found>\n");
+ dm_warn("<not found>\n");
if (sizep)
*sizep = -FDT_ERR_NOTFOUND;
return NULL;
@@ -549,10 +550,10 @@
return NULL;
if (strnlen(str, len) >= len) {
- debug("<invalid>\n");
+ dm_warn("<invalid>\n");
return NULL;
}
- debug("%s\n", str);
+ dm_warn("%s\n", str);
return str;
}
@@ -572,7 +573,7 @@
ofnode subnode;
assert(ofnode_valid(node));
- debug("%s: %s: ", __func__, subnode_name);
+ dm_warn("%s: %s: ", __func__, subnode_name);
if (ofnode_is_np(node)) {
struct device_node *np = ofnode_to_np(node);
@@ -587,8 +588,8 @@
ofnode_to_offset(node), subnode_name);
subnode = noffset_to_ofnode(node, ooffset);
}
- debug("%s\n", ofnode_valid(subnode) ?
- ofnode_get_name(subnode) : "<none>");
+ dm_warn("%s\n", ofnode_valid(subnode) ?
+ ofnode_get_name(subnode) : "<none>");
return subnode;
}
@@ -597,7 +598,7 @@
u32 *out_values, size_t sz)
{
assert(ofnode_valid(node));
- debug("%s: %s: ", __func__, propname);
+ dm_warn("%s: %s: ", __func__, propname);
if (ofnode_is_np(node)) {
return of_read_u32_array(ofnode_to_np(node), propname,
@@ -669,7 +670,7 @@
const char *ofnode_get_name(ofnode node)
{
if (!ofnode_valid(node)) {
- debug("%s node not valid\n", __func__);
+ dm_warn("%s node not valid\n", __func__);
return NULL;
}
@@ -1030,7 +1031,7 @@
if (!prop)
return ofnode_null();
- debug("%s: node_path: %s\n", __func__, prop);
+ dm_warn("%s: node_path: %s\n", __func__, prop);
return ofnode_path(prop);
}
@@ -1053,8 +1054,8 @@
length = ofnode_read_size(node, name);
if (length < 0) {
- debug("%s: could not find property %s\n",
- ofnode_get_name(node), name);
+ dm_warn("%s: could not find property %s\n",
+ ofnode_get_name(node), name);
return length;
}
@@ -1299,7 +1300,7 @@
int len;
int ret = -ENOENT;
- debug("%s: %s: ", __func__, propname);
+ dm_warn("%s: %s: ", __func__, propname);
/*
* If we follow the pci bus bindings strictly, we should check
@@ -1316,8 +1317,8 @@
int i;
for (i = 0; i < num; i++) {
- debug("pci address #%d: %08lx %08lx %08lx\n", i,
- (ulong)fdt32_to_cpu(cell[0]),
+ dm_warn("pci address #%d: %08lx %08lx %08lx\n", i,
+ (ulong)fdt32_to_cpu(cell[0]),
(ulong)fdt32_to_cpu(cell[1]),
(ulong)fdt32_to_cpu(cell[2]));
if ((fdt32_to_cpu(*cell) & type) == type) {
@@ -1346,7 +1347,7 @@
ret = -EINVAL;
fail:
- debug("(not found)\n");
+ dm_warn("(not found)\n");
return ret;
}
@@ -1630,7 +1631,7 @@
{
assert(ofnode_valid(node));
- debug("%s: %s = %s", __func__, propname, value);
+ dm_warn("%s: %s = %s", __func__, propname, value);
return ofnode_write_prop(node, propname, value, strlen(value) + 1,
false);
@@ -1743,7 +1744,7 @@
uboot = ofnode_path("/options/u-boot");
if (!ofnode_valid(uboot)) {
- debug("%s: Missing /u-boot node\n", __func__);
+ dm_warn("%s: Missing /u-boot node\n", __func__);
return -EINVAL;
}
@@ -1769,7 +1770,7 @@
uboot = ofnode_path("/options/u-boot");
if (!ofnode_valid(uboot)) {
- debug("%s: Missing /u-boot node\n", __func__);
+ dm_warn("%s: Missing /u-boot node\n", __func__);
return -EINVAL;
}
@@ -1784,7 +1785,7 @@
return -EINVAL;
if (!bootscr_flash_size) {
- debug("bootscr-flash-size is zero. Ignoring properties!\n");
+ dm_warn("bootscr-flash-size is zero. Ignoring properties!\n");
*bootscr_flash_offset = 0;
return -EINVAL;
}
@@ -1831,7 +1832,7 @@
if (!strcmp(mode, phy_interface_strings[i]))
return i;
- debug("%s: Invalid PHY interface '%s'\n", __func__, mode);
+ dm_warn("%s: Invalid PHY interface '%s'\n", __func__, mode);
return PHY_INTERFACE_MODE_NA;
}
diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c
index 7ff7834..304d5b0 100644
--- a/drivers/core/regmap.c
+++ b/drivers/core/regmap.c
@@ -17,6 +17,7 @@
#include <asm/io.h>
#include <dm/of_addr.h>
#include <dm/devres.h>
+#include <dm/util.h>
#include <linux/ioport.h>
#include <linux/compat.h>
#include <linux/err.h>
@@ -139,8 +140,8 @@
ret = of_address_to_resource(ofnode_to_np(node),
index, &r);
if (ret) {
- debug("%s: Could not read resource of range %d (ret = %d)\n",
- ofnode_get_name(node), index, ret);
+ dm_warn("%s: Could not read resource of range %d (ret = %d)\n",
+ ofnode_get_name(node), index, ret);
return ret;
}
@@ -154,8 +155,8 @@
addr_len, size_len,
&sz, true);
if (range->start == FDT_ADDR_T_NONE) {
- debug("%s: Could not read start of range %d\n",
- ofnode_get_name(node), index);
+ dm_warn("%s: Could not read start of range %d\n",
+ ofnode_get_name(node), index);
return -EINVAL;
}
@@ -173,15 +174,15 @@
addr_len = ofnode_read_simple_addr_cells(ofnode_get_parent(node));
if (addr_len < 0) {
- debug("%s: Error while reading the addr length (ret = %d)\n",
- ofnode_get_name(node), addr_len);
+ dm_warn("%s: Error while reading the addr length (ret = %d)\n",
+ ofnode_get_name(node), addr_len);
return addr_len;
}
size_len = ofnode_read_simple_size_cells(ofnode_get_parent(node));
if (size_len < 0) {
- debug("%s: Error while reading the size length: (ret = %d)\n",
- ofnode_get_name(node), size_len);
+ dm_warn("%s: Error while reading the size length: (ret = %d)\n",
+ ofnode_get_name(node), size_len);
return size_len;
}
@@ -250,36 +251,36 @@
addr_len = ofnode_read_simple_addr_cells(ofnode_get_parent(node));
if (addr_len < 0) {
- debug("%s: Error while reading the addr length (ret = %d)\n",
- ofnode_get_name(node), addr_len);
+ dm_warn("%s: Error while reading the addr length (ret = %d)\n",
+ ofnode_get_name(node), addr_len);
return addr_len;
}
size_len = ofnode_read_simple_size_cells(ofnode_get_parent(node));
if (size_len < 0) {
- debug("%s: Error while reading the size length: (ret = %d)\n",
- ofnode_get_name(node), size_len);
+ dm_warn("%s: Error while reading the size length: (ret = %d)\n",
+ ofnode_get_name(node), size_len);
return size_len;
}
both_len = addr_len + size_len;
if (!both_len) {
- debug("%s: Both addr and size length are zero\n",
- ofnode_get_name(node));
+ dm_warn("%s: Both addr and size length are zero\n",
+ ofnode_get_name(node));
return -EINVAL;
}
len = ofnode_read_size(node, "reg");
if (len < 0) {
- debug("%s: Error while reading reg size (ret = %d)\n",
- ofnode_get_name(node), len);
+ dm_warn("%s: Error while reading reg size (ret = %d)\n",
+ ofnode_get_name(node), len);
return len;
}
len /= sizeof(fdt32_t);
count = len / both_len;
if (!count) {
- debug("%s: Not enough data in reg property\n",
- ofnode_get_name(node));
+ dm_warn("%s: Not enough data in reg property\n",
+ ofnode_get_name(node));
return -EINVAL;
}
@@ -424,8 +425,8 @@
void *ptr;
if (do_range_check() && range_num >= map->range_count) {
- debug("%s: range index %d larger than range count\n",
- __func__, range_num);
+ dm_warn("%s: range index %d larger than range count\n",
+ __func__, range_num);
return -ERANGE;
}
range = &map->ranges[range_num];
@@ -433,7 +434,7 @@
offset <<= map->reg_offset_shift;
if (do_range_check() &&
(offset + val_len > range->size || offset + val_len < offset)) {
- debug("%s: offset/size combination invalid\n", __func__);
+ dm_warn("%s: offset/size combination invalid\n", __func__);
return -ERANGE;
}
@@ -455,7 +456,7 @@
break;
#endif
default:
- debug("%s: regmap size %zu unknown\n", __func__, val_len);
+ dm_warn("%s: regmap size %zu unknown\n", __func__, val_len);
return -EINVAL;
}
@@ -564,15 +565,15 @@
void *ptr;
if (range_num >= map->range_count) {
- debug("%s: range index %d larger than range count\n",
- __func__, range_num);
+ dm_warn("%s: range index %d larger than range count\n",
+ __func__, range_num);
return -ERANGE;
}
range = &map->ranges[range_num];
offset <<= map->reg_offset_shift;
if (offset + val_len > range->size || offset + val_len < offset) {
- debug("%s: offset/size combination invalid\n", __func__);
+ dm_warn("%s: offset/size combination invalid\n", __func__);
return -ERANGE;
}
@@ -594,7 +595,7 @@
break;
#endif
default:
- debug("%s: regmap size %zu unknown\n", __func__, val_len);
+ dm_warn("%s: regmap size %zu unknown\n", __func__, val_len);
return -EINVAL;
}
@@ -630,8 +631,8 @@
u.v64 = val;
break;
default:
- debug("%s: regmap size %zu unknown\n", __func__,
- (size_t)map->width);
+ dm_warn("%s: regmap size %zu unknown\n", __func__,
+ (size_t)map->width);
return -EINVAL;
}
diff --git a/drivers/core/root.c b/drivers/core/root.c
index 4bfd08f..7cf6607 100644
--- a/drivers/core/root.c
+++ b/drivers/core/root.c
@@ -207,7 +207,7 @@
err = lists_bind_fdt(parent, node, NULL, NULL, pre_reloc_only);
if (err && !ret) {
ret = err;
- debug("%s: ret=%d\n", node_name, ret);
+ dm_warn("%s: ret=%d\n", node_name, ret);
}
}
@@ -248,7 +248,7 @@
ret = dm_scan_fdt(pre_reloc_only);
if (ret) {
- debug("dm_scan_fdt() failed: %d\n", ret);
+ dm_warn("dm_scan_fdt() failed: %d\n", ret);
return ret;
}
@@ -256,8 +256,8 @@
for (i = 0; i < ARRAY_SIZE(nodes); i++) {
ret = dm_scan_fdt_ofnode_path(nodes[i], pre_reloc_only);
if (ret) {
- debug("dm_scan_fdt() scan for %s failed: %d\n",
- nodes[i], ret);
+ dm_warn("dm_scan_fdt() scan for %s failed: %d\n",
+ nodes[i], ret);
return ret;
}
}
@@ -320,14 +320,14 @@
ret = dm_scan_plat(pre_reloc_only);
if (ret) {
- debug("dm_scan_plat() failed: %d\n", ret);
+ dm_warn("dm_scan_plat() failed: %d\n", ret);
return ret;
}
if (CONFIG_IS_ENABLED(OF_REAL)) {
ret = dm_extended_scan(pre_reloc_only);
if (ret) {
- debug("dm_extended_scan() failed: %d\n", ret);
+ dm_warn("dm_extended_scan() failed: %d\n", ret);
return ret;
}
}
@@ -345,7 +345,7 @@
ret = dm_init(CONFIG_IS_ENABLED(OF_LIVE));
if (ret) {
- debug("dm_init() failed: %d\n", ret);
+ dm_warn("dm_init() failed: %d\n", ret);
return ret;
}
if (!CONFIG_IS_ENABLED(OF_PLATDATA_INST)) {
diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c
index 762536e..7ae0884 100644
--- a/drivers/core/uclass.c
+++ b/drivers/core/uclass.c
@@ -59,8 +59,8 @@
*ucp = NULL;
uc_drv = lists_uclass_lookup(id);
if (!uc_drv) {
- debug("Cannot find uclass for id %d: please add the UCLASS_DRIVER() declaration for this UCLASS_... id\n",
- id);
+ dm_warn("Cannot find uclass for id %d: please add the UCLASS_DRIVER() declaration for this UCLASS_... id\n",
+ id);
/*
* Use a strange error to make this case easier to find. When
* a uclass is not available it can prevent driver model from
diff --git a/drivers/cpu/Kconfig b/drivers/cpu/Kconfig
index 1c3c810..5c06cd9 100644
--- a/drivers/cpu/Kconfig
+++ b/drivers/cpu/Kconfig
@@ -33,3 +33,9 @@
select XILINX_MICROBLAZE0_PVR
help
Support CPU cores for Microblaze architecture.
+
+config CPU_XTENSA
+ bool "Enable Xtensa CPU driver"
+ depends on CPU && XTENSA
+ help
+ Support CPU cores for Xtensa architecture.
diff --git a/drivers/cpu/Makefile b/drivers/cpu/Makefile
index d4bbf6f..bc75d9b 100644
--- a/drivers/cpu/Makefile
+++ b/drivers/cpu/Makefile
@@ -14,4 +14,5 @@
obj-$(CONFIG_CPU_MPC83XX) += mpc83xx_cpu.o
obj-$(CONFIG_CPU_RISCV) += riscv_cpu.o
obj-$(CONFIG_CPU_MICROBLAZE) += microblaze_cpu.o
+obj-$(CONFIG_CPU_XTENSA) += xtensa_cpu.o
obj-$(CONFIG_SANDBOX) += cpu_sandbox.o
diff --git a/drivers/cpu/mpc83xx_cpu.c b/drivers/cpu/mpc83xx_cpu.c
index 9a7b5fd..127d3c3 100644
--- a/drivers/cpu/mpc83xx_cpu.c
+++ b/drivers/cpu/mpc83xx_cpu.c
@@ -9,7 +9,7 @@
#include <cpu.h>
#include <dm.h>
#include <log.h>
-#include <vsprintf.h>
+#include <stdio.h>
#include <linux/bitops.h>
#include "mpc83xx_cpu.h"
diff --git a/drivers/cpu/xtensa_cpu.c b/drivers/cpu/xtensa_cpu.c
new file mode 100644
index 0000000..fbb561d
--- /dev/null
+++ b/drivers/cpu/xtensa_cpu.c
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Jiaxun Yang <jiaxun.yang@flygoat.com>
+ */
+
+#include <clk.h>
+#include <cpu.h>
+#include <dm.h>
+#include <errno.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+
+#include <asm/arch/core.h>
+
+static int xtensa_cpu_get_desc(const struct udevice *dev, char *buf, int size)
+{
+ const char *cpu = XCHAL_CORE_ID;
+
+ if (!cpu || size < (strlen(cpu) + 1))
+ return -ENOSPC;
+
+ strcpy(buf, cpu);
+
+ return 0;
+}
+
+static int xtensa_cpu_get_info(const struct udevice *dev, struct cpu_info *info)
+{
+ struct cpu_plat *plat = dev_get_parent_plat(dev);
+
+ info->cpu_freq = plat->timebase_freq;
+
+#if XCHAL_HAVE_PTP_MMU
+ info->features |= BIT(CPU_FEAT_MMU);
+#endif
+#if XCHAL_ICACHE_SIZE || XCHAL_DCACHE_SIZE
+ info->features |= BIT(CPU_FEAT_L1_CACHE);
+#endif
+
+ return 0;
+}
+
+static int xtensa_cpu_get_count(const struct udevice *dev)
+{
+ ofnode node;
+ int num = 0;
+
+ ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
+ const char *device_type;
+
+ /* skip if hart is marked as not available in the device tree */
+ if (!ofnode_is_enabled(node))
+ continue;
+
+ device_type = ofnode_read_string(node, "device_type");
+ if (!device_type)
+ continue;
+ if (strcmp(device_type, "cpu") == 0)
+ num++;
+ }
+
+ return num;
+}
+
+static int xtensa_cpu_bind(struct udevice *dev)
+{
+ struct cpu_plat *plat = dev_get_parent_plat(dev);
+
+ plat->cpu_id = dev_read_addr(dev);
+
+ return 0;
+}
+
+static int xtensa_cpu_probe(struct udevice *dev)
+{
+ int ret = 0;
+ struct clk clk;
+ struct cpu_plat *plat = dev_get_parent_plat(dev);
+
+ asm volatile ("rsr %0, 176\n"
+ "rsr %1, 208\n"
+ : "=r"(plat->id[0]), "=r"(plat->id[1]));
+
+ /* Get a clock if it exists */
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (!ret) {
+ ret = clk_enable(&clk);
+ if (ret && (ret != -ENOSYS || ret != -ENOTSUPP))
+ return ret;
+ ret = clk_get_rate(&clk);
+ if (!IS_ERR_VALUE(ret))
+ plat->timebase_freq = ret;
+ }
+
+ return 0;
+}
+
+static const struct cpu_ops xtensa_cpu_ops = {
+ .get_desc = xtensa_cpu_get_desc,
+ .get_info = xtensa_cpu_get_info,
+ .get_count = xtensa_cpu_get_count,
+};
+
+static const struct udevice_id xtensa_cpu_ids[] = {
+ { .compatible = "cdns,xtensa-cpu" },
+ { }
+};
+
+U_BOOT_DRIVER(xtensa_cpu) = {
+ .name = "xtensa_cpu",
+ .id = UCLASS_CPU,
+ .of_match = xtensa_cpu_ids,
+ .bind = xtensa_cpu_bind,
+ .probe = xtensa_cpu_probe,
+ .ops = &xtensa_cpu_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/crypto/hash/hash_sw.c b/drivers/crypto/hash/hash_sw.c
index ffd4ab1..4590e22 100644
--- a/drivers/crypto/hash/hash_sw.c
+++ b/drivers/crypto/hash/hash_sw.c
@@ -50,17 +50,17 @@
/* MD5 */
static void hash_init_md5(void *ctx)
{
- MD5Init((struct MD5Context *)ctx);
+ MD5Init((MD5Context *)ctx);
}
static void hash_update_md5(void *ctx, const void *ibuf, uint32_t ilen)
{
- MD5Update((struct MD5Context *)ctx, ibuf, ilen);
+ MD5Update((MD5Context *)ctx, ibuf, ilen);
}
static void hash_finish_md5(void *ctx, void *obuf)
{
- MD5Final(obuf, (struct MD5Context *)ctx);
+ MD5Final(obuf, (MD5Context *)ctx);
}
/* SHA1 */
@@ -158,7 +158,7 @@
.init = hash_init_md5,
.update = hash_update_md5,
.finish = hash_finish_md5,
- .ctx_alloc_sz = sizeof(struct MD5Context),
+ .ctx_alloc_sz = sizeof(MD5Context),
},
[HASH_ALGO_SHA1] = {
diff --git a/drivers/ddr/marvell/a38x/Makefile b/drivers/ddr/marvell/a38x/Makefile
index fcfb615..4e8a9d1 100644
--- a/drivers/ddr/marvell/a38x/Makefile
+++ b/drivers/ddr/marvell/a38x/Makefile
@@ -18,6 +18,8 @@
obj-$(CONFIG_SPL_BUILD) += mv_ddr_topology.o
obj-$(CONFIG_SPL_BUILD) += xor.o
+obj-$(CONFIG_ARMADA_38X_SUPPORT_OLD_DDR3_TRAINING) += old/
+
ifdef CONFIG_DDR4
obj-$(CONFIG_SPL_BUILD) += mv_ddr4_mpr_pda_if.o
obj-$(CONFIG_SPL_BUILD) += mv_ddr4_training.o
diff --git a/drivers/ddr/marvell/a38x/ddr3_debug.c b/drivers/ddr/marvell/a38x/ddr3_debug.c
index 9e499cf..0b65168 100644
--- a/drivers/ddr/marvell/a38x/ddr3_debug.c
+++ b/drivers/ddr/marvell/a38x/ddr3_debug.c
@@ -7,18 +7,21 @@
#include "mv_ddr_training_db.h"
#include "mv_ddr_regs.h"
+#if !defined(CONFIG_DDR_IMMUTABLE_DEBUG_SETTINGS)
u8 is_reg_dump = 0;
u8 debug_pbs = DEBUG_LEVEL_ERROR;
+#endif
/*
* API to change flags outside of the lib
*/
-#if defined(SILENT_LIB)
+#if defined(SILENT_LIB) || defined(CONFIG_DDR_IMMUTABLE_DEBUG_SETTINGS)
void ddr3_hws_set_log_level(enum ddr_lib_debug_block block, u8 level)
{
/* do nothing */
}
-#else /* SILENT_LIB */
+#else /* !SILENT_LIB && !CONFIG_DDR_IMMUTABLE_DEBUG_SETTINGS */
+
/* Debug flags for other Training modules */
u8 debug_training_static = DEBUG_LEVEL_ERROR;
u8 debug_training = DEBUG_LEVEL_ERROR;
@@ -104,7 +107,7 @@
#endif /* CONFIG_DDR4 */
}
}
-#endif /* SILENT_LIB */
+#endif /* !SILENT_LIB && !CONFIG_DDR_IMMUTABLE_DEBUG_SETTINGS */
#if defined(DDR_VIEWER_TOOL)
static char *convert_freq(enum mv_ddr_freq freq);
@@ -114,16 +117,14 @@
u32 ctrl_adll1[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM];
u32 ctrl_level_phase[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM];
#endif /* EXCLUDE_SWITCH_DEBUG */
+
+static u8 is_validate_window_per_if = 0;
+static u8 is_validate_window_per_pup = 0;
+static u8 sweep_cnt = 1;
+static u8 is_run_leveling_sweep_tests;
#endif /* DDR_VIEWER_TOOL */
struct hws_tip_config_func_db config_func_info[MAX_DEVICE_NUM];
-u8 is_default_centralization = 0;
-u8 is_tune_result = 0;
-u8 is_validate_window_per_if = 0;
-u8 is_validate_window_per_pup = 0;
-u8 sweep_cnt = 1;
-u32 is_bist_reset_bit = 1;
-u8 is_run_leveling_sweep_tests;
static struct hws_xsb_info xsb_info[MAX_DEVICE_NUM];
@@ -399,6 +400,15 @@
}
#endif /* DDR_VIEWER_TOOL */
+ /* return early if we won't print anything anyway */
+ if (
+#if defined(SILENT_LIB)
+ 1 ||
+#endif
+ debug_training < DEBUG_LEVEL_INFO) {
+ return MV_OK;
+ }
+
for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
diff --git a/drivers/ddr/marvell/a38x/ddr3_init.c b/drivers/ddr/marvell/a38x/ddr3_init.c
index 27eb3ac..7c5147f 100644
--- a/drivers/ddr/marvell/a38x/ddr3_init.c
+++ b/drivers/ddr/marvell/a38x/ddr3_init.c
@@ -41,7 +41,8 @@
mv_ddr_pre_training_soc_config(ddr_type);
/* Set log level for training library */
- mv_ddr_user_log_level_set(DEBUG_BLOCK_ALL);
+ if (!IS_ENABLED(CONFIG_DDR_IMMUTABLE_DEBUG_SETTINGS))
+ mv_ddr_user_log_level_set(DEBUG_BLOCK_ALL);
mv_ddr_early_init();
diff --git a/drivers/ddr/marvell/a38x/ddr3_init.h b/drivers/ddr/marvell/a38x/ddr3_init.h
index 6854bb4..b513a13 100644
--- a/drivers/ddr/marvell/a38x/ddr3_init.h
+++ b/drivers/ddr/marvell/a38x/ddr3_init.h
@@ -45,15 +45,46 @@
#define MISL_PHY_ODT_N_OFFS 0x0
/* Globals */
-extern u8 debug_training, debug_calibration, debug_ddr4_centralization,
- debug_tap_tuning, debug_dm_tuning;
+#if defined(CONFIG_DDR_IMMUTABLE_DEBUG_SETTINGS)
+static const u8 is_reg_dump = 0;
+static const u8 debug_training_static = DEBUG_LEVEL_ERROR;
+static const u8 debug_training = DEBUG_LEVEL_ERROR;
+static const u8 debug_leveling = DEBUG_LEVEL_ERROR;
+static const u8 debug_centralization = DEBUG_LEVEL_ERROR;
+static const u8 debug_training_ip = DEBUG_LEVEL_ERROR;
+static const u8 debug_training_bist = DEBUG_LEVEL_ERROR;
+static const u8 debug_training_hw_alg = DEBUG_LEVEL_ERROR;
+static const u8 debug_training_access = DEBUG_LEVEL_ERROR;
+static const u8 debug_training_device = DEBUG_LEVEL_ERROR;
+static const u8 debug_pbs = DEBUG_LEVEL_ERROR;
+
+static const u8 debug_tap_tuning = DEBUG_LEVEL_ERROR;
+static const u8 debug_calibration = DEBUG_LEVEL_ERROR;
+static const u8 debug_ddr4_centralization = DEBUG_LEVEL_ERROR;
+static const u8 debug_dm_tuning = DEBUG_LEVEL_ERROR;
+#else /* !CONFIG_DDR_IMMUTABLE_DEBUG_SETTINGS */
extern u8 is_reg_dump;
+extern u8 debug_training_static;
+extern u8 debug_training;
+extern u8 debug_leveling;
+extern u8 debug_centralization;
+extern u8 debug_training_ip;
+extern u8 debug_training_bist;
+extern u8 debug_training_hw_alg;
+extern u8 debug_training_access;
+extern u8 debug_training_device;
+extern u8 debug_pbs;
+
+extern u8 debug_tap_tuning;
+extern u8 debug_calibration;
+extern u8 debug_ddr4_centralization;
+extern u8 debug_dm_tuning;
+#endif /* !CONFIG_DDR_IMMUTABLE_DEBUG_SETTINGS */
+
extern u8 generic_init_controller;
/* list of allowed frequency listed in order of enum mv_ddr_freq */
extern u32 is_pll_old;
extern struct pattern_info pattern_table[];
-extern u8 debug_centralization, debug_training_ip, debug_training_bist,
- debug_pbs, debug_training_static, debug_leveling;
extern struct hws_tip_config_func_db config_func_info[];
extern u8 twr_mask_table[];
extern u8 cl_mask_table[];
@@ -76,7 +107,6 @@
extern u32 g_rtt_wr;
extern u32 g_rtt_park;
-extern u8 debug_training_access;
extern u32 first_active_if;
extern u32 delay_enable, ck_delay, ca_delay;
extern u32 mask_tune_func;
@@ -116,15 +146,12 @@
extern u32 freq_mask[MAX_DEVICE_NUM][MV_DDR_FREQ_LAST];
extern u32 maxt_poll_tries;
-extern u32 is_bist_reset_bit;
extern u8 vref_window_size[MAX_INTERFACE_NUM][MAX_BUS_NUM];
extern u32 effective_cs;
extern int ddr3_tip_centr_skip_min_win_check;
extern u32 *dq_map_table;
-extern u8 debug_training_hw_alg;
-
extern u32 start_xsb_offset;
extern u32 odt_config;
diff --git a/drivers/ddr/marvell/a38x/old/Makefile b/drivers/ddr/marvell/a38x/old/Makefile
new file mode 100644
index 0000000..1645a79
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/Makefile
@@ -0,0 +1,29 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_SPL_BUILD) += ddr3_a38x.o
+obj-$(CONFIG_SPL_BUILD) += ddr3_a38x_training.o
+obj-$(CONFIG_SPL_BUILD) += ddr3_debug.o
+obj-$(CONFIG_SPL_BUILD) += ddr3_hws_hw_training.o
+obj-$(CONFIG_SPL_BUILD) += ddr3_init.o
+obj-$(CONFIG_SPL_BUILD) += ddr3_training.o
+obj-$(CONFIG_SPL_BUILD) += ddr3_training_bist.o
+obj-$(CONFIG_SPL_BUILD) += ddr3_training_centralization.o
+obj-$(CONFIG_SPL_BUILD) += ddr3_training_db.o
+obj-$(CONFIG_SPL_BUILD) += ddr3_training_hw_algo.o
+obj-$(CONFIG_SPL_BUILD) += ddr3_training_ip_engine.o
+obj-$(CONFIG_SPL_BUILD) += ddr3_training_leveling.o
+obj-$(CONFIG_SPL_BUILD) += ddr3_training_pbs.o
+obj-$(CONFIG_SPL_BUILD) += ddr3_training_static.o
+
+define IncludeSymbolRename
+ CFLAGS_$(1) = -include $(srctree)/drivers/ddr/marvell/a38x/old/glue_symbol_renames.h
+endef
+
+$(foreach obj,$(obj-y),$(eval $(call IncludeSymbolRename,$(obj))))
+
+# The old version of DDR training fails weirdly on some boards if the whole
+# driver is compiled with LTO. It seems to work if at least ddr3_init.c is
+# compiled without LTO.
+CFLAGS_REMOVE_ddr3_init.o := $(LTO_CFLAGS)
diff --git a/drivers/ddr/marvell/a38x/old/ddr3_a38x.c b/drivers/ddr/marvell/a38x/old/ddr3_a38x.c
new file mode 100644
index 0000000..8504b9b
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/ddr3_a38x.c
@@ -0,0 +1,737 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <i2c.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <linux/delay.h>
+
+#include "ddr3_init.h"
+
+#define A38X_NUMBER_OF_INTERFACES 5
+
+#define SAR_DEV_ID_OFFS 27
+#define SAR_DEV_ID_MASK 0x7
+
+/* Termal Sensor Registers */
+#define TSEN_STATE_REG 0xe4070
+#define TSEN_STATE_OFFSET 31
+#define TSEN_STATE_MASK (0x1 << TSEN_STATE_OFFSET)
+#define TSEN_CONF_REG 0xe4074
+#define TSEN_CONF_RST_OFFSET 8
+#define TSEN_CONF_RST_MASK (0x1 << TSEN_CONF_RST_OFFSET)
+#define TSEN_STATUS_REG 0xe4078
+#define TSEN_STATUS_READOUT_VALID_OFFSET 10
+#define TSEN_STATUS_READOUT_VALID_MASK (0x1 << \
+ TSEN_STATUS_READOUT_VALID_OFFSET)
+#define TSEN_STATUS_TEMP_OUT_OFFSET 0
+#define TSEN_STATUS_TEMP_OUT_MASK (0x3ff << TSEN_STATUS_TEMP_OUT_OFFSET)
+
+static struct dfx_access interface_map[] = {
+ /* Pipe Client */
+ { 0, 17 },
+ { 1, 7 },
+ { 1, 11 },
+ { 0, 3 },
+ { 1, 25 },
+ { 0, 0 },
+ { 0, 0 },
+ { 0, 0 },
+ { 0, 0 },
+ { 0, 0 },
+ { 0, 0 },
+ { 0, 0 }
+};
+
+/* This array hold the board round trip delay (DQ and CK) per <interface,bus> */
+struct trip_delay_element a38x_board_round_trip_delay_array[] = {
+ /* 1st board */
+ /* Interface bus DQS-delay CK-delay */
+ { 3952, 5060 },
+ { 3192, 4493 },
+ { 4785, 6677 },
+ { 3413, 7267 },
+ { 4282, 6086 }, /* ECC PUP */
+ { 3952, 5134 },
+ { 3192, 4567 },
+ { 4785, 6751 },
+ { 3413, 7341 },
+ { 4282, 6160 }, /* ECC PUP */
+
+ /* 2nd board */
+ /* Interface bus DQS-delay CK-delay */
+ { 3952, 5060 },
+ { 3192, 4493 },
+ { 4785, 6677 },
+ { 3413, 7267 },
+ { 4282, 6086 }, /* ECC PUP */
+ { 3952, 5134 },
+ { 3192, 4567 },
+ { 4785, 6751 },
+ { 3413, 7341 },
+ { 4282, 6160 } /* ECC PUP */
+};
+
+#ifdef STATIC_ALGO_SUPPORT
+/* package trace */
+static struct trip_delay_element a38x_package_round_trip_delay_array[] = {
+ /* IF BUS DQ_DELAY CK_DELAY */
+ { 0, 0 },
+ { 0, 0 },
+ { 0, 0 },
+ { 0, 0 },
+ { 0, 0 },
+ { 0, 0 },
+ { 0, 0 },
+ { 0, 0 },
+ { 0, 0 },
+ { 0, 0 },
+ { 0, 0 },
+ { 0, 0 },
+ { 0, 0 },
+ { 0, 0 },
+ { 0, 0 },
+ { 0, 0 },
+ { 0, 0 },
+ { 0, 0 },
+ { 0, 0 },
+ { 0, 0 }
+};
+
+static int a38x_silicon_delay_offset[] = {
+ /* board 0 */
+ 0,
+ /* board 1 */
+ 0,
+ /* board 2 */
+ 0
+};
+#endif
+
+static u8 a38x_bw_per_freq[DDR_FREQ_LIMIT] = {
+ 0x3, /* DDR_FREQ_100 */
+ 0x4, /* DDR_FREQ_400 */
+ 0x4, /* DDR_FREQ_533 */
+ 0x5, /* DDR_FREQ_667 */
+ 0x5, /* DDR_FREQ_800 */
+ 0x5, /* DDR_FREQ_933 */
+ 0x5, /* DDR_FREQ_1066 */
+ 0x3, /* DDR_FREQ_311 */
+ 0x3, /* DDR_FREQ_333 */
+ 0x4, /* DDR_FREQ_467 */
+ 0x5, /* DDR_FREQ_850 */
+ 0x5, /* DDR_FREQ_600 */
+ 0x3, /* DDR_FREQ_300 */
+ 0x5, /* DDR_FREQ_900 */
+ 0x3, /* DDR_FREQ_360 */
+ 0x5 /* DDR_FREQ_1000 */
+};
+
+static u8 a38x_rate_per_freq[DDR_FREQ_LIMIT] = {
+ /*TBD*/ 0x1, /* DDR_FREQ_100 */
+ 0x2, /* DDR_FREQ_400 */
+ 0x2, /* DDR_FREQ_533 */
+ 0x2, /* DDR_FREQ_667 */
+ 0x2, /* DDR_FREQ_800 */
+ 0x3, /* DDR_FREQ_933 */
+ 0x3, /* DDR_FREQ_1066 */
+ 0x1, /* DDR_FREQ_311 */
+ 0x1, /* DDR_FREQ_333 */
+ 0x2, /* DDR_FREQ_467 */
+ 0x2, /* DDR_FREQ_850 */
+ 0x2, /* DDR_FREQ_600 */
+ 0x1, /* DDR_FREQ_300 */
+ 0x2, /* DDR_FREQ_900 */
+ 0x1, /* DDR_FREQ_360 */
+ 0x2 /* DDR_FREQ_1000 */
+};
+
+static u16 a38x_vco_freq_per_sar[] = {
+ 666, /* 0 */
+ 1332,
+ 800,
+ 1600,
+ 1066,
+ 2132,
+ 1200,
+ 2400,
+ 1332,
+ 1332,
+ 1500,
+ 1500,
+ 1600, /* 12 */
+ 1600,
+ 1700,
+ 1700,
+ 1866,
+ 1866,
+ 1800, /* 18 */
+ 2000,
+ 2000,
+ 4000,
+ 2132,
+ 2132,
+ 2300,
+ 2300,
+ 2400,
+ 2400,
+ 2500,
+ 2500,
+ 800
+};
+
+u32 pipe_multicast_mask;
+
+u32 dq_bit_map_2_phy_pin[] = {
+ 1, 0, 2, 6, 9, 8, 3, 7, /* 0 */
+ 8, 9, 1, 7, 2, 6, 3, 0, /* 1 */
+ 3, 9, 7, 8, 1, 0, 2, 6, /* 2 */
+ 1, 0, 6, 2, 8, 3, 7, 9, /* 3 */
+ 0, 1, 2, 9, 7, 8, 3, 6, /* 4 */
+};
+
+static int ddr3_tip_a38x_set_divider(u8 dev_num, u32 if_id,
+ enum hws_ddr_freq freq);
+
+/*
+ * Read temperature TJ value
+ */
+u32 ddr3_ctrl_get_junc_temp(u8 dev_num)
+{
+ int reg = 0;
+
+ /* Initiates TSEN hardware reset once */
+ if ((reg_read(TSEN_CONF_REG) & TSEN_CONF_RST_MASK) == 0)
+ reg_bit_set(TSEN_CONF_REG, TSEN_CONF_RST_MASK);
+ mdelay(10);
+
+ /* Check if the readout field is valid */
+ if ((reg_read(TSEN_STATUS_REG) & TSEN_STATUS_READOUT_VALID_MASK) == 0) {
+ printf("%s: TSEN not ready\n", __func__);
+ return 0;
+ }
+
+ reg = reg_read(TSEN_STATUS_REG);
+ reg = (reg & TSEN_STATUS_TEMP_OUT_MASK) >> TSEN_STATUS_TEMP_OUT_OFFSET;
+
+ return ((((10000 * reg) / 21445) * 1000) - 272674) / 1000;
+}
+
+/*
+ * Name: ddr3_tip_a38x_get_freq_config.
+ * Desc:
+ * Args:
+ * Notes:
+ * Returns: MV_OK if success, other error code if fail.
+ */
+int ddr3_tip_a38x_get_freq_config(u8 dev_num, enum hws_ddr_freq freq,
+ struct hws_tip_freq_config_info
+ *freq_config_info)
+{
+ if (a38x_bw_per_freq[freq] == 0xff)
+ return MV_NOT_SUPPORTED;
+
+ if (freq_config_info == NULL)
+ return MV_BAD_PARAM;
+
+ freq_config_info->bw_per_freq = a38x_bw_per_freq[freq];
+ freq_config_info->rate_per_freq = a38x_rate_per_freq[freq];
+ freq_config_info->is_supported = 1;
+
+ return MV_OK;
+}
+
+/*
+ * Name: ddr3_tip_a38x_pipe_enable.
+ * Desc:
+ * Args:
+ * Notes:
+ * Returns: MV_OK if success, other error code if fail.
+ */
+int ddr3_tip_a38x_pipe_enable(u8 dev_num, enum hws_access_type interface_access,
+ u32 if_id, int enable)
+{
+ u32 data_value, pipe_enable_mask = 0;
+
+ if (enable == 0) {
+ pipe_enable_mask = 0;
+ } else {
+ if (interface_access == ACCESS_TYPE_MULTICAST)
+ pipe_enable_mask = pipe_multicast_mask;
+ else
+ pipe_enable_mask = (1 << interface_map[if_id].pipe);
+ }
+
+ CHECK_STATUS(ddr3_tip_reg_read
+ (dev_num, PIPE_ENABLE_ADDR, &data_value, MASK_ALL_BITS));
+ data_value = (data_value & (~0xff)) | pipe_enable_mask;
+ CHECK_STATUS(ddr3_tip_reg_write(dev_num, PIPE_ENABLE_ADDR, data_value));
+
+ return MV_OK;
+}
+
+/*
+ * Name: ddr3_tip_a38x_if_write.
+ * Desc:
+ * Args:
+ * Notes:
+ * Returns: MV_OK if success, other error code if fail.
+ */
+int ddr3_tip_a38x_if_write(u8 dev_num, enum hws_access_type interface_access,
+ u32 if_id, u32 reg_addr, u32 data_value,
+ u32 mask)
+{
+ u32 ui_data_read;
+
+ if (mask != MASK_ALL_BITS) {
+ CHECK_STATUS(ddr3_tip_a38x_if_read
+ (dev_num, ACCESS_TYPE_UNICAST, if_id, reg_addr,
+ &ui_data_read, MASK_ALL_BITS));
+ data_value = (ui_data_read & (~mask)) | (data_value & mask);
+ }
+
+ reg_write(reg_addr, data_value);
+
+ return MV_OK;
+}
+
+/*
+ * Name: ddr3_tip_a38x_if_read.
+ * Desc:
+ * Args:
+ * Notes:
+ * Returns: MV_OK if success, other error code if fail.
+ */
+int ddr3_tip_a38x_if_read(u8 dev_num, enum hws_access_type interface_access,
+ u32 if_id, u32 reg_addr, u32 *data, u32 mask)
+{
+ *data = reg_read(reg_addr) & mask;
+
+ return MV_OK;
+}
+
+/*
+ * Name: ddr3_tip_a38x_select_ddr_controller.
+ * Desc: Enable/Disable access to Marvell's server.
+ * Args: dev_num - device number
+ * enable - whether to enable or disable the server
+ * Notes:
+ * Returns: MV_OK if success, other error code if fail.
+ */
+int ddr3_tip_a38x_select_ddr_controller(u8 dev_num, int enable)
+{
+ u32 reg;
+
+ reg = reg_read(CS_ENABLE_REG);
+
+ if (enable)
+ reg |= (1 << 6);
+ else
+ reg &= ~(1 << 6);
+
+ reg_write(CS_ENABLE_REG, reg);
+
+ return MV_OK;
+}
+
+/*
+ * Name: ddr3_tip_init_a38x_silicon.
+ * Desc: init Training SW DB.
+ * Args:
+ * Notes:
+ * Returns: MV_OK if success, other error code if fail.
+ */
+static int ddr3_tip_init_a38x_silicon(u32 dev_num, u32 board_id)
+{
+ struct hws_tip_config_func_db config_func;
+ enum hws_ddr_freq ddr_freq;
+ int status;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ /* new read leveling version */
+ config_func.tip_dunit_read_func = ddr3_tip_a38x_if_read;
+ config_func.tip_dunit_write_func = ddr3_tip_a38x_if_write;
+ config_func.tip_dunit_mux_select_func =
+ ddr3_tip_a38x_select_ddr_controller;
+ config_func.tip_get_freq_config_info_func =
+ ddr3_tip_a38x_get_freq_config;
+ config_func.tip_set_freq_divider_func = ddr3_tip_a38x_set_divider;
+ config_func.tip_get_device_info_func = ddr3_tip_a38x_get_device_info;
+ config_func.tip_get_temperature = ddr3_ctrl_get_junc_temp;
+
+ ddr3_tip_init_config_func(dev_num, &config_func);
+
+ ddr3_tip_register_dq_table(dev_num, dq_bit_map_2_phy_pin);
+
+#ifdef STATIC_ALGO_SUPPORT
+ {
+ struct hws_tip_static_config_info static_config;
+ u32 board_offset =
+ board_id * A38X_NUMBER_OF_INTERFACES *
+ tm->num_of_bus_per_interface;
+
+ static_config.silicon_delay =
+ a38x_silicon_delay_offset[board_id];
+ static_config.package_trace_arr =
+ a38x_package_round_trip_delay_array;
+ static_config.board_trace_arr =
+ &a38x_board_round_trip_delay_array[board_offset];
+ ddr3_tip_init_static_config_db(dev_num, &static_config);
+ }
+#endif
+ status = ddr3_tip_a38x_get_init_freq(dev_num, &ddr_freq);
+ if (MV_OK != status) {
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR,
+ ("DDR3 silicon get target frequency - FAILED 0x%x\n",
+ status));
+ return status;
+ }
+
+ rl_version = 1;
+ mask_tune_func = (SET_LOW_FREQ_MASK_BIT |
+ LOAD_PATTERN_MASK_BIT |
+ SET_MEDIUM_FREQ_MASK_BIT | WRITE_LEVELING_MASK_BIT |
+ /* LOAD_PATTERN_2_MASK_BIT | */
+ WRITE_LEVELING_SUPP_MASK_BIT |
+ READ_LEVELING_MASK_BIT |
+ PBS_RX_MASK_BIT |
+ PBS_TX_MASK_BIT |
+ SET_TARGET_FREQ_MASK_BIT |
+ WRITE_LEVELING_TF_MASK_BIT |
+ WRITE_LEVELING_SUPP_TF_MASK_BIT |
+ READ_LEVELING_TF_MASK_BIT |
+ CENTRALIZATION_RX_MASK_BIT |
+ CENTRALIZATION_TX_MASK_BIT);
+ rl_mid_freq_wa = 1;
+
+ if ((ddr_freq == DDR_FREQ_333) || (ddr_freq == DDR_FREQ_400)) {
+ mask_tune_func = (WRITE_LEVELING_MASK_BIT |
+ LOAD_PATTERN_2_MASK_BIT |
+ WRITE_LEVELING_SUPP_MASK_BIT |
+ READ_LEVELING_MASK_BIT |
+ PBS_RX_MASK_BIT |
+ PBS_TX_MASK_BIT |
+ CENTRALIZATION_RX_MASK_BIT |
+ CENTRALIZATION_TX_MASK_BIT);
+ rl_mid_freq_wa = 0; /* WA not needed if 333/400 is TF */
+ }
+
+ /* Supplementary not supported for ECC modes */
+ if (1 == ddr3_if_ecc_enabled()) {
+ mask_tune_func &= ~WRITE_LEVELING_SUPP_TF_MASK_BIT;
+ mask_tune_func &= ~WRITE_LEVELING_SUPP_MASK_BIT;
+ mask_tune_func &= ~PBS_TX_MASK_BIT;
+ mask_tune_func &= ~PBS_RX_MASK_BIT;
+ }
+
+ if (ck_delay == -1)
+ ck_delay = 160;
+ if (ck_delay_16 == -1)
+ ck_delay_16 = 160;
+ ca_delay = 0;
+ delay_enable = 1;
+
+ calibration_update_control = 1;
+
+ init_freq = tm->interface_params[first_active_if].memory_freq;
+
+ ddr3_tip_a38x_get_medium_freq(dev_num, &medium_freq);
+
+ return MV_OK;
+}
+
+int ddr3_a38x_update_topology_map(u32 dev_num, struct hws_topology_map *tm)
+{
+ u32 if_id = 0;
+ enum hws_ddr_freq freq;
+
+ ddr3_tip_a38x_get_init_freq(dev_num, &freq);
+ tm->interface_params[if_id].memory_freq = freq;
+
+ /*
+ * re-calc topology parameters according to topology updates
+ * (if needed)
+ */
+ CHECK_STATUS(hws_ddr3_tip_load_topology_map(dev_num, tm));
+
+ return MV_OK;
+}
+
+int ddr3_tip_init_a38x(u32 dev_num, u32 board_id)
+{
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ if (NULL == tm)
+ return MV_FAIL;
+
+ ddr3_a38x_update_topology_map(dev_num, tm);
+ ddr3_tip_init_a38x_silicon(dev_num, board_id);
+
+ return MV_OK;
+}
+
+int ddr3_tip_a38x_get_init_freq(int dev_num, enum hws_ddr_freq *freq)
+{
+ u32 reg;
+
+ /* Read sample at reset setting */
+ reg = (reg_read(REG_DEVICE_SAR1_ADDR) >>
+ RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET) &
+ RST2_CPU_DDR_CLOCK_SELECT_IN_MASK;
+ switch (reg) {
+ case 0x0:
+ case 0x1:
+ *freq = DDR_FREQ_333;
+ break;
+ case 0x2:
+ case 0x3:
+ *freq = DDR_FREQ_400;
+ break;
+ case 0x4:
+ case 0xd:
+ *freq = DDR_FREQ_533;
+ break;
+ case 0x6:
+ *freq = DDR_FREQ_600;
+ break;
+ case 0x8:
+ case 0x11:
+ case 0x14:
+ *freq = DDR_FREQ_667;
+ break;
+ case 0xc:
+ case 0x15:
+ case 0x1b:
+ *freq = DDR_FREQ_800;
+ break;
+ case 0x10:
+ *freq = DDR_FREQ_933;
+ break;
+ case 0x12:
+ *freq = DDR_FREQ_900;
+ break;
+ case 0x13:
+ *freq = DDR_FREQ_900;
+ break;
+ default:
+ *freq = 0;
+ return MV_NOT_SUPPORTED;
+ }
+
+ return MV_OK;
+}
+
+int ddr3_tip_a38x_get_medium_freq(int dev_num, enum hws_ddr_freq *freq)
+{
+ u32 reg;
+
+ /* Read sample at reset setting */
+ reg = (reg_read(REG_DEVICE_SAR1_ADDR) >>
+ RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET) &
+ RST2_CPU_DDR_CLOCK_SELECT_IN_MASK;
+ switch (reg) {
+ case 0x0:
+ case 0x1:
+ /* Medium is same as TF to run PBS in this freq */
+ *freq = DDR_FREQ_333;
+ break;
+ case 0x2:
+ case 0x3:
+ /* Medium is same as TF to run PBS in this freq */
+ *freq = DDR_FREQ_400;
+ break;
+ case 0x4:
+ case 0xd:
+ *freq = DDR_FREQ_533;
+ break;
+ case 0x8:
+ case 0x11:
+ case 0x14:
+ *freq = DDR_FREQ_333;
+ break;
+ case 0xc:
+ case 0x15:
+ case 0x1b:
+ *freq = DDR_FREQ_400;
+ break;
+ case 0x6:
+ *freq = DDR_FREQ_300;
+ break;
+ case 0x12:
+ *freq = DDR_FREQ_360;
+ break;
+ case 0x13:
+ *freq = DDR_FREQ_400;
+ break;
+ default:
+ *freq = 0;
+ return MV_NOT_SUPPORTED;
+ }
+
+ return MV_OK;
+}
+
+u32 ddr3_tip_get_init_freq(void)
+{
+ enum hws_ddr_freq freq;
+
+ ddr3_tip_a38x_get_init_freq(0, &freq);
+
+ return freq;
+}
+
+static int ddr3_tip_a38x_set_divider(u8 dev_num, u32 if_id,
+ enum hws_ddr_freq frequency)
+{
+ u32 divider = 0;
+ u32 sar_val;
+
+ if (if_id != 0) {
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR,
+ ("A38x does not support interface 0x%x\n",
+ if_id));
+ return MV_BAD_PARAM;
+ }
+
+ /* get VCO freq index */
+ sar_val = (reg_read(REG_DEVICE_SAR1_ADDR) >>
+ RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET) &
+ RST2_CPU_DDR_CLOCK_SELECT_IN_MASK;
+ divider = a38x_vco_freq_per_sar[sar_val] / freq_val[frequency];
+
+ /* Set Sync mode */
+ CHECK_STATUS(ddr3_tip_a38x_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x20220, 0x0,
+ 0x1000));
+ CHECK_STATUS(ddr3_tip_a38x_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe42f4, 0x0,
+ 0x200));
+
+ /* cpupll_clkdiv_reset_mask */
+ CHECK_STATUS(ddr3_tip_a38x_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4264, 0x1f,
+ 0xff));
+
+ /* cpupll_clkdiv_reload_smooth */
+ CHECK_STATUS(ddr3_tip_a38x_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4260,
+ (0x2 << 8), (0xff << 8)));
+
+ /* cpupll_clkdiv_relax_en */
+ CHECK_STATUS(ddr3_tip_a38x_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4260,
+ (0x2 << 24), (0xff << 24)));
+
+ /* write the divider */
+ CHECK_STATUS(ddr3_tip_a38x_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4268,
+ (divider << 8), (0x3f << 8)));
+
+ /* set cpupll_clkdiv_reload_ratio */
+ CHECK_STATUS(ddr3_tip_a38x_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4264,
+ (1 << 8), (1 << 8)));
+
+ /* undet cpupll_clkdiv_reload_ratio */
+ CHECK_STATUS(ddr3_tip_a38x_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4264, 0,
+ (1 << 8)));
+
+ /* clear cpupll_clkdiv_reload_force */
+ CHECK_STATUS(ddr3_tip_a38x_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4260, 0,
+ (0xff << 8)));
+
+ /* clear cpupll_clkdiv_relax_en */
+ CHECK_STATUS(ddr3_tip_a38x_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4260, 0,
+ (0xff << 24)));
+
+ /* clear cpupll_clkdiv_reset_mask */
+ CHECK_STATUS(ddr3_tip_a38x_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4264, 0,
+ 0xff));
+
+ /* Dunit training clock + 1:1 mode */
+ if ((frequency == DDR_FREQ_LOW_FREQ) || (freq_val[frequency] <= 400)) {
+ CHECK_STATUS(ddr3_tip_a38x_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x18488,
+ (1 << 16), (1 << 16)));
+ CHECK_STATUS(ddr3_tip_a38x_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x1524,
+ (0 << 15), (1 << 15)));
+ } else {
+ CHECK_STATUS(ddr3_tip_a38x_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x18488,
+ 0, (1 << 16)));
+ CHECK_STATUS(ddr3_tip_a38x_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x1524,
+ (1 << 15), (1 << 15)));
+ }
+
+ return MV_OK;
+}
+
+/*
+ * external read from memory
+ */
+int ddr3_tip_ext_read(u32 dev_num, u32 if_id, u32 reg_addr,
+ u32 num_of_bursts, u32 *data)
+{
+ u32 burst_num;
+
+ for (burst_num = 0; burst_num < num_of_bursts * 8; burst_num++)
+ data[burst_num] = readl(reg_addr + 4 * burst_num);
+
+ return MV_OK;
+}
+
+/*
+ * external write to memory
+ */
+int ddr3_tip_ext_write(u32 dev_num, u32 if_id, u32 reg_addr,
+ u32 num_of_bursts, u32 *data) {
+ u32 burst_num;
+
+ for (burst_num = 0; burst_num < num_of_bursts * 8; burst_num++)
+ writel(data[burst_num], reg_addr + 4 * burst_num);
+
+ return MV_OK;
+}
+
+int ddr3_silicon_pre_init(void)
+{
+ return ddr3_silicon_init();
+}
+
+int ddr3_post_run_alg(void)
+{
+ return MV_OK;
+}
+
+int ddr3_silicon_post_init(void)
+{
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ /* Set half bus width */
+ if (DDR3_IS_16BIT_DRAM_MODE(tm->bus_act_mask)) {
+ CHECK_STATUS(ddr3_tip_if_write
+ (0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
+ REG_SDRAM_CONFIG_ADDR, 0x0, 0x8000));
+ }
+
+ return MV_OK;
+}
+
+int ddr3_tip_a38x_get_device_info(u8 dev_num, struct ddr3_device_info *info_ptr)
+{
+ info_ptr->device_id = 0x6800;
+ info_ptr->ck_delay = ck_delay;
+
+ return MV_OK;
+}
diff --git a/drivers/ddr/marvell/a38x/old/ddr3_a38x.h b/drivers/ddr/marvell/a38x/old/ddr3_a38x.h
new file mode 100644
index 0000000..1ed5174
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/ddr3_a38x.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _DDR3_A38X_H
+#define _DDR3_A38X_H
+
+#define MAX_INTERFACE_NUM 1
+#define MAX_BUS_NUM 5
+
+#include "ddr3_hws_hw_training_def.h"
+
+#define ECC_SUPPORT
+
+/* right now, we're not supporting this in mainline */
+#undef SUPPORT_STATIC_DUNIT_CONFIG
+
+/* Controler bus divider 1 for 32 bit, 2 for 64 bit */
+#define DDR_CONTROLLER_BUS_WIDTH_MULTIPLIER 1
+
+/* Tune internal training params values */
+#define TUNE_TRAINING_PARAMS_CK_DELAY 160
+#define TUNE_TRAINING_PARAMS_CK_DELAY_16 160
+#define TUNE_TRAINING_PARAMS_PFINGER 41
+#define TUNE_TRAINING_PARAMS_NFINGER 43
+#define TUNE_TRAINING_PARAMS_PHYREG3VAL 0xa
+
+#define MARVELL_BOARD MARVELL_BOARD_ID_BASE
+
+
+#define REG_DEVICE_SAR1_ADDR 0xe4204
+#define RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET 17
+#define RST2_CPU_DDR_CLOCK_SELECT_IN_MASK 0x1f
+
+/* DRAM Windows */
+#define REG_XBAR_WIN_5_CTRL_ADDR 0x20050
+#define REG_XBAR_WIN_5_BASE_ADDR 0x20054
+
+/* DRAM Windows */
+#define REG_XBAR_WIN_4_CTRL_ADDR 0x20040
+#define REG_XBAR_WIN_4_BASE_ADDR 0x20044
+#define REG_XBAR_WIN_4_REMAP_ADDR 0x20048
+#define REG_XBAR_WIN_7_REMAP_ADDR 0x20078
+#define REG_XBAR_WIN_16_CTRL_ADDR 0x200d0
+#define REG_XBAR_WIN_16_BASE_ADDR 0x200d4
+#define REG_XBAR_WIN_16_REMAP_ADDR 0x200dc
+#define REG_XBAR_WIN_19_CTRL_ADDR 0x200e8
+
+#define REG_FASTPATH_WIN_BASE_ADDR(win) (0x20180 + (0x8 * win))
+#define REG_FASTPATH_WIN_CTRL_ADDR(win) (0x20184 + (0x8 * win))
+
+/* SatR defined too change topology busWidth and ECC configuration */
+#define DDR_SATR_CONFIG_MASK_WIDTH 0x8
+#define DDR_SATR_CONFIG_MASK_ECC 0x10
+#define DDR_SATR_CONFIG_MASK_ECC_PUP 0x20
+
+#define REG_SAMPLE_RESET_HIGH_ADDR 0x18600
+
+#define MV_BOARD_REFCLK MV_BOARD_REFCLK_25MHZ
+
+/* Matrix enables DRAM modes (bus width/ECC) per boardId */
+#define TOPOLOGY_UPDATE_32BIT 0
+#define TOPOLOGY_UPDATE_32BIT_ECC 1
+#define TOPOLOGY_UPDATE_16BIT 2
+#define TOPOLOGY_UPDATE_16BIT_ECC 3
+#define TOPOLOGY_UPDATE_16BIT_ECC_PUP3 4
+#define TOPOLOGY_UPDATE { \
+ /* 32Bit, 32bit ECC, 16bit, 16bit ECC PUP4, 16bit ECC PUP3 */ \
+ {1, 1, 1, 1, 1}, /* RD_NAS_68XX_ID */ \
+ {1, 1, 1, 1, 1}, /* DB_68XX_ID */ \
+ {1, 0, 1, 0, 1}, /* RD_AP_68XX_ID */ \
+ {1, 0, 1, 0, 1}, /* DB_AP_68XX_ID */ \
+ {1, 0, 1, 0, 1}, /* DB_GP_68XX_ID */ \
+ {0, 0, 1, 1, 0}, /* DB_BP_6821_ID */ \
+ {1, 1, 1, 1, 1} /* DB_AMC_6820_ID */ \
+ };
+
+enum {
+ CPU_1066MHZ_DDR_400MHZ,
+ CPU_RESERVED_DDR_RESERVED0,
+ CPU_667MHZ_DDR_667MHZ,
+ CPU_800MHZ_DDR_800MHZ,
+ CPU_RESERVED_DDR_RESERVED1,
+ CPU_RESERVED_DDR_RESERVED2,
+ CPU_RESERVED_DDR_RESERVED3,
+ LAST_FREQ
+};
+
+#define ACTIVE_INTERFACE_MASK 0x1
+
+#endif /* _DDR3_A38X_H */
diff --git a/drivers/ddr/marvell/a38x/old/ddr3_a38x_mc_static.h b/drivers/ddr/marvell/a38x/old/ddr3_a38x_mc_static.h
new file mode 100644
index 0000000..b879a01
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/ddr3_a38x_mc_static.h
@@ -0,0 +1,226 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _DDR3_A38X_MC_STATIC_H
+#define _DDR3_A38X_MC_STATIC_H
+
+#include "ddr3_a38x.h"
+
+#ifdef SUPPORT_STATIC_DUNIT_CONFIG
+
+#ifdef CONFIG_CUSTOMER_BOARD_SUPPORT
+static struct reg_data ddr3_customer_800[] = {
+ /* parameters for customer board (based on 800MHZ) */
+ {0x1400, 0x7b00cc30, 0xffffffff},
+ {0x1404, 0x36301820, 0xffffffff},
+ {0x1408, 0x5415baab, 0xffffffff},
+ {0x140c, 0x38411def, 0xffffffff},
+ {0x1410, 0x18300000, 0xffffffff},
+ {0x1414, 0x00000700, 0xffffffff},
+ {0x1424, 0x0060f3ff, 0xffffffff},
+ {0x1428, 0x0011a940, 0xffffffff},
+ {0x142c, 0x28c5134, 0xffffffff},
+ {0x1474, 0x00000000, 0xffffffff},
+ {0x147c, 0x0000d771, 0xffffffff},
+ {0x1494, 0x00030000, 0xffffffff},
+ {0x149c, 0x00000300, 0xffffffff},
+ {0x14a8, 0x00000000, 0xffffffff},
+ {0x14cc, 0xbd09000d, 0xffffffff},
+ {0x1504, 0xfffffff1, 0xffffffff},
+ {0x150c, 0xffffffe5, 0xffffffff},
+ {0x1514, 0x00000000, 0xffffffff},
+ {0x151c, 0x00000000, 0xffffffff},
+ {0x1538, 0x00000b0b, 0xffffffff},
+ {0x153c, 0x00000c0c, 0xffffffff},
+ {0x15d0, 0x00000670, 0xffffffff},
+ {0x15d4, 0x00000046, 0xffffffff},
+ {0x15d8, 0x00000010, 0xffffffff},
+ {0x15dc, 0x00000000, 0xffffffff},
+ {0x15e0, 0x00000023, 0xffffffff},
+ {0x15e4, 0x00203c18, 0xffffffff},
+ {0x15ec, 0xf8000019, 0xffffffff},
+ {0x16a0, 0xcc000006, 0xffffffff}, /* Clock Delay */
+ {0xe4124, 0x08008073, 0xffffffff}, /* AVS BG default */
+ {0, 0, 0}
+};
+
+#else /* CONFIG_CUSTOMER_BOARD_SUPPORT */
+
+struct reg_data ddr3_a38x_933[MV_MAX_DDR3_STATIC_SIZE] = {
+ /* parameters for 933MHZ */
+ {0x1400, 0x7b00ce3a, 0xffffffff},
+ {0x1404, 0x36301820, 0xffffffff},
+ {0x1408, 0x7417eccf, 0xffffffff},
+ {0x140c, 0x3e421f98, 0xffffffff},
+ {0x1410, 0x1a300000, 0xffffffff},
+ {0x1414, 0x00000700, 0xffffffff},
+ {0x1424, 0x0060f3ff, 0xffffffff},
+ {0x1428, 0x0013ca50, 0xffffffff},
+ {0x142c, 0x028c5165, 0xffffffff},
+ {0x1474, 0x00000000, 0xffffffff},
+ {0x147c, 0x0000e871, 0xffffffff},
+ {0x1494, 0x00010000, 0xffffffff},
+ {0x149c, 0x00000001, 0xffffffff},
+ {0x14a8, 0x00000000, 0xffffffff},
+ {0x14cc, 0xbd09000d, 0xffffffff},
+ {0x1504, 0xffffffe1, 0xffffffff},
+ {0x150c, 0xffffffe5, 0xffffffff},
+ {0x1514, 0x00000000, 0xffffffff},
+ {0x151c, 0x00000000, 0xffffffff},
+ {0x1538, 0x00000d0d, 0xffffffff},
+ {0x153c, 0x00000d0d, 0xffffffff},
+ {0x15d0, 0x00000608, 0xffffffff},
+ {0x15d4, 0x00000044, 0xffffffff},
+ {0x15d8, 0x00000020, 0xffffffff},
+ {0x15dc, 0x00000000, 0xffffffff},
+ {0x15e0, 0x00000021, 0xffffffff},
+ {0x15e4, 0x00203c18, 0xffffffff},
+ {0x15ec, 0xf8000019, 0xffffffff},
+ {0x16a0, 0xcc000006, 0xffffffff}, /* Clock Delay */
+ {0xe4124, 0x08008073, 0xffffffff}, /* AVS BG default */
+ {0, 0, 0}
+};
+
+static struct reg_data ddr3_a38x_800[] = {
+ /* parameters for 800MHZ */
+ {0x1400, 0x7b00cc30, 0xffffffff},
+ {0x1404, 0x36301820, 0xffffffff},
+ {0x1408, 0x5415baab, 0xffffffff},
+ {0x140c, 0x38411def, 0xffffffff},
+ {0x1410, 0x18300000, 0xffffffff},
+ {0x1414, 0x00000700, 0xffffffff},
+ {0x1424, 0x0060f3ff, 0xffffffff},
+ {0x1428, 0x0011a940, 0xffffffff},
+ {0x142c, 0x28c5134, 0xffffffff},
+ {0x1474, 0x00000000, 0xffffffff},
+ {0x147c, 0x0000d771, 0xffffffff},
+ {0x1494, 0x00030000, 0xffffffff},
+ {0x149c, 0x00000300, 0xffffffff},
+ {0x14a8, 0x00000000, 0xffffffff},
+ {0x14cc, 0xbd09000d, 0xffffffff},
+ {0x1504, 0xfffffff1, 0xffffffff},
+ {0x150c, 0xffffffe5, 0xffffffff},
+ {0x1514, 0x00000000, 0xffffffff},
+ {0x151c, 0x00000000, 0xffffffff},
+ {0x1538, 0x00000b0b, 0xffffffff},
+ {0x153c, 0x00000c0c, 0xffffffff},
+ {0x15d0, 0x00000670, 0xffffffff},
+ {0x15d4, 0x00000046, 0xffffffff},
+ {0x15d8, 0x00000010, 0xffffffff},
+ {0x15dc, 0x00000000, 0xffffffff},
+ {0x15e0, 0x00000023, 0xffffffff},
+ {0x15e4, 0x00203c18, 0xffffffff},
+ {0x15ec, 0xf8000019, 0xffffffff},
+ {0x16a0, 0xcc000006, 0xffffffff}, /* Clock Delay */
+ {0xe4124, 0x08008073, 0xffffffff}, /* AVS BG default */
+ {0, 0, 0}
+};
+
+static struct reg_data ddr3_a38x_667[] = {
+ /* parameters for 667MHZ */
+ /* DDR SDRAM Configuration Register */
+ {0x1400, 0x7b00ca28, 0xffffffff},
+ /* Dunit Control Low Register - kw28 bit12 low (disable CLK1) */
+ {0x1404, 0x36301820, 0xffffffff},
+ /* DDR SDRAM Timing (Low) Register */
+ {0x1408, 0x43149997, 0xffffffff},
+ /* DDR SDRAM Timing (High) Register */
+ {0x140c, 0x38411bc7, 0xffffffff},
+ /* DDR SDRAM Address Control Register */
+ {0x1410, 0x14330000, 0xffffffff},
+ /* DDR SDRAM Open Pages Control Register */
+ {0x1414, 0x00000700, 0xffffffff},
+ /* Dunit Control High Register (2 :1 - bits 15:12 = 0xd) */
+ {0x1424, 0x0060f3ff, 0xffffffff},
+ /* Dunit Control High Register */
+ {0x1428, 0x000f8830, 0xffffffff},
+ /* Dunit Control High Register (2:1 - bit 29 = '1') */
+ {0x142c, 0x28c50f8, 0xffffffff},
+ {0x147c, 0x0000c671, 0xffffffff},
+ /* DDR SDRAM ODT Control (Low) Register */
+ {0x1494, 0x00030000, 0xffffffff},
+ /* DDR SDRAM ODT Control (High) Register, will be configured at WL */
+ {0x1498, 0x00000000, 0xffffffff},
+ /* DDR Dunit ODT Control Register */
+ {0x149c, 0x00000300, 0xffffffff},
+ {0x14a8, 0x00000000, 0xffffffff}, /* */
+ {0x14cc, 0xbd09000d, 0xffffffff}, /* */
+ {0x1474, 0x00000000, 0xffffffff},
+ /* Read Data Sample Delays Register */
+ {0x1538, 0x00000009, 0xffffffff},
+ /* Read Data Ready Delay Register */
+ {0x153c, 0x0000000c, 0xffffffff},
+ {0x1504, 0xfffffff1, 0xffffffff}, /* */
+ {0x150c, 0xffffffe5, 0xffffffff}, /* */
+ {0x1514, 0x00000000, 0xffffffff}, /* */
+ {0x151c, 0x0, 0xffffffff}, /* */
+ {0x15d0, 0x00000650, 0xffffffff}, /* MR0 */
+ {0x15d4, 0x00000046, 0xffffffff}, /* MR1 */
+ {0x15d8, 0x00000010, 0xffffffff}, /* MR2 */
+ {0x15dc, 0x00000000, 0xffffffff}, /* MR3 */
+ {0x15e0, 0x23, 0xffffffff}, /* */
+ {0x15e4, 0x00203c18, 0xffffffff}, /* ZQC Configuration Register */
+ {0x15ec, 0xf8000019, 0xffffffff}, /* DDR PHY */
+ {0x16a0, 0xcc000006, 0xffffffff}, /* Clock Delay */
+ {0xe4124, 0x08008073, 0xffffffff}, /* AVS BG default */
+ {0, 0, 0}
+};
+
+static struct reg_data ddr3_a38x_533[] = {
+ /* parameters for 533MHZ */
+ /* DDR SDRAM Configuration Register */
+ {0x1400, 0x7b00d040, 0xffffffff},
+ /* Dunit Control Low Register - kw28 bit12 low (disable CLK1) */
+ {0x1404, 0x36301820, 0xffffffff},
+ /* DDR SDRAM Timing (Low) Register */
+ {0x1408, 0x33137772, 0xffffffff},
+ /* DDR SDRAM Timing (High) Register */
+ {0x140c, 0x3841199f, 0xffffffff},
+ /* DDR SDRAM Address Control Register */
+ {0x1410, 0x10330000, 0xffffffff},
+ /* DDR SDRAM Open Pages Control Register */
+ {0x1414, 0x00000700, 0xffffffff},
+ /* Dunit Control High Register (2 :1 - bits 15:12 = 0xd) */
+ {0x1424, 0x0060f3ff, 0xffffffff},
+ /* Dunit Control High Register */
+ {0x1428, 0x000d6720, 0xffffffff},
+ /* Dunit Control High Register (2:1 - bit 29 = '1') */
+ {0x142c, 0x028c50c3, 0xffffffff},
+ {0x147c, 0x0000b571, 0xffffffff},
+ /* DDR SDRAM ODT Control (Low) Register */
+ {0x1494, 0x00030000, 0xffffffff},
+ /* DDR SDRAM ODT Control (High) Register, will be configured at WL */
+ {0x1498, 0x00000000, 0xffffffff},
+ /* DDR Dunit ODT Control Register */
+ {0x149c, 0x00000003, 0xffffffff},
+ {0x14a8, 0x00000000, 0xffffffff}, /* */
+ {0x14cc, 0xbd09000d, 0xffffffff}, /* */
+ {0x1474, 0x00000000, 0xffffffff},
+ /* Read Data Sample Delays Register */
+ {0x1538, 0x00000707, 0xffffffff},
+ /* Read Data Ready Delay Register */
+ {0x153c, 0x00000707, 0xffffffff},
+ {0x1504, 0xffffffe1, 0xffffffff}, /* */
+ {0x150c, 0xffffffe5, 0xffffffff}, /* */
+ {0x1514, 0x00000000, 0xffffffff}, /* */
+ {0x151c, 0x00000000, 0xffffffff}, /* */
+ {0x15d0, 0x00000630, 0xffffffff}, /* MR0 */
+ {0x15d4, 0x00000046, 0xffffffff}, /* MR1 */
+ {0x15d8, 0x00000008, 0xffffffff}, /* MR2 */
+ {0x15dc, 0x00000000, 0xffffffff}, /* MR3 */
+ {0x15e0, 0x00000023, 0xffffffff}, /* */
+ {0x15e4, 0x00203c18, 0xffffffff}, /* ZQC Configuration Register */
+ {0x15ec, 0xf8000019, 0xffffffff}, /* DDR PHY */
+ {0x16a0, 0xcc000006, 0xffffffff}, /* Clock Delay */
+ {0xe4124, 0x08008073, 0xffffffff}, /* AVS BG default */
+ {0, 0, 0}
+};
+
+#endif /* CONFIG_CUSTOMER_BOARD_SUPPORT */
+
+#endif /* SUPPORT_STATIC_DUNIT_CONFIG */
+
+#endif /* _DDR3_A38X_MC_STATIC_H */
diff --git a/drivers/ddr/marvell/a38x/old/ddr3_a38x_topology.h b/drivers/ddr/marvell/a38x/old/ddr3_a38x_topology.h
new file mode 100644
index 0000000..f27bbff7
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/ddr3_a38x_topology.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _DDR3_A38X_TOPOLOGY_H
+#define _DDR3_A38X_TOPOLOGY_H
+
+#include "ddr_topology_def.h"
+
+/* Bus mask variants */
+#define BUS_MASK_32BIT 0xf
+#define BUS_MASK_32BIT_ECC 0x1f
+#define BUS_MASK_16BIT 0x3
+#define BUS_MASK_16BIT_ECC 0x13
+#define BUS_MASK_16BIT_ECC_PUP3 0xb
+
+#define DYNAMIC_CS_SIZE_CONFIG
+#define DISABLE_L2_FILTERING_DURING_DDR_TRAINING
+
+#endif /* _DDR3_A38X_TOPOLOGY_H */
diff --git a/drivers/ddr/marvell/a38x/old/ddr3_a38x_training.c b/drivers/ddr/marvell/a38x/old/ddr3_a38x_training.c
new file mode 100644
index 0000000..edb2e70
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/ddr3_a38x_training.c
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <i2c.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+#include "ddr3_init.h"
+
+/*
+ * Name: ddr3_tip_init_silicon
+ * Desc: initiate silicon parameters
+ * Args:
+ * Notes:
+ * Returns: required value
+ */
+int ddr3_silicon_init(void)
+{
+ int status;
+ static int init_done;
+
+ if (init_done == 1)
+ return MV_OK;
+
+ status = ddr3_tip_init_a38x(0, 0);
+ if (MV_OK != status) {
+ printf("DDR3 A38x silicon init - FAILED 0x%x\n", status);
+ return status;
+ }
+
+ init_done = 1;
+
+ return MV_OK;
+}
diff --git a/drivers/ddr/marvell/a38x/old/ddr3_debug.c b/drivers/ddr/marvell/a38x/old/ddr3_debug.c
new file mode 100644
index 0000000..d559a84
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/ddr3_debug.c
@@ -0,0 +1,1546 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <i2c.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+#include "ddr3_init.h"
+
+#if !defined(CONFIG_DDR_IMMUTABLE_DEBUG_SETTINGS)
+u8 is_reg_dump = 0;
+u8 debug_pbs = DEBUG_LEVEL_ERROR;
+#endif
+
+/*
+ * API to change flags outside of the lib
+ */
+#if !defined(SILENT_LIB) && !defined(CONFIG_DDR_IMMUTABLE_DEBUG_SETTINGS)
+/* Debug flags for other Training modules */
+u8 debug_training_static = DEBUG_LEVEL_ERROR;
+u8 debug_training = DEBUG_LEVEL_ERROR;
+u8 debug_leveling = DEBUG_LEVEL_ERROR;
+u8 debug_centralization = DEBUG_LEVEL_ERROR;
+u8 debug_training_ip = DEBUG_LEVEL_ERROR;
+u8 debug_training_bist = DEBUG_LEVEL_ERROR;
+u8 debug_training_hw_alg = DEBUG_LEVEL_ERROR;
+u8 debug_training_access = DEBUG_LEVEL_ERROR;
+u8 debug_training_a38x = DEBUG_LEVEL_ERROR;
+
+void ddr3_hws_set_log_level(enum ddr_lib_debug_block block, u8 level)
+{
+ switch (block) {
+ case DEBUG_BLOCK_STATIC:
+ debug_training_static = level;
+ break;
+ case DEBUG_BLOCK_TRAINING_MAIN:
+ debug_training = level;
+ break;
+ case DEBUG_BLOCK_LEVELING:
+ debug_leveling = level;
+ break;
+ case DEBUG_BLOCK_CENTRALIZATION:
+ debug_centralization = level;
+ break;
+ case DEBUG_BLOCK_PBS:
+ debug_pbs = level;
+ break;
+ case DEBUG_BLOCK_ALG:
+ debug_training_hw_alg = level;
+ break;
+ case DEBUG_BLOCK_DEVICE:
+ debug_training_a38x = level;
+ break;
+ case DEBUG_BLOCK_ACCESS:
+ debug_training_access = level;
+ break;
+ case DEBUG_STAGES_REG_DUMP:
+ if (level == DEBUG_LEVEL_TRACE)
+ is_reg_dump = 1;
+ else
+ is_reg_dump = 0;
+ break;
+ case DEBUG_BLOCK_ALL:
+ default:
+ debug_training_static = level;
+ debug_training = level;
+ debug_leveling = level;
+ debug_centralization = level;
+ debug_pbs = level;
+ debug_training_hw_alg = level;
+ debug_training_access = level;
+ debug_training_a38x = level;
+ }
+}
+#else
+void ddr3_hws_set_log_level(enum ddr_lib_debug_block block, u8 level)
+{
+ return;
+}
+#endif
+
+struct hws_tip_config_func_db config_func_info[HWS_MAX_DEVICE_NUM];
+
+#if 0
+static u8 is_validate_window_per_if = 0;
+static u8 is_validate_window_per_pup = 0;
+static u8 sweep_cnt = 1;
+#endif
+
+static struct hws_xsb_info xsb_info[HWS_MAX_DEVICE_NUM];
+
+/*
+ * Dump Dunit & Phy registers
+ */
+int ddr3_tip_reg_dump(u32 dev_num)
+{
+ u32 if_id, reg_addr, data_value, bus_id;
+ u32 read_data[MAX_INTERFACE_NUM];
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ printf("-- dunit registers --\n");
+ for (reg_addr = 0x1400; reg_addr < 0x19f0; reg_addr += 4) {
+ printf("0x%x ", reg_addr);
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ CHECK_STATUS(ddr3_tip_if_read
+ (dev_num, ACCESS_TYPE_UNICAST,
+ if_id, reg_addr, read_data,
+ MASK_ALL_BITS));
+ printf("0x%x ", read_data[if_id]);
+ }
+ printf("\n");
+ }
+
+ printf("-- Phy registers --\n");
+ for (reg_addr = 0; reg_addr <= 0xff; reg_addr++) {
+ printf("0x%x ", reg_addr);
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ for (bus_id = 0;
+ bus_id < tm->num_of_bus_per_interface;
+ bus_id++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, bus_id);
+ CHECK_STATUS(ddr3_tip_bus_read
+ (dev_num, if_id,
+ ACCESS_TYPE_UNICAST, bus_id,
+ DDR_PHY_DATA, reg_addr,
+ &data_value));
+ printf("0x%x ", data_value);
+ }
+ for (bus_id = 0;
+ bus_id < tm->num_of_bus_per_interface;
+ bus_id++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, bus_id);
+ CHECK_STATUS(ddr3_tip_bus_read
+ (dev_num, if_id,
+ ACCESS_TYPE_UNICAST, bus_id,
+ DDR_PHY_CONTROL, reg_addr,
+ &data_value));
+ printf("0x%x ", data_value);
+ }
+ }
+ printf("\n");
+ }
+
+ return MV_OK;
+}
+
+/*
+ * Register access func registration
+ */
+int ddr3_tip_init_config_func(u32 dev_num,
+ struct hws_tip_config_func_db *config_func)
+{
+ if (config_func == NULL)
+ return MV_BAD_PARAM;
+
+ memcpy(&config_func_info[dev_num], config_func,
+ sizeof(struct hws_tip_config_func_db));
+
+ return MV_OK;
+}
+
+/*
+ * Get training result info pointer
+ */
+enum hws_result *ddr3_tip_get_result_ptr(u32 stage)
+{
+ return training_result[stage];
+}
+
+/*
+ * Device info read
+ */
+int ddr3_tip_get_device_info(u32 dev_num, struct ddr3_device_info *info_ptr)
+{
+ if (config_func_info[dev_num].tip_get_device_info_func != NULL) {
+ return config_func_info[dev_num].
+ tip_get_device_info_func((u8) dev_num, info_ptr);
+ }
+
+ return MV_FAIL;
+}
+
+#ifndef EXCLUDE_SWITCH_DEBUG
+/*
+ * Convert freq to character string
+ */
+static char *convert_freq(enum hws_ddr_freq freq)
+{
+ switch (freq) {
+ case DDR_FREQ_LOW_FREQ:
+ return "DDR_FREQ_LOW_FREQ";
+ case DDR_FREQ_400:
+ return "400";
+
+ case DDR_FREQ_533:
+ return "533";
+ case DDR_FREQ_667:
+ return "667";
+
+ case DDR_FREQ_800:
+ return "800";
+
+ case DDR_FREQ_933:
+ return "933";
+
+ case DDR_FREQ_1066:
+ return "1066";
+ case DDR_FREQ_311:
+ return "311";
+
+ case DDR_FREQ_333:
+ return "333";
+
+ case DDR_FREQ_467:
+ return "467";
+
+ case DDR_FREQ_850:
+ return "850";
+
+ case DDR_FREQ_900:
+ return "900";
+
+ case DDR_FREQ_360:
+ return "DDR_FREQ_360";
+
+ case DDR_FREQ_1000:
+ return "DDR_FREQ_1000";
+ default:
+ return "Unknown Frequency";
+ }
+}
+
+/*
+ * Convert device ID to character string
+ */
+static char *convert_dev_id(u32 dev_id)
+{
+ switch (dev_id) {
+ case 0x6800:
+ return "A38xx";
+ case 0x6900:
+ return "A39XX";
+ case 0xf400:
+ return "AC3";
+ case 0xfc00:
+ return "BC2";
+
+ default:
+ return "Unknown Device";
+ }
+}
+
+/*
+ * Convert device ID to character string
+ */
+static char *convert_mem_size(u32 dev_id)
+{
+ switch (dev_id) {
+ case 0:
+ return "512 MB";
+ case 1:
+ return "1 GB";
+ case 2:
+ return "2 GB";
+ case 3:
+ return "4 GB";
+ case 4:
+ return "8 GB";
+
+ default:
+ return "wrong mem size";
+ }
+}
+
+int print_device_info(u8 dev_num)
+{
+ struct ddr3_device_info info_ptr;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ CHECK_STATUS(ddr3_tip_get_device_info(dev_num, &info_ptr));
+ printf("=== DDR setup START===\n");
+ printf("\tDevice ID: %s\n", convert_dev_id(info_ptr.device_id));
+ printf("\tDDR3 CK delay: %d\n", info_ptr.ck_delay);
+ print_topology(tm);
+ printf("=== DDR setup END===\n");
+
+ return MV_OK;
+}
+
+#if 0
+void hws_ddr3_tip_sweep_test(int enable)
+{
+ if (enable) {
+ is_validate_window_per_if = 1;
+ is_validate_window_per_pup = 1;
+ debug_training = DEBUG_LEVEL_TRACE;
+ } else {
+ is_validate_window_per_if = 0;
+ is_validate_window_per_pup = 0;
+ }
+}
+#endif
+#endif
+
+char *ddr3_tip_convert_tune_result(enum hws_result tune_result)
+{
+ switch (tune_result) {
+ case TEST_FAILED:
+ return "FAILED";
+ case TEST_SUCCESS:
+ return "PASS";
+ case NO_TEST_DONE:
+ return "NOT COMPLETED";
+ default:
+ return "Un-KNOWN";
+ }
+}
+
+/*
+ * Print log info
+ */
+int ddr3_tip_print_log(u32 dev_num, u32 mem_addr)
+{
+ u32 if_id = 0;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+#if 0
+#ifndef EXCLUDE_SWITCH_DEBUG
+ if ((is_validate_window_per_if != 0) ||
+ (is_validate_window_per_pup != 0)) {
+ u32 is_pup_log = 0;
+ enum hws_ddr_freq freq;
+
+ freq = tm->interface_params[first_active_if].memory_freq;
+
+ is_pup_log = (is_validate_window_per_pup != 0) ? 1 : 0;
+ printf("===VALIDATE WINDOW LOG START===\n");
+ printf("DDR Frequency: %s ======\n", convert_freq(freq));
+ /* print sweep windows */
+ ddr3_tip_run_sweep_test(dev_num, sweep_cnt, 1, is_pup_log);
+ ddr3_tip_run_sweep_test(dev_num, sweep_cnt, 0, is_pup_log);
+ ddr3_tip_print_all_pbs_result(dev_num);
+ ddr3_tip_print_wl_supp_result(dev_num);
+ printf("===VALIDATE WINDOW LOG END ===\n");
+ CHECK_STATUS(ddr3_tip_restore_dunit_regs(dev_num));
+ ddr3_tip_reg_dump(dev_num);
+ }
+#endif
+#endif
+
+ /* return early if we won't print anything anyway */
+ if (
+#if defined(SILENT_LIB)
+ 1 ||
+#endif
+ debug_training < DEBUG_LEVEL_INFO) {
+ return MV_OK;
+ }
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("IF %d Status:\n", if_id));
+
+ if (mask_tune_func & INIT_CONTROLLER_MASK_BIT) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("\tInit Controller: %s\n",
+ ddr3_tip_convert_tune_result
+ (training_result[INIT_CONTROLLER]
+ [if_id])));
+ }
+ if (mask_tune_func & SET_LOW_FREQ_MASK_BIT) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("\tLow freq Config: %s\n",
+ ddr3_tip_convert_tune_result
+ (training_result[SET_LOW_FREQ]
+ [if_id])));
+ }
+ if (mask_tune_func & LOAD_PATTERN_MASK_BIT) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("\tLoad Pattern: %s\n",
+ ddr3_tip_convert_tune_result
+ (training_result[LOAD_PATTERN]
+ [if_id])));
+ }
+ if (mask_tune_func & SET_MEDIUM_FREQ_MASK_BIT) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("\tMedium freq Config: %s\n",
+ ddr3_tip_convert_tune_result
+ (training_result[SET_MEDIUM_FREQ]
+ [if_id])));
+ }
+ if (mask_tune_func & WRITE_LEVELING_MASK_BIT) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("\tWL: %s\n",
+ ddr3_tip_convert_tune_result
+ (training_result[WRITE_LEVELING]
+ [if_id])));
+ }
+ if (mask_tune_func & LOAD_PATTERN_2_MASK_BIT) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("\tLoad Pattern: %s\n",
+ ddr3_tip_convert_tune_result
+ (training_result[LOAD_PATTERN_2]
+ [if_id])));
+ }
+ if (mask_tune_func & READ_LEVELING_MASK_BIT) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("\tRL: %s\n",
+ ddr3_tip_convert_tune_result
+ (training_result[READ_LEVELING]
+ [if_id])));
+ }
+ if (mask_tune_func & WRITE_LEVELING_SUPP_MASK_BIT) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("\tWL Supp: %s\n",
+ ddr3_tip_convert_tune_result
+ (training_result[WRITE_LEVELING_SUPP]
+ [if_id])));
+ }
+ if (mask_tune_func & PBS_RX_MASK_BIT) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("\tPBS RX: %s\n",
+ ddr3_tip_convert_tune_result
+ (training_result[PBS_RX]
+ [if_id])));
+ }
+ if (mask_tune_func & PBS_TX_MASK_BIT) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("\tPBS TX: %s\n",
+ ddr3_tip_convert_tune_result
+ (training_result[PBS_TX]
+ [if_id])));
+ }
+ if (mask_tune_func & SET_TARGET_FREQ_MASK_BIT) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("\tTarget freq Config: %s\n",
+ ddr3_tip_convert_tune_result
+ (training_result[SET_TARGET_FREQ]
+ [if_id])));
+ }
+ if (mask_tune_func & WRITE_LEVELING_TF_MASK_BIT) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("\tWL TF: %s\n",
+ ddr3_tip_convert_tune_result
+ (training_result[WRITE_LEVELING_TF]
+ [if_id])));
+ }
+ if (mask_tune_func & READ_LEVELING_TF_MASK_BIT) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("\tRL TF: %s\n",
+ ddr3_tip_convert_tune_result
+ (training_result[READ_LEVELING_TF]
+ [if_id])));
+ }
+ if (mask_tune_func & WRITE_LEVELING_SUPP_TF_MASK_BIT) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("\tWL TF Supp: %s\n",
+ ddr3_tip_convert_tune_result
+ (training_result
+ [WRITE_LEVELING_SUPP_TF]
+ [if_id])));
+ }
+ if (mask_tune_func & CENTRALIZATION_RX_MASK_BIT) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("\tCentr RX: %s\n",
+ ddr3_tip_convert_tune_result
+ (training_result[CENTRALIZATION_RX]
+ [if_id])));
+ }
+ if (mask_tune_func & VREF_CALIBRATION_MASK_BIT) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("\tVREF_CALIBRATION: %s\n",
+ ddr3_tip_convert_tune_result
+ (training_result[VREF_CALIBRATION]
+ [if_id])));
+ }
+ if (mask_tune_func & CENTRALIZATION_TX_MASK_BIT) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("\tCentr TX: %s\n",
+ ddr3_tip_convert_tune_result
+ (training_result[CENTRALIZATION_TX]
+ [if_id])));
+ }
+ }
+
+ return MV_OK;
+}
+
+/*
+ * Print stability log info
+ */
+int ddr3_tip_print_stability_log(u32 dev_num)
+{
+ u8 if_id = 0, csindex = 0, bus_id = 0, idx = 0;
+ u32 reg_data;
+ u32 read_data[MAX_INTERFACE_NUM];
+ u32 max_cs = hws_ddr3_tip_max_cs_get();
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ /* Title print */
+ for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ printf("Title: I/F# , Tj, Calibration_n0, Calibration_p0, Calibration_n1, Calibration_p1, Calibration_n2, Calibration_p2,");
+ for (csindex = 0; csindex < max_cs; csindex++) {
+ printf("CS%d , ", csindex);
+ printf("\n");
+ VALIDATE_ACTIVE(tm->bus_act_mask, bus_id);
+ printf("VWTx, VWRx, WL_tot, WL_ADLL, WL_PH, RL_Tot, RL_ADLL, RL_PH, RL_Smp, Cen_tx, Cen_rx, Vref, DQVref,");
+ printf("\t\t");
+ for (idx = 0; idx < 11; idx++)
+ printf("PBSTx-Pad%d,", idx);
+ printf("\t\t");
+ for (idx = 0; idx < 11; idx++)
+ printf("PBSRx-Pad%d,", idx);
+ }
+ }
+ printf("\n");
+
+ /* Data print */
+ for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+
+ printf("Data: %d,%d,", if_id,
+ (config_func_info[dev_num].tip_get_temperature != NULL)
+ ? (config_func_info[dev_num].
+ tip_get_temperature(dev_num)) : (0));
+
+ CHECK_STATUS(ddr3_tip_if_read
+ (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x14c8,
+ read_data, MASK_ALL_BITS));
+ printf("%d,%d,", ((read_data[if_id] & 0x3f0) >> 4),
+ ((read_data[if_id] & 0xfc00) >> 10));
+ CHECK_STATUS(ddr3_tip_if_read
+ (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x17c8,
+ read_data, MASK_ALL_BITS));
+ printf("%d,%d,", ((read_data[if_id] & 0x3f0) >> 4),
+ ((read_data[if_id] & 0xfc00) >> 10));
+ CHECK_STATUS(ddr3_tip_if_read
+ (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x1dc8,
+ read_data, MASK_ALL_BITS));
+ printf("%d,%d,", ((read_data[if_id] & 0x3f0000) >> 16),
+ ((read_data[if_id] & 0xfc00000) >> 22));
+
+ for (csindex = 0; csindex < max_cs; csindex++) {
+ printf("CS%d , ", csindex);
+ for (bus_id = 0; bus_id < MAX_BUS_NUM; bus_id++) {
+ printf("\n");
+ VALIDATE_ACTIVE(tm->bus_act_mask, bus_id);
+ ddr3_tip_bus_read(dev_num, if_id,
+ ACCESS_TYPE_UNICAST,
+ bus_id, DDR_PHY_DATA,
+ RESULT_DB_PHY_REG_ADDR +
+ csindex, ®_data);
+ printf("%d,%d,", (reg_data & 0x1f),
+ ((reg_data & 0x3e0) >> 5));
+ /* WL */
+ ddr3_tip_bus_read(dev_num, if_id,
+ ACCESS_TYPE_UNICAST,
+ bus_id, DDR_PHY_DATA,
+ WL_PHY_REG +
+ csindex * 4, ®_data);
+ printf("%d,%d,%d,",
+ (reg_data & 0x1f) +
+ ((reg_data & 0x1c0) >> 6) * 32,
+ (reg_data & 0x1f),
+ (reg_data & 0x1c0) >> 6);
+ /* RL */
+ CHECK_STATUS(ddr3_tip_if_read
+ (dev_num, ACCESS_TYPE_UNICAST,
+ if_id,
+ READ_DATA_SAMPLE_DELAY,
+ read_data, MASK_ALL_BITS));
+ read_data[if_id] =
+ (read_data[if_id] &
+ (0xf << (4 * csindex))) >>
+ (4 * csindex);
+ ddr3_tip_bus_read(dev_num, if_id,
+ ACCESS_TYPE_UNICAST, bus_id,
+ DDR_PHY_DATA,
+ RL_PHY_REG + csindex * 4,
+ ®_data);
+ printf("%d,%d,%d,%d,",
+ (reg_data & 0x1f) +
+ ((reg_data & 0x1c0) >> 6) * 32 +
+ read_data[if_id] * 64,
+ (reg_data & 0x1f),
+ ((reg_data & 0x1c0) >> 6),
+ read_data[if_id]);
+ /* Centralization */
+ ddr3_tip_bus_read(dev_num, if_id,
+ ACCESS_TYPE_UNICAST, bus_id,
+ DDR_PHY_DATA,
+ WRITE_CENTRALIZATION_PHY_REG
+ + csindex * 4, ®_data);
+ printf("%d,", (reg_data & 0x3f));
+ ddr3_tip_bus_read(dev_num, if_id,
+ ACCESS_TYPE_UNICAST, bus_id,
+ DDR_PHY_DATA,
+ READ_CENTRALIZATION_PHY_REG
+ + csindex * 4, ®_data);
+ printf("%d,", (reg_data & 0x1f));
+ /* Vref */
+ ddr3_tip_bus_read(dev_num, if_id,
+ ACCESS_TYPE_UNICAST, bus_id,
+ DDR_PHY_DATA,
+ PAD_CONFIG_PHY_REG,
+ ®_data);
+ printf("%d,", (reg_data & 0x7));
+ /* DQVref */
+ /* Need to add the Read Function from device */
+ printf("%d,", 0);
+ printf("\t\t");
+ for (idx = 0; idx < 11; idx++) {
+ ddr3_tip_bus_read(dev_num, if_id,
+ ACCESS_TYPE_UNICAST,
+ bus_id, DDR_PHY_DATA,
+ 0xd0 +
+ 12 * csindex +
+ idx, ®_data);
+ printf("%d,", (reg_data & 0x3f));
+ }
+ printf("\t\t");
+ for (idx = 0; idx < 11; idx++) {
+ ddr3_tip_bus_read(dev_num, if_id,
+ ACCESS_TYPE_UNICAST,
+ bus_id, DDR_PHY_DATA,
+ 0x10 +
+ 16 * csindex +
+ idx, ®_data);
+ printf("%d,", (reg_data & 0x3f));
+ }
+ printf("\t\t");
+ for (idx = 0; idx < 11; idx++) {
+ ddr3_tip_bus_read(dev_num, if_id,
+ ACCESS_TYPE_UNICAST,
+ bus_id, DDR_PHY_DATA,
+ 0x50 +
+ 16 * csindex +
+ idx, ®_data);
+ printf("%d,", (reg_data & 0x3f));
+ }
+ }
+ }
+ }
+ printf("\n");
+
+ return MV_OK;
+}
+
+/*
+ * Register XSB information
+ */
+int ddr3_tip_register_xsb_info(u32 dev_num, struct hws_xsb_info *xsb_info_table)
+{
+ memcpy(&xsb_info[dev_num], xsb_info_table, sizeof(struct hws_xsb_info));
+ return MV_OK;
+}
+
+/*
+ * Read ADLL Value
+ */
+int read_adll_value(u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
+ int reg_addr, u32 mask)
+{
+ u32 data_value;
+ u32 if_id = 0, bus_id = 0;
+ u32 dev_num = 0;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ /*
+ * multi CS support - reg_addr is calucalated in calling function
+ * with CS offset
+ */
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ for (bus_id = 0; bus_id < tm->num_of_bus_per_interface;
+ bus_id++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, bus_id);
+ CHECK_STATUS(ddr3_tip_bus_read(dev_num, if_id,
+ ACCESS_TYPE_UNICAST,
+ bus_id,
+ DDR_PHY_DATA, reg_addr,
+ &data_value));
+ pup_values[if_id *
+ tm->num_of_bus_per_interface + bus_id] =
+ data_value & mask;
+ }
+ }
+
+ return 0;
+}
+
+/*
+ * Write ADLL Value
+ */
+int write_adll_value(u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
+ int reg_addr)
+{
+ u32 if_id = 0, bus_id = 0;
+ u32 dev_num = 0, data;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ /*
+ * multi CS support - reg_addr is calucalated in calling function
+ * with CS offset
+ */
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ for (bus_id = 0; bus_id < tm->num_of_bus_per_interface;
+ bus_id++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, bus_id);
+ data = pup_values[if_id *
+ tm->num_of_bus_per_interface +
+ bus_id];
+ CHECK_STATUS(ddr3_tip_bus_write(dev_num,
+ ACCESS_TYPE_UNICAST,
+ if_id,
+ ACCESS_TYPE_UNICAST,
+ bus_id, DDR_PHY_DATA,
+ reg_addr, data));
+ }
+ }
+
+ return 0;
+}
+
+#ifndef EXCLUDE_SWITCH_DEBUG
+u32 rl_version = 1; /* 0 - old RL machine */
+struct hws_tip_config_func_db config_func_info[HWS_MAX_DEVICE_NUM];
+u32 start_xsb_offset = 0;
+u8 is_rl_old = 0;
+u8 is_freq_old = 0;
+u8 is_dfs_disabled = 0;
+u32 default_centrlization_value = 0x12;
+u32 vref = 0x4;
+u32 activate_select_before_run_alg = 1, activate_deselect_after_run_alg = 1,
+ rl_test = 0, reset_read_fifo = 0;
+int debug_acc = 0;
+u32 ctrl_sweepres[ADLL_LENGTH][MAX_INTERFACE_NUM][MAX_BUS_NUM];
+u32 ctrl_adll[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM];
+u8 cs_mask_reg[] = {
+ 0, 4, 8, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+u32 xsb_test_table[][8] = {
+ {0x00000000, 0x11111111, 0x22222222, 0x33333333, 0x44444444, 0x55555555,
+ 0x66666666, 0x77777777},
+ {0x88888888, 0x99999999, 0xaaaaaaaa, 0xbbbbbbbb, 0xcccccccc, 0xdddddddd,
+ 0xeeeeeeee, 0xffffffff},
+ {0x00000000, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
+ 0x00000000, 0xffffffff},
+ {0x00000000, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
+ 0x00000000, 0xffffffff},
+ {0x00000000, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
+ 0x00000000, 0xffffffff},
+ {0x00000000, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
+ 0x00000000, 0xffffffff},
+ {0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff},
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000},
+ {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000000, 0xffffffff,
+ 0xffffffff, 0xffffffff}
+};
+
+#if 0
+static int ddr3_tip_access_atr(u32 dev_num, u32 flag_id, u32 value, u32 **ptr);
+#endif
+
+int ddr3_tip_print_adll(void)
+{
+ u32 bus_cnt = 0, if_id, data_p1, data_p2, ui_data3, dev_num = 0;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ for (bus_cnt = 0; bus_cnt < GET_TOPOLOGY_NUM_OF_BUSES();
+ bus_cnt++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, bus_cnt);
+ CHECK_STATUS(ddr3_tip_bus_read
+ (dev_num, if_id,
+ ACCESS_TYPE_UNICAST, bus_cnt,
+ DDR_PHY_DATA, 0x1, &data_p1));
+ CHECK_STATUS(ddr3_tip_bus_read
+ (dev_num, if_id, ACCESS_TYPE_UNICAST,
+ bus_cnt, DDR_PHY_DATA, 0x2, &data_p2));
+ CHECK_STATUS(ddr3_tip_bus_read
+ (dev_num, if_id, ACCESS_TYPE_UNICAST,
+ bus_cnt, DDR_PHY_DATA, 0x3, &ui_data3));
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
+ (" IF %d bus_cnt %d phy_reg_1_data 0x%x phy_reg_2_data 0x%x phy_reg_3_data 0x%x\n",
+ if_id, bus_cnt, data_p1, data_p2,
+ ui_data3));
+ }
+ }
+
+ return MV_OK;
+}
+
+#if 0
+/*
+ * Set attribute value
+ */
+int ddr3_tip_set_atr(u32 dev_num, u32 flag_id, u32 value)
+{
+ int ret;
+ u32 *ptr_flag = NULL;
+
+ ret = ddr3_tip_access_atr(dev_num, flag_id, value, &ptr_flag);
+ if (ptr_flag != NULL) {
+ printf("ddr3_tip_set_atr Flag ID 0x%x value is set to 0x%x (was 0x%x)\n",
+ flag_id, value, *ptr_flag);
+ *ptr_flag = value;
+ } else {
+ printf("ddr3_tip_set_atr Flag ID 0x%x value is set to 0x%x\n",
+ flag_id, value);
+ }
+
+ return ret;
+}
+
+/*
+ * Access attribute
+ */
+static int ddr3_tip_access_atr(u32 dev_num, u32 flag_id, u32 value, u32 **ptr)
+{
+ u32 tmp_val = 0, if_id = 0, pup_id = 0;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ *ptr = NULL;
+
+ switch (flag_id) {
+ case 0:
+ *ptr = (u32 *)&(tm->if_act_mask);
+ break;
+
+ case 0x1:
+ *ptr = (u32 *)&mask_tune_func;
+ break;
+
+ case 0x2:
+ *ptr = (u32 *)&low_freq;
+ break;
+
+ case 0x3:
+ *ptr = (u32 *)&medium_freq;
+ break;
+
+ case 0x4:
+ *ptr = (u32 *)&generic_init_controller;
+ break;
+
+ case 0x5:
+ *ptr = (u32 *)&rl_version;
+ break;
+
+ case 0x8:
+ *ptr = (u32 *)&start_xsb_offset;
+ break;
+
+ case 0x20:
+ *ptr = (u32 *)&is_rl_old;
+ break;
+
+ case 0x21:
+ *ptr = (u32 *)&is_freq_old;
+ break;
+
+ case 0x23:
+ *ptr = (u32 *)&is_dfs_disabled;
+ break;
+
+ case 0x24:
+ *ptr = (u32 *)&is_pll_before_init;
+ break;
+
+ case 0x25:
+ *ptr = (u32 *)&is_adll_calib_before_init;
+ break;
+#ifdef STATIC_ALGO_SUPPORT
+ case 0x26:
+ *ptr = (u32 *)&(silicon_delay[0]);
+ break;
+
+ case 0x27:
+ *ptr = (u32 *)&wl_debug_delay;
+ break;
+#endif
+ case 0x28:
+ *ptr = (u32 *)&is_tune_result;
+ break;
+
+ case 0x29:
+ *ptr = (u32 *)&is_validate_window_per_if;
+ break;
+
+ case 0x2a:
+ *ptr = (u32 *)&is_validate_window_per_pup;
+ break;
+
+ case 0x30:
+ *ptr = (u32 *)&sweep_cnt;
+ break;
+
+ case 0x31:
+ *ptr = (u32 *)&is_bist_reset_bit;
+ break;
+
+ case 0x32:
+ *ptr = (u32 *)&is_dfs_in_init;
+ break;
+
+ case 0x33:
+ *ptr = (u32 *)&p_finger;
+ break;
+
+ case 0x34:
+ *ptr = (u32 *)&n_finger;
+ break;
+
+ case 0x35:
+ *ptr = (u32 *)&init_freq;
+ break;
+
+ case 0x36:
+ *ptr = (u32 *)&(freq_val[DDR_FREQ_LOW_FREQ]);
+ break;
+
+ case 0x37:
+ *ptr = (u32 *)&start_pattern;
+ break;
+
+ case 0x38:
+ *ptr = (u32 *)&end_pattern;
+ break;
+
+ case 0x39:
+ *ptr = (u32 *)&phy_reg0_val;
+ break;
+
+ case 0x4a:
+ *ptr = (u32 *)&phy_reg1_val;
+ break;
+
+ case 0x4b:
+ *ptr = (u32 *)&phy_reg2_val;
+ break;
+
+ case 0x4c:
+ *ptr = (u32 *)&phy_reg3_val;
+ break;
+
+ case 0x4e:
+ *ptr = (u32 *)&sweep_pattern;
+ break;
+
+ case 0x50:
+ *ptr = (u32 *)&is_rzq6;
+ break;
+
+ case 0x51:
+ *ptr = (u32 *)&znri_data_phy_val;
+ break;
+
+ case 0x52:
+ *ptr = (u32 *)&zpri_data_phy_val;
+ break;
+
+ case 0x53:
+ *ptr = (u32 *)&finger_test;
+ break;
+
+ case 0x54:
+ *ptr = (u32 *)&n_finger_start;
+ break;
+
+ case 0x55:
+ *ptr = (u32 *)&n_finger_end;
+ break;
+
+ case 0x56:
+ *ptr = (u32 *)&p_finger_start;
+ break;
+
+ case 0x57:
+ *ptr = (u32 *)&p_finger_end;
+ break;
+
+ case 0x58:
+ *ptr = (u32 *)&p_finger_step;
+ break;
+
+ case 0x59:
+ *ptr = (u32 *)&n_finger_step;
+ break;
+
+ case 0x5a:
+ *ptr = (u32 *)&znri_ctrl_phy_val;
+ break;
+
+ case 0x5b:
+ *ptr = (u32 *)&zpri_ctrl_phy_val;
+ break;
+
+ case 0x5c:
+ *ptr = (u32 *)&is_reg_dump;
+ break;
+
+ case 0x5d:
+ *ptr = (u32 *)&vref;
+ break;
+
+ case 0x5e:
+ *ptr = (u32 *)&mode2_t;
+ break;
+
+ case 0x5f:
+ *ptr = (u32 *)&xsb_validate_type;
+ break;
+
+ case 0x60:
+ *ptr = (u32 *)&xsb_validation_base_address;
+ break;
+
+ case 0x67:
+ *ptr = (u32 *)&activate_select_before_run_alg;
+ break;
+
+ case 0x68:
+ *ptr = (u32 *)&activate_deselect_after_run_alg;
+ break;
+
+ case 0x69:
+ *ptr = (u32 *)&odt_additional;
+ break;
+
+ case 0x70:
+ *ptr = (u32 *)&debug_mode;
+ break;
+
+ case 0x71:
+ *ptr = (u32 *)&pbs_pattern;
+ break;
+
+ case 0x72:
+ *ptr = (u32 *)&delay_enable;
+ break;
+
+ case 0x73:
+ *ptr = (u32 *)&ck_delay;
+ break;
+
+ case 0x74:
+ *ptr = (u32 *)&ck_delay_16;
+ break;
+
+ case 0x75:
+ *ptr = (u32 *)&ca_delay;
+ break;
+
+ case 0x100:
+ *ptr = (u32 *)&debug_dunit;
+ break;
+
+ case 0x101:
+ debug_acc = (int)value;
+ break;
+
+ case 0x102:
+ debug_training = (u8)value;
+ break;
+
+ case 0x103:
+ debug_training_bist = (u8)value;
+ break;
+
+ case 0x104:
+ debug_centralization = (u8)value;
+ break;
+
+ case 0x105:
+ debug_training_ip = (u8)value;
+ break;
+
+ case 0x106:
+ debug_leveling = (u8)value;
+ break;
+
+ case 0x107:
+ debug_pbs = (u8)value;
+ break;
+
+ case 0x108:
+ debug_training_static = (u8)value;
+ break;
+
+ case 0x109:
+ debug_training_access = (u8)value;
+ break;
+
+ case 0x112:
+ *ptr = &start_pattern;
+ break;
+
+ case 0x113:
+ *ptr = &end_pattern;
+ break;
+
+ default:
+ if ((flag_id >= 0x200) && (flag_id < 0x210)) {
+ if_id = flag_id - 0x200;
+ *ptr = (u32 *)&(tm->interface_params
+ [if_id].memory_freq);
+ } else if ((flag_id >= 0x210) && (flag_id < 0x220)) {
+ if_id = flag_id - 0x210;
+ *ptr = (u32 *)&(tm->interface_params
+ [if_id].speed_bin_index);
+ } else if ((flag_id >= 0x220) && (flag_id < 0x230)) {
+ if_id = flag_id - 0x220;
+ *ptr = (u32 *)&(tm->interface_params
+ [if_id].bus_width);
+ } else if ((flag_id >= 0x230) && (flag_id < 0x240)) {
+ if_id = flag_id - 0x230;
+ *ptr = (u32 *)&(tm->interface_params
+ [if_id].memory_size);
+ } else if ((flag_id >= 0x240) && (flag_id < 0x250)) {
+ if_id = flag_id - 0x240;
+ *ptr = (u32 *)&(tm->interface_params
+ [if_id].cas_l);
+ } else if ((flag_id >= 0x250) && (flag_id < 0x260)) {
+ if_id = flag_id - 0x250;
+ *ptr = (u32 *)&(tm->interface_params
+ [if_id].cas_wl);
+ } else if ((flag_id >= 0x270) && (flag_id < 0x2cf)) {
+ if_id = (flag_id - 0x270) / MAX_BUS_NUM;
+ pup_id = (flag_id - 0x270) % MAX_BUS_NUM;
+ *ptr = (u32 *)&(tm->interface_params[if_id].
+ as_bus_params[pup_id].is_ck_swap);
+ } else if ((flag_id >= 0x2d0) && (flag_id < 0x32f)) {
+ if_id = (flag_id - 0x2d0) / MAX_BUS_NUM;
+ pup_id = (flag_id - 0x2d0) % MAX_BUS_NUM;
+ *ptr = (u32 *)&(tm->interface_params[if_id].
+ as_bus_params[pup_id].is_dqs_swap);
+ } else if ((flag_id >= 0x330) && (flag_id < 0x38f)) {
+ if_id = (flag_id - 0x330) / MAX_BUS_NUM;
+ pup_id = (flag_id - 0x330) % MAX_BUS_NUM;
+ *ptr = (u32 *)&(tm->interface_params[if_id].
+ as_bus_params[pup_id].cs_bitmask);
+ } else if ((flag_id >= 0x390) && (flag_id < 0x3ef)) {
+ if_id = (flag_id - 0x390) / MAX_BUS_NUM;
+ pup_id = (flag_id - 0x390) % MAX_BUS_NUM;
+ *ptr = (u32 *)&(tm->interface_params
+ [if_id].as_bus_params
+ [pup_id].mirror_enable_bitmask);
+ } else if ((flag_id >= 0x500) && (flag_id <= 0x50f)) {
+ tmp_val = flag_id - 0x320;
+ *ptr = (u32 *)&(clamp_tbl[tmp_val]);
+ } else {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("flag_id out of boundary %d\n",
+ flag_id));
+ return MV_BAD_PARAM;
+ }
+ }
+
+ return MV_OK;
+}
+#endif
+
+#ifndef EXCLUDE_SWITCH_DEBUG
+/*
+ * Print ADLL
+ */
+int print_adll(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM])
+{
+ u32 i, j;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ for (j = 0; j < tm->num_of_bus_per_interface; j++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, j);
+ for (i = 0; i < MAX_INTERFACE_NUM; i++) {
+ printf("%d ,",
+ adll[i * tm->num_of_bus_per_interface + j]);
+ }
+ }
+ printf("\n");
+
+ return MV_OK;
+}
+#endif
+
+/* byte_index - only byte 0, 1, 2, or 3, oxff - test all bytes */
+static u32 ddr3_tip_compare(u32 if_id, u32 *p_src, u32 *p_dst,
+ u32 byte_index)
+{
+ u32 burst_cnt = 0, addr_offset, i_id;
+ int b_is_fail = 0;
+
+ addr_offset =
+ (byte_index ==
+ 0xff) ? (u32) 0xffffffff : (u32) (0xff << (byte_index * 8));
+ for (burst_cnt = 0; burst_cnt < EXT_ACCESS_BURST_LENGTH; burst_cnt++) {
+ if ((p_src[burst_cnt] & addr_offset) !=
+ (p_dst[burst_cnt] & addr_offset))
+ b_is_fail = 1;
+ }
+
+ if (b_is_fail == 1) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("IF %d exp: ", if_id));
+ for (i_id = 0; i_id <= MAX_INTERFACE_NUM - 1; i_id++) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("0x%8x ", p_src[i_id]));
+ }
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("\n_i_f %d rcv: ", if_id));
+ for (i_id = 0; i_id <= MAX_INTERFACE_NUM - 1; i_id++) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("(0x%8x ", p_dst[i_id]));
+ }
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR, ("\n "));
+ }
+
+ return b_is_fail;
+}
+
+/* test_type = 0-tx , 1-rx */
+int ddr3_tip_sweep_test(u32 dev_num, u32 test_type,
+ u32 mem_addr, u32 is_modify_adll,
+ u32 start_if, u32 end_if, u32 startpup, u32 endpup)
+{
+ u32 bus_cnt = 0, adll_val = 0, if_id, ui_prev_adll, ui_mask_bit,
+ end_adll, start_adll;
+ u32 reg_addr = 0;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ if (test_type == 0) {
+ reg_addr = 1;
+ ui_mask_bit = 0x3f;
+ start_adll = 0;
+ end_adll = ui_mask_bit;
+ } else {
+ reg_addr = 3;
+ ui_mask_bit = 0x1f;
+ start_adll = 0;
+ end_adll = ui_mask_bit;
+ }
+
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("==============================\n"));
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("Test type %d (0-tx, 1-rx)\n", test_type));
+
+ for (if_id = start_if; if_id <= end_if; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ for (bus_cnt = startpup; bus_cnt < endpup; bus_cnt++) {
+ CHECK_STATUS(ddr3_tip_bus_read
+ (dev_num, if_id, ACCESS_TYPE_UNICAST,
+ bus_cnt, DDR_PHY_DATA, reg_addr,
+ &ui_prev_adll));
+
+ for (adll_val = start_adll; adll_val <= end_adll;
+ adll_val++) {
+ if (is_modify_adll == 1) {
+ CHECK_STATUS(ddr3_tip_bus_read_modify_write
+ (dev_num,
+ ACCESS_TYPE_UNICAST,
+ if_id, bus_cnt,
+ DDR_PHY_DATA, reg_addr,
+ adll_val, ui_mask_bit));
+ }
+ }
+ if (is_modify_adll == 1) {
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_UNICAST,
+ if_id, ACCESS_TYPE_UNICAST,
+ bus_cnt, DDR_PHY_DATA, reg_addr,
+ ui_prev_adll));
+ }
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("\n"));
+ }
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("\n"));
+ }
+
+ return MV_OK;
+}
+
+#ifndef EXCLUDE_SWITCH_DEBUG
+/*
+ * Sweep validation
+ */
+int ddr3_tip_run_sweep_test(int dev_num, u32 repeat_num, u32 direction,
+ u32 mode)
+{
+ u32 pup = 0, start_pup = 0, end_pup = 0;
+ u32 adll = 0;
+ u32 res[MAX_INTERFACE_NUM] = { 0 };
+ int if_id = 0;
+ u32 adll_value = 0;
+ int reg = (direction == 0) ? WRITE_CENTRALIZATION_PHY_REG :
+ READ_CENTRALIZATION_PHY_REG;
+ enum hws_access_type pup_access;
+ u32 cs;
+ u32 max_cs = hws_ddr3_tip_max_cs_get();
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ if (mode == 1) {
+ /* per pup */
+ start_pup = 0;
+ end_pup = tm->num_of_bus_per_interface - 1;
+ pup_access = ACCESS_TYPE_UNICAST;
+ } else {
+ start_pup = 0;
+ end_pup = 0;
+ pup_access = ACCESS_TYPE_MULTICAST;
+ }
+
+ for (cs = 0; cs < max_cs; cs++) {
+ for (adll = 0; adll < ADLL_LENGTH; adll++) {
+ for (if_id = 0;
+ if_id <= MAX_INTERFACE_NUM - 1;
+ if_id++) {
+ VALIDATE_ACTIVE
+ (tm->if_act_mask,
+ if_id);
+ for (pup = start_pup; pup <= end_pup; pup++) {
+ ctrl_sweepres[adll][if_id][pup] =
+ 0;
+ }
+ }
+ }
+
+ for (adll = 0; adll < (MAX_INTERFACE_NUM * MAX_BUS_NUM); adll++)
+ ctrl_adll[adll] = 0;
+ /* Save DQS value(after algorithm run) */
+ read_adll_value(ctrl_adll,
+ (reg + (cs * CS_REGISTER_ADDR_OFFSET)),
+ MASK_ALL_BITS);
+
+ /*
+ * Sweep ADLL from 0:31 on all I/F on all Pup and perform
+ * BIST on each stage.
+ */
+ for (pup = start_pup; pup <= end_pup; pup++) {
+ for (adll = 0; adll < ADLL_LENGTH; adll++) {
+ adll_value =
+ (direction == 0) ? (adll * 2) : adll;
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_MULTICAST, 0,
+ pup_access, pup, DDR_PHY_DATA,
+ reg + CS_REG_VALUE(cs),
+ adll_value));
+ hws_ddr3_run_bist(dev_num, sweep_pattern, res,
+ cs);
+ /* ddr3_tip_reset_fifo_ptr(dev_num); */
+ for (if_id = 0;
+ if_id <= MAX_INTERFACE_NUM - 1;
+ if_id++) {
+ VALIDATE_ACTIVE
+ (tm->if_act_mask,
+ if_id);
+ ctrl_sweepres[adll][if_id][pup]
+ = res[if_id];
+ if (mode == 1) {
+ CHECK_STATUS
+ (ddr3_tip_bus_write
+ (dev_num,
+ ACCESS_TYPE_UNICAST,
+ if_id,
+ ACCESS_TYPE_UNICAST,
+ pup,
+ DDR_PHY_DATA,
+ reg + CS_REG_VALUE(cs),
+ ctrl_adll[if_id *
+ cs *
+ tm->num_of_bus_per_interface
+ + pup]));
+ }
+ }
+ }
+ }
+ printf("Final, CS %d,%s, Sweep, Result, Adll,", cs,
+ ((direction == 0) ? "TX" : "RX"));
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ if (mode == 1) {
+ for (pup = start_pup; pup <= end_pup; pup++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, pup);
+ printf("I/F%d-PHY%d , ", if_id, pup);
+ }
+ } else {
+ printf("I/F%d , ", if_id);
+ }
+ }
+ printf("\n");
+
+ for (adll = 0; adll < ADLL_LENGTH; adll++) {
+ adll_value = (direction == 0) ? (adll * 2) : adll;
+ printf("Final,%s, Sweep, Result, %d ,",
+ ((direction == 0) ? "TX" : "RX"), adll_value);
+
+ for (if_id = 0;
+ if_id <= MAX_INTERFACE_NUM - 1;
+ if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ for (pup = start_pup; pup <= end_pup; pup++) {
+ printf("%d , ",
+ ctrl_sweepres[adll][if_id]
+ [pup]);
+ }
+ }
+ printf("\n");
+ }
+
+ /*
+ * Write back to the phy the Rx DQS value, we store in
+ * the beginning.
+ */
+ write_adll_value(ctrl_adll,
+ (reg + cs * CS_REGISTER_ADDR_OFFSET));
+ /* print adll results */
+ read_adll_value(ctrl_adll, (reg + cs * CS_REGISTER_ADDR_OFFSET),
+ MASK_ALL_BITS);
+ printf("%s, DQS, ADLL,,,", (direction == 0) ? "Tx" : "Rx");
+ print_adll(dev_num, ctrl_adll);
+ }
+ ddr3_tip_reset_fifo_ptr(dev_num);
+
+ return 0;
+}
+
+void print_topology(struct hws_topology_map *topology_db)
+{
+ u32 ui, uj;
+
+ printf("\tinterface_mask: 0x%x\n", topology_db->if_act_mask);
+ printf("\tNum Bus: %d\n", topology_db->num_of_bus_per_interface);
+ printf("\tbus_act_mask: 0x%x\n", topology_db->bus_act_mask);
+
+ for (ui = 0; ui < MAX_INTERFACE_NUM; ui++) {
+ VALIDATE_ACTIVE(topology_db->if_act_mask, ui);
+ printf("\n\tInterface ID: %d\n", ui);
+ printf("\t\tDDR Frequency: %s\n",
+ convert_freq(topology_db->
+ interface_params[ui].memory_freq));
+ printf("\t\tSpeed_bin: %d\n",
+ topology_db->interface_params[ui].speed_bin_index);
+ printf("\t\tBus_width: %d\n",
+ (4 << topology_db->interface_params[ui].bus_width));
+ printf("\t\tMem_size: %s\n",
+ convert_mem_size(topology_db->
+ interface_params[ui].memory_size));
+ printf("\t\tCAS-WL: %d\n",
+ topology_db->interface_params[ui].cas_wl);
+ printf("\t\tCAS-L: %d\n",
+ topology_db->interface_params[ui].cas_l);
+ printf("\t\tTemperature: %d\n",
+ topology_db->interface_params[ui].interface_temp);
+ printf("\n");
+ for (uj = 0; uj < 4; uj++) {
+ printf("\t\tBus %d parameters- CS Mask: 0x%x\t", uj,
+ topology_db->interface_params[ui].
+ as_bus_params[uj].cs_bitmask);
+ printf("Mirror: 0x%x\t",
+ topology_db->interface_params[ui].
+ as_bus_params[uj].mirror_enable_bitmask);
+ printf("DQS Swap is %s \t",
+ (topology_db->
+ interface_params[ui].as_bus_params[uj].
+ is_dqs_swap == 1) ? "enabled" : "disabled");
+ printf("Ck Swap:%s\t",
+ (topology_db->
+ interface_params[ui].as_bus_params[uj].
+ is_ck_swap == 1) ? "enabled" : "disabled");
+ printf("\n");
+ }
+ }
+}
+#endif
+
+/*
+ * Execute XSB Test transaction (rd/wr/both)
+ */
+int run_xsb_test(u32 dev_num, u32 mem_addr, u32 write_type,
+ u32 read_type, u32 burst_length)
+{
+ u32 seq = 0, if_id = 0, addr, cnt;
+ int ret = MV_OK, ret_tmp;
+ u32 data_read[MAX_INTERFACE_NUM];
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ addr = mem_addr;
+ for (cnt = 0; cnt <= burst_length; cnt++) {
+ seq = (seq + 1) % 8;
+ if (write_type != 0) {
+ CHECK_STATUS(ddr3_tip_ext_write
+ (dev_num, if_id, addr, 1,
+ xsb_test_table[seq]));
+ }
+ if (read_type != 0) {
+ CHECK_STATUS(ddr3_tip_ext_read
+ (dev_num, if_id, addr, 1,
+ data_read));
+ }
+ if ((read_type != 0) && (write_type != 0)) {
+ ret_tmp =
+ ddr3_tip_compare(if_id,
+ xsb_test_table[seq],
+ data_read,
+ 0xff);
+ addr += (EXT_ACCESS_BURST_LENGTH * 4);
+ ret = (ret != MV_OK) ? ret : ret_tmp;
+ }
+ }
+ }
+
+ return ret;
+}
+
+#else /*EXCLUDE_SWITCH_DEBUG */
+
+u32 rl_version = 1; /* 0 - old RL machine */
+u32 vref = 0x4;
+u32 start_xsb_offset = 0;
+u8 cs_mask_reg[] = {
+ 0, 4, 8, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+int run_xsb_test(u32 dev_num, u32 mem_addr, u32 write_type,
+ u32 read_type, u32 burst_length)
+{
+ return MV_OK;
+}
+
+#endif
diff --git a/drivers/ddr/marvell/a38x/old/ddr3_hws_hw_training.c b/drivers/ddr/marvell/a38x/old/ddr3_hws_hw_training.c
new file mode 100644
index 0000000..b9b0eb7
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/ddr3_hws_hw_training.c
@@ -0,0 +1,147 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <i2c.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+#include "ddr3_init.h"
+
+#define REG_READ_DATA_SAMPLE_DELAYS_ADDR 0x1538
+#define REG_READ_DATA_SAMPLE_DELAYS_MASK 0x1f
+#define REG_READ_DATA_SAMPLE_DELAYS_OFFS 8
+
+#define REG_READ_DATA_READY_DELAYS_ADDR 0x153c
+#define REG_READ_DATA_READY_DELAYS_MASK 0x1f
+#define REG_READ_DATA_READY_DELAYS_OFFS 8
+
+int ddr3_if_ecc_enabled(void)
+{
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ if (DDR3_IS_ECC_PUP4_MODE(tm->bus_act_mask) ||
+ DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask))
+ return 1;
+ else
+ return 0;
+}
+
+int ddr3_pre_algo_config(void)
+{
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ /* Set Bus3 ECC training mode */
+ if (DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask)) {
+ /* Set Bus3 ECC MUX */
+ CHECK_STATUS(ddr3_tip_if_write
+ (0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
+ REG_SDRAM_PINS_MUX, 0x100, 0x100));
+ }
+
+ /* Set regular ECC training mode (bus4 and bus 3) */
+ if ((DDR3_IS_ECC_PUP4_MODE(tm->bus_act_mask)) ||
+ (DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask))) {
+ /* Enable ECC Write MUX */
+ CHECK_STATUS(ddr3_tip_if_write
+ (0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
+ TRAINING_SW_2_REG, 0x100, 0x100));
+ /* General ECC enable */
+ CHECK_STATUS(ddr3_tip_if_write
+ (0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
+ REG_SDRAM_CONFIG_ADDR, 0x40000, 0x40000));
+ /* Disable Read Data ECC MUX */
+ CHECK_STATUS(ddr3_tip_if_write
+ (0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
+ TRAINING_SW_2_REG, 0x0, 0x2));
+ }
+
+ return MV_OK;
+}
+
+int ddr3_post_algo_config(void)
+{
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+ int status;
+
+ status = ddr3_post_run_alg();
+ if (MV_OK != status) {
+ printf("DDR3 Post Run Alg - FAILED 0x%x\n", status);
+ return status;
+ }
+
+ /* Un_set ECC training mode */
+ if ((DDR3_IS_ECC_PUP4_MODE(tm->bus_act_mask)) ||
+ (DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask))) {
+ /* Disable ECC Write MUX */
+ CHECK_STATUS(ddr3_tip_if_write
+ (0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
+ TRAINING_SW_2_REG, 0x0, 0x100));
+ /* General ECC and Bus3 ECC MUX remains enabled */
+ }
+
+ return MV_OK;
+}
+
+int ddr3_hws_hw_training(void)
+{
+ enum hws_algo_type algo_mode = ALGO_TYPE_DYNAMIC;
+ int status;
+ struct init_cntr_param init_param;
+
+ status = ddr3_silicon_pre_init();
+ if (MV_OK != status) {
+ printf("DDR3 Pre silicon Config - FAILED 0x%x\n", status);
+ return status;
+ }
+
+ init_param.do_mrs_phy = 1;
+#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
+ init_param.is_ctrl64_bit = 0;
+#else
+ init_param.is_ctrl64_bit = 1;
+#endif
+#if defined(CONFIG_ALLEYCAT3) || defined(CONFIG_ARMADA_38X) || \
+ defined(CONFIG_ARMADA_39X)
+ init_param.init_phy = 1;
+#else
+ init_param.init_phy = 0;
+#endif
+ init_param.msys_init = 1;
+ status = hws_ddr3_tip_init_controller(0, &init_param);
+ if (MV_OK != status) {
+ printf("DDR3 init controller - FAILED 0x%x\n", status);
+ return status;
+ }
+
+ status = ddr3_silicon_post_init();
+ if (MV_OK != status) {
+ printf("DDR3 Post Init - FAILED 0x%x\n", status);
+ return status;
+ }
+
+ status = ddr3_pre_algo_config();
+ if (MV_OK != status) {
+ printf("DDR3 Pre Algo Config - FAILED 0x%x\n", status);
+ return status;
+ }
+
+ /* run algorithm in order to configure the PHY */
+ status = hws_ddr3_tip_run_alg(0, algo_mode);
+ if (MV_OK != status) {
+ printf("DDR3 run algorithm - FAILED 0x%x\n", status);
+ return status;
+ }
+
+ status = ddr3_post_algo_config();
+ if (MV_OK != status) {
+ printf("DDR3 Post Algo Config - FAILED 0x%x\n", status);
+ return status;
+ }
+
+ return MV_OK;
+}
diff --git a/drivers/ddr/marvell/a38x/old/ddr3_hws_hw_training.h b/drivers/ddr/marvell/a38x/old/ddr3_hws_hw_training.h
new file mode 100644
index 0000000..17a0953
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/ddr3_hws_hw_training.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _DDR3_HWS_HW_TRAINING_H
+#define _DDR3_HWS_HW_TRAINING_H
+
+/* struct used for DLB configuration array */
+struct dlb_config {
+ u32 reg_addr;
+ u32 reg_data;
+};
+
+/* Topology update structure */
+struct topology_update_info {
+ int update_ecc;
+ u8 ecc;
+ int update_width;
+ u8 width;
+ int update_ecc_pup3_mode;
+ u8 ecc_pup_mode_offset;
+};
+
+/* Topology update defines */
+#define TOPOLOGY_UPDATE_WIDTH_16BIT 1
+#define TOPOLOGY_UPDATE_WIDTH_32BIT 0
+#define TOPOLOGY_UPDATE_WIDTH_32BIT_MASK 0xf
+#define TOPOLOGY_UPDATE_WIDTH_16BIT_MASK 0x3
+
+#define TOPOLOGY_UPDATE_ECC_ON 1
+#define TOPOLOGY_UPDATE_ECC_OFF 0
+#define TOPOLOGY_UPDATE_ECC_OFFSET_PUP4 4
+#define TOPOLOGY_UPDATE_ECC_OFFSET_PUP3 3
+
+/*
+ * 1. L2 filter should be set at binary header to 0xd000000,
+ * to avoid conflict with internal register IO.
+ * 2. U-Boot modifies internal registers base to 0xf100000,
+ * and than should update L2 filter accordingly to 0xf000000 (3.75 GB)
+ */
+/* temporary limit l2 filter to 3GiB (LSP issue) */
+#define L2_FILTER_FOR_MAX_MEMORY_SIZE 0xc0000000
+#define ADDRESS_FILTERING_END_REGISTER 0x8c04
+
+#define SUB_VERSION 0
+
+#endif /* _DDR3_HWS_HW_TRAINING_H */
diff --git a/drivers/ddr/marvell/a38x/old/ddr3_hws_hw_training_def.h b/drivers/ddr/marvell/a38x/old/ddr3_hws_hw_training_def.h
new file mode 100644
index 0000000..06d0ab1
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/ddr3_hws_hw_training_def.h
@@ -0,0 +1,464 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _DDR3_HWS_HW_TRAINING_DEF_H
+#define _DDR3_HWS_HW_TRAINING_DEF_H
+
+#define SAR_DDR3_FREQ_MASK 0xfe00000
+#define SAR_CPU_FAB_GET(cpu, fab) (((cpu & 0x7) << 21) | \
+ ((fab & 0xf) << 24))
+
+#define MAX_CS 4
+
+#define MIN_DIMM_ADDR 0x50
+#define FAR_END_DIMM_ADDR 0x50
+#define MAX_DIMM_ADDR 0x60
+
+#define SDRAM_CS_SIZE 0xfffffff
+#define SDRAM_CS_BASE 0x0
+#define SDRAM_DIMM_SIZE 0x80000000
+
+#define CPU_CONFIGURATION_REG(id) (0x21800 + (id * 0x100))
+#define CPU_MRVL_ID_OFFSET 0x10
+#define SAR1_CPU_CORE_MASK 0x38000000
+#define SAR1_CPU_CORE_OFFSET 27
+
+#define NEW_FABRIC_TWSI_ADDR 0x4e
+#ifdef DB_784MP_GP
+#define BUS_WIDTH_ECC_TWSI_ADDR 0x4e
+#else
+#define BUS_WIDTH_ECC_TWSI_ADDR 0x4f
+#endif
+#define MV_MAX_DDR3_STATIC_SIZE 50
+#define MV_DDR3_MODES_NUMBER 30
+
+#define RESUME_RL_PATTERNS_ADDR 0xfe0000
+#define RESUME_RL_PATTERNS_SIZE 0x100
+#define RESUME_TRAINING_VALUES_ADDR (RESUME_RL_PATTERNS_ADDR + \
+ RESUME_RL_PATTERNS_SIZE)
+#define RESUME_TRAINING_VALUES_MAX 0xcd0
+#define BOOT_INFO_ADDR (RESUME_RL_PATTERNS_ADDR + 0x1000)
+#define CHECKSUM_RESULT_ADDR (BOOT_INFO_ADDR + 0x1000)
+#define NUM_OF_REGISTER_ADDR (CHECKSUM_RESULT_ADDR + 4)
+#define SUSPEND_MAGIC_WORD 0xdeadb002
+#define REGISTER_LIST_END 0xffffffff
+
+/* MISC */
+#define INTER_REGS_BASE SOC_REGS_PHY_BASE
+
+/* DDR */
+#define REG_SDRAM_CONFIG_ADDR 0x1400
+#define REG_SDRAM_CONFIG_MASK 0x9fffffff
+#define REG_SDRAM_CONFIG_RFRS_MASK 0x3fff
+#define REG_SDRAM_CONFIG_WIDTH_OFFS 15
+#define REG_SDRAM_CONFIG_REGDIMM_OFFS 17
+#define REG_SDRAM_CONFIG_ECC_OFFS 18
+#define REG_SDRAM_CONFIG_IERR_OFFS 19
+#define REG_SDRAM_CONFIG_PUPRSTDIV_OFFS 28
+#define REG_SDRAM_CONFIG_RSTRD_OFFS 30
+
+#define REG_SDRAM_PINS_MUX 0x19d4
+
+#define REG_DUNIT_CTRL_LOW_ADDR 0x1404
+#define REG_DUNIT_CTRL_LOW_2T_OFFS 3
+#define REG_DUNIT_CTRL_LOW_2T_MASK 0x3
+#define REG_DUNIT_CTRL_LOW_DPDE_OFFS 14
+
+#define REG_SDRAM_TIMING_LOW_ADDR 0x1408
+#define REG_SDRAM_TIMING_HIGH_ADDR 0x140c
+#define REG_SDRAM_TIMING_H_R2R_OFFS 7
+#define REG_SDRAM_TIMING_H_R2R_MASK 0x3
+#define REG_SDRAM_TIMING_H_R2W_W2R_OFFS 9
+#define REG_SDRAM_TIMING_H_R2W_W2R_MASK 0x3
+#define REG_SDRAM_TIMING_H_W2W_OFFS 11
+#define REG_SDRAM_TIMING_H_W2W_MASK 0x1f
+#define REG_SDRAM_TIMING_H_R2R_H_OFFS 19
+#define REG_SDRAM_TIMING_H_R2R_H_MASK 0x7
+#define REG_SDRAM_TIMING_H_R2W_W2R_H_OFFS 22
+#define REG_SDRAM_TIMING_H_R2W_W2R_H_MASK 0x7
+
+#define REG_SDRAM_ADDRESS_CTRL_ADDR 0x1410
+#define REG_SDRAM_ADDRESS_SIZE_OFFS 2
+#define REG_SDRAM_ADDRESS_SIZE_HIGH_OFFS 18
+#define REG_SDRAM_ADDRESS_CTRL_STRUCT_OFFS 4
+
+#define REG_SDRAM_OPEN_PAGES_ADDR 0x1414
+#define REG_SDRAM_OPERATION_CS_OFFS 8
+
+#define REG_SDRAM_OPERATION_ADDR 0x1418
+#define REG_SDRAM_OPERATION_CWA_DELAY_SEL_OFFS 24
+#define REG_SDRAM_OPERATION_CWA_DATA_OFFS 20
+#define REG_SDRAM_OPERATION_CWA_DATA_MASK 0xf
+#define REG_SDRAM_OPERATION_CWA_RC_OFFS 16
+#define REG_SDRAM_OPERATION_CWA_RC_MASK 0xf
+#define REG_SDRAM_OPERATION_CMD_MR0 0xf03
+#define REG_SDRAM_OPERATION_CMD_MR1 0xf04
+#define REG_SDRAM_OPERATION_CMD_MR2 0xf08
+#define REG_SDRAM_OPERATION_CMD_MR3 0xf09
+#define REG_SDRAM_OPERATION_CMD_RFRS 0xf02
+#define REG_SDRAM_OPERATION_CMD_CWA 0xf0e
+#define REG_SDRAM_OPERATION_CMD_RFRS_DONE 0xf
+#define REG_SDRAM_OPERATION_CMD_MASK 0xf
+#define REG_SDRAM_OPERATION_CS_OFFS 8
+
+#define REG_OUDDR3_TIMING_ADDR 0x142c
+
+#define REG_SDRAM_MODE_ADDR 0x141c
+
+#define REG_SDRAM_EXT_MODE_ADDR 0x1420
+
+#define REG_DDR_CONT_HIGH_ADDR 0x1424
+
+#define REG_ODT_TIME_LOW_ADDR 0x1428
+#define REG_ODT_ON_CTL_RD_OFFS 12
+#define REG_ODT_OFF_CTL_RD_OFFS 16
+#define REG_SDRAM_ERROR_ADDR 0x1454
+#define REG_SDRAM_AUTO_PWR_SAVE_ADDR 0x1474
+#define REG_ODT_TIME_HIGH_ADDR 0x147c
+
+#define REG_SDRAM_INIT_CTRL_ADDR 0x1480
+#define REG_SDRAM_INIT_CTRL_OFFS 0
+#define REG_SDRAM_INIT_CKE_ASSERT_OFFS 2
+#define REG_SDRAM_INIT_RESET_DEASSERT_OFFS 3
+#define REG_SDRAM_INIT_RESET_MASK_OFFS 1
+
+#define REG_SDRAM_ODT_CTRL_LOW_ADDR 0x1494
+
+#define REG_SDRAM_ODT_CTRL_HIGH_ADDR 0x1498
+#define REG_SDRAM_ODT_CTRL_HIGH_OVRD_MASK 0x0
+#define REG_SDRAM_ODT_CTRL_HIGH_OVRD_ENA 0x3
+
+#define REG_DUNIT_ODT_CTRL_ADDR 0x149c
+#define REG_DUNIT_ODT_CTRL_OVRD_OFFS 8
+#define REG_DUNIT_ODT_CTRL_OVRD_VAL_OFFS 9
+
+#define REG_DRAM_FIFO_CTRL_ADDR 0x14a0
+
+#define REG_DRAM_AXI_CTRL_ADDR 0x14a8
+#define REG_DRAM_AXI_CTRL_AXIDATABUSWIDTH_OFFS 0
+
+#define REG_METAL_MASK_ADDR 0x14b0
+#define REG_METAL_MASK_MASK 0xdfffffff
+#define REG_METAL_MASK_RETRY_OFFS 0
+
+#define REG_DRAM_ADDR_CTRL_DRIVE_STRENGTH_ADDR 0x14c0
+
+#define REG_DRAM_DATA_DQS_DRIVE_STRENGTH_ADDR 0x14c4
+#define REG_DRAM_VER_CAL_MACHINE_CTRL_ADDR 0x14c8
+#define REG_DRAM_MAIN_PADS_CAL_ADDR 0x14cc
+
+#define REG_DRAM_HOR_CAL_MACHINE_CTRL_ADDR 0x17c8
+
+#define REG_CS_SIZE_SCRATCH_ADDR 0x1504
+#define REG_DYNAMIC_POWER_SAVE_ADDR 0x1520
+#define REG_DDR_IO_ADDR 0x1524
+#define REG_DDR_IO_CLK_RATIO_OFFS 15
+
+#define REG_DFS_ADDR 0x1528
+#define REG_DFS_DLLNEXTSTATE_OFFS 0
+#define REG_DFS_BLOCK_OFFS 1
+#define REG_DFS_SR_OFFS 2
+#define REG_DFS_ATSR_OFFS 3
+#define REG_DFS_RECONF_OFFS 4
+#define REG_DFS_CL_NEXT_STATE_OFFS 8
+#define REG_DFS_CL_NEXT_STATE_MASK 0xf
+#define REG_DFS_CWL_NEXT_STATE_OFFS 12
+#define REG_DFS_CWL_NEXT_STATE_MASK 0x7
+
+#define REG_READ_DATA_SAMPLE_DELAYS_ADDR 0x1538
+#define REG_READ_DATA_SAMPLE_DELAYS_MASK 0x1f
+#define REG_READ_DATA_SAMPLE_DELAYS_OFFS 8
+
+#define REG_READ_DATA_READY_DELAYS_ADDR 0x153c
+#define REG_READ_DATA_READY_DELAYS_MASK 0x1f
+#define REG_READ_DATA_READY_DELAYS_OFFS 8
+
+#define START_BURST_IN_ADDR 1
+
+#define REG_DRAM_TRAINING_SHADOW_ADDR 0x18488
+#define REG_DRAM_TRAINING_ADDR 0x15b0
+#define REG_DRAM_TRAINING_LOW_FREQ_OFFS 0
+#define REG_DRAM_TRAINING_PATTERNS_OFFS 4
+#define REG_DRAM_TRAINING_MED_FREQ_OFFS 2
+#define REG_DRAM_TRAINING_WL_OFFS 3
+#define REG_DRAM_TRAINING_RL_OFFS 6
+#define REG_DRAM_TRAINING_DQS_RX_OFFS 15
+#define REG_DRAM_TRAINING_DQS_TX_OFFS 16
+#define REG_DRAM_TRAINING_CS_OFFS 20
+#define REG_DRAM_TRAINING_RETEST_OFFS 24
+#define REG_DRAM_TRAINING_DFS_FREQ_OFFS 27
+#define REG_DRAM_TRAINING_DFS_REQ_OFFS 29
+#define REG_DRAM_TRAINING_ERROR_OFFS 30
+#define REG_DRAM_TRAINING_AUTO_OFFS 31
+#define REG_DRAM_TRAINING_RETEST_PAR 0x3
+#define REG_DRAM_TRAINING_RETEST_MASK 0xf8ffffff
+#define REG_DRAM_TRAINING_CS_MASK 0xff0fffff
+#define REG_DRAM_TRAINING_PATTERNS_MASK 0xff0f0000
+
+#define REG_DRAM_TRAINING_1_ADDR 0x15b4
+#define REG_DRAM_TRAINING_1_TRNBPOINT_OFFS 16
+
+#define REG_DRAM_TRAINING_2_ADDR 0x15b8
+#define REG_DRAM_TRAINING_2_OVERRUN_OFFS 17
+#define REG_DRAM_TRAINING_2_FIFO_RST_OFFS 4
+#define REG_DRAM_TRAINING_2_RL_MODE_OFFS 3
+#define REG_DRAM_TRAINING_2_WL_MODE_OFFS 2
+#define REG_DRAM_TRAINING_2_ECC_MUX_OFFS 1
+#define REG_DRAM_TRAINING_2_SW_OVRD_OFFS 0
+
+#define REG_DRAM_TRAINING_PATTERN_BASE_ADDR 0x15bc
+#define REG_DRAM_TRAINING_PATTERN_BASE_OFFS 3
+
+#define REG_TRAINING_DEBUG_2_ADDR 0x15c4
+#define REG_TRAINING_DEBUG_2_OFFS 16
+#define REG_TRAINING_DEBUG_2_MASK 0x3
+
+#define REG_TRAINING_DEBUG_3_ADDR 0x15c8
+#define REG_TRAINING_DEBUG_3_OFFS 3
+#define REG_TRAINING_DEBUG_3_MASK 0x7
+
+#define MR_CS_ADDR_OFFS 4
+
+#define REG_DDR3_MR0_ADDR 0x15d0
+#define REG_DDR3_MR0_CS_ADDR 0x1870
+#define REG_DDR3_MR0_CL_MASK 0x74
+#define REG_DDR3_MR0_CL_OFFS 2
+#define REG_DDR3_MR0_CL_HIGH_OFFS 3
+#define CL_MASK 0xf
+
+#define REG_DDR3_MR1_ADDR 0x15d4
+#define REG_DDR3_MR1_CS_ADDR 0x1874
+#define REG_DDR3_MR1_RTT_MASK 0xfffffdbb
+#define REG_DDR3_MR1_DLL_ENA_OFFS 0
+#define REG_DDR3_MR1_RTT_DISABLED 0x0
+#define REG_DDR3_MR1_RTT_RZQ2 0x40
+#define REG_DDR3_MR1_RTT_RZQ4 0x2
+#define REG_DDR3_MR1_RTT_RZQ6 0x42
+#define REG_DDR3_MR1_RTT_RZQ8 0x202
+#define REG_DDR3_MR1_RTT_RZQ12 0x4
+/* WL-disabled, OB-enabled */
+#define REG_DDR3_MR1_OUTBUF_WL_MASK 0xffffef7f
+/* Output Buffer Disabled */
+#define REG_DDR3_MR1_OUTBUF_DIS_OFFS 12
+#define REG_DDR3_MR1_WL_ENA_OFFS 7
+#define REG_DDR3_MR1_WL_ENA 0x80 /* WL Enabled */
+#define REG_DDR3_MR1_ODT_MASK 0xfffffdbb
+
+#define REG_DDR3_MR2_ADDR 0x15d8
+#define REG_DDR3_MR2_CS_ADDR 0x1878
+#define REG_DDR3_MR2_CWL_OFFS 3
+#define REG_DDR3_MR2_CWL_MASK 0x7
+#define REG_DDR3_MR2_ODT_MASK 0xfffff9ff
+#define REG_DDR3_MR3_ADDR 0x15dc
+#define REG_DDR3_MR3_CS_ADDR 0x187c
+
+#define REG_DDR3_RANK_CTRL_ADDR 0x15e0
+#define REG_DDR3_RANK_CTRL_CS_ENA_MASK 0xf
+#define REG_DDR3_RANK_CTRL_MIRROR_OFFS 4
+
+#define REG_ZQC_CONF_ADDR 0x15e4
+
+#define REG_DRAM_PHY_CONFIG_ADDR 0x15ec
+#define REG_DRAM_PHY_CONFIG_MASK 0x3fffffff
+
+#define REG_ODPG_CNTRL_ADDR 0x1600
+#define REG_ODPG_CNTRL_OFFS 21
+
+#define REG_PHY_LOCK_MASK_ADDR 0x1670
+#define REG_PHY_LOCK_MASK_MASK 0xfffff000
+
+#define REG_PHY_LOCK_STATUS_ADDR 0x1674
+#define REG_PHY_LOCK_STATUS_LOCK_OFFS 9
+#define REG_PHY_LOCK_STATUS_LOCK_MASK 0xfff
+#define REG_PHY_LOCK_APLL_ADLL_STATUS_MASK 0x7ff
+
+#define REG_PHY_REGISTRY_FILE_ACCESS_ADDR 0x16a0
+#define REG_PHY_REGISTRY_FILE_ACCESS_OP_WR 0xc0000000
+#define REG_PHY_REGISTRY_FILE_ACCESS_OP_RD 0x80000000
+#define REG_PHY_REGISTRY_FILE_ACCESS_OP_DONE 0x80000000
+#define REG_PHY_BC_OFFS 27
+#define REG_PHY_CNTRL_OFFS 26
+#define REG_PHY_CS_OFFS 16
+#define REG_PHY_DQS_REF_DLY_OFFS 10
+#define REG_PHY_PHASE_OFFS 8
+#define REG_PHY_PUP_OFFS 22
+
+#define REG_TRAINING_WL_ADDR 0x16ac
+#define REG_TRAINING_WL_CS_MASK 0xfffffffc
+#define REG_TRAINING_WL_UPD_OFFS 2
+#define REG_TRAINING_WL_CS_DONE_OFFS 3
+#define REG_TRAINING_WL_RATIO_MASK 0xffffff0f
+#define REG_TRAINING_WL_1TO1 0x50
+#define REG_TRAINING_WL_2TO1 0x10
+#define REG_TRAINING_WL_DELAYEXP_MASK 0x20000000
+#define REG_TRAINING_WL_RESULTS_MASK 0x000001ff
+#define REG_TRAINING_WL_RESULTS_OFFS 20
+
+#define REG_REGISTERED_DRAM_CTRL_ADDR 0x16d0
+#define REG_REGISTERED_DRAM_CTRL_SR_FLOAT_OFFS 15
+#define REG_REGISTERED_DRAM_CTRL_PARITY_MASK 0x3f
+
+/* DLB */
+#define REG_STATIC_DRAM_DLB_CONTROL 0x1700
+#define DLB_BUS_OPTIMIZATION_WEIGHTS_REG 0x1704
+#define DLB_AGING_REGISTER 0x1708
+#define DLB_EVICTION_CONTROL_REG 0x170c
+#define DLB_EVICTION_TIMERS_REGISTER_REG 0x1710
+#define DLB_USER_COMMAND_REG 0x1714
+#define DLB_BUS_WEIGHTS_DIFF_CS 0x1770
+#define DLB_BUS_WEIGHTS_DIFF_BG 0x1774
+#define DLB_BUS_WEIGHTS_SAME_BG 0x1778
+#define DLB_BUS_WEIGHTS_RD_WR 0x177c
+#define DLB_BUS_WEIGHTS_ATTR_SYS_PRIO 0x1780
+#define DLB_MAIN_QUEUE_MAP 0x1784
+#define DLB_LINE_SPLIT 0x1788
+
+#define DLB_ENABLE 0x1
+#define DLB_WRITE_COALESING (0x1 << 2)
+#define DLB_AXI_PREFETCH_EN (0x1 << 3)
+#define DLB_MBUS_PREFETCH_EN (0x1 << 4)
+#define PREFETCH_N_LN_SZ_TR (0x1 << 6)
+#define DLB_INTERJECTION_ENABLE (0x1 << 3)
+
+/* CPU */
+#define REG_BOOTROM_ROUTINE_ADDR 0x182d0
+#define REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS 12
+
+#define REG_DRAM_INIT_CTRL_STATUS_ADDR 0x18488
+#define REG_DRAM_INIT_CTRL_TRN_CLK_OFFS 16
+#define REG_CPU_DIV_CLK_CTRL_0_NEW_RATIO 0x000200ff
+#define REG_DRAM_INIT_CTRL_STATUS_2_ADDR 0x1488
+
+#define REG_CPU_DIV_CLK_CTRL_0_ADDR 0x18700
+
+#define REG_CPU_DIV_CLK_CTRL_1_ADDR 0x18704
+#define REG_CPU_DIV_CLK_CTRL_2_ADDR 0x18708
+
+#define REG_CPU_DIV_CLK_CTRL_3_ADDR 0x1870c
+#define REG_CPU_DIV_CLK_CTRL_3_FREQ_MASK 0xffffc0ff
+#define REG_CPU_DIV_CLK_CTRL_3_FREQ_OFFS 8
+
+#define REG_CPU_DIV_CLK_CTRL_4_ADDR 0x18710
+
+#define REG_CPU_DIV_CLK_STATUS_0_ADDR 0x18718
+#define REG_CPU_DIV_CLK_ALL_STABLE_OFFS 8
+
+#define REG_CPU_PLL_CTRL_0_ADDR 0x1871c
+#define REG_CPU_PLL_STATUS_0_ADDR 0x18724
+#define REG_CORE_DIV_CLK_CTRL_ADDR 0x18740
+#define REG_CORE_DIV_CLK_STATUS_ADDR 0x18744
+#define REG_DDRPHY_APLL_CTRL_ADDR 0x18780
+
+#define REG_DDRPHY_APLL_CTRL_2_ADDR 0x18784
+#define REG_SFABRIC_CLK_CTRL_ADDR 0x20858
+#define REG_SFABRIC_CLK_CTRL_SMPL_OFFS 8
+
+/* DRAM Windows */
+#define REG_XBAR_WIN_19_CTRL_ADDR 0x200e8
+#define REG_XBAR_WIN_4_CTRL_ADDR 0x20040
+#define REG_XBAR_WIN_4_BASE_ADDR 0x20044
+#define REG_XBAR_WIN_4_REMAP_ADDR 0x20048
+#define REG_FASTPATH_WIN_0_CTRL_ADDR 0x20184
+#define REG_XBAR_WIN_7_REMAP_ADDR 0x20078
+
+/* SRAM */
+#define REG_CDI_CONFIG_ADDR 0x20220
+#define REG_SRAM_WINDOW_0_ADDR 0x20240
+#define REG_SRAM_WINDOW_0_ENA_OFFS 0
+#define REG_SRAM_WINDOW_1_ADDR 0x20244
+#define REG_SRAM_L2_ENA_ADDR 0x8500
+#define REG_SRAM_CLEAN_BY_WAY_ADDR 0x87bc
+
+/* Timers */
+#define REG_TIMERS_CTRL_ADDR 0x20300
+#define REG_TIMERS_EVENTS_ADDR 0x20304
+#define REG_TIMER0_VALUE_ADDR 0x20314
+#define REG_TIMER1_VALUE_ADDR 0x2031c
+#define REG_TIMER0_ENABLE_MASK 0x1
+
+#define MV_BOARD_REFCLK_25MHZ 25000000
+#define CNTMR_RELOAD_REG(tmr) (REG_TIMERS_CTRL_ADDR + 0x10 + (tmr * 8))
+#define CNTMR_VAL_REG(tmr) (REG_TIMERS_CTRL_ADDR + 0x14 + (tmr * 8))
+#define CNTMR_CTRL_REG(tmr) (REG_TIMERS_CTRL_ADDR)
+#define CTCR_ARM_TIMER_EN_OFFS(timer) (timer * 2)
+#define CTCR_ARM_TIMER_EN_MASK(timer) (1 << CTCR_ARM_TIMER_EN_OFFS(timer))
+#define CTCR_ARM_TIMER_EN(timer) (1 << CTCR_ARM_TIMER_EN_OFFS(timer))
+
+#define CTCR_ARM_TIMER_AUTO_OFFS(timer) (1 + (timer * 2))
+#define CTCR_ARM_TIMER_AUTO_MASK(timer) (1 << CTCR_ARM_TIMER_EN_OFFS(timer))
+#define CTCR_ARM_TIMER_AUTO_EN(timer) (1 << CTCR_ARM_TIMER_AUTO_OFFS(timer))
+
+/* PMU */
+#define REG_PMU_I_F_CTRL_ADDR 0x1c090
+#define REG_PMU_DUNIT_BLK_OFFS 16
+#define REG_PMU_DUNIT_RFRS_OFFS 20
+#define REG_PMU_DUNIT_ACK_OFFS 24
+
+/* MBUS */
+#define MBUS_UNITS_PRIORITY_CONTROL_REG (MBUS_REGS_OFFSET + 0x420)
+#define FABRIC_UNITS_PRIORITY_CONTROL_REG (MBUS_REGS_OFFSET + 0x424)
+#define MBUS_UNITS_PREFETCH_CONTROL_REG (MBUS_REGS_OFFSET + 0x428)
+#define FABRIC_UNITS_PREFETCH_CONTROL_REG (MBUS_REGS_OFFSET + 0x42c)
+
+#define REG_PM_STAT_MASK_ADDR 0x2210c
+#define REG_PM_STAT_MASK_CPU0_IDLE_MASK_OFFS 16
+
+#define REG_PM_EVENT_STAT_MASK_ADDR 0x22120
+#define REG_PM_EVENT_STAT_MASK_DFS_DONE_OFFS 17
+
+#define REG_PM_CTRL_CONFIG_ADDR 0x22104
+#define REG_PM_CTRL_CONFIG_DFS_REQ_OFFS 18
+
+#define REG_FABRIC_LOCAL_IRQ_MASK_ADDR 0x218c4
+#define REG_FABRIC_LOCAL_IRQ_PMU_MASK_OFFS 18
+
+/* Controller revision info */
+#define PCI_CLASS_CODE_AND_REVISION_ID 0x008
+#define PCCRIR_REVID_OFFS 0 /* Revision ID */
+#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS)
+
+/* Power Management Clock Gating Control Register */
+#define POWER_MNG_CTRL_REG 0x18220
+#define PEX_DEVICE_AND_VENDOR_ID 0x000
+#define PEX_CFG_DIRECT_ACCESS(if, reg) (PEX_IF_REGS_BASE(if) + (reg))
+#define PMC_PEXSTOPCLOCK_OFFS(p) ((p) < 8 ? (5 + (p)) : (18 + (p)))
+#define PMC_PEXSTOPCLOCK_MASK(p) (1 << PMC_PEXSTOPCLOCK_OFFS(p))
+#define PMC_PEXSTOPCLOCK_EN(p) (1 << PMC_PEXSTOPCLOCK_OFFS(p))
+#define PMC_PEXSTOPCLOCK_STOP(p) (0 << PMC_PEXSTOPCLOCK_OFFS(p))
+
+/* TWSI */
+#define TWSI_DATA_ADDR_MASK 0x7
+#define TWSI_DATA_ADDR_OFFS 1
+
+/* General */
+#define MAX_CS 4
+
+/* Frequencies */
+#define FAB_OPT 21
+#define CLK_CPU 12
+#define CLK_VCO (2 * CLK_CPU)
+#define CLK_DDR 12
+
+/* CPU Frequencies: */
+#define CLK_CPU_1000 0
+#define CLK_CPU_1066 1
+#define CLK_CPU_1200 2
+#define CLK_CPU_1333 3
+#define CLK_CPU_1500 4
+#define CLK_CPU_1666 5
+#define CLK_CPU_1800 6
+#define CLK_CPU_2000 7
+#define CLK_CPU_600 8
+#define CLK_CPU_667 9
+#define CLK_CPU_800 0xa
+
+/* Extra Cpu Frequencies: */
+#define CLK_CPU_1600 11
+#define CLK_CPU_2133 12
+#define CLK_CPU_2200 13
+#define CLK_CPU_2400 14
+
+#endif /* _DDR3_HWS_HW_TRAINING_DEF_H */
diff --git a/drivers/ddr/marvell/a38x/old/ddr3_hws_sil_training.h b/drivers/ddr/marvell/a38x/old/ddr3_hws_sil_training.h
new file mode 100644
index 0000000..544237a
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/ddr3_hws_sil_training.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _DDR3_HWS_SIL_TRAINING_H
+#define _DDR3_HWS_SIL_TRAINING_H
+
+#include "ddr3_training_ip.h"
+#include "ddr3_training_ip_prv_if.h"
+
+int ddr3_silicon_pre_config(void);
+int ddr3_silicon_init(void);
+int ddr3_silicon_get_ddr_target_freq(u32 *ddr_freq);
+
+#endif /* _DDR3_HWS_SIL_TRAINING_H */
diff --git a/drivers/ddr/marvell/a38x/old/ddr3_init.c b/drivers/ddr/marvell/a38x/old/ddr3_init.c
new file mode 100644
index 0000000..b3c04eb
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/ddr3_init.c
@@ -0,0 +1,769 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <i2c.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+#include "ddr3_init.h"
+
+#include "../../../../arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h"
+
+static struct dlb_config ddr3_dlb_config_table[] = {
+ {REG_STATIC_DRAM_DLB_CONTROL, 0x2000005c},
+ {DLB_BUS_OPTIMIZATION_WEIGHTS_REG, 0x00880000},
+ {DLB_AGING_REGISTER, 0x0f7f007f},
+ {DLB_EVICTION_CONTROL_REG, 0x0000129f},
+ {DLB_EVICTION_TIMERS_REGISTER_REG, 0x00ff0000},
+ {DLB_BUS_WEIGHTS_DIFF_CS, 0x04030802},
+ {DLB_BUS_WEIGHTS_DIFF_BG, 0x00000a02},
+ {DLB_BUS_WEIGHTS_SAME_BG, 0x09000a01},
+ {DLB_BUS_WEIGHTS_RD_WR, 0x00020005},
+ {DLB_BUS_WEIGHTS_ATTR_SYS_PRIO, 0x00060f10},
+ {DLB_MAIN_QUEUE_MAP, 0x00000543},
+ {DLB_LINE_SPLIT, 0x00000000},
+ {DLB_USER_COMMAND_REG, 0x00000000},
+ {0x0, 0x0}
+};
+
+static struct dlb_config ddr3_dlb_config_table_a0[] = {
+ {REG_STATIC_DRAM_DLB_CONTROL, 0x2000005c},
+ {DLB_BUS_OPTIMIZATION_WEIGHTS_REG, 0x00880000},
+ {DLB_AGING_REGISTER, 0x0f7f007f},
+ {DLB_EVICTION_CONTROL_REG, 0x0000129f},
+ {DLB_EVICTION_TIMERS_REGISTER_REG, 0x00ff0000},
+ {DLB_BUS_WEIGHTS_DIFF_CS, 0x04030802},
+ {DLB_BUS_WEIGHTS_DIFF_BG, 0x00000a02},
+ {DLB_BUS_WEIGHTS_SAME_BG, 0x09000a01},
+ {DLB_BUS_WEIGHTS_RD_WR, 0x00020005},
+ {DLB_BUS_WEIGHTS_ATTR_SYS_PRIO, 0x00060f10},
+ {DLB_MAIN_QUEUE_MAP, 0x00000543},
+ {DLB_LINE_SPLIT, 0x00000000},
+ {DLB_USER_COMMAND_REG, 0x00000000},
+ {0x0, 0x0}
+};
+
+#if defined(CONFIG_ARMADA_38X)
+struct dram_modes {
+ char *mode_name;
+ u8 cpu_freq;
+ u8 fab_freq;
+ u8 chip_id;
+ u8 chip_board_rev;
+ struct reg_data *regs;
+};
+
+struct dram_modes ddr_modes[] = {
+#ifdef SUPPORT_STATIC_DUNIT_CONFIG
+ /* Conf name, CPUFreq, Fab_freq, Chip ID, Chip/Board, MC regs*/
+#ifdef CONFIG_CUSTOMER_BOARD_SUPPORT
+ {"a38x_customer_0_800", DDR_FREQ_800, 0, 0x0, A38X_CUSTOMER_BOARD_ID0,
+ ddr3_customer_800},
+ {"a38x_customer_1_800", DDR_FREQ_800, 0, 0x0, A38X_CUSTOMER_BOARD_ID1,
+ ddr3_customer_800},
+#else
+ {"a38x_533", DDR_FREQ_533, 0, 0x0, MARVELL_BOARD, ddr3_a38x_533},
+ {"a38x_667", DDR_FREQ_667, 0, 0x0, MARVELL_BOARD, ddr3_a38x_667},
+ {"a38x_800", DDR_FREQ_800, 0, 0x0, MARVELL_BOARD, ddr3_a38x_800},
+ {"a38x_933", DDR_FREQ_933, 0, 0x0, MARVELL_BOARD, ddr3_a38x_933},
+#endif
+#endif
+};
+#endif /* defined(CONFIG_ARMADA_38X) */
+
+/* Translates topology map definitions to real memory size in bits */
+u32 mem_size[] = {
+ ADDR_SIZE_512MB, ADDR_SIZE_1GB, ADDR_SIZE_2GB, ADDR_SIZE_4GB,
+ ADDR_SIZE_8GB
+};
+
+static char *ddr_type = "DDR3";
+
+/*
+ * Set 1 to use dynamic DUNIT configuration,
+ * set 0 (supported for A380 and AC3) to configure DUNIT in values set by
+ * ddr3_tip_init_specific_reg_config
+ */
+u8 generic_init_controller = 1;
+
+#ifdef SUPPORT_STATIC_DUNIT_CONFIG
+static u32 ddr3_get_static_ddr_mode(void);
+#endif
+static int ddr3_hws_tune_training_params(u8 dev_num);
+
+/* device revision */
+#define DEV_VERSION_ID_REG 0x1823c
+#define REVISON_ID_OFFS 8
+#define REVISON_ID_MASK 0xf00
+
+/* A38x revisions */
+#define MV_88F68XX_Z1_ID 0x0
+#define MV_88F68XX_A0_ID 0x4
+/* A39x revisions */
+#define MV_88F69XX_Z1_ID 0x2
+
+/*
+ * sys_env_device_rev_get - Get Marvell controller device revision number
+ *
+ * DESCRIPTION:
+ * This function returns 8bit describing the device revision as defined
+ * Revision ID Register.
+ *
+ * INPUT:
+ * None.
+ *
+ * OUTPUT:
+ * None.
+ *
+ * RETURN:
+ * 8bit desscribing Marvell controller revision number
+ */
+u8 sys_env_device_rev_get(void)
+{
+ u32 value;
+
+ value = reg_read(DEV_VERSION_ID_REG);
+ return (value & (REVISON_ID_MASK)) >> REVISON_ID_OFFS;
+}
+
+/*
+ * sys_env_dlb_config_ptr_get
+ *
+ * DESCRIPTION: defines pointer to to DLB COnfiguration table
+ *
+ * INPUT: none
+ *
+ * OUTPUT: pointer to DLB COnfiguration table
+ *
+ * RETURN:
+ * returns pointer to DLB COnfiguration table
+ */
+struct dlb_config *sys_env_dlb_config_ptr_get(void)
+{
+#ifdef CONFIG_ARMADA_39X
+ return &ddr3_dlb_config_table_a0[0];
+#else
+ if (sys_env_device_rev_get() == MV_88F68XX_A0_ID)
+ return &ddr3_dlb_config_table_a0[0];
+ else
+ return &ddr3_dlb_config_table[0];
+#endif
+}
+
+/*
+ * sys_env_get_cs_ena_from_reg
+ *
+ * DESCRIPTION: Get bit mask of enabled CS
+ *
+ * INPUT: None
+ *
+ * OUTPUT: None
+ *
+ * RETURN:
+ * Bit mask of enabled CS, 1 if only CS0 enabled,
+ * 3 if both CS0 and CS1 enabled
+ */
+u32 sys_env_get_cs_ena_from_reg(void)
+{
+ return reg_read(REG_DDR3_RANK_CTRL_ADDR) &
+ REG_DDR3_RANK_CTRL_CS_ENA_MASK;
+}
+
+static void ddr3_restore_and_set_final_windows(u32 *win)
+{
+ u32 win_ctrl_reg, num_of_win_regs;
+ u32 cs_ena = sys_env_get_cs_ena_from_reg();
+ u32 ui;
+
+ win_ctrl_reg = REG_XBAR_WIN_4_CTRL_ADDR;
+ num_of_win_regs = 16;
+
+ /* Return XBAR windows 4-7 or 16-19 init configuration */
+ for (ui = 0; ui < num_of_win_regs; ui++)
+ reg_write((win_ctrl_reg + 0x4 * ui), win[ui]);
+
+ printf("%s Training Sequence - Switching XBAR Window to FastPath Window\n",
+ ddr_type);
+
+#if defined DYNAMIC_CS_SIZE_CONFIG
+ if (ddr3_fast_path_dynamic_cs_size_config(cs_ena) != MV_OK)
+ printf("ddr3_fast_path_dynamic_cs_size_config FAILED\n");
+#else
+ u32 reg, cs;
+ reg = 0x1fffffe1;
+ for (cs = 0; cs < MAX_CS; cs++) {
+ if (cs_ena & (1 << cs)) {
+ reg |= (cs << 2);
+ break;
+ }
+ }
+ /* Open fast path Window to - 0.5G */
+ reg_write(REG_FASTPATH_WIN_0_CTRL_ADDR, reg);
+#endif
+}
+
+static int ddr3_save_and_set_training_windows(u32 *win)
+{
+ u32 cs_ena;
+ u32 reg, tmp_count, cs, ui;
+ u32 win_ctrl_reg, win_base_reg, win_remap_reg;
+ u32 num_of_win_regs, win_jump_index;
+ win_ctrl_reg = REG_XBAR_WIN_4_CTRL_ADDR;
+ win_base_reg = REG_XBAR_WIN_4_BASE_ADDR;
+ win_remap_reg = REG_XBAR_WIN_4_REMAP_ADDR;
+ win_jump_index = 0x10;
+ num_of_win_regs = 16;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+#ifdef DISABLE_L2_FILTERING_DURING_DDR_TRAINING
+ /*
+ * Disable L2 filtering during DDR training
+ * (when Cross Bar window is open)
+ */
+ reg_write(ADDRESS_FILTERING_END_REGISTER, 0);
+#endif
+
+ cs_ena = tm->interface_params[0].as_bus_params[0].cs_bitmask;
+
+ /* Close XBAR Window 19 - Not needed */
+ /* {0x000200e8} - Open Mbus Window - 2G */
+ reg_write(REG_XBAR_WIN_19_CTRL_ADDR, 0);
+
+ /* Save XBAR Windows 4-19 init configurations */
+ for (ui = 0; ui < num_of_win_regs; ui++)
+ win[ui] = reg_read(win_ctrl_reg + 0x4 * ui);
+
+ /* Open XBAR Windows 4-7 or 16-19 for other CS */
+ reg = 0;
+ tmp_count = 0;
+ for (cs = 0; cs < MAX_CS; cs++) {
+ if (cs_ena & (1 << cs)) {
+ switch (cs) {
+ case 0:
+ reg = 0x0e00;
+ break;
+ case 1:
+ reg = 0x0d00;
+ break;
+ case 2:
+ reg = 0x0b00;
+ break;
+ case 3:
+ reg = 0x0700;
+ break;
+ }
+ reg |= (1 << 0);
+ reg |= (SDRAM_CS_SIZE & 0xffff0000);
+
+ reg_write(win_ctrl_reg + win_jump_index * tmp_count,
+ reg);
+ reg = (((SDRAM_CS_SIZE + 1) * (tmp_count)) &
+ 0xffff0000);
+ reg_write(win_base_reg + win_jump_index * tmp_count,
+ reg);
+
+ if (win_remap_reg <= REG_XBAR_WIN_7_REMAP_ADDR)
+ reg_write(win_remap_reg +
+ win_jump_index * tmp_count, 0);
+
+ tmp_count++;
+ }
+ }
+
+ return MV_OK;
+}
+
+/*
+ * Name: ddr3_init - Main DDR3 Init function
+ * Desc: This routine initialize the DDR3 MC and runs HW training.
+ * Args: None.
+ * Notes:
+ * Returns: None.
+ */
+int ddr3_init(void)
+{
+ u32 reg = 0;
+ u32 soc_num;
+ int status;
+ u32 win[16];
+
+ /* SoC/Board special Initializtions */
+ /* Get version from internal library */
+ ddr3_print_version();
+
+ /*Add sub_version string */
+ DEBUG_INIT_C("", SUB_VERSION, 1);
+
+ /* Switching CPU to MRVL ID */
+ soc_num = (reg_read(REG_SAMPLE_RESET_HIGH_ADDR) & SAR1_CPU_CORE_MASK) >>
+ SAR1_CPU_CORE_OFFSET;
+ switch (soc_num) {
+ case 0x3:
+ case 0x1:
+ reg_bit_set(CPU_CONFIGURATION_REG(1), CPU_MRVL_ID_OFFSET);
+ case 0x0:
+ reg_bit_set(CPU_CONFIGURATION_REG(0), CPU_MRVL_ID_OFFSET);
+ default:
+ break;
+ }
+
+ /*
+ * Set DRAM Reset Mask in case detected GPIO indication of wakeup from
+ * suspend i.e the DRAM values will not be overwritten / reset when
+ * waking from suspend
+ */
+ if (sys_env_suspend_wakeup_check() ==
+ SUSPEND_WAKEUP_ENABLED_GPIO_DETECTED) {
+ reg_bit_set(REG_SDRAM_INIT_CTRL_ADDR,
+ 1 << REG_SDRAM_INIT_RESET_MASK_OFFS);
+ }
+
+ /*
+ * Stage 0 - Set board configuration
+ */
+
+ /* Check if DRAM is already initialized */
+ if (reg_read(REG_BOOTROM_ROUTINE_ADDR) &
+ (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS)) {
+ printf("%s Training Sequence - 2nd boot - Skip\n", ddr_type);
+ return MV_OK;
+ }
+
+ /*
+ * Stage 1 - Dunit Setup
+ */
+
+ /* Fix read ready phases for all SOC in reg 0x15c8 */
+ reg = reg_read(REG_TRAINING_DEBUG_3_ADDR);
+ reg &= ~(REG_TRAINING_DEBUG_3_MASK);
+ reg |= 0x4; /* Phase 0 */
+ reg &= ~(REG_TRAINING_DEBUG_3_MASK << REG_TRAINING_DEBUG_3_OFFS);
+ reg |= (0x4 << (1 * REG_TRAINING_DEBUG_3_OFFS)); /* Phase 1 */
+ reg &= ~(REG_TRAINING_DEBUG_3_MASK << (3 * REG_TRAINING_DEBUG_3_OFFS));
+ reg |= (0x6 << (3 * REG_TRAINING_DEBUG_3_OFFS)); /* Phase 3 */
+ reg &= ~(REG_TRAINING_DEBUG_3_MASK << (4 * REG_TRAINING_DEBUG_3_OFFS));
+ reg |= (0x6 << (4 * REG_TRAINING_DEBUG_3_OFFS));
+ reg &= ~(REG_TRAINING_DEBUG_3_MASK << (5 * REG_TRAINING_DEBUG_3_OFFS));
+ reg |= (0x6 << (5 * REG_TRAINING_DEBUG_3_OFFS));
+ reg_write(REG_TRAINING_DEBUG_3_ADDR, reg);
+
+ /*
+ * Axi_bresp_mode[8] = Compliant,
+ * Axi_addr_decode_cntrl[11] = Internal,
+ * Axi_data_bus_width[0] = 128bit
+ * */
+ /* 0x14a8 - AXI Control Register */
+ reg_write(REG_DRAM_AXI_CTRL_ADDR, 0);
+
+ /*
+ * Stage 2 - Training Values Setup
+ */
+ /* Set X-BAR windows for the training sequence */
+ ddr3_save_and_set_training_windows(win);
+
+#ifdef SUPPORT_STATIC_DUNIT_CONFIG
+ /*
+ * Load static controller configuration (in case dynamic/generic init
+ * is not enabled
+ */
+ if (generic_init_controller == 0) {
+ ddr3_tip_init_specific_reg_config(0,
+ ddr_modes
+ [ddr3_get_static_ddr_mode
+ ()].regs);
+ }
+#endif
+
+ /* Tune training algo paramteres */
+ status = ddr3_hws_tune_training_params(0);
+ if (MV_OK != status)
+ return status;
+
+ /* Set log level for training lib */
+ if (!IS_ENABLED(CONFIG_DDR_IMMUTABLE_DEBUG_SETTINGS))
+ ddr3_hws_set_log_level(DEBUG_BLOCK_ALL, DEBUG_LEVEL_ERROR);
+
+ /* Start New Training IP */
+ status = ddr3_hws_hw_training();
+ if (MV_OK != status) {
+ printf("%s Training Sequence - FAILED\n", ddr_type);
+ return status;
+ }
+
+ /*
+ * Stage 3 - Finish
+ */
+ /* Restore and set windows */
+ ddr3_restore_and_set_final_windows(win);
+
+ /* Update DRAM init indication in bootROM register */
+ reg = reg_read(REG_BOOTROM_ROUTINE_ADDR);
+ reg_write(REG_BOOTROM_ROUTINE_ADDR,
+ reg | (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS));
+
+ /* DLB config */
+ ddr3_new_tip_dlb_config();
+
+#if defined(ECC_SUPPORT)
+ if (ddr3_if_ecc_enabled())
+ ddr3_new_tip_ecc_scrub();
+#endif
+
+ printf("%s Training Sequence - Ended Successfully\n", ddr_type);
+
+ return MV_OK;
+}
+
+/*
+ * Name: ddr3_get_cpu_freq
+ * Desc: read S@R and return CPU frequency
+ * Args:
+ * Notes:
+ * Returns: required value
+ */
+u32 ddr3_get_cpu_freq(void)
+{
+ return ddr3_tip_get_init_freq();
+}
+
+/*
+ * Name: ddr3_get_fab_opt
+ * Desc: read S@R and return CPU frequency
+ * Args:
+ * Notes:
+ * Returns: required value
+ */
+u32 ddr3_get_fab_opt(void)
+{
+ return 0; /* No fabric */
+}
+
+/*
+ * Name: ddr3_get_static_m_cValue - Init Memory controller with
+ * static parameters
+ * Desc: Use this routine to init the controller without the HW training
+ * procedure.
+ * User must provide compatible header file with registers data.
+ * Args: None.
+ * Notes:
+ * Returns: None.
+ */
+u32 ddr3_get_static_mc_value(u32 reg_addr, u32 offset1, u32 mask1,
+ u32 offset2, u32 mask2)
+{
+ u32 reg, temp;
+
+ reg = reg_read(reg_addr);
+
+ temp = (reg >> offset1) & mask1;
+ if (mask2)
+ temp |= (reg >> offset2) & mask2;
+
+ return temp;
+}
+
+/*
+ * Name: ddr3_get_static_ddr_mode - Init Memory controller with
+ * static parameters
+ * Desc: Use this routine to init the controller without the HW training
+ * procedure.
+ * User must provide compatible header file with registers data.
+ * Args: None.
+ * Notes:
+ * Returns: None.
+ */
+u32 ddr3_get_static_ddr_mode(void)
+{
+ u32 chip_board_rev, i;
+ u32 size;
+
+ /* Valid only for A380 only, MSYS using dynamic controller config */
+#ifdef CONFIG_CUSTOMER_BOARD_SUPPORT
+ /*
+ * Customer boards select DDR mode according to
+ * board ID & Sample@Reset
+ */
+ chip_board_rev = mv_board_id_get();
+#else
+ /* Marvell boards select DDR mode according to Sample@Reset only */
+ chip_board_rev = MARVELL_BOARD;
+#endif
+
+ size = ARRAY_SIZE(ddr_modes);
+ for (i = 0; i < size; i++) {
+ if ((ddr3_get_cpu_freq() == ddr_modes[i].cpu_freq) &&
+ (ddr3_get_fab_opt() == ddr_modes[i].fab_freq) &&
+ (chip_board_rev == ddr_modes[i].chip_board_rev))
+ return i;
+ }
+
+ DEBUG_INIT_S("\n*** Error: ddr3_get_static_ddr_mode: No match for requested DDR mode. ***\n\n");
+
+ return 0;
+}
+
+/******************************************************************************
+ * Name: ddr3_get_cs_num_from_reg
+ * Desc:
+ * Args:
+ * Notes:
+ * Returns:
+ */
+u32 ddr3_get_cs_num_from_reg(void)
+{
+ u32 cs_ena = sys_env_get_cs_ena_from_reg();
+ u32 cs_count = 0;
+ u32 cs;
+
+ for (cs = 0; cs < MAX_CS; cs++) {
+ if (cs_ena & (1 << cs))
+ cs_count++;
+ }
+
+ return cs_count;
+}
+
+void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps)
+{
+ u32 tmp, hclk = 200;
+
+ switch (freq_mode) {
+ case 4:
+ tmp = 1; /* DDR_400; */
+ hclk = 200;
+ break;
+ case 0x8:
+ tmp = 1; /* DDR_666; */
+ hclk = 333;
+ break;
+ case 0xc:
+ tmp = 1; /* DDR_800; */
+ hclk = 400;
+ break;
+ default:
+ *ddr_freq = 0;
+ *hclk_ps = 0;
+ break;
+ }
+
+ *ddr_freq = tmp; /* DDR freq define */
+ *hclk_ps = 1000000 / hclk; /* values are 1/HCLK in ps */
+
+ return;
+}
+
+void ddr3_new_tip_dlb_config(void)
+{
+ u32 reg, i = 0;
+ struct dlb_config *config_table_ptr = sys_env_dlb_config_ptr_get();
+
+ /* Write the configuration */
+ while (config_table_ptr[i].reg_addr != 0) {
+ reg_write(config_table_ptr[i].reg_addr,
+ config_table_ptr[i].reg_data);
+ i++;
+ }
+
+ /* Enable DLB */
+ reg = reg_read(REG_STATIC_DRAM_DLB_CONTROL);
+ reg |= DLB_ENABLE | DLB_WRITE_COALESING | DLB_AXI_PREFETCH_EN |
+ DLB_MBUS_PREFETCH_EN | PREFETCH_N_LN_SZ_TR;
+ reg_write(REG_STATIC_DRAM_DLB_CONTROL, reg);
+}
+
+int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena)
+{
+ u32 reg, cs;
+ u32 mem_total_size = 0;
+ u32 cs_mem_size = 0;
+ u32 mem_total_size_c, cs_mem_size_c;
+
+#ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE
+ u32 physical_mem_size;
+ u32 max_mem_size = DEVICE_MAX_DRAM_ADDRESS_SIZE;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+#endif
+
+ /* Open fast path windows */
+ for (cs = 0; cs < MAX_CS; cs++) {
+ if (cs_ena & (1 << cs)) {
+ /* get CS size */
+ if (ddr3_calc_mem_cs_size(cs, &cs_mem_size) != MV_OK)
+ return MV_FAIL;
+
+#ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE
+ /*
+ * if number of address pins doesn't allow to use max
+ * mem size that is defined in topology
+ * mem size is defined by DEVICE_MAX_DRAM_ADDRESS_SIZE
+ */
+ physical_mem_size = mem_size
+ [tm->interface_params[0].memory_size];
+
+ if (ddr3_get_device_width(cs) == 16) {
+ /*
+ * 16bit mem device can be twice more - no need
+ * in less significant pin
+ */
+ max_mem_size = DEVICE_MAX_DRAM_ADDRESS_SIZE * 2;
+ }
+
+ if (physical_mem_size > max_mem_size) {
+ cs_mem_size = max_mem_size *
+ (ddr3_get_bus_width() /
+ ddr3_get_device_width(cs));
+ printf("Updated Physical Mem size is from 0x%x to %x\n",
+ physical_mem_size,
+ DEVICE_MAX_DRAM_ADDRESS_SIZE);
+ }
+#endif
+
+ /* set fast path window control for the cs */
+ reg = 0xffffe1;
+ reg |= (cs << 2);
+ reg |= (cs_mem_size - 1) & 0xffff0000;
+ /*Open fast path Window */
+ reg_write(REG_FASTPATH_WIN_CTRL_ADDR(cs), reg);
+
+ /* Set fast path window base address for the cs */
+ reg = ((cs_mem_size) * cs) & 0xffff0000;
+ /* Set base address */
+ reg_write(REG_FASTPATH_WIN_BASE_ADDR(cs), reg);
+
+ /*
+ * Since memory size may be bigger than 4G the summ may
+ * be more than 32 bit word,
+ * so to estimate the result divide mem_total_size and
+ * cs_mem_size by 0x10000 (it is equal to >> 16)
+ */
+ mem_total_size_c = mem_total_size >> 16;
+ cs_mem_size_c = cs_mem_size >> 16;
+ /* if the sum less than 2 G - calculate the value */
+ if (mem_total_size_c + cs_mem_size_c < 0x10000)
+ mem_total_size += cs_mem_size;
+ else /* put max possible size */
+ mem_total_size = L2_FILTER_FOR_MAX_MEMORY_SIZE;
+ }
+ }
+
+ /* Set L2 filtering to Max Memory size */
+ reg_write(ADDRESS_FILTERING_END_REGISTER, mem_total_size);
+
+ return MV_OK;
+}
+
+u32 ddr3_get_bus_width(void)
+{
+ u32 bus_width;
+
+ bus_width = (reg_read(REG_SDRAM_CONFIG_ADDR) & 0x8000) >>
+ REG_SDRAM_CONFIG_WIDTH_OFFS;
+
+ return (bus_width == 0) ? 16 : 32;
+}
+
+u32 ddr3_get_device_width(u32 cs)
+{
+ u32 device_width;
+
+ device_width = (reg_read(REG_SDRAM_ADDRESS_CTRL_ADDR) &
+ (0x3 << (REG_SDRAM_ADDRESS_CTRL_STRUCT_OFFS * cs))) >>
+ (REG_SDRAM_ADDRESS_CTRL_STRUCT_OFFS * cs);
+
+ return (device_width == 0) ? 8 : 16;
+}
+
+static int ddr3_get_device_size(u32 cs)
+{
+ u32 device_size_low, device_size_high, device_size;
+ u32 data, cs_low_offset, cs_high_offset;
+
+ cs_low_offset = REG_SDRAM_ADDRESS_SIZE_OFFS + cs * 4;
+ cs_high_offset = REG_SDRAM_ADDRESS_SIZE_OFFS +
+ REG_SDRAM_ADDRESS_SIZE_HIGH_OFFS + cs;
+
+ data = reg_read(REG_SDRAM_ADDRESS_CTRL_ADDR);
+ device_size_low = (data >> cs_low_offset) & 0x3;
+ device_size_high = (data >> cs_high_offset) & 0x1;
+
+ device_size = device_size_low | (device_size_high << 2);
+
+ switch (device_size) {
+ case 0:
+ return 2048;
+ case 2:
+ return 512;
+ case 3:
+ return 1024;
+ case 4:
+ return 4096;
+ case 5:
+ return 8192;
+ case 1:
+ default:
+ DEBUG_INIT_C("Error: Wrong device size of Cs: ", cs, 1);
+ /*
+ * Small value will give wrong emem size in
+ * ddr3_calc_mem_cs_size
+ */
+ return 0;
+ }
+}
+
+int ddr3_calc_mem_cs_size(u32 cs, u32 *cs_size)
+{
+ int cs_mem_size;
+
+ /* Calculate in GiB */
+ cs_mem_size = ((ddr3_get_bus_width() / ddr3_get_device_width(cs)) *
+ ddr3_get_device_size(cs)) / 8;
+
+ /*
+ * Multiple controller bus width, 2x for 64 bit
+ * (SoC controller may be 32 or 64 bit,
+ * so bit 15 in 0x1400, that means if whole bus used or only half,
+ * have a differnt meaning
+ */
+ cs_mem_size *= DDR_CONTROLLER_BUS_WIDTH_MULTIPLIER;
+
+ if (!cs_mem_size || (cs_mem_size == 64) || (cs_mem_size == 4096)) {
+ DEBUG_INIT_C("Error: Wrong Memory size of Cs: ", cs, 1);
+ return MV_BAD_VALUE;
+ }
+
+ *cs_size = cs_mem_size << 20;
+ return MV_OK;
+}
+
+/*
+ * Name: ddr3_hws_tune_training_params
+ * Desc:
+ * Args:
+ * Notes: Tune internal training params
+ * Returns:
+ */
+static int ddr3_hws_tune_training_params(u8 dev_num)
+{
+ struct tune_train_params params;
+ int status;
+
+ /* NOTE: do not remove any field initilization */
+ params.ck_delay = TUNE_TRAINING_PARAMS_CK_DELAY;
+ params.ck_delay_16 = TUNE_TRAINING_PARAMS_CK_DELAY_16;
+ params.p_finger = TUNE_TRAINING_PARAMS_PFINGER;
+ params.n_finger = TUNE_TRAINING_PARAMS_NFINGER;
+ params.phy_reg3_val = TUNE_TRAINING_PARAMS_PHYREG3VAL;
+
+ status = ddr3_tip_tune_training_params(dev_num, ¶ms);
+ if (MV_OK != status) {
+ printf("%s Training Sequence - FAILED\n", ddr_type);
+ return status;
+ }
+
+ return MV_OK;
+}
diff --git a/drivers/ddr/marvell/a38x/old/ddr3_init.h b/drivers/ddr/marvell/a38x/old/ddr3_init.h
new file mode 100644
index 0000000..5090cf9
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/ddr3_init.h
@@ -0,0 +1,405 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _DDR3_INIT_H
+#define _DDR3_INIT_H
+
+#if defined(CONFIG_ARMADA_38X)
+#include "ddr3_a38x.h"
+#include "ddr3_a38x_mc_static.h"
+#include "ddr3_a38x_topology.h"
+#endif
+#include "ddr3_hws_hw_training.h"
+#include "ddr3_hws_sil_training.h"
+#include "ddr3_logging_def.h"
+#include "ddr3_training_hw_algo.h"
+#include "ddr3_training_ip.h"
+#include "ddr3_training_ip_centralization.h"
+#include "ddr3_training_ip_engine.h"
+#include "ddr3_training_ip_flow.h"
+#include "ddr3_training_ip_pbs.h"
+#include "ddr3_training_ip_prv_if.h"
+#include "ddr3_training_ip_static.h"
+#include "ddr3_training_leveling.h"
+#include "xor.h"
+
+/*
+ * MV_DEBUG_INIT need to be defines, otherwise the output of the
+ * DDR2 training code is not complete and misleading
+ */
+#define MV_DEBUG_INIT
+
+#ifdef MV_DEBUG_INIT
+#define DEBUG_INIT_S(s) puts(s)
+#define DEBUG_INIT_D(d, l) printf("%x", d)
+#define DEBUG_INIT_D_10(d, l) printf("%d", d)
+#else
+#define DEBUG_INIT_S(s)
+#define DEBUG_INIT_D(d, l)
+#define DEBUG_INIT_D_10(d, l)
+#endif
+
+#ifdef MV_DEBUG_INIT_FULL
+#define DEBUG_INIT_FULL_S(s) puts(s)
+#define DEBUG_INIT_FULL_D(d, l) printf("%x", d)
+#define DEBUG_INIT_FULL_D_10(d, l) printf("%d", d)
+#define DEBUG_WR_REG(reg, val) \
+ { DEBUG_INIT_S("Write Reg: 0x"); DEBUG_INIT_D((reg), 8); \
+ DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); }
+#define DEBUG_RD_REG(reg, val) \
+ { DEBUG_INIT_S("Read Reg: 0x"); DEBUG_INIT_D((reg), 8); \
+ DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); }
+#else
+#define DEBUG_INIT_FULL_S(s)
+#define DEBUG_INIT_FULL_D(d, l)
+#define DEBUG_INIT_FULL_D_10(d, l)
+#define DEBUG_WR_REG(reg, val)
+#define DEBUG_RD_REG(reg, val)
+#endif
+
+#define DEBUG_INIT_FULL_C(s, d, l) \
+ { DEBUG_INIT_FULL_S(s); \
+ DEBUG_INIT_FULL_D(d, l); \
+ DEBUG_INIT_FULL_S("\n"); }
+#define DEBUG_INIT_C(s, d, l) \
+ { DEBUG_INIT_S(s); DEBUG_INIT_D(d, l); DEBUG_INIT_S("\n"); }
+
+/*
+ * Debug (Enable/Disable modules) and Error report
+ */
+
+#ifdef BASIC_DEBUG
+#define MV_DEBUG_WL
+#define MV_DEBUG_RL
+#define MV_DEBUG_DQS_RESULTS
+#endif
+
+#ifdef FULL_DEBUG
+#define MV_DEBUG_WL
+#define MV_DEBUG_RL
+#define MV_DEBUG_DQS
+
+#define MV_DEBUG_PBS
+#define MV_DEBUG_DFS
+#define MV_DEBUG_MAIN_FULL
+#define MV_DEBUG_DFS_FULL
+#define MV_DEBUG_DQS_FULL
+#define MV_DEBUG_RL_FULL
+#define MV_DEBUG_WL_FULL
+#endif
+
+#if defined(CONFIG_ARMADA_38X)
+#include "ddr3_a38x.h"
+#include "ddr3_a38x_topology.h"
+#endif
+
+/* The following is a list of Marvell status */
+#define MV_ERROR (-1)
+#define MV_OK (0x00) /* Operation succeeded */
+#define MV_FAIL (0x01) /* Operation failed */
+#define MV_BAD_VALUE (0x02) /* Illegal value (general) */
+#define MV_OUT_OF_RANGE (0x03) /* The value is out of range */
+#define MV_BAD_PARAM (0x04) /* Illegal parameter in function called */
+#define MV_BAD_PTR (0x05) /* Illegal pointer value */
+#define MV_BAD_SIZE (0x06) /* Illegal size */
+#define MV_BAD_STATE (0x07) /* Illegal state of state machine */
+#define MV_SET_ERROR (0x08) /* Set operation failed */
+#define MV_GET_ERROR (0x09) /* Get operation failed */
+#define MV_CREATE_ERROR (0x0a) /* Fail while creating an item */
+#define MV_NOT_FOUND (0x0b) /* Item not found */
+#define MV_NO_MORE (0x0c) /* No more items found */
+#define MV_NO_SUCH (0x0d) /* No such item */
+#define MV_TIMEOUT (0x0e) /* Time Out */
+#define MV_NO_CHANGE (0x0f) /* Parameter(s) is already in this value */
+#define MV_NOT_SUPPORTED (0x10) /* This request is not support */
+#define MV_NOT_IMPLEMENTED (0x11) /* Request supported but not implemented*/
+#define MV_NOT_INITIALIZED (0x12) /* The item is not initialized */
+#define MV_NO_RESOURCE (0x13) /* Resource not available (memory ...) */
+#define MV_FULL (0x14) /* Item is full (Queue or table etc...) */
+#define MV_EMPTY (0x15) /* Item is empty (Queue or table etc...) */
+#define MV_INIT_ERROR (0x16) /* Error occurred while INIT process */
+#define MV_HW_ERROR (0x17) /* Hardware error */
+#define MV_TX_ERROR (0x18) /* Transmit operation not succeeded */
+#define MV_RX_ERROR (0x19) /* Recieve operation not succeeded */
+#define MV_NOT_READY (0x1a) /* The other side is not ready yet */
+#define MV_ALREADY_EXIST (0x1b) /* Tried to create existing item */
+#define MV_OUT_OF_CPU_MEM (0x1c) /* Cpu memory allocation failed. */
+#define MV_NOT_STARTED (0x1d) /* Not started yet */
+#define MV_BUSY (0x1e) /* Item is busy. */
+#define MV_TERMINATE (0x1f) /* Item terminates it's work. */
+#define MV_NOT_ALIGNED (0x20) /* Wrong alignment */
+#define MV_NOT_ALLOWED (0x21) /* Operation NOT allowed */
+#define MV_WRITE_PROTECT (0x22) /* Write protected */
+#define MV_INVALID (int)(-1)
+
+/* For checking function return values */
+#define CHECK_STATUS(orig_func) \
+ { \
+ int status; \
+ status = orig_func; \
+ if (MV_OK != status) \
+ return status; \
+ }
+
+enum log_level {
+ MV_LOG_LEVEL_0,
+ MV_LOG_LEVEL_1,
+ MV_LOG_LEVEL_2,
+ MV_LOG_LEVEL_3
+};
+
+/* Globals */
+#if defined(CONFIG_DDR_IMMUTABLE_DEBUG_SETTINGS)
+static const u8 is_reg_dump = 0;
+static const u8 debug_training_static = DEBUG_LEVEL_ERROR;
+static const u8 debug_training = DEBUG_LEVEL_ERROR;
+static const u8 debug_leveling = DEBUG_LEVEL_ERROR;
+static const u8 debug_centralization = DEBUG_LEVEL_ERROR;
+static const u8 debug_training_ip = DEBUG_LEVEL_ERROR;
+static const u8 debug_training_bist = DEBUG_LEVEL_ERROR;
+static const u8 debug_training_hw_alg = DEBUG_LEVEL_ERROR;
+static const u8 debug_training_access = DEBUG_LEVEL_ERROR;
+static const u8 debug_training_a38x = DEBUG_LEVEL_ERROR;
+static const u8 debug_pbs = DEBUG_LEVEL_ERROR;
+#else /* !CONFIG_DDR_IMMUTABLE_DEBUG_SETTINGS */
+extern u8 is_reg_dump;
+extern u8 debug_training_static;
+extern u8 debug_training;
+extern u8 debug_leveling;
+extern u8 debug_centralization;
+extern u8 debug_training_ip;
+extern u8 debug_training_bist;
+extern u8 debug_training_hw_alg;
+extern u8 debug_training_access;
+extern u8 debug_training_a38x;
+extern u8 debug_pbs;
+#endif /* !CONFIG_DDR_IMMUTABLE_DEBUG_SETTINGS */
+
+extern u8 generic_init_controller;
+extern u32 freq_val[];
+extern u32 is_pll_old;
+extern struct cl_val_per_freq cas_latency_table[];
+extern struct pattern_info pattern_table[];
+extern struct cl_val_per_freq cas_write_latency_table[];
+extern u32 pipe_multicast_mask;
+extern struct hws_tip_config_func_db config_func_info[];
+extern u8 cs_mask_reg[];
+extern u8 twr_mask_table[];
+extern u8 cl_mask_table[];
+extern u8 cwl_mask_table[];
+extern u16 rfc_table[];
+extern u32 speed_bin_table_t_rc[];
+extern u32 speed_bin_table_t_rcd_t_rp[];
+extern u32 ck_delay, ck_delay_16;
+
+extern u32 g_zpri_data;
+extern u32 g_znri_data;
+extern u32 g_zpri_ctrl;
+extern u32 g_znri_ctrl;
+extern u32 g_zpodt_data;
+extern u32 g_znodt_data;
+extern u32 g_zpodt_ctrl;
+extern u32 g_znodt_ctrl;
+extern u32 g_dic;
+extern u32 g_odt_config;
+extern u32 g_rtt_nom;
+
+extern u32 first_active_if;
+extern enum hws_ddr_freq init_freq;
+extern u32 delay_enable, ck_delay, ck_delay_16, ca_delay;
+extern u32 mask_tune_func;
+extern u32 rl_version;
+extern int rl_mid_freq_wa;
+extern u8 calibration_update_control; /* 2 external only, 1 is internal only */
+extern enum hws_ddr_freq medium_freq;
+
+extern u32 ck_delay, ck_delay_16;
+extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
+extern u32 first_active_if;
+extern u32 mask_tune_func;
+extern u32 freq_val[];
+extern enum hws_ddr_freq init_freq;
+extern enum hws_ddr_freq low_freq;
+extern enum hws_ddr_freq medium_freq;
+extern u8 generic_init_controller;
+extern enum auto_tune_stage training_stage;
+extern u32 is_pll_before_init;
+extern u32 is_adll_calib_before_init;
+extern u32 is_dfs_in_init;
+extern int wl_debug_delay;
+extern u32 silicon_delay[HWS_MAX_DEVICE_NUM];
+extern u32 p_finger;
+extern u32 n_finger;
+extern u32 freq_val[DDR_FREQ_LIMIT];
+extern u32 start_pattern, end_pattern;
+extern u32 phy_reg0_val;
+extern u32 phy_reg1_val;
+extern u32 phy_reg2_val;
+extern u32 phy_reg3_val;
+extern enum hws_pattern sweep_pattern;
+extern enum hws_pattern pbs_pattern;
+extern u8 is_rzq6;
+extern u32 znri_data_phy_val;
+extern u32 zpri_data_phy_val;
+extern u32 znri_ctrl_phy_val;
+extern u32 zpri_ctrl_phy_val;
+extern u32 finger_test, p_finger_start, p_finger_end, n_finger_start,
+ n_finger_end, p_finger_step, n_finger_step;
+extern u32 mode2_t;
+extern u32 xsb_validate_type;
+extern u32 xsb_validation_base_address;
+extern u32 odt_additional;
+extern u32 debug_mode;
+extern u32 delay_enable;
+extern u32 ca_delay;
+extern u32 debug_dunit;
+extern u32 clamp_tbl[];
+extern u32 freq_mask[HWS_MAX_DEVICE_NUM][DDR_FREQ_LIMIT];
+extern u32 start_pattern, end_pattern;
+
+extern u32 maxt_poll_tries;
+
+extern u8 vref_window_size[MAX_INTERFACE_NUM][MAX_BUS_NUM];
+extern u32 debug_mode;
+extern u32 effective_cs;
+extern int ddr3_tip_centr_skip_min_win_check;
+extern u32 *dq_map_table;
+extern enum auto_tune_stage training_stage;
+
+extern u32 delay_enable;
+extern u32 start_pattern, end_pattern;
+extern u32 freq_val[DDR_FREQ_LIMIT];
+extern enum auto_tune_stage training_stage;
+
+extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
+extern enum auto_tune_stage training_stage;
+extern u32 effective_cs;
+
+extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
+extern enum auto_tune_stage training_stage;
+extern u32 rl_version;
+extern struct cl_val_per_freq cas_latency_table[];
+extern u32 start_xsb_offset;
+extern u32 debug_mode;
+extern u32 odt_config;
+extern u32 effective_cs;
+extern u32 phy_reg1_val;
+
+extern u32 effective_cs;
+extern u16 mask_results_dq_reg_map[];
+extern enum hws_ddr_freq medium_freq;
+extern u32 freq_val[];
+extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
+extern enum auto_tune_stage training_stage;
+extern u32 debug_mode;
+extern u32 *dq_map_table;
+
+extern u32 vref;
+extern struct cl_val_per_freq cas_latency_table[];
+extern u32 target_freq;
+extern struct hws_tip_config_func_db config_func_info[HWS_MAX_DEVICE_NUM];
+extern u32 clamp_tbl[];
+#if 0
+extern u32 init_freq;
+#endif
+/* list of allowed frequency listed in order of enum hws_ddr_freq */
+extern u32 freq_val[];
+extern u32 first_active_if;
+
+/* Prototypes */
+int ddr3_tip_enable_init_sequence(u32 dev_num);
+
+int ddr3_tip_init_a38x(u32 dev_num, u32 board_id);
+
+int ddr3_hws_hw_training(void);
+int ddr3_silicon_pre_init(void);
+int ddr3_silicon_post_init(void);
+int ddr3_post_run_alg(void);
+int ddr3_if_ecc_enabled(void);
+void ddr3_new_tip_ecc_scrub(void);
+
+void ddr3_print_version(void);
+void ddr3_new_tip_dlb_config(void);
+struct hws_topology_map *ddr3_get_topology_map(void);
+
+int ddr3_if_ecc_enabled(void);
+int ddr3_tip_reg_write(u32 dev_num, u32 reg_addr, u32 data);
+int ddr3_tip_reg_read(u32 dev_num, u32 reg_addr, u32 *data, u32 reg_mask);
+int ddr3_silicon_get_ddr_target_freq(u32 *ddr_freq);
+int ddr3_tip_a38x_get_freq_config(u8 dev_num, enum hws_ddr_freq freq,
+ struct hws_tip_freq_config_info
+ *freq_config_info);
+int ddr3_a38x_update_topology_map(u32 dev_num,
+ struct hws_topology_map *topology_map);
+int ddr3_tip_a38x_get_init_freq(int dev_num, enum hws_ddr_freq *freq);
+int ddr3_tip_a38x_get_medium_freq(int dev_num, enum hws_ddr_freq *freq);
+int ddr3_tip_a38x_if_read(u8 dev_num, enum hws_access_type interface_access,
+ u32 if_id, u32 reg_addr, u32 *data, u32 mask);
+int ddr3_tip_a38x_if_write(u8 dev_num, enum hws_access_type interface_access,
+ u32 if_id, u32 reg_addr, u32 data, u32 mask);
+int ddr3_tip_a38x_get_device_info(u8 dev_num,
+ struct ddr3_device_info *info_ptr);
+
+int ddr3_tip_init_a38x(u32 dev_num, u32 board_id);
+
+int print_adll(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM]);
+int ddr3_tip_restore_dunit_regs(u32 dev_num);
+void print_topology(struct hws_topology_map *topology_db);
+
+u32 mv_board_id_get(void);
+
+int ddr3_load_topology_map(void);
+int ddr3_tip_init_specific_reg_config(u32 dev_num,
+ struct reg_data *reg_config_arr);
+u32 ddr3_tip_get_init_freq(void);
+void ddr3_hws_set_log_level(enum ddr_lib_debug_block block, u8 level);
+int ddr3_tip_tune_training_params(u32 dev_num,
+ struct tune_train_params *params);
+void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
+int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena);
+void ddr3_fast_path_static_cs_size_config(u32 cs_ena);
+u32 ddr3_get_device_width(u32 cs);
+u32 mv_board_id_index_get(u32 board_id);
+u32 mv_board_id_get(void);
+u32 ddr3_get_bus_width(void);
+void ddr3_set_log_level(u32 n_log_level);
+int ddr3_calc_mem_cs_size(u32 cs, u32 *cs_size);
+
+int hws_ddr3_cs_base_adr_calc(u32 if_id, u32 cs, u32 *cs_base_addr);
+
+int ddr3_tip_print_pbs_result(u32 dev_num, u32 cs_num, enum pbs_dir pbs_mode);
+int ddr3_tip_clean_pbs_result(u32 dev_num, enum pbs_dir pbs_mode);
+
+int ddr3_tip_static_round_trip_arr_build(u32 dev_num,
+ struct trip_delay_element *table_ptr,
+ int is_wl, u32 *round_trip_delay_arr);
+
+u32 hws_ddr3_tip_max_cs_get(void);
+
+/*
+ * Accessor functions for the registers
+ */
+static inline void reg_write(u32 addr, u32 val)
+{
+ writel(val, INTER_REGS_BASE + addr);
+}
+
+static inline u32 reg_read(u32 addr)
+{
+ return readl(INTER_REGS_BASE + addr);
+}
+
+static inline void reg_bit_set(u32 addr, u32 mask)
+{
+ setbits_le32(INTER_REGS_BASE + addr, mask);
+}
+
+static inline void reg_bit_clr(u32 addr, u32 mask)
+{
+ clrbits_le32(INTER_REGS_BASE + addr, mask);
+}
+
+#endif /* _DDR3_INIT_H */
diff --git a/drivers/ddr/marvell/a38x/old/ddr3_logging_def.h b/drivers/ddr/marvell/a38x/old/ddr3_logging_def.h
new file mode 100644
index 0000000..2de7c4f
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/ddr3_logging_def.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _DDR3_LOGGING_CONFIG_H
+#define _DDR3_LOGGING_CONFIG_H
+
+#ifdef SILENT_LIB
+#define DEBUG_TRAINING_BIST_ENGINE(level, s)
+#define DEBUG_TRAINING_IP(level, s)
+#define DEBUG_CENTRALIZATION_ENGINE(level, s)
+#define DEBUG_TRAINING_HW_ALG(level, s)
+#define DEBUG_TRAINING_IP_ENGINE(level, s)
+#define DEBUG_LEVELING(level, s)
+#define DEBUG_PBS_ENGINE(level, s)
+#define DEBUG_TRAINING_STATIC_IP(level, s)
+#define DEBUG_TRAINING_ACCESS(level, s)
+#else
+#ifdef LIB_FUNCTIONAL_DEBUG_ONLY
+#define DEBUG_TRAINING_BIST_ENGINE(level, s)
+#define DEBUG_TRAINING_IP_ENGINE(level, s)
+#define DEBUG_TRAINING_IP(level, s) \
+ if (level >= debug_training) \
+ printf s
+#define DEBUG_CENTRALIZATION_ENGINE(level, s) \
+ if (level >= debug_centralization) \
+ printf s
+#define DEBUG_TRAINING_HW_ALG(level, s) \
+ if (level >= debug_training_hw_alg) \
+ printf s
+#define DEBUG_LEVELING(level, s) \
+ if (level >= debug_leveling) \
+ printf s
+#define DEBUG_PBS_ENGINE(level, s) \
+ if (level >= debug_pbs) \
+ printf s
+#define DEBUG_TRAINING_STATIC_IP(level, s) \
+ if (level >= debug_training_static) \
+ printf s
+#define DEBUG_TRAINING_ACCESS(level, s) \
+ if (level >= debug_training_access) \
+ printf s
+#else
+#define DEBUG_TRAINING_BIST_ENGINE(level, s) \
+ if (level >= debug_training_bist) \
+ printf s
+
+#define DEBUG_TRAINING_IP_ENGINE(level, s) \
+ if (level >= debug_training_ip) \
+ printf s
+#define DEBUG_TRAINING_IP(level, s) \
+ if (level >= debug_training) \
+ printf s
+#define DEBUG_CENTRALIZATION_ENGINE(level, s) \
+ if (level >= debug_centralization) \
+ printf s
+#define DEBUG_TRAINING_HW_ALG(level, s) \
+ if (level >= debug_training_hw_alg) \
+ printf s
+#define DEBUG_LEVELING(level, s) \
+ if (level >= debug_leveling) \
+ printf s
+#define DEBUG_PBS_ENGINE(level, s) \
+ if (level >= debug_pbs) \
+ printf s
+#define DEBUG_TRAINING_STATIC_IP(level, s) \
+ if (level >= debug_training_static) \
+ printf s
+#define DEBUG_TRAINING_ACCESS(level, s) \
+ if (level >= debug_training_access) \
+ printf s
+#endif
+#endif
+
+/* Logging defines */
+#define DEBUG_LEVEL_TRACE 1
+#define DEBUG_LEVEL_INFO 2
+#define DEBUG_LEVEL_ERROR 3
+
+enum ddr_lib_debug_block {
+ DEBUG_BLOCK_STATIC,
+ DEBUG_BLOCK_TRAINING_MAIN,
+ DEBUG_BLOCK_LEVELING,
+ DEBUG_BLOCK_CENTRALIZATION,
+ DEBUG_BLOCK_PBS,
+ DEBUG_BLOCK_IP,
+ DEBUG_BLOCK_BIST,
+ DEBUG_BLOCK_ALG,
+ DEBUG_BLOCK_DEVICE,
+ DEBUG_BLOCK_ACCESS,
+ DEBUG_STAGES_REG_DUMP,
+ /* All excluding IP and REG_DUMP, should be enabled separatelly */
+ DEBUG_BLOCK_ALL
+};
+
+int ddr3_tip_print_log(u32 dev_num, u32 mem_addr);
+int ddr3_tip_print_stability_log(u32 dev_num);
+
+#endif /* _DDR3_LOGGING_CONFIG_H */
diff --git a/drivers/ddr/marvell/a38x/old/ddr3_patterns_64bit.h b/drivers/ddr/marvell/a38x/old/ddr3_patterns_64bit.h
new file mode 100644
index 0000000..0ce0479
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/ddr3_patterns_64bit.h
@@ -0,0 +1,924 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __DDR3_PATTERNS_64_H
+#define __DDR3_PATTERNS_64_H
+
+/*
+ * Patterns Declerations
+ */
+
+u32 wl_sup_pattern[LEN_WL_SUP_PATTERN] __aligned(32) = {
+ 0x04030201, 0x08070605, 0x0c0b0a09, 0x100f0e0d,
+ 0x14131211, 0x18171615, 0x1c1b1a19, 0x201f1e1d,
+ 0x24232221, 0x28272625, 0x2c2b2a29, 0x302f2e2d,
+ 0x34333231, 0x38373635, 0x3c3b3a39, 0x403f3e3d,
+ 0x44434241, 0x48474645, 0x4c4b4a49, 0x504f4e4d,
+ 0x54535251, 0x58575655, 0x5c5b5a59, 0x605f5e5d,
+ 0x64636261, 0x68676665, 0x6c6b6a69, 0x706f6e6d,
+ 0x74737271, 0x78777675, 0x7c7b7a79, 0x807f7e7d
+};
+
+u32 pbs_pattern_32b[2][LEN_PBS_PATTERN] __aligned(32) = {
+ {
+ 0xaaaaaaaa, 0x55555555, 0xaaaaaaaa, 0x55555555,
+ 0xaaaaaaaa, 0x55555555, 0xaaaaaaaa, 0x55555555,
+ 0xaaaaaaaa, 0x55555555, 0xaaaaaaaa, 0x55555555,
+ 0xaaaaaaaa, 0x55555555, 0xaaaaaaaa, 0x55555555
+ },
+ {
+ 0x55555555, 0xaaaaaaaa, 0x55555555, 0xaaaaaaaa,
+ 0x55555555, 0xaaaaaaaa, 0x55555555, 0xaaaaaaaa,
+ 0x55555555, 0xaaaaaaaa, 0x55555555, 0xaaaaaaaa,
+ 0x55555555, 0xaaaaaaaa, 0x55555555, 0xaaaaaaaa
+ }
+};
+
+u32 pbs_pattern_64b[2][LEN_PBS_PATTERN] __aligned(32) = {
+ {
+ 0xaaaaaaaa, 0xaaaaaaaa, 0x55555555, 0x55555555,
+ 0xaaaaaaaa, 0xaaaaaaaa, 0x55555555, 0x55555555,
+ 0xaaaaaaaa, 0xaaaaaaaa, 0x55555555, 0x55555555,
+ 0xaaaaaaaa, 0xaaaaaaaa, 0x55555555, 0x55555555
+ },
+ {
+ 0x55555555, 0x55555555, 0xaaaaaaaa, 0xaaaaaaaa,
+ 0x55555555, 0x55555555, 0xaaaaaaaa, 0xaaaaaaaa,
+ 0x55555555, 0x55555555, 0xaaaaaaaa, 0xaaaaaaaa,
+ 0x55555555, 0x55555555, 0xaaaaaaaa, 0xaaaaaaaa
+ }
+};
+
+u32 rl_pattern[LEN_STD_PATTERN] __aligned(32) = {
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x01010101, 0x01010101, 0x01010101, 0x01010101
+};
+
+u32 killer_pattern_32b[DQ_NUM][LEN_KILLER_PATTERN] __aligned(32) = {
+ {
+ 0x01010101, 0x00000000, 0x01010101, 0xffffffff,
+ 0x01010101, 0x00000000, 0x01010101, 0xffffffff,
+ 0xfefefefe, 0xfefefefe, 0x01010101, 0xfefefefe,
+ 0xfefefefe, 0xfefefefe, 0x01010101, 0xfefefefe,
+ 0x01010101, 0xfefefefe, 0x01010101, 0x01010101,
+ 0x01010101, 0xfefefefe, 0x01010101, 0x01010101,
+ 0xfefefefe, 0x01010101, 0xfefefefe, 0x00000000,
+ 0xfefefefe, 0x01010101, 0xfefefefe, 0x00000000,
+ 0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
+ 0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
+ 0xffffffff, 0x00000000, 0xffffffff, 0x01010101,
+ 0xffffffff, 0x00000000, 0xffffffff, 0x01010101,
+ 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
+ 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
+ 0x00000000, 0x00000000, 0x00000000, 0xfefefefe,
+ 0x00000000, 0x00000000, 0x00000000, 0xfefefefe,
+ 0xfefefefe, 0xffffffff, 0x00000000, 0x00000000,
+ 0xfefefefe, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x00000000, 0xffffffff,
+ 0x00000000, 0xffffffff, 0xffffffff, 0x00000000,
+ 0x00000000, 0xffffffff, 0xffffffff, 0x00000000,
+ 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
+ 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
+ 0xfefefefe, 0x00000000, 0xfefefefe, 0x00000000,
+ 0xfefefefe, 0x00000000, 0xfefefefe, 0x00000000,
+ 0x00000000, 0xffffffff, 0xffffffff, 0x01010101,
+ 0x00000000, 0xffffffff, 0xffffffff, 0x01010101,
+ 0xffffffff, 0xffffffff, 0x01010101, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x01010101, 0x00000000,
+ 0x01010101, 0xffffffff, 0xfefefefe, 0xfefefefe,
+ 0x01010101, 0xffffffff, 0xfefefefe, 0xfefefefe
+ },
+ {
+ 0x02020202, 0x00000000, 0x02020202, 0xffffffff,
+ 0x02020202, 0x00000000, 0x02020202, 0xffffffff,
+ 0xfdfdfdfd, 0xfdfdfdfd, 0x02020202, 0xfdfdfdfd,
+ 0xfdfdfdfd, 0xfdfdfdfd, 0x02020202, 0xfdfdfdfd,
+ 0x02020202, 0xfdfdfdfd, 0x02020202, 0x02020202,
+ 0x02020202, 0xfdfdfdfd, 0x02020202, 0x02020202,
+ 0xfdfdfdfd, 0x02020202, 0xfdfdfdfd, 0x00000000,
+ 0xfdfdfdfd, 0x02020202, 0xfdfdfdfd, 0x00000000,
+ 0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
+ 0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
+ 0xffffffff, 0x00000000, 0xffffffff, 0x02020202,
+ 0xffffffff, 0x00000000, 0xffffffff, 0x02020202,
+ 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
+ 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
+ 0x00000000, 0x00000000, 0x00000000, 0xfdfdfdfd,
+ 0x00000000, 0x00000000, 0x00000000, 0xfdfdfdfd,
+ 0xfdfdfdfd, 0xffffffff, 0x00000000, 0x00000000,
+ 0xfdfdfdfd, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x00000000, 0xffffffff,
+ 0x00000000, 0xffffffff, 0xffffffff, 0x00000000,
+ 0x00000000, 0xffffffff, 0xffffffff, 0x00000000,
+ 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
+ 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
+ 0xfdfdfdfd, 0x00000000, 0xfdfdfdfd, 0x00000000,
+ 0xfdfdfdfd, 0x00000000, 0xfdfdfdfd, 0x00000000,
+ 0x00000000, 0xffffffff, 0xffffffff, 0x02020202,
+ 0x00000000, 0xffffffff, 0xffffffff, 0x02020202,
+ 0xffffffff, 0xffffffff, 0x02020202, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x02020202, 0x00000000,
+ 0x02020202, 0xffffffff, 0xfdfdfdfd, 0xfdfdfdfd,
+ 0x02020202, 0xffffffff, 0xfdfdfdfd, 0xfdfdfdfd
+ },
+ {
+ 0x04040404, 0x00000000, 0x04040404, 0xffffffff,
+ 0x04040404, 0x00000000, 0x04040404, 0xffffffff,
+ 0xfbfbfbfb, 0xfbfbfbfb, 0x04040404, 0xfbfbfbfb,
+ 0xfbfbfbfb, 0xfbfbfbfb, 0x04040404, 0xfbfbfbfb,
+ 0x04040404, 0xfbfbfbfb, 0x04040404, 0x04040404,
+ 0x04040404, 0xfbfbfbfb, 0x04040404, 0x04040404,
+ 0xfbfbfbfb, 0x04040404, 0xfbfbfbfb, 0x00000000,
+ 0xfbfbfbfb, 0x04040404, 0xfbfbfbfb, 0x00000000,
+ 0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
+ 0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
+ 0xffffffff, 0x00000000, 0xffffffff, 0x04040404,
+ 0xffffffff, 0x00000000, 0xffffffff, 0x04040404,
+ 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
+ 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
+ 0x00000000, 0x00000000, 0x00000000, 0xfbfbfbfb,
+ 0x00000000, 0x00000000, 0x00000000, 0xfbfbfbfb,
+ 0xfbfbfbfb, 0xffffffff, 0x00000000, 0x00000000,
+ 0xfbfbfbfb, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x00000000, 0xffffffff,
+ 0x00000000, 0xffffffff, 0xffffffff, 0x00000000,
+ 0x00000000, 0xffffffff, 0xffffffff, 0x00000000,
+ 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
+ 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
+ 0xfbfbfbfb, 0x00000000, 0xfbfbfbfb, 0x00000000,
+ 0xfbfbfbfb, 0x00000000, 0xfbfbfbfb, 0x00000000,
+ 0x00000000, 0xffffffff, 0xffffffff, 0x04040404,
+ 0x00000000, 0xffffffff, 0xffffffff, 0x04040404,
+ 0xffffffff, 0xffffffff, 0x04040404, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x04040404, 0x00000000,
+ 0x04040404, 0xffffffff, 0xfbfbfbfb, 0xfbfbfbfb,
+ 0x04040404, 0xffffffff, 0xfbfbfbfb, 0xfbfbfbfb
+ },
+ {
+ 0x08080808, 0x00000000, 0x08080808, 0xffffffff,
+ 0x08080808, 0x00000000, 0x08080808, 0xffffffff,
+ 0xf7f7f7f7, 0xf7f7f7f7, 0x08080808, 0xf7f7f7f7,
+ 0xf7f7f7f7, 0xf7f7f7f7, 0x08080808, 0xf7f7f7f7,
+ 0x08080808, 0xf7f7f7f7, 0x08080808, 0x08080808,
+ 0x08080808, 0xf7f7f7f7, 0x08080808, 0x08080808,
+ 0xf7f7f7f7, 0x08080808, 0xf7f7f7f7, 0x00000000,
+ 0xf7f7f7f7, 0x08080808, 0xf7f7f7f7, 0x00000000,
+ 0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
+ 0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
+ 0xffffffff, 0x00000000, 0xffffffff, 0x08080808,
+ 0xffffffff, 0x00000000, 0xffffffff, 0x08080808,
+ 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
+ 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
+ 0x00000000, 0x00000000, 0x00000000, 0xf7f7f7f7,
+ 0x00000000, 0x00000000, 0x00000000, 0xf7f7f7f7,
+ 0xf7f7f7f7, 0xffffffff, 0x00000000, 0x00000000,
+ 0xf7f7f7f7, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x00000000, 0xffffffff,
+ 0x00000000, 0xffffffff, 0xffffffff, 0x00000000,
+ 0x00000000, 0xffffffff, 0xffffffff, 0x00000000,
+ 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
+ 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
+ 0xf7f7f7f7, 0x00000000, 0xf7f7f7f7, 0x00000000,
+ 0xf7f7f7f7, 0x00000000, 0xf7f7f7f7, 0x00000000,
+ 0x00000000, 0xffffffff, 0xffffffff, 0x08080808,
+ 0x00000000, 0xffffffff, 0xffffffff, 0x08080808,
+ 0xffffffff, 0xffffffff, 0x08080808, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x08080808, 0x00000000,
+ 0x08080808, 0xffffffff, 0xf7f7f7f7, 0xf7f7f7f7,
+ 0x08080808, 0xffffffff, 0xf7f7f7f7, 0xf7f7f7f7
+ },
+ {
+ 0x10101010, 0x00000000, 0x10101010, 0xffffffff,
+ 0x10101010, 0x00000000, 0x10101010, 0xffffffff,
+ 0xefefefef, 0xefefefef, 0x10101010, 0xefefefef,
+ 0xefefefef, 0xefefefef, 0x10101010, 0xefefefef,
+ 0x10101010, 0xefefefef, 0x10101010, 0x10101010,
+ 0x10101010, 0xefefefef, 0x10101010, 0x10101010,
+ 0xefefefef, 0x10101010, 0xefefefef, 0x00000000,
+ 0xefefefef, 0x10101010, 0xefefefef, 0x00000000,
+ 0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
+ 0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
+ 0xffffffff, 0x00000000, 0xffffffff, 0x10101010,
+ 0xffffffff, 0x00000000, 0xffffffff, 0x10101010,
+ 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
+ 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
+ 0x00000000, 0x00000000, 0x00000000, 0xefefefef,
+ 0x00000000, 0x00000000, 0x00000000, 0xefefefef,
+ 0xefefefef, 0xffffffff, 0x00000000, 0x00000000,
+ 0xefefefef, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x00000000, 0xffffffff,
+ 0x00000000, 0xffffffff, 0xffffffff, 0x00000000,
+ 0x00000000, 0xffffffff, 0xffffffff, 0x00000000,
+ 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
+ 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
+ 0xefefefef, 0x00000000, 0xefefefef, 0x00000000,
+ 0xefefefef, 0x00000000, 0xefefefef, 0x00000000,
+ 0x00000000, 0xffffffff, 0xffffffff, 0x10101010,
+ 0x00000000, 0xffffffff, 0xffffffff, 0x10101010,
+ 0xffffffff, 0xffffffff, 0x10101010, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x10101010, 0x00000000,
+ 0x10101010, 0xffffffff, 0xefefefef, 0xefefefef,
+ 0x10101010, 0xffffffff, 0xefefefef, 0xefefefef
+ },
+ {
+ 0x20202020, 0x00000000, 0x20202020, 0xffffffff,
+ 0x20202020, 0x00000000, 0x20202020, 0xffffffff,
+ 0xdfdfdfdf, 0xdfdfdfdf, 0x20202020, 0xdfdfdfdf,
+ 0xdfdfdfdf, 0xdfdfdfdf, 0x20202020, 0xdfdfdfdf,
+ 0x20202020, 0xdfdfdfdf, 0x20202020, 0x20202020,
+ 0x20202020, 0xdfdfdfdf, 0x20202020, 0x20202020,
+ 0xdfdfdfdf, 0x20202020, 0xdfdfdfdf, 0x00000000,
+ 0xdfdfdfdf, 0x20202020, 0xdfdfdfdf, 0x00000000,
+ 0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
+ 0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
+ 0xffffffff, 0x00000000, 0xffffffff, 0x20202020,
+ 0xffffffff, 0x00000000, 0xffffffff, 0x20202020,
+ 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
+ 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
+ 0x00000000, 0x00000000, 0x00000000, 0xdfdfdfdf,
+ 0x00000000, 0x00000000, 0x00000000, 0xdfdfdfdf,
+ 0xdfdfdfdf, 0xffffffff, 0x00000000, 0x00000000,
+ 0xdfdfdfdf, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x00000000, 0xffffffff,
+ 0x00000000, 0xffffffff, 0xffffffff, 0x00000000,
+ 0x00000000, 0xffffffff, 0xffffffff, 0x00000000,
+ 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
+ 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
+ 0xdfdfdfdf, 0x00000000, 0xdfdfdfdf, 0x00000000,
+ 0xdfdfdfdf, 0x00000000, 0xdfdfdfdf, 0x00000000,
+ 0x00000000, 0xffffffff, 0xffffffff, 0x20202020,
+ 0x00000000, 0xffffffff, 0xffffffff, 0x20202020,
+ 0xffffffff, 0xffffffff, 0x20202020, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x20202020, 0x00000000,
+ 0x20202020, 0xffffffff, 0xdfdfdfdf, 0xdfdfdfdf,
+ 0x20202020, 0xffffffff, 0xdfdfdfdf, 0xdfdfdfdf
+ },
+ {
+ 0x40404040, 0x00000000, 0x40404040, 0xffffffff,
+ 0x40404040, 0x00000000, 0x40404040, 0xffffffff,
+ 0xbfbfbfbf, 0xbfbfbfbf, 0x40404040, 0xbfbfbfbf,
+ 0xbfbfbfbf, 0xbfbfbfbf, 0x40404040, 0xbfbfbfbf,
+ 0x40404040, 0xbfbfbfbf, 0x40404040, 0x40404040,
+ 0x40404040, 0xbfbfbfbf, 0x40404040, 0x40404040,
+ 0xbfbfbfbf, 0x40404040, 0xbfbfbfbf, 0x00000000,
+ 0xbfbfbfbf, 0x40404040, 0xbfbfbfbf, 0x00000000,
+ 0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
+ 0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
+ 0xffffffff, 0x00000000, 0xffffffff, 0x40404040,
+ 0xffffffff, 0x00000000, 0xffffffff, 0x40404040,
+ 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
+ 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
+ 0x00000000, 0x00000000, 0x00000000, 0xbfbfbfbf,
+ 0x00000000, 0x00000000, 0x00000000, 0xbfbfbfbf,
+ 0xbfbfbfbf, 0xffffffff, 0x00000000, 0x00000000,
+ 0xbfbfbfbf, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x00000000, 0xffffffff,
+ 0x00000000, 0xffffffff, 0xffffffff, 0x00000000,
+ 0x00000000, 0xffffffff, 0xffffffff, 0x00000000,
+ 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
+ 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
+ 0xbfbfbfbf, 0x00000000, 0xbfbfbfbf, 0x00000000,
+ 0xbfbfbfbf, 0x00000000, 0xbfbfbfbf, 0x00000000,
+ 0x00000000, 0xffffffff, 0xffffffff, 0x40404040,
+ 0x00000000, 0xffffffff, 0xffffffff, 0x40404040,
+ 0xffffffff, 0xffffffff, 0x40404040, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x40404040, 0x00000000,
+ 0x40404040, 0xffffffff, 0xbfbfbfbf, 0xbfbfbfbf,
+ 0x40404040, 0xffffffff, 0xbfbfbfbf, 0xbfbfbfbf
+ },
+ {
+ 0x80808080, 0x00000000, 0x80808080, 0xffffffff,
+ 0x80808080, 0x00000000, 0x80808080, 0xffffffff,
+ 0x7f7f7f7f, 0x7f7f7f7f, 0x80808080, 0x7f7f7f7f,
+ 0x7f7f7f7f, 0x7f7f7f7f, 0x80808080, 0x7f7f7f7f,
+ 0x80808080, 0x7f7f7f7f, 0x80808080, 0x80808080,
+ 0x80808080, 0x7f7f7f7f, 0x80808080, 0x80808080,
+ 0x7f7f7f7f, 0x80808080, 0x7f7f7f7f, 0x00000000,
+ 0x7f7f7f7f, 0x80808080, 0x7f7f7f7f, 0x00000000,
+ 0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
+ 0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
+ 0xffffffff, 0x00000000, 0xffffffff, 0x80808080,
+ 0xffffffff, 0x00000000, 0xffffffff, 0x80808080,
+ 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
+ 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
+ 0x00000000, 0x00000000, 0x00000000, 0x7f7f7f7f,
+ 0x00000000, 0x00000000, 0x00000000, 0x7f7f7f7f,
+ 0x7f7f7f7f, 0xffffffff, 0x00000000, 0x00000000,
+ 0x7f7f7f7f, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x00000000, 0xffffffff,
+ 0x00000000, 0xffffffff, 0xffffffff, 0x00000000,
+ 0x00000000, 0xffffffff, 0xffffffff, 0x00000000,
+ 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
+ 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
+ 0x7f7f7f7f, 0x00000000, 0x7f7f7f7f, 0x00000000,
+ 0x7f7f7f7f, 0x00000000, 0x7f7f7f7f, 0x00000000,
+ 0x00000000, 0xffffffff, 0xffffffff, 0x80808080,
+ 0x00000000, 0xffffffff, 0xffffffff, 0x80808080,
+ 0xffffffff, 0xffffffff, 0x80808080, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x80808080, 0x00000000,
+ 0x80808080, 0xffffffff, 0x7f7f7f7f, 0x7f7f7f7f,
+ 0x80808080, 0xffffffff, 0x7f7f7f7f, 0x7f7f7f7f
+ }
+};
+
+u32 killer_pattern_64b[DQ_NUM][LEN_KILLER_PATTERN] __aligned(32) = {
+ {
+ 0x01010101, 0x01010101, 0x00000000, 0x00000000,
+ 0x01010101, 0x01010101, 0xffffffff, 0xffffffff,
+ 0xfefefefe, 0xfefefefe, 0xfefefefe, 0xfefefefe,
+ 0x01010101, 0x01010101, 0xfefefefe, 0xfefefefe,
+ 0x01010101, 0x01010101, 0xfefefefe, 0xfefefefe,
+ 0x01010101, 0x01010101, 0x01010101, 0x01010101,
+ 0xfefefefe, 0xfefefefe, 0x01010101, 0x01010101,
+ 0xfefefefe, 0xfefefefe, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x01010101, 0x01010101,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xfefefefe, 0xfefefefe,
+ 0xfefefefe, 0xfefefefe, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0xfefefefe, 0xfefefefe, 0x00000000, 0x00000000,
+ 0xfefefefe, 0xfefefefe, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x01010101, 0x01010101,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x01010101, 0x01010101, 0x00000000, 0x00000000,
+ 0x01010101, 0x01010101, 0xffffffff, 0xffffffff,
+ 0xfefefefe, 0xfefefefe, 0xfefefefe, 0xfefefefe
+ },
+ {
+ 0x02020202, 0x02020202, 0x00000000, 0x00000000,
+ 0x02020202, 0x02020202, 0xffffffff, 0xffffffff,
+ 0xfdfdfdfd, 0xfdfdfdfd, 0xfdfdfdfd, 0xfdfdfdfd,
+ 0x02020202, 0x02020202, 0xfdfdfdfd, 0xfdfdfdfd,
+ 0x02020202, 0x02020202, 0xfdfdfdfd, 0xfdfdfdfd,
+ 0x02020202, 0x02020202, 0x02020202, 0x02020202,
+ 0xfdfdfdfd, 0xfdfdfdfd, 0x02020202, 0x02020202,
+ 0xfdfdfdfd, 0xfdfdfdfd, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x02020202, 0x02020202,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xfdfdfdfd, 0xfdfdfdfd,
+ 0xfdfdfdfd, 0xfdfdfdfd, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0xfdfdfdfd, 0xfdfdfdfd, 0x00000000, 0x00000000,
+ 0xfdfdfdfd, 0xfdfdfdfd, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x02020202, 0x02020202,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x02020202, 0x02020202, 0x00000000, 0x00000000,
+ 0x02020202, 0x02020202, 0xffffffff, 0xffffffff,
+ 0xfdfdfdfd, 0xfdfdfdfd, 0xfdfdfdfd, 0xfdfdfdfd
+ },
+ {
+ 0x04040404, 0x04040404, 0x00000000, 0x00000000,
+ 0x04040404, 0x04040404, 0xffffffff, 0xffffffff,
+ 0xfbfbfbfb, 0xfbfbfbfb, 0xfbfbfbfb, 0xfbfbfbfb,
+ 0x04040404, 0x04040404, 0xfbfbfbfb, 0xfbfbfbfb,
+ 0x04040404, 0x04040404, 0xfbfbfbfb, 0xfbfbfbfb,
+ 0x04040404, 0x04040404, 0x04040404, 0x04040404,
+ 0xfbfbfbfb, 0xfbfbfbfb, 0x04040404, 0x04040404,
+ 0xfbfbfbfb, 0xfbfbfbfb, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x04040404, 0x04040404,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xfbfbfbfb, 0xfbfbfbfb,
+ 0xfbfbfbfb, 0xfbfbfbfb, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0xfbfbfbfb, 0xfbfbfbfb, 0x00000000, 0x00000000,
+ 0xfbfbfbfb, 0xfbfbfbfb, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x04040404, 0x04040404,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x04040404, 0x04040404, 0x00000000, 0x00000000,
+ 0x04040404, 0x04040404, 0xffffffff, 0xffffffff,
+ 0xfbfbfbfb, 0xfbfbfbfb, 0xfbfbfbfb, 0xfbfbfbfb
+ },
+ {
+ 0x08080808, 0x08080808, 0x00000000, 0x00000000,
+ 0x08080808, 0x08080808, 0xffffffff, 0xffffffff,
+ 0xf7f7f7f7, 0xf7f7f7f7, 0xf7f7f7f7, 0xf7f7f7f7,
+ 0x08080808, 0x08080808, 0xf7f7f7f7, 0xf7f7f7f7,
+ 0x08080808, 0x08080808, 0xf7f7f7f7, 0xf7f7f7f7,
+ 0x08080808, 0x08080808, 0x08080808, 0x08080808,
+ 0xf7f7f7f7, 0xf7f7f7f7, 0x08080808, 0x08080808,
+ 0xf7f7f7f7, 0xf7f7f7f7, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x08080808, 0x08080808,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xf7f7f7f7, 0xf7f7f7f7,
+ 0xf7f7f7f7, 0xf7f7f7f7, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0xf7f7f7f7, 0xf7f7f7f7, 0x00000000, 0x00000000,
+ 0xf7f7f7f7, 0xf7f7f7f7, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x08080808, 0x08080808,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x08080808, 0x08080808, 0x00000000, 0x00000000,
+ 0x08080808, 0x08080808, 0xffffffff, 0xffffffff,
+ 0xf7f7f7f7, 0xf7f7f7f7, 0xf7f7f7f7, 0xf7f7f7f7
+ },
+ {
+ 0x10101010, 0x10101010, 0x00000000, 0x00000000,
+ 0x10101010, 0x10101010, 0xffffffff, 0xffffffff,
+ 0xefefefef, 0xefefefef, 0xefefefef, 0xefefefef,
+ 0x10101010, 0x10101010, 0xefefefef, 0xefefefef,
+ 0x10101010, 0x10101010, 0xefefefef, 0xefefefef,
+ 0x10101010, 0x10101010, 0x10101010, 0x10101010,
+ 0xefefefef, 0xefefefef, 0x10101010, 0x10101010,
+ 0xefefefef, 0xefefefef, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x10101010, 0x10101010,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xefefefef, 0xefefefef,
+ 0xefefefef, 0xefefefef, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0xefefefef, 0xefefefef, 0x00000000, 0x00000000,
+ 0xefefefef, 0xefefefef, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x10101010, 0x10101010,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x10101010, 0x10101010, 0x00000000, 0x00000000,
+ 0x10101010, 0x10101010, 0xffffffff, 0xffffffff,
+ 0xefefefef, 0xefefefef, 0xefefefef, 0xefefefef
+ },
+ {
+ 0x20202020, 0x20202020, 0x00000000, 0x00000000,
+ 0x20202020, 0x20202020, 0xffffffff, 0xffffffff,
+ 0xdfdfdfdf, 0xdfdfdfdf, 0xdfdfdfdf, 0xdfdfdfdf,
+ 0x20202020, 0x20202020, 0xdfdfdfdf, 0xdfdfdfdf,
+ 0x20202020, 0x20202020, 0xdfdfdfdf, 0xdfdfdfdf,
+ 0x20202020, 0x20202020, 0x20202020, 0x20202020,
+ 0xdfdfdfdf, 0xdfdfdfdf, 0x20202020, 0x20202020,
+ 0xdfdfdfdf, 0xdfdfdfdf, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x20202020, 0x20202020,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xdfdfdfdf, 0xdfdfdfdf,
+ 0xdfdfdfdf, 0xdfdfdfdf, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0xdfdfdfdf, 0xdfdfdfdf, 0x00000000, 0x00000000,
+ 0xdfdfdfdf, 0xdfdfdfdf, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x20202020, 0x20202020,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x20202020, 0x20202020, 0x00000000, 0x00000000,
+ 0x20202020, 0x20202020, 0xffffffff, 0xffffffff,
+ 0xdfdfdfdf, 0xdfdfdfdf, 0xdfdfdfdf, 0xdfdfdfdf
+ },
+ {
+ 0x40404040, 0x40404040, 0x00000000, 0x00000000,
+ 0x40404040, 0x40404040, 0xffffffff, 0xffffffff,
+ 0xbfbfbfbf, 0xbfbfbfbf, 0xbfbfbfbf, 0xbfbfbfbf,
+ 0x40404040, 0x40404040, 0xbfbfbfbf, 0xbfbfbfbf,
+ 0x40404040, 0x40404040, 0xbfbfbfbf, 0xbfbfbfbf,
+ 0x40404040, 0x40404040, 0x40404040, 0x40404040,
+ 0xbfbfbfbf, 0xbfbfbfbf, 0x40404040, 0x40404040,
+ 0xbfbfbfbf, 0xbfbfbfbf, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x40404040, 0x40404040,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xbfbfbfbf, 0xbfbfbfbf,
+ 0xbfbfbfbf, 0xbfbfbfbf, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0xbfbfbfbf, 0xbfbfbfbf, 0x00000000, 0x00000000,
+ 0xbfbfbfbf, 0xbfbfbfbf, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x40404040, 0x40404040,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x40404040, 0x40404040, 0x00000000, 0x00000000,
+ 0x40404040, 0x40404040, 0xffffffff, 0xffffffff,
+ 0xbfbfbfbf, 0xbfbfbfbf, 0xbfbfbfbf, 0xbfbfbfbf
+ },
+ {
+ 0x80808080, 0x80808080, 0x00000000, 0x00000000,
+ 0x80808080, 0x80808080, 0xffffffff, 0xffffffff,
+ 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f,
+ 0x80808080, 0x80808080, 0x7f7f7f7f, 0x7f7f7f7f,
+ 0x80808080, 0x80808080, 0x7f7f7f7f, 0x7f7f7f7f,
+ 0x80808080, 0x80808080, 0x80808080, 0x80808080,
+ 0x7f7f7f7f, 0x7f7f7f7f, 0x80808080, 0x80808080,
+ 0x7f7f7f7f, 0x7f7f7f7f, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x80808080, 0x80808080,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x7f7f7f7f, 0x7f7f7f7f,
+ 0x7f7f7f7f, 0x7f7f7f7f, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x7f7f7f7f, 0x7f7f7f7f, 0x00000000, 0x00000000,
+ 0x7f7f7f7f, 0x7f7f7f7f, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x80808080, 0x80808080,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x80808080, 0x80808080, 0x00000000, 0x00000000,
+ 0x80808080, 0x80808080, 0xffffffff, 0xffffffff,
+ 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f
+ }
+};
+
+u32 special_pattern[DQ_NUM][LEN_SPECIAL_PATTERN] __aligned(32) = {
+ {
+ 0x00000000, 0x00000000, 0x01010101, 0x01010101,
+ 0xffffffff, 0xffffffff, 0xfefefefe, 0xfefefefe,
+ 0xfefefefe, 0xfefefefe, 0x01010101, 0x01010101,
+ 0xfefefefe, 0xfefefefe, 0x01010101, 0x01010101,
+ 0xfefefefe, 0xfefefefe, 0x01010101, 0x01010101,
+ 0x01010101, 0x01010101, 0xfefefefe, 0xfefefefe,
+ 0x01010101, 0x01010101, 0xfefefefe, 0xfefefefe,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x01010101, 0x01010101, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xfefefefe, 0xfefefefe, 0xfefefefe, 0xfefefefe,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0xfefefefe, 0xfefefefe,
+ 0x00000000, 0x00000000, 0xfefefefe, 0xfefefefe,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x01010101, 0x01010101, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x01010101, 0x01010101,
+ 0x00000000, 0x00000000, 0x01010101, 0x01010101,
+ 0xffffffff, 0xffffffff, 0xfefefefe, 0xfefefefe,
+ 0xfefefefe, 0xfefefefe, 0x00000000, 0x00000000
+ },
+ {
+ 0x00000000, 0x00000000, 0x02020202, 0x02020202,
+ 0xffffffff, 0xffffffff, 0xfdfdfdfd, 0xfdfdfdfd,
+ 0xfdfdfdfd, 0xfdfdfdfd, 0x02020202, 0x02020202,
+ 0xfdfdfdfd, 0xfdfdfdfd, 0x02020202, 0x02020202,
+ 0xfdfdfdfd, 0xfdfdfdfd, 0x02020202, 0x02020202,
+ 0x02020202, 0x02020202, 0xfdfdfdfd, 0xfdfdfdfd,
+ 0x02020202, 0x02020202, 0xfdfdfdfd, 0xfdfdfdfd,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x02020202, 0x02020202, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xfdfdfdfd, 0xfdfdfdfd, 0xfdfdfdfd, 0xfdfdfdfd,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0xfdfdfdfd, 0xfdfdfdfd,
+ 0x00000000, 0x00000000, 0xfdfdfdfd, 0xfdfdfdfd,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x02020202, 0x02020202, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x02020202, 0x02020202,
+ 0x00000000, 0x00000000, 0x02020202, 0x02020202,
+ 0xffffffff, 0xffffffff, 0xfdfdfdfd, 0xfdfdfdfd,
+ 0xfdfdfdfd, 0xfdfdfdfd, 0x00000000, 0x00000000
+ },
+ {
+ 0x00000000, 0x00000000, 0x04040404, 0x04040404,
+ 0xffffffff, 0xffffffff, 0xfbfbfbfb, 0xfbfbfbfb,
+ 0xfbfbfbfb, 0xfbfbfbfb, 0x04040404, 0x04040404,
+ 0xfbfbfbfb, 0xfbfbfbfb, 0x04040404, 0x04040404,
+ 0xfbfbfbfb, 0xfbfbfbfb, 0x04040404, 0x04040404,
+ 0x04040404, 0x04040404, 0xfbfbfbfb, 0xfbfbfbfb,
+ 0x04040404, 0x04040404, 0xfbfbfbfb, 0xfbfbfbfb,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x04040404, 0x04040404, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xfbfbfbfb, 0xfbfbfbfb, 0xfbfbfbfb, 0xfbfbfbfb,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0xfbfbfbfb, 0xfbfbfbfb,
+ 0x00000000, 0x00000000, 0xfbfbfbfb, 0xfbfbfbfb,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x04040404, 0x04040404, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x04040404, 0x04040404,
+ 0x00000000, 0x00000000, 0x04040404, 0x04040404,
+ 0xffffffff, 0xffffffff, 0xfbfbfbfb, 0xfbfbfbfb,
+ 0xfbfbfbfb, 0xfbfbfbfb, 0x00000000, 0x00000000
+ },
+ {
+ 0x00000000, 0x00000000, 0x08080808, 0x08080808,
+ 0xffffffff, 0xffffffff, 0xf7f7f7f7, 0xf7f7f7f7,
+ 0xf7f7f7f7, 0xf7f7f7f7, 0x08080808, 0x08080808,
+ 0xf7f7f7f7, 0xf7f7f7f7, 0x08080808, 0x08080808,
+ 0xf7f7f7f7, 0xf7f7f7f7, 0x08080808, 0x08080808,
+ 0x08080808, 0x08080808, 0xf7f7f7f7, 0xf7f7f7f7,
+ 0x08080808, 0x08080808, 0xf7f7f7f7, 0xf7f7f7f7,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x08080808, 0x08080808, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xf7f7f7f7, 0xf7f7f7f7, 0xf7f7f7f7, 0xf7f7f7f7,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0xf7f7f7f7, 0xf7f7f7f7,
+ 0x00000000, 0x00000000, 0xf7f7f7f7, 0xf7f7f7f7,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x08080808, 0x08080808, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x08080808, 0x08080808,
+ 0x00000000, 0x00000000, 0x08080808, 0x08080808,
+ 0xffffffff, 0xffffffff, 0xf7f7f7f7, 0xf7f7f7f7,
+ 0xf7f7f7f7, 0xf7f7f7f7, 0x00000000, 0x00000000
+ },
+ {
+ 0x00000000, 0x00000000, 0x10101010, 0x10101010,
+ 0xffffffff, 0xffffffff, 0xefefefef, 0xefefefef,
+ 0xefefefef, 0xefefefef, 0x10101010, 0x10101010,
+ 0xefefefef, 0xefefefef, 0x10101010, 0x10101010,
+ 0xefefefef, 0xefefefef, 0x10101010, 0x10101010,
+ 0x10101010, 0x10101010, 0xefefefef, 0xefefefef,
+ 0x10101010, 0x10101010, 0xefefefef, 0xefefefef,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x10101010, 0x10101010, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xefefefef, 0xefefefef, 0xefefefef, 0xefefefef,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0xefefefef, 0xefefefef,
+ 0x00000000, 0x00000000, 0xefefefef, 0xefefefef,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x10101010, 0x10101010, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x10101010, 0x10101010,
+ 0x00000000, 0x00000000, 0x10101010, 0x10101010,
+ 0xffffffff, 0xffffffff, 0xefefefef, 0xefefefef,
+ 0xefefefef, 0xefefefef, 0x00000000, 0x00000000
+ },
+ {
+ 0x00000000, 0x00000000, 0x20202020, 0x20202020,
+ 0xffffffff, 0xffffffff, 0xdfdfdfdf, 0xdfdfdfdf,
+ 0xdfdfdfdf, 0xdfdfdfdf, 0x20202020, 0x20202020,
+ 0xdfdfdfdf, 0xdfdfdfdf, 0x20202020, 0x20202020,
+ 0xdfdfdfdf, 0xdfdfdfdf, 0x20202020, 0x20202020,
+ 0x20202020, 0x20202020, 0xdfdfdfdf, 0xdfdfdfdf,
+ 0x20202020, 0x20202020, 0xdfdfdfdf, 0xdfdfdfdf,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x20202020, 0x20202020, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xdfdfdfdf, 0xdfdfdfdf, 0xdfdfdfdf, 0xdfdfdfdf,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0xdfdfdfdf, 0xdfdfdfdf,
+ 0x00000000, 0x00000000, 0xdfdfdfdf, 0xdfdfdfdf,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x20202020, 0x20202020, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x20202020, 0x20202020,
+ 0x00000000, 0x00000000, 0x20202020, 0x20202020,
+ 0xffffffff, 0xffffffff, 0xdfdfdfdf, 0xdfdfdfdf,
+ 0xdfdfdfdf, 0xdfdfdfdf, 0x00000000, 0x00000000
+ },
+ {
+ 0x00000000, 0x00000000, 0x40404040, 0x40404040,
+ 0xffffffff, 0xffffffff, 0xbfbfbfbf, 0xbfbfbfbf,
+ 0xbfbfbfbf, 0xbfbfbfbf, 0x40404040, 0x40404040,
+ 0xbfbfbfbf, 0xbfbfbfbf, 0x40404040, 0x40404040,
+ 0xbfbfbfbf, 0xbfbfbfbf, 0x40404040, 0x40404040,
+ 0x40404040, 0x40404040, 0xbfbfbfbf, 0xbfbfbfbf,
+ 0x40404040, 0x40404040, 0xbfbfbfbf, 0xbfbfbfbf,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x40404040, 0x40404040, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xbfbfbfbf, 0xbfbfbfbf, 0xbfbfbfbf, 0xbfbfbfbf,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0xbfbfbfbf, 0xbfbfbfbf,
+ 0x00000000, 0x00000000, 0xbfbfbfbf, 0xbfbfbfbf,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x40404040, 0x40404040, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x40404040, 0x40404040,
+ 0x00000000, 0x00000000, 0x40404040, 0x40404040,
+ 0xffffffff, 0xffffffff, 0xbfbfbfbf, 0xbfbfbfbf,
+ 0xbfbfbfbf, 0xbfbfbfbf, 0x00000000, 0x00000000
+ },
+ {
+ 0x00000000, 0x00000000, 0x80808080, 0x80808080,
+ 0xffffffff, 0xffffffff, 0x7f7f7f7f, 0x7f7f7f7f,
+ 0x7f7f7f7f, 0x7f7f7f7f, 0x80808080, 0x80808080,
+ 0x7f7f7f7f, 0x7f7f7f7f, 0x80808080, 0x80808080,
+ 0x7f7f7f7f, 0x7f7f7f7f, 0x80808080, 0x80808080,
+ 0x80808080, 0x80808080, 0x7f7f7f7f, 0x7f7f7f7f,
+ 0x80808080, 0x80808080, 0x7f7f7f7f, 0x7f7f7f7f,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0x80808080, 0x80808080, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x7f7f7f7f, 0x7f7f7f7f,
+ 0x00000000, 0x00000000, 0x7f7f7f7f, 0x7f7f7f7f,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x80808080, 0x80808080, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x80808080, 0x80808080,
+ 0x00000000, 0x00000000, 0x80808080, 0x80808080,
+ 0xffffffff, 0xffffffff, 0x7f7f7f7f, 0x7f7f7f7f,
+ 0x7f7f7f7f, 0x7f7f7f7f, 0x00000000, 0x00000000
+ }
+};
+
+/* Fabric ratios table */
+u32 fabric_ratio[FAB_OPT] = {
+ 0x04010204,
+ 0x04020202,
+ 0x08020306,
+ 0x08020303,
+ 0x04020303,
+ 0x04020204,
+ 0x04010202,
+ 0x08030606,
+ 0x08030505,
+ 0x04020306,
+ 0x0804050a,
+ 0x04030606,
+ 0x04020404,
+ 0x04030306,
+ 0x04020505,
+ 0x08020505,
+ 0x04010303,
+ 0x08050a0a,
+ 0x04030408,
+ 0x04010102,
+ 0x08030306
+};
+
+u32 pbs_dq_mapping[PUP_NUM_64BIT + 1][DQ_NUM] = {
+ {3, 2, 5, 7, 1, 0, 6, 4},
+ {2, 3, 6, 7, 1, 0, 4, 5},
+ {1, 3, 5, 6, 0, 2, 4, 7},
+ {0, 2, 4, 7, 1, 3, 5, 6},
+ {3, 0, 4, 6, 1, 2, 5, 7},
+ {0, 3, 5, 7, 1, 2, 4, 6},
+ {2, 3, 5, 7, 1, 0, 4, 6},
+ {0, 2, 5, 4, 1, 3, 6, 7},
+ {2, 3, 4, 7, 0, 1, 5, 6}
+};
+
+#endif /* __DDR3_PATTERNS_64_H */
diff --git a/drivers/ddr/marvell/a38x/old/ddr3_topology_def.h b/drivers/ddr/marvell/a38x/old/ddr3_topology_def.h
new file mode 100644
index 0000000..64a0447
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/ddr3_topology_def.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _DDR3_TOPOLOGY_DEF_H
+#define _DDR3_TOPOLOGY_DEF_H
+
+/* TOPOLOGY */
+
+enum hws_speed_bin {
+ SPEED_BIN_DDR_800D,
+ SPEED_BIN_DDR_800E,
+ SPEED_BIN_DDR_1066E,
+ SPEED_BIN_DDR_1066F,
+ SPEED_BIN_DDR_1066G,
+ SPEED_BIN_DDR_1333F,
+ SPEED_BIN_DDR_1333G,
+ SPEED_BIN_DDR_1333H,
+ SPEED_BIN_DDR_1333J,
+ SPEED_BIN_DDR_1600G,
+ SPEED_BIN_DDR_1600H,
+ SPEED_BIN_DDR_1600J,
+ SPEED_BIN_DDR_1600K,
+ SPEED_BIN_DDR_1866J,
+ SPEED_BIN_DDR_1866K,
+ SPEED_BIN_DDR_1866L,
+ SPEED_BIN_DDR_1866M,
+ SPEED_BIN_DDR_2133K,
+ SPEED_BIN_DDR_2133L,
+ SPEED_BIN_DDR_2133M,
+ SPEED_BIN_DDR_2133N,
+
+ SPEED_BIN_DDR_1333H_EXT,
+ SPEED_BIN_DDR_1600K_EXT,
+ SPEED_BIN_DDR_1866M_EXT
+};
+
+enum hws_ddr_freq {
+ DDR_FREQ_LOW_FREQ,
+ DDR_FREQ_400,
+ DDR_FREQ_533,
+ DDR_FREQ_667,
+ DDR_FREQ_800,
+ DDR_FREQ_933,
+ DDR_FREQ_1066,
+ DDR_FREQ_311,
+ DDR_FREQ_333,
+ DDR_FREQ_467,
+ DDR_FREQ_850,
+ DDR_FREQ_600,
+ DDR_FREQ_300,
+ DDR_FREQ_900,
+ DDR_FREQ_360,
+ DDR_FREQ_1000,
+ DDR_FREQ_LIMIT
+};
+
+enum speed_bin_table_elements {
+ SPEED_BIN_TRCD,
+ SPEED_BIN_TRP,
+ SPEED_BIN_TRAS,
+ SPEED_BIN_TRC,
+ SPEED_BIN_TRRD1K,
+ SPEED_BIN_TRRD2K,
+ SPEED_BIN_TPD,
+ SPEED_BIN_TFAW1K,
+ SPEED_BIN_TFAW2K,
+ SPEED_BIN_TWTR,
+ SPEED_BIN_TRTP,
+ SPEED_BIN_TWR,
+ SPEED_BIN_TMOD
+};
+
+#endif /* _DDR3_TOPOLOGY_DEF_H */
diff --git a/drivers/ddr/marvell/a38x/old/ddr3_training.c b/drivers/ddr/marvell/a38x/old/ddr3_training.c
new file mode 100644
index 0000000..29b31a0
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/ddr3_training.c
@@ -0,0 +1,2650 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <linux/delay.h>
+
+#include "ddr3_init.h"
+
+#define GET_MAX_VALUE(x, y) \
+ ((x) > (y)) ? (x) : (y)
+#define CEIL_DIVIDE(x, y) \
+ ((x - (x / y) * y) == 0) ? ((x / y) - 1) : (x / y)
+
+#define TIME_2_CLOCK_CYCLES CEIL_DIVIDE
+
+#define GET_CS_FROM_MASK(mask) (cs_mask2_num[mask])
+#define CS_CBE_VALUE(cs_num) (cs_cbe_reg[cs_num])
+
+u32 window_mem_addr = 0;
+u32 phy_reg0_val = 0;
+u32 phy_reg1_val = 8;
+u32 phy_reg2_val = 0;
+u32 phy_reg3_val = 0xa;
+enum hws_ddr_freq init_freq = DDR_FREQ_667;
+enum hws_ddr_freq low_freq = DDR_FREQ_LOW_FREQ;
+enum hws_ddr_freq medium_freq;
+u32 debug_dunit = 0;
+u32 odt_additional = 1;
+u32 *dq_map_table = NULL;
+u32 odt_config = 1;
+
+#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ALLEYCAT3) || \
+ defined(CONFIG_ARMADA_39X)
+u32 is_pll_before_init = 0, is_adll_calib_before_init = 0, is_dfs_in_init = 0;
+u32 dfs_low_freq = 130;
+#else
+u32 is_pll_before_init = 0, is_adll_calib_before_init = 1, is_dfs_in_init = 0;
+u32 dfs_low_freq = 100;
+#endif
+u32 g_rtt_nom_c_s0, g_rtt_nom_c_s1;
+u8 calibration_update_control; /* 2 external only, 1 is internal only */
+
+enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
+enum auto_tune_stage training_stage = INIT_CONTROLLER;
+u32 finger_test = 0, p_finger_start = 11, p_finger_end = 64,
+ n_finger_start = 11, n_finger_end = 64,
+ p_finger_step = 3, n_finger_step = 3;
+u32 clamp_tbl[] = { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 };
+
+/* Initiate to 0xff, this variable is define by user in debug mode */
+u32 mode2_t = 0xff;
+u32 xsb_validate_type = 0;
+u32 xsb_validation_base_address = 0xf000;
+u32 first_active_if = 0;
+u32 dfs_low_phy1 = 0x1f;
+u32 multicast_id = 0;
+int use_broadcast = 0;
+struct hws_tip_freq_config_info *freq_info_table = NULL;
+u8 is_cbe_required = 0;
+u32 debug_mode = 0;
+u32 delay_enable = 0;
+int rl_mid_freq_wa = 0;
+
+u32 effective_cs = 0;
+
+u32 mask_tune_func = (SET_MEDIUM_FREQ_MASK_BIT |
+ WRITE_LEVELING_MASK_BIT |
+ LOAD_PATTERN_2_MASK_BIT |
+ READ_LEVELING_MASK_BIT |
+ SET_TARGET_FREQ_MASK_BIT | WRITE_LEVELING_TF_MASK_BIT |
+ READ_LEVELING_TF_MASK_BIT |
+ CENTRALIZATION_RX_MASK_BIT | CENTRALIZATION_TX_MASK_BIT);
+
+void ddr3_print_version(void)
+{
+ printf(DDR3_TIP_VERSION_STRING);
+}
+
+static int ddr3_tip_ddr3_training_main_flow(u32 dev_num);
+static int ddr3_tip_write_odt(u32 dev_num, enum hws_access_type access_type,
+ u32 if_id, u32 cl_value, u32 cwl_value);
+static int ddr3_tip_ddr3_auto_tune(u32 dev_num);
+static int is_bus_access_done(u32 dev_num, u32 if_id,
+ u32 dunit_reg_adrr, u32 bit);
+#ifdef ODT_TEST_SUPPORT
+static int odt_test(u32 dev_num, enum hws_algo_type algo_type);
+#endif
+
+int adll_calibration(u32 dev_num, enum hws_access_type access_type,
+ u32 if_id, enum hws_ddr_freq frequency);
+static int ddr3_tip_set_timing(u32 dev_num, enum hws_access_type access_type,
+ u32 if_id, enum hws_ddr_freq frequency);
+
+static struct page_element page_param[] = {
+ /*
+ * 8bits 16 bits
+ * page-size(K) page-size(K) mask
+ */
+ { 1, 2, 2},
+ /* 512M */
+ { 1, 2, 3},
+ /* 1G */
+ { 1, 2, 0},
+ /* 2G */
+ { 1, 2, 4},
+ /* 4G */
+ { 2, 2, 5}
+ /* 8G */
+};
+
+static u8 mem_size_config[MEM_SIZE_LAST] = {
+ 0x2, /* 512Mbit */
+ 0x3, /* 1Gbit */
+ 0x0, /* 2Gbit */
+ 0x4, /* 4Gbit */
+ 0x5 /* 8Gbit */
+};
+
+static u8 cs_mask2_num[] = { 0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3 };
+
+static struct reg_data odpg_default_value[] = {
+ {0x1034, 0x38000, MASK_ALL_BITS},
+ {0x1038, 0x0, MASK_ALL_BITS},
+ {0x10b0, 0x0, MASK_ALL_BITS},
+ {0x10b8, 0x0, MASK_ALL_BITS},
+ {0x10c0, 0x0, MASK_ALL_BITS},
+ {0x10f0, 0x0, MASK_ALL_BITS},
+ {0x10f4, 0x0, MASK_ALL_BITS},
+ {0x10f8, 0xff, MASK_ALL_BITS},
+ {0x10fc, 0xffff, MASK_ALL_BITS},
+ {0x1130, 0x0, MASK_ALL_BITS},
+ {0x1830, 0x2000000, MASK_ALL_BITS},
+ {0x14d0, 0x0, MASK_ALL_BITS},
+ {0x14d4, 0x0, MASK_ALL_BITS},
+ {0x14d8, 0x0, MASK_ALL_BITS},
+ {0x14dc, 0x0, MASK_ALL_BITS},
+ {0x1454, 0x0, MASK_ALL_BITS},
+ {0x1594, 0x0, MASK_ALL_BITS},
+ {0x1598, 0x0, MASK_ALL_BITS},
+ {0x159c, 0x0, MASK_ALL_BITS},
+ {0x15a0, 0x0, MASK_ALL_BITS},
+ {0x15a4, 0x0, MASK_ALL_BITS},
+ {0x15a8, 0x0, MASK_ALL_BITS},
+ {0x15ac, 0x0, MASK_ALL_BITS},
+ {0x1604, 0x0, MASK_ALL_BITS},
+ {0x1608, 0x0, MASK_ALL_BITS},
+ {0x160c, 0x0, MASK_ALL_BITS},
+ {0x1610, 0x0, MASK_ALL_BITS},
+ {0x1614, 0x0, MASK_ALL_BITS},
+ {0x1618, 0x0, MASK_ALL_BITS},
+ {0x1624, 0x0, MASK_ALL_BITS},
+ {0x1690, 0x0, MASK_ALL_BITS},
+ {0x1694, 0x0, MASK_ALL_BITS},
+ {0x1698, 0x0, MASK_ALL_BITS},
+ {0x169c, 0x0, MASK_ALL_BITS},
+ {0x14b8, 0x6f67, MASK_ALL_BITS},
+ {0x1630, 0x0, MASK_ALL_BITS},
+ {0x1634, 0x0, MASK_ALL_BITS},
+ {0x1638, 0x0, MASK_ALL_BITS},
+ {0x163c, 0x0, MASK_ALL_BITS},
+ {0x16b0, 0x0, MASK_ALL_BITS},
+ {0x16b4, 0x0, MASK_ALL_BITS},
+ {0x16b8, 0x0, MASK_ALL_BITS},
+ {0x16bc, 0x0, MASK_ALL_BITS},
+ {0x16c0, 0x0, MASK_ALL_BITS},
+ {0x16c4, 0x0, MASK_ALL_BITS},
+ {0x16c8, 0x0, MASK_ALL_BITS},
+ {0x16cc, 0x1, MASK_ALL_BITS},
+ {0x16f0, 0x1, MASK_ALL_BITS},
+ {0x16f4, 0x0, MASK_ALL_BITS},
+ {0x16f8, 0x0, MASK_ALL_BITS},
+ {0x16fc, 0x0, MASK_ALL_BITS}
+};
+
+static int ddr3_tip_bus_access(u32 dev_num, enum hws_access_type interface_access,
+ u32 if_id, enum hws_access_type phy_access,
+ u32 phy_id, enum hws_ddr_phy phy_type, u32 reg_addr,
+ u32 data_value, enum hws_operation oper_type);
+static int ddr3_tip_pad_inv(u32 dev_num, u32 if_id);
+static int ddr3_tip_rank_control(u32 dev_num, u32 if_id);
+
+/*
+ * Update global training parameters by data from user
+ */
+int ddr3_tip_tune_training_params(u32 dev_num,
+ struct tune_train_params *params)
+{
+ if (params->ck_delay != -1)
+ ck_delay = params->ck_delay;
+ if (params->ck_delay_16 != -1)
+ ck_delay_16 = params->ck_delay_16;
+ if (params->phy_reg3_val != -1)
+ phy_reg3_val = params->phy_reg3_val;
+
+ return MV_OK;
+}
+
+/*
+ * Configure CS
+ */
+int ddr3_tip_configure_cs(u32 dev_num, u32 if_id, u32 cs_num, u32 enable)
+{
+ u32 data, addr_hi, data_high;
+ u32 mem_index;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ if (enable == 1) {
+ data = (tm->interface_params[if_id].bus_width ==
+ BUS_WIDTH_8) ? 0 : 1;
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ SDRAM_ACCESS_CONTROL_REG, (data << (cs_num * 4)),
+ 0x3 << (cs_num * 4)));
+ mem_index = tm->interface_params[if_id].memory_size;
+
+ addr_hi = mem_size_config[mem_index] & 0x3;
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ SDRAM_ACCESS_CONTROL_REG,
+ (addr_hi << (2 + cs_num * 4)),
+ 0x3 << (2 + cs_num * 4)));
+
+ data_high = (mem_size_config[mem_index] & 0x4) >> 2;
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ SDRAM_ACCESS_CONTROL_REG,
+ data_high << (20 + cs_num), 1 << (20 + cs_num)));
+
+ /* Enable Address Select Mode */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ SDRAM_ACCESS_CONTROL_REG, 1 << (16 + cs_num),
+ 1 << (16 + cs_num)));
+ }
+ switch (cs_num) {
+ case 0:
+ case 1:
+ case 2:
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ DDR_CONTROL_LOW_REG, (enable << (cs_num + 11)),
+ 1 << (cs_num + 11)));
+ break;
+ case 3:
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ DDR_CONTROL_LOW_REG, (enable << 15), 1 << 15));
+ break;
+ }
+
+ return MV_OK;
+}
+
+/*
+ * Calculate number of CS
+ */
+static int calc_cs_num(u32 dev_num, u32 if_id, u32 *cs_num)
+{
+ u32 cs;
+ u32 bus_cnt;
+ u32 cs_count;
+ u32 cs_bitmask;
+ u32 curr_cs_num = 0;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ for (bus_cnt = 0; bus_cnt < GET_TOPOLOGY_NUM_OF_BUSES(); bus_cnt++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, bus_cnt);
+ cs_count = 0;
+ cs_bitmask = tm->interface_params[if_id].
+ as_bus_params[bus_cnt].cs_bitmask;
+ for (cs = 0; cs < MAX_CS_NUM; cs++) {
+ if ((cs_bitmask >> cs) & 1)
+ cs_count++;
+ }
+
+ if (curr_cs_num == 0) {
+ curr_cs_num = cs_count;
+ } else if (cs_count != curr_cs_num) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("CS number is different per bus (IF %d BUS %d cs_num %d curr_cs_num %d)\n",
+ if_id, bus_cnt, cs_count,
+ curr_cs_num));
+ return MV_NOT_SUPPORTED;
+ }
+ }
+ *cs_num = curr_cs_num;
+
+ return MV_OK;
+}
+
+/*
+ * Init Controller Flow
+ */
+int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_prm)
+{
+ u32 if_id;
+ u32 cs_num;
+ u32 t_refi = 0, t_hclk = 0, t_ckclk = 0, t_faw = 0, t_pd = 0,
+ t_wr = 0, t2t = 0, txpdll = 0;
+ u32 data_value = 0, bus_width = 0, page_size = 0, cs_cnt = 0,
+ mem_mask = 0, bus_index = 0;
+ enum hws_speed_bin speed_bin_index = SPEED_BIN_DDR_2133N;
+ enum hws_mem_size memory_size = MEM_2G;
+ enum hws_ddr_freq freq = init_freq;
+ enum hws_timing timing;
+ u32 cs_mask = 0;
+ u32 cl_value = 0, cwl_val = 0;
+ u32 refresh_interval_cnt = 0, bus_cnt = 0, adll_tap = 0;
+ enum hws_access_type access_type = ACCESS_TYPE_UNICAST;
+ u32 data_read[MAX_INTERFACE_NUM];
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
+ ("Init_controller, do_mrs_phy=%d, is_ctrl64_bit=%d\n",
+ init_cntr_prm->do_mrs_phy,
+ init_cntr_prm->is_ctrl64_bit));
+
+ if (init_cntr_prm->init_phy == 1) {
+ CHECK_STATUS(ddr3_tip_configure_phy(dev_num));
+ }
+
+ if (generic_init_controller == 1) {
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
+ ("active IF %d\n", if_id));
+ mem_mask = 0;
+ for (bus_index = 0;
+ bus_index < GET_TOPOLOGY_NUM_OF_BUSES();
+ bus_index++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, bus_index);
+ mem_mask |=
+ tm->interface_params[if_id].
+ as_bus_params[bus_index].mirror_enable_bitmask;
+ }
+
+ if (mem_mask != 0) {
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST,
+ if_id, CS_ENABLE_REG, 0,
+ 0x8));
+ }
+
+ memory_size =
+ tm->interface_params[if_id].
+ memory_size;
+ speed_bin_index =
+ tm->interface_params[if_id].
+ speed_bin_index;
+ freq = init_freq;
+ t_refi =
+ (tm->interface_params[if_id].
+ interface_temp ==
+ HWS_TEMP_HIGH) ? TREFI_HIGH : TREFI_LOW;
+ t_refi *= 1000; /* psec */
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
+ ("memy_size %d speed_bin_ind %d freq %d t_refi %d\n",
+ memory_size, speed_bin_index, freq,
+ t_refi));
+ /* HCLK & CK CLK in 2:1[ps] */
+ /* t_ckclk is external clock */
+ t_ckclk = (MEGA / freq_val[freq]);
+ /* t_hclk is internal clock */
+ t_hclk = 2 * t_ckclk;
+ refresh_interval_cnt = t_refi / t_hclk; /* no units */
+ bus_width =
+ (DDR3_IS_16BIT_DRAM_MODE(tm->bus_act_mask)
+ == 1) ? (16) : (32);
+
+ if (init_cntr_prm->is_ctrl64_bit)
+ bus_width = 64;
+
+ data_value =
+ (refresh_interval_cnt | 0x4000 |
+ ((bus_width ==
+ 32) ? 0x8000 : 0) | 0x1000000) & ~(1 << 26);
+
+ /* Interface Bus Width */
+ /* SRMode */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ SDRAM_CONFIGURATION_REG, data_value,
+ 0x100ffff));
+
+ /* Interleave first command pre-charge enable (TBD) */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ SDRAM_OPEN_PAGE_CONTROL_REG, (1 << 10),
+ (1 << 10)));
+
+ /* PHY configuration */
+ /*
+ * Postamble Length = 1.5cc, Addresscntl to clk skew
+ * \BD, Preamble length normal, parralal ADLL enable
+ */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ DRAM_PHY_CONFIGURATION, 0x28, 0x3e));
+ if (init_cntr_prm->is_ctrl64_bit) {
+ /* positive edge */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ DRAM_PHY_CONFIGURATION, 0x0,
+ 0xff80));
+ }
+
+ /* calibration block disable */
+ /* Xbar Read buffer select (for Internal access) */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ CALIB_MACHINE_CTRL_REG, 0x1200c,
+ 0x7dffe01c));
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ CALIB_MACHINE_CTRL_REG,
+ calibration_update_control << 3, 0x3 << 3));
+
+ /* Pad calibration control - enable */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ CALIB_MACHINE_CTRL_REG, 0x1, 0x1));
+
+ cs_mask = 0;
+ data_value = 0x7;
+ /*
+ * Address ctrl \96 Part of the Generic code
+ * The next configuration is done:
+ * 1) Memory Size
+ * 2) Bus_width
+ * 3) CS#
+ * 4) Page Number
+ * 5) t_faw
+ * Per Dunit get from the Map_topology the parameters:
+ * Bus_width
+ * t_faw is per Dunit not per CS
+ */
+ page_size =
+ (tm->interface_params[if_id].
+ bus_width ==
+ BUS_WIDTH_8) ? page_param[memory_size].
+ page_size_8bit : page_param[memory_size].
+ page_size_16bit;
+
+ t_faw =
+ (page_size == 1) ? speed_bin_table(speed_bin_index,
+ SPEED_BIN_TFAW1K)
+ : speed_bin_table(speed_bin_index,
+ SPEED_BIN_TFAW2K);
+
+ data_value = TIME_2_CLOCK_CYCLES(t_faw, t_ckclk);
+ data_value = data_value << 24;
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ SDRAM_ACCESS_CONTROL_REG, data_value,
+ 0x7f000000));
+
+ data_value =
+ (tm->interface_params[if_id].
+ bus_width == BUS_WIDTH_8) ? 0 : 1;
+
+ /* create merge cs mask for all cs available in dunit */
+ for (bus_cnt = 0;
+ bus_cnt < GET_TOPOLOGY_NUM_OF_BUSES();
+ bus_cnt++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, bus_cnt);
+ cs_mask |=
+ tm->interface_params[if_id].
+ as_bus_params[bus_cnt].cs_bitmask;
+ }
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
+ ("Init_controller IF %d cs_mask %d\n",
+ if_id, cs_mask));
+ /*
+ * Configure the next upon the Map Topology \96 If the
+ * Dunit is CS0 Configure CS0 if it is multi CS
+ * configure them both: The Bust_width it\92s the
+ * Memory Bus width \96 x8 or x16
+ */
+ for (cs_cnt = 0; cs_cnt < NUM_OF_CS; cs_cnt++) {
+ ddr3_tip_configure_cs(dev_num, if_id, cs_cnt,
+ ((cs_mask & (1 << cs_cnt)) ? 1
+ : 0));
+ }
+
+ if (init_cntr_prm->do_mrs_phy) {
+ /*
+ * MR0 \96 Part of the Generic code
+ * The next configuration is done:
+ * 1) Burst Length
+ * 2) CAS Latency
+ * get for each dunit what is it Speed_bin &
+ * Target Frequency. From those both parameters
+ * get the appropriate Cas_l from the CL table
+ */
+ cl_value =
+ tm->interface_params[if_id].
+ cas_l;
+ cwl_val =
+ tm->interface_params[if_id].
+ cas_wl;
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
+ ("cl_value 0x%x cwl_val 0x%x\n",
+ cl_value, cwl_val));
+
+ data_value =
+ ((cl_mask_table[cl_value] & 0x1) << 2) |
+ ((cl_mask_table[cl_value] & 0xe) << 3);
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ MR0_REG, data_value,
+ (0x7 << 4) | (1 << 2)));
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ MR0_REG, twr_mask_table[t_wr + 1],
+ 0xe00));
+
+ /*
+ * MR1: Set RTT and DIC Design GL values
+ * configured by user
+ */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST,
+ PARAM_NOT_CARE, MR1_REG,
+ g_dic | g_rtt_nom, 0x266));
+
+ /* MR2 - Part of the Generic code */
+ /*
+ * The next configuration is done:
+ * 1) SRT
+ * 2) CAS Write Latency
+ */
+ data_value = (cwl_mask_table[cwl_val] << 3);
+ data_value |=
+ ((tm->interface_params[if_id].
+ interface_temp ==
+ HWS_TEMP_HIGH) ? (1 << 7) : 0);
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ MR2_REG, data_value,
+ (0x7 << 3) | (0x1 << 7) | (0x3 <<
+ 9)));
+ }
+
+ ddr3_tip_write_odt(dev_num, access_type, if_id,
+ cl_value, cwl_val);
+ ddr3_tip_set_timing(dev_num, access_type, if_id, freq);
+
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ DUNIT_CONTROL_HIGH_REG, 0x177,
+ 0x1000177));
+
+ if (init_cntr_prm->is_ctrl64_bit) {
+ /* disable 0.25 cc delay */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ DUNIT_CONTROL_HIGH_REG, 0x0,
+ 0x800));
+ }
+
+ /* reset bit 7 */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ DUNIT_CONTROL_HIGH_REG,
+ (init_cntr_prm->msys_init << 7), (1 << 7)));
+
+ timing = tm->interface_params[if_id].timing;
+
+ if (mode2_t != 0xff) {
+ t2t = mode2_t;
+ } else if (timing != HWS_TIM_DEFAULT) {
+ /* Board topology map is forcing timing */
+ t2t = (timing == HWS_TIM_2T) ? 1 : 0;
+ } else {
+ /* calculate number of CS (per interface) */
+ CHECK_STATUS(calc_cs_num
+ (dev_num, if_id, &cs_num));
+ t2t = (cs_num == 1) ? 0 : 1;
+ }
+
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ DDR_CONTROL_LOW_REG, t2t << 3,
+ 0x3 << 3));
+ /* move the block to ddr3_tip_set_timing - start */
+ t_pd = GET_MAX_VALUE(t_ckclk * 3,
+ speed_bin_table(speed_bin_index,
+ SPEED_BIN_TPD));
+ t_pd = TIME_2_CLOCK_CYCLES(t_pd, t_ckclk);
+ txpdll = GET_MAX_VALUE(t_ckclk * 10, 24);
+ txpdll = CEIL_DIVIDE((txpdll - 1), t_ckclk);
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ DDR_TIMING_REG, txpdll << 4,
+ 0x1f << 4));
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ DDR_TIMING_REG, 0x28 << 9, 0x3f << 9));
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ DDR_TIMING_REG, 0xa << 21, 0xff << 21));
+
+ /* move the block to ddr3_tip_set_timing - end */
+ /* AUTO_ZQC_TIMING */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ TIMING_REG, (AUTO_ZQC_TIMING | (2 << 20)),
+ 0x3fffff));
+ CHECK_STATUS(ddr3_tip_if_read
+ (dev_num, access_type, if_id,
+ DRAM_PHY_CONFIGURATION, data_read, 0x30));
+ data_value =
+ (data_read[if_id] == 0) ? (1 << 11) : 0;
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ DUNIT_CONTROL_HIGH_REG, data_value,
+ (1 << 11)));
+
+ /* Set Active control for ODT write transactions */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST,
+ PARAM_NOT_CARE, 0x1494, g_odt_config,
+ MASK_ALL_BITS));
+ }
+ } else {
+#ifdef STATIC_ALGO_SUPPORT
+ CHECK_STATUS(ddr3_tip_static_init_controller(dev_num));
+#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
+ CHECK_STATUS(ddr3_tip_static_phy_init_controller(dev_num));
+#endif
+#endif /* STATIC_ALGO_SUPPORT */
+ }
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ CHECK_STATUS(ddr3_tip_rank_control(dev_num, if_id));
+
+ if (init_cntr_prm->do_mrs_phy) {
+ CHECK_STATUS(ddr3_tip_pad_inv(dev_num, if_id));
+ }
+
+ /* Pad calibration control - disable */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ CALIB_MACHINE_CTRL_REG, 0x0, 0x1));
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ CALIB_MACHINE_CTRL_REG,
+ calibration_update_control << 3, 0x3 << 3));
+ }
+
+ CHECK_STATUS(ddr3_tip_enable_init_sequence(dev_num));
+
+ if (delay_enable != 0) {
+ adll_tap = MEGA / (freq_val[freq] * 64);
+ ddr3_tip_cmd_addr_init_delay(dev_num, adll_tap);
+ }
+
+ return MV_OK;
+}
+
+/*
+ * Load Topology map
+ */
+int hws_ddr3_tip_load_topology_map(u32 dev_num, struct hws_topology_map *tm)
+{
+ enum hws_speed_bin speed_bin_index;
+ enum hws_ddr_freq freq = DDR_FREQ_LIMIT;
+ u32 if_id;
+
+ freq_val[DDR_FREQ_LOW_FREQ] = dfs_low_freq;
+ tm = ddr3_get_topology_map();
+ CHECK_STATUS(ddr3_tip_get_first_active_if
+ ((u8)dev_num, tm->if_act_mask,
+ &first_active_if));
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
+ ("board IF_Mask=0x%x num_of_bus_per_interface=0x%x\n",
+ tm->if_act_mask,
+ tm->num_of_bus_per_interface));
+
+ /*
+ * if CL, CWL values are missing in topology map, then fill them
+ * according to speedbin tables
+ */
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ speed_bin_index =
+ tm->interface_params[if_id].speed_bin_index;
+ /* TBD memory frequency of interface 0 only is used ! */
+ freq = tm->interface_params[first_active_if].memory_freq;
+
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
+ ("speed_bin_index =%d freq=%d cl=%d cwl=%d\n",
+ speed_bin_index, freq_val[freq],
+ tm->interface_params[if_id].
+ cas_l,
+ tm->interface_params[if_id].
+ cas_wl));
+
+ if (tm->interface_params[if_id].cas_l == 0) {
+ tm->interface_params[if_id].cas_l =
+ cas_latency_table[speed_bin_index].cl_val[freq];
+ }
+
+ if (tm->interface_params[if_id].cas_wl == 0) {
+ tm->interface_params[if_id].cas_wl =
+ cas_write_latency_table[speed_bin_index].cl_val[freq];
+ }
+ }
+
+ return MV_OK;
+}
+
+/*
+ * RANK Control Flow
+ */
+static int ddr3_tip_rank_control(u32 dev_num, u32 if_id)
+{
+ u32 data_value = 0, bus_cnt;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ for (bus_cnt = 1; bus_cnt < GET_TOPOLOGY_NUM_OF_BUSES(); bus_cnt++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, bus_cnt);
+ if ((tm->interface_params[if_id].
+ as_bus_params[0].cs_bitmask !=
+ tm->interface_params[if_id].
+ as_bus_params[bus_cnt].cs_bitmask) ||
+ (tm->interface_params[if_id].
+ as_bus_params[0].mirror_enable_bitmask !=
+ tm->interface_params[if_id].
+ as_bus_params[bus_cnt].mirror_enable_bitmask))
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("WARNING:Wrong configuration for pup #%d CS mask and CS mirroring for all pups should be the same\n",
+ bus_cnt));
+ }
+
+ data_value |= tm->interface_params[if_id].
+ as_bus_params[0].cs_bitmask;
+ data_value |= tm->interface_params[if_id].
+ as_bus_params[0].mirror_enable_bitmask << 4;
+
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id, RANK_CTRL_REG,
+ data_value, 0xff));
+
+ return MV_OK;
+}
+
+/*
+ * PAD Inverse Flow
+ */
+static int ddr3_tip_pad_inv(u32 dev_num, u32 if_id)
+{
+ u32 bus_cnt, data_value, ck_swap_pup_ctrl;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ for (bus_cnt = 0; bus_cnt < GET_TOPOLOGY_NUM_OF_BUSES(); bus_cnt++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, bus_cnt);
+ if (tm->interface_params[if_id].
+ as_bus_params[bus_cnt].is_dqs_swap == 1) {
+ /* dqs swap */
+ ddr3_tip_bus_read_modify_write(dev_num, ACCESS_TYPE_UNICAST,
+ if_id, bus_cnt,
+ DDR_PHY_DATA,
+ PHY_CONTROL_PHY_REG, 0xc0,
+ 0xc0);
+ }
+
+ if (tm->interface_params[if_id].
+ as_bus_params[bus_cnt].is_ck_swap == 1) {
+ if (bus_cnt <= 1)
+ data_value = 0x5 << 2;
+ else
+ data_value = 0xa << 2;
+
+ /* mask equals data */
+ /* ck swap pup is only control pup #0 ! */
+ ck_swap_pup_ctrl = 0;
+ ddr3_tip_bus_read_modify_write(dev_num, ACCESS_TYPE_UNICAST,
+ if_id, ck_swap_pup_ctrl,
+ DDR_PHY_CONTROL,
+ PHY_CONTROL_PHY_REG,
+ data_value, data_value);
+ }
+ }
+
+ return MV_OK;
+}
+
+/*
+ * Run Training Flow
+ */
+int hws_ddr3_tip_run_alg(u32 dev_num, enum hws_algo_type algo_type)
+{
+ int ret = MV_OK, ret_tune = MV_OK;
+
+#ifdef ODT_TEST_SUPPORT
+ if (finger_test == 1)
+ return odt_test(dev_num, algo_type);
+#endif
+
+ if (algo_type == ALGO_TYPE_DYNAMIC) {
+ ret = ddr3_tip_ddr3_auto_tune(dev_num);
+ } else {
+#ifdef STATIC_ALGO_SUPPORT
+ {
+ enum hws_ddr_freq freq;
+ freq = init_freq;
+
+ /* add to mask */
+ if (is_adll_calib_before_init != 0) {
+ printf("with adll calib before init\n");
+ adll_calibration(dev_num, ACCESS_TYPE_MULTICAST,
+ 0, freq);
+ }
+ /*
+ * Frequency per interface is not relevant,
+ * only interface 0
+ */
+ ret = ddr3_tip_run_static_alg(dev_num,
+ freq);
+ }
+#endif
+ }
+
+ if (ret != MV_OK) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("Run_alg: tuning failed %d\n", ret_tune));
+ }
+
+ return ret;
+}
+
+#ifdef ODT_TEST_SUPPORT
+/*
+ * ODT Test
+ */
+static int odt_test(u32 dev_num, enum hws_algo_type algo_type)
+{
+ int ret = MV_OK, ret_tune = MV_OK;
+ int pfinger_val = 0, nfinger_val;
+
+ for (pfinger_val = p_finger_start; pfinger_val <= p_finger_end;
+ pfinger_val += p_finger_step) {
+ for (nfinger_val = n_finger_start; nfinger_val <= n_finger_end;
+ nfinger_val += n_finger_step) {
+ if (finger_test != 0) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("pfinger_val %d nfinger_val %d\n",
+ pfinger_val, nfinger_val));
+ p_finger = pfinger_val;
+ n_finger = nfinger_val;
+ }
+
+ if (algo_type == ALGO_TYPE_DYNAMIC) {
+ ret = ddr3_tip_ddr3_auto_tune(dev_num);
+ } else {
+ /*
+ * Frequency per interface is not relevant,
+ * only interface 0
+ */
+ ret = ddr3_tip_run_static_alg(dev_num,
+ init_freq);
+ }
+ }
+ }
+
+ if (ret_tune != MV_OK) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("Run_alg: tuning failed %d\n", ret_tune));
+ ret = (ret == MV_OK) ? ret_tune : ret;
+ }
+
+ return ret;
+}
+#endif
+
+/*
+ * Select Controller
+ */
+int hws_ddr3_tip_select_ddr_controller(u32 dev_num, int enable)
+{
+ if (config_func_info[dev_num].tip_dunit_mux_select_func != NULL) {
+ return config_func_info[dev_num].
+ tip_dunit_mux_select_func((u8)dev_num, enable);
+ }
+
+ return MV_FAIL;
+}
+
+/*
+ * Dunit Register Write
+ */
+int ddr3_tip_if_write(u32 dev_num, enum hws_access_type interface_access,
+ u32 if_id, u32 reg_addr, u32 data_value, u32 mask)
+{
+ if (config_func_info[dev_num].tip_dunit_write_func != NULL) {
+ return config_func_info[dev_num].
+ tip_dunit_write_func((u8)dev_num, interface_access,
+ if_id, reg_addr,
+ data_value, mask);
+ }
+
+ return MV_FAIL;
+}
+
+/*
+ * Dunit Register Read
+ */
+int ddr3_tip_if_read(u32 dev_num, enum hws_access_type interface_access,
+ u32 if_id, u32 reg_addr, u32 *data, u32 mask)
+{
+ if (config_func_info[dev_num].tip_dunit_read_func != NULL) {
+ return config_func_info[dev_num].
+ tip_dunit_read_func((u8)dev_num, interface_access,
+ if_id, reg_addr,
+ data, mask);
+ }
+
+ return MV_FAIL;
+}
+
+/*
+ * Dunit Register Polling
+ */
+int ddr3_tip_if_polling(u32 dev_num, enum hws_access_type access_type,
+ u32 if_id, u32 exp_value, u32 mask, u32 offset,
+ u32 poll_tries)
+{
+ u32 poll_cnt = 0, interface_num = 0, start_if, end_if;
+ u32 read_data[MAX_INTERFACE_NUM];
+ int ret;
+ int is_fail = 0, is_if_fail;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ if (access_type == ACCESS_TYPE_MULTICAST) {
+ start_if = 0;
+ end_if = MAX_INTERFACE_NUM - 1;
+ } else {
+ start_if = if_id;
+ end_if = if_id;
+ }
+
+ for (interface_num = start_if; interface_num <= end_if; interface_num++) {
+ /* polling bit 3 for n times */
+ VALIDATE_ACTIVE(tm->if_act_mask, interface_num);
+
+ is_if_fail = 0;
+ for (poll_cnt = 0; poll_cnt < poll_tries; poll_cnt++) {
+ ret =
+ ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST,
+ interface_num, offset, read_data,
+ mask);
+ if (ret != MV_OK)
+ return ret;
+
+ if (read_data[interface_num] == exp_value)
+ break;
+ }
+
+ if (poll_cnt >= poll_tries) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("max poll IF #%d\n", interface_num));
+ is_fail = 1;
+ is_if_fail = 1;
+ }
+
+ training_result[training_stage][interface_num] =
+ (is_if_fail == 1) ? TEST_FAILED : TEST_SUCCESS;
+ }
+
+ return (is_fail == 0) ? MV_OK : MV_FAIL;
+}
+
+/*
+ * Bus read access
+ */
+int ddr3_tip_bus_read(u32 dev_num, u32 if_id,
+ enum hws_access_type phy_access, u32 phy_id,
+ enum hws_ddr_phy phy_type, u32 reg_addr, u32 *data)
+{
+ u32 bus_index = 0;
+ u32 data_read[MAX_INTERFACE_NUM];
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ if (phy_access == ACCESS_TYPE_MULTICAST) {
+ for (bus_index = 0; bus_index < GET_TOPOLOGY_NUM_OF_BUSES();
+ bus_index++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, bus_index);
+ CHECK_STATUS(ddr3_tip_bus_access
+ (dev_num, ACCESS_TYPE_UNICAST,
+ if_id, ACCESS_TYPE_UNICAST,
+ bus_index, phy_type, reg_addr, 0,
+ OPERATION_READ));
+ CHECK_STATUS(ddr3_tip_if_read
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ PHY_REG_FILE_ACCESS, data_read,
+ MASK_ALL_BITS));
+ data[bus_index] = (data_read[if_id] & 0xffff);
+ }
+ } else {
+ CHECK_STATUS(ddr3_tip_bus_access
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ phy_access, phy_id, phy_type, reg_addr, 0,
+ OPERATION_READ));
+ CHECK_STATUS(ddr3_tip_if_read
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ PHY_REG_FILE_ACCESS, data_read, MASK_ALL_BITS));
+
+ /*
+ * only 16 lsb bit are valid in Phy (each register is different,
+ * some can actually be less than 16 bits)
+ */
+ *data = (data_read[if_id] & 0xffff);
+ }
+
+ return MV_OK;
+}
+
+/*
+ * Bus write access
+ */
+int ddr3_tip_bus_write(u32 dev_num, enum hws_access_type interface_access,
+ u32 if_id, enum hws_access_type phy_access,
+ u32 phy_id, enum hws_ddr_phy phy_type, u32 reg_addr,
+ u32 data_value)
+{
+ CHECK_STATUS(ddr3_tip_bus_access
+ (dev_num, interface_access, if_id, phy_access,
+ phy_id, phy_type, reg_addr, data_value, OPERATION_WRITE));
+
+ return MV_OK;
+}
+
+/*
+ * Bus access routine (relevant for both read & write)
+ */
+static int ddr3_tip_bus_access(u32 dev_num, enum hws_access_type interface_access,
+ u32 if_id, enum hws_access_type phy_access,
+ u32 phy_id, enum hws_ddr_phy phy_type, u32 reg_addr,
+ u32 data_value, enum hws_operation oper_type)
+{
+ u32 addr_low = 0x3f & reg_addr;
+ u32 addr_hi = ((0xc0 & reg_addr) >> 6);
+ u32 data_p1 =
+ (oper_type << 30) + (addr_hi << 28) + (phy_access << 27) +
+ (phy_type << 26) + (phy_id << 22) + (addr_low << 16) +
+ (data_value & 0xffff);
+ u32 data_p2 = data_p1 + (1 << 31);
+ u32 start_if, end_if;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, interface_access, if_id, PHY_REG_FILE_ACCESS,
+ data_p1, MASK_ALL_BITS));
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, interface_access, if_id, PHY_REG_FILE_ACCESS,
+ data_p2, MASK_ALL_BITS));
+
+ if (interface_access == ACCESS_TYPE_UNICAST) {
+ start_if = if_id;
+ end_if = if_id;
+ } else {
+ start_if = 0;
+ end_if = MAX_INTERFACE_NUM - 1;
+ }
+
+ /* polling for read/write execution done */
+ for (if_id = start_if; if_id <= end_if; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ CHECK_STATUS(is_bus_access_done
+ (dev_num, if_id, PHY_REG_FILE_ACCESS, 31));
+ }
+
+ return MV_OK;
+}
+
+/*
+ * Check bus access done
+ */
+static int is_bus_access_done(u32 dev_num, u32 if_id, u32 dunit_reg_adrr,
+ u32 bit)
+{
+ u32 rd_data = 1;
+ u32 cnt = 0;
+ u32 data_read[MAX_INTERFACE_NUM];
+
+ CHECK_STATUS(ddr3_tip_if_read
+ (dev_num, ACCESS_TYPE_UNICAST, if_id, dunit_reg_adrr,
+ data_read, MASK_ALL_BITS));
+ rd_data = data_read[if_id];
+ rd_data &= (1 << bit);
+
+ while (rd_data != 0) {
+ if (cnt++ >= MAX_POLLING_ITERATIONS)
+ break;
+
+ CHECK_STATUS(ddr3_tip_if_read
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ dunit_reg_adrr, data_read, MASK_ALL_BITS));
+ rd_data = data_read[if_id];
+ rd_data &= (1 << bit);
+ }
+
+ if (cnt < MAX_POLLING_ITERATIONS)
+ return MV_OK;
+ else
+ return MV_FAIL;
+}
+
+/*
+ * Phy read-modify-write
+ */
+int ddr3_tip_bus_read_modify_write(u32 dev_num, enum hws_access_type access_type,
+ u32 interface_id, u32 phy_id,
+ enum hws_ddr_phy phy_type, u32 reg_addr,
+ u32 data_value, u32 reg_mask)
+{
+ u32 data_val = 0, if_id, start_if, end_if;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ if (access_type == ACCESS_TYPE_MULTICAST) {
+ start_if = 0;
+ end_if = MAX_INTERFACE_NUM - 1;
+ } else {
+ start_if = interface_id;
+ end_if = interface_id;
+ }
+
+ for (if_id = start_if; if_id <= end_if; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ CHECK_STATUS(ddr3_tip_bus_read
+ (dev_num, if_id, ACCESS_TYPE_UNICAST, phy_id,
+ phy_type, reg_addr, &data_val));
+ data_value = (data_val & (~reg_mask)) | (data_value & reg_mask);
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ ACCESS_TYPE_UNICAST, phy_id, phy_type, reg_addr,
+ data_value));
+ }
+
+ return MV_OK;
+}
+
+/*
+ * ADLL Calibration
+ */
+int adll_calibration(u32 dev_num, enum hws_access_type access_type,
+ u32 if_id, enum hws_ddr_freq frequency)
+{
+ struct hws_tip_freq_config_info freq_config_info;
+ u32 bus_cnt = 0;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ /* Reset Diver_b assert -> de-assert */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id, SDRAM_CONFIGURATION_REG,
+ 0, 0x10000000));
+ mdelay(10);
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id, SDRAM_CONFIGURATION_REG,
+ 0x10000000, 0x10000000));
+
+ if (config_func_info[dev_num].tip_get_freq_config_info_func != NULL) {
+ CHECK_STATUS(config_func_info[dev_num].
+ tip_get_freq_config_info_func((u8)dev_num, frequency,
+ &freq_config_info));
+ } else {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("tip_get_freq_config_info_func is NULL"));
+ return MV_NOT_INITIALIZED;
+ }
+
+ for (bus_cnt = 0; bus_cnt < GET_TOPOLOGY_NUM_OF_BUSES(); bus_cnt++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, bus_cnt);
+ CHECK_STATUS(ddr3_tip_bus_read_modify_write
+ (dev_num, access_type, if_id, bus_cnt,
+ DDR_PHY_DATA, BW_PHY_REG,
+ freq_config_info.bw_per_freq << 8, 0x700));
+ CHECK_STATUS(ddr3_tip_bus_read_modify_write
+ (dev_num, access_type, if_id, bus_cnt,
+ DDR_PHY_DATA, RATE_PHY_REG,
+ freq_config_info.rate_per_freq, 0x7));
+ }
+
+ /* DUnit to Phy drive post edge, ADLL reset assert de-assert */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id, DRAM_PHY_CONFIGURATION,
+ 0, (0x80000000 | 0x40000000)));
+ mdelay(100 / (freq_val[frequency] / freq_val[DDR_FREQ_LOW_FREQ]));
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id, DRAM_PHY_CONFIGURATION,
+ (0x80000000 | 0x40000000), (0x80000000 | 0x40000000)));
+
+ /* polling for ADLL Done */
+ if (ddr3_tip_if_polling(dev_num, access_type, if_id,
+ 0x3ff03ff, 0x3ff03ff, PHY_LOCK_STATUS_REG,
+ MAX_POLLING_ITERATIONS) != MV_OK) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("Freq_set: DDR3 poll failed(1)"));
+ }
+
+ /* pup data_pup reset assert-> deassert */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id, SDRAM_CONFIGURATION_REG,
+ 0, 0x60000000));
+ mdelay(10);
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id, SDRAM_CONFIGURATION_REG,
+ 0x60000000, 0x60000000));
+
+ return MV_OK;
+}
+
+int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type,
+ u32 if_id, enum hws_ddr_freq frequency)
+{
+ u32 cl_value = 0, cwl_value = 0, mem_mask = 0, val = 0,
+ bus_cnt = 0, t_hclk = 0, t_wr = 0,
+ refresh_interval_cnt = 0, cnt_id;
+ u32 t_refi = 0, end_if, start_if;
+ u32 bus_index = 0;
+ int is_dll_off = 0;
+ enum hws_speed_bin speed_bin_index = 0;
+ struct hws_tip_freq_config_info freq_config_info;
+ enum hws_result *flow_result = training_result[training_stage];
+ u32 adll_tap = 0;
+ u32 cs_mask[MAX_INTERFACE_NUM];
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
+ ("dev %d access %d IF %d freq %d\n", dev_num,
+ access_type, if_id, frequency));
+
+ if (frequency == DDR_FREQ_LOW_FREQ)
+ is_dll_off = 1;
+ if (access_type == ACCESS_TYPE_MULTICAST) {
+ start_if = 0;
+ end_if = MAX_INTERFACE_NUM - 1;
+ } else {
+ start_if = if_id;
+ end_if = if_id;
+ }
+
+ /* calculate interface cs mask - Oferb 4/11 */
+ /* speed bin can be different for each interface */
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ /* cs enable is active low */
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ cs_mask[if_id] = CS_BIT_MASK;
+ training_result[training_stage][if_id] = TEST_SUCCESS;
+ ddr3_tip_calc_cs_mask(dev_num, if_id, effective_cs,
+ &cs_mask[if_id]);
+ }
+
+ /* speed bin can be different for each interface */
+ /*
+ * moti b - need to remove the loop for multicas access functions
+ * and loop the unicast access functions
+ */
+ for (if_id = start_if; if_id <= end_if; if_id++) {
+ if (IS_ACTIVE(tm->if_act_mask, if_id) == 0)
+ continue;
+
+ flow_result[if_id] = TEST_SUCCESS;
+ speed_bin_index =
+ tm->interface_params[if_id].speed_bin_index;
+ if (tm->interface_params[if_id].memory_freq ==
+ frequency) {
+ cl_value =
+ tm->interface_params[if_id].cas_l;
+ cwl_value =
+ tm->interface_params[if_id].cas_wl;
+ } else {
+ cl_value =
+ cas_latency_table[speed_bin_index].cl_val[frequency];
+ cwl_value =
+ cas_write_latency_table[speed_bin_index].
+ cl_val[frequency];
+ }
+
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
+ ("Freq_set dev 0x%x access 0x%x if 0x%x freq 0x%x speed %d:\n\t",
+ dev_num, access_type, if_id,
+ frequency, speed_bin_index));
+
+ for (cnt_id = 0; cnt_id < DDR_FREQ_LIMIT; cnt_id++) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
+ ("%d ",
+ cas_latency_table[speed_bin_index].
+ cl_val[cnt_id]));
+ }
+
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE, ("\n"));
+ mem_mask = 0;
+ for (bus_index = 0; bus_index < GET_TOPOLOGY_NUM_OF_BUSES();
+ bus_index++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, bus_index);
+ mem_mask |=
+ tm->interface_params[if_id].
+ as_bus_params[bus_index].mirror_enable_bitmask;
+ }
+
+ if (mem_mask != 0) {
+ /* motib redundant in KW28 */
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
+ if_id,
+ CS_ENABLE_REG, 0, 0x8));
+ }
+
+ /* dll state after exiting SR */
+ if (is_dll_off == 1) {
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ DFS_REG, 0x1, 0x1));
+ } else {
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ DFS_REG, 0, 0x1));
+ }
+
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ DUNIT_MMASK_REG, 0, 0x1));
+ /* DFS - block transactions */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ DFS_REG, 0x2, 0x2));
+
+ /* disable ODT in case of dll off */
+ if (is_dll_off == 1) {
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ 0x1874, 0, 0x244));
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ 0x1884, 0, 0x244));
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ 0x1894, 0, 0x244));
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ 0x18a4, 0, 0x244));
+ }
+
+ /* DFS - Enter Self-Refresh */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id, DFS_REG, 0x4,
+ 0x4));
+ /* polling on self refresh entry */
+ if (ddr3_tip_if_polling(dev_num, ACCESS_TYPE_UNICAST,
+ if_id, 0x8, 0x8, DFS_REG,
+ MAX_POLLING_ITERATIONS) != MV_OK) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("Freq_set: DDR3 poll failed on SR entry\n"));
+ }
+
+ /* PLL configuration */
+ if (config_func_info[dev_num].tip_set_freq_divider_func != NULL) {
+ config_func_info[dev_num].
+ tip_set_freq_divider_func(dev_num, if_id,
+ frequency);
+ }
+
+ /* PLL configuration End */
+
+ /* adjust t_refi to new frequency */
+ t_refi = (tm->interface_params[if_id].interface_temp ==
+ HWS_TEMP_HIGH) ? TREFI_LOW : TREFI_HIGH;
+ t_refi *= 1000; /*psec */
+
+ /* HCLK in[ps] */
+ t_hclk = MEGA / (freq_val[frequency] / 2);
+ refresh_interval_cnt = t_refi / t_hclk; /* no units */
+ val = 0x4000 | refresh_interval_cnt;
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ SDRAM_CONFIGURATION_REG, val, 0x7fff));
+
+ /* DFS - CL/CWL/WR parameters after exiting SR */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id, DFS_REG,
+ (cl_mask_table[cl_value] << 8), 0xf00));
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id, DFS_REG,
+ (cwl_mask_table[cwl_value] << 12), 0x7000));
+ t_wr = speed_bin_table(speed_bin_index, SPEED_BIN_TWR);
+ t_wr = (t_wr / 1000);
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id, DFS_REG,
+ (twr_mask_table[t_wr + 1] << 16), 0x70000));
+
+ /* Restore original RTT values if returning from DLL OFF mode */
+ if (is_dll_off == 1) {
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id, 0x1874,
+ g_dic | g_rtt_nom, 0x266));
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id, 0x1884,
+ g_dic | g_rtt_nom, 0x266));
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id, 0x1894,
+ g_dic | g_rtt_nom, 0x266));
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id, 0x18a4,
+ g_dic | g_rtt_nom, 0x266));
+ }
+
+ /* Reset Diver_b assert -> de-assert */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ SDRAM_CONFIGURATION_REG, 0, 0x10000000));
+ mdelay(10);
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ SDRAM_CONFIGURATION_REG, 0x10000000, 0x10000000));
+
+ /* Adll configuration function of process and Frequency */
+ if (config_func_info[dev_num].tip_get_freq_config_info_func != NULL) {
+ CHECK_STATUS(config_func_info[dev_num].
+ tip_get_freq_config_info_func(dev_num, frequency,
+ &freq_config_info));
+ }
+ /* TBD check milo5 using device ID ? */
+ for (bus_cnt = 0; bus_cnt < GET_TOPOLOGY_NUM_OF_BUSES();
+ bus_cnt++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, bus_cnt);
+ CHECK_STATUS(ddr3_tip_bus_read_modify_write
+ (dev_num, ACCESS_TYPE_UNICAST,
+ if_id, bus_cnt, DDR_PHY_DATA,
+ 0x92,
+ freq_config_info.
+ bw_per_freq << 8
+ /*freq_mask[dev_num][frequency] << 8 */
+ , 0x700));
+ CHECK_STATUS(ddr3_tip_bus_read_modify_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ bus_cnt, DDR_PHY_DATA, 0x94,
+ freq_config_info.rate_per_freq, 0x7));
+ }
+
+ /* DUnit to Phy drive post edge, ADLL reset assert de-assert */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ DRAM_PHY_CONFIGURATION, 0,
+ (0x80000000 | 0x40000000)));
+ mdelay(100 / (freq_val[frequency] / freq_val[DDR_FREQ_LOW_FREQ]));
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ DRAM_PHY_CONFIGURATION, (0x80000000 | 0x40000000),
+ (0x80000000 | 0x40000000)));
+
+ /* polling for ADLL Done */
+ if (ddr3_tip_if_polling
+ (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x3ff03ff,
+ 0x3ff03ff, PHY_LOCK_STATUS_REG,
+ MAX_POLLING_ITERATIONS) != MV_OK) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("Freq_set: DDR3 poll failed(1)\n"));
+ }
+
+ /* pup data_pup reset assert-> deassert */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ SDRAM_CONFIGURATION_REG, 0, 0x60000000));
+ mdelay(10);
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ SDRAM_CONFIGURATION_REG, 0x60000000, 0x60000000));
+
+ /* Set proper timing params before existing Self-Refresh */
+ ddr3_tip_set_timing(dev_num, access_type, if_id, frequency);
+ if (delay_enable != 0) {
+ adll_tap = MEGA / (freq_val[frequency] * 64);
+ ddr3_tip_cmd_addr_init_delay(dev_num, adll_tap);
+ }
+
+ /* Exit SR */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id, DFS_REG, 0,
+ 0x4));
+ if (ddr3_tip_if_polling
+ (dev_num, ACCESS_TYPE_UNICAST, if_id, 0, 0x8, DFS_REG,
+ MAX_POLLING_ITERATIONS) != MV_OK) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("Freq_set: DDR3 poll failed(2)"));
+ }
+
+ /* Refresh Command */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ SDRAM_OPERATION_REG, 0x2, 0xf1f));
+ if (ddr3_tip_if_polling
+ (dev_num, ACCESS_TYPE_UNICAST, if_id, 0, 0x1f,
+ SDRAM_OPERATION_REG, MAX_POLLING_ITERATIONS) != MV_OK) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("Freq_set: DDR3 poll failed(3)"));
+ }
+
+ /* Release DFS Block */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id, DFS_REG, 0,
+ 0x2));
+ /* Controller to MBUS Retry - normal */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id, DUNIT_MMASK_REG,
+ 0x1, 0x1));
+
+ /* MRO: Burst Length 8, CL , Auto_precharge 0x16cc */
+ val =
+ ((cl_mask_table[cl_value] & 0x1) << 2) |
+ ((cl_mask_table[cl_value] & 0xe) << 3);
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id, MR0_REG,
+ val, (0x7 << 4) | (1 << 2)));
+ /* MR2: CWL = 10 , Auto Self-Refresh - disable */
+ val = (cwl_mask_table[cwl_value] << 3);
+ /*
+ * nklein 24.10.13 - should not be here - leave value as set in
+ * the init configuration val |= (1 << 9);
+ * val |= ((tm->interface_params[if_id].
+ * interface_temp == HWS_TEMP_HIGH) ? (1 << 7) : 0);
+ */
+ /* nklein 24.10.13 - see above comment */
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
+ if_id, MR2_REG,
+ val, (0x7 << 3)));
+
+ /* ODT TIMING */
+ val = ((cl_value - cwl_value + 1) << 4) |
+ ((cl_value - cwl_value + 6) << 8) |
+ ((cl_value - 1) << 12) | ((cl_value + 6) << 16);
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
+ if_id, ODT_TIMING_LOW,
+ val, 0xffff0));
+ val = 0x71 | ((cwl_value - 1) << 8) | ((cwl_value + 5) << 12);
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
+ if_id, ODT_TIMING_HI_REG,
+ val, 0xffff));
+
+ /* ODT Active */
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
+ if_id,
+ DUNIT_ODT_CONTROL_REG,
+ 0xf, 0xf));
+
+ /* re-write CL */
+ val = ((cl_mask_table[cl_value] & 0x1) << 2) |
+ ((cl_mask_table[cl_value] & 0xe) << 3);
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
+ 0, MR0_REG, val,
+ (0x7 << 4) | (1 << 2)));
+
+ /* re-write CWL */
+ val = (cwl_mask_table[cwl_value] << 3);
+ CHECK_STATUS(ddr3_tip_write_mrs_cmd(dev_num, cs_mask, MRS2_CMD,
+ val, (0x7 << 3)));
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
+ 0, MR2_REG, val, (0x7 << 3)));
+
+ if (mem_mask != 0) {
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
+ if_id,
+ CS_ENABLE_REG,
+ 1 << 3, 0x8));
+ }
+ }
+
+ return MV_OK;
+}
+
+/*
+ * Set ODT values
+ */
+static int ddr3_tip_write_odt(u32 dev_num, enum hws_access_type access_type,
+ u32 if_id, u32 cl_value, u32 cwl_value)
+{
+ /* ODT TIMING */
+ u32 val = (cl_value - cwl_value + 6);
+
+ val = ((cl_value - cwl_value + 1) << 4) | ((val & 0xf) << 8) |
+ (((cl_value - 1) & 0xf) << 12) |
+ (((cl_value + 6) & 0xf) << 16) | (((val & 0x10) >> 4) << 21);
+ val |= (((cl_value - 1) >> 4) << 22) | (((cl_value + 6) >> 4) << 23);
+
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
+ ODT_TIMING_LOW, val, 0xffff0));
+ val = 0x71 | ((cwl_value - 1) << 8) | ((cwl_value + 5) << 12);
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
+ ODT_TIMING_HI_REG, val, 0xffff));
+ if (odt_additional == 1) {
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
+ if_id,
+ SDRAM_ODT_CONTROL_HIGH_REG,
+ 0xf, 0xf));
+ }
+
+ /* ODT Active */
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
+ DUNIT_ODT_CONTROL_REG, 0xf, 0xf));
+
+ return MV_OK;
+}
+
+/*
+ * Set Timing values for training
+ */
+static int ddr3_tip_set_timing(u32 dev_num, enum hws_access_type access_type,
+ u32 if_id, enum hws_ddr_freq frequency)
+{
+ u32 t_ckclk = 0, t_ras = 0;
+ u32 t_rcd = 0, t_rp = 0, t_wr = 0, t_wtr = 0, t_rrd = 0, t_rtp = 0,
+ t_rfc = 0, t_mod = 0;
+ u32 val = 0, page_size = 0;
+ enum hws_speed_bin speed_bin_index;
+ enum hws_mem_size memory_size = MEM_2G;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ speed_bin_index = tm->interface_params[if_id].speed_bin_index;
+ memory_size = tm->interface_params[if_id].memory_size;
+ page_size =
+ (tm->interface_params[if_id].bus_width ==
+ BUS_WIDTH_8) ? page_param[memory_size].
+ page_size_8bit : page_param[memory_size].page_size_16bit;
+ t_ckclk = (MEGA / freq_val[frequency]);
+ t_rrd = (page_size == 1) ? speed_bin_table(speed_bin_index,
+ SPEED_BIN_TRRD1K) :
+ speed_bin_table(speed_bin_index, SPEED_BIN_TRRD2K);
+ t_rrd = GET_MAX_VALUE(t_ckclk * 4, t_rrd);
+ t_rtp = GET_MAX_VALUE(t_ckclk * 4, speed_bin_table(speed_bin_index,
+ SPEED_BIN_TRTP));
+ t_wtr = GET_MAX_VALUE(t_ckclk * 4, speed_bin_table(speed_bin_index,
+ SPEED_BIN_TWTR));
+ t_ras = TIME_2_CLOCK_CYCLES(speed_bin_table(speed_bin_index,
+ SPEED_BIN_TRAS),
+ t_ckclk);
+ t_rcd = TIME_2_CLOCK_CYCLES(speed_bin_table(speed_bin_index,
+ SPEED_BIN_TRCD),
+ t_ckclk);
+ t_rp = TIME_2_CLOCK_CYCLES(speed_bin_table(speed_bin_index,
+ SPEED_BIN_TRP),
+ t_ckclk);
+ t_wr = TIME_2_CLOCK_CYCLES(speed_bin_table(speed_bin_index,
+ SPEED_BIN_TWR),
+ t_ckclk);
+ t_wtr = TIME_2_CLOCK_CYCLES(t_wtr, t_ckclk);
+ t_rrd = TIME_2_CLOCK_CYCLES(t_rrd, t_ckclk);
+ t_rtp = TIME_2_CLOCK_CYCLES(t_rtp, t_ckclk);
+ t_rfc = TIME_2_CLOCK_CYCLES(rfc_table[memory_size] * 1000, t_ckclk);
+ t_mod = GET_MAX_VALUE(t_ckclk * 24, 15000);
+ t_mod = TIME_2_CLOCK_CYCLES(t_mod, t_ckclk);
+
+ /* SDRAM Timing Low */
+ val = (t_ras & 0xf) | (t_rcd << 4) | (t_rp << 8) | (t_wr << 12) |
+ (t_wtr << 16) | (((t_ras & 0x30) >> 4) << 20) | (t_rrd << 24) |
+ (t_rtp << 28);
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
+ SDRAM_TIMING_LOW_REG, val, 0xff3fffff));
+
+ /* SDRAM Timing High */
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
+ SDRAM_TIMING_HIGH_REG,
+ t_rfc & 0x7f, 0x7f));
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
+ SDRAM_TIMING_HIGH_REG,
+ 0x180, 0x180));
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
+ SDRAM_TIMING_HIGH_REG,
+ 0x600, 0x600));
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
+ SDRAM_TIMING_HIGH_REG,
+ 0x1800, 0xf800));
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
+ SDRAM_TIMING_HIGH_REG,
+ ((t_rfc & 0x380) >> 7) << 16, 0x70000));
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
+ SDRAM_TIMING_HIGH_REG, 0,
+ 0x380000));
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
+ SDRAM_TIMING_HIGH_REG,
+ (t_mod & 0xf) << 25, 0x1e00000));
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
+ SDRAM_TIMING_HIGH_REG,
+ (t_mod >> 4) << 30, 0xc0000000));
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
+ SDRAM_TIMING_HIGH_REG,
+ 0x16000000, 0x1e000000));
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
+ SDRAM_TIMING_HIGH_REG,
+ 0x40000000, 0xc0000000));
+
+ return MV_OK;
+}
+
+/*
+ * Mode Read
+ */
+int hws_ddr3_tip_mode_read(u32 dev_num, struct mode_info *mode_info)
+{
+ u32 ret;
+
+ ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ MR0_REG, mode_info->reg_mr0, MASK_ALL_BITS);
+ if (ret != MV_OK)
+ return ret;
+
+ ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ MR1_REG, mode_info->reg_mr1, MASK_ALL_BITS);
+ if (ret != MV_OK)
+ return ret;
+
+ ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ MR2_REG, mode_info->reg_mr2, MASK_ALL_BITS);
+ if (ret != MV_OK)
+ return ret;
+
+ ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ MR3_REG, mode_info->reg_mr2, MASK_ALL_BITS);
+ if (ret != MV_OK)
+ return ret;
+
+ ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ READ_DATA_SAMPLE_DELAY, mode_info->read_data_sample,
+ MASK_ALL_BITS);
+ if (ret != MV_OK)
+ return ret;
+
+ ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ READ_DATA_READY_DELAY, mode_info->read_data_ready,
+ MASK_ALL_BITS);
+ if (ret != MV_OK)
+ return ret;
+
+ return MV_OK;
+}
+
+/*
+ * Get first active IF
+ */
+int ddr3_tip_get_first_active_if(u8 dev_num, u32 interface_mask,
+ u32 *interface_id)
+{
+ u32 if_id;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ if (interface_mask & (1 << if_id)) {
+ *interface_id = if_id;
+ break;
+ }
+ }
+
+ return MV_OK;
+}
+
+/*
+ * Write CS Result
+ */
+int ddr3_tip_write_cs_result(u32 dev_num, u32 offset)
+{
+ u32 if_id, bus_num, cs_bitmask, data_val, cs_num;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ for (bus_num = 0; bus_num < tm->num_of_bus_per_interface;
+ bus_num++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, bus_num);
+ cs_bitmask =
+ tm->interface_params[if_id].
+ as_bus_params[bus_num].cs_bitmask;
+ if (cs_bitmask != effective_cs) {
+ cs_num = GET_CS_FROM_MASK(cs_bitmask);
+ ddr3_tip_bus_read(dev_num, if_id,
+ ACCESS_TYPE_UNICAST, bus_num,
+ DDR_PHY_DATA,
+ offset +
+ CS_REG_VALUE(effective_cs),
+ &data_val);
+ ddr3_tip_bus_write(dev_num,
+ ACCESS_TYPE_UNICAST,
+ if_id,
+ ACCESS_TYPE_UNICAST,
+ bus_num, DDR_PHY_DATA,
+ offset +
+ CS_REG_VALUE(cs_num),
+ data_val);
+ }
+ }
+ }
+
+ return MV_OK;
+}
+
+/*
+ * Write MRS
+ */
+int ddr3_tip_write_mrs_cmd(u32 dev_num, u32 *cs_mask_arr, u32 cmd,
+ u32 data, u32 mask)
+{
+ u32 if_id, reg;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ reg = (cmd == MRS1_CMD) ? MR1_REG : MR2_REG;
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
+ PARAM_NOT_CARE, reg, data, mask));
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ SDRAM_OPERATION_REG,
+ (cs_mask_arr[if_id] << 8) | cmd, 0xf1f));
+ }
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ if (ddr3_tip_if_polling(dev_num, ACCESS_TYPE_UNICAST, if_id, 0,
+ 0x1f, SDRAM_OPERATION_REG,
+ MAX_POLLING_ITERATIONS) != MV_OK) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("write_mrs_cmd: Poll cmd fail"));
+ }
+ }
+
+ return MV_OK;
+}
+
+/*
+ * Reset XSB Read FIFO
+ */
+int ddr3_tip_reset_fifo_ptr(u32 dev_num)
+{
+ u32 if_id = 0;
+
+ /* Configure PHY reset value to 0 in order to "clean" the FIFO */
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
+ if_id, 0x15c8, 0, 0xff000000));
+ /*
+ * Move PHY to RL mode (only in RL mode the PHY overrides FIFO values
+ * during FIFO reset)
+ */
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
+ if_id, TRAINING_SW_2_REG,
+ 0x1, 0x9));
+ /* In order that above configuration will influence the PHY */
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
+ if_id, 0x15b0,
+ 0x80000000, 0x80000000));
+ /* Reset read fifo assertion */
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
+ if_id, 0x1400, 0, 0x40000000));
+ /* Reset read fifo deassertion */
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
+ if_id, 0x1400,
+ 0x40000000, 0x40000000));
+ /* Move PHY back to functional mode */
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
+ if_id, TRAINING_SW_2_REG,
+ 0x8, 0x9));
+ /* Stop training machine */
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
+ if_id, 0x15b4, 0x10000, 0x10000));
+
+ return MV_OK;
+}
+
+/*
+ * Reset Phy registers
+ */
+int ddr3_tip_ddr3_reset_phy_regs(u32 dev_num)
+{
+ u32 if_id, phy_id, cs;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ for (phy_id = 0; phy_id < tm->num_of_bus_per_interface;
+ phy_id++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, phy_id);
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_UNICAST,
+ if_id, ACCESS_TYPE_UNICAST,
+ phy_id, DDR_PHY_DATA,
+ WL_PHY_REG +
+ CS_REG_VALUE(effective_cs),
+ phy_reg0_val));
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ ACCESS_TYPE_UNICAST, phy_id, DDR_PHY_DATA,
+ RL_PHY_REG + CS_REG_VALUE(effective_cs),
+ phy_reg2_val));
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ ACCESS_TYPE_UNICAST, phy_id, DDR_PHY_DATA,
+ READ_CENTRALIZATION_PHY_REG +
+ CS_REG_VALUE(effective_cs), phy_reg3_val));
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ ACCESS_TYPE_UNICAST, phy_id, DDR_PHY_DATA,
+ WRITE_CENTRALIZATION_PHY_REG +
+ CS_REG_VALUE(effective_cs), phy_reg3_val));
+ }
+ }
+
+ /* Set Receiver Calibration value */
+ for (cs = 0; cs < MAX_CS_NUM; cs++) {
+ /* PHY register 0xdb bits[5:0] - configure to 63 */
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ DDR_PHY_DATA, CSN_IOB_VREF_REG(cs), 63));
+ }
+
+ return MV_OK;
+}
+
+/*
+ * Restore Dunit registers
+ */
+int ddr3_tip_restore_dunit_regs(u32 dev_num)
+{
+ u32 index_cnt;
+
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
+ PARAM_NOT_CARE, CALIB_MACHINE_CTRL_REG,
+ 0x1, 0x1));
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
+ PARAM_NOT_CARE, CALIB_MACHINE_CTRL_REG,
+ calibration_update_control << 3,
+ 0x3 << 3));
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
+ PARAM_NOT_CARE,
+ ODPG_WRITE_READ_MODE_ENABLE_REG,
+ 0xffff, MASK_ALL_BITS));
+
+ for (index_cnt = 0; index_cnt < ARRAY_SIZE(odpg_default_value);
+ index_cnt++) {
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ odpg_default_value[index_cnt].reg_addr,
+ odpg_default_value[index_cnt].reg_data,
+ odpg_default_value[index_cnt].reg_mask));
+ }
+
+ return MV_OK;
+}
+
+/*
+ * Auto tune main flow
+ */
+static int ddr3_tip_ddr3_training_main_flow(u32 dev_num)
+{
+ enum hws_ddr_freq freq = init_freq;
+ struct init_cntr_param init_cntr_prm;
+ int ret = MV_OK;
+ u32 if_id;
+ u32 max_cs = hws_ddr3_tip_max_cs_get();
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+#ifndef EXCLUDE_SWITCH_DEBUG
+ if (debug_training == DEBUG_LEVEL_TRACE) {
+ CHECK_STATUS(print_device_info((u8)dev_num));
+ }
+#endif
+
+ for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
+ CHECK_STATUS(ddr3_tip_ddr3_reset_phy_regs(dev_num));
+ }
+ /* Set to 0 after each loop to avoid illegal value may be used */
+ effective_cs = 0;
+
+ freq = init_freq;
+ if (is_pll_before_init != 0) {
+ for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ config_func_info[dev_num].tip_set_freq_divider_func(
+ (u8)dev_num, if_id, freq);
+ }
+ }
+
+ if (is_adll_calib_before_init != 0) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("with adll calib before init\n"));
+ adll_calibration(dev_num, ACCESS_TYPE_MULTICAST, 0, freq);
+ }
+
+ if (is_reg_dump != 0) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("Dump before init controller\n"));
+ ddr3_tip_reg_dump(dev_num);
+ }
+
+ if (mask_tune_func & INIT_CONTROLLER_MASK_BIT) {
+ training_stage = INIT_CONTROLLER;
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("INIT_CONTROLLER_MASK_BIT\n"));
+ init_cntr_prm.do_mrs_phy = 1;
+ init_cntr_prm.is_ctrl64_bit = 0;
+ init_cntr_prm.init_phy = 1;
+ init_cntr_prm.msys_init = 0;
+ ret = hws_ddr3_tip_init_controller(dev_num, &init_cntr_prm);
+ if (is_reg_dump != 0)
+ ddr3_tip_reg_dump(dev_num);
+ if (ret != MV_OK) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("hws_ddr3_tip_init_controller failure\n"));
+ if (debug_mode == 0)
+ return MV_FAIL;
+ }
+ }
+
+#ifdef STATIC_ALGO_SUPPORT
+ if (mask_tune_func & STATIC_LEVELING_MASK_BIT) {
+ training_stage = STATIC_LEVELING;
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("STATIC_LEVELING_MASK_BIT\n"));
+ ret = ddr3_tip_run_static_alg(dev_num, freq);
+ if (is_reg_dump != 0)
+ ddr3_tip_reg_dump(dev_num);
+ if (ret != MV_OK) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("ddr3_tip_run_static_alg failure\n"));
+ if (debug_mode == 0)
+ return MV_FAIL;
+ }
+ }
+#endif
+
+ if (mask_tune_func & SET_LOW_FREQ_MASK_BIT) {
+ training_stage = SET_LOW_FREQ;
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("SET_LOW_FREQ_MASK_BIT %d\n",
+ freq_val[low_freq]));
+ ret = ddr3_tip_freq_set(dev_num, ACCESS_TYPE_MULTICAST,
+ PARAM_NOT_CARE, low_freq);
+ if (is_reg_dump != 0)
+ ddr3_tip_reg_dump(dev_num);
+ if (ret != MV_OK) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("ddr3_tip_freq_set failure\n"));
+ if (debug_mode == 0)
+ return MV_FAIL;
+ }
+ }
+
+ for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
+ if (mask_tune_func & LOAD_PATTERN_MASK_BIT) {
+ training_stage = LOAD_PATTERN;
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("LOAD_PATTERN_MASK_BIT #%d\n",
+ effective_cs));
+ ret = ddr3_tip_load_all_pattern_to_mem(dev_num);
+ if (is_reg_dump != 0)
+ ddr3_tip_reg_dump(dev_num);
+ if (ret != MV_OK) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("ddr3_tip_load_all_pattern_to_mem failure CS #%d\n",
+ effective_cs));
+ if (debug_mode == 0)
+ return MV_FAIL;
+ }
+ }
+ }
+ /* Set to 0 after each loop to avoid illegal value may be used */
+ effective_cs = 0;
+
+ if (mask_tune_func & SET_MEDIUM_FREQ_MASK_BIT) {
+ training_stage = SET_MEDIUM_FREQ;
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("SET_MEDIUM_FREQ_MASK_BIT %d\n",
+ freq_val[medium_freq]));
+ ret =
+ ddr3_tip_freq_set(dev_num, ACCESS_TYPE_MULTICAST,
+ PARAM_NOT_CARE, medium_freq);
+ if (is_reg_dump != 0)
+ ddr3_tip_reg_dump(dev_num);
+ if (ret != MV_OK) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("ddr3_tip_freq_set failure\n"));
+ if (debug_mode == 0)
+ return MV_FAIL;
+ }
+ }
+
+ if (mask_tune_func & WRITE_LEVELING_MASK_BIT) {
+ training_stage = WRITE_LEVELING;
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("WRITE_LEVELING_MASK_BIT\n"));
+ if ((rl_mid_freq_wa == 0) || (freq_val[medium_freq] == 533)) {
+ ret = ddr3_tip_dynamic_write_leveling(dev_num);
+ } else {
+ /* Use old WL */
+ ret = ddr3_tip_legacy_dynamic_write_leveling(dev_num);
+ }
+
+ if (is_reg_dump != 0)
+ ddr3_tip_reg_dump(dev_num);
+ if (ret != MV_OK) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("ddr3_tip_dynamic_write_leveling failure\n"));
+ if (debug_mode == 0)
+ return MV_FAIL;
+ }
+ }
+
+ for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
+ if (mask_tune_func & LOAD_PATTERN_2_MASK_BIT) {
+ training_stage = LOAD_PATTERN_2;
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("LOAD_PATTERN_2_MASK_BIT CS #%d\n",
+ effective_cs));
+ ret = ddr3_tip_load_all_pattern_to_mem(dev_num);
+ if (is_reg_dump != 0)
+ ddr3_tip_reg_dump(dev_num);
+ if (ret != MV_OK) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("ddr3_tip_load_all_pattern_to_mem failure CS #%d\n",
+ effective_cs));
+ if (debug_mode == 0)
+ return MV_FAIL;
+ }
+ }
+ }
+ /* Set to 0 after each loop to avoid illegal value may be used */
+ effective_cs = 0;
+
+ if (mask_tune_func & READ_LEVELING_MASK_BIT) {
+ training_stage = READ_LEVELING;
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("READ_LEVELING_MASK_BIT\n"));
+ if ((rl_mid_freq_wa == 0) || (freq_val[medium_freq] == 533)) {
+ ret = ddr3_tip_dynamic_read_leveling(dev_num, medium_freq);
+ } else {
+ /* Use old RL */
+ ret = ddr3_tip_legacy_dynamic_read_leveling(dev_num);
+ }
+
+ if (is_reg_dump != 0)
+ ddr3_tip_reg_dump(dev_num);
+ if (ret != MV_OK) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("ddr3_tip_dynamic_read_leveling failure\n"));
+ if (debug_mode == 0)
+ return MV_FAIL;
+ }
+ }
+
+ if (mask_tune_func & WRITE_LEVELING_SUPP_MASK_BIT) {
+ training_stage = WRITE_LEVELING_SUPP;
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("WRITE_LEVELING_SUPP_MASK_BIT\n"));
+ ret = ddr3_tip_dynamic_write_leveling_supp(dev_num);
+ if (is_reg_dump != 0)
+ ddr3_tip_reg_dump(dev_num);
+ if (ret != MV_OK) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("ddr3_tip_dynamic_write_leveling_supp failure\n"));
+ if (debug_mode == 0)
+ return MV_FAIL;
+ }
+ }
+
+ for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
+ if (mask_tune_func & PBS_RX_MASK_BIT) {
+ training_stage = PBS_RX;
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("PBS_RX_MASK_BIT CS #%d\n",
+ effective_cs));
+ ret = ddr3_tip_pbs_rx(dev_num);
+ if (is_reg_dump != 0)
+ ddr3_tip_reg_dump(dev_num);
+ if (ret != MV_OK) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("ddr3_tip_pbs_rx failure CS #%d\n",
+ effective_cs));
+ if (debug_mode == 0)
+ return MV_FAIL;
+ }
+ }
+ }
+
+ for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
+ if (mask_tune_func & PBS_TX_MASK_BIT) {
+ training_stage = PBS_TX;
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("PBS_TX_MASK_BIT CS #%d\n",
+ effective_cs));
+ ret = ddr3_tip_pbs_tx(dev_num);
+ if (is_reg_dump != 0)
+ ddr3_tip_reg_dump(dev_num);
+ if (ret != MV_OK) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("ddr3_tip_pbs_tx failure CS #%d\n",
+ effective_cs));
+ if (debug_mode == 0)
+ return MV_FAIL;
+ }
+ }
+ }
+ /* Set to 0 after each loop to avoid illegal value may be used */
+ effective_cs = 0;
+
+ if (mask_tune_func & SET_TARGET_FREQ_MASK_BIT) {
+ training_stage = SET_TARGET_FREQ;
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("SET_TARGET_FREQ_MASK_BIT %d\n",
+ freq_val[tm->
+ interface_params[first_active_if].
+ memory_freq]));
+ ret = ddr3_tip_freq_set(dev_num, ACCESS_TYPE_MULTICAST,
+ PARAM_NOT_CARE,
+ tm->interface_params[first_active_if].
+ memory_freq);
+ if (is_reg_dump != 0)
+ ddr3_tip_reg_dump(dev_num);
+ if (ret != MV_OK) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("ddr3_tip_freq_set failure\n"));
+ if (debug_mode == 0)
+ return MV_FAIL;
+ }
+ }
+
+ if (mask_tune_func & WRITE_LEVELING_TF_MASK_BIT) {
+ training_stage = WRITE_LEVELING_TF;
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("WRITE_LEVELING_TF_MASK_BIT\n"));
+ ret = ddr3_tip_dynamic_write_leveling(dev_num);
+ if (is_reg_dump != 0)
+ ddr3_tip_reg_dump(dev_num);
+ if (ret != MV_OK) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("ddr3_tip_dynamic_write_leveling TF failure\n"));
+ if (debug_mode == 0)
+ return MV_FAIL;
+ }
+ }
+
+ if (mask_tune_func & LOAD_PATTERN_HIGH_MASK_BIT) {
+ training_stage = LOAD_PATTERN_HIGH;
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("LOAD_PATTERN_HIGH\n"));
+ ret = ddr3_tip_load_all_pattern_to_mem(dev_num);
+ if (is_reg_dump != 0)
+ ddr3_tip_reg_dump(dev_num);
+ if (ret != MV_OK) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("ddr3_tip_load_all_pattern_to_mem failure\n"));
+ if (debug_mode == 0)
+ return MV_FAIL;
+ }
+ }
+
+ if (mask_tune_func & READ_LEVELING_TF_MASK_BIT) {
+ training_stage = READ_LEVELING_TF;
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("READ_LEVELING_TF_MASK_BIT\n"));
+ ret = ddr3_tip_dynamic_read_leveling(dev_num, tm->
+ interface_params[first_active_if].
+ memory_freq);
+ if (is_reg_dump != 0)
+ ddr3_tip_reg_dump(dev_num);
+ if (ret != MV_OK) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("ddr3_tip_dynamic_read_leveling TF failure\n"));
+ if (debug_mode == 0)
+ return MV_FAIL;
+ }
+ }
+
+ if (mask_tune_func & DM_PBS_TX_MASK_BIT) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("DM_PBS_TX_MASK_BIT\n"));
+ }
+
+ for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
+ if (mask_tune_func & VREF_CALIBRATION_MASK_BIT) {
+ training_stage = VREF_CALIBRATION;
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("VREF\n"));
+ ret = ddr3_tip_vref(dev_num);
+ if (is_reg_dump != 0) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("VREF Dump\n"));
+ ddr3_tip_reg_dump(dev_num);
+ }
+ if (ret != MV_OK) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("ddr3_tip_vref failure\n"));
+ if (debug_mode == 0)
+ return MV_FAIL;
+ }
+ }
+ }
+ /* Set to 0 after each loop to avoid illegal value may be used */
+ effective_cs = 0;
+
+ for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
+ if (mask_tune_func & CENTRALIZATION_RX_MASK_BIT) {
+ training_stage = CENTRALIZATION_RX;
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("CENTRALIZATION_RX_MASK_BIT CS #%d\n",
+ effective_cs));
+ ret = ddr3_tip_centralization_rx(dev_num);
+ if (is_reg_dump != 0)
+ ddr3_tip_reg_dump(dev_num);
+ if (ret != MV_OK) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("ddr3_tip_centralization_rx failure CS #%d\n",
+ effective_cs));
+ if (debug_mode == 0)
+ return MV_FAIL;
+ }
+ }
+ }
+ /* Set to 0 after each loop to avoid illegal value may be used */
+ effective_cs = 0;
+
+ for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
+ if (mask_tune_func & WRITE_LEVELING_SUPP_TF_MASK_BIT) {
+ training_stage = WRITE_LEVELING_SUPP_TF;
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("WRITE_LEVELING_SUPP_TF_MASK_BIT CS #%d\n",
+ effective_cs));
+ ret = ddr3_tip_dynamic_write_leveling_supp(dev_num);
+ if (is_reg_dump != 0)
+ ddr3_tip_reg_dump(dev_num);
+ if (ret != MV_OK) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("ddr3_tip_dynamic_write_leveling_supp TF failure CS #%d\n",
+ effective_cs));
+ if (debug_mode == 0)
+ return MV_FAIL;
+ }
+ }
+ }
+ /* Set to 0 after each loop to avoid illegal value may be used */
+ effective_cs = 0;
+
+ for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
+ if (mask_tune_func & CENTRALIZATION_TX_MASK_BIT) {
+ training_stage = CENTRALIZATION_TX;
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("CENTRALIZATION_TX_MASK_BIT CS #%d\n",
+ effective_cs));
+ ret = ddr3_tip_centralization_tx(dev_num);
+ if (is_reg_dump != 0)
+ ddr3_tip_reg_dump(dev_num);
+ if (ret != MV_OK) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("ddr3_tip_centralization_tx failure CS #%d\n",
+ effective_cs));
+ if (debug_mode == 0)
+ return MV_FAIL;
+ }
+ }
+ }
+ /* Set to 0 after each loop to avoid illegal value may be used */
+ effective_cs = 0;
+
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("restore registers to default\n"));
+ /* restore register values */
+ CHECK_STATUS(ddr3_tip_restore_dunit_regs(dev_num));
+
+ if (is_reg_dump != 0)
+ ddr3_tip_reg_dump(dev_num);
+
+ return MV_OK;
+}
+
+/*
+ * DDR3 Dynamic training flow
+ */
+static int ddr3_tip_ddr3_auto_tune(u32 dev_num)
+{
+ u32 if_id, stage, ret;
+ int is_if_fail = 0, is_auto_tune_fail = 0;
+
+ training_stage = INIT_CONTROLLER;
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ for (stage = 0; stage < MAX_STAGE_LIMIT; stage++)
+ training_result[stage][if_id] = NO_TEST_DONE;
+ }
+
+ ret = ddr3_tip_ddr3_training_main_flow(dev_num);
+
+ /* activate XSB test */
+ if (xsb_validate_type != 0) {
+ run_xsb_test(dev_num, xsb_validation_base_address, 1, 1,
+ 0x1024);
+ }
+
+ if (is_reg_dump != 0)
+ ddr3_tip_reg_dump(dev_num);
+
+ /* print log */
+ CHECK_STATUS(ddr3_tip_print_log(dev_num, window_mem_addr));
+
+ if (ret != MV_OK) {
+ CHECK_STATUS(ddr3_tip_print_stability_log(dev_num));
+ }
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ is_if_fail = 0;
+ for (stage = 0; stage < MAX_STAGE_LIMIT; stage++) {
+ if (training_result[stage][if_id] == TEST_FAILED)
+ is_if_fail = 1;
+ }
+ if (is_if_fail == 1) {
+ is_auto_tune_fail = 1;
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
+ ("Auto Tune failed for IF %d\n",
+ if_id));
+ }
+ }
+
+ if ((ret == MV_FAIL) || (is_auto_tune_fail == 1))
+ return MV_FAIL;
+ else
+ return MV_OK;
+}
+
+/*
+ * Enable init sequence
+ */
+int ddr3_tip_enable_init_sequence(u32 dev_num)
+{
+ int is_fail = 0;
+ u32 if_id = 0, mem_mask = 0, bus_index = 0;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ /* Enable init sequence */
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST, 0,
+ SDRAM_INIT_CONTROL_REG, 0x1, 0x1));
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+
+ if (ddr3_tip_if_polling
+ (dev_num, ACCESS_TYPE_UNICAST, if_id, 0, 0x1,
+ SDRAM_INIT_CONTROL_REG,
+ MAX_POLLING_ITERATIONS) != MV_OK) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("polling failed IF %d\n",
+ if_id));
+ is_fail = 1;
+ continue;
+ }
+
+ mem_mask = 0;
+ for (bus_index = 0; bus_index < GET_TOPOLOGY_NUM_OF_BUSES();
+ bus_index++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, bus_index);
+ mem_mask |=
+ tm->interface_params[if_id].
+ as_bus_params[bus_index].mirror_enable_bitmask;
+ }
+
+ if (mem_mask != 0) {
+ /* Disable Multi CS */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST,
+ if_id, CS_ENABLE_REG, 1 << 3,
+ 1 << 3));
+ }
+ }
+
+ return (is_fail == 0) ? MV_OK : MV_FAIL;
+}
+
+int ddr3_tip_register_dq_table(u32 dev_num, u32 *table)
+{
+ dq_map_table = table;
+
+ return MV_OK;
+}
+
+/*
+ * Check if pup search is locked
+ */
+int ddr3_tip_is_pup_lock(u32 *pup_buf, enum hws_training_result read_mode)
+{
+ u32 bit_start = 0, bit_end = 0, bit_id;
+
+ if (read_mode == RESULT_PER_BIT) {
+ bit_start = 0;
+ bit_end = BUS_WIDTH_IN_BITS - 1;
+ } else {
+ bit_start = 0;
+ bit_end = 0;
+ }
+
+ for (bit_id = bit_start; bit_id <= bit_end; bit_id++) {
+ if (GET_LOCK_RESULT(pup_buf[bit_id]) == 0)
+ return 0;
+ }
+
+ return 1;
+}
+
+/*
+ * Get minimum buffer value
+ */
+u8 ddr3_tip_get_buf_min(u8 *buf_ptr)
+{
+ u8 min_val = 0xff;
+ u8 cnt = 0;
+
+ for (cnt = 0; cnt < BUS_WIDTH_IN_BITS; cnt++) {
+ if (buf_ptr[cnt] < min_val)
+ min_val = buf_ptr[cnt];
+ }
+
+ return min_val;
+}
+
+/*
+ * Get maximum buffer value
+ */
+u8 ddr3_tip_get_buf_max(u8 *buf_ptr)
+{
+ u8 max_val = 0;
+ u8 cnt = 0;
+
+ for (cnt = 0; cnt < BUS_WIDTH_IN_BITS; cnt++) {
+ if (buf_ptr[cnt] > max_val)
+ max_val = buf_ptr[cnt];
+ }
+
+ return max_val;
+}
+
+/*
+ * The following functions return memory parameters:
+ * bus and device width, device size
+ */
+
+u32 hws_ddr3_get_bus_width(void)
+{
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ return (DDR3_IS_16BIT_DRAM_MODE(tm->bus_act_mask) ==
+ 1) ? 16 : 32;
+}
+
+u32 hws_ddr3_get_device_width(u32 if_id)
+{
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ return (tm->interface_params[if_id].bus_width ==
+ BUS_WIDTH_8) ? 8 : 16;
+}
+
+u32 hws_ddr3_get_device_size(u32 if_id)
+{
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ if (tm->interface_params[if_id].memory_size >=
+ MEM_SIZE_LAST) {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("Error: Wrong device size of Cs: %d",
+ tm->interface_params[if_id].memory_size));
+ return 0;
+ } else {
+ return 1 << tm->interface_params[if_id].memory_size;
+ }
+}
+
+int hws_ddr3_calc_mem_cs_size(u32 if_id, u32 cs, u32 *cs_size)
+{
+ u32 cs_mem_size, dev_size;
+
+ dev_size = hws_ddr3_get_device_size(if_id);
+ if (dev_size != 0) {
+ cs_mem_size = ((hws_ddr3_get_bus_width() /
+ hws_ddr3_get_device_width(if_id)) * dev_size);
+
+ /* the calculated result in Gbytex16 to avoid float using */
+
+ if (cs_mem_size == 2) {
+ *cs_size = _128M;
+ } else if (cs_mem_size == 4) {
+ *cs_size = _256M;
+ } else if (cs_mem_size == 8) {
+ *cs_size = _512M;
+ } else if (cs_mem_size == 16) {
+ *cs_size = _1G;
+ } else if (cs_mem_size == 32) {
+ *cs_size = _2G;
+ } else {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("Error: Wrong Memory size of Cs: %d", cs));
+ return MV_FAIL;
+ }
+ return MV_OK;
+ } else {
+ return MV_FAIL;
+ }
+}
+
+int hws_ddr3_cs_base_adr_calc(u32 if_id, u32 cs, u32 *cs_base_addr)
+{
+ u32 cs_mem_size = 0;
+#ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE
+ u32 physical_mem_size;
+ u32 max_mem_size = DEVICE_MAX_DRAM_ADDRESS_SIZE;
+#endif
+
+ if (hws_ddr3_calc_mem_cs_size(if_id, cs, &cs_mem_size) != MV_OK)
+ return MV_FAIL;
+
+#ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+ /*
+ * if number of address pins doesn't allow to use max mem size that
+ * is defined in topology mem size is defined by
+ * DEVICE_MAX_DRAM_ADDRESS_SIZE
+ */
+ physical_mem_size =
+ mv_hwsmem_size[tm->interface_params[0].memory_size];
+
+ if (hws_ddr3_get_device_width(cs) == 16) {
+ /*
+ * 16bit mem device can be twice more - no need in less
+ * significant pin
+ */
+ max_mem_size = DEVICE_MAX_DRAM_ADDRESS_SIZE * 2;
+ }
+
+ if (physical_mem_size > max_mem_size) {
+ cs_mem_size = max_mem_size *
+ (hws_ddr3_get_bus_width() /
+ hws_ddr3_get_device_width(if_id));
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
+ ("Updated Physical Mem size is from 0x%x to %x\n",
+ physical_mem_size,
+ DEVICE_MAX_DRAM_ADDRESS_SIZE));
+ }
+#endif
+
+ /* calculate CS base addr */
+ *cs_base_addr = ((cs_mem_size) * cs) & 0xffff0000;
+
+ return MV_OK;
+}
diff --git a/drivers/ddr/marvell/a38x/old/ddr3_training_bist.c b/drivers/ddr/marvell/a38x/old/ddr3_training_bist.c
new file mode 100644
index 0000000..fadce2d
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/ddr3_training_bist.c
@@ -0,0 +1,288 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+#include "ddr3_init.h"
+
+static u32 bist_offset = 32;
+enum hws_pattern sweep_pattern = PATTERN_KILLER_DQ0;
+
+static int ddr3_tip_bist_operation(u32 dev_num,
+ enum hws_access_type access_type,
+ u32 if_id,
+ enum hws_bist_operation oper_type);
+
+/*
+ * BIST activate
+ */
+int ddr3_tip_bist_activate(u32 dev_num, enum hws_pattern pattern,
+ enum hws_access_type access_type, u32 if_num,
+ enum hws_dir direction,
+ enum hws_stress_jump addr_stress_jump,
+ enum hws_pattern_duration duration,
+ enum hws_bist_operation oper_type,
+ u32 offset, u32 cs_num, u32 pattern_addr_length)
+{
+ u32 tx_burst_size;
+ u32 delay_between_burst;
+ u32 rd_mode, val;
+ u32 poll_cnt = 0, max_poll = 1000, i, start_if, end_if;
+ struct pattern_info *pattern_table = ddr3_tip_get_pattern_table();
+ u32 read_data[MAX_INTERFACE_NUM];
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ /* ODPG Write enable from BIST */
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_num,
+ ODPG_DATA_CONTROL_REG, 0x1, 0x1));
+ /* ODPG Read enable/disable from BIST */
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_num,
+ ODPG_DATA_CONTROL_REG,
+ (direction == OPER_READ) ?
+ 0x2 : 0, 0x2));
+ CHECK_STATUS(ddr3_tip_load_pattern_to_odpg(dev_num, access_type, if_num,
+ pattern, offset));
+
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_num,
+ ODPG_DATA_BUF_SIZE_REG,
+ pattern_addr_length, MASK_ALL_BITS));
+ tx_burst_size = (direction == OPER_WRITE) ?
+ pattern_table[pattern].tx_burst_size : 0;
+ delay_between_burst = (direction == OPER_WRITE) ? 2 : 0;
+ rd_mode = (direction == OPER_WRITE) ? 1 : 0;
+ CHECK_STATUS(ddr3_tip_configure_odpg
+ (dev_num, access_type, if_num, direction,
+ pattern_table[pattern].num_of_phases_tx, tx_burst_size,
+ pattern_table[pattern].num_of_phases_rx,
+ delay_between_burst,
+ rd_mode, cs_num, addr_stress_jump, duration));
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_num,
+ ODPG_PATTERN_ADDR_OFFSET_REG,
+ offset, MASK_ALL_BITS));
+ if (oper_type == BIST_STOP) {
+ CHECK_STATUS(ddr3_tip_bist_operation(dev_num, access_type,
+ if_num, BIST_STOP));
+ } else {
+ CHECK_STATUS(ddr3_tip_bist_operation(dev_num, access_type,
+ if_num, BIST_START));
+ if (duration != DURATION_CONT) {
+ /*
+ * This pdelay is a WA, becuase polling fives "done"
+ * also the odpg did nmot finish its task
+ */
+ if (access_type == ACCESS_TYPE_MULTICAST) {
+ start_if = 0;
+ end_if = MAX_INTERFACE_NUM - 1;
+ } else {
+ start_if = if_num;
+ end_if = if_num;
+ }
+
+ for (i = start_if; i <= end_if; i++) {
+ VALIDATE_ACTIVE(tm->
+ if_act_mask, i);
+
+ for (poll_cnt = 0; poll_cnt < max_poll;
+ poll_cnt++) {
+ CHECK_STATUS(ddr3_tip_if_read
+ (dev_num,
+ ACCESS_TYPE_UNICAST,
+ if_num, ODPG_BIST_DONE,
+ read_data,
+ MASK_ALL_BITS));
+ val = read_data[i];
+ if ((val & 0x1) == 0x0) {
+ /*
+ * In SOC type devices this bit
+ * is self clear so, if it was
+ * cleared all good
+ */
+ break;
+ }
+ }
+
+ if (poll_cnt >= max_poll) {
+ DEBUG_TRAINING_BIST_ENGINE
+ (DEBUG_LEVEL_ERROR,
+ ("Bist poll failure 2\n"));
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num,
+ ACCESS_TYPE_UNICAST,
+ if_num,
+ ODPG_DATA_CONTROL_REG, 0,
+ MASK_ALL_BITS));
+ return MV_FAIL;
+ }
+ }
+
+ CHECK_STATUS(ddr3_tip_bist_operation
+ (dev_num, access_type, if_num, BIST_STOP));
+ }
+ }
+
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_num,
+ ODPG_DATA_CONTROL_REG, 0,
+ MASK_ALL_BITS));
+
+ return MV_OK;
+}
+
+/*
+ * BIST read result
+ */
+int ddr3_tip_bist_read_result(u32 dev_num, u32 if_id,
+ struct bist_result *pst_bist_result)
+{
+ int ret;
+ u32 read_data[MAX_INTERFACE_NUM];
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ if (IS_ACTIVE(tm->if_act_mask, if_id) == 0)
+ return MV_NOT_SUPPORTED;
+ DEBUG_TRAINING_BIST_ENGINE(DEBUG_LEVEL_TRACE,
+ ("ddr3_tip_bist_read_result if_id %d\n",
+ if_id));
+ ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id,
+ ODPG_BIST_FAILED_DATA_HI_REG, read_data,
+ MASK_ALL_BITS);
+ if (ret != MV_OK)
+ return ret;
+ pst_bist_result->bist_fail_high = read_data[if_id];
+ ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id,
+ ODPG_BIST_FAILED_DATA_LOW_REG, read_data,
+ MASK_ALL_BITS);
+ if (ret != MV_OK)
+ return ret;
+ pst_bist_result->bist_fail_low = read_data[if_id];
+
+ ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id,
+ ODPG_BIST_LAST_FAIL_ADDR_REG, read_data,
+ MASK_ALL_BITS);
+ if (ret != MV_OK)
+ return ret;
+ pst_bist_result->bist_last_fail_addr = read_data[if_id];
+ ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id,
+ ODPG_BIST_DATA_ERROR_COUNTER_REG, read_data,
+ MASK_ALL_BITS);
+ if (ret != MV_OK)
+ return ret;
+ pst_bist_result->bist_error_cnt = read_data[if_id];
+
+ return MV_OK;
+}
+
+/*
+ * BIST flow - Activate & read result
+ */
+int hws_ddr3_run_bist(u32 dev_num, enum hws_pattern pattern, u32 *result,
+ u32 cs_num)
+{
+ int ret;
+ u32 i = 0;
+ u32 win_base;
+ struct bist_result st_bist_result;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ for (i = 0; i < MAX_INTERFACE_NUM; i++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, i);
+ hws_ddr3_cs_base_adr_calc(i, cs_num, &win_base);
+ ret = ddr3_tip_bist_activate(dev_num, pattern,
+ ACCESS_TYPE_UNICAST,
+ i, OPER_WRITE, STRESS_NONE,
+ DURATION_SINGLE, BIST_START,
+ bist_offset + win_base,
+ cs_num, 15);
+ if (ret != MV_OK) {
+ printf("ddr3_tip_bist_activate failed (0x%x)\n", ret);
+ return ret;
+ }
+
+ ret = ddr3_tip_bist_activate(dev_num, pattern,
+ ACCESS_TYPE_UNICAST,
+ i, OPER_READ, STRESS_NONE,
+ DURATION_SINGLE, BIST_START,
+ bist_offset + win_base,
+ cs_num, 15);
+ if (ret != MV_OK) {
+ printf("ddr3_tip_bist_activate failed (0x%x)\n", ret);
+ return ret;
+ }
+
+ ret = ddr3_tip_bist_read_result(dev_num, i, &st_bist_result);
+ if (ret != MV_OK) {
+ printf("ddr3_tip_bist_read_result failed\n");
+ return ret;
+ }
+ result[i] = st_bist_result.bist_error_cnt;
+ }
+
+ return MV_OK;
+}
+
+/*
+ * Set BIST Operation
+ */
+
+static int ddr3_tip_bist_operation(u32 dev_num,
+ enum hws_access_type access_type,
+ u32 if_id, enum hws_bist_operation oper_type)
+{
+ if (oper_type == BIST_STOP) {
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
+ ODPG_BIST_DONE, 1 << 8, 1 << 8));
+ } else {
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
+ ODPG_BIST_DONE, 1, 1));
+ }
+
+ return MV_OK;
+}
+
+/*
+ * Print BIST result
+ */
+void ddr3_tip_print_bist_res(void)
+{
+ u32 dev_num = 0;
+ u32 i;
+ struct bist_result st_bist_result[MAX_INTERFACE_NUM];
+ int res;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ for (i = 0; i < MAX_INTERFACE_NUM; i++) {
+ if (IS_ACTIVE(tm->if_act_mask, i) == 0)
+ continue;
+
+ res = ddr3_tip_bist_read_result(dev_num, i, &st_bist_result[i]);
+ if (res != MV_OK) {
+ DEBUG_TRAINING_BIST_ENGINE(
+ DEBUG_LEVEL_ERROR,
+ ("ddr3_tip_bist_read_result failed\n"));
+ return;
+ }
+ }
+
+ DEBUG_TRAINING_BIST_ENGINE(
+ DEBUG_LEVEL_INFO,
+ ("interface | error_cnt | fail_low | fail_high | fail_addr\n"));
+
+ for (i = 0; i < MAX_INTERFACE_NUM; i++) {
+ if (IS_ACTIVE(tm->if_act_mask, i) ==
+ 0)
+ continue;
+
+ DEBUG_TRAINING_BIST_ENGINE(
+ DEBUG_LEVEL_INFO,
+ ("%d | 0x%08x | 0x%08x | 0x%08x | 0x%08x\n",
+ i, st_bist_result[i].bist_error_cnt,
+ st_bist_result[i].bist_fail_low,
+ st_bist_result[i].bist_fail_high,
+ st_bist_result[i].bist_last_fail_addr));
+ }
+}
diff --git a/drivers/ddr/marvell/a38x/old/ddr3_training_centralization.c b/drivers/ddr/marvell/a38x/old/ddr3_training_centralization.c
new file mode 100644
index 0000000..248db49
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/ddr3_training_centralization.c
@@ -0,0 +1,711 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+#include "ddr3_init.h"
+
+#define VALIDATE_WIN_LENGTH(e1, e2, maxsize) \
+ (((e2) + 1 > (e1) + (u8)MIN_WINDOW_SIZE) && \
+ ((e2) + 1 < (e1) + (u8)maxsize))
+#define IS_WINDOW_OUT_BOUNDARY(e1, e2, maxsize) \
+ (((e1) == 0 && (e2) != 0) || \
+ ((e1) != (maxsize - 1) && (e2) == (maxsize - 1)))
+#define CENTRAL_TX 0
+#define CENTRAL_RX 1
+#define NUM_OF_CENTRAL_TYPES 2
+
+u32 start_pattern = PATTERN_KILLER_DQ0, end_pattern = PATTERN_KILLER_DQ7;
+u32 start_if = 0, end_if = (MAX_INTERFACE_NUM - 1);
+u8 bus_end_window[NUM_OF_CENTRAL_TYPES][MAX_INTERFACE_NUM][MAX_BUS_NUM];
+u8 bus_start_window[NUM_OF_CENTRAL_TYPES][MAX_INTERFACE_NUM][MAX_BUS_NUM];
+u8 centralization_state[MAX_INTERFACE_NUM][MAX_BUS_NUM];
+static u8 ddr3_tip_special_rx_run_once_flag;
+
+static int ddr3_tip_centralization(u32 dev_num, u32 mode);
+
+/*
+ * Centralization RX Flow
+ */
+int ddr3_tip_centralization_rx(u32 dev_num)
+{
+ CHECK_STATUS(ddr3_tip_special_rx(dev_num));
+ CHECK_STATUS(ddr3_tip_centralization(dev_num, CENTRAL_RX));
+
+ return MV_OK;
+}
+
+/*
+ * Centralization TX Flow
+ */
+int ddr3_tip_centralization_tx(u32 dev_num)
+{
+ CHECK_STATUS(ddr3_tip_centralization(dev_num, CENTRAL_TX));
+
+ return MV_OK;
+}
+
+/*
+ * Centralization Flow
+ */
+static int ddr3_tip_centralization(u32 dev_num, u32 mode)
+{
+ enum hws_training_ip_stat training_result[MAX_INTERFACE_NUM];
+ u32 if_id, pattern_id, bit_id;
+ u8 bus_id;
+ u8 cur_start_win[BUS_WIDTH_IN_BITS];
+ u8 centralization_result[MAX_INTERFACE_NUM][BUS_WIDTH_IN_BITS];
+ u8 cur_end_win[BUS_WIDTH_IN_BITS];
+ u8 current_window[BUS_WIDTH_IN_BITS];
+ u8 opt_window, waste_window, start_window_skew, end_window_skew;
+ u8 final_pup_window[MAX_INTERFACE_NUM][BUS_WIDTH_IN_BITS];
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+ enum hws_training_result result_type = RESULT_PER_BIT;
+ enum hws_dir direction;
+ u32 *result[HWS_SEARCH_DIR_LIMIT];
+ u32 reg_phy_off, reg;
+ u8 max_win_size;
+ int lock_success = 1;
+ u8 cur_end_win_min, cur_start_win_max;
+ u32 cs_enable_reg_val[MAX_INTERFACE_NUM];
+ int is_if_fail = 0;
+ enum hws_result *flow_result = ddr3_tip_get_result_ptr(training_stage);
+ u32 pup_win_length = 0;
+ enum hws_search_dir search_dir_id;
+ u8 cons_tap = (mode == CENTRAL_TX) ? (64) : (0);
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ /* save current cs enable reg val */
+ CHECK_STATUS(ddr3_tip_if_read
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ CS_ENABLE_REG, cs_enable_reg_val, MASK_ALL_BITS));
+ /* enable single cs */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ CS_ENABLE_REG, (1 << 3), (1 << 3)));
+ }
+
+ if (mode == CENTRAL_TX) {
+ max_win_size = MAX_WINDOW_SIZE_TX;
+ reg_phy_off = WRITE_CENTRALIZATION_PHY_REG + (effective_cs * 4);
+ direction = OPER_WRITE;
+ } else {
+ max_win_size = MAX_WINDOW_SIZE_RX;
+ reg_phy_off = READ_CENTRALIZATION_PHY_REG + (effective_cs * 4);
+ direction = OPER_READ;
+ }
+
+ /* DB initialization */
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ for (bus_id = 0;
+ bus_id < tm->num_of_bus_per_interface; bus_id++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, bus_id);
+ centralization_state[if_id][bus_id] = 0;
+ bus_end_window[mode][if_id][bus_id] =
+ (max_win_size - 1) + cons_tap;
+ bus_start_window[mode][if_id][bus_id] = 0;
+ centralization_result[if_id][bus_id] = 0;
+ }
+ }
+
+ /* start flow */
+ for (pattern_id = start_pattern; pattern_id <= end_pattern;
+ pattern_id++) {
+ ddr3_tip_ip_training_wrapper(dev_num, ACCESS_TYPE_MULTICAST,
+ PARAM_NOT_CARE,
+ ACCESS_TYPE_MULTICAST,
+ PARAM_NOT_CARE, result_type,
+ HWS_CONTROL_ELEMENT_ADLL,
+ PARAM_NOT_CARE, direction,
+ tm->
+ if_act_mask, 0x0,
+ max_win_size - 1,
+ max_win_size - 1,
+ pattern_id, EDGE_FPF, CS_SINGLE,
+ PARAM_NOT_CARE, training_result);
+
+ for (if_id = start_if; if_id <= end_if; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ for (bus_id = 0;
+ bus_id <= tm->num_of_bus_per_interface - 1;
+ bus_id++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, bus_id);
+
+ for (search_dir_id = HWS_LOW2HIGH;
+ search_dir_id <= HWS_HIGH2LOW;
+ search_dir_id++) {
+ CHECK_STATUS
+ (ddr3_tip_read_training_result
+ (dev_num, if_id,
+ ACCESS_TYPE_UNICAST, bus_id,
+ ALL_BITS_PER_PUP,
+ search_dir_id,
+ direction, result_type,
+ TRAINING_LOAD_OPERATION_UNLOAD,
+ CS_SINGLE,
+ &result[search_dir_id],
+ 1, 0, 0));
+ DEBUG_CENTRALIZATION_ENGINE
+ (DEBUG_LEVEL_INFO,
+ ("%s pat %d IF %d pup %d Regs: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
+ ((mode ==
+ CENTRAL_TX) ? "TX" : "RX"),
+ pattern_id, if_id, bus_id,
+ result[search_dir_id][0],
+ result[search_dir_id][1],
+ result[search_dir_id][2],
+ result[search_dir_id][3],
+ result[search_dir_id][4],
+ result[search_dir_id][5],
+ result[search_dir_id][6],
+ result[search_dir_id][7]));
+ }
+
+ for (bit_id = 0; bit_id < BUS_WIDTH_IN_BITS;
+ bit_id++) {
+ /* check if this code is valid for 2 edge, probably not :( */
+ cur_start_win[bit_id] =
+ GET_TAP_RESULT(result
+ [HWS_LOW2HIGH]
+ [bit_id],
+ EDGE_1);
+ cur_end_win[bit_id] =
+ GET_TAP_RESULT(result
+ [HWS_HIGH2LOW]
+ [bit_id],
+ EDGE_1);
+ /* window length */
+ current_window[bit_id] =
+ cur_end_win[bit_id] -
+ cur_start_win[bit_id] + 1;
+ DEBUG_CENTRALIZATION_ENGINE
+ (DEBUG_LEVEL_TRACE,
+ ("cs %x patern %d IF %d pup %d cur_start_win %d cur_end_win %d current_window %d\n",
+ effective_cs, pattern_id,
+ if_id, bus_id,
+ cur_start_win[bit_id],
+ cur_end_win[bit_id],
+ current_window[bit_id]));
+ }
+
+ if ((ddr3_tip_is_pup_lock
+ (result[HWS_LOW2HIGH], result_type)) &&
+ (ddr3_tip_is_pup_lock
+ (result[HWS_HIGH2LOW], result_type))) {
+ /* read result success */
+ DEBUG_CENTRALIZATION_ENGINE
+ (DEBUG_LEVEL_INFO,
+ ("Pup locked, pat %d IF %d pup %d\n",
+ pattern_id, if_id, bus_id));
+ } else {
+ /* read result failure */
+ DEBUG_CENTRALIZATION_ENGINE
+ (DEBUG_LEVEL_INFO,
+ ("fail Lock, pat %d IF %d pup %d\n",
+ pattern_id, if_id, bus_id));
+ if (centralization_state[if_id][bus_id]
+ == 1) {
+ /* continue with next pup */
+ DEBUG_CENTRALIZATION_ENGINE
+ (DEBUG_LEVEL_TRACE,
+ ("continue to next pup %d %d\n",
+ if_id, bus_id));
+ continue;
+ }
+
+ for (bit_id = 0;
+ bit_id < BUS_WIDTH_IN_BITS;
+ bit_id++) {
+ /*
+ * the next check is relevant
+ * only when using search
+ * machine 2 edges
+ */
+ if (cur_start_win[bit_id] > 0 &&
+ cur_end_win[bit_id] == 0) {
+ cur_end_win
+ [bit_id] =
+ max_win_size - 1;
+ DEBUG_CENTRALIZATION_ENGINE
+ (DEBUG_LEVEL_TRACE,
+ ("fail, IF %d pup %d bit %d fail #1\n",
+ if_id, bus_id,
+ bit_id));
+ /* the next bit */
+ continue;
+ } else {
+ centralization_state
+ [if_id][bus_id] = 1;
+ DEBUG_CENTRALIZATION_ENGINE
+ (DEBUG_LEVEL_TRACE,
+ ("fail, IF %d pup %d bit %d fail #2\n",
+ if_id, bus_id,
+ bit_id));
+ }
+ }
+
+ if (centralization_state[if_id][bus_id]
+ == 1) {
+ /* going to next pup */
+ continue;
+ }
+ } /*bit */
+
+ opt_window =
+ ddr3_tip_get_buf_min(current_window);
+ /* final pup window length */
+ final_pup_window[if_id][bus_id] =
+ ddr3_tip_get_buf_min(cur_end_win) -
+ ddr3_tip_get_buf_max(cur_start_win) +
+ 1;
+ waste_window =
+ opt_window -
+ final_pup_window[if_id][bus_id];
+ start_window_skew =
+ ddr3_tip_get_buf_max(cur_start_win) -
+ ddr3_tip_get_buf_min(
+ cur_start_win);
+ end_window_skew =
+ ddr3_tip_get_buf_max(
+ cur_end_win) -
+ ddr3_tip_get_buf_min(
+ cur_end_win);
+ /* min/max updated with pattern change */
+ cur_end_win_min =
+ ddr3_tip_get_buf_min(
+ cur_end_win);
+ cur_start_win_max =
+ ddr3_tip_get_buf_max(
+ cur_start_win);
+ bus_end_window[mode][if_id][bus_id] =
+ GET_MIN(bus_end_window[mode][if_id]
+ [bus_id],
+ cur_end_win_min);
+ bus_start_window[mode][if_id][bus_id] =
+ GET_MAX(bus_start_window[mode][if_id]
+ [bus_id],
+ cur_start_win_max);
+ DEBUG_CENTRALIZATION_ENGINE(
+ DEBUG_LEVEL_INFO,
+ ("pat %d IF %d pup %d opt_win %d final_win %d waste_win %d st_win_skew %d end_win_skew %d cur_st_win_max %d cur_end_win_min %d bus_st_win %d bus_end_win %d\n",
+ pattern_id, if_id, bus_id, opt_window,
+ final_pup_window[if_id][bus_id],
+ waste_window, start_window_skew,
+ end_window_skew,
+ cur_start_win_max,
+ cur_end_win_min,
+ bus_start_window[mode][if_id][bus_id],
+ bus_end_window[mode][if_id][bus_id]));
+
+ /* check if window is valid */
+ if (ddr3_tip_centr_skip_min_win_check == 0) {
+ if ((VALIDATE_WIN_LENGTH
+ (bus_start_window[mode][if_id]
+ [bus_id],
+ bus_end_window[mode][if_id]
+ [bus_id],
+ max_win_size) == 1) ||
+ (IS_WINDOW_OUT_BOUNDARY
+ (bus_start_window[mode][if_id]
+ [bus_id],
+ bus_end_window[mode][if_id]
+ [bus_id],
+ max_win_size) == 1)) {
+ DEBUG_CENTRALIZATION_ENGINE
+ (DEBUG_LEVEL_INFO,
+ ("win valid, pat %d IF %d pup %d\n",
+ pattern_id, if_id,
+ bus_id));
+ /* window is valid */
+ } else {
+ DEBUG_CENTRALIZATION_ENGINE
+ (DEBUG_LEVEL_INFO,
+ ("fail win, pat %d IF %d pup %d bus_st_win %d bus_end_win %d\n",
+ pattern_id, if_id, bus_id,
+ bus_start_window[mode]
+ [if_id][bus_id],
+ bus_end_window[mode]
+ [if_id][bus_id]));
+ centralization_state[if_id]
+ [bus_id] = 1;
+ if (debug_mode == 0)
+ return MV_FAIL;
+ }
+ } /* ddr3_tip_centr_skip_min_win_check */
+ } /* pup */
+ } /* interface */
+ } /* pattern */
+
+ for (if_id = start_if; if_id <= end_if; if_id++) {
+ if (IS_ACTIVE(tm->if_act_mask, if_id) == 0)
+ continue;
+
+ is_if_fail = 0;
+ flow_result[if_id] = TEST_SUCCESS;
+
+ for (bus_id = 0;
+ bus_id <= (tm->num_of_bus_per_interface - 1); bus_id++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, bus_id);
+
+ /* continue only if lock */
+ if (centralization_state[if_id][bus_id] != 1) {
+ if (ddr3_tip_centr_skip_min_win_check == 0) {
+ if ((bus_end_window
+ [mode][if_id][bus_id] ==
+ (max_win_size - 1)) &&
+ ((bus_end_window
+ [mode][if_id][bus_id] -
+ bus_start_window[mode][if_id]
+ [bus_id]) < MIN_WINDOW_SIZE) &&
+ ((bus_end_window[mode][if_id]
+ [bus_id] - bus_start_window
+ [mode][if_id][bus_id]) > 2)) {
+ /* prevent false lock */
+ /* TBD change to enum */
+ centralization_state
+ [if_id][bus_id] = 2;
+ }
+
+ if ((bus_end_window[mode][if_id][bus_id]
+ == 0) &&
+ ((bus_end_window[mode][if_id]
+ [bus_id] -
+ bus_start_window[mode][if_id]
+ [bus_id]) < MIN_WINDOW_SIZE) &&
+ ((bus_end_window[mode][if_id]
+ [bus_id] -
+ bus_start_window[mode][if_id]
+ [bus_id]) > 2))
+ /*prevent false lock */
+ centralization_state[if_id]
+ [bus_id] = 3;
+ }
+
+ if ((bus_end_window[mode][if_id][bus_id] >
+ (max_win_size - 1)) && direction ==
+ OPER_WRITE) {
+ DEBUG_CENTRALIZATION_ENGINE
+ (DEBUG_LEVEL_INFO,
+ ("Tx special pattern\n"));
+ cons_tap = 64;
+ }
+ }
+
+ /* check states */
+ if (centralization_state[if_id][bus_id] == 3) {
+ DEBUG_CENTRALIZATION_ENGINE(
+ DEBUG_LEVEL_INFO,
+ ("SSW - TBD IF %d pup %d\n",
+ if_id, bus_id));
+ lock_success = 1;
+ } else if (centralization_state[if_id][bus_id] == 2) {
+ DEBUG_CENTRALIZATION_ENGINE(
+ DEBUG_LEVEL_INFO,
+ ("SEW - TBD IF %d pup %d\n",
+ if_id, bus_id));
+ lock_success = 1;
+ } else if (centralization_state[if_id][bus_id] == 0) {
+ lock_success = 1;
+ } else {
+ DEBUG_CENTRALIZATION_ENGINE(
+ DEBUG_LEVEL_ERROR,
+ ("fail, IF %d pup %d\n",
+ if_id, bus_id));
+ lock_success = 0;
+ }
+
+ if (lock_success == 1) {
+ centralization_result[if_id][bus_id] =
+ (bus_end_window[mode][if_id][bus_id] +
+ bus_start_window[mode][if_id][bus_id])
+ / 2 - cons_tap;
+ DEBUG_CENTRALIZATION_ENGINE(
+ DEBUG_LEVEL_TRACE,
+ (" bus_id %d Res= %d\n", bus_id,
+ centralization_result[if_id][bus_id]));
+ /* copy results to registers */
+ pup_win_length =
+ bus_end_window[mode][if_id][bus_id] -
+ bus_start_window[mode][if_id][bus_id] +
+ 1;
+
+ ddr3_tip_bus_read(dev_num, if_id,
+ ACCESS_TYPE_UNICAST, bus_id,
+ DDR_PHY_DATA,
+ RESULT_DB_PHY_REG_ADDR +
+ effective_cs, ®);
+ reg = (reg & (~0x1f <<
+ ((mode == CENTRAL_TX) ?
+ (RESULT_DB_PHY_REG_TX_OFFSET) :
+ (RESULT_DB_PHY_REG_RX_OFFSET))))
+ | pup_win_length <<
+ ((mode == CENTRAL_TX) ?
+ (RESULT_DB_PHY_REG_TX_OFFSET) :
+ (RESULT_DB_PHY_REG_RX_OFFSET));
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_UNICAST,
+ if_id, ACCESS_TYPE_UNICAST,
+ bus_id, DDR_PHY_DATA,
+ RESULT_DB_PHY_REG_ADDR +
+ effective_cs, reg));
+
+ /* offset per CS is calculated earlier */
+ CHECK_STATUS(
+ ddr3_tip_bus_write(dev_num,
+ ACCESS_TYPE_UNICAST,
+ if_id,
+ ACCESS_TYPE_UNICAST,
+ bus_id,
+ DDR_PHY_DATA,
+ reg_phy_off,
+ centralization_result
+ [if_id]
+ [bus_id]));
+ } else {
+ is_if_fail = 1;
+ }
+ }
+
+ if (is_if_fail == 1)
+ flow_result[if_id] = TEST_FAILED;
+ }
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ /* restore cs enable value */
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST,
+ if_id, CS_ENABLE_REG,
+ cs_enable_reg_val[if_id],
+ MASK_ALL_BITS));
+ }
+
+ return is_if_fail;
+}
+
+/*
+ * Centralization Flow
+ */
+int ddr3_tip_special_rx(u32 dev_num)
+{
+ enum hws_training_ip_stat training_result[MAX_INTERFACE_NUM];
+ u32 if_id, pup_id, pattern_id, bit_id;
+ u8 cur_start_win[BUS_WIDTH_IN_BITS];
+ u8 cur_end_win[BUS_WIDTH_IN_BITS];
+ enum hws_training_result result_type = RESULT_PER_BIT;
+ enum hws_dir direction;
+ enum hws_search_dir search_dir_id;
+ u32 *result[HWS_SEARCH_DIR_LIMIT];
+ u32 max_win_size;
+ u8 cur_end_win_min, cur_start_win_max;
+ u32 cs_enable_reg_val[MAX_INTERFACE_NUM];
+ u32 temp = 0;
+ int pad_num = 0;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ if (ddr3_tip_special_rx_run_once_flag != 0)
+ return MV_OK;
+
+ ddr3_tip_special_rx_run_once_flag = 1;
+
+ for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ /* save current cs enable reg val */
+ CHECK_STATUS(ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST,
+ if_id, CS_ENABLE_REG,
+ cs_enable_reg_val,
+ MASK_ALL_BITS));
+ /* enable single cs */
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST,
+ if_id, CS_ENABLE_REG,
+ (1 << 3), (1 << 3)));
+ }
+
+ max_win_size = MAX_WINDOW_SIZE_RX;
+ direction = OPER_READ;
+ pattern_id = PATTERN_VREF;
+
+ /* start flow */
+ ddr3_tip_ip_training_wrapper(dev_num, ACCESS_TYPE_MULTICAST,
+ PARAM_NOT_CARE, ACCESS_TYPE_MULTICAST,
+ PARAM_NOT_CARE, result_type,
+ HWS_CONTROL_ELEMENT_ADLL,
+ PARAM_NOT_CARE, direction,
+ tm->if_act_mask, 0x0,
+ max_win_size - 1, max_win_size - 1,
+ pattern_id, EDGE_FPF, CS_SINGLE,
+ PARAM_NOT_CARE, training_result);
+
+ for (if_id = start_if; if_id <= end_if; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ for (pup_id = 0;
+ pup_id <= tm->num_of_bus_per_interface; pup_id++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, pup_id);
+
+ for (search_dir_id = HWS_LOW2HIGH;
+ search_dir_id <= HWS_HIGH2LOW;
+ search_dir_id++) {
+ CHECK_STATUS(ddr3_tip_read_training_result
+ (dev_num, if_id,
+ ACCESS_TYPE_UNICAST, pup_id,
+ ALL_BITS_PER_PUP, search_dir_id,
+ direction, result_type,
+ TRAINING_LOAD_OPERATION_UNLOAD,
+ CS_SINGLE, &result[search_dir_id],
+ 1, 0, 0));
+ DEBUG_CENTRALIZATION_ENGINE(DEBUG_LEVEL_INFO,
+ ("Special: pat %d IF %d pup %d Regs: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
+ pattern_id, if_id,
+ pup_id,
+ result
+ [search_dir_id][0],
+ result
+ [search_dir_id][1],
+ result
+ [search_dir_id][2],
+ result
+ [search_dir_id][3],
+ result
+ [search_dir_id][4],
+ result
+ [search_dir_id][5],
+ result
+ [search_dir_id][6],
+ result
+ [search_dir_id]
+ [7]));
+ }
+
+ for (bit_id = 0; bit_id < BUS_WIDTH_IN_BITS; bit_id++) {
+ /*
+ * check if this code is valid for 2 edge,
+ * probably not :(
+ */
+ cur_start_win[bit_id] =
+ GET_TAP_RESULT(result[HWS_LOW2HIGH]
+ [bit_id], EDGE_1);
+ cur_end_win[bit_id] =
+ GET_TAP_RESULT(result[HWS_HIGH2LOW]
+ [bit_id], EDGE_1);
+ }
+ if (!((ddr3_tip_is_pup_lock
+ (result[HWS_LOW2HIGH], result_type)) &&
+ (ddr3_tip_is_pup_lock
+ (result[HWS_HIGH2LOW], result_type)))) {
+ DEBUG_CENTRALIZATION_ENGINE(
+ DEBUG_LEVEL_ERROR,
+ ("Special: Pup lock fail, pat %d IF %d pup %d\n",
+ pattern_id, if_id, pup_id));
+ return MV_FAIL;
+ }
+
+ cur_end_win_min =
+ ddr3_tip_get_buf_min(cur_end_win);
+ cur_start_win_max =
+ ddr3_tip_get_buf_max(cur_start_win);
+
+ if (cur_start_win_max <= 1) { /* Align left */
+ for (bit_id = 0; bit_id < BUS_WIDTH_IN_BITS;
+ bit_id++) {
+ pad_num =
+ dq_map_table[bit_id +
+ pup_id *
+ BUS_WIDTH_IN_BITS +
+ if_id *
+ BUS_WIDTH_IN_BITS *
+ tm->
+ num_of_bus_per_interface];
+ CHECK_STATUS(ddr3_tip_bus_read
+ (dev_num, if_id,
+ ACCESS_TYPE_UNICAST,
+ pup_id, DDR_PHY_DATA,
+ PBS_RX_PHY_REG + pad_num,
+ &temp));
+ temp = (temp + 0xa > 31) ?
+ (31) : (temp + 0xa);
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num,
+ ACCESS_TYPE_UNICAST,
+ if_id,
+ ACCESS_TYPE_UNICAST,
+ pup_id, DDR_PHY_DATA,
+ PBS_RX_PHY_REG + pad_num,
+ temp));
+ }
+ DEBUG_CENTRALIZATION_ENGINE(
+ DEBUG_LEVEL_INFO,
+ ("Special: PBS:: I/F# %d , Bus# %d fix align to the Left\n",
+ if_id, pup_id));
+ }
+
+ if (cur_end_win_min > 30) { /* Align right */
+ CHECK_STATUS(ddr3_tip_bus_read
+ (dev_num, if_id,
+ ACCESS_TYPE_UNICAST, pup_id,
+ DDR_PHY_DATA, PBS_RX_PHY_REG + 4,
+ &temp));
+ temp += 0xa;
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_UNICAST,
+ if_id, ACCESS_TYPE_UNICAST,
+ pup_id, DDR_PHY_DATA,
+ PBS_RX_PHY_REG + 4, temp));
+ CHECK_STATUS(ddr3_tip_bus_read
+ (dev_num, if_id,
+ ACCESS_TYPE_UNICAST, pup_id,
+ DDR_PHY_DATA, PBS_RX_PHY_REG + 5,
+ &temp));
+ temp += 0xa;
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_UNICAST,
+ if_id, ACCESS_TYPE_UNICAST,
+ pup_id, DDR_PHY_DATA,
+ PBS_RX_PHY_REG + 5, temp));
+ DEBUG_CENTRALIZATION_ENGINE(
+ DEBUG_LEVEL_INFO,
+ ("Special: PBS:: I/F# %d , Bus# %d fix align to the right\n",
+ if_id, pup_id));
+ }
+
+ vref_window_size[if_id][pup_id] =
+ cur_end_win_min -
+ cur_start_win_max + 1;
+ DEBUG_CENTRALIZATION_ENGINE(
+ DEBUG_LEVEL_INFO,
+ ("Special: Winsize I/F# %d , Bus# %d is %d\n",
+ if_id, pup_id, vref_window_size
+ [if_id][pup_id]));
+ } /* pup */
+ } /* end of interface */
+
+ return MV_OK;
+}
+
+/*
+ * Print Centralization Result
+ */
+int ddr3_tip_print_centralization_result(u32 dev_num)
+{
+ u32 if_id = 0, bus_id = 0;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ printf("Centralization Results\n");
+ printf("I/F0 Result[0 - success 1-fail 2 - state_2 3 - state_3] ...\n");
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ for (bus_id = 0; bus_id < tm->num_of_bus_per_interface;
+ bus_id++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, bus_id);
+ printf("%d ,\n", centralization_state[if_id][bus_id]);
+ }
+ }
+
+ return MV_OK;
+}
diff --git a/drivers/ddr/marvell/a38x/old/ddr3_training_db.c b/drivers/ddr/marvell/a38x/old/ddr3_training_db.c
new file mode 100644
index 0000000..bd5413e
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/ddr3_training_db.c
@@ -0,0 +1,651 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+#include "ddr3_init.h"
+
+/* List of allowed frequency listed in order of enum hws_ddr_freq */
+u32 freq_val[DDR_FREQ_LIMIT] = {
+ 0, /*DDR_FREQ_LOW_FREQ */
+ 400, /*DDR_FREQ_400, */
+ 533, /*DDR_FREQ_533, */
+ 666, /*DDR_FREQ_667, */
+ 800, /*DDR_FREQ_800, */
+ 933, /*DDR_FREQ_933, */
+ 1066, /*DDR_FREQ_1066, */
+ 311, /*DDR_FREQ_311, */
+ 333, /*DDR_FREQ_333, */
+ 467, /*DDR_FREQ_467, */
+ 850, /*DDR_FREQ_850, */
+ 600, /*DDR_FREQ_600 */
+ 300, /*DDR_FREQ_300 */
+ 900, /*DDR_FREQ_900 */
+ 360, /*DDR_FREQ_360 */
+ 1000 /*DDR_FREQ_1000 */
+};
+
+/* Table for CL values per frequency for each speed bin index */
+struct cl_val_per_freq cas_latency_table[] = {
+ /*
+ * 400M 667M 933M 311M 467M 600M 360
+ * 100M 533M 800M 1066M 333M 850M 900
+ * 1000 (the order is 100, 400, 533 etc.)
+ */
+ /* DDR3-800D */
+ { {6, 5, 0, 0, 0, 0, 0, 5, 5, 0, 0, 0, 5, 0, 5, 0} },
+ /* DDR3-800E */
+ { {6, 6, 0, 0, 0, 0, 0, 6, 6, 0, 0, 0, 6, 0, 6, 0} },
+ /* DDR3-1066E */
+ { {6, 5, 6, 0, 0, 0, 0, 5, 5, 6, 0, 0, 5, 0, 5, 0} },
+ /* DDR3-1066F */
+ { {6, 6, 7, 0, 0, 0, 0, 6, 6, 7, 0, 0, 6, 0, 6, 0} },
+ /* DDR3-1066G */
+ { {6, 6, 8, 0, 0, 0, 0, 6, 6, 8, 0, 0, 6, 0, 6, 0} },
+ /* DDR3-1333F* */
+ { {6, 5, 6, 7, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
+ /* DDR3-1333G */
+ { {6, 5, 7, 8, 0, 0, 0, 5, 5, 7, 0, 8, 5, 0, 5, 0} },
+ /* DDR3-1333H */
+ { {6, 6, 8, 9, 0, 0, 0, 6, 6, 8, 0, 9, 6, 0, 6, 0} },
+ /* DDR3-1333J* */
+ { {6, 6, 8, 10, 0, 0, 0, 6, 6, 8, 0, 10, 6, 0, 6, 0}
+ /* DDR3-1600G* */},
+ { {6, 5, 6, 7, 8, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
+ /* DDR3-1600H */
+ { {6, 5, 6, 8, 9, 0, 0, 5, 5, 6, 0, 8, 5, 0, 5, 0} },
+ /* DDR3-1600J */
+ { {6, 5, 7, 9, 10, 0, 0, 5, 5, 7, 0, 9, 5, 0, 5, 0} },
+ /* DDR3-1600K */
+ { {6, 6, 8, 10, 11, 0, 0, 6, 6, 8, 0, 10, 6, 0, 6, 0 } },
+ /* DDR3-1866J* */
+ { {6, 5, 6, 8, 9, 11, 0, 5, 5, 6, 11, 8, 5, 0, 5, 0} },
+ /* DDR3-1866K */
+ { {6, 5, 7, 8, 10, 11, 0, 5, 5, 7, 11, 8, 5, 11, 5, 11} },
+ /* DDR3-1866L */
+ { {6, 6, 7, 9, 11, 12, 0, 6, 6, 7, 12, 9, 6, 12, 6, 12} },
+ /* DDR3-1866M* */
+ { {6, 6, 8, 10, 11, 13, 0, 6, 6, 8, 13, 10, 6, 13, 6, 13} },
+ /* DDR3-2133K* */
+ { {6, 5, 6, 7, 9, 10, 11, 5, 5, 6, 10, 7, 5, 11, 5, 11} },
+ /* DDR3-2133L */
+ { {6, 5, 6, 8, 9, 11, 12, 5, 5, 6, 11, 8, 5, 12, 5, 12} },
+ /* DDR3-2133M */
+ { {6, 5, 7, 9, 10, 12, 13, 5, 5, 7, 12, 9, 5, 13, 5, 13} },
+ /* DDR3-2133N* */
+ { {6, 6, 7, 9, 11, 13, 14, 6, 6, 7, 13, 9, 6, 14, 6, 14} },
+ /* DDR3-1333H-ext */
+ { {6, 6, 7, 9, 0, 0, 0, 6, 6, 7, 0, 9, 6, 0, 6, 0} },
+ /* DDR3-1600K-ext */
+ { {6, 6, 7, 9, 11, 0, 0, 6, 6, 7, 0, 9, 6, 0, 6, 0} },
+ /* DDR3-1866M-ext */
+ { {6, 6, 7, 9, 11, 13, 0, 6, 6, 7, 13, 9, 6, 13, 6, 13} },
+};
+
+/* Table for CWL values per speedbin index */
+struct cl_val_per_freq cas_write_latency_table[] = {
+ /*
+ * 400M 667M 933M 311M 467M 600M 360
+ * 100M 533M 800M 1066M 333M 850M 900
+ * (the order is 100, 400, 533 etc.)
+ */
+ /* DDR3-800D */
+ { {5, 5, 0, 0, 0, 0, 0, 5, 5, 0, 0, 0, 5, 0, 5, 0} },
+ /* DDR3-800E */
+ { {5, 5, 0, 0, 0, 0, 0, 5, 5, 0, 0, 0, 5, 0, 5, 0} },
+ /* DDR3-1066E */
+ { {5, 5, 6, 0, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
+ /* DDR3-1066F */
+ { {5, 5, 6, 0, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
+ /* DDR3-1066G */
+ { {5, 5, 6, 0, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
+ /* DDR3-1333F* */
+ { {5, 5, 6, 7, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
+ /* DDR3-1333G */
+ { {5, 5, 6, 7, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
+ /* DDR3-1333H */
+ { {5, 5, 6, 7, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
+ /* DDR3-1333J* */
+ { {5, 5, 6, 7, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
+ /* DDR3-1600G* */
+ { {5, 5, 6, 7, 8, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
+ /* DDR3-1600H */
+ { {5, 5, 6, 7, 8, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
+ /* DDR3-1600J */
+ { {5, 5, 6, 7, 8, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
+ /* DDR3-1600K */
+ { {5, 5, 6, 7, 8, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
+ /* DDR3-1866J* */
+ { {5, 5, 6, 7, 8, 9, 0, 5, 5, 6, 9, 7, 5, 0, 5, 0} },
+ /* DDR3-1866K */
+ { {5, 5, 6, 7, 8, 9, 0, 5, 5, 6, 9, 7, 5, 0, 5, 0} },
+ /* DDR3-1866L */
+ { {5, 5, 6, 7, 8, 9, 0, 5, 5, 6, 9, 7, 5, 9, 5, 9} },
+ /* DDR3-1866M* */
+ { {5, 5, 6, 7, 8, 9, 0, 5, 5, 6, 9, 7, 5, 9, 5, 9} },
+ /* DDR3-2133K* */
+ { {5, 5, 6, 7, 8, 9, 10, 5, 5, 6, 9, 7, 5, 9, 5, 10} },
+ /* DDR3-2133L */
+ { {5, 5, 6, 7, 8, 9, 10, 5, 5, 6, 9, 7, 5, 9, 5, 10} },
+ /* DDR3-2133M */
+ { {5, 5, 6, 7, 8, 9, 10, 5, 5, 6, 9, 7, 5, 9, 5, 10} },
+ /* DDR3-2133N* */
+ { {5, 5, 6, 7, 8, 9, 10, 5, 5, 6, 9, 7, 5, 9, 5, 10} },
+ /* DDR3-1333H-ext */
+ { {5, 5, 6, 7, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
+ /* DDR3-1600K-ext */
+ { {5, 5, 6, 7, 8, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
+ /* DDR3-1866M-ext */
+ { {5, 5, 6, 7, 8, 9, 0, 5, 5, 6, 9, 7, 5, 9, 5, 9} },
+};
+
+u8 twr_mask_table[] = {
+ 10,
+ 10,
+ 10,
+ 10,
+ 10,
+ 1, /*5 */
+ 2, /*6 */
+ 3, /*7 */
+ 10,
+ 10,
+ 5, /*10 */
+ 10,
+ 6, /*12 */
+ 10,
+ 7, /*14 */
+ 10,
+ 0 /*16 */
+};
+
+u8 cl_mask_table[] = {
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0x2,
+ 0x4,
+ 0x6,
+ 0x8,
+ 0xa,
+ 0xc,
+ 0xe,
+ 0x1,
+ 0x3,
+ 0x5,
+ 0x5
+};
+
+u8 cwl_mask_table[] = {
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0x1,
+ 0x2,
+ 0x3,
+ 0x4,
+ 0x5,
+ 0x6,
+ 0x7,
+ 0x8,
+ 0x9,
+ 0x9
+};
+
+/* RFC values (in ns) */
+u16 rfc_table[] = {
+ 90, /* 512M */
+ 110, /* 1G */
+ 160, /* 2G */
+ 260, /* 4G */
+ 350 /* 8G */
+};
+
+u32 speed_bin_table_t_rc[] = {
+ 50000,
+ 52500,
+ 48750,
+ 50625,
+ 52500,
+ 46500,
+ 48000,
+ 49500,
+ 51000,
+ 45000,
+ 46250,
+ 47500,
+ 48750,
+ 44700,
+ 45770,
+ 46840,
+ 47910,
+ 43285,
+ 44220,
+ 45155,
+ 46900
+};
+
+u32 speed_bin_table_t_rcd_t_rp[] = {
+ 12500,
+ 15000,
+ 11250,
+ 13125,
+ 15000,
+ 10500,
+ 12000,
+ 13500,
+ 15000,
+ 10000,
+ 11250,
+ 12500,
+ 13750,
+ 10700,
+ 11770,
+ 12840,
+ 13910,
+ 10285,
+ 11022,
+ 12155,
+ 13090,
+};
+
+enum {
+ PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_AGGRESSOR = 0,
+ PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM
+};
+
+static u8 pattern_killer_pattern_table_map[KILLER_PATTERN_LENGTH * 2][2] = {
+ /*Aggressor / Victim */
+ {1, 0},
+ {0, 0},
+ {1, 0},
+ {1, 1},
+ {0, 1},
+ {0, 1},
+ {1, 0},
+ {0, 1},
+ {1, 0},
+ {0, 1},
+ {1, 0},
+ {1, 0},
+ {0, 1},
+ {1, 0},
+ {0, 1},
+ {0, 0},
+ {1, 1},
+ {0, 0},
+ {1, 1},
+ {0, 0},
+ {1, 1},
+ {0, 0},
+ {1, 1},
+ {1, 0},
+ {0, 0},
+ {1, 1},
+ {0, 0},
+ {1, 1},
+ {0, 0},
+ {0, 0},
+ {0, 0},
+ {0, 1},
+ {0, 1},
+ {1, 1},
+ {0, 0},
+ {0, 0},
+ {1, 1},
+ {1, 1},
+ {0, 0},
+ {1, 1},
+ {0, 0},
+ {1, 1},
+ {1, 1},
+ {0, 0},
+ {0, 0},
+ {1, 1},
+ {0, 0},
+ {1, 1},
+ {0, 1},
+ {0, 0},
+ {0, 1},
+ {0, 1},
+ {0, 0},
+ {1, 1},
+ {1, 1},
+ {1, 0},
+ {1, 0},
+ {1, 1},
+ {1, 1},
+ {1, 1},
+ {1, 1},
+ {1, 1},
+ {1, 1},
+ {1, 1}
+};
+
+static u8 pattern_vref_pattern_table_map[] = {
+ /* 1 means 0xffffffff, 0 is 0x0 */
+ 0xb8,
+ 0x52,
+ 0x55,
+ 0x8a,
+ 0x33,
+ 0xa6,
+ 0x6d,
+ 0xfe
+};
+
+/* Return speed Bin value for selected index and t* element */
+u32 speed_bin_table(u8 index, enum speed_bin_table_elements element)
+{
+ u32 result = 0;
+
+ switch (element) {
+ case SPEED_BIN_TRCD:
+ case SPEED_BIN_TRP:
+ result = speed_bin_table_t_rcd_t_rp[index];
+ break;
+ case SPEED_BIN_TRAS:
+ if (index < 6)
+ result = 37500;
+ else if (index < 10)
+ result = 36000;
+ else if (index < 14)
+ result = 35000;
+ else if (index < 18)
+ result = 34000;
+ else
+ result = 33000;
+ break;
+ case SPEED_BIN_TRC:
+ result = speed_bin_table_t_rc[index];
+ break;
+ case SPEED_BIN_TRRD1K:
+ if (index < 3)
+ result = 10000;
+ else if (index < 6)
+ result = 7005;
+ else if (index < 14)
+ result = 6000;
+ else
+ result = 5000;
+ break;
+ case SPEED_BIN_TRRD2K:
+ if (index < 6)
+ result = 10000;
+ else if (index < 14)
+ result = 7005;
+ else
+ result = 6000;
+ break;
+ case SPEED_BIN_TPD:
+ if (index < 3)
+ result = 7500;
+ else if (index < 10)
+ result = 5625;
+ else
+ result = 5000;
+ break;
+ case SPEED_BIN_TFAW1K:
+ if (index < 3)
+ result = 40000;
+ else if (index < 6)
+ result = 37500;
+ else if (index < 14)
+ result = 30000;
+ else if (index < 18)
+ result = 27000;
+ else
+ result = 25000;
+ break;
+ case SPEED_BIN_TFAW2K:
+ if (index < 6)
+ result = 50000;
+ else if (index < 10)
+ result = 45000;
+ else if (index < 14)
+ result = 40000;
+ else
+ result = 35000;
+ break;
+ case SPEED_BIN_TWTR:
+ result = 7500;
+ break;
+ case SPEED_BIN_TRTP:
+ result = 7500;
+ break;
+ case SPEED_BIN_TWR:
+ result = 15000;
+ break;
+ case SPEED_BIN_TMOD:
+ result = 15000;
+ break;
+ default:
+ break;
+ }
+
+ return result;
+}
+
+static inline u32 pattern_table_get_killer_word(u8 dqs, u8 index)
+{
+ u8 i, byte = 0;
+ u8 role;
+
+ for (i = 0; i < 8; i++) {
+ role = (i == dqs) ?
+ (PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_AGGRESSOR) :
+ (PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM);
+ byte |= pattern_killer_pattern_table_map[index][role] << i;
+ }
+
+ return byte | (byte << 8) | (byte << 16) | (byte << 24);
+}
+
+static inline u32 pattern_table_get_killer_word16(u8 dqs, u8 index)
+{
+ u8 i, byte0 = 0, byte1 = 0;
+ u8 role;
+
+ for (i = 0; i < 8; i++) {
+ role = (i == dqs) ?
+ (PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_AGGRESSOR) :
+ (PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM);
+ byte0 |= pattern_killer_pattern_table_map[index * 2][role] << i;
+ }
+
+ for (i = 0; i < 8; i++) {
+ role = (i == dqs) ?
+ (PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_AGGRESSOR) :
+ (PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM);
+ byte1 |= pattern_killer_pattern_table_map
+ [index * 2 + 1][role] << i;
+ }
+
+ return byte0 | (byte0 << 8) | (byte1 << 16) | (byte1 << 24);
+}
+
+static inline u32 pattern_table_get_sso_word(u8 sso, u8 index)
+{
+ u8 step = sso + 1;
+
+ if (0 == ((index / step) & 1))
+ return 0x0;
+ else
+ return 0xffffffff;
+}
+
+static inline u32 pattern_table_get_vref_word(u8 index)
+{
+ if (0 == ((pattern_vref_pattern_table_map[index / 8] >>
+ (index % 8)) & 1))
+ return 0x0;
+ else
+ return 0xffffffff;
+}
+
+static inline u32 pattern_table_get_vref_word16(u8 index)
+{
+ if (0 == pattern_killer_pattern_table_map
+ [PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM][index * 2] &&
+ 0 == pattern_killer_pattern_table_map
+ [PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM][index * 2 + 1])
+ return 0x00000000;
+ else if (1 == pattern_killer_pattern_table_map
+ [PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM][index * 2] &&
+ 0 == pattern_killer_pattern_table_map
+ [PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM][index * 2 + 1])
+ return 0xffff0000;
+ else if (0 == pattern_killer_pattern_table_map
+ [PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM][index * 2] &&
+ 1 == pattern_killer_pattern_table_map
+ [PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM][index * 2 + 1])
+ return 0x0000ffff;
+ else
+ return 0xffffffff;
+}
+
+static inline u32 pattern_table_get_static_pbs_word(u8 index)
+{
+ u16 temp;
+
+ temp = ((0x00ff << (index / 3)) & 0xff00) >> 8;
+
+ return temp | (temp << 8) | (temp << 16) | (temp << 24);
+}
+
+inline u32 pattern_table_get_word(u32 dev_num, enum hws_pattern type, u8 index)
+{
+ u32 pattern;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ if (DDR3_IS_16BIT_DRAM_MODE(tm->bus_act_mask) == 0) {
+ /* 32bit patterns */
+ switch (type) {
+ case PATTERN_PBS1:
+ case PATTERN_PBS2:
+ if (index == 0 || index == 2 || index == 5 ||
+ index == 7)
+ pattern = PATTERN_55;
+ else
+ pattern = PATTERN_AA;
+ break;
+ case PATTERN_PBS3:
+ if (0 == (index & 1))
+ pattern = PATTERN_55;
+ else
+ pattern = PATTERN_AA;
+ break;
+ case PATTERN_RL:
+ if (index < 6)
+ pattern = PATTERN_00;
+ else
+ pattern = PATTERN_80;
+ break;
+ case PATTERN_STATIC_PBS:
+ pattern = pattern_table_get_static_pbs_word(index);
+ break;
+ case PATTERN_KILLER_DQ0:
+ case PATTERN_KILLER_DQ1:
+ case PATTERN_KILLER_DQ2:
+ case PATTERN_KILLER_DQ3:
+ case PATTERN_KILLER_DQ4:
+ case PATTERN_KILLER_DQ5:
+ case PATTERN_KILLER_DQ6:
+ case PATTERN_KILLER_DQ7:
+ pattern = pattern_table_get_killer_word(
+ (u8)(type - PATTERN_KILLER_DQ0), index);
+ break;
+ case PATTERN_RL2:
+ if (index < 6)
+ pattern = PATTERN_00;
+ else
+ pattern = PATTERN_01;
+ break;
+ case PATTERN_TEST:
+ if (index > 1 && index < 6)
+ pattern = PATTERN_20;
+ else
+ pattern = PATTERN_00;
+ break;
+ case PATTERN_FULL_SSO0:
+ case PATTERN_FULL_SSO1:
+ case PATTERN_FULL_SSO2:
+ case PATTERN_FULL_SSO3:
+ pattern = pattern_table_get_sso_word(
+ (u8)(type - PATTERN_FULL_SSO0), index);
+ break;
+ case PATTERN_VREF:
+ pattern = pattern_table_get_vref_word(index);
+ break;
+ default:
+ pattern = 0;
+ break;
+ }
+ } else {
+ /* 16bit patterns */
+ switch (type) {
+ case PATTERN_PBS1:
+ case PATTERN_PBS2:
+ case PATTERN_PBS3:
+ pattern = PATTERN_55AA;
+ break;
+ case PATTERN_RL:
+ if (index < 3)
+ pattern = PATTERN_00;
+ else
+ pattern = PATTERN_80;
+ break;
+ case PATTERN_STATIC_PBS:
+ pattern = PATTERN_00FF;
+ break;
+ case PATTERN_KILLER_DQ0:
+ case PATTERN_KILLER_DQ1:
+ case PATTERN_KILLER_DQ2:
+ case PATTERN_KILLER_DQ3:
+ case PATTERN_KILLER_DQ4:
+ case PATTERN_KILLER_DQ5:
+ case PATTERN_KILLER_DQ6:
+ case PATTERN_KILLER_DQ7:
+ pattern = pattern_table_get_killer_word16(
+ (u8)(type - PATTERN_KILLER_DQ0), index);
+ break;
+ case PATTERN_RL2:
+ if (index < 3)
+ pattern = PATTERN_00;
+ else
+ pattern = PATTERN_01;
+ break;
+ case PATTERN_TEST:
+ pattern = PATTERN_0080;
+ break;
+ case PATTERN_FULL_SSO0:
+ pattern = 0x0000ffff;
+ break;
+ case PATTERN_FULL_SSO1:
+ case PATTERN_FULL_SSO2:
+ case PATTERN_FULL_SSO3:
+ pattern = pattern_table_get_sso_word(
+ (u8)(type - PATTERN_FULL_SSO1), index);
+ break;
+ case PATTERN_VREF:
+ pattern = pattern_table_get_vref_word16(index);
+ break;
+ default:
+ pattern = 0;
+ break;
+ }
+ }
+
+ return pattern;
+}
diff --git a/drivers/ddr/marvell/a38x/old/ddr3_training_hw_algo.c b/drivers/ddr/marvell/a38x/old/ddr3_training_hw_algo.c
new file mode 100644
index 0000000..3a88527
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/ddr3_training_hw_algo.c
@@ -0,0 +1,685 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+#include "ddr3_init.h"
+
+#define VREF_INITIAL_STEP 3
+#define VREF_SECOND_STEP 1
+#define VREF_MAX_INDEX 7
+#define MAX_VALUE (1024 - 1)
+#define MIN_VALUE (-MAX_VALUE)
+#define GET_RD_SAMPLE_DELAY(data, cs) ((data >> rd_sample_mask[cs]) & 0xf)
+
+u32 ck_delay = (u32)-1, ck_delay_16 = (u32)-1;
+u32 ca_delay;
+int ddr3_tip_centr_skip_min_win_check = 0;
+u8 current_vref[MAX_BUS_NUM][MAX_INTERFACE_NUM];
+u8 last_vref[MAX_BUS_NUM][MAX_INTERFACE_NUM];
+u16 current_valid_window[MAX_BUS_NUM][MAX_INTERFACE_NUM];
+u16 last_valid_window[MAX_BUS_NUM][MAX_INTERFACE_NUM];
+u8 lim_vref[MAX_BUS_NUM][MAX_INTERFACE_NUM];
+u8 interface_state[MAX_INTERFACE_NUM];
+u8 vref_window_size[MAX_INTERFACE_NUM][MAX_BUS_NUM];
+u8 vref_window_size_th = 12;
+
+static u8 pup_st[MAX_BUS_NUM][MAX_INTERFACE_NUM];
+
+static u32 rd_sample_mask[] = {
+ 0,
+ 8,
+ 16,
+ 24
+};
+
+#define VREF_STEP_1 0
+#define VREF_STEP_2 1
+#define VREF_CONVERGE 2
+
+/*
+ * ODT additional timing
+ */
+int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id)
+{
+ u32 cs_num = 0, max_read_sample = 0, min_read_sample = 0;
+ u32 data_read[MAX_INTERFACE_NUM] = { 0 };
+ u32 read_sample[MAX_CS_NUM];
+ u32 val;
+ u32 pup_index;
+ int max_phase = MIN_VALUE, current_phase;
+ enum hws_access_type access_type = ACCESS_TYPE_UNICAST;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
+ DUNIT_ODT_CONTROL_REG,
+ 0 << 8, 0x3 << 8));
+ CHECK_STATUS(ddr3_tip_if_read(dev_num, access_type, if_id,
+ READ_DATA_SAMPLE_DELAY,
+ data_read, MASK_ALL_BITS));
+ val = data_read[if_id];
+
+ for (cs_num = 0; cs_num < MAX_CS_NUM; cs_num++) {
+ read_sample[cs_num] = GET_RD_SAMPLE_DELAY(val, cs_num);
+
+ /* find maximum of read_samples */
+ if (read_sample[cs_num] >= max_read_sample) {
+ if (read_sample[cs_num] == max_read_sample)
+ max_phase = MIN_VALUE;
+ else
+ max_read_sample = read_sample[cs_num];
+
+ for (pup_index = 0;
+ pup_index < tm->num_of_bus_per_interface;
+ pup_index++) {
+ CHECK_STATUS(ddr3_tip_bus_read
+ (dev_num, if_id,
+ ACCESS_TYPE_UNICAST, pup_index,
+ DDR_PHY_DATA,
+ RL_PHY_REG + CS_REG_VALUE(cs_num),
+ &val));
+
+ current_phase = ((int)val & 0xe0) >> 6;
+ if (current_phase >= max_phase)
+ max_phase = current_phase;
+ }
+ }
+
+ /* find minimum */
+ if (read_sample[cs_num] < min_read_sample)
+ min_read_sample = read_sample[cs_num];
+ }
+
+ min_read_sample = min_read_sample - 1;
+ max_read_sample = max_read_sample + 4 + (max_phase + 1) / 2 + 1;
+ if (min_read_sample >= 0xf)
+ min_read_sample = 0xf;
+ if (max_read_sample >= 0x1f)
+ max_read_sample = 0x1f;
+
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
+ ODT_TIMING_LOW,
+ ((min_read_sample - 1) << 12),
+ 0xf << 12));
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
+ ODT_TIMING_LOW,
+ (max_read_sample << 16),
+ 0x1f << 16));
+
+ return MV_OK;
+}
+
+int get_valid_win_rx(u32 dev_num, u32 if_id, u8 res[4])
+{
+ u32 reg_pup = RESULT_DB_PHY_REG_ADDR;
+ u32 reg_data;
+ u32 cs_num;
+ int i;
+
+ cs_num = 0;
+
+ /* TBD */
+ reg_pup += cs_num;
+
+ for (i = 0; i < 4; i++) {
+ CHECK_STATUS(ddr3_tip_bus_read(dev_num, if_id,
+ ACCESS_TYPE_UNICAST, i,
+ DDR_PHY_DATA, reg_pup,
+ ®_data));
+ res[i] = (reg_data >> RESULT_DB_PHY_REG_RX_OFFSET) & 0x1f;
+ }
+
+ return 0;
+}
+
+/*
+ * This algorithm deals with the vertical optimum from Voltage point of view
+ * of the sample signal.
+ * Voltage sample point can improve the Eye / window size of the bit and the
+ * pup.
+ * The problem is that it is tune for all DQ the same so there isn't any
+ * PBS like code.
+ * It is more like centralization.
+ * But because we don't have The training SM support we do it a bit more
+ * smart search to save time.
+ */
+int ddr3_tip_vref(u32 dev_num)
+{
+ /*
+ * The Vref register have non linear order. Need to check what will be
+ * in future projects.
+ */
+ u32 vref_map[8] = {
+ 1, 2, 3, 4, 5, 6, 7, 0
+ };
+ /* State and parameter definitions */
+ u32 initial_step = VREF_INITIAL_STEP;
+ /* need to be assign with minus ????? */
+ u32 second_step = VREF_SECOND_STEP;
+ u32 algo_run_flag = 0, currrent_vref = 0;
+ u32 while_count = 0;
+ u32 pup = 0, if_id = 0, num_pup = 0, rep = 0;
+ u32 val = 0;
+ u32 reg_addr = 0xa8;
+ u32 copy_start_pattern, copy_end_pattern;
+ enum hws_result *flow_result = ddr3_tip_get_result_ptr(training_stage);
+ u8 res[4];
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ CHECK_STATUS(ddr3_tip_special_rx(dev_num));
+
+ /* save start/end pattern */
+ copy_start_pattern = start_pattern;
+ copy_end_pattern = end_pattern;
+
+ /* set vref as centralization pattern */
+ start_pattern = PATTERN_VREF;
+ end_pattern = PATTERN_VREF;
+
+ /* init params */
+ for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ for (pup = 0;
+ pup < tm->num_of_bus_per_interface; pup++) {
+ current_vref[pup][if_id] = 0;
+ last_vref[pup][if_id] = 0;
+ lim_vref[pup][if_id] = 0;
+ current_valid_window[pup][if_id] = 0;
+ last_valid_window[pup][if_id] = 0;
+ if (vref_window_size[if_id][pup] >
+ vref_window_size_th) {
+ pup_st[pup][if_id] = VREF_CONVERGE;
+ DEBUG_TRAINING_HW_ALG(
+ DEBUG_LEVEL_INFO,
+ ("VREF config, IF[ %d ]pup[ %d ] - Vref tune not requered (%d)\n",
+ if_id, pup, __LINE__));
+ } else {
+ pup_st[pup][if_id] = VREF_STEP_1;
+ CHECK_STATUS(ddr3_tip_bus_read
+ (dev_num, if_id,
+ ACCESS_TYPE_UNICAST, pup,
+ DDR_PHY_DATA, reg_addr, &val));
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_UNICAST,
+ if_id, ACCESS_TYPE_UNICAST,
+ pup, DDR_PHY_DATA, reg_addr,
+ (val & (~0xf)) | vref_map[0]));
+ DEBUG_TRAINING_HW_ALG(
+ DEBUG_LEVEL_INFO,
+ ("VREF config, IF[ %d ]pup[ %d ] - Vref = %X (%d)\n",
+ if_id, pup,
+ (val & (~0xf)) | vref_map[0],
+ __LINE__));
+ }
+ }
+ interface_state[if_id] = 0;
+ }
+
+ /* TODO: Set number of active interfaces */
+ num_pup = tm->num_of_bus_per_interface * MAX_INTERFACE_NUM;
+
+ while ((algo_run_flag <= num_pup) & (while_count < 10)) {
+ while_count++;
+ for (rep = 1; rep < 4; rep++) {
+ ddr3_tip_centr_skip_min_win_check = 1;
+ ddr3_tip_centralization_rx(dev_num);
+ ddr3_tip_centr_skip_min_win_check = 0;
+
+ /* Read Valid window results only for non converge pups */
+ for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ if (interface_state[if_id] != 4) {
+ get_valid_win_rx(dev_num, if_id, res);
+ for (pup = 0;
+ pup < tm->num_of_bus_per_interface;
+ pup++) {
+ VALIDATE_ACTIVE
+ (tm->bus_act_mask, pup);
+ if (pup_st[pup]
+ [if_id] ==
+ VREF_CONVERGE)
+ continue;
+
+ current_valid_window[pup]
+ [if_id] =
+ (current_valid_window[pup]
+ [if_id] * (rep - 1) +
+ 1000 * res[pup]) / rep;
+ }
+ }
+ }
+ }
+
+ for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ DEBUG_TRAINING_HW_ALG(
+ DEBUG_LEVEL_TRACE,
+ ("current_valid_window: IF[ %d ] - ", if_id));
+
+ for (pup = 0;
+ pup < tm->num_of_bus_per_interface; pup++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, pup);
+ DEBUG_TRAINING_HW_ALG(DEBUG_LEVEL_TRACE,
+ ("%d ",
+ current_valid_window
+ [pup][if_id]));
+ }
+ DEBUG_TRAINING_HW_ALG(DEBUG_LEVEL_TRACE, ("\n"));
+ }
+
+ /* Compare results and respond as function of state */
+ for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ for (pup = 0;
+ pup < tm->num_of_bus_per_interface; pup++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, pup);
+ DEBUG_TRAINING_HW_ALG(DEBUG_LEVEL_TRACE,
+ ("I/F[ %d ], pup[ %d ] STATE #%d (%d)\n",
+ if_id, pup,
+ pup_st[pup]
+ [if_id], __LINE__));
+
+ if (pup_st[pup][if_id] == VREF_CONVERGE)
+ continue;
+
+ DEBUG_TRAINING_HW_ALG(DEBUG_LEVEL_TRACE,
+ ("I/F[ %d ], pup[ %d ] CHECK progress - Current %d Last %d, limit VREF %d (%d)\n",
+ if_id, pup,
+ current_valid_window[pup]
+ [if_id],
+ last_valid_window[pup]
+ [if_id], lim_vref[pup]
+ [if_id], __LINE__));
+
+ /*
+ * The -1 is for solution resolution +/- 1 tap
+ * of ADLL
+ */
+ if (current_valid_window[pup][if_id] + 200 >=
+ (last_valid_window[pup][if_id])) {
+ if (pup_st[pup][if_id] == VREF_STEP_1) {
+ /*
+ * We stay in the same state and
+ * step just update the window
+ * size (take the max) and Vref
+ */
+ if (current_vref[pup]
+ [if_id] == VREF_MAX_INDEX) {
+ /*
+ * If we step to the end
+ * and didn't converge
+ * to some particular
+ * better Vref value
+ * define the pup as
+ * converge and step
+ * back to nominal
+ * Vref.
+ */
+ pup_st[pup]
+ [if_id] =
+ VREF_CONVERGE;
+ algo_run_flag++;
+ interface_state
+ [if_id]++;
+ DEBUG_TRAINING_HW_ALG
+ (DEBUG_LEVEL_TRACE,
+ ("I/F[ %d ], pup[ %d ] VREF_CONVERGE - Vref = %X (%d)\n",
+ if_id, pup,
+ current_vref[pup]
+ [if_id],
+ __LINE__));
+ } else {
+ /* continue to update the Vref index */
+ current_vref[pup]
+ [if_id] =
+ ((current_vref[pup]
+ [if_id] +
+ initial_step) >
+ VREF_MAX_INDEX) ?
+ VREF_MAX_INDEX
+ : (current_vref[pup]
+ [if_id] +
+ initial_step);
+ if (current_vref[pup]
+ [if_id] ==
+ VREF_MAX_INDEX) {
+ pup_st[pup]
+ [if_id]
+ =
+ VREF_STEP_2;
+ }
+ lim_vref[pup]
+ [if_id] =
+ last_vref[pup]
+ [if_id] =
+ current_vref[pup]
+ [if_id];
+ }
+
+ last_valid_window[pup]
+ [if_id] =
+ GET_MAX(current_valid_window
+ [pup][if_id],
+ last_valid_window
+ [pup]
+ [if_id]);
+
+ /* update the Vref for next stage */
+ currrent_vref =
+ current_vref[pup]
+ [if_id];
+ CHECK_STATUS
+ (ddr3_tip_bus_read
+ (dev_num, if_id,
+ ACCESS_TYPE_UNICAST, pup,
+ DDR_PHY_DATA, reg_addr,
+ &val));
+ CHECK_STATUS
+ (ddr3_tip_bus_write
+ (dev_num,
+ ACCESS_TYPE_UNICAST,
+ if_id,
+ ACCESS_TYPE_UNICAST, pup,
+ DDR_PHY_DATA, reg_addr,
+ (val & (~0xf)) |
+ vref_map[currrent_vref]));
+ DEBUG_TRAINING_HW_ALG
+ (DEBUG_LEVEL_TRACE,
+ ("VREF config, IF[ %d ]pup[ %d ] - Vref = %X (%d)\n",
+ if_id, pup,
+ (val & (~0xf)) |
+ vref_map[currrent_vref],
+ __LINE__));
+ } else if (pup_st[pup][if_id]
+ == VREF_STEP_2) {
+ /*
+ * We keep on search back with
+ * the same step size.
+ */
+ last_valid_window[pup]
+ [if_id] =
+ GET_MAX(current_valid_window
+ [pup][if_id],
+ last_valid_window
+ [pup]
+ [if_id]);
+ last_vref[pup][if_id] =
+ current_vref[pup]
+ [if_id];
+
+ /* we finish all search space */
+ if ((current_vref[pup]
+ [if_id] - second_step) == lim_vref[pup][if_id]) {
+ /*
+ * If we step to the end
+ * and didn't converge
+ * to some particular
+ * better Vref value
+ * define the pup as
+ * converge and step
+ * back to nominal
+ * Vref.
+ */
+ pup_st[pup]
+ [if_id] =
+ VREF_CONVERGE;
+ algo_run_flag++;
+
+ interface_state
+ [if_id]++;
+
+ current_vref[pup]
+ [if_id] =
+ (current_vref[pup]
+ [if_id] -
+ second_step);
+
+ DEBUG_TRAINING_HW_ALG
+ (DEBUG_LEVEL_TRACE,
+ ("I/F[ %d ], pup[ %d ] VREF_CONVERGE - Vref = %X (%d)\n",
+ if_id, pup,
+ current_vref[pup]
+ [if_id],
+ __LINE__));
+ } else
+ /* we finish all search space */
+ if (current_vref[pup]
+ [if_id] ==
+ lim_vref[pup]
+ [if_id]) {
+ /*
+ * If we step to the end
+ * and didn't converge
+ * to some particular
+ * better Vref value
+ * define the pup as
+ * converge and step
+ * back to nominal
+ * Vref.
+ */
+ pup_st[pup]
+ [if_id] =
+ VREF_CONVERGE;
+
+ algo_run_flag++;
+ interface_state
+ [if_id]++;
+ DEBUG_TRAINING_HW_ALG
+ (DEBUG_LEVEL_TRACE,
+ ("I/F[ %d ], pup[ %d ] VREF_CONVERGE - Vref = %X (%d)\n",
+ if_id, pup,
+ current_vref[pup]
+ [if_id],
+ __LINE__));
+ } else {
+ current_vref[pup]
+ [if_id] =
+ current_vref[pup]
+ [if_id] -
+ second_step;
+ }
+
+ /* Update the Vref for next stage */
+ currrent_vref =
+ current_vref[pup]
+ [if_id];
+ CHECK_STATUS
+ (ddr3_tip_bus_read
+ (dev_num, if_id,
+ ACCESS_TYPE_UNICAST, pup,
+ DDR_PHY_DATA, reg_addr,
+ &val));
+ CHECK_STATUS
+ (ddr3_tip_bus_write
+ (dev_num,
+ ACCESS_TYPE_UNICAST,
+ if_id,
+ ACCESS_TYPE_UNICAST, pup,
+ DDR_PHY_DATA, reg_addr,
+ (val & (~0xf)) |
+ vref_map[currrent_vref]));
+ DEBUG_TRAINING_HW_ALG
+ (DEBUG_LEVEL_TRACE,
+ ("VREF config, IF[ %d ]pup[ %d ] - Vref = %X (%d)\n",
+ if_id, pup,
+ (val & (~0xf)) |
+ vref_map[currrent_vref],
+ __LINE__));
+ }
+ } else {
+ /* we change state and change step */
+ if (pup_st[pup][if_id] == VREF_STEP_1) {
+ pup_st[pup][if_id] =
+ VREF_STEP_2;
+ lim_vref[pup][if_id] =
+ current_vref[pup]
+ [if_id] - initial_step;
+ last_valid_window[pup]
+ [if_id] =
+ current_valid_window[pup]
+ [if_id];
+ last_vref[pup][if_id] =
+ current_vref[pup]
+ [if_id];
+ current_vref[pup][if_id] =
+ last_vref[pup][if_id] -
+ second_step;
+
+ /* Update the Vref for next stage */
+ CHECK_STATUS
+ (ddr3_tip_bus_read
+ (dev_num, if_id,
+ ACCESS_TYPE_UNICAST, pup,
+ DDR_PHY_DATA, reg_addr,
+ &val));
+ CHECK_STATUS
+ (ddr3_tip_bus_write
+ (dev_num,
+ ACCESS_TYPE_UNICAST,
+ if_id,
+ ACCESS_TYPE_UNICAST, pup,
+ DDR_PHY_DATA, reg_addr,
+ (val & (~0xf)) |
+ vref_map[current_vref[pup]
+ [if_id]]));
+ DEBUG_TRAINING_HW_ALG
+ (DEBUG_LEVEL_TRACE,
+ ("VREF config, IF[ %d ]pup[ %d ] - Vref = %X (%d)\n",
+ if_id, pup,
+ (val & (~0xf)) |
+ vref_map[current_vref[pup]
+ [if_id]],
+ __LINE__));
+
+ } else if (pup_st[pup][if_id] == VREF_STEP_2) {
+ /*
+ * The last search was the max
+ * point set value and exit
+ */
+ CHECK_STATUS
+ (ddr3_tip_bus_read
+ (dev_num, if_id,
+ ACCESS_TYPE_UNICAST, pup,
+ DDR_PHY_DATA, reg_addr,
+ &val));
+ CHECK_STATUS
+ (ddr3_tip_bus_write
+ (dev_num,
+ ACCESS_TYPE_UNICAST,
+ if_id,
+ ACCESS_TYPE_UNICAST, pup,
+ DDR_PHY_DATA, reg_addr,
+ (val & (~0xf)) |
+ vref_map[last_vref[pup]
+ [if_id]]));
+ DEBUG_TRAINING_HW_ALG
+ (DEBUG_LEVEL_TRACE,
+ ("VREF config, IF[ %d ]pup[ %d ] - Vref = %X (%d)\n",
+ if_id, pup,
+ (val & (~0xf)) |
+ vref_map[last_vref[pup]
+ [if_id]],
+ __LINE__));
+ pup_st[pup][if_id] =
+ VREF_CONVERGE;
+ algo_run_flag++;
+ interface_state[if_id]++;
+ DEBUG_TRAINING_HW_ALG
+ (DEBUG_LEVEL_TRACE,
+ ("I/F[ %d ], pup[ %d ] VREF_CONVERGE - Vref = %X (%d)\n",
+ if_id, pup,
+ current_vref[pup]
+ [if_id], __LINE__));
+ }
+ }
+ }
+ }
+ }
+
+ for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ for (pup = 0;
+ pup < tm->num_of_bus_per_interface; pup++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, pup);
+ CHECK_STATUS(ddr3_tip_bus_read
+ (dev_num, if_id,
+ ACCESS_TYPE_UNICAST, pup,
+ DDR_PHY_DATA, reg_addr, &val));
+ DEBUG_TRAINING_HW_ALG(
+ DEBUG_LEVEL_INFO,
+ ("FINAL values: I/F[ %d ], pup[ %d ] - Vref = %X (%d)\n",
+ if_id, pup, val, __LINE__));
+ }
+ }
+
+ flow_result[if_id] = TEST_SUCCESS;
+
+ /* restore start/end pattern */
+ start_pattern = copy_start_pattern;
+ end_pattern = copy_end_pattern;
+
+ return 0;
+}
+
+/*
+ * CK/CA Delay
+ */
+int ddr3_tip_cmd_addr_init_delay(u32 dev_num, u32 adll_tap)
+{
+ u32 if_id = 0;
+ u32 ck_num_adll_tap = 0, ca_num_adll_tap = 0, data = 0;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ /*
+ * ck_delay_table is delaying the of the clock signal only.
+ * (to overcome timing issues between_c_k & command/address signals)
+ */
+ /*
+ * ca_delay is delaying the of the entire command & Address signals
+ * (include Clock signal to overcome DGL error on the Clock versus
+ * the DQS).
+ */
+
+ /* Calc ADLL Tap */
+ if ((ck_delay == -1) || (ck_delay_16 == -1)) {
+ DEBUG_TRAINING_HW_ALG(
+ DEBUG_LEVEL_ERROR,
+ ("ERROR: One of ck_delay values not initialized!!!\n"));
+ }
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ /* Calc delay ps in ADLL tap */
+ if (tm->interface_params[if_id].bus_width ==
+ BUS_WIDTH_16)
+ ck_num_adll_tap = ck_delay_16 / adll_tap;
+ else
+ ck_num_adll_tap = ck_delay / adll_tap;
+
+ ca_num_adll_tap = ca_delay / adll_tap;
+ data = (ck_num_adll_tap & 0x3f) +
+ ((ca_num_adll_tap & 0x3f) << 10);
+
+ /*
+ * Set the ADLL number to the CK ADLL for Interfaces for
+ * all Pup
+ */
+ DEBUG_TRAINING_HW_ALG(
+ DEBUG_LEVEL_TRACE,
+ ("ck_num_adll_tap %d ca_num_adll_tap %d adll_tap %d\n",
+ ck_num_adll_tap, ca_num_adll_tap, adll_tap));
+
+ CHECK_STATUS(ddr3_tip_bus_write(dev_num, ACCESS_TYPE_UNICAST,
+ if_id, ACCESS_TYPE_MULTICAST,
+ PARAM_NOT_CARE, DDR_PHY_CONTROL,
+ 0x0, data));
+ }
+
+ return MV_OK;
+}
diff --git a/drivers/ddr/marvell/a38x/old/ddr3_training_hw_algo.h b/drivers/ddr/marvell/a38x/old/ddr3_training_hw_algo.h
new file mode 100644
index 0000000..6e1bab2
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/ddr3_training_hw_algo.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _DDR3_TRAINING_HW_ALGO_H_
+#define _DDR3_TRAINING_HW_ALGO_H_
+
+int ddr3_tip_vref(u32 dev_num);
+int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id);
+int ddr3_tip_cmd_addr_init_delay(u32 dev_num, u32 adll_tap);
+
+#endif /* _DDR3_TRAINING_HW_ALGO_H_ */
diff --git a/drivers/ddr/marvell/a38x/old/ddr3_training_ip.h b/drivers/ddr/marvell/a38x/old/ddr3_training_ip.h
new file mode 100644
index 0000000..ed92873
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/ddr3_training_ip.h
@@ -0,0 +1,178 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _DDR3_TRAINING_IP_H_
+#define _DDR3_TRAINING_IP_H_
+
+#include "ddr3_training_ip_def.h"
+#include "ddr_topology_def.h"
+#include "ddr_training_ip_db.h"
+
+#define DDR3_TIP_VERSION_STRING "DDR3 Training Sequence - Ver TIP-1.29."
+
+#define MAX_CS_NUM 4
+#define MAX_TOTAL_BUS_NUM (MAX_INTERFACE_NUM * MAX_BUS_NUM)
+#define MAX_DQ_NUM 40
+
+#define GET_MIN(arg1, arg2) ((arg1) < (arg2)) ? (arg1) : (arg2)
+#define GET_MAX(arg1, arg2) ((arg1) < (arg2)) ? (arg2) : (arg1)
+
+#define INIT_CONTROLLER_MASK_BIT 0x00000001
+#define STATIC_LEVELING_MASK_BIT 0x00000002
+#define SET_LOW_FREQ_MASK_BIT 0x00000004
+#define LOAD_PATTERN_MASK_BIT 0x00000008
+#define SET_MEDIUM_FREQ_MASK_BIT 0x00000010
+#define WRITE_LEVELING_MASK_BIT 0x00000020
+#define LOAD_PATTERN_2_MASK_BIT 0x00000040
+#define READ_LEVELING_MASK_BIT 0x00000080
+#define SW_READ_LEVELING_MASK_BIT 0x00000100
+#define WRITE_LEVELING_SUPP_MASK_BIT 0x00000200
+#define PBS_RX_MASK_BIT 0x00000400
+#define PBS_TX_MASK_BIT 0x00000800
+#define SET_TARGET_FREQ_MASK_BIT 0x00001000
+#define ADJUST_DQS_MASK_BIT 0x00002000
+#define WRITE_LEVELING_TF_MASK_BIT 0x00004000
+#define LOAD_PATTERN_HIGH_MASK_BIT 0x00008000
+#define READ_LEVELING_TF_MASK_BIT 0x00010000
+#define WRITE_LEVELING_SUPP_TF_MASK_BIT 0x00020000
+#define DM_PBS_TX_MASK_BIT 0x00040000
+#define CENTRALIZATION_RX_MASK_BIT 0x00100000
+#define CENTRALIZATION_TX_MASK_BIT 0x00200000
+#define TX_EMPHASIS_MASK_BIT 0x00400000
+#define PER_BIT_READ_LEVELING_TF_MASK_BIT 0x00800000
+#define VREF_CALIBRATION_MASK_BIT 0x01000000
+
+enum hws_result {
+ TEST_FAILED = 0,
+ TEST_SUCCESS = 1,
+ NO_TEST_DONE = 2
+};
+
+enum hws_training_result {
+ RESULT_PER_BIT,
+ RESULT_PER_BYTE
+};
+
+enum auto_tune_stage {
+ INIT_CONTROLLER,
+ STATIC_LEVELING,
+ SET_LOW_FREQ,
+ LOAD_PATTERN,
+ SET_MEDIUM_FREQ,
+ WRITE_LEVELING,
+ LOAD_PATTERN_2,
+ READ_LEVELING,
+ WRITE_LEVELING_SUPP,
+ PBS_RX,
+ PBS_TX,
+ SET_TARGET_FREQ,
+ ADJUST_DQS,
+ WRITE_LEVELING_TF,
+ READ_LEVELING_TF,
+ WRITE_LEVELING_SUPP_TF,
+ DM_PBS_TX,
+ VREF_CALIBRATION,
+ CENTRALIZATION_RX,
+ CENTRALIZATION_TX,
+ TX_EMPHASIS,
+ LOAD_PATTERN_HIGH,
+ PER_BIT_READ_LEVELING_TF,
+ MAX_STAGE_LIMIT
+};
+
+enum hws_access_type {
+ ACCESS_TYPE_UNICAST = 0,
+ ACCESS_TYPE_MULTICAST = 1
+};
+
+enum hws_algo_type {
+ ALGO_TYPE_DYNAMIC,
+ ALGO_TYPE_STATIC
+};
+
+struct init_cntr_param {
+ int is_ctrl64_bit;
+ int do_mrs_phy;
+ int init_phy;
+ int msys_init;
+};
+
+struct pattern_info {
+ u8 num_of_phases_tx;
+ u8 tx_burst_size;
+ u8 delay_between_bursts;
+ u8 num_of_phases_rx;
+ u32 start_addr;
+ u8 pattern_len;
+};
+
+/* CL value for each frequency */
+struct cl_val_per_freq {
+ u8 cl_val[DDR_FREQ_LIMIT];
+};
+
+struct cs_element {
+ u8 cs_num;
+ u8 num_of_cs;
+};
+
+struct mode_info {
+ /* 32 bits representing MRS bits */
+ u32 reg_mr0[MAX_INTERFACE_NUM];
+ u32 reg_mr1[MAX_INTERFACE_NUM];
+ u32 reg_mr2[MAX_INTERFACE_NUM];
+ u32 reg_m_r3[MAX_INTERFACE_NUM];
+ /*
+ * Each element in array represent read_data_sample register delay for
+ * a specific interface.
+ * Each register, 4 bits[0+CS*8 to 4+CS*8] represent Number of DDR
+ * cycles from read command until data is ready to be fetched from
+ * the PHY, when accessing CS.
+ */
+ u32 read_data_sample[MAX_INTERFACE_NUM];
+ /*
+ * Each element in array represent read_data_sample register delay for
+ * a specific interface.
+ * Each register, 4 bits[0+CS*8 to 4+CS*8] represent the total delay
+ * from read command until opening the read mask, when accessing CS.
+ * This field defines the delay in DDR cycles granularity.
+ */
+ u32 read_data_ready[MAX_INTERFACE_NUM];
+};
+
+struct hws_tip_freq_config_info {
+ u8 is_supported;
+ u8 bw_per_freq;
+ u8 rate_per_freq;
+};
+
+struct hws_cs_config_info {
+ u32 cs_reg_value;
+ u32 cs_cbe_value;
+};
+
+struct dfx_access {
+ u8 pipe;
+ u8 client;
+};
+
+struct hws_xsb_info {
+ struct dfx_access *dfx_table;
+};
+
+int ddr3_tip_register_dq_table(u32 dev_num, u32 *table);
+int hws_ddr3_tip_select_ddr_controller(u32 dev_num, int enable);
+int hws_ddr3_tip_init_controller(u32 dev_num,
+ struct init_cntr_param *init_cntr_prm);
+int hws_ddr3_tip_load_topology_map(u32 dev_num,
+ struct hws_topology_map *topology);
+int hws_ddr3_tip_run_alg(u32 dev_num, enum hws_algo_type algo_type);
+int hws_ddr3_tip_mode_read(u32 dev_num, struct mode_info *mode_info);
+int ddr3_tip_is_pup_lock(u32 *pup_buf, enum hws_training_result read_mode);
+u8 ddr3_tip_get_buf_min(u8 *buf_ptr);
+u8 ddr3_tip_get_buf_max(u8 *buf_ptr);
+
+#endif /* _DDR3_TRAINING_IP_H_ */
diff --git a/drivers/ddr/marvell/a38x/old/ddr3_training_ip_bist.h b/drivers/ddr/marvell/a38x/old/ddr3_training_ip_bist.h
new file mode 100644
index 0000000..5c9bfe9
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/ddr3_training_ip_bist.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _DDR3_TRAINING_IP_BIST_H_
+#define _DDR3_TRAINING_IP_BIST_H_
+
+#include "ddr3_training_ip.h"
+
+enum hws_bist_operation {
+ BIST_STOP = 0,
+ BIST_START = 1
+};
+
+enum hws_stress_jump {
+ STRESS_NONE = 0,
+ STRESS_ENABLE = 1
+};
+
+enum hws_pattern_duration {
+ DURATION_SINGLE = 0,
+ DURATION_STOP_AT_FAIL = 1,
+ DURATION_ADDRESS = 2,
+ DURATION_CONT = 4
+};
+
+struct bist_result {
+ u32 bist_error_cnt;
+ u32 bist_fail_low;
+ u32 bist_fail_high;
+ u32 bist_last_fail_addr;
+};
+
+int ddr3_tip_bist_read_result(u32 dev_num, u32 if_id,
+ struct bist_result *pst_bist_result);
+int ddr3_tip_bist_activate(u32 dev_num, enum hws_pattern pattern,
+ enum hws_access_type access_type,
+ u32 if_num, enum hws_dir direction,
+ enum hws_stress_jump addr_stress_jump,
+ enum hws_pattern_duration duration,
+ enum hws_bist_operation oper_type,
+ u32 offset, u32 cs_num, u32 pattern_addr_length);
+int hws_ddr3_run_bist(u32 dev_num, enum hws_pattern pattern, u32 *result,
+ u32 cs_num);
+int ddr3_tip_run_sweep_test(int dev_num, u32 repeat_num, u32 direction,
+ u32 mode);
+int ddr3_tip_print_regs(u32 dev_num);
+int ddr3_tip_reg_dump(u32 dev_num);
+int run_xsb_test(u32 dev_num, u32 mem_addr, u32 write_type, u32 read_type,
+ u32 burst_length);
+
+#endif /* _DDR3_TRAINING_IP_BIST_H_ */
diff --git a/drivers/ddr/marvell/a38x/old/ddr3_training_ip_centralization.h b/drivers/ddr/marvell/a38x/old/ddr3_training_ip_centralization.h
new file mode 100644
index 0000000..7c57603
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/ddr3_training_ip_centralization.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _DDR3_TRAINING_IP_CENTRALIZATION_H
+#define _DDR3_TRAINING_IP_CENTRALIZATION_H
+
+int ddr3_tip_centralization_tx(u32 dev_num);
+int ddr3_tip_centralization_rx(u32 dev_num);
+int ddr3_tip_print_centralization_result(u32 dev_num);
+int ddr3_tip_special_rx(u32 dev_num);
+
+#endif /* _DDR3_TRAINING_IP_CENTRALIZATION_H */
diff --git a/drivers/ddr/marvell/a38x/old/ddr3_training_ip_db.h b/drivers/ddr/marvell/a38x/old/ddr3_training_ip_db.h
new file mode 100644
index 0000000..c0afa77
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/ddr3_training_ip_db.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _DDR3_TRAINING_IP_DB_H_
+#define _DDR3_TRAINING_IP_DB_H_
+
+enum hws_pattern {
+ PATTERN_PBS1,
+ PATTERN_PBS2,
+ PATTERN_RL,
+ PATTERN_STATIC_PBS,
+ PATTERN_KILLER_DQ0,
+ PATTERN_KILLER_DQ1,
+ PATTERN_KILLER_DQ2,
+ PATTERN_KILLER_DQ3,
+ PATTERN_KILLER_DQ4,
+ PATTERN_KILLER_DQ5,
+ PATTERN_KILLER_DQ6,
+ PATTERN_KILLER_DQ7,
+ PATTERN_PBS3,
+ PATTERN_RL2,
+ PATTERN_TEST,
+ PATTERN_FULL_SSO0,
+ PATTERN_FULL_SSO1,
+ PATTERN_FULL_SSO2,
+ PATTERN_FULL_SSO3,
+ PATTERN_VREF,
+ PATTERN_LIMIT
+};
+
+#endif /* _DDR3_TRAINING_IP_DB_H_ */
diff --git a/drivers/ddr/marvell/a38x/old/ddr3_training_ip_def.h b/drivers/ddr/marvell/a38x/old/ddr3_training_ip_def.h
new file mode 100644
index 0000000..51a66d8
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/ddr3_training_ip_def.h
@@ -0,0 +1,173 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _DDR3_TRAINING_IP_DEF_H
+#define _DDR3_TRAINING_IP_DEF_H
+
+#include "silicon_if.h"
+
+#define PATTERN_55 0x55555555
+#define PATTERN_AA 0xaaaaaaaa
+#define PATTERN_80 0x80808080
+#define PATTERN_20 0x20202020
+#define PATTERN_01 0x01010101
+#define PATTERN_FF 0xffffffff
+#define PATTERN_00 0x00000000
+
+/* 16bit bus width patterns */
+#define PATTERN_55AA 0x5555aaaa
+#define PATTERN_00FF 0x0000ffff
+#define PATTERN_0080 0x00008080
+
+#define INVALID_VALUE 0xffffffff
+#define MAX_NUM_OF_DUNITS 32
+/*
+ * length *2 = length in words of pattern, first low address,
+ * second high address
+ */
+#define TEST_PATTERN_LENGTH 4
+#define KILLER_PATTERN_DQ_NUMBER 8
+#define SSO_DQ_NUMBER 4
+#define PATTERN_MAXIMUM_LENGTH 64
+#define ADLL_TX_LENGTH 64
+#define ADLL_RX_LENGTH 32
+
+#define PARAM_NOT_CARE 0
+
+#define READ_LEVELING_PHY_OFFSET 2
+#define WRITE_LEVELING_PHY_OFFSET 0
+
+#define MASK_ALL_BITS 0xffffffff
+
+#define CS_BIT_MASK 0xf
+
+/* DFX access */
+#define BROADCAST_ID 28
+#define MULTICAST_ID 29
+
+#define XSB_BASE_ADDR 0x00004000
+#define XSB_CTRL_0_REG 0x00000000
+#define XSB_CTRL_1_REG 0x00000004
+#define XSB_CMD_REG 0x00000008
+#define XSB_ADDRESS_REG 0x0000000c
+#define XSB_DATA_REG 0x00000010
+#define PIPE_ENABLE_ADDR 0x000f8000
+#define ENABLE_DDR_TUNING_ADDR 0x000f829c
+
+#define CLIENT_BASE_ADDR 0x00002000
+#define CLIENT_CTRL_REG 0x00000000
+
+#define TARGET_INT 0x1801
+#define TARGET_EXT 0x180e
+#define BYTE_EN 0
+#define CMD_READ 0
+#define CMD_WRITE 1
+
+#define INTERNAL_ACCESS_PORT 1
+#define EXECUTING 1
+#define ACCESS_EXT 1
+#define CS2_EXIST_BIT 2
+#define TRAINING_ID 0xf
+#define EXT_TRAINING_ID 1
+#define EXT_MODE 0x4
+
+#define GET_RESULT_STATE(res) (res)
+#define SET_RESULT_STATE(res, state) (res = state)
+
+#define _1K 0x00000400
+#define _4K 0x00001000
+#define _8K 0x00002000
+#define _16K 0x00004000
+#define _32K 0x00008000
+#define _64K 0x00010000
+#define _128K 0x00020000
+#define _256K 0x00040000
+#define _512K 0x00080000
+
+#define _1M 0x00100000
+#define _2M 0x00200000
+#define _4M 0x00400000
+#define _8M 0x00800000
+#define _16M 0x01000000
+#define _32M 0x02000000
+#define _64M 0x04000000
+#define _128M 0x08000000
+#define _256M 0x10000000
+#define _512M 0x20000000
+
+#define _1G 0x40000000
+#define _2G 0x80000000
+
+#define ADDR_SIZE_512MB 0x04000000
+#define ADDR_SIZE_1GB 0x08000000
+#define ADDR_SIZE_2GB 0x10000000
+#define ADDR_SIZE_4GB 0x20000000
+#define ADDR_SIZE_8GB 0x40000000
+
+enum hws_edge_compare {
+ EDGE_PF,
+ EDGE_FP,
+ EDGE_FPF,
+ EDGE_PFP
+};
+
+enum hws_control_element {
+ HWS_CONTROL_ELEMENT_ADLL, /* per bit 1 edge */
+ HWS_CONTROL_ELEMENT_DQ_SKEW,
+ HWS_CONTROL_ELEMENT_DQS_SKEW
+};
+
+enum hws_search_dir {
+ HWS_LOW2HIGH,
+ HWS_HIGH2LOW,
+ HWS_SEARCH_DIR_LIMIT
+};
+
+enum hws_page_size {
+ PAGE_SIZE_1K,
+ PAGE_SIZE_2K
+};
+
+enum hws_operation {
+ OPERATION_READ = 0,
+ OPERATION_WRITE = 1
+};
+
+enum hws_training_ip_stat {
+ HWS_TRAINING_IP_STATUS_FAIL,
+ HWS_TRAINING_IP_STATUS_SUCCESS,
+ HWS_TRAINING_IP_STATUS_TIMEOUT
+};
+
+enum hws_ddr_cs {
+ CS_SINGLE,
+ CS_NON_SINGLE
+};
+
+enum hws_ddr_phy {
+ DDR_PHY_DATA = 0,
+ DDR_PHY_CONTROL = 1
+};
+
+enum hws_dir {
+ OPER_WRITE,
+ OPER_READ,
+ OPER_WRITE_AND_READ
+};
+
+enum hws_wl_supp {
+ PHASE_SHIFT,
+ CLOCK_SHIFT,
+ ALIGN_SHIFT
+};
+
+struct reg_data {
+ u32 reg_addr;
+ u32 reg_data;
+ u32 reg_mask;
+};
+
+#endif /* _DDR3_TRAINING_IP_DEF_H */
diff --git a/drivers/ddr/marvell/a38x/old/ddr3_training_ip_engine.c b/drivers/ddr/marvell/a38x/old/ddr3_training_ip_engine.c
new file mode 100644
index 0000000..869f397
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/ddr3_training_ip_engine.c
@@ -0,0 +1,1354 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <linux/delay.h>
+
+#include "ddr3_init.h"
+
+#define PATTERN_1 0x55555555
+#define PATTERN_2 0xaaaaaaaa
+
+#define VALIDATE_TRAINING_LIMIT(e1, e2) \
+ ((((e2) - (e1) + 1) > 33) && ((e1) < 67))
+
+u32 phy_reg_bk[MAX_INTERFACE_NUM][MAX_BUS_NUM][BUS_WIDTH_IN_BITS];
+
+u32 training_res[MAX_INTERFACE_NUM * MAX_BUS_NUM * BUS_WIDTH_IN_BITS *
+ HWS_SEARCH_DIR_LIMIT];
+
+u16 mask_results_dq_reg_map[] = {
+ RESULT_CONTROL_PUP_0_BIT_0_REG, RESULT_CONTROL_PUP_0_BIT_1_REG,
+ RESULT_CONTROL_PUP_0_BIT_2_REG, RESULT_CONTROL_PUP_0_BIT_3_REG,
+ RESULT_CONTROL_PUP_0_BIT_4_REG, RESULT_CONTROL_PUP_0_BIT_5_REG,
+ RESULT_CONTROL_PUP_0_BIT_6_REG, RESULT_CONTROL_PUP_0_BIT_7_REG,
+ RESULT_CONTROL_PUP_1_BIT_0_REG, RESULT_CONTROL_PUP_1_BIT_1_REG,
+ RESULT_CONTROL_PUP_1_BIT_2_REG, RESULT_CONTROL_PUP_1_BIT_3_REG,
+ RESULT_CONTROL_PUP_1_BIT_4_REG, RESULT_CONTROL_PUP_1_BIT_5_REG,
+ RESULT_CONTROL_PUP_1_BIT_6_REG, RESULT_CONTROL_PUP_1_BIT_7_REG,
+ RESULT_CONTROL_PUP_2_BIT_0_REG, RESULT_CONTROL_PUP_2_BIT_1_REG,
+ RESULT_CONTROL_PUP_2_BIT_2_REG, RESULT_CONTROL_PUP_2_BIT_3_REG,
+ RESULT_CONTROL_PUP_2_BIT_4_REG, RESULT_CONTROL_PUP_2_BIT_5_REG,
+ RESULT_CONTROL_PUP_2_BIT_6_REG, RESULT_CONTROL_PUP_2_BIT_7_REG,
+ RESULT_CONTROL_PUP_3_BIT_0_REG, RESULT_CONTROL_PUP_3_BIT_1_REG,
+ RESULT_CONTROL_PUP_3_BIT_2_REG, RESULT_CONTROL_PUP_3_BIT_3_REG,
+ RESULT_CONTROL_PUP_3_BIT_4_REG, RESULT_CONTROL_PUP_3_BIT_5_REG,
+ RESULT_CONTROL_PUP_3_BIT_6_REG, RESULT_CONTROL_PUP_3_BIT_7_REG,
+ RESULT_CONTROL_PUP_4_BIT_0_REG, RESULT_CONTROL_PUP_4_BIT_1_REG,
+ RESULT_CONTROL_PUP_4_BIT_2_REG, RESULT_CONTROL_PUP_4_BIT_3_REG,
+ RESULT_CONTROL_PUP_4_BIT_4_REG, RESULT_CONTROL_PUP_4_BIT_5_REG,
+ RESULT_CONTROL_PUP_4_BIT_6_REG, RESULT_CONTROL_PUP_4_BIT_7_REG,
+};
+
+u16 mask_results_pup_reg_map[] = {
+ RESULT_CONTROL_BYTE_PUP_0_REG, RESULT_CONTROL_BYTE_PUP_1_REG,
+ RESULT_CONTROL_BYTE_PUP_2_REG, RESULT_CONTROL_BYTE_PUP_3_REG,
+ RESULT_CONTROL_BYTE_PUP_4_REG
+};
+
+u16 mask_results_dq_reg_map_pup3_ecc[] = {
+ RESULT_CONTROL_PUP_0_BIT_0_REG, RESULT_CONTROL_PUP_0_BIT_1_REG,
+ RESULT_CONTROL_PUP_0_BIT_2_REG, RESULT_CONTROL_PUP_0_BIT_3_REG,
+ RESULT_CONTROL_PUP_0_BIT_4_REG, RESULT_CONTROL_PUP_0_BIT_5_REG,
+ RESULT_CONTROL_PUP_0_BIT_6_REG, RESULT_CONTROL_PUP_0_BIT_7_REG,
+ RESULT_CONTROL_PUP_1_BIT_0_REG, RESULT_CONTROL_PUP_1_BIT_1_REG,
+ RESULT_CONTROL_PUP_1_BIT_2_REG, RESULT_CONTROL_PUP_1_BIT_3_REG,
+ RESULT_CONTROL_PUP_1_BIT_4_REG, RESULT_CONTROL_PUP_1_BIT_5_REG,
+ RESULT_CONTROL_PUP_1_BIT_6_REG, RESULT_CONTROL_PUP_1_BIT_7_REG,
+ RESULT_CONTROL_PUP_2_BIT_0_REG, RESULT_CONTROL_PUP_2_BIT_1_REG,
+ RESULT_CONTROL_PUP_2_BIT_2_REG, RESULT_CONTROL_PUP_2_BIT_3_REG,
+ RESULT_CONTROL_PUP_2_BIT_4_REG, RESULT_CONTROL_PUP_2_BIT_5_REG,
+ RESULT_CONTROL_PUP_2_BIT_6_REG, RESULT_CONTROL_PUP_2_BIT_7_REG,
+ RESULT_CONTROL_PUP_4_BIT_0_REG, RESULT_CONTROL_PUP_4_BIT_1_REG,
+ RESULT_CONTROL_PUP_4_BIT_2_REG, RESULT_CONTROL_PUP_4_BIT_3_REG,
+ RESULT_CONTROL_PUP_4_BIT_4_REG, RESULT_CONTROL_PUP_4_BIT_5_REG,
+ RESULT_CONTROL_PUP_4_BIT_6_REG, RESULT_CONTROL_PUP_4_BIT_7_REG,
+ RESULT_CONTROL_PUP_4_BIT_0_REG, RESULT_CONTROL_PUP_4_BIT_1_REG,
+ RESULT_CONTROL_PUP_4_BIT_2_REG, RESULT_CONTROL_PUP_4_BIT_3_REG,
+ RESULT_CONTROL_PUP_4_BIT_4_REG, RESULT_CONTROL_PUP_4_BIT_5_REG,
+ RESULT_CONTROL_PUP_4_BIT_6_REG, RESULT_CONTROL_PUP_4_BIT_7_REG,
+};
+
+u16 mask_results_pup_reg_map_pup3_ecc[] = {
+ RESULT_CONTROL_BYTE_PUP_0_REG, RESULT_CONTROL_BYTE_PUP_1_REG,
+ RESULT_CONTROL_BYTE_PUP_2_REG, RESULT_CONTROL_BYTE_PUP_4_REG,
+ RESULT_CONTROL_BYTE_PUP_4_REG
+};
+
+struct pattern_info pattern_table_16[] = {
+ /*
+ * num tx phases, tx burst, delay between, rx pattern,
+ * start_address, pattern_len
+ */
+ {1, 1, 2, 1, 0x0080, 2}, /* PATTERN_PBS1 */
+ {1, 1, 2, 1, 0x00c0, 2}, /* PATTERN_PBS2 */
+ {1, 1, 2, 1, 0x0100, 2}, /* PATTERN_RL */
+ {0xf, 0x7, 2, 0x7, 0x0140, 16}, /* PATTERN_STATIC_PBS */
+ {0xf, 0x7, 2, 0x7, 0x0190, 16}, /* PATTERN_KILLER_DQ0 */
+ {0xf, 0x7, 2, 0x7, 0x01d0, 16}, /* PATTERN_KILLER_DQ1 */
+ {0xf, 0x7, 2, 0x7, 0x0210, 16}, /* PATTERN_KILLER_DQ2 */
+ {0xf, 0x7, 2, 0x7, 0x0250, 16}, /* PATTERN_KILLER_DQ3 */
+ {0xf, 0x7, 2, 0x7, 0x0290, 16}, /* PATTERN_KILLER_DQ4 */
+ {0xf, 0x7, 2, 0x7, 0x02d0, 16}, /* PATTERN_KILLER_DQ5 */
+ {0xf, 0x7, 2, 0x7, 0x0310, 16}, /* PATTERN_KILLER_DQ6 */
+ {0xf, 0x7, 2, 0x7, 0x0350, 16}, /* PATTERN_KILLER_DQ7 */
+ {1, 1, 2, 1, 0x0380, 2}, /* PATTERN_PBS3 */
+ {1, 1, 2, 1, 0x0000, 2}, /* PATTERN_RL2 */
+ {1, 1, 2, 1, 0x0040, 2}, /* PATTERN_TEST */
+ {0xf, 0x7, 2, 0x7, 0x03c0, 16}, /* PATTERN_FULL_SSO_1T */
+ {0xf, 0x7, 2, 0x7, 0x0400, 16}, /* PATTERN_FULL_SSO_2T */
+ {0xf, 0x7, 2, 0x7, 0x0440, 16}, /* PATTERN_FULL_SSO_3T */
+ {0xf, 0x7, 2, 0x7, 0x0480, 16}, /* PATTERN_FULL_SSO_4T */
+ {0xf, 0x7, 2, 0x7, 0x04c0, 16} /* PATTERN_VREF */
+ /*Note: actual start_address is <<3 of defined addess */
+};
+
+struct pattern_info pattern_table_32[] = {
+ /*
+ * num tx phases, tx burst, delay between, rx pattern,
+ * start_address, pattern_len
+ */
+ {3, 3, 2, 3, 0x0080, 4}, /* PATTERN_PBS1 */
+ {3, 3, 2, 3, 0x00c0, 4}, /* PATTERN_PBS2 */
+ {3, 3, 2, 3, 0x0100, 4}, /* PATTERN_RL */
+ {0x1f, 0xf, 2, 0xf, 0x0140, 32}, /* PATTERN_STATIC_PBS */
+ {0x1f, 0xf, 2, 0xf, 0x0190, 32}, /* PATTERN_KILLER_DQ0 */
+ {0x1f, 0xf, 2, 0xf, 0x01d0, 32}, /* PATTERN_KILLER_DQ1 */
+ {0x1f, 0xf, 2, 0xf, 0x0210, 32}, /* PATTERN_KILLER_DQ2 */
+ {0x1f, 0xf, 2, 0xf, 0x0250, 32}, /* PATTERN_KILLER_DQ3 */
+ {0x1f, 0xf, 2, 0xf, 0x0290, 32}, /* PATTERN_KILLER_DQ4 */
+ {0x1f, 0xf, 2, 0xf, 0x02d0, 32}, /* PATTERN_KILLER_DQ5 */
+ {0x1f, 0xf, 2, 0xf, 0x0310, 32}, /* PATTERN_KILLER_DQ6 */
+ {0x1f, 0xf, 2, 0xf, 0x0350, 32}, /* PATTERN_KILLER_DQ7 */
+ {3, 3, 2, 3, 0x0380, 4}, /* PATTERN_PBS3 */
+ {3, 3, 2, 3, 0x0000, 4}, /* PATTERN_RL2 */
+ {3, 3, 2, 3, 0x0040, 4}, /* PATTERN_TEST */
+ {0x1f, 0xf, 2, 0xf, 0x03c0, 32}, /* PATTERN_FULL_SSO_1T */
+ {0x1f, 0xf, 2, 0xf, 0x0400, 32}, /* PATTERN_FULL_SSO_2T */
+ {0x1f, 0xf, 2, 0xf, 0x0440, 32}, /* PATTERN_FULL_SSO_3T */
+ {0x1f, 0xf, 2, 0xf, 0x0480, 32}, /* PATTERN_FULL_SSO_4T */
+ {0x1f, 0xf, 2, 0xf, 0x04c0, 32} /* PATTERN_VREF */
+ /*Note: actual start_address is <<3 of defined addess */
+};
+
+u32 train_dev_num;
+enum hws_ddr_cs traintrain_cs_type;
+u32 train_pup_num;
+enum hws_training_result train_result_type;
+enum hws_control_element train_control_element;
+enum hws_search_dir traine_search_dir;
+enum hws_dir train_direction;
+u32 train_if_select;
+u32 train_init_value;
+u32 train_number_iterations;
+enum hws_pattern train_pattern;
+enum hws_edge_compare train_edge_compare;
+u32 train_cs_num;
+u32 train_if_acess, train_if_id, train_pup_access;
+u32 max_polling_for_done = 1000000;
+
+u32 *ddr3_tip_get_buf_ptr(u32 dev_num, enum hws_search_dir search,
+ enum hws_training_result result_type,
+ u32 interface_num)
+{
+ u32 *buf_ptr = NULL;
+
+ buf_ptr = &training_res
+ [MAX_INTERFACE_NUM * MAX_BUS_NUM * BUS_WIDTH_IN_BITS * search +
+ interface_num * MAX_BUS_NUM * BUS_WIDTH_IN_BITS];
+
+ return buf_ptr;
+}
+
+/*
+ * IP Training search
+ * Note: for one edge search only from fail to pass, else jitter can
+ * be be entered into solution.
+ */
+int ddr3_tip_ip_training(u32 dev_num, enum hws_access_type access_type,
+ u32 interface_num,
+ enum hws_access_type pup_access_type,
+ u32 pup_num, enum hws_training_result result_type,
+ enum hws_control_element control_element,
+ enum hws_search_dir search_dir, enum hws_dir direction,
+ u32 interface_mask, u32 init_value, u32 num_iter,
+ enum hws_pattern pattern,
+ enum hws_edge_compare edge_comp,
+ enum hws_ddr_cs cs_type, u32 cs_num,
+ enum hws_training_ip_stat *train_status)
+{
+ u32 mask_dq_num_of_regs, mask_pup_num_of_regs, index_cnt, poll_cnt,
+ reg_data, pup_id;
+ u32 tx_burst_size;
+ u32 delay_between_burst;
+ u32 rd_mode;
+ u32 read_data[MAX_INTERFACE_NUM];
+ struct pattern_info *pattern_table = ddr3_tip_get_pattern_table();
+ u16 *mask_results_pup_reg_map = ddr3_tip_get_mask_results_pup_reg_map();
+ u16 *mask_results_dq_reg_map = ddr3_tip_get_mask_results_dq_reg();
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ if (pup_num >= tm->num_of_bus_per_interface) {
+ DEBUG_TRAINING_IP_ENGINE(DEBUG_LEVEL_ERROR,
+ ("pup_num %d not valid\n", pup_num));
+ }
+ if (interface_num >= MAX_INTERFACE_NUM) {
+ DEBUG_TRAINING_IP_ENGINE(DEBUG_LEVEL_ERROR,
+ ("if_id %d not valid\n",
+ interface_num));
+ }
+ if (train_status == NULL) {
+ DEBUG_TRAINING_IP_ENGINE(DEBUG_LEVEL_ERROR,
+ ("error param 4\n"));
+ return MV_BAD_PARAM;
+ }
+
+ /* load pattern */
+ if (cs_type == CS_SINGLE) {
+ /* All CSs to CS0 */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, interface_num,
+ CS_ENABLE_REG, 1 << 3, 1 << 3));
+ /* All CSs to CS0 */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, interface_num,
+ ODPG_DATA_CONTROL_REG,
+ (0x3 | (effective_cs << 26)), 0xc000003));
+ } else {
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, interface_num,
+ CS_ENABLE_REG, 0, 1 << 3));
+ /* CS select */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, interface_num,
+ ODPG_DATA_CONTROL_REG, 0x3 | cs_num << 26,
+ 0x3 | 3 << 26));
+ }
+
+ /* load pattern to ODPG */
+ ddr3_tip_load_pattern_to_odpg(dev_num, access_type, interface_num,
+ pattern,
+ pattern_table[pattern].start_addr);
+ tx_burst_size = (direction == OPER_WRITE) ?
+ pattern_table[pattern].tx_burst_size : 0;
+ delay_between_burst = (direction == OPER_WRITE) ? 2 : 0;
+ rd_mode = (direction == OPER_WRITE) ? 1 : 0;
+ CHECK_STATUS(ddr3_tip_configure_odpg
+ (dev_num, access_type, interface_num, direction,
+ pattern_table[pattern].num_of_phases_tx, tx_burst_size,
+ pattern_table[pattern].num_of_phases_rx,
+ delay_between_burst, rd_mode, effective_cs, STRESS_NONE,
+ DURATION_SINGLE));
+ reg_data = (direction == OPER_READ) ? 0 : (0x3 << 30);
+ reg_data |= (direction == OPER_READ) ? 0x60 : 0xfa;
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, interface_num,
+ ODPG_WRITE_READ_MODE_ENABLE_REG, reg_data,
+ MASK_ALL_BITS));
+ reg_data = (edge_comp == EDGE_PF || edge_comp == EDGE_FP) ? 0 : 1 << 6;
+ reg_data |= (edge_comp == EDGE_PF || edge_comp == EDGE_PFP) ?
+ (1 << 7) : 0;
+
+ /* change from Pass to Fail will lock the result */
+ if (pup_access_type == ACCESS_TYPE_MULTICAST)
+ reg_data |= 0xe << 14;
+ else
+ reg_data |= pup_num << 14;
+
+ if (edge_comp == EDGE_FP) {
+ /* don't search for readl edge change, only the state */
+ reg_data |= (0 << 20);
+ } else if (edge_comp == EDGE_FPF) {
+ reg_data |= (0 << 20);
+ } else {
+ reg_data |= (3 << 20);
+ }
+
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, interface_num,
+ ODPG_TRAINING_CONTROL_REG,
+ reg_data | (0x7 << 8) | (0x7 << 11),
+ (0x3 | (0x3 << 2) | (0x3 << 6) | (1 << 5) | (0x7 << 8) |
+ (0x7 << 11) | (0xf << 14) | (0x3 << 18) | (3 << 20))));
+ reg_data = (search_dir == HWS_LOW2HIGH) ? 0 : (1 << 8);
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, interface_num, ODPG_OBJ1_OPCODE_REG,
+ 1 | reg_data | init_value << 9 | (1 << 25) | (1 << 26),
+ 0xff | (1 << 8) | (0xffff << 9) | (1 << 25) | (1 << 26)));
+
+ /*
+ * Write2_dunit(0x10b4, Number_iteration , [15:0])
+ * Max number of iterations
+ */
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, interface_num,
+ ODPG_OBJ1_ITER_CNT_REG, num_iter,
+ 0xffff));
+ if (control_element == HWS_CONTROL_ELEMENT_DQ_SKEW &&
+ direction == OPER_READ) {
+ /*
+ * Write2_dunit(0x10c0, 0x5f , [7:0])
+ * MC PBS Reg Address at DDR PHY
+ */
+ reg_data = 0x5f +
+ effective_cs * CALIBRATED_OBJECTS_REG_ADDR_OFFSET;
+ } else if (control_element == HWS_CONTROL_ELEMENT_DQ_SKEW &&
+ direction == OPER_WRITE) {
+ reg_data = 0x1f +
+ effective_cs * CALIBRATED_OBJECTS_REG_ADDR_OFFSET;
+ } else if (control_element == HWS_CONTROL_ELEMENT_ADLL &&
+ direction == OPER_WRITE) {
+ /*
+ * LOOP 0x00000001 + 4*n:
+ * where n (0-3) represents M_CS number
+ */
+ /*
+ * Write2_dunit(0x10c0, 0x1 , [7:0])
+ * ADLL WR Reg Address at DDR PHY
+ */
+ reg_data = 1 + effective_cs * CS_REGISTER_ADDR_OFFSET;
+ } else if (control_element == HWS_CONTROL_ELEMENT_ADLL &&
+ direction == OPER_READ) {
+ /* ADLL RD Reg Address at DDR PHY */
+ reg_data = 3 + effective_cs * CS_REGISTER_ADDR_OFFSET;
+ } else if (control_element == HWS_CONTROL_ELEMENT_DQS_SKEW &&
+ direction == OPER_WRITE) {
+ /* TBD not defined in 0.5.0 requirement */
+ } else if (control_element == HWS_CONTROL_ELEMENT_DQS_SKEW &&
+ direction == OPER_READ) {
+ /* TBD not defined in 0.5.0 requirement */
+ }
+
+ reg_data |= (0x6 << 28);
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, interface_num, CALIB_OBJ_PRFA_REG,
+ reg_data | (init_value << 8),
+ 0xff | (0xffff << 8) | (0xf << 24) | (u32) (0xf << 28)));
+
+ mask_dq_num_of_regs = tm->num_of_bus_per_interface * BUS_WIDTH_IN_BITS;
+ mask_pup_num_of_regs = tm->num_of_bus_per_interface;
+
+ if (result_type == RESULT_PER_BIT) {
+ for (index_cnt = 0; index_cnt < mask_dq_num_of_regs;
+ index_cnt++) {
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, interface_num,
+ mask_results_dq_reg_map[index_cnt], 0,
+ 1 << 24));
+ }
+
+ /* Mask disabled buses */
+ for (pup_id = 0; pup_id < tm->num_of_bus_per_interface;
+ pup_id++) {
+ if (IS_ACTIVE(tm->bus_act_mask, pup_id) == 1)
+ continue;
+
+ for (index_cnt = (mask_dq_num_of_regs - pup_id * 8);
+ index_cnt <
+ (mask_dq_num_of_regs - (pup_id + 1) * 8);
+ index_cnt++) {
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type,
+ interface_num,
+ mask_results_dq_reg_map
+ [index_cnt], (1 << 24), 1 << 24));
+ }
+ }
+
+ for (index_cnt = 0; index_cnt < mask_pup_num_of_regs;
+ index_cnt++) {
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, interface_num,
+ mask_results_pup_reg_map[index_cnt],
+ (1 << 24), 1 << 24));
+ }
+ } else if (result_type == RESULT_PER_BYTE) {
+ /* write to adll */
+ for (index_cnt = 0; index_cnt < mask_pup_num_of_regs;
+ index_cnt++) {
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, interface_num,
+ mask_results_pup_reg_map[index_cnt], 0,
+ 1 << 24));
+ }
+ for (index_cnt = 0; index_cnt < mask_dq_num_of_regs;
+ index_cnt++) {
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, interface_num,
+ mask_results_dq_reg_map[index_cnt],
+ (1 << 24), (1 << 24)));
+ }
+ }
+
+ /* Start Training Trigger */
+ CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, interface_num,
+ ODPG_TRAINING_TRIGGER_REG, 1, 1));
+ /* wait for all RFU tests to finish (or timeout) */
+ /* WA for 16 bit mode, more investigation needed */
+ mdelay(1);
+
+ /* Training "Done ?" */
+ for (index_cnt = 0; index_cnt < MAX_INTERFACE_NUM; index_cnt++) {
+ if (IS_ACTIVE(tm->if_act_mask, index_cnt) == 0)
+ continue;
+
+ if (interface_mask & (1 << index_cnt)) {
+ /* need to check results for this Dunit */
+ for (poll_cnt = 0; poll_cnt < max_polling_for_done;
+ poll_cnt++) {
+ CHECK_STATUS(ddr3_tip_if_read
+ (dev_num, ACCESS_TYPE_UNICAST,
+ index_cnt,
+ ODPG_TRAINING_STATUS_REG,
+ ®_data, MASK_ALL_BITS));
+ if ((reg_data & 0x2) != 0) {
+ /*done */
+ train_status[index_cnt] =
+ HWS_TRAINING_IP_STATUS_SUCCESS;
+ break;
+ }
+ }
+
+ if (poll_cnt == max_polling_for_done) {
+ train_status[index_cnt] =
+ HWS_TRAINING_IP_STATUS_TIMEOUT;
+ }
+ }
+ /* Be sure that ODPG done */
+ CHECK_STATUS(is_odpg_access_done(dev_num, index_cnt));
+ }
+
+ /* Write ODPG done in Dunit */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ODPG_STATUS_DONE_REG, 0, 0x1));
+
+ /* wait for all Dunit tests to finish (or timeout) */
+ /* Training "Done ?" */
+ /* Training "Pass ?" */
+ for (index_cnt = 0; index_cnt < MAX_INTERFACE_NUM; index_cnt++) {
+ if (IS_ACTIVE(tm->if_act_mask, index_cnt) == 0)
+ continue;
+
+ if (interface_mask & (1 << index_cnt)) {
+ /* need to check results for this Dunit */
+ for (poll_cnt = 0; poll_cnt < max_polling_for_done;
+ poll_cnt++) {
+ CHECK_STATUS(ddr3_tip_if_read
+ (dev_num, ACCESS_TYPE_UNICAST,
+ index_cnt,
+ ODPG_TRAINING_TRIGGER_REG,
+ read_data, MASK_ALL_BITS));
+ reg_data = read_data[index_cnt];
+ if ((reg_data & 0x2) != 0) {
+ /* done */
+ if ((reg_data & 0x4) == 0) {
+ train_status[index_cnt] =
+ HWS_TRAINING_IP_STATUS_SUCCESS;
+ } else {
+ train_status[index_cnt] =
+ HWS_TRAINING_IP_STATUS_FAIL;
+ }
+ break;
+ }
+ }
+
+ if (poll_cnt == max_polling_for_done) {
+ train_status[index_cnt] =
+ HWS_TRAINING_IP_STATUS_TIMEOUT;
+ }
+ }
+ }
+
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ODPG_DATA_CONTROL_REG, 0, MASK_ALL_BITS));
+
+ return MV_OK;
+}
+
+/*
+ * Load expected Pattern to ODPG
+ */
+int ddr3_tip_load_pattern_to_odpg(u32 dev_num, enum hws_access_type access_type,
+ u32 if_id, enum hws_pattern pattern,
+ u32 load_addr)
+{
+ u32 pattern_length_cnt = 0;
+ struct pattern_info *pattern_table = ddr3_tip_get_pattern_table();
+
+ for (pattern_length_cnt = 0;
+ pattern_length_cnt < pattern_table[pattern].pattern_len;
+ pattern_length_cnt++) {
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ ODPG_PATTERN_DATA_LOW_REG,
+ pattern_table_get_word(dev_num, pattern,
+ (u8) (pattern_length_cnt *
+ 2)), MASK_ALL_BITS));
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ ODPG_PATTERN_DATA_HI_REG,
+ pattern_table_get_word(dev_num, pattern,
+ (u8) (pattern_length_cnt *
+ 2 + 1)),
+ MASK_ALL_BITS));
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ ODPG_PATTERN_ADDR_REG, pattern_length_cnt,
+ MASK_ALL_BITS));
+ }
+
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ ODPG_PATTERN_ADDR_OFFSET_REG, load_addr, MASK_ALL_BITS));
+
+ return MV_OK;
+}
+
+/*
+ * Configure ODPG
+ */
+int ddr3_tip_configure_odpg(u32 dev_num, enum hws_access_type access_type,
+ u32 if_id, enum hws_dir direction, u32 tx_phases,
+ u32 tx_burst_size, u32 rx_phases,
+ u32 delay_between_burst, u32 rd_mode, u32 cs_num,
+ u32 addr_stress_jump, u32 single_pattern)
+{
+ u32 data_value = 0;
+ int ret;
+
+ data_value = ((single_pattern << 2) | (tx_phases << 5) |
+ (tx_burst_size << 11) | (delay_between_burst << 15) |
+ (rx_phases << 21) | (rd_mode << 25) | (cs_num << 26) |
+ (addr_stress_jump << 29));
+ ret = ddr3_tip_if_write(dev_num, access_type, if_id,
+ ODPG_DATA_CONTROL_REG, data_value, 0xaffffffc);
+ if (ret != MV_OK)
+ return ret;
+
+ return MV_OK;
+}
+
+int ddr3_tip_process_result(u32 *ar_result, enum hws_edge e_edge,
+ enum hws_edge_search e_edge_search,
+ u32 *edge_result)
+{
+ u32 i, res;
+ int tap_val, max_val = -10000, min_val = 10000;
+ int lock_success = 1;
+
+ for (i = 0; i < BUS_WIDTH_IN_BITS; i++) {
+ res = GET_LOCK_RESULT(ar_result[i]);
+ if (res == 0) {
+ lock_success = 0;
+ break;
+ }
+ DEBUG_TRAINING_IP_ENGINE(DEBUG_LEVEL_ERROR,
+ ("lock failed for bit %d\n", i));
+ }
+
+ if (lock_success == 1) {
+ for (i = 0; i < BUS_WIDTH_IN_BITS; i++) {
+ tap_val = GET_TAP_RESULT(ar_result[i], e_edge);
+ if (tap_val > max_val)
+ max_val = tap_val;
+ if (tap_val < min_val)
+ min_val = tap_val;
+ if (e_edge_search == TRAINING_EDGE_MAX)
+ *edge_result = (u32) max_val;
+ else
+ *edge_result = (u32) min_val;
+
+ DEBUG_TRAINING_IP_ENGINE(DEBUG_LEVEL_ERROR,
+ ("i %d ar_result[i] 0x%x tap_val %d max_val %d min_val %d Edge_result %d\n",
+ i, ar_result[i], tap_val,
+ max_val, min_val,
+ *edge_result));
+ }
+ } else {
+ return MV_FAIL;
+ }
+
+ return MV_OK;
+}
+
+/*
+ * Read training search result
+ */
+int ddr3_tip_read_training_result(u32 dev_num, u32 if_id,
+ enum hws_access_type pup_access_type,
+ u32 pup_num, u32 bit_num,
+ enum hws_search_dir search,
+ enum hws_dir direction,
+ enum hws_training_result result_type,
+ enum hws_training_load_op operation,
+ u32 cs_num_type, u32 **load_res,
+ int is_read_from_db, u8 cons_tap,
+ int is_check_result_validity)
+{
+ u32 reg_offset, pup_cnt, start_pup, end_pup, start_reg, end_reg;
+ u32 *interface_train_res = NULL;
+ u16 *reg_addr = NULL;
+ u32 read_data[MAX_INTERFACE_NUM];
+ u16 *mask_results_pup_reg_map = ddr3_tip_get_mask_results_pup_reg_map();
+ u16 *mask_results_dq_reg_map = ddr3_tip_get_mask_results_dq_reg();
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ /*
+ * Agreed assumption: all CS mask contain same number of bits,
+ * i.e. in multi CS, the number of CS per memory is the same for
+ * all pups
+ */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id, CS_ENABLE_REG,
+ (cs_num_type == 0) ? 1 << 3 : 0, (1 << 3)));
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ ODPG_DATA_CONTROL_REG, (cs_num_type << 26), (3 << 26)));
+ DEBUG_TRAINING_IP_ENGINE(DEBUG_LEVEL_TRACE,
+ ("Read_from_d_b %d cs_type %d oper %d result_type %d direction %d search %d pup_num %d if_id %d pup_access_type %d\n",
+ is_read_from_db, cs_num_type, operation,
+ result_type, direction, search, pup_num,
+ if_id, pup_access_type));
+
+ if ((load_res == NULL) && (is_read_from_db == 1)) {
+ DEBUG_TRAINING_IP_ENGINE(DEBUG_LEVEL_ERROR,
+ ("ddr3_tip_read_training_result load_res = NULL"));
+ return MV_FAIL;
+ }
+ if (pup_num >= tm->num_of_bus_per_interface) {
+ DEBUG_TRAINING_IP_ENGINE(DEBUG_LEVEL_ERROR,
+ ("pup_num %d not valid\n", pup_num));
+ }
+ if (if_id >= MAX_INTERFACE_NUM) {
+ DEBUG_TRAINING_IP_ENGINE(DEBUG_LEVEL_ERROR,
+ ("if_id %d not valid\n", if_id));
+ }
+ if (result_type == RESULT_PER_BIT)
+ reg_addr = mask_results_dq_reg_map;
+ else
+ reg_addr = mask_results_pup_reg_map;
+ if (pup_access_type == ACCESS_TYPE_UNICAST) {
+ start_pup = pup_num;
+ end_pup = pup_num;
+ } else { /*pup_access_type == ACCESS_TYPE_MULTICAST) */
+
+ start_pup = 0;
+ end_pup = tm->num_of_bus_per_interface - 1;
+ }
+
+ for (pup_cnt = start_pup; pup_cnt <= end_pup; pup_cnt++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, pup_cnt);
+ DEBUG_TRAINING_IP_ENGINE(
+ DEBUG_LEVEL_TRACE,
+ ("if_id %d start_pup %d end_pup %d pup_cnt %d\n",
+ if_id, start_pup, end_pup, pup_cnt));
+ if (result_type == RESULT_PER_BIT) {
+ if (bit_num == ALL_BITS_PER_PUP) {
+ start_reg = pup_cnt * BUS_WIDTH_IN_BITS;
+ end_reg = (pup_cnt + 1) * BUS_WIDTH_IN_BITS - 1;
+ } else {
+ start_reg =
+ pup_cnt * BUS_WIDTH_IN_BITS + bit_num;
+ end_reg = pup_cnt * BUS_WIDTH_IN_BITS + bit_num;
+ }
+ } else {
+ start_reg = pup_cnt;
+ end_reg = pup_cnt;
+ }
+
+ interface_train_res =
+ ddr3_tip_get_buf_ptr(dev_num, search, result_type,
+ if_id);
+ DEBUG_TRAINING_IP_ENGINE(
+ DEBUG_LEVEL_TRACE,
+ ("start_reg %d end_reg %d interface %p\n",
+ start_reg, end_reg, interface_train_res));
+ if (interface_train_res == NULL) {
+ DEBUG_TRAINING_IP_ENGINE(
+ DEBUG_LEVEL_ERROR,
+ ("interface_train_res is NULL\n"));
+ return MV_FAIL;
+ }
+
+ for (reg_offset = start_reg; reg_offset <= end_reg;
+ reg_offset++) {
+ if (operation == TRAINING_LOAD_OPERATION_UNLOAD) {
+ if (is_read_from_db == 0) {
+ CHECK_STATUS(ddr3_tip_if_read
+ (dev_num,
+ ACCESS_TYPE_UNICAST,
+ if_id,
+ reg_addr[reg_offset],
+ read_data,
+ MASK_ALL_BITS));
+ if (is_check_result_validity == 1) {
+ if ((read_data[if_id] &
+ 0x02000000) == 0) {
+ interface_train_res
+ [reg_offset] =
+ 0x02000000 +
+ 64 + cons_tap;
+ } else {
+ interface_train_res
+ [reg_offset] =
+ read_data
+ [if_id] +
+ cons_tap;
+ }
+ } else {
+ interface_train_res[reg_offset]
+ = read_data[if_id] +
+ cons_tap;
+ }
+ DEBUG_TRAINING_IP_ENGINE
+ (DEBUG_LEVEL_TRACE,
+ ("reg_offset %d value 0x%x addr %p\n",
+ reg_offset,
+ interface_train_res
+ [reg_offset],
+ &interface_train_res
+ [reg_offset]));
+ } else {
+ *load_res =
+ &interface_train_res[start_reg];
+ DEBUG_TRAINING_IP_ENGINE
+ (DEBUG_LEVEL_TRACE,
+ ("*load_res %p\n", *load_res));
+ }
+ } else {
+ DEBUG_TRAINING_IP_ENGINE(DEBUG_LEVEL_TRACE,
+ ("not supported\n"));
+ }
+ }
+ }
+
+ return MV_OK;
+}
+
+/*
+ * Load all pattern to memory using ODPG
+ */
+int ddr3_tip_load_all_pattern_to_mem(u32 dev_num)
+{
+ u32 pattern = 0, if_id;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ training_result[training_stage][if_id] = TEST_SUCCESS;
+ }
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ /* enable single cs */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ CS_ENABLE_REG, (1 << 3), (1 << 3)));
+ }
+
+ for (pattern = 0; pattern < PATTERN_LIMIT; pattern++)
+ ddr3_tip_load_pattern_to_mem(dev_num, pattern);
+
+ return MV_OK;
+}
+
+/*
+ * Wait till ODPG access is ready
+ */
+int is_odpg_access_done(u32 dev_num, u32 if_id)
+{
+ u32 poll_cnt = 0, data_value;
+ u32 read_data[MAX_INTERFACE_NUM];
+
+ for (poll_cnt = 0; poll_cnt < MAX_POLLING_ITERATIONS; poll_cnt++) {
+ CHECK_STATUS(ddr3_tip_if_read
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ ODPG_BIST_DONE, read_data, MASK_ALL_BITS));
+ data_value = read_data[if_id];
+ if (((data_value >> ODPG_BIST_DONE_BIT_OFFS) & 0x1) ==
+ ODPG_BIST_DONE_BIT_VALUE) {
+ data_value = data_value & 0xfffffffe;
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_UNICAST,
+ if_id, ODPG_BIST_DONE, data_value,
+ MASK_ALL_BITS));
+ break;
+ }
+ }
+
+ if (poll_cnt >= MAX_POLLING_ITERATIONS) {
+ DEBUG_TRAINING_IP_ENGINE(DEBUG_LEVEL_ERROR,
+ ("Bist Activate: poll failure 2\n"));
+ return MV_FAIL;
+ }
+
+ return MV_OK;
+}
+
+/*
+ * Load specific pattern to memory using ODPG
+ */
+int ddr3_tip_load_pattern_to_mem(u32 dev_num, enum hws_pattern pattern)
+{
+ u32 reg_data, if_id;
+ struct pattern_info *pattern_table = ddr3_tip_get_pattern_table();
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ /* load pattern to memory */
+ /*
+ * Write Tx mode, CS0, phases, Tx burst size, delay between burst,
+ * rx pattern phases
+ */
+ reg_data =
+ 0x1 | (pattern_table[pattern].num_of_phases_tx << 5) |
+ (pattern_table[pattern].tx_burst_size << 11) |
+ (pattern_table[pattern].delay_between_bursts << 15) |
+ (pattern_table[pattern].num_of_phases_rx << 21) | (0x1 << 25) |
+ (effective_cs << 26);
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ODPG_DATA_CONTROL_REG, reg_data, MASK_ALL_BITS));
+ /* ODPG Write enable from BIST */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ODPG_DATA_CONTROL_REG, (0x1 | (effective_cs << 26)),
+ 0xc000003));
+ /* disable error injection */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ODPG_WRITE_DATA_ERROR_REG, 0, 0x1));
+ /* load pattern to ODPG */
+ ddr3_tip_load_pattern_to_odpg(dev_num, ACCESS_TYPE_MULTICAST,
+ PARAM_NOT_CARE, pattern,
+ pattern_table[pattern].start_addr);
+
+ for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
+ if (IS_ACTIVE(tm->if_act_mask, if_id) == 0)
+ continue;
+
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x1498,
+ 0x3, 0xf));
+ }
+
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ODPG_ENABLE_REG, 0x1 << ODPG_ENABLE_OFFS,
+ (0x1 << ODPG_ENABLE_OFFS)));
+
+ mdelay(1);
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ CHECK_STATUS(is_odpg_access_done(dev_num, if_id));
+ }
+
+ /* Disable ODPG and stop write to memory */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ODPG_DATA_CONTROL_REG, (0x1 << 30), (u32) (0x3 << 30)));
+
+ /* return to default */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ODPG_DATA_CONTROL_REG, 0, MASK_ALL_BITS));
+
+ /* Disable odt0 for CS0 training - need to adjust for multy CS */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, 0x1498,
+ 0x0, 0xf));
+
+ /* temporary added */
+ mdelay(1);
+
+ return MV_OK;
+}
+
+/*
+ * Load specific pattern to memory using CPU
+ */
+int ddr3_tip_load_pattern_to_mem_by_cpu(u32 dev_num, enum hws_pattern pattern,
+ u32 offset)
+{
+ /* eranba - TBD */
+ return MV_OK;
+}
+
+/*
+ * Training search routine
+ */
+int ddr3_tip_ip_training_wrapper_int(u32 dev_num,
+ enum hws_access_type access_type,
+ u32 if_id,
+ enum hws_access_type pup_access_type,
+ u32 pup_num, u32 bit_num,
+ enum hws_training_result result_type,
+ enum hws_control_element control_element,
+ enum hws_search_dir search_dir,
+ enum hws_dir direction,
+ u32 interface_mask, u32 init_value_l2h,
+ u32 init_value_h2l, u32 num_iter,
+ enum hws_pattern pattern,
+ enum hws_edge_compare edge_comp,
+ enum hws_ddr_cs train_cs_type, u32 cs_num,
+ enum hws_training_ip_stat *train_status)
+{
+ u32 interface_num = 0, start_if, end_if, init_value_used;
+ enum hws_search_dir search_dir_id, start_search, end_search;
+ enum hws_edge_compare edge_comp_used;
+ u8 cons_tap = (direction == OPER_WRITE) ? (64) : (0);
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ if (train_status == NULL) {
+ DEBUG_TRAINING_IP_ENGINE(DEBUG_LEVEL_ERROR,
+ ("train_status is NULL\n"));
+ return MV_FAIL;
+ }
+
+ if ((train_cs_type > CS_NON_SINGLE) ||
+ (edge_comp >= EDGE_PFP) ||
+ (pattern >= PATTERN_LIMIT) ||
+ (direction > OPER_WRITE_AND_READ) ||
+ (search_dir > HWS_HIGH2LOW) ||
+ (control_element > HWS_CONTROL_ELEMENT_DQS_SKEW) ||
+ (result_type > RESULT_PER_BYTE) ||
+ (pup_num >= tm->num_of_bus_per_interface) ||
+ (pup_access_type > ACCESS_TYPE_MULTICAST) ||
+ (if_id > 11) || (access_type > ACCESS_TYPE_MULTICAST)) {
+ DEBUG_TRAINING_IP_ENGINE(
+ DEBUG_LEVEL_ERROR,
+ ("wrong parameter train_cs_type %d edge_comp %d pattern %d direction %d search_dir %d control_element %d result_type %d pup_num %d pup_access_type %d if_id %d access_type %d\n",
+ train_cs_type, edge_comp, pattern, direction,
+ search_dir, control_element, result_type, pup_num,
+ pup_access_type, if_id, access_type));
+ return MV_FAIL;
+ }
+
+ if (edge_comp == EDGE_FPF) {
+ start_search = HWS_LOW2HIGH;
+ end_search = HWS_HIGH2LOW;
+ edge_comp_used = EDGE_FP;
+ } else {
+ start_search = search_dir;
+ end_search = search_dir;
+ edge_comp_used = edge_comp;
+ }
+
+ for (search_dir_id = start_search; search_dir_id <= end_search;
+ search_dir_id++) {
+ init_value_used = (search_dir_id == HWS_LOW2HIGH) ?
+ init_value_l2h : init_value_h2l;
+ DEBUG_TRAINING_IP_ENGINE(
+ DEBUG_LEVEL_TRACE,
+ ("dev_num %d, access_type %d, if_id %d, pup_access_type %d,pup_num %d, result_type %d, control_element %d search_dir_id %d, direction %d, interface_mask %d,init_value_used %d, num_iter %d, pattern %d, edge_comp_used %d, train_cs_type %d, cs_num %d\n",
+ dev_num, access_type, if_id, pup_access_type, pup_num,
+ result_type, control_element, search_dir_id,
+ direction, interface_mask, init_value_used, num_iter,
+ pattern, edge_comp_used, train_cs_type, cs_num));
+
+ ddr3_tip_ip_training(dev_num, access_type, if_id,
+ pup_access_type, pup_num, result_type,
+ control_element, search_dir_id, direction,
+ interface_mask, init_value_used, num_iter,
+ pattern, edge_comp_used, train_cs_type,
+ cs_num, train_status);
+ if (access_type == ACCESS_TYPE_MULTICAST) {
+ start_if = 0;
+ end_if = MAX_INTERFACE_NUM - 1;
+ } else {
+ start_if = if_id;
+ end_if = if_id;
+ }
+
+ for (interface_num = start_if; interface_num <= end_if;
+ interface_num++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, interface_num);
+ cs_num = 0;
+ CHECK_STATUS(ddr3_tip_read_training_result
+ (dev_num, interface_num, pup_access_type,
+ pup_num, bit_num, search_dir_id,
+ direction, result_type,
+ TRAINING_LOAD_OPERATION_UNLOAD,
+ train_cs_type, NULL, 0, cons_tap,
+ 0));
+ }
+ }
+
+ return MV_OK;
+}
+
+/*
+ * Training search & read result routine
+ */
+int ddr3_tip_ip_training_wrapper(u32 dev_num, enum hws_access_type access_type,
+ u32 if_id,
+ enum hws_access_type pup_access_type,
+ u32 pup_num,
+ enum hws_training_result result_type,
+ enum hws_control_element control_element,
+ enum hws_search_dir search_dir,
+ enum hws_dir direction, u32 interface_mask,
+ u32 init_value_l2h, u32 init_value_h2l,
+ u32 num_iter, enum hws_pattern pattern,
+ enum hws_edge_compare edge_comp,
+ enum hws_ddr_cs train_cs_type, u32 cs_num,
+ enum hws_training_ip_stat *train_status)
+{
+ u8 e1, e2;
+ u32 interface_cnt, bit_id, start_if, end_if, bit_end = 0;
+ u32 *result[HWS_SEARCH_DIR_LIMIT] = { 0 };
+ u8 cons_tap = (direction == OPER_WRITE) ? (64) : (0);
+ u8 bit_bit_mask[MAX_BUS_NUM] = { 0 }, bit_bit_mask_active = 0;
+ u8 pup_id;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ if (pup_num >= tm->num_of_bus_per_interface) {
+ DEBUG_TRAINING_IP_ENGINE(DEBUG_LEVEL_ERROR,
+ ("pup_num %d not valid\n", pup_num));
+ }
+
+ if (if_id >= MAX_INTERFACE_NUM) {
+ DEBUG_TRAINING_IP_ENGINE(DEBUG_LEVEL_ERROR,
+ ("if_id %d not valid\n", if_id));
+ }
+
+ CHECK_STATUS(ddr3_tip_ip_training_wrapper_int
+ (dev_num, access_type, if_id, pup_access_type, pup_num,
+ ALL_BITS_PER_PUP, result_type, control_element,
+ search_dir, direction, interface_mask, init_value_l2h,
+ init_value_h2l, num_iter, pattern, edge_comp,
+ train_cs_type, cs_num, train_status));
+
+ if (access_type == ACCESS_TYPE_MULTICAST) {
+ start_if = 0;
+ end_if = MAX_INTERFACE_NUM - 1;
+ } else {
+ start_if = if_id;
+ end_if = if_id;
+ }
+
+ for (interface_cnt = start_if; interface_cnt <= end_if;
+ interface_cnt++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, interface_cnt);
+ for (pup_id = 0;
+ pup_id <= (tm->num_of_bus_per_interface - 1); pup_id++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, pup_id);
+ if (result_type == RESULT_PER_BIT)
+ bit_end = BUS_WIDTH_IN_BITS - 1;
+ else
+ bit_end = 0;
+
+ bit_bit_mask[pup_id] = 0;
+ for (bit_id = 0; bit_id <= bit_end; bit_id++) {
+ enum hws_search_dir search_dir_id;
+ for (search_dir_id = HWS_LOW2HIGH;
+ search_dir_id <= HWS_HIGH2LOW;
+ search_dir_id++) {
+ CHECK_STATUS
+ (ddr3_tip_read_training_result
+ (dev_num, interface_cnt,
+ ACCESS_TYPE_UNICAST, pup_id,
+ bit_id, search_dir_id,
+ direction, result_type,
+ TRAINING_LOAD_OPERATION_UNLOAD,
+ CS_SINGLE,
+ &result[search_dir_id],
+ 1, 0, 0));
+ }
+ e1 = GET_TAP_RESULT(result[HWS_LOW2HIGH][0],
+ EDGE_1);
+ e2 = GET_TAP_RESULT(result[HWS_HIGH2LOW][0],
+ EDGE_1);
+ DEBUG_TRAINING_IP_ENGINE(
+ DEBUG_LEVEL_INFO,
+ ("wrapper if_id %d pup_id %d bit %d l2h 0x%x (e1 0x%x) h2l 0x%x (e2 0x%x)\n",
+ interface_cnt, pup_id, bit_id,
+ result[HWS_LOW2HIGH][0], e1,
+ result[HWS_HIGH2LOW][0], e2));
+ /* TBD validate is valid only for tx */
+ if (VALIDATE_TRAINING_LIMIT(e1, e2) == 1 &&
+ GET_LOCK_RESULT(result[HWS_LOW2HIGH][0]) &&
+ GET_LOCK_RESULT(result[HWS_LOW2HIGH][0])) {
+ /* Mark problem bits */
+ bit_bit_mask[pup_id] |= 1 << bit_id;
+ bit_bit_mask_active = 1;
+ }
+ } /* For all bits */
+ } /* For all PUPs */
+
+ /* Fix problem bits */
+ if (bit_bit_mask_active != 0) {
+ u32 *l2h_if_train_res = NULL;
+ u32 *h2l_if_train_res = NULL;
+ l2h_if_train_res =
+ ddr3_tip_get_buf_ptr(dev_num, HWS_LOW2HIGH,
+ result_type,
+ interface_cnt);
+ h2l_if_train_res =
+ ddr3_tip_get_buf_ptr(dev_num, HWS_HIGH2LOW,
+ result_type,
+ interface_cnt);
+
+ ddr3_tip_ip_training(dev_num, ACCESS_TYPE_UNICAST,
+ interface_cnt,
+ ACCESS_TYPE_MULTICAST,
+ PARAM_NOT_CARE, result_type,
+ control_element, HWS_LOW2HIGH,
+ direction, interface_mask,
+ num_iter / 2, num_iter / 2,
+ pattern, EDGE_FP, train_cs_type,
+ cs_num, train_status);
+
+ for (pup_id = 0;
+ pup_id <= (tm->num_of_bus_per_interface - 1);
+ pup_id++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, pup_id);
+
+ if (bit_bit_mask[pup_id] == 0)
+ continue;
+
+ for (bit_id = 0; bit_id <= bit_end; bit_id++) {
+ if ((bit_bit_mask[pup_id] &
+ (1 << bit_id)) == 0)
+ continue;
+ CHECK_STATUS
+ (ddr3_tip_read_training_result
+ (dev_num, interface_cnt,
+ ACCESS_TYPE_UNICAST, pup_id,
+ bit_id, HWS_LOW2HIGH,
+ direction,
+ result_type,
+ TRAINING_LOAD_OPERATION_UNLOAD,
+ CS_SINGLE, &l2h_if_train_res,
+ 0, 0, 1));
+ }
+ }
+
+ ddr3_tip_ip_training(dev_num, ACCESS_TYPE_UNICAST,
+ interface_cnt,
+ ACCESS_TYPE_MULTICAST,
+ PARAM_NOT_CARE, result_type,
+ control_element, HWS_HIGH2LOW,
+ direction, interface_mask,
+ num_iter / 2, num_iter / 2,
+ pattern, EDGE_FP, train_cs_type,
+ cs_num, train_status);
+
+ for (pup_id = 0;
+ pup_id <= (tm->num_of_bus_per_interface - 1);
+ pup_id++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, pup_id);
+
+ if (bit_bit_mask[pup_id] == 0)
+ continue;
+
+ for (bit_id = 0; bit_id <= bit_end; bit_id++) {
+ if ((bit_bit_mask[pup_id] &
+ (1 << bit_id)) == 0)
+ continue;
+ CHECK_STATUS
+ (ddr3_tip_read_training_result
+ (dev_num, interface_cnt,
+ ACCESS_TYPE_UNICAST, pup_id,
+ bit_id, HWS_HIGH2LOW, direction,
+ result_type,
+ TRAINING_LOAD_OPERATION_UNLOAD,
+ CS_SINGLE, &h2l_if_train_res,
+ 0, cons_tap, 1));
+ }
+ }
+ } /* if bit_bit_mask_active */
+ } /* For all Interfacess */
+
+ return MV_OK;
+}
+
+/*
+ * Load phy values
+ */
+int ddr3_tip_load_phy_values(int b_load)
+{
+ u32 bus_cnt = 0, if_id, dev_num = 0;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ for (bus_cnt = 0; bus_cnt < GET_TOPOLOGY_NUM_OF_BUSES();
+ bus_cnt++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, bus_cnt);
+ if (b_load == 1) {
+ CHECK_STATUS(ddr3_tip_bus_read
+ (dev_num, if_id,
+ ACCESS_TYPE_UNICAST, bus_cnt,
+ DDR_PHY_DATA,
+ WRITE_CENTRALIZATION_PHY_REG +
+ (effective_cs *
+ CS_REGISTER_ADDR_OFFSET),
+ &phy_reg_bk[if_id][bus_cnt]
+ [0]));
+ CHECK_STATUS(ddr3_tip_bus_read
+ (dev_num, if_id,
+ ACCESS_TYPE_UNICAST, bus_cnt,
+ DDR_PHY_DATA,
+ RL_PHY_REG +
+ (effective_cs *
+ CS_REGISTER_ADDR_OFFSET),
+ &phy_reg_bk[if_id][bus_cnt]
+ [1]));
+ CHECK_STATUS(ddr3_tip_bus_read
+ (dev_num, if_id,
+ ACCESS_TYPE_UNICAST, bus_cnt,
+ DDR_PHY_DATA,
+ READ_CENTRALIZATION_PHY_REG +
+ (effective_cs *
+ CS_REGISTER_ADDR_OFFSET),
+ &phy_reg_bk[if_id][bus_cnt]
+ [2]));
+ } else {
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_UNICAST,
+ if_id, ACCESS_TYPE_UNICAST,
+ bus_cnt, DDR_PHY_DATA,
+ WRITE_CENTRALIZATION_PHY_REG +
+ (effective_cs *
+ CS_REGISTER_ADDR_OFFSET),
+ phy_reg_bk[if_id][bus_cnt]
+ [0]));
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_UNICAST,
+ if_id, ACCESS_TYPE_UNICAST,
+ bus_cnt, DDR_PHY_DATA,
+ RL_PHY_REG +
+ (effective_cs *
+ CS_REGISTER_ADDR_OFFSET),
+ phy_reg_bk[if_id][bus_cnt]
+ [1]));
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_UNICAST,
+ if_id, ACCESS_TYPE_UNICAST,
+ bus_cnt, DDR_PHY_DATA,
+ READ_CENTRALIZATION_PHY_REG +
+ (effective_cs *
+ CS_REGISTER_ADDR_OFFSET),
+ phy_reg_bk[if_id][bus_cnt]
+ [2]));
+ }
+ }
+ }
+
+ return MV_OK;
+}
+
+int ddr3_tip_training_ip_test(u32 dev_num, enum hws_training_result result_type,
+ enum hws_search_dir search_dir,
+ enum hws_dir direction,
+ enum hws_edge_compare edge,
+ u32 init_val1, u32 init_val2,
+ u32 num_of_iterations,
+ u32 start_pattern, u32 end_pattern)
+{
+ u32 pattern, if_id, pup_id;
+ enum hws_training_ip_stat train_status[MAX_INTERFACE_NUM];
+ u32 *res = NULL;
+ u32 search_state = 0;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ ddr3_tip_load_phy_values(1);
+
+ for (pattern = start_pattern; pattern <= end_pattern; pattern++) {
+ for (search_state = 0; search_state < HWS_SEARCH_DIR_LIMIT;
+ search_state++) {
+ ddr3_tip_ip_training_wrapper(dev_num,
+ ACCESS_TYPE_MULTICAST, 0,
+ ACCESS_TYPE_MULTICAST, 0,
+ result_type,
+ HWS_CONTROL_ELEMENT_ADLL,
+ search_dir, direction,
+ 0xfff, init_val1,
+ init_val2,
+ num_of_iterations, pattern,
+ edge, CS_SINGLE,
+ PARAM_NOT_CARE,
+ train_status);
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1;
+ if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ for (pup_id = 0; pup_id <
+ tm->num_of_bus_per_interface;
+ pup_id++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask,
+ pup_id);
+ CHECK_STATUS
+ (ddr3_tip_read_training_result
+ (dev_num, if_id,
+ ACCESS_TYPE_UNICAST, pup_id,
+ ALL_BITS_PER_PUP,
+ search_state,
+ direction, result_type,
+ TRAINING_LOAD_OPERATION_UNLOAD,
+ CS_SINGLE, &res, 1, 0,
+ 0));
+ if (result_type == RESULT_PER_BYTE) {
+ DEBUG_TRAINING_IP_ENGINE
+ (DEBUG_LEVEL_INFO,
+ ("search_state %d if_id %d pup_id %d 0x%x\n",
+ search_state, if_id,
+ pup_id, res[0]));
+ } else {
+ DEBUG_TRAINING_IP_ENGINE
+ (DEBUG_LEVEL_INFO,
+ ("search_state %d if_id %d pup_id %d 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
+ search_state, if_id,
+ pup_id, res[0],
+ res[1], res[2],
+ res[3], res[4],
+ res[5], res[6],
+ res[7]));
+ }
+ }
+ } /* interface */
+ } /* search */
+ } /* pattern */
+
+ ddr3_tip_load_phy_values(0);
+
+ return MV_OK;
+}
+
+struct pattern_info *ddr3_tip_get_pattern_table()
+{
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ if (DDR3_IS_16BIT_DRAM_MODE(tm->bus_act_mask) == 0)
+ return pattern_table_32;
+ else
+ return pattern_table_16;
+}
+
+u16 *ddr3_tip_get_mask_results_dq_reg()
+{
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ if (DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask))
+ return mask_results_dq_reg_map_pup3_ecc;
+ else
+ return mask_results_dq_reg_map;
+}
+
+u16 *ddr3_tip_get_mask_results_pup_reg_map()
+{
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ if (DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask))
+ return mask_results_pup_reg_map_pup3_ecc;
+ else
+ return mask_results_pup_reg_map;
+}
diff --git a/drivers/ddr/marvell/a38x/old/ddr3_training_ip_engine.h b/drivers/ddr/marvell/a38x/old/ddr3_training_ip_engine.h
new file mode 100644
index 0000000..25b1462
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/ddr3_training_ip_engine.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _DDR3_TRAINING_IP_ENGINE_H_
+#define _DDR3_TRAINING_IP_ENGINE_H_
+
+#include "ddr3_training_ip_def.h"
+#include "ddr3_training_ip_flow.h"
+
+#define EDGE_1 0
+#define EDGE_2 1
+#define ALL_PUP_TRAINING 0xe
+#define PUP_RESULT_EDGE_1_MASK 0xff
+#define PUP_RESULT_EDGE_2_MASK (0xff << 8)
+#define PUP_LOCK_RESULT_BIT 25
+
+#define GET_TAP_RESULT(reg, edge) \
+ (((edge) == EDGE_1) ? ((reg) & PUP_RESULT_EDGE_1_MASK) : \
+ (((reg) & PUP_RESULT_EDGE_2_MASK) >> 8));
+#define GET_LOCK_RESULT(reg) \
+ (((reg) & (1<<PUP_LOCK_RESULT_BIT)) >> PUP_LOCK_RESULT_BIT)
+
+#define EDGE_FAILURE 128
+#define ALL_BITS_PER_PUP 128
+
+#define MIN_WINDOW_SIZE 6
+#define MAX_WINDOW_SIZE_RX 32
+#define MAX_WINDOW_SIZE_TX 64
+
+int ddr3_tip_training_ip_test(u32 dev_num, enum hws_training_result result_type,
+ enum hws_search_dir search_dir,
+ enum hws_dir direction,
+ enum hws_edge_compare edge,
+ u32 init_val1, u32 init_val2,
+ u32 num_of_iterations, u32 start_pattern,
+ u32 end_pattern);
+int ddr3_tip_load_pattern_to_mem(u32 dev_num, enum hws_pattern pattern);
+int ddr3_tip_load_pattern_to_mem_by_cpu(u32 dev_num, enum hws_pattern pattern,
+ u32 offset);
+int ddr3_tip_load_all_pattern_to_mem(u32 dev_num);
+int ddr3_tip_read_training_result(u32 dev_num, u32 if_id,
+ enum hws_access_type pup_access_type,
+ u32 pup_num, u32 bit_num,
+ enum hws_search_dir search,
+ enum hws_dir direction,
+ enum hws_training_result result_type,
+ enum hws_training_load_op operation,
+ u32 cs_num_type, u32 **load_res,
+ int is_read_from_db, u8 cons_tap,
+ int is_check_result_validity);
+int ddr3_tip_ip_training(u32 dev_num, enum hws_access_type access_type,
+ u32 interface_num,
+ enum hws_access_type pup_access_type,
+ u32 pup_num, enum hws_training_result result_type,
+ enum hws_control_element control_element,
+ enum hws_search_dir search_dir, enum hws_dir direction,
+ u32 interface_mask, u32 init_value, u32 num_iter,
+ enum hws_pattern pattern,
+ enum hws_edge_compare edge_comp,
+ enum hws_ddr_cs cs_type, u32 cs_num,
+ enum hws_training_ip_stat *train_status);
+int ddr3_tip_ip_training_wrapper(u32 dev_num, enum hws_access_type access_type,
+ u32 if_id,
+ enum hws_access_type pup_access_type,
+ u32 pup_num,
+ enum hws_training_result result_type,
+ enum hws_control_element control_element,
+ enum hws_search_dir search_dir,
+ enum hws_dir direction,
+ u32 interface_mask, u32 init_value1,
+ u32 init_value2, u32 num_iter,
+ enum hws_pattern pattern,
+ enum hws_edge_compare edge_comp,
+ enum hws_ddr_cs train_cs_type, u32 cs_num,
+ enum hws_training_ip_stat *train_status);
+int is_odpg_access_done(u32 dev_num, u32 if_id);
+void ddr3_tip_print_bist_res(void);
+struct pattern_info *ddr3_tip_get_pattern_table(void);
+u16 *ddr3_tip_get_mask_results_dq_reg(void);
+u16 *ddr3_tip_get_mask_results_pup_reg_map(void);
+
+#endif /* _DDR3_TRAINING_IP_ENGINE_H_ */
diff --git a/drivers/ddr/marvell/a38x/old/ddr3_training_ip_flow.h b/drivers/ddr/marvell/a38x/old/ddr3_training_ip_flow.h
new file mode 100644
index 0000000..22d7ce2
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/ddr3_training_ip_flow.h
@@ -0,0 +1,349 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _DDR3_TRAINING_IP_FLOW_H_
+#define _DDR3_TRAINING_IP_FLOW_H_
+
+#include "ddr3_training_ip.h"
+#include "ddr3_training_ip_pbs.h"
+
+#define MRS0_CMD 0x3
+#define MRS1_CMD 0x4
+#define MRS2_CMD 0x8
+#define MRS3_CMD 0x9
+
+/*
+ * Definitions of INTERFACE registers
+ */
+
+#define READ_BUFFER_SELECT 0x14a4
+
+/*
+ * Definitions of PHY registers
+ */
+
+#define KILLER_PATTERN_LENGTH 32
+#define EXT_ACCESS_BURST_LENGTH 8
+
+#define IS_ACTIVE(if_mask , if_id) \
+ ((if_mask) & (1 << (if_id)))
+#define VALIDATE_ACTIVE(mask, id) \
+ { \
+ if (IS_ACTIVE(mask, id) == 0) \
+ continue; \
+ }
+
+#define GET_TOPOLOGY_NUM_OF_BUSES() \
+ (ddr3_get_topology_map()->num_of_bus_per_interface)
+
+#define DDR3_IS_ECC_PUP3_MODE(if_mask) \
+ (((if_mask) == 0xb) ? 1 : 0)
+#define DDR3_IS_ECC_PUP4_MODE(if_mask) \
+ (((((if_mask) & 0x10) == 0)) ? 0 : 1)
+#define DDR3_IS_16BIT_DRAM_MODE(mask) \
+ (((((mask) & 0x4) == 0)) ? 1 : 0)
+
+#define MEGA 1000000
+#define BUS_WIDTH_IN_BITS 8
+
+/*
+ * DFX address Space
+ * Table 2: DFX address space
+ * Address Bits Value Description
+ * [31 : 20] 0x? DFX base address bases PCIe mapping
+ * [19 : 15] 0...Number_of_client-1 Client Index inside pipe.
+ * See also Table 1 Multi_cast = 29 Broadcast = 28
+ * [14 : 13] 2'b01 Access to Client Internal Register
+ * [12 : 0] Client Internal Register offset See related Client Registers
+ * [14 : 13] 2'b00 Access to Ram Wrappers Internal Register
+ * [12 : 6] 0 Number_of_rams-1 Ram Index inside Client
+ * [5 : 0] Ram Wrapper Internal Register offset See related Ram Wrappers
+ * Registers
+ */
+
+/* nsec */
+#define TREFI_LOW 7800
+#define TREFI_HIGH 3900
+
+#define TR2R_VALUE_REG 0x180
+#define TR2R_MASK_REG 0x180
+#define TRFC_MASK_REG 0x7f
+#define TR2W_MASK_REG 0x600
+#define TW2W_HIGH_VALUE_REG 0x1800
+#define TW2W_HIGH_MASK_REG 0xf800
+#define TRFC_HIGH_VALUE_REG 0x20000
+#define TRFC_HIGH_MASK_REG 0x70000
+#define TR2R_HIGH_VALUE_REG 0x0
+#define TR2R_HIGH_MASK_REG 0x380000
+#define TMOD_VALUE_REG 0x16000000
+#define TMOD_MASK_REG 0x1e000000
+#define T_VALUE_REG 0x40000000
+#define T_MASK_REG 0xc0000000
+#define AUTO_ZQC_TIMING 15384
+#define WRITE_XBAR_PORT1 0xc03f8077
+#define READ_XBAR_PORT1 0xc03f8073
+#define DISABLE_DDR_TUNING_DATA 0x02294285
+#define ENABLE_DDR_TUNING_DATA 0x12294285
+
+#define ODPG_TRAINING_STATUS_REG 0x18488
+#define ODPG_TRAINING_TRIGGER_REG 0x1030
+#define ODPG_STATUS_DONE_REG 0x16fc
+#define ODPG_ENABLE_REG 0x186d4
+#define ODPG_ENABLE_OFFS 0
+#define ODPG_DISABLE_OFFS 8
+
+#define ODPG_TRAINING_CONTROL_REG 0x1034
+#define ODPG_OBJ1_OPCODE_REG 0x103c
+#define ODPG_OBJ1_ITER_CNT_REG 0x10b4
+#define CALIB_OBJ_PRFA_REG 0x10c4
+#define ODPG_WRITE_LEVELING_DONE_CNTR_REG 0x10f8
+#define ODPG_WRITE_READ_MODE_ENABLE_REG 0x10fc
+#define TRAINING_OPCODE_1_REG 0x10b4
+#define SDRAM_CONFIGURATION_REG 0x1400
+#define DDR_CONTROL_LOW_REG 0x1404
+#define SDRAM_TIMING_LOW_REG 0x1408
+#define SDRAM_TIMING_HIGH_REG 0x140c
+#define SDRAM_ACCESS_CONTROL_REG 0x1410
+#define SDRAM_OPEN_PAGE_CONTROL_REG 0x1414
+#define SDRAM_OPERATION_REG 0x1418
+#define DUNIT_CONTROL_HIGH_REG 0x1424
+#define ODT_TIMING_LOW 0x1428
+#define DDR_TIMING_REG 0x142c
+#define ODT_TIMING_HI_REG 0x147c
+#define SDRAM_INIT_CONTROL_REG 0x1480
+#define SDRAM_ODT_CONTROL_HIGH_REG 0x1498
+#define DUNIT_ODT_CONTROL_REG 0x149c
+#define READ_BUFFER_SELECT_REG 0x14a4
+#define DUNIT_MMASK_REG 0x14b0
+#define CALIB_MACHINE_CTRL_REG 0x14cc
+#define DRAM_DLL_TIMING_REG 0x14e0
+#define DRAM_ZQ_INIT_TIMIMG_REG 0x14e4
+#define DRAM_ZQ_TIMING_REG 0x14e8
+#define DFS_REG 0x1528
+#define READ_DATA_SAMPLE_DELAY 0x1538
+#define READ_DATA_READY_DELAY 0x153c
+#define TRAINING_REG 0x15b0
+#define TRAINING_SW_1_REG 0x15b4
+#define TRAINING_SW_2_REG 0x15b8
+#define TRAINING_PATTERN_BASE_ADDRESS_REG 0x15bc
+#define TRAINING_DBG_1_REG 0x15c0
+#define TRAINING_DBG_2_REG 0x15c4
+#define TRAINING_DBG_3_REG 0x15c8
+#define RANK_CTRL_REG 0x15e0
+#define TIMING_REG 0x15e4
+#define DRAM_PHY_CONFIGURATION 0x15ec
+#define MR0_REG 0x15d0
+#define MR1_REG 0x15d4
+#define MR2_REG 0x15d8
+#define MR3_REG 0x15dc
+#define TIMING_REG 0x15e4
+#define ODPG_CTRL_CONTROL_REG 0x1600
+#define ODPG_DATA_CONTROL_REG 0x1630
+#define ODPG_PATTERN_ADDR_OFFSET_REG 0x1638
+#define ODPG_DATA_BUF_SIZE_REG 0x163c
+#define PHY_LOCK_STATUS_REG 0x1674
+#define PHY_REG_FILE_ACCESS 0x16a0
+#define TRAINING_WRITE_LEVELING_REG 0x16ac
+#define ODPG_PATTERN_ADDR_REG 0x16b0
+#define ODPG_PATTERN_DATA_HI_REG 0x16b4
+#define ODPG_PATTERN_DATA_LOW_REG 0x16b8
+#define ODPG_BIST_LAST_FAIL_ADDR_REG 0x16bc
+#define ODPG_BIST_DATA_ERROR_COUNTER_REG 0x16c0
+#define ODPG_BIST_FAILED_DATA_HI_REG 0x16c4
+#define ODPG_BIST_FAILED_DATA_LOW_REG 0x16c8
+#define ODPG_WRITE_DATA_ERROR_REG 0x16cc
+#define CS_ENABLE_REG 0x16d8
+#define WR_LEVELING_DQS_PATTERN_REG 0x16dc
+
+#define ODPG_BIST_DONE 0x186d4
+#define ODPG_BIST_DONE_BIT_OFFS 0
+#define ODPG_BIST_DONE_BIT_VALUE 0
+
+#define RESULT_CONTROL_BYTE_PUP_0_REG 0x1830
+#define RESULT_CONTROL_BYTE_PUP_1_REG 0x1834
+#define RESULT_CONTROL_BYTE_PUP_2_REG 0x1838
+#define RESULT_CONTROL_BYTE_PUP_3_REG 0x183c
+#define RESULT_CONTROL_BYTE_PUP_4_REG 0x18b0
+
+#define RESULT_CONTROL_PUP_0_BIT_0_REG 0x18b4
+#define RESULT_CONTROL_PUP_0_BIT_1_REG 0x18b8
+#define RESULT_CONTROL_PUP_0_BIT_2_REG 0x18bc
+#define RESULT_CONTROL_PUP_0_BIT_3_REG 0x18c0
+#define RESULT_CONTROL_PUP_0_BIT_4_REG 0x18c4
+#define RESULT_CONTROL_PUP_0_BIT_5_REG 0x18c8
+#define RESULT_CONTROL_PUP_0_BIT_6_REG 0x18cc
+#define RESULT_CONTROL_PUP_0_BIT_7_REG 0x18f0
+#define RESULT_CONTROL_PUP_1_BIT_0_REG 0x18f4
+#define RESULT_CONTROL_PUP_1_BIT_1_REG 0x18f8
+#define RESULT_CONTROL_PUP_1_BIT_2_REG 0x18fc
+#define RESULT_CONTROL_PUP_1_BIT_3_REG 0x1930
+#define RESULT_CONTROL_PUP_1_BIT_4_REG 0x1934
+#define RESULT_CONTROL_PUP_1_BIT_5_REG 0x1938
+#define RESULT_CONTROL_PUP_1_BIT_6_REG 0x193c
+#define RESULT_CONTROL_PUP_1_BIT_7_REG 0x19b0
+#define RESULT_CONTROL_PUP_2_BIT_0_REG 0x19b4
+#define RESULT_CONTROL_PUP_2_BIT_1_REG 0x19b8
+#define RESULT_CONTROL_PUP_2_BIT_2_REG 0x19bc
+#define RESULT_CONTROL_PUP_2_BIT_3_REG 0x19c0
+#define RESULT_CONTROL_PUP_2_BIT_4_REG 0x19c4
+#define RESULT_CONTROL_PUP_2_BIT_5_REG 0x19c8
+#define RESULT_CONTROL_PUP_2_BIT_6_REG 0x19cc
+#define RESULT_CONTROL_PUP_2_BIT_7_REG 0x19f0
+#define RESULT_CONTROL_PUP_3_BIT_0_REG 0x19f4
+#define RESULT_CONTROL_PUP_3_BIT_1_REG 0x19f8
+#define RESULT_CONTROL_PUP_3_BIT_2_REG 0x19fc
+#define RESULT_CONTROL_PUP_3_BIT_3_REG 0x1a30
+#define RESULT_CONTROL_PUP_3_BIT_4_REG 0x1a34
+#define RESULT_CONTROL_PUP_3_BIT_5_REG 0x1a38
+#define RESULT_CONTROL_PUP_3_BIT_6_REG 0x1a3c
+#define RESULT_CONTROL_PUP_3_BIT_7_REG 0x1ab0
+#define RESULT_CONTROL_PUP_4_BIT_0_REG 0x1ab4
+#define RESULT_CONTROL_PUP_4_BIT_1_REG 0x1ab8
+#define RESULT_CONTROL_PUP_4_BIT_2_REG 0x1abc
+#define RESULT_CONTROL_PUP_4_BIT_3_REG 0x1ac0
+#define RESULT_CONTROL_PUP_4_BIT_4_REG 0x1ac4
+#define RESULT_CONTROL_PUP_4_BIT_5_REG 0x1ac8
+#define RESULT_CONTROL_PUP_4_BIT_6_REG 0x1acc
+#define RESULT_CONTROL_PUP_4_BIT_7_REG 0x1af0
+
+#define WL_PHY_REG 0x0
+#define WRITE_CENTRALIZATION_PHY_REG 0x1
+#define RL_PHY_REG 0x2
+#define READ_CENTRALIZATION_PHY_REG 0x3
+#define PBS_RX_PHY_REG 0x50
+#define PBS_TX_PHY_REG 0x10
+#define PHY_CONTROL_PHY_REG 0x90
+#define BW_PHY_REG 0x92
+#define RATE_PHY_REG 0x94
+#define CMOS_CONFIG_PHY_REG 0xa2
+#define PAD_ZRI_CALIB_PHY_REG 0xa4
+#define PAD_ODT_CALIB_PHY_REG 0xa6
+#define PAD_CONFIG_PHY_REG 0xa8
+#define PAD_PRE_DISABLE_PHY_REG 0xa9
+#define TEST_ADLL_REG 0xbf
+#define CSN_IOB_VREF_REG(cs) (0xdb + (cs * 12))
+#define CSN_IO_BASE_VREF_REG(cs) (0xd0 + (cs * 12))
+
+#define RESULT_DB_PHY_REG_ADDR 0xc0
+#define RESULT_DB_PHY_REG_RX_OFFSET 5
+#define RESULT_DB_PHY_REG_TX_OFFSET 0
+
+/* TBD - for NP5 use only CS 0 */
+#define PHY_WRITE_DELAY(cs) WL_PHY_REG
+/*( ( _cs_ == 0 ) ? 0x0 : 0x4 )*/
+/* TBD - for NP5 use only CS 0 */
+#define PHY_READ_DELAY(cs) RL_PHY_REG
+
+#define DDR0_ADDR_1 0xf8258
+#define DDR0_ADDR_2 0xf8254
+#define DDR1_ADDR_1 0xf8270
+#define DDR1_ADDR_2 0xf8270
+#define DDR2_ADDR_1 0xf825c
+#define DDR2_ADDR_2 0xf825c
+#define DDR3_ADDR_1 0xf8264
+#define DDR3_ADDR_2 0xf8260
+#define DDR4_ADDR_1 0xf8274
+#define DDR4_ADDR_2 0xf8274
+
+#define GENERAL_PURPOSE_RESERVED0_REG 0x182e0
+
+#define GET_BLOCK_ID_MAX_FREQ(dev_num, block_id) 800000
+#define CS0_RD_LVL_REF_DLY_OFFS 0
+#define CS0_RD_LVL_REF_DLY_LEN 0
+#define CS0_RD_LVL_PH_SEL_OFFS 0
+#define CS0_RD_LVL_PH_SEL_LEN 0
+
+#define CS_REGISTER_ADDR_OFFSET 4
+#define CALIBRATED_OBJECTS_REG_ADDR_OFFSET 0x10
+
+#define MAX_POLLING_ITERATIONS 100000
+
+#define PHASE_REG_OFFSET 32
+#define NUM_BYTES_IN_BURST 31
+#define NUM_OF_CS 4
+#define CS_REG_VALUE(cs_num) (cs_mask_reg[cs_num])
+#define ADLL_LENGTH 32
+
+struct write_supp_result {
+ enum hws_wl_supp stage;
+ int is_pup_fail;
+};
+
+struct page_element {
+ enum hws_page_size page_size_8bit;
+ /* page size in 8 bits bus width */
+ enum hws_page_size page_size_16bit;
+ /* page size in 16 bits bus width */
+ u32 ui_page_mask;
+ /* Mask used in register */
+};
+
+int ddr3_tip_write_leveling_static_config(u32 dev_num, u32 if_id,
+ enum hws_ddr_freq frequency,
+ u32 *round_trip_delay_arr);
+int ddr3_tip_read_leveling_static_config(u32 dev_num, u32 if_id,
+ enum hws_ddr_freq frequency,
+ u32 *total_round_trip_delay_arr);
+int ddr3_tip_if_write(u32 dev_num, enum hws_access_type interface_access,
+ u32 if_id, u32 reg_addr, u32 data_value, u32 mask);
+int ddr3_tip_if_polling(u32 dev_num, enum hws_access_type access_type,
+ u32 if_id, u32 exp_value, u32 mask, u32 offset,
+ u32 poll_tries);
+int ddr3_tip_if_read(u32 dev_num, enum hws_access_type interface_access,
+ u32 if_id, u32 reg_addr, u32 *data, u32 mask);
+int ddr3_tip_bus_read_modify_write(u32 dev_num,
+ enum hws_access_type access_type,
+ u32 if_id, u32 phy_id,
+ enum hws_ddr_phy phy_type,
+ u32 reg_addr, u32 data_value, u32 reg_mask);
+int ddr3_tip_bus_read(u32 dev_num, u32 if_id, enum hws_access_type phy_access,
+ u32 phy_id, enum hws_ddr_phy phy_type, u32 reg_addr,
+ u32 *data);
+int ddr3_tip_bus_write(u32 dev_num, enum hws_access_type e_interface_access,
+ u32 if_id, enum hws_access_type e_phy_access, u32 phy_id,
+ enum hws_ddr_phy e_phy_type, u32 reg_addr,
+ u32 data_value);
+int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type e_access, u32 if_id,
+ enum hws_ddr_freq memory_freq);
+int ddr3_tip_adjust_dqs(u32 dev_num);
+int ddr3_tip_init_controller(u32 dev_num);
+int ddr3_tip_ext_read(u32 dev_num, u32 if_id, u32 reg_addr,
+ u32 num_of_bursts, u32 *addr);
+int ddr3_tip_ext_write(u32 dev_num, u32 if_id, u32 reg_addr,
+ u32 num_of_bursts, u32 *addr);
+int ddr3_tip_dynamic_read_leveling(u32 dev_num, u32 ui_freq);
+int ddr3_tip_legacy_dynamic_read_leveling(u32 dev_num);
+int ddr3_tip_dynamic_per_bit_read_leveling(u32 dev_num, u32 ui_freq);
+int ddr3_tip_legacy_dynamic_write_leveling(u32 dev_num);
+int ddr3_tip_dynamic_write_leveling(u32 dev_num);
+int ddr3_tip_dynamic_write_leveling_supp(u32 dev_num);
+int ddr3_tip_static_init_controller(u32 dev_num);
+int ddr3_tip_configure_phy(u32 dev_num);
+int ddr3_tip_load_pattern_to_odpg(u32 dev_num, enum hws_access_type access_type,
+ u32 if_id, enum hws_pattern pattern,
+ u32 load_addr);
+int ddr3_tip_load_pattern_to_mem(u32 dev_num, enum hws_pattern e_pattern);
+int ddr3_tip_configure_odpg(u32 dev_num, enum hws_access_type access_type,
+ u32 if_id, enum hws_dir direction, u32 tx_phases,
+ u32 tx_burst_size, u32 rx_phases,
+ u32 delay_between_burst, u32 rd_mode, u32 cs_num,
+ u32 addr_stress_jump, u32 single_pattern);
+int ddr3_tip_set_atr(u32 dev_num, u32 flag_id, u32 value);
+int ddr3_tip_write_mrs_cmd(u32 dev_num, u32 *cs_mask_arr, u32 cmd, u32 data,
+ u32 mask);
+int ddr3_tip_write_cs_result(u32 dev_num, u32 offset);
+int ddr3_tip_get_first_active_if(u8 dev_num, u32 interface_mask, u32 *if_id);
+int ddr3_tip_reset_fifo_ptr(u32 dev_num);
+int read_pup_value(int pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
+ int reg_addr, u32 mask);
+int read_adll_value(u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
+ int reg_addr, u32 mask);
+int write_adll_value(u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
+ int reg_addr);
+int ddr3_tip_tune_training_params(u32 dev_num,
+ struct tune_train_params *params);
+
+#endif /* _DDR3_TRAINING_IP_FLOW_H_ */
diff --git a/drivers/ddr/marvell/a38x/old/ddr3_training_ip_pbs.h b/drivers/ddr/marvell/a38x/old/ddr3_training_ip_pbs.h
new file mode 100644
index 0000000..c6be67c
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/ddr3_training_ip_pbs.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _DDR3_TRAINING_IP_PBS_H_
+#define _DDR3_TRAINING_IP_PBS_H_
+
+enum {
+ EBA_CONFIG,
+ EEBA_CONFIG,
+ SBA_CONFIG
+};
+
+enum hws_training_load_op {
+ TRAINING_LOAD_OPERATION_UNLOAD,
+ TRAINING_LOAD_OPERATION_LOAD
+};
+
+enum hws_edge {
+ TRAINING_EDGE_1,
+ TRAINING_EDGE_2
+};
+
+enum hws_edge_search {
+ TRAINING_EDGE_MAX,
+ TRAINING_EDGE_MIN
+};
+
+enum pbs_dir {
+ PBS_TX_MODE = 0,
+ PBS_RX_MODE,
+ NUM_OF_PBS_MODES
+};
+
+int ddr3_tip_pbs_rx(u32 dev_num);
+int ddr3_tip_print_all_pbs_result(u32 dev_num);
+int ddr3_tip_pbs_tx(u32 dev_num);
+
+#endif /* _DDR3_TRAINING_IP_PBS_H_ */
diff --git a/drivers/ddr/marvell/a38x/old/ddr3_training_ip_prv_if.h b/drivers/ddr/marvell/a38x/old/ddr3_training_ip_prv_if.h
new file mode 100644
index 0000000..724b106
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/ddr3_training_ip_prv_if.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _DDR3_TRAINING_IP_PRV_IF_H
+#define _DDR3_TRAINING_IP_PRV_IF_H
+
+#include "ddr3_training_ip.h"
+#include "ddr3_training_ip_flow.h"
+#include "ddr3_training_ip_bist.h"
+
+enum hws_static_config_type {
+ WRITE_LEVELING_STATIC,
+ READ_LEVELING_STATIC
+};
+
+struct ddr3_device_info {
+ u32 device_id;
+ u32 ck_delay;
+};
+
+typedef int (*HWS_TIP_DUNIT_MUX_SELECT_FUNC_PTR)(u8 dev_num, int enable);
+typedef int (*HWS_TIP_DUNIT_REG_READ_FUNC_PTR)(
+ u8 dev_num, enum hws_access_type interface_access, u32 if_id,
+ u32 offset, u32 *data, u32 mask);
+typedef int (*HWS_TIP_DUNIT_REG_WRITE_FUNC_PTR)(
+ u8 dev_num, enum hws_access_type interface_access, u32 if_id,
+ u32 offset, u32 data, u32 mask);
+typedef int (*HWS_TIP_GET_FREQ_CONFIG_INFO)(
+ u8 dev_num, enum hws_ddr_freq freq,
+ struct hws_tip_freq_config_info *freq_config_info);
+typedef int (*HWS_TIP_GET_DEVICE_INFO)(
+ u8 dev_num, struct ddr3_device_info *info_ptr);
+typedef int (*HWS_GET_CS_CONFIG_FUNC_PTR)(
+ u8 dev_num, u32 cs_mask, struct hws_cs_config_info *cs_info);
+typedef int (*HWS_SET_FREQ_DIVIDER_FUNC_PTR)(
+ u8 dev_num, u32 if_id, enum hws_ddr_freq freq);
+typedef int (*HWS_GET_INIT_FREQ)(u8 dev_num, enum hws_ddr_freq *freq);
+typedef int (*HWS_TRAINING_IP_IF_WRITE_FUNC_PTR)(
+ u32 dev_num, enum hws_access_type access_type, u32 dunit_id,
+ u32 reg_addr, u32 data, u32 mask);
+typedef int (*HWS_TRAINING_IP_IF_READ_FUNC_PTR)(
+ u32 dev_num, enum hws_access_type access_type, u32 dunit_id,
+ u32 reg_addr, u32 *data, u32 mask);
+typedef int (*HWS_TRAINING_IP_BUS_WRITE_FUNC_PTR)(
+ u32 dev_num, enum hws_access_type dunit_access_type, u32 if_id,
+ enum hws_access_type phy_access_type, u32 phy_id,
+ enum hws_ddr_phy phy_type, u32 reg_addr, u32 data);
+typedef int (*HWS_TRAINING_IP_BUS_READ_FUNC_PTR)(
+ u32 dev_num, u32 if_id, enum hws_access_type phy_access_type,
+ u32 phy_id, enum hws_ddr_phy phy_type, u32 reg_addr, u32 *data);
+typedef int (*HWS_TRAINING_IP_ALGO_RUN_FUNC_PTR)(
+ u32 dev_num, enum hws_algo_type algo_type);
+typedef int (*HWS_TRAINING_IP_SET_FREQ_FUNC_PTR)(
+ u32 dev_num, enum hws_access_type access_type, u32 if_id,
+ enum hws_ddr_freq frequency);
+typedef int (*HWS_TRAINING_IP_INIT_CONTROLLER_FUNC_PTR)(
+ u32 dev_num, struct init_cntr_param *init_cntr_prm);
+typedef int (*HWS_TRAINING_IP_PBS_RX_FUNC_PTR)(u32 dev_num);
+typedef int (*HWS_TRAINING_IP_PBS_TX_FUNC_PTR)(u32 dev_num);
+typedef int (*HWS_TRAINING_IP_SELECT_CONTROLLER_FUNC_PTR)(
+ u32 dev_num, int enable);
+typedef int (*HWS_TRAINING_IP_TOPOLOGY_MAP_LOAD_FUNC_PTR)(
+ u32 dev_num, struct hws_topology_map *topology_map);
+typedef int (*HWS_TRAINING_IP_STATIC_CONFIG_FUNC_PTR)(
+ u32 dev_num, enum hws_ddr_freq frequency,
+ enum hws_static_config_type static_config_type, u32 if_id);
+typedef int (*HWS_TRAINING_IP_EXTERNAL_READ_PTR)(
+ u32 dev_num, u32 if_id, u32 ddr_addr, u32 num_bursts, u32 *data);
+typedef int (*HWS_TRAINING_IP_EXTERNAL_WRITE_PTR)(
+ u32 dev_num, u32 if_id, u32 ddr_addr, u32 num_bursts, u32 *data);
+typedef int (*HWS_TRAINING_IP_BIST_ACTIVATE)(
+ u32 dev_num, enum hws_pattern pattern, enum hws_access_type access_type,
+ u32 if_num, enum hws_dir direction,
+ enum hws_stress_jump addr_stress_jump,
+ enum hws_pattern_duration duration,
+ enum hws_bist_operation oper_type, u32 offset, u32 cs_num,
+ u32 pattern_addr_length);
+typedef int (*HWS_TRAINING_IP_BIST_READ_RESULT)(
+ u32 dev_num, u32 if_id, struct bist_result *pst_bist_result);
+typedef int (*HWS_TRAINING_IP_LOAD_TOPOLOGY)(u32 dev_num, u32 config_num);
+typedef int (*HWS_TRAINING_IP_READ_LEVELING)(u32 dev_num, u32 config_num);
+typedef int (*HWS_TRAINING_IP_WRITE_LEVELING)(u32 dev_num, u32 config_num);
+typedef u32 (*HWS_TRAINING_IP_GET_TEMP)(u8 dev_num);
+
+struct hws_tip_config_func_db {
+ HWS_TIP_DUNIT_MUX_SELECT_FUNC_PTR tip_dunit_mux_select_func;
+ HWS_TIP_DUNIT_REG_READ_FUNC_PTR tip_dunit_read_func;
+ HWS_TIP_DUNIT_REG_WRITE_FUNC_PTR tip_dunit_write_func;
+ HWS_TIP_GET_FREQ_CONFIG_INFO tip_get_freq_config_info_func;
+ HWS_TIP_GET_DEVICE_INFO tip_get_device_info_func;
+ HWS_SET_FREQ_DIVIDER_FUNC_PTR tip_set_freq_divider_func;
+ HWS_GET_CS_CONFIG_FUNC_PTR tip_get_cs_config_info;
+ HWS_TRAINING_IP_GET_TEMP tip_get_temperature;
+};
+
+int ddr3_tip_init_config_func(u32 dev_num,
+ struct hws_tip_config_func_db *config_func);
+int ddr3_tip_register_xsb_info(u32 dev_num,
+ struct hws_xsb_info *xsb_info_table);
+enum hws_result *ddr3_tip_get_result_ptr(u32 stage);
+int ddr3_set_freq_config_info(struct hws_tip_freq_config_info *table);
+int print_device_info(u8 dev_num);
+
+#endif /* _DDR3_TRAINING_IP_PRV_IF_H */
diff --git a/drivers/ddr/marvell/a38x/old/ddr3_training_ip_static.h b/drivers/ddr/marvell/a38x/old/ddr3_training_ip_static.h
new file mode 100644
index 0000000..878068b
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/ddr3_training_ip_static.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _DDR3_TRAINING_IP_STATIC_H_
+#define _DDR3_TRAINING_IP_STATIC_H_
+
+#include "ddr3_training_ip_def.h"
+#include "ddr3_training_ip.h"
+
+struct trip_delay_element {
+ u32 dqs_delay; /* DQS delay (m_sec) */
+ u32 ck_delay; /* CK Delay (m_sec) */
+};
+
+struct hws_tip_static_config_info {
+ u32 silicon_delay;
+ struct trip_delay_element *package_trace_arr;
+ struct trip_delay_element *board_trace_arr;
+};
+
+int ddr3_tip_run_static_alg(u32 dev_num, enum hws_ddr_freq freq);
+int ddr3_tip_init_static_config_db(
+ u32 dev_num, struct hws_tip_static_config_info *static_config_info);
+int ddr3_tip_init_specific_reg_config(u32 dev_num,
+ struct reg_data *reg_config_arr);
+int ddr3_tip_static_phy_init_controller(u32 dev_num);
+
+#endif /* _DDR3_TRAINING_IP_STATIC_H_ */
diff --git a/drivers/ddr/marvell/a38x/old/ddr3_training_leveling.c b/drivers/ddr/marvell/a38x/old/ddr3_training_leveling.c
new file mode 100644
index 0000000..d41845a
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/ddr3_training_leveling.c
@@ -0,0 +1,1836 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <linux/delay.h>
+
+#include "ddr3_init.h"
+
+#define WL_ITERATION_NUM 10
+#define ONE_CLOCK_ERROR_SHIFT 2
+#define ALIGN_ERROR_SHIFT -2
+
+static u32 pup_mask_table[] = {
+ 0x000000ff,
+ 0x0000ff00,
+ 0x00ff0000,
+ 0xff000000
+};
+
+static struct write_supp_result wr_supp_res[MAX_INTERFACE_NUM][MAX_BUS_NUM];
+
+static int ddr3_tip_dynamic_write_leveling_seq(u32 dev_num);
+static int ddr3_tip_dynamic_read_leveling_seq(u32 dev_num);
+static int ddr3_tip_dynamic_per_bit_read_leveling_seq(u32 dev_num);
+static int ddr3_tip_wl_supp_align_err_shift(u32 dev_num, u32 if_id, u32 bus_id,
+ u32 bus_id_delta);
+static int ddr3_tip_wl_supp_align_phase_shift(u32 dev_num, u32 if_id,
+ u32 bus_id, u32 offset,
+ u32 bus_id_delta);
+static int ddr3_tip_xsb_compare_test(u32 dev_num, u32 if_id, u32 bus_id,
+ u32 edge_offset, u32 bus_id_delta);
+static int ddr3_tip_wl_supp_one_clk_err_shift(u32 dev_num, u32 if_id,
+ u32 bus_id, u32 bus_id_delta);
+
+u32 hws_ddr3_tip_max_cs_get(void)
+{
+ u32 c_cs;
+ static u32 max_cs;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ if (!max_cs) {
+ for (c_cs = 0; c_cs < NUM_OF_CS; c_cs++) {
+ VALIDATE_ACTIVE(tm->
+ interface_params[0].as_bus_params[0].
+ cs_bitmask, c_cs);
+ max_cs++;
+ }
+ }
+
+ return max_cs;
+}
+
+/*****************************************************************************
+Dynamic read leveling
+******************************************************************************/
+int ddr3_tip_dynamic_read_leveling(u32 dev_num, u32 freq)
+{
+ u32 data, mask;
+ u32 max_cs = hws_ddr3_tip_max_cs_get();
+ u32 bus_num, if_id, cl_val;
+ enum hws_speed_bin speed_bin_index;
+ /* save current CS value */
+ u32 cs_enable_reg_val[MAX_INTERFACE_NUM] = { 0 };
+ int is_any_pup_fail = 0;
+ u32 data_read[MAX_INTERFACE_NUM + 1] = { 0 };
+ u8 rl_values[NUM_OF_CS][MAX_BUS_NUM][MAX_INTERFACE_NUM];
+ struct pattern_info *pattern_table = ddr3_tip_get_pattern_table();
+ u16 *mask_results_pup_reg_map = ddr3_tip_get_mask_results_pup_reg_map();
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ if (rl_version == 0) {
+ /* OLD RL machine */
+ data = 0x40;
+ data |= (1 << 20);
+
+ /* TBD multi CS */
+ CHECK_STATUS(ddr3_tip_if_write(
+ dev_num, ACCESS_TYPE_MULTICAST,
+ PARAM_NOT_CARE, TRAINING_REG,
+ data, 0x11ffff));
+ CHECK_STATUS(ddr3_tip_if_write(
+ dev_num, ACCESS_TYPE_MULTICAST,
+ PARAM_NOT_CARE,
+ TRAINING_PATTERN_BASE_ADDRESS_REG,
+ 0, 0xfffffff8));
+ CHECK_STATUS(ddr3_tip_if_write(
+ dev_num, ACCESS_TYPE_MULTICAST,
+ PARAM_NOT_CARE, TRAINING_REG,
+ (u32)(1 << 31), (u32)(1 << 31)));
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ training_result[training_stage][if_id] = TEST_SUCCESS;
+ if (ddr3_tip_if_polling
+ (dev_num, ACCESS_TYPE_UNICAST, if_id, 0,
+ (u32)(1 << 31), TRAINING_REG,
+ MAX_POLLING_ITERATIONS) != MV_OK) {
+ DEBUG_LEVELING(
+ DEBUG_LEVEL_ERROR,
+ ("RL: DDR3 poll failed(1) IF %d\n",
+ if_id));
+ training_result[training_stage][if_id] =
+ TEST_FAILED;
+
+ if (debug_mode == 0)
+ return MV_FAIL;
+ }
+ }
+
+ /* read read-leveling result */
+ CHECK_STATUS(ddr3_tip_if_read
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ TRAINING_REG, data_read, 1 << 30));
+ /* exit read leveling mode */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ TRAINING_SW_2_REG, 0x8, 0x9));
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ TRAINING_SW_1_REG, 1 << 16, 1 << 16));
+
+ /* disable RL machine all Trn_CS[3:0] , [16:0] */
+
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ TRAINING_REG, 0, 0xf1ffff));
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ if ((data_read[if_id] & (1 << 30)) == 0) {
+ DEBUG_LEVELING(
+ DEBUG_LEVEL_ERROR,
+ ("\n_read Leveling failed for IF %d\n",
+ if_id));
+ training_result[training_stage][if_id] =
+ TEST_FAILED;
+ if (debug_mode == 0)
+ return MV_FAIL;
+ }
+ }
+ return MV_OK;
+ }
+
+ /* NEW RL machine */
+ for (effective_cs = 0; effective_cs < NUM_OF_CS; effective_cs++)
+ for (bus_num = 0; bus_num < MAX_BUS_NUM; bus_num++)
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++)
+ rl_values[effective_cs][bus_num][if_id] = 0;
+
+ for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ training_result[training_stage][if_id] = TEST_SUCCESS;
+
+ /* save current cs enable reg val */
+ CHECK_STATUS(ddr3_tip_if_read
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ CS_ENABLE_REG, cs_enable_reg_val,
+ MASK_ALL_BITS));
+ /* enable single cs */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ CS_ENABLE_REG, (1 << 3), (1 << 3)));
+ }
+
+ ddr3_tip_reset_fifo_ptr(dev_num);
+
+ /*
+ * Phase 1: Load pattern (using ODPG)
+ *
+ * enter Read Leveling mode
+ * only 27 bits are masked
+ * assuming non multi-CS configuration
+ * write to CS = 0 for the non multi CS configuration, note
+ * that the results shall be read back to the required CS !!!
+ */
+
+ /* BUS count is 0 shifted 26 */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ODPG_DATA_CONTROL_REG, 0x3, 0x3));
+ CHECK_STATUS(ddr3_tip_configure_odpg
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, 0,
+ pattern_table[PATTERN_RL].num_of_phases_tx, 0,
+ pattern_table[PATTERN_RL].num_of_phases_rx, 0, 0,
+ effective_cs, STRESS_NONE, DURATION_SINGLE));
+
+ /* load pattern to ODPG */
+ ddr3_tip_load_pattern_to_odpg(dev_num, ACCESS_TYPE_MULTICAST,
+ PARAM_NOT_CARE, PATTERN_RL,
+ pattern_table[PATTERN_RL].
+ start_addr);
+
+ /*
+ * Phase 2: ODPG to Read Leveling mode
+ */
+
+ /* General Training Opcode register */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ODPG_WRITE_READ_MODE_ENABLE_REG, 0,
+ MASK_ALL_BITS));
+
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ODPG_TRAINING_CONTROL_REG,
+ (0x301b01 | effective_cs << 2), 0x3c3fef));
+
+ /* Object1 opcode register 0 & 1 */
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ speed_bin_index =
+ tm->interface_params[if_id].speed_bin_index;
+ cl_val =
+ cas_latency_table[speed_bin_index].cl_val[freq];
+ data = (cl_val << 17) | (0x3 << 25);
+ mask = (0xff << 9) | (0x1f << 17) | (0x3 << 25);
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ ODPG_OBJ1_OPCODE_REG, data, mask));
+ }
+
+ /* Set iteration count to max value */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ TRAINING_OPCODE_1_REG, 0xd00, 0xd00));
+
+ /*
+ * Phase 2: Mask config
+ */
+
+ ddr3_tip_dynamic_read_leveling_seq(dev_num);
+
+ /*
+ * Phase 3: Read Leveling execution
+ */
+
+ /* temporary jira dunit=14751 */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ TRAINING_DBG_1_REG, 0, (u32)(1 << 31)));
+ /* configure phy reset value */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ TRAINING_DBG_3_REG, (0x7f << 24),
+ (u32)(0xff << 24)));
+ /* data pup rd reset enable */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ SDRAM_CONFIGURATION_REG, 0, (1 << 30)));
+ /* data pup rd reset disable */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ SDRAM_CONFIGURATION_REG, (1 << 30), (1 << 30)));
+ /* training SW override & training RL mode */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ TRAINING_SW_2_REG, 0x1, 0x9));
+ /* training enable */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ TRAINING_REG, (1 << 24) | (1 << 20),
+ (1 << 24) | (1 << 20)));
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ TRAINING_REG, (u32)(1 << 31), (u32)(1 << 31)));
+
+ /********* trigger training *******************/
+ /* Trigger, poll on status and disable ODPG */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ODPG_TRAINING_TRIGGER_REG, 0x1, 0x1));
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ODPG_TRAINING_STATUS_REG, 0x1, 0x1));
+
+ /* check for training done + results pass */
+ if (ddr3_tip_if_polling
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, 0x2, 0x2,
+ ODPG_TRAINING_STATUS_REG,
+ MAX_POLLING_ITERATIONS) != MV_OK) {
+ DEBUG_LEVELING(DEBUG_LEVEL_ERROR,
+ ("Training Done Failed\n"));
+ return MV_FAIL;
+ }
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ CHECK_STATUS(ddr3_tip_if_read
+ (dev_num, ACCESS_TYPE_UNICAST,
+ if_id,
+ ODPG_TRAINING_TRIGGER_REG, data_read,
+ 0x4));
+ data = data_read[if_id];
+ if (data != 0x0) {
+ DEBUG_LEVELING(DEBUG_LEVEL_ERROR,
+ ("Training Result Failed\n"));
+ }
+ }
+
+ /*disable ODPG - Back to functional mode */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ODPG_ENABLE_REG, 0x1 << ODPG_DISABLE_OFFS,
+ (0x1 << ODPG_DISABLE_OFFS)));
+ if (ddr3_tip_if_polling
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, 0x0, 0x1,
+ ODPG_ENABLE_REG, MAX_POLLING_ITERATIONS) != MV_OK) {
+ DEBUG_LEVELING(DEBUG_LEVEL_ERROR,
+ ("ODPG disable failed "));
+ return MV_FAIL;
+ }
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ODPG_DATA_CONTROL_REG, 0, MASK_ALL_BITS));
+
+ /* double loop on bus, pup */
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ /* check training done */
+ is_any_pup_fail = 0;
+ for (bus_num = 0;
+ bus_num < tm->num_of_bus_per_interface;
+ bus_num++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, bus_num);
+ if (ddr3_tip_if_polling
+ (dev_num, ACCESS_TYPE_UNICAST,
+ if_id, (1 << 25), (1 << 25),
+ mask_results_pup_reg_map[bus_num],
+ MAX_POLLING_ITERATIONS) != MV_OK) {
+ DEBUG_LEVELING(DEBUG_LEVEL_ERROR,
+ ("\n_r_l: DDR3 poll failed(2) for bus %d",
+ bus_num));
+ is_any_pup_fail = 1;
+ } else {
+ /* read result per pup */
+ CHECK_STATUS(ddr3_tip_if_read
+ (dev_num,
+ ACCESS_TYPE_UNICAST,
+ if_id,
+ mask_results_pup_reg_map
+ [bus_num], data_read,
+ 0xff));
+ rl_values[effective_cs][bus_num]
+ [if_id] = (u8)data_read[if_id];
+ }
+ }
+
+ if (is_any_pup_fail == 1) {
+ training_result[training_stage][if_id] =
+ TEST_FAILED;
+ if (debug_mode == 0)
+ return MV_FAIL;
+ }
+ }
+
+ DEBUG_LEVELING(DEBUG_LEVEL_INFO, ("RL exit read leveling\n"));
+
+ /*
+ * Phase 3: Exit Read Leveling
+ */
+
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ TRAINING_SW_2_REG, (1 << 3), (1 << 3)));
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ TRAINING_SW_1_REG, (1 << 16), (1 << 16)));
+ /* set ODPG to functional */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ODPG_DATA_CONTROL_REG, 0x0, MASK_ALL_BITS));
+
+ /*
+ * Copy the result from the effective CS search to the
+ * real Functional CS
+ */
+ /*ddr3_tip_write_cs_result(dev_num, RL_PHY_REG); */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ODPG_DATA_CONTROL_REG, 0x0, MASK_ALL_BITS));
+ }
+
+ for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
+ /* double loop on bus, pup */
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ for (bus_num = 0;
+ bus_num < tm->num_of_bus_per_interface;
+ bus_num++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, bus_num);
+ /* read result per pup from arry */
+ data = rl_values[effective_cs][bus_num][if_id];
+ data = (data & 0x1f) |
+ (((data & 0xe0) >> 5) << 6);
+ ddr3_tip_bus_write(dev_num,
+ ACCESS_TYPE_UNICAST,
+ if_id,
+ ACCESS_TYPE_UNICAST,
+ bus_num, DDR_PHY_DATA,
+ RL_PHY_REG +
+ ((effective_cs ==
+ 0) ? 0x0 : 0x4), data);
+ }
+ }
+ }
+ /* Set to 0 after each loop to avoid illegal value may be used */
+ effective_cs = 0;
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ /* restore cs enable value */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ CS_ENABLE_REG, cs_enable_reg_val[if_id],
+ MASK_ALL_BITS));
+ if (odt_config != 0) {
+ CHECK_STATUS(ddr3_tip_write_additional_odt_setting
+ (dev_num, if_id));
+ }
+ }
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ if (training_result[training_stage][if_id] == TEST_FAILED)
+ return MV_FAIL;
+ }
+
+ return MV_OK;
+}
+
+/*
+ * Legacy Dynamic write leveling
+ */
+int ddr3_tip_legacy_dynamic_write_leveling(u32 dev_num)
+{
+ u32 c_cs, if_id, cs_mask = 0;
+ u32 max_cs = hws_ddr3_tip_max_cs_get();
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ /*
+ * In TRAINIUNG reg (0x15b0) write 0x80000008 | cs_mask:
+ * Trn_start
+ * cs_mask = 0x1 <<20 Trn_CS0 - CS0 is included in the DDR3 training
+ * cs_mask = 0x1 <<21 Trn_CS1 - CS1 is included in the DDR3 training
+ * cs_mask = 0x1 <<22 Trn_CS2 - CS2 is included in the DDR3 training
+ * cs_mask = 0x1 <<23 Trn_CS3 - CS3 is included in the DDR3 training
+ * Trn_auto_seq = write leveling
+ */
+ for (c_cs = 0; c_cs < max_cs; c_cs++)
+ cs_mask = cs_mask | 1 << (20 + c_cs);
+
+ for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, 0,
+ TRAINING_REG, (0x80000008 | cs_mask),
+ 0xffffffff));
+ mdelay(20);
+ if (ddr3_tip_if_polling
+ (dev_num, ACCESS_TYPE_UNICAST, if_id, 0,
+ (u32)0x80000000, TRAINING_REG,
+ MAX_POLLING_ITERATIONS) != MV_OK) {
+ DEBUG_LEVELING(DEBUG_LEVEL_ERROR,
+ ("polling failed for Old WL result\n"));
+ return MV_FAIL;
+ }
+ }
+
+ return MV_OK;
+}
+
+/*
+ * Legacy Dynamic read leveling
+ */
+int ddr3_tip_legacy_dynamic_read_leveling(u32 dev_num)
+{
+ u32 c_cs, if_id, cs_mask = 0;
+ u32 max_cs = hws_ddr3_tip_max_cs_get();
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ /*
+ * In TRAINIUNG reg (0x15b0) write 0x80000040 | cs_mask:
+ * Trn_start
+ * cs_mask = 0x1 <<20 Trn_CS0 - CS0 is included in the DDR3 training
+ * cs_mask = 0x1 <<21 Trn_CS1 - CS1 is included in the DDR3 training
+ * cs_mask = 0x1 <<22 Trn_CS2 - CS2 is included in the DDR3 training
+ * cs_mask = 0x1 <<23 Trn_CS3 - CS3 is included in the DDR3 training
+ * Trn_auto_seq = Read Leveling using training pattern
+ */
+ for (c_cs = 0; c_cs < max_cs; c_cs++)
+ cs_mask = cs_mask | 1 << (20 + c_cs);
+
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, 0, TRAINING_REG,
+ (0x80000040 | cs_mask), 0xffffffff));
+ mdelay(100);
+
+ for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ if (ddr3_tip_if_polling
+ (dev_num, ACCESS_TYPE_UNICAST, if_id, 0,
+ (u32)0x80000000, TRAINING_REG,
+ MAX_POLLING_ITERATIONS) != MV_OK) {
+ DEBUG_LEVELING(DEBUG_LEVEL_ERROR,
+ ("polling failed for Old RL result\n"));
+ return MV_FAIL;
+ }
+ }
+
+ return MV_OK;
+}
+
+/*
+ * Dynamic per bit read leveling
+ */
+int ddr3_tip_dynamic_per_bit_read_leveling(u32 dev_num, u32 freq)
+{
+ u32 data, mask;
+ u32 bus_num, if_id, cl_val, bit_num;
+ u32 curr_numb, curr_min_delay;
+ int adll_array[3] = { 0, -0xa, 0x14 };
+ u32 phyreg3_arr[MAX_INTERFACE_NUM][MAX_BUS_NUM];
+ enum hws_speed_bin speed_bin_index;
+ int is_any_pup_fail = 0;
+ int break_loop = 0;
+ u32 cs_enable_reg_val[MAX_INTERFACE_NUM]; /* save current CS value */
+ u32 data_read[MAX_INTERFACE_NUM];
+ int per_bit_rl_pup_status[MAX_INTERFACE_NUM][MAX_BUS_NUM];
+ u32 data2_write[MAX_INTERFACE_NUM][MAX_BUS_NUM];
+ struct pattern_info *pattern_table = ddr3_tip_get_pattern_table();
+ u16 *mask_results_dq_reg_map = ddr3_tip_get_mask_results_dq_reg();
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ for (bus_num = 0;
+ bus_num <= tm->num_of_bus_per_interface; bus_num++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, bus_num);
+ per_bit_rl_pup_status[if_id][bus_num] = 0;
+ data2_write[if_id][bus_num] = 0;
+ /* read current value of phy register 0x3 */
+ CHECK_STATUS(ddr3_tip_bus_read
+ (dev_num, if_id, ACCESS_TYPE_UNICAST,
+ bus_num, DDR_PHY_DATA,
+ READ_CENTRALIZATION_PHY_REG,
+ &phyreg3_arr[if_id][bus_num]));
+ }
+ }
+
+ /* NEW RL machine */
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ training_result[training_stage][if_id] = TEST_SUCCESS;
+
+ /* save current cs enable reg val */
+ CHECK_STATUS(ddr3_tip_if_read
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ CS_ENABLE_REG, &cs_enable_reg_val[if_id],
+ MASK_ALL_BITS));
+ /* enable single cs */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ CS_ENABLE_REG, (1 << 3), (1 << 3)));
+ }
+
+ ddr3_tip_reset_fifo_ptr(dev_num);
+ for (curr_numb = 0; curr_numb < 3; curr_numb++) {
+ /*
+ * Phase 1: Load pattern (using ODPG)
+ *
+ * enter Read Leveling mode
+ * only 27 bits are masked
+ * assuming non multi-CS configuration
+ * write to CS = 0 for the non multi CS configuration, note that
+ * the results shall be read back to the required CS !!!
+ */
+
+ /* BUS count is 0 shifted 26 */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ODPG_DATA_CONTROL_REG, 0x3, 0x3));
+ CHECK_STATUS(ddr3_tip_configure_odpg
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, 0,
+ pattern_table[PATTERN_TEST].num_of_phases_tx, 0,
+ pattern_table[PATTERN_TEST].num_of_phases_rx, 0,
+ 0, 0, STRESS_NONE, DURATION_SINGLE));
+
+ /* load pattern to ODPG */
+ ddr3_tip_load_pattern_to_odpg(dev_num, ACCESS_TYPE_MULTICAST,
+ PARAM_NOT_CARE, PATTERN_TEST,
+ pattern_table[PATTERN_TEST].
+ start_addr);
+
+ /*
+ * Phase 2: ODPG to Read Leveling mode
+ */
+
+ /* General Training Opcode register */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ODPG_WRITE_READ_MODE_ENABLE_REG, 0,
+ MASK_ALL_BITS));
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ODPG_TRAINING_CONTROL_REG, 0x301b01, 0x3c3fef));
+
+ /* Object1 opcode register 0 & 1 */
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ speed_bin_index =
+ tm->interface_params[if_id].speed_bin_index;
+ cl_val =
+ cas_latency_table[speed_bin_index].cl_val[freq];
+ data = (cl_val << 17) | (0x3 << 25);
+ mask = (0xff << 9) | (0x1f << 17) | (0x3 << 25);
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ ODPG_OBJ1_OPCODE_REG, data, mask));
+ }
+
+ /* Set iteration count to max value */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ TRAINING_OPCODE_1_REG, 0xd00, 0xd00));
+
+ /*
+ * Phase 2: Mask config
+ */
+
+ ddr3_tip_dynamic_per_bit_read_leveling_seq(dev_num);
+
+ /*
+ * Phase 3: Read Leveling execution
+ */
+
+ /* temporary jira dunit=14751 */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ TRAINING_DBG_1_REG, 0, (u32)(1 << 31)));
+ /* configure phy reset value */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ TRAINING_DBG_3_REG, (0x7f << 24),
+ (u32)(0xff << 24)));
+ /* data pup rd reset enable */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ SDRAM_CONFIGURATION_REG, 0, (1 << 30)));
+ /* data pup rd reset disable */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ SDRAM_CONFIGURATION_REG, (1 << 30), (1 << 30)));
+ /* training SW override & training RL mode */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ TRAINING_SW_2_REG, 0x1, 0x9));
+ /* training enable */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ TRAINING_REG, (1 << 24) | (1 << 20),
+ (1 << 24) | (1 << 20)));
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ TRAINING_REG, (u32)(1 << 31), (u32)(1 << 31)));
+
+ /********* trigger training *******************/
+ /* Trigger, poll on status and disable ODPG */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ODPG_TRAINING_TRIGGER_REG, 0x1, 0x1));
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ODPG_TRAINING_STATUS_REG, 0x1, 0x1));
+
+ /*check for training done + results pass */
+ if (ddr3_tip_if_polling
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, 0x2, 0x2,
+ ODPG_TRAINING_STATUS_REG,
+ MAX_POLLING_ITERATIONS) != MV_OK) {
+ DEBUG_LEVELING(DEBUG_LEVEL_ERROR,
+ ("Training Done Failed\n"));
+ return MV_FAIL;
+ }
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ CHECK_STATUS(ddr3_tip_if_read
+ (dev_num, ACCESS_TYPE_UNICAST,
+ if_id,
+ ODPG_TRAINING_TRIGGER_REG, data_read,
+ 0x4));
+ data = data_read[if_id];
+ if (data != 0x0) {
+ DEBUG_LEVELING(DEBUG_LEVEL_ERROR,
+ ("Training Result Failed\n"));
+ }
+ }
+
+ /*disable ODPG - Back to functional mode */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ODPG_ENABLE_REG, 0x1 << ODPG_DISABLE_OFFS,
+ (0x1 << ODPG_DISABLE_OFFS)));
+ if (ddr3_tip_if_polling
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, 0x0, 0x1,
+ ODPG_ENABLE_REG, MAX_POLLING_ITERATIONS) != MV_OK) {
+ DEBUG_LEVELING(DEBUG_LEVEL_ERROR,
+ ("ODPG disable failed "));
+ return MV_FAIL;
+ }
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ODPG_DATA_CONTROL_REG, 0, MASK_ALL_BITS));
+
+ /* double loop on bus, pup */
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ /* check training done */
+ for (bus_num = 0;
+ bus_num < tm->num_of_bus_per_interface;
+ bus_num++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, bus_num);
+
+ if (per_bit_rl_pup_status[if_id][bus_num]
+ == 0) {
+ curr_min_delay = 0;
+ for (bit_num = 0; bit_num < 8;
+ bit_num++) {
+ if (ddr3_tip_if_polling
+ (dev_num,
+ ACCESS_TYPE_UNICAST,
+ if_id, (1 << 25),
+ (1 << 25),
+ mask_results_dq_reg_map
+ [bus_num * 8 + bit_num],
+ MAX_POLLING_ITERATIONS) !=
+ MV_OK) {
+ DEBUG_LEVELING
+ (DEBUG_LEVEL_ERROR,
+ ("\n_r_l: DDR3 poll failed(2) for bus %d bit %d\n",
+ bus_num,
+ bit_num));
+ } else {
+ /* read result per pup */
+ CHECK_STATUS
+ (ddr3_tip_if_read
+ (dev_num,
+ ACCESS_TYPE_UNICAST,
+ if_id,
+ mask_results_dq_reg_map
+ [bus_num * 8 +
+ bit_num],
+ data_read,
+ MASK_ALL_BITS));
+ data =
+ (data_read
+ [if_id] &
+ 0x1f) |
+ ((data_read
+ [if_id] &
+ 0xe0) << 1);
+ if (curr_min_delay == 0)
+ curr_min_delay =
+ data;
+ else if (data <
+ curr_min_delay)
+ curr_min_delay =
+ data;
+ if (data > data2_write[if_id][bus_num])
+ data2_write
+ [if_id]
+ [bus_num] =
+ data;
+ }
+ }
+
+ if (data2_write[if_id][bus_num] <=
+ (curr_min_delay +
+ MAX_DQ_READ_LEVELING_DELAY)) {
+ per_bit_rl_pup_status[if_id]
+ [bus_num] = 1;
+ }
+ }
+ }
+ }
+
+ /* check if there is need to search new phyreg3 value */
+ if (curr_numb < 2) {
+ /* if there is DLL that is not checked yet */
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1;
+ if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ for (bus_num = 0;
+ bus_num < tm->num_of_bus_per_interface;
+ bus_num++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask,
+ bus_num);
+ if (per_bit_rl_pup_status[if_id]
+ [bus_num] != 1) {
+ /* go to next ADLL value */
+ CHECK_STATUS
+ (ddr3_tip_bus_write
+ (dev_num,
+ ACCESS_TYPE_UNICAST,
+ if_id,
+ ACCESS_TYPE_UNICAST,
+ bus_num, DDR_PHY_DATA,
+ READ_CENTRALIZATION_PHY_REG,
+ (phyreg3_arr[if_id]
+ [bus_num] +
+ adll_array[curr_numb])));
+ break_loop = 1;
+ break;
+ }
+ }
+ if (break_loop)
+ break;
+ }
+ } /* if (curr_numb < 2) */
+ if (!break_loop)
+ break;
+ } /* for ( curr_numb = 0; curr_numb <3; curr_numb++) */
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ for (bus_num = 0; bus_num < tm->num_of_bus_per_interface;
+ bus_num++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, bus_num);
+ if (per_bit_rl_pup_status[if_id][bus_num] == 1)
+ ddr3_tip_bus_write(dev_num,
+ ACCESS_TYPE_UNICAST,
+ if_id,
+ ACCESS_TYPE_UNICAST,
+ bus_num, DDR_PHY_DATA,
+ RL_PHY_REG +
+ CS_REG_VALUE(effective_cs),
+ data2_write[if_id]
+ [bus_num]);
+ else
+ is_any_pup_fail = 1;
+ }
+
+ /* TBD flow does not support multi CS */
+ /*
+ * cs_bitmask = tm->interface_params[if_id].
+ * as_bus_params[bus_num].cs_bitmask;
+ */
+ /* divide by 4 is used for retrieving the CS number */
+ /*
+ * TBD BC2 - what is the PHY address for other
+ * CS ddr3_tip_write_cs_result() ???
+ */
+ /*
+ * find what should be written to PHY
+ * - max delay that is less than threshold
+ */
+ if (is_any_pup_fail == 1) {
+ training_result[training_stage][if_id] = TEST_FAILED;
+ if (debug_mode == 0)
+ return MV_FAIL;
+ }
+ }
+ DEBUG_LEVELING(DEBUG_LEVEL_INFO, ("RL exit read leveling\n"));
+
+ /*
+ * Phase 3: Exit Read Leveling
+ */
+
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ TRAINING_SW_2_REG, (1 << 3), (1 << 3)));
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ TRAINING_SW_1_REG, (1 << 16), (1 << 16)));
+ /* set ODPG to functional */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ODPG_DATA_CONTROL_REG, 0x0, MASK_ALL_BITS));
+ /*
+ * Copy the result from the effective CS search to the real
+ * Functional CS
+ */
+ ddr3_tip_write_cs_result(dev_num, RL_PHY_REG);
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ODPG_DATA_CONTROL_REG, 0x0, MASK_ALL_BITS));
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ /* restore cs enable value */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ CS_ENABLE_REG, cs_enable_reg_val[if_id],
+ MASK_ALL_BITS));
+ if (odt_config != 0) {
+ CHECK_STATUS(ddr3_tip_write_additional_odt_setting
+ (dev_num, if_id));
+ }
+ }
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ if (training_result[training_stage][if_id] == TEST_FAILED)
+ return MV_FAIL;
+ }
+
+ return MV_OK;
+}
+
+int ddr3_tip_calc_cs_mask(u32 dev_num, u32 if_id, u32 effective_cs,
+ u32 *cs_mask)
+{
+ u32 all_bus_cs = 0, same_bus_cs;
+ u32 bus_cnt;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ *cs_mask = same_bus_cs = CS_BIT_MASK;
+
+ /*
+ * In some of the devices (such as BC2), the CS is per pup and there
+ * for mixed mode is valid on like other devices where CS configuration
+ * is per interface.
+ * In order to know that, we do 'Or' and 'And' operation between all
+ * CS (of the pups).
+ * If they are they are not the same then it's mixed mode so all CS
+ * should be configured (when configuring the MRS)
+ */
+ for (bus_cnt = 0; bus_cnt < tm->num_of_bus_per_interface; bus_cnt++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, bus_cnt);
+
+ all_bus_cs |= tm->interface_params[if_id].
+ as_bus_params[bus_cnt].cs_bitmask;
+ same_bus_cs &= tm->interface_params[if_id].
+ as_bus_params[bus_cnt].cs_bitmask;
+
+ /* cs enable is active low */
+ *cs_mask &= ~tm->interface_params[if_id].
+ as_bus_params[bus_cnt].cs_bitmask;
+ }
+
+ if (all_bus_cs == same_bus_cs)
+ *cs_mask = (*cs_mask | (~(1 << effective_cs))) & CS_BIT_MASK;
+
+ return MV_OK;
+}
+
+/*
+ * Dynamic write leveling
+ */
+int ddr3_tip_dynamic_write_leveling(u32 dev_num)
+{
+ u32 reg_data = 0, iter, if_id, bus_cnt;
+ u32 cs_enable_reg_val[MAX_INTERFACE_NUM] = { 0 };
+ u32 cs_mask[MAX_INTERFACE_NUM];
+ u32 read_data_sample_delay_vals[MAX_INTERFACE_NUM] = { 0 };
+ u32 read_data_ready_delay_vals[MAX_INTERFACE_NUM] = { 0 };
+ /* 0 for failure */
+ u32 res_values[MAX_INTERFACE_NUM * MAX_BUS_NUM] = { 0 };
+ u32 test_res = 0; /* 0 - success for all pup */
+ u32 data_read[MAX_INTERFACE_NUM];
+ u8 wl_values[NUM_OF_CS][MAX_BUS_NUM][MAX_INTERFACE_NUM];
+ u16 *mask_results_pup_reg_map = ddr3_tip_get_mask_results_pup_reg_map();
+ u32 cs_mask0[MAX_INTERFACE_NUM] = { 0 };
+ u32 max_cs = hws_ddr3_tip_max_cs_get();
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+
+ training_result[training_stage][if_id] = TEST_SUCCESS;
+
+ /* save Read Data Sample Delay */
+ CHECK_STATUS(ddr3_tip_if_read
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ READ_DATA_SAMPLE_DELAY,
+ read_data_sample_delay_vals, MASK_ALL_BITS));
+ /* save Read Data Ready Delay */
+ CHECK_STATUS(ddr3_tip_if_read
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ READ_DATA_READY_DELAY, read_data_ready_delay_vals,
+ MASK_ALL_BITS));
+ /* save current cs reg val */
+ CHECK_STATUS(ddr3_tip_if_read
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ CS_ENABLE_REG, cs_enable_reg_val, MASK_ALL_BITS));
+ }
+
+ /*
+ * Phase 1: DRAM 2 Write Leveling mode
+ */
+
+ /*Assert 10 refresh commands to DRAM to all CS */
+ for (iter = 0; iter < WL_ITERATION_NUM; iter++) {
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_UNICAST,
+ if_id, SDRAM_OPERATION_REG,
+ (u32)((~(0xf) << 8) | 0x2), 0xf1f));
+ }
+ }
+ /* check controller back to normal */
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ if (ddr3_tip_if_polling
+ (dev_num, ACCESS_TYPE_UNICAST, if_id, 0, 0x1f,
+ SDRAM_OPERATION_REG, MAX_POLLING_ITERATIONS) != MV_OK) {
+ DEBUG_LEVELING(DEBUG_LEVEL_ERROR,
+ ("WL: DDR3 poll failed(3)"));
+ }
+ }
+
+ for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
+ /*enable write leveling to all cs - Q off , WL n */
+ /* calculate interface cs mask */
+ CHECK_STATUS(ddr3_tip_write_mrs_cmd(dev_num, cs_mask0, MRS1_CMD,
+ 0x1000, 0x1080));
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ /* cs enable is active low */
+ ddr3_tip_calc_cs_mask(dev_num, if_id, effective_cs,
+ &cs_mask[if_id]);
+ }
+
+ /* Enable Output buffer to relevant CS - Q on , WL on */
+ CHECK_STATUS(ddr3_tip_write_mrs_cmd
+ (dev_num, cs_mask, MRS1_CMD, 0x80, 0x1080));
+
+ /*enable odt for relevant CS */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ 0x1498, (0x3 << (effective_cs * 2)), 0xf));
+
+ /*
+ * Phase 2: Set training IP to write leveling mode
+ */
+
+ CHECK_STATUS(ddr3_tip_dynamic_write_leveling_seq(dev_num));
+
+ /*
+ * Phase 3: Trigger training
+ */
+
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ODPG_TRAINING_TRIGGER_REG, 0x1, 0x1));
+
+ for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+
+ /* training done */
+ if (ddr3_tip_if_polling
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ (1 << 1), (1 << 1), ODPG_TRAINING_STATUS_REG,
+ MAX_POLLING_ITERATIONS) != MV_OK) {
+ DEBUG_LEVELING(
+ DEBUG_LEVEL_ERROR,
+ ("WL: DDR3 poll (4) failed (Data: 0x%x)\n",
+ reg_data));
+ }
+#if !defined(CONFIG_ARMADA_38X) /*Disabled. JIRA #1498 */
+ else {
+ CHECK_STATUS(ddr3_tip_if_read
+ (dev_num, ACCESS_TYPE_UNICAST,
+ if_id,
+ ODPG_TRAINING_TRIGGER_REG,
+ ®_data, (1 << 2)));
+ if (reg_data != 0) {
+ DEBUG_LEVELING(
+ DEBUG_LEVEL_ERROR,
+ ("WL: WL failed IF %d reg_data=0x%x\n",
+ if_id, reg_data));
+ }
+ }
+#endif
+ }
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ /* training done */
+ if (ddr3_tip_if_polling
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ (1 << 1), (1 << 1), ODPG_TRAINING_STATUS_REG,
+ MAX_POLLING_ITERATIONS) != MV_OK) {
+ DEBUG_LEVELING(
+ DEBUG_LEVEL_ERROR,
+ ("WL: DDR3 poll (4) failed (Data: 0x%x)\n",
+ reg_data));
+ } else {
+#if !defined(CONFIG_ARMADA_38X) /*Disabled. JIRA #1498 */
+ CHECK_STATUS(ddr3_tip_if_read
+ (dev_num, ACCESS_TYPE_UNICAST,
+ if_id,
+ ODPG_TRAINING_STATUS_REG,
+ data_read, (1 << 2)));
+ reg_data = data_read[if_id];
+ if (reg_data != 0) {
+ DEBUG_LEVELING(
+ DEBUG_LEVEL_ERROR,
+ ("WL: WL failed IF %d reg_data=0x%x\n",
+ if_id, reg_data));
+ }
+#endif
+
+ /* check for training completion per bus */
+ for (bus_cnt = 0;
+ bus_cnt < tm->num_of_bus_per_interface;
+ bus_cnt++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask,
+ bus_cnt);
+ /* training status */
+ CHECK_STATUS(ddr3_tip_if_read
+ (dev_num,
+ ACCESS_TYPE_UNICAST,
+ if_id,
+ mask_results_pup_reg_map
+ [bus_cnt], data_read,
+ (1 << 25)));
+ reg_data = data_read[if_id];
+ DEBUG_LEVELING(
+ DEBUG_LEVEL_TRACE,
+ ("WL: IF %d BUS %d reg 0x%x\n",
+ if_id, bus_cnt, reg_data));
+ if (reg_data == 0) {
+ res_values[
+ (if_id *
+ tm->num_of_bus_per_interface)
+ + bus_cnt] = 1;
+ }
+ CHECK_STATUS(ddr3_tip_if_read
+ (dev_num,
+ ACCESS_TYPE_UNICAST,
+ if_id,
+ mask_results_pup_reg_map
+ [bus_cnt], data_read,
+ 0xff));
+ /*
+ * Save the read value that should be
+ * write to PHY register
+ */
+ wl_values[effective_cs]
+ [bus_cnt][if_id] =
+ (u8)data_read[if_id];
+ }
+ }
+ }
+
+ /*
+ * Phase 4: Exit write leveling mode
+ */
+
+ /* disable DQs toggling */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ WR_LEVELING_DQS_PATTERN_REG, 0x0, 0x1));
+
+ /* Update MRS 1 (WL off) */
+ CHECK_STATUS(ddr3_tip_write_mrs_cmd(dev_num, cs_mask0, MRS1_CMD,
+ 0x1000, 0x1080));
+
+ /* Update MRS 1 (return to functional mode - Q on , WL off) */
+ CHECK_STATUS(ddr3_tip_write_mrs_cmd
+ (dev_num, cs_mask0, MRS1_CMD, 0x0, 0x1080));
+
+ /* set phy to normal mode */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ TRAINING_SW_2_REG, 0x5, 0x7));
+
+ /* exit sw override mode */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ TRAINING_SW_2_REG, 0x4, 0x7));
+ }
+
+ /*
+ * Phase 5: Load WL values to each PHY
+ */
+
+ for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ test_res = 0;
+ for (bus_cnt = 0;
+ bus_cnt < tm->num_of_bus_per_interface;
+ bus_cnt++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, bus_cnt);
+ /* check if result == pass */
+ if (res_values
+ [(if_id *
+ tm->num_of_bus_per_interface) +
+ bus_cnt] == 0) {
+ /*
+ * read result control register
+ * according to pup
+ */
+ reg_data =
+ wl_values[effective_cs][bus_cnt]
+ [if_id];
+ /*
+ * Write into write leveling register
+ * ([4:0] ADLL, [8:6] Phase, [15:10]
+ * (centralization) ADLL + 0x10)
+ */
+ reg_data =
+ (reg_data & 0x1f) |
+ (((reg_data & 0xe0) >> 5) << 6) |
+ (((reg_data & 0x1f) +
+ phy_reg1_val) << 10);
+ ddr3_tip_bus_write(
+ dev_num,
+ ACCESS_TYPE_UNICAST,
+ if_id,
+ ACCESS_TYPE_UNICAST,
+ bus_cnt,
+ DDR_PHY_DATA,
+ WL_PHY_REG +
+ effective_cs *
+ CS_REGISTER_ADDR_OFFSET,
+ reg_data);
+ } else {
+ test_res = 1;
+ /*
+ * read result control register
+ * according to pup
+ */
+ CHECK_STATUS(ddr3_tip_if_read
+ (dev_num,
+ ACCESS_TYPE_UNICAST,
+ if_id,
+ mask_results_pup_reg_map
+ [bus_cnt], data_read,
+ 0xff));
+ reg_data = data_read[if_id];
+ DEBUG_LEVELING(
+ DEBUG_LEVEL_ERROR,
+ ("WL: IF %d BUS %d failed, reg 0x%x\n",
+ if_id, bus_cnt, reg_data));
+ }
+ }
+
+ if (test_res != 0) {
+ training_result[training_stage][if_id] =
+ TEST_FAILED;
+ }
+ }
+ }
+ /* Set to 0 after each loop to avoid illegal value may be used */
+ effective_cs = 0;
+
+ /*
+ * Copy the result from the effective CS search to the real
+ * Functional CS
+ */
+ /* ddr3_tip_write_cs_result(dev_num, WL_PHY_REG); */
+ /* restore saved values */
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ /* restore Read Data Sample Delay */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ READ_DATA_SAMPLE_DELAY,
+ read_data_sample_delay_vals[if_id],
+ MASK_ALL_BITS));
+
+ /* restore Read Data Ready Delay */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ READ_DATA_READY_DELAY,
+ read_data_ready_delay_vals[if_id],
+ MASK_ALL_BITS));
+
+ /* enable multi cs */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ CS_ENABLE_REG, cs_enable_reg_val[if_id],
+ MASK_ALL_BITS));
+ }
+
+ /* Disable modt0 for CS0 training - need to adjust for multy CS */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, 0x1498,
+ 0x0, 0xf));
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ if (training_result[training_stage][if_id] == TEST_FAILED)
+ return MV_FAIL;
+ }
+
+ return MV_OK;
+}
+
+/*
+ * Dynamic write leveling supplementary
+ */
+int ddr3_tip_dynamic_write_leveling_supp(u32 dev_num)
+{
+ int adll_offset;
+ u32 if_id, bus_id, data, data_tmp;
+ int is_if_fail = 0;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ is_if_fail = 0;
+
+ for (bus_id = 0; bus_id < GET_TOPOLOGY_NUM_OF_BUSES();
+ bus_id++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, bus_id);
+ wr_supp_res[if_id][bus_id].is_pup_fail = 1;
+ CHECK_STATUS(ddr3_tip_bus_read
+ (dev_num, if_id, ACCESS_TYPE_UNICAST,
+ bus_id, DDR_PHY_DATA,
+ WRITE_CENTRALIZATION_PHY_REG +
+ effective_cs * CS_REGISTER_ADDR_OFFSET,
+ &data));
+ DEBUG_LEVELING(
+ DEBUG_LEVEL_TRACE,
+ ("WL Supp: adll_offset=0 data delay = %d\n",
+ data));
+ if (ddr3_tip_wl_supp_align_phase_shift
+ (dev_num, if_id, bus_id, 0, 0) == MV_OK) {
+ DEBUG_LEVELING(
+ DEBUG_LEVEL_TRACE,
+ ("WL Supp: IF %d bus_id %d adll_offset=0 Success !\n",
+ if_id, bus_id));
+ continue;
+ }
+
+ /* change adll */
+ adll_offset = 5;
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ ACCESS_TYPE_UNICAST, bus_id, DDR_PHY_DATA,
+ WRITE_CENTRALIZATION_PHY_REG +
+ effective_cs * CS_REGISTER_ADDR_OFFSET,
+ data + adll_offset));
+ CHECK_STATUS(ddr3_tip_bus_read
+ (dev_num, if_id, ACCESS_TYPE_UNICAST,
+ bus_id, DDR_PHY_DATA,
+ WRITE_CENTRALIZATION_PHY_REG +
+ effective_cs * CS_REGISTER_ADDR_OFFSET,
+ &data_tmp));
+ DEBUG_LEVELING(
+ DEBUG_LEVEL_TRACE,
+ ("WL Supp: adll_offset= %d data delay = %d\n",
+ adll_offset, data_tmp));
+
+ if (ddr3_tip_wl_supp_align_phase_shift
+ (dev_num, if_id, bus_id, adll_offset, 0) == MV_OK) {
+ DEBUG_LEVELING(
+ DEBUG_LEVEL_TRACE,
+ ("WL Supp: IF %d bus_id %d adll_offset= %d Success !\n",
+ if_id, bus_id, adll_offset));
+ continue;
+ }
+
+ /* change adll */
+ adll_offset = -5;
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ ACCESS_TYPE_UNICAST, bus_id, DDR_PHY_DATA,
+ WRITE_CENTRALIZATION_PHY_REG +
+ effective_cs * CS_REGISTER_ADDR_OFFSET,
+ data + adll_offset));
+ CHECK_STATUS(ddr3_tip_bus_read
+ (dev_num, if_id, ACCESS_TYPE_UNICAST,
+ bus_id, DDR_PHY_DATA,
+ WRITE_CENTRALIZATION_PHY_REG +
+ effective_cs * CS_REGISTER_ADDR_OFFSET,
+ &data_tmp));
+ DEBUG_LEVELING(
+ DEBUG_LEVEL_TRACE,
+ ("WL Supp: adll_offset= %d data delay = %d\n",
+ adll_offset, data_tmp));
+ if (ddr3_tip_wl_supp_align_phase_shift
+ (dev_num, if_id, bus_id, adll_offset, 0) == MV_OK) {
+ DEBUG_LEVELING(
+ DEBUG_LEVEL_TRACE,
+ ("WL Supp: IF %d bus_id %d adll_offset= %d Success !\n",
+ if_id, bus_id, adll_offset));
+ continue;
+ } else {
+ DEBUG_LEVELING(
+ DEBUG_LEVEL_ERROR,
+ ("WL Supp: IF %d bus_id %d Failed !\n",
+ if_id, bus_id));
+ is_if_fail = 1;
+ }
+ }
+ DEBUG_LEVELING(DEBUG_LEVEL_TRACE,
+ ("WL Supp: IF %d bus_id %d is_pup_fail %d\n",
+ if_id, bus_id, is_if_fail));
+
+ if (is_if_fail == 1) {
+ DEBUG_LEVELING(DEBUG_LEVEL_ERROR,
+ ("WL Supp: IF %d failed\n", if_id));
+ training_result[training_stage][if_id] = TEST_FAILED;
+ } else {
+ training_result[training_stage][if_id] = TEST_SUCCESS;
+ }
+ }
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ if (training_result[training_stage][if_id] == TEST_FAILED)
+ return MV_FAIL;
+ }
+
+ return MV_OK;
+}
+
+/*
+ * Phase Shift
+ */
+static int ddr3_tip_wl_supp_align_phase_shift(u32 dev_num, u32 if_id,
+ u32 bus_id, u32 offset,
+ u32 bus_id_delta)
+{
+ wr_supp_res[if_id][bus_id].stage = PHASE_SHIFT;
+ if (ddr3_tip_xsb_compare_test(dev_num, if_id, bus_id,
+ 0, bus_id_delta) == MV_OK) {
+ wr_supp_res[if_id][bus_id].is_pup_fail = 0;
+ return MV_OK;
+ } else if (ddr3_tip_xsb_compare_test(dev_num, if_id, bus_id,
+ ONE_CLOCK_ERROR_SHIFT,
+ bus_id_delta) == MV_OK) {
+ /* 1 clock error */
+ wr_supp_res[if_id][bus_id].stage = CLOCK_SHIFT;
+ DEBUG_LEVELING(DEBUG_LEVEL_TRACE,
+ ("Supp: 1 error clock for if %d pup %d with ofsset %d success\n",
+ if_id, bus_id, offset));
+ ddr3_tip_wl_supp_one_clk_err_shift(dev_num, if_id, bus_id, 0);
+ wr_supp_res[if_id][bus_id].is_pup_fail = 0;
+ return MV_OK;
+ } else if (ddr3_tip_xsb_compare_test(dev_num, if_id, bus_id,
+ ALIGN_ERROR_SHIFT,
+ bus_id_delta) == MV_OK) {
+ /* align error */
+ DEBUG_LEVELING(DEBUG_LEVEL_TRACE,
+ ("Supp: align error for if %d pup %d with ofsset %d success\n",
+ if_id, bus_id, offset));
+ wr_supp_res[if_id][bus_id].stage = ALIGN_SHIFT;
+ ddr3_tip_wl_supp_align_err_shift(dev_num, if_id, bus_id, 0);
+ wr_supp_res[if_id][bus_id].is_pup_fail = 0;
+ return MV_OK;
+ } else {
+ wr_supp_res[if_id][bus_id].is_pup_fail = 1;
+ return MV_FAIL;
+ }
+}
+
+/*
+ * Compare Test
+ */
+static int ddr3_tip_xsb_compare_test(u32 dev_num, u32 if_id, u32 bus_id,
+ u32 edge_offset, u32 bus_id_delta)
+{
+ u32 num_of_succ_byte_compare, word_in_pattern, abs_offset;
+ u32 word_offset, i;
+ u32 read_pattern[TEST_PATTERN_LENGTH * 2];
+ struct pattern_info *pattern_table = ddr3_tip_get_pattern_table();
+ u32 pattern_test_pattern_table[8];
+
+ for (i = 0; i < 8; i++) {
+ pattern_test_pattern_table[i] =
+ pattern_table_get_word(dev_num, PATTERN_TEST, (u8)i);
+ }
+
+ /* extern write, than read and compare */
+ CHECK_STATUS(ddr3_tip_ext_write
+ (dev_num, if_id,
+ (pattern_table[PATTERN_TEST].start_addr +
+ ((SDRAM_CS_SIZE + 1) * effective_cs)), 1,
+ pattern_test_pattern_table));
+
+ CHECK_STATUS(ddr3_tip_reset_fifo_ptr(dev_num));
+
+ CHECK_STATUS(ddr3_tip_ext_read
+ (dev_num, if_id,
+ (pattern_table[PATTERN_TEST].start_addr +
+ ((SDRAM_CS_SIZE + 1) * effective_cs)), 1, read_pattern));
+
+ DEBUG_LEVELING(
+ DEBUG_LEVEL_TRACE,
+ ("XSB-compt: IF %d bus_id %d 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
+ if_id, bus_id, read_pattern[0], read_pattern[1],
+ read_pattern[2], read_pattern[3], read_pattern[4],
+ read_pattern[5], read_pattern[6], read_pattern[7]));
+
+ /* compare byte per pup */
+ num_of_succ_byte_compare = 0;
+ for (word_in_pattern = start_xsb_offset;
+ word_in_pattern < (TEST_PATTERN_LENGTH * 2); word_in_pattern++) {
+ word_offset = word_in_pattern + edge_offset;
+ if ((word_offset > (TEST_PATTERN_LENGTH * 2 - 1)) ||
+ (word_offset < 0))
+ continue;
+
+ if ((read_pattern[word_in_pattern] & pup_mask_table[bus_id]) ==
+ (pattern_test_pattern_table[word_offset] &
+ pup_mask_table[bus_id]))
+ num_of_succ_byte_compare++;
+ }
+
+ abs_offset = (edge_offset > 0) ? edge_offset : -edge_offset;
+ if (num_of_succ_byte_compare == ((TEST_PATTERN_LENGTH * 2) -
+ abs_offset - start_xsb_offset)) {
+ DEBUG_LEVELING(
+ DEBUG_LEVEL_TRACE,
+ ("XSB-compt: IF %d bus_id %d num_of_succ_byte_compare %d - Success\n",
+ if_id, bus_id, num_of_succ_byte_compare));
+ return MV_OK;
+ } else {
+ DEBUG_LEVELING(
+ DEBUG_LEVEL_TRACE,
+ ("XSB-compt: IF %d bus_id %d num_of_succ_byte_compare %d - Fail !\n",
+ if_id, bus_id, num_of_succ_byte_compare));
+
+ DEBUG_LEVELING(
+ DEBUG_LEVEL_TRACE,
+ ("XSB-compt: expected 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
+ pattern_test_pattern_table[0],
+ pattern_test_pattern_table[1],
+ pattern_test_pattern_table[2],
+ pattern_test_pattern_table[3],
+ pattern_test_pattern_table[4],
+ pattern_test_pattern_table[5],
+ pattern_test_pattern_table[6],
+ pattern_test_pattern_table[7]));
+ DEBUG_LEVELING(
+ DEBUG_LEVEL_TRACE,
+ ("XSB-compt: recieved 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
+ read_pattern[0], read_pattern[1],
+ read_pattern[2], read_pattern[3],
+ read_pattern[4], read_pattern[5],
+ read_pattern[6], read_pattern[7]));
+
+ DEBUG_LEVELING(
+ DEBUG_LEVEL_TRACE,
+ ("XSB-compt: IF %d bus_id %d num_of_succ_byte_compare %d - Fail !\n",
+ if_id, bus_id, num_of_succ_byte_compare));
+
+ return MV_FAIL;
+ }
+}
+
+/*
+ * Clock error shift - function moves the write leveling delay 1cc forward
+ */
+static int ddr3_tip_wl_supp_one_clk_err_shift(u32 dev_num, u32 if_id,
+ u32 bus_id, u32 bus_id_delta)
+{
+ int phase, adll;
+ u32 data;
+ DEBUG_LEVELING(DEBUG_LEVEL_TRACE, ("One_clk_err_shift\n"));
+
+ CHECK_STATUS(ddr3_tip_bus_read
+ (dev_num, if_id, ACCESS_TYPE_UNICAST, bus_id,
+ DDR_PHY_DATA, WL_PHY_REG, &data));
+ phase = ((data >> 6) & 0x7);
+ adll = data & 0x1f;
+ DEBUG_LEVELING(DEBUG_LEVEL_TRACE,
+ ("One_clk_err_shift: IF %d bus_id %d phase %d adll %d\n",
+ if_id, bus_id, phase, adll));
+
+ if ((phase == 0) || (phase == 1)) {
+ CHECK_STATUS(ddr3_tip_bus_read_modify_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id, bus_id,
+ DDR_PHY_DATA, 0, (phase + 2), 0x1f));
+ } else if (phase == 2) {
+ if (adll < 6) {
+ data = (3 << 6) + (0x1f);
+ CHECK_STATUS(ddr3_tip_bus_read_modify_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ bus_id, DDR_PHY_DATA, 0, data,
+ (0x7 << 6 | 0x1f)));
+ data = 0x2f;
+ CHECK_STATUS(ddr3_tip_bus_read_modify_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ bus_id, DDR_PHY_DATA, 1, data, 0x3f));
+ }
+ } else {
+ /* phase 3 */
+ return MV_FAIL;
+ }
+
+ return MV_OK;
+}
+
+/*
+ * Align error shift
+ */
+static int ddr3_tip_wl_supp_align_err_shift(u32 dev_num, u32 if_id,
+ u32 bus_id, u32 bus_id_delta)
+{
+ int phase, adll;
+ u32 data;
+
+ /* Shift WL result 1 phase back */
+ CHECK_STATUS(ddr3_tip_bus_read(dev_num, if_id, ACCESS_TYPE_UNICAST,
+ bus_id, DDR_PHY_DATA, WL_PHY_REG,
+ &data));
+ phase = ((data >> 6) & 0x7);
+ adll = data & 0x1f;
+ DEBUG_LEVELING(
+ DEBUG_LEVEL_TRACE,
+ ("Wl_supp_align_err_shift: IF %d bus_id %d phase %d adll %d\n",
+ if_id, bus_id, phase, adll));
+
+ if (phase < 2) {
+ if (adll > 0x1a) {
+ if (phase == 0)
+ return MV_FAIL;
+
+ if (phase == 1) {
+ data = 0;
+ CHECK_STATUS(ddr3_tip_bus_read_modify_write
+ (dev_num, ACCESS_TYPE_UNICAST,
+ if_id, bus_id, DDR_PHY_DATA,
+ 0, data, (0x7 << 6 | 0x1f)));
+ data = 0xf;
+ CHECK_STATUS(ddr3_tip_bus_read_modify_write
+ (dev_num, ACCESS_TYPE_UNICAST,
+ if_id, bus_id, DDR_PHY_DATA,
+ 1, data, 0x1f));
+ return MV_OK;
+ }
+ } else {
+ return MV_FAIL;
+ }
+ } else if ((phase == 2) || (phase == 3)) {
+ phase = phase - 2;
+ data = (phase << 6) + (adll & 0x1f);
+ CHECK_STATUS(ddr3_tip_bus_read_modify_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id, bus_id,
+ DDR_PHY_DATA, 0, data, (0x7 << 6 | 0x1f)));
+ return MV_OK;
+ } else {
+ DEBUG_LEVELING(DEBUG_LEVEL_ERROR,
+ ("Wl_supp_align_err_shift: unexpected phase\n"));
+
+ return MV_FAIL;
+ }
+
+ return MV_OK;
+}
+
+/*
+ * Dynamic write leveling sequence
+ */
+static int ddr3_tip_dynamic_write_leveling_seq(u32 dev_num)
+{
+ u32 bus_id, dq_id;
+ u16 *mask_results_pup_reg_map = ddr3_tip_get_mask_results_pup_reg_map();
+ u16 *mask_results_dq_reg_map = ddr3_tip_get_mask_results_dq_reg();
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ TRAINING_SW_2_REG, 0x1, 0x5));
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ TRAINING_WRITE_LEVELING_REG, 0x50, 0xff));
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ TRAINING_WRITE_LEVELING_REG, 0x5c, 0xff));
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ODPG_TRAINING_CONTROL_REG, 0x381b82, 0x3c3faf));
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ODPG_OBJ1_OPCODE_REG, (0x3 << 25), (0x3ffff << 9)));
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ODPG_OBJ1_ITER_CNT_REG, 0x80, 0xffff));
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ODPG_WRITE_LEVELING_DONE_CNTR_REG, 0x14, 0xff));
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ TRAINING_WRITE_LEVELING_REG, 0xff5c, 0xffff));
+
+ /* mask PBS */
+ for (dq_id = 0; dq_id < MAX_DQ_NUM; dq_id++) {
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ mask_results_dq_reg_map[dq_id], 0x1 << 24,
+ 0x1 << 24));
+ }
+
+ /* Mask all results */
+ for (bus_id = 0; bus_id < tm->num_of_bus_per_interface; bus_id++) {
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ mask_results_pup_reg_map[bus_id], 0x1 << 24,
+ 0x1 << 24));
+ }
+
+ /* Unmask only wanted */
+ for (bus_id = 0; bus_id < tm->num_of_bus_per_interface; bus_id++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, bus_id);
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ mask_results_pup_reg_map[bus_id], 0, 0x1 << 24));
+ }
+
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ WR_LEVELING_DQS_PATTERN_REG, 0x1, 0x1));
+
+ return MV_OK;
+}
+
+/*
+ * Dynamic read leveling sequence
+ */
+static int ddr3_tip_dynamic_read_leveling_seq(u32 dev_num)
+{
+ u32 bus_id, dq_id;
+ u16 *mask_results_pup_reg_map = ddr3_tip_get_mask_results_pup_reg_map();
+ u16 *mask_results_dq_reg_map = ddr3_tip_get_mask_results_dq_reg();
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ /* mask PBS */
+ for (dq_id = 0; dq_id < MAX_DQ_NUM; dq_id++) {
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ mask_results_dq_reg_map[dq_id], 0x1 << 24,
+ 0x1 << 24));
+ }
+
+ /* Mask all results */
+ for (bus_id = 0; bus_id < tm->num_of_bus_per_interface; bus_id++) {
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ mask_results_pup_reg_map[bus_id], 0x1 << 24,
+ 0x1 << 24));
+ }
+
+ /* Unmask only wanted */
+ for (bus_id = 0; bus_id < tm->num_of_bus_per_interface; bus_id++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, bus_id);
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ mask_results_pup_reg_map[bus_id], 0, 0x1 << 24));
+ }
+
+ return MV_OK;
+}
+
+/*
+ * Dynamic read leveling sequence
+ */
+static int ddr3_tip_dynamic_per_bit_read_leveling_seq(u32 dev_num)
+{
+ u32 bus_id, dq_id;
+ u16 *mask_results_pup_reg_map = ddr3_tip_get_mask_results_pup_reg_map();
+ u16 *mask_results_dq_reg_map = ddr3_tip_get_mask_results_dq_reg();
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ /* mask PBS */
+ for (dq_id = 0; dq_id < MAX_DQ_NUM; dq_id++) {
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ mask_results_dq_reg_map[dq_id], 0x1 << 24,
+ 0x1 << 24));
+ }
+
+ /* Mask all results */
+ for (bus_id = 0; bus_id < tm->num_of_bus_per_interface; bus_id++) {
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ mask_results_pup_reg_map[bus_id], 0x1 << 24,
+ 0x1 << 24));
+ }
+
+ /* Unmask only wanted */
+ for (dq_id = 0; dq_id < MAX_DQ_NUM; dq_id++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, dq_id / 8);
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ mask_results_dq_reg_map[dq_id], 0x0 << 24,
+ 0x1 << 24));
+ }
+
+ return MV_OK;
+}
+
+/*
+ * Print write leveling supplementary results
+ */
+int ddr3_tip_print_wl_supp_result(u32 dev_num)
+{
+ u32 bus_id = 0, if_id = 0;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ DEBUG_LEVELING(DEBUG_LEVEL_INFO,
+ ("I/F0 PUP0 Result[0 - success, 1-fail] ...\n"));
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ for (bus_id = 0; bus_id < tm->num_of_bus_per_interface;
+ bus_id++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, bus_id);
+ DEBUG_LEVELING(DEBUG_LEVEL_INFO,
+ ("%d ,", wr_supp_res[if_id]
+ [bus_id].is_pup_fail));
+ }
+ }
+ DEBUG_LEVELING(
+ DEBUG_LEVEL_INFO,
+ ("I/F0 PUP0 Stage[0-phase_shift, 1-clock_shift, 2-align_shift] ...\n"));
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ for (bus_id = 0; bus_id < tm->num_of_bus_per_interface;
+ bus_id++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, bus_id);
+ DEBUG_LEVELING(DEBUG_LEVEL_INFO,
+ ("%d ,", wr_supp_res[if_id]
+ [bus_id].stage));
+ }
+ }
+
+ return MV_OK;
+}
diff --git a/drivers/ddr/marvell/a38x/old/ddr3_training_leveling.h b/drivers/ddr/marvell/a38x/old/ddr3_training_leveling.h
new file mode 100644
index 0000000..f2b4177
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/ddr3_training_leveling.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _DDR3_TRAINING_LEVELING_H_
+#define _DDR3_TRAINING_LEVELING_H_
+
+#define MAX_DQ_READ_LEVELING_DELAY 15
+
+int ddr3_tip_print_wl_supp_result(u32 dev_num);
+int ddr3_tip_calc_cs_mask(u32 dev_num, u32 if_id, u32 effective_cs,
+ u32 *cs_mask);
+u32 hws_ddr3_tip_max_cs_get(void);
+
+#endif /* _DDR3_TRAINING_LEVELING_H_ */
diff --git a/drivers/ddr/marvell/a38x/old/ddr3_training_pbs.c b/drivers/ddr/marvell/a38x/old/ddr3_training_pbs.c
new file mode 100644
index 0000000..c6f58c9
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/ddr3_training_pbs.c
@@ -0,0 +1,994 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+#include "ddr3_init.h"
+
+#define TYPICAL_PBS_VALUE 12
+
+u32 nominal_adll[MAX_INTERFACE_NUM * MAX_BUS_NUM];
+enum hws_training_ip_stat train_status[MAX_INTERFACE_NUM];
+u8 result_mat[MAX_INTERFACE_NUM][MAX_BUS_NUM][BUS_WIDTH_IN_BITS];
+u8 result_mat_rx_dqs[MAX_INTERFACE_NUM][MAX_BUS_NUM][MAX_CS_NUM];
+/* 4-EEWA, 3-EWA, 2-SWA, 1-Fail, 0-Pass */
+u8 result_all_bit[MAX_BUS_NUM * BUS_WIDTH_IN_BITS * MAX_INTERFACE_NUM];
+u8 max_pbs_per_pup[MAX_INTERFACE_NUM][MAX_BUS_NUM];
+u8 min_pbs_per_pup[MAX_INTERFACE_NUM][MAX_BUS_NUM];
+u8 max_adll_per_pup[MAX_INTERFACE_NUM][MAX_BUS_NUM];
+u8 min_adll_per_pup[MAX_INTERFACE_NUM][MAX_BUS_NUM];
+u32 pbsdelay_per_pup[NUM_OF_PBS_MODES][MAX_INTERFACE_NUM][MAX_BUS_NUM];
+u8 adll_shift_lock[MAX_INTERFACE_NUM][MAX_BUS_NUM];
+u8 adll_shift_val[MAX_INTERFACE_NUM][MAX_BUS_NUM];
+enum hws_pattern pbs_pattern = PATTERN_VREF;
+static u8 pup_state[MAX_INTERFACE_NUM][MAX_BUS_NUM];
+
+/*
+ * Name: ddr3_tip_pbs
+ * Desc: PBS
+ * Args: TBD
+ * Notes:
+ * Returns: OK if success, other error code if fail.
+ */
+int ddr3_tip_pbs(u32 dev_num, enum pbs_dir pbs_mode)
+{
+ u32 res0[MAX_INTERFACE_NUM];
+ int adll_tap = MEGA / freq_val[medium_freq] / 64;
+ int pad_num = 0;
+ enum hws_search_dir search_dir =
+ (pbs_mode == PBS_RX_MODE) ? HWS_HIGH2LOW : HWS_LOW2HIGH;
+ enum hws_dir dir = (pbs_mode == PBS_RX_MODE) ? OPER_READ : OPER_WRITE;
+ int iterations = (pbs_mode == PBS_RX_MODE) ? 31 : 63;
+ u32 res_valid_mask = (pbs_mode == PBS_RX_MODE) ? 0x1f : 0x3f;
+ int init_val = (search_dir == HWS_LOW2HIGH) ? 0 : iterations;
+ enum hws_edge_compare search_edge = EDGE_FP;
+ u32 pup = 0, bit = 0, if_id = 0, all_lock = 0, cs_num = 0;
+ int reg_addr = 0;
+ u32 validation_val = 0;
+ u32 cs_enable_reg_val[MAX_INTERFACE_NUM];
+ u16 *mask_results_dq_reg_map = ddr3_tip_get_mask_results_dq_reg();
+ u8 temp = 0;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ /* save current cs enable reg val */
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+
+ /* save current cs enable reg val */
+ CHECK_STATUS(ddr3_tip_if_read
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ CS_ENABLE_REG, cs_enable_reg_val, MASK_ALL_BITS));
+
+ /* enable single cs */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ CS_ENABLE_REG, (1 << 3), (1 << 3)));
+ }
+
+ reg_addr = (pbs_mode == PBS_RX_MODE) ?
+ (READ_CENTRALIZATION_PHY_REG +
+ (effective_cs * CS_REGISTER_ADDR_OFFSET)) :
+ (WRITE_CENTRALIZATION_PHY_REG +
+ (effective_cs * CS_REGISTER_ADDR_OFFSET));
+ read_adll_value(nominal_adll, reg_addr, MASK_ALL_BITS);
+
+ /* stage 1 shift ADLL */
+ ddr3_tip_ip_training(dev_num, ACCESS_TYPE_MULTICAST,
+ PARAM_NOT_CARE, ACCESS_TYPE_MULTICAST,
+ PARAM_NOT_CARE, RESULT_PER_BIT,
+ HWS_CONTROL_ELEMENT_ADLL, search_dir, dir,
+ tm->if_act_mask, init_val, iterations,
+ pbs_pattern, search_edge, CS_SINGLE, cs_num,
+ train_status);
+ validation_val = (pbs_mode == PBS_RX_MODE) ? 0x1f : 0;
+ for (pup = 0; pup < tm->num_of_bus_per_interface; pup++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, pup);
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ min_adll_per_pup[if_id][pup] =
+ (pbs_mode == PBS_RX_MODE) ? 0x1f : 0x3f;
+ pup_state[if_id][pup] = 0x3;
+ adll_shift_lock[if_id][pup] = 1;
+ max_adll_per_pup[if_id][pup] = 0x0;
+ }
+ }
+
+ /* EBA */
+ for (pup = 0; pup < tm->num_of_bus_per_interface; pup++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, pup);
+ for (bit = 0; bit < BUS_WIDTH_IN_BITS; bit++) {
+ CHECK_STATUS(ddr3_tip_if_read
+ (dev_num, ACCESS_TYPE_MULTICAST,
+ PARAM_NOT_CARE,
+ mask_results_dq_reg_map[
+ bit + pup * BUS_WIDTH_IN_BITS],
+ res0, MASK_ALL_BITS));
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1;
+ if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ DEBUG_PBS_ENGINE(DEBUG_LEVEL_TRACE,
+ ("FP I/F %d, bit:%d, pup:%d res0 0x%x\n",
+ if_id, bit, pup,
+ res0[if_id]));
+ if (pup_state[if_id][pup] != 3)
+ continue;
+ /* if not EBA state than move to next pup */
+
+ if ((res0[if_id] & 0x2000000) == 0) {
+ DEBUG_PBS_ENGINE(DEBUG_LEVEL_TRACE,
+ ("-- Fail Training IP\n"));
+ /* training machine failed */
+ pup_state[if_id][pup] = 1;
+ adll_shift_lock[if_id][pup] = 0;
+ continue;
+ }
+
+ else if ((res0[if_id] & res_valid_mask) ==
+ validation_val) {
+ DEBUG_PBS_ENGINE(DEBUG_LEVEL_TRACE,
+ ("-- FAIL EBA %d %d %d %d\n",
+ if_id, bit, pup,
+ res0[if_id]));
+ pup_state[if_id][pup] = 4;
+ /* this pup move to EEBA */
+ adll_shift_lock[if_id][pup] = 0;
+ continue;
+ } else {
+ /*
+ * The search ended in Pass we need
+ * Fail
+ */
+ res0[if_id] =
+ (pbs_mode == PBS_RX_MODE) ?
+ ((res0[if_id] &
+ res_valid_mask) + 1) :
+ ((res0[if_id] &
+ res_valid_mask) - 1);
+ max_adll_per_pup[if_id][pup] =
+ (max_adll_per_pup[if_id][pup] <
+ res0[if_id]) ?
+ (u8)res0[if_id] :
+ max_adll_per_pup[if_id][pup];
+ min_adll_per_pup[if_id][pup] =
+ (res0[if_id] >
+ min_adll_per_pup[if_id][pup]) ?
+ min_adll_per_pup[if_id][pup] :
+ (u8)
+ res0[if_id];
+ /*
+ * vs the Rx we are searching for the
+ * smallest value of DQ shift so all
+ * Bus would fail
+ */
+ adll_shift_val[if_id][pup] =
+ (pbs_mode == PBS_RX_MODE) ?
+ max_adll_per_pup[if_id][pup] :
+ min_adll_per_pup[if_id][pup];
+ }
+ }
+ }
+ }
+
+ /* EEBA */
+ for (pup = 0; pup < tm->num_of_bus_per_interface; pup++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, pup);
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+
+ if (pup_state[if_id][pup] != 4)
+ continue;
+ /*
+ * if pup state different from EEBA than move to
+ * next pup
+ */
+ reg_addr = (pbs_mode == PBS_RX_MODE) ?
+ (0x54 + effective_cs * 0x10) :
+ (0x14 + effective_cs * 0x10);
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ ACCESS_TYPE_UNICAST, pup, DDR_PHY_DATA,
+ reg_addr, 0x1f));
+ reg_addr = (pbs_mode == PBS_RX_MODE) ?
+ (0x55 + effective_cs * 0x10) :
+ (0x15 + effective_cs * 0x10);
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ ACCESS_TYPE_UNICAST, pup, DDR_PHY_DATA,
+ reg_addr, 0x1f));
+ /* initialize the Edge2 Max. */
+ adll_shift_val[if_id][pup] = 0;
+ min_adll_per_pup[if_id][pup] =
+ (pbs_mode == PBS_RX_MODE) ? 0x1f : 0x3f;
+ max_adll_per_pup[if_id][pup] = 0x0;
+
+ ddr3_tip_ip_training(dev_num, ACCESS_TYPE_MULTICAST,
+ PARAM_NOT_CARE,
+ ACCESS_TYPE_MULTICAST,
+ PARAM_NOT_CARE, RESULT_PER_BIT,
+ HWS_CONTROL_ELEMENT_ADLL,
+ search_dir, dir,
+ tm->if_act_mask, init_val,
+ iterations, pbs_pattern,
+ search_edge, CS_SINGLE, cs_num,
+ train_status);
+ DEBUG_PBS_ENGINE(DEBUG_LEVEL_INFO,
+ ("ADLL shift results:\n"));
+
+ for (bit = 0; bit < BUS_WIDTH_IN_BITS; bit++) {
+ CHECK_STATUS(ddr3_tip_if_read
+ (dev_num, ACCESS_TYPE_MULTICAST,
+ PARAM_NOT_CARE,
+ mask_results_dq_reg_map[
+ bit + pup *
+ BUS_WIDTH_IN_BITS],
+ res0, MASK_ALL_BITS));
+ DEBUG_PBS_ENGINE(DEBUG_LEVEL_TRACE,
+ ("FP I/F %d, bit:%d, pup:%d res0 0x%x\n",
+ if_id, bit, pup,
+ res0[if_id]));
+
+ if ((res0[if_id] & 0x2000000) == 0) {
+ DEBUG_PBS_ENGINE(DEBUG_LEVEL_TRACE,
+ (" -- EEBA Fail\n"));
+ bit = BUS_WIDTH_IN_BITS;
+ /* exit bit loop */
+ DEBUG_PBS_ENGINE(DEBUG_LEVEL_TRACE,
+ ("-- EEBA Fail Training IP\n"));
+ /*
+ * training machine failed but pass
+ * before in the EBA so maybe the DQS
+ * shift change env.
+ */
+ pup_state[if_id][pup] = 2;
+ adll_shift_lock[if_id][pup] = 0;
+ reg_addr = (pbs_mode == PBS_RX_MODE) ?
+ (0x54 + effective_cs * 0x10) :
+ (0x14 + effective_cs * 0x10);
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num,
+ ACCESS_TYPE_UNICAST,
+ if_id,
+ ACCESS_TYPE_UNICAST, pup,
+ DDR_PHY_DATA, reg_addr,
+ 0x0));
+ reg_addr = (pbs_mode == PBS_RX_MODE) ?
+ (0x55 + effective_cs * 0x10) :
+ (0x15 + effective_cs * 0x10);
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num,
+ ACCESS_TYPE_UNICAST,
+ if_id,
+ ACCESS_TYPE_UNICAST, pup,
+ DDR_PHY_DATA, reg_addr,
+ 0x0));
+ continue;
+ } else if ((res0[if_id] & res_valid_mask) ==
+ validation_val) {
+ /* exit bit loop */
+ bit = BUS_WIDTH_IN_BITS;
+ DEBUG_PBS_ENGINE(DEBUG_LEVEL_TRACE,
+ ("-- FAIL EEBA\n"));
+ /* this pup move to SBA */
+ pup_state[if_id][pup] = 2;
+ adll_shift_lock[if_id][pup] = 0;
+ reg_addr = (pbs_mode == PBS_RX_MODE) ?
+ (0x54 + effective_cs * 0x10) :
+ (0x14 + effective_cs * 0x10);
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num,
+ ACCESS_TYPE_UNICAST,
+ if_id,
+ ACCESS_TYPE_UNICAST, pup,
+ DDR_PHY_DATA, reg_addr,
+ 0x0));
+ reg_addr = (pbs_mode == PBS_RX_MODE) ?
+ (0x55 + effective_cs * 0x10) :
+ (0x15 + effective_cs * 0x10);
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num,
+ ACCESS_TYPE_UNICAST,
+ if_id,
+ ACCESS_TYPE_UNICAST, pup,
+ DDR_PHY_DATA, reg_addr,
+ 0x0));
+ continue;
+ } else {
+ adll_shift_lock[if_id][pup] = 1;
+ /*
+ * The search ended in Pass we need
+ * Fail
+ */
+ res0[if_id] =
+ (pbs_mode == PBS_RX_MODE) ?
+ ((res0[if_id] &
+ res_valid_mask) + 1) :
+ ((res0[if_id] &
+ res_valid_mask) - 1);
+ max_adll_per_pup[if_id][pup] =
+ (max_adll_per_pup[if_id][pup] <
+ res0[if_id]) ?
+ (u8)res0[if_id] :
+ max_adll_per_pup[if_id][pup];
+ min_adll_per_pup[if_id][pup] =
+ (res0[if_id] >
+ min_adll_per_pup[if_id][pup]) ?
+ min_adll_per_pup[if_id][pup] :
+ (u8)res0[if_id];
+ /*
+ * vs the Rx we are searching for the
+ * smallest value of DQ shift so all Bus
+ * would fail
+ */
+ adll_shift_val[if_id][pup] =
+ (pbs_mode == PBS_RX_MODE) ?
+ max_adll_per_pup[if_id][pup] :
+ min_adll_per_pup[if_id][pup];
+ }
+ }
+ }
+ }
+
+ /* Print Stage result */
+ for (pup = 0; pup < tm->num_of_bus_per_interface; pup++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, pup);
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ DEBUG_PBS_ENGINE(DEBUG_LEVEL_TRACE,
+ ("FP I/F %d, ADLL Shift for EBA: pup[%d] Lock status = %d Lock Val = %d,%d\n",
+ if_id, pup,
+ adll_shift_lock[if_id][pup],
+ max_adll_per_pup[if_id][pup],
+ min_adll_per_pup[if_id][pup]));
+ }
+ }
+ DEBUG_PBS_ENGINE(DEBUG_LEVEL_INFO,
+ ("Update ADLL Shift of all pups:\n"));
+
+ for (pup = 0; pup < tm->num_of_bus_per_interface; pup++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, pup);
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ if (adll_shift_lock[if_id][pup] != 1)
+ continue;
+ /* if pup not locked continue to next pup */
+
+ reg_addr = (pbs_mode == PBS_RX_MODE) ?
+ (0x3 + effective_cs * 4) :
+ (0x1 + effective_cs * 4);
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ ACCESS_TYPE_UNICAST, pup, DDR_PHY_DATA,
+ reg_addr, adll_shift_val[if_id][pup]));
+ DEBUG_PBS_ENGINE(DEBUG_LEVEL_TRACE,
+ ("FP I/F %d, Pup[%d] = %d\n", if_id,
+ pup, adll_shift_val[if_id][pup]));
+ }
+ }
+
+ /* PBS EEBA&EBA */
+ /* Start the Per Bit Skew search */
+ for (pup = 0; pup < tm->num_of_bus_per_interface; pup++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, pup);
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ max_pbs_per_pup[if_id][pup] = 0x0;
+ min_pbs_per_pup[if_id][pup] = 0x1f;
+ for (bit = 0; bit < BUS_WIDTH_IN_BITS; bit++) {
+ /* reset result for PBS */
+ result_all_bit[bit + pup * BUS_WIDTH_IN_BITS +
+ if_id * MAX_BUS_NUM *
+ BUS_WIDTH_IN_BITS] = 0;
+ }
+ }
+ }
+
+ iterations = 31;
+ search_dir = HWS_LOW2HIGH;
+ /* !!!!! ran sh (search_dir == HWS_LOW2HIGH)?0:iterations; */
+ init_val = 0;
+
+ ddr3_tip_ip_training(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ RESULT_PER_BIT, HWS_CONTROL_ELEMENT_DQ_SKEW,
+ search_dir, dir, tm->if_act_mask, init_val,
+ iterations, pbs_pattern, search_edge,
+ CS_SINGLE, cs_num, train_status);
+
+ for (pup = 0; pup < tm->num_of_bus_per_interface; pup++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, pup);
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ if (adll_shift_lock[if_id][pup] != 1) {
+ /* if pup not lock continue to next pup */
+ continue;
+ }
+
+ for (bit = 0; bit < BUS_WIDTH_IN_BITS; bit++) {
+ CHECK_STATUS(ddr3_tip_if_read
+ (dev_num, ACCESS_TYPE_MULTICAST,
+ PARAM_NOT_CARE,
+ mask_results_dq_reg_map[
+ bit +
+ pup * BUS_WIDTH_IN_BITS],
+ res0, MASK_ALL_BITS));
+ DEBUG_PBS_ENGINE(DEBUG_LEVEL_INFO,
+ ("Per Bit Skew search, FP I/F %d, bit:%d, pup:%d res0 0x%x\n",
+ if_id, bit, pup,
+ res0[if_id]));
+ if ((res0[if_id] & 0x2000000) == 0) {
+ DEBUG_PBS_ENGINE(DEBUG_LEVEL_INFO,
+ ("--EBA PBS Fail - Training IP machine\n"));
+ /* exit the bit loop */
+ bit = BUS_WIDTH_IN_BITS;
+ /*
+ * ADLL is no long in lock need new
+ * search
+ */
+ adll_shift_lock[if_id][pup] = 0;
+ /* Move to SBA */
+ pup_state[if_id][pup] = 2;
+ max_pbs_per_pup[if_id][pup] = 0x0;
+ min_pbs_per_pup[if_id][pup] = 0x1f;
+ continue;
+ } else {
+ temp = (u8)(res0[if_id] &
+ res_valid_mask);
+ max_pbs_per_pup[if_id][pup] =
+ (temp >
+ max_pbs_per_pup[if_id][pup]) ?
+ temp :
+ max_pbs_per_pup[if_id][pup];
+ min_pbs_per_pup[if_id][pup] =
+ (temp <
+ min_pbs_per_pup[if_id][pup]) ?
+ temp :
+ min_pbs_per_pup[if_id][pup];
+ result_all_bit[bit +
+ pup * BUS_WIDTH_IN_BITS +
+ if_id * MAX_BUS_NUM *
+ BUS_WIDTH_IN_BITS] =
+ temp;
+ }
+ }
+ }
+ }
+
+ /* Check all Pup lock */
+ all_lock = 1;
+ for (pup = 0; pup < tm->num_of_bus_per_interface; pup++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, pup);
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ all_lock = all_lock * adll_shift_lock[if_id][pup];
+ }
+ }
+
+ /* Only if not all Pups Lock */
+ if (all_lock == 0) {
+ DEBUG_PBS_ENGINE(DEBUG_LEVEL_INFO,
+ ("##########ADLL shift for SBA###########\n"));
+
+ /* ADLL shift for SBA */
+ search_dir = (pbs_mode == PBS_RX_MODE) ? HWS_LOW2HIGH :
+ HWS_HIGH2LOW;
+ init_val = (search_dir == HWS_LOW2HIGH) ? 0 : iterations;
+ for (pup = 0; pup < tm->num_of_bus_per_interface; pup++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, pup);
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1;
+ if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ if (adll_shift_lock[if_id][pup] == 1) {
+ /*if pup lock continue to next pup */
+ continue;
+ }
+ /*init the var altogth init before */
+ adll_shift_lock[if_id][pup] = 0;
+ reg_addr = (pbs_mode == PBS_RX_MODE) ?
+ (0x54 + effective_cs * 0x10) :
+ (0x14 + effective_cs * 0x10);
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_UNICAST,
+ if_id, ACCESS_TYPE_UNICAST, pup,
+ DDR_PHY_DATA, reg_addr, 0));
+ reg_addr = (pbs_mode == PBS_RX_MODE) ?
+ (0x55 + effective_cs * 0x10) :
+ (0x15 + effective_cs * 0x10);
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_UNICAST,
+ if_id, ACCESS_TYPE_UNICAST, pup,
+ DDR_PHY_DATA, reg_addr, 0));
+ reg_addr = (pbs_mode == PBS_RX_MODE) ?
+ (0x5f + effective_cs * 0x10) :
+ (0x1f + effective_cs * 0x10);
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_UNICAST,
+ if_id, ACCESS_TYPE_UNICAST, pup,
+ DDR_PHY_DATA, reg_addr, 0));
+ /* initilaze the Edge2 Max. */
+ adll_shift_val[if_id][pup] = 0;
+ min_adll_per_pup[if_id][pup] = 0x1f;
+ max_adll_per_pup[if_id][pup] = 0x0;
+
+ ddr3_tip_ip_training(dev_num,
+ ACCESS_TYPE_MULTICAST,
+ PARAM_NOT_CARE,
+ ACCESS_TYPE_MULTICAST,
+ PARAM_NOT_CARE,
+ RESULT_PER_BIT,
+ HWS_CONTROL_ELEMENT_ADLL,
+ search_dir, dir,
+ tm->if_act_mask,
+ init_val, iterations,
+ pbs_pattern,
+ search_edge, CS_SINGLE,
+ cs_num, train_status);
+
+ for (bit = 0; bit < BUS_WIDTH_IN_BITS; bit++) {
+ CHECK_STATUS(ddr3_tip_if_read
+ (dev_num,
+ ACCESS_TYPE_MULTICAST,
+ PARAM_NOT_CARE,
+ mask_results_dq_reg_map
+ [bit +
+ pup *
+ BUS_WIDTH_IN_BITS],
+ res0, MASK_ALL_BITS));
+ DEBUG_PBS_ENGINE(
+ DEBUG_LEVEL_INFO,
+ ("FP I/F %d, bit:%d, pup:%d res0 0x%x\n",
+ if_id, bit, pup, res0[if_id]));
+ if ((res0[if_id] & 0x2000000) == 0) {
+ /* exit the bit loop */
+ bit = BUS_WIDTH_IN_BITS;
+ /* Fail SBA --> Fail PBS */
+ pup_state[if_id][pup] = 1;
+ DEBUG_PBS_ENGINE
+ (DEBUG_LEVEL_INFO,
+ (" SBA Fail\n"));
+ continue;
+ } else {
+ /*
+ * - increment to get all
+ * 8 bit lock.
+ */
+ adll_shift_lock[if_id][pup]++;
+ /*
+ * The search ended in Pass
+ * we need Fail
+ */
+ res0[if_id] =
+ (pbs_mode == PBS_RX_MODE) ?
+ ((res0[if_id] & res_valid_mask) + 1) :
+ ((res0[if_id] & res_valid_mask) - 1);
+ max_adll_per_pup[if_id][pup] =
+ (max_adll_per_pup[if_id]
+ [pup] < res0[if_id]) ?
+ (u8)res0[if_id] :
+ max_adll_per_pup[if_id][pup];
+ min_adll_per_pup[if_id][pup] =
+ (res0[if_id] >
+ min_adll_per_pup[if_id]
+ [pup]) ?
+ min_adll_per_pup[if_id][pup] :
+ (u8)res0[if_id];
+ /*
+ * vs the Rx we are searching for
+ * the smallest value of DQ shift
+ * so all Bus would fail
+ */
+ adll_shift_val[if_id][pup] =
+ (pbs_mode == PBS_RX_MODE) ?
+ max_adll_per_pup[if_id][pup] :
+ min_adll_per_pup[if_id][pup];
+ }
+ }
+ /* 1 is lock */
+ adll_shift_lock[if_id][pup] =
+ (adll_shift_lock[if_id][pup] == 8) ?
+ 1 : 0;
+ reg_addr = (pbs_mode == PBS_RX_MODE) ?
+ (0x3 + effective_cs * 4) :
+ (0x1 + effective_cs * 4);
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_UNICAST,
+ if_id, ACCESS_TYPE_UNICAST, pup,
+ DDR_PHY_DATA, reg_addr,
+ adll_shift_val[if_id][pup]));
+ DEBUG_PBS_ENGINE(
+ DEBUG_LEVEL_INFO,
+ ("adll_shift_lock[%x][%x] = %x\n",
+ if_id, pup,
+ adll_shift_lock[if_id][pup]));
+ }
+ }
+
+ /* End ADLL Shift for SBA */
+ /* Start the Per Bit Skew search */
+ /* The ADLL shift finished with a Pass */
+ search_edge = (pbs_mode == PBS_RX_MODE) ? EDGE_PF : EDGE_FP;
+ search_dir = (pbs_mode == PBS_RX_MODE) ?
+ HWS_LOW2HIGH : HWS_HIGH2LOW;
+ iterations = 0x1f;
+ /* - The initial value is different in Rx and Tx mode */
+ init_val = (pbs_mode == PBS_RX_MODE) ? 0 : iterations;
+
+ ddr3_tip_ip_training(dev_num, ACCESS_TYPE_MULTICAST,
+ PARAM_NOT_CARE, ACCESS_TYPE_MULTICAST,
+ PARAM_NOT_CARE, RESULT_PER_BIT,
+ HWS_CONTROL_ELEMENT_DQ_SKEW,
+ search_dir, dir, tm->if_act_mask,
+ init_val, iterations, pbs_pattern,
+ search_edge, CS_SINGLE, cs_num,
+ train_status);
+
+ for (pup = 0; pup < tm->num_of_bus_per_interface; pup++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, pup);
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1;
+ if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ for (bit = 0; bit < BUS_WIDTH_IN_BITS; bit++) {
+ CHECK_STATUS(ddr3_tip_if_read
+ (dev_num,
+ ACCESS_TYPE_MULTICAST,
+ PARAM_NOT_CARE,
+ mask_results_dq_reg_map
+ [bit +
+ pup *
+ BUS_WIDTH_IN_BITS],
+ res0, MASK_ALL_BITS));
+ if (pup_state[if_id][pup] != 2) {
+ /*
+ * if pup is not SBA continue
+ * to next pup
+ */
+ bit = BUS_WIDTH_IN_BITS;
+ continue;
+ }
+ DEBUG_PBS_ENGINE(
+ DEBUG_LEVEL_INFO,
+ ("Per Bit Skew search, PF I/F %d, bit:%d, pup:%d res0 0x%x\n",
+ if_id, bit, pup, res0[if_id]));
+ if ((res0[if_id] & 0x2000000) == 0) {
+ DEBUG_PBS_ENGINE
+ (DEBUG_LEVEL_INFO,
+ ("SBA Fail\n"));
+
+ max_pbs_per_pup[if_id][pup] =
+ 0x1f;
+ result_all_bit[
+ bit + pup *
+ BUS_WIDTH_IN_BITS +
+ if_id * MAX_BUS_NUM *
+ BUS_WIDTH_IN_BITS] =
+ 0x1f;
+ } else {
+ temp = (u8)(res0[if_id] &
+ res_valid_mask);
+ max_pbs_per_pup[if_id][pup] =
+ (temp >
+ max_pbs_per_pup[if_id]
+ [pup]) ? temp :
+ max_pbs_per_pup
+ [if_id][pup];
+ min_pbs_per_pup[if_id][pup] =
+ (temp <
+ min_pbs_per_pup[if_id]
+ [pup]) ? temp :
+ min_pbs_per_pup
+ [if_id][pup];
+ result_all_bit[
+ bit + pup *
+ BUS_WIDTH_IN_BITS +
+ if_id * MAX_BUS_NUM *
+ BUS_WIDTH_IN_BITS] =
+ temp;
+ adll_shift_lock[if_id][pup] = 1;
+ }
+ }
+ }
+ }
+
+ /* Check all Pup state */
+ all_lock = 1;
+ for (pup = 0; pup < tm->num_of_bus_per_interface; pup++) {
+ /*
+ * DEBUG_PBS_ENGINE(DEBUG_LEVEL_INFO,
+ * ("pup_state[%d][%d] = %d\n",if_id,pup,pup_state
+ * [if_id][pup]));
+ */
+ }
+ }
+
+ /* END OF SBA */
+ /* Norm */
+ for (pup = 0; pup < tm->num_of_bus_per_interface; pup++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, pup);
+ for (bit = 0; bit < BUS_WIDTH_IN_BITS; bit++) {
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1;
+ if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ /* if pup not lock continue to next pup */
+ if (adll_shift_lock[if_id][pup] != 1) {
+ DEBUG_PBS_ENGINE(
+ DEBUG_LEVEL_ERROR,
+ ("PBS failed for IF #%d\n",
+ if_id));
+ training_result[training_stage][if_id]
+ = TEST_FAILED;
+
+ result_mat[if_id][pup][bit] = 0;
+ max_pbs_per_pup[if_id][pup] = 0;
+ min_pbs_per_pup[if_id][pup] = 0;
+ } else {
+ training_result[
+ training_stage][if_id] =
+ (training_result[training_stage]
+ [if_id] == TEST_FAILED) ?
+ TEST_FAILED : TEST_SUCCESS;
+ result_mat[if_id][pup][bit] =
+ result_all_bit[
+ bit + pup *
+ BUS_WIDTH_IN_BITS +
+ if_id * MAX_BUS_NUM *
+ BUS_WIDTH_IN_BITS] -
+ min_pbs_per_pup[if_id][pup];
+ }
+ DEBUG_PBS_ENGINE(
+ DEBUG_LEVEL_INFO,
+ ("The abs min_pbs[%d][%d] = %d\n",
+ if_id, pup,
+ min_pbs_per_pup[if_id][pup]));
+ }
+ }
+ }
+
+ /* Clean all results */
+ ddr3_tip_clean_pbs_result(dev_num, pbs_mode);
+
+ /* DQ PBS register update with the final result */
+ for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ for (pup = 0; pup < tm->num_of_bus_per_interface; pup++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, pup);
+
+ DEBUG_PBS_ENGINE(
+ DEBUG_LEVEL_INFO,
+ ("Final Results: if_id %d, pup %d, Pup State: %d\n",
+ if_id, pup, pup_state[if_id][pup]));
+ for (bit = 0; bit < BUS_WIDTH_IN_BITS; bit++) {
+ if (dq_map_table == NULL) {
+ DEBUG_PBS_ENGINE(
+ DEBUG_LEVEL_ERROR,
+ ("dq_map_table not initialized\n"));
+ return MV_FAIL;
+ }
+ pad_num = dq_map_table[
+ bit + pup * BUS_WIDTH_IN_BITS +
+ if_id * BUS_WIDTH_IN_BITS *
+ tm->num_of_bus_per_interface];
+ DEBUG_PBS_ENGINE(DEBUG_LEVEL_INFO,
+ ("result_mat: %d ",
+ result_mat[if_id][pup]
+ [bit]));
+ reg_addr = (pbs_mode == PBS_RX_MODE) ?
+ (PBS_RX_PHY_REG + effective_cs * 0x10) :
+ (PBS_TX_PHY_REG + effective_cs * 0x10);
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_UNICAST,
+ if_id, ACCESS_TYPE_UNICAST, pup,
+ DDR_PHY_DATA, reg_addr + pad_num,
+ result_mat[if_id][pup][bit]));
+ }
+ pbsdelay_per_pup[pbs_mode][if_id][pup] =
+ (max_pbs_per_pup[if_id][pup] ==
+ min_pbs_per_pup[if_id][pup]) ?
+ TYPICAL_PBS_VALUE :
+ ((max_adll_per_pup[if_id][pup] -
+ min_adll_per_pup[if_id][pup]) * adll_tap /
+ (max_pbs_per_pup[if_id][pup] -
+ min_pbs_per_pup[if_id][pup]));
+
+ /* RX results ready, write RX also */
+ if (pbs_mode == PBS_TX_MODE) {
+ /* Write TX results */
+ reg_addr = (0x14 + effective_cs * 0x10);
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_UNICAST,
+ if_id, ACCESS_TYPE_UNICAST, pup,
+ DDR_PHY_DATA, reg_addr,
+ (max_pbs_per_pup[if_id][pup] -
+ min_pbs_per_pup[if_id][pup]) /
+ 2));
+ reg_addr = (0x15 + effective_cs * 0x10);
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_UNICAST,
+ if_id, ACCESS_TYPE_UNICAST, pup,
+ DDR_PHY_DATA, reg_addr,
+ (max_pbs_per_pup[if_id][pup] -
+ min_pbs_per_pup[if_id][pup]) /
+ 2));
+
+ /* Write previously stored RX results */
+ reg_addr = (0x54 + effective_cs * 0x10);
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_UNICAST,
+ if_id, ACCESS_TYPE_UNICAST, pup,
+ DDR_PHY_DATA, reg_addr,
+ result_mat_rx_dqs[if_id][pup]
+ [effective_cs]));
+ reg_addr = (0x55 + effective_cs * 0x10);
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_UNICAST,
+ if_id, ACCESS_TYPE_UNICAST, pup,
+ DDR_PHY_DATA, reg_addr,
+ result_mat_rx_dqs[if_id][pup]
+ [effective_cs]));
+ } else {
+ /*
+ * RX results may affect RL results correctess,
+ * so just store the results that will written
+ * in TX stage
+ */
+ result_mat_rx_dqs[if_id][pup][effective_cs] =
+ (max_pbs_per_pup[if_id][pup] -
+ min_pbs_per_pup[if_id][pup]) / 2;
+ }
+ DEBUG_PBS_ENGINE(
+ DEBUG_LEVEL_INFO,
+ (", PBS tap=%d [psec] ==> skew observed = %d\n",
+ pbsdelay_per_pup[pbs_mode][if_id][pup],
+ ((max_pbs_per_pup[if_id][pup] -
+ min_pbs_per_pup[if_id][pup]) *
+ pbsdelay_per_pup[pbs_mode][if_id][pup])));
+ }
+ }
+
+ /* Write back to the phy the default values */
+ reg_addr = (pbs_mode == PBS_RX_MODE) ?
+ (READ_CENTRALIZATION_PHY_REG + effective_cs * 4) :
+ (WRITE_CENTRALIZATION_PHY_REG + effective_cs * 4);
+ write_adll_value(nominal_adll, reg_addr);
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ reg_addr = (pbs_mode == PBS_RX_MODE) ?
+ (0x5a + effective_cs * 0x10) :
+ (0x1a + effective_cs * 0x10);
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ ACCESS_TYPE_UNICAST, pup, DDR_PHY_DATA, reg_addr,
+ 0));
+
+ /* restore cs enable value */
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ CS_ENABLE_REG, cs_enable_reg_val[if_id],
+ MASK_ALL_BITS));
+ }
+
+ /* exit test mode */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ODPG_WRITE_READ_MODE_ENABLE_REG, 0xffff, MASK_ALL_BITS));
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ /*
+ * meaning that there is no VW exist at all (No lock at
+ * the EBA ADLL shift at EBS)
+ */
+ if (pup_state[if_id][pup] == 1)
+ return MV_FAIL;
+ }
+
+ return MV_OK;
+}
+
+/*
+ * Name: ddr3_tip_pbs_rx.
+ * Desc: PBS TX
+ * Args: TBD
+ * Notes:
+ * Returns: OK if success, other error code if fail.
+ */
+int ddr3_tip_pbs_rx(u32 uidev_num)
+{
+ return ddr3_tip_pbs(uidev_num, PBS_RX_MODE);
+}
+
+/*
+ * Name: ddr3_tip_pbs_tx.
+ * Desc: PBS TX
+ * Args: TBD
+ * Notes:
+ * Returns: OK if success, other error code if fail.
+ */
+int ddr3_tip_pbs_tx(u32 uidev_num)
+{
+ return ddr3_tip_pbs(uidev_num, PBS_TX_MODE);
+}
+
+#ifndef EXCLUDE_SWITCH_DEBUG
+/*
+ * Print PBS Result
+ */
+int ddr3_tip_print_all_pbs_result(u32 dev_num)
+{
+ u32 curr_cs;
+ u32 max_cs = hws_ddr3_tip_max_cs_get();
+
+ for (curr_cs = 0; curr_cs < max_cs; curr_cs++) {
+ ddr3_tip_print_pbs_result(dev_num, curr_cs, PBS_RX_MODE);
+ ddr3_tip_print_pbs_result(dev_num, curr_cs, PBS_TX_MODE);
+ }
+
+ return MV_OK;
+}
+
+/*
+ * Print PBS Result
+ */
+int ddr3_tip_print_pbs_result(u32 dev_num, u32 cs_num, enum pbs_dir pbs_mode)
+{
+ u32 data_value = 0, bit = 0, if_id = 0, pup = 0;
+ u32 reg_addr = (pbs_mode == PBS_RX_MODE) ?
+ (PBS_RX_PHY_REG + cs_num * 0x10) :
+ (PBS_TX_PHY_REG + cs_num * 0x10);
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ printf("CS%d, %s ,PBS\n", cs_num,
+ (pbs_mode == PBS_RX_MODE) ? "Rx" : "Tx");
+
+ for (bit = 0; bit < BUS_WIDTH_IN_BITS; bit++) {
+ printf("%s, DQ", (pbs_mode == PBS_RX_MODE) ? "Rx" : "Tx");
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ printf("%d ,PBS,,, ", bit);
+ for (pup = 0; pup <= tm->num_of_bus_per_interface;
+ pup++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, pup);
+ CHECK_STATUS(ddr3_tip_bus_read
+ (dev_num, if_id,
+ ACCESS_TYPE_UNICAST, pup,
+ DDR_PHY_DATA, reg_addr + bit,
+ &data_value));
+ printf("%d , ", data_value);
+ }
+ }
+ printf("\n");
+ }
+ printf("\n");
+
+ return MV_OK;
+}
+#endif
+
+/*
+ * Fixup PBS Result
+ */
+int ddr3_tip_clean_pbs_result(u32 dev_num, enum pbs_dir pbs_mode)
+{
+ u32 if_id, pup, bit;
+ u32 reg_addr = (pbs_mode == PBS_RX_MODE) ?
+ (PBS_RX_PHY_REG + effective_cs * 0x10) :
+ (PBS_TX_PHY_REG + effective_cs * 0x10);
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ for (pup = 0; pup <= tm->num_of_bus_per_interface; pup++) {
+ for (bit = 0; bit <= BUS_WIDTH_IN_BITS + 3; bit++) {
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_UNICAST,
+ if_id, ACCESS_TYPE_UNICAST, pup,
+ DDR_PHY_DATA, reg_addr + bit, 0));
+ }
+ }
+ }
+
+ return MV_OK;
+}
diff --git a/drivers/ddr/marvell/a38x/old/ddr3_training_static.c b/drivers/ddr/marvell/a38x/old/ddr3_training_static.c
new file mode 100644
index 0000000..3129dfa
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/ddr3_training_static.c
@@ -0,0 +1,537 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+#include "ddr3_init.h"
+
+/* Design Guidelines parameters */
+u32 g_zpri_data = 123; /* controller data - P drive strength */
+u32 g_znri_data = 123; /* controller data - N drive strength */
+u32 g_zpri_ctrl = 74; /* controller C/A - P drive strength */
+u32 g_znri_ctrl = 74; /* controller C/A - N drive strength */
+u32 g_zpodt_data = 45; /* controller data - P ODT */
+u32 g_znodt_data = 45; /* controller data - N ODT */
+u32 g_zpodt_ctrl = 45; /* controller data - P ODT */
+u32 g_znodt_ctrl = 45; /* controller data - N ODT */
+u32 g_odt_config = 0x120012;
+u32 g_rtt_nom = 0x44;
+u32 g_dic = 0x2;
+
+#ifdef STATIC_ALGO_SUPPORT
+
+#define PARAM_NOT_CARE 0
+#define MAX_STATIC_SEQ 48
+
+u32 silicon_delay[HWS_MAX_DEVICE_NUM];
+struct hws_tip_static_config_info static_config[HWS_MAX_DEVICE_NUM];
+static reg_data *static_init_controller_config[HWS_MAX_DEVICE_NUM];
+
+/* debug delay in write leveling */
+int wl_debug_delay = 0;
+/* pup register #3 for functional board */
+int function_reg_value = 8;
+u32 silicon;
+
+u32 read_ready_delay_phase_offset[] = { 4, 4, 4, 4, 6, 6, 6, 6 };
+
+static struct cs_element chip_select_map[] = {
+ /* CS Value (single only) Num_CS */
+ {0, 0},
+ {0, 1},
+ {1, 1},
+ {0, 2},
+ {2, 1},
+ {0, 2},
+ {0, 2},
+ {0, 3},
+ {3, 1},
+ {0, 2},
+ {0, 2},
+ {0, 3},
+ {0, 2},
+ {0, 3},
+ {0, 3},
+ {0, 4}
+};
+
+/*
+ * Register static init controller DB
+ */
+int ddr3_tip_init_specific_reg_config(u32 dev_num, reg_data *reg_config_arr)
+{
+ static_init_controller_config[dev_num] = reg_config_arr;
+ return MV_OK;
+}
+
+/*
+ * Register static info DB
+ */
+int ddr3_tip_init_static_config_db(
+ u32 dev_num, struct hws_tip_static_config_info *static_config_info)
+{
+ static_config[dev_num].board_trace_arr =
+ static_config_info->board_trace_arr;
+ static_config[dev_num].package_trace_arr =
+ static_config_info->package_trace_arr;
+ silicon_delay[dev_num] = static_config_info->silicon_delay;
+
+ return MV_OK;
+}
+
+/*
+ * Static round trip flow - Calculates the total round trip delay.
+ */
+int ddr3_tip_static_round_trip_arr_build(u32 dev_num,
+ struct trip_delay_element *table_ptr,
+ int is_wl, u32 *round_trip_delay_arr)
+{
+ u32 bus_index, global_bus;
+ u32 if_id;
+ u32 bus_per_interface;
+ int sign;
+ u32 temp;
+ u32 board_trace;
+ struct trip_delay_element *pkg_delay_ptr;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ /*
+ * In WL we calc the diff between Clock to DQs in RL we sum the round
+ * trip of Clock and DQs
+ */
+ sign = (is_wl) ? -1 : 1;
+
+ bus_per_interface = GET_TOPOLOGY_NUM_OF_BUSES();
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ for (bus_index = 0; bus_index < bus_per_interface;
+ bus_index++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, bus_index);
+ global_bus = (if_id * bus_per_interface) + bus_index;
+
+ /* calculate total trip delay (package and board) */
+ board_trace = (table_ptr[global_bus].dqs_delay * sign) +
+ table_ptr[global_bus].ck_delay;
+ temp = (board_trace * 163) / 1000;
+
+ /* Convert the length to delay in psec units */
+ pkg_delay_ptr =
+ static_config[dev_num].package_trace_arr;
+ round_trip_delay_arr[global_bus] = temp +
+ (int)(pkg_delay_ptr[global_bus].dqs_delay *
+ sign) +
+ (int)pkg_delay_ptr[global_bus].ck_delay +
+ (int)((is_wl == 1) ? wl_debug_delay :
+ (int)silicon_delay[dev_num]);
+ DEBUG_TRAINING_STATIC_IP(
+ DEBUG_LEVEL_TRACE,
+ ("Round Trip Build round_trip_delay_arr[0x%x]: 0x%x temp 0x%x\n",
+ global_bus, round_trip_delay_arr[global_bus],
+ temp));
+ }
+ }
+
+ return MV_OK;
+}
+
+/*
+ * Write leveling for static flow - calculating the round trip delay of the
+ * DQS signal.
+ */
+int ddr3_tip_write_leveling_static_config(u32 dev_num, u32 if_id,
+ enum hws_ddr_freq frequency,
+ u32 *round_trip_delay_arr)
+{
+ u32 bus_index; /* index to the bus loop */
+ u32 bus_start_index;
+ u32 bus_per_interface;
+ u32 phase = 0;
+ u32 adll = 0, adll_cen, adll_inv, adll_final;
+ u32 adll_period = MEGA / freq_val[frequency] / 64;
+
+ DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE,
+ ("ddr3_tip_write_leveling_static_config\n"));
+ DEBUG_TRAINING_STATIC_IP(
+ DEBUG_LEVEL_TRACE,
+ ("dev_num 0x%x IF 0x%x freq %d (adll_period 0x%x)\n",
+ dev_num, if_id, frequency, adll_period));
+
+ bus_per_interface = GET_TOPOLOGY_NUM_OF_BUSES();
+ bus_start_index = if_id * bus_per_interface;
+ for (bus_index = bus_start_index;
+ bus_index < (bus_start_index + bus_per_interface); bus_index++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, bus_index);
+ phase = round_trip_delay_arr[bus_index] / (32 * adll_period);
+ adll = (round_trip_delay_arr[bus_index] -
+ (phase * 32 * adll_period)) / adll_period;
+ adll = (adll > 31) ? 31 : adll;
+ adll_cen = 16 + adll;
+ adll_inv = adll_cen / 32;
+ adll_final = adll_cen - (adll_inv * 32);
+ adll_final = (adll_final > 31) ? 31 : adll_final;
+
+ DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE,
+ ("\t%d - phase 0x%x adll 0x%x\n",
+ bus_index, phase, adll));
+ /*
+ * Writing to all 4 phy of Interface number,
+ * bit 0 \96 4 \96 ADLL, bit 6-8 phase
+ */
+ CHECK_STATUS(ddr3_tip_bus_read_modify_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ (bus_index % 4), DDR_PHY_DATA,
+ PHY_WRITE_DELAY(cs),
+ ((phase << 6) + (adll & 0x1f)), 0x1df));
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ ACCESS_TYPE_UNICAST, (bus_index % 4),
+ DDR_PHY_DATA, WRITE_CENTRALIZATION_PHY_REG,
+ ((adll_inv & 0x1) << 5) + adll_final));
+ }
+
+ return MV_OK;
+}
+
+/*
+ * Read leveling for static flow
+ */
+int ddr3_tip_read_leveling_static_config(u32 dev_num,
+ u32 if_id,
+ enum hws_ddr_freq frequency,
+ u32 *total_round_trip_delay_arr)
+{
+ u32 cs, data0, data1, data3 = 0;
+ u32 bus_index; /* index to the bus loop */
+ u32 bus_start_index;
+ u32 phase0, phase1, max_phase;
+ u32 adll0, adll1;
+ u32 cl_value;
+ u32 min_delay;
+ u32 sdr_period = MEGA / freq_val[frequency];
+ u32 ddr_period = MEGA / freq_val[frequency] / 2;
+ u32 adll_period = MEGA / freq_val[frequency] / 64;
+ enum hws_speed_bin speed_bin_index;
+ u32 rd_sample_dly[MAX_CS_NUM] = { 0 };
+ u32 rd_ready_del[MAX_CS_NUM] = { 0 };
+ u32 bus_per_interface = GET_TOPOLOGY_NUM_OF_BUSES();
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE,
+ ("ddr3_tip_read_leveling_static_config\n"));
+ DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE,
+ ("dev_num 0x%x ifc 0x%x freq %d\n", dev_num,
+ if_id, frequency));
+ DEBUG_TRAINING_STATIC_IP(
+ DEBUG_LEVEL_TRACE,
+ ("Sdr_period 0x%x Ddr_period 0x%x adll_period 0x%x\n",
+ sdr_period, ddr_period, adll_period));
+
+ if (tm->interface_params[first_active_if].memory_freq ==
+ frequency) {
+ cl_value = tm->interface_params[first_active_if].cas_l;
+ DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE,
+ ("cl_value 0x%x\n", cl_value));
+ } else {
+ speed_bin_index = tm->interface_params[if_id].speed_bin_index;
+ cl_value = cas_latency_table[speed_bin_index].cl_val[frequency];
+ DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE,
+ ("cl_value 0x%x speed_bin_index %d\n",
+ cl_value, speed_bin_index));
+ }
+
+ bus_start_index = if_id * bus_per_interface;
+
+ for (bus_index = bus_start_index;
+ bus_index < (bus_start_index + bus_per_interface);
+ bus_index += 2) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, bus_index);
+ cs = chip_select_map[
+ tm->interface_params[if_id].as_bus_params[
+ (bus_index % 4)].cs_bitmask].cs_num;
+
+ /* read sample delay calculation */
+ min_delay = (total_round_trip_delay_arr[bus_index] <
+ total_round_trip_delay_arr[bus_index + 1]) ?
+ total_round_trip_delay_arr[bus_index] :
+ total_round_trip_delay_arr[bus_index + 1];
+ /* round down */
+ rd_sample_dly[cs] = 2 * (min_delay / (sdr_period * 2));
+ DEBUG_TRAINING_STATIC_IP(
+ DEBUG_LEVEL_TRACE,
+ ("\t%d - min_delay 0x%x cs 0x%x rd_sample_dly[cs] 0x%x\n",
+ bus_index, min_delay, cs, rd_sample_dly[cs]));
+
+ /* phase calculation */
+ phase0 = (total_round_trip_delay_arr[bus_index] -
+ (sdr_period * rd_sample_dly[cs])) / (ddr_period);
+ phase1 = (total_round_trip_delay_arr[bus_index + 1] -
+ (sdr_period * rd_sample_dly[cs])) / (ddr_period);
+ max_phase = (phase0 > phase1) ? phase0 : phase1;
+ DEBUG_TRAINING_STATIC_IP(
+ DEBUG_LEVEL_TRACE,
+ ("\tphase0 0x%x phase1 0x%x max_phase 0x%x\n",
+ phase0, phase1, max_phase));
+
+ /* ADLL calculation */
+ adll0 = (u32)((total_round_trip_delay_arr[bus_index] -
+ (sdr_period * rd_sample_dly[cs]) -
+ (ddr_period * phase0)) / adll_period);
+ adll0 = (adll0 > 31) ? 31 : adll0;
+ adll1 = (u32)((total_round_trip_delay_arr[bus_index + 1] -
+ (sdr_period * rd_sample_dly[cs]) -
+ (ddr_period * phase1)) / adll_period);
+ adll1 = (adll1 > 31) ? 31 : adll1;
+
+ /* The Read delay close the Read FIFO */
+ rd_ready_del[cs] = rd_sample_dly[cs] +
+ read_ready_delay_phase_offset[max_phase];
+ DEBUG_TRAINING_STATIC_IP(
+ DEBUG_LEVEL_TRACE,
+ ("\tadll0 0x%x adll1 0x%x rd_ready_del[cs] 0x%x\n",
+ adll0, adll1, rd_ready_del[cs]));
+
+ /*
+ * Write to the phy of Interface (bit 0 \96 4 \96 ADLL,
+ * bit 6-8 phase)
+ */
+ data0 = ((phase0 << 6) + (adll0 & 0x1f));
+ data1 = ((phase1 << 6) + (adll1 & 0x1f));
+
+ CHECK_STATUS(ddr3_tip_bus_read_modify_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ (bus_index % 4), DDR_PHY_DATA, PHY_READ_DELAY(cs),
+ data0, 0x1df));
+ CHECK_STATUS(ddr3_tip_bus_read_modify_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ ((bus_index + 1) % 4), DDR_PHY_DATA,
+ PHY_READ_DELAY(cs), data1, 0x1df));
+ }
+
+ for (bus_index = 0; bus_index < bus_per_interface; bus_index++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, bus_index);
+ CHECK_STATUS(ddr3_tip_bus_read_modify_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ bus_index, DDR_PHY_DATA, 0x3, data3, 0x1f));
+ }
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ READ_DATA_SAMPLE_DELAY,
+ (rd_sample_dly[0] + cl_value) + (rd_sample_dly[1] << 8),
+ MASK_ALL_BITS));
+
+ /* Read_ready_del0 bit 0-4 , CS bits 8-12 */
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_UNICAST, if_id,
+ READ_DATA_READY_DELAY,
+ rd_ready_del[0] + (rd_ready_del[1] << 8) + cl_value,
+ MASK_ALL_BITS));
+
+ return MV_OK;
+}
+
+/*
+ * DDR3 Static flow
+ */
+int ddr3_tip_run_static_alg(u32 dev_num, enum hws_ddr_freq freq)
+{
+ u32 if_id = 0;
+ struct trip_delay_element *table_ptr;
+ u32 wl_total_round_trip_delay_arr[MAX_TOTAL_BUS_NUM];
+ u32 rl_total_round_trip_delay_arr[MAX_TOTAL_BUS_NUM];
+ struct init_cntr_param init_cntr_prm;
+ int ret;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE,
+ ("ddr3_tip_run_static_alg"));
+
+ init_cntr_prm.do_mrs_phy = 1;
+ init_cntr_prm.is_ctrl64_bit = 0;
+ init_cntr_prm.init_phy = 1;
+ ret = hws_ddr3_tip_init_controller(dev_num, &init_cntr_prm);
+ if (ret != MV_OK) {
+ DEBUG_TRAINING_STATIC_IP(
+ DEBUG_LEVEL_ERROR,
+ ("hws_ddr3_tip_init_controller failure\n"));
+ }
+
+ /* calculate the round trip delay for Write Leveling */
+ table_ptr = static_config[dev_num].board_trace_arr;
+ CHECK_STATUS(ddr3_tip_static_round_trip_arr_build
+ (dev_num, table_ptr, 1,
+ wl_total_round_trip_delay_arr));
+ /* calculate the round trip delay for Read Leveling */
+ CHECK_STATUS(ddr3_tip_static_round_trip_arr_build
+ (dev_num, table_ptr, 0,
+ rl_total_round_trip_delay_arr));
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ /* check if the interface is enabled */
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+ /*
+ * Static frequency is defined according to init-frequency
+ * (not target)
+ */
+ DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE,
+ ("Static IF %d freq %d\n",
+ if_id, freq));
+ CHECK_STATUS(ddr3_tip_write_leveling_static_config
+ (dev_num, if_id, freq,
+ wl_total_round_trip_delay_arr));
+ CHECK_STATUS(ddr3_tip_read_leveling_static_config
+ (dev_num, if_id, freq,
+ rl_total_round_trip_delay_arr));
+ }
+
+ return MV_OK;
+}
+
+/*
+ * Init controller for static flow
+ */
+int ddr3_tip_static_init_controller(u32 dev_num)
+{
+ u32 index_cnt = 0;
+
+ DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE,
+ ("ddr3_tip_static_init_controller\n"));
+ while (static_init_controller_config[dev_num][index_cnt].reg_addr !=
+ 0) {
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ static_init_controller_config[dev_num][index_cnt].
+ reg_addr,
+ static_init_controller_config[dev_num][index_cnt].
+ reg_data,
+ static_init_controller_config[dev_num][index_cnt].
+ reg_mask));
+
+ DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE,
+ ("Init_controller index_cnt %d\n",
+ index_cnt));
+ index_cnt++;
+ }
+
+ return MV_OK;
+}
+
+int ddr3_tip_static_phy_init_controller(u32 dev_num)
+{
+ DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE,
+ ("Phy Init Controller 2\n"));
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA, 0xa4,
+ 0x3dfe));
+
+ DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE,
+ ("Phy Init Controller 3\n"));
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA, 0xa6,
+ 0xcb2));
+
+ DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE,
+ ("Phy Init Controller 4\n"));
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA, 0xa9,
+ 0));
+
+ DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE,
+ ("Static Receiver Calibration\n"));
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA, 0xd0,
+ 0x1f));
+
+ DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE,
+ ("Static V-REF Calibration\n"));
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA, 0xa8,
+ 0x434));
+
+ return MV_OK;
+}
+#endif
+
+/*
+ * Configure phy (called by static init controller) for static flow
+ */
+int ddr3_tip_configure_phy(u32 dev_num)
+{
+ u32 if_id, phy_id;
+ struct hws_topology_map *tm = ddr3_get_topology_map();
+
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA,
+ PAD_ZRI_CALIB_PHY_REG,
+ ((0x7f & g_zpri_data) << 7 | (0x7f & g_znri_data))));
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_CONTROL,
+ PAD_ZRI_CALIB_PHY_REG,
+ ((0x7f & g_zpri_ctrl) << 7 | (0x7f & g_znri_ctrl))));
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA,
+ PAD_ODT_CALIB_PHY_REG,
+ ((0x3f & g_zpodt_data) << 6 | (0x3f & g_znodt_data))));
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_CONTROL,
+ PAD_ODT_CALIB_PHY_REG,
+ ((0x3f & g_zpodt_ctrl) << 6 | (0x3f & g_znodt_ctrl))));
+
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA,
+ PAD_PRE_DISABLE_PHY_REG, 0));
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA,
+ CMOS_CONFIG_PHY_REG, 0));
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_CONTROL,
+ CMOS_CONFIG_PHY_REG, 0));
+
+ for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
+ /* check if the interface is enabled */
+ VALIDATE_ACTIVE(tm->if_act_mask, if_id);
+
+ for (phy_id = 0;
+ phy_id < tm->num_of_bus_per_interface;
+ phy_id++) {
+ VALIDATE_ACTIVE(tm->bus_act_mask, phy_id);
+ /* Vref & clamp */
+ CHECK_STATUS(ddr3_tip_bus_read_modify_write
+ (dev_num, ACCESS_TYPE_UNICAST,
+ if_id, phy_id, DDR_PHY_DATA,
+ PAD_CONFIG_PHY_REG,
+ ((clamp_tbl[if_id] << 4) | vref),
+ ((0x7 << 4) | 0x7)));
+ /* clamp not relevant for control */
+ CHECK_STATUS(ddr3_tip_bus_read_modify_write
+ (dev_num, ACCESS_TYPE_UNICAST,
+ if_id, phy_id, DDR_PHY_CONTROL,
+ PAD_CONFIG_PHY_REG, 0x4, 0x7));
+ }
+ }
+
+ CHECK_STATUS(ddr3_tip_bus_write
+ (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
+ ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA, 0x90,
+ 0x6002));
+
+ return MV_OK;
+}
diff --git a/drivers/ddr/marvell/a38x/old/ddr_topology_def.h b/drivers/ddr/marvell/a38x/old/ddr_topology_def.h
new file mode 100644
index 0000000..229c3a1
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/ddr_topology_def.h
@@ -0,0 +1,121 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _DDR_TOPOLOGY_DEF_H
+#define _DDR_TOPOLOGY_DEF_H
+
+#include "ddr3_training_ip_def.h"
+#include "ddr3_topology_def.h"
+
+#if defined(CONFIG_ARMADA_38X)
+#include "ddr3_a38x.h"
+#endif
+
+/* bus width in bits */
+enum hws_bus_width {
+ BUS_WIDTH_4,
+ BUS_WIDTH_8,
+ BUS_WIDTH_16,
+ BUS_WIDTH_32
+};
+
+enum hws_temperature {
+ HWS_TEMP_LOW,
+ HWS_TEMP_NORMAL,
+ HWS_TEMP_HIGH
+};
+
+enum hws_mem_size {
+ MEM_512M,
+ MEM_1G,
+ MEM_2G,
+ MEM_4G,
+ MEM_8G,
+ MEM_SIZE_LAST
+};
+
+enum hws_timing {
+ HWS_TIM_DEFAULT,
+ HWS_TIM_1T,
+ HWS_TIM_2T
+};
+
+struct bus_params {
+ /* Chip Select (CS) bitmask (bits 0-CS0, bit 1- CS1 ...) */
+ u8 cs_bitmask;
+
+ /*
+ * mirror enable/disable
+ * (bits 0-CS0 mirroring, bit 1- CS1 mirroring ...)
+ */
+ int mirror_enable_bitmask;
+
+ /* DQS Swap (polarity) - true if enable */
+ int is_dqs_swap;
+
+ /* CK swap (polarity) - true if enable */
+ int is_ck_swap;
+};
+
+struct if_params {
+ /* bus configuration */
+ struct bus_params as_bus_params[MAX_BUS_NUM];
+
+ /* Speed Bin Table */
+ enum hws_speed_bin speed_bin_index;
+
+ /* bus width of memory */
+ enum hws_bus_width bus_width;
+
+ /* Bus memory size (MBit) */
+ enum hws_mem_size memory_size;
+
+ /* The DDR frequency for each interfaces */
+ enum hws_ddr_freq memory_freq;
+
+ /*
+ * delay CAS Write Latency
+ * - 0 for using default value (jedec suggested)
+ */
+ u8 cas_wl;
+
+ /*
+ * delay CAS Latency
+ * - 0 for using default value (jedec suggested)
+ */
+ u8 cas_l;
+
+ /* operation temperature */
+ enum hws_temperature interface_temp;
+
+ /* 2T vs 1T mode (by default computed from number of CSs) */
+ enum hws_timing timing;
+};
+
+struct hws_topology_map {
+ /* Number of interfaces (default is 12) */
+ u8 if_act_mask;
+
+ /* Controller configuration per interface */
+ struct if_params interface_params[MAX_INTERFACE_NUM];
+
+ /* BUS per interface (default is 4) */
+ u8 num_of_bus_per_interface;
+
+ /* Bit mask for active buses */
+ u8 bus_act_mask;
+};
+
+/* DDR3 training global configuration parameters */
+struct tune_train_params {
+ u32 ck_delay;
+ u32 ck_delay_16;
+ u32 p_finger;
+ u32 n_finger;
+ u32 phy_reg3_val;
+};
+
+#endif /* _DDR_TOPOLOGY_DEF_H */
diff --git a/drivers/ddr/marvell/a38x/old/ddr_training_ip_db.h b/drivers/ddr/marvell/a38x/old/ddr_training_ip_db.h
new file mode 100644
index 0000000..ff5f817
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/ddr_training_ip_db.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _DDR_TRAINING_IP_DB_H_
+#define _DDR_TRAINING_IP_DB_H_
+
+#include "ddr_topology_def.h"
+#include "ddr3_training_ip_db.h"
+
+u32 speed_bin_table(u8 index, enum speed_bin_table_elements element);
+u32 pattern_table_get_word(u32 dev_num, enum hws_pattern type, u8 index);
+
+#endif /* _DDR3_TRAINING_IP_DB_H_ */
diff --git a/drivers/ddr/marvell/a38x/old/glue_symbol_renames.h b/drivers/ddr/marvell/a38x/old/glue_symbol_renames.h
new file mode 100644
index 0000000..9bdfecd
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/glue_symbol_renames.h
@@ -0,0 +1,247 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Glue old A38x DDR training code with new U-Boot
+ *
+ * This header renames symbols so that they do not clash with new A38x DDR
+ * training code (the one living in the parent directory).
+ *
+ * Copyright (C) 2024 Marek Behún <kabel@kernel.org>
+ */
+
+#ifndef GLUE_SYMBOL_RENAMES_H
+#define GLUE_SYMBOL_RENAMES_H
+
+#define activate_deselect_after_run_alg old_activate_deselect_after_run_alg
+#define activate_select_before_run_alg old_activate_select_before_run_alg
+#define adll_calibration old_adll_calibration
+#define adll_shift_lock old_adll_shift_lock
+#define adll_shift_val old_adll_shift_val
+#define bus_end_window old_bus_end_window
+#define bus_start_window old_bus_start_window
+#define ca_delay old_ca_delay
+#define calibration_update_control old_calibration_update_control
+#define centralization_state old_centralization_state
+#define ck_delay old_ck_delay
+#define clamp_tbl old_clamp_tbl
+#define cl_mask_table old_cl_mask_table
+#define config_func_info old_config_func_info
+#define ctrl_adll old_ctrl_adll
+#define ctrl_sweepres old_ctrl_sweepres
+#define current_valid_window old_current_valid_window
+#define current_vref old_current_vref
+#define cwl_mask_table old_cwl_mask_table
+#define ddr3_calc_mem_cs_size old_ddr3_calc_mem_cs_size
+#define ddr3_hws_set_log_level old_ddr3_hws_set_log_level
+#define ddr3_init old_ddr3_init
+#define ddr3_post_algo_config old_ddr3_post_algo_config
+#define ddr3_post_run_alg old_ddr3_post_run_alg
+#define ddr3_pre_algo_config old_ddr3_pre_algo_config
+#define ddr3_silicon_post_init old_ddr3_silicon_post_init
+#define ddr3_tip_bist_activate old_ddr3_tip_bist_activate
+#define ddr3_tip_bist_read_result old_ddr3_tip_bist_read_result
+#define ddr3_tip_bus_read old_ddr3_tip_bus_read
+#define ddr3_tip_bus_read_modify_write old_ddr3_tip_bus_read_modify_write
+#define ddr3_tip_bus_write old_ddr3_tip_bus_write
+#define ddr3_tip_calc_cs_mask old_ddr3_tip_calc_cs_mask
+#define ddr3_tip_centralization_rx old_ddr3_tip_centralization_rx
+#define ddr3_tip_centralization_tx old_ddr3_tip_centralization_tx
+#define ddr3_tip_centr_skip_min_win_check old_ddr3_tip_centr_skip_min_win_check
+#define ddr3_tip_clean_pbs_result old_ddr3_tip_clean_pbs_result
+#define ddr3_tip_cmd_addr_init_delay old_ddr3_tip_cmd_addr_init_delay
+#define ddr3_tip_configure_cs old_ddr3_tip_configure_cs
+#define ddr3_tip_configure_odpg old_ddr3_tip_configure_odpg
+#define ddr3_tip_configure_phy old_ddr3_tip_configure_phy
+#define ddr3_tip_convert_tune_result old_ddr3_tip_convert_tune_result
+#define ddr3_tip_ddr3_reset_phy_regs old_ddr3_tip_ddr3_reset_phy_regs
+#define ddr3_tip_dynamic_per_bit_read_leveling old_ddr3_tip_dynamic_per_bit_read_leveling
+#define ddr3_tip_dynamic_read_leveling old_ddr3_tip_dynamic_read_leveling
+#define ddr3_tip_dynamic_write_leveling old_ddr3_tip_dynamic_write_leveling
+#define ddr3_tip_dynamic_write_leveling_supp old_ddr3_tip_dynamic_write_leveling_supp
+#define ddr3_tip_enable_init_sequence old_ddr3_tip_enable_init_sequence
+#define ddr3_tip_ext_read old_ddr3_tip_ext_read
+#define ddr3_tip_ext_write old_ddr3_tip_ext_write
+#define ddr3_tip_freq_set old_ddr3_tip_freq_set
+#define ddr3_tip_get_buf_max old_ddr3_tip_get_buf_max
+#define ddr3_tip_get_buf_min old_ddr3_tip_get_buf_min
+#define ddr3_tip_get_buf_ptr old_ddr3_tip_get_buf_ptr
+#define ddr3_tip_get_device_info old_ddr3_tip_get_device_info
+#define ddr3_tip_get_mask_results_dq_reg old_ddr3_tip_get_mask_results_dq_reg
+#define ddr3_tip_get_mask_results_pup_reg_map old_ddr3_tip_get_mask_results_pup_reg_map
+#define ddr3_tip_get_pattern_table old_ddr3_tip_get_pattern_table
+#define ddr3_tip_get_result_ptr old_ddr3_tip_get_result_ptr
+#define ddr3_tip_if_polling old_ddr3_tip_if_polling
+#define ddr3_tip_if_read old_ddr3_tip_if_read
+#define ddr3_tip_if_write old_ddr3_tip_if_write
+#define ddr3_tip_init_config_func old_ddr3_tip_init_config_func
+#define ddr3_tip_ip_training old_ddr3_tip_ip_training
+#define ddr3_tip_ip_training_wrapper old_ddr3_tip_ip_training_wrapper
+#define ddr3_tip_ip_training_wrapper_int old_ddr3_tip_ip_training_wrapper_int
+#define ddr3_tip_is_pup_lock old_ddr3_tip_is_pup_lock
+#define ddr3_tip_legacy_dynamic_read_leveling old_ddr3_tip_legacy_dynamic_read_leveling
+#define ddr3_tip_legacy_dynamic_write_leveling old_ddr3_tip_legacy_dynamic_write_leveling
+#define ddr3_tip_load_all_pattern_to_mem old_ddr3_tip_load_all_pattern_to_mem
+#define ddr3_tip_load_pattern_to_mem old_ddr3_tip_load_pattern_to_mem
+#define ddr3_tip_load_pattern_to_odpg old_ddr3_tip_load_pattern_to_odpg
+#define ddr3_tip_load_phy_values old_ddr3_tip_load_phy_values
+#define ddr3_tip_pbs old_ddr3_tip_pbs
+#define ddr3_tip_pbs_rx old_ddr3_tip_pbs_rx
+#define ddr3_tip_pbs_tx old_ddr3_tip_pbs_tx
+#define ddr3_tip_print_adll old_ddr3_tip_print_adll
+#define ddr3_tip_print_bist_res old_ddr3_tip_print_bist_res
+#define ddr3_tip_print_centralization_result old_ddr3_tip_print_centralization_result
+#define ddr3_tip_print_log old_ddr3_tip_print_log
+#define ddr3_tip_print_stability_log old_ddr3_tip_print_stability_log
+#define ddr3_tip_print_wl_supp_result old_ddr3_tip_print_wl_supp_result
+#define ddr3_tip_process_result old_ddr3_tip_process_result
+#define ddr3_tip_read_training_result old_ddr3_tip_read_training_result
+#define ddr3_tip_reg_dump old_ddr3_tip_reg_dump
+#define ddr3_tip_register_dq_table old_ddr3_tip_register_dq_table
+#define ddr3_tip_register_xsb_info old_ddr3_tip_register_xsb_info
+#define ddr3_tip_reset_fifo_ptr old_ddr3_tip_reset_fifo_ptr
+#define ddr3_tip_restore_dunit_regs old_ddr3_tip_restore_dunit_regs
+#define ddr3_tip_special_rx old_ddr3_tip_special_rx
+#define ddr3_tip_training_ip_test old_ddr3_tip_training_ip_test
+#define ddr3_tip_tune_training_params old_ddr3_tip_tune_training_params
+#define ddr3_tip_vref old_ddr3_tip_vref
+#define ddr3_tip_write_additional_odt_setting old_ddr3_tip_write_additional_odt_setting
+#define ddr3_tip_write_cs_result old_ddr3_tip_write_cs_result
+#define ddr3_tip_write_mrs_cmd old_ddr3_tip_write_mrs_cmd
+#define debug_acc old_debug_acc
+#define debug_centralization old_debug_centralization
+#define debug_dunit old_debug_dunit
+#define debug_leveling old_debug_leveling
+#define debug_mode old_debug_mode
+#define debug_pbs old_debug_pbs
+#define debug_training old_debug_training
+#define debug_training_access old_debug_training_access
+#define debug_training_bist old_debug_training_bist
+#define debug_training_hw_alg old_debug_training_hw_alg
+#define debug_training_ip old_debug_training_ip
+#define debug_training_static old_debug_training_static
+#define default_centrlization_value old_default_centrlization_value
+#define delay_enable old_delay_enable
+#define dfs_low_freq old_dfs_low_freq
+#define dfs_low_phy1 old_dfs_low_phy1
+#define dq_map_table old_dq_map_table
+#define effective_cs old_effective_cs
+#define end_if old_end_if
+#define end_pattern old_end_pattern
+#define finger_test old_finger_test
+#define first_active_if old_first_active_if
+#define freq_info_table old_freq_info_table
+#define g_dic old_g_dic
+#define generic_init_controller old_generic_init_controller
+#define get_valid_win_rx old_get_valid_win_rx
+#define g_odt_config old_g_odt_config
+#define g_rtt_nom old_g_rtt_nom
+#define g_znodt_ctrl old_g_znodt_ctrl
+#define g_znodt_data old_g_znodt_data
+#define g_znri_ctrl old_g_znri_ctrl
+#define g_znri_data old_g_znri_data
+#define g_zpodt_ctrl old_g_zpodt_ctrl
+#define g_zpodt_data old_g_zpodt_data
+#define g_zpri_ctrl old_g_zpri_ctrl
+#define g_zpri_data old_g_zpri_data
+#define hws_ddr3_calc_mem_cs_size old_hws_ddr3_calc_mem_cs_size
+#define hws_ddr3_cs_base_adr_calc old_hws_ddr3_cs_base_adr_calc
+#define hws_ddr3_get_bus_width old_hws_ddr3_get_bus_width
+#define hws_ddr3_get_device_size old_hws_ddr3_get_device_size
+#define hws_ddr3_get_device_width old_hws_ddr3_get_device_width
+#define hws_ddr3_run_bist old_hws_ddr3_run_bist
+#define hws_ddr3_tip_init_controller old_hws_ddr3_tip_init_controller
+#define hws_ddr3_tip_run_alg old_hws_ddr3_tip_run_alg
+#define hws_ddr3_tip_select_ddr_controller old_hws_ddr3_tip_select_ddr_controller
+#define interface_state old_interface_state
+#define is_adll_calib_before_init old_is_adll_calib_before_init
+#define is_bist_reset_bit old_is_bist_reset_bit
+#define is_cbe_required old_is_cbe_required
+#define is_default_centralization old_is_default_centralization
+#define is_dfs_disabled old_is_dfs_disabled
+#define is_dfs_in_init old_is_dfs_in_init
+#define is_freq_old old_is_freq_old
+#define is_pll_before_init old_is_pll_before_init
+#define is_reg_dump old_is_reg_dump
+#define is_rl_old old_is_rl_old
+#define is_tune_result old_is_tune_result
+#define is_validate_window_per_if old_is_validate_window_per_if
+#define is_validate_window_per_pup old_is_validate_window_per_pup
+#define last_valid_window old_last_valid_window
+#define last_vref old_last_vref
+#define lim_vref old_lim_vref
+#define low_freq old_low_freq
+#define mask_results_dq_reg_map old_mask_results_dq_reg_map
+#define mask_results_dq_reg_map_pup3_ecc old_mask_results_dq_reg_map_pup3_ecc
+#define mask_results_pup_reg_map old_mask_results_pup_reg_map
+#define mask_results_pup_reg_map_pup3_ecc old_mask_results_pup_reg_map_pup3_ecc
+#define mask_tune_func old_mask_tune_func
+#define max_adll_per_pup old_max_adll_per_pup
+#define max_pbs_per_pup old_max_pbs_per_pup
+#define max_polling_for_done old_max_polling_for_done
+#define medium_freq old_medium_freq
+#define min_adll_per_pup old_min_adll_per_pup
+#define min_pbs_per_pup old_min_pbs_per_pup
+#define multicast_id old_multicast_id
+#define n_finger_end old_n_finger_end
+#define n_finger_start old_n_finger_start
+#define n_finger_step old_n_finger_step
+#define nominal_adll old_nominal_adll
+#define odt_additional old_odt_additional
+#define odt_config old_odt_config
+#define pattern_table_16 old_pattern_table_16
+#define pattern_table_32 old_pattern_table_32
+#define pattern_table_get_word old_pattern_table_get_word
+#define pbsdelay_per_pup old_pbsdelay_per_pup
+#define pbs_pattern old_pbs_pattern
+#define p_finger_end old_p_finger_end
+#define p_finger_start old_p_finger_start
+#define p_finger_step old_p_finger_step
+#define phy_reg0_val old_phy_reg0_val
+#define phy_reg1_val old_phy_reg1_val
+#define phy_reg2_val old_phy_reg2_val
+#define phy_reg3_val old_phy_reg3_val
+#define phy_reg_bk old_phy_reg_bk
+#define reset_read_fifo old_reset_read_fifo
+#define result_all_bit old_result_all_bit
+#define result_mat old_result_mat
+#define result_mat_rx_dqs old_result_mat_rx_dqs
+#define rl_mid_freq_wa old_rl_mid_freq_wa
+#define rl_test old_rl_test
+#define run_xsb_test old_run_xsb_test
+#define speed_bin_table_t_rc old_speed_bin_table_t_rc
+#define speed_bin_table_t_rcd_t_rp old_speed_bin_table_t_rcd_t_rp
+#define start_if old_start_if
+#define start_pattern old_start_pattern
+#define start_xsb_offset old_start_xsb_offset
+#define sweep_cnt old_sweep_cnt
+#define sweep_pattern old_sweep_pattern
+#define sys_env_device_rev_get old_sys_env_device_rev_get
+#define train_control_element old_train_control_element
+#define train_cs_num old_train_cs_num
+#define train_dev_num old_train_dev_num
+#define train_direction old_train_direction
+#define train_edge_compare old_train_edge_compare
+#define traine_search_dir old_traine_search_dir
+#define train_if_acess old_train_if_acess
+#define train_if_id old_train_if_id
+#define train_if_select old_train_if_select
+#define training_res old_training_res
+#define training_result old_training_result
+#define training_stage old_training_stage
+#define train_init_value old_train_init_value
+#define train_number_iterations old_train_number_iterations
+#define train_pattern old_train_pattern
+#define train_pup_access old_train_pup_access
+#define train_pup_num old_train_pup_num
+#define train_result_type old_train_result_type
+#define train_status old_train_status
+#define traintrain_cs_type old_traintrain_cs_type
+#define twr_mask_table old_twr_mask_table
+#define use_broadcast old_use_broadcast
+#define vref_window_size old_vref_window_size
+#define vref_window_size_th old_vref_window_size_th
+#define window_mem_addr old_window_mem_addr
+#define xsb_test_table old_xsb_test_table
+#define xsb_validate_type old_xsb_validate_type
+#define xsb_validation_base_address old_xsb_validation_base_address
+
+#endif /* !GLUE_SYMBOL_RENAMES_H */
diff --git a/drivers/ddr/marvell/a38x/old/silicon_if.h b/drivers/ddr/marvell/a38x/old/silicon_if.h
new file mode 100644
index 0000000..7fce27d
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/silicon_if.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __silicon_if_H
+#define __silicon_if_H
+
+/* max number of devices supported by driver */
+#ifdef CO_CPU_RUN
+#define HWS_MAX_DEVICE_NUM (1)
+#else
+#define HWS_MAX_DEVICE_NUM (16)
+#endif
+
+#endif /* __silicon_if_H */
diff --git a/drivers/ddr/marvell/a38x/old/xor.h b/drivers/ddr/marvell/a38x/old/xor.h
new file mode 100644
index 0000000..7b1e316
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/old/xor.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _XOR_H
+#define _XOR_H
+
+#define SRAM_BASE 0x40000000
+
+#include "ddr3_hws_hw_training_def.h"
+
+#define MV_XOR_MAX_UNIT 2 /* XOR unit == XOR engine */
+#define MV_XOR_MAX_CHAN 4 /* total channels for all units */
+#define MV_XOR_MAX_CHAN_PER_UNIT 2 /* channels for units */
+
+#define MV_IS_POWER_OF_2(num) (((num) != 0) && (((num) & ((num) - 1)) == 0))
+
+/*
+ * This structure describes address space window. Window base can be
+ * 64 bit, window size up to 4GB
+ */
+struct addr_win {
+ u32 base_low; /* 32bit base low */
+ u32 base_high; /* 32bit base high */
+ u32 size; /* 32bit size */
+};
+
+/* This structure describes SoC units address decode window */
+struct unit_win_info {
+ struct addr_win addr_win; /* An address window */
+ int enable; /* Address decode window is enabled/disabled */
+ u8 attrib; /* chip select attributes */
+ u8 target_id; /* Target Id of this MV_TARGET */
+};
+
+/*
+ * This enumerator describes the type of functionality the XOR channel
+ * can have while using the same data structures.
+ */
+enum xor_type {
+ MV_XOR, /* XOR channel functions as XOR accelerator */
+ MV_DMA, /* XOR channel functions as IDMA channel */
+ MV_CRC32 /* XOR channel functions as CRC 32 calculator */
+};
+
+enum mv_state {
+ MV_IDLE,
+ MV_ACTIVE,
+ MV_PAUSED,
+ MV_UNDEFINED_STATE
+};
+
+/*
+ * This enumerator describes the set of commands that can be applied on
+ * an engine (e.g. IDMA, XOR). Appling a comman depends on the current
+ * status (see MV_STATE enumerator)
+ *
+ * Start can be applied only when status is IDLE
+ * Stop can be applied only when status is IDLE, ACTIVE or PAUSED
+ * Pause can be applied only when status is ACTIVE
+ * Restart can be applied only when status is PAUSED
+ */
+enum mv_command {
+ MV_START, /* Start */
+ MV_STOP, /* Stop */
+ MV_PAUSE, /* Pause */
+ MV_RESTART /* Restart */
+};
+
+enum xor_override_target {
+ SRC_ADDR0, /* Source Address #0 Control */
+ SRC_ADDR1, /* Source Address #1 Control */
+ SRC_ADDR2, /* Source Address #2 Control */
+ SRC_ADDR3, /* Source Address #3 Control */
+ SRC_ADDR4, /* Source Address #4 Control */
+ SRC_ADDR5, /* Source Address #5 Control */
+ SRC_ADDR6, /* Source Address #6 Control */
+ SRC_ADDR7, /* Source Address #7 Control */
+ XOR_DST_ADDR, /* Destination Address Control */
+ XOR_NEXT_DESC /* Next Descriptor Address Control */
+};
+
+enum mv_state mv_xor_state_get(u32 chan);
+void mv_xor_hal_init(u32 xor_chan_num);
+int mv_xor_ctrl_set(u32 chan, u32 xor_ctrl);
+int mv_xor_command_set(u32 chan, enum mv_command command);
+int mv_xor_override_set(u32 chan, enum xor_override_target target, u32 win_num,
+ int enable);
+
+#endif
diff --git a/drivers/dfu/Kconfig b/drivers/dfu/Kconfig
index 0360d9d..9712047 100644
--- a/drivers/dfu/Kconfig
+++ b/drivers/dfu/Kconfig
@@ -68,6 +68,7 @@
config DFU_SF
bool "SPI flash back end for DFU"
+ depends on SPI_FLASH || DM_SPI_FLASH
help
This option enables using DFU to read and write to SPI flash based
storage.
diff --git a/drivers/firmware/ti_sci_static_data.h b/drivers/firmware/ti_sci_static_data.h
index 9662bd9..3370f80 100644
--- a/drivers/firmware/ti_sci_static_data.h
+++ b/drivers/firmware/ti_sci_static_data.h
@@ -85,7 +85,7 @@
#endif /* CONFIG_SOC_K3_J721S2 */
#if IS_ENABLED(CONFIG_SOC_K3_AM625) || IS_ENABLED(CONFIG_SOC_K3_AM62A7) || \
- IS_ENABLED(CONFIG_SOC_K3_AM62P5)
+ IS_ENABLED(CONFIG_SOC_K3_AM62P5) || IS_ENABLED(CONFIG_SOC_K3_J722S)
static struct ti_sci_resource_static_data rm_static_data[] = {
/* BC channels */
{
diff --git a/drivers/fwu-mdata/fwu-mdata-uclass.c b/drivers/fwu-mdata/fwu-mdata-uclass.c
index bab7a7e..92abb94 100644
--- a/drivers/fwu-mdata/fwu-mdata-uclass.c
+++ b/drivers/fwu-mdata/fwu-mdata-uclass.c
@@ -19,7 +19,8 @@
*
* Return: 0 if OK, -ve on error
*/
-int fwu_read_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary)
+int fwu_read_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary,
+ uint32_t size)
{
const struct fwu_mdata_ops *ops = device_get_ops(dev);
@@ -28,7 +29,7 @@
return -ENOSYS;
}
- return ops->read_mdata(dev, mdata, primary);
+ return ops->read_mdata(dev, mdata, primary, size);
}
/**
@@ -36,7 +37,8 @@
*
* Return: 0 if OK, -ve on error
*/
-int fwu_write_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary)
+int fwu_write_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary,
+ uint32_t size)
{
const struct fwu_mdata_ops *ops = device_get_ops(dev);
@@ -45,7 +47,7 @@
return -ENOSYS;
}
- return ops->write_mdata(dev, mdata, primary);
+ return ops->write_mdata(dev, mdata, primary, size);
}
UCLASS_DRIVER(fwu_mdata) = {
diff --git a/drivers/fwu-mdata/gpt_blk.c b/drivers/fwu-mdata/gpt_blk.c
index c728491..97eac36 100644
--- a/drivers/fwu-mdata/gpt_blk.c
+++ b/drivers/fwu-mdata/gpt_blk.c
@@ -81,15 +81,14 @@
return -ENOENT;
}
-static int gpt_read_write_mdata(struct blk_desc *desc,
- struct fwu_mdata *mdata,
- u8 access, u32 part_num)
+static int gpt_read_write_mdata(struct blk_desc *desc, struct fwu_mdata *mdata,
+ u8 access, u32 part_num, u32 size)
{
int ret;
u32 len, blk_start, blkcnt;
struct disk_partition info;
- ALLOC_CACHE_ALIGN_BUFFER_PAD(struct fwu_mdata, mdata_aligned, 1,
+ ALLOC_CACHE_ALIGN_BUFFER_PAD(u8, mdata_aligned, size,
desc->blksz);
if (!mdata)
@@ -101,7 +100,7 @@
return -ENOENT;
}
- len = sizeof(*mdata);
+ len = size;
blkcnt = BLOCK_CNT(len, desc);
if (blkcnt > info.size) {
log_debug("Block count exceeds FWU metadata partition size\n");
@@ -114,7 +113,7 @@
log_debug("Error reading FWU metadata from the device\n");
return -EIO;
}
- memcpy(mdata, mdata_aligned, sizeof(struct fwu_mdata));
+ memcpy(mdata, mdata_aligned, size);
} else {
if (blk_dwrite(desc, blk_start, blkcnt, mdata) != blkcnt) {
log_debug("Error writing FWU metadata to the device\n");
@@ -164,7 +163,7 @@
}
static int fwu_gpt_read_mdata(struct udevice *dev, struct fwu_mdata *mdata,
- bool primary)
+ bool primary, u32 size)
{
struct fwu_mdata_gpt_blk_priv *priv = dev_get_priv(dev);
struct blk_desc *desc = dev_get_uclass_plat(priv->blk_dev);
@@ -177,11 +176,13 @@
}
return gpt_read_write_mdata(desc, mdata, MDATA_READ,
- primary ? g_mdata_part[0] : g_mdata_part[1]);
+ primary ?
+ g_mdata_part[0] : g_mdata_part[1],
+ size);
}
static int fwu_gpt_write_mdata(struct udevice *dev, struct fwu_mdata *mdata,
- bool primary)
+ bool primary, u32 size)
{
struct fwu_mdata_gpt_blk_priv *priv = dev_get_priv(dev);
struct blk_desc *desc = dev_get_uclass_plat(priv->blk_dev);
@@ -194,7 +195,9 @@
}
return gpt_read_write_mdata(desc, mdata, MDATA_WRITE,
- primary ? g_mdata_part[0] : g_mdata_part[1]);
+ primary ?
+ g_mdata_part[0] : g_mdata_part[1],
+ size);
}
static const struct fwu_mdata_ops fwu_gpt_blk_ops = {
diff --git a/drivers/fwu-mdata/raw_mtd.c b/drivers/fwu-mdata/raw_mtd.c
index 17e4517..78a709f 100644
--- a/drivers/fwu-mdata/raw_mtd.c
+++ b/drivers/fwu-mdata/raw_mtd.c
@@ -12,22 +12,11 @@
#include <linux/errno.h>
#include <linux/types.h>
-/* Internal helper structure to move data around */
-struct fwu_mdata_mtd_priv {
- struct mtd_info *mtd;
- char pri_label[50];
- char sec_label[50];
- u32 pri_offset;
- u32 sec_offset;
-};
-
enum fwu_mtd_op {
FWU_MTD_READ,
FWU_MTD_WRITE,
};
-extern struct fwu_mtd_image_info fwu_mtd_images[];
-
static bool mtd_is_aligned_with_block_size(struct mtd_info *mtd, u64 size)
{
return !do_div(size, mtd->erasesize);
@@ -97,22 +86,24 @@
return ret;
}
-static int fwu_mtd_read_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary)
+static int fwu_mtd_read_mdata(struct udevice *dev, struct fwu_mdata *mdata,
+ bool primary, u32 size)
{
struct fwu_mdata_mtd_priv *mtd_priv = dev_get_priv(dev);
struct mtd_info *mtd = mtd_priv->mtd;
u32 offs = primary ? mtd_priv->pri_offset : mtd_priv->sec_offset;
- return mtd_io_data(mtd, offs, sizeof(struct fwu_mdata), mdata, FWU_MTD_READ);
+ return mtd_io_data(mtd, offs, size, mdata, FWU_MTD_READ);
}
-static int fwu_mtd_write_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary)
+static int fwu_mtd_write_mdata(struct udevice *dev, struct fwu_mdata *mdata,
+ bool primary, u32 size)
{
struct fwu_mdata_mtd_priv *mtd_priv = dev_get_priv(dev);
struct mtd_info *mtd = mtd_priv->mtd;
u32 offs = primary ? mtd_priv->pri_offset : mtd_priv->sec_offset;
- return mtd_io_data(mtd, offs, sizeof(struct fwu_mdata), mdata, FWU_MTD_WRITE);
+ return mtd_io_data(mtd, offs, size, mdata, FWU_MTD_WRITE);
}
static int flash_partition_offset(struct udevice *dev, const char *part_name, fdt_addr_t *offset)
@@ -132,7 +123,7 @@
return (int)size;
}
-static int fwu_mdata_mtd_of_to_plat(struct udevice *dev)
+static int get_fwu_mdata_dev(struct udevice *dev)
{
struct fwu_mdata_mtd_priv *mtd_priv = dev_get_priv(dev);
const fdt32_t *phandle_p = NULL;
@@ -142,8 +133,6 @@
fdt_addr_t offset;
int ret, size;
u32 phandle;
- ofnode bank;
- int off_img;
/* Find the FWU mdata storage device */
phandle_p = ofnode_get_property(dev_ofnode(dev),
@@ -197,8 +186,28 @@
return ret;
mtd_priv->sec_offset = offset;
- off_img = 0;
+ return 0;
+}
+
+static int fwu_mtd_image_info_populate(struct udevice *dev, u8 nbanks,
+ u16 nimages)
+{
+ struct fwu_mtd_image_info *mtd_images;
+ struct fwu_mdata_mtd_priv *mtd_priv = dev_get_priv(dev);
+ struct udevice *mtd_dev = mtd_priv->mtd->dev;
+ fdt_addr_t offset;
+ ofnode bank;
+ int off_img;
+ u32 total_images;
+ total_images = nbanks * nimages;
+ mtd_priv->fwu_mtd_images = malloc(sizeof(struct fwu_mtd_image_info) *
+ total_images);
+ if (!mtd_priv->fwu_mtd_images)
+ return -ENOMEM;
+
+ off_img = 0;
+ mtd_images = mtd_priv->fwu_mtd_images;
ofnode_for_each_subnode(bank, dev_ofnode(dev)) {
int bank_num, bank_offset, bank_size;
const char *bank_name;
@@ -217,8 +226,7 @@
int image_num, image_offset, image_size;
const char *uuid;
- if (off_img == CONFIG_FWU_NUM_BANKS *
- CONFIG_FWU_NUM_IMAGES_PER_BANK) {
+ if (off_img == total_images) {
log_err("DT provides more images than configured!\n");
break;
}
@@ -228,11 +236,11 @@
ofnode_read_u32(image, "offset", &image_offset);
ofnode_read_u32(image, "size", &image_size);
- fwu_mtd_images[off_img].start = bank_offset + image_offset;
- fwu_mtd_images[off_img].size = image_size;
- fwu_mtd_images[off_img].bank_num = bank_num;
- fwu_mtd_images[off_img].image_num = image_num;
- strcpy(fwu_mtd_images[off_img].uuidbuf, uuid);
+ mtd_images[off_img].start = bank_offset + image_offset;
+ mtd_images[off_img].size = image_size;
+ mtd_images[off_img].bank_num = bank_num;
+ mtd_images[off_img].image_num = image_num;
+ strcpy(mtd_images[off_img].uuidbuf, uuid);
log_debug("\tImage%d: %s @0x%x\n\n",
image_num, uuid, bank_offset + image_offset);
off_img++;
@@ -244,8 +252,21 @@
static int fwu_mdata_mtd_probe(struct udevice *dev)
{
- /* Ensure the metadata can be read. */
- return fwu_get_mdata(NULL);
+ u8 nbanks;
+ u16 nimages;
+ int ret;
+
+ ret = get_fwu_mdata_dev(dev);
+ if (ret)
+ return ret;
+
+ nbanks = CONFIG_FWU_NUM_BANKS;
+ nimages = CONFIG_FWU_NUM_IMAGES_PER_BANK;
+ ret = fwu_mtd_image_info_populate(dev, nbanks, nimages);
+ if (ret)
+ return ret;
+
+ return 0;
}
static struct fwu_mdata_ops fwu_mtd_ops = {
@@ -264,6 +285,5 @@
.of_match = fwu_mdata_ids,
.ops = &fwu_mtd_ops,
.probe = fwu_mdata_mtd_probe,
- .of_to_plat = fwu_mdata_mtd_of_to_plat,
.priv_auto = sizeof(struct fwu_mdata_mtd_priv),
};
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index b050585..fcca694 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -487,7 +487,7 @@
config ZYNQ_GPIO
bool "Zynq GPIO driver"
depends on DM_GPIO
- default y if ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL
+ default y if ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL2
help
Supports GPIO access on Zynq SoC.
@@ -639,7 +639,7 @@
config ZYNQMP_GPIO_MODEPIN
bool "ZynqMP gpio modepin"
- depends on DM_GPIO
+ depends on DM_GPIO && ZYNQMP_FIRMWARE
help
This config enables the ZynqMP gpio modepin driver. ZynqMP modepin
driver will set and get the status of PS_MODE pins. These modepins
diff --git a/drivers/i2c/mtk_i2c.c b/drivers/i2c/mtk_i2c.c
index 5592fe9..3450177 100644
--- a/drivers/i2c/mtk_i2c.c
+++ b/drivers/i2c/mtk_i2c.c
@@ -221,6 +221,8 @@
void __iomem *pdmabase; /* dma base address*/
struct clk clk_main; /* main clock for i2c bus */
struct clk clk_dma; /* DMA clock for i2c via DMA */
+ struct clk clk_arb; /* DMA clock for i2c ARB */
+ struct clk clk_pmic; /* DMA clock for i2c PMIC */
const struct mtk_i2c_soc_data *soc_data; /* Compatible data for different IC */
int op; /* operation mode */
bool zero_len; /* Only transfer slave address, no data */
@@ -255,6 +257,18 @@
if (ret)
return log_msg_ret("enable clk_dma", ret);
+ if (priv->clk_arb.dev) {
+ ret = clk_enable(&priv->clk_arb);
+ if (ret)
+ return log_msg_ret("enable clk_arb", ret);
+ }
+
+ if (priv->clk_pmic.dev) {
+ ret = clk_enable(&priv->clk_pmic);
+ if (ret)
+ return log_msg_ret("enable clk_pmic", ret);
+ }
+
return 0;
}
@@ -262,6 +276,18 @@
{
int ret;
+ if (priv->clk_pmic.dev) {
+ ret = clk_disable(&priv->clk_pmic);
+ if (ret)
+ return log_msg_ret("disable clk_pmic", ret);
+ }
+
+ if (priv->clk_arb.dev) {
+ ret = clk_disable(&priv->clk_arb);
+ if (ret)
+ return log_msg_ret("disable clk_arb", ret);
+ }
+
ret = clk_disable(&priv->clk_dma);
if (ret)
return log_msg_ret("disable clk_dma", ret);
@@ -748,6 +774,10 @@
ret = clk_get_by_index(dev, 1, &priv->clk_dma);
+ /* optional i2c clock */
+ clk_get_by_name(dev, "arb", &priv->clk_arb);
+ clk_get_by_name(dev, "pmic", &priv->clk_pmic);
+
return ret;
}
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index 47f24e0..67d5ac1 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -54,7 +54,7 @@
config ZYNQMP_IPI
bool "Xilinx ZynqMP IPI controller support"
- depends on DM_MAILBOX && (ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET)
+ depends on DM_MAILBOX && (ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2)
help
This enables support for the Xilinx ZynqMP Inter Processor Interrupt
communication controller.
diff --git a/drivers/memory/ti-gpmc.c b/drivers/memory/ti-gpmc.c
index 8af48e1..e979c43 100644
--- a/drivers/memory/ti-gpmc.c
+++ b/drivers/memory/ti-gpmc.c
@@ -242,20 +242,20 @@
if (l)
time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1;
time_ns = gpmc_clk_ticks_to_ns(l, cs, cd);
- pr_info("gpmc,%s = <%u>; /* %u ns - %u ns; %i ticks%s*/\n",
- name, time_ns, time_ns_min, time_ns, l,
- invalid ? "; invalid " : " ");
+ printf("gpmc,%s = <%u>; /* %u ns - %u ns; %i ticks%s*/\n",
+ name, time_ns, time_ns_min, time_ns, l,
+ invalid ? "; invalid " : " ");
} else {
/* raw format */
- pr_info("gpmc,%s = <%u>;%s\n", name, l,
- invalid ? " /* invalid */" : "");
+ printf("gpmc,%s = <%u>;%s\n", name, l,
+ invalid ? " /* invalid */" : "");
}
return l;
}
#define GPMC_PRINT_CONFIG(cs, config) \
- pr_info("CS%i %s: 0x%08x\n", cs, #config, \
+ printf("CS%i %s: 0x%08x\n", cs, #config, \
gpmc_cs_read_reg(cs, config))
#define GPMC_GET_RAW(reg, st, end, field) \
get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0)
@@ -274,7 +274,7 @@
static void gpmc_show_regs(int cs, const char *desc)
{
- pr_info("gpmc cs%i %s:\n", cs, desc);
+ printf("gpmc cs%i %s:\n", cs, desc);
GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
@@ -291,7 +291,7 @@
{
gpmc_show_regs(cs, desc);
- pr_info("gpmc cs%i access configuration:\n", cs);
+ printf("gpmc cs%i access configuration:\n", cs);
GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 4, 4, "time-para-granularity");
GPMC_GET_RAW(GPMC_CS_CONFIG1, 8, 9, "mux-add-data");
GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 12, 13, 1,
@@ -318,7 +318,7 @@
GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 7, 7, "cycle2cycle-samecsen");
GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 6, 6, "cycle2cycle-diffcsen");
- pr_info("gpmc cs%i timings configuration:\n", cs);
+ printf("gpmc cs%i timings configuration:\n", cs);
GPMC_GET_TICKS(GPMC_CS_CONFIG2, 0, 3, "cs-on-ns");
GPMC_GET_TICKS(GPMC_CS_CONFIG2, 8, 12, "cs-rd-off-ns");
GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
@@ -409,9 +409,9 @@
l = gpmc_cs_read_reg(cs, reg);
if (IS_ENABLED(CONFIG_TI_GPMC_DEBUG)) {
- pr_info("GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
- cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
- (l >> st_bit) & mask, time);
+ printf("GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
+ cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
+ (l >> st_bit) & mask, time);
}
l &= ~(mask << st_bit);
@@ -618,8 +618,8 @@
return -ENXIO;
if (IS_ENABLED(CONFIG_TI_GPMC_DEBUG)) {
- pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
- cs, (div * gpmc_get_fclk_period()) / 1000, div);
+ printf("GPMC CS%d CLK period is %lu ns (div %d)\n",
+ cs, (div * gpmc_get_fclk_period()) / 1000, div);
}
gpmc_cs_bool_timings(cs, &t->bool_timings);
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index d094479..8b13a08 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -41,7 +41,6 @@
config DM_MMC
bool "Enable MMC controllers using Driver Model"
depends on DM
- select BLK
help
This enables the MultiMediaCard (MMC) uclass which supports MMC and
Secure Digital I/O (SDIO) cards. Both removable (SD, micro-SD, etc.)
@@ -249,7 +248,6 @@
bool "Cortina specific extensions for Synopsys DW Memory Card Interface"
depends on DM_MMC
depends on MMC_DW
- depends on BLK
help
This selects support for Cortina SoC specific extensions to the
Synopsys DesignWare Memory Card Interface driver. Select this option
@@ -313,7 +311,7 @@
config MMC_MESON_GX
bool "Meson GX EMMC controller support"
- depends on DM_MMC && BLK && ARCH_MESON
+ depends on DM_MMC && ARCH_MESON
help
Support for EMMC host controller on Meson GX ARM SoCs platform (S905)
@@ -367,7 +365,7 @@
config MVEBU_MMC
bool "Kirkwood MMC controller support"
- depends on DM_MMC && BLK && ARCH_KIRKWOOD
+ depends on DM_MMC && ARCH_KIRKWOOD
help
Support for MMC host controller on Kirkwood SoCs.
If you are on a Kirkwood architecture, say Y here.
@@ -420,7 +418,7 @@
config MMC_UNIPHIER
bool "UniPhier SD/MMC Host Controller support"
depends on ARCH_UNIPHIER
- depends on BLK && DM_MMC
+ depends on DM_MMC
depends on OF_CONTROL
help
This selects support for the Matsushita SD/MMC Host Controller on
@@ -429,7 +427,7 @@
config RENESAS_SDHI
bool "Renesas R-Car SD/MMC Host Controller support"
depends on ARCH_RENESAS
- depends on BLK && DM_MMC
+ depends on DM_MMC
depends on OF_CONTROL
select BOUNCE_BUFFER
help
@@ -439,7 +437,7 @@
config MMC_BCM2835
bool "BCM2835 family custom SD/MMC Host Controller support"
depends on ARCH_BCM283X
- depends on BLK && DM_MMC
+ depends on DM_MMC
depends on OF_CONTROL
default y
help
@@ -459,7 +457,7 @@
config MMC_SANDBOX
bool "Sandbox MMC support"
depends on SANDBOX
- depends on BLK && DM_MMC && OF_CONTROL
+ depends on DM_MMC && OF_CONTROL
help
This select a dummy sandbox MMC driver. At present this does nothing
other than allow sandbox to be build with MMC support. This
@@ -561,7 +559,7 @@
config MMC_SDHCI_ATMEL
bool "Atmel SDHCI controller support"
depends on ARCH_AT91
- depends on DM_MMC && BLK && ARCH_AT91
+ depends on DM_MMC && ARCH_AT91
depends on MMC_SDHCI
help
This enables support for the Atmel SDHCI controller, which supports
@@ -596,7 +594,7 @@
config MMC_SDHCI_CADENCE
bool "SDHCI support for the Cadence SD/SDIO/eMMC controller"
- depends on BLK && DM_MMC
+ depends on DM_MMC
depends on MMC_SDHCI
depends on OF_CONTROL
help
@@ -608,7 +606,7 @@
config MMC_SDHCI_CV1800B
bool "SDHCI support for the CV1800B SD/SDIO/eMMC controller"
- depends on BLK && DM_MMC
+ depends on DM_MMC
depends on MMC_SDHCI
depends on OF_CONTROL
help
@@ -643,7 +641,7 @@
config MMC_SDHCI_F_SDH30
bool "SDHCI support for Fujitsu Semiconductor/Socionext F_SDH30"
- depends on BLK && DM_MMC
+ depends on DM_MMC
depends on MMC_SDHCI
help
This selects the Secure Digital Host Controller Interface (SDHCI)
@@ -663,7 +661,7 @@
config MMC_SDHCI_MSM
bool "Qualcomm SDHCI controller"
- depends on BLK && DM_MMC
+ depends on DM_MMC
depends on MMC_SDHCI
help
Enables support for SDHCI 2.0 controller present on some Qualcomm
@@ -829,7 +827,7 @@
config GENERIC_ATMEL_MCI
bool "Atmel Multimedia Card Interface support"
- depends on DM_MMC && BLK && ARCH_AT91
+ depends on DM_MMC && ARCH_AT91
help
This enables support for Atmel High Speed Multimedia Card Interface
(HSMCI), which supports the MultiMedia Card (MMC) Specification V4.3,
@@ -838,7 +836,7 @@
config STM32_SDMMC2
bool "STMicroelectronics STM32H7 SD/MMC Host Controller support"
- depends on DM_MMC && BLK && OF_CONTROL
+ depends on DM_MMC && OF_CONTROL
help
This selects support for the SD/MMC controller on STM32H7 SoCs.
If you have a board based on such a SoC and with a SD/MMC slot,
@@ -858,7 +856,7 @@
config MMC_MTK
bool "MediaTek SD/MMC Card Interface support"
depends on ARCH_MEDIATEK || ARCH_MTMIPS
- depends on BLK && DM_MMC
+ depends on DM_MMC
depends on OF_CONTROL
help
This selects the MediaTek(R) Secure digital and Multimedia card Interface.
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index 48fac7a..b4c60a4 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -105,6 +105,8 @@
#define FREQSEL_2_BIT BIT(2)
#define STRBSEL_4_BIT BIT(3)
#define DLL_CALIB BIT(4)
+ u32 quirks;
+#define SDHCI_AM654_QUIRK_FORCE_CDTEST BIT(0)
};
struct timing_data {
@@ -350,10 +352,8 @@
}
#define MAX_SDCD_DEBOUNCE_TIME 2000
-static int am654_sdhci_deferred_probe(struct sdhci_host *host)
+static int am654_sdhci_cd_poll(struct mmc *mmc)
{
- struct udevice *dev = host->mmc->dev;
- struct am654_sdhci_plat *plat = dev_get_plat(dev);
unsigned long start;
int val;
@@ -368,12 +368,35 @@
if (get_timer(start) > MAX_SDCD_DEBOUNCE_TIME)
return -ENOMEDIUM;
- val = mmc_getcd(host->mmc);
+ val = mmc_getcd(mmc);
} while (!val);
+ return 0;
+}
+
+static int am654_sdhci_deferred_probe(struct sdhci_host *host)
+{
+ struct udevice *dev = host->mmc->dev;
+ struct am654_sdhci_plat *plat = dev_get_plat(dev);
+ int ret;
+
+ if (!(plat->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST)) {
+ if (am654_sdhci_cd_poll(host->mmc))
+ return -ENOMEDIUM;
+ }
+
am654_sdhci_init(plat);
+ ret = sdhci_probe(dev);
+
- return sdhci_probe(dev);
+ if (plat->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST) {
+ u8 hostctrlreg = sdhci_readb(host, SDHCI_HOST_CONTROL);
+
+ hostctrlreg |= SDHCI_CTRL_CD_TEST_INS | SDHCI_CTRL_CD_TEST;
+ sdhci_writeb(host, hostctrlreg, SDHCI_HOST_CONTROL);
+ }
+
+ return ret;
}
static void am654_sdhci_write_b(struct sdhci_host *host, u8 val, int reg)
@@ -679,6 +702,9 @@
regmap_init_mem_index(dev_ofnode(dev), &plat->base, 1);
+ if (plat->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST)
+ am654_sdhci_deferred_probe(host);
+
return 0;
}
@@ -728,6 +754,8 @@
dev_read_u32(dev, "ti,strobe-sel", &plat->strb_sel);
dev_read_u32(dev, "ti,clkbuf-sel", &plat->clkbuf_sel);
+ if (dev_read_bool(dev, "ti,fails-without-test-cd"))
+ plat->quirks |= SDHCI_AM654_QUIRK_FORCE_CDTEST;
ret = mmc_of_parse(dev, cfg);
if (ret)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index a9b8d7d..03de7dc 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -766,7 +766,7 @@
ret = regulator_set_value(priv->vqmmc_dev,
3300000);
if (ret) {
- printf("Setting to 3.3V error");
+ printf("Setting to 3.3V error: %d\n", ret);
return -EIO;
}
mdelay(5);
@@ -784,7 +784,7 @@
ret = regulator_set_value(priv->vqmmc_dev,
1800000);
if (ret) {
- printf("Setting to 1.8V error");
+ printf("Setting to 1.8V error: %d\n", ret);
return -EIO;
}
}
diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c
index 3a92582..ebd7217 100644
--- a/drivers/mmc/mtk-sd.c
+++ b/drivers/mmc/mtk-sd.c
@@ -335,6 +335,7 @@
bool enhance_rx;
bool builtin_pad_ctrl;
bool default_pad_dly;
+ bool use_internal_cd;
};
struct msdc_delay_phase {
@@ -365,6 +366,10 @@
struct clk src_clk_cg; /* optional, MSDC source clock control gate */
struct clk h_clk; /* MSDC core clock */
+ /* upstream linux clock */
+ struct clk axi_cg_clk; /* optional, AXI clock */
+ struct clk ahb_cg_clk; /* optional, AHB clock */
+
u32 src_clk_freq; /* source clock */
u32 mclk; /* mmc framework required bus clock */
u32 sclk; /* actual calculated bus clock */
@@ -1637,6 +1642,11 @@
clk_enable(&host->h_clk);
if (host->src_clk_cg.dev)
clk_enable(&host->src_clk_cg);
+
+ if (host->axi_cg_clk.dev)
+ clk_enable(&host->axi_cg_clk);
+ if (host->ahb_cg_clk.dev)
+ clk_enable(&host->ahb_cg_clk);
}
static int msdc_drv_probe(struct udevice *dev)
@@ -1650,6 +1660,9 @@
host->dev_comp = (struct msdc_compatible *)dev_get_driver_data(dev);
+ if (host->dev_comp->use_internal_cd)
+ host->builtin_cd = 1;
+
host->src_clk_freq = clk_get_rate(&host->src_clk);
if (host->dev_comp->clk_div_bits == 8)
@@ -1715,18 +1728,31 @@
clk_get_by_name(dev, "source_cg", &host->src_clk_cg); /* optional */
+ /* upstream linux clock */
+ clk_get_by_name(dev, "axi_cg", &host->axi_cg_clk); /* optional */
+ clk_get_by_name(dev, "ahb_cg", &host->ahb_cg_clk); /* optional */
+
#if CONFIG_IS_ENABLED(DM_GPIO)
gpio_request_by_name(dev, "wp-gpios", 0, &host->gpio_wp, GPIOD_IS_IN);
gpio_request_by_name(dev, "cd-gpios", 0, &host->gpio_cd, GPIOD_IS_IN);
#endif
host->hs400_ds_delay = dev_read_u32_default(dev, "hs400-ds-delay", 0);
- host->hs200_cmd_int_delay =
- dev_read_u32_default(dev, "cmd_int_delay", 0);
+ if (dev_read_u32(dev, "mediatek,hs200-cmd-int-delay",
+ &host->hs200_cmd_int_delay))
+ host->hs200_cmd_int_delay =
+ dev_read_u32_default(dev, "cmd_int_delay", 0);
+
host->hs200_write_int_delay =
dev_read_u32_default(dev, "write_int_delay", 0);
- host->latch_ck = dev_read_u32_default(dev, "latch-ck", 0);
+
+ if (dev_read_u32(dev, "mediatek,latch-ck", &host->latch_ck))
+ host->latch_ck = dev_read_u32_default(dev, "latch-ck", 0);
+
host->r_smpl = dev_read_u32_default(dev, "r_smpl", 0);
+ if (dev_read_bool(dev, "mediatek,hs400-cmd-resp-sel-rising"))
+ host->r_smpl = 1;
+
host->builtin_cd = dev_read_u32_default(dev, "builtin-cd", 0);
host->cd_active_high = dev_read_bool(dev, "cd-active-high");
@@ -1775,6 +1801,7 @@
.enhance_rx = false,
.builtin_pad_ctrl = true,
.default_pad_dly = true,
+ .use_internal_cd = true,
};
static const struct msdc_compatible mt7621_compat = {
@@ -1805,7 +1832,7 @@
.data_tune = true,
.busy_check = false,
.stop_clk_fix = false,
- .enhance_rx = false
+ .enhance_rx = false,
};
static const struct msdc_compatible mt7986_compat = {
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 898be5a..28d2b45 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -122,7 +122,8 @@
return 1;
}
-#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL) || defined(CONFIG_ARCH_VERSAL_NET)
+#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL) || \
+ defined(CONFIG_ARCH_VERSAL_NET) || defined(CONFIG_ARCH_VERSAL2)
/* Default settings for ZynqMP Clock Phases */
static const u32 zynqmp_iclk_phases[] = {0, 63, 63, 0, 63, 0,
0, 183, 54, 0, 0};
@@ -156,7 +157,7 @@
[MMC_HS_400] = MMC_TIMING_MMC_HS400,
};
-#if defined(CONFIG_ARCH_VERSAL_NET)
+#if defined(CONFIG_ARCH_VERSAL_NET) || defined(CONFIG_ARCH_VERSAL2)
/**
* arasan_phy_set_delaychain - Set eMMC delay chain based Input/Output clock
*
@@ -865,7 +866,9 @@
ret = sdhci_zynqmp_sdcardclk_set_phase(host, oclk_phase);
if (ret)
return ret;
- } else if (IS_ENABLED(CONFIG_ARCH_VERSAL) &&
+ } else if ((IS_ENABLED(CONFIG_ARCH_VERSAL) ||
+ IS_ENABLED(CONFIG_ARCH_VERSAL_NET) ||
+ IS_ENABLED(CONFIG_ARCH_VERSAL2)) &&
device_is_compatible(dev, "xlnx,versal-8.9a")) {
ret = sdhci_versal_sampleclk_set_phase(host, iclk_phase);
if (ret)
@@ -874,7 +877,8 @@
ret = sdhci_versal_sdcardclk_set_phase(host, oclk_phase);
if (ret)
return ret;
- } else if (IS_ENABLED(CONFIG_ARCH_VERSAL_NET) &&
+ } else if ((IS_ENABLED(CONFIG_ARCH_VERSAL_NET) ||
+ IS_ENABLED(CONFIG_ARCH_VERSAL2)) &&
device_is_compatible(dev, "xlnx,versal-net-emmc")) {
if (mmc->clock >= MIN_PHY_CLK_HZ)
if (iclk_phase == VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLY_CHAIN)
@@ -941,7 +945,9 @@
}
}
- if (IS_ENABLED(CONFIG_ARCH_VERSAL) &&
+ if ((IS_ENABLED(CONFIG_ARCH_VERSAL) ||
+ IS_ENABLED(CONFIG_ARCH_VERSAL_NET) ||
+ IS_ENABLED(CONFIG_ARCH_VERSAL2)) &&
device_is_compatible(dev, "xlnx,versal-8.9a")) {
for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
clk_data->clk_phase_in[i] = versal_iclk_phases[i];
@@ -949,7 +955,8 @@
}
}
- if (IS_ENABLED(CONFIG_ARCH_VERSAL_NET) &&
+ if ((IS_ENABLED(CONFIG_ARCH_VERSAL_NET) ||
+ IS_ENABLED(CONFIG_ARCH_VERSAL2)) &&
device_is_compatible(dev, "xlnx,versal-net-emmc")) {
for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
clk_data->clk_phase_in[i] = versal_net_emmc_iclk_phases[i];
@@ -985,7 +992,7 @@
.platform_execute_tuning = &arasan_sdhci_execute_tuning,
.set_delay = &arasan_sdhci_set_tapdelay,
.set_control_reg = &sdhci_set_control_reg,
-#if defined(CONFIG_ARCH_VERSAL_NET)
+#if defined(CONFIG_ARCH_VERSAL_NET) || defined(CONFIG_ARCH_VERSAL2)
.config_dll = &arasan_sdhci_config_dll,
#endif
};
@@ -1193,7 +1200,8 @@
priv->host->name = dev->name;
-#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL) || defined(CONFIG_ARCH_VERSAL_NET)
+#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL) || defined(CONFIG_ARCH_VERSAL_NET) || \
+ defined(CONFIG_ARCH_VERSAL2)
priv->host->ops = &arasan_ops;
arasan_dt_parse_clk_phases(dev);
#endif
diff --git a/drivers/mtd/nand/raw/nand_macronix.c b/drivers/mtd/nand/raw/nand_macronix.c
index dc972e5..4c6ddd9 100644
--- a/drivers/mtd/nand/raw/nand_macronix.c
+++ b/drivers/mtd/nand/raw/nand_macronix.c
@@ -16,13 +16,183 @@
* GNU General Public License for more details.
*/
+#include <dm/device_compat.h>
#include <linux/mtd/rawnand.h>
+#define ONFI_FEATURE_ADDR_30LFXG18AC_OTP 0x90
+#define MACRONIX_30LFXG18AC_OTP_START_PAGE 2
+#define MACRONIX_30LFXG18AC_OTP_PAGES 30
+#define MACRONIX_30LFXG18AC_OTP_PAGE_SIZE 2112
+#define MACRONIX_30LFXG18AC_OTP_SIZE_BYTES \
+ (MACRONIX_30LFXG18AC_OTP_PAGES * \
+ MACRONIX_30LFXG18AC_OTP_PAGE_SIZE)
+
+#define MACRONIX_30LFXG18AC_OTP_EN BIT(0)
+
+static int macronix_30lfxg18ac_get_otp_info(struct mtd_info *mtd, size_t len,
+ size_t *retlen,
+ struct otp_info *buf)
+{
+ if (len < sizeof(*buf))
+ return -EINVAL;
+
+ /* Always report that OTP is unlocked. Reason is that this
+ * type of flash chip doesn't provide way to check that OTP
+ * is locked or not: subfeature parameter is implemented as
+ * volatile register. Technically OTP region could be locked
+ * and become readonly, but as there is no way to check it,
+ * don't allow to lock it ('_lock_user_prot_reg' callback
+ * always returns -EOPNOTSUPP) and thus we report that OTP
+ * is unlocked.
+ */
+ buf->locked = 0;
+ buf->start = 0;
+ buf->length = MACRONIX_30LFXG18AC_OTP_SIZE_BYTES;
+
+ *retlen = sizeof(*buf);
+
+ return 0;
+}
+
+static int macronix_30lfxg18ac_otp_enable(struct nand_chip *nand)
+{
+ u8 feature_buf[ONFI_SUBFEATURE_PARAM_LEN] = { 0 };
+ struct mtd_info *mtd;
+
+ mtd = nand_to_mtd(nand);
+ feature_buf[0] = MACRONIX_30LFXG18AC_OTP_EN;
+
+ return nand->onfi_set_features(mtd, nand, ONFI_FEATURE_ADDR_30LFXG18AC_OTP, feature_buf);
+}
+
+static int macronix_30lfxg18ac_otp_disable(struct nand_chip *nand)
+{
+ u8 feature_buf[ONFI_SUBFEATURE_PARAM_LEN] = { 0 };
+ struct mtd_info *mtd;
+
+ mtd = nand_to_mtd(nand);
+ return nand->onfi_set_features(mtd, nand, ONFI_FEATURE_ADDR_30LFXG18AC_OTP, feature_buf);
+}
+
+static int __macronix_30lfxg18ac_rw_otp(struct mtd_info *mtd,
+ loff_t offs_in_flash,
+ size_t len, size_t *retlen,
+ u_char *buf, bool write)
+{
+ struct nand_chip *nand;
+ size_t bytes_handled;
+ off_t offs_in_page;
+ u64 page;
+ int ret;
+
+ nand = mtd_to_nand(mtd);
+ nand->select_chip(mtd, 0);
+
+ ret = macronix_30lfxg18ac_otp_enable(nand);
+ if (ret)
+ goto out_otp;
+
+ page = offs_in_flash;
+ /* 'page' will be result of division. */
+ offs_in_page = do_div(page, MACRONIX_30LFXG18AC_OTP_PAGE_SIZE);
+ bytes_handled = 0;
+
+ while (bytes_handled < len &&
+ page < MACRONIX_30LFXG18AC_OTP_PAGES) {
+ size_t bytes_to_handle;
+ u64 phys_page = page + MACRONIX_30LFXG18AC_OTP_START_PAGE;
+
+ bytes_to_handle = min_t(size_t, len - bytes_handled,
+ MACRONIX_30LFXG18AC_OTP_PAGE_SIZE -
+ offs_in_page);
+
+ if (write)
+ ret = nand_prog_page_op(nand, phys_page, offs_in_page,
+ &buf[bytes_handled], bytes_to_handle);
+ else
+ ret = nand_read_page_op(nand, phys_page, offs_in_page,
+ &buf[bytes_handled], bytes_to_handle);
+ if (ret)
+ goto out_otp;
+
+ bytes_handled += bytes_to_handle;
+ offs_in_page = 0;
+ page++;
+ }
+
+ *retlen = bytes_handled;
+
+out_otp:
+ if (ret)
+ dev_err(mtd->dev, "failed to perform OTP IO: %i\n", ret);
+
+ ret = macronix_30lfxg18ac_otp_disable(nand);
+ if (ret)
+ dev_err(mtd->dev, "failed to leave OTP mode after %s\n",
+ write ? "write" : "read");
+
+ nand->select_chip(mtd, -1);
+
+ return ret;
+}
+
+static int macronix_30lfxg18ac_write_otp(struct mtd_info *mtd, loff_t to,
+ size_t len, size_t *rlen,
+ u_char *buf)
+{
+ return __macronix_30lfxg18ac_rw_otp(mtd, to, len, rlen, (u_char *)buf,
+ true);
+}
+
+static int macronix_30lfxg18ac_read_otp(struct mtd_info *mtd, loff_t from,
+ size_t len, size_t *rlen,
+ u_char *buf)
+{
+ return __macronix_30lfxg18ac_rw_otp(mtd, from, len, rlen, buf, false);
+}
+
+static int macronix_30lfxg18ac_lock_otp(struct mtd_info *mtd, loff_t from,
+ size_t len)
+{
+ /* See comment in 'macronix_30lfxg18ac_get_otp_info()'. */
+ return -EOPNOTSUPP;
+}
+
+static void macronix_nand_setup_otp(struct nand_chip *chip)
+{
+ static const char * const supported_otp_models[] = {
+ "MX30LF1G18AC",
+ "MX30LF2G18AC",
+ "MX30LF4G18AC",
+ };
+ int i;
+
+ if (!chip->onfi_version ||
+ !(le16_to_cpu(chip->onfi_params.opt_cmd)
+ & ONFI_OPT_CMD_SET_GET_FEATURES))
+ return;
+
+ for (i = 0; i < ARRAY_SIZE(supported_otp_models); i++) {
+ if (!strcmp(chip->onfi_params.model, supported_otp_models[i])) {
+ struct mtd_info *mtd;
+
+ mtd = nand_to_mtd(chip);
+ mtd->_get_user_prot_info = macronix_30lfxg18ac_get_otp_info;
+ mtd->_read_user_prot_reg = macronix_30lfxg18ac_read_otp;
+ mtd->_write_user_prot_reg = macronix_30lfxg18ac_write_otp;
+ mtd->_lock_user_prot_reg = macronix_30lfxg18ac_lock_otp;
+ return;
+ }
+ }
+}
+
static int macronix_nand_init(struct nand_chip *chip)
{
if (nand_is_slc(chip))
chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
+ macronix_nand_setup_otp(chip);
+
return 0;
}
diff --git a/drivers/mtd/nand/raw/pxa3xx_nand.c b/drivers/mtd/nand/raw/pxa3xx_nand.c
index 17c5601..b78b4e6 100644
--- a/drivers/mtd/nand/raw/pxa3xx_nand.c
+++ b/drivers/mtd/nand/raw/pxa3xx_nand.c
@@ -799,6 +799,11 @@
info->ecc_err_cnt = 0;
info->ndcb3 = 0;
info->need_wait = 0;
+ /*
+ * Reset max_bitflips to zero. Once command is complete,
+ * max_bitflips for this READ is returned in ecc.read_page()
+ */
+ info->max_bitflips = 0;
switch (command) {
case NAND_CMD_READ0:
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 982dd25..aea611f 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -1804,11 +1804,62 @@
if (ret < 0)
return ret;
#endif
+
write_enable(nor);
- ret = nor->write(nor, addr, page_remain, buf + i);
- if (ret < 0)
- goto write_err;
- written = ret;
+
+ /*
+ * On DTR capable flashes like Micron Xcella the writes cannot
+ * start or end at an odd address in DTR mode. So we need to
+ * append or prepend extra 0xff bytes to make sure the start
+ * address and end address are even.
+ */
+ if (spi_nor_protocol_is_dtr(nor->write_proto) &&
+ ((addr | page_remain) & 1)) {
+ u_char *tmp;
+ size_t extra_bytes = 0;
+
+ tmp = kmalloc(nor->page_size, 0);
+ if (!tmp) {
+ ret = -ENOMEM;
+ goto write_err;
+ }
+
+ /* Prepend a 0xff byte if the start address is odd. */
+ if (addr & 1) {
+ tmp[0] = 0xff;
+ memcpy(tmp + 1, buf + i, page_remain);
+ addr--;
+ page_remain++;
+ extra_bytes++;
+ } else {
+ memcpy(tmp, buf + i, page_remain);
+ }
+
+ /* Append a 0xff byte if the end address is odd. */
+ if ((addr + page_remain) & 1) {
+ tmp[page_remain + extra_bytes] = 0xff;
+ extra_bytes++;
+ page_remain++;
+ }
+
+ ret = nor->write(nor, addr, page_remain, tmp);
+
+ kfree(tmp);
+
+ if (ret < 0)
+ goto write_err;
+
+ /*
+ * We write extra bytes but they are not part of the
+ * original write.
+ */
+ written = ret - extra_bytes;
+ } else {
+ ret = nor->write(nor, addr, page_remain, buf + i);
+ if (ret < 0)
+ goto write_err;
+ written = ret;
+ }
ret = spi_nor_wait_till_ready(nor);
if (ret)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 684206e..2206d73 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -274,7 +274,7 @@
{ INFO("mx66l2g45g", 0xc2201c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx25l1633e", 0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) },
{ INFO("mx25r6435f", 0xc22817, 0, 64 * 1024, 128, SECT_4K) },
- { INFO("mx66uw2g345gx0", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+ { INFO("mx66uw2g345gx0", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_READ) },
{ INFO("mx66lm1g45g", 0xc2853b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx25lm51245g", 0xc2853a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx25lw51245g", 0xc2863a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
diff --git a/drivers/mtd/ubi/Kconfig b/drivers/mtd/ubi/Kconfig
index 5783d36..fd446d6 100644
--- a/drivers/mtd/ubi/Kconfig
+++ b/drivers/mtd/ubi/Kconfig
@@ -9,6 +9,7 @@
config MTD_UBI
bool "Enable UBI - Unsorted block images"
+ depends on MTD
select RBTREE
select MTD_PARTITIONS
help
diff --git a/drivers/net/bcmgenet.c b/drivers/net/bcmgenet.c
index 4e1f8ed..a0264dc 100644
--- a/drivers/net/bcmgenet.c
+++ b/drivers/net/bcmgenet.c
@@ -360,6 +360,10 @@
int length)
{
struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
+ void *desc_base = priv->rx_desc_base + priv->rx_index * DMA_DESC_SIZE;
+ u32 addr = readl(desc_base + DMA_DESC_ADDRESS_LO);
+
+ flush_dcache_range(addr, addr + RX_BUF_LENGTH);
/* Tell the MAC we have consumed that last receive buffer. */
priv->c_index = (priv->c_index + 1) & 0xFFFF;
diff --git a/drivers/net/dwc_eth_qos_stm32.c b/drivers/net/dwc_eth_qos_stm32.c
index fbc08bb..cffaa10 100644
--- a/drivers/net/dwc_eth_qos_stm32.c
+++ b/drivers/net/dwc_eth_qos_stm32.c
@@ -266,6 +266,12 @@
if (ret)
dev_warn(dev, "No phy clock provided %d\n", ret);
+ /* Get reset gpio pin (optional) */
+ ret = gpio_request_by_name(dev, "phy-reset-gpios", 0,
+ &eqos->phy_reset_gpio, GPIOD_IS_OUT);
+ if (ret)
+ pr_warn("No phy reset gpio provided: %d\n", ret);
+
dev_dbg(dev, "%s: OK\n", __func__);
return 0;
@@ -277,6 +283,21 @@
return ret;
}
+static int eqos_start_resets_stm32(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) {
+ dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
+ udelay(2);
+ dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
+ }
+
+ return 0;
+}
+
static int eqos_remove_resources_stm32(struct udevice *dev)
{
dev_dbg(dev, "%s:\n", __func__);
@@ -292,7 +313,7 @@
.eqos_probe_resources = eqos_probe_resources_stm32,
.eqos_remove_resources = eqos_remove_resources_stm32,
.eqos_stop_resets = eqos_null_ops,
- .eqos_start_resets = eqos_null_ops,
+ .eqos_start_resets = eqos_start_resets_stm32,
.eqos_stop_clks = eqos_stop_clks_stm32,
.eqos_start_clks = eqos_start_clks_stm32,
.eqos_calibrate_pads = eqos_null_ops,
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index 663d900..fcb2053 100644
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c
@@ -107,6 +107,12 @@
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT) },
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT) },
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT) },
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I226_K) },
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I226_LMVP) },
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I226_LM) },
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I226_V) },
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I226_IT) },
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I226_UNPROGRAMMED) },
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED) },
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED) },
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER) },
@@ -1568,6 +1574,12 @@
case E1000_DEV_ID_ICH8_IGP_M:
hw->mac_type = e1000_ich8lan;
break;
+ case PCI_DEVICE_ID_INTEL_I226_K:
+ case PCI_DEVICE_ID_INTEL_I226_LMVP:
+ case PCI_DEVICE_ID_INTEL_I226_LM:
+ case PCI_DEVICE_ID_INTEL_I226_V:
+ case PCI_DEVICE_ID_INTEL_I226_IT:
+ case PCI_DEVICE_ID_INTEL_I226_UNPROGRAMMED:
case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED:
case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED:
case PCI_DEVICE_ID_INTEL_I210_COPPER:
@@ -4842,6 +4854,8 @@
hw->phy_type = e1000_phy_igb;
break;
case I225_I_PHY_ID:
+ case I226_LM_PHY_ID:
+ case I226_I_PHY_ID:
hw->phy_type = e1000_phy_igc;
break;
/* Fall Through */
@@ -4953,6 +4967,10 @@
match = true;
if (hw->phy_id == I225_I_PHY_ID)
match = true;
+ if (hw->phy_id == I226_LM_PHY_ID)
+ match = true;
+ if (hw->phy_id == I226_I_PHY_ID)
+ match = true;
break;
default:
DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h
index e131112..aa64932 100644
--- a/drivers/net/e1000.h
+++ b/drivers/net/e1000.h
@@ -2421,7 +2421,9 @@
#define BME1000_E_PHY_ID 0x01410CB0
#define I210_I_PHY_ID 0x01410C00
+#define I226_LM_PHY_ID 0x67C9DC10
#define I225_I_PHY_ID 0x67C9DCC0
+#define I226_I_PHY_ID 0x67C9DCD0
/* Miscellaneous PHY bit definitions. */
#define PHY_PREAMBLE 0xFFFFFFFF
diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c
index 04b711e..7e53492 100644
--- a/drivers/net/mcffec.c
+++ b/drivers/net/mcffec.c
@@ -11,6 +11,7 @@
*/
#include <config.h>
+#include <cpu_func.h>
#include <env.h>
#include <hang.h>
#include <malloc.h>
@@ -399,7 +400,7 @@
#endif
#ifdef CONFIG_SYS_UNIFY_CACHE
- icache_invalid();
+ invalidate_icache_all();
#endif
j = 0;
@@ -433,7 +434,7 @@
for (;;) {
#ifdef CONFIG_SYS_UNIFY_CACHE
- icache_invalid();
+ invalidate_icache_all();
#endif
/* If nothing received - leave for() loop */
if (info->rxbd[info->rx_idx].cbd_sc & BD_ENET_RX_EMPTY)
diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c
index 94f17a9..5098afe 100644
--- a/drivers/net/mtk_eth.c
+++ b/drivers/net/mtk_eth.c
@@ -1964,7 +1964,9 @@
return -ENODEV;
}
- priv->pn_swap = ofnode_read_bool(args.node, "pn_swap");
+ /* Upstream linux use mediatek,pnswap instead of pn_swap */
+ priv->pn_swap = ofnode_read_bool(args.node, "pn_swap") ||
+ ofnode_read_bool(args.node, "mediatek,pnswap");
} else if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII) {
/* get corresponding usxgmii phandle */
ret = dev_read_phandle_with_args(dev, "mediatek,usxgmiisys",
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 3d96938..73064b2 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -23,6 +23,12 @@
help
Select this if you want to control which phy address is used
+config PHY_ANEG_TIMEOUT
+ int "PHY auto-negotiation timeout"
+ default 4000
+ help
+ Default PHY auto-negotiation timeout.
+
if PHY_ADDR_ENABLE
config PHY_ADDR
int "PHY address"
diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c
index 4517a6b..d2db8d9 100644
--- a/drivers/net/phy/aquantia.c
+++ b/drivers/net/phy/aquantia.c
@@ -566,9 +566,9 @@
if ((i++ % 500) == 0)
printf(".");
} while (!aquantia_link_is_up(phydev) &&
- i < (4 * PHY_ANEG_TIMEOUT));
+ i < (4 * CONFIG_PHY_ANEG_TIMEOUT));
- if (i > PHY_ANEG_TIMEOUT)
+ if (i > CONFIG_PHY_ANEG_TIMEOUT)
printf(" TIMEOUT !\n");
}
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index fbf85d9..716a1d4 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -250,7 +250,7 @@
/*
* Timeout reached ?
*/
- if (i > (PHY_ANEG_TIMEOUT / 50)) {
+ if (i > (CONFIG_PHY_ANEG_TIMEOUT / 50)) {
printf(" TIMEOUT !\n");
phydev->link = 0;
return -ETIMEDOUT;
diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index a1a39f6..4d87e2d 100644
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -361,7 +361,7 @@
* and the external PHY is not obtained.
*/
debug("axiemac: waiting for link status of the PCS/PMA PHY");
- while (retry_cnt * 10 < PHY_ANEG_TIMEOUT) {
+ while (retry_cnt * 10 < CONFIG_PHY_ANEG_TIMEOUT) {
rc = phyread(priv, priv->pcsaddr, MII_BMSR, &mii_reg);
if ((mii_reg & BMSR_LSTATUS) && mii_reg != 0xffff && !rc) {
debug(".Done\n");
diff --git a/drivers/nvme/nvme_show.c b/drivers/nvme/nvme_show.c
index 1581023..b06cb5c 100644
--- a/drivers/nvme/nvme_show.c
+++ b/drivers/nvme/nvme_show.c
@@ -67,7 +67,7 @@
printf("Blk device %d: LBA Format Support:\n", ns->devnum);
for (i = 0; i < id->nlbaf; i++) {
- printf("\tLBA Foramt %d Support: ", i);
+ printf("\tLBA Format %d Support: ", i);
if (i == ns->flbas)
printf("(current)\n");
else
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 8d02ab8..22a56f4 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -350,6 +350,13 @@
Say Y here if you want to enable Gen2 PCIe controller,
which could be found on MT7623 SoC family.
+config PCIE_MEDIATEK_GEN3
+ bool "MediaTek PCIe Gen3 controller"
+ depends on ARCH_MEDIATEK
+ help
+ Say Y here if you want to enable Gen3 PCIe controller,
+ which could be found on the Mediatek Filogic SoC family.
+
config PCIE_DW_MESON
bool "Amlogic Meson DesignWare based PCIe controller"
depends on ARCH_MESON
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 2927c51..5b2d296 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -42,6 +42,7 @@
obj-$(CONFIG_PCIE_DW_COMMON) += pcie_dw_common.o
obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o
obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o
+obj-$(CONFIG_PCIE_MEDIATEK_GEN3) += pcie_mediatek_gen3.o
obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o
obj-$(CONFIG_PCIE_DW_ROCKCHIP) += pcie_dw_rockchip.o
obj-$(CONFIG_PCIE_DW_MESON) += pcie_dw_meson.o
diff --git a/drivers/pci/pcie_mediatek_gen3.c b/drivers/pci/pcie_mediatek_gen3.c
new file mode 100644
index 0000000..0149eda
--- /dev/null
+++ b/drivers/pci/pcie_mediatek_gen3.c
@@ -0,0 +1,384 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek PCIe host controller driver.
+ *
+ * Copyright (c) 2023 John Crispin <john@phrozen.org>
+ * Driver is based on u-boot gen1/2 and upstream linux gen3 code
+ */
+
+#include <clk.h>
+#include <dm.h>
+#include <generic-phy.h>
+#include <log.h>
+#include <malloc.h>
+#include <pci.h>
+#include <reset.h>
+#include <asm/io.h>
+#include <dm/device_compat.h>
+#include <dm/devres.h>
+#include <linux/bitops.h>
+#include <linux/iopoll.h>
+#include <linux/list.h>
+#include "pci_internal.h"
+
+/* PCIe shared registers */
+#define PCIE_CFG_ADDR 0x20
+#define PCIE_CFG_DATA 0x24
+
+#define PCIE_SETTING_REG 0x80
+
+#define PCIE_PCI_IDS_1 0x9c
+#define PCIE_RC_MODE BIT(0)
+#define PCI_CLASS(class) ((class) << 8)
+
+#define PCIE_CFGNUM_REG 0x140
+#define PCIE_CFG_DEVFN(devfn) ((devfn) & GENMASK(7, 0))
+#define PCIE_CFG_BUS(bus) (((bus) << 8) & GENMASK(15, 8))
+#define PCIE_CFG_BYTE_EN(bytes) (((bytes) << 16) & GENMASK(19, 16))
+#define PCIE_CFG_FORCE_BYTE_EN BIT(20)
+#define PCIE_CFG_OFFSET_ADDR 0x1000
+#define PCIE_CFG_HEADER(bus, devfn) (PCIE_CFG_BUS(bus) | PCIE_CFG_DEVFN(devfn))
+
+#define PCIE_RST_CTRL_REG 0x148
+#define PCIE_MAC_RSTB BIT(0)
+#define PCIE_PHY_RSTB BIT(1)
+#define PCIE_BRG_RSTB BIT(2)
+#define PCIE_PE_RSTB BIT(3)
+
+#define PCIE_LINK_STATUS_REG 0x154
+#define PCIE_PORT_LINKUP BIT(8)
+
+#define PCIE_INT_ENABLE_REG 0x180
+
+#define PCIE_MISC_CTRL_REG 0x348
+#define PCIE_DISABLE_DVFSRC_VLT_REQ BIT(1)
+
+#define PCIE_TRANS_TABLE_BASE_REG 0x800
+#define PCIE_ATR_SRC_ADDR_MSB_OFFSET 0x4
+#define PCIE_ATR_TRSL_ADDR_LSB_OFFSET 0x8
+#define PCIE_ATR_TRSL_ADDR_MSB_OFFSET 0xc
+#define PCIE_ATR_TRSL_PARAM_OFFSET 0x10
+#define PCIE_ATR_TLB_SET_OFFSET 0x20
+
+#define PCIE_MAX_TRANS_TABLES 8
+#define PCIE_ATR_EN BIT(0)
+#define PCIE_ATR_SIZE(size) \
+ (((((size) - 1) << 1) & GENMASK(6, 1)) | PCIE_ATR_EN)
+#define PCIE_ATR_ID(id) ((id) & GENMASK(3, 0))
+#define PCIE_ATR_TYPE_MEM PCIE_ATR_ID(0)
+#define PCIE_ATR_TYPE_IO PCIE_ATR_ID(1)
+#define PCIE_ATR_TLP_TYPE(type) (((type) << 16) & GENMASK(18, 16))
+#define PCIE_ATR_TLP_TYPE_MEM PCIE_ATR_TLP_TYPE(0)
+#define PCIE_ATR_TLP_TYPE_IO PCIE_ATR_TLP_TYPE(2)
+
+struct mtk_pcie {
+ void __iomem *base;
+ void *priv;
+ struct clk pl_250m_ck;
+ struct clk tl_26m_ck;
+ struct clk peri_26m_ck;
+ struct clk top_133m_ck;
+ struct reset_ctl reset_phy;
+ struct reset_ctl reset_mac;
+ struct phy phy;
+};
+
+static void mtk_pcie_config_tlp_header(const struct udevice *bus,
+ pci_dev_t devfn,
+ int where, int size)
+{
+ struct mtk_pcie *pcie = dev_get_priv(bus);
+ int bytes;
+ u32 val;
+
+ size = 1 << size;
+ bytes = (GENMASK(size - 1, 0) & 0xf) << (where & 0x3);
+
+ val = PCIE_CFG_FORCE_BYTE_EN | PCIE_CFG_BYTE_EN(bytes) |
+ PCIE_CFG_HEADER(PCI_BUS(devfn), (devfn >> 8));
+
+ writel(val, pcie->base + PCIE_CFGNUM_REG);
+}
+
+static int mtk_pcie_config_address(const struct udevice *udev, pci_dev_t bdf,
+ uint offset, void **paddress)
+{
+ struct mtk_pcie *pcie = dev_get_priv(udev);
+
+ *paddress = pcie->base + PCIE_CFG_OFFSET_ADDR + offset;
+
+ return 0;
+}
+
+static int mtk_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
+ uint offset, ulong *valuep,
+ enum pci_size_t size)
+{
+ int ret;
+
+ mtk_pcie_config_tlp_header(bus, bdf, offset, size);
+ ret = pci_generic_mmap_read_config(bus, mtk_pcie_config_address,
+ bdf, offset, valuep, size);
+ return ret;
+}
+
+static int mtk_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
+ uint offset, ulong value,
+ enum pci_size_t size)
+{
+ mtk_pcie_config_tlp_header(bus, bdf, offset, size);
+
+ switch (size) {
+ case PCI_SIZE_8:
+ case PCI_SIZE_16:
+ value <<= (offset & 0x3) * 8;
+ case PCI_SIZE_32:
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return pci_generic_mmap_write_config(bus, mtk_pcie_config_address,
+ bdf, (offset & ~0x3), value, PCI_SIZE_32);
+}
+
+static const struct dm_pci_ops mtk_pcie_ops = {
+ .read_config = mtk_pcie_read_config,
+ .write_config = mtk_pcie_write_config,
+};
+
+static int mtk_pcie_set_trans_table(struct udevice *dev, struct mtk_pcie *pcie,
+ u64 cpu_addr, u64 pci_addr, u64 size,
+ unsigned long type, int num)
+{
+ void __iomem *table;
+ u32 val;
+
+ if (num >= PCIE_MAX_TRANS_TABLES) {
+ dev_err(dev, "not enough translate table for addr: %#llx, limited to [%d]\n",
+ (unsigned long long)cpu_addr, PCIE_MAX_TRANS_TABLES);
+ return -ENODEV;
+ }
+
+ dev_dbg(dev, "set trans table %d: %#llx %#llx, %#llx\n", num, cpu_addr,
+ pci_addr, size);
+ table = pcie->base + PCIE_TRANS_TABLE_BASE_REG +
+ num * PCIE_ATR_TLB_SET_OFFSET;
+
+ writel(lower_32_bits(cpu_addr) | PCIE_ATR_SIZE(fls(size) - 1), table);
+ writel(upper_32_bits(cpu_addr), table + PCIE_ATR_SRC_ADDR_MSB_OFFSET);
+ writel(lower_32_bits(pci_addr), table + PCIE_ATR_TRSL_ADDR_LSB_OFFSET);
+ writel(upper_32_bits(pci_addr), table + PCIE_ATR_TRSL_ADDR_MSB_OFFSET);
+
+ if (type == PCI_REGION_IO)
+ val = PCIE_ATR_TYPE_IO | PCIE_ATR_TLP_TYPE_IO;
+ else
+ val = PCIE_ATR_TYPE_MEM | PCIE_ATR_TLP_TYPE_MEM;
+ writel(val, table + PCIE_ATR_TRSL_PARAM_OFFSET);
+
+ return 0;
+}
+
+static int mtk_pcie_startup_port(struct udevice *dev)
+{
+ struct mtk_pcie *pcie = dev_get_priv(dev);
+ struct udevice *ctlr = pci_get_controller(dev);
+ struct pci_controller *hose = dev_get_uclass_priv(ctlr);
+ u32 val;
+ int i, err;
+
+ /* Set as RC mode */
+ val = readl(pcie->base + PCIE_SETTING_REG);
+ val |= PCIE_RC_MODE;
+ writel(val, pcie->base + PCIE_SETTING_REG);
+
+ /* setup RC BARs */
+ writel(PCI_BASE_ADDRESS_MEM_TYPE_64,
+ pcie->base + PCI_BASE_ADDRESS_0);
+ writel(0x0, pcie->base + PCI_BASE_ADDRESS_1);
+
+ /* setup interrupt pins */
+ clrsetbits_le32(pcie->base + PCI_INTERRUPT_LINE,
+ 0xff00, 0x100);
+
+ /* setup bus numbers */
+ clrsetbits_le32(pcie->base + PCI_PRIMARY_BUS,
+ 0xffffff, 0x00ff0100);
+
+ /* setup command register */
+ clrsetbits_le32(pcie->base + PCI_PRIMARY_BUS,
+ 0xffff,
+ PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
+ PCI_COMMAND_MASTER | PCI_COMMAND_SERR);
+
+ /* Set class code */
+ val = readl(pcie->base + PCIE_PCI_IDS_1);
+ val &= ~GENMASK(31, 8);
+ val |= PCI_CLASS(PCI_CLASS_BRIDGE_PCI << 8);
+ writel(val, pcie->base + PCIE_PCI_IDS_1);
+
+ /* Mask all INTx interrupts */
+ val = readl(pcie->base + PCIE_INT_ENABLE_REG);
+ val &= ~0xFF000000;
+ writel(val, pcie->base + PCIE_INT_ENABLE_REG);
+
+ /* Disable DVFSRC voltage request */
+ val = readl(pcie->base + PCIE_MISC_CTRL_REG);
+ val |= PCIE_DISABLE_DVFSRC_VLT_REQ;
+ writel(val, pcie->base + PCIE_MISC_CTRL_REG);
+
+ /* Assert all reset signals */
+ val = readl(pcie->base + PCIE_RST_CTRL_REG);
+ val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB;
+ writel(val, pcie->base + PCIE_RST_CTRL_REG);
+
+ /*
+ * Described in PCIe CEM specification sections 2.2 (PERST# Signal)
+ * and 2.2.1 (Initial Power-Up (G3 to S0)).
+ * The deassertion of PERST# should be delayed 100ms (TPVPERL)
+ * for the power and clock to become stable.
+ */
+ mdelay(100);
+
+ /* De-assert reset signals */
+ val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB);
+ writel(val, pcie->base + PCIE_RST_CTRL_REG);
+
+ mdelay(100);
+
+ /* De-assert PERST# signals */
+ val &= ~(PCIE_PE_RSTB);
+ writel(val, pcie->base + PCIE_RST_CTRL_REG);
+
+ /* 100ms timeout value should be enough for Gen1/2 training */
+ err = readl_poll_timeout(pcie->base + PCIE_LINK_STATUS_REG, val,
+ !!(val & PCIE_PORT_LINKUP),
+ 100 * 1000);
+ if (err) {
+ dev_dbg(dev, "no card detected\n");
+ return -ETIMEDOUT;
+ }
+ dev_dbg(dev, "detected a card\n");
+
+ for (i = 0; i < hose->region_count; i++) {
+ struct pci_region *reg = &hose->regions[i];
+
+ if (reg->flags != PCI_REGION_MEM)
+ continue;
+
+ mtk_pcie_set_trans_table(dev, pcie, reg->bus_start, reg->phys_start,
+ reg->size, reg->flags, 0);
+ }
+
+ return 0;
+}
+
+static int mtk_pcie_power_on(struct udevice *dev)
+{
+ struct mtk_pcie *pcie = dev_get_priv(dev);
+ int err;
+
+ pcie->base = dev_remap_addr_name(dev, "pcie-mac");
+ if (!pcie->base)
+ return -ENOENT;
+
+ pcie->priv = dev;
+
+ /* pcie-phy is optional (mt7988 doesn't need it) */
+ generic_phy_get_by_name(dev, "pcie-phy", &pcie->phy);
+
+ /*
+ * Upstream linux kernel devine these clock without clock-names
+ * and use clk bulk API to enable them all.
+ */
+ err = clk_get_by_index(dev, 0, &pcie->pl_250m_ck);
+ if (err)
+ return err;
+
+ err = clk_get_by_index(dev, 1, &pcie->tl_26m_ck);
+ if (err)
+ return err;
+
+ err = clk_get_by_index(dev, 2, &pcie->peri_26m_ck);
+ if (err)
+ return err;
+
+ err = clk_get_by_index(dev, 3, &pcie->top_133m_ck);
+ if (err)
+ return err;
+
+ if (pcie->phy.dev) {
+ err = generic_phy_init(&pcie->phy);
+ if (err)
+ return err;
+
+ err = generic_phy_power_on(&pcie->phy);
+ if (err)
+ goto err_phy_on;
+ }
+
+ err = clk_enable(&pcie->pl_250m_ck);
+ if (err)
+ goto err_clk_pl_250m;
+
+ err = clk_enable(&pcie->tl_26m_ck);
+ if (err)
+ goto err_clk_tl_26m;
+
+ err = clk_enable(&pcie->peri_26m_ck);
+ if (err)
+ goto err_clk_peri_26m;
+
+ err = clk_enable(&pcie->top_133m_ck);
+ if (err)
+ goto err_clk_top_133m;
+
+ err = mtk_pcie_startup_port(dev);
+ if (err)
+ goto err_startup;
+
+ return 0;
+
+err_startup:
+err_clk_top_133m:
+ clk_disable(&pcie->top_133m_ck);
+err_clk_peri_26m:
+ clk_disable(&pcie->peri_26m_ck);
+err_clk_tl_26m:
+ clk_disable(&pcie->tl_26m_ck);
+err_clk_pl_250m:
+ clk_disable(&pcie->pl_250m_ck);
+err_phy_on:
+ if (pcie->phy.dev)
+ generic_phy_exit(&pcie->phy);
+
+ return err;
+}
+
+static int mtk_pcie_probe(struct udevice *dev)
+{
+ struct mtk_pcie *pcie = dev_get_priv(dev);
+ int err;
+
+ pcie->priv = dev;
+
+ err = mtk_pcie_power_on(dev);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+static const struct udevice_id mtk_pcie_ids[] = {
+ { .compatible = "mediatek,mt8192-pcie" },
+ { }
+};
+
+U_BOOT_DRIVER(pcie_mediatek_gen3) = {
+ .name = "pcie_mediatek_gen3",
+ .id = UCLASS_PCI,
+ .of_match = mtk_pcie_ids,
+ .ops = &mtk_pcie_ops,
+ .probe = mtk_pcie_probe,
+ .priv_auto = sizeof(struct mtk_pcie),
+};
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 8f76787..e12347e 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -263,6 +263,8 @@
bool "MediaTek T-PHY Driver"
depends on PHY
depends on ARCH_MEDIATEK || SOC_MT7621
+ select REGMAP
+ select SYSCON
help
MediaTek T-PHY driver supports usb2.0, usb3.0 ports, PCIe and
SATA, and meanwhile supports two version T-PHY which have
diff --git a/drivers/phy/meson-gxl-usb2.c b/drivers/phy/meson-gxl-usb2.c
index 92c2851..140e936 100644
--- a/drivers/phy/meson-gxl-usb2.c
+++ b/drivers/phy/meson-gxl-usb2.c
@@ -19,8 +19,6 @@
#include <linux/printk.h>
#include <linux/usb/otg.h>
-#include <asm/arch/usb-gx.h>
-
#include <linux/bitops.h>
#include <linux/compat.h>
@@ -121,33 +119,40 @@
udelay(RESET_COMPLETE_TIME);
}
-void phy_meson_gxl_usb2_set_mode(struct phy *phy, enum usb_dr_mode mode)
+static int phy_meson_gxl_usb2_set_mode(struct phy *phy, enum phy_mode mode, int submode)
{
struct udevice *dev = phy->dev;
struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
uint val;
+ if (submode)
+ return -EOPNOTSUPP;
+
regmap_read(priv->regmap, U2P_R0, &val);
switch (mode) {
- case USB_DR_MODE_UNKNOWN:
- case USB_DR_MODE_HOST:
- case USB_DR_MODE_OTG:
+ case PHY_MODE_USB_DEVICE:
+ val &= ~U2P_R0_DM_PULLDOWN;
+ val &= ~U2P_R0_DP_PULLDOWN;
+ val |= U2P_R0_ID_PULLUP;
+ break;
+
+ case PHY_MODE_USB_HOST:
+ case PHY_MODE_USB_OTG:
val |= U2P_R0_DM_PULLDOWN;
val |= U2P_R0_DP_PULLDOWN;
val &= ~U2P_R0_ID_PULLUP;
break;
- case USB_DR_MODE_PERIPHERAL:
- val &= ~U2P_R0_DM_PULLDOWN;
- val &= ~U2P_R0_DP_PULLDOWN;
- val |= U2P_R0_ID_PULLUP;
- break;
+ default:
+ return -EINVAL;
}
regmap_write(priv->regmap, U2P_R0, val);
phy_meson_gxl_usb2_reset(priv);
+
+ return 0;
}
static int phy_meson_gxl_usb2_power_on(struct phy *phy)
@@ -161,7 +166,7 @@
val &= ~U2P_R0_POWER_ON_RESET;
regmap_write(priv->regmap, U2P_R0, val);
- phy_meson_gxl_usb2_set_mode(phy, USB_DR_MODE_HOST);
+ phy_meson_gxl_usb2_set_mode(phy, PHY_MODE_USB_HOST, 0);
return 0;
}
@@ -183,6 +188,7 @@
struct phy_ops meson_gxl_usb2_phy_ops = {
.power_on = phy_meson_gxl_usb2_power_on,
.power_off = phy_meson_gxl_usb2_power_off,
+ .set_mode = phy_meson_gxl_usb2_set_mode,
};
int meson_gxl_usb2_phy_probe(struct udevice *dev)
diff --git a/drivers/phy/phy-mtk-tphy.c b/drivers/phy/phy-mtk-tphy.c
index 6f9ac15..0a45dc5 100644
--- a/drivers/phy/phy-mtk-tphy.c
+++ b/drivers/phy/phy-mtk-tphy.c
@@ -10,6 +10,8 @@
#include <generic-phy.h>
#include <malloc.h>
#include <mapmem.h>
+#include <regmap.h>
+#include <syscon.h>
#include <asm/io.h>
#include <dm/device_compat.h>
#include <dm/devres.h>
@@ -215,6 +217,14 @@
#define ANA_EQ_EYE_CTRL_SIGNAL5 0xdc
#define RG_CDR_BIRLTD0_GEN3_MSK GENMASK(4, 0)
+/* PHY switch between pcie/usb3/sgmii/sata */
+#define USB_PHY_SWITCH_CTRL 0x0
+#define RG_PHY_SW_TYPE GENMASK(3, 0)
+#define RG_PHY_SW_PCIE 0x0
+#define RG_PHY_SW_USB3 0x1
+#define RG_PHY_SW_SGMII 0x2
+#define RG_PHY_SW_SATA 0x3
+
enum mtk_phy_version {
MTK_TPHY_V1 = 1,
MTK_TPHY_V2,
@@ -257,6 +267,10 @@
u32 index;
u32 type;
+ struct regmap *type_sw;
+ u32 type_sw_reg;
+ u32 type_sw_index;
+
u32 eye_vrt;
u32 eye_term;
u32 discth;
@@ -616,6 +630,67 @@
FIELD_PREP(PA6_RG_U2_PRE_EMP, instance->pre_emphasis));
}
+/* type switch for usb3/pcie/sgmii/sata */
+static int phy_type_syscon_get(struct udevice *dev, struct mtk_phy_instance *instance,
+ ofnode dn)
+{
+ struct ofnode_phandle_args args;
+ int err;
+
+ if (!ofnode_read_bool(dn, "mediatek,syscon-type"))
+ return 0;
+
+ err = ofnode_parse_phandle_with_args(dn, "mediatek,syscon-type",
+ NULL, 2, 0, &args);
+ if (err)
+ return err;
+
+ instance->type_sw_reg = args.args[0];
+ instance->type_sw_index = args.args[1] & 0x3; /* <=3 */
+ instance->type_sw = syscon_node_to_regmap(args.node);
+ if (IS_ERR(instance->type_sw))
+ return PTR_ERR(instance->type_sw);
+
+ debug("phy-%s.%d: type_sw - reg %#x, index %d\n",
+ dev->name, instance->index, instance->type_sw_reg,
+ instance->type_sw_index);
+
+ return 0;
+}
+
+static int phy_type_set(struct mtk_phy_instance *instance)
+{
+ int type;
+ u32 offset;
+
+ if (!instance->type_sw)
+ return 0;
+
+ switch (instance->type) {
+ case PHY_TYPE_USB3:
+ type = RG_PHY_SW_USB3;
+ break;
+ case PHY_TYPE_PCIE:
+ type = RG_PHY_SW_PCIE;
+ break;
+ case PHY_TYPE_SGMII:
+ type = RG_PHY_SW_SGMII;
+ break;
+ case PHY_TYPE_SATA:
+ type = RG_PHY_SW_SATA;
+ break;
+ case PHY_TYPE_USB2:
+ default:
+ return 0;
+ }
+
+ offset = instance->type_sw_index * BITS_PER_BYTE;
+ regmap_update_bits(instance->type_sw, instance->type_sw_reg,
+ RG_PHY_SW_TYPE << offset, type << offset);
+
+ return 0;
+}
+
static int mtk_phy_init(struct phy *phy)
{
struct mtk_tphy *tphy = dev_get_priv(phy->dev);
@@ -746,6 +821,7 @@
}
phy_parse_property(tphy, instance);
+ phy_type_set(instance);
return 0;
}
@@ -807,6 +883,10 @@
&instance->da_ref_clk);
if (err)
return err;
+
+ err = phy_type_syscon_get(dev, instance, subnode);
+ if (err)
+ return err;
}
return 0;
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7981.c b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
index 3fa198e..4bc4abe 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
@@ -1050,4 +1050,5 @@
.ops = &mtk_pinctrl_ops,
.probe = mtk_pinctrl_mt7981_probe,
.priv_auto = sizeof(struct mtk_pinctrl_priv),
+ .flags = DM_FLAG_PRE_RELOC,
};
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
index 37fc28b..ede3959 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
@@ -761,6 +761,15 @@
if (!drv)
return -ENOENT;
+ /*
+ * Support upstream linux DTSI that define gpio-controller
+ * in the root node (instead of a dedicated subnode)
+ */
+ if (dev_read_bool(parent, "gpio-controller")) {
+ node = dev_ofnode(parent);
+ goto bind;
+ }
+
ret = -ENOENT;
dev_for_each_subnode(node, parent)
if (ofnode_read_bool(node, "gpio-controller")) {
@@ -771,6 +780,7 @@
if (ret)
return ret;
+bind:
ret = device_bind_with_driver_data(parent, &mtk_gpio_driver,
"mediatek_gpio", 0, node,
&dev);
diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c
index 52c726c..15ebd57 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c
@@ -179,7 +179,7 @@
.direction_output = meson_gpio_direction_output,
};
-const struct driver meson_axg_gpio_driver = {
+U_BOOT_DRIVER(meson_axg_gpio) = {
.name = "meson-axg-gpio",
.id = UCLASS_GPIO,
.probe = meson_gpio_probe,
diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg.c b/drivers/pinctrl/meson/pinctrl-meson-axg.c
index 94e09cd..ed3f92b 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-axg.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-axg.c
@@ -939,7 +939,7 @@
.num_groups = ARRAY_SIZE(meson_axg_periphs_groups),
.num_funcs = ARRAY_SIZE(meson_axg_periphs_functions),
.num_banks = ARRAY_SIZE(meson_axg_periphs_banks),
- .gpio_driver = &meson_axg_gpio_driver,
+ .gpio_driver = DM_DRIVER_REF(meson_axg_gpio),
.pmx_data = &meson_axg_periphs_pmx_banks_data,
};
@@ -953,7 +953,7 @@
.num_groups = ARRAY_SIZE(meson_axg_aobus_groups),
.num_funcs = ARRAY_SIZE(meson_axg_aobus_functions),
.num_banks = ARRAY_SIZE(meson_axg_aobus_banks),
- .gpio_driver = &meson_axg_gpio_driver,
+ .gpio_driver = DM_DRIVER_REF(meson_axg_gpio),
.pmx_data = &meson_axg_aobus_pmx_banks_data,
};
diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg.h b/drivers/pinctrl/meson/pinctrl-meson-axg.h
index c8d2b3a..a6581ba 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-axg.h
+++ b/drivers/pinctrl/meson/pinctrl-meson-axg.h
@@ -61,6 +61,6 @@
}
extern const struct pinctrl_ops meson_axg_pinctrl_ops;
-extern const struct driver meson_axg_gpio_driver;
+extern U_BOOT_DRIVER(meson_axg_gpio);
#endif /* __PINCTRL_MESON_AXG_H__ */
diff --git a/drivers/pinctrl/meson/pinctrl-meson-g12a.c b/drivers/pinctrl/meson/pinctrl-meson-g12a.c
index 24f47f8..67114df 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-g12a.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-g12a.c
@@ -1253,7 +1253,7 @@
.num_groups = ARRAY_SIZE(meson_g12a_periphs_groups),
.num_funcs = ARRAY_SIZE(meson_g12a_periphs_functions),
.num_banks = ARRAY_SIZE(meson_g12a_periphs_banks),
- .gpio_driver = &meson_axg_gpio_driver,
+ .gpio_driver = DM_DRIVER_REF(meson_axg_gpio),
.pmx_data = &meson_g12a_periphs_pmx_banks_data,
};
@@ -1267,7 +1267,7 @@
.num_groups = ARRAY_SIZE(meson_g12a_aobus_groups),
.num_funcs = ARRAY_SIZE(meson_g12a_aobus_functions),
.num_banks = ARRAY_SIZE(meson_g12a_aobus_banks),
- .gpio_driver = &meson_axg_gpio_driver,
+ .gpio_driver = DM_DRIVER_REF(meson_axg_gpio),
.pmx_data = &meson_g12a_aobus_pmx_banks_data,
};
diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c b/drivers/pinctrl/qcom/pinctrl-qcom.c
index 3c3336e..26a3fba 100644
--- a/drivers/pinctrl/qcom/pinctrl-qcom.c
+++ b/drivers/pinctrl/qcom/pinctrl-qcom.c
@@ -44,6 +44,7 @@
{ "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 2 },
{ "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
{ "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 3 },
+ { "bias-pull-down", PIN_CONFIG_BIAS_PULL_UP, 1 },
{ "output-high", PIN_CONFIG_OUTPUT, 1, },
{ "output-low", PIN_CONFIG_OUTPUT, 0, },
};
@@ -102,14 +103,47 @@
return 0;
}
+static int msm_pinconf_set_special(struct msm_pinctrl_priv *priv, unsigned int pin_selector,
+ unsigned int param, unsigned int argument)
+{
+ unsigned int offset = pin_selector - priv->data->pin_data.special_pins_start;
+ const struct msm_special_pin_data *data;
+
+ if (!priv->data->pin_data.special_pins_data)
+ return 0;
+
+ data = &priv->data->pin_data.special_pins_data[offset];
+
+ switch (param) {
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ argument = (argument / 2) - 1;
+ clrsetbits_le32(priv->base + data->ctl_reg,
+ GENMASK(2, 0) << data->drv_bit,
+ argument << data->drv_bit);
+ break;
+ case PIN_CONFIG_BIAS_DISABLE:
+ clrbits_le32(priv->base + data->ctl_reg,
+ TLMM_GPIO_PULL_MASK << data->pull_bit);
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ clrsetbits_le32(priv->base + data->ctl_reg,
+ TLMM_GPIO_PULL_MASK << data->pull_bit,
+ argument << data->pull_bit);
+ break;
+ default:
+ return 0;
+ }
+
+ return 0;
+}
+
static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector,
unsigned int param, unsigned int argument)
{
struct msm_pinctrl_priv *priv = dev_get_priv(dev);
- /* Always NOP for special pins */
if (qcom_is_special_pin(&priv->data->pin_data, pin_selector))
- return 0;
+ return msm_pinconf_set_special(priv, pin_selector, param, argument);
switch (param) {
case PIN_CONFIG_DRIVE_STRENGTH:
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550.c b/drivers/pinctrl/qcom/pinctrl-sm8550.c
index 7265cb7..c65dfe0 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8550.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8550.c
@@ -18,6 +18,37 @@
{"gpio", 0},
};
+#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
+ { \
+ .name = pg_name, \
+ .ctl_reg = ctl, \
+ .io_reg = 0, \
+ .pull_bit = pull, \
+ .drv_bit = drv, \
+ .oe_bit = -1, \
+ .in_bit = -1, \
+ .out_bit = -1, \
+ }
+
+#define UFS_RESET(pg_name, ctl, io) \
+ { \
+ .name = pg_name, \
+ .ctl_reg = ctl, \
+ .io_reg = io, \
+ .pull_bit = 3, \
+ .drv_bit = 0, \
+ .oe_bit = -1, \
+ .in_bit = -1, \
+ .out_bit = 0, \
+ }
+
+static const struct msm_special_pin_data msm_special_pins_data[] = {
+ [0] = UFS_RESET("ufs_reset", 0xde000, 0xde004),
+ [1] = SDC_QDSD_PINGROUP("sdc2_clk", 0xd6000, 14, 6),
+ [2] = SDC_QDSD_PINGROUP("sdc2_cmd", 0xd6000, 11, 3),
+ [3] = SDC_QDSD_PINGROUP("sdc2_data", 0xd6000, 9, 0),
+};
+
static const char *sm8550_get_function_name(struct udevice *dev,
unsigned int selector)
{
@@ -27,15 +58,9 @@
static const char *sm8550_get_pin_name(struct udevice *dev,
unsigned int selector)
{
- static const char *special_pins_names[] = {
- "ufs_reset",
- "sdc2_clk",
- "sdc2_cmd",
- "sdc2_data",
- };
-
if (selector >= 210 && selector <= 213)
- snprintf(pin_name, MAX_PIN_NAME_LEN, special_pins_names[selector - 210]);
+ snprintf(pin_name, MAX_PIN_NAME_LEN,
+ msm_special_pins_data[selector - 210].name);
else
snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
@@ -52,6 +77,7 @@
.pin_data = {
.pin_count = 214,
.special_pins_start = 210,
+ .special_pins_data = msm_special_pins_data,
},
.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
.get_function_name = sm8550_get_function_name,
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8650.c b/drivers/pinctrl/qcom/pinctrl-sm8650.c
index d6cc1bb..58fc94e 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8650.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8650.c
@@ -18,6 +18,37 @@
{"gpio", 0},
};
+#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
+ { \
+ .name = pg_name, \
+ .ctl_reg = ctl, \
+ .io_reg = 0, \
+ .pull_bit = pull, \
+ .drv_bit = drv, \
+ .oe_bit = -1, \
+ .in_bit = -1, \
+ .out_bit = -1, \
+ }
+
+#define UFS_RESET(pg_name, ctl, io) \
+ { \
+ .name = pg_name, \
+ .ctl_reg = ctl, \
+ .io_reg = io, \
+ .pull_bit = 3, \
+ .drv_bit = 0, \
+ .oe_bit = -1, \
+ .in_bit = -1, \
+ .out_bit = 0, \
+ }
+
+static const struct msm_special_pin_data msm_special_pins_data[] = {
+ [0] = UFS_RESET("ufs_reset", 0xde004, 0xdf000),
+ [1] = SDC_QDSD_PINGROUP("sdc2_clk", 0xd6000, 14, 6),
+ [2] = SDC_QDSD_PINGROUP("sdc2_cmd", 0xd6000, 11, 3),
+ [3] = SDC_QDSD_PINGROUP("sdc2_data", 0xd6000, 9, 0),
+};
+
static const char *sm8650_get_function_name(struct udevice *dev,
unsigned int selector)
{
@@ -27,15 +58,9 @@
static const char *sm8650_get_pin_name(struct udevice *dev,
unsigned int selector)
{
- static const char *special_pins_names[] = {
- "ufs_reset",
- "sdc2_clk",
- "sdc2_cmd",
- "sdc2_data",
- };
-
if (selector >= 210 && selector <= 213)
- snprintf(pin_name, MAX_PIN_NAME_LEN, special_pins_names[selector - 210]);
+ snprintf(pin_name, MAX_PIN_NAME_LEN,
+ msm_special_pins_data[selector - 210].name);
else
snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
@@ -52,6 +77,7 @@
.pin_data = {
.pin_count = 214,
.special_pins_start = 210,
+ .special_pins_data = msm_special_pins_data,
},
.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
.get_function_name = sm8650_get_function_name,
diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c
index 6749c15..aa58b79 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
@@ -2386,6 +2386,14 @@
SCIF_CLK_MARK,
};
+static const unsigned int scif_clk2_pins[] = {
+ /* SCIF_CLK2 */
+ RCAR_GP_PIN(8, 11),
+};
+static const unsigned int scif_clk2_mux[] = {
+ SCIF_CLK2_MARK,
+};
+
/* - SSI ------------------------------------------------- */
static const unsigned int ssi_data_pins[] = {
/* SSI_SD */
@@ -2696,6 +2704,7 @@
SH_PFC_PIN_GROUP(scif4_clk),
SH_PFC_PIN_GROUP(scif4_ctrl),
SH_PFC_PIN_GROUP(scif_clk),
+ SH_PFC_PIN_GROUP(scif_clk2),
SH_PFC_PIN_GROUP(ssi_data),
SH_PFC_PIN_GROUP(ssi_ctrl),
@@ -3017,6 +3026,10 @@
"scif_clk",
};
+static const char * const scif_clk2_groups[] = {
+ "scif_clk2",
+};
+
static const char * const ssi_groups[] = {
"ssi_data",
"ssi_ctrl",
@@ -3104,6 +3117,7 @@
SH_PFC_FUNCTION(scif3),
SH_PFC_FUNCTION(scif4),
SH_PFC_FUNCTION(scif_clk),
+ SH_PFC_FUNCTION(scif_clk2),
SH_PFC_FUNCTION(ssi),
diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
index 3e74e2f..d449d07 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
@@ -13,10 +13,10 @@
#include <linux/libfdt.h>
#include "pinctrl-rockchip.h"
+#include <dt-bindings/pinctrl/rockchip.h>
#define MAX_ROCKCHIP_PINS_ENTRIES 30
#define MAX_ROCKCHIP_GPIO_PER_BANK 32
-#define RK_FUNC_GPIO 0
static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin)
{
@@ -131,8 +131,12 @@
if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
return RK_FUNC_GPIO;
- regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
- ? priv->regmap_pmu : priv->regmap_base;
+ if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
+ regmap = priv->regmap_pmu;
+ else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
+ regmap = (pin % 8 < 4) ? priv->regmap_pmu : priv->regmap_base;
+ else
+ regmap = priv->regmap_base;
/* get basic quadrupel of mux registers and the correct reg inside */
mux_type = bank->iomux[iomux_num].type;
@@ -142,6 +146,28 @@
if (bank->recalced_mask & BIT(pin))
rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
+ if (IS_ENABLED(CONFIG_ROCKCHIP_RK3588)) {
+ if (bank->bank_num == 0) {
+ if (pin >= RK_PB4 && pin <= RK_PD7) {
+ u32 reg0 = 0;
+
+ reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
+ ret = regmap_read(regmap, reg0, &val);
+ if (ret)
+ return ret;
+
+ ret = ((val >> bit) & mask);
+ if (ret != 8)
+ return ret;
+
+ reg = reg + 0x8000; /* BUS_IOC_BASE */
+ regmap = priv->regmap_base;
+ }
+ } else if (bank->bank_num > 0) {
+ reg += 0x8000; /* BUS_IOC_BASE */
+ }
+ }
+
ret = regmap_read(regmap, reg, &val);
if (ret)
return ret;
@@ -171,7 +197,7 @@
}
if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
- if (mux != IOMUX_GPIO_ONLY) {
+ if (mux != RK_FUNC_GPIO) {
debug("pin %d only supports a gpio mux\n", pin);
return -ENOTSUPP;
}
@@ -531,12 +557,14 @@
/* preset iomux offset value, set new start value */
if (iom->offset >= 0) {
- if (iom->type & IOMUX_SOURCE_PMU)
+ if ((iom->type & IOMUX_SOURCE_PMU) ||
+ (iom->type & IOMUX_L_SOURCE_PMU))
pmu_offs = iom->offset;
else
grf_offs = iom->offset;
} else { /* set current iomux offset */
- iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
+ iom->offset = ((iom->type & IOMUX_SOURCE_PMU) ||
+ (iom->type & IOMUX_L_SOURCE_PMU)) ?
pmu_offs : grf_offs;
}
diff --git a/drivers/power/domain/ti-power-domain.c b/drivers/power/domain/ti-power-domain.c
index b059dd3..5e7a4c5 100644
--- a/drivers/power/domain/ti-power-domain.c
+++ b/drivers/power/domain/ti-power-domain.c
@@ -71,6 +71,24 @@
}
static const struct soc_attr ti_k3_soc_pd_data[] = {
+#if IS_ENABLED(CONFIG_SOC_K3_AM625)
+ {
+ .family = "AM62X",
+ .data = &am62x_pd_platdata,
+ },
+#endif
+#if IS_ENABLED(CONFIG_SOC_K3_AM62A7)
+ {
+ .family = "AM62AX",
+ .data = &am62ax_pd_platdata,
+ },
+#endif
+#if IS_ENABLED(CONFIG_SOC_K3_AM62P5)
+ {
+ .family = "AM62PX",
+ .data = &am62px_pd_platdata,
+ },
+#endif
#if IS_ENABLED(CONFIG_SOC_K3_J721E)
{
.family = "J721E",
@@ -87,16 +105,10 @@
.data = &j721s2_pd_platdata,
},
#endif
-#if IS_ENABLED(CONFIG_SOC_K3_AM625)
- {
- .family = "AM62X",
- .data = &am62x_pd_platdata,
- },
-#endif
-#if IS_ENABLED(CONFIG_SOC_K3_AM62A7)
+#if IS_ENABLED(CONFIG_SOC_K3_J722S)
{
- .family = "AM62AX",
- .data = &am62ax_pd_platdata,
+ .family = "J722S",
+ .data = &j722s_pd_platdata,
},
#endif
#if IS_ENABLED(CONFIG_SOC_K3_J784S4)
@@ -105,12 +117,6 @@
.data = &j784s4_pd_platdata,
},
#endif
-#if IS_ENABLED(CONFIG_SOC_K3_AM62P5)
- {
- .family = "AM62PX",
- .data = &am62px_pd_platdata,
- },
-#endif
{ /* sentinel */ }
};
diff --git a/drivers/power/pmic/rk8xx.c b/drivers/power/pmic/rk8xx.c
index 12ff26a..617bb51 100644
--- a/drivers/power/pmic/rk8xx.c
+++ b/drivers/power/pmic/rk8xx.c
@@ -6,6 +6,7 @@
#include <dm.h>
#include <dm/lists.h>
+#include <bitfield.h>
#include <errno.h>
#include <log.h>
#include <linux/bitfield.h>
@@ -277,10 +278,9 @@
return ret;
priv->variant = ((msb << 8) | lsb) & RK8XX_ID_MSK;
- show_variant = priv->variant;
+ show_variant = bitfield_extract_by_mask(priv->variant, RK8XX_ID_MSK);
switch (priv->variant) {
case RK808_ID:
- show_variant = 0x808; /* RK808 hardware ID is 0 */
break;
case RK805_ID:
case RK816_ID:
@@ -311,7 +311,7 @@
init_data_num = ARRAY_SIZE(rk806_init_reg);
break;
default:
- printf("Unknown PMIC: RK%x!!\n", priv->variant);
+ printf("Unknown PMIC: RK%x!!\n", show_variant);
return -EINVAL;
}
diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c
index 66fd531..88a8525 100644
--- a/drivers/power/regulator/regulator-uclass.c
+++ b/drivers/power/regulator/regulator-uclass.c
@@ -517,7 +517,7 @@
dev;
uclass_next_device(&dev)) {
ret = regulator_autoset(dev);
- if (ret == -EMEDIUMTYPE) {
+ if (ret == -EMEDIUMTYPE || ret == -EALREADY) {
ret = 0;
continue;
}
diff --git a/drivers/power/regulator/rk8xx.c b/drivers/power/regulator/rk8xx.c
index bf3af78..34e6151 100644
--- a/drivers/power/regulator/rk8xx.c
+++ b/drivers/power/regulator/rk8xx.c
@@ -519,7 +519,7 @@
if (ret < 0)
return ret;
- return ret & mask ? true : false;
+ return (ret & mask) ? true : false;
}
static int _buck_set_suspend_enable(struct udevice *pmic, int buck, bool enable)
@@ -584,7 +584,7 @@
val = pmic_reg_read(pmic, RK816_REG_DCDC_SLP_EN);
if (val < 0)
return val;
- ret = val & mask ? 1 : 0;
+ ret = (val & mask) ? 1 : 0;
break;
case RK806_ID:
{
@@ -607,7 +607,7 @@
val = pmic_reg_read(pmic, REG_SLEEP_SET_OFF1);
if (val < 0)
return val;
- ret = val & mask ? 0 : 1;
+ ret = (val & mask) ? 0 : 1;
break;
case RK809_ID:
case RK817_ID:
@@ -619,7 +619,7 @@
val = pmic_reg_read(pmic, RK817_POWER_SLP_EN(0));
if (val < 0)
return val;
- ret = val & mask ? 1 : 0;
+ ret = (val & mask) ? 1 : 0;
break;
default:
ret = -EINVAL;
@@ -722,7 +722,7 @@
if (ret < 0)
return ret;
- return ret & mask ? true : false;
+ return (ret & mask) ? true : false;
}
static int _nldo_get_enable(struct udevice *pmic, int nldo)
@@ -979,7 +979,7 @@
val = pmic_reg_read(pmic, RK816_REG_LDO_SLP_EN);
if (val < 0)
return val;
- ret = val & mask ? 1 : 0;
+ ret = (val & mask) ? 1 : 0;
break;
case RK808_ID:
case RK818_ID:
@@ -987,7 +987,7 @@
val = pmic_reg_read(pmic, REG_SLEEP_SET_OFF2);
if (val < 0)
return val;
- ret = val & mask ? 0 : 1;
+ ret = (val & mask) ? 0 : 1;
break;
case RK809_ID:
case RK817_ID:
@@ -996,13 +996,13 @@
val = pmic_reg_read(pmic, RK817_POWER_SLP_EN(0));
if (val < 0)
return val;
- ret = val & mask ? 1 : 0;
+ ret = (val & mask) ? 1 : 0;
} else {
mask = 1 << ldo;
val = pmic_reg_read(pmic, RK817_POWER_SLP_EN(1));
if (val < 0)
return val;
- ret = val & mask ? 1 : 0;
+ ret = (val & mask) ? 1 : 0;
}
break;
}
@@ -1133,14 +1133,14 @@
return _buck_get_enable(dev->parent, buck);
}
-static int _ldo_get_value(struct udevice *dev, const struct rk8xx_reg_info *info)
+static int _ldo_get_value(struct udevice *pmic, const struct rk8xx_reg_info *info)
{
int mask = info->vsel_mask;
int ret, val;
if (info->vsel_reg == NA)
return -ENOSYS;
- ret = pmic_reg_read(dev->parent, info->vsel_reg);
+ ret = pmic_reg_read(pmic, info->vsel_reg);
if (ret < 0)
return ret;
val = ret & mask;
@@ -1153,7 +1153,7 @@
int ldo = dev->driver_data - 1;
const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, 0);
- return _ldo_get_value(dev, info);
+ return _ldo_get_value(dev->parent, info);
}
static int nldo_get_value(struct udevice *dev)
@@ -1161,7 +1161,7 @@
int nldo = dev->driver_data - 1;
const struct rk8xx_reg_info *info = get_nldo_reg(dev->parent, nldo, 0);
- return _ldo_get_value(dev, info);
+ return _ldo_get_value(dev->parent, info);
}
static int pldo_get_value(struct udevice *dev)
@@ -1169,10 +1169,10 @@
int pldo = dev->driver_data - 1;
const struct rk8xx_reg_info *info = get_pldo_reg(dev->parent, pldo, 0);
- return _ldo_get_value(dev, info);
+ return _ldo_get_value(dev->parent, info);
}
-static int _ldo_set_value(struct udevice *dev, const struct rk8xx_reg_info *info, int uvolt)
+static int _ldo_set_value(struct udevice *pmic, const struct rk8xx_reg_info *info, int uvolt)
{
int mask = info->vsel_mask;
int val;
@@ -1188,7 +1188,7 @@
debug("%s: volt=%d, reg=0x%x, mask=0x%x, val=0x%x\n",
__func__, uvolt, info->vsel_reg, mask, val);
- return pmic_clrsetbits(dev->parent, info->vsel_reg, mask, val);
+ return pmic_clrsetbits(pmic, info->vsel_reg, mask, val);
}
static int ldo_set_value(struct udevice *dev, int uvolt)
@@ -1196,7 +1196,7 @@
int ldo = dev->driver_data - 1;
const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, uvolt);
- return _ldo_set_value(dev, info, uvolt);
+ return _ldo_set_value(dev->parent, info, uvolt);
}
static int nldo_set_value(struct udevice *dev, int uvolt)
@@ -1204,7 +1204,7 @@
int nldo = dev->driver_data - 1;
const struct rk8xx_reg_info *info = get_nldo_reg(dev->parent, nldo, uvolt);
- return _ldo_set_value(dev, info, uvolt);
+ return _ldo_set_value(dev->parent, info, uvolt);
}
static int pldo_set_value(struct udevice *dev, int uvolt)
@@ -1212,10 +1212,10 @@
int pldo = dev->driver_data - 1;
const struct rk8xx_reg_info *info = get_pldo_reg(dev->parent, pldo, uvolt);
- return _ldo_set_value(dev, info, uvolt);
+ return _ldo_set_value(dev->parent, info, uvolt);
}
-static int _ldo_set_suspend_value(struct udevice *dev, const struct rk8xx_reg_info *info, int uvolt)
+static int _ldo_set_suspend_value(struct udevice *pmic, const struct rk8xx_reg_info *info, int uvolt)
{
int mask = info->vsel_mask;
int val;
@@ -1231,7 +1231,7 @@
debug("%s: volt=%d, reg=0x%x, mask=0x%x, val=0x%x\n",
__func__, uvolt, info->vsel_sleep_reg, mask, val);
- return pmic_clrsetbits(dev->parent, info->vsel_sleep_reg, mask, val);
+ return pmic_clrsetbits(pmic, info->vsel_sleep_reg, mask, val);
}
static int ldo_set_suspend_value(struct udevice *dev, int uvolt)
@@ -1258,7 +1258,7 @@
return _ldo_set_suspend_value(dev->parent, info, uvolt);
}
-static int _ldo_get_suspend_value(struct udevice *dev, const struct rk8xx_reg_info *info)
+static int _ldo_get_suspend_value(struct udevice *pmic, const struct rk8xx_reg_info *info)
{
int mask = info->vsel_mask;
int val, ret;
@@ -1266,7 +1266,7 @@
if (info->vsel_sleep_reg == NA)
return -ENOSYS;
- ret = pmic_reg_read(dev->parent, info->vsel_sleep_reg);
+ ret = pmic_reg_read(pmic, info->vsel_sleep_reg);
if (ret < 0)
return ret;
@@ -1437,7 +1437,7 @@
if (ret < 0)
return ret;
- return ret & mask ? true : false;
+ return (ret & mask) ? true : false;
}
static int switch_set_suspend_value(struct udevice *dev, int uvolt)
@@ -1492,21 +1492,21 @@
val = pmic_reg_read(dev->parent, REG_SLEEP_SET_OFF1);
if (val < 0)
return val;
- ret = val & mask ? 0 : 1;
+ ret = (val & mask) ? 0 : 1;
break;
case RK809_ID:
mask = 1 << (sw + 6);
val = pmic_reg_read(dev->parent, RK817_POWER_SLP_EN(0));
if (val < 0)
return val;
- ret = val & mask ? 1 : 0;
+ ret = (val & mask) ? 1 : 0;
break;
case RK818_ID:
mask = 1 << 6;
val = pmic_reg_read(dev->parent, REG_SLEEP_SET_OFF1);
if (val < 0)
return val;
- ret = val & mask ? 0 : 1;
+ ret = (val & mask) ? 0 : 1;
break;
}
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index 9838a27..a64d2df 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -65,7 +65,7 @@
default K3_J721E_DDRSS if SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_J784S4
default K3_AM64_DDRSS if SOC_K3_AM642
default K3_AM64_DDRSS if SOC_K3_AM625
- default K3_AM62A_DDRSS if SOC_K3_AM62A7 || SOC_K3_AM62P5
+ default K3_AM62A_DDRSS if SOC_K3_AM62A7 || SOC_K3_AM62P5 || SOC_K3_J722S
config K3_J721E_DDRSS
bool "Enable J721E DDRSS support"
diff --git a/drivers/remoteproc/ti_k3_dsp_rproc.c b/drivers/remoteproc/ti_k3_dsp_rproc.c
index 076b6f2..e90f75a 100644
--- a/drivers/remoteproc/ti_k3_dsp_rproc.c
+++ b/drivers/remoteproc/ti_k3_dsp_rproc.c
@@ -21,6 +21,7 @@
#include <linux/sizes.h>
#include <linux/soc/ti/ti_sci_protocol.h>
#include "ti_sci_proc.h"
+#include <mach/security.h>
#define KEYSTONE_RPROC_LOCAL_ADDRESS_MASK (SZ_16M - 1)
@@ -127,6 +128,7 @@
struct k3_dsp_privdata *dsp = dev_get_priv(dev);
struct k3_dsp_boot_data *data = dsp->data;
u32 boot_vector;
+ void *image_addr = (void *)addr;
int ret;
if (dsp->in_use) {
@@ -148,6 +150,8 @@
goto proc_release;
}
+ ti_secure_image_post_process(&image_addr, &size);
+
ret = rproc_elf_load_image(dev, addr, size);
if (ret < 0) {
dev_err(dev, "Loading elf failed %d\n", ret);
diff --git a/drivers/remoteproc/ti_k3_r5f_rproc.c b/drivers/remoteproc/ti_k3_r5f_rproc.c
index 74bf043..ef2c187 100644
--- a/drivers/remoteproc/ti_k3_r5f_rproc.c
+++ b/drivers/remoteproc/ti_k3_r5f_rproc.c
@@ -20,6 +20,7 @@
#include <linux/kernel.h>
#include <linux/soc/ti/ti_sci_protocol.h>
#include "ti_sci_proc.h"
+#include <mach/security.h>
/*
* R5F's view of this address can either be for ATCM or BTCM with the other
@@ -306,6 +307,7 @@
u64 boot_vector;
u32 ctrl, sts, cfg = 0;
bool mem_auto_init;
+ void *image_addr = (void *)addr;
int ret;
dev_dbg(dev, "%s addr = 0x%lx, size = 0x%lx\n", __func__, addr, size);
@@ -333,6 +335,8 @@
k3_r5f_init_tcm_memories(core, mem_auto_init);
+ ti_secure_image_post_process(&image_addr, &size);
+
ret = rproc_elf_load_image(dev, addr, size);
if (ret < 0) {
dev_err(dev, "Loading elf failedi %d\n", ret);
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 1fe4607..3a1e5a6 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -501,6 +501,15 @@
driver will be available until the real driver model serial is
running.
+config DEBUG_UART_XTENSA_SEMIHOSTING
+ bool "Xtensa semihosting"
+ depends on XTENSA_SEMIHOSTING_SERIAL
+ help
+ Select this to enable the debug UART using the Xtensa semihosting driver.
+ This provides basic serial output from the console without needing to
+ start up driver model. The driver will be available until the real
+ driver model serial is running.
+
endchoice
config DEBUG_UART_BASE
@@ -936,7 +945,6 @@
config SEMIHOSTING_SERIAL
bool "Semihosting UART support"
depends on SEMIHOSTING && !SERIAL_RX_BUFFER
- imply SERIAL_PUTS
help
Select this to enable a serial UART using semihosting. Special halt
instructions will be issued which an external debugger (such as a
@@ -1115,6 +1123,14 @@
If built without DM support, then requires Xen
to be built with CONFIG_VERBOSE_DEBUG.
+config XTENSA_SEMIHOSTING_SERIAL
+ bool "Xtensa Semihosting UART support"
+ depends on DM_SERIAL
+ depends on XTENSA_SEMIHOSTING
+ imply SERIAL_PUTS
+ help
+ Select this to enable a serial UART using Xtensa semihosting.
+
choice
prompt "Console port"
default 8xx_CONS_SMC1
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index dbe598b..78810f9 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -60,6 +60,7 @@
obj-$(CONFIG_HTIF_CONSOLE) += serial_htif.o
obj-$(CONFIG_SIFIVE_SERIAL) += serial_sifive.o
obj-$(CONFIG_XEN_SERIAL) += serial_xen.o
+obj-$(CONFIG_XTENSA_SEMIHOSTING_SERIAL) += serial_xtensa_semihosting.o
obj-$(CONFIG_S5P4418_PL011_SERIAL) += serial_s5p4418_pl011.o
ifndef CONFIG_SPL_BUILD
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 4963385..42b6971 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -291,9 +291,9 @@
serial_out(c, &com_port->thr);
/*
- * Call watchdog_reset() upon newline. This is done here in putc
+ * Call schedule() upon newline. This is done here in putc
* since the environment code uses a single puts() to print the complete
- * environment upon "printenv". So we can't put this watchdog call
+ * environment upon "printenv". So we can't put this schedule call
* in puts().
*/
if (c == '\n')
@@ -390,9 +390,9 @@
serial_out(ch, &com_port->thr);
/*
- * Call watchdog_reset() upon newline. This is done here in putc
+ * Call schedule() upon newline. This is done here in putc
* since the environment code uses a single puts() to print the complete
- * environment upon "printenv". So we can't put this watchdog call
+ * environment upon "printenv". So we can't put this schedule call
* in puts().
*/
if (ch == '\n')
diff --git a/drivers/serial/serial_mtk.c b/drivers/serial/serial_mtk.c
index 3f569c6..becf931 100644
--- a/drivers/serial/serial_mtk.c
+++ b/drivers/serial/serial_mtk.c
@@ -10,6 +10,7 @@
#include <config.h>
#include <div64.h>
#include <dm.h>
+#include <dm/device.h>
#include <dm/device_compat.h>
#include <errno.h>
#include <log.h>
@@ -76,15 +77,19 @@
* driver
* @regs: Register base of the serial port
* @clk: The baud clock device
+ * @clk_bus: The bus clock device
* @fixed_clk_rate: Fallback fixed baud clock rate if baud clock
* device is not specified
* @force_highspeed: Force using high-speed mode
+ * @upstream_highspeed_logic: Apply upstream high-speed logic
*/
struct mtk_serial_priv {
struct mtk_serial_regs __iomem *regs;
struct clk clk;
+ struct clk clk_bus;
u32 fixed_clk_rate;
bool force_highspeed;
+ bool upstream_highspeed_logic;
};
static void _mtk_serial_setbrg(struct mtk_serial_priv *priv, int baud,
@@ -111,7 +116,12 @@
goto set_baud;
}
- if (priv->force_highspeed)
+ /*
+ * Upstream linux use highspeed for anything >= 115200 and lowspeed
+ * for < 115200. Simulate this if we are using the upstream compatible.
+ */
+ if (priv->force_highspeed ||
+ (priv->upstream_highspeed_logic && baud >= 115200))
goto use_hs3;
if (baud <= 115200) {
@@ -220,6 +230,10 @@
writel(UART_MCRVAL, &priv->regs->mcr);
writel(UART_FCRVAL, &priv->regs->fcr);
+ clk_enable(&priv->clk);
+ if (priv->clk_bus.dev)
+ clk_enable(&priv->clk_bus);
+
return 0;
}
@@ -250,7 +264,11 @@
}
}
+ clk_get_by_name(dev, "bus", &priv->clk_bus);
+
priv->force_highspeed = dev_read_bool(dev, "mediatek,force-highspeed");
+ priv->upstream_highspeed_logic =
+ device_is_compatible(dev, "mediatek,mt6577-uart");
return 0;
}
diff --git a/drivers/serial/serial_xtensa_semihosting.c b/drivers/serial/serial_xtensa_semihosting.c
new file mode 100644
index 0000000..0e59a9b
--- /dev/null
+++ b/drivers/serial/serial_xtensa_semihosting.c
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Jiaxun Yang <jiaxun.yang@flygoat.com>
+ */
+
+#include <dm.h>
+#include <malloc.h>
+#include <serial.h>
+
+#include <asm/platform/simcall.h>
+
+/**
+ * struct simc_serial_priv - Semihosting serial private data
+ * @counter: Counter used to fake pending every other call
+ */
+struct simc_serial_priv {
+ unsigned int counter;
+};
+
+static int simc_serial_getc(struct udevice *dev)
+{
+ char ch = 0;
+
+ simc_read(0, &ch, sizeof(ch));
+
+ return ch;
+}
+
+static int simc_serial_putc(struct udevice *dev, const char ch)
+{
+ char str[2] = {0};
+
+ str[0] = ch;
+ simc_write(1, str, 1);
+
+ return 0;
+}
+
+static int simc_serial_pending(struct udevice *dev, bool input)
+{
+ struct simc_serial_priv *priv = dev_get_priv(dev);
+
+ if (input) {
+ int res = simc_poll(0);
+ return res < 0 ? priv->counter++ & 1 : res;
+ }
+
+ return false;
+}
+
+static ssize_t smh_serial_puts(struct udevice *dev, const char *s, size_t len)
+{
+ int ret;
+
+ ret = simc_write(1, s, len);
+
+ return ret;
+}
+
+static const struct dm_serial_ops simc_serial_ops = {
+ .putc = simc_serial_putc,
+ .puts = smh_serial_puts,
+ .getc = simc_serial_getc,
+ .pending = simc_serial_pending,
+};
+
+U_BOOT_DRIVER(simc_serial) = {
+ .name = "serial_xtensa_semihosting",
+ .id = UCLASS_SERIAL,
+ .priv_auto = sizeof(struct simc_serial_priv),
+ .ops = &simc_serial_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRVINFO(simc_serial) = {
+ .name = "serial_xtensa_semihosting",
+};
+
+#if CONFIG_IS_ENABLED(DEBUG_UART_XTENSA_SEMIHOSTING)
+#include <debug_uart.h>
+
+static inline void _debug_uart_init(void)
+{
+}
+
+static inline void _debug_uart_putc(int c)
+{
+ simc_serial_putc(NULL, c);
+}
+
+DEBUG_UART_FUNCS
+#endif
diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index 03433bc0..cee506f 100644
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -9,6 +9,14 @@
need different parameters or quirks enabled depending on the
specific device variant in use.
+config SOC_AMD_VERSAL2
+ bool "Enable SoC Device ID driver for AMD Versal Gen 2"
+ depends on SOC_DEVICE && ARCH_VERSAL2
+ help
+ Enable this option to select SoC device id driver for AMD Versal Gen 2.
+ This allows other drivers to verify the SoC familiy & revision using
+ matching SoC attributes.
+
config SOC_DEVICE_TI_K3
depends on SOC_DEVICE && ARCH_K3
bool "Enable SoC Device ID driver for TI K3 SoCs"
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 610bf81..5ec89a0 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -2,6 +2,7 @@
#
# Makefile for the U-Boot SOC specific device drivers.
+obj-$(CONFIG_SOC_AMD_VERSAL2) += soc_amd_versal2.o
obj-$(CONFIG_SOC_SAMSUNG) += samsung/
obj-$(CONFIG_SOC_TI) += ti/
obj-$(CONFIG_SOC_DEVICE) += soc-uclass.o
diff --git a/drivers/soc/soc_amd_versal2.c b/drivers/soc/soc_amd_versal2.c
new file mode 100644
index 0000000..66bcb22
--- /dev/null
+++ b/drivers/soc/soc_amd_versal2.c
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * AMD Versal Gen 2 SOC driver
+ *
+ * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc.
+ */
+
+#include <dm.h>
+#include <soc.h>
+#include <zynqmp_firmware.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+#include <linux/bitfield.h>
+
+/*
+ * v1 -> 0x10 - ES1
+ * v2 -> 0x20 - Production
+ */
+static const char versal2_family[] = "Versal Gen 2";
+
+struct soc_amd_versal2_priv {
+ const char *family;
+ char revision;
+};
+
+static int soc_amd_versal2_get_family(struct udevice *dev, char *buf, int size)
+{
+ struct soc_amd_versal2_priv *priv = dev_get_priv(dev);
+
+ return snprintf(buf, size, "%s", priv->family);
+}
+
+static int soc_amd_versal2_get_revision(struct udevice *dev, char *buf, int size)
+{
+ struct soc_amd_versal2_priv *priv = dev_get_priv(dev);
+
+ return snprintf(buf, size, "v%d", priv->revision);
+}
+
+static const struct soc_ops soc_amd_versal2_ops = {
+ .get_family = soc_amd_versal2_get_family,
+ .get_revision = soc_amd_versal2_get_revision,
+};
+
+static int soc_amd_versal2_probe(struct udevice *dev)
+{
+ struct soc_amd_versal2_priv *priv = dev_get_priv(dev);
+ u32 ret_payload[PAYLOAD_ARG_CNT];
+ int ret;
+
+ priv->family = versal2_family;
+
+ if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE)) {
+ ret = xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0,
+ ret_payload);
+ if (ret)
+ return ret;
+ } else {
+ ret_payload[2] = readl(PMC_TAP_VERSION);
+ if (!ret_payload[2])
+ return -EINVAL;
+ }
+
+ priv->revision = FIELD_GET(PS_VERSION_MASK, ret_payload[2]);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(soc_amd_versal2) = {
+ .name = "soc_amd_versal2",
+ .id = UCLASS_SOC,
+ .ops = &soc_amd_versal2_ops,
+ .probe = soc_amd_versal2_probe,
+ .priv_auto = sizeof(struct soc_amd_versal2_priv),
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c
index b585e47..f948914 100644
--- a/drivers/soc/soc_ti_k3.c
+++ b/drivers/soc/soc_ti_k3.c
@@ -23,33 +23,36 @@
soc = (idreg & JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT;
switch (soc) {
+ case JTAG_ID_PARTNO_AM62X:
+ family = "AM62X";
+ break;
+ case JTAG_ID_PARTNO_AM62AX:
+ family = "AM62AX";
+ break;
+ case JTAG_ID_PARTNO_AM62PX:
+ family = "AM62PX";
+ break;
+ case JTAG_ID_PARTNO_AM64X:
+ family = "AM64X";
+ break;
case JTAG_ID_PARTNO_AM65X:
family = "AM65X";
break;
- case JTAG_ID_PARTNO_J721E:
- family = "J721E";
- break;
case JTAG_ID_PARTNO_J7200:
family = "J7200";
break;
- case JTAG_ID_PARTNO_AM64X:
- family = "AM64X";
+ case JTAG_ID_PARTNO_J721E:
+ family = "J721E";
break;
case JTAG_ID_PARTNO_J721S2:
family = "J721S2";
break;
- case JTAG_ID_PARTNO_AM62X:
- family = "AM62X";
- break;
- case JTAG_ID_PARTNO_AM62AX:
- family = "AM62AX";
+ case JTAG_ID_PARTNO_J722S:
+ family = "J722S";
break;
case JTAG_ID_PARTNO_J784S4:
family = "J784S4";
break;
- case JTAG_ID_PARTNO_AM62PX:
- family = "AM62PX";
- break;
default:
family = "Unknown Silicon";
};
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 35030ab..cd785ae 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -156,7 +156,7 @@
config CADENCE_OSPI_VERSAL
bool "Configure Versal OSPI"
- depends on (ARCH_VERSAL || ARCH_VERSAL_NET) && CADENCE_QSPI
+ depends on (ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2) && CADENCE_QSPI
imply DM_GPIO
help
This option is used to enable Versal OSPI DMA operations which
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 75e5223..9c466f8 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -253,7 +253,8 @@
/* Versal and Versal-NET use spi calibration to set read delay */
if (CONFIG_IS_ENABLED(ARCH_VERSAL) ||
- CONFIG_IS_ENABLED(ARCH_VERSAL_NET))
+ CONFIG_IS_ENABLED(ARCH_VERSAL_NET) ||
+ CONFIG_IS_ENABLED(ARCH_VERSAL2))
if (priv->read_delay >= 0)
priv->read_delay = -1;
diff --git a/drivers/spi/mtk_spim.c b/drivers/spi/mtk_spim.c
index 90f4c3c..b360eca 100644
--- a/drivers/spi/mtk_spim.c
+++ b/drivers/spi/mtk_spim.c
@@ -137,6 +137,8 @@
* @state: Controller state
* @sel_clk: Pad clock
* @spi_clk: Core clock
+ * @parent_clk: Parent clock (needed for mediatek,spi-ipm, upstream DTSI)
+ * @hclk: HCLK clock (needed for mediatek,spi-ipm, upstream DTSI)
* @pll_clk_rate: Controller's PLL source clock rate, which is different
* from SPI bus clock rate
* @xfer_len: Current length of data for transfer
@@ -151,6 +153,7 @@
void __iomem *base;
u32 state;
struct clk sel_clk, spi_clk;
+ struct clk parent_clk, hclk;
u32 pll_clk_rate;
u32 xfer_len;
struct mtk_spim_capability hw_cap;
@@ -650,7 +653,21 @@
if (!priv->base)
return -EINVAL;
- mtk_spim_get_attr(priv, dev);
+ /*
+ * Upstream linux driver for ipm design enable all the modes
+ * and setup the calibrarion values directly in the driver with
+ * standard values.
+ */
+ if (device_is_compatible(dev, "mediatek,spi-ipm")) {
+ priv->hw_cap.enhance_timing = true;
+ priv->hw_cap.dma_ext = true;
+ priv->hw_cap.ipm_design = true;
+ priv->hw_cap.support_quad = true;
+ priv->sample_sel = 0;
+ priv->tick_dly = 2;
+ } else {
+ mtk_spim_get_attr(priv, dev);
+ }
ret = clk_get_by_name(dev, "sel-clk", &priv->sel_clk);
if (ret < 0) {
@@ -664,8 +681,31 @@
return ret;
}
- clk_enable(&priv->sel_clk);
+ /*
+ * Upstream DTSI use a different compatible that provide additional
+ * clock instead of the assigned-clock implementation.
+ */
+ if (device_is_compatible(dev, "mediatek,spi-ipm")) {
+ ret = clk_get_by_name(dev, "parent-clk", &priv->parent_clk);
+ if (ret < 0) {
+ dev_err(dev, "failed to get parent-clk\n");
+ return ret;
+ }
+
+ ret = clk_get_by_name(dev, "hclk", &priv->hclk);
+ if (ret < 0) {
+ dev_err(dev, "failed to get hclk\n");
+ return ret;
+ }
+
+ clk_enable(&priv->parent_clk);
+ clk_set_parent(&priv->sel_clk, &priv->parent_clk);
+
+ clk_enable(&priv->hclk);
+ }
+
clk_enable(&priv->spi_clk);
+ clk_enable(&priv->sel_clk);
priv->pll_clk_rate = clk_get_rate(&priv->spi_clk);
if (priv->pll_clk_rate == 0)
@@ -698,6 +738,7 @@
static const struct udevice_id mtk_spim_ids[] = {
{ .compatible = "mediatek,ipm-spi" },
+ { .compatible = "mediatek,spi-ipm", },
{}
};
diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index 61349a4..ae795e5 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -106,7 +106,8 @@
#define TAP_DLY_BYPASS_LQSPI_RX_SHIFT 2
#define GQSPI_DATA_DLY_ADJ_OFST 0x000001F8
#define IOU_TAPDLY_BYPASS_OFST !(IS_ENABLED(CONFIG_ARCH_VERSAL) || \
- IS_ENABLED(CONFIG_ARCH_VERSAL_NET)) ? \
+ IS_ENABLED(CONFIG_ARCH_VERSAL_NET) || \
+ IS_ENABLED(CONFIG_ARCH_VERSAL2)) ? \
0xFF180390 : 0xF103003C
#define GQSPI_LPBK_DLY_ADJ_LPBK_MASK 0x00000020
#define GQSPI_FREQ_37_5MHZ 37500000
@@ -316,7 +317,8 @@
__func__, clk_rate, baudrateval, reqhz);
if (!(IS_ENABLED(CONFIG_ARCH_VERSAL) ||
- IS_ENABLED(CONFIG_ARCH_VERSAL_NET))) {
+ IS_ENABLED(CONFIG_ARCH_VERSAL_NET) ||
+ IS_ENABLED(CONFIG_ARCH_VERSAL2))) {
if (reqhz <= GQSPI_FREQ_40MHZ) {
tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
TAP_DLY_BYPASS_LQSPI_RX_SHIFT;
diff --git a/drivers/spmi/spmi-msm.c b/drivers/spmi/spmi-msm.c
index b0d6226..5cc5a9e 100644
--- a/drivers/spmi/spmi-msm.c
+++ b/drivers/spmi/spmi-msm.c
@@ -119,7 +119,7 @@
channel = priv->channel_map[usid][pid] & SPMI_CHANNEL_MASK;
- dev_dbg(dev, "[%d:%d] %s: channel %d\n", usid, pid, __func__, channel);
+ debug("%s: [%d:%d] %s: channel %d\n", dev->name, usid, pid, __func__, channel);
switch (priv->arb_ver) {
case V1:
@@ -186,7 +186,7 @@
channel = priv->channel_map[usid][pid] & SPMI_CHANNEL_MASK;
- dev_dbg(dev, "[%d:%d] %s: channel %d\n", usid, pid, __func__, channel);
+ debug("%s: [%d:%d] %s: channel %d\n", dev->name, usid, pid, __func__, channel);
switch (priv->arb_ver) {
case V1:
@@ -271,7 +271,7 @@
} else if (hw_ver < PMIC_ARB_VERSION_V7_MIN) {
priv->arb_ver = V5;
priv->arb_chnl = core_addr + APID_MAP_OFFSET_V5;
- priv->max_channels = SPMI_MAX_CHANNELS;
+ priv->max_channels = SPMI_MAX_CHANNELS_V5;
priv->spmi_cnfg = dev_read_addr_name(dev, "cnfg");
} else {
/* TOFIX: handle second bus */
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index b64bfad..121194e 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -240,6 +240,12 @@
help
Add support for the system reboot via the Renesas RAA215300 PMIC.
+config SYSRESET_QCOM_PSHOLD
+ bool "Support sysreset for Qualcomm SoCs via PSHOLD"
+ depends on ARCH_IPQ40XX
+ help
+ Add support for the system reboot on Qualcomm SoCs via PSHOLD.
+
endif
endmenu
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index d59299a..a6a0584 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -29,4 +29,5 @@
obj-$(CONFIG_$(SPL_TPL_)SYSRESET_AT91) += sysreset_at91.o
obj-$(CONFIG_$(SPL_TPL_)SYSRESET_X86) += sysreset_x86.o
obj-$(CONFIG_SYSRESET_RAA215300) += sysreset_raa215300.o
+obj-$(CONFIG_SYSRESET_QCOM_PSHOLD) += sysreset_qcom-pshold.o
obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o
diff --git a/drivers/sysreset/sysreset_qcom-pshold.c b/drivers/sysreset/sysreset_qcom-pshold.c
new file mode 100644
index 0000000..4529047
--- /dev/null
+++ b/drivers/sysreset/sysreset_qcom-pshold.c
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm PSHOLD reset driver
+ *
+ * Copyright (c) 2024 Sartura Ltd.
+ *
+ * Author: Robert Marko <robert.marko@sartura.hr>
+ * Based on the Linux msm-poweroff driver.
+ *
+ */
+
+#include <dm.h>
+#include <sysreset.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+
+struct qcom_pshold_priv {
+ phys_addr_t base;
+};
+
+static int qcom_pshold_request(struct udevice *dev, enum sysreset_t type)
+{
+ struct qcom_pshold_priv *priv = dev_get_priv(dev);
+
+ writel(0, priv->base);
+ mdelay(10000);
+
+ return 0;
+}
+
+static struct sysreset_ops qcom_pshold_ops = {
+ .request = qcom_pshold_request,
+};
+
+static int qcom_pshold_probe(struct udevice *dev)
+{
+ struct qcom_pshold_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_read_addr(dev);
+ return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
+}
+
+static const struct udevice_id qcom_pshold_ids[] = {
+ { .compatible = "qcom,pshold", },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(qcom_pshold) = {
+ .name = "qcom_pshold",
+ .id = UCLASS_SYSRESET,
+ .of_match = qcom_pshold_ids,
+ .probe = qcom_pshold_probe,
+ .priv_auto = sizeof(struct qcom_pshold_priv),
+ .ops = &qcom_pshold_ops,
+};
diff --git a/drivers/tpm/tpm2_tis_spi.c b/drivers/tpm/tpm2_tis_spi.c
index 28079b5..b0fe97a 100644
--- a/drivers/tpm/tpm2_tis_spi.c
+++ b/drivers/tpm/tpm2_tis_spi.c
@@ -237,19 +237,22 @@
/* legacy reset */
ret = gpio_request_by_name(dev, "gpio-reset", 0,
&reset_gpio, GPIOD_IS_OUT);
- if (ret) {
+ if (!ret) {
log(LOGC_NONE, LOGL_NOTICE,
- "%s: missing reset GPIO\n", __func__);
- goto init;
+ "%s: gpio-reset is deprecated\n", __func__);
}
- log(LOGC_NONE, LOGL_NOTICE,
- "%s: gpio-reset is deprecated\n", __func__);
}
- dm_gpio_set_value(&reset_gpio, 1);
- mdelay(1);
- dm_gpio_set_value(&reset_gpio, 0);
+
+ if (!ret) {
+ log(LOGC_NONE, LOGL_WARNING,
+ "%s: TPM gpio reset should not be used on secure production devices\n",
+ dev->name);
+ dm_gpio_set_value(&reset_gpio, 1);
+ mdelay(1);
+ dm_gpio_set_value(&reset_gpio, 0);
+ }
}
-init:
+
/* Ensure a minimum amount of time elapsed since reset of the TPM */
mdelay(drv_data->time_before_first_cmd_ms);
diff --git a/drivers/usb/cdns3/core.c b/drivers/usb/cdns3/core.c
index b4e9316..cbe06a9 100644
--- a/drivers/usb/cdns3/core.c
+++ b/drivers/usb/cdns3/core.c
@@ -20,6 +20,7 @@
#include <linux/bug.h>
#include <linux/kernel.h>
#include <linux/io.h>
+#include <linux/usb/gadget.h>
#include <usb.h>
#include <usb/xhci.h>
@@ -462,15 +463,38 @@
return cdns3_remove(cdns);
}
+static int cdns3_gadget_handle_interrupts(struct udevice *dev)
+{
+ struct cdns3 *cdns = dev_get_priv(dev);
+
+ cdns3_gadget_uboot_handle_interrupt(cdns);
+
+ return 0;
+}
+
+static const struct usb_gadget_generic_ops cdns3_gadget_ops = {
+ .handle_interrupts = cdns3_gadget_handle_interrupts,
+};
+
U_BOOT_DRIVER(cdns_usb3_peripheral) = {
.name = "cdns-usb3-peripheral",
.id = UCLASS_USB_GADGET_GENERIC,
.of_match = cdns3_ids,
+ .ops = &cdns3_gadget_ops,
.probe = cdns3_gadget_probe,
.remove = cdns3_gadget_remove,
.priv_auto = sizeof(struct cdns3_gadget_priv),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
+#else
+int dm_usb_gadget_handle_interrupts(struct udevice *dev)
+{
+ struct cdns3 *cdns = dev_get_priv(dev);
+
+ cdns3_gadget_uboot_handle_interrupt(cdns);
+
+ return 0;
+}
#endif
#if defined(CONFIG_SPL_USB_HOST) || \
diff --git a/drivers/usb/cdns3/gadget-export.h b/drivers/usb/cdns3/gadget-export.h
index 577469e..b3fd7c5 100644
--- a/drivers/usb/cdns3/gadget-export.h
+++ b/drivers/usb/cdns3/gadget-export.h
@@ -25,4 +25,6 @@
#endif
+void cdns3_gadget_uboot_handle_interrupt(struct cdns3 *cdns);
+
#endif /* __LINUX_CDNS3_GADGET_EXPORT */
diff --git a/drivers/usb/cdns3/gadget.c b/drivers/usb/cdns3/gadget.c
index d11175d..32b2c41 100644
--- a/drivers/usb/cdns3/gadget.c
+++ b/drivers/usb/cdns3/gadget.c
@@ -2755,19 +2755,10 @@
*
* Handles ep0 and gadget interrupt
*/
-static void cdns3_gadget_uboot_handle_interrupt(struct cdns3 *cdns)
+void cdns3_gadget_uboot_handle_interrupt(struct cdns3 *cdns)
{
int ret = cdns3_device_irq_handler(0, cdns);
if (ret == IRQ_WAKE_THREAD)
cdns3_device_thread_irq_handler(0, cdns);
}
-
-int dm_usb_gadget_handle_interrupts(struct udevice *dev)
-{
- struct cdns3 *cdns = dev_get_priv(dev);
-
- cdns3_gadget_uboot_handle_interrupt(cdns);
-
- return 0;
-}
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 8db678e..731ede2 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -194,34 +194,39 @@
}
#if CONFIG_IS_ENABLED(DM_USB_GADGET)
-int dm_usb_gadget_handle_interrupts(struct udevice *dev)
+static int dwc3_generic_peripheral_probe(struct udevice *dev)
{
struct dwc3_generic_priv *priv = dev_get_priv(dev);
- struct dwc3 *dwc3 = &priv->dwc3;
- dwc3_gadget_uboot_handle_interrupt(dwc3);
-
- return 0;
+ return dwc3_generic_probe(dev, priv);
}
-static int dwc3_generic_peripheral_probe(struct udevice *dev)
+static int dwc3_generic_peripheral_remove(struct udevice *dev)
{
struct dwc3_generic_priv *priv = dev_get_priv(dev);
- return dwc3_generic_probe(dev, priv);
+ return dwc3_generic_remove(dev, priv);
}
-static int dwc3_generic_peripheral_remove(struct udevice *dev)
+static int dwc3_gadget_handle_interrupts(struct udevice *dev)
{
struct dwc3_generic_priv *priv = dev_get_priv(dev);
+ struct dwc3 *dwc3 = &priv->dwc3;
- return dwc3_generic_remove(dev, priv);
+ dwc3_gadget_uboot_handle_interrupt(dwc3);
+
+ return 0;
}
+static const struct usb_gadget_generic_ops dwc3_gadget_ops = {
+ .handle_interrupts = dwc3_gadget_handle_interrupts,
+};
+
U_BOOT_DRIVER(dwc3_generic_peripheral) = {
.name = "dwc3-generic-peripheral",
.id = UCLASS_USB_GADGET_GENERIC,
.of_to_plat = dwc3_generic_of_to_plat,
+ .ops = &dwc3_gadget_ops,
.probe = dwc3_generic_peripheral_probe,
.remove = dwc3_generic_peripheral_remove,
.priv_auto = sizeof(struct dwc3_generic_priv),
diff --git a/drivers/usb/dwc3/dwc3-layerscape.c b/drivers/usb/dwc3/dwc3-layerscape.c
index ff83bf7..108b44c 100644
--- a/drivers/usb/dwc3/dwc3-layerscape.c
+++ b/drivers/usb/dwc3/dwc3-layerscape.c
@@ -99,33 +99,38 @@
}
#if CONFIG_IS_ENABLED(DM_USB_GADGET)
-int dm_usb_gadget_handle_interrupts(struct udevice *dev)
+static int dwc3_layerscape_peripheral_probe(struct udevice *dev)
{
struct dwc3_layerscape_priv *priv = dev_get_priv(dev);
- dwc3_gadget_uboot_handle_interrupt(&priv->dwc3);
-
- return 0;
+ return dwc3_layerscape_probe(dev, priv);
}
-static int dwc3_layerscape_peripheral_probe(struct udevice *dev)
+static int dwc3_layerscape_peripheral_remove(struct udevice *dev)
{
struct dwc3_layerscape_priv *priv = dev_get_priv(dev);
- return dwc3_layerscape_probe(dev, priv);
+ return dwc3_layerscape_remove(dev, priv);
}
-static int dwc3_layerscape_peripheral_remove(struct udevice *dev)
+static int dwc3_layerscape_gadget_handle_interrupts(struct udevice *dev)
{
struct dwc3_layerscape_priv *priv = dev_get_priv(dev);
- return dwc3_layerscape_remove(dev, priv);
+ dwc3_gadget_uboot_handle_interrupt(&priv->dwc3);
+
+ return 0;
}
+static const struct usb_gadget_generic_ops dwc3_layerscape_gadget_ops = {
+ .handle_interrupts = dwc3_layerscape_gadget_handle_interrupts,
+};
+
U_BOOT_DRIVER(dwc3_layerscape_peripheral) = {
.name = "dwc3-layerscape-peripheral",
.id = UCLASS_USB_GADGET_GENERIC,
.of_to_plat = dwc3_layerscape_of_to_plat,
+ .ops = &dwc3_layerscape_gadget_ops,
.probe = dwc3_layerscape_peripheral_probe,
.remove = dwc3_layerscape_peripheral_remove,
.priv_auto = sizeof(struct dwc3_layerscape_priv),
diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c
index 21e4f63..41d1599 100644
--- a/drivers/usb/dwc3/dwc3-meson-g12a.c
+++ b/drivers/usb/dwc3/dwc3-meson-g12a.c
@@ -270,7 +270,7 @@
return 0;
}
-int dwc3_meson_g12a_force_mode(struct udevice *dev, enum usb_dr_mode mode)
+static int dwc3_meson_g12a_force_mode(struct udevice *dev, enum usb_dr_mode mode)
{
struct dwc3_meson_g12a *priv = dev_get_plat(dev);
diff --git a/drivers/usb/dwc3/dwc3-meson-gxl.c b/drivers/usb/dwc3/dwc3-meson-gxl.c
index 3e693c5..5fb9b47 100644
--- a/drivers/usb/dwc3/dwc3-meson-gxl.c
+++ b/drivers/usb/dwc3/dwc3-meson-gxl.c
@@ -26,7 +26,6 @@
#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/compat.h>
-#include <asm/arch/usb-gx.h>
/* USB Glue Control Registers */
@@ -158,9 +157,9 @@
if (!priv->phys[i].dev)
continue;
- phy_meson_gxl_usb2_set_mode(&priv->phys[i],
- (i == USB2_OTG_PHY) ? USB_DR_MODE_PERIPHERAL
- : USB_DR_MODE_HOST);
+ generic_phy_set_mode(&priv->phys[i],
+ (i == USB2_OTG_PHY) ? PHY_MODE_USB_DEVICE
+ : PHY_MODE_USB_HOST, 0);
}
return 0;
@@ -193,7 +192,7 @@
return 0;
}
-int dwc3_meson_gxl_force_mode(struct udevice *dev, enum usb_dr_mode mode)
+static int dwc3_meson_gxl_force_mode(struct udevice *dev, enum usb_dr_mode mode)
{
struct dwc3_meson_gxl *priv = dev_get_plat(dev);
@@ -224,7 +223,9 @@
#endif
priv->otg_phy_mode = mode;
- phy_meson_gxl_usb2_set_mode(&priv->phys[USB2_OTG_PHY], mode);
+ generic_phy_set_mode(&priv->phys[USB2_OTG_PHY],
+ mode == USB_DR_MODE_PERIPHERAL ? PHY_MODE_USB_DEVICE
+ : PHY_MODE_USB_HOST, 0);
dwc3_meson_gxl_usb2_set_mode(priv, mode);
@@ -361,8 +362,9 @@
}
if (priv->phys[USB2_OTG_PHY].dev)
- phy_meson_gxl_usb2_set_mode(&priv->phys[USB2_OTG_PHY],
- priv->otg_phy_mode);
+ generic_phy_set_mode(&priv->phys[USB2_OTG_PHY],
+ priv->otg_phy_mode == USB_DR_MODE_PERIPHERAL ? PHY_MODE_USB_DEVICE
+ : PHY_MODE_USB_HOST, 0);
dwc3_meson_gxl_usb2_set_mode(priv, priv->otg_phy_mode);
diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
index 117d38a..24f516a 100644
--- a/drivers/usb/dwc3/ep0.c
+++ b/drivers/usb/dwc3/ep0.c
@@ -60,7 +60,7 @@
dep = dwc->eps[epnum];
if (dep->flags & DWC3_EP_BUSY) {
- dev_vdbg(dwc->dev, "%s still busy", dep->name);
+ dev_vdbg(dwc->dev, "%s still busy\n", dep->name);
return 0;
}
@@ -237,9 +237,9 @@
goto out;
}
- dev_vdbg(dwc->dev, "queueing request %p to %s length %d state '%s'",
- request, dep->name, request->length,
- dwc3_ep0_state_string(dwc->ep0state));
+ dev_vdbg(dwc->dev, "queueing request %p to %s length %d state '%s\n'",
+ request, dep->name, request->length,
+ dwc3_ep0_state_string(dwc->ep0state));
ret = __dwc3_gadget_ep0_queue(dep, req);
@@ -696,35 +696,35 @@
switch (ctrl->bRequest) {
case USB_REQ_GET_STATUS:
- dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS");
+ dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n");
ret = dwc3_ep0_handle_status(dwc, ctrl);
break;
case USB_REQ_CLEAR_FEATURE:
- dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE");
+ dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n");
ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
break;
case USB_REQ_SET_FEATURE:
- dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE");
+ dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n");
ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
break;
case USB_REQ_SET_ADDRESS:
- dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS");
+ dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n");
ret = dwc3_ep0_set_address(dwc, ctrl);
break;
case USB_REQ_SET_CONFIGURATION:
- dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION");
+ dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n");
ret = dwc3_ep0_set_config(dwc, ctrl);
break;
case USB_REQ_SET_SEL:
- dev_vdbg(dwc->dev, "USB_REQ_SET_SEL");
+ dev_vdbg(dwc->dev, "USB_REQ_SET_SEL\n");
ret = dwc3_ep0_set_sel(dwc, ctrl);
break;
case USB_REQ_SET_ISOCH_DELAY:
- dev_vdbg(dwc->dev, "USB_REQ_SET_ISOCH_DELAY");
+ dev_vdbg(dwc->dev, "USB_REQ_SET_ISOCH_DELAY\n");
ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
break;
default:
- dev_vdbg(dwc->dev, "Forwarding to gadget driver");
+ dev_vdbg(dwc->dev, "Forwarding to gadget driver\n");
ret = dwc3_ep0_delegate_req(dwc, ctrl);
break;
}
@@ -910,17 +910,17 @@
switch (dwc->ep0state) {
case EP0_SETUP_PHASE:
- dev_vdbg(dwc->dev, "Setup Phase");
+ dev_vdbg(dwc->dev, "Setup Phase\n");
dwc3_ep0_inspect_setup(dwc, event);
break;
case EP0_DATA_PHASE:
- dev_vdbg(dwc->dev, "Data Phase");
+ dev_vdbg(dwc->dev, "Data Phase\n");
dwc3_ep0_complete_data(dwc, event);
break;
case EP0_STATUS_PHASE:
- dev_vdbg(dwc->dev, "Status Phase");
+ dev_vdbg(dwc->dev, "Status Phase\n");
dwc3_ep0_complete_status(dwc, event);
break;
default:
@@ -1046,7 +1046,7 @@
switch (event->status) {
case DEPEVT_STATUS_CONTROL_DATA:
- dev_vdbg(dwc->dev, "Control Data");
+ dev_vdbg(dwc->dev, "Control Data\n");
/*
* We already have a DATA transfer in the controller's cache,
@@ -1060,7 +1060,7 @@
if (dwc->ep0_expect_in != event->endpoint_number) {
struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in];
- dev_vdbg(dwc->dev, "Wrong direction for Data phase");
+ dev_vdbg(dwc->dev, "Wrong direction for Data phase\n");
dwc3_ep0_end_control_data(dwc, dep);
dwc3_ep0_stall_and_restart(dwc);
return;
@@ -1072,13 +1072,13 @@
if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
return;
- dev_vdbg(dwc->dev, "Control Status");
+ dev_vdbg(dwc->dev, "Control Status\n");
dwc->ep0state = EP0_STATUS_PHASE;
if (dwc->delayed_status) {
WARN_ON_ONCE(event->endpoint_number != 1);
- dev_vdbg(dwc->dev, "Delayed Status");
+ dev_vdbg(dwc->dev, "Delayed Status\n");
return;
}
@@ -1091,10 +1091,10 @@
{
u8 epnum = event->endpoint_number;
- dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'",
- dwc3_ep_event_string(event->endpoint_event),
- epnum >> 1, (epnum & 1) ? "in" : "out",
- dwc3_ep0_state_string(dwc->ep0state));
+ dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n",
+ dwc3_ep_event_string(event->endpoint_event),
+ epnum >> 1, (epnum & 1) ? "in" : "out",
+ dwc3_ep0_state_string(dwc->ep0state));
switch (event->endpoint_event) {
case DWC3_DEPEVT_XFERCOMPLETE:
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index fab3257..8f08fda 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -248,7 +248,7 @@
list_del(&req->list);
req->trb = NULL;
- if (req->request.length)
+ if (req->request.dma && req->request.length)
dwc3_flush_cache((uintptr_t)req->request.dma, req->request.length);
if (req->request.status == -EINPROGRESS)
@@ -256,7 +256,7 @@
if (dwc->ep0_bounced && dep->number == 0)
dwc->ep0_bounced = false;
- else
+ else if (req->request.dma)
usb_gadget_unmap_request(&dwc->gadget, &req->request,
req->direction);
@@ -1606,6 +1606,38 @@
return 0;
}
+static struct usb_ep *dwc3_find_ep(struct usb_gadget *gadget, const char *name)
+{
+ struct usb_ep *ep;
+
+ list_for_each_entry(ep, &gadget->ep_list, ep_list)
+ if (!strcmp(ep->name, name))
+ return ep;
+
+ return NULL;
+}
+
+static struct
+usb_ep *dwc3_gadget_match_ep(struct usb_gadget *gadget,
+ struct usb_endpoint_descriptor *desc,
+ struct usb_ss_ep_comp_descriptor *comp_desc)
+{
+ /*
+ * First try standard, common configuration: ep1in-bulk,
+ * ep2out-bulk, ep3in-int to match other udc drivers to avoid
+ * confusion in already deployed software (endpoint numbers
+ * hardcoded in userspace software/drivers)
+ */
+ if (usb_endpoint_is_bulk_in(desc))
+ return dwc3_find_ep(gadget, "ep1in");
+ if (usb_endpoint_is_bulk_out(desc))
+ return dwc3_find_ep(gadget, "ep2out");
+ if (usb_endpoint_is_int_in(desc))
+ return dwc3_find_ep(gadget, "ep3in");
+
+ return NULL;
+}
+
static const struct usb_gadget_ops dwc3_gadget_ops = {
.get_frame = dwc3_gadget_get_frame,
.wakeup = dwc3_gadget_wakeup,
@@ -1613,6 +1645,7 @@
.pullup = dwc3_gadget_pullup,
.udc_start = dwc3_gadget_start,
.udc_stop = dwc3_gadget_stop,
+ .match_ep = dwc3_gadget_match_ep,
};
/* -------------------------------------------------------------------------- */
diff --git a/drivers/usb/gadget/dwc2_udc_otg.c b/drivers/usb/gadget/dwc2_udc_otg.c
index 6bd395a..7e9dd6f 100644
--- a/drivers/usb/gadget/dwc2_udc_otg.c
+++ b/drivers/usb/gadget/dwc2_udc_otg.c
@@ -941,11 +941,6 @@
return 0;
}
-int dm_usb_gadget_handle_interrupts(struct udevice *dev)
-{
- return dwc2_udc_handle_interrupt();
-}
-
#if CONFIG_IS_ENABLED(DM_USB_GADGET)
struct dwc2_priv_data {
struct clk_bulk clks;
@@ -1173,6 +1168,15 @@
return dm_scan_fdt_dev(dev);
}
+static int dwc2_gadget_handle_interrupts(struct udevice *dev)
+{
+ return dwc2_udc_handle_interrupt();
+}
+
+static const struct usb_gadget_generic_ops dwc2_gadget_ops = {
+ .handle_interrupts = dwc2_gadget_handle_interrupts,
+};
+
static const struct udevice_id dwc2_udc_otg_ids[] = {
{ .compatible = "snps,dwc2" },
{ .compatible = "brcm,bcm2835-usb" },
@@ -1185,6 +1189,7 @@
.name = "dwc2-udc-otg",
.id = UCLASS_USB_GADGET_GENERIC,
.of_match = dwc2_udc_otg_ids,
+ .ops = &dwc2_gadget_ops,
.of_to_plat = dwc2_udc_otg_of_to_plat,
.probe = dwc2_udc_otg_probe,
.remove = dwc2_udc_otg_remove,
@@ -1200,4 +1205,9 @@
return readl(&usbotg_reg->gotgctl) & B_SESSION_VALID;
}
+#else
+int dm_usb_gadget_handle_interrupts(struct udevice *dev)
+{
+ return dwc2_udc_handle_interrupt();
+}
#endif /* CONFIG_IS_ENABLED(DM_USB_GADGET) */
diff --git a/drivers/usb/gadget/epautoconf.c b/drivers/usb/gadget/epautoconf.c
index 0a70035..a4da4f7 100644
--- a/drivers/usb/gadget/epautoconf.c
+++ b/drivers/usb/gadget/epautoconf.c
@@ -12,7 +12,6 @@
#include <linux/errno.h>
#include <linux/usb/gadget.h>
#include <asm/unaligned.h>
-#include "gadget_chips.h"
#define isdigit(c) ('0' <= (c) && (c) <= '9')
@@ -167,18 +166,6 @@
return 1;
}
-static struct usb_ep *
-find_ep(struct usb_gadget *gadget, const char *name)
-{
- struct usb_ep *ep;
-
- list_for_each_entry(ep, &gadget->ep_list, ep_list) {
- if (0 == strcmp(ep->name, name))
- return ep;
- }
- return NULL;
-}
-
/**
* usb_ep_autoconfig - choose an endpoint matching the descriptor
* @gadget: The device to which the endpoint must belong.
@@ -214,76 +201,14 @@
struct usb_endpoint_descriptor *desc
)
{
- struct usb_ep *ep = NULL;
- u8 type;
+ struct usb_ep *ep;
- type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
-
- /* First, apply chip-specific "best usage" knowledge.
- * This might make a good usb_gadget_ops hook ...
- */
- if (gadget_is_net2280(gadget) && type == USB_ENDPOINT_XFER_INT) {
- /* ep-e, ep-f are PIO with only 64 byte fifos */
- ep = find_ep(gadget, "ep-e");
- if (ep && ep_matches(gadget, ep, desc))
- return ep;
- ep = find_ep(gadget, "ep-f");
- if (ep && ep_matches(gadget, ep, desc))
- return ep;
-
- } else if (gadget_is_goku(gadget)) {
- if (USB_ENDPOINT_XFER_INT == type) {
- /* single buffering is enough */
- ep = find_ep(gadget, "ep3-bulk");
- if (ep && ep_matches(gadget, ep, desc))
- return ep;
- } else if (USB_ENDPOINT_XFER_BULK == type
- && (USB_DIR_IN & desc->bEndpointAddress)) {
- /* DMA may be available */
- ep = find_ep(gadget, "ep2-bulk");
- if (ep && ep_matches(gadget, ep, desc))
- return ep;
- }
-
- } else if (gadget_is_sh(gadget) && USB_ENDPOINT_XFER_INT == type) {
- /* single buffering is enough; maybe 8 byte fifo is too */
- ep = find_ep(gadget, "ep3in-bulk");
- if (ep && ep_matches(gadget, ep, desc))
- return ep;
-
- } else if (gadget_is_mq11xx(gadget) && USB_ENDPOINT_XFER_INT == type) {
- ep = find_ep(gadget, "ep1-bulk");
- if (ep && ep_matches(gadget, ep, desc))
- return ep;
-#ifndef CONFIG_SPL_BUILD
- } else if (gadget_is_dwc3(gadget)) {
- const char *name = NULL;
- /*
- * First try standard, common configuration: ep1in-bulk,
- * ep2out-bulk, ep3in-int to match other udc drivers to avoid
- * confusion in already deployed software (endpoint numbers
- * hardcoded in userspace software/drivers)
- */
- if ((desc->bEndpointAddress & USB_DIR_IN) &&
- type == USB_ENDPOINT_XFER_BULK)
- name = "ep1in";
- else if ((desc->bEndpointAddress & USB_DIR_IN) == 0 &&
- type == USB_ENDPOINT_XFER_BULK)
- name = "ep2out";
- else if ((desc->bEndpointAddress & USB_DIR_IN) &&
- type == USB_ENDPOINT_XFER_INT)
- name = "ep3in";
-
- if (name)
- ep = find_ep(gadget, name);
+ if (gadget->ops->match_ep) {
+ ep = gadget->ops->match_ep(gadget, desc, NULL);
if (ep && ep_matches(gadget, ep, desc))
return ep;
-#endif
}
- if (gadget->ops->match_ep)
- ep = gadget->ops->match_ep(gadget, desc, NULL);
-
/* Second, look at endpoints until an unclaimed one looks usable */
list_for_each_entry(ep, &gadget->ep_list, ep_list) {
if (ep_matches(gadget, ep, desc))
diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c
index b8b29d3..b7b7bac 100644
--- a/drivers/usb/gadget/ether.c
+++ b/drivers/usb/gadget/ether.c
@@ -22,8 +22,8 @@
#include <malloc.h>
#include <memalign.h>
#include <linux/ctype.h>
+#include <version.h>
-#include "gadget_chips.h"
#include "rndis.h"
#include <dm.h>
@@ -1989,28 +1989,15 @@
* standard protocol is _strongly_ preferred for interop purposes.
* (By everyone except Microsoft.)
*/
- if (gadget_is_musbhdrc(gadget)) {
+
+ if (IS_ENABLED(CONFIG_USB_MUSB_GADGET) &&
+ !strcmp("musb-hdrc", gadget->name)) {
/* reduce tx dma overhead by avoiding special cases */
zlp = 0;
- } else if (gadget_is_sh(gadget)) {
- /* sh doesn't support multiple interfaces or configs */
- cdc = 0;
- rndis = 0;
}
- gcnum = usb_gadget_controller_number(gadget);
- if (gcnum >= 0)
- device_desc.bcdDevice = cpu_to_le16(0x0300 + gcnum);
- else {
- /*
- * can't assume CDC works. don't want to default to
- * anything less functional on CDC-capable hardware,
- * so we fail in this case.
- */
- pr_err("controller '%s' not recognized",
- gadget->name);
- return -ENODEV;
- }
+ gcnum = (U_BOOT_VERSION_NUM << 4) | U_BOOT_VERSION_NUM_PATCH;
+ device_desc.bcdDevice = cpu_to_le16(gcnum);
/*
* If there's an RNDIS configuration, that's what Windows wants to
diff --git a/drivers/usb/gadget/g_dnl.c b/drivers/usb/gadget/g_dnl.c
index b5b5f5d..631969b 100644
--- a/drivers/usb/gadget/g_dnl.c
+++ b/drivers/usb/gadget/g_dnl.c
@@ -17,10 +17,10 @@
#include <usb_mass_storage.h>
#include <dfu.h>
#include <thor.h>
+#include <version.h>
#include <env_callback.h>
-#include "gadget_chips.h"
#include "composite.c"
/*
@@ -199,18 +199,6 @@
g_dnl_detach_request = false;
}
-static int g_dnl_get_bcd_device_number(struct usb_composite_dev *cdev)
-{
- struct usb_gadget *gadget = cdev->gadget;
- int gcnum;
-
- gcnum = usb_gadget_controller_number(gadget);
- if (gcnum > 0)
- gcnum += 0x200;
-
- return g_dnl_get_board_bcd_device_number(gcnum);
-}
-
/**
* Update internal serial number variable when the "serial#" env var changes.
*
@@ -261,7 +249,8 @@
if (ret)
goto error;
- gcnum = g_dnl_get_bcd_device_number(cdev);
+ gcnum = g_dnl_get_board_bcd_device_number((U_BOOT_VERSION_NUM << 4) |
+ U_BOOT_VERSION_NUM_PATCH);
if (gcnum >= 0)
device_desc.bcdDevice = cpu_to_le16(gcnum);
else {
diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h
deleted file mode 100644
index 98156c3..0000000
--- a/drivers/usb/gadget/gadget_chips.h
+++ /dev/null
@@ -1,210 +0,0 @@
-/*
- * USB device controllers have lots of quirks. Use these macros in
- * gadget drivers or other code that needs to deal with them, and which
- * autoconfigures instead of using early binding to the hardware.
- *
- * This SHOULD eventually work like the ARM mach_is_*() stuff, driven by
- * some config file that gets updated as new hardware is supported.
- * (And avoiding all runtime comparisons in typical one-choice configs!)
- *
- * NOTE: some of these controller drivers may not be available yet.
- * Some are available on 2.4 kernels; several are available, but not
- * yet pushed in the 2.6 mainline tree.
- *
- * Ported to U-Boot by: Thomas Smits <ts.smits@gmail.com> and
- * Remy Bohmer <linux@bohmer.net>
- */
-#ifdef CONFIG_USB_GADGET_NET2280
-#define gadget_is_net2280(g) (!strcmp("net2280", (g)->name))
-#else
-#define gadget_is_net2280(g) 0
-#endif
-
-#ifdef CONFIG_USB_GADGET_AMD5536UDC
-#define gadget_is_amd5536udc(g) (!strcmp("amd5536udc", (g)->name))
-#else
-#define gadget_is_amd5536udc(g) 0
-#endif
-
-#ifdef CONFIG_USB_GADGET_DUMMY_HCD
-#define gadget_is_dummy(g) (!strcmp("dummy_udc", (g)->name))
-#else
-#define gadget_is_dummy(g) 0
-#endif
-
-#ifdef CONFIG_USB_GADGET_GOKU
-#define gadget_is_goku(g) (!strcmp("goku_udc", (g)->name))
-#else
-#define gadget_is_goku(g) 0
-#endif
-
-/* SH3 UDC -- not yet ported 2.4 --> 2.6 */
-#ifdef CONFIG_USB_GADGET_SUPERH
-#define gadget_is_sh(g) (!strcmp("sh_udc", (g)->name))
-#else
-#define gadget_is_sh(g) 0
-#endif
-
-/* handhelds.org tree (?) */
-#ifdef CONFIG_USB_GADGET_MQ11XX
-#define gadget_is_mq11xx(g) (!strcmp("mq11xx_udc", (g)->name))
-#else
-#define gadget_is_mq11xx(g) 0
-#endif
-
-#ifdef CONFIG_USB_GADGET_OMAP
-#define gadget_is_omap(g) (!strcmp("omap_udc", (g)->name))
-#else
-#define gadget_is_omap(g) 0
-#endif
-
-/* not yet ported 2.4 --> 2.6 */
-#ifdef CONFIG_USB_GADGET_N9604
-#define gadget_is_n9604(g) (!strcmp("n9604_udc", (g)->name))
-#else
-#define gadget_is_n9604(g) 0
-#endif
-
-#ifdef CONFIG_USB_GADGET_ATMEL_USBA
-#define gadget_is_atmel_usba(g) (!strcmp("atmel_usba_udc", (g)->name))
-#else
-#define gadget_is_atmel_usba(g) 0
-#endif
-
-#ifdef CONFIG_USB_GADGET_AT91
-#define gadget_is_at91(g) (!strcmp("at91_udc", (g)->name))
-#else
-#define gadget_is_at91(g) 0
-#endif
-
-/* status unclear */
-#ifdef CONFIG_USB_GADGET_IMX
-#define gadget_is_imx(g) (!strcmp("imx_udc", (g)->name))
-#else
-#define gadget_is_imx(g) 0
-#endif
-
-#ifdef CONFIG_USB_GADGET_FSL_USB2
-#define gadget_is_fsl_usb2(g) (!strcmp("fsl-usb2-udc", (g)->name))
-#else
-#define gadget_is_fsl_usb2(g) 0
-#endif
-
-/* Mentor high speed function controller */
-/* from Montavista kernel (?) */
-#ifdef CONFIG_USB_GADGET_MUSBHSFC
-#define gadget_is_musbhsfc(g) (!strcmp("musbhsfc_udc", (g)->name))
-#else
-#define gadget_is_musbhsfc(g) 0
-#endif
-
-/* Mentor high speed "dual role" controller, in peripheral role */
-#ifdef CONFIG_USB_MUSB_GADGET
-#define gadget_is_musbhdrc(g) (!strcmp("musb-hdrc", (g)->name))
-#else
-#define gadget_is_musbhdrc(g) 0
-#endif
-
-#ifdef CONFIG_USB_GADGET_M66592
-#define gadget_is_m66592(g) (!strcmp("m66592_udc", (g)->name))
-#else
-#define gadget_is_m66592(g) 0
-#endif
-
-#ifdef CONFIG_CI_UDC
-#define gadget_is_ci(g) (!strcmp("ci_udc", (g)->name))
-#else
-#define gadget_is_ci(g) 0
-#endif
-
-#ifdef CONFIG_USB_DWC3_GADGET
-#define gadget_is_dwc3(g) (!strcmp("dwc3-gadget", (g)->name))
-#else
-#define gadget_is_dwc3(g) 0
-#endif
-
-#ifdef CONFIG_USB_CDNS3_GADGET
-#define gadget_is_cdns3(g) (!strcmp("cdns3-gadget", (g)->name))
-#else
-#define gadget_is_cdns3(g) 0
-#endif
-
-#ifdef CONFIG_USB_GADGET_MAX3420
-#define gadget_is_max3420(g) (!strcmp("max3420-udc", (g)->name))
-#else
-#define gadget_is_max3420(g) 0
-#endif
-
-#ifdef CONFIG_USB_MTU3_GADGET
-#define gadget_is_mtu3(g) (!strcmp("mtu3-gadget", (g)->name))
-#else
-#define gadget_is_mtu3(g) 0
-#endif
-
-#ifdef CONFIG_USB_GADGET_DWC2_OTG
-#define gadget_is_dwc2(g) (!strcmp("dwc2-udc", (g)->name))
-#else
-#define gadget_is_dwc2(g) 0
-#endif
-
-/**
- * usb_gadget_controller_number - support bcdDevice id convention
- * @gadget: the controller being driven
- *
- * Return a 2-digit BCD value associated with the peripheral controller,
- * suitable for use as part of a bcdDevice value, or a negative error code.
- *
- * NOTE: this convention is purely optional, and has no meaning in terms of
- * any USB specification. If you want to use a different convention in your
- * gadget driver firmware -- maybe a more formal revision ID -- feel free.
- *
- * Hosts see these bcdDevice numbers, and are allowed (but not encouraged!)
- * to change their behavior accordingly. For example it might help avoiding
- * some chip bug.
- */
-static inline int usb_gadget_controller_number(struct usb_gadget *gadget)
-{
- if (gadget_is_net2280(gadget))
- return 0x01;
- else if (gadget_is_dummy(gadget))
- return 0x02;
- else if (gadget_is_sh(gadget))
- return 0x04;
- else if (gadget_is_goku(gadget))
- return 0x06;
- else if (gadget_is_mq11xx(gadget))
- return 0x07;
- else if (gadget_is_omap(gadget))
- return 0x08;
- else if (gadget_is_n9604(gadget))
- return 0x09;
- else if (gadget_is_at91(gadget))
- return 0x12;
- else if (gadget_is_imx(gadget))
- return 0x13;
- else if (gadget_is_musbhsfc(gadget))
- return 0x14;
- else if (gadget_is_musbhdrc(gadget))
- return 0x15;
- else if (gadget_is_atmel_usba(gadget))
- return 0x17;
- else if (gadget_is_fsl_usb2(gadget))
- return 0x18;
- else if (gadget_is_amd5536udc(gadget))
- return 0x19;
- else if (gadget_is_m66592(gadget))
- return 0x20;
- else if (gadget_is_ci(gadget))
- return 0x21;
- else if (gadget_is_dwc3(gadget))
- return 0x23;
- else if (gadget_is_cdns3(gadget))
- return 0x24;
- else if (gadget_is_max3420(gadget))
- return 0x25;
- else if (gadget_is_mtu3(gadget))
- return 0x26;
- else if (gadget_is_dwc2(gadget))
- return 0x27;
- return -ENOENT;
-}
diff --git a/drivers/usb/gadget/max3420_udc.c b/drivers/usb/gadget/max3420_udc.c
index 5a227c0..557a1f0 100644
--- a/drivers/usb/gadget/max3420_udc.c
+++ b/drivers/usb/gadget/max3420_udc.c
@@ -808,13 +808,6 @@
spi_wr8(udc, MAX3420_REG_PINCTL, bFDUPSPI);
}
-int dm_usb_gadget_handle_interrupts(struct udevice *dev)
-{
- struct max3420_udc *udc = dev_get_priv(dev);
-
- return max3420_irq(udc);
-}
-
static int max3420_udc_probe(struct udevice *dev)
{
struct max3420_udc *udc = dev_get_priv(dev);
@@ -859,6 +852,17 @@
return 0;
}
+static int max3420_gadget_handle_interrupts(struct udevice *dev)
+{
+ struct max3420_udc *udc = dev_get_priv(dev);
+
+ return max3420_irq(udc);
+}
+
+static const struct usb_gadget_generic_ops max3420_gadget_ops = {
+ .handle_interrupts = max3420_gadget_handle_interrupts,
+};
+
static const struct udevice_id max3420_ids[] = {
{ .compatible = "maxim,max3421-udc" },
{ }
@@ -868,6 +872,7 @@
.name = "max3420-udc",
.id = UCLASS_USB_GADGET_GENERIC,
.of_match = max3420_ids,
+ .ops = &max3420_gadget_ops,
.probe = max3420_udc_probe,
.remove = max3420_udc_remove,
.priv_auto = sizeof(struct max3420_udc),
diff --git a/drivers/usb/gadget/udc/udc-uclass.c b/drivers/usb/gadget/udc/udc-uclass.c
index 5dc23a5..fbe62bb 100644
--- a/drivers/usb/gadget/udc/udc-uclass.c
+++ b/drivers/usb/gadget/udc/udc-uclass.c
@@ -12,6 +12,25 @@
#include <linux/usb/gadget.h>
#if CONFIG_IS_ENABLED(DM_USB_GADGET)
+static inline const struct usb_gadget_generic_ops *
+usb_gadget_generic_dev_ops(struct udevice *dev)
+{
+ return (const struct usb_gadget_generic_ops *)dev->driver->ops;
+}
+
+int dm_usb_gadget_handle_interrupts(struct udevice *dev)
+{
+ const struct usb_gadget_generic_ops *ops;
+
+ ops = usb_gadget_generic_dev_ops(dev);
+ if (!ops)
+ return -EFAULT;
+ if (!ops->handle_interrupts)
+ return -ENOSYS;
+
+ return ops->handle_interrupts(dev);
+}
+
int udc_device_get_by_index(int index, struct udevice **udev)
{
struct udevice *dev = NULL;
@@ -54,6 +73,11 @@
{
return board_usb_cleanup(legacy_index, USB_INIT_DEVICE);
}
+
+__weak int dm_usb_gadget_handle_interrupts(struct udevice *dev)
+{
+ return 0;
+}
#endif
#if CONFIG_IS_ENABLED(DM)
diff --git a/drivers/usb/host/ehci-msm.c b/drivers/usb/host/ehci-msm.c
index a081f71..ff33608 100644
--- a/drivers/usb/host/ehci-msm.c
+++ b/drivers/usb/host/ehci-msm.c
@@ -7,7 +7,9 @@
* Based on Linux driver
*/
+#include <clk.h>
#include <dm.h>
+#include <dm/device_compat.h>
#include <dm/lists.h>
#include <errno.h>
#include <usb.h>
@@ -24,6 +26,8 @@
struct usb_ehci *ehci; /* Start of IP core*/
struct ulpi_viewport ulpi_vp; /* ULPI Viewport */
struct phy phy;
+ struct clk iface_clk;
+ struct clk core_clk;
};
static int msm_init_after_reset(struct ehci_ctrl *dev)
@@ -52,20 +56,46 @@
struct ehci_hcor *hcor;
int ret;
+ ret = clk_get_by_name(dev, "core", &p->core_clk);
+ if (ret) {
+ dev_err(dev, "Failed to get core clock: %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_get_by_name(dev, "iface", &p->iface_clk);
+ if (ret) {
+ dev_err(dev, "Failed to get iface clock: %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(&p->core_clk);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(&p->iface_clk);
+ if (ret)
+ goto cleanup_core;
+
hccr = (struct ehci_hccr *)((phys_addr_t)&ehci->caplength);
hcor = (struct ehci_hcor *)((phys_addr_t)hccr +
HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
ret = generic_setup_phy(dev, &p->phy, 0);
if (ret)
- return ret;
+ goto cleanup_iface;
ret = board_usb_init(0, plat->init_type);
if (ret < 0)
- return ret;
+ goto cleanup_iface;
return ehci_register(dev, hccr, hcor, &msm_ehci_ops, 0,
plat->init_type);
+
+cleanup_iface:
+ clk_disable_unprepare(&p->iface_clk);
+cleanup_core:
+ clk_disable_unprepare(&p->core_clk);
+ return ret;
}
static int ehci_usb_remove(struct udevice *dev)
@@ -81,6 +111,9 @@
/* Stop controller. */
clrbits_le32(&ehci->usbcmd, CMD_RUN);
+ clk_disable_unprepare(&p->iface_clk);
+ clk_disable_unprepare(&p->core_clk);
+
ret = generic_shutdown_phy(&p->phy);
if (ret)
return ret;
diff --git a/drivers/usb/host/usb-sandbox.c b/drivers/usb/host/usb-sandbox.c
index e26f0b2..f687fe2 100644
--- a/drivers/usb/host/usb-sandbox.c
+++ b/drivers/usb/host/usb-sandbox.c
@@ -123,12 +123,7 @@
return ret;
}
-#if CONFIG_IS_ENABLED(DM_USB_GADGET)
-int dm_usb_gadget_handle_interrupts(struct udevice *dev)
-{
- return 0;
-}
-#else
+#if !CONFIG_IS_ENABLED(DM_USB_GADGET)
int usb_gadget_register_driver(struct usb_gadget_driver *driver)
{
struct sandbox_udc *dev = this_controller;
diff --git a/drivers/usb/host/usb-uclass.c b/drivers/usb/host/usb-uclass.c
index cd3a07e..bfec303 100644
--- a/drivers/usb/host/usb-uclass.c
+++ b/drivers/usb/host/usb-uclass.c
@@ -387,7 +387,7 @@
/* if we were not able to find at least one working bus, bail out */
if (controllers_initialized == 0)
- printf("No working controllers found\n");
+ printf("No USB controllers found\n");
return usb_started ? 0 : -ENOENT;
}
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index 1360a59..68cf08e 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -530,9 +530,8 @@
if (!event)
return;
- BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
- != udev->slot_id || GET_COMP_CODE(le32_to_cpu(
- event->event_cmd.status)) != COMP_SUCCESS);
+ BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags)) != udev->slot_id ||
+ GET_COMP_CODE(le32_to_cpu(event->event_cmd.status)) != COMP_SUCCESS);
xhci_acknowledge_event(ctrl);
}
@@ -565,8 +564,7 @@
field = le32_to_cpu(event->trans_event.flags);
BUG_ON(TRB_TO_SLOT_ID(field) != udev->slot_id);
BUG_ON(TRB_TO_EP_INDEX(field) != ep_index);
- BUG_ON(GET_COMP_CODE(le32_to_cpu(event->trans_event.transfer_len
- != COMP_STOP)));
+ BUG_ON(GET_COMP_CODE(le32_to_cpu(event->trans_event.transfer_len != COMP_STOP)));
xhci_acknowledge_event(ctrl);
event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
@@ -580,9 +578,8 @@
comp = GET_COMP_CODE(le32_to_cpu(event->event_cmd.status));
BUG_ON(type != TRB_COMPLETION ||
- TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
- != udev->slot_id || (comp != COMP_SUCCESS && comp
- != COMP_CTX_STATE));
+ TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags)) != udev->slot_id ||
+ (comp != COMP_SUCCESS && comp != COMP_CTX_STATE));
xhci_acknowledge_event(ctrl);
addr = xhci_trb_virt_to_dma(ring->enq_seg,
@@ -592,9 +589,8 @@
if (!event)
return;
- BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
- != udev->slot_id || GET_COMP_CODE(le32_to_cpu(
- event->event_cmd.status)) != COMP_SUCCESS);
+ BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags)) != udev->slot_id ||
+ GET_COMP_CODE(le32_to_cpu(event->event_cmd.status)) != COMP_SUCCESS);
xhci_acknowledge_event(ctrl);
}
diff --git a/drivers/usb/mtu3/mtu3_plat.c b/drivers/usb/mtu3/mtu3_plat.c
index ca86b58..f8e14ea 100644
--- a/drivers/usb/mtu3/mtu3_plat.c
+++ b/drivers/usb/mtu3/mtu3_plat.c
@@ -223,15 +223,6 @@
};
#if CONFIG_IS_ENABLED(DM_USB_GADGET)
-int dm_usb_gadget_handle_interrupts(struct udevice *dev)
-{
- struct mtu3 *mtu = dev_get_priv(dev);
-
- mtu3_irq(0, mtu);
-
- return 0;
-}
-
static int mtu3_gadget_probe(struct udevice *dev)
{
struct ssusb_mtk *ssusb = dev_to_ssusb(dev->parent);
@@ -250,10 +241,24 @@
return 0;
}
+static int mtu3_gadget_handle_interrupts(struct udevice *dev)
+{
+ struct mtu3 *mtu = dev_get_priv(dev);
+
+ mtu3_irq(0, mtu);
+
+ return 0;
+}
+
+static const struct usb_gadget_generic_ops mtu3_gadget_ops = {
+ .handle_interrupts = mtu3_gadget_handle_interrupts,
+};
+
U_BOOT_DRIVER(mtu3_peripheral) = {
.name = "mtu3-peripheral",
.id = UCLASS_USB_GADGET_GENERIC,
.of_match = ssusb_of_match,
+ .ops = &mtu3_gadget_ops,
.probe = mtu3_gadget_probe,
.remove = mtu3_gadget_remove,
.priv_auto = sizeof(struct mtu3),
diff --git a/drivers/usb/musb-new/omap2430.c b/drivers/usb/musb-new/omap2430.c
index c8dd730..96771c2 100644
--- a/drivers/usb/musb-new/omap2430.c
+++ b/drivers/usb/musb-new/omap2430.c
@@ -46,16 +46,6 @@
musb_writel(musb->mregs, OTG_FORCESTDBY, l);
}
-#ifdef CONFIG_DM_USB_GADGET
-int dm_usb_gadget_handle_interrupts(struct udevice *dev)
-{
- struct musb_host_data *host = dev_get_priv(dev);
-
- host->host->isr(0, host->host);
- return 0;
-}
-#endif
-
static int omap2430_musb_init(struct musb *musb)
{
u32 l;
@@ -273,6 +263,21 @@
return 0;
}
+#ifndef CONFIG_USB_MUSB_HOST
+static int omap2340_gadget_handle_interrupts(struct udevice *dev)
+{
+ struct musb_host_data *host = dev_get_priv(dev);
+
+ host->host->isr(0, host->host);
+
+ return 0;
+}
+
+static const struct usb_gadget_generic_ops omap2340_gadget_ops = {
+ .handle_interrupts = omap2340_gadget_handle_interrupts,
+};
+#endif
+
static const struct udevice_id omap2430_musb_ids[] = {
{ .compatible = "ti,omap3-musb" },
{ .compatible = "ti,omap4-musb" },
@@ -285,6 +290,7 @@
.id = UCLASS_USB,
#else
.id = UCLASS_USB_GADGET_GENERIC,
+ .ops = &omap2340_gadget_ops,
#endif
.of_match = omap2430_musb_ids,
.of_to_plat = omap2430_musb_of_to_plat,
diff --git a/drivers/usb/musb-new/ti-musb.c b/drivers/usb/musb-new/ti-musb.c
index 76e8b88..ec1baa9 100644
--- a/drivers/usb/musb-new/ti-musb.c
+++ b/drivers/usb/musb-new/ti-musb.c
@@ -233,15 +233,6 @@
}
#endif
-int dm_usb_gadget_handle_interrupts(struct udevice *dev)
-{
- struct ti_musb_peripheral *priv = dev_get_priv(dev);
-
- priv->periph->isr(0, priv->periph);
-
- return 0;
-}
-
static int ti_musb_peripheral_probe(struct udevice *dev)
{
struct ti_musb_peripheral *priv = dev_get_priv(dev);
@@ -269,12 +260,26 @@
return 0;
}
+static int ti_musb_gadget_handle_interrupts(struct udevice *dev)
+{
+ struct ti_musb_peripheral *priv = dev_get_priv(dev);
+
+ priv->periph->isr(0, priv->periph);
+
+ return 0;
+}
+
+static const struct usb_gadget_generic_ops ti_musb_gadget_ops = {
+ .handle_interrupts = ti_musb_gadget_handle_interrupts,
+};
+
U_BOOT_DRIVER(ti_musb_peripheral) = {
.name = "ti-musb-peripheral",
.id = UCLASS_USB_GADGET_GENERIC,
#if CONFIG_IS_ENABLED(OF_CONTROL)
.of_to_plat = ti_musb_peripheral_of_to_plat,
#endif
+ .ops = &ti_musb_gadget_ops,
.probe = ti_musb_peripheral_probe,
.remove = ti_musb_peripheral_remove,
.ops = &musb_usb_ops,
diff --git a/drivers/usb/musb-new/ux500.c b/drivers/usb/musb-new/ux500.c
index 6b4ef3c..89dd75b 100644
--- a/drivers/usb/musb-new/ux500.c
+++ b/drivers/usb/musb-new/ux500.c
@@ -91,14 +91,6 @@
.disable = ux500_musb_disable,
};
-int dm_usb_gadget_handle_interrupts(struct udevice *dev)
-{
- struct ux500_glue *glue = dev_get_priv(dev);
-
- glue->mdata.host->isr(0, glue->mdata.host);
- return 0;
-}
-
static int ux500_musb_probe(struct udevice *dev)
{
#ifdef CONFIG_USB_MUSB_HOST
@@ -155,6 +147,19 @@
return 0;
}
+static int ux500_gadget_handle_interrupts(struct udevice *dev)
+{
+ struct ux500_glue *glue = dev_get_priv(dev);
+
+ glue->mdata.host->isr(0, glue->mdata.host);
+
+ return 0;
+}
+
+static const struct usb_gadget_generic_ops ux500_gadget_ops = {
+ .handle_interrupts = ux500_gadget_handle_interrupts,
+};
+
static const struct udevice_id ux500_musb_ids[] = {
{ .compatible = "stericsson,db8500-musb" },
{ }
@@ -168,6 +173,7 @@
.id = UCLASS_USB_GADGET_GENERIC,
#endif
.of_match = ux500_musb_ids,
+ .ops = &ux500_gadget_ops,
.probe = ux500_musb_probe,
.remove = ux500_musb_remove,
#ifdef CONFIG_USB_MUSB_HOST
diff --git a/drivers/video/tegra20/tegra-dc.c b/drivers/video/tegra20/tegra-dc.c
index d073da7..accabbf 100644
--- a/drivers/video/tegra20/tegra-dc.c
+++ b/drivers/video/tegra20/tegra-dc.c
@@ -49,7 +49,7 @@
int dc_clk[2]; /* Contains clk and its parent */
ulong scdiv; /* Clock divider used by disp_clk_ctrl */
bool rotation; /* 180 degree panel turn */
- bool pipe; /* DC controller: 0 for A, 1 for B */
+ int pipe; /* DC controller: 0 for A, 1 for B */
};
enum {
@@ -461,9 +461,7 @@
}
priv->rotation = dev_read_bool(dev, "nvidia,180-rotation");
-
- if (!strcmp(dev->name, TEGRA_DC_B))
- priv->pipe = 1;
+ priv->pipe = dev_read_u32_default(dev, "nvidia,head", 0);
rgb = fdt_subnode_offset(blob, node, "rgb");
if (rgb < 0) {
diff --git a/drivers/video/tegra20/tegra-dc.h b/drivers/video/tegra20/tegra-dc.h
index 05042da..7d0c189 100644
--- a/drivers/video/tegra20/tegra-dc.h
+++ b/drivers/video/tegra20/tegra-dc.h
@@ -14,15 +14,13 @@
/* arch-tegra/dc exists only because T124 uses it */
#include <asm/arch-tegra/dc.h>
-#define TEGRA_DC_A "dc@54200000"
-#define TEGRA_DC_B "dc@54240000"
#define TEGRA_DSI_A "dsi@54300000"
#define TEGRA_DSI_B "dsi@54400000"
struct tegra_dc_plat {
struct udevice *dev; /* Display controller device */
struct dc_ctlr *dc; /* Display controller regmap */
- bool pipe; /* DC number: 0 for A, 1 for B */
+ int pipe; /* DC number: 0 for A, 1 for B */
ulong scdiv; /* Shift clock divider */
};
diff --git a/drivers/watchdog/mpc8xxx_wdt.c b/drivers/watchdog/mpc8xxx_wdt.c
index 036ff69..7fcb866 100644
--- a/drivers/watchdog/mpc8xxx_wdt.c
+++ b/drivers/watchdog/mpc8xxx_wdt.c
@@ -43,7 +43,7 @@
struct mpc8xxx_wdt_priv *priv = dev_get_priv(dev);
const char *mode = env_get("watchdog_mode");
ulong prescaler = dev_get_driver_data(dev);
- u16 swtc = min_t(u16, timeout * get_board_sys_clk() / 1000 / prescaler, U16_MAX);
+ u16 swtc = min_t(u32, timeout * get_board_sys_clk() / 1000 / prescaler, U16_MAX);
u32 val;
mpc8xxx_wdt_reset(dev);
diff --git a/drivers/watchdog/wdt-uclass.c b/drivers/watchdog/wdt-uclass.c
index c88312e..10be334 100644
--- a/drivers/watchdog/wdt-uclass.c
+++ b/drivers/watchdog/wdt-uclass.c
@@ -17,17 +17,20 @@
#include <asm/global_data.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
+#include <linux/kernel.h>
DECLARE_GLOBAL_DATA_PTR;
#define WATCHDOG_TIMEOUT_SECS (CONFIG_WATCHDOG_TIMEOUT_MSECS / 1000)
struct wdt_priv {
+ /* The udevice owning this wdt_priv. */
+ struct udevice *dev;
/* Timeout, in seconds, to configure this device to. */
u32 timeout;
/*
* Time, in milliseconds, between calling the device's ->reset()
- * method from watchdog_reset().
+ * method from schedule().
*/
ulong reset_period;
/*
@@ -40,18 +43,17 @@
/* autostart */
bool autostart;
- struct cyclic_info *cyclic;
+ struct cyclic_info cyclic;
};
-static void wdt_cyclic(void *ctx)
+static void wdt_cyclic(struct cyclic_info *c)
{
- struct udevice *dev = ctx;
- struct wdt_priv *priv;
+ struct wdt_priv *priv = container_of(c, struct wdt_priv, cyclic);
+ struct udevice *dev = priv->dev;
if (!device_active(dev))
return;
- priv = dev_get_uclass_priv(dev);
if (!priv->running)
return;
@@ -121,24 +123,20 @@
struct wdt_priv *priv = dev_get_uclass_priv(dev);
char str[16];
- priv->running = true;
-
memset(str, 0, 16);
if (IS_ENABLED(CONFIG_WATCHDOG)) {
+ if (priv->running)
+ cyclic_unregister(&priv->cyclic);
+
/* Register the watchdog driver as a cyclic function */
- priv->cyclic = cyclic_register(wdt_cyclic,
- priv->reset_period * 1000,
- dev->name, dev);
- if (!priv->cyclic) {
- printf("cyclic_register for %s failed\n",
- dev->name);
- return -ENODEV;
- } else {
- snprintf(str, 16, "every %ldms",
- priv->reset_period);
- }
+ cyclic_register(&priv->cyclic, wdt_cyclic,
+ priv->reset_period * 1000,
+ dev->name);
+
+ snprintf(str, 16, "every %ldms", priv->reset_period);
}
+ priv->running = true;
printf("WDT: Started %s with%s servicing %s (%ds timeout)\n",
dev->name, IS_ENABLED(CONFIG_WATCHDOG) ? "" : "out",
str, (u32)lldiv(timeout_ms, 1000));
@@ -159,6 +157,9 @@
if (ret == 0) {
struct wdt_priv *priv = dev_get_uclass_priv(dev);
+ if (IS_ENABLED(CONFIG_WATCHDOG) && priv->running)
+ cyclic_unregister(&priv->cyclic);
+
priv->running = false;
}
@@ -220,21 +221,6 @@
return ret;
}
-
-#if defined(CONFIG_WATCHDOG)
-/*
- * Called by macro WATCHDOG_RESET. This function be called *very* early,
- * so we need to make sure, that the watchdog driver is ready before using
- * it in this function.
- */
-void watchdog_reset(void)
-{
- /*
- * Empty function for now. The actual WDT handling is now done in
- * the cyclic function instead.
- */
-}
-#endif
static int wdt_pre_probe(struct udevice *dev)
{
@@ -257,12 +243,13 @@
autostart = true;
}
priv = dev_get_uclass_priv(dev);
+ priv->dev = dev;
priv->timeout = timeout;
priv->reset_period = reset_period;
priv->autostart = autostart;
/*
* Pretend this device was last reset "long" ago so the first
- * watchdog_reset will actually call its ->reset method.
+ * schedule() will actually call its ->reset method.
*/
priv->next_reset = get_timer(0);
diff --git a/dts/upstream/src/arm64/Makefile b/dts/upstream/src/arm64/Makefile
index 9a8f6aa..26a83d3 100644
--- a/dts/upstream/src/arm64/Makefile
+++ b/dts/upstream/src/arm64/Makefile
@@ -7,6 +7,10 @@
# Add any required device tree compiler flags here
DTC_FLAGS += -a 0x8
+ifdef CONFIG_RCAR_64
+DTC_FLAGS += -R 4 -p 0x1000
+endif
+
PHONY += dtbs
dtbs: $(addprefix $(obj)/, $(dtb-y))
@:
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts b/dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts
new file mode 100644
index 0000000..98c622b
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts
@@ -0,0 +1,721 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include "rk3588.dtsi"
+
+/ {
+ model = "ArmSoM Sige7";
+ compatible = "armsom,sige7", "rockchip,rk3588";
+
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ analog-sound {
+ compatible = "audio-graph-card";
+ dais = <&i2s0_8ch_p0>;
+ label = "rk3588-es8316";
+ hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hp_detect>;
+ routing = "MIC2", "Mic Jack",
+ "Headphones", "HPOL",
+ "Headphones", "HPOR";
+ widgets = "Microphone", "Mic Jack",
+ "Headphone", "Headphones";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_rgb_g>;
+
+ led_green: led-0 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led_red: led-1 {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "none";
+ };
+ };
+
+ fan: pwm-fan {
+ compatible = "pwm-fan";
+ cooling-levels = <0 95 145 195 255>;
+ fan-supply = <&vcc5v0_sys>;
+ pwms = <&pwm1 0 50000 0>;
+ #cooling-cells = <2>;
+ };
+
+ vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_pcie2x1l2";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <5000>;
+ vin-supply = <&vcc_3v3_s3>;
+ };
+
+ vcc3v3_pcie30: vcc3v3-pcie30-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
+ regulator-name = "vcc3v3_pcie30";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <5000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_host: vcc5v0-host-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_host";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_host_en>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v1_nldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&combphy0_ps {
+ status = "okay";
+};
+
+&combphy1_ps {
+ status = "okay";
+};
+
+&combphy2_psu {
+ status = "okay";
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu_s0>;
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0m2_xfer>;
+ status = "okay";
+
+ vdd_cpu_big0_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big0_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_big1_s0: regulator@43 {
+ compatible = "rockchip,rk8603", "rockchip,rk8602";
+ reg = <0x43>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big1_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c6 {
+ status = "okay";
+
+ hym8563: rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <0>;
+ clock-output-names = "hym8563";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hym8563_int>;
+ wakeup-source;
+ };
+};
+
+&i2c7 {
+ status = "okay";
+
+ es8316: audio-codec@11 {
+ compatible = "everest,es8316";
+ reg = <0x11>;
+ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
+ assigned-clock-rates = <12288000>;
+ clocks = <&cru I2S0_8CH_MCLKOUT>;
+ clock-names = "mclk";
+ #sound-dai-cells = <0>;
+
+ port {
+ es8316_p0_0: endpoint {
+ remote-endpoint = <&i2s0_8ch_p0_0>;
+ };
+ };
+ };
+};
+
+&i2s0_8ch {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s0_lrck
+ &i2s0_mclk
+ &i2s0_sclk
+ &i2s0_sdi0
+ &i2s0_sdo0>;
+ status = "okay";
+
+ i2s0_8ch_p0: port {
+ i2s0_8ch_p0_0: endpoint {
+ dai-format = "i2s";
+ mclk-fs = <256>;
+ remote-endpoint = <&es8316_p0_0>;
+ };
+ };
+};
+
+/* phy1 - right ethernet port */
+&pcie2x1l0 {
+ reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+/* phy2 - WiFi */
+&pcie2x1l1 {
+ reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+/* phy0 - left ethernet port */
+&pcie2x1l2 {
+ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&pcie30phy {
+ status = "okay";
+};
+
+&pcie3x4 {
+ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie30>;
+ status = "okay";
+};
+
+&pinctrl {
+ hym8563 {
+ hym8563_int: hym8563-int {
+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ leds {
+ led_rgb_g: led-rgb-g {
+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ led_rgb_r: led-rgb-r {
+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sound {
+ hp_detect: hp-detect {
+ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ vcc5v0_host_en: vcc5v0-host-en {
+ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&avcc_1v8_s0>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ no-sdio;
+ no-sd;
+ non-removable;
+ mmc-hs200-1_8v;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ max-frequency = <200000000>;
+ no-sdio;
+ no-mmc;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_3v3_s3>;
+ vqmmc-supply = <&vccio_sd_s0>;
+ status = "okay";
+};
+
+&spi2 {
+ assigned-clocks = <&cru CLK_SPI2>;
+ assigned-clock-rates = <200000000>;
+ num-cs = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+ status = "okay";
+
+ pmic@0 {
+ compatible = "rockchip,rk806";
+ spi-max-frequency = <1000000>;
+ reg = <0x0>;
+
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+
+ system-power-controller;
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc5-supply = <&vcc5v0_sys>;
+ vcc6-supply = <&vcc5v0_sys>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc5v0_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+ vcc10-supply = <&vcc5v0_sys>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+ vcc12-supply = <&vcc5v0_sys>;
+ vcc13-supply = <&vcc_1v1_nldo_s3>;
+ vcc14-supply = <&vcc_1v1_nldo_s3>;
+ vcca-supply = <&vcc5v0_sys>;
+
+ rk806_dvs1_null: dvs1-null-pins {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs2_null: dvs2-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs3_null: dvs3-null-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ regulators {
+ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_gpu_s0";
+ regulator-enable-ramp-delay = <400>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_cpu_lit_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_log_s0: dcdc-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_log_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_vdenc_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_ddr_s0: dcdc-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <900000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_ddr_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ vdd2_ddr_s3: dcdc-reg6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vdd2_ddr_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_2v0_pldo_s3: dcdc-reg7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_2v0_pldo_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <2000000>;
+ };
+ };
+
+ vcc_3v3_s3: dcdc-reg8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_3v3_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vddq_ddr_s0: dcdc-reg9 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vddq_ddr_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s3: dcdc-reg10 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avcc_1v8_s0: pldo-reg1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "avcc_1v8_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s0: pldo-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avdd_1v2_s0: pldo-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "avdd_1v2_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3_s0: pldo-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vcc_3v3_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd_s0: pldo-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vccio_sd_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ pldo6_s3: pldo-reg6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "pldo6_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_0v75_s3: nldo-reg1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-name = "vdd_0v75_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_ddr_pll_s0: nldo-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-name = "vdd_ddr_pll_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ avdd_0v75_s0: nldo-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-name = "avdd_0v75_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v85_s0: nldo-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-name = "vdd_0v85_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v75_s0: nldo-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-name = "vdd_0v75_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&u2phy0 {
+ status = "okay";
+};
+
+&u2phy0_otg {
+ status = "okay";
+};
+
+&u2phy1 {
+ status = "okay";
+};
+
+&u2phy1_otg {
+ status = "okay";
+};
+
+&u2phy3 {
+ status = "okay";
+};
+
+&u2phy3_host {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-0 = <&uart2m0_xfer>;
+ status = "okay";
+};
+
+&usbdp_phy1 {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&usb_host1_xhci {
+ dr_mode = "host";
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi
index 94ecb9b..170501a 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi
@@ -357,7 +357,7 @@
vcca-supply = <&vcc5v0_sys>;
rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl2";
+ pins = "gpio_pwrctrl1";
function = "pin_fun0";
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi
index c0d4a15..d9bf675 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi
@@ -182,7 +182,7 @@
#gpio-cells = <2>;
rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl2";
+ pins = "gpio_pwrctrl1";
function = "pin_fun0";
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts b/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts
index 39d6500..7d7303f 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts
@@ -452,7 +452,7 @@
vcca-supply = <&vcc5v0_sys>;
rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl2";
+ pins = "gpio_pwrctrl1";
function = "pin_fun0";
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-tiger-haikou.dts b/dts/upstream/src/arm64/rockchip/rk3588-tiger-haikou.dts
index d672198..e4b7a0a 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-tiger-haikou.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588-tiger-haikou.dts
@@ -113,6 +113,16 @@
vin-supply = <&dc_12v>;
};
+ vcc5v0_otg: vcc5v0-otg-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&otg_vbus_drv>;
+ regulator-name = "vcc5v0_otg";
+ regulator-always-on;
+ };
+
vcc5v0_usb: vcc5v0-usb-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb";
@@ -137,6 +147,10 @@
status = "okay";
};
+&extcon_usb3 {
+ status = "okay";
+};
+
&gmac0 {
status = "okay";
};
@@ -199,6 +213,13 @@
<3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
+
+ usb2 {
+ otg_vbus_drv: otg-vbus-drv {
+ rockchip,pins =
+ <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
};
&sdmmc {
@@ -214,6 +235,23 @@
status = "okay";
};
+&u2phy0 {
+ status = "okay";
+};
+
+&u2phy0_otg {
+ phy-supply = <&vcc5v0_otg>;
+ status = "okay";
+};
+
+&u2phy1 {
+ status = "okay";
+};
+
+&u2phy1_otg {
+ status = "okay";
+};
+
&u2phy2 {
status = "okay";
};
@@ -231,25 +269,38 @@
};
&uart2 {
- pinctrl-0 = <&uart2m2_xfer>;
status = "okay";
};
&uart5 {
rts-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>;
+};
+
+&usbdp_phy0 {
status = "okay";
};
-/* host0 on Q7_USB_P2, lower usb3 port */
+&usbdp_phy1 {
+ status = "okay";
+};
+
+/* host0 on Q7_USB_P2, upper usb3 port */
&usb_host0_ehci {
status = "okay";
};
-/* host0 on Q7_USB_P2, lower usb3 port */
+/* host0 on Q7_USB_P2, upper usb3 port */
&usb_host0_ohci {
status = "okay";
};
+/* host0_xhci on Q7_USB_P1, usb3-otg port */
+&usb_host0_xhci {
+ dr_mode = "otg";
+ extcon = <&extcon_usb3>;
+ status = "okay";
+};
+
/* host1 on Q7_USB_P3, usb2 port */
&usb_host1_ehci {
status = "okay";
@@ -260,7 +311,13 @@
status = "okay";
};
+/* host1_xhci on Q7_USB_P0, lower usb3 port */
+&usb_host1_xhci {
+ dr_mode = "host";
+ status = "okay";
+};
+
-/* host2 on Q7_USB_P2, lower usb3 port */
+/* host2 on Q7_USB_P2, upper usb3 port */
&usb_host2_xhci {
status = "okay";
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi
index 1eb2543..aebe1fe 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi
@@ -23,6 +23,14 @@
reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>;
};
+ extcon_usb3: extcon-usb3 {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb3_id>;
+ status = "disabled";
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -46,7 +54,7 @@
pcie_refclk_gen: pcie-refclk-gen-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency = <1000000000>;
+ clock-frequency = <100000000>;
};
pcie_refclk: pcie-refclk-clock {
@@ -139,6 +147,11 @@
snps,reset-delays-us = <0 10000 100000>;
};
+&gpu {
+ mali-supply = <&vdd_gpu_s0>;
+ status = "okay";
+};
+
&i2c1 {
pinctrl-0 = <&i2c1m0_xfer>;
};
@@ -322,6 +335,13 @@
rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
+
+ usb3 {
+ usb3_id: usb3-id {
+ rockchip,pins =
+ <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
};
&saradc {
@@ -396,7 +416,7 @@
vcca-supply = <&vcc5v0_sys>;
rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl2";
+ pins = "gpio_pwrctrl1";
function = "pin_fun0";
};
@@ -683,6 +703,11 @@
status = "okay";
};
+/* Routed to UART0 on the Q7 connector */
+&uart2 {
+ pinctrl-0 = <&uart2m2_xfer>;
+};
+
/* Mule-ATtiny UPDI */
&uart4 {
pinctrl-0 = <&uart4m2_xfer>;
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-turing-rk1.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-turing-rk1.dtsi
index dc08da5..6b9206c 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-turing-rk1.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588-turing-rk1.dtsi
@@ -318,7 +318,7 @@
#gpio-cells = <2>;
rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl2";
+ pins = "gpio_pwrctrl1";
function = "pin_fun0";
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588.dtsi b/dts/upstream/src/arm64/rockchip/rk3588.dtsi
index 5519c14..5984016 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588.dtsi
@@ -7,6 +7,26 @@
#include "rk3588-pinctrl.dtsi"
/ {
+ usb_host1_xhci: usb@fc400000 {
+ compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
+ reg = <0x0 0xfc400000 0x0 0x400000>;
+ interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
+ <&cru ACLK_USB3OTG1>;
+ clock-names = "ref_clk", "suspend_clk", "bus_clk";
+ dr_mode = "otg";
+ phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ phy_type = "utmi_wide";
+ power-domains = <&power RK3588_PD_USB>;
+ resets = <&cru SRST_A_USB3OTG1>;
+ snps,dis_enblslpm_quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis-tx-ipgap-linecheck-quirk;
+ status = "disabled";
+ };
+
pcie30_phy_grf: syscon@fd5b8000 {
compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
reg = <0x0 0xfd5b8000 0x0 0x10000>;
@@ -17,6 +37,36 @@
reg = <0x0 0xfd5c0000 0x0 0x100>;
};
+ usbdpphy1_grf: syscon@fd5cc000 {
+ compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
+ reg = <0x0 0xfd5cc000 0x0 0x4000>;
+ };
+
+ usb2phy1_grf: syscon@fd5d4000 {
+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
+ reg = <0x0 0xfd5d4000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u2phy1: usb2phy@4000 {
+ compatible = "rockchip,rk3588-usb2phy";
+ reg = <0x4000 0x10>;
+ #clock-cells = <0>;
+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
+ clock-names = "phyclk";
+ clock-output-names = "usb480m_phy1";
+ interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
+ resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
+ reset-names = "phy", "apb";
+ status = "disabled";
+
+ u2phy1_otg: otg-port {
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+ };
+
i2s8_8ch: i2s@fddc8000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfddc8000 0x0 0x1000>;
@@ -310,6 +360,28 @@
};
};
+ usbdp_phy1: phy@fed90000 {
+ compatible = "rockchip,rk3588-usbdp-phy";
+ reg = <0x0 0xfed90000 0x0 0x10000>;
+ #phy-cells = <1>;
+ clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
+ <&cru CLK_USBDP_PHY1_IMMORTAL>,
+ <&cru PCLK_USBDPPHY1>,
+ <&u2phy1>;
+ clock-names = "refclk", "immortal", "pclk", "utmi";
+ resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>,
+ <&cru SRST_USBDP_COMBO_PHY1_CMN>,
+ <&cru SRST_USBDP_COMBO_PHY1_LANE>,
+ <&cru SRST_USBDP_COMBO_PHY1_PCS>,
+ <&cru SRST_P_USBDPPHY1>;
+ reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
+ rockchip,u2phy-grf = <&usb2phy1_grf>;
+ rockchip,usb-grf = <&usb_grf>;
+ rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
+ rockchip,vo-grf = <&vo0_grf>;
+ status = "disabled";
+ };
+
combphy1_ps: phy@fee10000 {
compatible = "rockchip,rk3588-naneng-combphy";
reg = <0x0 0xfee10000 0x0 0x100>;
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-coolpi-4b.dts b/dts/upstream/src/arm64/rockchip/rk3588s-coolpi-4b.dts
index e037bf9..7f4d7bb 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s-coolpi-4b.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588s-coolpi-4b.dts
@@ -479,7 +479,7 @@
vcca-supply = <&vcc5v0_sys>;
rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl2";
+ pins = "gpio_pwrctrl1";
function = "pin_fun0";
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-indiedroid-nova.dts b/dts/upstream/src/arm64/rockchip/rk3588s-indiedroid-nova.dts
index ce8119c..a5b76e2 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s-indiedroid-nova.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588s-indiedroid-nova.dts
@@ -528,7 +528,7 @@
vcca-supply = <&vcc5v0_sys>;
rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl2";
+ pins = "gpio_pwrctrl1";
function = "pin_fun0";
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dts b/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dts
index 25de436..73700d7 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dts
@@ -336,7 +336,7 @@
#gpio-cells = <2>;
rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl2";
+ pins = "gpio_pwrctrl1";
function = "pin_fun0";
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts
index 00afb90..5c99636 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts
@@ -414,7 +414,7 @@
#gpio-cells = <2>;
rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl2";
+ pins = "gpio_pwrctrl1";
function = "pin_fun0";
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
index 87b83c8..6ac5ac8 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
@@ -347,6 +347,11 @@
};
};
+ display_subsystem: display-subsystem {
+ compatible = "rockchip,display-subsystem";
+ ports = <&vop_out>;
+ };
+
firmware {
optee: optee {
compatible = "linaro,optee-tz";
@@ -394,11 +399,6 @@
#clock-cells = <0>;
};
- display_subsystem: display-subsystem {
- compatible = "rockchip,display-subsystem";
- ports = <&vop_out>;
- };
-
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
@@ -436,6 +436,84 @@
};
};
+ gpu: gpu@fb000000 {
+ compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf";
+ reg = <0x0 0xfb000000 0x0 0x200000>;
+ #cooling-cells = <2>;
+ assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
+ assigned-clock-rates = <200000000>;
+ clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>,
+ <&cru CLK_GPU_STACKS>;
+ clock-names = "core", "coregroup", "stacks";
+ dynamic-power-coefficient = <2982>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "job", "mmu", "gpu";
+ operating-points-v2 = <&gpu_opp_table>;
+ power-domains = <&power RK3588_PD_GPU>;
+ status = "disabled";
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <675000 675000 850000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <675000 675000 850000>;
+ };
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <675000 675000 850000>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <675000 675000 850000>;
+ };
+ opp-700000000 {
+ opp-hz = /bits/ 64 <700000000>;
+ opp-microvolt = <700000 700000 850000>;
+ };
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <750000 750000 850000>;
+ };
+ opp-900000000 {
+ opp-hz = /bits/ 64 <900000000>;
+ opp-microvolt = <800000 800000 850000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <850000 850000 850000>;
+ };
+ };
+ };
+
+ usb_host0_xhci: usb@fc000000 {
+ compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
+ reg = <0x0 0xfc000000 0x0 0x400000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
+ <&cru ACLK_USB3OTG0>;
+ clock-names = "ref_clk", "suspend_clk", "bus_clk";
+ dr_mode = "otg";
+ phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ phy_type = "utmi_wide";
+ power-domains = <&power RK3588_PD_USB>;
+ resets = <&cru SRST_A_USB3OTG0>;
+ snps,dis_enblslpm_quirk;
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis-tx-ipgap-linecheck-quirk;
+ status = "disabled";
+ };
+
usb_host0_ehci: usb@fc800000 {
compatible = "rockchip,rk3588-ehci", "generic-ehci";
reg = <0x0 0xfc800000 0x0 0x40000>;
@@ -501,6 +579,30 @@
status = "disabled";
};
+ mmu600_pcie: iommu@fc900000 {
+ compatible = "arm,smmu-v3";
+ reg = <0x0 0xfc900000 0x0 0x200000>;
+ interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ mmu600_php: iommu@fcb00000 {
+ compatible = "arm,smmu-v3";
+ reg = <0x0 0xfcb00000 0x0 0x200000>;
+ interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
pmu1grf: syscon@fd58a000 {
compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
reg = <0x0 0xfd58a000 0x0 0x10000>;
@@ -516,12 +618,23 @@
reg = <0x0 0xfd5a4000 0x0 0x2000>;
};
+ vo0_grf: syscon@fd5a6000 {
+ compatible = "rockchip,rk3588-vo-grf", "syscon";
+ reg = <0x0 0xfd5a6000 0x0 0x2000>;
+ clocks = <&cru PCLK_VO0GRF>;
+ };
+
vo1_grf: syscon@fd5a8000 {
compatible = "rockchip,rk3588-vo-grf", "syscon";
reg = <0x0 0xfd5a8000 0x0 0x100>;
clocks = <&cru PCLK_VO1GRF>;
};
+ usb_grf: syscon@fd5ac000 {
+ compatible = "rockchip,rk3588-usb-grf", "syscon";
+ reg = <0x0 0xfd5ac000 0x0 0x4000>;
+ };
+
php_grf: syscon@fd5b0000 {
compatible = "rockchip,rk3588-php-grf", "syscon";
reg = <0x0 0xfd5b0000 0x0 0x1000>;
@@ -537,22 +650,52 @@
reg = <0x0 0xfd5c4000 0x0 0x100>;
};
+ usbdpphy0_grf: syscon@fd5c8000 {
+ compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
+ reg = <0x0 0xfd5c8000 0x0 0x4000>;
+ };
+
+ usb2phy0_grf: syscon@fd5d0000 {
+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
+ reg = <0x0 0xfd5d0000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u2phy0: usb2phy@0 {
+ compatible = "rockchip,rk3588-usb2phy";
+ reg = <0x0 0x10>;
+ #clock-cells = <0>;
+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
+ clock-names = "phyclk";
+ clock-output-names = "usb480m_phy0";
+ interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>;
+ resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
+ reset-names = "phy", "apb";
+ status = "disabled";
+
+ u2phy0_otg: otg-port {
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+ };
+
usb2phy2_grf: syscon@fd5d8000 {
compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
reg = <0x0 0xfd5d8000 0x0 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
- u2phy2: usb2-phy@8000 {
+ u2phy2: usb2phy@8000 {
compatible = "rockchip,rk3588-usb2phy";
reg = <0x8000 0x10>;
- interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
- resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
- reset-names = "phy", "apb";
+ #clock-cells = <0>;
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
clock-names = "phyclk";
clock-output-names = "usb480m_phy2";
- #clock-cells = <0>;
+ interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
+ resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
+ reset-names = "phy", "apb";
status = "disabled";
u2phy2_host: host-port {
@@ -568,16 +711,16 @@
#address-cells = <1>;
#size-cells = <1>;
- u2phy3: usb2-phy@c000 {
+ u2phy3: usb2phy@c000 {
compatible = "rockchip,rk3588-usb2phy";
reg = <0xc000 0x10>;
- interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
- resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
- reset-names = "phy", "apb";
+ #clock-cells = <0>;
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
clock-names = "phyclk";
clock-output-names = "usb480m_phy3";
- #clock-cells = <0>;
+ interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
+ resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
+ reset-names = "phy", "apb";
status = "disabled";
u2phy3_host: host-port {
@@ -646,74 +789,6 @@
status = "disabled";
};
- vop: vop@fdd90000 {
- compatible = "rockchip,rk3588-vop";
- reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>;
- reg-names = "vop", "gamma-lut";
- interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru ACLK_VOP>,
- <&cru HCLK_VOP>,
- <&cru DCLK_VOP0>,
- <&cru DCLK_VOP1>,
- <&cru DCLK_VOP2>,
- <&cru DCLK_VOP3>,
- <&cru PCLK_VOP_ROOT>;
- clock-names = "aclk",
- "hclk",
- "dclk_vp0",
- "dclk_vp1",
- "dclk_vp2",
- "dclk_vp3",
- "pclk_vop";
- iommus = <&vop_mmu>;
- power-domains = <&power RK3588_PD_VOP>;
- rockchip,grf = <&sys_grf>;
- rockchip,vop-grf = <&vop_grf>;
- rockchip,vo1-grf = <&vo1_grf>;
- rockchip,pmu = <&pmu>;
- status = "disabled";
-
- vop_out: ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- vp0: port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
- };
-
- vp1: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
- };
-
- vp2: port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <2>;
- };
-
- vp3: port@3 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <3>;
- };
- };
- };
-
- vop_mmu: iommu@fdd97e00 {
- compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
- reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>;
- interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
- clock-names = "aclk", "iface";
- #iommu-cells = <0>;
- power-domains = <&power RK3588_PD_VOP>;
- status = "disabled";
- };
-
uart0: serial@fd890000 {
compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
reg = <0x0 0xfd890000 0x0 0x100>;
@@ -1084,6 +1159,87 @@
};
};
+ av1d: video-codec@fdc70000 {
+ compatible = "rockchip,rk3588-av1-vpu";
+ reg = <0x0 0xfdc70000 0x0 0x800>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "vdpu";
+ assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
+ assigned-clock-rates = <400000000>, <400000000>;
+ clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
+ clock-names = "aclk", "hclk";
+ power-domains = <&power RK3588_PD_AV1>;
+ resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>;
+ };
+
+ vop: vop@fdd90000 {
+ compatible = "rockchip,rk3588-vop";
+ reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>;
+ reg-names = "vop", "gamma-lut";
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_VOP>,
+ <&cru HCLK_VOP>,
+ <&cru DCLK_VOP0>,
+ <&cru DCLK_VOP1>,
+ <&cru DCLK_VOP2>,
+ <&cru DCLK_VOP3>,
+ <&cru PCLK_VOP_ROOT>;
+ clock-names = "aclk",
+ "hclk",
+ "dclk_vp0",
+ "dclk_vp1",
+ "dclk_vp2",
+ "dclk_vp3",
+ "pclk_vop";
+ iommus = <&vop_mmu>;
+ power-domains = <&power RK3588_PD_VOP>;
+ rockchip,grf = <&sys_grf>;
+ rockchip,vop-grf = <&vop_grf>;
+ rockchip,vo1-grf = <&vo1_grf>;
+ rockchip,pmu = <&pmu>;
+ status = "disabled";
+
+ vop_out: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vp0: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ vp1: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ vp2: port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ vp3: port@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ };
+ };
+
+ vop_mmu: iommu@fdd97e00 {
+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
+ reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ power-domains = <&power RK3588_PD_VOP>;
+ status = "disabled";
+ };
+
i2s4_8ch: i2s@fddc0000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfddc0000 0x0 0x1000>;
@@ -1375,6 +1531,16 @@
reg = <0x0 0xfdf82200 0x0 0x20>;
};
+ dfi: dfi@fe060000 {
+ reg = <0x00 0xfe060000 0x00 0x10000>;
+ compatible = "rockchip,rk3588-dfi";
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
+ rockchip,pmu = <&pmu1grf>;
+ };
+
pcie2x1l1: pcie@fe180000 {
compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
bus-range = <0x30 0x3f>;
@@ -1477,16 +1643,6 @@
};
};
- dfi: dfi@fe060000 {
- reg = <0x00 0xfe060000 0x00 0x10000>;
- compatible = "rockchip,rk3588-dfi";
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
- rockchip,pmu = <&pmu1grf>;
- };
-
gmac1: ethernet@fe1c0000 {
compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
reg = <0x0 0xfe1c0000 0x0 0x10000>;
@@ -2380,6 +2536,28 @@
status = "disabled";
};
+ usbdp_phy0: phy@fed80000 {
+ compatible = "rockchip,rk3588-usbdp-phy";
+ reg = <0x0 0xfed80000 0x0 0x10000>;
+ #phy-cells = <1>;
+ clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
+ <&cru CLK_USBDP_PHY0_IMMORTAL>,
+ <&cru PCLK_USBDPPHY0>,
+ <&u2phy0>;
+ clock-names = "refclk", "immortal", "pclk", "utmi";
+ resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
+ <&cru SRST_USBDP_COMBO_PHY0_CMN>,
+ <&cru SRST_USBDP_COMBO_PHY0_LANE>,
+ <&cru SRST_USBDP_COMBO_PHY0_PCS>,
+ <&cru SRST_P_USBDPPHY0>;
+ reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
+ rockchip,u2phy-grf = <&usb2phy0_grf>;
+ rockchip,usb-grf = <&usb_grf>;
+ rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
+ rockchip,vo-grf = <&vo0_grf>;
+ status = "disabled";
+ };
+
combphy0_ps: phy@fee00000 {
compatible = "rockchip,rk3588-naneng-combphy";
reg = <0x0 0xfee00000 0x0 0x100>;
@@ -2487,19 +2665,6 @@
#interrupt-cells = <2>;
};
};
-
- av1d: video-codec@fdc70000 {
- compatible = "rockchip,rk3588-av1-vpu";
- reg = <0x0 0xfdc70000 0x0 0x800>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "vdpu";
- assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
- assigned-clock-rates = <400000000>, <400000000>;
- clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
- clock-names = "aclk", "hclk";
- power-domains = <&power RK3588_PD_AV1>;
- resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>;
- };
};
#include "rk3588s-pinctrl.dtsi"
diff --git a/dts/upstream/src/xtensa/Makefile b/dts/upstream/src/xtensa/Makefile
new file mode 100644
index 0000000..2a81acb
--- /dev/null
+++ b/dts/upstream/src/xtensa/Makefile
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+include $(srctree)/scripts/Makefile.dts
+
+targets += $(dtb-y)
+
+# Add any required device tree compiler flags here
+DTC_FLAGS += -a 0x8
+
+PHONY += dtbs
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+ @:
+
+clean-files := *.dtb *.dtbo */*.dtb */*.dtbo
diff --git a/env/Kconfig b/env/Kconfig
index 9641abe..451bab4 100644
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -570,7 +570,7 @@
default 0xF0000 if ARCH_SUNXI
default 0xE0000 if ARCH_ZYNQ
default 0x1E00000 if ARCH_ZYNQMP
- default 0x7F40000 if ARCH_VERSAL || ARCH_VERSAL_NET
+ default 0x7F40000 if ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2
default 0x0 if ARC
default 0x140000 if ARCH_AT91
default 0x260000 if ARCH_OMAP2PLUS
@@ -605,7 +605,7 @@
default 0x10000 if ARCH_SUNXI
default 0x8000 if ARCH_ROCKCHIP && ENV_IS_IN_MMC
default 0x2000 if ARCH_ROCKCHIP && ENV_IS_IN_SPI_FLASH
- default 0x8000 if ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET
+ default 0x8000 if ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2
default 0x4000 if ARC
default 0x1f000
help
@@ -615,7 +615,7 @@
hex "Environment Sector-Size"
depends on ENV_IS_IN_FLASH || ENV_IS_IN_SPI_FLASH
default 0x2000 if ARCH_ROCKCHIP
- default 0x40000 if ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET
+ default 0x40000 if ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2
default 0x20000 if ARCH_ZYNQ || ARCH_OMAP2PLUS || ARCH_AT91
default 0x20000 if MICROBLAZE && ENV_IS_IN_SPI_FLASH
default 0x10000 if ARCH_SUNXI && ENV_IS_IN_SPI_FLASH
diff --git a/examples/api/crt0.S b/examples/api/crt0.S
index 57bba9d..06f6d1f 100644
--- a/examples/api/crt0.S
+++ b/examples/api/crt0.S
@@ -33,6 +33,21 @@
str sp, [ip]
b main
+#elif defined(CONFIG_ARM64)
+
+ .text
+ .globl _start
+_start:
+ ldr ip0, =search_hint
+ str sp_el2, [ip0]
+ b main
+
+
+ .globl syscall
+syscall:
+ ldr ip0, =syscall_ptr
+ ldr pc_el2, [ip0]
+
.globl syscall
syscall:
diff --git a/fs/btrfs/inode.c b/fs/btrfs/inode.c
index 4691612..3998ffc 100644
--- a/fs/btrfs/inode.c
+++ b/fs/btrfs/inode.c
@@ -640,7 +640,11 @@
extent_type = btrfs_file_extent_type(leaf, fi);
if (extent_type == BTRFS_FILE_EXTENT_INLINE) {
ret = btrfs_read_extent_inline(path, fi, buf);
- memcpy(dest, buf + page_off, min(page_len, ret));
+ if (ret < 0) {
+ free(buf);
+ return ret;
+ }
+ memcpy(dest, buf + page_off, min3(page_len, ret, len));
free(buf);
return len;
}
@@ -652,7 +656,7 @@
free(buf);
return ret;
}
- memcpy(dest, buf + page_off, page_len);
+ memcpy(dest, buf + page_off, min(page_len, len));
free(buf);
return len;
}
diff --git a/fs/erofs/data.c b/fs/erofs/data.c
index f4b21d7..95b609d 100644
--- a/fs/erofs/data.c
+++ b/fs/erofs/data.c
@@ -313,7 +313,7 @@
}
if (!(map.m_flags & EROFS_MAP_MAPPED)) {
- memset(buffer + end - offset, 0, length);
+ memset(buffer + end - offset, 0, length - skip);
end = map.m_la;
continue;
}
diff --git a/fs/fs.c b/fs/fs.c
index bed1f72..0c47943 100644
--- a/fs/fs.c
+++ b/fs/fs.c
@@ -224,7 +224,7 @@
.exists = ext4fs_exists,
.size = ext4fs_size,
.read = ext4_read_file,
-#ifdef CONFIG_CMD_EXT4_WRITE
+#ifdef CONFIG_EXT4_WRITE
.write = ext4_write_file,
.ln = ext4fs_create_link,
#else
diff --git a/fs/ubifs/ubifs-media.h b/fs/ubifs/ubifs-media.h
index 2b5b26a..299d80f 100644
--- a/fs/ubifs/ubifs-media.h
+++ b/fs/ubifs/ubifs-media.h
@@ -320,12 +320,14 @@
* UBIFS_COMPR_NONE: no compression
* UBIFS_COMPR_LZO: LZO compression
* UBIFS_COMPR_ZLIB: ZLIB compression
+ * UBIFS_COMPR_ZSTD: ZSTD compression
* UBIFS_COMPR_TYPES_CNT: count of supported compression types
*/
enum {
UBIFS_COMPR_NONE,
UBIFS_COMPR_LZO,
UBIFS_COMPR_ZLIB,
+ UBIFS_COMPR_ZSTD,
UBIFS_COMPR_TYPES_CNT,
};
diff --git a/fs/ubifs/ubifs.c b/fs/ubifs/ubifs.c
index 75de01e..f0ea7e5 100644
--- a/fs/ubifs/ubifs.c
+++ b/fs/ubifs/ubifs.c
@@ -26,6 +26,11 @@
#include <linux/err.h>
#include <linux/lzo.h>
+#if IS_ENABLED(CONFIG_ZSTD)
+#include <linux/zstd.h>
+#include <abuf.h>
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
/* compress.c */
@@ -41,6 +46,25 @@
(unsigned long *)out_len, 0, 0);
}
+#if IS_ENABLED(CONFIG_ZSTD)
+static int zstd_decompress_wrapper(const unsigned char *in, size_t in_len,
+ unsigned char *out, size_t *out_len)
+{
+ struct abuf abuf_in, abuf_out;
+ int ret;
+
+ abuf_init_set(&abuf_in, (void *)in, in_len);
+ abuf_init_set(&abuf_out, (void *)out, *out_len);
+
+ ret = zstd_decompress(&abuf_in, &abuf_out);
+ if (ret < 0)
+ return ret;
+
+ *out_len = ret;
+ return 0;
+}
+#endif
+
/* Fake description object for the "none" compressor */
static struct ubifs_compressor none_compr = {
.compr_type = UBIFS_COMPR_NONE,
@@ -69,9 +93,22 @@
.capi_name = "deflate",
.decompress = gzip_decompress,
};
+
+#if IS_ENABLED(CONFIG_ZSTD)
+static struct ubifs_compressor zstd_compr = {
+ .compr_type = UBIFS_COMPR_ZSTD,
+#ifndef __UBOOT__
+ .comp_mutex = &zstd_enc_mutex,
+ .decomp_mutex = &zstd_dec_mutex,
+#endif
+ .name = "zstd",
+ .capi_name = "zstd",
+ .decompress = zstd_decompress_wrapper,
+};
+#endif
/* All UBIFS compressors */
-struct ubifs_compressor *ubifs_compressors[UBIFS_COMPR_TYPES_CNT];
+struct ubifs_compressor *ubifs_compressors[UBIFS_COMPR_TYPES_CNT] = {NULL};
#ifdef __UBOOT__
@@ -165,8 +202,14 @@
compr = ubifs_compressors[compr_type];
+ if (unlikely(!compr)) {
+ ubifs_err(c, "compression type %d is not compiled in", compr_type);
+ return -EINVAL;
+ }
+
if (unlikely(!compr->capi_name)) {
- ubifs_err(c, "%s compression is not compiled in", compr->name);
+ ubifs_err(c, "%s compression is not compiled in",
+ compr->name ? compr->name : "unknown");
return -EINVAL;
}
@@ -231,6 +274,12 @@
if (err)
return err;
+#if IS_ENABLED(CONFIG_ZSTD)
+ err = compr_init(&zstd_compr);
+ if (err)
+ return err;
+#endif
+
err = compr_init(&none_compr);
if (err)
return err;
diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
index fcc3c6e..aa336d6 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -196,10 +196,6 @@
*/
struct udevice *dm_root;
/**
- * @dm_root_f: pre-relocation root instance
- */
- struct udevice *dm_root_f;
- /**
* @uclass_root_s:
* head of core tree when uclasses are not in read-only memory.
*
diff --git a/include/bcb.h b/include/bcb.h
index 1941d8c..a56b547 100644
--- a/include/bcb.h
+++ b/include/bcb.h
@@ -58,7 +58,8 @@
return -EOPNOTSUPP;
}
-static inline int bcb_get(enum bcb_field field, char *value_out)
+static inline int bcb_get(enum bcb_field field,
+ char *value_out, size_t value_size)
{
return -EOPNOTSUPP;
}
diff --git a/include/bootflow.h b/include/bootflow.h
index 080ee85..6affc5e 100644
--- a/include/bootflow.h
+++ b/include/bootflow.h
@@ -63,7 +63,8 @@
*
* @bm_node: Points to siblings in the same bootdev
* @glob_node: Points to siblings in the global list (all bootdev)
- * @dev: Bootdev device which produced this bootflow
+ * @dev: Bootdev device which produced this bootflow, NULL for flows created by
+ * BOOTMETHF_GLOBAL bootmeths
* @blk: Block device which contains this bootflow, NULL if this is a network
* device or sandbox 'host' device
* @part: Partition number (0 for whole device)
diff --git a/include/bootmeth.h b/include/bootmeth.h
index cd95173..4d8ca48 100644
--- a/include/bootmeth.h
+++ b/include/bootmeth.h
@@ -42,7 +42,7 @@
/**
* get_state_desc() - get detailed state information
*
- * Prodecues a textual description of the state of the bootmeth. This
+ * Produces a textual description of the state of the boot method. This
* can include newline characters if it extends to multiple lines. It
* must be a nul-terminated string.
*
@@ -140,7 +140,7 @@
* @dev: Bootmethod device to boot
* @bflow: Bootflow to boot
* Return: does not return on success, since it should boot the
- * Operating Systemn. Returns -EFAULT if that fails, -ENOTSUPP if
+ * operating system. Returns -EFAULT if that fails, -ENOTSUPP if
* trying method resulted in finding out that is not actually
* supported for this boot and should not be tried again unless
* something changes, other -ve on other error
@@ -153,7 +153,7 @@
/**
* bootmeth_get_state_desc() - get detailed state information
*
- * Prodecues a textual description of the state of the bootmeth. This
+ * Produces a textual description of the state of the boot method. This
* can include newline characters if it extends to multiple lines. It
* must be a nul-terminated string.
*
@@ -246,7 +246,7 @@
* @dev: Bootmethod device to use
* @bflow: Bootflow to read
* Return: does not return on success, since it should boot the
- * Operating Systemn. Returns -EFAULT if that fails, other -ve on
+ * operating system. Returns -EFAULT if that fails, other -ve on
* other error
*/
int bootmeth_read_all(struct udevice *dev, struct bootflow *bflow);
@@ -257,7 +257,7 @@
* @dev: Bootmethod device to boot
* @bflow: Bootflow to boot
* Return: does not return on success, since it should boot the
- * Operating Systemn. Returns -EFAULT if that fails, other -ve on
+ * operating system. Returns -EFAULT if that fails, other -ve on
* other error
*/
int bootmeth_boot(struct udevice *dev, struct bootflow *bflow);
@@ -266,7 +266,7 @@
* bootmeth_setup_iter_order() - Set up the ordering of bootmeths to scan
*
* This sets up the ordering information in @iter, based on the selected
- * ordering of the bootmethds in bootstd_priv->bootmeth_order. If there is no
+ * ordering of the boot methods in bootstd_priv->bootmeth_order. If there is no
* ordering there, then all bootmethods are added
*
* @iter: Iterator to update with the order
diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h
index d4c1e06..a4fda55 100644
--- a/include/configs/M5208EVBE.h
+++ b/include/configs/M5208EVBE.h
@@ -111,5 +111,4 @@
#define CFG_SYS_CS0_MASK 0x007F0001
#define CFG_SYS_CS0_CTRL 0x00001FA0
-
#endif /* _M5208EVBE_H */
diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h
index e542818..8939c8e 100644
--- a/include/configs/M5235EVB.h
+++ b/include/configs/M5235EVB.h
@@ -130,5 +130,4 @@
# define CFG_SYS_CS0_CTRL 0x00001D80
#endif
-
#endif /* _M5329EVB_H */
diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h
index 2f4743c..4fd539c 100644
--- a/include/configs/M5249EVB.h
+++ b/include/configs/M5249EVB.h
@@ -120,5 +120,4 @@
#define CFG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
#define CFG_SYS_GPIO1_LED 0x00400000 /* user led */
-
#endif /* M5249 */
diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h
index 0ff0bfc..75c70be 100644
--- a/include/configs/M5253DEMO.h
+++ b/include/configs/M5253DEMO.h
@@ -10,7 +10,6 @@
#define CFG_SYS_UART_PORT (0)
-
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
*/
@@ -132,5 +131,4 @@
#define CFG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
#define CFG_SYS_GPIO1_LED 0x00400000 /* user led */
-
#endif /* _M5253DEMO_H */
diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h
index 98a1718..0d332cb 100644
--- a/include/configs/M5272C3.h
+++ b/include/configs/M5272C3.h
@@ -107,5 +107,4 @@
#define CFG_SYS_PBDAT 0x0000
#define CFG_SYS_PDCNT 0x00000000
-
#endif /* _M5272C3_H */
diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h
index 77ddf71..607c5de 100644
--- a/include/configs/M5275EVB.h
+++ b/include/configs/M5275EVB.h
@@ -116,5 +116,4 @@
#define CFG_SYS_CS1_CTRL 0x00001900
#define CFG_SYS_CS1_MASK 0x00070001
-
#endif /* _M5275EVB_H */
diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h
index e289a23..31699a4 100644
--- a/include/configs/M5282EVB.h
+++ b/include/configs/M5282EVB.h
@@ -127,5 +127,4 @@
#define CFG_SYS_DDRUA 0x05
#define CFG_SYS_PJPAR 0xFF
-
#endif /* _CONFIG_M5282EVB_H */
diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h
index dcc5701..6359915 100644
--- a/include/configs/M53017EVB.h
+++ b/include/configs/M53017EVB.h
@@ -132,5 +132,4 @@
#define CFG_SYS_CS1_MASK 0x00070001
#define CFG_SYS_CS1_CTRL 0x00001FA0
-
#endif /* _M53017EVB_H */
diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
index dd5d4c9..456135b 100644
--- a/include/configs/M5329EVB.h
+++ b/include/configs/M5329EVB.h
@@ -138,5 +138,4 @@
#define CFG_SYS_CS2_CTRL 0x00001f60
#endif
-
#endif /* _M5329EVB_H */
diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h
index 4bb9948..4e8dcb5 100644
--- a/include/configs/M5373EVB.h
+++ b/include/configs/M5373EVB.h
@@ -136,5 +136,4 @@
#define CFG_SYS_CS2_MASK (16 << 20)
#define CFG_SYS_CS2_CTRL 0x00001f60
-
#endif /* _M5373EVB_H */
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 3967cc2..a5176d1 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -132,7 +132,6 @@
*/
#define CFG_SYS_NAND_BASE 0xE0600000
-
/* Vitesse 7385 */
#define CFG_SYS_VSC7385_BASE 0xF0000000
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 28f53ae..7cf6514 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -160,7 +160,6 @@
/* I2C */
-
/*
* RapidIO
*/
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index 78e1362..c95325e 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -355,7 +355,6 @@
#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
#endif
-
#define __USB_PHY_TYPE utmi
/*
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 9834289..87ffa76 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -102,8 +102,6 @@
#endif
-#define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */
-
/* NAND support */
#ifdef CONFIG_MTD_RAW_NAND
/* NAND: device related configs */
diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h
index 06edde6..4b4362c 100644
--- a/include/configs/am57xx_evm.h
+++ b/include/configs/am57xx_evm.h
@@ -36,7 +36,6 @@
#include <configs/ti_omap5_common.h>
/* CPSW Ethernet */
-#define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */
/*
* Default to using SPI for environment, etc.
diff --git a/include/configs/am62px_evm.h b/include/configs/am62px_evm.h
index 06b1286..57a1ba9 100644
--- a/include/configs/am62px_evm.h
+++ b/include/configs/am62px_evm.h
@@ -8,6 +8,30 @@
#ifndef __CONFIG_AM62PX_EVM_H
#define __CONFIG_AM62PX_EVM_H
+/**
+ * define AM62PX_SK_TIBOOT3_IMAGE_GUID - firmware GUID for AM62PX sk tiboot3.bin
+ * define AM62PX_SK_SPL_IMAGE_GUID - firmware GUID for AM62PX sk SPL
+ * define AM62PX_SK_UBOOT_IMAGE_GUID - firmware GUID for AM62PX sk UBOOT
+ *
+ * These GUIDs are used in capsules updates to identify the corresponding
+ * firmware object.
+ *
+ * Board developers using this as a starting reference should
+ * define their own GUIDs to ensure that firmware repositories (like
+ * LVFS) do not confuse them.
+ */
+#define AM62PX_SK_TIBOOT3_IMAGE_GUID \
+ EFI_GUID(0xb08471b7, 0xbe2d, 0x4489, 0x87, 0xa1, \
+ 0xca, 0xb2, 0x8a, 0x0c, 0xf7, 0x43)
+
+#define AM62PX_SK_SPL_IMAGE_GUID \
+ EFI_GUID(0xd02ed781, 0x6d71, 0x4c1a, 0xa9, 0x99, \
+ 0x3c, 0x6a, 0x41, 0xc3, 0x63, 0x24)
+
+#define AM62PX_SK_UBOOT_IMAGE_GUID \
+ EFI_GUID(0x7e6aea51, 0x965c, 0x44ab, 0xb3, 0x88, \
+ 0xda, 0xeb, 0x03, 0xb5, 0x4f, 0x66)
+
/* Now for the remaining common defines */
#include <configs/ti_armv7_common.h>
diff --git a/include/configs/am62x_evm.h b/include/configs/am62x_evm.h
index c8fe59b..0d98f14a 100644
--- a/include/configs/am62x_evm.h
+++ b/include/configs/am62x_evm.h
@@ -9,6 +9,30 @@
#ifndef __CONFIG_AM625_EVM_H
#define __CONFIG_AM625_EVM_H
+/**
+ * define AM62X_SK_TIBOOT3_IMAGE_GUID - firmware GUID for AM62X sk tiboot3.bin
+ * define AM62X_SK_SPL_IMAGE_GUID - firmware GUID for AM62X sk SPL
+ * define AM62X_SK_UBOOT_IMAGE_GUID - firmware GUID for AM62X sk UBOOT
+ *
+ * These GUIDs are used in capsules updates to identify the corresponding
+ * firmware object.
+ *
+ * Board developers using this as a starting reference should
+ * define their own GUIDs to ensure that firmware repositories (like
+ * LVFS) do not confuse them.
+ */
+#define AM62X_SK_TIBOOT3_IMAGE_GUID \
+ EFI_GUID(0xabcb83d2, 0x9cb6, 0x4351, 0xb8, 0xf1, \
+ 0x64, 0x94, 0xbb, 0xe3, 0x70, 0x0a)
+
+#define AM62X_SK_SPL_IMAGE_GUID \
+ EFI_GUID(0xaee355fc, 0xbf97, 0x4264, 0x8c, 0x82, \
+ 0x43, 0x72, 0x55, 0xef, 0xdc, 0x1d)
+
+#define AM62X_SK_UBOOT_IMAGE_GUID \
+ EFI_GUID(0x28ab8c6c, 0xfca8, 0x41d3, 0x8e, 0xa1, \
+ 0x5f, 0x17, 0x1b, 0x7d, 0x29, 0x29)
+
/* Now for the remaining common defines */
#include <configs/ti_armv7_common.h>
diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h
index f9f8c7b..9db8362 100644
--- a/include/configs/am64x_evm.h
+++ b/include/configs/am64x_evm.h
@@ -9,6 +9,30 @@
#ifndef __CONFIG_AM642_EVM_H
#define __CONFIG_AM642_EVM_H
+/**
+ * define AM64X_SK_TIBOOT3_IMAGE_GUID - firmware GUID for AM64X sk tiboot3.bin
+ * define AM64X_SK_SPL_IMAGE_GUID - firmware GUID for AM64X sk SPL
+ * define AM64X_SK_UBOOT_IMAGE_GUID - firmware GUID for AM64X sk UBOOT
+ *
+ * These GUIDs are used in capsules updates to identify the corresponding
+ * firmware object.
+ *
+ * Board developers using this as a starting reference should
+ * define their own GUIDs to ensure that firmware repositories (like
+ * LVFS) do not confuse them.
+ */
+#define AM64X_SK_TIBOOT3_IMAGE_GUID \
+ EFI_GUID(0xede0a0d5, 0x9116, 0x4bfb, 0xaa, 0x54, \
+ 0x09, 0xe9, 0x7b, 0x5a, 0xfe, 0x1a)
+
+#define AM64X_SK_SPL_IMAGE_GUID \
+ EFI_GUID(0x77678f5c, 0x64d4, 0x4910, 0xad, 0x75, \
+ 0x52, 0xc9, 0xd9, 0x5c, 0xdb, 0x1d)
+
+#define AM64X_SK_UBOOT_IMAGE_GUID \
+ EFI_GUID(0xc6ad43a9, 0x7d31, 0x4f5d, 0x83, 0xe9, \
+ 0xb8, 0xef, 0xec, 0xae, 0x05, 0xbf)
+
/* Now for the remaining common defines */
#include <configs/ti_armv7_common.h>
diff --git a/include/configs/amd_versal2.h b/include/configs/amd_versal2.h
new file mode 100644
index 0000000..6a40bbd
--- /dev/null
+++ b/include/configs/amd_versal2.h
@@ -0,0 +1,143 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Configuration for AMD Versal Gen 2
+ * Copyright (C) 2016 - 2022, Xilinx, Inc.
+ * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ *
+ * Based on Configuration for Xilinx ZynqMP
+ */
+
+#ifndef __AMD_VERSAL2_H
+#define __AMD_VERSAL2_H
+
+/* FIXME this is causing issue at least on IPP */
+/* #define CONFIG_ARMV8_SWITCH_TO_EL1 */
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE 0xF9000000
+#define GICR_BASE 0xF9060000
+
+/* Serial setup */
+#define CFG_SYS_BAUDRATE_TABLE \
+ { 4800, 9600, 19200, 38400, 57600, 115200 }
+
+#if defined(CONFIG_CMD_DFU)
+#define DFU_DEFAULT_POLL_TIMEOUT 300
+#define DFU_ALT_INFO_RAM \
+ "dfu_ram_info=" \
+ "setenv dfu_alt_info " \
+ "Image ram 80000 $kernel_size_r\\\\;" \
+ "system.dtb ram $fdt_addr_r $fdt_size_r\0" \
+ "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
+ "thor_ram=run dfu_ram_info && thordown 0 ram 0\0"
+
+#define DFU_ALT_INFO \
+ DFU_ALT_INFO_RAM
+#endif
+
+#if !defined(DFU_ALT_INFO)
+# define DFU_ALT_INFO
+#endif
+
+/* Ethernet driver */
+#if defined(CONFIG_ZYNQ_GEM)
+# define PHY_ANEG_TIMEOUT 20000
+#endif
+
+#define ENV_MEM_LAYOUT_SETTINGS \
+ "fdt_addr_r=0x40000000\0" \
+ "fdt_size_r=0x400000\0" \
+ "pxefile_addr_r=0x10000000\0" \
+ "kernel_addr_r=0x18000000\0" \
+ "kernel_size_r=0x10000000\0" \
+ "kernel_comp_addr_r=0x30000000\0" \
+ "kernel_comp_size=0x3C00000\0" \
+ "ramdisk_addr_r=0x02100000\0" \
+ "script_size_f=0x80000\0"
+
+#if defined(CONFIG_DISTRO_DEFAULTS)
+
+#if defined(CONFIG_MMC_SDHCI_ZYNQ)
+# define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1)
+#else
+# define BOOT_TARGET_DEVICES_MMC(func)
+#endif
+
+#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
+# define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
+#else
+# define BOOT_TARGET_DEVICES_PXE(func)
+#endif
+
+#if defined(CONFIG_CMD_DHCP)
+# define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
+#else
+# define BOOT_TARGET_DEVICES_DHCP(func)
+#endif
+
+#if defined(CONFIG_ZYNQMP_GQSPI) || defined(CONFIG_CADENCE_OSPI_VERSAL)
+# define BOOT_TARGET_DEVICES_XSPI(func) func(XSPI, xspi, 0) func(XSPI, xspi, 1)
+# define BOOTENV_DEV_SHARED_XSPI \
+ "xspi_boot=sf probe $devnum_xspi:0 0 0 && " \
+ "sf read $scriptaddr $script_offset_f $script_size_f && " \
+ "echo XSPI: Trying to boot script at ${scriptaddr} && " \
+ "source ${scriptaddr}; echo XSPI: SCRIPT FAILED: continuing...;\0"
+#else
+# define BOOT_TARGET_DEVICES_XSPI(func)
+# define BOOTENV_DEV_SHARED_XSPI
+#endif
+
+#define BOOTENV_DEV_XSPI(devtypeu, devtypel, instance) \
+ "bootcmd_" #devtypel #instance "=" \
+ "devnum_xspi=" #instance "; run " #devtypel "_boot\0" \
+
+#define BOOTENV_DEV_NAME_XSPI(devtypeu, devtypel, instance) \
+ ""
+
+#define BOOT_TARGET_DEVICES_JTAG(func) func(JTAG, jtag, na)
+
+#define BOOTENV_DEV_JTAG(devtypeu, devtypel, instance) \
+ "bootcmd_jtag=echo JTAG: Trying to boot script at ${scriptaddr} && " \
+ "source ${scriptaddr}; echo JTAG: SCRIPT FAILED: continuing...;\0"
+
+#define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \
+ "jtag "
+
+#define BOOT_TARGET_DEVICES_DFU_USB(func) func(DFU_USB, dfu_usb, 0)
+
+#define BOOTENV_DEV_DFU_USB(devtypeu, devtypel, instance) \
+ "bootcmd_dfu_usb=setenv dfu_alt_info boot.scr ram $scriptaddr " \
+ "$script_size_f; dfu 0 ram 0 && " \
+ "echo DFU: Trying to boot script at ${scriptaddr} && " \
+ "source ${scriptaddr}; " \
+ "echo DFU: SCRIPT FAILED: continuing...;\0"
+
+#define BOOTENV_DEV_NAME_DFU_USB(devtypeu, devtypel, instance) \
+ ""
+
+#define BOOT_TARGET_DEVICES(func) \
+ BOOT_TARGET_DEVICES_JTAG(func) \
+ BOOT_TARGET_DEVICES_MMC(func) \
+ BOOT_TARGET_DEVICES_XSPI(func) \
+ BOOT_TARGET_DEVICES_DFU_USB(func) \
+ BOOT_TARGET_DEVICES_PXE(func) \
+ BOOT_TARGET_DEVICES_DHCP(func)
+
+#include <config_distro_bootcmd.h>
+
+#else /* CONFIG_DISTRO_DEFAULTS */
+# define BOOTENV
+#endif /* CONFIG_DISTRO_DEFAULTS */
+
+/* Initial environment variables */
+#ifndef CFG_EXTRA_ENV_SETTINGS
+#define CFG_EXTRA_ENV_SETTINGS \
+ ENV_MEM_LAYOUT_SETTINGS \
+ BOOTENV \
+ BOOTENV_DEV_SHARED_XSPI \
+ DFU_ALT_INFO
+#endif
+
+#endif /* __AMD_VERSAL2_H */
diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h
index 0df3917..6fd4351 100644
--- a/include/configs/apalis_imx6.h
+++ b/include/configs/apalis_imx6.h
@@ -22,7 +22,6 @@
#define CFG_SYS_FSL_USDHC_NUM 3
/* Network */
-#define PHY_ANEG_TIMEOUT 15000 /* PHY needs longer aneg time */
/* USB Configs */
/* Host */
diff --git a/include/configs/arbel.h b/include/configs/arbel.h
index d8ccc45..61f6a5e 100644
--- a/include/configs/arbel.h
+++ b/include/configs/arbel.h
@@ -15,7 +15,6 @@
#define CFG_SYS_BAUDRATE_TABLE \
{ 9600, 14400, 19200, 38400, 57600, 115200, 230400, 380400, 460800, 921600 }
-
/* Default environemnt variables */
#define CFG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80400000\0" \
"stdin=serial\0" \
diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h
index 286435d..9d4a4bb 100644
--- a/include/configs/aristainetos2.h
+++ b/include/configs/aristainetos2.h
@@ -22,7 +22,6 @@
#include "mx6_common.h"
-
/* MMC Configs */
#define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h
index f3bfefa..6522432 100644
--- a/include/configs/astro_mcf5373l.h
+++ b/include/configs/astro_mcf5373l.h
@@ -184,5 +184,4 @@
#define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
CF_CACR_DCM_P)
-
#endif /* _CONFIG_ASTRO_MCF5373L_H */
diff --git a/include/configs/beagleboneai64.h b/include/configs/beagleboneai64.h
new file mode 100644
index 0000000..85d5724
--- /dev/null
+++ b/include/configs/beagleboneai64.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Configuration header file for BeagleBoneAI64
+ *
+ * https://beagleboard.org/ai-64
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef __CONFIG_BEAGLEBONEAI64_H
+#define __CONFIG_BEAGLEBONEAI64_H
+
+/* FLASH Configuration */
+#define CFG_SYS_FLASH_BASE 0x000000000
+
+/* SPL Loader Configuration */
+#define CFG_SYS_UBOOT_BASE 0x50080000
+
+/**
+ * define BEAGLEBONEAI64_TIBOOT3_IMAGE_GUID - firmware GUID for BeagleBoneAI64
+ * tiboot3.bin
+ * define BEAGLEBONEAI64_SPL_IMAGE_GUID - firmware GUID for BeagleBoneAI64
+ * SPL
+ * define BEAGLEBONEAI64_UBOOT_IMAGE_GUID - firmware GUID for BeagleBoneAI64
+ * UBOOT
+ * define BEAGLEBONEAI64_SYSFW_IMAGE_GUID - firmware GUID for BeagleBoneAI64
+ * SYSFW
+ *
+ * These GUIDs are used in capsules updates to identify the corresponding
+ * firmware object.
+ *
+ * Board developers using this as a starting reference should
+ * define their own GUIDs to ensure that firmware repositories (like
+ * LVFS) do not confuse them.
+ */
+#define BEAGLEBONEAI64_TIBOOT3_IMAGE_GUID \
+ EFI_GUID(0x772a4810, 0x2194, 0x4923, 0x87, 0x54, \
+ 0x01, 0x15, 0x87, 0x0e, 0xf3, 0x67)
+
+#define BEAGLEBONEAI64_SPL_IMAGE_GUID \
+ EFI_GUID(0x83447222, 0x1e26, 0x40cd, 0xa3, 0x95, \
+ 0xb7, 0xde, 0x09, 0x57, 0xe8, 0x75)
+
+#define BEAGLEBONEAI64_UBOOT_IMAGE_GUID \
+ EFI_GUID(0x4249ff77, 0xc17d, 0x4eb7, 0xa1, 0xdb, \
+ 0x45, 0xaa, 0x98, 0x87, 0xd4, 0x9e)
+
+#define BEAGLEBONEAI64_SYSFW_IMAGE_GUID \
+ EFI_GUID(0xdfc9c683, 0x49b7, 0x46bd, 0xb3, 0xc1, \
+ 0x3a, 0x3b, 0x2f, 0xdb, 0x13, 0x5b)
+
+/* Now for the remaining common defines */
+#include <configs/ti_armv7_common.h>
+
+#endif /* __CONFIG_BEAGLEBONEAI64_H */
diff --git a/include/configs/beagleplay.h b/include/configs/beagleplay.h
new file mode 100644
index 0000000..4baeab6
--- /dev/null
+++ b/include/configs/beagleplay.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Configuration header file for BeaglePlay
+ *
+ * https://beagleplay.org/
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef __CONFIG_BEAGLEPLAY_H
+#define __CONFIG_BEAGLEPLAY_H
+
+/**
+ * define BEAGLEPLAY_TIBOOT3_IMAGE_GUID - firmware GUID for BeaglePlay
+ * tiboot3.bin
+ * define BEAGLEPLAY_SPL_IMAGE_GUID - firmware GUID for BeaglePlay SPL
+ * define BEAGLEPLAY_UBOOT_IMAGE_GUID - firmware GUID for BeaglePlay UBOOT
+ *
+ * These GUIDs are used in capsules updates to identify the corresponding
+ * firmware object.
+ *
+ * Board developers using this as a starting reference should
+ * define their own GUIDs to ensure that firmware repositories (like
+ * LVFS) do not confuse them.
+ */
+#define BEAGLEPLAY_TIBOOT3_IMAGE_GUID \
+ EFI_GUID(0x0e225a09, 0xf720, 0x4d57, 0x91, 0x20, \
+ 0xe2, 0x8f, 0x73, 0x7f, 0x5a, 0x5e)
+
+#define BEAGLEPLAY_SPL_IMAGE_GUID \
+ EFI_GUID(0xb2e7cc49, 0x1a5a, 0x4036, 0xae, 0x01, \
+ 0x33, 0x87, 0xc3, 0xbe, 0xf6, 0x57)
+
+#define BEAGLEPLAY_UBOOT_IMAGE_GUID \
+ EFI_GUID(0x92c92b11, 0xa7ee, 0x486f, 0xaa, 0xa2, \
+ 0x71, 0x3d, 0x84, 0x42, 0x5b, 0x0e)
+
+/* Now for the remaining common defines */
+#include <configs/ti_armv7_common.h>
+
+#endif /* __CONFIG_BEAGLEPLAY_H */
diff --git a/include/configs/clearfog.h b/include/configs/clearfog.h
index 062d3d8..7c7ada1 100644
--- a/include/configs/clearfog.h
+++ b/include/configs/clearfog.h
@@ -26,8 +26,6 @@
* image and environment
*/
-#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-
/* Keep device tree and initrd in lower memory so the kernel can access them */
#define RELOCATION_LIMITS_ENV_SETTINGS \
"fdt_high=0x10000000\0" \
diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h
index 556705f..cd50ffe 100644
--- a/include/configs/cobra5272.h
+++ b/include/configs/cobra5272.h
@@ -184,5 +184,4 @@
#define CFG_SYS_PBDAT 0x0000 /* PortB value reg. */
#define CFG_SYS_PDCNT 0x00000000 /* PortD control reg. */
-
#endif /* _CONFIG_COBRA5272_H */
diff --git a/include/configs/controlcenterdc.h b/include/configs/controlcenterdc.h
index 0e922b9..1ba63b2 100644
--- a/include/configs/controlcenterdc.h
+++ b/include/configs/controlcenterdc.h
@@ -15,8 +15,6 @@
/* Environment in SPI NOR flash */
-#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-
/*
* Environment Configuration
*/
diff --git a/include/configs/db-88f6720.h b/include/configs/db-88f6720.h
index 54de2d0..cf00217 100644
--- a/include/configs/db-88f6720.h
+++ b/include/configs/db-88f6720.h
@@ -23,8 +23,6 @@
/* Environment in SPI NOR flash */
-#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
diff --git a/include/configs/db-88f6820-amc.h b/include/configs/db-88f6820-amc.h
index c4ae397..b174b0d 100644
--- a/include/configs/db-88f6820-amc.h
+++ b/include/configs/db-88f6820-amc.h
@@ -12,8 +12,6 @@
/* Environment in SPI NOR flash */
-#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-
/* NAND */
/* Keep device tree and initrd in lower memory so the kernel can access them */
diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h
index 2cbe4eb..4ac1f3c 100644
--- a/include/configs/db-88f6820-gp.h
+++ b/include/configs/db-88f6820-gp.h
@@ -15,8 +15,6 @@
/* Environment in SPI NOR flash */
-#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-
/* Keep device tree and initrd in lower memory so the kernel can access them */
#define CFG_EXTRA_ENV_SETTINGS \
"fdt_high=0x10000000\0" \
diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h
index 5c6d7fa..67e62d6 100644
--- a/include/configs/db-mv784mp-gp.h
+++ b/include/configs/db-mv784mp-gp.h
@@ -19,8 +19,6 @@
/* Environment in SPI NOR flash */
-#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-
/* NAND */
/*
diff --git a/include/configs/display5.h b/include/configs/display5.h
index 3b96fff..2005a25 100644
--- a/include/configs/display5.h
+++ b/include/configs/display5.h
@@ -119,7 +119,6 @@
"run tftp_mmc_rootfs;" \
"run tftp_mmc_rootfs_bkp;" \
-
#define TFTP_UPDATE_RECOVERY_SWU_KERNEL \
"tftp_sf_fitImg_SWU=" \
"if tftp ${loadaddr} ${kernel_file}; then " \
diff --git a/include/configs/ds116.h b/include/configs/ds116.h
index 0883ec4..c232659 100644
--- a/include/configs/ds116.h
+++ b/include/configs/ds116.h
@@ -7,8 +7,6 @@
#ifndef _CONFIG_DS116_H
#define _CONFIG_DS116_H
-#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-
/* Keep device tree and initrd in lower memory so the kernel can access them */
#define RELOCATION_LIMITS_ENV_SETTINGS \
"fdt_high=0x10000000\0" \
diff --git a/include/configs/ds414.h b/include/configs/ds414.h
index 9446acb..6fbcec0 100644
--- a/include/configs/ds414.h
+++ b/include/configs/ds414.h
@@ -53,8 +53,6 @@
"tftpboot ${loadaddr} u-boot-with-spl.kwb; " \
"sf update ${loadaddr} 0x0 0xd0000\0"
-
/* increase autoneg timeout, my NIC sucks */
-#define PHY_ANEG_TIMEOUT 16000
#endif /* _CONFIG_SYNOLOGY_DS414_H */
diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h
index e2c9d9c..26e4ade 100644
--- a/include/configs/eb_cpu5282.h
+++ b/include/configs/eb_cpu5282.h
@@ -138,6 +138,5 @@
#define CFG_SYS_DDRUA 0x05
#define CFG_SYS_PJPAR 0xFF
-
#endif /* _CONFIG_M5282EVB_H */
/*---------------------------------------------------------------------*/
diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h
index 182369d..807c696 100644
--- a/include/configs/ethernut5.h
+++ b/include/configs/ethernut5.h
@@ -32,7 +32,6 @@
/* 512kB on-chip NOR flash */
# define CFG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */
-
/* bootstrap + u-boot + env + linux in dataflash on CS0 */
/* NAND flash */
diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
index 32960fb..07b3670 100644
--- a/include/configs/ge_bx50v3.h
+++ b/include/configs/ge_bx50v3.h
@@ -88,7 +88,6 @@
"run doboot; " \
"run failbootcmd\0" \
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
diff --git a/include/configs/helios4.h b/include/configs/helios4.h
index 7d81d1c..a3b6335 100644
--- a/include/configs/helios4.h
+++ b/include/configs/helios4.h
@@ -26,8 +26,6 @@
* image and environment
*/
-#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-
/* Keep device tree and initrd in lower memory so the kernel can access them */
#define RELOCATION_LIMITS_ENV_SETTINGS \
"fdt_high=0x10000000\0" \
diff --git a/include/configs/hmibsc.h b/include/configs/hmibsc.h
index 27404c8..950ec8b 100644
--- a/include/configs/hmibsc.h
+++ b/include/configs/hmibsc.h
@@ -9,7 +9,6 @@
#define __CONFIGS_HMIBSC_H
/* PHY needs a longer aneg time */
-#define PHY_ANEG_TIMEOUT 8000
#define CFG_ENV_FLAGS_LIST_STATIC "BOOT_A_LEFT:dw,BOOT_B_LEFT:dw,BOOT_ORDER:sw"
diff --git a/include/configs/ideapad-yoga-11.h b/include/configs/ideapad-yoga-11.h
new file mode 100644
index 0000000..12c7649
--- /dev/null
+++ b/include/configs/ideapad-yoga-11.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "tegra30-common.h"
+
+/* High-level configuration options */
+#define CFG_TEGRA_BOARD_STRING "Lenovo Ideapad Yoga 11"
+
+#define IDEAPAD_FLASH_UBOOT \
+ "flash_uboot=sf probe 0:1;" \
+ "echo Dumping current SPI flash content ...;" \
+ "sf read ${kernel_addr_r} 0x0 ${spi_size};" \
+ "if fatwrite mmc 1:1 ${kernel_addr_r} spi-flash-backup.bin ${spi_size};" \
+ "then echo SPI flash content was successfully written into spi-flash-backup.bin;" \
+ "echo Reading SPI flash binary;" \
+ "if load mmc 1:1 ${kernel_addr_r} repart-block.bin;" \
+ "then echo Writing bootloader into SPI flash;" \
+ "sf probe 0:1;" \
+ "sf update ${kernel_addr_r} 0x0 ${spi_size};" \
+ "echo Bootloader SUCCESSFULLY written into SPI flash;" \
+ "pause 'Press ANY key to reboot...'; reset;" \
+ "else echo Preparing RAM;" \
+ "mw ${kernel_addr_r} 0 ${boot_block_size_r};" \
+ "mw ${ramdisk_addr_r} 0 ${boot_block_size_r};" \
+ "echo Reading BCT;" \
+ "sf read ${kernel_addr_r} 0x0 ${boot_block_size_r};" \
+ "echo Reading bootloader;" \
+ "if load mmc 1:1 ${ramdisk_addr_r} ${bootloader_file};" \
+ "then echo Calculating bootloader size;" \
+ "size mmc 1:1 ${bootloader_file};" \
+ "ebtupdate ${kernel_addr_r} ${ramdisk_addr_r} ${filesize};" \
+ "echo Writing bootloader into SPI flash;" \
+ "sf probe 0:1;" \
+ "sf update ${kernel_addr_r} 0x0 ${boot_block_size_r};" \
+ "sf update ${ramdisk_addr_r} ${boot_block_size_r} ${boot_block_size_r};" \
+ "echo Bootloader written SUCCESSFULLY;" \
+ "pause 'Press ANY key to reboot...'; reset;" \
+ "else echo Reading bootloader failed;" \
+ "pause 'Press ANY key to reboot...'; reset; fi;" \
+ "fi;" \
+ "else echo SPI flash backup FAILED! Aborting ...;" \
+ "pause 'Press ANY key to reboot...'; reset; fi\0"
+
+#define IDEAPAD_BOOTMENU \
+ IDEAPAD_FLASH_UBOOT \
+ "bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu\0" \
+ "bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu\0" \
+ "bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu\0" \
+ "bootmenu_3=update bootloader=run flash_uboot\0" \
+ "bootmenu_4=reboot RCM=enterrcm\0" \
+ "bootmenu_5=reboot=reset\0" \
+ "bootmenu_6=power off=poweroff\0" \
+ "bootmenu_delay=-1\0"
+
+#define BOARD_EXTRA_ENV_SETTINGS \
+ "spi_size=0x400000\0" \
+ "boot_block_size_r=0x200000\0" \
+ "boot_block_size=0x1000\0" \
+ "bootloader_file=u-boot-dtb-tegra.bin\0" \
+ "button_cmd_0_name=Volume Down\0" \
+ "button_cmd_0=bootmenu\0" \
+ "button_cmd_1_name=Lid sensor\0" \
+ "button_cmd_1=poweroff\0" \
+ "partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" \
+ IDEAPAD_BOOTMENU
+
+/* Board-specific serial config */
+#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h
index 85c0544..66004a6 100644
--- a/include/configs/imx6_logic.h
+++ b/include/configs/imx6_logic.h
@@ -17,7 +17,6 @@
#define CFG_SYS_FSL_ESDHC_ADDR 0
#define CFG_SYS_FSL_USDHC_NUM 2
-
/* Ethernet Configs */
#define CFG_FEC_MXC_PHYADDR 0
diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h
index 106fbdb..131f182 100644
--- a/include/configs/imx7-cm.h
+++ b/include/configs/imx7-cm.h
@@ -77,7 +77,6 @@
#define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
#define CFG_SYS_FSL_USDHC_NUM 2
-
/* USB Configs */
#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h
index 09d87cf..6442e3d 100644
--- a/include/configs/imx8mm-cl-iot-gate.h
+++ b/include/configs/imx8mm-cl-iot-gate.h
@@ -126,7 +126,6 @@
#define CFG_SYS_INIT_RAM_ADDR 0x40000000
#define CFG_SYS_INIT_RAM_SIZE 0x80000
-
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
@@ -136,7 +135,7 @@
#define CFG_SYS_FSL_USDHC_NUM 2
#define CFG_SYS_FSL_ESDHC_ADDR 0
-#define CFG_FEC_MXC_PHYADDR 0
+#define CFG_FEC_MXC_PHYADDR -1 /* Auto search of PHY on MII */
/* USB Configs */
#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
diff --git a/include/configs/imx8mm-mx8menlo.h b/include/configs/imx8mm-mx8menlo.h
index a86bd76..7058d63 100644
--- a/include/configs/imx8mm-mx8menlo.h
+++ b/include/configs/imx8mm-mx8menlo.h
@@ -8,6 +8,8 @@
#include <configs/verdin-imx8mm.h>
+/* PHY needs a longer autoneg timeout */
+
/* Custom initial environment variables */
#undef CFG_EXTRA_ENV_SETTINGS
#define CFG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h
index b777fe6..9a5e5bd 100644
--- a/include/configs/imx8mm_data_modul_edm_sbc.h
+++ b/include/configs/imx8mm_data_modul_edm_sbc.h
@@ -28,7 +28,6 @@
#define CFG_MXC_UART_BASE UART3_BASE_ADDR
/* PHY needs a longer autonegotiation timeout after reset */
-#define PHY_ANEG_TIMEOUT 20000
/* USDHC */
#define CFG_SYS_FSL_USDHC_NUM 2
diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h
index d5642b9..9dd63fc 100644
--- a/include/configs/imx8mm_evk.h
+++ b/include/configs/imx8mm_evk.h
@@ -56,7 +56,6 @@
#define CFG_SYS_INIT_RAM_ADDR 0x40000000
#define CFG_SYS_INIT_RAM_SIZE 0x200000
-
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h
index 046d568..6681661 100644
--- a/include/configs/imx8mm_venice.h
+++ b/include/configs/imx8mm_venice.h
@@ -23,6 +23,7 @@
func(MMC, mmc, 2) \
func(USB, usb, 0) \
func(USB, usb, 1) \
+ func(NVME, nvme, 0) \
func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
#define CFG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h
index b759b83..ca02e26 100644
--- a/include/configs/imx8mn_evk.h
+++ b/include/configs/imx8mn_evk.h
@@ -48,7 +48,6 @@
#define CFG_SYS_INIT_RAM_ADDR 0x40000000
#define CFG_SYS_INIT_RAM_SIZE 0x200000
-
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
diff --git a/include/configs/imx8mp_beacon.h b/include/configs/imx8mp_beacon.h
index ee0fd07..b36dae7 100644
--- a/include/configs/imx8mp_beacon.h
+++ b/include/configs/imx8mp_beacon.h
@@ -10,10 +10,6 @@
#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
-#if defined(CONFIG_CMD_NET)
-#define PHY_ANEG_TIMEOUT 20000
-#endif
-
/* Link Definitions */
#define CFG_SYS_INIT_RAM_ADDR 0x40000000
diff --git a/include/configs/imx8mp_data_modul_edm_sbc.h b/include/configs/imx8mp_data_modul_edm_sbc.h
index 8d79540..f953847 100644
--- a/include/configs/imx8mp_data_modul_edm_sbc.h
+++ b/include/configs/imx8mp_data_modul_edm_sbc.h
@@ -21,7 +21,6 @@
#define CFG_MXC_UART_BASE UART3_BASE_ADDR
/* PHY needs a longer autonegotiation timeout after reset */
-#define PHY_ANEG_TIMEOUT 20000
#define FEC_QUIRK_ENET_MAC
#define CFG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/imx8mp_debix_model_a.h b/include/configs/imx8mp_debix_model_a.h
index e82e8b1..14b9110 100644
--- a/include/configs/imx8mp_debix_model_a.h
+++ b/include/configs/imx8mp_debix_model_a.h
@@ -16,8 +16,6 @@
#if defined(CONFIG_CMD_NET)
#define CFG_FEC_MXC_PHYADDR 1
-#define PHY_ANEG_TIMEOUT 20000
-
#endif
#define BOOT_TARGET_DEVICES(func) \
diff --git a/include/configs/imx8mp_dhcom_pdk2.h b/include/configs/imx8mp_dhcom_pdk2.h
index ea32fe1..c848fce 100644
--- a/include/configs/imx8mp_dhcom_pdk2.h
+++ b/include/configs/imx8mp_dhcom_pdk2.h
@@ -21,7 +21,6 @@
#define CFG_MXC_UART_BASE UART1_BASE_ADDR
/* PHY needs a longer autonegotiation timeout after reset */
-#define PHY_ANEG_TIMEOUT 20000
#define FEC_QUIRK_ENET_MAC
/* USDHC */
diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h
index 1759318..741ee39 100644
--- a/include/configs/imx8mp_evk.h
+++ b/include/configs/imx8mp_evk.h
@@ -15,8 +15,6 @@
#if defined(CONFIG_CMD_NET)
#define CFG_FEC_MXC_PHYADDR 1
-#define PHY_ANEG_TIMEOUT 20000
-
#endif
#define BOOT_TARGET_DEVICES(func) \
@@ -45,7 +43,6 @@
#define CFG_SYS_INIT_RAM_ADDR 0x40000000
#define CFG_SYS_INIT_RAM_SIZE 0x80000
-
/* Totally 6GB DDR */
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
diff --git a/include/configs/imx8mp_icore_mx8mp.h b/include/configs/imx8mp_icore_mx8mp.h
index bbbd917..0a861a1 100644
--- a/include/configs/imx8mp_icore_mx8mp.h
+++ b/include/configs/imx8mp_icore_mx8mp.h
@@ -18,8 +18,6 @@
#define DWC_NET_PHYADDR 1
-#define PHY_ANEG_TIMEOUT 20000
-
#endif
#define BOOT_TARGET_DEVICES(func) \
diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h
index e577f60..b82e35f 100644
--- a/include/configs/imx8mp_rsb3720.h
+++ b/include/configs/imx8mp_rsb3720.h
@@ -35,8 +35,6 @@
#if defined(CONFIG_CMD_NET)
#define CFG_FEC_MXC_PHYADDR 4
-#define PHY_ANEG_TIMEOUT 20000
-
#endif
#if IS_ENABLED(CONFIG_CMD_MMC)
@@ -128,7 +126,6 @@
#define CFG_SYS_INIT_RAM_ADDR 0x40000000
#define CFG_SYS_INIT_RAM_SIZE 0x80000
-
/* Totally 6GB or 4G DDR */
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
diff --git a/include/configs/imx8mp_venice.h b/include/configs/imx8mp_venice.h
index 47413ec..8114430 100644
--- a/include/configs/imx8mp_venice.h
+++ b/include/configs/imx8mp_venice.h
@@ -17,6 +17,7 @@
func(MMC, mmc, 1) \
func(MMC, mmc, 2) \
func(USB, usb, 0) \
+ func(NVME, nvme, 0) \
func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
#define CFG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/imx8mq_cm.h b/include/configs/imx8mq_cm.h
index 7cf482d..2bbd6b1 100644
--- a/include/configs/imx8mq_cm.h
+++ b/include/configs/imx8mq_cm.h
@@ -48,7 +48,6 @@
#define CFG_SYS_INIT_RAM_ADDR 0x40000000
#define CFG_SYS_INIT_RAM_SIZE 0x80000
-
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x40000000 /* 1 GB DDR */
diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h
index d2e1649..9eefc31 100644
--- a/include/configs/imx8mq_evk.h
+++ b/include/configs/imx8mq_evk.h
@@ -53,7 +53,6 @@
#define CFG_SYS_INIT_RAM_ADDR 0x40000000
#define CFG_SYS_INIT_RAM_SIZE 0x80000
-
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */
diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h
index b66fc18..cd73a72 100644
--- a/include/configs/imx8mq_phanbell.h
+++ b/include/configs/imx8mq_phanbell.h
@@ -86,7 +86,6 @@
#define CFG_SYS_INIT_RAM_ADDR 0x40000000
#define CFG_SYS_INIT_RAM_SIZE 0x80000
-
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */
diff --git a/include/configs/imx8mq_reform2.h b/include/configs/imx8mq_reform2.h
index 3148e86..7fa441a 100644
--- a/include/configs/imx8mq_reform2.h
+++ b/include/configs/imx8mq_reform2.h
@@ -54,7 +54,6 @@
#define CFG_SYS_INIT_RAM_ADDR 0x40000000
#define CFG_SYS_INIT_RAM_SIZE 0x80000
-
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x100000000 /* 4 GiB DDR */
diff --git a/include/configs/imx8ulp_evk.h b/include/configs/imx8ulp_evk.h
index d77510e..aa9da19 100644
--- a/include/configs/imx8ulp_evk.h
+++ b/include/configs/imx8ulp_evk.h
@@ -14,13 +14,10 @@
#ifdef CONFIG_SPL_BUILD
#define CFG_MALLOC_F_ADDR 0x22040000
-
#endif
/* ENET Config */
#if defined(CONFIG_FEC_MXC)
-#define PHY_ANEG_TIMEOUT 20000
-
#define CFG_FEC_MXC_PHYADDR 1
#endif
@@ -53,7 +50,6 @@
#define CFG_SYS_INIT_RAM_ADDR 0x80000000
#define CFG_SYS_INIT_RAM_SIZE 0x80000
-
#define CFG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h
index 2705587..ce6567e 100644
--- a/include/configs/imx93_evk.h
+++ b/include/configs/imx93_evk.h
@@ -134,8 +134,4 @@
/* Using ULP WDOG for reset */
#define WDOG_BASE_ADDR WDG3_BASE_ADDR
-#if defined(CONFIG_CMD_NET)
-#define PHY_ANEG_TIMEOUT 20000
-#endif
-
#endif
diff --git a/include/configs/imx93_var_som.h b/include/configs/imx93_var_som.h
index 18a8ee5..9dc10ae 100644
--- a/include/configs/imx93_var_som.h
+++ b/include/configs/imx93_var_som.h
@@ -41,8 +41,4 @@
/* Using ULP WDOG for reset */
#define WDOG_BASE_ADDR WDG3_BASE_ADDR
-#if defined(CONFIG_CMD_NET)
-#define PHY_ANEG_TIMEOUT 20000
-#endif
-
#endif
diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h
index c26438c..bdf12ee 100644
--- a/include/configs/j721e_evm.h
+++ b/include/configs/j721e_evm.h
@@ -22,8 +22,36 @@
#define CFG_SYS_UBOOT_BASE 0x50080000
#endif
+/**
+ * define J721E_SK_TIBOOT3_IMAGE_GUID - firmware GUID for J721e sk tiboot3.bin
+ * define J721E_SK_SPL_IMAGE_GUID - firmware GUID for J721e sk SPL
+ * define J721E_SK_UBOOT_IMAGE_GUID - firmware GUID for J721e sk UBOOT
+ * define J721E_SK_SYSFW_IMAGE_GUID - firmware GUID for J721e sk SYSFW
+ *
+ * These GUIDs are used in capsules updates to identify the corresponding
+ * firmware object.
+ *
+ * Board developers using this as a starting reference should
+ * define their own GUIDs to ensure that firmware repositories (like
+ * LVFS) do not confuse them.
+ */
+#define J721E_SK_TIBOOT3_IMAGE_GUID \
+ EFI_GUID(0xe672b518, 0x7cd7, 0x4014, 0xbd, 0x8d, \
+ 0x40, 0x72, 0x4d, 0x0a, 0xd4, 0xdc)
+
+#define J721E_SK_SPL_IMAGE_GUID \
+ EFI_GUID(0x86f710ad, 0x10cf, 0x46ea, 0xac, 0x67, \
+ 0x85, 0x6a, 0xe0, 0x6e, 0xfa, 0xd2)
+
+#define J721E_SK_UBOOT_IMAGE_GUID \
+ EFI_GUID(0x81b58fb0, 0x3b00, 0x4add, 0xa2, 0x0a, \
+ 0xc1, 0x85, 0xbb, 0xac, 0xa1, 0xed)
+
+#define J721E_SK_SYSFW_IMAGE_GUID \
+ EFI_GUID(0x6fd10680, 0x361b, 0x431f, 0x80, 0xaa, \
+ 0x89, 0x94, 0x55, 0x81, 0x9e, 0x11)
+
/* Now for the remaining common defines */
#include <configs/ti_armv7_common.h>
-
#endif /* __CONFIG_J721E_EVM_H */
diff --git a/include/configs/j722s_evm.h b/include/configs/j722s_evm.h
new file mode 100644
index 0000000..10f2e2d
--- /dev/null
+++ b/include/configs/j722s_evm.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration header file for K3 J722S SoC family
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef __CONFIG_J722S_EVM_H
+#define __CONFIG_J722S_EVM_H
+
+/* Now for the remaining common defines */
+#include <configs/ti_armv7_common.h>
+
+#endif /* __CONFIG_J722S_EVM_H */
diff --git a/include/configs/j784s4_evm.h b/include/configs/j784s4_evm.h
index 4a2ccdc..53eb2bf 100644
--- a/include/configs/j784s4_evm.h
+++ b/include/configs/j784s4_evm.h
@@ -9,6 +9,30 @@
#ifndef __CONFIG_J784S4_EVM_H
#define __CONFIG_J784S4_EVM_H
+/**
+ * define AM69_SK_TIBOOT3_IMAGE_GUID - firmware GUID for AM69 SK tiboot3.bin
+ * define AM69_SK_SPL_IMAGE_GUID - firmware GUID for AM69 SK SPL
+ * define AM69_SK_UBOOT_IMAGE_GUID - firmware GUID for AM69 SK UBOOT
+ *
+ * These GUIDs are used in capsules updates to identify the corresponding
+ * firmware object.
+ *
+ * Board developers using this as a starting reference should
+ * define their own GUIDs to ensure that firmware repositories (like
+ * LVFS) do not confuse them.
+ */
+#define AM69_SK_TIBOOT3_IMAGE_GUID \
+ EFI_GUID(0xadf49ec5, 0x61bb, 0x4dbe, 0x8b, 0x8d, \
+ 0x39, 0xdf, 0x4d, 0x7e, 0xbf, 0x46)
+
+#define AM69_SK_SPL_IMAGE_GUID \
+ EFI_GUID(0x787f0059, 0x63a1, 0x461c, 0xa1, 0x8e, \
+ 0x9d, 0x83, 0x83, 0x45, 0xfe, 0x8e)
+
+#define AM69_SK_UBOOT_IMAGE_GUID \
+ EFI_GUID(0x9300505d, 0x6ec5, 0x4ff8, 0x99, 0xe4, \
+ 0x54, 0x59, 0xa0, 0x4b, 0xe6, 0x17)
+
/* Now for the remaining common defines */
#include <configs/ti_armv7_common.h>
diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h
index 2f25d39..ce7bd66 100644
--- a/include/configs/k2g_evm.h
+++ b/include/configs/k2g_evm.h
@@ -11,7 +11,6 @@
/* Network */
#define CFG_KSNET_CPSW_NUM_PORTS 2
-#define PHY_ANEG_TIMEOUT 10000 /* PHY needs longer aneg time */
#include <configs/ti_armv7_keystone2.h>
diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h
index 5cf6b5a..3dda7b6 100644
--- a/include/configs/kontron_pitx_imx8m.h
+++ b/include/configs/kontron_pitx_imx8m.h
@@ -18,7 +18,6 @@
#define CFG_MALLOC_F_ADDR 0x182000
/* For RAW image gives a error info not panic */
-
#define CFG_POWER_PFUZE100_I2C_ADDR 0x08
#endif
@@ -26,8 +25,6 @@
#if defined(CONFIG_CMD_NET)
#define CFG_FEC_MXC_PHYADDR 0
-#define PHY_ANEG_TIMEOUT 20000
-
#endif
#define ENV_MEM_LAYOUT_SETTINGS \
@@ -58,7 +55,6 @@
ENV_MEM_LAYOUT_SETTINGS \
BOOTENV
-
#define CFG_SYS_INIT_RAM_ADDR 0x40000000
#define CFG_SYS_INIT_RAM_SIZE 0x80000
diff --git a/include/configs/lion_rk3368.h b/include/configs/lion_rk3368.h
index c5b78f9..0d29e1d 100644
--- a/include/configs/lion_rk3368.h
+++ b/include/configs/lion_rk3368.h
@@ -12,6 +12,5 @@
#define DTB_LOAD_ADDR 0x5600000
#define INITRD_LOAD_ADDR 0x5bf0000
/* PHY needs longer aneg time at 1G */
-#define PHY_ANEG_TIMEOUT 8000
#endif
diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
index 35e8ff0..3c4f8b7 100644
--- a/include/configs/ls1012aqds.h
+++ b/include/configs/ls1012aqds.h
@@ -48,7 +48,6 @@
*/
#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
-
/* Voltage monitor on channel 2*/
#define I2C_VOL_MONITOR_ADDR 0x40
#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index ac2319c..e500a7d 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -159,7 +159,6 @@
" && esbc_validate ${kernelheader_addr_r};" \
"bootm $load_addr#$board\0"
-
#ifdef CONFIG_TFABOOT
#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
"env exists secureboot && esbc_halt;"
diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h
index 720a95d..34085ee 100644
--- a/include/configs/ls1088a_common.h
+++ b/include/configs/ls1088a_common.h
@@ -42,7 +42,6 @@
/* I2C */
-
/* Serial Port */
#define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
@@ -84,11 +83,9 @@
#define QIXIS_BASE_PHYS 0x20000000
#define QIXIS_BASE_PHYS_EARLY 0xC000000
-
#define CFG_SYS_NAND_BASE 0x530000000ULL
#define CFG_SYS_NAND_BASE_PHYS 0x30000000
-
/* MC firmware */
/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
#define CFG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h
index 084ee06..36e8422 100644
--- a/include/configs/ls1088aqds.h
+++ b/include/configs/ls1088aqds.h
@@ -16,7 +16,6 @@
#define SPD_EEPROM_ADDRESS 0x51
-
/*
* IFC Definitions
*/
diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h
index a174914..8be5feb 100644
--- a/include/configs/ls1088ardb.h
+++ b/include/configs/ls1088ardb.h
@@ -17,7 +17,6 @@
#define SPD_EEPROM_ADDRESS 0x51
-
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CFG_SYS_NOR0_CSPR_EXT (0x0)
#define CFG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
index 6f46ca7..4c1b4bf 100644
--- a/include/configs/lx2160a_common.h
+++ b/include/configs/lx2160a_common.h
@@ -37,7 +37,6 @@
* will be udpated later when get_bus_freq(0) is available.
*/
-
/* Serial Port */
#define CFG_PL011_CLOCK (get_bus_freq(0) / 4)
#define CFG_SYS_SERIAL0 0x21c0000
diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h
index 1ecbba1..9cf46b2 100644
--- a/include/configs/m53menlo.h
+++ b/include/configs/m53menlo.h
@@ -119,7 +119,7 @@
"addargs=run addcons addmisc addmtd\0" \
"mmcload=" \
"mmc rescan || reset ; load mmc ${mmcdev}:${mmcpart} " \
- "${kernel_addr_r} ${bootfile} || reset\0" \
+ "${kernel_addr_r} boot/${bootfile} || reset\0" \
"miscargs=nohlt panic=1\0" \
"mmcargs=setenv bootargs root=/dev/mmcblk0p${mmcpart} rw " \
"rootwait\0" \
diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h
index 413597e..4c2b538 100644
--- a/include/configs/maxbcm.h
+++ b/include/configs/maxbcm.h
@@ -25,8 +25,6 @@
/* Environment in SPI NOR flash */
-#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
diff --git a/include/configs/meson64.h b/include/configs/meson64.h
index 65fa5f3..ccb8ea2 100644
--- a/include/configs/meson64.h
+++ b/include/configs/meson64.h
@@ -144,5 +144,4 @@
BOOTENV
#endif
-
#endif /* __MESON64_CONFIG_H */
diff --git a/include/configs/msc_sm2s_imx8mp.h b/include/configs/msc_sm2s_imx8mp.h
index 3c7d96c..ea5c93e 100644
--- a/include/configs/msc_sm2s_imx8mp.h
+++ b/include/configs/msc_sm2s_imx8mp.h
@@ -18,7 +18,6 @@
#if defined(CONFIG_CMD_NET)
#define CFG_FEC_MXC_PHYADDR 1
-#define PHY_ANEG_TIMEOUT 20000
#endif
#ifndef CONFIG_SPL_BUILD
@@ -36,10 +35,10 @@
"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"image=Image\0" \
"console=ttymxc1,115200\0" \
- "fdt_addr_r=0x43000000\0" \
+ "fdt_addr_r=0x48600000\0" \
"boot_fdt=try\0" \
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
- "initrd_addr=0x43800000\0" \
+ "initrd_addr=0x48680000\0" \
"bootm_size=0x10000000\0" \
"mmcpart=1\0" \
"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
diff --git a/include/configs/mt8183.h b/include/configs/mt8183.h
index 1f97382..7c31e21 100644
--- a/include/configs/mt8183.h
+++ b/include/configs/mt8183.h
@@ -11,7 +11,6 @@
#include <linux/sizes.h>
-
#define CFG_SYS_NS16550_COM1 0x11005200
#define CFG_SYS_NS16550_CLK 26000000
diff --git a/include/configs/mt8516.h b/include/configs/mt8516.h
index 73776e3..27c3718 100644
--- a/include/configs/mt8516.h
+++ b/include/configs/mt8516.h
@@ -11,7 +11,6 @@
#include <linux/sizes.h>
-
#define CFG_SYS_NS16550_COM1 0x11005000
#define CFG_SYS_NS16550_CLK 26000000
diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h
index 239a097..6fedbe9 100644
--- a/include/configs/mvebu_armada-8k.h
+++ b/include/configs/mvebu_armada-8k.h
@@ -30,7 +30,7 @@
/*
* PCI configuration
*/
-
+#ifdef CONFIG_DISTRO_DEFAULTS
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 1) \
func(MMC, mmc, 0) \
@@ -40,6 +40,9 @@
func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
+#else
+#define BOOTENV
+#endif
#define CFG_EXTRA_ENV_SETTINGS \
"scriptaddr=0x6d00000\0" \
diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h
index e995776..dccfdc3 100644
--- a/include/configs/mx53cx9020.h
+++ b/include/configs/mx53cx9020.h
@@ -21,7 +21,6 @@
/* bootz: zImage/initrd.img support */
-
/* USB Configs */
#define CFG_MXC_USB_PORT 1
#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h
index 2c3cd32..910140a 100644
--- a/include/configs/mx6ullevk.h
+++ b/include/configs/mx6ullevk.h
@@ -7,7 +7,6 @@
#ifndef __MX6ULLEVK_CONFIG_H
#define __MX6ULLEVK_CONFIG_H
-
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
#include <linux/stringify.h>
diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h
index 5f4cd93..d1c1202 100644
--- a/include/configs/mx7ulp_evk.h
+++ b/include/configs/mx7ulp_evk.h
@@ -11,7 +11,6 @@
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
-
/* Using ULP WDOG for reset */
#define WDOG_BASE_ADDR WDG1_RBASE
diff --git a/include/configs/n2350.h b/include/configs/n2350.h
index d8a9814..f98b9f8 100644
--- a/include/configs/n2350.h
+++ b/include/configs/n2350.h
@@ -7,8 +7,6 @@
#ifndef _CONFIG_N2350_H
#define _CONFIG_N2350_H
-#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-
/* Keep device tree and initrd in lower memory so the kernel can access them */
#define RELOCATION_LIMITS_ENV_SETTINGS \
"fdt_high=0x10000000\0" \
diff --git a/include/configs/nova-rk3588s.h b/include/configs/nova-rk3588s.h
new file mode 100644
index 0000000..0edd1ce
--- /dev/null
+++ b/include/configs/nova-rk3588s.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2022 Collabora Ltd.
+ */
+
+#ifndef __NOVA_RK3588S_H
+#define __NOVA_RK3588S_H
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
+
+#include <configs/rk3588_common.h>
+
+#endif /* __NOVA_RK3588S_H */
diff --git a/include/configs/octeon_ebb7304.h b/include/configs/octeon_ebb7304.h
index 5479bde..7d99fd1 100644
--- a/include/configs/octeon_ebb7304.h
+++ b/include/configs/octeon_ebb7304.h
@@ -9,6 +9,4 @@
#include "octeon_common.h"
-#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-
#endif /* __CONFIG_H__ */
diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h
index ce6dc87..dd7cfdb 100644
--- a/include/configs/phycore_imx8mm.h
+++ b/include/configs/phycore_imx8mm.h
@@ -63,7 +63,6 @@
#define CFG_SYS_INIT_RAM_ADDR 0x40000000
#define CFG_SYS_INIT_RAM_SIZE SZ_512K
-
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h
index 206c4d5..47c56b5 100644
--- a/include/configs/phycore_imx8mp.h
+++ b/include/configs/phycore_imx8mp.h
@@ -18,10 +18,11 @@
#define CFG_SYS_INIT_RAM_ADDR 0x40000000
#define CFG_SYS_INIT_RAM_SIZE SZ_512K
-
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
-#define PHYS_SDRAM_SIZE 0x80000000
+#define PHYS_SDRAM_SIZE (SZ_2G + SZ_1G) /* 3GB */
+#define PHYS_SDRAM_2 0x100000000
+#define PHYS_SDRAM_2_SIZE (SZ_4G + SZ_1G) /* 5GB */
#endif /* __PHYCORE_IMX8MP_H */
diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h
index 4caa823..8a22f01 100644
--- a/include/configs/pico-imx6ul.h
+++ b/include/configs/pico-imx6ul.h
@@ -7,7 +7,6 @@
#ifndef __PICO_IMX6UL_CONFIG_H
#define __PICO_IMX6UL_CONFIG_H
-
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
#include "mx6_common.h"
diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h
index be31f8a..422b89a 100644
--- a/include/configs/pico-imx8mq.h
+++ b/include/configs/pico-imx8mq.h
@@ -65,7 +65,6 @@
#define CFG_SYS_INIT_RAM_ADDR 0x40000000
#define CFG_SYS_INIT_RAM_SIZE 0x80000
-
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2 GiB DDR */
diff --git a/include/configs/powkiddy-x55-rk3566.h b/include/configs/powkiddy-x55-rk3566.h
new file mode 100644
index 0000000..4b25c6a
--- /dev/null
+++ b/include/configs/powkiddy-x55-rk3566.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __POWKIDDY_X55_RK3566_H
+#define __POWKIDDY_X55_RK3566_H
+
+#include <configs/rk3568_common.h>
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
+
+#endif
diff --git a/include/configs/qc750.h b/include/configs/qc750.h
new file mode 100644
index 0000000..ce6665d
--- /dev/null
+++ b/include/configs/qc750.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2010,2012
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * (C) Copyright 2023
+ * Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "tegra30-common.h"
+
+/* High-level configuration options */
+#define CFG_TEGRA_BOARD_STRING "Wexler QC750"
+
+#define QC750_FLASH_UBOOT \
+ "flash_uboot=echo Preparing RAM;" \
+ "mw ${kernel_addr_r} 0 ${boot_block_size_r};" \
+ "mw ${ramdisk_addr_r} 0 ${boot_block_size_r};" \
+ "echo Reading BCT;" \
+ "mmc dev 0 1;" \
+ "mmc read ${kernel_addr_r} 0 ${boot_block_size};" \
+ "echo Reading bootloader;" \
+ "if load mmc 1:1 ${ramdisk_addr_r} ${bootloader_file};" \
+ "then echo Calculating bootloader size;" \
+ "size mmc 1:1 ${bootloader_file};" \
+ "ebtupdate ${kernel_addr_r} ${ramdisk_addr_r} ${filesize};" \
+ "echo Writing bootloader to eMMC;" \
+ "mmc dev 0 1;" \
+ "mmc write ${kernel_addr_r} 0 ${boot_block_size};" \
+ "mmc dev 0 2;" \
+ "mmc write ${ramdisk_addr_r} 0 ${boot_block_size};" \
+ "echo Bootloader written successfully;" \
+ "pause 'Press ANY key to reboot device...'; reset;" \
+ "else echo Reading bootloader failed;" \
+ "pause 'Press ANY key to return to bootmenu...'; bootmenu; fi\0"
+
+#define QC750_BOOTMENU \
+ QC750_FLASH_UBOOT \
+ "bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu\0" \
+ "bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu\0" \
+ "bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu\0" \
+ "bootmenu_3=update bootloader=run flash_uboot\0" \
+ "bootmenu_4=reboot RCM=enterrcm\0" \
+ "bootmenu_5=reboot=reset\0" \
+ "bootmenu_6=power off=poweroff\0" \
+ "bootmenu_delay=-1\0"
+
+#define BOARD_EXTRA_ENV_SETTINGS \
+ "boot_block_size_r=0x200000\0" \
+ "boot_block_size=0x1000\0" \
+ "bootloader_file=u-boot-dtb-tegra.bin\0" \
+ "button_cmd_0_name=Volume Down\0" \
+ "button_cmd_0=bootmenu\0" \
+ "partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" \
+ QC750_BOOTMENU
+
+/* Board-specific serial config */
+#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/qcom.h b/include/configs/qcom.h
index e50b3bc..5b5ebbd 100644
--- a/include/configs/qcom.h
+++ b/include/configs/qcom.h
@@ -11,11 +11,4 @@
#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }
-/* Load addressed are calculated during board_late_init(). See arm/mach-snapdragon/board.c */
-#define CFG_EXTRA_ENV_SETTINGS \
- "stdin=serial,button-kbd\0" \
- "stdout=serial,vidconsole\0" \
- "stderr=serial,vidconsole\0" \
- "bootcmd=bootm $prevbl_initrd_start_addr\0"
-
#endif
diff --git a/include/configs/qemu-xtensa.h b/include/configs/qemu-xtensa.h
new file mode 100644
index 0000000..505aa06
--- /dev/null
+++ b/include/configs/qemu-xtensa.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2007-2013 Tensilica, Inc.
+ * Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
+ * Copyright (C) 2024 Jiaxun Yang <jiaxun.yang@flygoat.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/core.h>
+#include <asm/addrspace.h>
+#include <asm/config.h>
+
+#if XCHAL_HAVE_PTP_MMU
+#define CFG_SYS_MEMORY_BASE \
+ (XCHAL_VECBASE_RESET_VADDR - XCHAL_VECBASE_RESET_PADDR)
+#define CFG_SYS_IO_BASE 0xf0000000
+#define CFG_SYS_SDRAM_SIZE 0x80000000 /* xtensa.sysram0 */
+#else
+#define CFG_SYS_MEMORY_BASE 0x60000000
+#define CFG_SYS_SDRAM_SIZE 0x08000000 /* xtensa.sysram0 */
+#endif
+
+#define CFG_SYS_SDRAM_BASE MEMADDR(0x00000000)
+
+#if defined(CFG_MAX_MEM_MAPPED) && \
+ CFG_MAX_MEM_MAPPED < CFG_SYS_SDRAM_SIZE
+#define XTENSA_SYS_TEXT_ADDR \
+ (MEMADDR(CFG_MAX_MEM_MAPPED) - CONFIG_SYS_MONITOR_LEN)
+#else
+#define XTENSA_SYS_TEXT_ADDR \
+ (MEMADDR(CFG_SYS_SDRAM_SIZE) - CONFIG_SYS_MONITOR_LEN)
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h
index 5f4d5ce..3f0831a 100644
--- a/include/configs/rcar-gen3-common.h
+++ b/include/configs/rcar-gen3-common.h
@@ -20,11 +20,7 @@
/* console */
#define CFG_SYS_BAUDRATE_TABLE { 115200, 38400 }
-/* PHY needs a longer autoneg timeout */
-#define PHY_ANEG_TIMEOUT 20000
-
/* MEMORY */
-
#define DRAM_RSV_SIZE 0x08000000
#define CFG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE)
#define CFG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE)
diff --git a/include/configs/rcar-gen4-common.h b/include/configs/rcar-gen4-common.h
index 3465b4d..37a37c0 100644
--- a/include/configs/rcar-gen4-common.h
+++ b/include/configs/rcar-gen4-common.h
@@ -21,7 +21,6 @@
#define CFG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE)
/* PHY needs a longer autoneg timeout */
-#define PHY_ANEG_TIMEOUT 20000
/* Environment setting */
#define CFG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/sei510.h b/include/configs/sei510.h
index ea91a06..0f8070b 100644
--- a/include/configs/sei510.h
+++ b/include/configs/sei510.h
@@ -25,7 +25,6 @@
"name=userdata,size=4820M,uuid=${uuid_gpt_userdata};" \
"name=rootfs,size=-,uuid=" ROOT_UUID
-
#include <configs/meson64_android.h>
#endif /* __CONFIG_H */
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index 6b1d5ca..74b7fe8 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -40,7 +40,6 @@
#define CFG_SYS_NS16550_COM1 0x44e09000
#define CFG_SYS_NS16550_COM4 0x481a6000
-
/* I2C Configuration */
/* Defines for SPL */
diff --git a/include/configs/sige7-rk3588.h b/include/configs/sige7-rk3588.h
new file mode 100644
index 0000000..fd08da5
--- /dev/null
+++ b/include/configs/sige7-rk3588.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2024 ArmSoM Technology Co., Ltd.
+ */
+
+#ifndef __SIGE7_RK3588_H
+#define __SIGE7_RK3588_H
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
+
+#include <configs/rk3588_common.h>
+
+#endif /* __SIGE7_RK3588_H */
diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h
index caff0cf..aa33cf4 100644
--- a/include/configs/socfpga_sr1500.h
+++ b/include/configs/socfpga_sr1500.h
@@ -12,7 +12,6 @@
/* Ethernet on SoC (EMAC) */
/* The PHY is autodetected, so no MII PHY address is needed here */
-#define PHY_ANEG_TIMEOUT 8000
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 64cc17c..006d649 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -48,7 +48,6 @@
/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */
-
/* Hardcoded values, to use instead of SPD */
#define CFG_SYS_DDR_CS0_BNDS 0x0000000f
#define CFG_SYS_DDR_CS0_CONFIG 0x80010102
diff --git a/include/configs/stm32mp15_dh_dhsom.h b/include/configs/stm32mp15_dh_dhsom.h
index de39b19..6fe6e7b 100644
--- a/include/configs/stm32mp15_dh_dhsom.h
+++ b/include/configs/stm32mp15_dh_dhsom.h
@@ -9,7 +9,6 @@
#define __CONFIG_STM32MP15_DH_DHSOM_H__
/* PHY needs a longer autoneg timeout */
-#define PHY_ANEG_TIMEOUT 20000
#ifdef CONFIG_SPL_BUILD
#define CFG_EXTRA_ENV_SETTINGS \
@@ -54,7 +53,6 @@
"update_sf=run dh_update_sd_to_sf\0" \
"usb_pgood_delay=1000\0"
-
#include <configs/stm32mp15_common.h>
#endif
diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h
index af5da09..c8a39e1 100644
--- a/include/configs/stmark2.h
+++ b/include/configs/stmark2.h
@@ -95,7 +95,6 @@
#define CACR_STATUS (CFG_SYS_INIT_RAM_ADDR + \
CFG_SYS_INIT_RAM_SIZE - 12)
-
#define CFG_SYS_I2C_0
#endif /* __STMARK2_CONFIG_H */
diff --git a/include/configs/surface-rt.h b/include/configs/surface-rt.h
new file mode 100644
index 0000000..30f6450
--- /dev/null
+++ b/include/configs/surface-rt.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Copyright (c) 2021, Open Surface RT
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "tegra30-common.h"
+
+/* High-level configuration options */
+#define CFG_TEGRA_BOARD_STRING "Microsoft Surface RT"
+
+#define SURFACE_RT_BOOTMENU \
+ "bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu\0" \
+ "bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu\0" \
+ "bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu\0" \
+ "bootmenu_3=boot from USB=usb reset; usb start; bootflow scan\0" \
+ "bootmenu_4=reboot RCM=enterrcm\0" \
+ "bootmenu_5=reboot=reset\0" \
+ "bootmenu_6=power off=poweroff\0" \
+ "bootmenu_delay=-1\0"
+
+#define BOARD_EXTRA_ENV_SETTINGS \
+ "button_cmd_0_name=Volume Down\0" \
+ "button_cmd_0=bootmenu\0" \
+ "button_cmd_1_name=Hall Sensor\0" \
+ "button_cmd_1=poweroff\0" \
+ "partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" \
+ SURFACE_RT_BOOTMENU
+
+/* Board-specific serial config */
+#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h
index fc74980..2f08dfe 100644
--- a/include/configs/tegra-common-post.h
+++ b/include/configs/tegra-common-post.h
@@ -7,7 +7,7 @@
#ifndef __TEGRA_COMMON_POST_H
#define __TEGRA_COMMON_POST_H
-#define BOOT_TARGETS "mmc1 mmc0 usb pxe dhcp"
+#define BOOT_TARGETS "usb mmc1 mmc0 pxe dhcp"
#ifdef CONFIG_TEGRA_KEYBOARD
#define STDIN_KBD_KBC ",tegra-kbc"
diff --git a/include/configs/ten64.h b/include/configs/ten64.h
index d2bef9b..d5bb2e9 100644
--- a/include/configs/ten64.h
+++ b/include/configs/ten64.h
@@ -9,7 +9,6 @@
#include "ls1088a_common.h"
-
#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd"
diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h
index 2ce9284..40432c9 100644
--- a/include/configs/theadorable.h
+++ b/include/configs/theadorable.h
@@ -32,8 +32,6 @@
/* Environment in SPI NOR flash */
-#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-
/* Keep device tree and initrd in lower memory so the kernel can access them */
#define CFG_EXTRA_ENV_SETTINGS \
"fdt_high=0x10000000\0" \
diff --git a/include/configs/tiger_rk3588.h b/include/configs/tiger_rk3588.h
new file mode 100644
index 0000000..7a32adf
--- /dev/null
+++ b/include/configs/tiger_rk3588.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH
+ */
+
+#ifndef __TIGER_RK3588_H
+#define __TIGER_RK3588_H
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
+
+#include <configs/rk3588_common.h>
+
+#endif /* __TIGER_RK3588_H */
diff --git a/include/configs/topic_miami.h b/include/configs/topic_miami.h
index 3795e61..0627617 100644
--- a/include/configs/topic_miami.h
+++ b/include/configs/topic_miami.h
@@ -9,7 +9,6 @@
#ifndef __CONFIG_TOPIC_MIAMI_H
#define __CONFIG_TOPIC_MIAMI_H
-
/* Speed up boot time by ignoring the environment which we never used */
#include "zynq-common.h"
diff --git a/include/configs/transformer-t20.h b/include/configs/transformer-t20.h
new file mode 100644
index 0000000..ca1e70c
--- /dev/null
+++ b/include/configs/transformer-t20.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * (C) Copyright 2022
+ * Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "tegra20-common.h"
+#include "transformer-common.h"
+
+/* Board-specific serial config */
+#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/turris_omnia.h b/include/configs/turris_omnia.h
index 47b220f..302194b 100644
--- a/include/configs/turris_omnia.h
+++ b/include/configs/turris_omnia.h
@@ -19,8 +19,6 @@
/* Environment in SPI NOR flash */
-#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-
/* Keep device tree and initrd in lower memory so the kernel can access them */
#define RELOCATION_LIMITS_ENV_SETTINGS \
"fdt_high=0x10000000\0" \
diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h
index 34238d3..12d2b68 100644
--- a/include/configs/verdin-imx8mm.h
+++ b/include/configs/verdin-imx8mm.h
@@ -58,8 +58,10 @@
#define CFG_SYS_SDRAM_BASE 0x40000000
/* SDRAM configuration */
-#define PHYS_SDRAM 0x40000000
-#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
+#define PHYS_SDRAM 0x40000000
+#define PHYS_SDRAM_SIZE (long)(SZ_2G + SZ_1G)
+#define PHYS_SDRAM_2 0x100000000
+#define PHYS_SDRAM_2_SIZE (long)(SZ_1G)
/* USB Configs */
#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
diff --git a/include/configs/warp7.h b/include/configs/warp7.h
index 5d2956a..0da9250 100644
--- a/include/configs/warp7.h
+++ b/include/configs/warp7.h
@@ -92,7 +92,6 @@
#define CFG_SYS_FSL_USDHC_NUM 1
-
#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
/* USB Device Firmware Update support */
diff --git a/include/configs/x530.h b/include/configs/x530.h
index e1678e7..982b129 100644
--- a/include/configs/x530.h
+++ b/include/configs/x530.h
@@ -40,8 +40,6 @@
/* Environment in SPI NOR flash */
-#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-
/* NAND */
#include <asm/arch/config.h>
diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
index 8bd0716..d93a45d 100644
--- a/include/configs/x86-common.h
+++ b/include/configs/x86-common.h
@@ -36,5 +36,4 @@
"ramdisk_addr_r=0x4000000\0" \
"ramdiskfile=initramfs.gz\0"
-
#endif /* __CONFIG_H */
diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h
index b634bb1..dc3f41b 100644
--- a/include/configs/xilinx_versal.h
+++ b/include/configs/xilinx_versal.h
@@ -28,9 +28,6 @@
#endif
/* Ethernet driver */
-#if defined(CONFIG_ZYNQ_GEM)
-# define PHY_ANEG_TIMEOUT 20000
-#endif
#define ENV_MEM_LAYOUT_SETTINGS \
"fdt_addr_r=0x40000000\0" \
diff --git a/include/configs/xilinx_versal_net.h b/include/configs/xilinx_versal_net.h
index 9cb6b2b..2a03f4c 100644
--- a/include/configs/xilinx_versal_net.h
+++ b/include/configs/xilinx_versal_net.h
@@ -42,9 +42,6 @@
#endif
/* Ethernet driver */
-#if defined(CONFIG_ZYNQ_GEM)
-# define PHY_ANEG_TIMEOUT 20000
-#endif
#define ENV_MEM_LAYOUT_SETTINGS \
"fdt_addr_r=0x40000000\0" \
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 5bc117e..de0db7b 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -42,12 +42,7 @@
# define PARTS_DEFAULT
#endif
-/* Console I/O Buffer Size */
-
/* Ethernet driver */
-#if defined(CONFIG_ZYNQ_GEM)
-# define PHY_ANEG_TIMEOUT 20000
-#endif
#define ENV_MEM_LAYOUT_SETTINGS \
"fdt_addr_r=0x40000000\0" \
@@ -204,10 +199,6 @@
# define CFG_SYS_SPI_ARGS_SIZE 0xa0000
#endif
-/* u-boot is like dtb */
-
-/* ATF is my kernel image */
-
#ifdef CONFIG_SPL_SYS_MALLOC_SIMPLE
# error "Disable CONFIG_SPL_SYS_MALLOC_SIMPLE. Full malloc needs to be used"
#endif
diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h
index 9655b66..468c5b8 100644
--- a/include/configs/xtfpga.h
+++ b/include/configs/xtfpga.h
@@ -71,7 +71,6 @@
/* U-Boot autoboot configuration */
/*==============================*/
-
/*=========================================*/
/* FPGA Registers (board info and control) */
/*=========================================*/
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 553bb1b..03af859 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -185,7 +185,6 @@
#define CFG_SYS_INIT_RAM_ADDR 0xFFFF0000
#define CFG_SYS_INIT_RAM_SIZE 0x2000
-
/* Extend size of kernel image for uncompression */
/* Address in RAM where the parameters must be copied by SPL. */
diff --git a/include/cyclic.h b/include/cyclic.h
index 44ad3cb..2c3d383 100644
--- a/include/cyclic.h
+++ b/include/cyclic.h
@@ -18,7 +18,6 @@
* struct cyclic_info - Information about cyclic execution function
*
* @func: Function to call periodically
- * @ctx: Context pointer to get passed to this function
* @name: Name of the cyclic function, e.g. shown in the commands
* @delay_ns: Delay is ns after which this function shall get executed
* @start_time_us: Start time in us, when this function started its execution
@@ -27,11 +26,13 @@
* @next_call: Next time in us, when the function shall be executed again
* @list: List node
* @already_warned: Flag that we've warned about exceeding CPU time usage
+ *
+ * When !CONFIG_CYCLIC, this struct is empty.
*/
struct cyclic_info {
- void (*func)(void *ctx);
- void *ctx;
- char *name;
+#if defined(CONFIG_CYCLIC)
+ void (*func)(struct cyclic_info *c);
+ const char *name;
uint64_t delay_us;
uint64_t start_time_us;
uint64_t cpu_time_us;
@@ -39,31 +40,34 @@
uint64_t next_call;
struct hlist_node list;
bool already_warned;
+#endif
};
/** Function type for cyclic functions */
-typedef void (*cyclic_func_t)(void *ctx);
+typedef void (*cyclic_func_t)(struct cyclic_info *c);
#if defined(CONFIG_CYCLIC)
/**
* cyclic_register - Register a new cyclic function
*
+ * @cyclic: Cyclic info structure
* @func: Function to call periodically
* @delay_us: Delay is us after which this function shall get executed
* @name: Cyclic function name/id
- * @ctx: Context to pass to the function
- * @return: pointer to cyclic_struct if OK, NULL on error
+ *
+ * The function @func will be called with @cyclic as its
+ * argument. @cyclic will usually be embedded in some device-specific
+ * structure, which the callback can retrieve using container_of().
*/
-struct cyclic_info *cyclic_register(cyclic_func_t func, uint64_t delay_us,
- const char *name, void *ctx);
+void cyclic_register(struct cyclic_info *cyclic, cyclic_func_t func,
+ uint64_t delay_us, const char *name);
/**
* cyclic_unregister - Unregister a cyclic function
*
* @cyclic: Pointer to cyclic_struct of the function that shall be removed
- * @return: 0 if OK, -ve on error
*/
-int cyclic_unregister(struct cyclic_info *cyclic);
+void cyclic_unregister(struct cyclic_info *cyclic);
/**
* cyclic_unregister_all() - Clean up cyclic functions
@@ -97,17 +101,14 @@
*/
void schedule(void);
#else
-static inline struct cyclic_info *cyclic_register(cyclic_func_t func,
- uint64_t delay_us,
- const char *name,
- void *ctx)
+
+static inline void cyclic_register(struct cyclic_info *cyclic, cyclic_func_t func,
+ uint64_t delay_us, const char *name)
{
- return NULL;
}
-static inline int cyclic_unregister(struct cyclic_info *cyclic)
+static inline void cyclic_unregister(struct cyclic_info *cyclic)
{
- return 0;
}
static inline void cyclic_run(void)
diff --git a/include/dm/devres.h b/include/dm/devres.h
index 697534a..27761de 100644
--- a/include/dm/devres.h
+++ b/include/dm/devres.h
@@ -266,17 +266,13 @@
static inline void *devm_kmalloc_array(struct udevice *dev,
size_t n, size_t size, gfp_t flags)
{
- /* TODO: add kmalloc_array() to linux/compat.h */
- if (size != 0 && n > SIZE_MAX / size)
- return NULL;
- return kmalloc(n * size, flags);
+ return kmalloc_array(n, size, flags);
}
static inline void *devm_kcalloc(struct udevice *dev,
size_t n, size_t size, gfp_t flags)
{
- /* TODO: add kcalloc() to linux/compat.h */
- return kmalloc(n * size, flags | __GFP_ZERO);
+ return kcalloc(n, size, flags);
}
static inline void devm_kfree(struct udevice *dev, void *ptr)
diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h
deleted file mode 100644
index 3090e09..0000000
--- a/include/dt-bindings/clock/exynos850.h
+++ /dev/null
@@ -1,337 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-/*
- * Copyright (C) 2021 Linaro Ltd.
- * Author: Sam Protsenko <semen.protsenko@linaro.org>
- *
- * Device Tree binding constants for Exynos850 clock controller.
- */
-
-#ifndef _DT_BINDINGS_CLOCK_EXYNOS_850_H
-#define _DT_BINDINGS_CLOCK_EXYNOS_850_H
-
-/* CMU_TOP */
-#define CLK_FOUT_SHARED0_PLL 1
-#define CLK_FOUT_SHARED1_PLL 2
-#define CLK_FOUT_MMC_PLL 3
-#define CLK_MOUT_SHARED0_PLL 4
-#define CLK_MOUT_SHARED1_PLL 5
-#define CLK_MOUT_MMC_PLL 6
-#define CLK_MOUT_CORE_BUS 7
-#define CLK_MOUT_CORE_CCI 8
-#define CLK_MOUT_CORE_MMC_EMBD 9
-#define CLK_MOUT_CORE_SSS 10
-#define CLK_MOUT_DPU 11
-#define CLK_MOUT_HSI_BUS 12
-#define CLK_MOUT_HSI_MMC_CARD 13
-#define CLK_MOUT_HSI_USB20DRD 14
-#define CLK_MOUT_PERI_BUS 15
-#define CLK_MOUT_PERI_UART 16
-#define CLK_MOUT_PERI_IP 17
-#define CLK_DOUT_SHARED0_DIV3 18
-#define CLK_DOUT_SHARED0_DIV2 19
-#define CLK_DOUT_SHARED1_DIV3 20
-#define CLK_DOUT_SHARED1_DIV2 21
-#define CLK_DOUT_SHARED0_DIV4 22
-#define CLK_DOUT_SHARED1_DIV4 23
-#define CLK_DOUT_CORE_BUS 24
-#define CLK_DOUT_CORE_CCI 25
-#define CLK_DOUT_CORE_MMC_EMBD 26
-#define CLK_DOUT_CORE_SSS 27
-#define CLK_DOUT_DPU 28
-#define CLK_DOUT_HSI_BUS 29
-#define CLK_DOUT_HSI_MMC_CARD 30
-#define CLK_DOUT_HSI_USB20DRD 31
-#define CLK_DOUT_PERI_BUS 32
-#define CLK_DOUT_PERI_UART 33
-#define CLK_DOUT_PERI_IP 34
-#define CLK_GOUT_CORE_BUS 35
-#define CLK_GOUT_CORE_CCI 36
-#define CLK_GOUT_CORE_MMC_EMBD 37
-#define CLK_GOUT_CORE_SSS 38
-#define CLK_GOUT_DPU 39
-#define CLK_GOUT_HSI_BUS 40
-#define CLK_GOUT_HSI_MMC_CARD 41
-#define CLK_GOUT_HSI_USB20DRD 42
-#define CLK_GOUT_PERI_BUS 43
-#define CLK_GOUT_PERI_UART 44
-#define CLK_GOUT_PERI_IP 45
-#define CLK_MOUT_CLKCMU_APM_BUS 46
-#define CLK_DOUT_CLKCMU_APM_BUS 47
-#define CLK_GOUT_CLKCMU_APM_BUS 48
-#define CLK_MOUT_AUD 49
-#define CLK_GOUT_AUD 50
-#define CLK_DOUT_AUD 51
-#define CLK_MOUT_IS_BUS 52
-#define CLK_MOUT_IS_ITP 53
-#define CLK_MOUT_IS_VRA 54
-#define CLK_MOUT_IS_GDC 55
-#define CLK_GOUT_IS_BUS 56
-#define CLK_GOUT_IS_ITP 57
-#define CLK_GOUT_IS_VRA 58
-#define CLK_GOUT_IS_GDC 59
-#define CLK_DOUT_IS_BUS 60
-#define CLK_DOUT_IS_ITP 61
-#define CLK_DOUT_IS_VRA 62
-#define CLK_DOUT_IS_GDC 63
-#define CLK_MOUT_MFCMSCL_MFC 64
-#define CLK_MOUT_MFCMSCL_M2M 65
-#define CLK_MOUT_MFCMSCL_MCSC 66
-#define CLK_MOUT_MFCMSCL_JPEG 67
-#define CLK_GOUT_MFCMSCL_MFC 68
-#define CLK_GOUT_MFCMSCL_M2M 69
-#define CLK_GOUT_MFCMSCL_MCSC 70
-#define CLK_GOUT_MFCMSCL_JPEG 71
-#define CLK_DOUT_MFCMSCL_MFC 72
-#define CLK_DOUT_MFCMSCL_M2M 73
-#define CLK_DOUT_MFCMSCL_MCSC 74
-#define CLK_DOUT_MFCMSCL_JPEG 75
-#define CLK_MOUT_G3D_SWITCH 76
-#define CLK_GOUT_G3D_SWITCH 77
-#define CLK_DOUT_G3D_SWITCH 78
-
-/* CMU_APM */
-#define CLK_RCO_I3C_PMIC 1
-#define OSCCLK_RCO_APM 2
-#define CLK_RCO_APM__ALV 3
-#define CLK_DLL_DCO 4
-#define CLK_MOUT_APM_BUS_USER 5
-#define CLK_MOUT_RCO_APM_I3C_USER 6
-#define CLK_MOUT_RCO_APM_USER 7
-#define CLK_MOUT_DLL_USER 8
-#define CLK_MOUT_CLKCMU_CHUB_BUS 9
-#define CLK_MOUT_APM_BUS 10
-#define CLK_MOUT_APM_I3C 11
-#define CLK_DOUT_CLKCMU_CHUB_BUS 12
-#define CLK_DOUT_APM_BUS 13
-#define CLK_DOUT_APM_I3C 14
-#define CLK_GOUT_CLKCMU_CMGP_BUS 15
-#define CLK_GOUT_CLKCMU_CHUB_BUS 16
-#define CLK_GOUT_RTC_PCLK 17
-#define CLK_GOUT_TOP_RTC_PCLK 18
-#define CLK_GOUT_I3C_PCLK 19
-#define CLK_GOUT_I3C_SCLK 20
-#define CLK_GOUT_SPEEDY_PCLK 21
-#define CLK_GOUT_GPIO_ALIVE_PCLK 22
-#define CLK_GOUT_PMU_ALIVE_PCLK 23
-#define CLK_GOUT_SYSREG_APM_PCLK 24
-
-/* CMU_AUD */
-#define CLK_DOUT_AUD_AUDIF 1
-#define CLK_DOUT_AUD_BUSD 2
-#define CLK_DOUT_AUD_BUSP 3
-#define CLK_DOUT_AUD_CNT 4
-#define CLK_DOUT_AUD_CPU 5
-#define CLK_DOUT_AUD_CPU_ACLK 6
-#define CLK_DOUT_AUD_CPU_PCLKDBG 7
-#define CLK_DOUT_AUD_FM 8
-#define CLK_DOUT_AUD_FM_SPDY 9
-#define CLK_DOUT_AUD_MCLK 10
-#define CLK_DOUT_AUD_UAIF0 11
-#define CLK_DOUT_AUD_UAIF1 12
-#define CLK_DOUT_AUD_UAIF2 13
-#define CLK_DOUT_AUD_UAIF3 14
-#define CLK_DOUT_AUD_UAIF4 15
-#define CLK_DOUT_AUD_UAIF5 16
-#define CLK_DOUT_AUD_UAIF6 17
-#define CLK_FOUT_AUD_PLL 18
-#define CLK_GOUT_AUD_ABOX_ACLK 19
-#define CLK_GOUT_AUD_ASB_CCLK 20
-#define CLK_GOUT_AUD_CA32_CCLK 21
-#define CLK_GOUT_AUD_CNT_BCLK 22
-#define CLK_GOUT_AUD_CODEC_MCLK 23
-#define CLK_GOUT_AUD_DAP_CCLK 24
-#define CLK_GOUT_AUD_GPIO_PCLK 25
-#define CLK_GOUT_AUD_PPMU_ACLK 26
-#define CLK_GOUT_AUD_PPMU_PCLK 27
-#define CLK_GOUT_AUD_SPDY_BCLK 28
-#define CLK_GOUT_AUD_SYSMMU_CLK 29
-#define CLK_GOUT_AUD_SYSREG_PCLK 30
-#define CLK_GOUT_AUD_TZPC_PCLK 31
-#define CLK_GOUT_AUD_UAIF0_BCLK 32
-#define CLK_GOUT_AUD_UAIF1_BCLK 33
-#define CLK_GOUT_AUD_UAIF2_BCLK 34
-#define CLK_GOUT_AUD_UAIF3_BCLK 35
-#define CLK_GOUT_AUD_UAIF4_BCLK 36
-#define CLK_GOUT_AUD_UAIF5_BCLK 37
-#define CLK_GOUT_AUD_UAIF6_BCLK 38
-#define CLK_GOUT_AUD_WDT_PCLK 39
-#define CLK_MOUT_AUD_CPU 40
-#define CLK_MOUT_AUD_CPU_HCH 41
-#define CLK_MOUT_AUD_CPU_USER 42
-#define CLK_MOUT_AUD_FM 43
-#define CLK_MOUT_AUD_PLL 44
-#define CLK_MOUT_AUD_TICK_USB_USER 45
-#define CLK_MOUT_AUD_UAIF0 46
-#define CLK_MOUT_AUD_UAIF1 47
-#define CLK_MOUT_AUD_UAIF2 48
-#define CLK_MOUT_AUD_UAIF3 49
-#define CLK_MOUT_AUD_UAIF4 50
-#define CLK_MOUT_AUD_UAIF5 51
-#define CLK_MOUT_AUD_UAIF6 52
-#define IOCLK_AUDIOCDCLK0 53
-#define IOCLK_AUDIOCDCLK1 54
-#define IOCLK_AUDIOCDCLK2 55
-#define IOCLK_AUDIOCDCLK3 56
-#define IOCLK_AUDIOCDCLK4 57
-#define IOCLK_AUDIOCDCLK5 58
-#define IOCLK_AUDIOCDCLK6 59
-#define TICK_USB 60
-#define CLK_GOUT_AUD_CMU_AUD_PCLK 61
-
-/* CMU_CMGP */
-#define CLK_RCO_CMGP 1
-#define CLK_MOUT_CMGP_ADC 2
-#define CLK_MOUT_CMGP_USI0 3
-#define CLK_MOUT_CMGP_USI1 4
-#define CLK_DOUT_CMGP_ADC 5
-#define CLK_DOUT_CMGP_USI0 6
-#define CLK_DOUT_CMGP_USI1 7
-#define CLK_GOUT_CMGP_ADC_S0_PCLK 8
-#define CLK_GOUT_CMGP_ADC_S1_PCLK 9
-#define CLK_GOUT_CMGP_GPIO_PCLK 10
-#define CLK_GOUT_CMGP_USI0_IPCLK 11
-#define CLK_GOUT_CMGP_USI0_PCLK 12
-#define CLK_GOUT_CMGP_USI1_IPCLK 13
-#define CLK_GOUT_CMGP_USI1_PCLK 14
-#define CLK_GOUT_SYSREG_CMGP_PCLK 15
-
-/* CMU_G3D */
-#define CLK_FOUT_G3D_PLL 1
-#define CLK_MOUT_G3D_PLL 2
-#define CLK_MOUT_G3D_SWITCH_USER 3
-#define CLK_MOUT_G3D_BUSD 4
-#define CLK_DOUT_G3D_BUSP 5
-#define CLK_GOUT_G3D_CMU_G3D_PCLK 6
-#define CLK_GOUT_G3D_GPU_CLK 7
-#define CLK_GOUT_G3D_TZPC_PCLK 8
-#define CLK_GOUT_G3D_GRAY2BIN_CLK 9
-#define CLK_GOUT_G3D_BUSD_CLK 10
-#define CLK_GOUT_G3D_BUSP_CLK 11
-#define CLK_GOUT_G3D_SYSREG_PCLK 12
-
-/* CMU_HSI */
-#define CLK_MOUT_HSI_BUS_USER 1
-#define CLK_MOUT_HSI_MMC_CARD_USER 2
-#define CLK_MOUT_HSI_USB20DRD_USER 3
-#define CLK_MOUT_HSI_RTC 4
-#define CLK_GOUT_USB_RTC_CLK 5
-#define CLK_GOUT_USB_REF_CLK 6
-#define CLK_GOUT_USB_PHY_REF_CLK 7
-#define CLK_GOUT_USB_PHY_ACLK 8
-#define CLK_GOUT_USB_BUS_EARLY_CLK 9
-#define CLK_GOUT_GPIO_HSI_PCLK 10
-#define CLK_GOUT_MMC_CARD_ACLK 11
-#define CLK_GOUT_MMC_CARD_SDCLKIN 12
-#define CLK_GOUT_SYSREG_HSI_PCLK 13
-#define CLK_GOUT_HSI_PPMU_ACLK 14
-#define CLK_GOUT_HSI_PPMU_PCLK 15
-#define CLK_GOUT_HSI_CMU_HSI_PCLK 16
-
-/* CMU_IS */
-#define CLK_MOUT_IS_BUS_USER 1
-#define CLK_MOUT_IS_ITP_USER 2
-#define CLK_MOUT_IS_VRA_USER 3
-#define CLK_MOUT_IS_GDC_USER 4
-#define CLK_DOUT_IS_BUSP 5
-#define CLK_GOUT_IS_CMU_IS_PCLK 6
-#define CLK_GOUT_IS_CSIS0_ACLK 7
-#define CLK_GOUT_IS_CSIS1_ACLK 8
-#define CLK_GOUT_IS_CSIS2_ACLK 9
-#define CLK_GOUT_IS_TZPC_PCLK 10
-#define CLK_GOUT_IS_CSIS_DMA_CLK 11
-#define CLK_GOUT_IS_GDC_CLK 12
-#define CLK_GOUT_IS_IPP_CLK 13
-#define CLK_GOUT_IS_ITP_CLK 14
-#define CLK_GOUT_IS_MCSC_CLK 15
-#define CLK_GOUT_IS_VRA_CLK 16
-#define CLK_GOUT_IS_PPMU_IS0_ACLK 17
-#define CLK_GOUT_IS_PPMU_IS0_PCLK 18
-#define CLK_GOUT_IS_PPMU_IS1_ACLK 19
-#define CLK_GOUT_IS_PPMU_IS1_PCLK 20
-#define CLK_GOUT_IS_SYSMMU_IS0_CLK 21
-#define CLK_GOUT_IS_SYSMMU_IS1_CLK 22
-#define CLK_GOUT_IS_SYSREG_PCLK 23
-
-/* CMU_MFCMSCL */
-#define CLK_MOUT_MFCMSCL_MFC_USER 1
-#define CLK_MOUT_MFCMSCL_M2M_USER 2
-#define CLK_MOUT_MFCMSCL_MCSC_USER 3
-#define CLK_MOUT_MFCMSCL_JPEG_USER 4
-#define CLK_DOUT_MFCMSCL_BUSP 5
-#define CLK_GOUT_MFCMSCL_CMU_MFCMSCL_PCLK 6
-#define CLK_GOUT_MFCMSCL_TZPC_PCLK 7
-#define CLK_GOUT_MFCMSCL_JPEG_ACLK 8
-#define CLK_GOUT_MFCMSCL_M2M_ACLK 9
-#define CLK_GOUT_MFCMSCL_MCSC_CLK 10
-#define CLK_GOUT_MFCMSCL_MFC_ACLK 11
-#define CLK_GOUT_MFCMSCL_PPMU_ACLK 12
-#define CLK_GOUT_MFCMSCL_PPMU_PCLK 13
-#define CLK_GOUT_MFCMSCL_SYSMMU_CLK 14
-#define CLK_GOUT_MFCMSCL_SYSREG_PCLK 15
-
-/* CMU_PERI */
-#define CLK_MOUT_PERI_BUS_USER 1
-#define CLK_MOUT_PERI_UART_USER 2
-#define CLK_MOUT_PERI_HSI2C_USER 3
-#define CLK_MOUT_PERI_SPI_USER 4
-#define CLK_DOUT_PERI_HSI2C0 5
-#define CLK_DOUT_PERI_HSI2C1 6
-#define CLK_DOUT_PERI_HSI2C2 7
-#define CLK_DOUT_PERI_SPI0 8
-#define CLK_GOUT_PERI_HSI2C0 9
-#define CLK_GOUT_PERI_HSI2C1 10
-#define CLK_GOUT_PERI_HSI2C2 11
-#define CLK_GOUT_GPIO_PERI_PCLK 12
-#define CLK_GOUT_HSI2C0_IPCLK 13
-#define CLK_GOUT_HSI2C0_PCLK 14
-#define CLK_GOUT_HSI2C1_IPCLK 15
-#define CLK_GOUT_HSI2C1_PCLK 16
-#define CLK_GOUT_HSI2C2_IPCLK 17
-#define CLK_GOUT_HSI2C2_PCLK 18
-#define CLK_GOUT_I2C0_PCLK 19
-#define CLK_GOUT_I2C1_PCLK 20
-#define CLK_GOUT_I2C2_PCLK 21
-#define CLK_GOUT_I2C3_PCLK 22
-#define CLK_GOUT_I2C4_PCLK 23
-#define CLK_GOUT_I2C5_PCLK 24
-#define CLK_GOUT_I2C6_PCLK 25
-#define CLK_GOUT_MCT_PCLK 26
-#define CLK_GOUT_PWM_MOTOR_PCLK 27
-#define CLK_GOUT_SPI0_IPCLK 28
-#define CLK_GOUT_SPI0_PCLK 29
-#define CLK_GOUT_SYSREG_PERI_PCLK 30
-#define CLK_GOUT_UART_IPCLK 31
-#define CLK_GOUT_UART_PCLK 32
-#define CLK_GOUT_WDT0_PCLK 33
-#define CLK_GOUT_WDT1_PCLK 34
-
-/* CMU_CORE */
-#define CLK_MOUT_CORE_BUS_USER 1
-#define CLK_MOUT_CORE_CCI_USER 2
-#define CLK_MOUT_CORE_MMC_EMBD_USER 3
-#define CLK_MOUT_CORE_SSS_USER 4
-#define CLK_MOUT_CORE_GIC 5
-#define CLK_DOUT_CORE_BUSP 6
-#define CLK_GOUT_CCI_ACLK 7
-#define CLK_GOUT_GIC_CLK 8
-#define CLK_GOUT_MMC_EMBD_ACLK 9
-#define CLK_GOUT_MMC_EMBD_SDCLKIN 10
-#define CLK_GOUT_SSS_ACLK 11
-#define CLK_GOUT_SSS_PCLK 12
-#define CLK_GOUT_GPIO_CORE_PCLK 13
-#define CLK_GOUT_SYSREG_CORE_PCLK 14
-
-/* CMU_DPU */
-#define CLK_MOUT_DPU_USER 1
-#define CLK_DOUT_DPU_BUSP 2
-#define CLK_GOUT_DPU_CMU_DPU_PCLK 3
-#define CLK_GOUT_DPU_DECON0_ACLK 4
-#define CLK_GOUT_DPU_DMA_ACLK 5
-#define CLK_GOUT_DPU_DPP_ACLK 6
-#define CLK_GOUT_DPU_PPMU_ACLK 7
-#define CLK_GOUT_DPU_PPMU_PCLK 8
-#define CLK_GOUT_DPU_SMMU_CLK 9
-#define CLK_GOUT_DPU_SYSREG_PCLK 10
-#define DPU_NR_CLK 11
-
-#endif /* _DT_BINDINGS_CLOCK_EXYNOS_850_H */
diff --git a/include/dt-bindings/clock/imx5-clock.h b/include/dt-bindings/clock/imx5-clock.h
deleted file mode 100644
index d382fc7..0000000
--- a/include/dt-bindings/clock/imx5-clock.h
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
- * Copyright 2013 Lucas Stach, Pengutronix <l.stach@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef __DT_BINDINGS_CLOCK_IMX5_H
-#define __DT_BINDINGS_CLOCK_IMX5_H
-
-#define IMX5_CLK_DUMMY 0
-#define IMX5_CLK_CKIL 1
-#define IMX5_CLK_OSC 2
-#define IMX5_CLK_CKIH1 3
-#define IMX5_CLK_CKIH2 4
-#define IMX5_CLK_AHB 5
-#define IMX5_CLK_IPG 6
-#define IMX5_CLK_AXI_A 7
-#define IMX5_CLK_AXI_B 8
-#define IMX5_CLK_UART_PRED 9
-#define IMX5_CLK_UART_ROOT 10
-#define IMX5_CLK_ESDHC_A_PRED 11
-#define IMX5_CLK_ESDHC_B_PRED 12
-#define IMX5_CLK_ESDHC_C_SEL 13
-#define IMX5_CLK_ESDHC_D_SEL 14
-#define IMX5_CLK_EMI_SEL 15
-#define IMX5_CLK_EMI_SLOW_PODF 16
-#define IMX5_CLK_NFC_PODF 17
-#define IMX5_CLK_ECSPI_PRED 18
-#define IMX5_CLK_ECSPI_PODF 19
-#define IMX5_CLK_USBOH3_PRED 20
-#define IMX5_CLK_USBOH3_PODF 21
-#define IMX5_CLK_USB_PHY_PRED 22
-#define IMX5_CLK_USB_PHY_PODF 23
-#define IMX5_CLK_CPU_PODF 24
-#define IMX5_CLK_DI_PRED 25
-#define IMX5_CLK_TVE_SEL 27
-#define IMX5_CLK_UART1_IPG_GATE 28
-#define IMX5_CLK_UART1_PER_GATE 29
-#define IMX5_CLK_UART2_IPG_GATE 30
-#define IMX5_CLK_UART2_PER_GATE 31
-#define IMX5_CLK_UART3_IPG_GATE 32
-#define IMX5_CLK_UART3_PER_GATE 33
-#define IMX5_CLK_I2C1_GATE 34
-#define IMX5_CLK_I2C2_GATE 35
-#define IMX5_CLK_GPT_IPG_GATE 36
-#define IMX5_CLK_PWM1_IPG_GATE 37
-#define IMX5_CLK_PWM1_HF_GATE 38
-#define IMX5_CLK_PWM2_IPG_GATE 39
-#define IMX5_CLK_PWM2_HF_GATE 40
-#define IMX5_CLK_GPT_HF_GATE 41
-#define IMX5_CLK_FEC_GATE 42
-#define IMX5_CLK_USBOH3_PER_GATE 43
-#define IMX5_CLK_ESDHC1_IPG_GATE 44
-#define IMX5_CLK_ESDHC2_IPG_GATE 45
-#define IMX5_CLK_ESDHC3_IPG_GATE 46
-#define IMX5_CLK_ESDHC4_IPG_GATE 47
-#define IMX5_CLK_SSI1_IPG_GATE 48
-#define IMX5_CLK_SSI2_IPG_GATE 49
-#define IMX5_CLK_SSI3_IPG_GATE 50
-#define IMX5_CLK_ECSPI1_IPG_GATE 51
-#define IMX5_CLK_ECSPI1_PER_GATE 52
-#define IMX5_CLK_ECSPI2_IPG_GATE 53
-#define IMX5_CLK_ECSPI2_PER_GATE 54
-#define IMX5_CLK_CSPI_IPG_GATE 55
-#define IMX5_CLK_SDMA_GATE 56
-#define IMX5_CLK_EMI_SLOW_GATE 57
-#define IMX5_CLK_IPU_SEL 58
-#define IMX5_CLK_IPU_GATE 59
-#define IMX5_CLK_NFC_GATE 60
-#define IMX5_CLK_IPU_DI1_GATE 61
-#define IMX5_CLK_VPU_SEL 62
-#define IMX5_CLK_VPU_GATE 63
-#define IMX5_CLK_VPU_REFERENCE_GATE 64
-#define IMX5_CLK_UART4_IPG_GATE 65
-#define IMX5_CLK_UART4_PER_GATE 66
-#define IMX5_CLK_UART5_IPG_GATE 67
-#define IMX5_CLK_UART5_PER_GATE 68
-#define IMX5_CLK_TVE_GATE 69
-#define IMX5_CLK_TVE_PRED 70
-#define IMX5_CLK_ESDHC1_PER_GATE 71
-#define IMX5_CLK_ESDHC2_PER_GATE 72
-#define IMX5_CLK_ESDHC3_PER_GATE 73
-#define IMX5_CLK_ESDHC4_PER_GATE 74
-#define IMX5_CLK_USB_PHY_GATE 75
-#define IMX5_CLK_HSI2C_GATE 76
-#define IMX5_CLK_MIPI_HSC1_GATE 77
-#define IMX5_CLK_MIPI_HSC2_GATE 78
-#define IMX5_CLK_MIPI_ESC_GATE 79
-#define IMX5_CLK_MIPI_HSP_GATE 80
-#define IMX5_CLK_LDB_DI1_DIV_3_5 81
-#define IMX5_CLK_LDB_DI1_DIV 82
-#define IMX5_CLK_LDB_DI0_DIV_3_5 83
-#define IMX5_CLK_LDB_DI0_DIV 84
-#define IMX5_CLK_LDB_DI1_GATE 85
-#define IMX5_CLK_CAN2_SERIAL_GATE 86
-#define IMX5_CLK_CAN2_IPG_GATE 87
-#define IMX5_CLK_I2C3_GATE 88
-#define IMX5_CLK_LP_APM 89
-#define IMX5_CLK_PERIPH_APM 90
-#define IMX5_CLK_MAIN_BUS 91
-#define IMX5_CLK_AHB_MAX 92
-#define IMX5_CLK_AIPS_TZ1 93
-#define IMX5_CLK_AIPS_TZ2 94
-#define IMX5_CLK_TMAX1 95
-#define IMX5_CLK_TMAX2 96
-#define IMX5_CLK_TMAX3 97
-#define IMX5_CLK_SPBA 98
-#define IMX5_CLK_UART_SEL 99
-#define IMX5_CLK_ESDHC_A_SEL 100
-#define IMX5_CLK_ESDHC_B_SEL 101
-#define IMX5_CLK_ESDHC_A_PODF 102
-#define IMX5_CLK_ESDHC_B_PODF 103
-#define IMX5_CLK_ECSPI_SEL 104
-#define IMX5_CLK_USBOH3_SEL 105
-#define IMX5_CLK_USB_PHY_SEL 106
-#define IMX5_CLK_IIM_GATE 107
-#define IMX5_CLK_USBOH3_GATE 108
-#define IMX5_CLK_EMI_FAST_GATE 109
-#define IMX5_CLK_IPU_DI0_GATE 110
-#define IMX5_CLK_GPC_DVFS 111
-#define IMX5_CLK_PLL1_SW 112
-#define IMX5_CLK_PLL2_SW 113
-#define IMX5_CLK_PLL3_SW 114
-#define IMX5_CLK_IPU_DI0_SEL 115
-#define IMX5_CLK_IPU_DI1_SEL 116
-#define IMX5_CLK_TVE_EXT_SEL 117
-#define IMX5_CLK_MX51_MIPI 118
-#define IMX5_CLK_PLL4_SW 119
-#define IMX5_CLK_LDB_DI1_SEL 120
-#define IMX5_CLK_DI_PLL4_PODF 121
-#define IMX5_CLK_LDB_DI0_SEL 122
-#define IMX5_CLK_LDB_DI0_GATE 123
-#define IMX5_CLK_USB_PHY1_GATE 124
-#define IMX5_CLK_USB_PHY2_GATE 125
-#define IMX5_CLK_PER_LP_APM 126
-#define IMX5_CLK_PER_PRED1 127
-#define IMX5_CLK_PER_PRED2 128
-#define IMX5_CLK_PER_PODF 129
-#define IMX5_CLK_PER_ROOT 130
-#define IMX5_CLK_SSI_APM 131
-#define IMX5_CLK_SSI1_ROOT_SEL 132
-#define IMX5_CLK_SSI2_ROOT_SEL 133
-#define IMX5_CLK_SSI3_ROOT_SEL 134
-#define IMX5_CLK_SSI_EXT1_SEL 135
-#define IMX5_CLK_SSI_EXT2_SEL 136
-#define IMX5_CLK_SSI_EXT1_COM_SEL 137
-#define IMX5_CLK_SSI_EXT2_COM_SEL 138
-#define IMX5_CLK_SSI1_ROOT_PRED 139
-#define IMX5_CLK_SSI1_ROOT_PODF 140
-#define IMX5_CLK_SSI2_ROOT_PRED 141
-#define IMX5_CLK_SSI2_ROOT_PODF 142
-#define IMX5_CLK_SSI_EXT1_PRED 143
-#define IMX5_CLK_SSI_EXT1_PODF 144
-#define IMX5_CLK_SSI_EXT2_PRED 145
-#define IMX5_CLK_SSI_EXT2_PODF 146
-#define IMX5_CLK_SSI1_ROOT_GATE 147
-#define IMX5_CLK_SSI2_ROOT_GATE 148
-#define IMX5_CLK_SSI3_ROOT_GATE 149
-#define IMX5_CLK_SSI_EXT1_GATE 150
-#define IMX5_CLK_SSI_EXT2_GATE 151
-#define IMX5_CLK_EPIT1_IPG_GATE 152
-#define IMX5_CLK_EPIT1_HF_GATE 153
-#define IMX5_CLK_EPIT2_IPG_GATE 154
-#define IMX5_CLK_EPIT2_HF_GATE 155
-#define IMX5_CLK_CAN_SEL 156
-#define IMX5_CLK_CAN1_SERIAL_GATE 157
-#define IMX5_CLK_CAN1_IPG_GATE 158
-#define IMX5_CLK_OWIRE_GATE 159
-#define IMX5_CLK_GPU3D_SEL 160
-#define IMX5_CLK_GPU2D_SEL 161
-#define IMX5_CLK_GPU3D_GATE 162
-#define IMX5_CLK_GPU2D_GATE 163
-#define IMX5_CLK_GARB_GATE 164
-#define IMX5_CLK_CKO1_SEL 165
-#define IMX5_CLK_CKO1_PODF 166
-#define IMX5_CLK_CKO1 167
-#define IMX5_CLK_CKO2_SEL 168
-#define IMX5_CLK_CKO2_PODF 169
-#define IMX5_CLK_CKO2 170
-#define IMX5_CLK_SRTC_GATE 171
-#define IMX5_CLK_PATA_GATE 172
-#define IMX5_CLK_SATA_GATE 173
-#define IMX5_CLK_SPDIF_XTAL_SEL 174
-#define IMX5_CLK_SPDIF0_SEL 175
-#define IMX5_CLK_SPDIF1_SEL 176
-#define IMX5_CLK_SPDIF0_PRED 177
-#define IMX5_CLK_SPDIF0_PODF 178
-#define IMX5_CLK_SPDIF1_PRED 179
-#define IMX5_CLK_SPDIF1_PODF 180
-#define IMX5_CLK_SPDIF0_COM_SEL 181
-#define IMX5_CLK_SPDIF1_COM_SEL 182
-#define IMX5_CLK_SPDIF0_GATE 183
-#define IMX5_CLK_SPDIF1_GATE 184
-#define IMX5_CLK_SPDIF_IPG_GATE 185
-#define IMX5_CLK_OCRAM 186
-#define IMX5_CLK_SAHARA_IPG_GATE 187
-#define IMX5_CLK_SATA_REF 188
-#define IMX5_CLK_STEP_SEL 189
-#define IMX5_CLK_CPU_PODF_SEL 190
-#define IMX5_CLK_ARM 191
-#define IMX5_CLK_FIRI_PRED 192
-#define IMX5_CLK_FIRI_SEL 193
-#define IMX5_CLK_FIRI_PODF 194
-#define IMX5_CLK_FIRI_SERIAL_GATE 195
-#define IMX5_CLK_FIRI_IPG_GATE 196
-#define IMX5_CLK_CSI0_MCLK1_PRED 197
-#define IMX5_CLK_CSI0_MCLK1_SEL 198
-#define IMX5_CLK_CSI0_MCLK1_PODF 199
-#define IMX5_CLK_CSI0_MCLK1_GATE 200
-#define IMX5_CLK_IEEE1588_PRED 201
-#define IMX5_CLK_IEEE1588_SEL 202
-#define IMX5_CLK_IEEE1588_PODF 203
-#define IMX5_CLK_IEEE1588_GATE 204
-#define IMX5_CLK_END 205
-
-#endif /* __DT_BINDINGS_CLOCK_IMX5_H */
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
deleted file mode 100644
index e20c43c..0000000
--- a/include/dt-bindings/clock/imx6qdl-clock.h
+++ /dev/null
@@ -1,278 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#ifndef __DT_BINDINGS_CLOCK_IMX6QDL_H
-#define __DT_BINDINGS_CLOCK_IMX6QDL_H
-
-#define IMX6QDL_CLK_DUMMY 0
-#define IMX6QDL_CLK_CKIL 1
-#define IMX6QDL_CLK_CKIH 2
-#define IMX6QDL_CLK_OSC 3
-#define IMX6QDL_CLK_PLL2_PFD0_352M 4
-#define IMX6QDL_CLK_PLL2_PFD1_594M 5
-#define IMX6QDL_CLK_PLL2_PFD2_396M 6
-#define IMX6QDL_CLK_PLL3_PFD0_720M 7
-#define IMX6QDL_CLK_PLL3_PFD1_540M 8
-#define IMX6QDL_CLK_PLL3_PFD2_508M 9
-#define IMX6QDL_CLK_PLL3_PFD3_454M 10
-#define IMX6QDL_CLK_PLL2_198M 11
-#define IMX6QDL_CLK_PLL3_120M 12
-#define IMX6QDL_CLK_PLL3_80M 13
-#define IMX6QDL_CLK_PLL3_60M 14
-#define IMX6QDL_CLK_TWD 15
-#define IMX6QDL_CLK_STEP 16
-#define IMX6QDL_CLK_PLL1_SW 17
-#define IMX6QDL_CLK_PERIPH_PRE 18
-#define IMX6QDL_CLK_PERIPH2_PRE 19
-#define IMX6QDL_CLK_PERIPH_CLK2_SEL 20
-#define IMX6QDL_CLK_PERIPH2_CLK2_SEL 21
-#define IMX6QDL_CLK_AXI_SEL 22
-#define IMX6QDL_CLK_ESAI_SEL 23
-#define IMX6QDL_CLK_ASRC_SEL 24
-#define IMX6QDL_CLK_SPDIF_SEL 25
-#define IMX6QDL_CLK_GPU2D_AXI 26
-#define IMX6QDL_CLK_GPU3D_AXI 27
-#define IMX6QDL_CLK_GPU2D_CORE_SEL 28
-#define IMX6QDL_CLK_GPU3D_CORE_SEL 29
-#define IMX6QDL_CLK_GPU3D_SHADER_SEL 30
-#define IMX6QDL_CLK_IPU1_SEL 31
-#define IMX6QDL_CLK_IPU2_SEL 32
-#define IMX6QDL_CLK_LDB_DI0_SEL 33
-#define IMX6QDL_CLK_LDB_DI1_SEL 34
-#define IMX6QDL_CLK_IPU1_DI0_PRE_SEL 35
-#define IMX6QDL_CLK_IPU1_DI1_PRE_SEL 36
-#define IMX6QDL_CLK_IPU2_DI0_PRE_SEL 37
-#define IMX6QDL_CLK_IPU2_DI1_PRE_SEL 38
-#define IMX6QDL_CLK_IPU1_DI0_SEL 39
-#define IMX6QDL_CLK_IPU1_DI1_SEL 40
-#define IMX6QDL_CLK_IPU2_DI0_SEL 41
-#define IMX6QDL_CLK_IPU2_DI1_SEL 42
-#define IMX6QDL_CLK_HSI_TX_SEL 43
-#define IMX6QDL_CLK_PCIE_AXI_SEL 44
-#define IMX6QDL_CLK_SSI1_SEL 45
-#define IMX6QDL_CLK_SSI2_SEL 46
-#define IMX6QDL_CLK_SSI3_SEL 47
-#define IMX6QDL_CLK_USDHC1_SEL 48
-#define IMX6QDL_CLK_USDHC2_SEL 49
-#define IMX6QDL_CLK_USDHC3_SEL 50
-#define IMX6QDL_CLK_USDHC4_SEL 51
-#define IMX6QDL_CLK_ENFC_SEL 52
-#define IMX6QDL_CLK_EIM_SEL 53
-#define IMX6QDL_CLK_EIM_SLOW_SEL 54
-#define IMX6QDL_CLK_VDO_AXI_SEL 55
-#define IMX6QDL_CLK_VPU_AXI_SEL 56
-#define IMX6QDL_CLK_CKO1_SEL 57
-#define IMX6QDL_CLK_PERIPH 58
-#define IMX6QDL_CLK_PERIPH2 59
-#define IMX6QDL_CLK_PERIPH_CLK2 60
-#define IMX6QDL_CLK_PERIPH2_CLK2 61
-#define IMX6QDL_CLK_IPG 62
-#define IMX6QDL_CLK_IPG_PER 63
-#define IMX6QDL_CLK_ESAI_PRED 64
-#define IMX6QDL_CLK_ESAI_PODF 65
-#define IMX6QDL_CLK_ASRC_PRED 66
-#define IMX6QDL_CLK_ASRC_PODF 67
-#define IMX6QDL_CLK_SPDIF_PRED 68
-#define IMX6QDL_CLK_SPDIF_PODF 69
-#define IMX6QDL_CLK_CAN_ROOT 70
-#define IMX6QDL_CLK_ECSPI_ROOT 71
-#define IMX6QDL_CLK_GPU2D_CORE_PODF 72
-#define IMX6QDL_CLK_GPU3D_CORE_PODF 73
-#define IMX6QDL_CLK_GPU3D_SHADER 74
-#define IMX6QDL_CLK_IPU1_PODF 75
-#define IMX6QDL_CLK_IPU2_PODF 76
-#define IMX6QDL_CLK_LDB_DI0_PODF 77
-#define IMX6QDL_CLK_LDB_DI1_PODF 78
-#define IMX6QDL_CLK_IPU1_DI0_PRE 79
-#define IMX6QDL_CLK_IPU1_DI1_PRE 80
-#define IMX6QDL_CLK_IPU2_DI0_PRE 81
-#define IMX6QDL_CLK_IPU2_DI1_PRE 82
-#define IMX6QDL_CLK_HSI_TX_PODF 83
-#define IMX6QDL_CLK_SSI1_PRED 84
-#define IMX6QDL_CLK_SSI1_PODF 85
-#define IMX6QDL_CLK_SSI2_PRED 86
-#define IMX6QDL_CLK_SSI2_PODF 87
-#define IMX6QDL_CLK_SSI3_PRED 88
-#define IMX6QDL_CLK_SSI3_PODF 89
-#define IMX6QDL_CLK_UART_SERIAL_PODF 90
-#define IMX6QDL_CLK_USDHC1_PODF 91
-#define IMX6QDL_CLK_USDHC2_PODF 92
-#define IMX6QDL_CLK_USDHC3_PODF 93
-#define IMX6QDL_CLK_USDHC4_PODF 94
-#define IMX6QDL_CLK_ENFC_PRED 95
-#define IMX6QDL_CLK_ENFC_PODF 96
-#define IMX6QDL_CLK_EIM_PODF 97
-#define IMX6QDL_CLK_EIM_SLOW_PODF 98
-#define IMX6QDL_CLK_VPU_AXI_PODF 99
-#define IMX6QDL_CLK_CKO1_PODF 100
-#define IMX6QDL_CLK_AXI 101
-#define IMX6QDL_CLK_MMDC_CH0_AXI_PODF 102
-#define IMX6QDL_CLK_MMDC_CH1_AXI_PODF 103
-#define IMX6QDL_CLK_ARM 104
-#define IMX6QDL_CLK_AHB 105
-#define IMX6QDL_CLK_APBH_DMA 106
-#define IMX6QDL_CLK_ASRC 107
-#define IMX6QDL_CLK_CAN1_IPG 108
-#define IMX6QDL_CLK_CAN1_SERIAL 109
-#define IMX6QDL_CLK_CAN2_IPG 110
-#define IMX6QDL_CLK_CAN2_SERIAL 111
-#define IMX6QDL_CLK_ECSPI1 112
-#define IMX6QDL_CLK_ECSPI2 113
-#define IMX6QDL_CLK_ECSPI3 114
-#define IMX6QDL_CLK_ECSPI4 115
-#define IMX6Q_CLK_ECSPI5 116
-#define IMX6DL_CLK_I2C4 116
-#define IMX6QDL_CLK_ENET 117
-#define IMX6QDL_CLK_ESAI_EXTAL 118
-#define IMX6QDL_CLK_GPT_IPG 119
-#define IMX6QDL_CLK_GPT_IPG_PER 120
-#define IMX6QDL_CLK_GPU2D_CORE 121
-#define IMX6QDL_CLK_GPU3D_CORE 122
-#define IMX6QDL_CLK_HDMI_IAHB 123
-#define IMX6QDL_CLK_HDMI_ISFR 124
-#define IMX6QDL_CLK_I2C1 125
-#define IMX6QDL_CLK_I2C2 126
-#define IMX6QDL_CLK_I2C3 127
-#define IMX6QDL_CLK_IIM 128
-#define IMX6QDL_CLK_ENFC 129
-#define IMX6QDL_CLK_IPU1 130
-#define IMX6QDL_CLK_IPU1_DI0 131
-#define IMX6QDL_CLK_IPU1_DI1 132
-#define IMX6QDL_CLK_IPU2 133
-#define IMX6QDL_CLK_IPU2_DI0 134
-#define IMX6QDL_CLK_LDB_DI0 135
-#define IMX6QDL_CLK_LDB_DI1 136
-#define IMX6QDL_CLK_IPU2_DI1 137
-#define IMX6QDL_CLK_HSI_TX 138
-#define IMX6QDL_CLK_MLB 139
-#define IMX6QDL_CLK_MMDC_CH0_AXI 140
-#define IMX6QDL_CLK_MMDC_CH1_AXI 141
-#define IMX6QDL_CLK_OCRAM 142
-#define IMX6QDL_CLK_OPENVG_AXI 143
-#define IMX6QDL_CLK_PCIE_AXI 144
-#define IMX6QDL_CLK_PWM1 145
-#define IMX6QDL_CLK_PWM2 146
-#define IMX6QDL_CLK_PWM3 147
-#define IMX6QDL_CLK_PWM4 148
-#define IMX6QDL_CLK_PER1_BCH 149
-#define IMX6QDL_CLK_GPMI_BCH_APB 150
-#define IMX6QDL_CLK_GPMI_BCH 151
-#define IMX6QDL_CLK_GPMI_IO 152
-#define IMX6QDL_CLK_GPMI_APB 153
-#define IMX6QDL_CLK_SATA 154
-#define IMX6QDL_CLK_SDMA 155
-#define IMX6QDL_CLK_SPBA 156
-#define IMX6QDL_CLK_SSI1 157
-#define IMX6QDL_CLK_SSI2 158
-#define IMX6QDL_CLK_SSI3 159
-#define IMX6QDL_CLK_UART_IPG 160
-#define IMX6QDL_CLK_UART_SERIAL 161
-#define IMX6QDL_CLK_USBOH3 162
-#define IMX6QDL_CLK_USDHC1 163
-#define IMX6QDL_CLK_USDHC2 164
-#define IMX6QDL_CLK_USDHC3 165
-#define IMX6QDL_CLK_USDHC4 166
-#define IMX6QDL_CLK_VDO_AXI 167
-#define IMX6QDL_CLK_VPU_AXI 168
-#define IMX6QDL_CLK_CKO1 169
-#define IMX6QDL_CLK_PLL1_SYS 170
-#define IMX6QDL_CLK_PLL2_BUS 171
-#define IMX6QDL_CLK_PLL3_USB_OTG 172
-#define IMX6QDL_CLK_PLL4_AUDIO 173
-#define IMX6QDL_CLK_PLL5_VIDEO 174
-#define IMX6QDL_CLK_PLL8_MLB 175
-#define IMX6QDL_CLK_PLL7_USB_HOST 176
-#define IMX6QDL_CLK_PLL6_ENET 177
-#define IMX6QDL_CLK_SSI1_IPG 178
-#define IMX6QDL_CLK_SSI2_IPG 179
-#define IMX6QDL_CLK_SSI3_IPG 180
-#define IMX6QDL_CLK_ROM 181
-#define IMX6QDL_CLK_USBPHY1 182
-#define IMX6QDL_CLK_USBPHY2 183
-#define IMX6QDL_CLK_LDB_DI0_DIV_3_5 184
-#define IMX6QDL_CLK_LDB_DI1_DIV_3_5 185
-#define IMX6QDL_CLK_SATA_REF 186
-#define IMX6QDL_CLK_SATA_REF_100M 187
-#define IMX6QDL_CLK_PCIE_REF 188
-#define IMX6QDL_CLK_PCIE_REF_125M 189
-#define IMX6QDL_CLK_ENET_REF 190
-#define IMX6QDL_CLK_USBPHY1_GATE 191
-#define IMX6QDL_CLK_USBPHY2_GATE 192
-#define IMX6QDL_CLK_PLL4_POST_DIV 193
-#define IMX6QDL_CLK_PLL5_POST_DIV 194
-#define IMX6QDL_CLK_PLL5_VIDEO_DIV 195
-#define IMX6QDL_CLK_EIM_SLOW 196
-#define IMX6QDL_CLK_SPDIF 197
-#define IMX6QDL_CLK_CKO2_SEL 198
-#define IMX6QDL_CLK_CKO2_PODF 199
-#define IMX6QDL_CLK_CKO2 200
-#define IMX6QDL_CLK_CKO 201
-#define IMX6QDL_CLK_VDOA 202
-#define IMX6QDL_CLK_PLL4_AUDIO_DIV 203
-#define IMX6QDL_CLK_LVDS1_SEL 204
-#define IMX6QDL_CLK_LVDS2_SEL 205
-#define IMX6QDL_CLK_LVDS1_GATE 206
-#define IMX6QDL_CLK_LVDS2_GATE 207
-#define IMX6QDL_CLK_ESAI_IPG 208
-#define IMX6QDL_CLK_ESAI_MEM 209
-#define IMX6QDL_CLK_ASRC_IPG 210
-#define IMX6QDL_CLK_ASRC_MEM 211
-#define IMX6QDL_CLK_LVDS1_IN 212
-#define IMX6QDL_CLK_LVDS2_IN 213
-#define IMX6QDL_CLK_ANACLK1 214
-#define IMX6QDL_CLK_ANACLK2 215
-#define IMX6QDL_PLL1_BYPASS_SRC 216
-#define IMX6QDL_PLL2_BYPASS_SRC 217
-#define IMX6QDL_PLL3_BYPASS_SRC 218
-#define IMX6QDL_PLL4_BYPASS_SRC 219
-#define IMX6QDL_PLL5_BYPASS_SRC 220
-#define IMX6QDL_PLL6_BYPASS_SRC 221
-#define IMX6QDL_PLL7_BYPASS_SRC 222
-#define IMX6QDL_CLK_PLL1 223
-#define IMX6QDL_CLK_PLL2 224
-#define IMX6QDL_CLK_PLL3 225
-#define IMX6QDL_CLK_PLL4 226
-#define IMX6QDL_CLK_PLL5 227
-#define IMX6QDL_CLK_PLL6 228
-#define IMX6QDL_CLK_PLL7 229
-#define IMX6QDL_PLL1_BYPASS 230
-#define IMX6QDL_PLL2_BYPASS 231
-#define IMX6QDL_PLL3_BYPASS 232
-#define IMX6QDL_PLL4_BYPASS 233
-#define IMX6QDL_PLL5_BYPASS 234
-#define IMX6QDL_PLL6_BYPASS 235
-#define IMX6QDL_PLL7_BYPASS 236
-#define IMX6QDL_CLK_GPT_3M 237
-#define IMX6QDL_CLK_VIDEO_27M 238
-#define IMX6QDL_CLK_MIPI_CORE_CFG 239
-#define IMX6QDL_CLK_MIPI_IPG 240
-#define IMX6QDL_CLK_CAAM_MEM 241
-#define IMX6QDL_CLK_CAAM_ACLK 242
-#define IMX6QDL_CLK_CAAM_IPG 243
-#define IMX6QDL_CLK_SPDIF_GCLK 244
-#define IMX6QDL_CLK_UART_SEL 245
-#define IMX6QDL_CLK_IPG_PER_SEL 246
-#define IMX6QDL_CLK_ECSPI_SEL 247
-#define IMX6QDL_CLK_CAN_SEL 248
-#define IMX6QDL_CLK_MMDC_CH1_AXI_CG 249
-#define IMX6QDL_CLK_PRE0 250
-#define IMX6QDL_CLK_PRE1 251
-#define IMX6QDL_CLK_PRE2 252
-#define IMX6QDL_CLK_PRE3 253
-#define IMX6QDL_CLK_PRG0_AXI 254
-#define IMX6QDL_CLK_PRG1_AXI 255
-#define IMX6QDL_CLK_PRG0_APB 256
-#define IMX6QDL_CLK_PRG1_APB 257
-#define IMX6QDL_CLK_PRE_AXI 258
-#define IMX6QDL_CLK_MLB_SEL 259
-#define IMX6QDL_CLK_MLB_PODF 260
-#define IMX6QDL_CLK_EPIT1 261
-#define IMX6QDL_CLK_EPIT2 262
-#define IMX6QDL_CLK_MMDC_P0_IPG 263
-#define IMX6QDL_CLK_DCIC1 264
-#define IMX6QDL_CLK_DCIC2 265
-#define IMX6QDL_CLK_END 266
-
-#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
diff --git a/include/dt-bindings/clock/imx6sl-clock.h b/include/dt-bindings/clock/imx6sl-clock.h
deleted file mode 100644
index 31364d2..0000000
--- a/include/dt-bindings/clock/imx6sl-clock.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#ifndef __DT_BINDINGS_CLOCK_IMX6SL_H
-#define __DT_BINDINGS_CLOCK_IMX6SL_H
-
-#define IMX6SL_CLK_DUMMY 0
-#define IMX6SL_CLK_CKIL 1
-#define IMX6SL_CLK_OSC 2
-#define IMX6SL_CLK_PLL1_SYS 3
-#define IMX6SL_CLK_PLL2_BUS 4
-#define IMX6SL_CLK_PLL3_USB_OTG 5
-#define IMX6SL_CLK_PLL4_AUDIO 6
-#define IMX6SL_CLK_PLL5_VIDEO 7
-#define IMX6SL_CLK_PLL6_ENET 8
-#define IMX6SL_CLK_PLL7_USB_HOST 9
-#define IMX6SL_CLK_USBPHY1 10
-#define IMX6SL_CLK_USBPHY2 11
-#define IMX6SL_CLK_USBPHY1_GATE 12
-#define IMX6SL_CLK_USBPHY2_GATE 13
-#define IMX6SL_CLK_PLL4_POST_DIV 14
-#define IMX6SL_CLK_PLL5_POST_DIV 15
-#define IMX6SL_CLK_PLL5_VIDEO_DIV 16
-#define IMX6SL_CLK_ENET_REF 17
-#define IMX6SL_CLK_PLL2_PFD0 18
-#define IMX6SL_CLK_PLL2_PFD1 19
-#define IMX6SL_CLK_PLL2_PFD2 20
-#define IMX6SL_CLK_PLL3_PFD0 21
-#define IMX6SL_CLK_PLL3_PFD1 22
-#define IMX6SL_CLK_PLL3_PFD2 23
-#define IMX6SL_CLK_PLL3_PFD3 24
-#define IMX6SL_CLK_PLL2_198M 25
-#define IMX6SL_CLK_PLL3_120M 26
-#define IMX6SL_CLK_PLL3_80M 27
-#define IMX6SL_CLK_PLL3_60M 28
-#define IMX6SL_CLK_STEP 29
-#define IMX6SL_CLK_PLL1_SW 30
-#define IMX6SL_CLK_OCRAM_ALT_SEL 31
-#define IMX6SL_CLK_OCRAM_SEL 32
-#define IMX6SL_CLK_PRE_PERIPH2_SEL 33
-#define IMX6SL_CLK_PRE_PERIPH_SEL 34
-#define IMX6SL_CLK_PERIPH2_CLK2_SEL 35
-#define IMX6SL_CLK_PERIPH_CLK2_SEL 36
-#define IMX6SL_CLK_CSI_SEL 37
-#define IMX6SL_CLK_LCDIF_AXI_SEL 38
-#define IMX6SL_CLK_USDHC1_SEL 39
-#define IMX6SL_CLK_USDHC2_SEL 40
-#define IMX6SL_CLK_USDHC3_SEL 41
-#define IMX6SL_CLK_USDHC4_SEL 42
-#define IMX6SL_CLK_SSI1_SEL 43
-#define IMX6SL_CLK_SSI2_SEL 44
-#define IMX6SL_CLK_SSI3_SEL 45
-#define IMX6SL_CLK_PERCLK_SEL 46
-#define IMX6SL_CLK_PXP_AXI_SEL 47
-#define IMX6SL_CLK_EPDC_AXI_SEL 48
-#define IMX6SL_CLK_GPU2D_OVG_SEL 49
-#define IMX6SL_CLK_GPU2D_SEL 50
-#define IMX6SL_CLK_LCDIF_PIX_SEL 51
-#define IMX6SL_CLK_EPDC_PIX_SEL 52
-#define IMX6SL_CLK_SPDIF0_SEL 53
-#define IMX6SL_CLK_SPDIF1_SEL 54
-#define IMX6SL_CLK_EXTERN_AUDIO_SEL 55
-#define IMX6SL_CLK_ECSPI_SEL 56
-#define IMX6SL_CLK_UART_SEL 57
-#define IMX6SL_CLK_PERIPH 58
-#define IMX6SL_CLK_PERIPH2 59
-#define IMX6SL_CLK_OCRAM_PODF 60
-#define IMX6SL_CLK_PERIPH_CLK2_PODF 61
-#define IMX6SL_CLK_PERIPH2_CLK2_PODF 62
-#define IMX6SL_CLK_IPG 63
-#define IMX6SL_CLK_CSI_PODF 64
-#define IMX6SL_CLK_LCDIF_AXI_PODF 65
-#define IMX6SL_CLK_USDHC1_PODF 66
-#define IMX6SL_CLK_USDHC2_PODF 67
-#define IMX6SL_CLK_USDHC3_PODF 68
-#define IMX6SL_CLK_USDHC4_PODF 69
-#define IMX6SL_CLK_SSI1_PRED 70
-#define IMX6SL_CLK_SSI1_PODF 71
-#define IMX6SL_CLK_SSI2_PRED 72
-#define IMX6SL_CLK_SSI2_PODF 73
-#define IMX6SL_CLK_SSI3_PRED 74
-#define IMX6SL_CLK_SSI3_PODF 75
-#define IMX6SL_CLK_PERCLK 76
-#define IMX6SL_CLK_PXP_AXI_PODF 77
-#define IMX6SL_CLK_EPDC_AXI_PODF 78
-#define IMX6SL_CLK_GPU2D_OVG_PODF 79
-#define IMX6SL_CLK_GPU2D_PODF 80
-#define IMX6SL_CLK_LCDIF_PIX_PRED 81
-#define IMX6SL_CLK_EPDC_PIX_PRED 82
-#define IMX6SL_CLK_LCDIF_PIX_PODF 83
-#define IMX6SL_CLK_EPDC_PIX_PODF 84
-#define IMX6SL_CLK_SPDIF0_PRED 85
-#define IMX6SL_CLK_SPDIF0_PODF 86
-#define IMX6SL_CLK_SPDIF1_PRED 87
-#define IMX6SL_CLK_SPDIF1_PODF 88
-#define IMX6SL_CLK_EXTERN_AUDIO_PRED 89
-#define IMX6SL_CLK_EXTERN_AUDIO_PODF 90
-#define IMX6SL_CLK_ECSPI_ROOT 91
-#define IMX6SL_CLK_UART_ROOT 92
-#define IMX6SL_CLK_AHB 93
-#define IMX6SL_CLK_MMDC_ROOT 94
-#define IMX6SL_CLK_ARM 95
-#define IMX6SL_CLK_ECSPI1 96
-#define IMX6SL_CLK_ECSPI2 97
-#define IMX6SL_CLK_ECSPI3 98
-#define IMX6SL_CLK_ECSPI4 99
-#define IMX6SL_CLK_EPIT1 100
-#define IMX6SL_CLK_EPIT2 101
-#define IMX6SL_CLK_EXTERN_AUDIO 102
-#define IMX6SL_CLK_GPT 103
-#define IMX6SL_CLK_GPT_SERIAL 104
-#define IMX6SL_CLK_GPU2D_OVG 105
-#define IMX6SL_CLK_I2C1 106
-#define IMX6SL_CLK_I2C2 107
-#define IMX6SL_CLK_I2C3 108
-#define IMX6SL_CLK_OCOTP 109
-#define IMX6SL_CLK_CSI 110
-#define IMX6SL_CLK_PXP_AXI 111
-#define IMX6SL_CLK_EPDC_AXI 112
-#define IMX6SL_CLK_LCDIF_AXI 113
-#define IMX6SL_CLK_LCDIF_PIX 114
-#define IMX6SL_CLK_EPDC_PIX 115
-#define IMX6SL_CLK_OCRAM 116
-#define IMX6SL_CLK_PWM1 117
-#define IMX6SL_CLK_PWM2 118
-#define IMX6SL_CLK_PWM3 119
-#define IMX6SL_CLK_PWM4 120
-#define IMX6SL_CLK_SDMA 121
-#define IMX6SL_CLK_SPDIF 122
-#define IMX6SL_CLK_SSI1 123
-#define IMX6SL_CLK_SSI2 124
-#define IMX6SL_CLK_SSI3 125
-#define IMX6SL_CLK_UART 126
-#define IMX6SL_CLK_UART_SERIAL 127
-#define IMX6SL_CLK_USBOH3 128
-#define IMX6SL_CLK_USDHC1 129
-#define IMX6SL_CLK_USDHC2 130
-#define IMX6SL_CLK_USDHC3 131
-#define IMX6SL_CLK_USDHC4 132
-#define IMX6SL_CLK_PLL4_AUDIO_DIV 133
-#define IMX6SL_CLK_SPBA 134
-#define IMX6SL_CLK_ENET 135
-#define IMX6SL_CLK_LVDS1_SEL 136
-#define IMX6SL_CLK_LVDS1_OUT 137
-#define IMX6SL_CLK_LVDS1_IN 138
-#define IMX6SL_CLK_ANACLK1 139
-#define IMX6SL_PLL1_BYPASS_SRC 140
-#define IMX6SL_PLL2_BYPASS_SRC 141
-#define IMX6SL_PLL3_BYPASS_SRC 142
-#define IMX6SL_PLL4_BYPASS_SRC 143
-#define IMX6SL_PLL5_BYPASS_SRC 144
-#define IMX6SL_PLL6_BYPASS_SRC 145
-#define IMX6SL_PLL7_BYPASS_SRC 146
-#define IMX6SL_CLK_PLL1 147
-#define IMX6SL_CLK_PLL2 148
-#define IMX6SL_CLK_PLL3 149
-#define IMX6SL_CLK_PLL4 150
-#define IMX6SL_CLK_PLL5 151
-#define IMX6SL_CLK_PLL6 152
-#define IMX6SL_CLK_PLL7 153
-#define IMX6SL_PLL1_BYPASS 154
-#define IMX6SL_PLL2_BYPASS 155
-#define IMX6SL_PLL3_BYPASS 156
-#define IMX6SL_PLL4_BYPASS 157
-#define IMX6SL_PLL5_BYPASS 158
-#define IMX6SL_PLL6_BYPASS 159
-#define IMX6SL_PLL7_BYPASS 160
-#define IMX6SL_CLK_SSI1_IPG 161
-#define IMX6SL_CLK_SSI2_IPG 162
-#define IMX6SL_CLK_SSI3_IPG 163
-#define IMX6SL_CLK_SPDIF_GCLK 164
-#define IMX6SL_CLK_MMDC_P0_IPG 165
-#define IMX6SL_CLK_MMDC_P1_IPG 166
-#define IMX6SL_CLK_END 167
-
-#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */
diff --git a/include/dt-bindings/clock/imx6sll-clock.h b/include/dt-bindings/clock/imx6sll-clock.h
deleted file mode 100644
index 494fd0c..0000000
--- a/include/dt-bindings/clock/imx6sll-clock.h
+++ /dev/null
@@ -1,210 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2016 Freescale Semiconductor, Inc.
- * Copyright 2017-2018 NXP.
- *
- */
-
-#ifndef __DT_BINDINGS_CLOCK_IMX6SLL_H
-#define __DT_BINDINGS_CLOCK_IMX6SLL_H
-
-#define IMX6SLL_CLK_DUMMY 0
-#define IMX6SLL_CLK_CKIL 1
-#define IMX6SLL_CLK_OSC 2
-#define IMX6SLL_PLL1_BYPASS_SRC 3
-#define IMX6SLL_PLL2_BYPASS_SRC 4
-#define IMX6SLL_PLL3_BYPASS_SRC 5
-#define IMX6SLL_PLL4_BYPASS_SRC 6
-#define IMX6SLL_PLL5_BYPASS_SRC 7
-#define IMX6SLL_PLL6_BYPASS_SRC 8
-#define IMX6SLL_PLL7_BYPASS_SRC 9
-#define IMX6SLL_CLK_PLL1 10
-#define IMX6SLL_CLK_PLL2 11
-#define IMX6SLL_CLK_PLL3 12
-#define IMX6SLL_CLK_PLL4 13
-#define IMX6SLL_CLK_PLL5 14
-#define IMX6SLL_CLK_PLL6 15
-#define IMX6SLL_CLK_PLL7 16
-#define IMX6SLL_PLL1_BYPASS 17
-#define IMX6SLL_PLL2_BYPASS 18
-#define IMX6SLL_PLL3_BYPASS 19
-#define IMX6SLL_PLL4_BYPASS 20
-#define IMX6SLL_PLL5_BYPASS 21
-#define IMX6SLL_PLL6_BYPASS 22
-#define IMX6SLL_PLL7_BYPASS 23
-#define IMX6SLL_CLK_PLL1_SYS 24
-#define IMX6SLL_CLK_PLL2_BUS 25
-#define IMX6SLL_CLK_PLL3_USB_OTG 26
-#define IMX6SLL_CLK_PLL4_AUDIO 27
-#define IMX6SLL_CLK_PLL5_VIDEO 28
-#define IMX6SLL_CLK_PLL6_ENET 29
-#define IMX6SLL_CLK_PLL7_USB_HOST 30
-#define IMX6SLL_CLK_USBPHY1 31
-#define IMX6SLL_CLK_USBPHY2 32
-#define IMX6SLL_CLK_USBPHY1_GATE 33
-#define IMX6SLL_CLK_USBPHY2_GATE 34
-#define IMX6SLL_CLK_PLL2_PFD0 35
-#define IMX6SLL_CLK_PLL2_PFD1 36
-#define IMX6SLL_CLK_PLL2_PFD2 37
-#define IMX6SLL_CLK_PLL2_PFD3 38
-#define IMX6SLL_CLK_PLL3_PFD0 39
-#define IMX6SLL_CLK_PLL3_PFD1 40
-#define IMX6SLL_CLK_PLL3_PFD2 41
-#define IMX6SLL_CLK_PLL3_PFD3 42
-#define IMX6SLL_CLK_PLL4_POST_DIV 43
-#define IMX6SLL_CLK_PLL4_AUDIO_DIV 44
-#define IMX6SLL_CLK_PLL5_POST_DIV 45
-#define IMX6SLL_CLK_PLL5_VIDEO_DIV 46
-#define IMX6SLL_CLK_PLL2_198M 47
-#define IMX6SLL_CLK_PLL3_120M 48
-#define IMX6SLL_CLK_PLL3_80M 49
-#define IMX6SLL_CLK_PLL3_60M 50
-#define IMX6SLL_CLK_STEP 51
-#define IMX6SLL_CLK_PLL1_SW 52
-#define IMX6SLL_CLK_AXI_ALT_SEL 53
-#define IMX6SLL_CLK_AXI_SEL 54
-#define IMX6SLL_CLK_PERIPH_PRE 55
-#define IMX6SLL_CLK_PERIPH2_PRE 56
-#define IMX6SLL_CLK_PERIPH_CLK2_SEL 57
-#define IMX6SLL_CLK_PERIPH2_CLK2_SEL 58
-#define IMX6SLL_CLK_PERCLK_SEL 59
-#define IMX6SLL_CLK_USDHC1_SEL 60
-#define IMX6SLL_CLK_USDHC2_SEL 61
-#define IMX6SLL_CLK_USDHC3_SEL 62
-#define IMX6SLL_CLK_SSI1_SEL 63
-#define IMX6SLL_CLK_SSI2_SEL 64
-#define IMX6SLL_CLK_SSI3_SEL 65
-#define IMX6SLL_CLK_PXP_SEL 66
-#define IMX6SLL_CLK_LCDIF_PRE_SEL 67
-#define IMX6SLL_CLK_LCDIF_SEL 68
-#define IMX6SLL_CLK_EPDC_PRE_SEL 69
-#define IMX6SLL_CLK_SPDIF_SEL 70
-#define IMX6SLL_CLK_ECSPI_SEL 71
-#define IMX6SLL_CLK_UART_SEL 72
-#define IMX6SLL_CLK_ARM 73
-#define IMX6SLL_CLK_PERIPH 74
-#define IMX6SLL_CLK_PERIPH2 75
-#define IMX6SLL_CLK_PERIPH2_CLK2 76
-#define IMX6SLL_CLK_PERIPH_CLK2 77
-#define IMX6SLL_CLK_MMDC_PODF 78
-#define IMX6SLL_CLK_AXI_PODF 79
-#define IMX6SLL_CLK_AHB 80
-#define IMX6SLL_CLK_IPG 81
-#define IMX6SLL_CLK_PERCLK 82
-#define IMX6SLL_CLK_USDHC1_PODF 83
-#define IMX6SLL_CLK_USDHC2_PODF 84
-#define IMX6SLL_CLK_USDHC3_PODF 85
-#define IMX6SLL_CLK_SSI1_PRED 86
-#define IMX6SLL_CLK_SSI2_PRED 87
-#define IMX6SLL_CLK_SSI3_PRED 88
-#define IMX6SLL_CLK_SSI1_PODF 89
-#define IMX6SLL_CLK_SSI2_PODF 90
-#define IMX6SLL_CLK_SSI3_PODF 91
-#define IMX6SLL_CLK_PXP_PODF 92
-#define IMX6SLL_CLK_LCDIF_PRED 93
-#define IMX6SLL_CLK_LCDIF_PODF 94
-#define IMX6SLL_CLK_EPDC_SEL 95
-#define IMX6SLL_CLK_EPDC_PODF 96
-#define IMX6SLL_CLK_SPDIF_PRED 97
-#define IMX6SLL_CLK_SPDIF_PODF 98
-#define IMX6SLL_CLK_ECSPI_PODF 99
-#define IMX6SLL_CLK_UART_PODF 100
-
-/* CCGR 0 */
-#define IMX6SLL_CLK_AIPSTZ1 101
-#define IMX6SLL_CLK_AIPSTZ2 102
-#define IMX6SLL_CLK_DCP 103
-#define IMX6SLL_CLK_UART2_IPG 104
-#define IMX6SLL_CLK_UART2_SERIAL 105
-
-/* CCGR 1 */
-#define IMX6SLL_CLK_ECSPI1 106
-#define IMX6SLL_CLK_ECSPI2 107
-#define IMX6SLL_CLK_ECSPI3 108
-#define IMX6SLL_CLK_ECSPI4 109
-#define IMX6SLL_CLK_UART3_IPG 110
-#define IMX6SLL_CLK_UART3_SERIAL 111
-#define IMX6SLL_CLK_UART4_IPG 112
-#define IMX6SLL_CLK_UART4_SERIAL 113
-#define IMX6SLL_CLK_EPIT1 114
-#define IMX6SLL_CLK_EPIT2 115
-#define IMX6SLL_CLK_GPT_BUS 116
-#define IMX6SLL_CLK_GPT_SERIAL 117
-
-/* CCGR2 */
-#define IMX6SLL_CLK_CSI 118
-#define IMX6SLL_CLK_I2C1 119
-#define IMX6SLL_CLK_I2C2 120
-#define IMX6SLL_CLK_I2C3 121
-#define IMX6SLL_CLK_OCOTP 122
-#define IMX6SLL_CLK_LCDIF_APB 123
-#define IMX6SLL_CLK_PXP 124
-
-/* CCGR3 */
-#define IMX6SLL_CLK_UART5_IPG 125
-#define IMX6SLL_CLK_UART5_SERIAL 126
-#define IMX6SLL_CLK_EPDC_AXI 127
-#define IMX6SLL_CLK_EPDC_PIX 128
-#define IMX6SLL_CLK_LCDIF_PIX 129
-#define IMX6SLL_CLK_WDOG1 130
-#define IMX6SLL_CLK_MMDC_P0_FAST 131
-#define IMX6SLL_CLK_MMDC_P0_IPG 132
-#define IMX6SLL_CLK_OCRAM 133
-
-/* CCGR4 */
-#define IMX6SLL_CLK_PWM1 134
-#define IMX6SLL_CLK_PWM2 135
-#define IMX6SLL_CLK_PWM3 136
-#define IMX6SLL_CLK_PWM4 137
-
-/* CCGR 5 */
-#define IMX6SLL_CLK_ROM 138
-#define IMX6SLL_CLK_SDMA 139
-#define IMX6SLL_CLK_KPP 140
-#define IMX6SLL_CLK_WDOG2 141
-#define IMX6SLL_CLK_SPBA 142
-#define IMX6SLL_CLK_SPDIF 143
-#define IMX6SLL_CLK_SPDIF_GCLK 144
-#define IMX6SLL_CLK_SSI1 145
-#define IMX6SLL_CLK_SSI1_IPG 146
-#define IMX6SLL_CLK_SSI2 147
-#define IMX6SLL_CLK_SSI2_IPG 148
-#define IMX6SLL_CLK_SSI3 149
-#define IMX6SLL_CLK_SSI3_IPG 150
-#define IMX6SLL_CLK_UART1_IPG 151
-#define IMX6SLL_CLK_UART1_SERIAL 152
-
-/* CCGR 6 */
-#define IMX6SLL_CLK_USBOH3 153
-#define IMX6SLL_CLK_USDHC1 154
-#define IMX6SLL_CLK_USDHC2 155
-#define IMX6SLL_CLK_USDHC3 156
-
-#define IMX6SLL_CLK_IPP_DI0 157
-#define IMX6SLL_CLK_IPP_DI1 158
-#define IMX6SLL_CLK_LDB_DI0_SEL 159
-#define IMX6SLL_CLK_LDB_DI0_DIV_3_5 160
-#define IMX6SLL_CLK_LDB_DI0_DIV_7 161
-#define IMX6SLL_CLK_LDB_DI0_DIV_SEL 162
-#define IMX6SLL_CLK_LDB_DI0 163
-#define IMX6SLL_CLK_LDB_DI1_SEL 164
-#define IMX6SLL_CLK_LDB_DI1_DIV_3_5 165
-#define IMX6SLL_CLK_LDB_DI1_DIV_7 166
-#define IMX6SLL_CLK_LDB_DI1_DIV_SEL 167
-#define IMX6SLL_CLK_LDB_DI1 168
-#define IMX6SLL_CLK_EXTERN_AUDIO_SEL 169
-#define IMX6SLL_CLK_EXTERN_AUDIO_PRED 170
-#define IMX6SLL_CLK_EXTERN_AUDIO_PODF 171
-#define IMX6SLL_CLK_EXTERN_AUDIO 172
-
-#define IMX6SLL_CLK_GPIO1 173
-#define IMX6SLL_CLK_GPIO2 174
-#define IMX6SLL_CLK_GPIO3 175
-#define IMX6SLL_CLK_GPIO4 176
-#define IMX6SLL_CLK_GPIO5 177
-#define IMX6SLL_CLK_GPIO6 178
-#define IMX6SLL_CLK_MMDC_P1_IPG 179
-
-#define IMX6SLL_CLK_END 180
-
-#endif /* __DT_BINDINGS_CLOCK_IMX6SLL_H */
diff --git a/include/dt-bindings/clock/imx6sx-clock.h b/include/dt-bindings/clock/imx6sx-clock.h
deleted file mode 100644
index 1c64997..0000000
--- a/include/dt-bindings/clock/imx6sx-clock.h
+++ /dev/null
@@ -1,281 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2014 Freescale Semiconductor, Inc.
- */
-
-#ifndef __DT_BINDINGS_CLOCK_IMX6SX_H
-#define __DT_BINDINGS_CLOCK_IMX6SX_H
-
-#define IMX6SX_CLK_DUMMY 0
-#define IMX6SX_CLK_CKIL 1
-#define IMX6SX_CLK_CKIH 2
-#define IMX6SX_CLK_OSC 3
-#define IMX6SX_CLK_PLL1_SYS 4
-#define IMX6SX_CLK_PLL2_BUS 5
-#define IMX6SX_CLK_PLL3_USB_OTG 6
-#define IMX6SX_CLK_PLL4_AUDIO 7
-#define IMX6SX_CLK_PLL5_VIDEO 8
-#define IMX6SX_CLK_PLL6_ENET 9
-#define IMX6SX_CLK_PLL7_USB_HOST 10
-#define IMX6SX_CLK_USBPHY1 11
-#define IMX6SX_CLK_USBPHY2 12
-#define IMX6SX_CLK_USBPHY1_GATE 13
-#define IMX6SX_CLK_USBPHY2_GATE 14
-#define IMX6SX_CLK_PCIE_REF 15
-#define IMX6SX_CLK_PCIE_REF_125M 16
-#define IMX6SX_CLK_ENET_REF 17
-#define IMX6SX_CLK_PLL2_PFD0 18
-#define IMX6SX_CLK_PLL2_PFD1 19
-#define IMX6SX_CLK_PLL2_PFD2 20
-#define IMX6SX_CLK_PLL2_PFD3 21
-#define IMX6SX_CLK_PLL3_PFD0 22
-#define IMX6SX_CLK_PLL3_PFD1 23
-#define IMX6SX_CLK_PLL3_PFD2 24
-#define IMX6SX_CLK_PLL3_PFD3 25
-#define IMX6SX_CLK_PLL2_198M 26
-#define IMX6SX_CLK_PLL3_120M 27
-#define IMX6SX_CLK_PLL3_80M 28
-#define IMX6SX_CLK_PLL3_60M 29
-#define IMX6SX_CLK_TWD 30
-#define IMX6SX_CLK_PLL4_POST_DIV 31
-#define IMX6SX_CLK_PLL4_AUDIO_DIV 32
-#define IMX6SX_CLK_PLL5_POST_DIV 33
-#define IMX6SX_CLK_PLL5_VIDEO_DIV 34
-#define IMX6SX_CLK_STEP 35
-#define IMX6SX_CLK_PLL1_SW 36
-#define IMX6SX_CLK_OCRAM_SEL 37
-#define IMX6SX_CLK_PERIPH_PRE 38
-#define IMX6SX_CLK_PERIPH2_PRE 39
-#define IMX6SX_CLK_PERIPH_CLK2_SEL 40
-#define IMX6SX_CLK_PERIPH2_CLK2_SEL 41
-#define IMX6SX_CLK_PCIE_AXI_SEL 42
-#define IMX6SX_CLK_GPU_AXI_SEL 43
-#define IMX6SX_CLK_GPU_CORE_SEL 44
-#define IMX6SX_CLK_EIM_SLOW_SEL 45
-#define IMX6SX_CLK_USDHC1_SEL 46
-#define IMX6SX_CLK_USDHC2_SEL 47
-#define IMX6SX_CLK_USDHC3_SEL 48
-#define IMX6SX_CLK_USDHC4_SEL 49
-#define IMX6SX_CLK_SSI1_SEL 50
-#define IMX6SX_CLK_SSI2_SEL 51
-#define IMX6SX_CLK_SSI3_SEL 52
-#define IMX6SX_CLK_QSPI1_SEL 53
-#define IMX6SX_CLK_PERCLK_SEL 54
-#define IMX6SX_CLK_VID_SEL 55
-#define IMX6SX_CLK_ESAI_SEL 56
-#define IMX6SX_CLK_LDB_DI0_DIV_SEL 57
-#define IMX6SX_CLK_LDB_DI1_DIV_SEL 58
-#define IMX6SX_CLK_CAN_SEL 59
-#define IMX6SX_CLK_UART_SEL 60
-#define IMX6SX_CLK_QSPI2_SEL 61
-#define IMX6SX_CLK_LDB_DI1_SEL 62
-#define IMX6SX_CLK_LDB_DI0_SEL 63
-#define IMX6SX_CLK_SPDIF_SEL 64
-#define IMX6SX_CLK_AUDIO_SEL 65
-#define IMX6SX_CLK_ENET_PRE_SEL 66
-#define IMX6SX_CLK_ENET_SEL 67
-#define IMX6SX_CLK_M4_PRE_SEL 68
-#define IMX6SX_CLK_M4_SEL 69
-#define IMX6SX_CLK_ECSPI_SEL 70
-#define IMX6SX_CLK_LCDIF1_PRE_SEL 71
-#define IMX6SX_CLK_LCDIF2_PRE_SEL 72
-#define IMX6SX_CLK_LCDIF1_SEL 73
-#define IMX6SX_CLK_LCDIF2_SEL 74
-#define IMX6SX_CLK_DISPLAY_SEL 75
-#define IMX6SX_CLK_CSI_SEL 76
-#define IMX6SX_CLK_CKO1_SEL 77
-#define IMX6SX_CLK_CKO2_SEL 78
-#define IMX6SX_CLK_CKO 79
-#define IMX6SX_CLK_PERIPH_CLK2 80
-#define IMX6SX_CLK_PERIPH2_CLK2 81
-#define IMX6SX_CLK_IPG 82
-#define IMX6SX_CLK_GPU_CORE_PODF 83
-#define IMX6SX_CLK_GPU_AXI_PODF 84
-#define IMX6SX_CLK_LCDIF1_PODF 85
-#define IMX6SX_CLK_QSPI1_PODF 86
-#define IMX6SX_CLK_EIM_SLOW_PODF 87
-#define IMX6SX_CLK_LCDIF2_PODF 88
-#define IMX6SX_CLK_PERCLK 89
-#define IMX6SX_CLK_VID_PODF 90
-#define IMX6SX_CLK_CAN_PODF 91
-#define IMX6SX_CLK_USDHC1_PODF 92
-#define IMX6SX_CLK_USDHC2_PODF 93
-#define IMX6SX_CLK_USDHC3_PODF 94
-#define IMX6SX_CLK_USDHC4_PODF 95
-#define IMX6SX_CLK_UART_PODF 96
-#define IMX6SX_CLK_ESAI_PRED 97
-#define IMX6SX_CLK_ESAI_PODF 98
-#define IMX6SX_CLK_SSI3_PRED 99
-#define IMX6SX_CLK_SSI3_PODF 100
-#define IMX6SX_CLK_SSI1_PRED 101
-#define IMX6SX_CLK_SSI1_PODF 102
-#define IMX6SX_CLK_QSPI2_PRED 103
-#define IMX6SX_CLK_QSPI2_PODF 104
-#define IMX6SX_CLK_SSI2_PRED 105
-#define IMX6SX_CLK_SSI2_PODF 106
-#define IMX6SX_CLK_SPDIF_PRED 107
-#define IMX6SX_CLK_SPDIF_PODF 108
-#define IMX6SX_CLK_AUDIO_PRED 109
-#define IMX6SX_CLK_AUDIO_PODF 110
-#define IMX6SX_CLK_ENET_PODF 111
-#define IMX6SX_CLK_M4_PODF 112
-#define IMX6SX_CLK_ECSPI_PODF 113
-#define IMX6SX_CLK_LCDIF1_PRED 114
-#define IMX6SX_CLK_LCDIF2_PRED 115
-#define IMX6SX_CLK_DISPLAY_PODF 116
-#define IMX6SX_CLK_CSI_PODF 117
-#define IMX6SX_CLK_LDB_DI0_DIV_3_5 118
-#define IMX6SX_CLK_LDB_DI0_DIV_7 119
-#define IMX6SX_CLK_LDB_DI1_DIV_3_5 120
-#define IMX6SX_CLK_LDB_DI1_DIV_7 121
-#define IMX6SX_CLK_CKO1_PODF 122
-#define IMX6SX_CLK_CKO2_PODF 123
-#define IMX6SX_CLK_PERIPH 124
-#define IMX6SX_CLK_PERIPH2 125
-#define IMX6SX_CLK_OCRAM 126
-#define IMX6SX_CLK_AHB 127
-#define IMX6SX_CLK_MMDC_PODF 128
-#define IMX6SX_CLK_ARM 129
-#define IMX6SX_CLK_AIPS_TZ1 130
-#define IMX6SX_CLK_AIPS_TZ2 131
-#define IMX6SX_CLK_APBH_DMA 132
-#define IMX6SX_CLK_ASRC_GATE 133
-#define IMX6SX_CLK_CAAM_MEM 134
-#define IMX6SX_CLK_CAAM_ACLK 135
-#define IMX6SX_CLK_CAAM_IPG 136
-#define IMX6SX_CLK_CAN1_IPG 137
-#define IMX6SX_CLK_CAN1_SERIAL 138
-#define IMX6SX_CLK_CAN2_IPG 139
-#define IMX6SX_CLK_CAN2_SERIAL 140
-#define IMX6SX_CLK_CPU_DEBUG 141
-#define IMX6SX_CLK_DCIC1 142
-#define IMX6SX_CLK_DCIC2 143
-#define IMX6SX_CLK_AIPS_TZ3 144
-#define IMX6SX_CLK_ECSPI1 145
-#define IMX6SX_CLK_ECSPI2 146
-#define IMX6SX_CLK_ECSPI3 147
-#define IMX6SX_CLK_ECSPI4 148
-#define IMX6SX_CLK_ECSPI5 149
-#define IMX6SX_CLK_EPIT1 150
-#define IMX6SX_CLK_EPIT2 151
-#define IMX6SX_CLK_ESAI_EXTAL 152
-#define IMX6SX_CLK_WAKEUP 153
-#define IMX6SX_CLK_GPT_BUS 154
-#define IMX6SX_CLK_GPT_SERIAL 155
-#define IMX6SX_CLK_GPU 156
-#define IMX6SX_CLK_OCRAM_S 157
-#define IMX6SX_CLK_CANFD 158
-#define IMX6SX_CLK_CSI 159
-#define IMX6SX_CLK_I2C1 160
-#define IMX6SX_CLK_I2C2 161
-#define IMX6SX_CLK_I2C3 162
-#define IMX6SX_CLK_OCOTP 163
-#define IMX6SX_CLK_IOMUXC 164
-#define IMX6SX_CLK_IPMUX1 165
-#define IMX6SX_CLK_IPMUX2 166
-#define IMX6SX_CLK_IPMUX3 167
-#define IMX6SX_CLK_TZASC1 168
-#define IMX6SX_CLK_LCDIF_APB 169
-#define IMX6SX_CLK_PXP_AXI 170
-#define IMX6SX_CLK_M4 171
-#define IMX6SX_CLK_ENET 172
-#define IMX6SX_CLK_DISPLAY_AXI 173
-#define IMX6SX_CLK_LCDIF2_PIX 174
-#define IMX6SX_CLK_LCDIF1_PIX 175
-#define IMX6SX_CLK_LDB_DI0 176
-#define IMX6SX_CLK_QSPI1 177
-#define IMX6SX_CLK_MLB 178
-#define IMX6SX_CLK_MMDC_P0_FAST 179
-#define IMX6SX_CLK_MMDC_P0_IPG 180
-#define IMX6SX_CLK_AXI 181
-#define IMX6SX_CLK_PCIE_AXI 182
-#define IMX6SX_CLK_QSPI2 183
-#define IMX6SX_CLK_PER1_BCH 184
-#define IMX6SX_CLK_PER2_MAIN 185
-#define IMX6SX_CLK_PWM1 186
-#define IMX6SX_CLK_PWM2 187
-#define IMX6SX_CLK_PWM3 188
-#define IMX6SX_CLK_PWM4 189
-#define IMX6SX_CLK_GPMI_BCH_APB 190
-#define IMX6SX_CLK_GPMI_BCH 191
-#define IMX6SX_CLK_GPMI_IO 192
-#define IMX6SX_CLK_GPMI_APB 193
-#define IMX6SX_CLK_ROM 194
-#define IMX6SX_CLK_SDMA 195
-#define IMX6SX_CLK_SPBA 196
-#define IMX6SX_CLK_SPDIF 197
-#define IMX6SX_CLK_SSI1_IPG 198
-#define IMX6SX_CLK_SSI2_IPG 199
-#define IMX6SX_CLK_SSI3_IPG 200
-#define IMX6SX_CLK_SSI1 201
-#define IMX6SX_CLK_SSI2 202
-#define IMX6SX_CLK_SSI3 203
-#define IMX6SX_CLK_UART_IPG 204
-#define IMX6SX_CLK_UART_SERIAL 205
-#define IMX6SX_CLK_SAI1 206
-#define IMX6SX_CLK_SAI2 207
-#define IMX6SX_CLK_USBOH3 208
-#define IMX6SX_CLK_USDHC1 209
-#define IMX6SX_CLK_USDHC2 210
-#define IMX6SX_CLK_USDHC3 211
-#define IMX6SX_CLK_USDHC4 212
-#define IMX6SX_CLK_EIM_SLOW 213
-#define IMX6SX_CLK_PWM8 214
-#define IMX6SX_CLK_VADC 215
-#define IMX6SX_CLK_GIS 216
-#define IMX6SX_CLK_I2C4 217
-#define IMX6SX_CLK_PWM5 218
-#define IMX6SX_CLK_PWM6 219
-#define IMX6SX_CLK_PWM7 220
-#define IMX6SX_CLK_CKO1 221
-#define IMX6SX_CLK_CKO2 222
-#define IMX6SX_CLK_IPP_DI0 223
-#define IMX6SX_CLK_IPP_DI1 224
-#define IMX6SX_CLK_ENET_AHB 225
-#define IMX6SX_CLK_OCRAM_PODF 226
-#define IMX6SX_CLK_GPT_3M 227
-#define IMX6SX_CLK_ENET_PTP 228
-#define IMX6SX_CLK_ENET_PTP_REF 229
-#define IMX6SX_CLK_ENET2_REF 230
-#define IMX6SX_CLK_ENET2_REF_125M 231
-#define IMX6SX_CLK_AUDIO 232
-#define IMX6SX_CLK_LVDS1_SEL 233
-#define IMX6SX_CLK_LVDS1_OUT 234
-#define IMX6SX_CLK_ASRC_IPG 235
-#define IMX6SX_CLK_ASRC_MEM 236
-#define IMX6SX_CLK_SAI1_IPG 237
-#define IMX6SX_CLK_SAI2_IPG 238
-#define IMX6SX_CLK_ESAI_IPG 239
-#define IMX6SX_CLK_ESAI_MEM 240
-#define IMX6SX_CLK_LVDS1_IN 241
-#define IMX6SX_CLK_ANACLK1 242
-#define IMX6SX_PLL1_BYPASS_SRC 243
-#define IMX6SX_PLL2_BYPASS_SRC 244
-#define IMX6SX_PLL3_BYPASS_SRC 245
-#define IMX6SX_PLL4_BYPASS_SRC 246
-#define IMX6SX_PLL5_BYPASS_SRC 247
-#define IMX6SX_PLL6_BYPASS_SRC 248
-#define IMX6SX_PLL7_BYPASS_SRC 249
-#define IMX6SX_CLK_PLL1 250
-#define IMX6SX_CLK_PLL2 251
-#define IMX6SX_CLK_PLL3 252
-#define IMX6SX_CLK_PLL4 253
-#define IMX6SX_CLK_PLL5 254
-#define IMX6SX_CLK_PLL6 255
-#define IMX6SX_CLK_PLL7 256
-#define IMX6SX_PLL1_BYPASS 257
-#define IMX6SX_PLL2_BYPASS 258
-#define IMX6SX_PLL3_BYPASS 259
-#define IMX6SX_PLL4_BYPASS 260
-#define IMX6SX_PLL5_BYPASS 261
-#define IMX6SX_PLL6_BYPASS 262
-#define IMX6SX_PLL7_BYPASS 263
-#define IMX6SX_CLK_SPDIF_GCLK 264
-#define IMX6SX_CLK_LVDS2_SEL 265
-#define IMX6SX_CLK_LVDS2_OUT 266
-#define IMX6SX_CLK_LVDS2_IN 267
-#define IMX6SX_CLK_ANACLK2 268
-#define IMX6SX_CLK_MMDC_P1_IPG 269
-#define IMX6SX_CLK_CLK_END 270
-
-#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */
diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h
deleted file mode 100644
index 7909433..0000000
--- a/include/dt-bindings/clock/imx6ul-clock.h
+++ /dev/null
@@ -1,262 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2015 Freescale Semiconductor, Inc.
- */
-
-#ifndef __DT_BINDINGS_CLOCK_IMX6UL_H
-#define __DT_BINDINGS_CLOCK_IMX6UL_H
-
-#define IMX6UL_CLK_DUMMY 0
-#define IMX6UL_CLK_CKIL 1
-#define IMX6UL_CLK_CKIH 2
-#define IMX6UL_CLK_OSC 3
-#define IMX6UL_PLL1_BYPASS_SRC 4
-#define IMX6UL_PLL2_BYPASS_SRC 5
-#define IMX6UL_PLL3_BYPASS_SRC 6
-#define IMX6UL_PLL4_BYPASS_SRC 7
-#define IMX6UL_PLL5_BYPASS_SRC 8
-#define IMX6UL_PLL6_BYPASS_SRC 9
-#define IMX6UL_PLL7_BYPASS_SRC 10
-#define IMX6UL_CLK_PLL1 11
-#define IMX6UL_CLK_PLL2 12
-#define IMX6UL_CLK_PLL3 13
-#define IMX6UL_CLK_PLL4 14
-#define IMX6UL_CLK_PLL5 15
-#define IMX6UL_CLK_PLL6 16
-#define IMX6UL_CLK_PLL7 17
-#define IMX6UL_PLL1_BYPASS 18
-#define IMX6UL_PLL2_BYPASS 19
-#define IMX6UL_PLL3_BYPASS 20
-#define IMX6UL_PLL4_BYPASS 21
-#define IMX6UL_PLL5_BYPASS 22
-#define IMX6UL_PLL6_BYPASS 23
-#define IMX6UL_PLL7_BYPASS 24
-#define IMX6UL_CLK_PLL1_SYS 25
-#define IMX6UL_CLK_PLL2_BUS 26
-#define IMX6UL_CLK_PLL3_USB_OTG 27
-#define IMX6UL_CLK_PLL4_AUDIO 28
-#define IMX6UL_CLK_PLL5_VIDEO 29
-#define IMX6UL_CLK_PLL6_ENET 30
-#define IMX6UL_CLK_PLL7_USB_HOST 31
-#define IMX6UL_CLK_USBPHY1 32
-#define IMX6UL_CLK_USBPHY2 33
-#define IMX6UL_CLK_USBPHY1_GATE 34
-#define IMX6UL_CLK_USBPHY2_GATE 35
-#define IMX6UL_CLK_PLL2_PFD0 36
-#define IMX6UL_CLK_PLL2_PFD1 37
-#define IMX6UL_CLK_PLL2_PFD2 38
-#define IMX6UL_CLK_PLL2_PFD3 39
-#define IMX6UL_CLK_PLL3_PFD0 40
-#define IMX6UL_CLK_PLL3_PFD1 41
-#define IMX6UL_CLK_PLL3_PFD2 42
-#define IMX6UL_CLK_PLL3_PFD3 43
-#define IMX6UL_CLK_ENET_REF 44
-#define IMX6UL_CLK_ENET2_REF 45
-#define IMX6UL_CLK_ENET2_REF_125M 46
-#define IMX6UL_CLK_ENET_PTP_REF 47
-#define IMX6UL_CLK_ENET_PTP 48
-#define IMX6UL_CLK_PLL4_POST_DIV 49
-#define IMX6UL_CLK_PLL4_AUDIO_DIV 50
-#define IMX6UL_CLK_PLL5_POST_DIV 51
-#define IMX6UL_CLK_PLL5_VIDEO_DIV 52
-#define IMX6UL_CLK_PLL2_198M 53
-#define IMX6UL_CLK_PLL3_80M 54
-#define IMX6UL_CLK_PLL3_60M 55
-#define IMX6UL_CLK_STEP 56
-#define IMX6UL_CLK_PLL1_SW 57
-#define IMX6UL_CLK_AXI_ALT_SEL 58
-#define IMX6UL_CLK_AXI_SEL 59
-#define IMX6UL_CLK_PERIPH_PRE 60
-#define IMX6UL_CLK_PERIPH2_PRE 61
-#define IMX6UL_CLK_PERIPH_CLK2_SEL 62
-#define IMX6UL_CLK_PERIPH2_CLK2_SEL 63
-#define IMX6UL_CLK_USDHC1_SEL 64
-#define IMX6UL_CLK_USDHC2_SEL 65
-#define IMX6UL_CLK_BCH_SEL 66
-#define IMX6UL_CLK_GPMI_SEL 67
-#define IMX6UL_CLK_EIM_SLOW_SEL 68
-#define IMX6UL_CLK_SPDIF_SEL 69
-#define IMX6UL_CLK_SAI1_SEL 70
-#define IMX6UL_CLK_SAI2_SEL 71
-#define IMX6UL_CLK_SAI3_SEL 72
-#define IMX6UL_CLK_LCDIF_PRE_SEL 73
-#define IMX6UL_CLK_SIM_PRE_SEL 74
-#define IMX6UL_CLK_LDB_DI0_SEL 75
-#define IMX6UL_CLK_LDB_DI1_SEL 76
-#define IMX6UL_CLK_ENFC_SEL 77
-#define IMX6UL_CLK_CAN_SEL 78
-#define IMX6UL_CLK_ECSPI_SEL 79
-#define IMX6UL_CLK_UART_SEL 80
-#define IMX6UL_CLK_QSPI1_SEL 81
-#define IMX6UL_CLK_PERCLK_SEL 82
-#define IMX6UL_CLK_LCDIF_SEL 83
-#define IMX6UL_CLK_SIM_SEL 84
-#define IMX6UL_CLK_PERIPH 85
-#define IMX6UL_CLK_PERIPH2 86
-#define IMX6UL_CLK_LDB_DI0_DIV_3_5 87
-#define IMX6UL_CLK_LDB_DI0_DIV_7 88
-#define IMX6UL_CLK_LDB_DI1_DIV_3_5 89
-#define IMX6UL_CLK_LDB_DI1_DIV_7 90
-#define IMX6UL_CLK_LDB_DI0_DIV_SEL 91
-#define IMX6UL_CLK_LDB_DI1_DIV_SEL 92
-#define IMX6UL_CLK_ARM 93
-#define IMX6UL_CLK_PERIPH_CLK2 94
-#define IMX6UL_CLK_PERIPH2_CLK2 95
-#define IMX6UL_CLK_AHB 96
-#define IMX6UL_CLK_MMDC_PODF 97
-#define IMX6UL_CLK_AXI_PODF 98
-#define IMX6UL_CLK_PERCLK 99
-#define IMX6UL_CLK_IPG 100
-#define IMX6UL_CLK_USDHC1_PODF 101
-#define IMX6UL_CLK_USDHC2_PODF 102
-#define IMX6UL_CLK_BCH_PODF 103
-#define IMX6UL_CLK_GPMI_PODF 104
-#define IMX6UL_CLK_EIM_SLOW_PODF 105
-#define IMX6UL_CLK_SPDIF_PRED 106
-#define IMX6UL_CLK_SPDIF_PODF 107
-#define IMX6UL_CLK_SAI1_PRED 108
-#define IMX6UL_CLK_SAI1_PODF 109
-#define IMX6UL_CLK_SAI2_PRED 110
-#define IMX6UL_CLK_SAI2_PODF 111
-#define IMX6UL_CLK_SAI3_PRED 112
-#define IMX6UL_CLK_SAI3_PODF 113
-#define IMX6UL_CLK_LCDIF_PRED 114
-#define IMX6UL_CLK_LCDIF_PODF 115
-#define IMX6UL_CLK_SIM_PODF 116
-#define IMX6UL_CLK_QSPI1_PDOF 117
-#define IMX6UL_CLK_ENFC_PRED 118
-#define IMX6UL_CLK_ENFC_PODF 119
-#define IMX6UL_CLK_CAN_PODF 120
-#define IMX6UL_CLK_ECSPI_PODF 121
-#define IMX6UL_CLK_UART_PODF 122
-#define IMX6UL_CLK_ADC1 123
-#define IMX6UL_CLK_ADC2 124
-#define IMX6UL_CLK_AIPSTZ1 125
-#define IMX6UL_CLK_AIPSTZ2 126
-#define IMX6UL_CLK_AIPSTZ3 127
-#define IMX6UL_CLK_APBHDMA 128
-#define IMX6UL_CLK_ASRC_IPG 129
-#define IMX6UL_CLK_ASRC_MEM 130
-#define IMX6UL_CLK_GPMI_BCH_APB 131
-#define IMX6UL_CLK_GPMI_BCH 132
-#define IMX6UL_CLK_GPMI_IO 133
-#define IMX6UL_CLK_GPMI_APB 134
-#define IMX6UL_CLK_CAAM_MEM 135
-#define IMX6UL_CLK_CAAM_ACLK 136
-#define IMX6UL_CLK_CAAM_IPG 137
-#define IMX6UL_CLK_CSI 138
-#define IMX6UL_CLK_ECSPI1 139
-#define IMX6UL_CLK_ECSPI2 140
-#define IMX6UL_CLK_ECSPI3 141
-#define IMX6UL_CLK_ECSPI4 142
-#define IMX6UL_CLK_EIM 143
-#define IMX6UL_CLK_ENET 144
-#define IMX6UL_CLK_ENET_AHB 145
-#define IMX6UL_CLK_EPIT1 146
-#define IMX6UL_CLK_EPIT2 147
-#define IMX6UL_CLK_CAN1_IPG 148
-#define IMX6UL_CLK_CAN1_SERIAL 149
-#define IMX6UL_CLK_CAN2_IPG 150
-#define IMX6UL_CLK_CAN2_SERIAL 151
-#define IMX6UL_CLK_GPT1_BUS 152
-#define IMX6UL_CLK_GPT1_SERIAL 153
-#define IMX6UL_CLK_GPT2_BUS 154
-#define IMX6UL_CLK_GPT2_SERIAL 155
-#define IMX6UL_CLK_I2C1 156
-#define IMX6UL_CLK_I2C2 157
-#define IMX6UL_CLK_I2C3 158
-#define IMX6UL_CLK_I2C4 159
-#define IMX6UL_CLK_IOMUXC 160
-#define IMX6UL_CLK_LCDIF_APB 161
-#define IMX6UL_CLK_LCDIF_PIX 162
-#define IMX6UL_CLK_MMDC_P0_FAST 163
-#define IMX6UL_CLK_MMDC_P0_IPG 164
-#define IMX6UL_CLK_OCOTP 165
-#define IMX6UL_CLK_OCRAM 166
-#define IMX6UL_CLK_PWM1 167
-#define IMX6UL_CLK_PWM2 168
-#define IMX6UL_CLK_PWM3 169
-#define IMX6UL_CLK_PWM4 170
-#define IMX6UL_CLK_PWM5 171
-#define IMX6UL_CLK_PWM6 172
-#define IMX6UL_CLK_PWM7 173
-#define IMX6UL_CLK_PWM8 174
-#define IMX6UL_CLK_PXP 175
-#define IMX6UL_CLK_QSPI 176
-#define IMX6UL_CLK_ROM 177
-#define IMX6UL_CLK_SAI1 178
-#define IMX6UL_CLK_SAI1_IPG 179
-#define IMX6UL_CLK_SAI2 180
-#define IMX6UL_CLK_SAI2_IPG 181
-#define IMX6UL_CLK_SAI3 182
-#define IMX6UL_CLK_SAI3_IPG 183
-#define IMX6UL_CLK_SDMA 184
-#define IMX6UL_CLK_SIM 185
-#define IMX6UL_CLK_SIM_S 186
-#define IMX6UL_CLK_SPBA 187
-#define IMX6UL_CLK_SPDIF 188
-#define IMX6UL_CLK_UART1_IPG 189
-#define IMX6UL_CLK_UART1_SERIAL 190
-#define IMX6UL_CLK_UART2_IPG 191
-#define IMX6UL_CLK_UART2_SERIAL 192
-#define IMX6UL_CLK_UART3_IPG 193
-#define IMX6UL_CLK_UART3_SERIAL 194
-#define IMX6UL_CLK_UART4_IPG 195
-#define IMX6UL_CLK_UART4_SERIAL 196
-#define IMX6UL_CLK_UART5_IPG 197
-#define IMX6UL_CLK_UART5_SERIAL 198
-#define IMX6UL_CLK_UART6_IPG 199
-#define IMX6UL_CLK_UART6_SERIAL 200
-#define IMX6UL_CLK_UART7_IPG 201
-#define IMX6UL_CLK_UART7_SERIAL 202
-#define IMX6UL_CLK_UART8_IPG 203
-#define IMX6UL_CLK_UART8_SERIAL 204
-#define IMX6UL_CLK_USBOH3 205
-#define IMX6UL_CLK_USDHC1 206
-#define IMX6UL_CLK_USDHC2 207
-#define IMX6UL_CLK_WDOG1 208
-#define IMX6UL_CLK_WDOG2 209
-#define IMX6UL_CLK_WDOG3 210
-#define IMX6UL_CLK_LDB_DI0 211
-#define IMX6UL_CLK_AXI 212
-#define IMX6UL_CLK_SPDIF_GCLK 213
-#define IMX6UL_CLK_GPT_3M 214
-#define IMX6UL_CLK_SIM2 215
-#define IMX6UL_CLK_SIM1 216
-#define IMX6UL_CLK_IPP_DI0 217
-#define IMX6UL_CLK_IPP_DI1 218
-#define IMX6UL_CA7_SECONDARY_SEL 219
-#define IMX6UL_CLK_PER_BCH 220
-#define IMX6UL_CLK_CSI_SEL 221
-#define IMX6UL_CLK_CSI_PODF 222
-#define IMX6UL_CLK_PLL3_120M 223
-#define IMX6UL_CLK_KPP 224
-#define IMX6ULL_CLK_ESAI_PRED 225
-#define IMX6ULL_CLK_ESAI_PODF 226
-#define IMX6ULL_CLK_ESAI_EXTAL 227
-#define IMX6ULL_CLK_ESAI_MEM 228
-#define IMX6ULL_CLK_ESAI_IPG 229
-#define IMX6ULL_CLK_DCP_CLK 230
-#define IMX6ULL_CLK_EPDC_PRE_SEL 231
-#define IMX6ULL_CLK_EPDC_SEL 232
-#define IMX6ULL_CLK_EPDC_PODF 233
-#define IMX6ULL_CLK_EPDC_ACLK 234
-#define IMX6ULL_CLK_EPDC_PIX 235
-#define IMX6ULL_CLK_ESAI_SEL 236
-#define IMX6UL_CLK_CKO1_SEL 237
-#define IMX6UL_CLK_CKO1_PODF 238
-#define IMX6UL_CLK_CKO1 239
-#define IMX6UL_CLK_CKO2_SEL 240
-#define IMX6UL_CLK_CKO2_PODF 241
-#define IMX6UL_CLK_CKO2 242
-#define IMX6UL_CLK_CKO 243
-#define IMX6UL_CLK_GPIO1 244
-#define IMX6UL_CLK_GPIO2 245
-#define IMX6UL_CLK_GPIO3 246
-#define IMX6UL_CLK_GPIO4 247
-#define IMX6UL_CLK_GPIO5 248
-#define IMX6UL_CLK_MMDC_P1_IPG 249
-
-#define IMX6UL_CLK_END 250
-
-#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */
diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h
deleted file mode 100644
index 1d4c0df..0000000
--- a/include/dt-bindings/clock/imx7d-clock.h
+++ /dev/null
@@ -1,456 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
- */
-
-#ifndef __DT_BINDINGS_CLOCK_IMX7D_H
-#define __DT_BINDINGS_CLOCK_IMX7D_H
-
-#define IMX7D_OSC_24M_CLK 0
-#define IMX7D_PLL_ARM_MAIN 1
-#define IMX7D_PLL_ARM_MAIN_CLK 2
-#define IMX7D_PLL_ARM_MAIN_SRC 3
-#define IMX7D_PLL_ARM_MAIN_BYPASS 4
-#define IMX7D_PLL_SYS_MAIN 5
-#define IMX7D_PLL_SYS_MAIN_CLK 6
-#define IMX7D_PLL_SYS_MAIN_SRC 7
-#define IMX7D_PLL_SYS_MAIN_BYPASS 8
-#define IMX7D_PLL_SYS_MAIN_480M 9
-#define IMX7D_PLL_SYS_MAIN_240M 10
-#define IMX7D_PLL_SYS_MAIN_120M 11
-#define IMX7D_PLL_SYS_MAIN_480M_CLK 12
-#define IMX7D_PLL_SYS_MAIN_240M_CLK 13
-#define IMX7D_PLL_SYS_MAIN_120M_CLK 14
-#define IMX7D_PLL_SYS_PFD0_392M_CLK 15
-#define IMX7D_PLL_SYS_PFD0_196M 16
-#define IMX7D_PLL_SYS_PFD0_196M_CLK 17
-#define IMX7D_PLL_SYS_PFD1_332M_CLK 18
-#define IMX7D_PLL_SYS_PFD1_166M 19
-#define IMX7D_PLL_SYS_PFD1_166M_CLK 20
-#define IMX7D_PLL_SYS_PFD2_270M_CLK 21
-#define IMX7D_PLL_SYS_PFD2_135M 22
-#define IMX7D_PLL_SYS_PFD2_135M_CLK 23
-#define IMX7D_PLL_SYS_PFD3_CLK 24
-#define IMX7D_PLL_SYS_PFD4_CLK 25
-#define IMX7D_PLL_SYS_PFD5_CLK 26
-#define IMX7D_PLL_SYS_PFD6_CLK 27
-#define IMX7D_PLL_SYS_PFD7_CLK 28
-#define IMX7D_PLL_ENET_MAIN 29
-#define IMX7D_PLL_ENET_MAIN_CLK 30
-#define IMX7D_PLL_ENET_MAIN_SRC 31
-#define IMX7D_PLL_ENET_MAIN_BYPASS 32
-#define IMX7D_PLL_ENET_MAIN_500M 33
-#define IMX7D_PLL_ENET_MAIN_250M 34
-#define IMX7D_PLL_ENET_MAIN_125M 35
-#define IMX7D_PLL_ENET_MAIN_100M 36
-#define IMX7D_PLL_ENET_MAIN_50M 37
-#define IMX7D_PLL_ENET_MAIN_40M 38
-#define IMX7D_PLL_ENET_MAIN_25M 39
-#define IMX7D_PLL_ENET_MAIN_500M_CLK 40
-#define IMX7D_PLL_ENET_MAIN_250M_CLK 41
-#define IMX7D_PLL_ENET_MAIN_125M_CLK 42
-#define IMX7D_PLL_ENET_MAIN_100M_CLK 43
-#define IMX7D_PLL_ENET_MAIN_50M_CLK 44
-#define IMX7D_PLL_ENET_MAIN_40M_CLK 45
-#define IMX7D_PLL_ENET_MAIN_25M_CLK 46
-#define IMX7D_PLL_DRAM_MAIN 47
-#define IMX7D_PLL_DRAM_MAIN_CLK 48
-#define IMX7D_PLL_DRAM_MAIN_SRC 49
-#define IMX7D_PLL_DRAM_MAIN_BYPASS 50
-#define IMX7D_PLL_DRAM_MAIN_533M 51
-#define IMX7D_PLL_DRAM_MAIN_533M_CLK 52
-#define IMX7D_PLL_AUDIO_MAIN 53
-#define IMX7D_PLL_AUDIO_MAIN_CLK 54
-#define IMX7D_PLL_AUDIO_MAIN_SRC 55
-#define IMX7D_PLL_AUDIO_MAIN_BYPASS 56
-#define IMX7D_PLL_VIDEO_MAIN_CLK 57
-#define IMX7D_PLL_VIDEO_MAIN 58
-#define IMX7D_PLL_VIDEO_MAIN_SRC 59
-#define IMX7D_PLL_VIDEO_MAIN_BYPASS 60
-#define IMX7D_USB_MAIN_480M_CLK 61
-#define IMX7D_ARM_A7_ROOT_CLK 62
-#define IMX7D_ARM_A7_ROOT_SRC 63
-#define IMX7D_ARM_A7_ROOT_CG 64
-#define IMX7D_ARM_A7_ROOT_DIV 65
-#define IMX7D_ARM_M4_ROOT_CLK 66
-#define IMX7D_ARM_M4_ROOT_SRC 67
-#define IMX7D_ARM_M4_ROOT_CG 68
-#define IMX7D_ARM_M4_ROOT_DIV 69
-#define IMX7D_ARM_M0_ROOT_CLK 70 /* unused */
-#define IMX7D_ARM_M0_ROOT_SRC 71 /* unused */
-#define IMX7D_ARM_M0_ROOT_CG 72 /* unused */
-#define IMX7D_ARM_M0_ROOT_DIV 73 /* unused */
-#define IMX7D_MAIN_AXI_ROOT_CLK 74
-#define IMX7D_MAIN_AXI_ROOT_SRC 75
-#define IMX7D_MAIN_AXI_ROOT_CG 76
-#define IMX7D_MAIN_AXI_ROOT_DIV 77
-#define IMX7D_DISP_AXI_ROOT_CLK 78
-#define IMX7D_DISP_AXI_ROOT_SRC 79
-#define IMX7D_DISP_AXI_ROOT_CG 80
-#define IMX7D_DISP_AXI_ROOT_DIV 81
-#define IMX7D_ENET_AXI_ROOT_CLK 82
-#define IMX7D_ENET_AXI_ROOT_SRC 83
-#define IMX7D_ENET_AXI_ROOT_CG 84
-#define IMX7D_ENET_AXI_ROOT_DIV 85
-#define IMX7D_NAND_USDHC_BUS_ROOT_CLK 86
-#define IMX7D_NAND_USDHC_BUS_ROOT_SRC 87
-#define IMX7D_NAND_USDHC_BUS_ROOT_CG 88
-#define IMX7D_NAND_USDHC_BUS_ROOT_DIV 89
-#define IMX7D_AHB_CHANNEL_ROOT_CLK 90
-#define IMX7D_AHB_CHANNEL_ROOT_SRC 91
-#define IMX7D_AHB_CHANNEL_ROOT_CG 92
-#define IMX7D_AHB_CHANNEL_ROOT_DIV 93
-#define IMX7D_DRAM_PHYM_ROOT_CLK 94
-#define IMX7D_DRAM_PHYM_ROOT_SRC 95
-#define IMX7D_DRAM_PHYM_ROOT_CG 96
-#define IMX7D_DRAM_PHYM_ROOT_DIV 97
-#define IMX7D_DRAM_ROOT_CLK 98
-#define IMX7D_DRAM_ROOT_SRC 99
-#define IMX7D_DRAM_ROOT_CG 100
-#define IMX7D_DRAM_ROOT_DIV 101
-#define IMX7D_DRAM_PHYM_ALT_ROOT_CLK 102
-#define IMX7D_DRAM_PHYM_ALT_ROOT_SRC 103
-#define IMX7D_DRAM_PHYM_ALT_ROOT_CG 104
-#define IMX7D_DRAM_PHYM_ALT_ROOT_DIV 105
-#define IMX7D_DRAM_ALT_ROOT_CLK 106
-#define IMX7D_DRAM_ALT_ROOT_SRC 107
-#define IMX7D_DRAM_ALT_ROOT_CG 108
-#define IMX7D_DRAM_ALT_ROOT_DIV 109
-#define IMX7D_USB_HSIC_ROOT_CLK 110
-#define IMX7D_USB_HSIC_ROOT_SRC 111
-#define IMX7D_USB_HSIC_ROOT_CG 112
-#define IMX7D_USB_HSIC_ROOT_DIV 113
-#define IMX7D_PCIE_CTRL_ROOT_CLK 114
-#define IMX7D_PCIE_CTRL_ROOT_SRC 115
-#define IMX7D_PCIE_CTRL_ROOT_CG 116
-#define IMX7D_PCIE_CTRL_ROOT_DIV 117
-#define IMX7D_PCIE_PHY_ROOT_CLK 118
-#define IMX7D_PCIE_PHY_ROOT_SRC 119
-#define IMX7D_PCIE_PHY_ROOT_CG 120
-#define IMX7D_PCIE_PHY_ROOT_DIV 121
-#define IMX7D_EPDC_PIXEL_ROOT_CLK 122
-#define IMX7D_EPDC_PIXEL_ROOT_SRC 123
-#define IMX7D_EPDC_PIXEL_ROOT_CG 124
-#define IMX7D_EPDC_PIXEL_ROOT_DIV 125
-#define IMX7D_LCDIF_PIXEL_ROOT_CLK 126
-#define IMX7D_LCDIF_PIXEL_ROOT_SRC 127
-#define IMX7D_LCDIF_PIXEL_ROOT_CG 128
-#define IMX7D_LCDIF_PIXEL_ROOT_DIV 129
-#define IMX7D_MIPI_DSI_ROOT_CLK 130
-#define IMX7D_MIPI_DSI_ROOT_SRC 131
-#define IMX7D_MIPI_DSI_ROOT_CG 132
-#define IMX7D_MIPI_DSI_ROOT_DIV 133
-#define IMX7D_MIPI_CSI_ROOT_CLK 134
-#define IMX7D_MIPI_CSI_ROOT_SRC 135
-#define IMX7D_MIPI_CSI_ROOT_CG 136
-#define IMX7D_MIPI_CSI_ROOT_DIV 137
-#define IMX7D_MIPI_DPHY_ROOT_CLK 138
-#define IMX7D_MIPI_DPHY_ROOT_SRC 139
-#define IMX7D_MIPI_DPHY_ROOT_CG 140
-#define IMX7D_MIPI_DPHY_ROOT_DIV 141
-#define IMX7D_SAI1_ROOT_CLK 142
-#define IMX7D_SAI1_ROOT_SRC 143
-#define IMX7D_SAI1_ROOT_CG 144
-#define IMX7D_SAI1_ROOT_DIV 145
-#define IMX7D_SAI2_ROOT_CLK 146
-#define IMX7D_SAI2_ROOT_SRC 147
-#define IMX7D_SAI2_ROOT_CG 148
-#define IMX7D_SAI2_ROOT_DIV 149
-#define IMX7D_SAI3_ROOT_CLK 150
-#define IMX7D_SAI3_ROOT_SRC 151
-#define IMX7D_SAI3_ROOT_CG 152
-#define IMX7D_SAI3_ROOT_DIV 153
-#define IMX7D_SPDIF_ROOT_CLK 154
-#define IMX7D_SPDIF_ROOT_SRC 155
-#define IMX7D_SPDIF_ROOT_CG 156
-#define IMX7D_SPDIF_ROOT_DIV 157
-#define IMX7D_ENET1_IPG_ROOT_CLK 158
-#define IMX7D_ENET1_REF_ROOT_SRC 159
-#define IMX7D_ENET1_REF_ROOT_CG 160
-#define IMX7D_ENET1_REF_ROOT_DIV 161
-#define IMX7D_ENET1_TIME_ROOT_CLK 162
-#define IMX7D_ENET1_TIME_ROOT_SRC 163
-#define IMX7D_ENET1_TIME_ROOT_CG 164
-#define IMX7D_ENET1_TIME_ROOT_DIV 165
-#define IMX7D_ENET2_IPG_ROOT_CLK 166
-#define IMX7D_ENET2_REF_ROOT_SRC 167
-#define IMX7D_ENET2_REF_ROOT_CG 168
-#define IMX7D_ENET2_REF_ROOT_DIV 169
-#define IMX7D_ENET2_TIME_ROOT_CLK 170
-#define IMX7D_ENET2_TIME_ROOT_SRC 171
-#define IMX7D_ENET2_TIME_ROOT_CG 172
-#define IMX7D_ENET2_TIME_ROOT_DIV 173
-#define IMX7D_ENET_PHY_REF_ROOT_CLK 174
-#define IMX7D_ENET_PHY_REF_ROOT_SRC 175
-#define IMX7D_ENET_PHY_REF_ROOT_CG 176
-#define IMX7D_ENET_PHY_REF_ROOT_DIV 177
-#define IMX7D_EIM_ROOT_CLK 178
-#define IMX7D_EIM_ROOT_SRC 179
-#define IMX7D_EIM_ROOT_CG 180
-#define IMX7D_EIM_ROOT_DIV 181
-#define IMX7D_NAND_ROOT_CLK 182
-#define IMX7D_NAND_ROOT_SRC 183
-#define IMX7D_NAND_ROOT_CG 184
-#define IMX7D_NAND_ROOT_DIV 185
-#define IMX7D_QSPI_ROOT_CLK 186
-#define IMX7D_QSPI_ROOT_SRC 187
-#define IMX7D_QSPI_ROOT_CG 188
-#define IMX7D_QSPI_ROOT_DIV 189
-#define IMX7D_USDHC1_ROOT_CLK 190
-#define IMX7D_USDHC1_ROOT_SRC 191
-#define IMX7D_USDHC1_ROOT_CG 192
-#define IMX7D_USDHC1_ROOT_DIV 193
-#define IMX7D_USDHC2_ROOT_CLK 194
-#define IMX7D_USDHC2_ROOT_SRC 195
-#define IMX7D_USDHC2_ROOT_CG 196
-#define IMX7D_USDHC2_ROOT_DIV 197
-#define IMX7D_USDHC3_ROOT_CLK 198
-#define IMX7D_USDHC3_ROOT_SRC 199
-#define IMX7D_USDHC3_ROOT_CG 200
-#define IMX7D_USDHC3_ROOT_DIV 201
-#define IMX7D_CAN1_ROOT_CLK 202
-#define IMX7D_CAN1_ROOT_SRC 203
-#define IMX7D_CAN1_ROOT_CG 204
-#define IMX7D_CAN1_ROOT_DIV 205
-#define IMX7D_CAN2_ROOT_CLK 206
-#define IMX7D_CAN2_ROOT_SRC 207
-#define IMX7D_CAN2_ROOT_CG 208
-#define IMX7D_CAN2_ROOT_DIV 209
-#define IMX7D_I2C1_ROOT_CLK 210
-#define IMX7D_I2C1_ROOT_SRC 211
-#define IMX7D_I2C1_ROOT_CG 212
-#define IMX7D_I2C1_ROOT_DIV 213
-#define IMX7D_I2C2_ROOT_CLK 214
-#define IMX7D_I2C2_ROOT_SRC 215
-#define IMX7D_I2C2_ROOT_CG 216
-#define IMX7D_I2C2_ROOT_DIV 217
-#define IMX7D_I2C3_ROOT_CLK 218
-#define IMX7D_I2C3_ROOT_SRC 219
-#define IMX7D_I2C3_ROOT_CG 220
-#define IMX7D_I2C3_ROOT_DIV 221
-#define IMX7D_I2C4_ROOT_CLK 222
-#define IMX7D_I2C4_ROOT_SRC 223
-#define IMX7D_I2C4_ROOT_CG 224
-#define IMX7D_I2C4_ROOT_DIV 225
-#define IMX7D_UART1_ROOT_CLK 226
-#define IMX7D_UART1_ROOT_SRC 227
-#define IMX7D_UART1_ROOT_CG 228
-#define IMX7D_UART1_ROOT_DIV 229
-#define IMX7D_UART2_ROOT_CLK 230
-#define IMX7D_UART2_ROOT_SRC 231
-#define IMX7D_UART2_ROOT_CG 232
-#define IMX7D_UART2_ROOT_DIV 233
-#define IMX7D_UART3_ROOT_CLK 234
-#define IMX7D_UART3_ROOT_SRC 235
-#define IMX7D_UART3_ROOT_CG 236
-#define IMX7D_UART3_ROOT_DIV 237
-#define IMX7D_UART4_ROOT_CLK 238
-#define IMX7D_UART4_ROOT_SRC 239
-#define IMX7D_UART4_ROOT_CG 240
-#define IMX7D_UART4_ROOT_DIV 241
-#define IMX7D_UART5_ROOT_CLK 242
-#define IMX7D_UART5_ROOT_SRC 243
-#define IMX7D_UART5_ROOT_CG 244
-#define IMX7D_UART5_ROOT_DIV 245
-#define IMX7D_UART6_ROOT_CLK 246
-#define IMX7D_UART6_ROOT_SRC 247
-#define IMX7D_UART6_ROOT_CG 248
-#define IMX7D_UART6_ROOT_DIV 249
-#define IMX7D_UART7_ROOT_CLK 250
-#define IMX7D_UART7_ROOT_SRC 251
-#define IMX7D_UART7_ROOT_CG 252
-#define IMX7D_UART7_ROOT_DIV 253
-#define IMX7D_ECSPI1_ROOT_CLK 254
-#define IMX7D_ECSPI1_ROOT_SRC 255
-#define IMX7D_ECSPI1_ROOT_CG 256
-#define IMX7D_ECSPI1_ROOT_DIV 257
-#define IMX7D_ECSPI2_ROOT_CLK 258
-#define IMX7D_ECSPI2_ROOT_SRC 259
-#define IMX7D_ECSPI2_ROOT_CG 260
-#define IMX7D_ECSPI2_ROOT_DIV 261
-#define IMX7D_ECSPI3_ROOT_CLK 262
-#define IMX7D_ECSPI3_ROOT_SRC 263
-#define IMX7D_ECSPI3_ROOT_CG 264
-#define IMX7D_ECSPI3_ROOT_DIV 265
-#define IMX7D_ECSPI4_ROOT_CLK 266
-#define IMX7D_ECSPI4_ROOT_SRC 267
-#define IMX7D_ECSPI4_ROOT_CG 268
-#define IMX7D_ECSPI4_ROOT_DIV 269
-#define IMX7D_PWM1_ROOT_CLK 270
-#define IMX7D_PWM1_ROOT_SRC 271
-#define IMX7D_PWM1_ROOT_CG 272
-#define IMX7D_PWM1_ROOT_DIV 273
-#define IMX7D_PWM2_ROOT_CLK 274
-#define IMX7D_PWM2_ROOT_SRC 275
-#define IMX7D_PWM2_ROOT_CG 276
-#define IMX7D_PWM2_ROOT_DIV 277
-#define IMX7D_PWM3_ROOT_CLK 278
-#define IMX7D_PWM3_ROOT_SRC 279
-#define IMX7D_PWM3_ROOT_CG 280
-#define IMX7D_PWM3_ROOT_DIV 281
-#define IMX7D_PWM4_ROOT_CLK 282
-#define IMX7D_PWM4_ROOT_SRC 283
-#define IMX7D_PWM4_ROOT_CG 284
-#define IMX7D_PWM4_ROOT_DIV 285
-#define IMX7D_FLEXTIMER1_ROOT_CLK 286
-#define IMX7D_FLEXTIMER1_ROOT_SRC 287
-#define IMX7D_FLEXTIMER1_ROOT_CG 288
-#define IMX7D_FLEXTIMER1_ROOT_DIV 289
-#define IMX7D_FLEXTIMER2_ROOT_CLK 290
-#define IMX7D_FLEXTIMER2_ROOT_SRC 291
-#define IMX7D_FLEXTIMER2_ROOT_CG 292
-#define IMX7D_FLEXTIMER2_ROOT_DIV 293
-#define IMX7D_SIM1_ROOT_CLK 294
-#define IMX7D_SIM1_ROOT_SRC 295
-#define IMX7D_SIM1_ROOT_CG 296
-#define IMX7D_SIM1_ROOT_DIV 297
-#define IMX7D_SIM2_ROOT_CLK 298
-#define IMX7D_SIM2_ROOT_SRC 299
-#define IMX7D_SIM2_ROOT_CG 300
-#define IMX7D_SIM2_ROOT_DIV 301
-#define IMX7D_GPT1_ROOT_CLK 302
-#define IMX7D_GPT1_ROOT_SRC 303
-#define IMX7D_GPT1_ROOT_CG 304
-#define IMX7D_GPT1_ROOT_DIV 305
-#define IMX7D_GPT2_ROOT_CLK 306
-#define IMX7D_GPT2_ROOT_SRC 307
-#define IMX7D_GPT2_ROOT_CG 308
-#define IMX7D_GPT2_ROOT_DIV 309
-#define IMX7D_GPT3_ROOT_CLK 310
-#define IMX7D_GPT3_ROOT_SRC 311
-#define IMX7D_GPT3_ROOT_CG 312
-#define IMX7D_GPT3_ROOT_DIV 313
-#define IMX7D_GPT4_ROOT_CLK 314
-#define IMX7D_GPT4_ROOT_SRC 315
-#define IMX7D_GPT4_ROOT_CG 316
-#define IMX7D_GPT4_ROOT_DIV 317
-#define IMX7D_TRACE_ROOT_CLK 318
-#define IMX7D_TRACE_ROOT_SRC 319
-#define IMX7D_TRACE_ROOT_CG 320
-#define IMX7D_TRACE_ROOT_DIV 321
-#define IMX7D_WDOG1_ROOT_CLK 322
-#define IMX7D_WDOG_ROOT_SRC 323
-#define IMX7D_WDOG_ROOT_CG 324
-#define IMX7D_WDOG_ROOT_DIV 325
-#define IMX7D_CSI_MCLK_ROOT_CLK 326
-#define IMX7D_CSI_MCLK_ROOT_SRC 327
-#define IMX7D_CSI_MCLK_ROOT_CG 328
-#define IMX7D_CSI_MCLK_ROOT_DIV 329
-#define IMX7D_AUDIO_MCLK_ROOT_CLK 330
-#define IMX7D_AUDIO_MCLK_ROOT_SRC 331
-#define IMX7D_AUDIO_MCLK_ROOT_CG 332
-#define IMX7D_AUDIO_MCLK_ROOT_DIV 333
-#define IMX7D_WRCLK_ROOT_CLK 334
-#define IMX7D_WRCLK_ROOT_SRC 335
-#define IMX7D_WRCLK_ROOT_CG 336
-#define IMX7D_WRCLK_ROOT_DIV 337
-#define IMX7D_CLKO1_ROOT_SRC 338
-#define IMX7D_CLKO1_ROOT_CG 339
-#define IMX7D_CLKO1_ROOT_DIV 340
-#define IMX7D_CLKO2_ROOT_SRC 341
-#define IMX7D_CLKO2_ROOT_CG 342
-#define IMX7D_CLKO2_ROOT_DIV 343
-#define IMX7D_MAIN_AXI_ROOT_PRE_DIV 344
-#define IMX7D_DISP_AXI_ROOT_PRE_DIV 345
-#define IMX7D_ENET_AXI_ROOT_PRE_DIV 346
-#define IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV 347
-#define IMX7D_AHB_CHANNEL_ROOT_PRE_DIV 348
-#define IMX7D_USB_HSIC_ROOT_PRE_DIV 349
-#define IMX7D_PCIE_CTRL_ROOT_PRE_DIV 350
-#define IMX7D_PCIE_PHY_ROOT_PRE_DIV 351
-#define IMX7D_EPDC_PIXEL_ROOT_PRE_DIV 352
-#define IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV 353
-#define IMX7D_MIPI_DSI_ROOT_PRE_DIV 354
-#define IMX7D_MIPI_CSI_ROOT_PRE_DIV 355
-#define IMX7D_MIPI_DPHY_ROOT_PRE_DIV 356
-#define IMX7D_SAI1_ROOT_PRE_DIV 357
-#define IMX7D_SAI2_ROOT_PRE_DIV 358
-#define IMX7D_SAI3_ROOT_PRE_DIV 359
-#define IMX7D_SPDIF_ROOT_PRE_DIV 360
-#define IMX7D_ENET1_REF_ROOT_PRE_DIV 361
-#define IMX7D_ENET1_TIME_ROOT_PRE_DIV 362
-#define IMX7D_ENET2_REF_ROOT_PRE_DIV 363
-#define IMX7D_ENET2_TIME_ROOT_PRE_DIV 364
-#define IMX7D_ENET_PHY_REF_ROOT_PRE_DIV 365
-#define IMX7D_EIM_ROOT_PRE_DIV 366
-#define IMX7D_NAND_ROOT_PRE_DIV 367
-#define IMX7D_QSPI_ROOT_PRE_DIV 368
-#define IMX7D_USDHC1_ROOT_PRE_DIV 369
-#define IMX7D_USDHC2_ROOT_PRE_DIV 370
-#define IMX7D_USDHC3_ROOT_PRE_DIV 371
-#define IMX7D_CAN1_ROOT_PRE_DIV 372
-#define IMX7D_CAN2_ROOT_PRE_DIV 373
-#define IMX7D_I2C1_ROOT_PRE_DIV 374
-#define IMX7D_I2C2_ROOT_PRE_DIV 375
-#define IMX7D_I2C3_ROOT_PRE_DIV 376
-#define IMX7D_I2C4_ROOT_PRE_DIV 377
-#define IMX7D_UART1_ROOT_PRE_DIV 378
-#define IMX7D_UART2_ROOT_PRE_DIV 379
-#define IMX7D_UART3_ROOT_PRE_DIV 380
-#define IMX7D_UART4_ROOT_PRE_DIV 381
-#define IMX7D_UART5_ROOT_PRE_DIV 382
-#define IMX7D_UART6_ROOT_PRE_DIV 383
-#define IMX7D_UART7_ROOT_PRE_DIV 384
-#define IMX7D_ECSPI1_ROOT_PRE_DIV 385
-#define IMX7D_ECSPI2_ROOT_PRE_DIV 386
-#define IMX7D_ECSPI3_ROOT_PRE_DIV 387
-#define IMX7D_ECSPI4_ROOT_PRE_DIV 388
-#define IMX7D_PWM1_ROOT_PRE_DIV 389
-#define IMX7D_PWM2_ROOT_PRE_DIV 390
-#define IMX7D_PWM3_ROOT_PRE_DIV 391
-#define IMX7D_PWM4_ROOT_PRE_DIV 392
-#define IMX7D_FLEXTIMER1_ROOT_PRE_DIV 393
-#define IMX7D_FLEXTIMER2_ROOT_PRE_DIV 394
-#define IMX7D_SIM1_ROOT_PRE_DIV 395
-#define IMX7D_SIM2_ROOT_PRE_DIV 396
-#define IMX7D_GPT1_ROOT_PRE_DIV 397
-#define IMX7D_GPT2_ROOT_PRE_DIV 398
-#define IMX7D_GPT3_ROOT_PRE_DIV 399
-#define IMX7D_GPT4_ROOT_PRE_DIV 400
-#define IMX7D_TRACE_ROOT_PRE_DIV 401
-#define IMX7D_WDOG_ROOT_PRE_DIV 402
-#define IMX7D_CSI_MCLK_ROOT_PRE_DIV 403
-#define IMX7D_AUDIO_MCLK_ROOT_PRE_DIV 404
-#define IMX7D_WRCLK_ROOT_PRE_DIV 405
-#define IMX7D_CLKO1_ROOT_PRE_DIV 406
-#define IMX7D_CLKO2_ROOT_PRE_DIV 407
-#define IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV 408
-#define IMX7D_DRAM_ALT_ROOT_PRE_DIV 409
-#define IMX7D_LVDS1_IN_CLK 410
-#define IMX7D_LVDS1_OUT_SEL 411
-#define IMX7D_LVDS1_OUT_CLK 412
-#define IMX7D_CLK_DUMMY 413
-#define IMX7D_GPT_3M_CLK 414
-#define IMX7D_OCRAM_CLK 415
-#define IMX7D_OCRAM_S_CLK 416
-#define IMX7D_WDOG2_ROOT_CLK 417
-#define IMX7D_WDOG3_ROOT_CLK 418
-#define IMX7D_WDOG4_ROOT_CLK 419
-#define IMX7D_SDMA_CORE_CLK 420
-#define IMX7D_USB1_MAIN_480M_CLK 421
-#define IMX7D_USB_CTRL_CLK 422
-#define IMX7D_USB_PHY1_CLK 423
-#define IMX7D_USB_PHY2_CLK 424
-#define IMX7D_IPG_ROOT_CLK 425
-#define IMX7D_SAI1_IPG_CLK 426
-#define IMX7D_SAI2_IPG_CLK 427
-#define IMX7D_SAI3_IPG_CLK 428
-#define IMX7D_PLL_AUDIO_TEST_DIV 429
-#define IMX7D_PLL_AUDIO_POST_DIV 430
-#define IMX7D_PLL_VIDEO_TEST_DIV 431
-#define IMX7D_PLL_VIDEO_POST_DIV 432
-#define IMX7D_MU_ROOT_CLK 433
-#define IMX7D_SEMA4_HS_ROOT_CLK 434
-#define IMX7D_PLL_DRAM_TEST_DIV 435
-#define IMX7D_ADC_ROOT_CLK 436
-#define IMX7D_CLK_ARM 437
-#define IMX7D_CKIL 438
-#define IMX7D_OCOTP_CLK 439
-#define IMX7D_NAND_RAWNAND_CLK 440
-#define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 441
-#define IMX7D_SNVS_CLK 442
-#define IMX7D_CAAM_CLK 443
-#define IMX7D_KPP_ROOT_CLK 444
-#define IMX7D_PXP_CLK 445
-#define IMX7D_CLK_END 446
-#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */
diff --git a/include/dt-bindings/clock/imx7ulp-clock.h b/include/dt-bindings/clock/imx7ulp-clock.h
deleted file mode 100644
index b58370d..0000000
--- a/include/dt-bindings/clock/imx7ulp-clock.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2016 Freescale Semiconductor, Inc.
- * Copyright 2017~2018 NXP
- *
- */
-
-#ifndef __DT_BINDINGS_CLOCK_IMX7ULP_H
-#define __DT_BINDINGS_CLOCK_IMX7ULP_H
-
-/* SCG1 */
-
-#define IMX7ULP_CLK_DUMMY 0
-#define IMX7ULP_CLK_ROSC 1
-#define IMX7ULP_CLK_SOSC 2
-#define IMX7ULP_CLK_FIRC 3
-#define IMX7ULP_CLK_SPLL_PRE_SEL 4
-#define IMX7ULP_CLK_SPLL_PRE_DIV 5
-#define IMX7ULP_CLK_SPLL 6
-#define IMX7ULP_CLK_SPLL_POST_DIV1 7
-#define IMX7ULP_CLK_SPLL_POST_DIV2 8
-#define IMX7ULP_CLK_SPLL_PFD0 9
-#define IMX7ULP_CLK_SPLL_PFD1 10
-#define IMX7ULP_CLK_SPLL_PFD2 11
-#define IMX7ULP_CLK_SPLL_PFD3 12
-#define IMX7ULP_CLK_SPLL_PFD_SEL 13
-#define IMX7ULP_CLK_SPLL_SEL 14
-#define IMX7ULP_CLK_APLL_PRE_SEL 15
-#define IMX7ULP_CLK_APLL_PRE_DIV 16
-#define IMX7ULP_CLK_APLL 17
-#define IMX7ULP_CLK_APLL_POST_DIV1 18
-#define IMX7ULP_CLK_APLL_POST_DIV2 19
-#define IMX7ULP_CLK_APLL_PFD0 20
-#define IMX7ULP_CLK_APLL_PFD1 21
-#define IMX7ULP_CLK_APLL_PFD2 22
-#define IMX7ULP_CLK_APLL_PFD3 23
-#define IMX7ULP_CLK_APLL_PFD_SEL 24
-#define IMX7ULP_CLK_APLL_SEL 25
-#define IMX7ULP_CLK_UPLL 26
-#define IMX7ULP_CLK_SYS_SEL 27
-#define IMX7ULP_CLK_CORE_DIV 28
-#define IMX7ULP_CLK_BUS_DIV 29
-#define IMX7ULP_CLK_PLAT_DIV 30
-#define IMX7ULP_CLK_DDR_SEL 31
-#define IMX7ULP_CLK_DDR_DIV 32
-#define IMX7ULP_CLK_NIC_SEL 33
-#define IMX7ULP_CLK_NIC0_DIV 34
-#define IMX7ULP_CLK_GPU_DIV 35
-#define IMX7ULP_CLK_NIC1_DIV 36
-#define IMX7ULP_CLK_NIC1_BUS_DIV 37
-#define IMX7ULP_CLK_NIC1_EXT_DIV 38
-/* IMX7ULP_CLK_MIPI_PLL is unsupported and shouldn't be used in DT */
-#define IMX7ULP_CLK_MIPI_PLL 39
-#define IMX7ULP_CLK_SIRC 40
-#define IMX7ULP_CLK_SOSC_BUS_CLK 41
-#define IMX7ULP_CLK_FIRC_BUS_CLK 42
-#define IMX7ULP_CLK_SPLL_BUS_CLK 43
-#define IMX7ULP_CLK_HSRUN_SYS_SEL 44
-#define IMX7ULP_CLK_HSRUN_CORE_DIV 45
-
-#define IMX7ULP_CLK_CORE 46
-#define IMX7ULP_CLK_HSRUN_CORE 47
-
-#define IMX7ULP_CLK_SCG1_END 48
-
-/* PCC2 */
-#define IMX7ULP_CLK_DMA1 0
-#define IMX7ULP_CLK_RGPIO2P1 1
-#define IMX7ULP_CLK_FLEXBUS 2
-#define IMX7ULP_CLK_SEMA42_1 3
-#define IMX7ULP_CLK_DMA_MUX1 4
-#define IMX7ULP_CLK_CAAM 6
-#define IMX7ULP_CLK_LPTPM4 7
-#define IMX7ULP_CLK_LPTPM5 8
-#define IMX7ULP_CLK_LPIT1 9
-#define IMX7ULP_CLK_LPSPI2 10
-#define IMX7ULP_CLK_LPSPI3 11
-#define IMX7ULP_CLK_LPI2C4 12
-#define IMX7ULP_CLK_LPI2C5 13
-#define IMX7ULP_CLK_LPUART4 14
-#define IMX7ULP_CLK_LPUART5 15
-#define IMX7ULP_CLK_FLEXIO1 16
-#define IMX7ULP_CLK_USB0 17
-#define IMX7ULP_CLK_USB1 18
-#define IMX7ULP_CLK_USB_PHY 19
-#define IMX7ULP_CLK_USB_PL301 20
-#define IMX7ULP_CLK_USDHC0 21
-#define IMX7ULP_CLK_USDHC1 22
-#define IMX7ULP_CLK_WDG1 23
-#define IMX7ULP_CLK_WDG2 24
-
-#define IMX7ULP_CLK_PCC2_END 25
-
-/* PCC3 */
-#define IMX7ULP_CLK_LPTPM6 0
-#define IMX7ULP_CLK_LPTPM7 1
-#define IMX7ULP_CLK_LPI2C6 2
-#define IMX7ULP_CLK_LPI2C7 3
-#define IMX7ULP_CLK_LPUART6 4
-#define IMX7ULP_CLK_LPUART7 5
-#define IMX7ULP_CLK_VIU 6
-#define IMX7ULP_CLK_DSI 7
-#define IMX7ULP_CLK_LCDIF 8
-#define IMX7ULP_CLK_MMDC 9
-#define IMX7ULP_CLK_PCTLC 10
-#define IMX7ULP_CLK_PCTLD 11
-#define IMX7ULP_CLK_PCTLE 12
-#define IMX7ULP_CLK_PCTLF 13
-#define IMX7ULP_CLK_GPU3D 14
-#define IMX7ULP_CLK_GPU2D 15
-
-#define IMX7ULP_CLK_PCC3_END 16
-
-/* SMC1 */
-#define IMX7ULP_CLK_ARM 0
-
-#define IMX7ULP_CLK_SMC1_END 1
-
-#endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */
diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h
deleted file mode 100644
index 1f768b2..0000000
--- a/include/dt-bindings/clock/imx8mm-clock.h
+++ /dev/null
@@ -1,286 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright 2017-2018 NXP
- */
-
-#ifndef __DT_BINDINGS_CLOCK_IMX8MM_H
-#define __DT_BINDINGS_CLOCK_IMX8MM_H
-
-#define IMX8MM_CLK_DUMMY 0
-#define IMX8MM_CLK_32K 1
-#define IMX8MM_CLK_24M 2
-#define IMX8MM_OSC_HDMI_CLK 3
-#define IMX8MM_CLK_EXT1 4
-#define IMX8MM_CLK_EXT2 5
-#define IMX8MM_CLK_EXT3 6
-#define IMX8MM_CLK_EXT4 7
-#define IMX8MM_AUDIO_PLL1_REF_SEL 8
-#define IMX8MM_AUDIO_PLL2_REF_SEL 9
-#define IMX8MM_VIDEO_PLL1_REF_SEL 10
-#define IMX8MM_DRAM_PLL_REF_SEL 11
-#define IMX8MM_GPU_PLL_REF_SEL 12
-#define IMX8MM_VPU_PLL_REF_SEL 13
-#define IMX8MM_ARM_PLL_REF_SEL 14
-#define IMX8MM_SYS_PLL1_REF_SEL 15
-#define IMX8MM_SYS_PLL2_REF_SEL 16
-#define IMX8MM_SYS_PLL3_REF_SEL 17
-#define IMX8MM_AUDIO_PLL1 18
-#define IMX8MM_AUDIO_PLL2 19
-#define IMX8MM_VIDEO_PLL1 20
-#define IMX8MM_DRAM_PLL 21
-#define IMX8MM_GPU_PLL 22
-#define IMX8MM_VPU_PLL 23
-#define IMX8MM_ARM_PLL 24
-#define IMX8MM_SYS_PLL1 25
-#define IMX8MM_SYS_PLL2 26
-#define IMX8MM_SYS_PLL3 27
-#define IMX8MM_AUDIO_PLL1_BYPASS 28
-#define IMX8MM_AUDIO_PLL2_BYPASS 29
-#define IMX8MM_VIDEO_PLL1_BYPASS 30
-#define IMX8MM_DRAM_PLL_BYPASS 31
-#define IMX8MM_GPU_PLL_BYPASS 32
-#define IMX8MM_VPU_PLL_BYPASS 33
-#define IMX8MM_ARM_PLL_BYPASS 34
-#define IMX8MM_SYS_PLL1_BYPASS 35
-#define IMX8MM_SYS_PLL2_BYPASS 36
-#define IMX8MM_SYS_PLL3_BYPASS 37
-#define IMX8MM_AUDIO_PLL1_OUT 38
-#define IMX8MM_AUDIO_PLL2_OUT 39
-#define IMX8MM_VIDEO_PLL1_OUT 40
-#define IMX8MM_DRAM_PLL_OUT 41
-#define IMX8MM_GPU_PLL_OUT 42
-#define IMX8MM_VPU_PLL_OUT 43
-#define IMX8MM_ARM_PLL_OUT 44
-#define IMX8MM_SYS_PLL1_OUT 45
-#define IMX8MM_SYS_PLL2_OUT 46
-#define IMX8MM_SYS_PLL3_OUT 47
-#define IMX8MM_SYS_PLL1_40M 48
-#define IMX8MM_SYS_PLL1_80M 49
-#define IMX8MM_SYS_PLL1_100M 50
-#define IMX8MM_SYS_PLL1_133M 51
-#define IMX8MM_SYS_PLL1_160M 52
-#define IMX8MM_SYS_PLL1_200M 53
-#define IMX8MM_SYS_PLL1_266M 54
-#define IMX8MM_SYS_PLL1_400M 55
-#define IMX8MM_SYS_PLL1_800M 56
-#define IMX8MM_SYS_PLL2_50M 57
-#define IMX8MM_SYS_PLL2_100M 58
-#define IMX8MM_SYS_PLL2_125M 59
-#define IMX8MM_SYS_PLL2_166M 60
-#define IMX8MM_SYS_PLL2_200M 61
-#define IMX8MM_SYS_PLL2_250M 62
-#define IMX8MM_SYS_PLL2_333M 63
-#define IMX8MM_SYS_PLL2_500M 64
-#define IMX8MM_SYS_PLL2_1000M 65
-
-/* core */
-#define IMX8MM_CLK_A53_SRC 66
-#define IMX8MM_CLK_M4_SRC 67
-#define IMX8MM_CLK_VPU_SRC 68
-#define IMX8MM_CLK_GPU3D_SRC 69
-#define IMX8MM_CLK_GPU2D_SRC 70
-#define IMX8MM_CLK_A53_CG 71
-#define IMX8MM_CLK_M4_CG 72
-#define IMX8MM_CLK_VPU_CG 73
-#define IMX8MM_CLK_GPU3D_CG 74
-#define IMX8MM_CLK_GPU2D_CG 75
-#define IMX8MM_CLK_A53_DIV 76
-#define IMX8MM_CLK_M4_DIV 77
-#define IMX8MM_CLK_VPU_DIV 78
-#define IMX8MM_CLK_GPU3D_DIV 79
-#define IMX8MM_CLK_GPU2D_DIV 80
-
-/* bus */
-#define IMX8MM_CLK_MAIN_AXI 81
-#define IMX8MM_CLK_ENET_AXI 82
-#define IMX8MM_CLK_NAND_USDHC_BUS 83
-#define IMX8MM_CLK_VPU_BUS 84
-#define IMX8MM_CLK_DISP_AXI 85
-#define IMX8MM_CLK_DISP_APB 86
-#define IMX8MM_CLK_DISP_RTRM 87
-#define IMX8MM_CLK_USB_BUS 88
-#define IMX8MM_CLK_GPU_AXI 89
-#define IMX8MM_CLK_GPU_AHB 90
-#define IMX8MM_CLK_NOC 91
-#define IMX8MM_CLK_NOC_APB 92
-
-#define IMX8MM_CLK_AHB 93
-#define IMX8MM_CLK_AUDIO_AHB 94
-#define IMX8MM_CLK_IPG_ROOT 95
-#define IMX8MM_CLK_IPG_AUDIO_ROOT 96
-
-#define IMX8MM_CLK_DRAM_ALT 97
-#define IMX8MM_CLK_DRAM_APB 98
-#define IMX8MM_CLK_VPU_G1 99
-#define IMX8MM_CLK_VPU_G2 100
-#define IMX8MM_CLK_DISP_DTRC 101
-#define IMX8MM_CLK_DISP_DC8000 102
-#define IMX8MM_CLK_PCIE1_CTRL 103
-#define IMX8MM_CLK_PCIE1_PHY 104
-#define IMX8MM_CLK_PCIE1_AUX 105
-#define IMX8MM_CLK_DC_PIXEL 106
-#define IMX8MM_CLK_LCDIF_PIXEL 107
-#define IMX8MM_CLK_SAI1 108
-#define IMX8MM_CLK_SAI2 109
-#define IMX8MM_CLK_SAI3 110
-#define IMX8MM_CLK_SAI4 111
-#define IMX8MM_CLK_SAI5 112
-#define IMX8MM_CLK_SAI6 113
-#define IMX8MM_CLK_SPDIF1 114
-#define IMX8MM_CLK_SPDIF2 115
-#define IMX8MM_CLK_ENET_REF 116
-#define IMX8MM_CLK_ENET_TIMER 117
-#define IMX8MM_CLK_ENET_PHY_REF 118
-#define IMX8MM_CLK_NAND 119
-#define IMX8MM_CLK_QSPI 120
-#define IMX8MM_CLK_USDHC1 121
-#define IMX8MM_CLK_USDHC2 122
-#define IMX8MM_CLK_I2C1 123
-#define IMX8MM_CLK_I2C2 124
-#define IMX8MM_CLK_I2C3 125
-#define IMX8MM_CLK_I2C4 126
-#define IMX8MM_CLK_UART1 127
-#define IMX8MM_CLK_UART2 128
-#define IMX8MM_CLK_UART3 129
-#define IMX8MM_CLK_UART4 130
-#define IMX8MM_CLK_USB_CORE_REF 131
-#define IMX8MM_CLK_USB_PHY_REF 132
-#define IMX8MM_CLK_ECSPI1 133
-#define IMX8MM_CLK_ECSPI2 134
-#define IMX8MM_CLK_PWM1 135
-#define IMX8MM_CLK_PWM2 136
-#define IMX8MM_CLK_PWM3 137
-#define IMX8MM_CLK_PWM4 138
-#define IMX8MM_CLK_GPT1 139
-#define IMX8MM_CLK_WDOG 140
-#define IMX8MM_CLK_WRCLK 141
-#define IMX8MM_CLK_DSI_CORE 142
-#define IMX8MM_CLK_DSI_PHY_REF 143
-#define IMX8MM_CLK_DSI_DBI 144
-#define IMX8MM_CLK_USDHC3 145
-#define IMX8MM_CLK_CSI1_CORE 146
-#define IMX8MM_CLK_CSI1_PHY_REF 147
-#define IMX8MM_CLK_CSI1_ESC 148
-#define IMX8MM_CLK_CSI2_CORE 149
-#define IMX8MM_CLK_CSI2_PHY_REF 150
-#define IMX8MM_CLK_CSI2_ESC 151
-#define IMX8MM_CLK_PCIE2_CTRL 152
-#define IMX8MM_CLK_PCIE2_PHY 153
-#define IMX8MM_CLK_PCIE2_AUX 154
-#define IMX8MM_CLK_ECSPI3 155
-#define IMX8MM_CLK_PDM 156
-#define IMX8MM_CLK_VPU_H1 157
-#define IMX8MM_CLK_CLKO1 158
-
-#define IMX8MM_CLK_ECSPI1_ROOT 159
-#define IMX8MM_CLK_ECSPI2_ROOT 160
-#define IMX8MM_CLK_ECSPI3_ROOT 161
-#define IMX8MM_CLK_ENET1_ROOT 162
-#define IMX8MM_CLK_GPT1_ROOT 163
-#define IMX8MM_CLK_I2C1_ROOT 164
-#define IMX8MM_CLK_I2C2_ROOT 165
-#define IMX8MM_CLK_I2C3_ROOT 166
-#define IMX8MM_CLK_I2C4_ROOT 167
-#define IMX8MM_CLK_OCOTP_ROOT 168
-#define IMX8MM_CLK_PCIE1_ROOT 169
-#define IMX8MM_CLK_PWM1_ROOT 170
-#define IMX8MM_CLK_PWM2_ROOT 171
-#define IMX8MM_CLK_PWM3_ROOT 172
-#define IMX8MM_CLK_PWM4_ROOT 173
-#define IMX8MM_CLK_QSPI_ROOT 174
-#define IMX8MM_CLK_NAND_ROOT 175
-#define IMX8MM_CLK_SAI1_ROOT 176
-#define IMX8MM_CLK_SAI1_IPG 177
-#define IMX8MM_CLK_SAI2_ROOT 178
-#define IMX8MM_CLK_SAI2_IPG 179
-#define IMX8MM_CLK_SAI3_ROOT 180
-#define IMX8MM_CLK_SAI3_IPG 181
-#define IMX8MM_CLK_SAI4_ROOT 182
-#define IMX8MM_CLK_SAI4_IPG 183
-#define IMX8MM_CLK_SAI5_ROOT 184
-#define IMX8MM_CLK_SAI5_IPG 185
-#define IMX8MM_CLK_SAI6_ROOT 186
-#define IMX8MM_CLK_SAI6_IPG 187
-#define IMX8MM_CLK_UART1_ROOT 188
-#define IMX8MM_CLK_UART2_ROOT 189
-#define IMX8MM_CLK_UART3_ROOT 190
-#define IMX8MM_CLK_UART4_ROOT 191
-#define IMX8MM_CLK_USB1_CTRL_ROOT 192
-#define IMX8MM_CLK_GPU3D_ROOT 193
-#define IMX8MM_CLK_USDHC1_ROOT 194
-#define IMX8MM_CLK_USDHC2_ROOT 195
-#define IMX8MM_CLK_WDOG1_ROOT 196
-#define IMX8MM_CLK_WDOG2_ROOT 197
-#define IMX8MM_CLK_WDOG3_ROOT 198
-#define IMX8MM_CLK_VPU_G1_ROOT 199
-#define IMX8MM_CLK_GPU_BUS_ROOT 200
-#define IMX8MM_CLK_VPU_H1_ROOT 201
-#define IMX8MM_CLK_VPU_G2_ROOT 202
-#define IMX8MM_CLK_PDM_ROOT 203
-#define IMX8MM_CLK_DISP_ROOT 204
-#define IMX8MM_CLK_DISP_AXI_ROOT 205
-#define IMX8MM_CLK_DISP_APB_ROOT 206
-#define IMX8MM_CLK_DISP_RTRM_ROOT 207
-#define IMX8MM_CLK_USDHC3_ROOT 208
-#define IMX8MM_CLK_TMU_ROOT 209
-#define IMX8MM_CLK_VPU_DEC_ROOT 210
-#define IMX8MM_CLK_SDMA1_ROOT 211
-#define IMX8MM_CLK_SDMA2_ROOT 212
-#define IMX8MM_CLK_SDMA3_ROOT 213
-#define IMX8MM_CLK_GPT_3M 214
-#define IMX8MM_CLK_ARM 215
-#define IMX8MM_CLK_PDM_IPG 216
-#define IMX8MM_CLK_GPU2D_ROOT 217
-#define IMX8MM_CLK_MU_ROOT 218
-#define IMX8MM_CLK_CSI1_ROOT 219
-
-#define IMX8MM_CLK_DRAM_CORE 220
-#define IMX8MM_CLK_DRAM_ALT_ROOT 221
-
-#define IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK 222
-
-#define IMX8MM_CLK_GPIO1_ROOT 223
-#define IMX8MM_CLK_GPIO2_ROOT 224
-#define IMX8MM_CLK_GPIO3_ROOT 225
-#define IMX8MM_CLK_GPIO4_ROOT 226
-#define IMX8MM_CLK_GPIO5_ROOT 227
-
-#define IMX8MM_CLK_SNVS_ROOT 228
-#define IMX8MM_CLK_GIC 229
-
-#define IMX8MM_SYS_PLL1_40M_CG 230
-#define IMX8MM_SYS_PLL1_80M_CG 231
-#define IMX8MM_SYS_PLL1_100M_CG 232
-#define IMX8MM_SYS_PLL1_133M_CG 233
-#define IMX8MM_SYS_PLL1_160M_CG 234
-#define IMX8MM_SYS_PLL1_200M_CG 235
-#define IMX8MM_SYS_PLL1_266M_CG 236
-#define IMX8MM_SYS_PLL1_400M_CG 237
-#define IMX8MM_SYS_PLL2_50M_CG 238
-#define IMX8MM_SYS_PLL2_100M_CG 239
-#define IMX8MM_SYS_PLL2_125M_CG 240
-#define IMX8MM_SYS_PLL2_166M_CG 241
-#define IMX8MM_SYS_PLL2_200M_CG 242
-#define IMX8MM_SYS_PLL2_250M_CG 243
-#define IMX8MM_SYS_PLL2_333M_CG 244
-#define IMX8MM_SYS_PLL2_500M_CG 245
-
-#define IMX8MM_CLK_M4_CORE 246
-#define IMX8MM_CLK_VPU_CORE 247
-#define IMX8MM_CLK_GPU3D_CORE 248
-#define IMX8MM_CLK_GPU2D_CORE 249
-
-#define IMX8MM_CLK_CLKO2 250
-
-#define IMX8MM_CLK_A53_CORE 251
-
-#define IMX8MM_CLK_CLKOUT1_SEL 252
-#define IMX8MM_CLK_CLKOUT1_DIV 253
-#define IMX8MM_CLK_CLKOUT1 254
-#define IMX8MM_CLK_CLKOUT2_SEL 255
-#define IMX8MM_CLK_CLKOUT2_DIV 256
-#define IMX8MM_CLK_CLKOUT2 257
-
-#define IMX8MM_CLK_END 258
-
-#endif
diff --git a/include/dt-bindings/clock/imx8mn-clock.h b/include/dt-bindings/clock/imx8mn-clock.h
deleted file mode 100644
index 07b8a28..0000000
--- a/include/dt-bindings/clock/imx8mn-clock.h
+++ /dev/null
@@ -1,262 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright 2018-2019 NXP
- */
-
-#ifndef __DT_BINDINGS_CLOCK_IMX8MN_H
-#define __DT_BINDINGS_CLOCK_IMX8MN_H
-
-#define IMX8MN_CLK_DUMMY 0
-#define IMX8MN_CLK_32K 1
-#define IMX8MN_CLK_24M 2
-#define IMX8MN_OSC_HDMI_CLK 3
-#define IMX8MN_CLK_EXT1 4
-#define IMX8MN_CLK_EXT2 5
-#define IMX8MN_CLK_EXT3 6
-#define IMX8MN_CLK_EXT4 7
-#define IMX8MN_AUDIO_PLL1_REF_SEL 8
-#define IMX8MN_AUDIO_PLL2_REF_SEL 9
-#define IMX8MN_VIDEO_PLL1_REF_SEL 10
-#define IMX8MN_DRAM_PLL_REF_SEL 11
-#define IMX8MN_GPU_PLL_REF_SEL 12
-#define IMX8MN_VPU_PLL_REF_SEL 13
-#define IMX8MN_ARM_PLL_REF_SEL 14
-#define IMX8MN_SYS_PLL1_REF_SEL 15
-#define IMX8MN_SYS_PLL2_REF_SEL 16
-#define IMX8MN_SYS_PLL3_REF_SEL 17
-#define IMX8MN_AUDIO_PLL1 18
-#define IMX8MN_AUDIO_PLL2 19
-#define IMX8MN_VIDEO_PLL1 20
-#define IMX8MN_DRAM_PLL 21
-#define IMX8MN_GPU_PLL 22
-#define IMX8MN_VPU_PLL 23
-#define IMX8MN_ARM_PLL 24
-#define IMX8MN_SYS_PLL1 25
-#define IMX8MN_SYS_PLL2 26
-#define IMX8MN_SYS_PLL3 27
-#define IMX8MN_AUDIO_PLL1_BYPASS 28
-#define IMX8MN_AUDIO_PLL2_BYPASS 29
-#define IMX8MN_VIDEO_PLL1_BYPASS 30
-#define IMX8MN_DRAM_PLL_BYPASS 31
-#define IMX8MN_GPU_PLL_BYPASS 32
-#define IMX8MN_VPU_PLL_BYPASS 33
-#define IMX8MN_ARM_PLL_BYPASS 34
-#define IMX8MN_SYS_PLL1_BYPASS 35
-#define IMX8MN_SYS_PLL2_BYPASS 36
-#define IMX8MN_SYS_PLL3_BYPASS 37
-#define IMX8MN_AUDIO_PLL1_OUT 38
-#define IMX8MN_AUDIO_PLL2_OUT 39
-#define IMX8MN_VIDEO_PLL1_OUT 40
-#define IMX8MN_DRAM_PLL_OUT 41
-#define IMX8MN_GPU_PLL_OUT 42
-#define IMX8MN_VPU_PLL_OUT 43
-#define IMX8MN_ARM_PLL_OUT 44
-#define IMX8MN_SYS_PLL1_OUT 45
-#define IMX8MN_SYS_PLL2_OUT 46
-#define IMX8MN_SYS_PLL3_OUT 47
-#define IMX8MN_SYS_PLL1_40M 48
-#define IMX8MN_SYS_PLL1_80M 49
-#define IMX8MN_SYS_PLL1_100M 50
-#define IMX8MN_SYS_PLL1_133M 51
-#define IMX8MN_SYS_PLL1_160M 52
-#define IMX8MN_SYS_PLL1_200M 53
-#define IMX8MN_SYS_PLL1_266M 54
-#define IMX8MN_SYS_PLL1_400M 55
-#define IMX8MN_SYS_PLL1_800M 56
-#define IMX8MN_SYS_PLL2_50M 57
-#define IMX8MN_SYS_PLL2_100M 58
-#define IMX8MN_SYS_PLL2_125M 59
-#define IMX8MN_SYS_PLL2_166M 60
-#define IMX8MN_SYS_PLL2_200M 61
-#define IMX8MN_SYS_PLL2_250M 62
-#define IMX8MN_SYS_PLL2_333M 63
-#define IMX8MN_SYS_PLL2_500M 64
-#define IMX8MN_SYS_PLL2_1000M 65
-
-/* CORE CLOCK ROOT */
-#define IMX8MN_CLK_A53_SRC 66
-#define IMX8MN_CLK_GPU_CORE_SRC 67
-#define IMX8MN_CLK_GPU_SHADER_SRC 68
-#define IMX8MN_CLK_A53_CG 69
-#define IMX8MN_CLK_GPU_CORE_CG 70
-#define IMX8MN_CLK_GPU_SHADER_CG 71
-#define IMX8MN_CLK_A53_DIV 72
-#define IMX8MN_CLK_GPU_CORE_DIV 73
-#define IMX8MN_CLK_GPU_SHADER_DIV 74
-
-/* BUS CLOCK ROOT */
-#define IMX8MN_CLK_MAIN_AXI 75
-#define IMX8MN_CLK_ENET_AXI 76
-#define IMX8MN_CLK_NAND_USDHC_BUS 77
-#define IMX8MN_CLK_DISP_AXI 78
-#define IMX8MN_CLK_DISP_APB 79
-#define IMX8MN_CLK_USB_BUS 80
-#define IMX8MN_CLK_GPU_AXI 81
-#define IMX8MN_CLK_GPU_AHB 82
-#define IMX8MN_CLK_NOC 83
-#define IMX8MN_CLK_AHB 84
-#define IMX8MN_CLK_AUDIO_AHB 85
-
-/* IPG CLOCK ROOT */
-#define IMX8MN_CLK_IPG_ROOT 86
-#define IMX8MN_CLK_IPG_AUDIO_ROOT 87
-
-/* IP */
-#define IMX8MN_CLK_DRAM_CORE 88
-#define IMX8MN_CLK_DRAM_ALT 89
-#define IMX8MN_CLK_DRAM_APB 90
-#define IMX8MN_CLK_DRAM_ALT_ROOT 91
-#define IMX8MN_CLK_DISP_PIXEL 92
-#define IMX8MN_CLK_SAI2 93
-#define IMX8MN_CLK_SAI3 94
-#define IMX8MN_CLK_SAI5 95
-#define IMX8MN_CLK_SAI6 96
-#define IMX8MN_CLK_SPDIF1 97
-#define IMX8MN_CLK_ENET_REF 98
-#define IMX8MN_CLK_ENET_TIMER 99
-#define IMX8MN_CLK_ENET_PHY_REF 100
-#define IMX8MN_CLK_NAND 101
-#define IMX8MN_CLK_QSPI 102
-#define IMX8MN_CLK_USDHC1 103
-#define IMX8MN_CLK_USDHC2 104
-#define IMX8MN_CLK_I2C1 105
-#define IMX8MN_CLK_I2C2 106
-#define IMX8MN_CLK_I2C3 107
-#define IMX8MN_CLK_I2C4 108
-#define IMX8MN_CLK_UART1 109
-#define IMX8MN_CLK_UART2 110
-#define IMX8MN_CLK_UART3 111
-#define IMX8MN_CLK_UART4 112
-#define IMX8MN_CLK_USB_CORE_REF 113
-#define IMX8MN_CLK_USB_PHY_REF 114
-#define IMX8MN_CLK_ECSPI1 115
-#define IMX8MN_CLK_ECSPI2 116
-#define IMX8MN_CLK_PWM1 117
-#define IMX8MN_CLK_PWM2 118
-#define IMX8MN_CLK_PWM3 119
-#define IMX8MN_CLK_PWM4 120
-#define IMX8MN_CLK_WDOG 121
-#define IMX8MN_CLK_WRCLK 122
-#define IMX8MN_CLK_CLKO1 123
-#define IMX8MN_CLK_CLKO2 124
-#define IMX8MN_CLK_DSI_CORE 125
-#define IMX8MN_CLK_DSI_PHY_REF 126
-#define IMX8MN_CLK_DSI_DBI 127
-#define IMX8MN_CLK_USDHC3 128
-#define IMX8MN_CLK_CAMERA_PIXEL 129
-#define IMX8MN_CLK_CSI1_PHY_REF 130
-#define IMX8MN_CLK_CSI2_PHY_REF 131
-#define IMX8MN_CLK_CSI2_ESC 132
-#define IMX8MN_CLK_ECSPI3 133
-#define IMX8MN_CLK_PDM 134
-#define IMX8MN_CLK_SAI7 135
-
-#define IMX8MN_CLK_ECSPI1_ROOT 136
-#define IMX8MN_CLK_ECSPI2_ROOT 137
-#define IMX8MN_CLK_ECSPI3_ROOT 138
-#define IMX8MN_CLK_ENET1_ROOT 139
-#define IMX8MN_CLK_GPIO1_ROOT 140
-#define IMX8MN_CLK_GPIO2_ROOT 141
-#define IMX8MN_CLK_GPIO3_ROOT 142
-#define IMX8MN_CLK_GPIO4_ROOT 143
-#define IMX8MN_CLK_GPIO5_ROOT 144
-#define IMX8MN_CLK_I2C1_ROOT 145
-#define IMX8MN_CLK_I2C2_ROOT 146
-#define IMX8MN_CLK_I2C3_ROOT 147
-#define IMX8MN_CLK_I2C4_ROOT 148
-#define IMX8MN_CLK_MU_ROOT 149
-#define IMX8MN_CLK_OCOTP_ROOT 150
-#define IMX8MN_CLK_PWM1_ROOT 151
-#define IMX8MN_CLK_PWM2_ROOT 152
-#define IMX8MN_CLK_PWM3_ROOT 153
-#define IMX8MN_CLK_PWM4_ROOT 154
-#define IMX8MN_CLK_QSPI_ROOT 155
-#define IMX8MN_CLK_NAND_ROOT 156
-#define IMX8MN_CLK_SAI2_ROOT 157
-#define IMX8MN_CLK_SAI2_IPG 158
-#define IMX8MN_CLK_SAI3_ROOT 159
-#define IMX8MN_CLK_SAI3_IPG 160
-#define IMX8MN_CLK_SAI5_ROOT 161
-#define IMX8MN_CLK_SAI5_IPG 162
-#define IMX8MN_CLK_SAI6_ROOT 163
-#define IMX8MN_CLK_SAI6_IPG 164
-#define IMX8MN_CLK_SAI7_ROOT 165
-#define IMX8MN_CLK_SAI7_IPG 166
-#define IMX8MN_CLK_SDMA1_ROOT 167
-#define IMX8MN_CLK_SDMA2_ROOT 168
-#define IMX8MN_CLK_UART1_ROOT 169
-#define IMX8MN_CLK_UART2_ROOT 170
-#define IMX8MN_CLK_UART3_ROOT 171
-#define IMX8MN_CLK_UART4_ROOT 172
-#define IMX8MN_CLK_USB1_CTRL_ROOT 173
-#define IMX8MN_CLK_USDHC1_ROOT 174
-#define IMX8MN_CLK_USDHC2_ROOT 175
-#define IMX8MN_CLK_WDOG1_ROOT 176
-#define IMX8MN_CLK_WDOG2_ROOT 177
-#define IMX8MN_CLK_WDOG3_ROOT 178
-#define IMX8MN_CLK_GPU_BUS_ROOT 179
-#define IMX8MN_CLK_ASRC_ROOT 180
-#define IMX8MN_CLK_GPU3D_ROOT 181
-#define IMX8MN_CLK_PDM_ROOT 182
-#define IMX8MN_CLK_PDM_IPG 183
-#define IMX8MN_CLK_DISP_AXI_ROOT 184
-#define IMX8MN_CLK_DISP_APB_ROOT 185
-#define IMX8MN_CLK_DISP_PIXEL_ROOT 186
-#define IMX8MN_CLK_CAMERA_PIXEL_ROOT 187
-#define IMX8MN_CLK_USDHC3_ROOT 188
-#define IMX8MN_CLK_SDMA3_ROOT 189
-#define IMX8MN_CLK_TMU_ROOT 190
-#define IMX8MN_CLK_ARM 191
-#define IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK 192
-#define IMX8MN_CLK_GPU_CORE_ROOT 193
-#define IMX8MN_CLK_GIC 194
-
-#define IMX8MN_SYS_PLL1_40M_CG 195
-#define IMX8MN_SYS_PLL1_80M_CG 196
-#define IMX8MN_SYS_PLL1_100M_CG 197
-#define IMX8MN_SYS_PLL1_133M_CG 198
-#define IMX8MN_SYS_PLL1_160M_CG 199
-#define IMX8MN_SYS_PLL1_200M_CG 200
-#define IMX8MN_SYS_PLL1_266M_CG 201
-#define IMX8MN_SYS_PLL1_400M_CG 202
-#define IMX8MN_SYS_PLL2_50M_CG 203
-#define IMX8MN_SYS_PLL2_100M_CG 204
-#define IMX8MN_SYS_PLL2_125M_CG 205
-#define IMX8MN_SYS_PLL2_166M_CG 206
-#define IMX8MN_SYS_PLL2_200M_CG 207
-#define IMX8MN_SYS_PLL2_250M_CG 208
-#define IMX8MN_SYS_PLL2_333M_CG 209
-#define IMX8MN_SYS_PLL2_500M_CG 210
-
-#define IMX8MN_CLK_SNVS_ROOT 211
-#define IMX8MN_CLK_GPU_CORE 212
-#define IMX8MN_CLK_GPU_SHADER 213
-
-#define IMX8MN_CLK_A53_CORE 214
-
-#define IMX8MN_CLK_CLKOUT1_SEL 215
-#define IMX8MN_CLK_CLKOUT1_DIV 216
-#define IMX8MN_CLK_CLKOUT1 217
-#define IMX8MN_CLK_CLKOUT2_SEL 218
-#define IMX8MN_CLK_CLKOUT2_DIV 219
-#define IMX8MN_CLK_CLKOUT2 220
-
-#define IMX8MN_CLK_M7_CORE 221
-
-#define IMX8MN_CLK_GPT_3M 222
-#define IMX8MN_CLK_GPT1 223
-#define IMX8MN_CLK_GPT1_ROOT 224
-#define IMX8MN_CLK_GPT2 225
-#define IMX8MN_CLK_GPT2_ROOT 226
-#define IMX8MN_CLK_GPT3 227
-#define IMX8MN_CLK_GPT3_ROOT 228
-#define IMX8MN_CLK_GPT4 229
-#define IMX8MN_CLK_GPT4_ROOT 230
-#define IMX8MN_CLK_GPT5 231
-#define IMX8MN_CLK_GPT5_ROOT 232
-#define IMX8MN_CLK_GPT6 233
-#define IMX8MN_CLK_GPT6_ROOT 234
-
-#define IMX8MN_CLK_END 235
-
-#endif
diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h
deleted file mode 100644
index 7da4243..0000000
--- a/include/dt-bindings/clock/imx8mp-clock.h
+++ /dev/null
@@ -1,401 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright 2019 NXP
- */
-
-#ifndef __DT_BINDINGS_CLOCK_IMX8MP_H
-#define __DT_BINDINGS_CLOCK_IMX8MP_H
-
-#define IMX8MP_CLK_DUMMY 0
-#define IMX8MP_CLK_32K 1
-#define IMX8MP_CLK_24M 2
-#define IMX8MP_OSC_HDMI_CLK 3
-#define IMX8MP_CLK_EXT1 4
-#define IMX8MP_CLK_EXT2 5
-#define IMX8MP_CLK_EXT3 6
-#define IMX8MP_CLK_EXT4 7
-#define IMX8MP_AUDIO_PLL1_REF_SEL 8
-#define IMX8MP_AUDIO_PLL2_REF_SEL 9
-#define IMX8MP_VIDEO_PLL1_REF_SEL 10
-#define IMX8MP_DRAM_PLL_REF_SEL 11
-#define IMX8MP_GPU_PLL_REF_SEL 12
-#define IMX8MP_VPU_PLL_REF_SEL 13
-#define IMX8MP_ARM_PLL_REF_SEL 14
-#define IMX8MP_SYS_PLL1_REF_SEL 15
-#define IMX8MP_SYS_PLL2_REF_SEL 16
-#define IMX8MP_SYS_PLL3_REF_SEL 17
-#define IMX8MP_AUDIO_PLL1 18
-#define IMX8MP_AUDIO_PLL2 19
-#define IMX8MP_VIDEO_PLL1 20
-#define IMX8MP_DRAM_PLL 21
-#define IMX8MP_GPU_PLL 22
-#define IMX8MP_VPU_PLL 23
-#define IMX8MP_ARM_PLL 24
-#define IMX8MP_SYS_PLL1 25
-#define IMX8MP_SYS_PLL2 26
-#define IMX8MP_SYS_PLL3 27
-#define IMX8MP_AUDIO_PLL1_BYPASS 28
-#define IMX8MP_AUDIO_PLL2_BYPASS 29
-#define IMX8MP_VIDEO_PLL1_BYPASS 30
-#define IMX8MP_DRAM_PLL_BYPASS 31
-#define IMX8MP_GPU_PLL_BYPASS 32
-#define IMX8MP_VPU_PLL_BYPASS 33
-#define IMX8MP_ARM_PLL_BYPASS 34
-#define IMX8MP_SYS_PLL1_BYPASS 35
-#define IMX8MP_SYS_PLL2_BYPASS 36
-#define IMX8MP_SYS_PLL3_BYPASS 37
-#define IMX8MP_AUDIO_PLL1_OUT 38
-#define IMX8MP_AUDIO_PLL2_OUT 39
-#define IMX8MP_VIDEO_PLL1_OUT 40
-#define IMX8MP_DRAM_PLL_OUT 41
-#define IMX8MP_GPU_PLL_OUT 42
-#define IMX8MP_VPU_PLL_OUT 43
-#define IMX8MP_ARM_PLL_OUT 44
-#define IMX8MP_SYS_PLL1_OUT 45
-#define IMX8MP_SYS_PLL2_OUT 46
-#define IMX8MP_SYS_PLL3_OUT 47
-#define IMX8MP_SYS_PLL1_40M 48
-#define IMX8MP_SYS_PLL1_80M 49
-#define IMX8MP_SYS_PLL1_100M 50
-#define IMX8MP_SYS_PLL1_133M 51
-#define IMX8MP_SYS_PLL1_160M 52
-#define IMX8MP_SYS_PLL1_200M 53
-#define IMX8MP_SYS_PLL1_266M 54
-#define IMX8MP_SYS_PLL1_400M 55
-#define IMX8MP_SYS_PLL1_800M 56
-#define IMX8MP_SYS_PLL2_50M 57
-#define IMX8MP_SYS_PLL2_100M 58
-#define IMX8MP_SYS_PLL2_125M 59
-#define IMX8MP_SYS_PLL2_166M 60
-#define IMX8MP_SYS_PLL2_200M 61
-#define IMX8MP_SYS_PLL2_250M 62
-#define IMX8MP_SYS_PLL2_333M 63
-#define IMX8MP_SYS_PLL2_500M 64
-#define IMX8MP_SYS_PLL2_1000M 65
-#define IMX8MP_CLK_A53_SRC 66
-#define IMX8MP_CLK_M7_SRC 67
-#define IMX8MP_CLK_ML_SRC 68
-#define IMX8MP_CLK_GPU3D_CORE_SRC 69
-#define IMX8MP_CLK_GPU3D_SHADER_SRC 70
-#define IMX8MP_CLK_GPU2D_SRC 71
-#define IMX8MP_CLK_AUDIO_AXI_SRC 72
-#define IMX8MP_CLK_HSIO_AXI_SRC 73
-#define IMX8MP_CLK_MEDIA_ISP_SRC 74
-#define IMX8MP_CLK_A53_CG 75
-#define IMX8MP_CLK_M4_CG 76
-#define IMX8MP_CLK_ML_CG 77
-#define IMX8MP_CLK_GPU3D_CORE_CG 78
-#define IMX8MP_CLK_GPU3D_SHADER_CG 79
-#define IMX8MP_CLK_GPU2D_CG 80
-#define IMX8MP_CLK_AUDIO_AXI_CG 81
-#define IMX8MP_CLK_HSIO_AXI_CG 82
-#define IMX8MP_CLK_MEDIA_ISP_CG 83
-#define IMX8MP_CLK_A53_DIV 84
-#define IMX8MP_CLK_M7_DIV 85
-#define IMX8MP_CLK_ML_DIV 86
-#define IMX8MP_CLK_GPU3D_CORE_DIV 87
-#define IMX8MP_CLK_GPU3D_SHADER_DIV 88
-#define IMX8MP_CLK_GPU2D_DIV 89
-#define IMX8MP_CLK_AUDIO_AXI_DIV 90
-#define IMX8MP_CLK_HSIO_AXI_DIV 91
-#define IMX8MP_CLK_MEDIA_ISP_DIV 92
-#define IMX8MP_CLK_MAIN_AXI 93
-#define IMX8MP_CLK_ENET_AXI 94
-#define IMX8MP_CLK_NAND_USDHC_BUS 95
-#define IMX8MP_CLK_VPU_BUS 96
-#define IMX8MP_CLK_MEDIA_AXI 97
-#define IMX8MP_CLK_MEDIA_APB 98
-#define IMX8MP_CLK_HDMI_APB 99
-#define IMX8MP_CLK_HDMI_AXI 100
-#define IMX8MP_CLK_GPU_AXI 101
-#define IMX8MP_CLK_GPU_AHB 102
-#define IMX8MP_CLK_NOC 103
-#define IMX8MP_CLK_NOC_IO 104
-#define IMX8MP_CLK_ML_AXI 105
-#define IMX8MP_CLK_ML_AHB 106
-#define IMX8MP_CLK_AHB 107
-#define IMX8MP_CLK_AUDIO_AHB 108
-#define IMX8MP_CLK_MIPI_DSI_ESC_RX 109
-#define IMX8MP_CLK_IPG_ROOT 110
-#define IMX8MP_CLK_DRAM_ALT 112
-#define IMX8MP_CLK_DRAM_APB 113
-#define IMX8MP_CLK_VPU_G1 114
-#define IMX8MP_CLK_VPU_G2 115
-#define IMX8MP_CLK_CAN1 116
-#define IMX8MP_CLK_CAN2 117
-#define IMX8MP_CLK_MEMREPAIR 118
-#define IMX8MP_CLK_PCIE_AUX 120
-#define IMX8MP_CLK_I2C5 121
-#define IMX8MP_CLK_I2C6 122
-#define IMX8MP_CLK_SAI1 123
-#define IMX8MP_CLK_SAI2 124
-#define IMX8MP_CLK_SAI3 125
-/* #define IMX8MP_CLK_SAI4 126 */
-#define IMX8MP_CLK_SAI5 127
-#define IMX8MP_CLK_SAI6 128
-#define IMX8MP_CLK_ENET_QOS 129
-#define IMX8MP_CLK_ENET_QOS_TIMER 130
-#define IMX8MP_CLK_ENET_REF 131
-#define IMX8MP_CLK_ENET_TIMER 132
-#define IMX8MP_CLK_ENET_PHY_REF 133
-#define IMX8MP_CLK_NAND 134
-#define IMX8MP_CLK_QSPI 135
-#define IMX8MP_CLK_USDHC1 136
-#define IMX8MP_CLK_USDHC2 137
-#define IMX8MP_CLK_I2C1 138
-#define IMX8MP_CLK_I2C2 139
-#define IMX8MP_CLK_I2C3 140
-#define IMX8MP_CLK_I2C4 141
-#define IMX8MP_CLK_UART1 142
-#define IMX8MP_CLK_UART2 143
-#define IMX8MP_CLK_UART3 144
-#define IMX8MP_CLK_UART4 145
-#define IMX8MP_CLK_USB_CORE_REF 146
-#define IMX8MP_CLK_USB_PHY_REF 147
-#define IMX8MP_CLK_GIC 148
-#define IMX8MP_CLK_ECSPI1 149
-#define IMX8MP_CLK_ECSPI2 150
-#define IMX8MP_CLK_PWM1 151
-#define IMX8MP_CLK_PWM2 152
-#define IMX8MP_CLK_PWM3 153
-#define IMX8MP_CLK_PWM4 154
-#define IMX8MP_CLK_GPT1 155
-#define IMX8MP_CLK_GPT2 156
-#define IMX8MP_CLK_GPT3 157
-#define IMX8MP_CLK_GPT4 158
-#define IMX8MP_CLK_GPT5 159
-#define IMX8MP_CLK_GPT6 160
-#define IMX8MP_CLK_TRACE 161
-#define IMX8MP_CLK_WDOG 162
-#define IMX8MP_CLK_WRCLK 163
-#define IMX8MP_CLK_IPP_DO_CLKO1 164
-#define IMX8MP_CLK_IPP_DO_CLKO2 165
-#define IMX8MP_CLK_HDMI_FDCC_TST 166
-#define IMX8MP_CLK_HDMI_24M 167
-#define IMX8MP_CLK_HDMI_REF_266M 168
-#define IMX8MP_CLK_USDHC3 169
-#define IMX8MP_CLK_MEDIA_CAM1_PIX 170
-#define IMX8MP_CLK_MEDIA_MIPI_PHY1_REF 171
-#define IMX8MP_CLK_MEDIA_DISP1_PIX 172
-#define IMX8MP_CLK_MEDIA_CAM2_PIX 173
-#define IMX8MP_CLK_MEDIA_LDB 174
-#define IMX8MP_CLK_MEDIA_MIPI_CSI2_ESC 175
-#define IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE 178
-#define IMX8MP_CLK_ECSPI3 179
-#define IMX8MP_CLK_PDM 180
-#define IMX8MP_CLK_VPU_VC8000E 181
-#define IMX8MP_CLK_SAI7 182
-#define IMX8MP_CLK_GPC_ROOT 183
-#define IMX8MP_CLK_ANAMIX_ROOT 184
-#define IMX8MP_CLK_CPU_ROOT 185
-#define IMX8MP_CLK_CSU_ROOT 186
-#define IMX8MP_CLK_DEBUG_ROOT 187
-#define IMX8MP_CLK_DRAM1_ROOT 188
-#define IMX8MP_CLK_ECSPI1_ROOT 189
-#define IMX8MP_CLK_ECSPI2_ROOT 190
-#define IMX8MP_CLK_ECSPI3_ROOT 191
-#define IMX8MP_CLK_ENET1_ROOT 192
-#define IMX8MP_CLK_GPIO1_ROOT 193
-#define IMX8MP_CLK_GPIO2_ROOT 194
-#define IMX8MP_CLK_GPIO3_ROOT 195
-#define IMX8MP_CLK_GPIO4_ROOT 196
-#define IMX8MP_CLK_GPIO5_ROOT 197
-#define IMX8MP_CLK_GPT1_ROOT 198
-#define IMX8MP_CLK_GPT2_ROOT 199
-#define IMX8MP_CLK_GPT3_ROOT 200
-#define IMX8MP_CLK_GPT4_ROOT 201
-#define IMX8MP_CLK_GPT5_ROOT 202
-#define IMX8MP_CLK_GPT6_ROOT 203
-#define IMX8MP_CLK_HS_ROOT 204
-#define IMX8MP_CLK_I2C1_ROOT 205
-#define IMX8MP_CLK_I2C2_ROOT 206
-#define IMX8MP_CLK_I2C3_ROOT 207
-#define IMX8MP_CLK_I2C4_ROOT 208
-#define IMX8MP_CLK_IOMUX_ROOT 209
-#define IMX8MP_CLK_IPMUX1_ROOT 210
-#define IMX8MP_CLK_IPMUX2_ROOT 211
-#define IMX8MP_CLK_IPMUX3_ROOT 212
-#define IMX8MP_CLK_MU_ROOT 213
-#define IMX8MP_CLK_OCOTP_ROOT 214
-#define IMX8MP_CLK_OCRAM_ROOT 215
-#define IMX8MP_CLK_OCRAM_S_ROOT 216
-#define IMX8MP_CLK_PCIE_ROOT 217
-#define IMX8MP_CLK_PERFMON1_ROOT 218
-#define IMX8MP_CLK_PERFMON2_ROOT 219
-#define IMX8MP_CLK_PWM1_ROOT 220
-#define IMX8MP_CLK_PWM2_ROOT 221
-#define IMX8MP_CLK_PWM3_ROOT 222
-#define IMX8MP_CLK_PWM4_ROOT 223
-#define IMX8MP_CLK_QOS_ROOT 224
-#define IMX8MP_CLK_QOS_ENET_ROOT 225
-#define IMX8MP_CLK_QSPI_ROOT 226
-#define IMX8MP_CLK_NAND_ROOT 227
-#define IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK 228
-#define IMX8MP_CLK_RDC_ROOT 229
-#define IMX8MP_CLK_ROM_ROOT 230
-#define IMX8MP_CLK_I2C5_ROOT 231
-#define IMX8MP_CLK_I2C6_ROOT 232
-#define IMX8MP_CLK_CAN1_ROOT 233
-#define IMX8MP_CLK_CAN2_ROOT 234
-#define IMX8MP_CLK_SCTR_ROOT 235
-#define IMX8MP_CLK_SDMA1_ROOT 236
-#define IMX8MP_CLK_ENET_QOS_ROOT 237
-#define IMX8MP_CLK_SEC_DEBUG_ROOT 238
-#define IMX8MP_CLK_SEMA1_ROOT 239
-#define IMX8MP_CLK_SEMA2_ROOT 240
-#define IMX8MP_CLK_IRQ_STEER_ROOT 241
-#define IMX8MP_CLK_SIM_ENET_ROOT 242
-#define IMX8MP_CLK_SIM_M_ROOT 243
-#define IMX8MP_CLK_SIM_MAIN_ROOT 244
-#define IMX8MP_CLK_SIM_S_ROOT 245
-#define IMX8MP_CLK_SIM_WAKEUP_ROOT 246
-#define IMX8MP_CLK_GPU2D_ROOT 247
-#define IMX8MP_CLK_GPU3D_ROOT 248
-#define IMX8MP_CLK_SNVS_ROOT 249
-#define IMX8MP_CLK_TRACE_ROOT 250
-#define IMX8MP_CLK_UART1_ROOT 251
-#define IMX8MP_CLK_UART2_ROOT 252
-#define IMX8MP_CLK_UART3_ROOT 253
-#define IMX8MP_CLK_UART4_ROOT 254
-#define IMX8MP_CLK_USB_ROOT 255
-#define IMX8MP_CLK_USB_PHY_ROOT 256
-#define IMX8MP_CLK_USDHC1_ROOT 257
-#define IMX8MP_CLK_USDHC2_ROOT 258
-#define IMX8MP_CLK_WDOG1_ROOT 259
-#define IMX8MP_CLK_WDOG2_ROOT 260
-#define IMX8MP_CLK_WDOG3_ROOT 261
-#define IMX8MP_CLK_VPU_G1_ROOT 262
-#define IMX8MP_CLK_GPU_ROOT 263
-#define IMX8MP_CLK_NOC_WRAPPER_ROOT 264
-#define IMX8MP_CLK_VPU_VC8KE_ROOT 265
-#define IMX8MP_CLK_VPU_G2_ROOT 266
-#define IMX8MP_CLK_NPU_ROOT 267
-#define IMX8MP_CLK_HSIO_ROOT 268
-#define IMX8MP_CLK_MEDIA_APB_ROOT 269
-#define IMX8MP_CLK_MEDIA_AXI_ROOT 270
-#define IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT 271
-#define IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT 272
-#define IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT 273
-#define IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT 274
-#define IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT 275
-#define IMX8MP_CLK_MEDIA_ISP_ROOT 276
-#define IMX8MP_CLK_USDHC3_ROOT 277
-#define IMX8MP_CLK_HDMI_ROOT 278
-#define IMX8MP_CLK_XTAL_ROOT 279
-#define IMX8MP_CLK_PLL_ROOT 280
-#define IMX8MP_CLK_TSENSOR_ROOT 281
-#define IMX8MP_CLK_VPU_ROOT 282
-#define IMX8MP_CLK_MRPR_ROOT 283
-#define IMX8MP_CLK_AUDIO_ROOT 284
-#define IMX8MP_CLK_DRAM_ALT_ROOT 285
-#define IMX8MP_CLK_DRAM_CORE 286
-#define IMX8MP_CLK_ARM 287
-#define IMX8MP_CLK_A53_CORE 288
-
-#define IMX8MP_SYS_PLL1_40M_CG 289
-#define IMX8MP_SYS_PLL1_80M_CG 290
-#define IMX8MP_SYS_PLL1_100M_CG 291
-#define IMX8MP_SYS_PLL1_133M_CG 292
-#define IMX8MP_SYS_PLL1_160M_CG 293
-#define IMX8MP_SYS_PLL1_200M_CG 294
-#define IMX8MP_SYS_PLL1_266M_CG 295
-#define IMX8MP_SYS_PLL1_400M_CG 296
-#define IMX8MP_SYS_PLL2_50M_CG 297
-#define IMX8MP_SYS_PLL2_100M_CG 298
-#define IMX8MP_SYS_PLL2_125M_CG 299
-#define IMX8MP_SYS_PLL2_166M_CG 300
-#define IMX8MP_SYS_PLL2_200M_CG 301
-#define IMX8MP_SYS_PLL2_250M_CG 302
-#define IMX8MP_SYS_PLL2_333M_CG 303
-#define IMX8MP_SYS_PLL2_500M_CG 304
-
-#define IMX8MP_CLK_M7_CORE 305
-#define IMX8MP_CLK_ML_CORE 306
-#define IMX8MP_CLK_GPU3D_CORE 307
-#define IMX8MP_CLK_GPU3D_SHADER_CORE 308
-#define IMX8MP_CLK_GPU2D_CORE 309
-#define IMX8MP_CLK_AUDIO_AXI 310
-#define IMX8MP_CLK_HSIO_AXI 311
-#define IMX8MP_CLK_MEDIA_ISP 312
-#define IMX8MP_CLK_MEDIA_DISP2_PIX 313
-#define IMX8MP_CLK_CLKOUT1_SEL 314
-#define IMX8MP_CLK_CLKOUT1_DIV 315
-#define IMX8MP_CLK_CLKOUT1 316
-#define IMX8MP_CLK_CLKOUT2_SEL 317
-#define IMX8MP_CLK_CLKOUT2_DIV 318
-#define IMX8MP_CLK_CLKOUT2 319
-#define IMX8MP_CLK_USB_SUSP 320
-#define IMX8MP_CLK_AUDIO_AHB_ROOT IMX8MP_CLK_AUDIO_ROOT
-#define IMX8MP_CLK_AUDIO_AXI_ROOT 321
-#define IMX8MP_CLK_SAI1_ROOT 322
-#define IMX8MP_CLK_SAI2_ROOT 323
-#define IMX8MP_CLK_SAI3_ROOT 324
-#define IMX8MP_CLK_SAI5_ROOT 325
-#define IMX8MP_CLK_SAI6_ROOT 326
-#define IMX8MP_CLK_SAI7_ROOT 327
-#define IMX8MP_CLK_PDM_ROOT 328
-#define IMX8MP_CLK_MEDIA_LDB_ROOT 329
-#define IMX8MP_CLK_END 330
-
-#define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0
-#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1
-#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2 2
-#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3 3
-#define IMX8MP_CLK_AUDIOMIX_SAI2_IPG 4
-#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1 5
-#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2 6
-#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3 7
-#define IMX8MP_CLK_AUDIOMIX_SAI3_IPG 8
-#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1 9
-#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2 10
-#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3 11
-#define IMX8MP_CLK_AUDIOMIX_SAI5_IPG 12
-#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1 13
-#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2 14
-#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3 15
-#define IMX8MP_CLK_AUDIOMIX_SAI6_IPG 16
-#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1 17
-#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2 18
-#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3 19
-#define IMX8MP_CLK_AUDIOMIX_SAI7_IPG 20
-#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1 21
-#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2 22
-#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3 23
-#define IMX8MP_CLK_AUDIOMIX_ASRC_IPG 24
-#define IMX8MP_CLK_AUDIOMIX_PDM_IPG 25
-#define IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT 26
-#define IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT 27
-#define IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT 28
-#define IMX8MP_CLK_AUDIOMIX_DSP_ROOT 29
-#define IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT 30
-#define IMX8MP_CLK_AUDIOMIX_EARC_IPG 31
-#define IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG 32
-#define IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG 33
-#define IMX8MP_CLK_AUDIOMIX_EDMA_ROOT 34
-#define IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT 35
-#define IMX8MP_CLK_AUDIOMIX_MU2_ROOT 36
-#define IMX8MP_CLK_AUDIOMIX_MU3_ROOT 37
-#define IMX8MP_CLK_AUDIOMIX_EARC_PHY 38
-#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1_SEL 40
-#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2_SEL 41
-#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1_SEL 42
-#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2_SEL 43
-#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1_SEL 44
-#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2_SEL 45
-#define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK1_SEL 46
-#define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK2_SEL 47
-#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1_SEL 48
-#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2_SEL 49
-#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1_SEL 50
-#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2_SEL 51
-#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1_SEL 52
-#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2_SEL 53
-#define IMX8MP_CLK_AUDIOMIX_PDM_SEL 54
-#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_REF_SEL 55
-#define IMX8MP_CLK_AUDIOMIX_SAI_PLL 56
-#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS 57
-#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_OUT 58
-
-#define IMX8MP_CLK_AUDIOMIX_END 59
-
-#endif
diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h
deleted file mode 100644
index afa74d7..0000000
--- a/include/dt-bindings/clock/imx8mq-clock.h
+++ /dev/null
@@ -1,431 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
- */
-
-#ifndef __DT_BINDINGS_CLOCK_IMX8MQ_H
-#define __DT_BINDINGS_CLOCK_IMX8MQ_H
-
-#define IMX8MQ_CLK_DUMMY 0
-#define IMX8MQ_CLK_32K 1
-#define IMX8MQ_CLK_25M 2
-#define IMX8MQ_CLK_27M 3
-#define IMX8MQ_CLK_EXT1 4
-#define IMX8MQ_CLK_EXT2 5
-#define IMX8MQ_CLK_EXT3 6
-#define IMX8MQ_CLK_EXT4 7
-
-/* ANAMIX PLL clocks */
-/* FRAC PLLs */
-/* ARM PLL */
-#define IMX8MQ_ARM_PLL_REF_SEL 8
-#define IMX8MQ_ARM_PLL_REF_DIV 9
-#define IMX8MQ_ARM_PLL 10
-#define IMX8MQ_ARM_PLL_BYPASS 11
-#define IMX8MQ_ARM_PLL_OUT 12
-
-/* GPU PLL */
-#define IMX8MQ_GPU_PLL_REF_SEL 13
-#define IMX8MQ_GPU_PLL_REF_DIV 14
-#define IMX8MQ_GPU_PLL 15
-#define IMX8MQ_GPU_PLL_BYPASS 16
-#define IMX8MQ_GPU_PLL_OUT 17
-
-/* VPU PLL */
-#define IMX8MQ_VPU_PLL_REF_SEL 18
-#define IMX8MQ_VPU_PLL_REF_DIV 19
-#define IMX8MQ_VPU_PLL 20
-#define IMX8MQ_VPU_PLL_BYPASS 21
-#define IMX8MQ_VPU_PLL_OUT 22
-
-/* AUDIO PLL1 */
-#define IMX8MQ_AUDIO_PLL1_REF_SEL 23
-#define IMX8MQ_AUDIO_PLL1_REF_DIV 24
-#define IMX8MQ_AUDIO_PLL1 25
-#define IMX8MQ_AUDIO_PLL1_BYPASS 26
-#define IMX8MQ_AUDIO_PLL1_OUT 27
-
-/* AUDIO PLL2 */
-#define IMX8MQ_AUDIO_PLL2_REF_SEL 28
-#define IMX8MQ_AUDIO_PLL2_REF_DIV 29
-#define IMX8MQ_AUDIO_PLL2 30
-#define IMX8MQ_AUDIO_PLL2_BYPASS 31
-#define IMX8MQ_AUDIO_PLL2_OUT 32
-
-/* VIDEO PLL1 */
-#define IMX8MQ_VIDEO_PLL1_REF_SEL 33
-#define IMX8MQ_VIDEO_PLL1_REF_DIV 34
-#define IMX8MQ_VIDEO_PLL1 35
-#define IMX8MQ_VIDEO_PLL1_BYPASS 36
-#define IMX8MQ_VIDEO_PLL1_OUT 37
-
-/* SYS1 PLL */
-#define IMX8MQ_SYS1_PLL1_REF_SEL 38
-#define IMX8MQ_SYS1_PLL1_REF_DIV 39
-#define IMX8MQ_SYS1_PLL1 40
-#define IMX8MQ_SYS1_PLL1_OUT 41
-#define IMX8MQ_SYS1_PLL1_OUT_DIV 42
-#define IMX8MQ_SYS1_PLL2 43
-#define IMX8MQ_SYS1_PLL2_DIV 44
-#define IMX8MQ_SYS1_PLL2_OUT 45
-
-/* SYS2 PLL */
-#define IMX8MQ_SYS2_PLL1_REF_SEL 46
-#define IMX8MQ_SYS2_PLL1_REF_DIV 47
-#define IMX8MQ_SYS2_PLL1 48
-#define IMX8MQ_SYS2_PLL1_OUT 49
-#define IMX8MQ_SYS2_PLL1_OUT_DIV 50
-#define IMX8MQ_SYS2_PLL2 51
-#define IMX8MQ_SYS2_PLL2_DIV 52
-#define IMX8MQ_SYS2_PLL2_OUT 53
-
-/* SYS3 PLL */
-#define IMX8MQ_SYS3_PLL1_REF_SEL 54
-#define IMX8MQ_SYS3_PLL1_REF_DIV 55
-#define IMX8MQ_SYS3_PLL1 56
-#define IMX8MQ_SYS3_PLL1_OUT 57
-#define IMX8MQ_SYS3_PLL1_OUT_DIV 58
-#define IMX8MQ_SYS3_PLL2 59
-#define IMX8MQ_SYS3_PLL2_DIV 60
-#define IMX8MQ_SYS3_PLL2_OUT 61
-
-/* DRAM PLL */
-#define IMX8MQ_DRAM_PLL1_REF_SEL 62
-#define IMX8MQ_DRAM_PLL1_REF_DIV 63
-#define IMX8MQ_DRAM_PLL1 64
-#define IMX8MQ_DRAM_PLL1_OUT 65
-#define IMX8MQ_DRAM_PLL1_OUT_DIV 66
-#define IMX8MQ_DRAM_PLL2 67
-#define IMX8MQ_DRAM_PLL2_DIV 68
-#define IMX8MQ_DRAM_PLL2_OUT 69
-
-/* SYS PLL DIV */
-#define IMX8MQ_SYS1_PLL_40M 70
-#define IMX8MQ_SYS1_PLL_80M 71
-#define IMX8MQ_SYS1_PLL_100M 72
-#define IMX8MQ_SYS1_PLL_133M 73
-#define IMX8MQ_SYS1_PLL_160M 74
-#define IMX8MQ_SYS1_PLL_200M 75
-#define IMX8MQ_SYS1_PLL_266M 76
-#define IMX8MQ_SYS1_PLL_400M 77
-#define IMX8MQ_SYS1_PLL_800M 78
-
-#define IMX8MQ_SYS2_PLL_50M 79
-#define IMX8MQ_SYS2_PLL_100M 80
-#define IMX8MQ_SYS2_PLL_125M 81
-#define IMX8MQ_SYS2_PLL_166M 82
-#define IMX8MQ_SYS2_PLL_200M 83
-#define IMX8MQ_SYS2_PLL_250M 84
-#define IMX8MQ_SYS2_PLL_333M 85
-#define IMX8MQ_SYS2_PLL_500M 86
-#define IMX8MQ_SYS2_PLL_1000M 87
-
-/* CCM ROOT clocks */
-/* A53 */
-#define IMX8MQ_CLK_A53_SRC 88
-#define IMX8MQ_CLK_A53_CG 89
-#define IMX8MQ_CLK_A53_DIV 90
-/* M4 */
-#define IMX8MQ_CLK_M4_SRC 91
-#define IMX8MQ_CLK_M4_CG 92
-#define IMX8MQ_CLK_M4_DIV 93
-/* VPU */
-#define IMX8MQ_CLK_VPU_SRC 94
-#define IMX8MQ_CLK_VPU_CG 95
-#define IMX8MQ_CLK_VPU_DIV 96
-/* GPU CORE */
-#define IMX8MQ_CLK_GPU_CORE_SRC 97
-#define IMX8MQ_CLK_GPU_CORE_CG 98
-#define IMX8MQ_CLK_GPU_CORE_DIV 99
-/* GPU SHADER */
-#define IMX8MQ_CLK_GPU_SHADER_SRC 100
-#define IMX8MQ_CLK_GPU_SHADER_CG 101
-#define IMX8MQ_CLK_GPU_SHADER_DIV 102
-
-/* BUS TYPE */
-/* MAIN AXI */
-#define IMX8MQ_CLK_MAIN_AXI 103
-/* ENET AXI */
-#define IMX8MQ_CLK_ENET_AXI 104
-/* NAND_USDHC_BUS */
-#define IMX8MQ_CLK_NAND_USDHC_BUS 105
-/* VPU BUS */
-#define IMX8MQ_CLK_VPU_BUS 106
-/* DISP_AXI */
-#define IMX8MQ_CLK_DISP_AXI 107
-/* DISP APB */
-#define IMX8MQ_CLK_DISP_APB 108
-/* DISP RTRM */
-#define IMX8MQ_CLK_DISP_RTRM 109
-/* USB_BUS */
-#define IMX8MQ_CLK_USB_BUS 110
-/* GPU_AXI */
-#define IMX8MQ_CLK_GPU_AXI 111
-/* GPU_AHB */
-#define IMX8MQ_CLK_GPU_AHB 112
-/* NOC */
-#define IMX8MQ_CLK_NOC 113
-/* NOC_APB */
-#define IMX8MQ_CLK_NOC_APB 115
-
-/* AHB */
-#define IMX8MQ_CLK_AHB 116
-/* AUDIO AHB */
-#define IMX8MQ_CLK_AUDIO_AHB 117
-
-/* DRAM_ALT */
-#define IMX8MQ_CLK_DRAM_ALT 118
-/* DRAM APB */
-#define IMX8MQ_CLK_DRAM_APB 119
-/* VPU_G1 */
-#define IMX8MQ_CLK_VPU_G1 120
-/* VPU_G2 */
-#define IMX8MQ_CLK_VPU_G2 121
-/* DISP_DTRC */
-#define IMX8MQ_CLK_DISP_DTRC 122
-/* DISP_DC8000 */
-#define IMX8MQ_CLK_DISP_DC8000 123
-/* PCIE_CTRL */
-#define IMX8MQ_CLK_PCIE1_CTRL 124
-/* PCIE_PHY */
-#define IMX8MQ_CLK_PCIE1_PHY 125
-/* PCIE_AUX */
-#define IMX8MQ_CLK_PCIE1_AUX 126
-/* DC_PIXEL */
-#define IMX8MQ_CLK_DC_PIXEL 127
-/* LCDIF_PIXEL */
-#define IMX8MQ_CLK_LCDIF_PIXEL 128
-/* SAI1~6 */
-#define IMX8MQ_CLK_SAI1 129
-
-#define IMX8MQ_CLK_SAI2 130
-
-#define IMX8MQ_CLK_SAI3 131
-
-#define IMX8MQ_CLK_SAI4 132
-
-#define IMX8MQ_CLK_SAI5 133
-
-#define IMX8MQ_CLK_SAI6 134
-/* SPDIF1 */
-#define IMX8MQ_CLK_SPDIF1 135
-/* SPDIF2 */
-#define IMX8MQ_CLK_SPDIF2 136
-/* ENET_REF */
-#define IMX8MQ_CLK_ENET_REF 137
-/* ENET_TIMER */
-#define IMX8MQ_CLK_ENET_TIMER 138
-/* ENET_PHY */
-#define IMX8MQ_CLK_ENET_PHY_REF 139
-/* NAND */
-#define IMX8MQ_CLK_NAND 140
-/* QSPI */
-#define IMX8MQ_CLK_QSPI 141
-/* USDHC1 */
-#define IMX8MQ_CLK_USDHC1 142
-/* USDHC2 */
-#define IMX8MQ_CLK_USDHC2 143
-/* I2C1 */
-#define IMX8MQ_CLK_I2C1 144
-/* I2C2 */
-#define IMX8MQ_CLK_I2C2 145
-/* I2C3 */
-#define IMX8MQ_CLK_I2C3 146
-/* I2C4 */
-#define IMX8MQ_CLK_I2C4 147
-/* UART1 */
-#define IMX8MQ_CLK_UART1 148
-/* UART2 */
-#define IMX8MQ_CLK_UART2 149
-/* UART3 */
-#define IMX8MQ_CLK_UART3 150
-/* UART4 */
-#define IMX8MQ_CLK_UART4 151
-/* USB_CORE_REF */
-#define IMX8MQ_CLK_USB_CORE_REF 152
-/* USB_PHY_REF */
-#define IMX8MQ_CLK_USB_PHY_REF 153
-/* ECSPI1 */
-#define IMX8MQ_CLK_ECSPI1 154
-/* ECSPI2 */
-#define IMX8MQ_CLK_ECSPI2 155
-/* PWM1 */
-#define IMX8MQ_CLK_PWM1 156
-/* PWM2 */
-#define IMX8MQ_CLK_PWM2 157
-/* PWM3 */
-#define IMX8MQ_CLK_PWM3 158
-/* PWM4 */
-#define IMX8MQ_CLK_PWM4 159
-/* GPT1 */
-#define IMX8MQ_CLK_GPT1 160
-/* WDOG */
-#define IMX8MQ_CLK_WDOG 161
-/* WRCLK */
-#define IMX8MQ_CLK_WRCLK 162
-/* DSI_CORE */
-#define IMX8MQ_CLK_DSI_CORE 163
-/* DSI_PHY */
-#define IMX8MQ_CLK_DSI_PHY_REF 164
-/* DSI_DBI */
-#define IMX8MQ_CLK_DSI_DBI 165
-/*DSI_ESC */
-#define IMX8MQ_CLK_DSI_ESC 166
-/* CSI1_CORE */
-#define IMX8MQ_CLK_CSI1_CORE 167
-/* CSI1_PHY */
-#define IMX8MQ_CLK_CSI1_PHY_REF 168
-/* CSI_ESC */
-#define IMX8MQ_CLK_CSI1_ESC 169
-/* CSI2_CORE */
-#define IMX8MQ_CLK_CSI2_CORE 170
-/* CSI2_PHY */
-#define IMX8MQ_CLK_CSI2_PHY_REF 171
-/* CSI2_ESC */
-#define IMX8MQ_CLK_CSI2_ESC 172
-/* PCIE2_CTRL */
-#define IMX8MQ_CLK_PCIE2_CTRL 173
-/* PCIE2_PHY */
-#define IMX8MQ_CLK_PCIE2_PHY 174
-/* PCIE2_AUX */
-#define IMX8MQ_CLK_PCIE2_AUX 175
-/* ECSPI3 */
-#define IMX8MQ_CLK_ECSPI3 176
-
-/* CCGR clocks */
-#define IMX8MQ_CLK_A53_ROOT 177
-#define IMX8MQ_CLK_DRAM_ROOT 178
-#define IMX8MQ_CLK_ECSPI1_ROOT 179
-#define IMX8MQ_CLK_ECSPI2_ROOT 180
-#define IMX8MQ_CLK_ECSPI3_ROOT 181
-#define IMX8MQ_CLK_ENET1_ROOT 182
-#define IMX8MQ_CLK_GPT1_ROOT 183
-#define IMX8MQ_CLK_I2C1_ROOT 184
-#define IMX8MQ_CLK_I2C2_ROOT 185
-#define IMX8MQ_CLK_I2C3_ROOT 186
-#define IMX8MQ_CLK_I2C4_ROOT 187
-#define IMX8MQ_CLK_M4_ROOT 188
-#define IMX8MQ_CLK_PCIE1_ROOT 189
-#define IMX8MQ_CLK_PCIE2_ROOT 190
-#define IMX8MQ_CLK_PWM1_ROOT 191
-#define IMX8MQ_CLK_PWM2_ROOT 192
-#define IMX8MQ_CLK_PWM3_ROOT 193
-#define IMX8MQ_CLK_PWM4_ROOT 194
-#define IMX8MQ_CLK_QSPI_ROOT 195
-#define IMX8MQ_CLK_SAI1_ROOT 196
-#define IMX8MQ_CLK_SAI2_ROOT 197
-#define IMX8MQ_CLK_SAI3_ROOT 198
-#define IMX8MQ_CLK_SAI4_ROOT 199
-#define IMX8MQ_CLK_SAI5_ROOT 200
-#define IMX8MQ_CLK_SAI6_ROOT 201
-#define IMX8MQ_CLK_UART1_ROOT 202
-#define IMX8MQ_CLK_UART2_ROOT 203
-#define IMX8MQ_CLK_UART3_ROOT 204
-#define IMX8MQ_CLK_UART4_ROOT 205
-#define IMX8MQ_CLK_USB1_CTRL_ROOT 206
-#define IMX8MQ_CLK_USB2_CTRL_ROOT 207
-#define IMX8MQ_CLK_USB1_PHY_ROOT 208
-#define IMX8MQ_CLK_USB2_PHY_ROOT 209
-#define IMX8MQ_CLK_USDHC1_ROOT 210
-#define IMX8MQ_CLK_USDHC2_ROOT 211
-#define IMX8MQ_CLK_WDOG1_ROOT 212
-#define IMX8MQ_CLK_WDOG2_ROOT 213
-#define IMX8MQ_CLK_WDOG3_ROOT 214
-#define IMX8MQ_CLK_GPU_ROOT 215
-#define IMX8MQ_CLK_HEVC_ROOT 216
-#define IMX8MQ_CLK_AVC_ROOT 217
-#define IMX8MQ_CLK_VP9_ROOT 218
-#define IMX8MQ_CLK_HEVC_INTER_ROOT 219
-#define IMX8MQ_CLK_DISP_ROOT 220
-#define IMX8MQ_CLK_HDMI_ROOT 221
-#define IMX8MQ_CLK_HDMI_PHY_ROOT 222
-#define IMX8MQ_CLK_VPU_DEC_ROOT 223
-#define IMX8MQ_CLK_CSI1_ROOT 224
-#define IMX8MQ_CLK_CSI2_ROOT 225
-#define IMX8MQ_CLK_RAWNAND_ROOT 226
-#define IMX8MQ_CLK_SDMA1_ROOT 227
-#define IMX8MQ_CLK_SDMA2_ROOT 228
-#define IMX8MQ_CLK_VPU_G1_ROOT 229
-#define IMX8MQ_CLK_VPU_G2_ROOT 230
-
-/* SCCG PLL GATE */
-#define IMX8MQ_SYS1_PLL_OUT 231
-#define IMX8MQ_SYS2_PLL_OUT 232
-#define IMX8MQ_SYS3_PLL_OUT 233
-#define IMX8MQ_DRAM_PLL_OUT 234
-
-#define IMX8MQ_GPT_3M_CLK 235
-
-#define IMX8MQ_CLK_IPG_ROOT 236
-#define IMX8MQ_CLK_IPG_AUDIO_ROOT 237
-#define IMX8MQ_CLK_SAI1_IPG 238
-#define IMX8MQ_CLK_SAI2_IPG 239
-#define IMX8MQ_CLK_SAI3_IPG 240
-#define IMX8MQ_CLK_SAI4_IPG 241
-#define IMX8MQ_CLK_SAI5_IPG 242
-#define IMX8MQ_CLK_SAI6_IPG 243
-
-/* DSI AHB/IPG clocks */
-/* rxesc clock */
-#define IMX8MQ_CLK_DSI_AHB 244
-/* txesc clock */
-#define IMX8MQ_CLK_DSI_IPG_DIV 245
-
-#define IMX8MQ_CLK_TMU_ROOT 246
-
-/* Display root clocks */
-#define IMX8MQ_CLK_DISP_AXI_ROOT 247
-#define IMX8MQ_CLK_DISP_APB_ROOT 248
-#define IMX8MQ_CLK_DISP_RTRM_ROOT 249
-
-#define IMX8MQ_CLK_OCOTP_ROOT 250
-
-#define IMX8MQ_CLK_DRAM_ALT_ROOT 251
-#define IMX8MQ_CLK_DRAM_CORE 252
-
-#define IMX8MQ_CLK_MU_ROOT 253
-#define IMX8MQ_VIDEO2_PLL_OUT 254
-
-#define IMX8MQ_CLK_CLKO2 255
-
-#define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK 256
-
-#define IMX8MQ_CLK_CLKO1 257
-#define IMX8MQ_CLK_ARM 258
-
-#define IMX8MQ_CLK_GPIO1_ROOT 259
-#define IMX8MQ_CLK_GPIO2_ROOT 260
-#define IMX8MQ_CLK_GPIO3_ROOT 261
-#define IMX8MQ_CLK_GPIO4_ROOT 262
-#define IMX8MQ_CLK_GPIO5_ROOT 263
-
-#define IMX8MQ_CLK_SNVS_ROOT 264
-#define IMX8MQ_CLK_GIC 265
-
-#define IMX8MQ_VIDEO2_PLL1_REF_SEL 266
-
-#define IMX8MQ_CLK_GPU_CORE 285
-#define IMX8MQ_CLK_GPU_SHADER 286
-#define IMX8MQ_CLK_M4_CORE 287
-#define IMX8MQ_CLK_VPU_CORE 288
-
-#define IMX8MQ_CLK_A53_CORE 289
-
-#define IMX8MQ_CLK_MON_AUDIO_PLL1_DIV 290
-#define IMX8MQ_CLK_MON_AUDIO_PLL2_DIV 291
-#define IMX8MQ_CLK_MON_VIDEO_PLL1_DIV 292
-#define IMX8MQ_CLK_MON_GPU_PLL_DIV 293
-#define IMX8MQ_CLK_MON_VPU_PLL_DIV 294
-#define IMX8MQ_CLK_MON_ARM_PLL_DIV 295
-#define IMX8MQ_CLK_MON_SYS_PLL1_DIV 296
-#define IMX8MQ_CLK_MON_SYS_PLL2_DIV 297
-#define IMX8MQ_CLK_MON_SYS_PLL3_DIV 298
-#define IMX8MQ_CLK_MON_DRAM_PLL_DIV 299
-#define IMX8MQ_CLK_MON_VIDEO_PLL2_DIV 300
-#define IMX8MQ_CLK_MON_SEL 301
-#define IMX8MQ_CLK_MON_CLK2_OUT 302
-
-#define IMX8MQ_CLK_END 303
-
-#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
diff --git a/include/dt-bindings/clock/imx8ulp-clock.h b/include/dt-bindings/clock/imx8ulp-clock.h
deleted file mode 100644
index 953ecfe..0000000
--- a/include/dt-bindings/clock/imx8ulp-clock.h
+++ /dev/null
@@ -1,258 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ OR MIT */
-/*
- * Copyright 2021 NXP
- */
-
-#ifndef __DT_BINDINGS_CLOCK_IMX8ULP_H
-#define __DT_BINDINGS_CLOCK_IMX8ULP_H
-
-#define IMX8ULP_CLK_DUMMY 0
-
-/* CGC1 */
-#define IMX8ULP_CLK_SPLL2 5
-#define IMX8ULP_CLK_SPLL3 6
-#define IMX8ULP_CLK_A35_SEL 7
-#define IMX8ULP_CLK_A35_DIV 8
-#define IMX8ULP_CLK_SPLL2_PRE_SEL 9
-#define IMX8ULP_CLK_SPLL3_PRE_SEL 10
-#define IMX8ULP_CLK_SPLL3_PFD0 11
-#define IMX8ULP_CLK_SPLL3_PFD1 12
-#define IMX8ULP_CLK_SPLL3_PFD2 13
-#define IMX8ULP_CLK_SPLL3_PFD3 14
-#define IMX8ULP_CLK_SPLL3_PFD0_DIV1 15
-#define IMX8ULP_CLK_SPLL3_PFD0_DIV2 16
-#define IMX8ULP_CLK_SPLL3_PFD1_DIV1 17
-#define IMX8ULP_CLK_SPLL3_PFD1_DIV2 18
-#define IMX8ULP_CLK_SPLL3_PFD2_DIV1 19
-#define IMX8ULP_CLK_SPLL3_PFD2_DIV2 20
-#define IMX8ULP_CLK_SPLL3_PFD3_DIV1 21
-#define IMX8ULP_CLK_SPLL3_PFD3_DIV2 22
-#define IMX8ULP_CLK_NIC_SEL 23
-#define IMX8ULP_CLK_NIC_AD_DIVPLAT 24
-#define IMX8ULP_CLK_NIC_PER_DIVPLAT 25
-#define IMX8ULP_CLK_XBAR_SEL 26
-#define IMX8ULP_CLK_XBAR_AD_DIVPLAT 27
-#define IMX8ULP_CLK_XBAR_DIVBUS 28
-#define IMX8ULP_CLK_XBAR_AD_SLOW 29
-#define IMX8ULP_CLK_SOSC_DIV1 30
-#define IMX8ULP_CLK_SOSC_DIV2 31
-#define IMX8ULP_CLK_SOSC_DIV3 32
-#define IMX8ULP_CLK_FROSC_DIV1 33
-#define IMX8ULP_CLK_FROSC_DIV2 34
-#define IMX8ULP_CLK_FROSC_DIV3 35
-#define IMX8ULP_CLK_SPLL3_VCODIV 36
-#define IMX8ULP_CLK_SPLL3_PFD0_DIV1_GATE 37
-#define IMX8ULP_CLK_SPLL3_PFD0_DIV2_GATE 38
-#define IMX8ULP_CLK_SPLL3_PFD1_DIV1_GATE 39
-#define IMX8ULP_CLK_SPLL3_PFD1_DIV2_GATE 40
-#define IMX8ULP_CLK_SPLL3_PFD2_DIV1_GATE 41
-#define IMX8ULP_CLK_SPLL3_PFD2_DIV2_GATE 42
-#define IMX8ULP_CLK_SPLL3_PFD3_DIV1_GATE 43
-#define IMX8ULP_CLK_SPLL3_PFD3_DIV2_GATE 44
-#define IMX8ULP_CLK_SOSC_DIV1_GATE 45
-#define IMX8ULP_CLK_SOSC_DIV2_GATE 46
-#define IMX8ULP_CLK_SOSC_DIV3_GATE 47
-#define IMX8ULP_CLK_FROSC_DIV1_GATE 48
-#define IMX8ULP_CLK_FROSC_DIV2_GATE 49
-#define IMX8ULP_CLK_FROSC_DIV3_GATE 50
-#define IMX8ULP_CLK_SAI4_SEL 51
-#define IMX8ULP_CLK_SAI5_SEL 52
-#define IMX8ULP_CLK_AUD_CLK1 53
-#define IMX8ULP_CLK_ARM 54
-#define IMX8ULP_CLK_ENET_TS_SEL 55
-
-#define IMX8ULP_CLK_CGC1_END 56
-
-/* CGC2 */
-#define IMX8ULP_CLK_PLL4_PRE_SEL 0
-#define IMX8ULP_CLK_PLL4 1
-#define IMX8ULP_CLK_PLL4_VCODIV 2
-#define IMX8ULP_CLK_DDR_SEL 3
-#define IMX8ULP_CLK_DDR_DIV 4
-#define IMX8ULP_CLK_LPAV_AXI_SEL 5
-#define IMX8ULP_CLK_LPAV_AXI_DIV 6
-#define IMX8ULP_CLK_LPAV_AHB_DIV 7
-#define IMX8ULP_CLK_LPAV_BUS_DIV 8
-#define IMX8ULP_CLK_PLL4_PFD0 9
-#define IMX8ULP_CLK_PLL4_PFD1 10
-#define IMX8ULP_CLK_PLL4_PFD2 11
-#define IMX8ULP_CLK_PLL4_PFD3 12
-#define IMX8ULP_CLK_PLL4_PFD0_DIV1_GATE 13
-#define IMX8ULP_CLK_PLL4_PFD0_DIV2_GATE 14
-#define IMX8ULP_CLK_PLL4_PFD1_DIV1_GATE 15
-#define IMX8ULP_CLK_PLL4_PFD1_DIV2_GATE 16
-#define IMX8ULP_CLK_PLL4_PFD2_DIV1_GATE 17
-#define IMX8ULP_CLK_PLL4_PFD2_DIV2_GATE 18
-#define IMX8ULP_CLK_PLL4_PFD3_DIV1_GATE 19
-#define IMX8ULP_CLK_PLL4_PFD3_DIV2_GATE 20
-#define IMX8ULP_CLK_PLL4_PFD0_DIV1 21
-#define IMX8ULP_CLK_PLL4_PFD0_DIV2 22
-#define IMX8ULP_CLK_PLL4_PFD1_DIV1 23
-#define IMX8ULP_CLK_PLL4_PFD1_DIV2 24
-#define IMX8ULP_CLK_PLL4_PFD2_DIV1 25
-#define IMX8ULP_CLK_PLL4_PFD2_DIV2 26
-#define IMX8ULP_CLK_PLL4_PFD3_DIV1 27
-#define IMX8ULP_CLK_PLL4_PFD3_DIV2 28
-#define IMX8ULP_CLK_CGC2_SOSC_DIV1_GATE 29
-#define IMX8ULP_CLK_CGC2_SOSC_DIV2_GATE 30
-#define IMX8ULP_CLK_CGC2_SOSC_DIV3_GATE 31
-#define IMX8ULP_CLK_CGC2_SOSC_DIV1 32
-#define IMX8ULP_CLK_CGC2_SOSC_DIV2 33
-#define IMX8ULP_CLK_CGC2_SOSC_DIV3 34
-#define IMX8ULP_CLK_CGC2_FROSC_DIV1_GATE 35
-#define IMX8ULP_CLK_CGC2_FROSC_DIV2_GATE 36
-#define IMX8ULP_CLK_CGC2_FROSC_DIV3_GATE 37
-#define IMX8ULP_CLK_CGC2_FROSC_DIV1 38
-#define IMX8ULP_CLK_CGC2_FROSC_DIV2 39
-#define IMX8ULP_CLK_CGC2_FROSC_DIV3 40
-#define IMX8ULP_CLK_AUD_CLK2 41
-#define IMX8ULP_CLK_SAI6_SEL 42
-#define IMX8ULP_CLK_SAI7_SEL 43
-#define IMX8ULP_CLK_SPDIF_SEL 44
-#define IMX8ULP_CLK_HIFI_SEL 45
-#define IMX8ULP_CLK_HIFI_DIVCORE 46
-#define IMX8ULP_CLK_HIFI_DIVPLAT 47
-#define IMX8ULP_CLK_DSI_PHY_REF 48
-
-#define IMX8ULP_CLK_CGC2_END 49
-
-/* PCC3 */
-#define IMX8ULP_CLK_WDOG3 0
-#define IMX8ULP_CLK_WDOG4 1
-#define IMX8ULP_CLK_LPIT1 2
-#define IMX8ULP_CLK_TPM4 3
-#define IMX8ULP_CLK_TPM5 4
-#define IMX8ULP_CLK_FLEXIO1 5
-#define IMX8ULP_CLK_I3C2 6
-#define IMX8ULP_CLK_LPI2C4 7
-#define IMX8ULP_CLK_LPI2C5 8
-#define IMX8ULP_CLK_LPUART4 9
-#define IMX8ULP_CLK_LPUART5 10
-#define IMX8ULP_CLK_LPSPI4 11
-#define IMX8ULP_CLK_LPSPI5 12
-#define IMX8ULP_CLK_DMA1_MP 13
-#define IMX8ULP_CLK_DMA1_CH0 14
-#define IMX8ULP_CLK_DMA1_CH1 15
-#define IMX8ULP_CLK_DMA1_CH2 16
-#define IMX8ULP_CLK_DMA1_CH3 17
-#define IMX8ULP_CLK_DMA1_CH4 18
-#define IMX8ULP_CLK_DMA1_CH5 19
-#define IMX8ULP_CLK_DMA1_CH6 20
-#define IMX8ULP_CLK_DMA1_CH7 21
-#define IMX8ULP_CLK_DMA1_CH8 22
-#define IMX8ULP_CLK_DMA1_CH9 23
-#define IMX8ULP_CLK_DMA1_CH10 24
-#define IMX8ULP_CLK_DMA1_CH11 25
-#define IMX8ULP_CLK_DMA1_CH12 26
-#define IMX8ULP_CLK_DMA1_CH13 27
-#define IMX8ULP_CLK_DMA1_CH14 28
-#define IMX8ULP_CLK_DMA1_CH15 29
-#define IMX8ULP_CLK_DMA1_CH16 30
-#define IMX8ULP_CLK_DMA1_CH17 31
-#define IMX8ULP_CLK_DMA1_CH18 32
-#define IMX8ULP_CLK_DMA1_CH19 33
-#define IMX8ULP_CLK_DMA1_CH20 34
-#define IMX8ULP_CLK_DMA1_CH21 35
-#define IMX8ULP_CLK_DMA1_CH22 36
-#define IMX8ULP_CLK_DMA1_CH23 37
-#define IMX8ULP_CLK_DMA1_CH24 38
-#define IMX8ULP_CLK_DMA1_CH25 39
-#define IMX8ULP_CLK_DMA1_CH26 40
-#define IMX8ULP_CLK_DMA1_CH27 41
-#define IMX8ULP_CLK_DMA1_CH28 42
-#define IMX8ULP_CLK_DMA1_CH29 43
-#define IMX8ULP_CLK_DMA1_CH30 44
-#define IMX8ULP_CLK_DMA1_CH31 45
-#define IMX8ULP_CLK_MU3_A 46
-#define IMX8ULP_CLK_MU0_B 47
-
-#define IMX8ULP_CLK_PCC3_END 48
-
-/* PCC4 */
-#define IMX8ULP_CLK_FLEXSPI2 0
-#define IMX8ULP_CLK_TPM6 1
-#define IMX8ULP_CLK_TPM7 2
-#define IMX8ULP_CLK_LPI2C6 3
-#define IMX8ULP_CLK_LPI2C7 4
-#define IMX8ULP_CLK_LPUART6 5
-#define IMX8ULP_CLK_LPUART7 6
-#define IMX8ULP_CLK_SAI4 7
-#define IMX8ULP_CLK_SAI5 8
-#define IMX8ULP_CLK_PCTLE 9
-#define IMX8ULP_CLK_PCTLF 10
-#define IMX8ULP_CLK_USDHC0 11
-#define IMX8ULP_CLK_USDHC1 12
-#define IMX8ULP_CLK_USDHC2 13
-#define IMX8ULP_CLK_USB0 14
-#define IMX8ULP_CLK_USB0_PHY 15
-#define IMX8ULP_CLK_USB1 16
-#define IMX8ULP_CLK_USB1_PHY 17
-#define IMX8ULP_CLK_USB_XBAR 18
-#define IMX8ULP_CLK_ENET 19
-#define IMX8ULP_CLK_SFA1 20
-#define IMX8ULP_CLK_RGPIOE 21
-#define IMX8ULP_CLK_RGPIOF 22
-
-#define IMX8ULP_CLK_PCC4_END 23
-
-/* PCC5 */
-#define IMX8ULP_CLK_TPM8 0
-#define IMX8ULP_CLK_SAI6 1
-#define IMX8ULP_CLK_SAI7 2
-#define IMX8ULP_CLK_SPDIF 3
-#define IMX8ULP_CLK_ISI 4
-#define IMX8ULP_CLK_CSI_REGS 5
-#define IMX8ULP_CLK_PCTLD 6
-#define IMX8ULP_CLK_CSI 7
-#define IMX8ULP_CLK_DSI 8
-#define IMX8ULP_CLK_WDOG5 9
-#define IMX8ULP_CLK_EPDC 10
-#define IMX8ULP_CLK_PXP 11
-#define IMX8ULP_CLK_SFA2 12
-#define IMX8ULP_CLK_GPU2D 13
-#define IMX8ULP_CLK_GPU3D 14
-#define IMX8ULP_CLK_DC_NANO 15
-#define IMX8ULP_CLK_CSI_CLK_UI 16
-#define IMX8ULP_CLK_CSI_CLK_ESC 17
-#define IMX8ULP_CLK_RGPIOD 18
-#define IMX8ULP_CLK_DMA2_MP 19
-#define IMX8ULP_CLK_DMA2_CH0 20
-#define IMX8ULP_CLK_DMA2_CH1 21
-#define IMX8ULP_CLK_DMA2_CH2 22
-#define IMX8ULP_CLK_DMA2_CH3 23
-#define IMX8ULP_CLK_DMA2_CH4 24
-#define IMX8ULP_CLK_DMA2_CH5 25
-#define IMX8ULP_CLK_DMA2_CH6 26
-#define IMX8ULP_CLK_DMA2_CH7 27
-#define IMX8ULP_CLK_DMA2_CH8 28
-#define IMX8ULP_CLK_DMA2_CH9 29
-#define IMX8ULP_CLK_DMA2_CH10 30
-#define IMX8ULP_CLK_DMA2_CH11 31
-#define IMX8ULP_CLK_DMA2_CH12 32
-#define IMX8ULP_CLK_DMA2_CH13 33
-#define IMX8ULP_CLK_DMA2_CH14 34
-#define IMX8ULP_CLK_DMA2_CH15 35
-#define IMX8ULP_CLK_DMA2_CH16 36
-#define IMX8ULP_CLK_DMA2_CH17 37
-#define IMX8ULP_CLK_DMA2_CH18 38
-#define IMX8ULP_CLK_DMA2_CH19 39
-#define IMX8ULP_CLK_DMA2_CH20 40
-#define IMX8ULP_CLK_DMA2_CH21 41
-#define IMX8ULP_CLK_DMA2_CH22 42
-#define IMX8ULP_CLK_DMA2_CH23 43
-#define IMX8ULP_CLK_DMA2_CH24 44
-#define IMX8ULP_CLK_DMA2_CH25 45
-#define IMX8ULP_CLK_DMA2_CH26 46
-#define IMX8ULP_CLK_DMA2_CH27 47
-#define IMX8ULP_CLK_DMA2_CH28 48
-#define IMX8ULP_CLK_DMA2_CH29 49
-#define IMX8ULP_CLK_DMA2_CH30 50
-#define IMX8ULP_CLK_DMA2_CH31 51
-#define IMX8ULP_CLK_MU2_B 52
-#define IMX8ULP_CLK_MU3_B 53
-#define IMX8ULP_CLK_AVD_SIM 54
-#define IMX8ULP_CLK_DSI_TX_ESC 55
-
-#define IMX8ULP_CLK_PCC5_END 56
-
-#endif
diff --git a/include/dt-bindings/clock/imx93-clock.h b/include/dt-bindings/clock/imx93-clock.h
deleted file mode 100644
index 787c9e7..0000000
--- a/include/dt-bindings/clock/imx93-clock.h
+++ /dev/null
@@ -1,209 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ OR MIT */
-/*
- * Copyright 2022 NXP
- */
-
-#ifndef __DT_BINDINGS_CLOCK_IMX93_CLK_H
-#define __DT_BINDINGS_CLOCK_IMX93_CLK_H
-
-#define IMX93_CLK_DUMMY 0
-#define IMX93_CLK_24M 1
-#define IMX93_CLK_EXT1 2
-#define IMX93_CLK_SYS_PLL_PFD0 3
-#define IMX93_CLK_SYS_PLL_PFD0_DIV2 4
-#define IMX93_CLK_SYS_PLL_PFD1 5
-#define IMX93_CLK_SYS_PLL_PFD1_DIV2 6
-#define IMX93_CLK_SYS_PLL_PFD2 7
-#define IMX93_CLK_SYS_PLL_PFD2_DIV2 8
-#define IMX93_CLK_AUDIO_PLL 9
-#define IMX93_CLK_VIDEO_PLL 10
-#define IMX93_CLK_A55_PERIPH 11
-#define IMX93_CLK_A55_MTR_BUS 12
-#define IMX93_CLK_A55 13
-#define IMX93_CLK_M33 14
-#define IMX93_CLK_BUS_WAKEUP 15
-#define IMX93_CLK_BUS_AON 16
-#define IMX93_CLK_WAKEUP_AXI 17
-#define IMX93_CLK_SWO_TRACE 18
-#define IMX93_CLK_M33_SYSTICK 19
-#define IMX93_CLK_FLEXIO1 20
-#define IMX93_CLK_FLEXIO2 21
-#define IMX93_CLK_LPTMR1 24
-#define IMX93_CLK_LPTMR2 25
-#define IMX93_CLK_TPM2 27
-#define IMX93_CLK_TPM4 29
-#define IMX93_CLK_TPM5 30
-#define IMX93_CLK_TPM6 31
-#define IMX93_CLK_FLEXSPI1 32
-#define IMX93_CLK_CAN1 33
-#define IMX93_CLK_CAN2 34
-#define IMX93_CLK_LPUART1 35
-#define IMX93_CLK_LPUART2 36
-#define IMX93_CLK_LPUART3 37
-#define IMX93_CLK_LPUART4 38
-#define IMX93_CLK_LPUART5 39
-#define IMX93_CLK_LPUART6 40
-#define IMX93_CLK_LPUART7 41
-#define IMX93_CLK_LPUART8 42
-#define IMX93_CLK_LPI2C1 43
-#define IMX93_CLK_LPI2C2 44
-#define IMX93_CLK_LPI2C3 45
-#define IMX93_CLK_LPI2C4 46
-#define IMX93_CLK_LPI2C5 47
-#define IMX93_CLK_LPI2C6 48
-#define IMX93_CLK_LPI2C7 49
-#define IMX93_CLK_LPI2C8 50
-#define IMX93_CLK_LPSPI1 51
-#define IMX93_CLK_LPSPI2 52
-#define IMX93_CLK_LPSPI3 53
-#define IMX93_CLK_LPSPI4 54
-#define IMX93_CLK_LPSPI5 55
-#define IMX93_CLK_LPSPI6 56
-#define IMX93_CLK_LPSPI7 57
-#define IMX93_CLK_LPSPI8 58
-#define IMX93_CLK_I3C1 59
-#define IMX93_CLK_I3C2 60
-#define IMX93_CLK_USDHC1 61
-#define IMX93_CLK_USDHC2 62
-#define IMX93_CLK_USDHC3 63
-#define IMX93_CLK_SAI1 64
-#define IMX93_CLK_SAI2 65
-#define IMX93_CLK_SAI3 66
-#define IMX93_CLK_CCM_CKO1 67
-#define IMX93_CLK_CCM_CKO2 68
-#define IMX93_CLK_CCM_CKO3 69
-#define IMX93_CLK_CCM_CKO4 70
-#define IMX93_CLK_HSIO 71
-#define IMX93_CLK_HSIO_USB_TEST_60M 72
-#define IMX93_CLK_HSIO_ACSCAN_80M 73
-#define IMX93_CLK_HSIO_ACSCAN_480M 74
-#define IMX93_CLK_ML_APB 75
-#define IMX93_CLK_ML 76
-#define IMX93_CLK_MEDIA_AXI 77
-#define IMX93_CLK_MEDIA_APB 78
-#define IMX93_CLK_MEDIA_LDB 79
-#define IMX93_CLK_MEDIA_DISP_PIX 80
-#define IMX93_CLK_CAM_PIX 81
-#define IMX93_CLK_MIPI_TEST_BYTE 82
-#define IMX93_CLK_MIPI_PHY_CFG 83
-#define IMX93_CLK_ADC 84
-#define IMX93_CLK_PDM 85
-#define IMX93_CLK_TSTMR1 86
-#define IMX93_CLK_TSTMR2 87
-#define IMX93_CLK_MQS1 88
-#define IMX93_CLK_MQS2 89
-#define IMX93_CLK_AUDIO_XCVR 90
-#define IMX93_CLK_SPDIF 91
-#define IMX93_CLK_ENET 92
-#define IMX93_CLK_ENET_TIMER1 93
-#define IMX93_CLK_ENET_TIMER2 94
-#define IMX93_CLK_ENET_REF 95
-#define IMX93_CLK_ENET_REF_PHY 96
-#define IMX93_CLK_I3C1_SLOW 97
-#define IMX93_CLK_I3C2_SLOW 98
-#define IMX93_CLK_USB_PHY_BURUNIN 99
-#define IMX93_CLK_PAL_CAME_SCAN 100
-#define IMX93_CLK_A55_GATE 101
-#define IMX93_CLK_CM33_GATE 102
-#define IMX93_CLK_ADC1_GATE 103
-#define IMX93_CLK_WDOG1_GATE 104
-#define IMX93_CLK_WDOG2_GATE 105
-#define IMX93_CLK_WDOG3_GATE 106
-#define IMX93_CLK_WDOG4_GATE 107
-#define IMX93_CLK_WDOG5_GATE 108
-#define IMX93_CLK_SEMA1_GATE 109
-#define IMX93_CLK_SEMA2_GATE 110
-#define IMX93_CLK_MU_A_GATE 111
-#define IMX93_CLK_MU_B_GATE 112
-#define IMX93_CLK_EDMA1_GATE 113
-#define IMX93_CLK_EDMA2_GATE 114
-#define IMX93_CLK_FLEXSPI1_GATE 115
-#define IMX93_CLK_GPIO1_GATE 116
-#define IMX93_CLK_GPIO2_GATE 117
-#define IMX93_CLK_GPIO3_GATE 118
-#define IMX93_CLK_GPIO4_GATE 119
-#define IMX93_CLK_FLEXIO1_GATE 120
-#define IMX93_CLK_FLEXIO2_GATE 121
-#define IMX93_CLK_LPIT1_GATE 122
-#define IMX93_CLK_LPIT2_GATE 123
-#define IMX93_CLK_LPTMR1_GATE 124
-#define IMX93_CLK_LPTMR2_GATE 125
-#define IMX93_CLK_TPM1_GATE 126
-#define IMX93_CLK_TPM2_GATE 127
-#define IMX93_CLK_TPM3_GATE 128
-#define IMX93_CLK_TPM4_GATE 129
-#define IMX93_CLK_TPM5_GATE 130
-#define IMX93_CLK_TPM6_GATE 131
-#define IMX93_CLK_CAN1_GATE 132
-#define IMX93_CLK_CAN2_GATE 133
-#define IMX93_CLK_LPUART1_GATE 134
-#define IMX93_CLK_LPUART2_GATE 135
-#define IMX93_CLK_LPUART3_GATE 136
-#define IMX93_CLK_LPUART4_GATE 137
-#define IMX93_CLK_LPUART5_GATE 138
-#define IMX93_CLK_LPUART6_GATE 139
-#define IMX93_CLK_LPUART7_GATE 140
-#define IMX93_CLK_LPUART8_GATE 141
-#define IMX93_CLK_LPI2C1_GATE 142
-#define IMX93_CLK_LPI2C2_GATE 143
-#define IMX93_CLK_LPI2C3_GATE 144
-#define IMX93_CLK_LPI2C4_GATE 145
-#define IMX93_CLK_LPI2C5_GATE 146
-#define IMX93_CLK_LPI2C6_GATE 147
-#define IMX93_CLK_LPI2C7_GATE 148
-#define IMX93_CLK_LPI2C8_GATE 149
-#define IMX93_CLK_LPSPI1_GATE 150
-#define IMX93_CLK_LPSPI2_GATE 151
-#define IMX93_CLK_LPSPI3_GATE 152
-#define IMX93_CLK_LPSPI4_GATE 153
-#define IMX93_CLK_LPSPI5_GATE 154
-#define IMX93_CLK_LPSPI6_GATE 155
-#define IMX93_CLK_LPSPI7_GATE 156
-#define IMX93_CLK_LPSPI8_GATE 157
-#define IMX93_CLK_I3C1_GATE 158
-#define IMX93_CLK_I3C2_GATE 159
-#define IMX93_CLK_USDHC1_GATE 160
-#define IMX93_CLK_USDHC2_GATE 161
-#define IMX93_CLK_USDHC3_GATE 162
-#define IMX93_CLK_SAI1_GATE 163
-#define IMX93_CLK_SAI2_GATE 164
-#define IMX93_CLK_SAI3_GATE 165
-#define IMX93_CLK_MIPI_CSI_GATE 166
-#define IMX93_CLK_MIPI_DSI_GATE 167
-#define IMX93_CLK_LVDS_GATE 168
-#define IMX93_CLK_LCDIF_GATE 169
-#define IMX93_CLK_PXP_GATE 170
-#define IMX93_CLK_ISI_GATE 171
-#define IMX93_CLK_NIC_MEDIA_GATE 172
-#define IMX93_CLK_USB_CONTROLLER_GATE 173
-#define IMX93_CLK_USB_TEST_60M_GATE 174
-#define IMX93_CLK_HSIO_TROUT_24M_GATE 175
-#define IMX93_CLK_PDM_GATE 176
-#define IMX93_CLK_MQS1_GATE 177
-#define IMX93_CLK_MQS2_GATE 178
-#define IMX93_CLK_AUD_XCVR_GATE 179
-#define IMX93_CLK_SPDIF_GATE 180
-#define IMX93_CLK_HSIO_32K_GATE 181
-#define IMX93_CLK_ENET1_GATE 182
-#define IMX93_CLK_ENET_QOS_GATE 183
-#define IMX93_CLK_SYS_CNT_GATE 184
-#define IMX93_CLK_TSTMR1_GATE 185
-#define IMX93_CLK_TSTMR2_GATE 186
-#define IMX93_CLK_TMC_GATE 187
-#define IMX93_CLK_PMRO_GATE 188
-#define IMX93_CLK_32K 189
-#define IMX93_CLK_SAI1_IPG 190
-#define IMX93_CLK_SAI2_IPG 191
-#define IMX93_CLK_SAI3_IPG 192
-#define IMX93_CLK_MU1_A_GATE 193
-#define IMX93_CLK_MU1_B_GATE 194
-#define IMX93_CLK_MU2_A_GATE 195
-#define IMX93_CLK_MU2_B_GATE 196
-#define IMX93_CLK_NIC_AXI 197
-#define IMX93_CLK_ARM_PLL 198
-#define IMX93_CLK_A55_SEL 199
-#define IMX93_CLK_A55_CORE 200
-#define IMX93_CLK_PDM_IPG 201
-#define IMX93_CLK_END 202
-
-#endif
diff --git a/include/dt-bindings/clock/imxrt1050-clock.h b/include/dt-bindings/clock/imxrt1050-clock.h
deleted file mode 100644
index 93bef08..0000000
--- a/include/dt-bindings/clock/imxrt1050-clock.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-/*
- * Copyright(C) 2019
- * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
- */
-
-#ifndef __DT_BINDINGS_CLOCK_IMXRT1050_H
-#define __DT_BINDINGS_CLOCK_IMXRT1050_H
-
-#define IMXRT1050_CLK_DUMMY 0
-#define IMXRT1050_CLK_CKIL 1
-#define IMXRT1050_CLK_CKIH 2
-#define IMXRT1050_CLK_OSC 3
-#define IMXRT1050_CLK_PLL2_PFD0_352M 4
-#define IMXRT1050_CLK_PLL2_PFD1_594M 5
-#define IMXRT1050_CLK_PLL2_PFD2_396M 6
-#define IMXRT1050_CLK_PLL3_PFD0_720M 7
-#define IMXRT1050_CLK_PLL3_PFD1_664_62M 8
-#define IMXRT1050_CLK_PLL3_PFD2_508_24M 9
-#define IMXRT1050_CLK_PLL3_PFD3_454_74M 10
-#define IMXRT1050_CLK_PLL2_198M 11
-#define IMXRT1050_CLK_PLL3_120M 12
-#define IMXRT1050_CLK_PLL3_80M 13
-#define IMXRT1050_CLK_PLL3_60M 14
-#define IMXRT1050_CLK_PLL1_BYPASS 15
-#define IMXRT1050_CLK_PLL2_BYPASS 16
-#define IMXRT1050_CLK_PLL3_BYPASS 17
-#define IMXRT1050_CLK_PLL5_BYPASS 19
-#define IMXRT1050_CLK_PLL1_REF_SEL 20
-#define IMXRT1050_CLK_PLL2_REF_SEL 21
-#define IMXRT1050_CLK_PLL3_REF_SEL 22
-#define IMXRT1050_CLK_PLL5_REF_SEL 23
-#define IMXRT1050_CLK_PRE_PERIPH_SEL 24
-#define IMXRT1050_CLK_PERIPH_SEL 25
-#define IMXRT1050_CLK_SEMC_ALT_SEL 26
-#define IMXRT1050_CLK_SEMC_SEL 27
-#define IMXRT1050_CLK_USDHC1_SEL 28
-#define IMXRT1050_CLK_USDHC2_SEL 29
-#define IMXRT1050_CLK_LPUART_SEL 30
-#define IMXRT1050_CLK_LCDIF_SEL 31
-#define IMXRT1050_CLK_VIDEO_POST_DIV_SEL 32
-#define IMXRT1050_CLK_VIDEO_DIV 33
-#define IMXRT1050_CLK_ARM_PODF 34
-#define IMXRT1050_CLK_LPUART_PODF 35
-#define IMXRT1050_CLK_USDHC1_PODF 36
-#define IMXRT1050_CLK_USDHC2_PODF 37
-#define IMXRT1050_CLK_SEMC_PODF 38
-#define IMXRT1050_CLK_AHB_PODF 39
-#define IMXRT1050_CLK_LCDIF_PRED 40
-#define IMXRT1050_CLK_LCDIF_PODF 41
-#define IMXRT1050_CLK_USDHC1 42
-#define IMXRT1050_CLK_USDHC2 43
-#define IMXRT1050_CLK_LPUART1 44
-#define IMXRT1050_CLK_SEMC 45
-#define IMXRT1050_CLK_LCDIF_APB 46
-#define IMXRT1050_CLK_PLL1_ARM 47
-#define IMXRT1050_CLK_PLL2_SYS 48
-#define IMXRT1050_CLK_PLL3_USB_OTG 49
-#define IMXRT1050_CLK_PLL4_AUDIO 50
-#define IMXRT1050_CLK_PLL5_VIDEO 51
-#define IMXRT1050_CLK_PLL6_ENET 52
-#define IMXRT1050_CLK_PLL7_USB_HOST 53
-#define IMXRT1050_CLK_LCDIF_PIX 54
-#define IMXRT1050_CLK_USBOH3 55
-#define IMXRT1050_CLK_IPG_PDOF 56
-#define IMXRT1050_CLK_PER_CLK_SEL 57
-#define IMXRT1050_CLK_PER_PDOF 58
-#define IMXRT1050_CLK_DMA 59
-#define IMXRT1050_CLK_DMA_MUX 60
-#define IMXRT1050_CLK_END 61
-
-#endif /* __DT_BINDINGS_CLOCK_IMXRT1050_H */
diff --git a/include/dt-bindings/clock/r8a779g0-cpg-mssr.h b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h
index 754c54a..7850cdc 100644
--- a/include/dt-bindings/clock/r8a779g0-cpg-mssr.h
+++ b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h
@@ -86,5 +86,6 @@
#define R8A779G0_CLK_CPEX 74
#define R8A779G0_CLK_CBFUSA 75
#define R8A779G0_CLK_R 76
+#define R8A779G0_CLK_CP 77
#endif /* __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/rockchip,rv1126-cru.h b/include/dt-bindings/clock/rockchip,rv1126-cru.h
deleted file mode 100644
index e89a3a5..0000000
--- a/include/dt-bindings/clock/rockchip,rv1126-cru.h
+++ /dev/null
@@ -1,632 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-/*
- * Copyright (c) 2019 Rockchip Electronics Co. Ltd.
- * Author: Finley Xiao <finley.xiao@rock-chips.com>
- */
-
-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H
-#define _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H
-
-/* pmucru-clocks indices */
-
-/* pll clocks */
-#define PLL_GPLL 1
-
-/* sclk (special clocks) */
-#define CLK_OSC0_DIV32K 2
-#define CLK_RTC32K 3
-#define CLK_WIFI_DIV 4
-#define CLK_WIFI_OSC0 5
-#define CLK_WIFI 6
-#define CLK_PMU 7
-#define SCLK_UART1_DIV 8
-#define SCLK_UART1_FRACDIV 9
-#define SCLK_UART1_MUX 10
-#define SCLK_UART1 11
-#define CLK_I2C0 12
-#define CLK_I2C2 13
-#define CLK_CAPTURE_PWM0 14
-#define CLK_PWM0 15
-#define CLK_CAPTURE_PWM1 16
-#define CLK_PWM1 17
-#define CLK_SPI0 18
-#define DBCLK_GPIO0 19
-#define CLK_PMUPVTM 20
-#define CLK_CORE_PMUPVTM 21
-#define CLK_REF12M 22
-#define CLK_USBPHY_OTG_REF 23
-#define CLK_USBPHY_HOST_REF 24
-#define CLK_REF24M 25
-#define CLK_MIPIDSIPHY_REF 26
-
-/* pclk */
-#define PCLK_PDPMU 30
-#define PCLK_PMU 31
-#define PCLK_UART1 32
-#define PCLK_I2C0 33
-#define PCLK_I2C2 34
-#define PCLK_PWM0 35
-#define PCLK_PWM1 36
-#define PCLK_SPI0 37
-#define PCLK_GPIO0 38
-#define PCLK_PMUSGRF 39
-#define PCLK_PMUGRF 40
-#define PCLK_PMUCRU 41
-#define PCLK_CHIPVEROTP 42
-#define PCLK_PDPMU_NIU 43
-#define PCLK_PMUPVTM 44
-#define PCLK_SCRKEYGEN 45
-
-#define CLKPMU_NR_CLKS (PCLK_SCRKEYGEN + 1)
-
-/* cru-clocks indices */
-
-/* pll clocks */
-#define PLL_APLL 1
-#define PLL_DPLL 2
-#define PLL_CPLL 3
-#define PLL_HPLL 4
-
-/* sclk (special clocks) */
-#define ARMCLK 5
-#define USB480M 6
-#define CLK_CORE_CPUPVTM 7
-#define CLK_CPUPVTM 8
-#define CLK_SCR1 9
-#define CLK_SCR1_CORE 10
-#define CLK_SCR1_RTC 11
-#define CLK_SCR1_JTAG 12
-#define SCLK_UART0_DIV 13
-#define SCLK_UART0_FRAC 14
-#define SCLK_UART0_MUX 15
-#define SCLK_UART0 16
-#define SCLK_UART2_DIV 17
-#define SCLK_UART2_FRAC 18
-#define SCLK_UART2_MUX 19
-#define SCLK_UART2 20
-#define SCLK_UART3_DIV 21
-#define SCLK_UART3_FRAC 22
-#define SCLK_UART3_MUX 23
-#define SCLK_UART3 24
-#define SCLK_UART4_DIV 25
-#define SCLK_UART4_FRAC 26
-#define SCLK_UART4_MUX 27
-#define SCLK_UART4 28
-#define SCLK_UART5_DIV 29
-#define SCLK_UART5_FRAC 30
-#define SCLK_UART5_MUX 31
-#define SCLK_UART5 32
-#define CLK_I2C1 33
-#define CLK_I2C3 34
-#define CLK_I2C4 35
-#define CLK_I2C5 36
-#define CLK_SPI1 37
-#define CLK_CAPTURE_PWM2 38
-#define CLK_PWM2 39
-#define DBCLK_GPIO1 40
-#define DBCLK_GPIO2 41
-#define DBCLK_GPIO3 42
-#define DBCLK_GPIO4 43
-#define CLK_SARADC 44
-#define CLK_TIMER0 45
-#define CLK_TIMER1 46
-#define CLK_TIMER2 47
-#define CLK_TIMER3 48
-#define CLK_TIMER4 49
-#define CLK_TIMER5 50
-#define CLK_CAN 51
-#define CLK_NPU_TSADC 52
-#define CLK_NPU_TSADCPHY 53
-#define CLK_CPU_TSADC 54
-#define CLK_CPU_TSADCPHY 55
-#define CLK_CRYPTO_CORE 56
-#define CLK_CRYPTO_PKA 57
-#define MCLK_I2S0_TX_DIV 58
-#define MCLK_I2S0_TX_FRACDIV 59
-#define MCLK_I2S0_TX_MUX 60
-#define MCLK_I2S0_TX 61
-#define MCLK_I2S0_RX_DIV 62
-#define MCLK_I2S0_RX_FRACDIV 63
-#define MCLK_I2S0_RX_MUX 64
-#define MCLK_I2S0_RX 65
-#define MCLK_I2S0_TX_OUT2IO 66
-#define MCLK_I2S0_RX_OUT2IO 67
-#define MCLK_I2S1_DIV 68
-#define MCLK_I2S1_FRACDIV 69
-#define MCLK_I2S1_MUX 70
-#define MCLK_I2S1 71
-#define MCLK_I2S1_OUT2IO 72
-#define MCLK_I2S2_DIV 73
-#define MCLK_I2S2_FRACDIV 74
-#define MCLK_I2S2_MUX 75
-#define MCLK_I2S2 76
-#define MCLK_I2S2_OUT2IO 77
-#define MCLK_PDM 78
-#define SCLK_ADUPWM_DIV 79
-#define SCLK_AUDPWM_FRACDIV 80
-#define SCLK_AUDPWM_MUX 81
-#define SCLK_AUDPWM 82
-#define CLK_ACDCDIG_ADC 83
-#define CLK_ACDCDIG_DAC 84
-#define CLK_ACDCDIG_I2C 85
-#define CLK_VENC_CORE 86
-#define CLK_VDEC_CORE 87
-#define CLK_VDEC_CA 88
-#define CLK_VDEC_HEVC_CA 89
-#define CLK_RGA_CORE 90
-#define CLK_IEP_CORE 91
-#define CLK_ISP_DIV 92
-#define CLK_ISP_NP5 93
-#define CLK_ISP_NUX 94
-#define CLK_ISP 95
-#define CLK_CIF_OUT_DIV 96
-#define CLK_CIF_OUT_FRACDIV 97
-#define CLK_CIF_OUT_MUX 98
-#define CLK_CIF_OUT 99
-#define CLK_MIPICSI_OUT_DIV 100
-#define CLK_MIPICSI_OUT_FRACDIV 101
-#define CLK_MIPICSI_OUT_MUX 102
-#define CLK_MIPICSI_OUT 103
-#define CLK_ISPP_DIV 104
-#define CLK_ISPP_NP5 105
-#define CLK_ISPP_NUX 106
-#define CLK_ISPP 107
-#define CLK_SDMMC 108
-#define SCLK_SDMMC_DRV 109
-#define SCLK_SDMMC_SAMPLE 110
-#define CLK_SDIO 111
-#define SCLK_SDIO_DRV 112
-#define SCLK_SDIO_SAMPLE 113
-#define CLK_EMMC 114
-#define SCLK_EMMC_DRV 115
-#define SCLK_EMMC_SAMPLE 116
-#define CLK_NANDC 117
-#define SCLK_SFC 118
-#define CLK_USBHOST_UTMI_OHCI 119
-#define CLK_USBOTG_REF 120
-#define CLK_GMAC_DIV 121
-#define CLK_GMAC_RGMII_M0 122
-#define CLK_GMAC_SRC_M0 123
-#define CLK_GMAC_RGMII_M1 124
-#define CLK_GMAC_SRC_M1 125
-#define CLK_GMAC_SRC 126
-#define CLK_GMAC_REF 127
-#define CLK_GMAC_TX_SRC 128
-#define CLK_GMAC_TX_DIV5 129
-#define CLK_GMAC_TX_DIV50 130
-#define RGMII_MODE_CLK 131
-#define CLK_GMAC_RX_SRC 132
-#define CLK_GMAC_RX_DIV2 133
-#define CLK_GMAC_RX_DIV20 134
-#define RMII_MODE_CLK 135
-#define CLK_GMAC_TX_RX 136
-#define CLK_GMAC_PTPREF 137
-#define CLK_GMAC_ETHERNET_OUT 138
-#define CLK_DDRPHY 139
-#define CLK_DDR_MON 140
-#define TMCLK_DDR_MON 141
-#define CLK_NPU_DIV 142
-#define CLK_NPU_NP5 143
-#define CLK_CORE_NPU 144
-#define CLK_CORE_NPUPVTM 145
-#define CLK_NPUPVTM 146
-#define SCLK_DDRCLK 147
-#define CLK_OTP 148
-
-/* dclk */
-#define DCLK_DECOM 150
-#define DCLK_VOP_DIV 151
-#define DCLK_VOP_FRACDIV 152
-#define DCLK_VOP_MUX 153
-#define DCLK_VOP 154
-#define DCLK_CIF 155
-#define DCLK_CIFLITE 156
-
-/* aclk */
-#define ACLK_PDBUS 160
-#define ACLK_DMAC 161
-#define ACLK_DCF 162
-#define ACLK_SPINLOCK 163
-#define ACLK_DECOM 164
-#define ACLK_PDCRYPTO 165
-#define ACLK_CRYPTO 166
-#define ACLK_PDVEPU 167
-#define ACLK_VENC 168
-#define ACLK_PDVDEC 169
-#define ACLK_PDJPEG 170
-#define ACLK_VDEC 171
-#define ACLK_JPEG 172
-#define ACLK_PDVO 173
-#define ACLK_RGA 174
-#define ACLK_VOP 175
-#define ACLK_IEP 176
-#define ACLK_PDVI_DIV 177
-#define ACLK_PDVI_NP5 178
-#define ACLK_PDVI 179
-#define ACLK_ISP 180
-#define ACLK_CIF 181
-#define ACLK_CIFLITE 182
-#define ACLK_PDISPP_DIV 183
-#define ACLK_PDISPP_NP5 184
-#define ACLK_PDISPP 185
-#define ACLK_ISPP 186
-#define ACLK_PDPHP 187
-#define ACLK_PDUSB 188
-#define ACLK_USBOTG 189
-#define ACLK_PDGMAC 190
-#define ACLK_GMAC 191
-#define ACLK_PDNPU_DIV 192
-#define ACLK_PDNPU_NP5 193
-#define ACLK_PDNPU 194
-#define ACLK_NPU 195
-
-/* hclk */
-#define HCLK_PDCORE_NIU 200
-#define HCLK_PDUSB 201
-#define HCLK_PDCRYPTO 202
-#define HCLK_CRYPTO 203
-#define HCLK_PDAUDIO 204
-#define HCLK_I2S0 205
-#define HCLK_I2S1 206
-#define HCLK_I2S2 207
-#define HCLK_PDM 208
-#define HCLK_AUDPWM 209
-#define HCLK_PDVEPU 210
-#define HCLK_VENC 211
-#define HCLK_PDVDEC 212
-#define HCLK_PDJPEG 213
-#define HCLK_VDEC 214
-#define HCLK_JPEG 215
-#define HCLK_PDVO 216
-#define HCLK_RGA 217
-#define HCLK_VOP 218
-#define HCLK_IEP 219
-#define HCLK_PDVI 220
-#define HCLK_ISP 221
-#define HCLK_CIF 222
-#define HCLK_CIFLITE 223
-#define HCLK_PDISPP 224
-#define HCLK_ISPP 225
-#define HCLK_PDPHP 226
-#define HCLK_PDSDMMC 227
-#define HCLK_SDMMC 228
-#define HCLK_PDSDIO 229
-#define HCLK_SDIO 230
-#define HCLK_PDNVM 231
-#define HCLK_EMMC 232
-#define HCLK_NANDC 233
-#define HCLK_SFC 234
-#define HCLK_SFCXIP 235
-#define HCLK_PDBUS 236
-#define HCLK_USBHOST 237
-#define HCLK_USBHOST_ARB 238
-#define HCLK_PDNPU 239
-#define HCLK_NPU 240
-
-/* pclk */
-#define PCLK_CPUPVTM 245
-#define PCLK_PDBUS 246
-#define PCLK_DCF 247
-#define PCLK_WDT 248
-#define PCLK_MAILBOX 249
-#define PCLK_UART0 250
-#define PCLK_UART2 251
-#define PCLK_UART3 252
-#define PCLK_UART4 253
-#define PCLK_UART5 254
-#define PCLK_I2C1 255
-#define PCLK_I2C3 256
-#define PCLK_I2C4 257
-#define PCLK_I2C5 258
-#define PCLK_SPI1 259
-#define PCLK_PWM2 261
-#define PCLK_GPIO1 262
-#define PCLK_GPIO2 263
-#define PCLK_GPIO3 264
-#define PCLK_GPIO4 265
-#define PCLK_SARADC 266
-#define PCLK_TIMER 267
-#define PCLK_DECOM 268
-#define PCLK_CAN 269
-#define PCLK_NPU_TSADC 270
-#define PCLK_CPU_TSADC 271
-#define PCLK_ACDCDIG 272
-#define PCLK_PDVO 273
-#define PCLK_DSIHOST 274
-#define PCLK_PDVI 275
-#define PCLK_CSIHOST 276
-#define PCLK_PDGMAC 277
-#define PCLK_GMAC 278
-#define PCLK_PDDDR 279
-#define PCLK_DDR_MON 280
-#define PCLK_PDNPU 281
-#define PCLK_NPUPVTM 282
-#define PCLK_PDTOP 283
-#define PCLK_TOPCRU 284
-#define PCLK_TOPGRF 285
-#define PCLK_CPUEMADET 286
-#define PCLK_DDRPHY 287
-#define PCLK_DSIPHY 289
-#define PCLK_CSIPHY0 290
-#define PCLK_CSIPHY1 291
-#define PCLK_USBPHY_HOST 292
-#define PCLK_USBPHY_OTG 293
-#define PCLK_OTP 294
-
-#define CLK_NR_CLKS (PCLK_OTP + 1)
-
-/* pmu soft-reset indices */
-
-/* pmu_cru_softrst_con0 */
-#define SRST_PDPMU_NIU_P 0
-#define SRST_PMU_SGRF_P 1
-#define SRST_PMU_SGRF_REMAP_P 2
-#define SRST_I2C0_P 3
-#define SRST_I2C0 4
-#define SRST_I2C2_P 7
-#define SRST_I2C2 8
-#define SRST_UART1_P 9
-#define SRST_UART1 10
-#define SRST_PWM0_P 11
-#define SRST_PWM0 12
-#define SRST_PWM1_P 13
-#define SRST_PWM1 14
-#define SRST_DDR_FAIL_SAFE 15
-
-/* pmu_cru_softrst_con1 */
-#define SRST_GPIO0_P 17
-#define SRST_GPIO0_DB 18
-#define SRST_SPI0_P 19
-#define SRST_SPI0 20
-#define SRST_PMUGRF_P 21
-#define SRST_CHIPVEROTP_P 22
-#define SRST_PMUPVTM 24
-#define SRST_PMUPVTM_P 25
-#define SRST_PMUCRU_P 30
-
-/* soft-reset indices */
-
-/* cru_softrst_con0 */
-#define SRST_CORE0_PO 0
-#define SRST_CORE1_PO 1
-#define SRST_CORE2_PO 2
-#define SRST_CORE3_PO 3
-#define SRST_CORE0 4
-#define SRST_CORE1 5
-#define SRST_CORE2 6
-#define SRST_CORE3 7
-#define SRST_CORE0_DBG 8
-#define SRST_CORE1_DBG 9
-#define SRST_CORE2_DBG 10
-#define SRST_CORE3_DBG 11
-#define SRST_NL2 12
-#define SRST_CORE_NIU_A 13
-#define SRST_DBG_DAPLITE_P 14
-#define SRST_DAPLITE_P 15
-
-/* cru_softrst_con1 */
-#define SRST_PDBUS_NIU1_A 16
-#define SRST_PDBUS_NIU1_H 17
-#define SRST_PDBUS_NIU1_P 18
-#define SRST_PDBUS_NIU2_A 19
-#define SRST_PDBUS_NIU2_H 20
-#define SRST_PDBUS_NIU3_A 21
-#define SRST_PDBUS_NIU3_H 22
-#define SRST_PDBUS_HOLD_NIU1_A 23
-#define SRST_DBG_NIU_P 24
-#define SRST_PDCORE_NIIU_H 25
-#define SRST_MUC_NIU 26
-#define SRST_DCF_A 29
-#define SRST_DCF_P 30
-#define SRST_SYSTEM_SRAM_A 31
-
-/* cru_softrst_con2 */
-#define SRST_I2C1_P 32
-#define SRST_I2C1 33
-#define SRST_I2C3_P 34
-#define SRST_I2C3 35
-#define SRST_I2C4_P 36
-#define SRST_I2C4 37
-#define SRST_I2C5_P 38
-#define SRST_I2C5 39
-#define SRST_SPI1_P 40
-#define SRST_SPI1 41
-#define SRST_MCU_CORE 42
-#define SRST_PWM2_P 44
-#define SRST_PWM2 45
-#define SRST_SPINLOCK_A 46
-
-/* cru_softrst_con3 */
-#define SRST_UART0_P 48
-#define SRST_UART0 49
-#define SRST_UART2_P 50
-#define SRST_UART2 51
-#define SRST_UART3_P 52
-#define SRST_UART3 53
-#define SRST_UART4_P 54
-#define SRST_UART4 55
-#define SRST_UART5_P 56
-#define SRST_UART5 57
-#define SRST_WDT_P 58
-#define SRST_SARADC_P 59
-#define SRST_GRF_P 61
-#define SRST_TIMER_P 62
-#define SRST_MAILBOX_P 63
-
-/* cru_softrst_con4 */
-#define SRST_TIMER0 64
-#define SRST_TIMER1 65
-#define SRST_TIMER2 66
-#define SRST_TIMER3 67
-#define SRST_TIMER4 68
-#define SRST_TIMER5 69
-#define SRST_INTMUX_P 70
-#define SRST_GPIO1_P 72
-#define SRST_GPIO1_DB 73
-#define SRST_GPIO2_P 74
-#define SRST_GPIO2_DB 75
-#define SRST_GPIO3_P 76
-#define SRST_GPIO3_DB 77
-#define SRST_GPIO4_P 78
-#define SRST_GPIO4_DB 79
-
-/* cru_softrst_con5 */
-#define SRST_CAN_P 80
-#define SRST_CAN 81
-#define SRST_DECOM_A 85
-#define SRST_DECOM_P 86
-#define SRST_DECOM_D 87
-#define SRST_PDCRYPTO_NIU_A 88
-#define SRST_PDCRYPTO_NIU_H 89
-#define SRST_CRYPTO_A 90
-#define SRST_CRYPTO_H 91
-#define SRST_CRYPTO_CORE 92
-#define SRST_CRYPTO_PKA 93
-#define SRST_SGRF_P 95
-
-/* cru_softrst_con6 */
-#define SRST_PDAUDIO_NIU_H 96
-#define SRST_PDAUDIO_NIU_P 97
-#define SRST_I2S0_H 98
-#define SRST_I2S0_TX_M 99
-#define SRST_I2S0_RX_M 100
-#define SRST_I2S1_H 101
-#define SRST_I2S1_M 102
-#define SRST_I2S2_H 103
-#define SRST_I2S2_M 104
-#define SRST_PDM_H 105
-#define SRST_PDM_M 106
-#define SRST_AUDPWM_H 107
-#define SRST_AUDPWM 108
-#define SRST_ACDCDIG_P 109
-#define SRST_ACDCDIG 110
-
-/* cru_softrst_con7 */
-#define SRST_PDVEPU_NIU_A 112
-#define SRST_PDVEPU_NIU_H 113
-#define SRST_VENC_A 114
-#define SRST_VENC_H 115
-#define SRST_VENC_CORE 116
-#define SRST_PDVDEC_NIU_A 117
-#define SRST_PDVDEC_NIU_H 118
-#define SRST_VDEC_A 119
-#define SRST_VDEC_H 120
-#define SRST_VDEC_CORE 121
-#define SRST_VDEC_CA 122
-#define SRST_VDEC_HEVC_CA 123
-#define SRST_PDJPEG_NIU_A 124
-#define SRST_PDJPEG_NIU_H 125
-#define SRST_JPEG_A 126
-#define SRST_JPEG_H 127
-
-/* cru_softrst_con8 */
-#define SRST_PDVO_NIU_A 128
-#define SRST_PDVO_NIU_H 129
-#define SRST_PDVO_NIU_P 130
-#define SRST_RGA_A 131
-#define SRST_RGA_H 132
-#define SRST_RGA_CORE 133
-#define SRST_VOP_A 134
-#define SRST_VOP_H 135
-#define SRST_VOP_D 136
-#define SRST_TXBYTEHS_DSIHOST 137
-#define SRST_DSIHOST_P 138
-#define SRST_IEP_A 139
-#define SRST_IEP_H 140
-#define SRST_IEP_CORE 141
-#define SRST_ISP_RX_P 142
-
-/* cru_softrst_con9 */
-#define SRST_PDVI_NIU_A 144
-#define SRST_PDVI_NIU_H 145
-#define SRST_PDVI_NIU_P 146
-#define SRST_ISP 147
-#define SRST_CIF_A 148
-#define SRST_CIF_H 149
-#define SRST_CIF_D 150
-#define SRST_CIF_P 151
-#define SRST_CIF_I 152
-#define SRST_CIF_RX_P 153
-#define SRST_PDISPP_NIU_A 154
-#define SRST_PDISPP_NIU_H 155
-#define SRST_ISPP_A 156
-#define SRST_ISPP_H 157
-#define SRST_ISPP 158
-#define SRST_CSIHOST_P 159
-
-/* cru_softrst_con10 */
-#define SRST_PDPHPMID_NIU_A 160
-#define SRST_PDPHPMID_NIU_H 161
-#define SRST_PDNVM_NIU_H 163
-#define SRST_SDMMC_H 164
-#define SRST_SDIO_H 165
-#define SRST_EMMC_H 166
-#define SRST_SFC_H 167
-#define SRST_SFCXIP_H 168
-#define SRST_SFC 169
-#define SRST_NANDC_H 170
-#define SRST_NANDC 171
-#define SRST_PDSDMMC_H 173
-#define SRST_PDSDIO_H 174
-
-/* cru_softrst_con11 */
-#define SRST_PDUSB_NIU_A 176
-#define SRST_PDUSB_NIU_H 177
-#define SRST_USBHOST_H 178
-#define SRST_USBHOST_ARB_H 179
-#define SRST_USBHOST_UTMI 180
-#define SRST_USBOTG_A 181
-#define SRST_USBPHY_OTG_P 182
-#define SRST_USBPHY_HOST_P 183
-#define SRST_USBPHYPOR_OTG 184
-#define SRST_USBPHYPOR_HOST 185
-#define SRST_PDGMAC_NIU_A 188
-#define SRST_PDGMAC_NIU_P 189
-#define SRST_GMAC_A 190
-
-/* cru_softrst_con12 */
-#define SRST_DDR_DFICTL_P 193
-#define SRST_DDR_MON_P 194
-#define SRST_DDR_STANDBY_P 195
-#define SRST_DDR_GRF_P 196
-#define SRST_DDR_MSCH_P 197
-#define SRST_DDR_SPLIT_A 198
-#define SRST_DDR_MSCH 199
-#define SRST_DDR_DFICTL 202
-#define SRST_DDR_STANDBY 203
-#define SRST_NPUMCU_NIU 205
-#define SRST_DDRPHY_P 206
-#define SRST_DDRPHY 207
-
-/* cru_softrst_con13 */
-#define SRST_PDNPU_NIU_A 208
-#define SRST_PDNPU_NIU_H 209
-#define SRST_PDNPU_NIU_P 210
-#define SRST_NPU_A 211
-#define SRST_NPU_H 212
-#define SRST_NPU 213
-#define SRST_NPUPVTM_P 214
-#define SRST_NPUPVTM 215
-#define SRST_NPU_TSADC_P 216
-#define SRST_NPU_TSADC 217
-#define SRST_NPU_TSADCPHY 218
-#define SRST_CIFLITE_A 220
-#define SRST_CIFLITE_H 221
-#define SRST_CIFLITE_D 222
-#define SRST_CIFLITE_RX_P 223
-
-/* cru_softrst_con14 */
-#define SRST_TOPNIU_P 224
-#define SRST_TOPCRU_P 225
-#define SRST_TOPGRF_P 226
-#define SRST_CPUEMADET_P 227
-#define SRST_CSIPHY0_P 228
-#define SRST_CSIPHY1_P 229
-#define SRST_DSIPHY_P 230
-#define SRST_CPU_TSADC_P 232
-#define SRST_CPU_TSADC 233
-#define SRST_CPU_TSADCPHY 234
-#define SRST_CPUPVTM_P 235
-#define SRST_CPUPVTM 236
-
-#endif
diff --git a/include/dt-bindings/clock/rv1108-cru.h b/include/dt-bindings/clock/rv1108-cru.h
deleted file mode 100644
index 10ed9d1..0000000
--- a/include/dt-bindings/clock/rv1108-cru.h
+++ /dev/null
@@ -1,356 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2017 Rockchip Electronics Co. Ltd.
- * Author: Shawn Lin <shawn.lin@rock-chips.com>
- */
-
-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H
-#define _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H
-
-/* pll id */
-#define PLL_APLL 0
-#define PLL_DPLL 1
-#define PLL_GPLL 2
-#define ARMCLK 3
-
-/* sclk gates (special clocks) */
-#define SCLK_SPI0 65
-#define SCLK_NANDC 67
-#define SCLK_SDMMC 68
-#define SCLK_SDIO 69
-#define SCLK_EMMC 71
-#define SCLK_UART0 72
-#define SCLK_UART1 73
-#define SCLK_UART2 74
-#define SCLK_I2S0 75
-#define SCLK_I2S1 76
-#define SCLK_I2S2 77
-#define SCLK_TIMER0 78
-#define SCLK_TIMER1 79
-#define SCLK_SFC 80
-#define SCLK_SDMMC_DRV 81
-#define SCLK_SDIO_DRV 82
-#define SCLK_EMMC_DRV 83
-#define SCLK_SDMMC_SAMPLE 84
-#define SCLK_SDIO_SAMPLE 85
-#define SCLK_EMMC_SAMPLE 86
-#define SCLK_VENC_CORE 87
-#define SCLK_HEVC_CORE 88
-#define SCLK_HEVC_CABAC 89
-#define SCLK_PWM0_PMU 90
-#define SCLK_I2C0_PMU 91
-#define SCLK_WIFI 92
-#define SCLK_CIFOUT 93
-#define SCLK_MIPI_CSI_OUT 94
-#define SCLK_CIF0 95
-#define SCLK_CIF1 96
-#define SCLK_CIF2 97
-#define SCLK_CIF3 98
-#define SCLK_DSP 99
-#define SCLK_DSP_IOP 100
-#define SCLK_DSP_EPP 101
-#define SCLK_DSP_EDP 102
-#define SCLK_DSP_EDAP 103
-#define SCLK_CVBS_HOST 104
-#define SCLK_HDMI_SFR 105
-#define SCLK_HDMI_CEC 106
-#define SCLK_CRYPTO 107
-#define SCLK_SPI 108
-#define SCLK_SARADC 109
-#define SCLK_TSADC 110
-#define SCLK_MAC_PRE 111
-#define SCLK_MAC 112
-#define SCLK_MAC_RX 113
-#define SCLK_MAC_REF 114
-#define SCLK_MAC_REFOUT 115
-#define SCLK_DSP_PFM 116
-#define SCLK_RGA 117
-#define SCLK_I2C1 118
-#define SCLK_I2C2 119
-#define SCLK_I2C3 120
-#define SCLK_PWM 121
-#define SCLK_ISP 122
-#define SCLK_USBPHY 123
-#define SCLK_I2S0_SRC 124
-#define SCLK_I2S1_SRC 125
-#define SCLK_I2S2_SRC 126
-#define SCLK_UART0_SRC 127
-#define SCLK_UART1_SRC 128
-#define SCLK_UART2_SRC 129
-#define SCLK_MAC_TX 130
-#define SCLK_MACREF 131
-#define SCLK_MACREF_OUT 132
-
-#define DCLK_VOP_SRC 185
-#define DCLK_HDMIPHY 186
-#define DCLK_VOP 187
-
-/* aclk gates */
-#define ACLK_DMAC 192
-#define ACLK_PRE 193
-#define ACLK_CORE 194
-#define ACLK_ENMCORE 195
-#define ACLK_RKVENC 196
-#define ACLK_RKVDEC 197
-#define ACLK_VPU 198
-#define ACLK_CIF0 199
-#define ACLK_VIO0 200
-#define ACLK_VIO1 201
-#define ACLK_VOP 202
-#define ACLK_IEP 203
-#define ACLK_RGA 204
-#define ACLK_ISP 205
-#define ACLK_CIF1 206
-#define ACLK_CIF2 207
-#define ACLK_CIF3 208
-#define ACLK_PERI 209
-#define ACLK_GMAC 210
-
-/* pclk gates */
-#define PCLK_GPIO1 256
-#define PCLK_GPIO2 257
-#define PCLK_GPIO3 258
-#define PCLK_GRF 259
-#define PCLK_I2C1 260
-#define PCLK_I2C2 261
-#define PCLK_I2C3 262
-#define PCLK_SPI 263
-#define PCLK_SFC 264
-#define PCLK_UART0 265
-#define PCLK_UART1 266
-#define PCLK_UART2 267
-#define PCLK_TSADC 268
-#define PCLK_PWM 269
-#define PCLK_TIMER 270
-#define PCLK_PERI 271
-#define PCLK_GPIO0_PMU 272
-#define PCLK_I2C0_PMU 273
-#define PCLK_PWM0_PMU 274
-#define PCLK_ISP 275
-#define PCLK_VIO 276
-#define PCLK_MIPI_DSI 277
-#define PCLK_HDMI_CTRL 278
-#define PCLK_SARADC 279
-#define PCLK_DSP_CFG 280
-#define PCLK_BUS 281
-#define PCLK_EFUSE0 282
-#define PCLK_EFUSE1 283
-#define PCLK_WDT 284
-#define PCLK_GMAC 285
-
-/* hclk gates */
-#define HCLK_I2S0_8CH 320
-#define HCLK_I2S1_2CH 321
-#define HCLK_I2S2_2CH 322
-#define HCLK_NANDC 323
-#define HCLK_SDMMC 324
-#define HCLK_SDIO 325
-#define HCLK_EMMC 326
-#define HCLK_PERI 327
-#define HCLK_SFC 328
-#define HCLK_RKVENC 329
-#define HCLK_RKVDEC 330
-#define HCLK_CIF0 331
-#define HCLK_VIO 332
-#define HCLK_VOP 333
-#define HCLK_IEP 334
-#define HCLK_RGA 335
-#define HCLK_ISP 336
-#define HCLK_CRYPTO_MST 337
-#define HCLK_CRYPTO_SLV 338
-#define HCLK_HOST0 339
-#define HCLK_OTG 340
-#define HCLK_CIF1 341
-#define HCLK_CIF2 342
-#define HCLK_CIF3 343
-#define HCLK_BUS 344
-#define HCLK_VPU 345
-
-#define CLK_NR_CLKS (HCLK_VPU + 1)
-
-/* reset id */
-#define SRST_CORE_PO_AD 0
-#define SRST_CORE_AD 1
-#define SRST_L2_AD 2
-#define SRST_CPU_NIU_AD 3
-#define SRST_CORE_PO 4
-#define SRST_CORE 5
-#define SRST_L2 6
-#define SRST_CORE_DBG 8
-#define PRST_DBG 9
-#define RST_DAP 10
-#define PRST_DBG_NIU 11
-#define ARST_STRC_SYS_AD 15
-
-#define SRST_DDRPHY_CLKDIV 16
-#define SRST_DDRPHY 17
-#define PRST_DDRPHY 18
-#define PRST_HDMIPHY 19
-#define PRST_VDACPHY 20
-#define PRST_VADCPHY 21
-#define PRST_MIPI_CSI_PHY 22
-#define PRST_MIPI_DSI_PHY 23
-#define PRST_ACODEC 24
-#define ARST_BUS_NIU 25
-#define PRST_TOP_NIU 26
-#define ARST_INTMEM 27
-#define HRST_ROM 28
-#define ARST_DMAC 29
-#define SRST_MSCH_NIU 30
-#define PRST_MSCH_NIU 31
-
-#define PRST_DDRUPCTL 32
-#define NRST_DDRUPCTL 33
-#define PRST_DDRMON 34
-#define HRST_I2S0_8CH 35
-#define MRST_I2S0_8CH 36
-#define HRST_I2S1_2CH 37
-#define MRST_IS21_2CH 38
-#define HRST_I2S2_2CH 39
-#define MRST_I2S2_2CH 40
-#define HRST_CRYPTO 41
-#define SRST_CRYPTO 42
-#define PRST_SPI 43
-#define SRST_SPI 44
-#define PRST_UART0 45
-#define PRST_UART1 46
-#define PRST_UART2 47
-
-#define SRST_UART0 48
-#define SRST_UART1 49
-#define SRST_UART2 50
-#define PRST_I2C1 51
-#define PRST_I2C2 52
-#define PRST_I2C3 53
-#define SRST_I2C1 54
-#define SRST_I2C2 55
-#define SRST_I2C3 56
-#define PRST_PWM1 58
-#define SRST_PWM1 60
-#define PRST_WDT 61
-#define PRST_GPIO1 62
-#define PRST_GPIO2 63
-
-#define PRST_GPIO3 64
-#define PRST_GRF 65
-#define PRST_EFUSE 66
-#define PRST_EFUSE512 67
-#define PRST_TIMER0 68
-#define SRST_TIMER0 69
-#define SRST_TIMER1 70
-#define PRST_TSADC 71
-#define SRST_TSADC 72
-#define PRST_SARADC 73
-#define SRST_SARADC 74
-#define HRST_SYSBUS 75
-#define PRST_USBGRF 76
-
-#define ARST_PERIPH_NIU 80
-#define HRST_PERIPH_NIU 81
-#define PRST_PERIPH_NIU 82
-#define HRST_PERIPH 83
-#define HRST_SDMMC 84
-#define HRST_SDIO 85
-#define HRST_EMMC 86
-#define HRST_NANDC 87
-#define NRST_NANDC 88
-#define HRST_SFC 89
-#define SRST_SFC 90
-#define ARST_GMAC 91
-#define HRST_OTG 92
-#define SRST_OTG 93
-#define SRST_OTG_ADP 94
-#define HRST_HOST0 95
-
-#define HRST_HOST0_AUX 96
-#define HRST_HOST0_ARB 97
-#define SRST_HOST0_EHCIPHY 98
-#define SRST_HOST0_UTMI 99
-#define SRST_USBPOR 100
-#define SRST_UTMI0 101
-#define SRST_UTMI1 102
-
-#define ARST_VIO0_NIU 102
-#define ARST_VIO1_NIU 103
-#define HRST_VIO_NIU 104
-#define PRST_VIO_NIU 105
-#define ARST_VOP 106
-#define HRST_VOP 107
-#define DRST_VOP 108
-#define ARST_IEP 109
-#define HRST_IEP 110
-#define ARST_RGA 111
-#define HRST_RGA 112
-#define SRST_RGA 113
-#define PRST_CVBS 114
-#define PRST_HDMI 115
-#define SRST_HDMI 116
-#define PRST_MIPI_DSI 117
-
-#define ARST_ISP_NIU 118
-#define HRST_ISP_NIU 119
-#define HRST_ISP 120
-#define SRST_ISP 121
-#define ARST_VIP0 122
-#define HRST_VIP0 123
-#define PRST_VIP0 124
-#define ARST_VIP1 125
-#define HRST_VIP1 126
-#define PRST_VIP1 127
-#define ARST_VIP2 128
-#define HRST_VIP2 129
-#define PRST_VIP2 120
-#define ARST_VIP3 121
-#define HRST_VIP3 122
-#define PRST_VIP4 123
-
-#define PRST_CIF1TO4 124
-#define SRST_CVBS_CLK 125
-#define HRST_CVBS 126
-
-#define ARST_VPU_NIU 140
-#define HRST_VPU_NIU 141
-#define ARST_VPU 142
-#define HRST_VPU 143
-#define ARST_RKVDEC_NIU 144
-#define HRST_RKVDEC_NIU 145
-#define ARST_RKVDEC 146
-#define HRST_RKVDEC 147
-#define SRST_RKVDEC_CABAC 148
-#define SRST_RKVDEC_CORE 149
-#define ARST_RKVENC_NIU 150
-#define HRST_RKVENC_NIU 151
-#define ARST_RKVENC 152
-#define HRST_RKVENC 153
-#define SRST_RKVENC_CORE 154
-
-#define SRST_DSP_CORE 156
-#define SRST_DSP_SYS 157
-#define SRST_DSP_GLOBAL 158
-#define SRST_DSP_OECM 159
-#define PRST_DSP_IOP_NIU 160
-#define ARST_DSP_EPP_NIU 161
-#define ARST_DSP_EDP_NIU 162
-#define PRST_DSP_DBG_NIU 163
-#define PRST_DSP_CFG_NIU 164
-#define PRST_DSP_GRF 165
-#define PRST_DSP_MAILBOX 166
-#define PRST_DSP_INTC 167
-#define PRST_DSP_PFM_MON 169
-#define SRST_DSP_PFM_MON 170
-#define ARST_DSP_EDAP_NIU 171
-
-#define SRST_PMU 172
-#define SRST_PMU_I2C0 173
-#define PRST_PMU_I2C0 174
-#define PRST_PMU_GPIO0 175
-#define PRST_PMU_INTMEM 176
-#define PRST_PMU_PWM0 177
-#define SRST_PMU_PWM0 178
-#define PRST_PMU_GRF 179
-#define SRST_PMU_NIU 180
-#define SRST_PMU_PVTM 181
-#define ARST_DSP_EDP_PERF 184
-#define ARST_DSP_EPP_PERF 185
-
-#endif /* _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H */
diff --git a/include/dt-bindings/interconnect/fsl,imx8mp.h b/include/dt-bindings/interconnect/fsl,imx8mp.h
deleted file mode 100644
index 7357d41..0000000
--- a/include/dt-bindings/interconnect/fsl,imx8mp.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-/*
- * Interconnect framework driver for i.MX SoC
- *
- * Copyright 2022 NXP
- * Peng Fan <peng.fan@nxp.com>
- */
-
-#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MP_H
-#define __DT_BINDINGS_INTERCONNECT_IMX8MP_H
-
-#define IMX8MP_ICN_NOC 0
-#define IMX8MP_ICN_MAIN 1
-#define IMX8MP_ICS_DRAM 2
-#define IMX8MP_ICS_OCRAM 3
-#define IMX8MP_ICM_A53 4
-#define IMX8MP_ICM_SUPERMIX 5
-#define IMX8MP_ICM_GIC 6
-#define IMX8MP_ICM_MLMIX 7
-
-#define IMX8MP_ICN_AUDIO 8
-#define IMX8MP_ICM_DSP 9
-#define IMX8MP_ICM_SDMA2PER 10
-#define IMX8MP_ICM_SDMA2BURST 11
-#define IMX8MP_ICM_SDMA3PER 12
-#define IMX8MP_ICM_SDMA3BURST 13
-#define IMX8MP_ICM_EDMA 14
-
-#define IMX8MP_ICN_GPU 15
-#define IMX8MP_ICM_GPU2D 16
-#define IMX8MP_ICM_GPU3D 17
-
-#define IMX8MP_ICN_HDMI 18
-#define IMX8MP_ICM_HRV 19
-#define IMX8MP_ICM_LCDIF_HDMI 20
-#define IMX8MP_ICM_HDCP 21
-
-#define IMX8MP_ICN_HSIO 22
-#define IMX8MP_ICM_NOC_PCIE 23
-#define IMX8MP_ICM_USB1 24
-#define IMX8MP_ICM_USB2 25
-#define IMX8MP_ICM_PCIE 26
-
-#define IMX8MP_ICN_MEDIA 27
-#define IMX8MP_ICM_LCDIF_RD 28
-#define IMX8MP_ICM_LCDIF_WR 29
-#define IMX8MP_ICM_ISI0 30
-#define IMX8MP_ICM_ISI1 31
-#define IMX8MP_ICM_ISI2 32
-#define IMX8MP_ICM_ISP0 33
-#define IMX8MP_ICM_ISP1 34
-#define IMX8MP_ICM_DWE 35
-
-#define IMX8MP_ICN_VIDEO 36
-#define IMX8MP_ICM_VPU_G1 37
-#define IMX8MP_ICM_VPU_G2 38
-#define IMX8MP_ICM_VPU_H1 39
-
-#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MP_H */
diff --git a/include/dt-bindings/interconnect/imx8mm.h b/include/dt-bindings/interconnect/imx8mm.h
deleted file mode 100644
index 8f10bb0..0000000
--- a/include/dt-bindings/interconnect/imx8mm.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Interconnect framework driver for i.MX SoC
- *
- * Copyright (c) 2019, BayLibre
- * Copyright (c) 2019-2020, NXP
- * Author: Alexandre Bailon <abailon@baylibre.com>
- */
-
-#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MM_H
-#define __DT_BINDINGS_INTERCONNECT_IMX8MM_H
-
-#define IMX8MM_ICN_NOC 1
-#define IMX8MM_ICS_DRAM 2
-#define IMX8MM_ICS_OCRAM 3
-#define IMX8MM_ICM_A53 4
-
-#define IMX8MM_ICM_VPU_H1 5
-#define IMX8MM_ICM_VPU_G1 6
-#define IMX8MM_ICM_VPU_G2 7
-#define IMX8MM_ICN_VIDEO 8
-
-#define IMX8MM_ICM_GPU2D 9
-#define IMX8MM_ICM_GPU3D 10
-#define IMX8MM_ICN_GPU 11
-
-#define IMX8MM_ICM_CSI 12
-#define IMX8MM_ICM_LCDIF 13
-#define IMX8MM_ICN_MIPI 14
-
-#define IMX8MM_ICM_USB1 15
-#define IMX8MM_ICM_USB2 16
-#define IMX8MM_ICM_PCIE 17
-#define IMX8MM_ICN_HSIO 18
-
-#define IMX8MM_ICM_SDMA2 19
-#define IMX8MM_ICM_SDMA3 20
-#define IMX8MM_ICN_AUDIO 21
-
-#define IMX8MM_ICN_ENET 22
-#define IMX8MM_ICM_ENET 23
-
-#define IMX8MM_ICN_MAIN 24
-#define IMX8MM_ICM_NAND 25
-#define IMX8MM_ICM_SDMA1 26
-#define IMX8MM_ICM_USDHC1 27
-#define IMX8MM_ICM_USDHC2 28
-#define IMX8MM_ICM_USDHC3 29
-
-#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MM_H */
diff --git a/include/dt-bindings/interconnect/imx8mn.h b/include/dt-bindings/interconnect/imx8mn.h
deleted file mode 100644
index 307b977..0000000
--- a/include/dt-bindings/interconnect/imx8mn.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Interconnect framework driver for i.MX SoC
- *
- * Copyright (c) 2019-2020, NXP
- */
-
-#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MN_H
-#define __DT_BINDINGS_INTERCONNECT_IMX8MN_H
-
-#define IMX8MN_ICN_NOC 1
-#define IMX8MN_ICS_DRAM 2
-#define IMX8MN_ICS_OCRAM 3
-#define IMX8MN_ICM_A53 4
-
-#define IMX8MN_ICM_GPU 5
-#define IMX8MN_ICN_GPU 6
-
-#define IMX8MN_ICM_CSI1 7
-#define IMX8MN_ICM_CSI2 8
-#define IMX8MN_ICM_ISI 9
-#define IMX8MN_ICM_LCDIF 10
-#define IMX8MN_ICN_MIPI 11
-
-#define IMX8MN_ICM_USB 12
-
-#define IMX8MN_ICM_SDMA2 13
-#define IMX8MN_ICM_SDMA3 14
-#define IMX8MN_ICN_AUDIO 15
-
-#define IMX8MN_ICN_ENET 16
-#define IMX8MN_ICM_ENET 17
-
-#define IMX8MN_ICM_NAND 18
-#define IMX8MN_ICM_SDMA1 19
-#define IMX8MN_ICM_USDHC1 20
-#define IMX8MN_ICM_USDHC2 21
-#define IMX8MN_ICM_USDHC3 22
-#define IMX8MN_ICN_MAIN 23
-
-#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MN_H */
diff --git a/include/dt-bindings/interconnect/imx8mq.h b/include/dt-bindings/interconnect/imx8mq.h
deleted file mode 100644
index 1a4cae7..0000000
--- a/include/dt-bindings/interconnect/imx8mq.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Interconnect framework driver for i.MX SoC
- *
- * Copyright (c) 2019-2020, NXP
- */
-
-#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MQ_H
-#define __DT_BINDINGS_INTERCONNECT_IMX8MQ_H
-
-#define IMX8MQ_ICN_NOC 1
-#define IMX8MQ_ICS_DRAM 2
-#define IMX8MQ_ICS_OCRAM 3
-#define IMX8MQ_ICM_A53 4
-
-#define IMX8MQ_ICM_VPU 5
-#define IMX8MQ_ICN_VIDEO 6
-
-#define IMX8MQ_ICM_GPU 7
-#define IMX8MQ_ICN_GPU 8
-
-#define IMX8MQ_ICM_DCSS 9
-#define IMX8MQ_ICN_DCSS 10
-
-#define IMX8MQ_ICM_USB1 11
-#define IMX8MQ_ICM_USB2 12
-#define IMX8MQ_ICN_USB 13
-
-#define IMX8MQ_ICM_CSI1 14
-#define IMX8MQ_ICM_CSI2 15
-#define IMX8MQ_ICM_LCDIF 16
-#define IMX8MQ_ICN_DISPLAY 17
-
-#define IMX8MQ_ICM_SDMA2 18
-#define IMX8MQ_ICN_AUDIO 19
-
-#define IMX8MQ_ICN_ENET 20
-#define IMX8MQ_ICM_ENET 21
-
-#define IMX8MQ_ICM_SDMA1 22
-#define IMX8MQ_ICM_NAND 23
-#define IMX8MQ_ICM_USDHC1 24
-#define IMX8MQ_ICM_USDHC2 25
-#define IMX8MQ_ICM_PCIE1 26
-#define IMX8MQ_ICM_PCIE2 27
-#define IMX8MQ_ICN_MAIN 28
-
-#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MQ_H */
diff --git a/include/dt-bindings/phy/phy-imx8-pcie.h b/include/dt-bindings/phy/phy-imx8-pcie.h
deleted file mode 100644
index 8bbe2d6..0000000
--- a/include/dt-bindings/phy/phy-imx8-pcie.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-/*
- * This header provides constants for i.MX8 PCIe.
- */
-
-#ifndef _DT_BINDINGS_IMX8_PCIE_H
-#define _DT_BINDINGS_IMX8_PCIE_H
-
-/* Reference clock PAD mode */
-#define IMX8_PCIE_REFCLK_PAD_UNUSED 0
-#define IMX8_PCIE_REFCLK_PAD_INPUT 1
-#define IMX8_PCIE_REFCLK_PAD_OUTPUT 2
-
-#endif /* _DT_BINDINGS_IMX8_PCIE_H */
diff --git a/include/dt-bindings/pinctrl/pins-imx8mq.h b/include/dt-bindings/pinctrl/pins-imx8mq.h
deleted file mode 100644
index 0e1d67d..0000000
--- a/include/dt-bindings/pinctrl/pins-imx8mq.h
+++ /dev/null
@@ -1,632 +0,0 @@
-/*
- * Copyright (C) 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __DTS_IMX8MQ_PINFUNC_H
-#define __DTS_IMX8MQ_PINFUNC_H
-
-/*
- * The pin function ID is a tuple of
- * <mux_reg conf_reg input_reg mux_mode input_val>
- */
-
-#define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x030 0x298 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x030 0x298 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x030 0x298 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO02_SJC_DE_B 0x030 0x298 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x034 0x29C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x034 0x29C 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x034 0x29C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x034 0x29C 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO03_SJC_DONE 0x034 0x29C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x038 0x2A0 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x038 0x2A0 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x038 0x2A0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x038 0x2A0 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG 0x038 0x2A0 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x03C 0x2A4 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO05_M4_NMI 0x03C 0x2A4 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x03C 0x2A4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x03C 0x2A4 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG 0x03C 0x2A4 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x040 0x2A8 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO06_ENET1_MDC 0x040 0x2A8 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x040 0x2A8 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x040 0x2A8 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG 0x040 0x2A8 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x044 0x2AC 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x044 0x2AC 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO07_USDHC1_WP 0x044 0x2AC 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x044 0x2AC 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG 0x044 0x2AC 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x048 0x2B0 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x048 0x2B0 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x048 0x2B0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x048 0x2B0 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG 0x048 0x2B0 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x04C 0x2B4 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x04C 0x2B4 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x04C 0x2B4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x04C 0x2B4 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG 0x04C 0x2B4 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x050 0x2B8 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x050 0x2B8 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x050 0x2B8 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x054 0x2BC 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x054 0x2BC 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x054 0x2BC 0x4BC 0x5 0x1
-#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x054 0x2BC 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS 0x054 0x2BC 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x058 0x2C0 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x058 0x2C0 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x058 0x2C0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x058 0x2C0 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0 0x058 0x2C0 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x05C 0x2C4 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x05C 0x2C4 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x05C 0x2C4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x05C 0x2C4 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1 0x05C 0x2C4 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x060 0x2C8 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x060 0x2C8 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO14_PWM3_OUT 0x060 0x2C8 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x060 0x2C8 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2 0x060 0x2C8 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x064 0x2CC 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x064 0x2CC 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO15_PWM4_OUT 0x064 0x2CC 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x064 0x2CC 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB 0x064 0x2CC 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x068 0x2D0 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16 0x068 0x2D0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x06C 0x2D4 0x4C0 0x0 0x1
-#define MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17 0x06C 0x2D4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x070 0x2D8 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ENET_TD3_GPIO1_IO18 0x070 0x2D8 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x074 0x2DC 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x074 0x2DC 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_ENET_TD2_GPIO1_IO19 0x074 0x2DC 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x078 0x2E0 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ENET_TD1_GPIO1_IO20 0x078 0x2E0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x07C 0x2E4 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ENET_TD0_GPIO1_IO21 0x07C 0x2E4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x080 0x2E8 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x080 0x2E8 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x084 0x2EC 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ENET_TXC_ENET1_TX_ER 0x084 0x2EC 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_ENET_TXC_GPIO1_IO23 0x084 0x2EC 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x088 0x2F0 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x088 0x2F0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x08C 0x2F4 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x08C 0x2F4 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_ENET_RXC_GPIO1_IO25 0x08C 0x2F4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 0x2F8 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ENET_RD0_GPIO1_IO26 0x090 0x2F8 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x094 0x2FC 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ENET_RD1_GPIO1_IO27 0x094 0x2FC 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x098 0x300 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ENET_RD2_GPIO1_IO28 0x098 0x300 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x09C 0x304 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29 0x09C 0x304 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x0A0 0x308 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD1_CLK_GPIO2_IO0 0x0A0 0x308 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD1_DATA2_GPIO2_IO4 0x0B0 0x318 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0B4 0x31C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD1_DATA3_GPIO2_IO5 0x0B4 0x31C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0B8 0x320 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0B8 0x320 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0BC 0x324 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0BC 0x324 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0C0 0x328 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD1_DATA6_GPIO2_IO8 0x0C0 0x328 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0C4 0x32C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD1_DATA7_GPIO2_IO9 0x0C4 0x32C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x0C8 0x330 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0C8 0x330 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x0CC 0x334 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x0CC 0x334 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0D0 0x338 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0D0 0x338 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x0D4 0x33C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD2_CLK_GPIO2_IO13 0x0D4 0x33C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x0D4 0x33C 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0 0x0D4 0x33C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0x0D8 0x340 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD2_CMD_GPIO2_IO14 0x0D8 0x340 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x0D8 0x340 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1 0x0D8 0x340 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0DC 0x344 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD2_DATA0_GPIO2_IO15 0x0DC 0x344 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x0DC 0x344 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2 0x0DC 0x344 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0E0 0x348 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD2_DATA1_GPIO2_IO16 0x0E0 0x348 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x0E0 0x348 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3 0x0E0 0x348 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0E4 0x34C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD2_DATA2_GPIO2_IO17 0x0E4 0x34C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x0E4 0x34C 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4 0x0E4 0x34C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0E8 0x350 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD2_DATA3_GPIO2_IO18 0x0E8 0x350 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x0E8 0x350 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x0EC 0x354 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0EC 0x354 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x0EC 0x354 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SD2_WP_USDHC2_WP 0x0F0 0x358 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x0F0 0x358 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD2_WP_SIM_M_HMASTLOCK 0x0F0 0x358 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_ALE_RAWNAND_ALE 0x0F4 0x35C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x0F4 0x35C 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x0F4 0x35C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_ALE_SIM_M_HPROT0 0x0F4 0x35C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x0F8 0x360 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x0F8 0x360 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x0F8 0x360 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_CE0_B_SIM_M_HPROT1 0x0F8 0x360 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x0FC 0x364 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x0FC 0x364 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x0FC 0x364 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_CE1_B_SIM_M_HPROT2 0x0FC 0x364 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_CE2_B_SIM_M_HPROT3 0x100 0x368 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x104 0x36C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x104 0x36C 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x104 0x36C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_CE3_B_SIM_M_HADDR0 0x104 0x36C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_CLE_RAWNAND_CLE 0x108 0x370 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x108 0x370 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x108 0x370 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_CLE_SIM_M_HADDR1 0x108 0x370 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x10C 0x374 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x10C 0x374 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x10C 0x374 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_DATA00_SIM_M_HADDR2 0x10C 0x374 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x110 0x378 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x110 0x378 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x110 0x378 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_DATA01_SIM_M_HADDR3 0x110 0x378 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x114 0x37C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x114 0x37C 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x114 0x37C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_DATA02_SIM_M_HADDR4 0x114 0x37C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x118 0x380 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x118 0x380 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x118 0x380 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_DATA03_SIM_M_HADDR5 0x118 0x380 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x11C 0x384 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x11C 0x384 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_DATA04_SIM_M_HADDR6 0x11C 0x384 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x120 0x388 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x120 0x388 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_DATA05_SIM_M_HADDR7 0x120 0x388 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x124 0x38C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x124 0x38C 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_DATA06_SIM_M_HADDR8 0x124 0x38C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_DATA07_SIM_M_HADDR9 0x128 0x390 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_DQS_RAWNAND_DQS 0x12C 0x394 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_DQS_QSPI_A_DQS 0x12C 0x394 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x12C 0x394 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_DQS_SIM_M_HADDR10 0x12C 0x394 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x130 0x398 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x130 0x398 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_RE_B_SIM_M_HADDR11 0x130 0x398 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_READY_B_SIM_M_HADDR12 0x134 0x39C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x138 0x3A0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_WE_B_SIM_M_HADDR13 0x138 0x3A0 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x13C 0x3A4 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x13C 0x3A4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_WP_B_SIM_M_HADDR14 0x13C 0x3A4 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x140 0x3A8 0x4E4 0x0 0x0
-#define MX8MQ_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x140 0x3A8 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x140 0x3A8 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x144 0x3AC 0x4D0 0x0 0x0
-#define MX8MQ_IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x144 0x3AC 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x144 0x3AC 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x148 0x3B0 0x4D4 0x0 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x148 0x3B0 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x148 0x3B0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x14C 0x3B4 0x4D8 0x0 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x14C 0x3B4 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x14C 0x3B4 0x4CC 0x2 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x14C 0x3B4 0x4EC 0x3 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x14C 0x3B4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x150 0x3B8 0x4DC 0x0 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x150 0x3B8 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x150 0x3B8 0x4CC 0x2 0x1
-#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x154 0x3BC 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x154 0x3BC 0x4CC 0x2 0x2
-#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x154 0x3BC 0x000 0x3 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x154 0x3BC 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x158 0x3C0 0x52C 0x0 0x0
-#define MX8MQ_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x158 0x3C0 0x4C8 0x1 0x0
-#define MX8MQ_IOMUXC_SAI5_MCLK_SAI4_MCLK 0x158 0x3C0 0x000 0x2 0x0
-#define MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x158 0x3C0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK 0x158 0x3C0 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x15C 0x3C4 0x4C4 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x15C 0x3C4 0x4E4 0x1 0x1
-#define MX8MQ_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x15C 0x3C4 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x15C 0x3C4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_RXFS_SIM_M_HADDR15 0x15C 0x3C4 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x160 0x3C8 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x160 0x3C8 0x4D0 0x1 0x1
-#define MX8MQ_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x160 0x3C8 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x160 0x3C8 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_RXC_SIM_M_HADDR16 0x160 0x3C8 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x164 0x3CC 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x164 0x3CC 0x4D4 0x1 0x1
-#define MX8MQ_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x164 0x3CC 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x164 0x3CC 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0 0x164 0x3CC 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD0_SIM_M_HADDR17 0x164 0x3CC 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x168 0x3D0 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x168 0x3D0 0x4D8 0x1 0x1
-#define MX8MQ_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x168 0x3D0 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x168 0x3D0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1 0x168 0x3D0 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD1_SIM_M_HADDR18 0x168 0x3D0 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x16C 0x3D4 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x16C 0x3D4 0x4DC 0x1 0x1
-#define MX8MQ_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x16C 0x3D4 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x16C 0x3D4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2 0x16C 0x3D4 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD2_SIM_M_HADDR19 0x16C 0x3D4 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x170 0x3D8 0x4E0 0x0 0x1
-#define MX8MQ_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x170 0x3D8 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x170 0x3D8 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x170 0x3D8 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3 0x170 0x3D8 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD3_SIM_M_HADDR20 0x170 0x3D8 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x174 0x3DC 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x174 0x3DC 0x51C 0x1 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x174 0x3DC 0x510 0x2 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x174 0x3DC 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x174 0x3DC 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4 0x174 0x3DC 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD4_SIM_M_HADDR21 0x174 0x3DC 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x178 0x3E0 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x178 0x3E0 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x178 0x3E0 0x514 0x2 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x178 0x3E0 0x4C4 0x3 0x1
-#define MX8MQ_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x178 0x3E0 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x178 0x3E0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5 0x178 0x3E0 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD5_SIM_M_HADDR22 0x178 0x3E0 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x17C 0x3E4 0x520 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x17C 0x3E4 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x17C 0x3E4 0x518 0x2 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x17C 0x3E4 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x17C 0x3E4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6 0x17C 0x3E4 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD6_SIM_M_HADDR23 0x17C 0x3E4 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x180 0x3E8 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD7_SAI6_MCLK 0x180 0x3E8 0x530 0x1 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x180 0x3E8 0x4CC 0x2 0x4
-#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x180 0x3E8 0x000 0x3 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x180 0x3E8 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x180 0x3E8 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7 0x180 0x3E8 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD7_SIM_M_HADDR24 0x180 0x3E8 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x184 0x3EC 0x4CC 0x0 0x3
-#define MX8MQ_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x184 0x3EC 0x4EC 0x1 0x1
-#define MX8MQ_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x184 0x3EC 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x184 0x3EC 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_TXFS_SIM_M_HADDR25 0x184 0x3EC 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x188 0x3F0 0x4C8 0x0 0x1
-#define MX8MQ_IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x188 0x3F0 0x4E8 0x1 0x1
-#define MX8MQ_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x188 0x3F0 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_TXC_GPIO4_IO11 0x188 0x3F0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_TXC_SIM_M_HADDR26 0x188 0x3F0 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x18C 0x3F4 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x18C 0x3F4 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x18C 0x3F4 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x18C 0x3F4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8 0x18C 0x3F4 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD0_SIM_M_HADDR27 0x18C 0x3F4 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x190 0x3F8 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x190 0x3F8 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x190 0x3F8 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x190 0x3F8 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9 0x190 0x3F8 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD1_SIM_M_HADDR28 0x190 0x3F8 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x194 0x3FC 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x194 0x3FC 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x194 0x3FC 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x194 0x3FC 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10 0x194 0x3FC 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD2_SIM_M_HADDR29 0x194 0x3FC 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x198 0x400 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x198 0x400 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x198 0x400 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x198 0x400 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11 0x198 0x400 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD3_SIM_M_HADDR30 0x198 0x400 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x19C 0x404 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x19C 0x404 0x510 0x1 0x1
-#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x19C 0x404 0x51C 0x2 0x1
-#define MX8MQ_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x19C 0x404 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19C 0x404 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12 0x19C 0x404 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD4_SIM_M_HADDR31 0x19C 0x404 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x1A0 0x408 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x1A0 0x408 0x514 0x1 0x1
-#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x1A0 0x408 0x000 0x2 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x1A0 0x408 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x1A0 0x408 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13 0x1A0 0x408 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD5_SIM_M_HBURST0 0x1A0 0x408 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x1A4 0x40C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x1A4 0x40C 0x518 0x1 0x1
-#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x1A4 0x40C 0x520 0x2 0x1
-#define MX8MQ_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x1A4 0x40C 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1A4 0x40C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14 0x1A4 0x40C 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD6_SIM_M_HBURST1 0x1A4 0x40C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x1A8 0x410 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD7_SAI6_MCLK 0x1A8 0x410 0x530 0x1 0x1
-#define MX8MQ_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x1A8 0x410 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x1A8 0x410 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15 0x1A8 0x410 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD7_SIM_M_HBURST2 0x1A8 0x410 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x1AC 0x414 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_MCLK_SAI5_MCLK 0x1AC 0x414 0x52C 0x1 0x1
-#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x1AC 0x414 0x4C8 0x2 0x2
-#define MX8MQ_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1AC 0x414 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_MCLK_SIM_M_HRESP 0x1AC 0x414 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2
-#define MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0 0x1B0 0x418 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2
-#define MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI2_RXC_SIM_M_HSIZE1 0x1B4 0x41C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2 0x1B8 0x420 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI2_TXFS_SIM_M_HWRITE 0x1BC 0x424 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x1C0 0x428 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI2_TXC_GPIO4_IO25 0x1C0 0x428 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT 0x1C0 0x428 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x1C4 0x42C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x1C4 0x42C 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x1C4 0x42C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI2_TXD0_TPSMP_CLK 0x1C4 0x42C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x1C8 0x430 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x1C8 0x430 0x52C 0x1 0x2
-#define MX8MQ_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1C8 0x430 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR 0x1C8 0x430 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x1CC 0x434 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x1CC 0x434 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x1CC 0x434 0x4E4 0x2 0x2
-#define MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 0x1CC 0x434 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x1D0 0x438 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2
-#define MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2
-#define MX8MQ_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI3_TXFS_GPT1_CLK 0x1D8 0x440 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2
-#define MX8MQ_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2
-#define MX8MQ_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x1E0 0x448 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x1E0 0x448 0x4E0 0x2 0x2
-#define MX8MQ_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1E0 0x448 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI3_TXD_TPSMP_HDATA3 0x1E0 0x448 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x1E4 0x44C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x1E4 0x44C 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x1E4 0x44C 0x52C 0x2 0x3
-#define MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1E4 0x44C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI3_MCLK_TPSMP_HDATA4 0x1E4 0x44C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x1E8 0x450 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x1E8 0x450 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1E8 0x450 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SPDIF_TX_TPSMP_HDATA5 0x1E8 0x450 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0x1EC 0x454 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x1EC 0x454 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0x1EC 0x454 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SPDIF_RX_TPSMP_HDATA6 0x1EC 0x454 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x1F0 0x458 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x1F0 0x458 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1F0 0x458 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7 0x1F0 0x458 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1F4 0x45C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1F4 0x45C 0x504 0x1 0x0
-#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x1F4 0x45C 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x1F4 0x45C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8 0x1F4 0x45C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x1F8 0x460 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1F8 0x460 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x1F8 0x460 0x504 0x1 0x1
-#define MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x1F8 0x460 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9 0x1F8 0x460 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1FC 0x464 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1FC 0x464 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x1FC 0x464 0x500 0x1 0x0
-#define MX8MQ_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x1FC 0x464 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10 0x1FC 0x464 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x200 0x468 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x200 0x468 0x500 0x1 0x1
-#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x200 0x468 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x200 0x468 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11 0x200 0x468 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x204 0x46C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x204 0x46C 0x50C 0x1 0x0
-#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x204 0x46C 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x204 0x46C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12 0x204 0x46C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x208 0x470 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x208 0x470 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x208 0x470 0x50C 0x1 0x1
-#define MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x208 0x470 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13 0x208 0x470 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x20C 0x474 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x20C 0x474 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x20C 0x474 0x508 0x1 0x0
-#define MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x20C 0x474 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14 0x20C 0x474 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x210 0x478 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x210 0x478 0x508 0x1 0x1
-#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x210 0x478 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x210 0x478 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15 0x210 0x478 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x214 0x47C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_I2C1_SCL_ENET1_MDC 0x214 0x47C 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x214 0x47C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_I2C1_SCL_TPSMP_HDATA16 0x214 0x47C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x218 0x480 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_I2C1_SDA_ENET1_MDIO 0x218 0x480 0x4C0 0x1 0x2
-#define MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x218 0x480 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_I2C1_SDA_TPSMP_HDATA17 0x218 0x480 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x21C 0x484 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x21C 0x484 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x21C 0x484 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_I2C2_SCL_TPSMP_HDATA18 0x21C 0x484 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x220 0x488 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x220 0x488 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x220 0x488 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_I2C2_SDA_TPSMP_HDATA19 0x220 0x488 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0
-#define MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_I2C3_SCL_TPSMP_HDATA20 0x224 0x48C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x228 0x490 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_I2C3_SDA_PWM3_OUT 0x228 0x490 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_I2C3_SDA_GPT3_CLK 0x228 0x490 0x000 0x2 0x0
-#define MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19 0x228 0x490 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_I2C3_SDA_TPSMP_HDATA21 0x228 0x490 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x2 0x0
-#define MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_I2C4_SCL_TPSMP_HDATA22 0x22C 0x494 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x230 0x498 0x528 0x2 0x0
-#define MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_I2C4_SDA_TPSMP_HDATA23 0x230 0x498 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0
-#define MX8MQ_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_UART1_RXD_TPSMP_HDATA24 0x234 0x49C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x0
-#define MX8MQ_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_UART1_TXD_TPSMP_HDATA25 0x238 0x4A0 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x23C 0x4A4 0x4FC 0x0 0x0
-#define MX8MQ_IOMUXC_UART2_RXD_UART2_DTE_TX 0x23C 0x4A4 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_UART2_RXD_ECSPI3_MISO 0x23C 0x4A4 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_UART2_RXD_GPIO5_IO24 0x23C 0x4A4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_UART2_RXD_TPSMP_HDATA26 0x23C 0x4A4 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1
-#define MX8MQ_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_UART2_TXD_TPSMP_HDATA27 0x240 0x4A8 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x244 0x4AC 0x504 0x0 0x2
-#define MX8MQ_IOMUXC_UART3_RXD_UART3_DTE_TX 0x244 0x4AC 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x244 0x4AC 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x244 0x4AC 0x4F0 0x1 0x0
-#define MX8MQ_IOMUXC_UART3_RXD_GPIO5_IO26 0x244 0x4AC 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_UART3_RXD_TPSMP_HDATA28 0x244 0x4AC 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3
-#define MX8MQ_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1
-#define MX8MQ_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_UART3_TXD_TPSMP_HDATA29 0x248 0x4B0 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x24C 0x4B4 0x50C 0x0 0x2
-#define MX8MQ_IOMUXC_UART4_RXD_UART4_DTE_TX 0x24C 0x4B4 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x24C 0x4B4 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x24C 0x4B4 0x4F8 0x1 0x0
-#define MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x24C 0x4B4 0x524 0x2 0x1
-#define MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x24C 0x4B4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_UART4_RXD_TPSMP_HDATA30 0x24C 0x4B4 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3
-#define MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1
-#define MX8MQ_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x250 0x4B8 0x528 0x2 0x1
-#define MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_UART4_TXD_TPSMP_HDATA31 0x250 0x4B8 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_TEST_MODE 0x000 0x254 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_BOOT_MODE0 0x000 0x258 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_BOOT_MODE1 0x000 0x25C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_JTAG_MOD 0x000 0x260 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_JTAG_TRST_B 0x000 0x264 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_JTAG_TDI 0x000 0x268 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_JTAG_TMS 0x000 0x26C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_JTAG_TCK 0x000 0x270 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_JTAG_TDO 0x000 0x274 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_RTC 0x000 0x278 0x000 0x0 0x0
-
-#endif /* __DTS_IMX8MQ_PINFUNC_H */
diff --git a/include/dt-bindings/power/fsl,imx93-power.h b/include/dt-bindings/power/fsl,imx93-power.h
deleted file mode 100644
index 17f9f01..0000000
--- a/include/dt-bindings/power/fsl,imx93-power.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
-/*
- * Copyright 2022 NXP
- */
-
-#ifndef __DT_BINDINGS_IMX93_POWER_H__
-#define __DT_BINDINGS_IMX93_POWER_H__
-
-#define IMX93_MEDIABLK_PD_MIPI_DSI 0
-#define IMX93_MEDIABLK_PD_MIPI_CSI 1
-#define IMX93_MEDIABLK_PD_PXP 2
-#define IMX93_MEDIABLK_PD_LCDIF 3
-#define IMX93_MEDIABLK_PD_ISI 4
-
-#endif
diff --git a/include/dt-bindings/power/imx7-power.h b/include/dt-bindings/power/imx7-power.h
deleted file mode 100644
index 597c1aa..0000000
--- a/include/dt-bindings/power/imx7-power.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2017 Impinj
- */
-
-#ifndef __DT_BINDINGS_IMX7_POWER_H__
-#define __DT_BINDINGS_IMX7_POWER_H__
-
-#define IMX7_POWER_DOMAIN_MIPI_PHY 0
-#define IMX7_POWER_DOMAIN_PCIE_PHY 1
-#define IMX7_POWER_DOMAIN_USB_HSIC_PHY 2
-
-#endif
diff --git a/include/dt-bindings/power/imx8mm-power.h b/include/dt-bindings/power/imx8mm-power.h
deleted file mode 100644
index 648938f..0000000
--- a/include/dt-bindings/power/imx8mm-power.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
-/*
- * Copyright (C) 2020 Pengutronix, Lucas Stach <kernel@pengutronix.de>
- */
-
-#ifndef __DT_BINDINGS_IMX8MM_POWER_H__
-#define __DT_BINDINGS_IMX8MM_POWER_H__
-
-#define IMX8MM_POWER_DOMAIN_HSIOMIX 0
-#define IMX8MM_POWER_DOMAIN_PCIE 1
-#define IMX8MM_POWER_DOMAIN_OTG1 2
-#define IMX8MM_POWER_DOMAIN_OTG2 3
-#define IMX8MM_POWER_DOMAIN_GPUMIX 4
-#define IMX8MM_POWER_DOMAIN_GPU 5
-#define IMX8MM_POWER_DOMAIN_VPUMIX 6
-#define IMX8MM_POWER_DOMAIN_VPUG1 7
-#define IMX8MM_POWER_DOMAIN_VPUG2 8
-#define IMX8MM_POWER_DOMAIN_VPUH1 9
-#define IMX8MM_POWER_DOMAIN_DISPMIX 10
-#define IMX8MM_POWER_DOMAIN_MIPI 11
-
-#define IMX8MM_VPUBLK_PD_G1 0
-#define IMX8MM_VPUBLK_PD_G2 1
-#define IMX8MM_VPUBLK_PD_H1 2
-
-#define IMX8MM_DISPBLK_PD_CSI_BRIDGE 0
-#define IMX8MM_DISPBLK_PD_LCDIF 1
-#define IMX8MM_DISPBLK_PD_MIPI_DSI 2
-#define IMX8MM_DISPBLK_PD_MIPI_CSI 3
-
-#endif
diff --git a/include/dt-bindings/power/imx8mn-power.h b/include/dt-bindings/power/imx8mn-power.h
deleted file mode 100644
index eedd0e5..0000000
--- a/include/dt-bindings/power/imx8mn-power.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
-/*
- * Copyright (C) 2020 Compass Electronics Group, LLC
- */
-
-#ifndef __DT_BINDINGS_IMX8MN_POWER_H__
-#define __DT_BINDINGS_IMX8MN_POWER_H__
-
-#define IMX8MN_POWER_DOMAIN_HSIOMIX 0
-#define IMX8MN_POWER_DOMAIN_OTG1 1
-#define IMX8MN_POWER_DOMAIN_GPUMIX 2
-#define IMX8MN_POWER_DOMAIN_DISPMIX 3
-#define IMX8MN_POWER_DOMAIN_MIPI 4
-
-#define IMX8MN_DISPBLK_PD_MIPI_DSI 0
-#define IMX8MN_DISPBLK_PD_MIPI_CSI 1
-#define IMX8MN_DISPBLK_PD_LCDIF 2
-#define IMX8MN_DISPBLK_PD_ISI 3
-
-#endif
diff --git a/include/dt-bindings/power/imx8mp-power.h b/include/dt-bindings/power/imx8mp-power.h
deleted file mode 100644
index 2fe3c2a..0000000
--- a/include/dt-bindings/power/imx8mp-power.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
-/*
- * Copyright (C) 2020 Pengutronix, Sascha Hauer <kernel@pengutronix.de>
- */
-
-#ifndef __DT_BINDINGS_IMX8MP_POWER_DOMAIN_POWER_H__
-#define __DT_BINDINGS_IMX8MP_POWER_DOMAIN_POWER_H__
-
-#define IMX8MP_POWER_DOMAIN_MIPI_PHY1 0
-#define IMX8MP_POWER_DOMAIN_PCIE_PHY 1
-#define IMX8MP_POWER_DOMAIN_USB1_PHY 2
-#define IMX8MP_POWER_DOMAIN_USB2_PHY 3
-#define IMX8MP_POWER_DOMAIN_MLMIX 4
-#define IMX8MP_POWER_DOMAIN_AUDIOMIX 5
-#define IMX8MP_POWER_DOMAIN_GPU2D 6
-#define IMX8MP_POWER_DOMAIN_GPUMIX 7
-#define IMX8MP_POWER_DOMAIN_VPUMIX 8
-#define IMX8MP_POWER_DOMAIN_GPU3D 9
-#define IMX8MP_POWER_DOMAIN_MEDIAMIX 10
-#define IMX8MP_POWER_DOMAIN_VPU_G1 11
-#define IMX8MP_POWER_DOMAIN_VPU_G2 12
-#define IMX8MP_POWER_DOMAIN_VPU_VC8000E 13
-#define IMX8MP_POWER_DOMAIN_HDMIMIX 14
-#define IMX8MP_POWER_DOMAIN_HDMI_PHY 15
-#define IMX8MP_POWER_DOMAIN_MIPI_PHY2 16
-#define IMX8MP_POWER_DOMAIN_HSIOMIX 17
-#define IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP 18
-
-#define IMX8MP_HSIOBLK_PD_USB 0
-#define IMX8MP_HSIOBLK_PD_USB_PHY1 1
-#define IMX8MP_HSIOBLK_PD_USB_PHY2 2
-#define IMX8MP_HSIOBLK_PD_PCIE 3
-#define IMX8MP_HSIOBLK_PD_PCIE_PHY 4
-
-#define IMX8MP_MEDIABLK_PD_MIPI_DSI_1 0
-#define IMX8MP_MEDIABLK_PD_MIPI_CSI2_1 1
-#define IMX8MP_MEDIABLK_PD_LCDIF_1 2
-#define IMX8MP_MEDIABLK_PD_ISI 3
-#define IMX8MP_MEDIABLK_PD_MIPI_CSI2_2 4
-#define IMX8MP_MEDIABLK_PD_LCDIF_2 5
-#define IMX8MP_MEDIABLK_PD_ISP 6
-#define IMX8MP_MEDIABLK_PD_DWE 7
-#define IMX8MP_MEDIABLK_PD_MIPI_DSI_2 8
-
-#define IMX8MP_HDMIBLK_PD_IRQSTEER 0
-#define IMX8MP_HDMIBLK_PD_LCDIF 1
-#define IMX8MP_HDMIBLK_PD_PAI 2
-#define IMX8MP_HDMIBLK_PD_PVI 3
-#define IMX8MP_HDMIBLK_PD_TRNG 4
-#define IMX8MP_HDMIBLK_PD_HDMI_TX 5
-#define IMX8MP_HDMIBLK_PD_HDMI_TX_PHY 6
-#define IMX8MP_HDMIBLK_PD_HDCP 7
-#define IMX8MP_HDMIBLK_PD_HRV 8
-
-#define IMX8MP_VPUBLK_PD_G1 0
-#define IMX8MP_VPUBLK_PD_G2 1
-#define IMX8MP_VPUBLK_PD_VC8000E 2
-
-#endif
diff --git a/include/dt-bindings/power/imx8mq-power.h b/include/dt-bindings/power/imx8mq-power.h
deleted file mode 100755
index 9f7d0f1..0000000
--- a/include/dt-bindings/power/imx8mq-power.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
-/*
- * Copyright (C) 2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
- */
-
-#ifndef __DT_BINDINGS_IMX8MQ_POWER_H__
-#define __DT_BINDINGS_IMX8MQ_POWER_H__
-
-#define IMX8M_POWER_DOMAIN_MIPI 0
-#define IMX8M_POWER_DOMAIN_PCIE1 1
-#define IMX8M_POWER_DOMAIN_USB_OTG1 2
-#define IMX8M_POWER_DOMAIN_USB_OTG2 3
-#define IMX8M_POWER_DOMAIN_DDR1 4
-#define IMX8M_POWER_DOMAIN_GPU 5
-#define IMX8M_POWER_DOMAIN_VPU 6
-#define IMX8M_POWER_DOMAIN_DISP 7
-#define IMX8M_POWER_DOMAIN_MIPI_CSI1 8
-#define IMX8M_POWER_DOMAIN_MIPI_CSI2 9
-#define IMX8M_POWER_DOMAIN_PCIE2 10
-
-#define IMX8MQ_VPUBLK_PD_G1 0
-#define IMX8MQ_VPUBLK_PD_G2 1
-
-#endif
diff --git a/include/dt-bindings/power/imx8ulp-power.h b/include/dt-bindings/power/imx8ulp-power.h
deleted file mode 100644
index a556b2e..0000000
--- a/include/dt-bindings/power/imx8ulp-power.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
-/*
- * Copyright 2021 NXP
- */
-
-#ifndef __DT_BINDINGS_IMX8ULP_POWER_H__
-#define __DT_BINDINGS_IMX8ULP_POWER_H__
-
-#define IMX8ULP_PD_DMA1 0
-#define IMX8ULP_PD_FLEXSPI2 1
-#define IMX8ULP_PD_USB0 2
-#define IMX8ULP_PD_USDHC0 3
-#define IMX8ULP_PD_USDHC1 4
-#define IMX8ULP_PD_USDHC2_USB1 5
-#define IMX8ULP_PD_DCNANO 6
-#define IMX8ULP_PD_EPDC 7
-#define IMX8ULP_PD_DMA2 8
-#define IMX8ULP_PD_GPU2D 9
-#define IMX8ULP_PD_GPU3D 10
-#define IMX8ULP_PD_HIFI4 11
-#define IMX8ULP_PD_ISI 12
-#define IMX8ULP_PD_MIPI_CSI 13
-#define IMX8ULP_PD_MIPI_DSI 14
-#define IMX8ULP_PD_PXP 15
-
-#endif
diff --git a/include/dt-bindings/power/rockchip,rv1126-power.h b/include/dt-bindings/power/rockchip,rv1126-power.h
deleted file mode 100644
index 38a68e0..0000000
--- a/include/dt-bindings/power/rockchip,rv1126-power.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-
-#ifndef __DT_BINDINGS_POWER_RV1126_POWER_H__
-#define __DT_BINDINGS_POWER_RV1126_POWER_H__
-
-/* VD_CORE */
-#define RV1126_PD_CPU_0 0
-#define RV1126_PD_CPU_1 1
-#define RV1126_PD_CPU_2 2
-#define RV1126_PD_CPU_3 3
-#define RV1126_PD_CORE_ALIVE 4
-
-/* VD_PMU */
-#define RV1126_PD_PMU 5
-#define RV1126_PD_PMU_ALIVE 6
-
-/* VD_NPU */
-#define RV1126_PD_NPU 7
-
-/* VD_VEPU */
-#define RV1126_PD_VEPU 8
-
-/* VD_LOGIC */
-#define RV1126_PD_VI 9
-#define RV1126_PD_VO 10
-#define RV1126_PD_ISPP 11
-#define RV1126_PD_VDPU 12
-#define RV1126_PD_CRYPTO 13
-#define RV1126_PD_DDR 14
-#define RV1126_PD_NVM 15
-#define RV1126_PD_SDIO 16
-#define RV1126_PD_USB 17
-#define RV1126_PD_LOGIC_ALIVE 18
-
-#endif
diff --git a/include/dt-bindings/power/xlnx-zynqmp-power.h b/include/dt-bindings/power/xlnx-zynqmp-power.h
index e7eb096..618024c 100644
--- a/include/dt-bindings/power/xlnx-zynqmp-power.h
+++ b/include/dt-bindings/power/xlnx-zynqmp-power.h
@@ -6,16 +6,12 @@
#ifndef _DT_BINDINGS_ZYNQMP_POWER_H
#define _DT_BINDINGS_ZYNQMP_POWER_H
-#define PD_RPU_0 6
-#define PD_RPU_1 7
-#define PD_OCM_BANK_0 11
-#define PD_OCM_BANK_1 12
-#define PD_OCM_BANK_2 13
-#define PD_OCM_BANK_3 14
-#define PD_TCM_BANK_0 15
-#define PD_TCM_BANK_1 16
-#define PD_TCM_BANK_2 17
-#define PD_TCM_BANK_3 18
+#define PD_RPU_0 7
+#define PD_RPU_1 8
+#define PD_R5_0_ATCM 15
+#define PD_R5_0_BTCM 16
+#define PD_R5_1_ATCM 17
+#define PD_R5_1_BTCM 18
#define PD_USB_0 22
#define PD_USB_1 23
#define PD_TTC_0 24
@@ -45,6 +41,5 @@
#define PD_CAN_1 48
#define PD_GPU 58
#define PD_PCIE 59
-#define PD_PL 69
#endif
diff --git a/include/dt-bindings/reset/imx7-reset.h b/include/dt-bindings/reset/imx7-reset.h
deleted file mode 100644
index bb92452..0000000
--- a/include/dt-bindings/reset/imx7-reset.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2017 Impinj, Inc.
- *
- * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
- */
-
-#ifndef DT_BINDING_RESET_IMX7_H
-#define DT_BINDING_RESET_IMX7_H
-
-#define IMX7_RESET_A7_CORE_POR_RESET0 0
-#define IMX7_RESET_A7_CORE_POR_RESET1 1
-#define IMX7_RESET_A7_CORE_RESET0 2
-#define IMX7_RESET_A7_CORE_RESET1 3
-#define IMX7_RESET_A7_DBG_RESET0 4
-#define IMX7_RESET_A7_DBG_RESET1 5
-#define IMX7_RESET_A7_ETM_RESET0 6
-#define IMX7_RESET_A7_ETM_RESET1 7
-#define IMX7_RESET_A7_SOC_DBG_RESET 8
-#define IMX7_RESET_A7_L2RESET 9
-#define IMX7_RESET_SW_M4C_RST 10
-#define IMX7_RESET_SW_M4P_RST 11
-#define IMX7_RESET_EIM_RST 12
-#define IMX7_RESET_HSICPHY_PORT_RST 13
-#define IMX7_RESET_USBPHY1_POR 14
-#define IMX7_RESET_USBPHY1_PORT_RST 15
-#define IMX7_RESET_USBPHY2_POR 16
-#define IMX7_RESET_USBPHY2_PORT_RST 17
-#define IMX7_RESET_MIPI_PHY_MRST 18
-#define IMX7_RESET_MIPI_PHY_SRST 19
-
-/*
- * IMX7_RESET_PCIEPHY is a logical reset line combining PCIEPHY_BTN
- * and PCIEPHY_G_RST
- */
-#define IMX7_RESET_PCIEPHY 20
-#define IMX7_RESET_PCIEPHY_PERST 21
-
-/*
- * IMX7_RESET_PCIE_CTRL_APPS_EN is not strictly a reset line, but it
- * can be used to inhibit PCIe LTTSM, so, in a way, it can be thoguht
- * of as one
- */
-#define IMX7_RESET_PCIE_CTRL_APPS_EN 22
-#define IMX7_RESET_DDRC_PRST 23
-#define IMX7_RESET_DDRC_CORE_RST 24
-
-#define IMX7_RESET_PCIE_CTRL_APPS_TURNOFF 25
-
-#define IMX7_RESET_NUM 26
-
-#endif
diff --git a/include/dt-bindings/reset/imx8mp-reset.h b/include/dt-bindings/reset/imx8mp-reset.h
deleted file mode 100644
index 2e8c910..0000000
--- a/include/dt-bindings/reset/imx8mp-reset.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright 2020 NXP
- */
-
-#ifndef DT_BINDING_RESET_IMX8MP_H
-#define DT_BINDING_RESET_IMX8MP_H
-
-#define IMX8MP_RESET_A53_CORE_POR_RESET0 0
-#define IMX8MP_RESET_A53_CORE_POR_RESET1 1
-#define IMX8MP_RESET_A53_CORE_POR_RESET2 2
-#define IMX8MP_RESET_A53_CORE_POR_RESET3 3
-#define IMX8MP_RESET_A53_CORE_RESET0 4
-#define IMX8MP_RESET_A53_CORE_RESET1 5
-#define IMX8MP_RESET_A53_CORE_RESET2 6
-#define IMX8MP_RESET_A53_CORE_RESET3 7
-#define IMX8MP_RESET_A53_DBG_RESET0 8
-#define IMX8MP_RESET_A53_DBG_RESET1 9
-#define IMX8MP_RESET_A53_DBG_RESET2 10
-#define IMX8MP_RESET_A53_DBG_RESET3 11
-#define IMX8MP_RESET_A53_ETM_RESET0 12
-#define IMX8MP_RESET_A53_ETM_RESET1 13
-#define IMX8MP_RESET_A53_ETM_RESET2 14
-#define IMX8MP_RESET_A53_ETM_RESET3 15
-#define IMX8MP_RESET_A53_SOC_DBG_RESET 16
-#define IMX8MP_RESET_A53_L2RESET 17
-#define IMX8MP_RESET_SW_NON_SCLR_M7C_RST 18
-#define IMX8MP_RESET_OTG1_PHY_RESET 19
-#define IMX8MP_RESET_OTG2_PHY_RESET 20
-#define IMX8MP_RESET_SUPERMIX_RESET 21
-#define IMX8MP_RESET_AUDIOMIX_RESET 22
-#define IMX8MP_RESET_MLMIX_RESET 23
-#define IMX8MP_RESET_PCIEPHY 24
-#define IMX8MP_RESET_PCIEPHY_PERST 25
-#define IMX8MP_RESET_PCIE_CTRL_APPS_EN 26
-#define IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF 27
-#define IMX8MP_RESET_HDMI_PHY_APB_RESET 28
-#define IMX8MP_RESET_MEDIA_RESET 29
-#define IMX8MP_RESET_GPU2D_RESET 30
-#define IMX8MP_RESET_GPU3D_RESET 31
-#define IMX8MP_RESET_GPU_RESET 32
-#define IMX8MP_RESET_VPU_RESET 33
-#define IMX8MP_RESET_VPU_G1_RESET 34
-#define IMX8MP_RESET_VPU_G2_RESET 35
-#define IMX8MP_RESET_VPUVC8KE_RESET 36
-#define IMX8MP_RESET_NOC_RESET 37
-
-#define IMX8MP_RESET_NUM 38
-
-#endif
diff --git a/include/dt-bindings/reset/imx8mq-reset.h b/include/dt-bindings/reset/imx8mq-reset.h
deleted file mode 100755
index 7058706..0000000
--- a/include/dt-bindings/reset/imx8mq-reset.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2018 Zodiac Inflight Innovations
- *
- * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
- */
-
-#ifndef DT_BINDING_RESET_IMX8MQ_H
-#define DT_BINDING_RESET_IMX8MQ_H
-
-#define IMX8MQ_RESET_A53_CORE_POR_RESET0 0
-#define IMX8MQ_RESET_A53_CORE_POR_RESET1 1
-#define IMX8MQ_RESET_A53_CORE_POR_RESET2 2
-#define IMX8MQ_RESET_A53_CORE_POR_RESET3 3
-#define IMX8MQ_RESET_A53_CORE_RESET0 4
-#define IMX8MQ_RESET_A53_CORE_RESET1 5
-#define IMX8MQ_RESET_A53_CORE_RESET2 6
-#define IMX8MQ_RESET_A53_CORE_RESET3 7
-#define IMX8MQ_RESET_A53_DBG_RESET0 8
-#define IMX8MQ_RESET_A53_DBG_RESET1 9
-#define IMX8MQ_RESET_A53_DBG_RESET2 10
-#define IMX8MQ_RESET_A53_DBG_RESET3 11
-#define IMX8MQ_RESET_A53_ETM_RESET0 12
-#define IMX8MQ_RESET_A53_ETM_RESET1 13
-#define IMX8MQ_RESET_A53_ETM_RESET2 14
-#define IMX8MQ_RESET_A53_ETM_RESET3 15
-#define IMX8MQ_RESET_A53_SOC_DBG_RESET 16
-#define IMX8MQ_RESET_A53_L2RESET 17
-#define IMX8MQ_RESET_SW_NON_SCLR_M4C_RST 18
-#define IMX8MQ_RESET_OTG1_PHY_RESET 19
-#define IMX8MQ_RESET_OTG2_PHY_RESET 20 /* i.MX8MN does NOT support */
-#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21 /* i.MX8MN does NOT support */
-#define IMX8MQ_RESET_MIPI_DSI_RESET_N 22 /* i.MX8MN does NOT support */
-#define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N 23 /* i.MX8MN does NOT support */
-#define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N 24 /* i.MX8MN does NOT support */
-#define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N 25 /* i.MX8MN does NOT support */
-#define IMX8MQ_RESET_PCIEPHY 26 /* i.MX8MN does NOT support */
-#define IMX8MQ_RESET_PCIEPHY_PERST 27 /* i.MX8MN does NOT support */
-#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28 /* i.MX8MN does NOT support */
-#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29 /* i.MX8MN does NOT support */
-#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30 /* i.MX8MM/i.MX8MN does NOT support */
-#define IMX8MQ_RESET_DISP_RESET 31
-#define IMX8MQ_RESET_GPU_RESET 32
-#define IMX8MQ_RESET_VPU_RESET 33 /* i.MX8MN does NOT support */
-#define IMX8MQ_RESET_PCIEPHY2 34 /* i.MX8MM/i.MX8MN does NOT support */
-#define IMX8MQ_RESET_PCIEPHY2_PERST 35 /* i.MX8MM/i.MX8MN does NOT support */
-#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36 /* i.MX8MM/i.MX8MN does NOT support */
-#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37 /* i.MX8MM/i.MX8MN does NOT support */
-#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38 /* i.MX8MM/i.MX8MN does NOT support */
-#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39 /* i.MX8MM/i.MX8MN does NOT support */
-#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40 /* i.MX8MM/i.MX8MN does NOT support */
-#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41 /* i.MX8MM/i.MX8MN does NOT support */
-#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42 /* i.MX8MM/i.MX8MN does NOT support */
-#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43 /* i.MX8MM/i.MX8MN does NOT support */
-#define IMX8MQ_RESET_DDRC1_PRST 44 /* i.MX8MN does NOT support */
-#define IMX8MQ_RESET_DDRC1_CORE_RESET 45 /* i.MX8MN does NOT support */
-#define IMX8MQ_RESET_DDRC1_PHY_RESET 46 /* i.MX8MN does NOT support */
-#define IMX8MQ_RESET_DDRC2_PRST 47 /* i.MX8MM/i.MX8MN does NOT support */
-#define IMX8MQ_RESET_DDRC2_CORE_RESET 48 /* i.MX8MM/i.MX8MN does NOT support */
-#define IMX8MQ_RESET_DDRC2_PHY_RESET 49 /* i.MX8MM/i.MX8MN does NOT support */
-#define IMX8MQ_RESET_SW_M4C_RST 50
-#define IMX8MQ_RESET_SW_M4P_RST 51
-#define IMX8MQ_RESET_M4_ENABLE 52
-
-#define IMX8MQ_RESET_NUM 53
-
-#endif
diff --git a/include/dt-bindings/reset/imx8ulp-pcc-reset.h b/include/dt-bindings/reset/imx8ulp-pcc-reset.h
deleted file mode 100644
index e99a473..0000000
--- a/include/dt-bindings/reset/imx8ulp-pcc-reset.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright 2021 NXP
- */
-
-#ifndef DT_BINDING_PCC_RESET_IMX8ULP_H
-#define DT_BINDING_PCC_RESET_IMX8ULP_H
-
-/* PCC3 */
-#define PCC3_WDOG3_SWRST 0
-#define PCC3_WDOG4_SWRST 1
-#define PCC3_LPIT1_SWRST 2
-#define PCC3_TPM4_SWRST 3
-#define PCC3_TPM5_SWRST 4
-#define PCC3_FLEXIO1_SWRST 5
-#define PCC3_I3C2_SWRST 6
-#define PCC3_LPI2C4_SWRST 7
-#define PCC3_LPI2C5_SWRST 8
-#define PCC3_LPUART4_SWRST 9
-#define PCC3_LPUART5_SWRST 10
-#define PCC3_LPSPI4_SWRST 11
-#define PCC3_LPSPI5_SWRST 12
-
-/* PCC4 */
-#define PCC4_FLEXSPI2_SWRST 0
-#define PCC4_TPM6_SWRST 1
-#define PCC4_TPM7_SWRST 2
-#define PCC4_LPI2C6_SWRST 3
-#define PCC4_LPI2C7_SWRST 4
-#define PCC4_LPUART6_SWRST 5
-#define PCC4_LPUART7_SWRST 6
-#define PCC4_SAI4_SWRST 7
-#define PCC4_SAI5_SWRST 8
-#define PCC4_USDHC0_SWRST 9
-#define PCC4_USDHC1_SWRST 10
-#define PCC4_USDHC2_SWRST 11
-#define PCC4_USB0_SWRST 12
-#define PCC4_USB0_PHY_SWRST 13
-#define PCC4_USB1_SWRST 14
-#define PCC4_USB1_PHY_SWRST 15
-#define PCC4_ENET_SWRST 16
-
-/* PCC5 */
-#define PCC5_TPM8_SWRST 0
-#define PCC5_SAI6_SWRST 1
-#define PCC5_SAI7_SWRST 2
-#define PCC5_SPDIF_SWRST 3
-#define PCC5_ISI_SWRST 4
-#define PCC5_CSI_REGS_SWRST 5
-#define PCC5_CSI_SWRST 6
-#define PCC5_DSI_SWRST 7
-#define PCC5_WDOG5_SWRST 8
-#define PCC5_EPDC_SWRST 9
-#define PCC5_PXP_SWRST 10
-#define PCC5_GPU2D_SWRST 11
-#define PCC5_GPU3D_SWRST 12
-#define PCC5_DC_NANO_SWRST 13
-
-#endif /*DT_BINDING_RESET_IMX8ULP_H */
diff --git a/include/dt-bindings/soc/samsung,exynos-usi.h b/include/dt-bindings/soc/samsung,exynos-usi.h
deleted file mode 100644
index a01af16..0000000
--- a/include/dt-bindings/soc/samsung,exynos-usi.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-/*
- * Copyright (c) 2021 Linaro Ltd.
- * Author: Sam Protsenko <semen.protsenko@linaro.org>
- *
- * Device Tree bindings for Samsung Exynos USI (Universal Serial Interface).
- */
-
-#ifndef __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H
-#define __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H
-
-#define USI_V2_NONE 0
-#define USI_V2_UART 1
-#define USI_V2_SPI 2
-#define USI_V2_I2C 3
-
-#endif /* __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H */
diff --git a/include/dt-bindings/sound/fsl-imx-audmux.h b/include/dt-bindings/sound/fsl-imx-audmux.h
deleted file mode 100644
index 15f138b..0000000
--- a/include/dt-bindings/sound/fsl-imx-audmux.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __DT_FSL_IMX_AUDMUX_H
-#define __DT_FSL_IMX_AUDMUX_H
-
-#define MX27_AUDMUX_HPCR1_SSI0 0
-#define MX27_AUDMUX_HPCR2_SSI1 1
-#define MX27_AUDMUX_HPCR3_SSI_PINS_4 2
-#define MX27_AUDMUX_PPCR1_SSI_PINS_1 3
-#define MX27_AUDMUX_PPCR2_SSI_PINS_2 4
-#define MX27_AUDMUX_PPCR3_SSI_PINS_3 5
-
-#define MX31_AUDMUX_PORT1_SSI0 0
-#define MX31_AUDMUX_PORT2_SSI1 1
-#define MX31_AUDMUX_PORT3_SSI_PINS_3 2
-#define MX31_AUDMUX_PORT4_SSI_PINS_4 3
-#define MX31_AUDMUX_PORT5_SSI_PINS_5 4
-#define MX31_AUDMUX_PORT6_SSI_PINS_6 5
-#define MX31_AUDMUX_PORT7_SSI_PINS_7 6
-
-#define MX51_AUDMUX_PORT1_SSI0 0
-#define MX51_AUDMUX_PORT2_SSI1 1
-#define MX51_AUDMUX_PORT3 2
-#define MX51_AUDMUX_PORT4 3
-#define MX51_AUDMUX_PORT5 4
-#define MX51_AUDMUX_PORT6 5
-#define MX51_AUDMUX_PORT7 6
-
-/*
- * TFCSEL/RFCSEL (i.MX27) or TFSEL/TCSEL/RFSEL/RCSEL (i.MX31/51/53/6Q)
- * can be sourced from Rx/Tx.
- */
-#define IMX_AUDMUX_RXFS 0x8
-#define IMX_AUDMUX_RXCLK 0x8
-
-/* Register definitions for the i.MX21/27 Digital Audio Multiplexer */
-#define IMX_AUDMUX_V1_PCR_INMMASK(x) ((x) & 0xff)
-#define IMX_AUDMUX_V1_PCR_INMEN (1 << 8)
-#define IMX_AUDMUX_V1_PCR_TXRXEN (1 << 10)
-#define IMX_AUDMUX_V1_PCR_SYN (1 << 12)
-#define IMX_AUDMUX_V1_PCR_RXDSEL(x) (((x) & 0x7) << 13)
-#define IMX_AUDMUX_V1_PCR_RFCSEL(x) (((x) & 0xf) << 20)
-#define IMX_AUDMUX_V1_PCR_RCLKDIR (1 << 24)
-#define IMX_AUDMUX_V1_PCR_RFSDIR (1 << 25)
-#define IMX_AUDMUX_V1_PCR_TFCSEL(x) (((x) & 0xf) << 26)
-#define IMX_AUDMUX_V1_PCR_TCLKDIR (1 << 30)
-#define IMX_AUDMUX_V1_PCR_TFSDIR (1 << 31)
-
-/* Register definitions for the i.MX25/31/35/51 Digital Audio Multiplexer */
-#define IMX_AUDMUX_V2_PTCR_TFSDIR (1 << 31)
-#define IMX_AUDMUX_V2_PTCR_TFSEL(x) (((x) & 0xf) << 27)
-#define IMX_AUDMUX_V2_PTCR_TCLKDIR (1 << 26)
-#define IMX_AUDMUX_V2_PTCR_TCSEL(x) (((x) & 0xf) << 22)
-#define IMX_AUDMUX_V2_PTCR_RFSDIR (1 << 21)
-#define IMX_AUDMUX_V2_PTCR_RFSEL(x) (((x) & 0xf) << 17)
-#define IMX_AUDMUX_V2_PTCR_RCLKDIR (1 << 16)
-#define IMX_AUDMUX_V2_PTCR_RCSEL(x) (((x) & 0xf) << 12)
-#define IMX_AUDMUX_V2_PTCR_SYN (1 << 11)
-
-#define IMX_AUDMUX_V2_PDCR_RXDSEL(x) (((x) & 0x7) << 13)
-#define IMX_AUDMUX_V2_PDCR_TXRXEN (1 << 12)
-#define IMX_AUDMUX_V2_PDCR_MODE(x) (((x) & 0x3) << 8)
-#define IMX_AUDMUX_V2_PDCR_INMMASK(x) ((x) & 0xff)
-
-#endif /* __DT_FSL_IMX_AUDMUX_H */
diff --git a/include/eeprom_layout.h b/include/eeprom_layout.h
index 730d963..b1d6220 100644
--- a/include/eeprom_layout.h
+++ b/include/eeprom_layout.h
@@ -9,6 +9,8 @@
#ifndef _LAYOUT_
#define _LAYOUT_
+#include <eeprom_field.h>
+
#define RESERVED_FIELDS NULL
#define LAYOUT_VERSION_UNRECOGNIZED -1
#define LAYOUT_VERSION_AUTODETECT -2
@@ -24,6 +26,8 @@
char *new_data);
};
+struct eeprom_field *eeprom_layout_find_field(struct eeprom_layout *layout,
+ char *field_name, bool warn);
void eeprom_layout_setup(struct eeprom_layout *layout, unsigned char *buf,
unsigned int buf_size, int layout_version);
__weak void __eeprom_layout_assign(struct eeprom_layout *layout,
diff --git a/include/efi_load_initrd.h b/include/efi_load_initrd.h
index be5d5a7..9feafb1 100644
--- a/include/efi_load_initrd.h
+++ b/include/efi_load_initrd.h
@@ -18,7 +18,17 @@
0xac, 0x74, 0xca, 0x55, 0x52, 0x31, 0xcc, 0x68)
extern const efi_guid_t efi_lf2_initrd_guid;
-struct efi_initrd_dp {
+/**
+ * struct efi_lo_dp_prefix - separator device path used in load options
+ *
+ * We use vendor media device nodes in UEFI load options to separate
+ * the binary, initrd, and fdt device-paths. This structure contains
+ * the vendor media device node and an end node.
+ *
+ * @vendor: vendor media device node
+ * @end: end node
+ */
+struct efi_lo_dp_prefix {
struct efi_device_path_vendor vendor;
struct efi_device_path end;
} __packed;
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 9600941..6c993e1 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -664,6 +664,10 @@
void *source_buffer,
efi_uintn_t source_size,
efi_handle_t *image_handle);
+/* Load image from path */
+efi_status_t efi_load_image_from_path(bool boot_policy,
+ struct efi_device_path *file_path,
+ void **buffer, efi_uintn_t *size);
/* Start image */
efi_status_t EFIAPI efi_start_image(efi_handle_t image_handle,
efi_uintn_t *exit_data_size,
@@ -946,7 +950,7 @@
const efi_guid_t *guid);
struct efi_device_path *efi_dp_concat(const struct efi_device_path *dp1,
const struct efi_device_path *dp2,
- bool split_end_node);
+ size_t split_end_node);
struct efi_device_path *search_gpt_dp_node(struct efi_device_path *device_path);
efi_status_t efi_deserialize_load_option(struct efi_load_option *lo, u8 *data,
efi_uintn_t *size);
@@ -1185,4 +1189,22 @@
*/
void efi_add_known_memory(void);
+/**
+ * efi_load_option_dp_join() - join device-paths for load option
+ *
+ * @dp: in: binary device-path, out: joined device-path
+ * @dp_size: size of joined device-path
+ * @initrd_dp: initrd device-path or NULL
+ * @fdt_dp: device-tree device-path or NULL
+ * Return: status_code
+ */
+efi_status_t efi_load_option_dp_join(struct efi_device_path **dp,
+ size_t *dp_size,
+ struct efi_device_path *initrd_dp,
+ struct efi_device_path *fdt_dp);
+
+int efi_get_distro_fdt_name(char *fname, int size, int seq);
+
+void efi_load_distro_fdt(void **fdt, efi_uintn_t *fdt_size);
+
#endif /* _EFI_LOADER_H */
diff --git a/include/efi_tcg2.h b/include/efi_tcg2.h
index a75b5a3..8dfb1bc 100644
--- a/include/efi_tcg2.h
+++ b/include/efi_tcg2.h
@@ -18,6 +18,7 @@
#include <efi_api.h>
#include <tpm-v2.h>
+#include <tpm_tcg2.h>
/* TPMV2 only */
#define TCG2_EVENT_LOG_FORMAT_TCG_2 0x00000002
@@ -25,14 +26,6 @@
#define PE_COFF_IMAGE 0x0000000000000010
#define EFI_TCG2_MAX_PCR_INDEX 23
-
-/* Algorithm Registry */
-#define EFI_TCG2_BOOT_HASH_ALG_SHA1 0x00000001
-#define EFI_TCG2_BOOT_HASH_ALG_SHA256 0x00000002
-#define EFI_TCG2_BOOT_HASH_ALG_SHA384 0x00000004
-#define EFI_TCG2_BOOT_HASH_ALG_SHA512 0x00000008
-#define EFI_TCG2_BOOT_HASH_ALG_SM3_256 0x00000010
-
#define EFI_TCG2_FINAL_EVENTS_TABLE_VERSION 1
#define TPM2_EVENT_LOG_SIZE CONFIG_EFI_TCG2_PROTOCOL_EVENTLOG_SIZE
diff --git a/include/elf.h b/include/elf.h
index a4ba74d..b88e6cf 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -12,6 +12,12 @@
#ifndef __ASSEMBLY__
#include "compiler.h"
+/* Flag param bits for bootelf() function */
+typedef struct {
+ unsigned phdr : 1; /* load via program (not section) headers */
+ unsigned autostart : 1; /* Start ELF after loading */
+} Bootelf_flags;
+
/* This version doesn't work for 64-bit ABIs - Erik */
/* These typedefs need to be handled better */
@@ -700,6 +706,10 @@
#define R_RISCV_RELATIVE 3
#ifndef __ASSEMBLY__
+unsigned long bootelf_exec(ulong (*entry)(int, char * const[]),
+ int argc, char *const argv[]);
+unsigned long bootelf(unsigned long addr, Bootelf_flags flags,
+ int argc, char *const argv[]);
int valid_elf_image(unsigned long addr);
unsigned long load_elf64_image_phdr(unsigned long addr);
unsigned long load_elf64_image_shdr(unsigned long addr);
diff --git a/include/env/ti/k3_dfu.env b/include/env/ti/k3_dfu.env
index 2015296..b42cf21 100644
--- a/include/env/ti/k3_dfu.env
+++ b/include/env/ti/k3_dfu.env
@@ -9,7 +9,7 @@
dfu_alt_info_emmc=
rawemmc raw 0 0x800000 mmcpart 1;
- rootfs part 0 1 mmcpart 0;
+ rootfs part 0 1;
tiboot3.bin.raw raw 0x0 0x400 mmcpart 1;
tispl.bin.raw raw 0x400 0x1000 mmcpart 1;
u-boot.img.raw raw 0x1400 0x2000 mmcpart 1;
diff --git a/include/env/ti/k3_rproc.env b/include/env/ti/k3_rproc.env
index 87d9d76..d4f0f17 100644
--- a/include/env/ti/k3_rproc.env
+++ b/include/env/ti/k3_rproc.env
@@ -13,11 +13,15 @@
boot_rprocs_mmc=
env set rproc_id;
env set rproc_fw;
+ env set secure_suffix;
+ if test ${secure_rprocs} -eq 1; then
+ env set secure_suffix -sec;
+ fi;
for i in ${rproc_fw_binaries} ; do
if test -z "${rproc_id}" ; then
env set rproc_id $i;
else
- env set rproc_fw $i;
+ env set rproc_fw $i${secure_suffix};
run rproc_load_and_boot_one;
env set rproc_id;
env set rproc_fw;
diff --git a/include/env/ti/ti_common.env b/include/env/ti/ti_common.env
index 02b410c..c5c3642 100644
--- a/include/env/ti/ti_common.env
+++ b/include/env/ti/ti_common.env
@@ -12,6 +12,7 @@
boot_fdt=try
boot_fit=0
+secure_rprocs=0
addr_fit=0x90000000
name_fit=fitImage
update_to_fit=setenv loadaddr ${addr_fit}; setenv bootfile ${name_fit}
diff --git a/include/extension_board.h b/include/extension_board.h
index 87d404c..22e4104 100644
--- a/include/extension_board.h
+++ b/include/extension_board.h
@@ -14,7 +14,7 @@
char name[32];
char owner[32];
char version[32];
- char overlay[32];
+ char overlay[64];
char other[32];
};
diff --git a/include/fastboot.h b/include/fastboot.h
index 2ca1b90..b106d61 100644
--- a/include/fastboot.h
+++ b/include/fastboot.h
@@ -12,6 +12,8 @@
#ifndef _FASTBOOT_H_
#define _FASTBOOT_H_
+#include <linux/types.h>
+
#define FASTBOOT_VERSION "0.4"
/*
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 4b71b89..741e236 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -463,4 +463,14 @@
#ifdef CONFIG_CMD_PSTORE
void fdt_fixup_pstore(void *blob);
#endif
+
+/**
+ * fdt_kaslrseed() - create a 'kaslr-seed' node in chosen
+ *
+ * @blob: fdt blob
+ * @overwrite: do not overwrite existing non-zero node unless true
+ * Return: 0 if OK, -ve on error
+ */
+int fdt_kaslrseed(void *blob, bool overwrite);
+
#endif /* ifndef __FDT_SUPPORT_H */
diff --git a/include/fwu.h b/include/fwu.h
index eb5638f..77ec65e 100644
--- a/include/fwu.h
+++ b/include/fwu.h
@@ -8,6 +8,7 @@
#include <blk.h>
#include <efi.h>
+#include <fwu_mdata.h>
#include <mtd.h>
#include <uuid.h>
@@ -26,31 +27,70 @@
char uuidbuf[UUID_STR_LEN + 1];
};
+struct fwu_mdata_mtd_priv {
+ struct mtd_info *mtd;
+ char pri_label[50];
+ char sec_label[50];
+ u32 pri_offset;
+ u32 sec_offset;
+ struct fwu_mtd_image_info *fwu_mtd_images;
+};
+
+struct fwu_data {
+ uint32_t crc32;
+ uint32_t version;
+ uint32_t active_index;
+ uint32_t previous_active_index;
+ uint32_t metadata_size;
+ uint32_t boot_index;
+ uint32_t num_banks;
+ uint32_t num_images;
+ uint8_t bank_state[4];
+ bool trial_state;
+
+ struct fwu_mdata *fwu_mdata;
+
+ struct fwu_image_entry fwu_images[CONFIG_FWU_NUM_IMAGES_PER_BANK];
+};
+
struct fwu_mdata_ops {
/**
* read_mdata() - Populate the asked FWU metadata copy
* @dev: FWU metadata device
* @mdata: Output FWU mdata read
* @primary: If primary or secondary copy of metadata is to be read
+ * @size: Size in bytes of the metadata to be read
*
* Return: 0 if OK, -ve on error
*/
- int (*read_mdata)(struct udevice *dev, struct fwu_mdata *mdata, bool primary);
+ int (*read_mdata)(struct udevice *dev, struct fwu_mdata *mdata,
+ bool primary, uint32_t size);
/**
* write_mdata() - Write the given FWU metadata copy
* @dev: FWU metadata device
* @mdata: Copy of the FWU metadata to write
* @primary: If primary or secondary copy of metadata is to be written
+ * @size: Size in bytes of the metadata to be written
*
* Return: 0 if OK, -ve on error
*/
- int (*write_mdata)(struct udevice *dev, struct fwu_mdata *mdata, bool primary);
+ int (*write_mdata)(struct udevice *dev, struct fwu_mdata *mdata,
+ bool primary, uint32_t size);
};
-#define FWU_MDATA_VERSION 0x1
#define FWU_IMAGE_ACCEPTED 0x1
+#define FWU_BANK_INVALID (uint8_t)0xFF
+#define FWU_BANK_VALID (uint8_t)0xFE
+#define FWU_BANK_ACCEPTED (uint8_t)0xFC
+
+enum {
+ PRIMARY_PART = 1,
+ SECONDARY_PART,
+ BOTH_PARTS,
+};
+
/*
* GUID value defined in the FWU specification for identification
* of the FWU metadata partition.
@@ -80,12 +120,14 @@
/**
* fwu_read_mdata() - Wrapper around fwu_mdata_ops.read_mdata()
*/
-int fwu_read_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary);
+int fwu_read_mdata(struct udevice *dev, struct fwu_mdata *mdata,
+ bool primary, uint32_t size);
/**
* fwu_write_mdata() - Wrapper around fwu_mdata_ops.write_mdata()
*/
-int fwu_write_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary);
+int fwu_write_mdata(struct udevice *dev, struct fwu_mdata *mdata,
+ bool primary, uint32_t size);
/**
* fwu_get_mdata() - Read, verify and return the FWU metadata
@@ -280,4 +322,99 @@
*/
int fwu_mtd_get_alt_num(efi_guid_t *image_guid, u8 *alt_num, const char *mtd_dev);
+/**
+ * fwu_mdata_copies_allocate() - Allocate memory for metadata
+ * @mdata_size: Size of the metadata structure
+ *
+ * Allocate memory for storing both the copies of the FWU metadata. The
+ * copies are then used as a cache for storing FWU metadata contents.
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int fwu_mdata_copies_allocate(u32 mdata_size);
+
+/**
+ * fwu_get_dev() - Return the FWU metadata device
+ *
+ * Return the pointer to the FWU metadata device.
+ *
+ * Return: Pointer to the FWU metadata dev
+ */
+struct udevice *fwu_get_dev(void);
+
+/**
+ * fwu_get_data() - Return the version agnostic FWU structure
+ *
+ * Return the pointer to the version agnostic FWU structure.
+ *
+ * Return: Pointer to the FWU data structure
+ */
+struct fwu_data *fwu_get_data(void);
+
+/**
+ * fwu_sync_mdata() - Update given meta-data partition(s) with the copy provided
+ * @data: FWU Data structure
+ * @part: Bitmask of FWU metadata partitions to be written to
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int fwu_sync_mdata(struct fwu_mdata *mdata, int part);
+
+/**
+ * fwu_populate_mdata_image_info() - Populate the image information
+ * of the metadata
+ * @data: Version agnostic FWU metadata information
+ *
+ * Populate the image information in the FWU metadata by copying it
+ * from the version agnostic structure. This is done before the
+ * metadata gets written to the storage media.
+ *
+ * Return: None
+ */
+void fwu_populate_mdata_image_info(struct fwu_data *data);
+
+/**
+ * fwu_get_mdata_size() - Get the FWU metadata size
+ * @mdata_size: Size of the metadata structure
+ *
+ * Get the size of the FWU metadata from the structure. This is later used
+ * to allocate memory for the structure.
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int fwu_get_mdata_size(uint32_t *mdata_size);
+
+/**
+ * fwu_state_machine_updates() - Update FWU state of the platform
+ * @trial_state: Is platform transitioning into Trial State
+ * @update_index: Bank number to which images have been updated
+ *
+ * On successful completion of updates, transition the platform to
+ * either Trial State or Regular State.
+ *
+ * To transition the platform to Trial State, start the
+ * TrialStateCtr counter, followed by setting the value of bank_state
+ * field of the metadata to Valid state(applicable only in version 2
+ * of metadata).
+ *
+ * In case, the platform is to transition directly to Regular State,
+ * update the bank_state field of the metadata to Accepted
+ * state(applicable only in version 2 of metadata).
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int fwu_state_machine_updates(bool trial_state, uint32_t update_index);
+
+/**
+ * fwu_init() - FWU specific initialisations
+ *
+ * Carry out some FWU specific initialisations including allocation
+ * of memory for the metadata copies, and reading the FWU metadata
+ * copies into the allocated memory. The metadata fields are then
+ * copied into a version agnostic structure.
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int fwu_init(void);
+
#endif /* _FWU_H_ */
diff --git a/include/fwu_mdata.h b/include/fwu_mdata.h
index 56189e2..d2521f3 100644
--- a/include/fwu_mdata.h
+++ b/include/fwu_mdata.h
@@ -11,7 +11,7 @@
/**
* struct fwu_image_bank_info - firmware image information
- * @image_uuid: Guid value of the image in this bank
+ * @image_guid: Guid value of the image in this bank
* @accepted: Acceptance status of the image
* @reserved: Reserved
*
@@ -20,15 +20,15 @@
* acceptance status
*/
struct fwu_image_bank_info {
- efi_guid_t image_uuid;
+ efi_guid_t image_guid;
uint32_t accepted;
uint32_t reserved;
} __packed;
/**
* struct fwu_image_entry - information for a particular type of image
- * @image_type_uuid: Guid value for identifying the image type
- * @location_uuid: Guid of the storage volume where the image is located
+ * @image_type_guid: Guid value for identifying the image type
+ * @location_guid: Guid of the storage volume where the image is located
* @img_bank_info: Array containing properties of images
*
* This structure contains information on various types of updatable
@@ -36,12 +36,36 @@
* information per bank.
*/
struct fwu_image_entry {
- efi_guid_t image_type_uuid;
- efi_guid_t location_uuid;
+ efi_guid_t image_type_guid;
+ efi_guid_t location_guid;
struct fwu_image_bank_info img_bank_info[CONFIG_FWU_NUM_BANKS];
} __packed;
/**
+ * struct fwu_fw_store_desc - FWU updatable image information
+ * @num_banks: Number of firmware banks
+ * @num_images: Number of images per bank
+ * @img_entry_size: The size of the img_entry array
+ * @bank_info_entry_size: The size of the img_bank_info array
+ * @img_entry: Array of image entries each giving information on a image
+ *
+ * This image descriptor structure contains information on the number of
+ * updatable banks and images per bank. It also gives the total sizes of
+ * the fwu_image_entry and fwu_image_bank_info arrays. This structure is
+ * only present in version 2 of the metadata structure.
+ */
+struct fwu_fw_store_desc {
+ uint8_t num_banks;
+ uint8_t reserved;
+ uint16_t num_images;
+ uint16_t img_entry_size;
+ uint16_t bank_info_entry_size;
+
+ struct fwu_image_entry img_entry[CONFIG_FWU_NUM_IMAGES_PER_BANK];
+} __packed;
+
+#if defined(CONFIG_FWU_MDATA_V1)
+/**
* struct fwu_mdata - FWU metadata structure for multi-bank updates
* @crc32: crc32 value for the FWU metadata
* @version: FWU metadata version
@@ -65,4 +89,39 @@
struct fwu_image_entry img_entry[CONFIG_FWU_NUM_IMAGES_PER_BANK];
} __packed;
+#else /* CONFIG_FWU_MDATA_V1 */
+/**
+ * struct fwu_mdata - FWU metadata structure for multi-bank updates
+ * @crc32: crc32 value for the FWU metadata
+ * @version: FWU metadata version
+ * @active_index: Index of the bank currently used for booting images
+ * @previous_active_inde: Index of the bank used before the current bank
+ * being used for booting
+ * @metadata_size: Size of the entire metadata structure, including the
+ * image descriptors
+ * @desc_offset: The offset from the start of this structure where the
+ * image descriptor structure starts. 0 if absent
+ * @bank_state: State of each bank, valid, invalid or accepted
+ * @fw_desc: The structure describing the FWU updatable images
+ *
+ * This is the top level structure used to store all information for performing
+ * multi bank updates on the platform. This contains info on the bank being
+ * used to boot along with the information on state of individual banks.
+ */
+struct fwu_mdata {
+ uint32_t crc32;
+ uint32_t version;
+ uint32_t active_index;
+ uint32_t previous_active_index;
+ uint32_t metadata_size;
+ uint16_t desc_offset;
+ uint16_t reserved1;
+ uint8_t bank_state[4];
+ uint32_t reserved2;
+
+ // struct fwu_fw_store_desc fw_desc;
+} __packed;
+
+#endif /* CONFIG_FWU_MDATA_V1 */
+
#endif /* _FWU_MDATA_H_ */
diff --git a/include/image.h b/include/image.h
index acffd17..9daaee1 100644
--- a/include/image.h
+++ b/include/image.h
@@ -100,6 +100,7 @@
IH_OS_TEE, /* Trusted Execution Environment */
IH_OS_OPENSBI, /* RISC-V OpenSBI */
IH_OS_EFI, /* EFI Firmware (e.g. GRUB2) */
+ IH_OS_ELF, /* ELF Image (e.g. seL4) */
IH_OS_COUNT,
};
@@ -1971,6 +1972,13 @@
ulong get_abootimg_addr(void);
/**
+ * get_ainit_bootimg_addr() - Get Android init boot image address
+ *
+ * Return: Android init boot image address
+ */
+ulong get_ainit_bootimg_addr(void);
+
+/**
* get_avendor_bootimg_addr() - Get Android vendor boot image address
*
* Return: Android vendor boot image address
diff --git a/include/k3-clk.h b/include/k3-clk.h
index 7bc42ec..855d31c 100644
--- a/include/k3-clk.h
+++ b/include/k3-clk.h
@@ -178,6 +178,7 @@
extern const struct ti_k3_clk_platdata am62ax_clk_platdata;
extern const struct ti_k3_clk_platdata j784s4_clk_platdata;
extern const struct ti_k3_clk_platdata am62px_clk_platdata;
+extern const struct ti_k3_clk_platdata j722s_clk_platdata;
struct clk *clk_register_ti_pll(const char *name, const char *parent_name,
void __iomem *reg);
diff --git a/include/k3-dev.h b/include/k3-dev.h
index 0c5ae9a..23b3167 100644
--- a/include/k3-dev.h
+++ b/include/k3-dev.h
@@ -82,6 +82,7 @@
extern const struct ti_k3_pd_platdata am62ax_pd_platdata;
extern const struct ti_k3_pd_platdata j784s4_pd_platdata;
extern const struct ti_k3_pd_platdata am62px_pd_platdata;
+extern const struct ti_k3_pd_platdata j722s_pd_platdata;
u8 ti_pd_state(struct ti_pd *pd);
u8 lpsc_get_state(struct ti_lpsc *lpsc);
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index b8acacd..59f9c24 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -74,6 +74,7 @@
#define to_clk_mux(_clk) container_of(_clk, struct clk_mux, clk)
extern const struct clk_ops clk_mux_ops;
u8 clk_mux_get_parent(struct clk *clk);
+int clk_mux_fetch_parent_index(struct clk *clk, struct clk *parent);
/**
* clk_mux_index_to_val() - Convert the parent index to the register value
diff --git a/include/linux/usb/gadget.h b/include/linux/usb/gadget.h
index 36572be..cf21616 100644
--- a/include/linux/usb/gadget.h
+++ b/include/linux/usb/gadget.h
@@ -971,6 +971,14 @@
extern int dm_usb_gadget_handle_interrupts(struct udevice *);
/**
+ * struct usb_gadget_generic_ops - The functions that a gadget driver must implement.
+ * @handle_interrupts: Handle UDC interrupts.
+ */
+struct usb_gadget_generic_ops {
+ int (*handle_interrupts)(struct udevice *udevice);
+};
+
+/**
* udc_device_get_by_index() - Get UDC udevice by index
* @index: UDC device index
* @udev: UDC udevice matching the index (if found)
diff --git a/include/pci_ids.h b/include/pci_ids.h
index f1886c3..6f09544 100644
--- a/include/pci_ids.h
+++ b/include/pci_ids.h
@@ -2701,6 +2701,11 @@
#define PCI_DEVICE_ID_INTEL_82441 0x1237
#define PCI_DEVICE_ID_INTEL_82380FB 0x124b
#define PCI_DEVICE_ID_INTEL_82439 0x1250
+#define PCI_DEVICE_ID_INTEL_I226_LM 0x125b
+#define PCI_DEVICE_ID_INTEL_I226_V 0x125c
+#define PCI_DEVICE_ID_INTEL_I226_IT 0x125d
+#define PCI_DEVICE_ID_INTEL_I221_V 0x125e
+#define PCI_DEVICE_ID_INTEL_I226_UNPROGRAMMED 0x125f
#define PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED 0x1531
#define PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED 0x1532
#define PCI_DEVICE_ID_INTEL_I210_COPPER 0x1533
@@ -2710,7 +2715,7 @@
#define PCI_DEVICE_ID_INTEL_I211_COPPER 0x1539
#define PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS 0x157b
#define PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS 0x157c
-#define PCI_DEVICE_ID_INTEL_I225_UNPROGRAMMED 0x15dF
+#define PCI_DEVICE_ID_INTEL_I225_UNPROGRAMMED 0x15fd
#define PCI_DEVICE_ID_INTEL_I225_IT 0x0d9f
#define PCI_DEVICE_ID_INTEL_80960_RP 0x1960
#define PCI_DEVICE_ID_INTEL_82840_HB 0x1a21
@@ -2930,6 +2935,7 @@
#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_ADDR_REV2 0x2db1
#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2 0x2db2
#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2 0x2db3
+#define PCI_DEVICE_ID_INTEL_I226_K 0x3102
#define PCI_DEVICE_ID_INTEL_82855PM_HB 0x3340
#define PCI_DEVICE_ID_INTEL_IOAT_TBG4 0x3429
#define PCI_DEVICE_ID_INTEL_IOAT_TBG5 0x342a
@@ -3001,6 +3007,7 @@
#define PCI_DEVICE_ID_INTEL_UNC_R3QPI1 0x3c45
#define PCI_DEVICE_ID_INTEL_JAKETOWN_UBOX 0x3ce0
#define PCI_DEVICE_ID_INTEL_IOAT_SNB 0x402f
+#define PCI_DEVICE_ID_INTEL_I226_LMVP 0x5503
#define PCI_DEVICE_ID_INTEL_5100_16 0x65f0
#define PCI_DEVICE_ID_INTEL_5100_19 0x65f3
#define PCI_DEVICE_ID_INTEL_5100_21 0x65f5
diff --git a/include/phy.h b/include/phy.h
index 90b7e36..3678503 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -58,11 +58,6 @@
#define PHY_10G_FEATURES (PHY_GBIT_FEATURES | \
SUPPORTED_10000baseT_Full)
-#ifndef PHY_ANEG_TIMEOUT
-#define PHY_ANEG_TIMEOUT 4000
-#endif
-
-
struct phy_device;
#define MDIO_NAME_LEN 32
diff --git a/include/spl.h b/include/spl.h
index 043875f..5dfdf77 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -817,6 +817,14 @@
int spl_init(void);
/*
+ * spl_soc_init() - Do architecture-specific init in SPL
+ *
+ * If SPL_SOC_INIT is enabled, this is called from board_init_r() before
+ * jumping to the next phase.
+ */
+void spl_soc_init(void);
+
+/*
* spl_board_init() - Do board-specific init in SPL
*
* If xPL_BOARD_INIT is enabled, this is called from board_init_r() before
diff --git a/include/stdio.h b/include/stdio.h
index 3241e2d..7b999a5 100644
--- a/include/stdio.h
+++ b/include/stdio.h
@@ -46,6 +46,23 @@
}
#endif
+/**
+ * Format a string and place it in a buffer
+ *
+ * @buf: The buffer to place the result into
+ * @size: The size of the buffer, including the trailing null space
+ * @fmt: The format string to use
+ * @...: Arguments for the format string
+ * Return: the number of characters which would be
+ * generated for the given input, excluding the trailing null,
+ * as per ISO C99. If the return is greater than or equal to
+ * @size, the resulting string is truncated.
+ *
+ * See the vsprintf() documentation for format string extensions over C99.
+ */
+int snprintf(char *buf, size_t size, const char *fmt, ...)
+ __attribute__ ((format (__printf__, 3, 4)));
+
/*
* FILE based functions (can only be used AFTER relocation!)
*/
diff --git a/include/sysinfo.h b/include/sysinfo.h
index 524c7d6..8a77ef4 100644
--- a/include/sysinfo.h
+++ b/include/sysinfo.h
@@ -43,8 +43,17 @@
SYSINFO_ID_NONE,
/* For SMBIOS tables */
+ SYSINFO_ID_SMBIOS_SYSTEM_MANUFACTURER,
+ SYSINFO_ID_SMBIOS_SYSTEM_PRODUCT,
SYSINFO_ID_SMBIOS_SYSTEM_VERSION,
+ SYSINFO_ID_SMBIOS_SYSTEM_SERIAL,
+ SYSINFO_ID_SMBIOS_SYSTEM_SKU,
+ SYSINFO_ID_SMBIOS_SYSTEM_FAMILY,
+ SYSINFO_ID_SMBIOS_BASEBOARD_MANUFACTURER,
+ SYSINFO_ID_SMBIOS_BASEBOARD_PRODUCT,
SYSINFO_ID_SMBIOS_BASEBOARD_VERSION,
+ SYSINFO_ID_SMBIOS_BASEBOARD_SERIAL,
+ SYSINFO_ID_SMBIOS_BASEBOARD_ASSET_TAG,
/* For show_board_info() */
SYSINFO_ID_BOARD_MODEL,
diff --git a/include/tpm-v2.h b/include/tpm-v2.h
index 33dd103..4fd19c5 100644
--- a/include/tpm-v2.h
+++ b/include/tpm-v2.h
@@ -55,59 +55,6 @@
#define TPM2_PT_MAX_COMMAND_SIZE (u32)(TPM2_PT_FIXED + 30)
#define TPM2_PT_MAX_RESPONSE_SIZE (u32)(TPM2_PT_FIXED + 31)
-/*
- * event types, cf.
- * "TCG Server Management Domain Firmware Profile Specification",
- * rev 1.00, 2020-05-01
- */
-#define EV_POST_CODE ((u32)0x00000001)
-#define EV_NO_ACTION ((u32)0x00000003)
-#define EV_SEPARATOR ((u32)0x00000004)
-#define EV_ACTION ((u32)0x00000005)
-#define EV_TAG ((u32)0x00000006)
-#define EV_S_CRTM_CONTENTS ((u32)0x00000007)
-#define EV_S_CRTM_VERSION ((u32)0x00000008)
-#define EV_CPU_MICROCODE ((u32)0x00000009)
-#define EV_PLATFORM_CONFIG_FLAGS ((u32)0x0000000A)
-#define EV_TABLE_OF_DEVICES ((u32)0x0000000B)
-#define EV_COMPACT_HASH ((u32)0x0000000C)
-
-/*
- * event types, cf.
- * "TCG PC Client Platform Firmware Profile Specification", Family "2.0"
- * Level 00 Version 1.05 Revision 23, May 7, 2021
- */
-#define EV_EFI_EVENT_BASE ((u32)0x80000000)
-#define EV_EFI_VARIABLE_DRIVER_CONFIG ((u32)0x80000001)
-#define EV_EFI_VARIABLE_BOOT ((u32)0x80000002)
-#define EV_EFI_BOOT_SERVICES_APPLICATION ((u32)0x80000003)
-#define EV_EFI_BOOT_SERVICES_DRIVER ((u32)0x80000004)
-#define EV_EFI_RUNTIME_SERVICES_DRIVER ((u32)0x80000005)
-#define EV_EFI_GPT_EVENT ((u32)0x80000006)
-#define EV_EFI_ACTION ((u32)0x80000007)
-#define EV_EFI_PLATFORM_FIRMWARE_BLOB ((u32)0x80000008)
-#define EV_EFI_HANDOFF_TABLES ((u32)0x80000009)
-#define EV_EFI_PLATFORM_FIRMWARE_BLOB2 ((u32)0x8000000A)
-#define EV_EFI_HANDOFF_TABLES2 ((u32)0x8000000B)
-#define EV_EFI_VARIABLE_BOOT2 ((u32)0x8000000C)
-#define EV_EFI_HCRTM_EVENT ((u32)0x80000010)
-#define EV_EFI_VARIABLE_AUTHORITY ((u32)0x800000E0)
-#define EV_EFI_SPDM_FIRMWARE_BLOB ((u32)0x800000E1)
-#define EV_EFI_SPDM_FIRMWARE_CONFIG ((u32)0x800000E2)
-
-#define EFI_CALLING_EFI_APPLICATION \
- "Calling EFI Application from Boot Option"
-#define EFI_RETURNING_FROM_EFI_APPLICATION \
- "Returning from EFI Application from Boot Option"
-#define EFI_EXIT_BOOT_SERVICES_INVOCATION \
- "Exit Boot Services Invocation"
-#define EFI_EXIT_BOOT_SERVICES_FAILED \
- "Exit Boot Services Returned with Failure"
-#define EFI_EXIT_BOOT_SERVICES_SUCCEEDED \
- "Exit Boot Services Returned with Success"
-#define EFI_DTB_EVENT_STRING \
- "DTB DATA"
-
/* TPMS_TAGGED_PROPERTY Structure */
struct tpms_tagged_property {
u32 property;
@@ -150,23 +97,6 @@
} __packed;
/**
- * SHA1 Event Log Entry Format
- *
- * @pcr_index: PCRIndex event extended to
- * @event_type: Type of event (see EFI specs)
- * @digest: Value extended into PCR index
- * @event_size: Size of event
- * @event: Event data
- */
-struct tcg_pcr_event {
- u32 pcr_index;
- u32 event_type;
- u8 digest[TPM2_SHA1_DIGEST_SIZE];
- u32 event_size;
- u8 event[];
-} __packed;
-
-/**
* Definition of TPMU_HA Union
*/
union tpmu_ha {
@@ -200,67 +130,6 @@
} __packed;
/**
- * Crypto Agile Log Entry Format
- *
- * @pcr_index: PCRIndex event extended to
- * @event_type: Type of event
- * @digests: List of digestsextended to PCR index
- * @event_size: Size of the event data
- * @event: Event data
- */
-struct tcg_pcr_event2 {
- u32 pcr_index;
- u32 event_type;
- struct tpml_digest_values digests;
- u32 event_size;
- u8 event[];
-} __packed;
-
-/**
- * struct TCG_EfiSpecIdEventAlgorithmSize - hashing algorithm information
- *
- * @algorithm_id: algorithm defined in enum tpm2_algorithms
- * @digest_size: size of the algorithm
- */
-struct tcg_efi_spec_id_event_algorithm_size {
- u16 algorithm_id;
- u16 digest_size;
-} __packed;
-
-#define TCG_EFI_SPEC_ID_EVENT_SIGNATURE_03 "Spec ID Event03"
-#define TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MAJOR_TPM2 2
-#define TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MINOR_TPM2 0
-#define TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_ERRATA_TPM2 2
-
-/**
- * struct TCG_EfiSpecIDEventStruct - content of the event log header
- *
- * @signature: signature, set to Spec ID Event03
- * @platform_class: class defined in TCG ACPI Specification
- * Client Common Header.
- * @spec_version_minor: minor version
- * @spec_version_major: major version
- * @spec_version_errata: major version
- * @uintn_size: size of the efi_uintn_t fields used in various
- * data structures used in this specification.
- * 0x01 indicates u32 and 0x02 indicates u64
- * @number_of_algorithms: hashing algorithms used in this event log
- * @digest_sizes: array of number_of_algorithms pairs
- * 1st member defines the algorithm id
- * 2nd member defines the algorithm size
- */
-struct tcg_efi_spec_id_event {
- u8 signature[16];
- u32 platform_class;
- u8 spec_version_minor;
- u8 spec_version_major;
- u8 spec_errata;
- u8 uintn_size;
- u32 number_of_algorithms;
- struct tcg_efi_spec_id_event_algorithm_size digest_sizes[];
-} __packed;
-
-/**
* TPM2 Structure Tags for command/response buffers.
*
* @TPM2_ST_NO_SESSIONS: the command does not need an authentication.
@@ -386,25 +255,62 @@
TPM2_ALG_SM3_256 = 0x12,
};
-extern const enum tpm2_algorithms tpm2_supported_algorithms[4];
+/**
+ * struct digest_info - details of supported digests
+ *
+ * @hash_name: hash name
+ * @hash_alg: hash algorithm id
+ * @hash_mask: hash registry mask
+ * @hash_len: hash digest length
+ */
+struct digest_info {
+ const char *hash_name;
+ u16 hash_alg;
+ u32 hash_mask;
+ u16 hash_len;
+};
-static inline u16 tpm2_algorithm_to_len(enum tpm2_algorithms a)
-{
- switch (a) {
- case TPM2_ALG_SHA1:
- return TPM2_SHA1_DIGEST_SIZE;
- case TPM2_ALG_SHA256:
- return TPM2_SHA256_DIGEST_SIZE;
- case TPM2_ALG_SHA384:
- return TPM2_SHA384_DIGEST_SIZE;
- case TPM2_ALG_SHA512:
- return TPM2_SHA512_DIGEST_SIZE;
- default:
- return 0;
- }
-}
+/* Algorithm Registry */
+#define TCG2_BOOT_HASH_ALG_SHA1 0x00000001
+#define TCG2_BOOT_HASH_ALG_SHA256 0x00000002
+#define TCG2_BOOT_HASH_ALG_SHA384 0x00000004
+#define TCG2_BOOT_HASH_ALG_SHA512 0x00000008
+#define TCG2_BOOT_HASH_ALG_SM3_256 0x00000010
-#define tpm2_algorithm_to_mask(a) (1 << (a))
+static const struct digest_info hash_algo_list[] = {
+#if IS_ENABLED(CONFIG_SHA1)
+ {
+ "sha1",
+ TPM2_ALG_SHA1,
+ TCG2_BOOT_HASH_ALG_SHA1,
+ TPM2_SHA1_DIGEST_SIZE,
+ },
+#endif
+#if IS_ENABLED(CONFIG_SHA256)
+ {
+ "sha256",
+ TPM2_ALG_SHA256,
+ TCG2_BOOT_HASH_ALG_SHA256,
+ TPM2_SHA256_DIGEST_SIZE,
+ },
+#endif
+#if IS_ENABLED(CONFIG_SHA384)
+ {
+ "sha384",
+ TPM2_ALG_SHA384,
+ TCG2_BOOT_HASH_ALG_SHA384,
+ TPM2_SHA384_DIGEST_SIZE,
+ },
+#endif
+#if IS_ENABLED(CONFIG_SHA512)
+ {
+ "sha512",
+ TPM2_ALG_SHA512,
+ TCG2_BOOT_HASH_ALG_SHA512,
+ TPM2_SHA512_DIGEST_SIZE,
+ },
+#endif
+};
/* NV index attributes */
enum tpm_index_attrs {
@@ -486,188 +392,6 @@
};
/**
- * struct tcg2_event_log - Container for managing the platform event log
- *
- * @log: Address of the log
- * @log_position: Current entry position
- * @log_size: Log space available
- * @found: Boolean indicating if an existing log was discovered
- */
-struct tcg2_event_log {
- u8 *log;
- u32 log_position;
- u32 log_size;
- bool found;
-};
-
-/**
- * Create a list of digests of the supported PCR banks for a given input data
- *
- * @dev TPM device
- * @input Data
- * @length Length of the data to calculate the digest
- * @digest_list List of digests to fill in
- *
- * Return: zero on success, negative errno otherwise
- */
-int tcg2_create_digest(struct udevice *dev, const u8 *input, u32 length,
- struct tpml_digest_values *digest_list);
-
-/**
- * Get the event size of the specified digests
- *
- * @digest_list List of digests for the event
- *
- * Return: Size in bytes of the event
- */
-u32 tcg2_event_get_size(struct tpml_digest_values *digest_list);
-
-/**
- * tcg2_get_active_pcr_banks
- *
- * @dev TPM device
- * @active_pcr_banks Bitmask of PCR algorithms supported
- *
- * Return: zero on success, negative errno otherwise
- */
-int tcg2_get_active_pcr_banks(struct udevice *dev, u32 *active_pcr_banks);
-
-/**
- * tcg2_log_append - Append an event to an event log
- *
- * @pcr_index Index of the PCR
- * @event_type Type of event
- * @digest_list List of digests to add
- * @size Size of event
- * @event Event data
- * @log Log buffer to append the event to
- */
-void tcg2_log_append(u32 pcr_index, u32 event_type,
- struct tpml_digest_values *digest_list, u32 size,
- const u8 *event, u8 *log);
-
-/**
- * Extend the PCR with specified digests
- *
- * @dev TPM device
- * @pcr_index Index of the PCR
- * @digest_list List of digests to extend
- *
- * Return: zero on success, negative errno otherwise
- */
-int tcg2_pcr_extend(struct udevice *dev, u32 pcr_index,
- struct tpml_digest_values *digest_list);
-
-/**
- * Read the PCR into a list of digests
- *
- * @dev TPM device
- * @pcr_index Index of the PCR
- * @digest_list List of digests to extend
- *
- * Return: zero on success, negative errno otherwise
- */
-int tcg2_pcr_read(struct udevice *dev, u32 pcr_index,
- struct tpml_digest_values *digest_list);
-
-/**
- * Measure data into the TPM PCRs and the platform event log.
- *
- * @dev TPM device
- * @log Platform event log
- * @pcr_index Index of the PCR
- * @size Size of the data or 0 for event only
- * @data Pointer to the data or NULL for event only
- * @event_type Event log type
- * @event_size Size of the event
- * @event Pointer to the event
- *
- * Return: zero on success, negative errno otherwise
- */
-int tcg2_measure_data(struct udevice *dev, struct tcg2_event_log *elog,
- u32 pcr_index, u32 size, const u8 *data, u32 event_type,
- u32 event_size, const u8 *event);
-
-#define tcg2_measure_event(dev, elog, pcr_index, event_type, size, event) \
- tcg2_measure_data(dev, elog, pcr_index, 0, NULL, event_type, size, \
- event)
-
-/**
- * Prepare the event log buffer. This function tries to discover an existing
- * event log in memory from a previous bootloader stage. If such a log exists
- * and the PCRs are not extended, the log is "replayed" to extend the PCRs.
- * If no log is discovered, create the log header.
- *
- * @dev TPM device
- * @elog Platform event log. The log pointer and log_size
- * members must be initialized to either 0 or to a valid
- * memory region, in which case any existing log
- * discovered will be copied to the specified memory
- * region.
- * @ignore_existing_log Boolean to indicate whether or not to ignore an
- * existing platform log in memory
- *
- * Return: zero on success, negative errno otherwise
- */
-int tcg2_log_prepare_buffer(struct udevice *dev, struct tcg2_event_log *elog,
- bool ignore_existing_log);
-
-/**
- * Begin measurements.
- *
- * @dev TPM device
- * @elog Platform event log. The log pointer and log_size
- * members must be initialized to either 0 or to a valid
- * memory region, in which case any existing log
- * discovered will be copied to the specified memory
- * region.
- * @ignore_existing_log Boolean to indicate whether or not to ignore an
- * existing platform log in memory
- *
- * Return: zero on success, negative errno otherwise
- */
-int tcg2_measurement_init(struct udevice **dev, struct tcg2_event_log *elog,
- bool ignore_existing_log);
-
-/**
- * Stop measurements and record separator events.
- *
- * @dev TPM device
- * @elog Platform event log
- * @error Boolean to indicate whether an error ocurred or not
- */
-void tcg2_measurement_term(struct udevice *dev, struct tcg2_event_log *elog,
- bool error);
-
-/**
- * Get the platform event log address and size.
- *
- * @dev TPM device
- * @addr Address of the log
- * @size Size of the log
- *
- * Return: zero on success, negative errno otherwise
- */
-int tcg2_platform_get_log(struct udevice *dev, void **addr, u32 *size);
-
-/**
- * Get the first TPM2 device found.
- *
- * @dev TPM device
- *
- * Return: zero on success, negative errno otherwise
- */
-int tcg2_platform_get_tpm2(struct udevice **dev);
-
-/**
- * Platform-specific function for handling TPM startup errors
- *
- * @dev TPM device
- * @rc The TPM response code
- */
-void tcg2_platform_startup_error(struct udevice *dev, int rc);
-
-/**
* Issue a TPM2_Startup command.
*
* @dev TPM device
@@ -790,14 +514,11 @@
* tpm2_get_pcr_info() - get the supported, active PCRs and number of banks
*
* @dev: TPM device
- * @supported_pcr: bitmask with the algorithms supported
- * @active_pcr: bitmask with the active algorithms
- * @pcr_banks: number of PCR banks
+ * @pcrs: struct tpml_pcr_selection of available PCRs
*
* @return 0 on success, code of operation or negative errno on failure
*/
-int tpm2_get_pcr_info(struct udevice *dev, u32 *supported_pcr, u32 *active_pcr,
- u32 *pcr_banks);
+int tpm2_get_pcr_info(struct udevice *dev, struct tpml_pcr_selection *pcrs);
/**
* Issue a TPM2_DictionaryAttackLockReset command.
@@ -965,4 +686,66 @@
*/
u32 tpm2_auto_start(struct udevice *dev);
+/**
+ * tpm2_name_to_algorithm() - Return an algorithm id given a supported
+ * algorithm name
+ *
+ * @name: algorithm name
+ * Return: enum tpm2_algorithms or -EINVAL
+ */
+enum tpm2_algorithms tpm2_name_to_algorithm(const char *name);
+
+/**
+ * tpm2_algorithm_name() - Return an algorithm name string for a
+ * supported algorithm id
+ *
+ * @algorithm_id: algorithm defined in enum tpm2_algorithms
+ * Return: algorithm name string or ""
+ */
+const char *tpm2_algorithm_name(enum tpm2_algorithms);
+
+/**
+ * tpm2_algorithm_to_len() - Return an algorithm length for supported algorithm id
+ *
+ * @algorithm_id: algorithm defined in enum tpm2_algorithms
+ * Return: len or 0 if not supported
+ */
+u16 tpm2_algorithm_to_len(enum tpm2_algorithms algo);
+
+/*
+ * When measured boot is enabled via EFI or bootX commands all the algorithms
+ * above are selected by our Kconfigs. Due to U-Boots nature of being small there
+ * are cases where we need some functionality from the TPM -- e.g storage or RNG
+ * but we don't want to support measurements.
+ *
+ * The choice of hash algorithms are determined by the platform and the TPM
+ * configuration. Failing to cap a PCR in a bank which the platform left
+ * active is a security vulnerability. It permits the unsealing of secrets
+ * if an attacker can replay a good set of measurements into an unused bank.
+ *
+ * On top of that a previous stage bootloader (e.g TF-A), migh pass an eventlog
+ * since it doesn't have a TPM driver, which U-Boot needs to replace. The algorit h
+ * choice is a compile time option in that case and we need to make sure we conform.
+ *
+ * Add a variable here that sums the supported algorithms U-Boot was compiled
+ * with so we can refuse to do measurements if we don't support all of them
+ */
+
+/**
+ * tpm2_allow_extend() - Check if extending PCRs is allowed and safe
+ *
+ * @dev: TPM device
+ * Return: true if allowed
+ */
+bool tpm2_allow_extend(struct udevice *dev);
+
+/**
+ * tpm2_is_active_pcr() - check the pcr_select. If at least one of the PCRs
+ * supports the algorithm add it on the active ones
+ *
+ * @selection: PCR selection structure
+ * Return: True if the algorithm is active
+ */
+bool tpm2_is_active_pcr(struct tpms_pcr_selection *selection);
+
#endif /* __TPM_V2_H */
diff --git a/include/tpm_tcg2.h b/include/tpm_tcg2.h
new file mode 100644
index 0000000..6519004
--- /dev/null
+++ b/include/tpm_tcg2.h
@@ -0,0 +1,348 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Defines APIs and structures that adhere to
+ * https://trustedcomputinggroup.org/resource/pc-client-specific-platform-firmware-profile-specification/
+ * https://trustedcomputinggroup.org/resource/tcg-efi-protocol-specification/
+ *
+ * Copyright (c) 2020 Linaro Limited
+ */
+
+#ifndef __TPM_TCG_V2_H
+#define __TPM_TCG_V2_H
+
+#include <tpm-v2.h>
+
+/*
+ * event types, cf.
+ * "TCG Server Management Domain Firmware Profile Specification",
+ * rev 1.00, 2020-05-01
+ */
+#define EV_POST_CODE ((u32)0x00000001)
+#define EV_NO_ACTION ((u32)0x00000003)
+#define EV_SEPARATOR ((u32)0x00000004)
+#define EV_ACTION ((u32)0x00000005)
+#define EV_TAG ((u32)0x00000006)
+#define EV_S_CRTM_CONTENTS ((u32)0x00000007)
+#define EV_S_CRTM_VERSION ((u32)0x00000008)
+#define EV_CPU_MICROCODE ((u32)0x00000009)
+#define EV_PLATFORM_CONFIG_FLAGS ((u32)0x0000000A)
+#define EV_TABLE_OF_DEVICES ((u32)0x0000000B)
+#define EV_COMPACT_HASH ((u32)0x0000000C)
+
+/*
+ * event types, cf.
+ * "TCG PC Client Platform Firmware Profile Specification", Family "2.0"
+ * Level 00 Version 1.05 Revision 23, May 7, 2021
+ */
+#define EV_EFI_EVENT_BASE ((u32)0x80000000)
+#define EV_EFI_VARIABLE_DRIVER_CONFIG ((u32)0x80000001)
+#define EV_EFI_VARIABLE_BOOT ((u32)0x80000002)
+#define EV_EFI_BOOT_SERVICES_APPLICATION ((u32)0x80000003)
+#define EV_EFI_BOOT_SERVICES_DRIVER ((u32)0x80000004)
+#define EV_EFI_RUNTIME_SERVICES_DRIVER ((u32)0x80000005)
+#define EV_EFI_GPT_EVENT ((u32)0x80000006)
+#define EV_EFI_ACTION ((u32)0x80000007)
+#define EV_EFI_PLATFORM_FIRMWARE_BLOB ((u32)0x80000008)
+#define EV_EFI_HANDOFF_TABLES ((u32)0x80000009)
+#define EV_EFI_PLATFORM_FIRMWARE_BLOB2 ((u32)0x8000000A)
+#define EV_EFI_HANDOFF_TABLES2 ((u32)0x8000000B)
+#define EV_EFI_VARIABLE_BOOT2 ((u32)0x8000000C)
+#define EV_EFI_HCRTM_EVENT ((u32)0x80000010)
+#define EV_EFI_VARIABLE_AUTHORITY ((u32)0x800000E0)
+#define EV_EFI_SPDM_FIRMWARE_BLOB ((u32)0x800000E1)
+#define EV_EFI_SPDM_FIRMWARE_CONFIG ((u32)0x800000E2)
+
+#define EFI_CALLING_EFI_APPLICATION \
+ "Calling EFI Application from Boot Option"
+#define EFI_RETURNING_FROM_EFI_APPLICATION \
+ "Returning from EFI Application from Boot Option"
+#define EFI_EXIT_BOOT_SERVICES_INVOCATION \
+ "Exit Boot Services Invocation"
+#define EFI_EXIT_BOOT_SERVICES_FAILED \
+ "Exit Boot Services Returned with Failure"
+#define EFI_EXIT_BOOT_SERVICES_SUCCEEDED \
+ "Exit Boot Services Returned with Success"
+#define EFI_DTB_EVENT_STRING \
+ "DTB DATA"
+
+/**
+ * struct TCG_EfiSpecIdEventAlgorithmSize - hashing algorithm information
+ *
+ * @algorithm_id: algorithm defined in enum tpm2_algorithms
+ * @digest_size: size of the algorithm
+ */
+struct tcg_efi_spec_id_event_algorithm_size {
+ u16 algorithm_id;
+ u16 digest_size;
+} __packed;
+
+/**
+ * SHA1 Event Log Entry Format
+ *
+ * @pcr_index: PCRIndex event extended to
+ * @event_type: Type of event (see EFI specs)
+ * @digest: Value extended into PCR index
+ * @event_size: Size of event
+ * @event: Event data
+ */
+struct tcg_pcr_event {
+ u32 pcr_index;
+ u32 event_type;
+ u8 digest[TPM2_SHA1_DIGEST_SIZE];
+ u32 event_size;
+ u8 event[];
+} __packed;
+
+/**
+ * tcg2_get_pcr_info() - get the supported, active PCRs and number of banks
+ *
+ * @dev: TPM device
+ * @supported_pcr: bitmask with the algorithms supported
+ * @active_pcr: bitmask with the active algorithms
+ * @pcr_banks: number of PCR banks
+ *
+ * @return 0 on success, code of operation or negative errno on failure
+ */
+int tcg2_get_pcr_info(struct udevice *dev, u32 *supported_pcr, u32 *active_pcr,
+ u32 *pcr_banks);
+
+/**
+ * Crypto Agile Log Entry Format
+ *
+ * @pcr_index: PCRIndex event extended to
+ * @event_type: Type of event
+ * @digests: List of digestsextended to PCR index
+ * @event_size: Size of the event data
+ * @event: Event data
+ */
+struct tcg_pcr_event2 {
+ u32 pcr_index;
+ u32 event_type;
+ struct tpml_digest_values digests;
+ u32 event_size;
+ u8 event[];
+} __packed;
+
+/**
+ * struct TCG_EfiSpecIDEventStruct - content of the event log header
+ *
+ * @signature: signature, set to Spec ID Event03
+ * @platform_class: class defined in TCG ACPI Specification
+ * Client Common Header.
+ * @spec_version_minor: minor version
+ * @spec_version_major: major version
+ * @spec_version_errata: major version
+ * @uintn_size: size of the efi_uintn_t fields used in various
+ * data structures used in this specification.
+ * 0x01 indicates u32 and 0x02 indicates u64
+ * @number_of_algorithms: hashing algorithms used in this event log
+ * @digest_sizes: array of number_of_algorithms pairs
+ * 1st member defines the algorithm id
+ * 2nd member defines the algorithm size
+ */
+struct tcg_efi_spec_id_event {
+ u8 signature[16];
+ u32 platform_class;
+ u8 spec_version_minor;
+ u8 spec_version_major;
+ u8 spec_errata;
+ u8 uintn_size;
+ u32 number_of_algorithms;
+ struct tcg_efi_spec_id_event_algorithm_size digest_sizes[];
+} __packed;
+
+#define TCG_EFI_SPEC_ID_EVENT_SIGNATURE_03 "Spec ID Event03"
+#define TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MAJOR_TPM2 2
+#define TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MINOR_TPM2 0
+#define TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_ERRATA_TPM2 2
+/**
+ * struct tcg2_event_log - Container for managing the platform event log
+ *
+ * @log: Address of the log
+ * @log_position: Current entry position
+ * @log_size: Log space available
+ * @found: Boolean indicating if an existing log was discovered
+ */
+struct tcg2_event_log {
+ u8 *log;
+ u32 log_position;
+ u32 log_size;
+ bool found;
+};
+
+/**
+ * Create a list of digests of the supported PCR banks for a given input data
+ *
+ * @dev TPM device
+ * @input Data
+ * @length Length of the data to calculate the digest
+ * @digest_list List of digests to fill in
+ *
+ * Return: zero on success, negative errno otherwise
+ */
+int tcg2_create_digest(struct udevice *dev, const u8 *input, u32 length,
+ struct tpml_digest_values *digest_list);
+
+/**
+ * Get the event size of the specified digests
+ *
+ * @digest_list List of digests for the event
+ *
+ * Return: Size in bytes of the event
+ */
+u32 tcg2_event_get_size(struct tpml_digest_values *digest_list);
+
+/**
+ * tcg2_get_active_pcr_banks
+ *
+ * @dev TPM device
+ * @active_pcr_banks Bitmask of PCR algorithms supported
+ *
+ * Return: zero on success, negative errno otherwise
+ */
+int tcg2_get_active_pcr_banks(struct udevice *dev, u32 *active_pcr_banks);
+
+/**
+ * tcg2_log_append - Append an event to an event log
+ *
+ * @pcr_index Index of the PCR
+ * @event_type Type of event
+ * @digest_list List of digests to add
+ * @size Size of event
+ * @event Event data
+ * @log Log buffer to append the event to
+ */
+void tcg2_log_append(u32 pcr_index, u32 event_type,
+ struct tpml_digest_values *digest_list, u32 size,
+ const u8 *event, u8 *log);
+
+/**
+ * Extend the PCR with specified digests
+ *
+ * @dev TPM device
+ * @pcr_index Index of the PCR
+ * @digest_list List of digests to extend
+ *
+ * Return: zero on success, negative errno otherwise
+ */
+int tcg2_pcr_extend(struct udevice *dev, u32 pcr_index,
+ struct tpml_digest_values *digest_list);
+
+/**
+ * Read the PCR into a list of digests
+ *
+ * @dev TPM device
+ * @pcr_index Index of the PCR
+ * @digest_list List of digests to extend
+ *
+ * Return: zero on success, negative errno otherwise
+ */
+int tcg2_pcr_read(struct udevice *dev, u32 pcr_index,
+ struct tpml_digest_values *digest_list);
+
+/**
+ * Measure data into the TPM PCRs and the platform event log.
+ *
+ * @dev TPM device
+ * @log Platform event log
+ * @pcr_index Index of the PCR
+ * @size Size of the data or 0 for event only
+ * @data Pointer to the data or NULL for event only
+ * @event_type Event log type
+ * @event_size Size of the event
+ * @event Pointer to the event
+ *
+ * Return: zero on success, negative errno otherwise
+ */
+int tcg2_measure_data(struct udevice *dev, struct tcg2_event_log *elog,
+ u32 pcr_index, u32 size, const u8 *data, u32 event_type,
+ u32 event_size, const u8 *event);
+
+#define tcg2_measure_event(dev, elog, pcr_index, event_type, size, event) \
+ tcg2_measure_data(dev, elog, pcr_index, 0, NULL, event_type, size, \
+ event)
+
+/**
+ * Prepare the event log buffer. This function tries to discover an existing
+ * event log in memory from a previous bootloader stage. If such a log exists
+ * and the PCRs are not extended, the log is "replayed" to extend the PCRs.
+ * If no log is discovered, create the log header.
+ *
+ * @dev TPM device
+ * @elog Platform event log. The log pointer and log_size
+ * members must be initialized to either 0 or to a valid
+ * memory region, in which case any existing log
+ * discovered will be copied to the specified memory
+ * region.
+ * @ignore_existing_log Boolean to indicate whether or not to ignore an
+ * existing platform log in memory
+ *
+ * Return: zero on success, negative errno otherwise
+ */
+int tcg2_log_prepare_buffer(struct udevice *dev, struct tcg2_event_log *elog,
+ bool ignore_existing_log);
+
+/**
+ * Begin measurements.
+ *
+ * @dev TPM device
+ * @elog Platform event log. The log pointer and log_size
+ * members must be initialized to either 0 or to a valid
+ * memory region, in which case any existing log
+ * discovered will be copied to the specified memory
+ * region.
+ * @ignore_existing_log Boolean to indicate whether or not to ignore an
+ * existing platform log in memory
+ *
+ * Return: zero on success, negative errno otherwise
+ */
+int tcg2_measurement_init(struct udevice **dev, struct tcg2_event_log *elog,
+ bool ignore_existing_log);
+
+/**
+ * Stop measurements and record separator events.
+ *
+ * @dev TPM device
+ * @elog Platform event log
+ * @error Boolean to indicate whether an error ocurred or not
+ */
+void tcg2_measurement_term(struct udevice *dev, struct tcg2_event_log *elog,
+ bool error);
+
+/**
+ * Get the platform event log address and size.
+ *
+ * @dev TPM device
+ * @addr Address of the log
+ * @size Size of the log
+ *
+ * Return: zero on success, negative errno otherwise
+ */
+int tcg2_platform_get_log(struct udevice *dev, void **addr, u32 *size);
+
+/**
+ * Get the first TPM2 device found.
+ *
+ * @dev TPM device
+ *
+ * Return: zero on success, negative errno otherwise
+ */
+int tcg2_platform_get_tpm2(struct udevice **dev);
+
+/**
+ * Platform-specific function for handling TPM startup errors
+ *
+ * @dev TPM device
+ * @rc The TPM response code
+ */
+void tcg2_platform_startup_error(struct udevice *dev, int rc);
+
+/**
+ * tcg2_algorithm_to_mask() - Get a TCG hash mask for algorithm
+ *
+ * @hash_alg: TCG defined algorithm
+ * Return: TCG hashing algorithm bitmaps (or 0 if algo not supported)
+ */
+u32 tcg2_algorithm_to_mask(enum tpm2_algorithms);
+
+#endif /* __TPM_TCG_V2_H */
diff --git a/include/u-boot/md5.h b/include/u-boot/md5.h
index d61364c..c465925 100644
--- a/include/u-boot/md5.h
+++ b/include/u-boot/md5.h
@@ -10,18 +10,18 @@
#define MD5_SUM_LEN 16
-struct MD5Context {
+typedef struct MD5Context {
__u32 buf[4];
__u32 bits[2];
union {
unsigned char in[64];
__u32 in32[16];
};
-};
+} MD5Context;
-void MD5Init(struct MD5Context *ctx);
-void MD5Update(struct MD5Context *ctx, unsigned char const *buf, unsigned len);
-void MD5Final(unsigned char digest[16], struct MD5Context *ctx);
+void MD5Init(MD5Context *ctx);
+void MD5Update(MD5Context *ctx, unsigned char const *buf, unsigned int len);
+void MD5Final(unsigned char digest[16], MD5Context *ctx);
/*
* Calculate and store in 'output' the MD5 digest of 'len' bytes at
diff --git a/include/vsprintf.h b/include/vsprintf.h
index ed8a060..fe95147 100644
--- a/include/vsprintf.h
+++ b/include/vsprintf.h
@@ -225,23 +225,6 @@
* @size: The size of the buffer, including the trailing null space
* @fmt: The format string to use
* @...: Arguments for the format string
- * Return: the number of characters which would be
- * generated for the given input, excluding the trailing null,
- * as per ISO C99. If the return is greater than or equal to
- * @size, the resulting string is truncated.
- *
- * See the vsprintf() documentation for format string extensions over C99.
- */
-int snprintf(char *buf, size_t size, const char *fmt, ...)
- __attribute__ ((format (__printf__, 3, 4)));
-
-/**
- * Format a string and place it in a buffer
- *
- * @buf: The buffer to place the result into
- * @size: The size of the buffer, including the trailing null space
- * @fmt: The format string to use
- * @...: Arguments for the format string
*
* The return value is the number of characters written into @buf not including
* the trailing '\0'. If @size is == 0 the function returns 0.
diff --git a/include/watchdog.h b/include/watchdog.h
index ac5f11e..d1956fa 100644
--- a/include/watchdog.h
+++ b/include/watchdog.h
@@ -40,7 +40,4 @@
void hw_watchdog_init(void);
#endif
-#if defined(CONFIG_MPC85xx)
- void init_85xx_watchdog(void);
-#endif
#endif /* _WATCHDOG_H_ */
diff --git a/lib/Kconfig b/lib/Kconfig
index 189e6eb..2059219 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -439,9 +439,6 @@
depends on DM
imply DM_RNG
select SHA1
- select SHA256
- select SHA384
- select SHA512
help
This enables support for TPMs which can be used to provide security
features for your board. The TPM can be connected via LPC or I2C
@@ -449,6 +446,9 @@
command to interactive the TPM. Driver model support is provided
for the low-level TPM interface, but only one TPM is supported at
a time by the TPM library.
+ For size reasons only SHA1 is selected which is supported on TPM1.2.
+ If you want a fully functional TPM enable all hashing algorithms.
+ If you enabled measured boot all hashing algorithms are selected.
config SPL_TPM
bool "Trusted Platform Module (TPM) Support in SPL"
@@ -1143,7 +1143,7 @@
bool "Enable phandle check while getting sequence number"
help
When there are multiple device tree nodes with same name,
- enable this config option to distinguish them using
+ enable this config option to distinguish them using
phandles in fdtdec_get_alias_seq() function.
endmenu
diff --git a/lib/Makefile b/lib/Makefile
index 2a76acf..e389ad0 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -61,6 +61,8 @@
obj-$(CONFIG_TPM) += tpm_api.o
obj-$(CONFIG_TPM_V1) += tpm-v1.o
obj-$(CONFIG_TPM_V2) += tpm-v2.o
+obj-$(CONFIG_EFI_TCG2_PROTOCOL) += tpm_tcg2.o
+obj-$(CONFIG_MEASURED_BOOT) += tpm_tcg2.o
endif
obj-$(CONFIG_$(SPL_TPL_)CRC8) += crc8.o
diff --git a/lib/acpi/acpi_table.c b/lib/acpi/acpi_table.c
index c16ead6..6dbfdb2 100644
--- a/lib/acpi/acpi_table.c
+++ b/lib/acpi/acpi_table.c
@@ -117,6 +117,7 @@
memcpy(header->oem_table_id, OEM_TABLE_ID, 8);
header->oem_revision = OEM_REVISION;
memcpy(header->creator_id, ASLC_ID, 4);
+ header->creator_revision = ASL_REVISION;
}
void acpi_align(struct acpi_ctx *ctx)
@@ -219,7 +220,6 @@
header->revision = acpi_get_table_revision(ACPITAB_DBG2);
acpi_fill_header(header, "DBG2");
- header->creator_revision = ASL_REVISION;
/* One debug device defined */
dbg2->devices_offset = sizeof(struct acpi_dbg2_header);
diff --git a/lib/acpi/ssdt.c b/lib/acpi/ssdt.c
index e032e26..df1d739 100644
--- a/lib/acpi/ssdt.c
+++ b/lib/acpi/ssdt.c
@@ -23,7 +23,6 @@
acpi_fill_header(ssdt, "SSDT");
ssdt->revision = acpi_get_table_revision(ACPITAB_SSDT);
- ssdt->creator_revision = 1;
ssdt->length = sizeof(struct acpi_table_header);
acpi_inc(ctx, sizeof(struct acpi_table_header));
diff --git a/lib/display_options.c b/lib/display_options.c
index d6b9355..d5df53a 100644
--- a/lib/display_options.c
+++ b/lib/display_options.c
@@ -12,6 +12,7 @@
#include <linux/ctype.h>
#include <linux/kernel.h>
#include <asm/io.h>
+#include <stdio.h>
#include <vsprintf.h>
char *display_options_get_banner_priv(bool newlines, const char *build_tag,
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index 430bb7f..ee71f41 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -10,9 +10,9 @@
depends on !EFI_STUB || !X86_64 || EFI_STUB_64BIT
# We need EFI_STUB_32BIT to be set on x86_32 with EFI_STUB
depends on !EFI_STUB || !X86 || X86_64 || EFI_STUB_32BIT
- depends on BLK
depends on !EFI_APP
default y if !ARM || SYS_CPU = armv7 || SYS_CPU = armv8
+ select BLK
select CHARSET
# We need to send DM events, dynamically, in the EFI block driver
select DM_EVENT
diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile
index 034e366..2af6f20 100644
--- a/lib/efi_loader/Makefile
+++ b/lib/efi_loader/Makefile
@@ -59,6 +59,7 @@
obj-$(CONFIG_EFI_DEVICE_PATH_TO_TEXT) += efi_device_path_to_text.o
obj-$(CONFIG_EFI_DEVICE_PATH_UTIL) += efi_device_path_utilities.o
obj-y += efi_dt_fixup.o
+obj-y += efi_fdt.o
obj-y += efi_file.o
obj-$(CONFIG_EFI_LOADER_HII) += efi_hii.o
obj-y += efi_image_loader.o
diff --git a/lib/efi_loader/capsule_esl.dtsi.in b/lib/efi_loader/capsule_esl.dtsi.in
index 61a9f2b..bc7db83 100644
--- a/lib/efi_loader/capsule_esl.dtsi.in
+++ b/lib/efi_loader/capsule_esl.dtsi.in
@@ -1,9 +1,9 @@
// SPDX-License-Identifier: GPL-2.0+
-/**
+/*
* Devicetree file with the public key EFI Signature List(ESL)
* node. This file is used to generate the dtsi file to be
* included into the DTB.
-*/
+ */
/ {
signature {
capsule-key = /incbin/("ESL_BIN_FILE");
diff --git a/lib/efi_loader/efi_bootbin.c b/lib/efi_loader/efi_bootbin.c
index b7910f7..a87006b 100644
--- a/lib/efi_loader/efi_bootbin.c
+++ b/lib/efi_loader/efi_bootbin.c
@@ -150,7 +150,7 @@
msg_path = file_path;
} else {
file_path = efi_dp_concat(bootefi_device_path,
- bootefi_image_path, false);
+ bootefi_image_path, 0);
msg_path = bootefi_image_path;
log_debug("Loaded from disk\n");
}
diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c
index 7da3139..304ed43 100644
--- a/lib/efi_loader/efi_bootmgr.c
+++ b/lib/efi_loader/efi_bootmgr.c
@@ -130,7 +130,7 @@
if (!dp)
continue;
- dp = efi_dp_concat(dp, fp, false);
+ dp = efi_dp_concat(dp, fp, 0);
if (!dp)
continue;
@@ -1186,6 +1186,59 @@
}
/**
+ * load_fdt_from_load_option - load device-tree from load option
+ *
+ * @fdt: pointer to loaded device-tree or NULL
+ * Return: status code
+ */
+static efi_status_t load_fdt_from_load_option(void **fdt)
+{
+ struct efi_device_path *dp = NULL;
+ struct efi_file_handle *f = NULL;
+ efi_uintn_t filesize;
+ efi_status_t ret;
+
+ *fdt = NULL;
+
+ dp = efi_get_dp_from_boot(&efi_guid_fdt);
+ if (!dp)
+ return EFI_SUCCESS;
+
+ /* Open file */
+ f = efi_file_from_path(dp);
+ if (!f) {
+ log_err("Can't find %pD specified in Boot####\n", dp);
+ ret = EFI_NOT_FOUND;
+ goto out;
+ }
+
+ /* Get file size */
+ ret = efi_file_size(f, &filesize);
+ if (ret != EFI_SUCCESS)
+ goto out;
+
+ *fdt = calloc(1, filesize);
+ if (!*fdt) {
+ log_err("Out of memory\n");
+ ret = EFI_OUT_OF_RESOURCES;
+ goto out;
+ }
+ ret = EFI_CALL(f->read(f, &filesize, *fdt));
+ if (ret != EFI_SUCCESS) {
+ log_err("Can't read fdt\n");
+ free(*fdt);
+ *fdt = NULL;
+ }
+
+out:
+ efi_free_pool(dp);
+ if (f)
+ EFI_CALL(f->close(f));
+
+ return ret;
+}
+
+/**
* efi_bootmgr_run() - execute EFI boot manager
* @fdt: Flat device tree
*
@@ -1200,6 +1253,8 @@
efi_handle_t handle;
void *load_options;
efi_status_t ret;
+ void *fdt_lo, *fdt_distro = NULL;
+ efi_uintn_t fdt_size;
/* Initialize EFI drivers */
ret = efi_init_obj_list();
@@ -1215,7 +1270,31 @@
return ret;
}
+ if (!IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE)) {
+ ret = load_fdt_from_load_option(&fdt_lo);
+ if (ret != EFI_SUCCESS)
+ return ret;
+ if (fdt_lo)
+ fdt = fdt_lo;
+ if (!fdt) {
+ efi_load_distro_fdt(&fdt_distro, &fdt_size);
+ fdt = fdt_distro;
+ }
+ }
+
+ /*
+ * Needed in ACPI case to create reservations based on
+ * control device-tree.
+ */
ret = efi_install_fdt(fdt);
+
+ if (!IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE)) {
+ free(fdt_lo);
+ if (fdt_distro)
+ efi_free_pages((uintptr_t)fdt_distro,
+ efi_size_in_pages(fdt_size));
+ }
+
if (ret != EFI_SUCCESS) {
if (EFI_CALL(efi_unload_image(handle)) == EFI_SUCCESS)
free(load_options);
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index 1951291..eedc5f3 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -1816,7 +1816,7 @@
if (device_path) {
info->device_handle = efi_dp_find_obj(device_path, NULL, NULL);
- dp = efi_dp_concat(device_path, file_path, false);
+ dp = efi_dp_concat(device_path, file_path, 0);
if (!dp) {
ret = EFI_OUT_OF_RESOURCES;
goto failure;
@@ -1996,7 +1996,6 @@
* @size: size of the loaded image
* Return: status code
*/
-static
efi_status_t efi_load_image_from_path(bool boot_policy,
struct efi_device_path *file_path,
void **buffer, efi_uintn_t *size)
diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c
index de0d49e..0937800 100644
--- a/lib/efi_loader/efi_capsule.c
+++ b/lib/efi_loader/efi_capsule.c
@@ -480,6 +480,11 @@
if (ret != EFI_SUCCESS)
log_err("Unable to set the Accept bit for the image %pUs\n",
image_guid);
+
+ status = fwu_state_machine_updates(0, active_idx);
+ if (status < 0)
+ ret = EFI_DEVICE_ERROR;
+
}
return ret;
@@ -521,11 +526,10 @@
log_err("Failed to update FWU metadata index values\n");
} else {
log_debug("Successfully updated the active_index\n");
- if (fw_accept_os) {
- status = fwu_trial_state_ctr_start();
- if (status < 0)
- ret = EFI_DEVICE_ERROR;
- }
+ status = fwu_state_machine_updates(fw_accept_os ? 1 : 0,
+ update_index);
+ if (status < 0)
+ ret = EFI_DEVICE_ERROR;
}
return ret;
diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c
index aec224d..0f68459 100644
--- a/lib/efi_loader/efi_device_path.c
+++ b/lib/efi_loader/efi_device_path.c
@@ -276,10 +276,11 @@
*
* @dp1: First device path
* @dp2: Second device path
- * @split_end_node: If true the two device paths will be concatenated and
- * separated by an end node (DEVICE_PATH_SUB_TYPE_END).
- * If false the second device path will be concatenated to the
- * first one as-is.
+ * @split_end_node:
+ * * 0 to concatenate
+ * * 1 to concatenate with end node added as separator
+ * * size of dp1 excluding last end node to concatenate with end node as
+ * separator in case dp1 contains an end node
*
* Return:
* concatenated device path or NULL. Caller must free the returned value
@@ -287,7 +288,7 @@
struct
efi_device_path *efi_dp_concat(const struct efi_device_path *dp1,
const struct efi_device_path *dp2,
- bool split_end_node)
+ size_t split_end_node)
{
struct efi_device_path *ret;
size_t end_size;
@@ -301,10 +302,15 @@
ret = efi_dp_dup(dp1);
} else {
/* both dp1 and dp2 are non-null */
- unsigned sz1 = efi_dp_size(dp1);
- unsigned sz2 = efi_dp_size(dp2);
+ size_t sz1;
+ size_t sz2 = efi_dp_size(dp2);
void *p;
+ if (split_end_node < sizeof(struct efi_device_path))
+ sz1 = efi_dp_size(dp1);
+ else
+ sz1 = split_end_node;
+
if (split_end_node)
end_size = 2 * sizeof(END);
else
@@ -1127,17 +1133,18 @@
}
/**
- * efi_dp_from_lo() - Get the instance of a VenMedia node in a
- * multi-instance device path that matches
- * a specific GUID. This kind of device paths
- * is found in Boot#### options describing an
- * initrd location
+ * efi_dp_from_lo() - get device-path from load option
*
- * @lo: EFI_LOAD_OPTION containing a valid device path
- * @guid: guid to search for
+ * The load options in U-Boot may contain multiple concatenated device-paths.
+ * The first device-path indicates the EFI binary to execute. Subsequent
+ * device-paths start with a VenMedia node where the GUID identifies the
+ * function (initrd or fdt).
+ *
+ * @lo: EFI load option containing a valid device path
+ * @guid: GUID identifying device-path or NULL for the EFI binary
*
* Return:
- * device path including the VenMedia node or NULL.
+ * device path excluding the matched VenMedia node or NULL.
* Caller must free the returned value.
*/
struct
@@ -1148,6 +1155,9 @@
struct efi_device_path_vendor *vendor;
int lo_len = lo->file_path_length;
+ if (!guid)
+ return efi_dp_dup(fp);
+
for (; lo_len >= sizeof(struct efi_device_path);
lo_len -= fp->length, fp = (void *)fp + fp->length) {
if (lo_len < 0 || efi_dp_check_length(fp, lo_len) < 0)
diff --git a/lib/efi_loader/efi_device_path_utilities.c b/lib/efi_loader/efi_device_path_utilities.c
index c95dbfa..ac250bb 100644
--- a/lib/efi_loader/efi_device_path_utilities.c
+++ b/lib/efi_loader/efi_device_path_utilities.c
@@ -76,7 +76,7 @@
const struct efi_device_path *src2)
{
EFI_ENTRY("%pD, %pD", src1, src2);
- return EFI_EXIT(efi_dp_concat(src1, src2, false));
+ return EFI_EXIT(efi_dp_concat(src1, src2, 0));
}
/*
diff --git a/lib/efi_loader/efi_fdt.c b/lib/efi_loader/efi_fdt.c
new file mode 100644
index 0000000..86ba00c
--- /dev/null
+++ b/lib/efi_loader/efi_fdt.c
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Bootmethod for distro boot via EFI
+ *
+ * Copyright 2021 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <efi_loader.h>
+#include <env.h>
+#include <errno.h>
+#include <log.h>
+#include <string.h>
+#include <vsprintf.h>
+
+/**
+ * distro_efi_get_fdt_name() - get the filename for reading the .dtb file
+ *
+ * @fname: buffer for filename
+ * @size: buffer size
+ * @seq: sequence number, to cycle through options (0=first)
+ *
+ * Returns:
+ * 0 on success,
+ * -ENOENT if the "fdtfile" env var does not exist,
+ * -EINVAL if there are no more options,
+ * -EALREADY if the control FDT should be used
+ */
+int efi_get_distro_fdt_name(char *fname, int size, int seq)
+{
+ const char *fdt_fname;
+ const char *prefix;
+
+ /* select the prefix */
+ switch (seq) {
+ case 0:
+ /* this is the default */
+ prefix = "/dtb";
+ break;
+ case 1:
+ prefix = "";
+ break;
+ case 2:
+ prefix = "/dtb/current";
+ break;
+ default:
+ return log_msg_ret("pref", -EINVAL);
+ }
+
+ fdt_fname = env_get("fdtfile");
+ if (fdt_fname) {
+ snprintf(fname, size, "%s/%s", prefix, fdt_fname);
+ log_debug("Using device tree: %s\n", fname);
+ } else if (IS_ENABLED(CONFIG_OF_HAS_PRIOR_STAGE)) {
+ strcpy(fname, "<prior>");
+ return log_msg_ret("pref", -EALREADY);
+ /* Use this fallback only for 32-bit ARM */
+ } else if (IS_ENABLED(CONFIG_ARM) && !IS_ENABLED(CONFIG_ARM64)) {
+ const char *soc = env_get("soc");
+ const char *board = env_get("board");
+ const char *boardver = env_get("boardver");
+
+ /* cf the code in label_boot() which seems very complex */
+ snprintf(fname, size, "%s/%s%s%s%s.dtb", prefix,
+ soc ? soc : "", soc ? "-" : "", board ? board : "",
+ boardver ? boardver : "");
+ log_debug("Using default device tree: %s\n", fname);
+ } else {
+ return log_msg_ret("env", -ENOENT);
+ }
+
+ return 0;
+}
+
+/**
+ * efi_load_distro_fdt() - load distro device-tree
+ *
+ * @fdt: on return device-tree, must be freed via efi_free_pages()
+ * @fdt_size: buffer size
+ */
+void efi_load_distro_fdt(void **fdt, efi_uintn_t *fdt_size)
+{
+ struct efi_device_path *rem, *dp;
+ efi_status_t ret;
+ efi_handle_t device;
+
+ *fdt = NULL;
+
+ dp = efi_get_dp_from_boot(NULL);
+ if (!dp)
+ return;
+ device = efi_dp_find_obj(dp, NULL, &rem);
+ ret = efi_search_protocol(device, &efi_simple_file_system_protocol_guid,
+ NULL);
+ if (ret != EFI_SUCCESS)
+ goto err;
+ memcpy(rem, &END, sizeof(END));
+
+ /* try the various available names */
+ for (int seq = 0; ; ++seq) {
+ struct efi_device_path *file;
+ char buf[255];
+
+ if (efi_get_distro_fdt_name(buf, sizeof(buf), seq))
+ break;
+ file = efi_dp_from_file(dp, buf);
+ if (!file)
+ break;
+ ret = efi_load_image_from_path(true, file, fdt, fdt_size);
+ efi_free_pool(file);
+ if (ret == EFI_SUCCESS)
+ break;
+ }
+
+err:
+ efi_free_pool(dp);
+}
diff --git a/lib/efi_loader/efi_helper.c b/lib/efi_loader/efi_helper.c
index 73d0279..348612c 100644
--- a/lib/efi_loader/efi_helper.c
+++ b/lib/efi_loader/efi_helper.c
@@ -99,6 +99,50 @@
return NULL;
}
+/**
+ * efi_load_option_dp_join() - join device-paths for load option
+ *
+ * @dp: in: binary device-path, out: joined device-path
+ * @dp_size: size of joined device-path
+ * @initrd_dp: initrd device-path or NULL
+ * @fdt_dp: device-tree device-path or NULL
+ * Return: status_code
+ */
+efi_status_t efi_load_option_dp_join(struct efi_device_path **dp,
+ size_t *dp_size,
+ struct efi_device_path *initrd_dp,
+ struct efi_device_path *fdt_dp)
+{
+ if (!dp)
+ return EFI_INVALID_PARAMETER;
+
+ *dp_size = efi_dp_size(*dp);
+
+ if (initrd_dp) {
+ struct efi_device_path *tmp_dp = *dp;
+
+ *dp = efi_dp_concat(tmp_dp, initrd_dp, *dp_size);
+ efi_free_pool(tmp_dp);
+ if (!*dp)
+ return EFI_OUT_OF_RESOURCES;
+ *dp_size += efi_dp_size(initrd_dp) + sizeof(END);
+ }
+
+ if (fdt_dp) {
+ struct efi_device_path *tmp_dp = *dp;
+
+ *dp = efi_dp_concat(tmp_dp, fdt_dp, *dp_size);
+ efi_free_pool(tmp_dp);
+ if (!dp)
+ return EFI_OUT_OF_RESOURCES;
+ *dp_size += efi_dp_size(fdt_dp) + sizeof(END);
+ }
+
+ *dp_size += sizeof(END);
+
+ return EFI_SUCCESS;
+}
+
const struct guid_to_hash_map {
efi_guid_t guid;
const char algo[32];
diff --git a/lib/efi_loader/efi_image_loader.c b/lib/efi_loader/efi_image_loader.c
index 6042436..45dc5b6 100644
--- a/lib/efi_loader/efi_image_loader.c
+++ b/lib/efi_loader/efi_image_loader.c
@@ -173,11 +173,6 @@
return EFI_SUCCESS;
}
-void __weak invalidate_icache_all(void)
-{
- /* If the system doesn't support icache_all flush, cross our fingers */
-}
-
/**
* efi_set_code_and_data_type() - determine the memory types to be used for code
* and data.
@@ -986,7 +981,13 @@
/* Flush cache */
flush_cache((ulong)efi_reloc,
ALIGN(virt_size, EFI_CACHELINE_SIZE));
- invalidate_icache_all();
+
+ /*
+ * If on x86 a write affects a prefetched instruction,
+ * the prefetch queue is invalidated.
+ */
+ if (!CONFIG_IS_ENABLED(X86))
+ invalidate_icache_all();
/* Populate the loaded image interface bits */
loaded_image_info->image_base = efi_reloc;
diff --git a/lib/efi_loader/efi_load_initrd.c b/lib/efi_loader/efi_load_initrd.c
index d911354..2350843 100644
--- a/lib/efi_loader/efi_load_initrd.c
+++ b/lib/efi_loader/efi_load_initrd.c
@@ -24,7 +24,7 @@
* Device path defined by Linux to identify the handle providing the
* EFI_LOAD_FILE2_PROTOCOL used for loading the initial ramdisk.
*/
-static const struct efi_initrd_dp dp_lf2_handle = {
+static const struct efi_lo_dp_prefix dp_lf2_handle = {
.vendor = {
{
DEVICE_PATH_TYPE_MEDIA_DEVICE,
diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c
index 011bcd0..05369c4 100644
--- a/lib/efi_loader/efi_runtime.c
+++ b/lib/efi_loader/efi_runtime.c
@@ -783,7 +783,12 @@
lastoff = offset;
#endif
- invalidate_icache_all();
+ /*
+ * If on x86 a write affects a prefetched instruction,
+ * the prefetch queue is invalidated.
+ */
+ if (!CONFIG_IS_ENABLED(X86))
+ invalidate_icache_all();
}
/**
diff --git a/lib/efi_loader/efi_signature.c b/lib/efi_loader/efi_signature.c
index f338e73..184eac8 100644
--- a/lib/efi_loader/efi_signature.c
+++ b/lib/efi_loader/efi_signature.c
@@ -17,7 +17,6 @@
#include <linux/oid_registry.h>
#include <u-boot/hash-checksum.h>
#include <u-boot/rsa.h>
-#include <u-boot/sha256.h>
const efi_guid_t efi_guid_sha256 = EFI_CERT_SHA256_GUID;
const efi_guid_t efi_guid_cert_rsa2048 = EFI_CERT_RSA2048_GUID;
diff --git a/lib/efi_loader/efi_tcg2.c b/lib/efi_loader/efi_tcg2.c
index b07e009..45f451e 100644
--- a/lib/efi_loader/efi_tcg2.c
+++ b/lib/efi_loader/efi_tcg2.c
@@ -16,12 +16,8 @@
#include <malloc.h>
#include <smbios.h>
#include <version_string.h>
-#include <tpm-v2.h>
#include <tpm_api.h>
#include <u-boot/hash-checksum.h>
-#include <u-boot/sha1.h>
-#include <u-boot/sha256.h>
-#include <u-boot/sha512.h>
#include <linux/unaligned/be_byteshift.h>
#include <linux/unaligned/le_byteshift.h>
#include <linux/unaligned/generic.h>
@@ -257,8 +253,8 @@
capability->protocol_version.major = 1;
capability->protocol_version.minor = 1;
- efi_ret = tcg2_platform_get_tpm2(&dev);
- if (efi_ret != EFI_SUCCESS) {
+ ret = tcg2_platform_get_tpm2(&dev);
+ if (ret) {
capability->supported_event_logs = 0;
capability->hash_algorithm_bitmap = 0;
capability->tpm_present_flag = false;
@@ -280,7 +276,7 @@
/* Supported and active PCRs */
capability->hash_algorithm_bitmap = 0;
capability->active_pcr_banks = 0;
- ret = tpm2_get_pcr_info(dev, &capability->hash_algorithm_bitmap,
+ ret = tcg2_get_pcr_info(dev, &capability->hash_algorithm_bitmap,
&capability->active_pcr_banks,
&capability->number_of_pcr_banks);
if (ret) {
@@ -353,8 +349,7 @@
goto out;
}
- ret = tcg2_platform_get_tpm2(&dev);
- if (ret != EFI_SUCCESS) {
+ if (tcg2_platform_get_tpm2(&dev)) {
event_log_location = NULL;
event_log_last_entry = NULL;
*event_log_truncated = false;
@@ -389,7 +384,7 @@
void *new_efi = NULL;
u8 hash[TPM2_SHA512_DIGEST_SIZE];
struct udevice *dev;
- efi_status_t ret;
+ efi_status_t ret = EFI_SUCCESS;
u32 active;
int i;
@@ -404,20 +399,21 @@
goto out;
}
- ret = tcg2_platform_get_tpm2(&dev);
- if (ret != EFI_SUCCESS)
+ if (tcg2_platform_get_tpm2(&dev)) {
+ ret = EFI_DEVICE_ERROR;
goto out;
+ }
- ret = tcg2_get_active_pcr_banks(dev, &active);
- if (ret != EFI_SUCCESS) {
+ if (tcg2_get_active_pcr_banks(dev, &active)) {
+ ret = EFI_DEVICE_ERROR;
goto out;
}
digest_list->count = 0;
- for (i = 0; i < ARRAY_SIZE(tpm2_supported_algorithms); i++) {
- u16 hash_alg = tpm2_supported_algorithms[i];
+ for (i = 0; i < ARRAY_SIZE(hash_algo_list); i++) {
+ u16 hash_alg = hash_algo_list[i].hash_alg;
- if (!(active & tpm2_algorithm_to_mask(hash_alg)))
+ if (!(active & hash_algo_list[i].hash_mask))
continue;
switch (hash_alg) {
case TPM2_ALG_SHA1:
@@ -473,12 +469,12 @@
IMAGE_DOS_HEADER *dos;
IMAGE_NT_HEADERS32 *nt;
struct efi_handler *handler;
+ int rc;
if (!is_tcg2_protocol_installed())
return EFI_SUCCESS;
- ret = tcg2_platform_get_tpm2(&dev);
- if (ret != EFI_SUCCESS)
+ if (tcg2_platform_get_tpm2(&dev))
return EFI_SECURITY_VIOLATION;
switch (handle->image_type) {
@@ -502,9 +498,9 @@
if (ret != EFI_SUCCESS)
return ret;
- ret = tcg2_pcr_extend(dev, pcr_index, &digest_list);
- if (ret != EFI_SUCCESS)
- return ret;
+ rc = tcg2_pcr_extend(dev, pcr_index, &digest_list);
+ if (rc)
+ return EFI_DEVICE_ERROR;
ret = efi_search_protocol(&handle->header,
&efi_guid_loaded_image_device_path, &handler);
@@ -574,9 +570,10 @@
struct efi_tcg2_event *efi_tcg_event)
{
struct udevice *dev;
- efi_status_t ret;
+ efi_status_t ret = EFI_SUCCESS;
u32 event_type, pcr_index, event_size;
struct tpml_digest_values digest_list;
+ int rc = 0;
EFI_ENTRY("%p, %llu, %llu, %llu, %p", this, flags, data_to_hash,
data_to_hash_len, efi_tcg_event);
@@ -586,9 +583,10 @@
goto out;
}
- ret = tcg2_platform_get_tpm2(&dev);
- if (ret != EFI_SUCCESS)
+ if (tcg2_platform_get_tpm2(&dev)) {
+ ret = EFI_DEVICE_ERROR;
goto out;
+ }
if (efi_tcg_event->size < efi_tcg_event->header.header_size +
sizeof(u32)) {
@@ -621,8 +619,10 @@
ret = tcg2_hash_pe_image((void *)(uintptr_t)data_to_hash,
data_to_hash_len, &digest_list);
} else {
- ret = tcg2_create_digest(dev, (u8 *)(uintptr_t)data_to_hash,
- data_to_hash_len, &digest_list);
+ rc = tcg2_create_digest(dev, (u8 *)(uintptr_t)data_to_hash,
+ data_to_hash_len, &digest_list);
+ if (rc)
+ ret = EFI_DEVICE_ERROR;
}
if (ret != EFI_SUCCESS)
@@ -631,9 +631,11 @@
pcr_index = efi_tcg_event->header.pcr_index;
event_type = efi_tcg_event->header.event_type;
- ret = tcg2_pcr_extend(dev, pcr_index, &digest_list);
- if (ret != EFI_SUCCESS)
+ rc = tcg2_pcr_extend(dev, pcr_index, &digest_list);
+ if (rc) {
+ ret = EFI_DEVICE_ERROR;
goto out;
+ }
if (flags & EFI_TCG2_EXTEND_ONLY) {
if (event_log.truncated)
@@ -672,7 +674,7 @@
u8 *output_param_block)
{
struct udevice *dev;
- efi_status_t ret;
+ efi_status_t ret = EFI_SUCCESS;
u32 rc;
size_t resp_buf_size = output_param_block_size;
@@ -684,9 +686,10 @@
goto out;
}
- ret = tcg2_platform_get_tpm2(&dev);
- if (ret != EFI_SUCCESS)
+ if (tcg2_platform_get_tpm2(&dev)) {
+ ret = EFI_DEVICE_ERROR;
goto out;
+ }
rc = tpm2_submit_command(dev, input_param_block,
output_param_block, &resp_buf_size);
@@ -714,19 +717,25 @@
u32 *active_pcr_banks)
{
struct udevice *dev;
- efi_status_t ret;
+ efi_status_t ret = EFI_INVALID_PARAMETER;
EFI_ENTRY("%p, %p", this, active_pcr_banks);
- if (!this || !active_pcr_banks) {
- ret = EFI_INVALID_PARAMETER;
+ if (!this || !active_pcr_banks)
goto out;
- }
- ret = tcg2_platform_get_tpm2(&dev);
- if (ret != EFI_SUCCESS)
+
+ if (tcg2_platform_get_tpm2(&dev))
+ goto out;
+
+ /*
+ * EFI_INVALID_PARAMETER does not convey the problem type.
+ * but that's what currently the spec specifies.
+ * EFI_DEVICE_ERROR would be better
+ */
+ if (tcg2_get_active_pcr_banks(dev, active_pcr_banks))
goto out;
- ret = tcg2_get_active_pcr_banks(dev, active_pcr_banks);
+ ret = EFI_SUCCESS;
out:
return EFI_EXIT(ret);
@@ -852,14 +861,15 @@
u32 event_type, u32 size, u8 event[])
{
struct tpml_digest_values digest_list;
- efi_status_t ret;
+ efi_status_t ret = EFI_DEVICE_ERROR;
+ int rc;
- ret = tcg2_create_digest(dev, event, size, &digest_list);
- if (ret != EFI_SUCCESS)
+ rc = tcg2_create_digest(dev, event, size, &digest_list);
+ if (rc)
goto out;
- ret = tcg2_pcr_extend(dev, pcr_index, &digest_list);
- if (ret != EFI_SUCCESS)
+ rc = tcg2_pcr_extend(dev, pcr_index, &digest_list);
+ if (rc)
goto out;
ret = tcg2_agile_log_append(pcr_index, event_type, &digest_list,
@@ -901,10 +911,10 @@
struct tcg2_event_log elog;
struct udevice *dev;
efi_status_t ret;
+ int rc;
- ret = tcg2_platform_get_tpm2(&dev);
- if (ret != EFI_SUCCESS)
- return ret;
+ if (tcg2_platform_get_tpm2(&dev))
+ return EFI_DEVICE_ERROR;
ret = efi_allocate_pool(EFI_BOOT_SERVICES_DATA, TPM2_EVENT_LOG_SIZE,
(void **)&event_log.buffer);
@@ -933,9 +943,11 @@
*/
elog.log = event_log.buffer;
elog.log_size = TPM2_EVENT_LOG_SIZE;
- ret = tcg2_log_prepare_buffer(dev, &elog, false);
- if (ret != EFI_SUCCESS)
+ rc = tcg2_log_prepare_buffer(dev, &elog, false);
+ if (rc) {
+ ret = (rc == -ENOBUFS) ? EFI_BUFFER_TOO_SMALL : EFI_DEVICE_ERROR;
goto free_pool;
+ }
event_log.pos = elog.log_position;
@@ -1306,8 +1318,7 @@
if (!is_tcg2_protocol_installed())
return EFI_SUCCESS;
- ret = tcg2_platform_get_tpm2(&dev);
- if (ret != EFI_SUCCESS)
+ if (tcg2_platform_get_tpm2(&dev))
return EFI_SECURITY_VIOLATION;
rsvmap_size = size_of_rsvmap(dtb);
@@ -1331,7 +1342,7 @@
sha256_update(&hash_ctx, (u8 *)dtb + fdt_off_mem_rsvmap(dtb), rsvmap_size);
sha256_finish(&hash_ctx, blob->data + blob->blob_description_size);
- ret = measure_event(dev, 0, EV_POST_CODE, event_size, (u8 *)blob);
+ ret = measure_event(dev, 1, EV_POST_CODE, event_size, (u8 *)blob);
free(blob);
return ret;
@@ -1356,8 +1367,7 @@
if (tcg2_efi_app_invoked)
return EFI_SUCCESS;
- ret = tcg2_platform_get_tpm2(&dev);
- if (ret != EFI_SUCCESS)
+ if (tcg2_platform_get_tpm2(&dev))
return EFI_SECURITY_VIOLATION;
ret = tcg2_measure_boot_variable(dev);
@@ -1406,9 +1416,8 @@
if (!is_tcg2_protocol_installed())
return EFI_SUCCESS;
- ret = tcg2_platform_get_tpm2(&dev);
- if (ret != EFI_SUCCESS)
- return ret;
+ if (tcg2_platform_get_tpm2(&dev))
+ return EFI_SECURITY_VIOLATION;
ret = measure_event(dev, 4, EV_EFI_ACTION,
strlen(EFI_RETURNING_FROM_EFI_APPLICATION),
@@ -1437,9 +1446,10 @@
goto out;
}
- ret = tcg2_platform_get_tpm2(&dev);
- if (ret != EFI_SUCCESS)
+ if (tcg2_platform_get_tpm2(&dev)) {
+ ret = EFI_SECURITY_VIOLATION;
goto out;
+ }
ret = measure_event(dev, 5, EV_EFI_ACTION,
strlen(EFI_EXIT_BOOT_SERVICES_INVOCATION),
@@ -1469,9 +1479,8 @@
if (!is_tcg2_protocol_installed())
return EFI_SUCCESS;
- ret = tcg2_platform_get_tpm2(&dev);
- if (ret != EFI_SUCCESS)
- goto out;
+ if (tcg2_platform_get_tpm2(&dev))
+ return EFI_SECURITY_VIOLATION;
ret = measure_event(dev, 5, EV_EFI_ACTION,
strlen(EFI_EXIT_BOOT_SERVICES_INVOCATION),
@@ -1551,8 +1560,7 @@
if (!is_tcg2_protocol_installed())
return EFI_SUCCESS;
- ret = tcg2_platform_get_tpm2(&dev);
- if (ret != EFI_SUCCESS)
+ if (tcg2_platform_get_tpm2(&dev))
return EFI_SECURITY_VIOLATION;
ret = tcg2_measure_secure_boot_variable(dev);
@@ -1577,8 +1585,7 @@
struct efi_event *event;
u32 err;
- ret = tcg2_platform_get_tpm2(&dev);
- if (ret != EFI_SUCCESS) {
+ if (tcg2_platform_get_tpm2(&dev)) {
log_warning("Missing TPMv2 device for EFI_TCG_PROTOCOL\n");
return EFI_SUCCESS;
}
@@ -1586,6 +1593,7 @@
/* initialize the TPM as early as possible. */
err = tpm_auto_start(dev);
if (err) {
+ ret = EFI_DEVICE_ERROR;
log_err("TPM startup failed\n");
goto fail;
}
diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c
index 1cc02ac..09651d4 100644
--- a/lib/efi_loader/efi_variable.c
+++ b/lib/efi_loader/efi_variable.c
@@ -288,7 +288,6 @@
/* check if a variable exists */
var = efi_var_mem_find(vendor, variable_name, NULL);
append = !!(attributes & EFI_VARIABLE_APPEND_WRITE);
- attributes &= ~EFI_VARIABLE_APPEND_WRITE;
delete = !append && (!data_size || !attributes);
/* check attributes */
@@ -304,7 +303,7 @@
/* attributes won't be changed */
if (!delete &&
- ((ro_check && var->attr != attributes) ||
+ ((ro_check && var->attr != (attributes & ~EFI_VARIABLE_APPEND_WRITE)) ||
(!ro_check && ((var->attr & ~EFI_VARIABLE_READ_ONLY)
!= (attributes & ~EFI_VARIABLE_READ_ONLY))))) {
return EFI_INVALID_PARAMETER;
@@ -378,7 +377,8 @@
for (; *old_data; ++old_data)
;
++old_data;
- ret = efi_var_mem_ins(variable_name, vendor, attributes,
+ ret = efi_var_mem_ins(variable_name, vendor,
+ attributes & ~EFI_VARIABLE_APPEND_WRITE,
var->length, old_data, data_size, data,
time);
} else {
diff --git a/lib/efi_loader/initrddump.c b/lib/efi_loader/initrddump.c
index 0004b6b..6151190 100644
--- a/lib/efi_loader/initrddump.c
+++ b/lib/efi_loader/initrddump.c
@@ -33,7 +33,7 @@
* Device path defined by Linux to identify the handle providing the
* EFI_LOAD_FILE2_PROTOCOL used for loading the initial ramdisk.
*/
-static const struct efi_initrd_dp initrd_dp = {
+static const struct efi_lo_dp_prefix initrd_dp = {
.vendor = {
{
DEVICE_PATH_TYPE_MEDIA_DEVICE,
diff --git a/lib/efi_selftest/efi_selftest_fdt.c b/lib/efi_selftest/efi_selftest_fdt.c
index aa3b13a..a4b0cef 100644
--- a/lib/efi_selftest/efi_selftest_fdt.c
+++ b/lib/efi_selftest/efi_selftest_fdt.c
@@ -227,6 +227,13 @@
return EFI_ST_FAILURE;
}
}
+ if (IS_ENABLED(CONFIG_EFI_TCG2_PROTOCOL_MEASURE_DTB)) {
+ str = get_property(u"kaslr-seed", u"chosen");
+ if (str) {
+ efi_st_error("kaslr-seed with measured fdt\n");
+ return EFI_ST_FAILURE;
+ }
+ }
if (IS_ENABLED(CONFIG_RISCV)) {
u32 fdt_hartid;
diff --git a/lib/elf.c b/lib/elf.c
index 9a794f9..dc13935 100644
--- a/lib/elf.c
+++ b/lib/elf.c
@@ -7,6 +7,7 @@
#include <cpu_func.h>
#include <elf.h>
#include <env.h>
+#include <errno.h>
#include <net.h>
#include <vxworks.h>
#ifdef CONFIG_X86
@@ -15,6 +16,59 @@
#include <linux/linkage.h>
#endif
+/**
+ * bootelf_exec() - start the ELF image execution.
+ *
+ * @entry: address of entry point of ELF.
+ *
+ * May by used to allow ports to override the default behavior.
+ */
+unsigned long bootelf_exec(ulong (*entry)(int, char * const[]),
+ int argc, char *const argv[])
+{
+ return entry(argc, argv);
+}
+
+/**
+ * bootelf() - Boot ELF from memory.
+ *
+ * @addr: Loading address of ELF in memory.
+ * @flags: Bits like ELF_PHDR to control boot details.
+ * @argc: May be used to pass command line arguments (maybe unused).
+ * Necessary for backward compatibility with the CLI command.
+ * If unused, must be 0.
+ * @argv: see @argc. If unused, must be NULL.
+ * Return: Number returned by ELF application.
+ *
+ * Sets errno = ENOEXEC if the ELF image is not valid.
+ */
+unsigned long bootelf(unsigned long addr, Bootelf_flags flags,
+ int argc, char *const argv[])
+{
+ unsigned long entry_addr;
+ char *args[] = {"", NULL};
+
+ errno = 0;
+
+ if (!valid_elf_image(addr)) {
+ errno = ENOEXEC;
+ return 1;
+ }
+
+ entry_addr = flags.phdr ? load_elf_image_phdr(addr)
+ : load_elf_image_shdr(addr);
+
+ if (!flags.autostart)
+ return 0;
+
+ if (!argc && !argv) {
+ argc = 1;
+ argv = args;
+ }
+
+ return bootelf_exec((void *)entry_addr, argc, argv);
+}
+
/*
* A very simple ELF64 loader, assumes the image is valid, returns the
* entry point address.
diff --git a/lib/fwu_updates/Kconfig b/lib/fwu_updates/Kconfig
index d35247d..51b7fbb 100644
--- a/lib/fwu_updates/Kconfig
+++ b/lib/fwu_updates/Kconfig
@@ -31,4 +31,18 @@
the platform is allowed to boot in Trial State after an
update.
+config FWU_MDATA_V1
+ bool "Enable support FWU Metadata version 1"
+ help
+ The FWU specification supports two versions of the
+ metadata structure. This option enables support for FWU
+ Metadata version 1 access.
+
+config FWU_MDATA_V2
+ bool "Enable support FWU Metadata version 2"
+ help
+ The FWU specification supports two versions of the
+ metadata structure. This option enables support for FWU
+ Metadata version 2 access.
+
endif
diff --git a/lib/fwu_updates/Makefile b/lib/fwu_updates/Makefile
index c9e3c06..3681bef 100644
--- a/lib/fwu_updates/Makefile
+++ b/lib/fwu_updates/Makefile
@@ -6,3 +6,5 @@
obj-$(CONFIG_FWU_MULTI_BANK_UPDATE) += fwu.o
obj-$(CONFIG_FWU_MDATA_GPT_BLK) += fwu_gpt.o
obj-$(CONFIG_FWU_MDATA_MTD) += fwu_mtd.o
+obj-$(CONFIG_FWU_MDATA_V1) += fwu_v1.o
+obj-$(CONFIG_FWU_MDATA_V2) += fwu_v2.o
diff --git a/lib/fwu_updates/fwu.c b/lib/fwu_updates/fwu.c
index 8651810..5dfea2a 100644
--- a/lib/fwu_updates/fwu.c
+++ b/lib/fwu_updates/fwu.c
@@ -10,6 +10,7 @@
#include <event.h>
#include <fwu.h>
#include <fwu_mdata.h>
+#include <log.h>
#include <malloc.h>
#include <linux/errno.h>
@@ -17,7 +18,7 @@
#include <u-boot/crc.h>
-static struct fwu_mdata g_mdata; /* = {0} makes uninit crc32 always invalid */
+struct fwu_data g_fwu_data;
static struct udevice *g_dev;
static u8 in_trial;
static u8 boottime_check;
@@ -27,12 +28,6 @@
IMAGE_ACCEPT_CLEAR,
};
-enum {
- PRIMARY_PART = 1,
- SECONDARY_PART,
- BOTH_PARTS,
-};
-
static int trial_counter_update(u16 *trial_state_ctr)
{
bool delete;
@@ -106,23 +101,9 @@
return ret;
}
-static int in_trial_state(struct fwu_mdata *mdata)
+static u32 in_trial_state(void)
{
- u32 i, active_bank;
- struct fwu_image_entry *img_entry;
- struct fwu_image_bank_info *img_bank_info;
-
- active_bank = mdata->active_index;
- img_entry = &mdata->img_entry[0];
- for (i = 0; i < CONFIG_FWU_NUM_IMAGES_PER_BANK; i++) {
- img_bank_info = &img_entry[i].img_bank_info[active_bank];
- if (!img_bank_info->accepted) {
- log_info("System booting in Trial State\n");
- return 1;
- }
- }
-
- return 0;
+ return g_fwu_data.trial_state;
}
static int fwu_get_image_type_id(u8 image_index, efi_guid_t *image_type_id)
@@ -141,17 +122,70 @@
return -ENOENT;
}
+static int mdata_crc_check(struct fwu_mdata *mdata)
+{
+ int ret;
+ u32 calc_crc32;
+ uint32_t mdata_size;
+ void *buf = &mdata->version;
+
+ ret = fwu_get_mdata_size(&mdata_size);
+ if (ret)
+ return ret;
+
+ calc_crc32 = crc32(0, buf, mdata_size - sizeof(u32));
+ return calc_crc32 == mdata->crc32 ? 0 : -EINVAL;
+}
+
+static void fwu_data_crc_update(uint32_t crc32)
+{
+ g_fwu_data.crc32 = crc32;
+}
+
+/**
+ * fwu_get_data() - Return the version agnostic FWU structure
+ *
+ * Return the pointer to the version agnostic FWU structure.
+ *
+ * Return: Pointer to the FWU data structure
+ */
+struct fwu_data *fwu_get_data(void)
+{
+ return &g_fwu_data;
+}
+
+static void fwu_populate_mdata_bank_index(struct fwu_data *fwu_data)
+{
+ struct fwu_mdata *mdata = fwu_data->fwu_mdata;
+
+ mdata->active_index = fwu_data->active_index;
+ mdata->previous_active_index = fwu_data->previous_active_index;
+}
+
/**
+ * fwu_get_dev() - Return the FWU metadata device
+ *
+ * Return the pointer to the FWU metadata device.
+ *
+ * Return: Pointer to the FWU metadata dev
+ */
+struct udevice *fwu_get_dev(void)
+{
+ return g_dev;
+}
+
+/**
* fwu_sync_mdata() - Update given meta-data partition(s) with the copy provided
- * @mdata: FWU metadata structure
+ * @data: FWU Data structure
* @part: Bitmask of FWU metadata partitions to be written to
*
* Return: 0 if OK, -ve on error
*/
-static int fwu_sync_mdata(struct fwu_mdata *mdata, int part)
+int fwu_sync_mdata(struct fwu_mdata *mdata, int part)
{
- void *buf = &mdata->version;
int err;
+ uint mdata_size;
+ void *buf = &mdata->version;
if (part == BOTH_PARTS) {
err = fwu_sync_mdata(mdata, SECONDARY_PART);
@@ -160,32 +194,53 @@
part = PRIMARY_PART;
}
+ err = fwu_get_mdata_size(&mdata_size);
+ if (err)
+ return err;
+
/*
* Calculate the crc32 for the updated FWU metadata
* and put the updated value in the FWU metadata crc32
* field
*/
- mdata->crc32 = crc32(0, buf, sizeof(*mdata) - sizeof(u32));
+ mdata->crc32 = crc32(0, buf, mdata_size - sizeof(u32));
+ fwu_data_crc_update(mdata->crc32);
- err = fwu_write_mdata(g_dev, mdata, part == PRIMARY_PART);
+ err = fwu_write_mdata(g_dev, mdata, part == PRIMARY_PART, mdata_size);
if (err) {
log_err("Unable to write %s mdata\n",
part == PRIMARY_PART ? "primary" : "secondary");
return err;
}
- /* update the cached copy of meta-data */
- memcpy(&g_mdata, mdata, sizeof(struct fwu_mdata));
-
return 0;
}
-static inline int mdata_crc_check(struct fwu_mdata *mdata)
+/**
+ * fwu_mdata_copies_allocate() - Allocate memory for metadata
+ * @mdata_size: Size of the metadata structure
+ *
+ * Allocate memory for storing both the copies of the FWU metadata. The
+ * copies are then used as a cache for storing FWU metadata contents.
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int fwu_mdata_copies_allocate(u32 mdata_size)
{
- void *buf = &mdata->version;
- u32 calc_crc32 = crc32(0, buf, sizeof(*mdata) - sizeof(u32));
+ if (g_fwu_data.fwu_mdata)
+ return 0;
- return calc_crc32 == mdata->crc32 ? 0 : -EINVAL;
+ /*
+ * Allocate the total memory that would be needed for both
+ * the copies.
+ */
+ g_fwu_data.fwu_mdata = calloc(2, mdata_size);
+ if (!g_fwu_data.fwu_mdata) {
+ log_err("Unable to allocate space for FWU metadata\n");
+ return -ENOMEM;
+ }
+
+ return 0;
}
/**
@@ -201,21 +256,33 @@
int fwu_get_mdata(struct fwu_mdata *mdata)
{
int err;
+ uint32_t mdata_size;
bool parts_ok[2] = { false };
- struct fwu_mdata s, *parts_mdata[2];
+ struct fwu_mdata *parts_mdata[2];
- parts_mdata[0] = &g_mdata;
- parts_mdata[1] = &s;
+ err = fwu_get_mdata_size(&mdata_size);
+ if (err)
+ return err;
+
+ parts_mdata[0] = g_fwu_data.fwu_mdata;
+ if (!parts_mdata[0]) {
+ log_err("Memory not allocated for the FWU Metadata copies\n");
+ return -ENOMEM;
+ }
+
+ parts_mdata[1] = (struct fwu_mdata *)((char *)parts_mdata[0] +
+ mdata_size);
/* if mdata already read and ready */
err = mdata_crc_check(parts_mdata[0]);
if (!err)
goto ret_mdata;
- /* else read, verify and, if needed, fix mdata */
+
+ /* else read, verify and, if needed, fix mdata */
for (int i = 0; i < 2; i++) {
parts_ok[i] = false;
- err = fwu_read_mdata(g_dev, parts_mdata[i], !i);
+ err = fwu_read_mdata(g_dev, parts_mdata[i], !i, mdata_size);
if (!err) {
err = mdata_crc_check(parts_mdata[i]);
if (!err)
@@ -230,7 +297,7 @@
* Before returning, check that both the
* FWU metadata copies are the same.
*/
- err = memcmp(parts_mdata[0], parts_mdata[1], sizeof(struct fwu_mdata));
+ err = memcmp(parts_mdata[0], parts_mdata[1], mdata_size);
if (!err)
goto ret_mdata;
@@ -247,7 +314,7 @@
if (parts_ok[i])
continue;
- memcpy(parts_mdata[i], parts_mdata[1 - i], sizeof(struct fwu_mdata));
+ memcpy(parts_mdata[i], parts_mdata[1 - i], mdata_size);
err = fwu_sync_mdata(parts_mdata[i], i ? SECONDARY_PART : PRIMARY_PART);
if (err) {
log_debug("mdata : %s write failed\n", i ? "secondary" : "primary");
@@ -257,7 +324,7 @@
ret_mdata:
if (!err && mdata)
- memcpy(mdata, parts_mdata[0], sizeof(struct fwu_mdata));
+ memcpy(mdata, parts_mdata[0], mdata_size);
return err;
}
@@ -275,13 +342,13 @@
int fwu_get_active_index(uint *active_idx)
{
int ret = 0;
- struct fwu_mdata *mdata = &g_mdata;
+ struct fwu_data *data = &g_fwu_data;
/*
* Found the FWU metadata partition, now read the active_index
* value
*/
- *active_idx = mdata->active_index;
+ *active_idx = data->active_index;
if (*active_idx >= CONFIG_FWU_NUM_BANKS) {
log_debug("Active index value read is incorrect\n");
ret = -EINVAL;
@@ -302,7 +369,7 @@
int fwu_set_active_index(uint active_idx)
{
int ret;
- struct fwu_mdata *mdata = &g_mdata;
+ struct fwu_data *data = &g_fwu_data;
if (active_idx >= CONFIG_FWU_NUM_BANKS) {
log_debug("Invalid active index value\n");
@@ -313,14 +380,16 @@
* Update the active index and previous_active_index fields
* in the FWU metadata
*/
- mdata->previous_active_index = mdata->active_index;
- mdata->active_index = active_idx;
+ data->previous_active_index = data->active_index;
+ data->active_index = active_idx;
+
+ fwu_populate_mdata_bank_index(data);
/*
* Now write this updated FWU metadata to both the
* FWU metadata partitions
*/
- ret = fwu_sync_mdata(mdata, BOTH_PARTS);
+ ret = fwu_sync_mdata(data->fwu_mdata, BOTH_PARTS);
if (ret) {
log_debug("Failed to update FWU metadata partitions\n");
ret = -EIO;
@@ -346,7 +415,7 @@
int ret, i;
uint update_bank;
efi_guid_t *image_guid, image_type_id;
- struct fwu_mdata *mdata = &g_mdata;
+ struct fwu_data *data = &g_fwu_data;
struct fwu_image_entry *img_entry;
struct fwu_image_bank_info *img_bank_info;
@@ -365,15 +434,15 @@
ret = -EINVAL;
/*
- * The FWU metadata has been read. Now get the image_uuid for the
+ * The FWU metadata has been read. Now get the image_guid for the
* image with the update_bank.
*/
for (i = 0; i < CONFIG_FWU_NUM_IMAGES_PER_BANK; i++) {
if (!guidcmp(&image_type_id,
- &mdata->img_entry[i].image_type_uuid)) {
- img_entry = &mdata->img_entry[i];
+ &data->fwu_images[i].image_type_guid)) {
+ img_entry = &data->fwu_images[i];
img_bank_info = &img_entry->img_bank_info[update_bank];
- image_guid = &img_bank_info->image_uuid;
+ image_guid = &img_bank_info->image_guid;
ret = fwu_plat_get_alt_num(g_dev, image_guid, alt_num);
if (ret)
log_debug("alt_num not found for partition with GUID %pUs\n",
@@ -407,21 +476,23 @@
{
int ret;
u32 cur_active_index;
- struct fwu_mdata *mdata = &g_mdata;
+ struct fwu_data *data = &g_fwu_data;
/*
* Swap the active index and previous_active_index fields
* in the FWU metadata
*/
- cur_active_index = mdata->active_index;
- mdata->active_index = mdata->previous_active_index;
- mdata->previous_active_index = cur_active_index;
+ cur_active_index = data->active_index;
+ data->active_index = data->previous_active_index;
+ data->previous_active_index = cur_active_index;
+
+ fwu_populate_mdata_bank_index(data);
/*
* Now write this updated FWU metadata to both the
* FWU metadata partitions
*/
- ret = fwu_sync_mdata(mdata, BOTH_PARTS);
+ ret = fwu_sync_mdata(data->fwu_mdata, BOTH_PARTS);
if (ret) {
log_debug("Failed to update FWU metadata partitions\n");
ret = -EIO;
@@ -448,20 +519,21 @@
static int fwu_clrset_image_accept(efi_guid_t *img_type_id, u32 bank, u8 action)
{
int ret, i;
- struct fwu_mdata *mdata = &g_mdata;
+ struct fwu_data *data = &g_fwu_data;
struct fwu_image_entry *img_entry;
struct fwu_image_bank_info *img_bank_info;
- img_entry = &mdata->img_entry[0];
+ img_entry = &data->fwu_images[0];
for (i = 0; i < CONFIG_FWU_NUM_IMAGES_PER_BANK; i++) {
- if (!guidcmp(&img_entry[i].image_type_uuid, img_type_id)) {
+ if (!guidcmp(&img_entry[i].image_type_guid, img_type_id)) {
img_bank_info = &img_entry[i].img_bank_info[bank];
if (action == IMAGE_ACCEPT_SET)
img_bank_info->accepted |= FWU_IMAGE_ACCEPTED;
else
img_bank_info->accepted = 0;
- ret = fwu_sync_mdata(mdata, BOTH_PARTS);
+ fwu_populate_mdata_image_info(data);
+ ret = fwu_sync_mdata(data->fwu_mdata, BOTH_PARTS);
goto out;
}
}
@@ -627,9 +699,9 @@
return 0;
}
- ret = fwu_get_mdata(NULL);
+ ret = fwu_init();
if (ret) {
- log_debug("Unable to read meta-data\n");
+ log_debug("fwu_init() failed\n");
return ret;
}
@@ -665,7 +737,7 @@
if (efi_init_obj_list() != EFI_SUCCESS)
return 0;
- in_trial = in_trial_state(&g_mdata);
+ in_trial = in_trial_state();
if (!in_trial || (ret = fwu_trial_count_update()) > 0)
ret = trial_counter_update(NULL);
diff --git a/lib/fwu_updates/fwu_mtd.c b/lib/fwu_updates/fwu_mtd.c
index 69cd3d7..ccaba3f 100644
--- a/lib/fwu_updates/fwu_mtd.c
+++ b/lib/fwu_updates/fwu_mtd.c
@@ -11,20 +11,25 @@
#include <malloc.h>
#include <mtd.h>
#include <uuid.h>
-#include <vsprintf.h>
+#include <stdio.h>
#include <dm/ofnode.h>
-struct fwu_mtd_image_info
-fwu_mtd_images[CONFIG_FWU_NUM_BANKS * CONFIG_FWU_NUM_IMAGES_PER_BANK];
-
static struct fwu_mtd_image_info *mtd_img_by_uuid(const char *uuidbuf)
{
- int num_images = ARRAY_SIZE(fwu_mtd_images);
+ int num_images;
+ struct fwu_mdata_mtd_priv *mtd_priv = dev_get_priv(fwu_get_dev());
+ struct fwu_mtd_image_info *image_info = mtd_priv->fwu_mtd_images;
+
+ if (!image_info)
+ return NULL;
+
+ num_images = CONFIG_FWU_NUM_BANKS *
+ CONFIG_FWU_NUM_IMAGES_PER_BANK;
for (int i = 0; i < num_images; i++)
- if (!strcmp(uuidbuf, fwu_mtd_images[i].uuidbuf))
- return &fwu_mtd_images[i];
+ if (!strcmp(uuidbuf, image_info[i].uuidbuf))
+ return &image_info[i];
return NULL;
}
@@ -107,7 +112,7 @@
return fwu_mtd_get_alt_num(image_id, alt_num, "nor1");
}
-static int gen_image_alt_info(char *buf, size_t len, int sidx,
+static int gen_image_alt_info(char *buf, size_t len,
struct fwu_image_entry *img, struct mtd_info *mtd)
{
char *p = buf, *end = buf + len;
@@ -131,7 +136,7 @@
/* Query a partition by image UUID */
bank = &img->img_bank_info[i];
- uuid_bin_to_str(bank->image_uuid.b, uuidbuf, UUID_STR_FORMAT_STD);
+ uuid_bin_to_str(bank->image_guid.b, uuidbuf, UUID_STR_FORMAT_STD);
mtd_img_info = mtd_img_by_uuid(uuidbuf);
if (!mtd_img_info) {
@@ -158,18 +163,13 @@
int fwu_gen_alt_info_from_mtd(char *buf, size_t len, struct mtd_info *mtd)
{
- struct fwu_mdata mdata;
int i, l, ret;
-
- ret = fwu_get_mdata(&mdata);
- if (ret < 0) {
- log_err("Failed to get the FWU mdata.\n");
- return ret;
- }
+ struct fwu_data *data = fwu_get_data();
+ struct fwu_image_entry *img_entry;
for (i = 0; i < CONFIG_FWU_NUM_IMAGES_PER_BANK; i++) {
- ret = gen_image_alt_info(buf, len, i * CONFIG_FWU_NUM_BANKS,
- &mdata.img_entry[i], mtd);
+ img_entry = &data->fwu_images[i];
+ ret = gen_image_alt_info(buf, len, img_entry, mtd);
if (ret)
break;
diff --git a/lib/fwu_updates/fwu_v1.c b/lib/fwu_updates/fwu_v1.c
new file mode 100644
index 0000000..efb8d51
--- /dev/null
+++ b/lib/fwu_updates/fwu_v1.c
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2024, Linaro Limited
+ */
+
+#include <fwu.h>
+#include <fwu_mdata.h>
+
+#include <linux/types.h>
+
+#define FWU_MDATA_VERSION 0x1U
+
+static uint32_t fwu_check_trial_state(struct fwu_mdata *mdata, uint32_t bank)
+{
+ u32 i;
+ struct fwu_image_entry *img_entry;
+ struct fwu_image_bank_info *img_bank_info;
+
+ img_entry = &mdata->img_entry[0];
+ for (i = 0; i < CONFIG_FWU_NUM_IMAGES_PER_BANK; i++) {
+ img_bank_info = &img_entry[i].img_bank_info[bank];
+ if (!img_bank_info->accepted) {
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
+static void fwu_data_init(void)
+{
+ size_t image_info_size;
+ void *dst_img_info, *src_img_info;
+ struct fwu_data *data = fwu_get_data();
+ struct fwu_mdata *mdata = data->fwu_mdata;
+
+ data->crc32 = mdata->crc32;
+ data->version = mdata->version;
+ data->active_index = mdata->active_index;
+ data->previous_active_index = mdata->previous_active_index;
+
+ data->metadata_size = sizeof(struct fwu_mdata);
+ data->num_banks = CONFIG_FWU_NUM_BANKS;
+ data->num_images = CONFIG_FWU_NUM_IMAGES_PER_BANK;
+ fwu_plat_get_bootidx(&data->boot_index);
+ data->trial_state = fwu_check_trial_state(mdata, data->boot_index);
+
+ src_img_info = &mdata->img_entry[0];
+ dst_img_info = &data->fwu_images[0];
+ image_info_size = sizeof(data->fwu_images);
+
+ memcpy(dst_img_info, src_img_info, image_info_size);
+}
+
+static int fwu_trial_state_update(bool trial_state)
+{
+ int ret;
+ struct fwu_data *data = fwu_get_data();
+
+ if (trial_state) {
+ ret = fwu_trial_state_ctr_start();
+ if (ret)
+ return ret;
+ }
+
+ data->trial_state = trial_state;
+
+ return 0;
+}
+
+/**
+ * fwu_populate_mdata_image_info() - Populate the image information
+ * of the metadata
+ * @data: Version agnostic FWU metadata information
+ *
+ * Populate the image information in the FWU metadata by copying it
+ * from the version agnostic structure. This is done before the
+ * metadata gets written to the storage media.
+ *
+ * Return: None
+ */
+void fwu_populate_mdata_image_info(struct fwu_data *data)
+{
+ size_t image_info_size;
+ void *dst_img_info, *src_img_info;
+ struct fwu_mdata *mdata = data->fwu_mdata;
+
+ image_info_size = sizeof(data->fwu_images);
+ dst_img_info = &mdata->img_entry[0];
+ src_img_info = &data->fwu_images[0];
+
+ memcpy(dst_img_info, src_img_info, image_info_size);
+}
+
+/**
+ * fwu_state_machine_updates() - Update FWU state of the platform
+ * @trial_state: Is platform transitioning into Trial State
+ * @update_index: Bank number to which images have been updated
+ *
+ * On successful completion of updates, transition the platform to
+ * either Trial State or Regular State.
+ *
+ * To transition the platform to Trial State, start the
+ * TrialStateCtr counter, followed by setting the value of bank_state
+ * field of the metadata to Valid state(applicable only in version 2
+ * of metadata).
+ *
+ * In case, the platform is to transition directly to Regular State,
+ * update the bank_state field of the metadata to Accepted
+ * state(applicable only in version 2 of metadata).
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int fwu_state_machine_updates(bool trial_state,
+ __maybe_unused uint32_t update_index)
+{
+ return fwu_trial_state_update(trial_state);
+}
+
+/**
+ * fwu_get_mdata_size() - Get the FWU metadata size
+ * @mdata_size: Size of the metadata structure
+ *
+ * Get the size of the FWU metadata.
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int fwu_get_mdata_size(uint32_t *mdata_size)
+{
+ *mdata_size = sizeof(struct fwu_mdata);
+
+ return 0;
+}
+
+/**
+ * fwu_init() - FWU specific initialisations
+ *
+ * Carry out some FWU specific initialisations including allocation
+ * of memory for the metadata copies, and reading the FWU metadata
+ * copies into the allocated memory. The metadata fields are then
+ * copied into a version agnostic structure.
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int fwu_init(void)
+{
+ int ret;
+ uint32_t mdata_size;
+
+ fwu_get_mdata_size(&mdata_size);
+
+ ret = fwu_mdata_copies_allocate(mdata_size);
+ if (ret)
+ return ret;
+
+ /*
+ * Now read the entire structure, both copies, and
+ * validate that the copies.
+ */
+ ret = fwu_get_mdata(NULL);
+ if (ret)
+ return ret;
+
+ fwu_data_init();
+
+ return 0;
+}
diff --git a/lib/fwu_updates/fwu_v2.c b/lib/fwu_updates/fwu_v2.c
new file mode 100644
index 0000000..108bc9b
--- /dev/null
+++ b/lib/fwu_updates/fwu_v2.c
@@ -0,0 +1,260 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2024, Linaro Limited
+ */
+
+#include <fwu.h>
+#include <fwu_mdata.h>
+#include <log.h>
+
+#include <linux/types.h>
+
+#define FWU_MDATA_VERSION 0x2U
+
+static inline struct fwu_fw_store_desc *fwu_get_fw_desc(struct fwu_mdata *mdata)
+{
+ return (struct fwu_fw_store_desc *)((u8 *)mdata + sizeof(*mdata));
+}
+
+static uint32_t fwu_check_trial_state(struct fwu_mdata *mdata, uint32_t bank)
+{
+ return mdata->bank_state[bank] == FWU_BANK_VALID ? 1 : 0;
+}
+
+static void fwu_data_init(void)
+{
+ int i;
+ size_t image_info_size;
+ void *dst_img_info, *src_img_info;
+ struct fwu_data *data = fwu_get_data();
+ struct fwu_mdata *mdata = data->fwu_mdata;
+
+ data->crc32 = mdata->crc32;
+ data->version = mdata->version;
+ data->active_index = mdata->active_index;
+ data->previous_active_index = mdata->previous_active_index;
+ data->metadata_size = mdata->metadata_size;
+ fwu_plat_get_bootidx(&data->boot_index);
+ data->trial_state = fwu_check_trial_state(mdata, data->boot_index);
+
+ data->num_banks = fwu_get_fw_desc(mdata)->num_banks;
+ data->num_images = fwu_get_fw_desc(mdata)->num_images;
+
+ for (i = 0; i < 4; i++) {
+ data->bank_state[i] = mdata->bank_state[i];
+ }
+
+ image_info_size = sizeof(data->fwu_images);
+ src_img_info = &fwu_get_fw_desc(mdata)->img_entry[0];
+ dst_img_info = &data->fwu_images[0];
+
+ memcpy(dst_img_info, src_img_info, image_info_size);
+}
+
+static int fwu_mdata_sanity_checks(void)
+{
+ uint8_t num_banks;
+ uint16_t num_images;
+ struct fwu_data *data = fwu_get_data();
+ struct fwu_mdata *mdata = data->fwu_mdata;
+
+ if (mdata->version != FWU_MDATA_VERSION) {
+ log_err("FWU metadata version %u. Expected value of %u\n",
+ mdata->version, FWU_MDATA_VERSION);
+ return -EINVAL;
+ }
+
+ if (!mdata->desc_offset) {
+ log_err("No image information provided with the Metadata. ");
+ log_err("Image information expected in the metadata\n");
+ return -EINVAL;
+ }
+
+ if (mdata->desc_offset != 0x20) {
+ log_err("Descriptor Offset(0x%x) in the FWU Metadata not equal to 0x20\n",
+ mdata->desc_offset);
+ return -EINVAL;
+ }
+
+ num_banks = fwu_get_fw_desc(mdata)->num_banks;
+ num_images = fwu_get_fw_desc(mdata)->num_images;
+
+ if (num_banks != CONFIG_FWU_NUM_BANKS) {
+ log_err("Number of Banks(%u) in FWU Metadata different from the configured value(%d)",
+ num_banks, CONFIG_FWU_NUM_BANKS);
+ return -EINVAL;
+ }
+
+ if (num_images != CONFIG_FWU_NUM_IMAGES_PER_BANK) {
+ log_err("Number of Images(%u) in FWU Metadata different from the configured value(%d)",
+ num_images, CONFIG_FWU_NUM_IMAGES_PER_BANK);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int fwu_bank_state_update(bool trial_state, uint32_t bank)
+{
+ int ret;
+ struct fwu_data *data = fwu_get_data();
+ struct fwu_mdata *mdata = data->fwu_mdata;
+
+ mdata->bank_state[bank] = data->bank_state[bank] = trial_state ?
+ FWU_BANK_VALID : FWU_BANK_ACCEPTED;
+
+ ret = fwu_sync_mdata(mdata, BOTH_PARTS);
+ if (ret)
+ log_err("Unable to set bank_state for bank %u\n", bank);
+ else
+ data->trial_state = trial_state;
+
+ return ret;
+}
+
+static int fwu_trial_state_start(uint update_index)
+{
+ int ret;
+
+ ret = fwu_trial_state_ctr_start();
+ if (ret)
+ return ret;
+
+ ret = fwu_bank_state_update(1, update_index);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+/**
+ * fwu_populate_mdata_image_info() - Populate the image information
+ * of the metadata
+ * @data: Version agnostic FWU metadata information
+ *
+ * Populate the image information in the FWU metadata by copying it
+ * from the version agnostic structure. This is done before the
+ * metadata gets written to the storage media.
+ *
+ * Return: None
+ */
+void fwu_populate_mdata_image_info(struct fwu_data *data)
+{
+ size_t image_info_size;
+ struct fwu_mdata *mdata = data->fwu_mdata;
+ void *dst_img_info, *src_img_info;
+
+ image_info_size = sizeof(data->fwu_images);
+ dst_img_info = &fwu_get_fw_desc(mdata)->img_entry[0];
+ src_img_info = &data->fwu_images[0];
+
+ memcpy(dst_img_info, src_img_info, image_info_size);
+}
+
+/**
+ * fwu_state_machine_updates() - Update FWU state of the platform
+ * @trial_state: Is platform transitioning into Trial State
+ * @update_index: Bank number to which images have been updated
+ *
+ * On successful completion of updates, transition the platform to
+ * either Trial State or Regular State.
+ *
+ * To transition the platform to Trial State, start the
+ * TrialStateCtr counter, followed by setting the value of bank_state
+ * field of the metadata to Valid state(applicable only in version 2
+ * of metadata).
+ *
+ * In case, the platform is to transition directly to Regular State,
+ * update the bank_state field of the metadata to Accepted
+ * state(applicable only in version 2 of metadata).
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int fwu_state_machine_updates(bool trial_state, uint32_t update_index)
+{
+ return trial_state ? fwu_trial_state_start(update_index) :
+ fwu_bank_state_update(0, update_index);
+}
+
+/**
+ * fwu_get_mdata_size() - Get the FWU metadata size
+ * @mdata_size: Size of the metadata structure
+ *
+ * Get the size of the FWU metadata from the structure. This is later used
+ * to allocate memory for the structure.
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int fwu_get_mdata_size(uint32_t *mdata_size)
+{
+ int ret = 0;
+ struct fwu_mdata mdata = { 0 };
+ struct fwu_data *data = fwu_get_data();
+ struct udevice *fwu_dev = fwu_get_dev();
+
+ if (data->metadata_size) {
+ *mdata_size = data->metadata_size;
+ return 0;
+ }
+
+ ret = fwu_read_mdata(fwu_dev, &mdata, 1,
+ sizeof(struct fwu_mdata));
+ if (ret) {
+ log_err("FWU metadata read failed\n");
+ return ret;
+ }
+
+ *mdata_size = mdata.metadata_size;
+ if (!*mdata_size)
+ return -EINVAL;
+
+ return 0;
+}
+
+/**
+ * fwu_init() - FWU specific initialisations
+ *
+ * Carry out some FWU specific initialisations including allocation
+ * of memory for the metadata copies, and reading the FWU metadata
+ * copies into the allocated memory. The metadata fields are then
+ * copied into a version agnostic structure.
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int fwu_init(void)
+{
+ int ret;
+ struct fwu_mdata mdata = { 0 };
+ struct udevice *fwu_dev = fwu_get_dev();
+
+ /*
+ * First we read only the top level structure
+ * and get the size of the complete structure.
+ */
+ ret = fwu_read_mdata(fwu_dev, &mdata, 1,
+ sizeof(struct fwu_mdata));
+ if (ret) {
+ log_err("FWU metadata read failed\n");
+ return ret;
+ }
+
+ ret = fwu_mdata_copies_allocate(mdata.metadata_size);
+ if (ret)
+ return ret;
+
+ /*
+ * Now read the entire structure, both copies, and
+ * validate that the copies.
+ */
+ ret = fwu_get_mdata(NULL);
+ if (ret)
+ return ret;
+
+ ret = fwu_mdata_sanity_checks();
+ if (ret)
+ return ret;
+
+ fwu_data_init();
+
+ return 0;
+}
diff --git a/lib/hexdump.c b/lib/hexdump.c
index 33e3e6e..2bc508f 100644
--- a/lib/hexdump.c
+++ b/lib/hexdump.c
@@ -10,7 +10,7 @@
#include <hexdump.h>
#include <mapmem.h>
-#include <vsprintf.h>
+#include <stdio.h>
#include <linux/ctype.h>
#include <linux/compat.h>
#include <linux/log2.h>
diff --git a/lib/initcall.c b/lib/initcall.c
index c8e2b0f..2686b9a 100644
--- a/lib/initcall.c
+++ b/lib/initcall.c
@@ -49,13 +49,14 @@
*/
int initcall_run_list(const init_fnc_t init_sequence[])
{
- ulong reloc_ofs = calc_reloc_ofs();
+ ulong reloc_ofs;
const init_fnc_t *ptr;
enum event_t type;
init_fnc_t func;
int ret = 0;
for (ptr = init_sequence; func = *ptr, func; ptr++) {
+ reloc_ofs = calc_reloc_ofs();
type = initcall_is_event(func);
if (type) {
@@ -84,7 +85,8 @@
sprintf(buf, "event %d/%s", type,
event_type_name(type));
} else {
- sprintf(buf, "call %p", func);
+ sprintf(buf, "call %p",
+ (char *)func - reloc_ofs);
}
printf("initcall failed at %s (err=%dE)\n", buf, ret);
diff --git a/lib/md5.c b/lib/md5.c
index faf3f78..34343cf 100644
--- a/lib/md5.c
+++ b/lib/md5.c
@@ -55,7 +55,7 @@
* initialization constants.
*/
void
-MD5Init(struct MD5Context *ctx)
+MD5Init(MD5Context *ctx)
{
ctx->buf[0] = 0x67452301;
ctx->buf[1] = 0xefcdab89;
@@ -71,7 +71,7 @@
* of bytes.
*/
void
-MD5Update(struct MD5Context *ctx, unsigned char const *buf, unsigned len)
+MD5Update(MD5Context *ctx, unsigned char const *buf, unsigned int len)
{
register __u32 t;
@@ -120,7 +120,7 @@
* 1 0* (64-bit count of bits processed, MSB-first)
*/
void
-MD5Final(unsigned char digest[16], struct MD5Context *ctx)
+MD5Final(unsigned char digest[16], MD5Context *ctx)
{
unsigned int count;
unsigned char *p;
@@ -269,7 +269,7 @@
void
md5 (unsigned char *input, int len, unsigned char output[16])
{
- struct MD5Context context;
+ MD5Context context;
MD5Init(&context);
MD5Update(&context, input, len);
@@ -286,7 +286,7 @@
md5_wd(const unsigned char *input, unsigned int len, unsigned char output[16],
unsigned int chunk_sz)
{
- struct MD5Context context;
+ MD5Context context;
#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
const unsigned char *end, *curr;
int chunk;
diff --git a/lib/smbios.c b/lib/smbios.c
index b190b01..4126466 100644
--- a/lib/smbios.c
+++ b/lib/smbios.c
@@ -5,6 +5,8 @@
* Adapted from coreboot src/arch/x86/smbios.c
*/
+#define LOG_CATEGORY LOGC_BOARD
+
#include <dm.h>
#include <env.h>
#include <linux/stringify.h>
@@ -383,8 +385,12 @@
memset(t, 0, sizeof(struct smbios_type1));
fill_smbios_header(t, SMBIOS_SYSTEM_INFORMATION, len, handle);
smbios_set_eos(ctx, t->eos);
- t->manufacturer = smbios_add_prop(ctx, "manufacturer", NULL);
- t->product_name = smbios_add_prop(ctx, "product", NULL);
+ t->manufacturer = smbios_add_prop_si(ctx, "manufacturer",
+ SYSINFO_ID_SMBIOS_SYSTEM_MANUFACTURER,
+ NULL);
+ t->product_name = smbios_add_prop_si(ctx, "product",
+ SYSINFO_ID_SMBIOS_SYSTEM_PRODUCT,
+ NULL);
t->version = smbios_add_prop_si(ctx, "version",
SYSINFO_ID_SMBIOS_SYSTEM_VERSION,
NULL);
@@ -392,11 +398,15 @@
t->serial_number = smbios_add_prop(ctx, NULL, serial_str);
strncpy((char *)t->uuid, serial_str, sizeof(t->uuid));
} else {
- t->serial_number = smbios_add_prop(ctx, "serial", NULL);
+ t->serial_number = smbios_add_prop_si(ctx, "serial",
+ SYSINFO_ID_SMBIOS_SYSTEM_SERIAL,
+ NULL);
}
t->wakeup_type = SMBIOS_WAKEUP_TYPE_UNKNOWN;
- t->sku_number = smbios_add_prop(ctx, "sku", NULL);
- t->family = smbios_add_prop(ctx, "family", NULL);
+ t->sku_number = smbios_add_prop_si(ctx, "sku",
+ SYSINFO_ID_SMBIOS_SYSTEM_SKU, NULL);
+ t->family = smbios_add_prop_si(ctx, "family",
+ SYSINFO_ID_SMBIOS_SYSTEM_FAMILY, NULL);
len = t->length + smbios_string_table_len(ctx);
*current += len;
@@ -415,12 +425,22 @@
memset(t, 0, sizeof(struct smbios_type2));
fill_smbios_header(t, SMBIOS_BOARD_INFORMATION, len, handle);
smbios_set_eos(ctx, t->eos);
- t->manufacturer = smbios_add_prop(ctx, "manufacturer", NULL);
- t->product_name = smbios_add_prop(ctx, "product", NULL);
+ t->manufacturer = smbios_add_prop_si(ctx, "manufacturer",
+ SYSINFO_ID_SMBIOS_BASEBOARD_MANUFACTURER,
+ NULL);
+ t->product_name = smbios_add_prop_si(ctx, "product",
+ SYSINFO_ID_SMBIOS_BASEBOARD_PRODUCT,
+ NULL);
t->version = smbios_add_prop_si(ctx, "version",
SYSINFO_ID_SMBIOS_BASEBOARD_VERSION,
NULL);
- t->asset_tag_number = smbios_add_prop(ctx, "asset-tag", NULL);
+
+ t->serial_number = smbios_add_prop_si(ctx, "serial",
+ SYSINFO_ID_SMBIOS_BASEBOARD_SERIAL,
+ NULL);
+ t->asset_tag_number = smbios_add_prop_si(ctx, "asset-tag",
+ SYSINFO_ID_SMBIOS_BASEBOARD_ASSET_TAG,
+ NULL);
t->feature_flags = SMBIOS_BOARD_FEATURE_HOSTING;
t->board_type = SMBIOS_BOARD_MOTHERBOARD;
t->chassis_handle = handle + 1;
@@ -571,10 +591,20 @@
int i;
ctx.node = ofnode_null();
- if (IS_ENABLED(CONFIG_OF_CONTROL)) {
+ if (IS_ENABLED(CONFIG_OF_CONTROL) && CONFIG_IS_ENABLED(SYSINFO)) {
uclass_first_device(UCLASS_SYSINFO, &ctx.dev);
- if (ctx.dev)
+ if (ctx.dev) {
+ int ret;
+
parent_node = dev_read_subnode(ctx.dev, "smbios");
+ ret = sysinfo_detect(ctx.dev);
+
+ /*
+ * ignore the error since many boards don't implement
+ * this and we can still use the info in the devicetree
+ */
+ ret = log_msg_ret("sys", ret);
+ }
} else {
ctx.dev = NULL;
}
diff --git a/lib/tpm-v2.c b/lib/tpm-v2.c
index 68eaaa6..59e6cba 100644
--- a/lib/tpm-v2.c
+++ b/lib/tpm-v2.c
@@ -10,6 +10,7 @@
#include <tpm_api.h>
#include <tpm-common.h>
#include <tpm-v2.h>
+#include <tpm_tcg2.h>
#include <u-boot/sha1.h>
#include <u-boot/sha256.h>
#include <u-boot/sha512.h>
@@ -22,683 +23,6 @@
#include "tpm-utils.h"
-const enum tpm2_algorithms tpm2_supported_algorithms[4] = {
- TPM2_ALG_SHA1,
- TPM2_ALG_SHA256,
- TPM2_ALG_SHA384,
- TPM2_ALG_SHA512,
-};
-
-int tcg2_get_active_pcr_banks(struct udevice *dev, u32 *active_pcr_banks)
-{
- u32 supported = 0;
- u32 pcr_banks = 0;
- u32 active = 0;
- int rc;
-
- rc = tpm2_get_pcr_info(dev, &supported, &active, &pcr_banks);
- if (rc)
- return rc;
-
- *active_pcr_banks = active;
-
- return 0;
-}
-
-u32 tcg2_event_get_size(struct tpml_digest_values *digest_list)
-{
- u32 len;
- size_t i;
-
- len = offsetof(struct tcg_pcr_event2, digests);
- len += offsetof(struct tpml_digest_values, digests);
- for (i = 0; i < digest_list->count; ++i) {
- u16 l = tpm2_algorithm_to_len(digest_list->digests[i].hash_alg);
-
- if (!l)
- continue;
-
- len += l + offsetof(struct tpmt_ha, digest);
- }
- len += sizeof(u32);
-
- return len;
-}
-
-int tcg2_create_digest(struct udevice *dev, const u8 *input, u32 length,
- struct tpml_digest_values *digest_list)
-{
- u8 final[sizeof(union tpmu_ha)];
- sha256_context ctx_256;
- sha512_context ctx_512;
- sha1_context ctx;
- u32 active;
- size_t i;
- u32 len;
- int rc;
-
- rc = tcg2_get_active_pcr_banks(dev, &active);
- if (rc)
- return rc;
-
- digest_list->count = 0;
- for (i = 0; i < ARRAY_SIZE(tpm2_supported_algorithms); ++i) {
- u32 mask =
- tpm2_algorithm_to_mask(tpm2_supported_algorithms[i]);
-
- if (!(active & mask))
- continue;
-
- switch (tpm2_supported_algorithms[i]) {
- case TPM2_ALG_SHA1:
- sha1_starts(&ctx);
- sha1_update(&ctx, input, length);
- sha1_finish(&ctx, final);
- len = TPM2_SHA1_DIGEST_SIZE;
- break;
- case TPM2_ALG_SHA256:
- sha256_starts(&ctx_256);
- sha256_update(&ctx_256, input, length);
- sha256_finish(&ctx_256, final);
- len = TPM2_SHA256_DIGEST_SIZE;
- break;
- case TPM2_ALG_SHA384:
- sha384_starts(&ctx_512);
- sha384_update(&ctx_512, input, length);
- sha384_finish(&ctx_512, final);
- len = TPM2_SHA384_DIGEST_SIZE;
- break;
- case TPM2_ALG_SHA512:
- sha512_starts(&ctx_512);
- sha512_update(&ctx_512, input, length);
- sha512_finish(&ctx_512, final);
- len = TPM2_SHA512_DIGEST_SIZE;
- break;
- default:
- printf("%s: unsupported algorithm %x\n", __func__,
- tpm2_supported_algorithms[i]);
- continue;
- }
-
- digest_list->digests[digest_list->count].hash_alg =
- tpm2_supported_algorithms[i];
- memcpy(&digest_list->digests[digest_list->count].digest, final,
- len);
- digest_list->count++;
- }
-
- return 0;
-}
-
-void tcg2_log_append(u32 pcr_index, u32 event_type,
- struct tpml_digest_values *digest_list, u32 size,
- const u8 *event, u8 *log)
-{
- size_t len;
- size_t pos;
- u32 i;
-
- pos = offsetof(struct tcg_pcr_event2, pcr_index);
- put_unaligned_le32(pcr_index, log);
- pos = offsetof(struct tcg_pcr_event2, event_type);
- put_unaligned_le32(event_type, log + pos);
- pos = offsetof(struct tcg_pcr_event2, digests) +
- offsetof(struct tpml_digest_values, count);
- put_unaligned_le32(digest_list->count, log + pos);
-
- pos = offsetof(struct tcg_pcr_event2, digests) +
- offsetof(struct tpml_digest_values, digests);
- for (i = 0; i < digest_list->count; ++i) {
- u16 hash_alg = digest_list->digests[i].hash_alg;
-
- len = tpm2_algorithm_to_len(hash_alg);
- if (!len)
- continue;
-
- pos += offsetof(struct tpmt_ha, hash_alg);
- put_unaligned_le16(hash_alg, log + pos);
- pos += offsetof(struct tpmt_ha, digest);
- memcpy(log + pos, (u8 *)&digest_list->digests[i].digest, len);
- pos += len;
- }
-
- put_unaligned_le32(size, log + pos);
- pos += sizeof(u32);
- memcpy(log + pos, event, size);
-}
-
-static int tcg2_log_append_check(struct tcg2_event_log *elog, u32 pcr_index,
- u32 event_type,
- struct tpml_digest_values *digest_list,
- u32 size, const u8 *event)
-{
- u32 event_size;
- u8 *log;
-
- event_size = size + tcg2_event_get_size(digest_list);
- if (elog->log_position + event_size > elog->log_size) {
- printf("%s: log too large: %u + %u > %u\n", __func__,
- elog->log_position, event_size, elog->log_size);
- return -ENOBUFS;
- }
-
- log = elog->log + elog->log_position;
- elog->log_position += event_size;
-
- tcg2_log_append(pcr_index, event_type, digest_list, size, event, log);
-
- return 0;
-}
-
-static int tcg2_log_init(struct udevice *dev, struct tcg2_event_log *elog)
-{
- struct tcg_efi_spec_id_event *ev;
- struct tcg_pcr_event *log;
- u32 event_size;
- u32 count = 0;
- u32 log_size;
- u32 active;
- u32 mask;
- size_t i;
- u16 len;
- int rc;
-
- rc = tcg2_get_active_pcr_banks(dev, &active);
- if (rc)
- return rc;
-
- event_size = offsetof(struct tcg_efi_spec_id_event, digest_sizes);
- for (i = 0; i < ARRAY_SIZE(tpm2_supported_algorithms); ++i) {
- mask = tpm2_algorithm_to_mask(tpm2_supported_algorithms[i]);
-
- if (!(active & mask))
- continue;
-
- switch (tpm2_supported_algorithms[i]) {
- case TPM2_ALG_SHA1:
- case TPM2_ALG_SHA256:
- case TPM2_ALG_SHA384:
- case TPM2_ALG_SHA512:
- count++;
- break;
- default:
- continue;
- }
- }
-
- event_size += 1 +
- (sizeof(struct tcg_efi_spec_id_event_algorithm_size) * count);
- log_size = offsetof(struct tcg_pcr_event, event) + event_size;
-
- if (log_size > elog->log_size) {
- printf("%s: log too large: %u > %u\n", __func__, log_size,
- elog->log_size);
- return -ENOBUFS;
- }
-
- log = (struct tcg_pcr_event *)elog->log;
- put_unaligned_le32(0, &log->pcr_index);
- put_unaligned_le32(EV_NO_ACTION, &log->event_type);
- memset(&log->digest, 0, sizeof(log->digest));
- put_unaligned_le32(event_size, &log->event_size);
-
- ev = (struct tcg_efi_spec_id_event *)log->event;
- strlcpy((char *)ev->signature, TCG_EFI_SPEC_ID_EVENT_SIGNATURE_03,
- sizeof(ev->signature));
- put_unaligned_le32(0, &ev->platform_class);
- ev->spec_version_minor = TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MINOR_TPM2;
- ev->spec_version_major = TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MAJOR_TPM2;
- ev->spec_errata = TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_ERRATA_TPM2;
- ev->uintn_size = sizeof(size_t) / sizeof(u32);
- put_unaligned_le32(count, &ev->number_of_algorithms);
-
- count = 0;
- for (i = 0; i < ARRAY_SIZE(tpm2_supported_algorithms); ++i) {
- mask = tpm2_algorithm_to_mask(tpm2_supported_algorithms[i]);
-
- if (!(active & mask))
- continue;
-
- len = tpm2_algorithm_to_len(tpm2_supported_algorithms[i]);
- if (!len)
- continue;
-
- put_unaligned_le16(tpm2_supported_algorithms[i],
- &ev->digest_sizes[count].algorithm_id);
- put_unaligned_le16(len, &ev->digest_sizes[count].digest_size);
- count++;
- }
-
- *((u8 *)ev + (event_size - 1)) = 0;
- elog->log_position = log_size;
-
- return 0;
-}
-
-static int tcg2_replay_eventlog(struct tcg2_event_log *elog,
- struct udevice *dev,
- struct tpml_digest_values *digest_list,
- u32 log_position)
-{
- const u32 offset = offsetof(struct tcg_pcr_event2, digests) +
- offsetof(struct tpml_digest_values, digests);
- u32 event_size;
- u32 count;
- u16 algo;
- u32 pcr;
- u32 pos;
- u16 len;
- u8 *log;
- int rc;
- u32 i;
-
- while (log_position + offset < elog->log_size) {
- log = elog->log + log_position;
-
- pos = offsetof(struct tcg_pcr_event2, pcr_index);
- pcr = get_unaligned_le32(log + pos);
- pos = offsetof(struct tcg_pcr_event2, event_type);
- if (!get_unaligned_le32(log + pos))
- return 0;
-
- pos = offsetof(struct tcg_pcr_event2, digests) +
- offsetof(struct tpml_digest_values, count);
- count = get_unaligned_le32(log + pos);
- if (count > ARRAY_SIZE(tpm2_supported_algorithms) ||
- (digest_list->count && digest_list->count != count))
- return 0;
-
- pos = offsetof(struct tcg_pcr_event2, digests) +
- offsetof(struct tpml_digest_values, digests);
- for (i = 0; i < count; ++i) {
- pos += offsetof(struct tpmt_ha, hash_alg);
- if (log_position + pos + sizeof(u16) >= elog->log_size)
- return 0;
-
- algo = get_unaligned_le16(log + pos);
- pos += offsetof(struct tpmt_ha, digest);
- switch (algo) {
- case TPM2_ALG_SHA1:
- case TPM2_ALG_SHA256:
- case TPM2_ALG_SHA384:
- case TPM2_ALG_SHA512:
- len = tpm2_algorithm_to_len(algo);
- break;
- default:
- return 0;
- }
-
- if (digest_list->count) {
- if (algo != digest_list->digests[i].hash_alg ||
- log_position + pos + len >= elog->log_size)
- return 0;
-
- memcpy(digest_list->digests[i].digest.sha512,
- log + pos, len);
- }
-
- pos += len;
- }
-
- if (log_position + pos + sizeof(u32) >= elog->log_size)
- return 0;
-
- event_size = get_unaligned_le32(log + pos);
- pos += event_size + sizeof(u32);
- if (log_position + pos > elog->log_size)
- return 0;
-
- if (digest_list->count) {
- rc = tcg2_pcr_extend(dev, pcr, digest_list);
- if (rc)
- return rc;
- }
-
- log_position += pos;
- }
-
- elog->log_position = log_position;
- elog->found = true;
- return 0;
-}
-
-static int tcg2_log_parse(struct udevice *dev, struct tcg2_event_log *elog)
-{
- struct tpml_digest_values digest_list;
- struct tcg_efi_spec_id_event *event;
- struct tcg_pcr_event *log;
- u32 log_active;
- u32 calc_size;
- u32 active;
- u32 count;
- u32 evsz;
- u32 mask;
- u16 algo;
- u16 len;
- int rc;
- u32 i;
- u16 j;
-
- if (elog->log_size <= offsetof(struct tcg_pcr_event, event))
- return 0;
-
- log = (struct tcg_pcr_event *)elog->log;
- if (get_unaligned_le32(&log->pcr_index) != 0 ||
- get_unaligned_le32(&log->event_type) != EV_NO_ACTION)
- return 0;
-
- for (i = 0; i < sizeof(log->digest); i++) {
- if (log->digest[i])
- return 0;
- }
-
- evsz = get_unaligned_le32(&log->event_size);
- if (evsz < offsetof(struct tcg_efi_spec_id_event, digest_sizes) ||
- evsz + offsetof(struct tcg_pcr_event, event) > elog->log_size)
- return 0;
-
- event = (struct tcg_efi_spec_id_event *)log->event;
- if (memcmp(event->signature, TCG_EFI_SPEC_ID_EVENT_SIGNATURE_03,
- sizeof(TCG_EFI_SPEC_ID_EVENT_SIGNATURE_03)))
- return 0;
-
- if (event->spec_version_minor != TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MINOR_TPM2 ||
- event->spec_version_major != TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MAJOR_TPM2)
- return 0;
-
- count = get_unaligned_le32(&event->number_of_algorithms);
- if (count > ARRAY_SIZE(tpm2_supported_algorithms))
- return 0;
-
- calc_size = offsetof(struct tcg_efi_spec_id_event, digest_sizes) +
- (sizeof(struct tcg_efi_spec_id_event_algorithm_size) * count) +
- 1;
- if (evsz != calc_size)
- return 0;
-
- rc = tcg2_get_active_pcr_banks(dev, &active);
- if (rc)
- return rc;
-
- digest_list.count = 0;
- log_active = 0;
-
- for (i = 0; i < count; ++i) {
- algo = get_unaligned_le16(&event->digest_sizes[i].algorithm_id);
- mask = tpm2_algorithm_to_mask(algo);
-
- if (!(active & mask))
- return 0;
-
- switch (algo) {
- case TPM2_ALG_SHA1:
- case TPM2_ALG_SHA256:
- case TPM2_ALG_SHA384:
- case TPM2_ALG_SHA512:
- len = get_unaligned_le16(&event->digest_sizes[i].digest_size);
- if (tpm2_algorithm_to_len(algo) != len)
- return 0;
- digest_list.digests[digest_list.count++].hash_alg = algo;
- break;
- default:
- return 0;
- }
-
- log_active |= mask;
- }
-
- /* Ensure the previous firmware extended all the PCRs. */
- if (log_active != active)
- return 0;
-
- /* Read PCR0 to check if previous firmware extended the PCRs or not. */
- rc = tcg2_pcr_read(dev, 0, &digest_list);
- if (rc)
- return rc;
-
- for (i = 0; i < digest_list.count; ++i) {
- len = tpm2_algorithm_to_len(digest_list.digests[i].hash_alg);
- for (j = 0; j < len; ++j) {
- if (digest_list.digests[i].digest.sha512[j])
- break;
- }
-
- /* PCR is non-zero; it has been extended, so skip extending. */
- if (j != len) {
- digest_list.count = 0;
- break;
- }
- }
-
- return tcg2_replay_eventlog(elog, dev, &digest_list,
- offsetof(struct tcg_pcr_event, event) +
- evsz);
-}
-
-int tcg2_pcr_extend(struct udevice *dev, u32 pcr_index,
- struct tpml_digest_values *digest_list)
-{
- u32 rc;
- u32 i;
-
- for (i = 0; i < digest_list->count; i++) {
- u32 alg = digest_list->digests[i].hash_alg;
-
- rc = tpm2_pcr_extend(dev, pcr_index, alg,
- (u8 *)&digest_list->digests[i].digest,
- tpm2_algorithm_to_len(alg));
- if (rc) {
- printf("%s: error pcr:%u alg:%08x\n", __func__,
- pcr_index, alg);
- return rc;
- }
- }
-
- return 0;
-}
-
-int tcg2_pcr_read(struct udevice *dev, u32 pcr_index,
- struct tpml_digest_values *digest_list)
-{
- struct tpm_chip_priv *priv;
- u32 rc;
- u32 i;
-
- priv = dev_get_uclass_priv(dev);
- if (!priv)
- return -ENODEV;
-
- for (i = 0; i < digest_list->count; i++) {
- u32 alg = digest_list->digests[i].hash_alg;
- u8 *digest = (u8 *)&digest_list->digests[i].digest;
-
- rc = tpm2_pcr_read(dev, pcr_index, priv->pcr_select_min, alg,
- digest, tpm2_algorithm_to_len(alg), NULL);
- if (rc) {
- printf("%s: error pcr:%u alg:%08x\n", __func__,
- pcr_index, alg);
- return rc;
- }
- }
-
- return 0;
-}
-
-int tcg2_measure_data(struct udevice *dev, struct tcg2_event_log *elog,
- u32 pcr_index, u32 size, const u8 *data, u32 event_type,
- u32 event_size, const u8 *event)
-{
- struct tpml_digest_values digest_list;
- int rc;
-
- if (data)
- rc = tcg2_create_digest(dev, data, size, &digest_list);
- else
- rc = tcg2_create_digest(dev, event, event_size, &digest_list);
- if (rc)
- return rc;
-
- rc = tcg2_pcr_extend(dev, pcr_index, &digest_list);
- if (rc)
- return rc;
-
- return tcg2_log_append_check(elog, pcr_index, event_type, &digest_list,
- event_size, event);
-}
-
-int tcg2_log_prepare_buffer(struct udevice *dev, struct tcg2_event_log *elog,
- bool ignore_existing_log)
-{
- struct tcg2_event_log log;
- int rc;
-
- elog->log_position = 0;
- elog->found = false;
-
- rc = tcg2_platform_get_log(dev, (void **)&log.log, &log.log_size);
- if (!rc) {
- log.log_position = 0;
- log.found = false;
-
- if (!ignore_existing_log) {
- rc = tcg2_log_parse(dev, &log);
- if (rc)
- return rc;
- }
-
- if (elog->log_size) {
- if (log.found) {
- if (elog->log_size < log.log_position)
- return -ENOSPC;
-
- /*
- * Copy the discovered log into the user buffer
- * if there's enough space.
- */
- memcpy(elog->log, log.log, log.log_position);
- }
-
- unmap_physmem(log.log, MAP_NOCACHE);
- } else {
- elog->log = log.log;
- elog->log_size = log.log_size;
- }
-
- elog->log_position = log.log_position;
- elog->found = log.found;
- }
-
- /*
- * Initialize the log buffer if no log was discovered and the buffer is
- * valid. User's can pass in their own buffer as a fallback if no
- * memory region is found.
- */
- if (!elog->found && elog->log_size)
- rc = tcg2_log_init(dev, elog);
-
- return rc;
-}
-
-int tcg2_measurement_init(struct udevice **dev, struct tcg2_event_log *elog,
- bool ignore_existing_log)
-{
- int rc;
-
- rc = tcg2_platform_get_tpm2(dev);
- if (rc)
- return rc;
-
- rc = tpm_auto_start(*dev);
- if (rc)
- return rc;
-
- rc = tcg2_log_prepare_buffer(*dev, elog, ignore_existing_log);
- if (rc) {
- tcg2_measurement_term(*dev, elog, true);
- return rc;
- }
-
- rc = tcg2_measure_event(*dev, elog, 0, EV_S_CRTM_VERSION,
- strlen(version_string) + 1,
- (u8 *)version_string);
- if (rc) {
- tcg2_measurement_term(*dev, elog, true);
- return rc;
- }
-
- return 0;
-}
-
-void tcg2_measurement_term(struct udevice *dev, struct tcg2_event_log *elog,
- bool error)
-{
- u32 event = error ? 0x1 : 0xffffffff;
- int i;
-
- for (i = 0; i < 8; ++i)
- tcg2_measure_event(dev, elog, i, EV_SEPARATOR, sizeof(event),
- (const u8 *)&event);
-
- if (elog->log)
- unmap_physmem(elog->log, MAP_NOCACHE);
-}
-
-__weak int tcg2_platform_get_log(struct udevice *dev, void **addr, u32 *size)
-{
- const __be32 *addr_prop;
- const __be32 *size_prop;
- int asize;
- int ssize;
-
- *addr = NULL;
- *size = 0;
-
- addr_prop = dev_read_prop(dev, "tpm_event_log_addr", &asize);
- if (!addr_prop)
- addr_prop = dev_read_prop(dev, "linux,sml-base", &asize);
-
- size_prop = dev_read_prop(dev, "tpm_event_log_size", &ssize);
- if (!size_prop)
- size_prop = dev_read_prop(dev, "linux,sml-size", &ssize);
-
- if (addr_prop && size_prop) {
- u64 a = of_read_number(addr_prop, asize / sizeof(__be32));
- u64 s = of_read_number(size_prop, ssize / sizeof(__be32));
-
- *addr = map_physmem(a, s, MAP_NOCACHE);
- *size = (u32)s;
- } else {
- struct ofnode_phandle_args args;
- phys_addr_t a;
- fdt_size_t s;
-
- if (dev_read_phandle_with_args(dev, "memory-region", NULL, 0,
- 0, &args))
- return -ENODEV;
-
- a = ofnode_get_addr_size(args.node, "reg", &s);
- if (a == FDT_ADDR_T_NONE)
- return -ENOMEM;
-
- *addr = map_physmem(a, s, MAP_NOCACHE);
- *size = (u32)s;
- }
-
- return 0;
-}
-
-__weak int tcg2_platform_get_tpm2(struct udevice **dev)
-{
- for_each_tpm_device(*dev) {
- if (tpm_get_version(*dev) == TPM_V2)
- return 0;
- }
-
- return -ENODEV;
-}
-
-__weak void tcg2_platform_startup_error(struct udevice *dev, int rc) {}
-
u32 tpm2_startup(struct udevice *dev, enum tpm2_startup_types mode)
{
const u8 command_v2[12] = {
@@ -872,6 +196,11 @@
if (!digest)
return -EINVAL;
+
+ if (!tpm2_allow_extend(dev)) {
+ log_err("Cannot extend PCRs if all the TPM enabled algorithms are not supported\n");
+ return -EINVAL;
+ }
/*
* Fill the command structure starting from the first buffer:
* - the digest
@@ -1071,48 +400,25 @@
return 0;
}
-static bool tpm2_is_active_pcr(struct tpms_pcr_selection *selection)
-{
- int i;
-
- /*
- * check the pcr_select. If at least one of the PCRs supports the
- * algorithm add it on the active ones
- */
- for (i = 0; i < selection->size_of_select; i++) {
- if (selection->pcr_select[i])
- return true;
- }
-
- return false;
-}
-
-int tpm2_get_pcr_info(struct udevice *dev, u32 *supported_pcr, u32 *active_pcr,
- u32 *pcr_banks)
+int tpm2_get_pcr_info(struct udevice *dev, struct tpml_pcr_selection *pcrs)
{
u8 response[(sizeof(struct tpms_capability_data) -
offsetof(struct tpms_capability_data, data))];
- struct tpml_pcr_selection pcrs;
u32 num_pcr;
size_t i;
u32 ret;
- *supported_pcr = 0;
- *active_pcr = 0;
- *pcr_banks = 0;
- memset(response, 0, sizeof(response));
ret = tpm2_get_capability(dev, TPM2_CAP_PCRS, 0, response, 1);
if (ret)
return ret;
- pcrs.count = get_unaligned_be32(response);
+ pcrs->count = get_unaligned_be32(response);
/*
- * We only support 5 algorithms for now so check against that
+ * We only support 4 algorithms for now so check against that
* instead of TPM2_NUM_PCR_BANKS
*/
- if (pcrs.count > ARRAY_SIZE(tpm2_supported_algorithms) ||
- pcrs.count < 1) {
- printf("%s: too many pcrs: %u\n", __func__, pcrs.count);
+ if (pcrs->count > 4 || pcrs->count < 1) {
+ printf("%s: too many pcrs: %u\n", __func__, pcrs->count);
return -EMSGSIZE;
}
@@ -1120,7 +426,7 @@
if (ret)
return ret;
- for (i = 0; i < pcrs.count; i++) {
+ for (i = 0; i < pcrs->count; i++) {
/*
* Definition of TPMS_PCR_SELECTION Structure
* hash: u16
@@ -1140,35 +446,20 @@
hash_offset + offsetof(struct tpms_pcr_selection,
pcr_select);
- pcrs.selection[i].hash =
+ pcrs->selection[i].hash =
get_unaligned_be16(response + hash_offset);
- pcrs.selection[i].size_of_select =
+ pcrs->selection[i].size_of_select =
__get_unaligned_be(response + size_select_offset);
- if (pcrs.selection[i].size_of_select > TPM2_PCR_SELECT_MAX) {
+ if (pcrs->selection[i].size_of_select > TPM2_PCR_SELECT_MAX) {
printf("%s: pcrs selection too large: %u\n", __func__,
- pcrs.selection[i].size_of_select);
+ pcrs->selection[i].size_of_select);
return -ENOBUFS;
}
/* copy the array of pcr_select */
- memcpy(pcrs.selection[i].pcr_select, response + pcr_select_offset,
- pcrs.selection[i].size_of_select);
+ memcpy(pcrs->selection[i].pcr_select, response + pcr_select_offset,
+ pcrs->selection[i].size_of_select);
}
- for (i = 0; i < pcrs.count; i++) {
- u32 hash_mask = tpm2_algorithm_to_mask(pcrs.selection[i].hash);
-
- if (hash_mask) {
- *supported_pcr |= hash_mask;
- if (tpm2_is_active_pcr(&pcrs.selection[i]))
- *active_pcr |= hash_mask;
- } else {
- printf("%s: unknown algorithm %x\n", __func__,
- pcrs.selection[i].hash);
- }
- }
-
- *pcr_banks = pcrs.count;
-
return 0;
}
@@ -1555,3 +846,71 @@
return 0;
}
+
+bool tpm2_is_active_pcr(struct tpms_pcr_selection *selection)
+{
+ int i;
+
+ for (i = 0; i < selection->size_of_select; i++) {
+ if (selection->pcr_select[i])
+ return true;
+ }
+
+ return false;
+}
+
+enum tpm2_algorithms tpm2_name_to_algorithm(const char *name)
+{
+ size_t i;
+
+ for (i = 0; i < ARRAY_SIZE(hash_algo_list); ++i) {
+ if (!strcasecmp(name, hash_algo_list[i].hash_name))
+ return hash_algo_list[i].hash_alg;
+ }
+ printf("%s: unsupported algorithm %s\n", __func__, name);
+
+ return -EINVAL;
+}
+
+const char *tpm2_algorithm_name(enum tpm2_algorithms algo)
+{
+ size_t i;
+
+ for (i = 0; i < ARRAY_SIZE(hash_algo_list); ++i) {
+ if (hash_algo_list[i].hash_alg == algo)
+ return hash_algo_list[i].hash_name;
+ }
+
+ return "";
+}
+
+u16 tpm2_algorithm_to_len(enum tpm2_algorithms algo)
+{
+ size_t i;
+
+ for (i = 0; i < ARRAY_SIZE(hash_algo_list); ++i) {
+ if (hash_algo_list[i].hash_alg == algo)
+ return hash_algo_list[i].hash_len;
+ }
+
+ return 0;
+}
+
+bool tpm2_allow_extend(struct udevice *dev)
+{
+ struct tpml_pcr_selection pcrs;
+ size_t i;
+ int rc;
+
+ rc = tpm2_get_pcr_info(dev, &pcrs);
+ if (rc)
+ return false;
+
+ for (i = 0; i < pcrs.count; i++) {
+ if (tpm2_is_active_pcr(&pcrs.selection[i]) &&
+ !tpm2_algorithm_to_len(pcrs.selection[i].hash))
+ return false;
+ }
+
+ return true;
+}
diff --git a/lib/tpm_tcg2.c b/lib/tpm_tcg2.c
new file mode 100644
index 0000000..7f868cc
--- /dev/null
+++ b/lib/tpm_tcg2.c
@@ -0,0 +1,731 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023 Linaro Limited
+ */
+
+#include <dm.h>
+#include <dm/of_access.h>
+#include <tpm_api.h>
+#include <tpm-common.h>
+#include <tpm-v2.h>
+#include <tpm_tcg2.h>
+#include <u-boot/sha1.h>
+#include <u-boot/sha256.h>
+#include <u-boot/sha512.h>
+#include <version_string.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <linux/unaligned/be_byteshift.h>
+#include <linux/unaligned/generic.h>
+#include <linux/unaligned/le_byteshift.h>
+#include "tpm-utils.h"
+
+int tcg2_get_pcr_info(struct udevice *dev, u32 *supported_pcr, u32 *active_pcr,
+ u32 *pcr_banks)
+{
+ u8 response[(sizeof(struct tpms_capability_data) -
+ offsetof(struct tpms_capability_data, data))];
+ struct tpml_pcr_selection pcrs;
+ size_t i;
+ u32 ret;
+
+ *supported_pcr = 0;
+ *active_pcr = 0;
+ *pcr_banks = 0;
+ memset(response, 0, sizeof(response));
+
+ ret = tpm2_get_pcr_info(dev, &pcrs);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < pcrs.count; i++) {
+ u32 hash_mask = tcg2_algorithm_to_mask(pcrs.selection[i].hash);
+
+ if (hash_mask) {
+ *supported_pcr |= hash_mask;
+ if (tpm2_is_active_pcr(&pcrs.selection[i]))
+ *active_pcr |= hash_mask;
+ } else {
+ printf("%s: unknown algorithm %x\n", __func__,
+ pcrs.selection[i].hash);
+ }
+ }
+
+ *pcr_banks = pcrs.count;
+
+ return 0;
+}
+
+int tcg2_get_active_pcr_banks(struct udevice *dev, u32 *active_pcr_banks)
+{
+ u32 supported = 0;
+ u32 pcr_banks = 0;
+ u32 active = 0;
+ int rc;
+
+ rc = tcg2_get_pcr_info(dev, &supported, &active, &pcr_banks);
+ if (rc)
+ return rc;
+
+ *active_pcr_banks = active;
+
+ return 0;
+}
+
+u32 tcg2_event_get_size(struct tpml_digest_values *digest_list)
+{
+ u32 len;
+ size_t i;
+
+ len = offsetof(struct tcg_pcr_event2, digests);
+ len += offsetof(struct tpml_digest_values, digests);
+ for (i = 0; i < digest_list->count; ++i) {
+ u16 l = tpm2_algorithm_to_len(digest_list->digests[i].hash_alg);
+
+ if (!l)
+ continue;
+
+ len += l + offsetof(struct tpmt_ha, digest);
+ }
+ len += sizeof(u32);
+
+ return len;
+}
+
+int tcg2_create_digest(struct udevice *dev, const u8 *input, u32 length,
+ struct tpml_digest_values *digest_list)
+{
+ u8 final[sizeof(union tpmu_ha)];
+ sha256_context ctx_256;
+ sha512_context ctx_512;
+ sha1_context ctx;
+ u32 active;
+ size_t i;
+ u32 len;
+ int rc;
+
+ rc = tcg2_get_active_pcr_banks(dev, &active);
+ if (rc)
+ return rc;
+
+ digest_list->count = 0;
+ for (i = 0; i < ARRAY_SIZE(hash_algo_list); ++i) {
+ if (!(active & hash_algo_list[i].hash_mask))
+ continue;
+
+ switch (hash_algo_list[i].hash_alg) {
+ case TPM2_ALG_SHA1:
+ sha1_starts(&ctx);
+ sha1_update(&ctx, input, length);
+ sha1_finish(&ctx, final);
+ len = TPM2_SHA1_DIGEST_SIZE;
+ break;
+ case TPM2_ALG_SHA256:
+ sha256_starts(&ctx_256);
+ sha256_update(&ctx_256, input, length);
+ sha256_finish(&ctx_256, final);
+ len = TPM2_SHA256_DIGEST_SIZE;
+ break;
+ case TPM2_ALG_SHA384:
+ sha384_starts(&ctx_512);
+ sha384_update(&ctx_512, input, length);
+ sha384_finish(&ctx_512, final);
+ len = TPM2_SHA384_DIGEST_SIZE;
+ break;
+ case TPM2_ALG_SHA512:
+ sha512_starts(&ctx_512);
+ sha512_update(&ctx_512, input, length);
+ sha512_finish(&ctx_512, final);
+ len = TPM2_SHA512_DIGEST_SIZE;
+ break;
+ default:
+ printf("%s: unsupported algorithm %x\n", __func__,
+ hash_algo_list[i].hash_alg);
+ continue;
+ }
+
+ digest_list->digests[digest_list->count].hash_alg =
+ hash_algo_list[i].hash_alg;
+ memcpy(&digest_list->digests[digest_list->count].digest, final,
+ len);
+ digest_list->count++;
+ }
+
+ return 0;
+}
+
+void tcg2_log_append(u32 pcr_index, u32 event_type,
+ struct tpml_digest_values *digest_list, u32 size,
+ const u8 *event, u8 *log)
+{
+ size_t len;
+ size_t pos;
+ u32 i;
+
+ pos = offsetof(struct tcg_pcr_event2, pcr_index);
+ put_unaligned_le32(pcr_index, log);
+ pos = offsetof(struct tcg_pcr_event2, event_type);
+ put_unaligned_le32(event_type, log + pos);
+ pos = offsetof(struct tcg_pcr_event2, digests) +
+ offsetof(struct tpml_digest_values, count);
+ put_unaligned_le32(digest_list->count, log + pos);
+
+ pos = offsetof(struct tcg_pcr_event2, digests) +
+ offsetof(struct tpml_digest_values, digests);
+ for (i = 0; i < digest_list->count; ++i) {
+ u16 hash_alg = digest_list->digests[i].hash_alg;
+
+ len = tpm2_algorithm_to_len(hash_alg);
+ if (!len)
+ continue;
+
+ pos += offsetof(struct tpmt_ha, hash_alg);
+ put_unaligned_le16(hash_alg, log + pos);
+ pos += offsetof(struct tpmt_ha, digest);
+ memcpy(log + pos, (u8 *)&digest_list->digests[i].digest, len);
+ pos += len;
+ }
+
+ put_unaligned_le32(size, log + pos);
+ pos += sizeof(u32);
+ memcpy(log + pos, event, size);
+}
+
+static int tcg2_log_append_check(struct tcg2_event_log *elog, u32 pcr_index,
+ u32 event_type,
+ struct tpml_digest_values *digest_list,
+ u32 size, const u8 *event)
+{
+ u32 event_size;
+ u8 *log;
+
+ event_size = size + tcg2_event_get_size(digest_list);
+ if (elog->log_position + event_size > elog->log_size) {
+ printf("%s: log too large: %u + %u > %u\n", __func__,
+ elog->log_position, event_size, elog->log_size);
+ return -ENOBUFS;
+ }
+
+ log = elog->log + elog->log_position;
+ elog->log_position += event_size;
+
+ tcg2_log_append(pcr_index, event_type, digest_list, size, event, log);
+
+ return 0;
+}
+
+static int tcg2_log_init(struct udevice *dev, struct tcg2_event_log *elog)
+{
+ struct tcg_efi_spec_id_event *ev;
+ struct tcg_pcr_event *log;
+ u32 event_size;
+ u32 count = 0;
+ u32 log_size;
+ u32 active;
+ size_t i;
+ u16 len;
+ int rc;
+
+ rc = tcg2_get_active_pcr_banks(dev, &active);
+ if (rc)
+ return rc;
+
+ event_size = offsetof(struct tcg_efi_spec_id_event, digest_sizes);
+ for (i = 0; i < ARRAY_SIZE(hash_algo_list); ++i) {
+ if (!(active & hash_algo_list[i].hash_mask))
+ continue;
+
+ switch (hash_algo_list[i].hash_alg) {
+ case TPM2_ALG_SHA1:
+ case TPM2_ALG_SHA256:
+ case TPM2_ALG_SHA384:
+ case TPM2_ALG_SHA512:
+ count++;
+ break;
+ default:
+ continue;
+ }
+ }
+
+ event_size += 1 +
+ (sizeof(struct tcg_efi_spec_id_event_algorithm_size) * count);
+ log_size = offsetof(struct tcg_pcr_event, event) + event_size;
+
+ if (log_size > elog->log_size) {
+ printf("%s: log too large: %u > %u\n", __func__, log_size,
+ elog->log_size);
+ return -ENOBUFS;
+ }
+
+ log = (struct tcg_pcr_event *)elog->log;
+ put_unaligned_le32(0, &log->pcr_index);
+ put_unaligned_le32(EV_NO_ACTION, &log->event_type);
+ memset(&log->digest, 0, sizeof(log->digest));
+ put_unaligned_le32(event_size, &log->event_size);
+
+ ev = (struct tcg_efi_spec_id_event *)log->event;
+ strlcpy((char *)ev->signature, TCG_EFI_SPEC_ID_EVENT_SIGNATURE_03,
+ sizeof(ev->signature));
+ put_unaligned_le32(0, &ev->platform_class);
+ ev->spec_version_minor = TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MINOR_TPM2;
+ ev->spec_version_major = TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MAJOR_TPM2;
+ ev->spec_errata = TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_ERRATA_TPM2;
+ ev->uintn_size = sizeof(size_t) / sizeof(u32);
+ put_unaligned_le32(count, &ev->number_of_algorithms);
+
+ count = 0;
+ for (i = 0; i < ARRAY_SIZE(hash_algo_list); ++i) {
+ if (!(active & hash_algo_list[i].hash_mask))
+ continue;
+
+ len = hash_algo_list[i].hash_len;
+ if (!len)
+ continue;
+
+ put_unaligned_le16(hash_algo_list[i].hash_alg,
+ &ev->digest_sizes[count].algorithm_id);
+ put_unaligned_le16(len, &ev->digest_sizes[count].digest_size);
+ count++;
+ }
+
+ *((u8 *)ev + (event_size - 1)) = 0;
+ elog->log_position = log_size;
+
+ return 0;
+}
+
+static int tcg2_replay_eventlog(struct tcg2_event_log *elog,
+ struct udevice *dev,
+ struct tpml_digest_values *digest_list,
+ u32 log_position)
+{
+ const u32 offset = offsetof(struct tcg_pcr_event2, digests) +
+ offsetof(struct tpml_digest_values, digests);
+ u32 event_size;
+ u32 count;
+ u16 algo;
+ u32 pcr;
+ u32 pos;
+ u16 len;
+ u8 *log;
+ int rc;
+ u32 i;
+
+ while (log_position + offset < elog->log_size) {
+ log = elog->log + log_position;
+
+ pos = offsetof(struct tcg_pcr_event2, pcr_index);
+ pcr = get_unaligned_le32(log + pos);
+ pos = offsetof(struct tcg_pcr_event2, event_type);
+ if (!get_unaligned_le32(log + pos))
+ return 0;
+
+ pos = offsetof(struct tcg_pcr_event2, digests) +
+ offsetof(struct tpml_digest_values, count);
+ count = get_unaligned_le32(log + pos);
+ if (count > ARRAY_SIZE(hash_algo_list) ||
+ (digest_list->count && digest_list->count != count))
+ return 0;
+
+ pos = offsetof(struct tcg_pcr_event2, digests) +
+ offsetof(struct tpml_digest_values, digests);
+ for (i = 0; i < count; ++i) {
+ pos += offsetof(struct tpmt_ha, hash_alg);
+ if (log_position + pos + sizeof(u16) >= elog->log_size)
+ return 0;
+
+ algo = get_unaligned_le16(log + pos);
+ pos += offsetof(struct tpmt_ha, digest);
+ switch (algo) {
+ case TPM2_ALG_SHA1:
+ case TPM2_ALG_SHA256:
+ case TPM2_ALG_SHA384:
+ case TPM2_ALG_SHA512:
+ len = tpm2_algorithm_to_len(algo);
+ break;
+ default:
+ return 0;
+ }
+
+ if (digest_list->count) {
+ if (algo != digest_list->digests[i].hash_alg ||
+ log_position + pos + len >= elog->log_size)
+ return 0;
+
+ memcpy(digest_list->digests[i].digest.sha512,
+ log + pos, len);
+ }
+
+ pos += len;
+ }
+
+ if (log_position + pos + sizeof(u32) >= elog->log_size)
+ return 0;
+
+ event_size = get_unaligned_le32(log + pos);
+ pos += event_size + sizeof(u32);
+ if (log_position + pos > elog->log_size)
+ return 0;
+
+ if (digest_list->count) {
+ rc = tcg2_pcr_extend(dev, pcr, digest_list);
+ if (rc)
+ return rc;
+ }
+
+ log_position += pos;
+ }
+
+ elog->log_position = log_position;
+ elog->found = true;
+ return 0;
+}
+
+static int tcg2_log_parse(struct udevice *dev, struct tcg2_event_log *elog)
+{
+ struct tpml_digest_values digest_list;
+ struct tcg_efi_spec_id_event *event;
+ struct tcg_pcr_event *log;
+ u32 log_active;
+ u32 calc_size;
+ u32 active;
+ u32 count;
+ u32 evsz;
+ u32 mask;
+ u16 algo;
+ u16 len;
+ int rc;
+ u32 i;
+ u16 j;
+
+ if (elog->log_size <= offsetof(struct tcg_pcr_event, event))
+ return 0;
+
+ log = (struct tcg_pcr_event *)elog->log;
+ if (get_unaligned_le32(&log->pcr_index) != 0 ||
+ get_unaligned_le32(&log->event_type) != EV_NO_ACTION)
+ return 0;
+
+ for (i = 0; i < sizeof(log->digest); i++) {
+ if (log->digest[i])
+ return 0;
+ }
+
+ evsz = get_unaligned_le32(&log->event_size);
+ if (evsz < offsetof(struct tcg_efi_spec_id_event, digest_sizes) ||
+ evsz + offsetof(struct tcg_pcr_event, event) > elog->log_size)
+ return 0;
+
+ event = (struct tcg_efi_spec_id_event *)log->event;
+ if (memcmp(event->signature, TCG_EFI_SPEC_ID_EVENT_SIGNATURE_03,
+ sizeof(TCG_EFI_SPEC_ID_EVENT_SIGNATURE_03)))
+ return 0;
+
+ if (event->spec_version_minor != TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MINOR_TPM2 ||
+ event->spec_version_major != TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MAJOR_TPM2)
+ return 0;
+
+ count = get_unaligned_le32(&event->number_of_algorithms);
+ if (count > ARRAY_SIZE(hash_algo_list))
+ return 0;
+
+ calc_size = offsetof(struct tcg_efi_spec_id_event, digest_sizes) +
+ (sizeof(struct tcg_efi_spec_id_event_algorithm_size) * count) +
+ 1;
+ if (evsz != calc_size)
+ return 0;
+
+ rc = tcg2_get_active_pcr_banks(dev, &active);
+ if (rc)
+ return rc;
+
+ digest_list.count = 0;
+ log_active = 0;
+
+ for (i = 0; i < count; ++i) {
+ algo = get_unaligned_le16(&event->digest_sizes[i].algorithm_id);
+ mask = tcg2_algorithm_to_mask(algo);
+
+ if (!(active & mask))
+ return 0;
+
+ switch (algo) {
+ case TPM2_ALG_SHA1:
+ case TPM2_ALG_SHA256:
+ case TPM2_ALG_SHA384:
+ case TPM2_ALG_SHA512:
+ len = get_unaligned_le16(&event->digest_sizes[i].digest_size);
+ if (tpm2_algorithm_to_len(algo) != len)
+ return 0;
+ digest_list.digests[digest_list.count++].hash_alg = algo;
+ break;
+ default:
+ return 0;
+ }
+
+ log_active |= mask;
+ }
+
+ /* Ensure the previous firmware extended all the PCRs. */
+ if (log_active != active)
+ return 0;
+
+ /* Read PCR0 to check if previous firmware extended the PCRs or not. */
+ rc = tcg2_pcr_read(dev, 0, &digest_list);
+ if (rc)
+ return rc;
+
+ for (i = 0; i < digest_list.count; ++i) {
+ len = tpm2_algorithm_to_len(digest_list.digests[i].hash_alg);
+ for (j = 0; j < len; ++j) {
+ if (digest_list.digests[i].digest.sha512[j])
+ break;
+ }
+
+ /* PCR is non-zero; it has been extended, so skip extending. */
+ if (j != len) {
+ digest_list.count = 0;
+ break;
+ }
+ }
+
+ return tcg2_replay_eventlog(elog, dev, &digest_list,
+ offsetof(struct tcg_pcr_event, event) +
+ evsz);
+}
+
+int tcg2_pcr_extend(struct udevice *dev, u32 pcr_index,
+ struct tpml_digest_values *digest_list)
+{
+ u32 rc;
+ u32 i;
+
+ for (i = 0; i < digest_list->count; i++) {
+ u32 alg = digest_list->digests[i].hash_alg;
+
+ rc = tpm2_pcr_extend(dev, pcr_index, alg,
+ (u8 *)&digest_list->digests[i].digest,
+ tpm2_algorithm_to_len(alg));
+ if (rc) {
+ printf("%s: error pcr:%u alg:%08x\n", __func__,
+ pcr_index, alg);
+ return rc;
+ }
+ }
+
+ return 0;
+}
+
+int tcg2_pcr_read(struct udevice *dev, u32 pcr_index,
+ struct tpml_digest_values *digest_list)
+{
+ struct tpm_chip_priv *priv;
+ u32 rc;
+ u32 i;
+
+ priv = dev_get_uclass_priv(dev);
+ if (!priv)
+ return -ENODEV;
+
+ for (i = 0; i < digest_list->count; i++) {
+ u32 alg = digest_list->digests[i].hash_alg;
+ u8 *digest = (u8 *)&digest_list->digests[i].digest;
+
+ rc = tpm2_pcr_read(dev, pcr_index, priv->pcr_select_min, alg,
+ digest, tpm2_algorithm_to_len(alg), NULL);
+ if (rc) {
+ printf("%s: error pcr:%u alg:%08x\n", __func__,
+ pcr_index, alg);
+ return rc;
+ }
+ }
+
+ return 0;
+}
+
+int tcg2_measure_data(struct udevice *dev, struct tcg2_event_log *elog,
+ u32 pcr_index, u32 size, const u8 *data, u32 event_type,
+ u32 event_size, const u8 *event)
+{
+ struct tpml_digest_values digest_list;
+ int rc;
+
+ if (data)
+ rc = tcg2_create_digest(dev, data, size, &digest_list);
+ else
+ rc = tcg2_create_digest(dev, event, event_size, &digest_list);
+ if (rc)
+ return rc;
+
+ rc = tcg2_pcr_extend(dev, pcr_index, &digest_list);
+ if (rc)
+ return rc;
+
+ return tcg2_log_append_check(elog, pcr_index, event_type, &digest_list,
+ event_size, event);
+}
+
+int tcg2_log_prepare_buffer(struct udevice *dev, struct tcg2_event_log *elog,
+ bool ignore_existing_log)
+{
+ struct tcg2_event_log log;
+ int rc;
+
+ elog->log_position = 0;
+ elog->found = false;
+
+ rc = tcg2_platform_get_log(dev, (void **)&log.log, &log.log_size);
+ if (!rc) {
+ log.log_position = 0;
+ log.found = false;
+
+ if (!ignore_existing_log) {
+ rc = tcg2_log_parse(dev, &log);
+ if (rc)
+ return rc;
+ }
+
+ if (elog->log_size) {
+ if (log.found) {
+ if (elog->log_size < log.log_position)
+ return -ENOBUFS;
+
+ /*
+ * Copy the discovered log into the user buffer
+ * if there's enough space.
+ */
+ memcpy(elog->log, log.log, log.log_position);
+ }
+
+ unmap_physmem(log.log, MAP_NOCACHE);
+ } else {
+ elog->log = log.log;
+ elog->log_size = log.log_size;
+ }
+
+ elog->log_position = log.log_position;
+ elog->found = log.found;
+ }
+
+ /*
+ * Initialize the log buffer if no log was discovered and the buffer is
+ * valid. User's can pass in their own buffer as a fallback if no
+ * memory region is found.
+ */
+ if (!elog->found && elog->log_size)
+ rc = tcg2_log_init(dev, elog);
+
+ return rc;
+}
+
+int tcg2_measurement_init(struct udevice **dev, struct tcg2_event_log *elog,
+ bool ignore_existing_log)
+{
+ int rc;
+
+ rc = tcg2_platform_get_tpm2(dev);
+ if (rc)
+ return rc;
+
+ rc = tpm_auto_start(*dev);
+ if (rc)
+ return rc;
+
+ rc = tcg2_log_prepare_buffer(*dev, elog, ignore_existing_log);
+ if (rc) {
+ tcg2_measurement_term(*dev, elog, true);
+ return rc;
+ }
+
+ rc = tcg2_measure_event(*dev, elog, 0, EV_S_CRTM_VERSION,
+ strlen(version_string) + 1,
+ (u8 *)version_string);
+ if (rc) {
+ tcg2_measurement_term(*dev, elog, true);
+ return rc;
+ }
+
+ return 0;
+}
+
+void tcg2_measurement_term(struct udevice *dev, struct tcg2_event_log *elog,
+ bool error)
+{
+ u32 event = error ? 0x1 : 0xffffffff;
+ int i;
+
+ for (i = 0; i < 8; ++i)
+ tcg2_measure_event(dev, elog, i, EV_SEPARATOR, sizeof(event),
+ (const u8 *)&event);
+
+ if (elog->log)
+ unmap_physmem(elog->log, MAP_NOCACHE);
+}
+
+__weak int tcg2_platform_get_log(struct udevice *dev, void **addr, u32 *size)
+{
+ const __be32 *addr_prop;
+ const __be32 *size_prop;
+ int asize;
+ int ssize;
+
+ *addr = NULL;
+ *size = 0;
+
+ addr_prop = dev_read_prop(dev, "tpm_event_log_addr", &asize);
+ if (!addr_prop)
+ addr_prop = dev_read_prop(dev, "linux,sml-base", &asize);
+
+ size_prop = dev_read_prop(dev, "tpm_event_log_size", &ssize);
+ if (!size_prop)
+ size_prop = dev_read_prop(dev, "linux,sml-size", &ssize);
+
+ if (addr_prop && size_prop) {
+ u64 a = of_read_number(addr_prop, asize / sizeof(__be32));
+ u64 s = of_read_number(size_prop, ssize / sizeof(__be32));
+
+ *addr = map_physmem(a, s, MAP_NOCACHE);
+ *size = (u32)s;
+ } else {
+ struct ofnode_phandle_args args;
+ phys_addr_t a;
+ fdt_size_t s;
+
+ if (dev_read_phandle_with_args(dev, "memory-region", NULL, 0,
+ 0, &args))
+ return -ENODEV;
+
+ a = ofnode_get_addr_size(args.node, "reg", &s);
+ if (a == FDT_ADDR_T_NONE)
+ return -ENOMEM;
+
+ *addr = map_physmem(a, s, MAP_NOCACHE);
+ *size = (u32)s;
+ }
+
+ return 0;
+}
+
+__weak int tcg2_platform_get_tpm2(struct udevice **dev)
+{
+ for_each_tpm_device(*dev) {
+ if (tpm_get_version(*dev) == TPM_V2)
+ return 0;
+ }
+
+ return -ENODEV;
+}
+
+u32 tcg2_algorithm_to_mask(enum tpm2_algorithms algo)
+{
+ size_t i;
+
+ for (i = 0; i < ARRAY_SIZE(hash_algo_list); i++) {
+ if (hash_algo_list[i].hash_alg == algo)
+ return hash_algo_list[i].hash_mask;
+ }
+
+ return 0;
+}
+
+__weak void tcg2_platform_startup_error(struct udevice *dev, int rc) {}
diff --git a/lib/vsprintf.c b/lib/vsprintf.c
index 27ea9c9..cfd1f19 100644
--- a/lib/vsprintf.c
+++ b/lib/vsprintf.c
@@ -19,6 +19,7 @@
#include <hexdump.h>
#include <stdarg.h>
#include <uuid.h>
+#include <stdio.h>
#include <vsprintf.h>
#include <linux/ctype.h>
#include <linux/err.h>
diff --git a/net/Kconfig b/net/Kconfig
index 5dff633..7cb80b8 100644
--- a/net/Kconfig
+++ b/net/Kconfig
@@ -42,8 +42,8 @@
DNS server. To do this, they need the hostname of the DHCP
requester.
If CONFIG_BOOTP_SEND_HOSTNAME is defined, the content
- of the "hostname" environment variable is passed as
- option 12 to the DHCP server.
+ of the "hostname" environment variable is passed as
+ option 12 to the DHCP server.
config NET_RANDOM_ETHADDR
bool "Random ethaddr if unset"
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 62f8751..3e68d5a 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -673,7 +673,7 @@
-n /chosen -n /config -O dtb | \
$(objtree)/tools/fdtgrep -r -O dtb - -o $@ \
-P bootph-all -P bootph-pre-ram -P bootph-pre-sram \
- -P bootph-verify \
+ -P bootph-verify -P bootph-some-ram \
$(migrate_all) \
$(addprefix -P ,$(subst $\",,$(CONFIG_OF_SPL_REMOVE_PROPS)))
diff --git a/scripts/setlocalversion b/scripts/setlocalversion
index 4a63143..dbe0482 100755
--- a/scripts/setlocalversion
+++ b/scripts/setlocalversion
@@ -2,7 +2,7 @@
# SPDX-License-Identifier: GPL-2.0
#
# This scripts adds local version information from the version
-# control systems git, mercurial (hg) and subversion (svn).
+# control system git.
#
# If something goes wrong, send a mail the kernel build mailinglist
# (see MAINTAINERS) and CC Nico Schottelius
@@ -11,16 +11,17 @@
#
usage() {
- echo "Usage: $0 [--save-scmversion] [srctree]" >&2
+ echo "Usage: $0 [--no-local] [srctree]" >&2
exit 1
}
-scm_only=false
-srctree=.
-if test "$1" = "--save-scmversion"; then
- scm_only=true
+no_local=false
+if test "$1" = "--no-local"; then
+ no_local=true
shift
fi
+
+srctree=.
if test $# -gt 0; then
srctree=$1
shift
@@ -31,96 +32,98 @@
scm_version()
{
- local short
- short=false
+ local short=false
+ local no_dirty=false
+ local tag
+
+ while [ $# -gt 0 ];
+ do
+ case "$1" in
+ --short)
+ short=true;;
+ --no-dirty)
+ no_dirty=true;;
+ esac
+ shift
+ done
cd "$srctree"
- if test -e .scmversion; then
- cat .scmversion
+
+ if test -n "$(git rev-parse --show-cdup 2>/dev/null)"; then
return
fi
- if test "$1" = "--short"; then
- short=true
+
+ if ! head=$(git rev-parse --verify HEAD 2>/dev/null); then
+ return
fi
- # Check for git and a git repo.
- if test -z "$(git rev-parse --show-cdup 2>/dev/null)" &&
- head=$(git rev-parse --verify --short HEAD 2>/dev/null); then
+ # mainline kernel: 6.2.0-rc5 -> v6.2-rc5
+ # stable kernel: 6.1.7 -> v6.1.7
+ version_tag=v$(echo "${KERNELVERSION}" | sed -E 's/^([0-9]+\.[0-9]+)\.0(.*)$/\1\2/')
- # If we are at a tagged commit (like "v2.6.30-rc6"), we ignore
- # it, because this version is defined in the top level Makefile.
- if [ -z "$(git describe --exact-match 2>/dev/null)" ]; then
+ # If a localversion* file exists, and the corresponding
+ # annotated tag exists and is an ancestor of HEAD, use
+ # it. This is the case in linux-next.
+ tag=${file_localversion#-}
+ desc=
+ if [ -n "${tag}" ]; then
+ desc=$(git describe --match=$tag 2>/dev/null)
+ fi
- # If only the short version is requested, don't bother
- # running further git commands
- if $short; then
- echo "+"
- return
- fi
- # If we are past a tagged commit (like
- # "v2.6.30-rc5-302-g72357d5"), we pretty print it.
- if atag="$(git describe 2>/dev/null)"; then
- echo "$atag" | awk -F- '{printf("-%05d-%s", $(NF-1),$(NF))}'
+ # Otherwise, if a localversion* file exists, and the tag
+ # obtained by appending it to the tag derived from
+ # KERNELVERSION exists and is an ancestor of HEAD, use
+ # it. This is e.g. the case in linux-rt.
+ if [ -z "${desc}" ] && [ -n "${file_localversion}" ]; then
+ tag="${version_tag}${file_localversion}"
+ desc=$(git describe --match=$tag 2>/dev/null)
+ fi
- # If we don't have a tag at all we print -g{commitish}.
- else
- printf '%s%s' -g $head
- fi
- fi
+ # Otherwise, default to the annotated tag derived from KERNELVERSION.
+ if [ -z "${desc}" ]; then
+ tag="${version_tag}"
+ desc=$(git describe --match=$tag 2>/dev/null)
+ fi
- # Is this git on svn?
- if git config --get svn-remote.svn.url >/dev/null; then
- printf -- '-svn%s' "$(git svn find-rev $head)"
- fi
+ # If we are at the tagged commit, we ignore it because the version is
+ # well-defined.
+ if [ "${tag}" != "${desc}" ]; then
- # Check for uncommitted changes.
- # First, with git-status, but --no-optional-locks is only
- # supported in git >= 2.14, so fall back to git-diff-index if
- # it fails. Note that git-diff-index does not refresh the
- # index, so it may give misleading results. See
- # git-update-index(1), git-diff-index(1), and git-status(1).
- if {
- git --no-optional-locks status -uno --porcelain 2>/dev/null ||
- git diff-index --name-only HEAD
- } | grep -qvE '^(.. )?scripts/package'; then
- printf '%s' -dirty
+ # If only the short version is requested, don't bother
+ # running further git commands
+ if $short; then
+ echo "+"
+ return
fi
-
- # All done with git
- return
- fi
-
- # Check for mercurial and a mercurial repo.
- if test -d .hg && hgid=$(hg id 2>/dev/null); then
- # Do we have an tagged version? If so, latesttagdistance == 1
- if [ "$(hg log -r . --template '{latesttagdistance}')" = "1" ]; then
- id=$(hg log -r . --template '{latesttag}')
- printf '%s%s' -hg "$id"
- else
- tag=$(printf '%s' "$hgid" | cut -d' ' -f2)
- if [ -z "$tag" -o "$tag" = tip ]; then
- id=$(printf '%s' "$hgid" | sed 's/[+ ].*//')
- printf '%s%s' -hg "$id"
- fi
+ # If we are past the tagged commit, we pretty print it.
+ # (like 6.1.0-14595-g292a089d78d3)
+ if [ -n "${desc}" ]; then
+ echo "${desc}" | awk -F- '{printf("-%05d", $(NF-1))}'
fi
- # Are there uncommitted changes?
- # These are represented by + after the changeset id.
- case "$hgid" in
- *+|*+\ *) printf '%s' -dirty ;;
- esac
+ # Add -g and exactly 12 hex chars.
+ printf '%s%s' -g "$(echo $head | cut -c1-12)"
+ fi
- # All done with mercurial
+ if ${no_dirty}; then
return
fi
- # Check for svn and a svn repo.
- if rev=$(LANG= LC_ALL= LC_MESSAGES=C svn info 2>/dev/null | grep '^Last Changed Rev'); then
- rev=$(echo $rev | awk '{print $NF}')
- printf -- '-svn%s' "$rev"
-
- # All done with svn
- return
+ # Check for uncommitted changes.
+ # This script must avoid any write attempt to the source tree, which
+ # might be read-only.
+ # You cannot use 'git describe --dirty' because it tries to create
+ # .git/index.lock .
+ # First, with git-status, but --no-optional-locks is only supported in
+ # git >= 2.14, so fall back to git-diff-index if it fails. Note that
+ # git-diff-index does not refresh the index, so it may give misleading
+ # results.
+ # See git-update-index(1), git-diff-index(1), and git-status(1).
+ if {
+ git --no-optional-locks status -uno --porcelain 2>/dev/null ||
+ git diff-index --name-only HEAD
+ } | read dummy; then
+ printf '%s' -dirty
fi
}
@@ -141,48 +144,43 @@
echo "$res"
}
-if $scm_only; then
- if test ! -e .scmversion; then
- res=$(scm_version)
- echo "$res" >.scmversion
- fi
- exit
-fi
-
-if test -e include/config/auto.conf; then
- # We are interested only in CONFIG_LOCALVERSION and
- # CONFIG_LOCALVERSION_AUTO, so extract these in a safe
- # way (i.e. w/o sourcing auto.conf)
- # xargs echo removes quotes
- CONFIG_LOCALVERSION=`cat include/config/auto.conf | awk -F '=' '/^CONFIG_LOCALVERSION=/ {print $2}' | xargs echo`
- CONFIG_LOCALVERSION_AUTO=`cat include/config/auto.conf | awk -F '=' '/^CONFIG_LOCALVERSION_AUTO=/ {print $2}' | xargs echo`
-else
- echo "Error: kernelrelease not valid - run 'make prepare' to update it" >&2
+if [ -z "${KERNELVERSION}" ]; then
+ echo "KERNELVERSION is not set" >&2
exit 1
fi
# localversion* files in the build and source directory
-res="$(collect_files localversion*)"
+file_localversion="$(collect_files localversion*)"
if test ! "$srctree" -ef .; then
- res="$res$(collect_files "$srctree"/localversion*)"
+ file_localversion="${file_localversion}$(collect_files "$srctree"/localversion*)"
+fi
+
+if ${no_local}; then
+ echo "${KERNELVERSION}$(scm_version --no-dirty)"
+ exit 0
+fi
+
+if ! test -e include/config/auto.conf; then
+ echo "Error: kernelrelease not valid - run 'make prepare' to update it" >&2
+ exit 1
fi
-# CONFIG_LOCALVERSION and LOCALVERSION (if set)
-res="${res}${CONFIG_LOCALVERSION}${LOCALVERSION}"
+# version string from CONFIG_LOCALVERSION
+config_localversion=$(sed -n 's/^CONFIG_LOCALVERSION=\(.*\)$/\1/p' include/config/auto.conf | tr -d '"')
-# scm version string if not at a tagged commit
-if test "$CONFIG_LOCALVERSION_AUTO" = "y"; then
+# scm version string if not at the kernel version tag or at the file_localversion
+if grep -q "^CONFIG_LOCALVERSION_AUTO=y$" include/config/auto.conf; then
# full scm version string
- res="$res$(scm_version)"
-else
- # append a plus sign if the repository is not in a clean
- # annotated or signed tagged state (as git describe only
- # looks at signed or annotated tags - git tag -a/-s) and
- # LOCALVERSION= is not specified
- if test "${LOCALVERSION+set}" != "set"; then
- scm=$(scm_version --short)
- res="$res${scm:++}"
- fi
+ scm_version="$(scm_version)"
+elif [ "${LOCALVERSION+set}" != "set" ]; then
+ # If the variable LOCALVERSION is not set, append a plus
+ # sign if the repository is not in a clean annotated or
+ # signed tagged state (as git describe only looks at signed
+ # or annotated tags - git tag -a/-s).
+ #
+ # If the variable LOCALVERSION is set (including being set
+ # to an empty string), we don't want to append a plus sign.
+ scm_version="$(scm_version --short)"
fi
-echo "$res"
+echo "${KERNELVERSION}${file_localversion}${config_localversion}${LOCALVERSION}${scm_version}"
diff --git a/test/cmd/fdt.c b/test/cmd/fdt.c
index a0faf5a..e09a929 100644
--- a/test/cmd/fdt.c
+++ b/test/cmd/fdt.c
@@ -1346,6 +1346,10 @@
ut_assert_nextlinen("\tu-boot,version = "); /* Ignore the version string */
if (env_bootargs)
ut_assert_nextline("\tbootargs = \"%s\";", env_bootargs);
+ if (IS_ENABLED(CONFIG_DM_RNG) &&
+ !IS_ENABLED(CONFIG_MEASURED_BOOT) &&
+ !IS_ENABLED(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT))
+ ut_assert_nextlinen("\tkaslr-seed = ");
ut_assert_nextline("};");
ut_assertok(ut_check_console_end(uts));
@@ -1362,6 +1366,10 @@
ut_assert_nextlinen("\tu-boot,version = "); /* Ignore the version string */
if (env_bootargs)
ut_assert_nextline("\tbootargs = \"%s\";", env_bootargs);
+ if (IS_ENABLED(CONFIG_DM_RNG) &&
+ !IS_ENABLED(CONFIG_MEASURED_BOOT) &&
+ !IS_ENABLED(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT))
+ ut_assert_nextlinen("\tkaslr-seed = ");
ut_assert_nextline("};");
ut_assertok(ut_check_console_end(uts));
diff --git a/test/common/cyclic.c b/test/common/cyclic.c
index 461f8cf..51a07c5 100644
--- a/test/common/cyclic.c
+++ b/test/common/cyclic.c
@@ -12,22 +12,27 @@
#include <linux/delay.h>
/* Test that cyclic function is called */
-static bool cyclic_active = false;
+static struct cyclic_test {
+ struct cyclic_info cyclic;
+ bool called;
+} cyclic_test;
-static void cyclic_test(void *ctx)
+static void test_cb(struct cyclic_info *c)
{
- cyclic_active = true;
+ struct cyclic_test *t = container_of(c, struct cyclic_test, cyclic);
+ t->called = true;
}
static int dm_test_cyclic_running(struct unit_test_state *uts)
{
- cyclic_active = false;
- ut_assertnonnull(cyclic_register(cyclic_test, 10 * 1000, "cyclic_demo",
- NULL));
+ cyclic_test.called = false;
+ cyclic_register(&cyclic_test.cyclic, test_cb, 10 * 1000, "cyclic_test");
/* Execute all registered cyclic functions */
schedule();
- ut_asserteq(true, cyclic_active);
+ ut_asserteq(true, cyclic_test.called);
+
+ cyclic_unregister(&cyclic_test.cyclic);
return 0;
}
diff --git a/test/dm/acpi.c b/test/dm/acpi.c
index 4db2171..7da381f 100644
--- a/test/dm/acpi.c
+++ b/test/dm/acpi.c
@@ -236,7 +236,6 @@
hdr.length = 0x11;
hdr.revision = 0x22;
hdr.checksum = 0x33;
- hdr.creator_revision = 0x44;
acpi_fill_header(&hdr, "ABCD");
ut_asserteq_mem("ABCD", hdr.signature, sizeof(hdr.signature));
@@ -248,7 +247,7 @@
sizeof(hdr.oem_table_id));
ut_asserteq(OEM_REVISION, hdr.oem_revision);
ut_asserteq_mem(ASLC_ID, hdr.creator_id, sizeof(hdr.creator_id));
- ut_asserteq(0x44, hdr.creator_revision);
+ ut_asserteq(ASL_REVISION, hdr.creator_revision);
return 0;
}
diff --git a/test/dm/core.c b/test/dm/core.c
index 4741c81..dbad1b3 100644
--- a/test/dm/core.c
+++ b/test/dm/core.c
@@ -1006,7 +1006,6 @@
ut_assertok(uclass_get(UCLASS_TEST, &uc));
gd->dm_root = NULL;
- gd->dm_root_f = NULL;
memset(&gd->uclass_root, '\0', sizeof(gd->uclass_root));
ut_asserteq_ptr(NULL, uclass_find(UCLASS_TEST));
diff --git a/test/dm/fwu_mdata.c b/test/dm/fwu_mdata.c
index 43ce3d0..0be7f45 100644
--- a/test/dm/fwu_mdata.c
+++ b/test/dm/fwu_mdata.c
@@ -92,6 +92,10 @@
struct udevice *dev;
struct fwu_mdata mdata = { 0 };
+ ut_assertok(setup_blk_device(uts));
+ ut_assertok(populate_mmc_disk_image(uts));
+ ut_assertok(write_mmc_blk_device(uts));
+
/*
* Trigger lib/fwu_updates/fwu.c fwu_boottime_checks()
* to populate g_dev global pointer in that library.
@@ -99,9 +103,7 @@
event_notify_null(EVT_MAIN_LOOP);
ut_assertok(uclass_first_device_err(UCLASS_FWU_MDATA, &dev));
- ut_assertok(setup_blk_device(uts));
- ut_assertok(populate_mmc_disk_image(uts));
- ut_assertok(write_mmc_blk_device(uts));
+ ut_assertok(fwu_init());
ut_assertok(fwu_get_mdata(&mdata));
@@ -117,18 +119,20 @@
struct udevice *dev;
struct fwu_mdata mdata = { 0 };
+ ut_assertok(setup_blk_device(uts));
+ ut_assertok(populate_mmc_disk_image(uts));
+ ut_assertok(write_mmc_blk_device(uts));
+
/*
* Trigger lib/fwu_updates/fwu.c fwu_boottime_checks()
* to populate g_dev global pointer in that library.
*/
event_notify_null(EVT_MAIN_LOOP);
- ut_assertok(setup_blk_device(uts));
- ut_assertok(populate_mmc_disk_image(uts));
- ut_assertok(write_mmc_blk_device(uts));
ut_assertok(uclass_first_device_err(UCLASS_FWU_MDATA, &dev));
+ ut_assertok(fwu_init());
ut_assertok(fwu_get_mdata(&mdata));
active_idx = (mdata.active_index + 1) % CONFIG_FWU_NUM_BANKS;
diff --git a/test/dm/scmi.c b/test/dm/scmi.c
index 69fc900..c9a0352 100644
--- a/test/dm/scmi.c
+++ b/test/dm/scmi.c
@@ -18,7 +18,7 @@
#include <scmi_agent.h>
#include <scmi_agent-uclass.h>
#include <scmi_protocols.h>
-#include <vsprintf.h>
+#include <stdio.h>
#include <asm/scmi_test.h>
#include <dm/device-internal.h>
#include <dm/test.h>
diff --git a/test/print_ut.c b/test/print_ut.c
index bded2b6..53d3354 100644
--- a/test/print_ut.c
+++ b/test/print_ut.c
@@ -9,6 +9,7 @@
#include <log.h>
#include <mapmem.h>
#include <version_string.h>
+#include <stdio.h>
#include <vsprintf.h>
#include <test/suites.h>
#include <test/test.h>
diff --git a/test/py/requirements.txt b/test/py/requirements.txt
index 0f67c3c..c1dd636 100644
--- a/test/py/requirements.txt
+++ b/test/py/requirements.txt
@@ -20,7 +20,7 @@
pytest-xdist==2.5.0
python-mimeparse==1.6.0
python-subunit==1.3.0
-requests==2.31.0
+requests==2.32.2
setuptools==65.5.1
six==1.16.0
testtools==2.3.0
diff --git a/test/py/tests/test_dm.py b/test/py/tests/test_dm.py
index 68d4ea1..be94971 100644
--- a/test/py/tests/test_dm.py
+++ b/test/py/tests/test_dm.py
@@ -13,8 +13,11 @@
for line in response[:-1].split('\n')[2:])
response = u_boot_console.run_command('dm compat')
+ bad_drivers = set()
for driver in drivers:
- assert driver in response
+ if not driver in response:
+ bad_drivers.add(driver)
+ assert not bad_drivers
# check sorting - output looks something like this:
# testacpi 0 [ ] testacpi_drv |-- acpi-test
diff --git a/test/py/tests/test_efi_secboot/conftest.py b/test/py/tests/test_efi_secboot/conftest.py
index ff7ac7c..0fa0747 100644
--- a/test/py/tests/test_efi_secboot/conftest.py
+++ b/test/py/tests/test_efi_secboot/conftest.py
@@ -64,6 +64,12 @@
check_call('cd %s; %scert-to-efi-sig-list -g %s db1.crt db1.esl; %ssign-efi-sig-list -t "2020-04-05" -c KEK.crt -k KEK.key db db1.esl db1.auth'
% (mnt_point, EFITOOLS_PATH, GUID, EFITOOLS_PATH),
shell=True)
+ # db2 (APPEND_WRITE)
+ check_call('cd %s; openssl req -x509 -sha256 -newkey rsa:2048 -subj /CN=TEST_db2/ -keyout db2.key -out db2.crt -nodes -days 365'
+ % mnt_point, shell=True)
+ check_call('cd %s; %scert-to-efi-sig-list -g %s db2.crt db2.esl; %ssign-efi-sig-list -a -c KEK.crt -k KEK.key db db2.esl db2.auth'
+ % (mnt_point, EFITOOLS_PATH, GUID, EFITOOLS_PATH),
+ shell=True)
# dbx (TEST_dbx certificate)
check_call('cd %s; openssl req -x509 -sha256 -newkey rsa:2048 -subj /CN=TEST_dbx/ -keyout dbx.key -out dbx.crt -nodes -days 365'
% mnt_point, shell=True)
@@ -84,6 +90,10 @@
check_call('cd %s; %scert-to-efi-hash-list -g %s -s 256 db1.crt dbx_hash1.crl; %ssign-efi-sig-list -t "2020-04-06" -c KEK.crt -k KEK.key dbx dbx_hash1.crl dbx_hash1.auth'
% (mnt_point, EFITOOLS_PATH, GUID, EFITOOLS_PATH),
shell=True)
+ # dbx_hash2 (digest of TEST_db2 certificate, with APPEND_WRITE)
+ check_call('cd %s; %scert-to-efi-hash-list -g %s -s 256 db2.crt dbx_hash2.crl; %ssign-efi-sig-list -a -c KEK.crt -k KEK.key dbx dbx_hash2.crl dbx_hash2.auth'
+ % (mnt_point, EFITOOLS_PATH, GUID, EFITOOLS_PATH),
+ shell=True)
# dbx_db (with TEST_db certificate)
check_call('cd %s; %ssign-efi-sig-list -t "2020-04-05" -c KEK.crt -k KEK.key dbx db.esl dbx_db.auth'
% (mnt_point, EFITOOLS_PATH),
diff --git a/test/py/tests/test_efi_secboot/test_authvar.py b/test/py/tests/test_efi_secboot/test_authvar.py
index f99b827..d5aeb65 100644
--- a/test/py/tests/test_efi_secboot/test_authvar.py
+++ b/test/py/tests/test_efi_secboot/test_authvar.py
@@ -183,7 +183,7 @@
assert 'db:' in ''.join(output)
output = u_boot_console.run_command_list([
- 'fatload host 0:1 4000000 db1.auth',
+ 'fatload host 0:1 4000000 db2.auth',
'setenv -e -nv -bs -rt -a -i 4000000:$filesize db'])
assert 'Failed to set EFI variable' in ''.join(output)
@@ -197,7 +197,7 @@
with u_boot_console.log.section('Test Case 3c'):
# Test Case 3c, update with correct signature
output = u_boot_console.run_command_list([
- 'fatload host 0:1 4000000 db1.auth',
+ 'fatload host 0:1 4000000 db2.auth',
'setenv -e -nv -bs -rt -at -a -i 4000000:$filesize db',
'printenv -e -n -guid d719b2cb-3d3a-4596-a3bc-dad00e67656f db'])
assert 'Failed to set EFI variable' not in ''.join(output)
diff --git a/test/py/tests/test_efi_secboot/test_signed.py b/test/py/tests/test_efi_secboot/test_signed.py
index 5000a4a..f604138 100644
--- a/test/py/tests/test_efi_secboot/test_signed.py
+++ b/test/py/tests/test_efi_secboot/test_signed.py
@@ -177,7 +177,7 @@
with u_boot_console.log.section('Test Case 5b'):
# Test Case 5b, authenticated if both signatures are verified
output = u_boot_console.run_command_list([
- 'fatload host 0:1 4000000 db1.auth',
+ 'fatload host 0:1 4000000 db2.auth',
'setenv -e -nv -bs -rt -at -a -i 4000000:$filesize db'])
assert 'Failed to set EFI variable' not in ''.join(output)
output = u_boot_console.run_command_list([
@@ -201,7 +201,7 @@
with u_boot_console.log.section('Test Case 5d'):
# Test Case 5d, rejected if both of signatures are revoked
output = u_boot_console.run_command_list([
- 'fatload host 0:1 4000000 dbx_hash1.auth',
+ 'fatload host 0:1 4000000 dbx_hash2.auth',
'setenv -e -nv -bs -rt -at -a -i 4000000:$filesize dbx'])
assert 'Failed to set EFI variable' not in ''.join(output)
output = u_boot_console.run_command_list([
@@ -223,7 +223,7 @@
'setenv -e -nv -bs -rt -at -i 4000000:$filesize KEK',
'fatload host 0:1 4000000 PK.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK',
- 'fatload host 0:1 4000000 db1.auth',
+ 'fatload host 0:1 4000000 db2.auth',
'setenv -e -nv -bs -rt -at -a -i 4000000:$filesize db',
'fatload host 0:1 4000000 dbx_hash1.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx'])
@@ -300,7 +300,7 @@
'setenv -e -nv -bs -rt -at -i 4000000:$filesize KEK',
'fatload host 0:1 4000000 PK.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK',
- 'fatload host 0:1 4000000 db1.auth',
+ 'fatload host 0:1 4000000 db2.auth',
'setenv -e -nv -bs -rt -at -a -i 4000000:$filesize db',
'fatload host 0:1 4000000 dbx_hash384.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx'])
@@ -323,7 +323,7 @@
'setenv -e -nv -bs -rt -at -i 4000000:$filesize KEK',
'fatload host 0:1 4000000 PK.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK',
- 'fatload host 0:1 4000000 db1.auth',
+ 'fatload host 0:1 4000000 db2.auth',
'setenv -e -nv -bs -rt -at -a -i 4000000:$filesize db',
'fatload host 0:1 4000000 dbx_hash512.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx'])
diff --git a/test/py/tests/test_fpga.py b/test/py/tests/test_fpga.py
index ca7ef8e..460ff22 100644
--- a/test/py/tests/test_fpga.py
+++ b/test/py/tests/test_fpga.py
@@ -256,7 +256,7 @@
@pytest.mark.buildconfigspec('cmd_fpga')
@pytest.mark.buildconfigspec('cmd_fpga_loadmk')
@pytest.mark.buildconfigspec('cmd_echo')
-@pytest.mark.buildconfigspec('image_format_legacy')
+@pytest.mark.buildconfigspec('legacy_image_format')
def test_fpga_loadmk_fail(u_boot_console):
f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'mkimage_legacy')
@@ -275,7 +275,7 @@
@pytest.mark.buildconfigspec('cmd_fpga')
@pytest.mark.buildconfigspec('cmd_fpga_loadmk')
@pytest.mark.buildconfigspec('cmd_echo')
-@pytest.mark.buildconfigspec('image_format_legacy')
+@pytest.mark.buildconfigspec('legacy_image_format')
def test_fpga_loadmk_legacy(u_boot_console):
f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'mkimage_legacy')
@@ -289,7 +289,7 @@
@pytest.mark.buildconfigspec('cmd_fpga')
@pytest.mark.buildconfigspec('cmd_fpga_loadmk')
@pytest.mark.buildconfigspec('cmd_echo')
-@pytest.mark.buildconfigspec('image_format_legacy')
+@pytest.mark.buildconfigspec('legacy_image_format')
def test_fpga_loadmk_legacy_variable_fpga(u_boot_console):
f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'mkimage_legacy')
@@ -306,7 +306,7 @@
@pytest.mark.buildconfigspec('cmd_fpga')
@pytest.mark.buildconfigspec('cmd_fpga_loadmk')
@pytest.mark.buildconfigspec('cmd_echo')
-@pytest.mark.buildconfigspec('image_format_legacy')
+@pytest.mark.buildconfigspec('legacy_image_format')
def test_fpga_loadmk_legacy_variable_fpgadata(u_boot_console):
f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'mkimage_legacy')
@@ -323,7 +323,7 @@
@pytest.mark.buildconfigspec('cmd_fpga')
@pytest.mark.buildconfigspec('cmd_fpga_loadmk')
@pytest.mark.buildconfigspec('cmd_echo')
-@pytest.mark.buildconfigspec('image_format_legacy')
+@pytest.mark.buildconfigspec('legacy_image_format')
def test_fpga_loadmk_legacy_variable(u_boot_console):
f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'mkimage_legacy')
@@ -342,7 +342,7 @@
@pytest.mark.buildconfigspec('cmd_fpga')
@pytest.mark.buildconfigspec('cmd_fpga_loadmk')
@pytest.mark.buildconfigspec('cmd_echo')
-@pytest.mark.buildconfigspec('image_format_legacy')
+@pytest.mark.buildconfigspec('legacy_image_format')
@pytest.mark.buildconfigspec('gzip')
def test_fpga_loadmk_legacy_gz(u_boot_console):
f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'mkimage_legacy_gz')
diff --git a/test/py/tests/test_help.py b/test/py/tests/test_help.py
index 153133c..2325ff6 100644
--- a/test/py/tests/test_help.py
+++ b/test/py/tests/test_help.py
@@ -7,7 +7,11 @@
def test_help(u_boot_console):
"""Test that the "help" command can be executed."""
- u_boot_console.run_command('help')
+ lines = u_boot_console.run_command('help')
+ if u_boot_console.config.buildconfig.get('config_cmd_2048', 'n') == 'y':
+ assert lines.splitlines()[0] == "2048 - The 2048 game"
+ else:
+ assert lines.splitlines()[0] == "? - alias for 'help'"
@pytest.mark.boardspec('sandbox')
def test_help_no_devicetree(u_boot_console):
diff --git a/test/py/tests/test_log.py b/test/py/tests/test_log.py
index 140dcb9..7980867 100644
--- a/test/py/tests/test_log.py
+++ b/test/py/tests/test_log.py
@@ -27,13 +27,16 @@
cons = u_boot_console
with cons.log.section('format'):
- run_with_format('all', 'NOTICE.arch,file.c:123-func() msg')
+ pad = int(u_boot_console.config.buildconfig.get('config_logf_func_pad'))
+ padding = ' ' * (pad - len('func'))
+
+ run_with_format('all', f'NOTICE.arch,file.c:123-{padding}func() msg')
output = cons.run_command('log format')
assert output == 'Log format: clFLfm'
- run_with_format('fm', 'func() msg')
- run_with_format('clfm', 'NOTICE.arch,func() msg')
- run_with_format('FLfm', 'file.c:123-func() msg')
+ run_with_format('fm', f'{padding}func() msg')
+ run_with_format('clfm', f'NOTICE.arch,{padding}func() msg')
+ run_with_format('FLfm', f'file.c:123-{padding}func() msg')
run_with_format('lm', 'NOTICE. msg')
run_with_format('m', 'msg')
diff --git a/test/py/tests/test_net.py b/test/py/tests/test_net.py
index 038a473..ad143c1 100644
--- a/test/py/tests/test_net.py
+++ b/test/py/tests/test_net.py
@@ -254,7 +254,7 @@
assert 'Set gatewayip6:' in output
assert '0000:0000:0000:0000:0000:0000:0000:0000' not in output
-@pytest.mark.buildconfigspec('cmd_net')
+@pytest.mark.buildconfigspec('cmd_tftpboot')
def test_net_tftpboot(u_boot_console):
"""Test the tftpboot command.
@@ -335,7 +335,6 @@
output = u_boot_console.run_command('crc32 %x $filesize' % addr)
assert expected_crc in output
-@pytest.mark.buildconfigspec("cmd_net")
@pytest.mark.buildconfigspec("cmd_pxe")
def test_net_pxe_get(u_boot_console):
"""Test the pxe get command.
@@ -391,7 +390,7 @@
assert "Config file 'default.boot' found" in output
@pytest.mark.buildconfigspec("cmd_crc32")
-@pytest.mark.buildconfigspec("cmd_net")
+@pytest.mark.buildconfigspec("cmd_tftpboot")
@pytest.mark.buildconfigspec("cmd_tftpput")
def test_net_tftpput(u_boot_console):
"""Test the tftpput command.
diff --git a/test/py/tests/test_net_boot.py b/test/py/tests/test_net_boot.py
new file mode 100644
index 0000000..63309fe
--- /dev/null
+++ b/test/py/tests/test_net_boot.py
@@ -0,0 +1,400 @@
+# SPDX-License-Identifier: GPL-2.0
+# (C) Copyright 2023, Advanced Micro Devices, Inc.
+
+import pytest
+import u_boot_utils
+import test_net
+import re
+
+"""
+Note: This test relies on boardenv_* containing configuration values to define
+which the network environment available for testing. Without this, this test
+will be automatically skipped.
+
+For example:
+
+# Details regarding a boot image file that may be read from a TFTP server. This
+# variable may be omitted or set to None if TFTP boot testing is not possible
+# or desired.
+env__net_tftp_bootable_file = {
+ 'fn': 'image.ub',
+ 'addr': 0x10000000,
+ 'size': 5058624,
+ 'crc32': 'c2244b26',
+ 'pattern': 'Linux',
+ 'config': 'config@2',
+ 'timeout': 50000,
+ 'check_type': 'boot_error',
+ 'check_pattern': 'ERROR',
+}
+
+# False or omitted if a TFTP boot test should be tested.
+# If TFTP boot testing is not possible or desired, set this variable to True.
+# For example: If FIT image is not proper to boot
+env__tftp_boot_test_skip = False
+
+# Here is the example of FIT image configurations:
+configurations {
+ default = "config@1";
+ config@1 {
+ description = "Boot Linux kernel with config@1";
+ kernel = "kernel@0";
+ fdt = "fdt@0";
+ ramdisk = "ramdisk@0";
+ hash@1 {
+ algo = "sha1";
+ };
+ };
+ config@2 {
+ description = "Boot Linux kernel with config@2";
+ kernel = "kernel@1";
+ fdt = "fdt@1";
+ ramdisk = "ramdisk@1";
+ hash@1 {
+ algo = "sha1";
+ };
+ };
+};
+
+# Details regarding a file that may be read from a TFTP server. This variable
+# may be omitted or set to None if PXE testing is not possible or desired.
+env__net_pxe_bootable_file = {
+ 'fn': 'default',
+ 'addr': 0x10000000,
+ 'size': 74,
+ 'timeout': 50000,
+ 'pattern': 'Linux',
+ 'valid_label': '1',
+ 'invalid_label': '2',
+ 'exp_str_invalid': 'Skipping install for failure retrieving',
+ 'local_label': '3',
+ 'exp_str_local': 'missing environment variable: localcmd',
+ 'empty_label': '4',
+ 'exp_str_empty': 'No kernel given, skipping boot',
+ 'check_type': 'boot_error',
+ 'check_pattern': 'ERROR',
+}
+
+# False or omitted if a PXE boot test should be tested.
+# If PXE boot testing is not possible or desired, set this variable to True.
+# For example: If pxe configuration file is not proper to boot
+env__pxe_boot_test_skip = False
+
+# Here is the example of pxe configuration file ordered based on the execution
+# flow:
+1) /tftpboot/pxelinux.cfg/default-arm-zynqmp
+
+ menu include pxelinux.cfg/default-arm
+ timeout 50
+
+ default Linux
+
+2) /tftpboot/pxelinux.cfg/default-arm
+
+ menu title Linux boot selections
+ menu include pxelinux.cfg/default
+
+ label install
+ menu label Invalid boot
+ kernel kernels/install.bin
+ append console=ttyAMA0,38400 debug earlyprintk
+ initrd initrds/uzInitrdDebInstall
+
+ label local
+ menu label Local boot
+ append root=/dev/sdb1
+ localboot 1
+
+ label boot
+ menu label Empty boot
+
+3) /tftpboot/pxelinux.cfg/default
+
+ label Linux
+ menu label Boot kernel
+ kernel Image
+ fdt system.dtb
+ initrd rootfs.cpio.gz.u-boot
+"""
+
+def setup_networking(u_boot_console):
+ test_net.test_net_dhcp(u_boot_console)
+ if not test_net.net_set_up:
+ test_net.test_net_setup_static(u_boot_console)
+
+def setup_tftpboot_boot(u_boot_console):
+ f = u_boot_console.config.env.get('env__net_tftp_bootable_file', None)
+ if not f:
+ pytest.skip('No TFTP bootable file to read')
+
+ setup_networking(u_boot_console)
+ addr = f.get('addr', None)
+ if not addr:
+ addr = u_boot_utils.find_ram_base(u_boot_console)
+
+ fn = f['fn']
+ timeout = f.get('timeout', 50000)
+
+ with u_boot_console.temporary_timeout(timeout):
+ output = u_boot_console.run_command('tftpboot %x %s' % (addr, fn))
+
+ expected_text = 'Bytes transferred = '
+ sz = f.get('size', None)
+ if sz:
+ expected_text += '%d' % sz
+ assert expected_text in output
+
+ expected_crc = f.get('crc32', None)
+ output = u_boot_console.run_command('crc32 %x $filesize' % addr)
+ if expected_crc:
+ assert expected_crc in output
+
+ pattern = f.get('pattern')
+ chk_type = f.get('check_type', 'boot_error')
+ chk_pattern = re.compile(f.get('check_pattern', 'ERROR'))
+ config = f.get('config', None)
+
+ return addr, timeout, pattern, chk_type, chk_pattern, config
+
+@pytest.mark.buildconfigspec('cmd_tftpboot')
+def test_net_tftpboot_boot(u_boot_console):
+ """Boot the loaded image
+
+ A boot file (fit image) is downloaded from the TFTP server and booted using
+ bootm command with the default fit configuration, its boot log pattern are
+ validated.
+
+ The details of the file to download are provided by the boardenv_* file;
+ see the comment at the beginning of this file.
+ """
+ if u_boot_console.config.env.get('env__tftp_boot_test_skip', True):
+ pytest.skip('TFTP boot test is not enabled!')
+
+ addr, timeout, pattern, chk_type, chk_pattern, imcfg = setup_tftpboot_boot(
+ u_boot_console
+ )
+
+ if imcfg:
+ bootcmd = 'bootm %x#%s' % (addr, imcfg)
+ else:
+ bootcmd = 'bootm %x' % addr
+
+ with u_boot_console.enable_check(
+ chk_type, chk_pattern
+ ), u_boot_console.temporary_timeout(timeout):
+ try:
+ # wait_for_prompt=False makes the core code not wait for the U-Boot
+ # prompt code to be seen, since it won't be on a successful kernel
+ # boot
+ u_boot_console.run_command(bootcmd, wait_for_prompt=False)
+
+ # Wait for boot log pattern
+ u_boot_console.wait_for(pattern)
+ finally:
+ # This forces the console object to be shutdown, so any subsequent
+ # test will reset the board back into U-Boot. We want to force this
+ # no matter whether the kernel boot passed or failed.
+ u_boot_console.drain_console()
+ u_boot_console.cleanup_spawn()
+
+def setup_pxe_boot(u_boot_console):
+ f = u_boot_console.config.env.get('env__net_pxe_bootable_file', None)
+ if not f:
+ pytest.skip('No PXE bootable file to read')
+
+ setup_networking(u_boot_console)
+ bootfile = u_boot_console.run_command('echo $bootfile')
+ if not bootfile:
+ bootfile = '<NULL>'
+
+ return f, bootfile
+
+@pytest.mark.buildconfigspec('cmd_pxe')
+def test_net_pxe_boot(u_boot_console):
+ """Test the pxe boot command.
+
+ A pxe configuration file is downloaded from the TFTP server and interpreted
+ to boot the images mentioned in pxe configuration file.
+
+ The details of the file to download are provided by the boardenv_* file;
+ see the comment at the beginning of this file.
+ """
+ if u_boot_console.config.env.get('env__pxe_boot_test_skip', True):
+ pytest.skip('PXE boot test is not enabled!')
+
+ f, bootfile = setup_pxe_boot(u_boot_console)
+ addr = f.get('addr', None)
+ timeout = f.get('timeout', u_boot_console.p.timeout)
+ fn = f['fn']
+
+ if addr:
+ u_boot_console.run_command('setenv pxefile_addr_r %x' % addr)
+
+ with u_boot_console.temporary_timeout(timeout):
+ output = u_boot_console.run_command('pxe get')
+
+ expected_text = 'Bytes transferred = '
+ sz = f.get('size', None)
+ if sz:
+ expected_text += '%d' % sz
+ assert 'TIMEOUT' not in output
+ assert expected_text in output
+ assert f"Config file '{bootfile}' found" in output
+
+ pattern = f.get('pattern')
+ chk_type = f.get('check_type', 'boot_error')
+ chk_pattern = re.compile(f.get('check_pattern', 'ERROR'))
+
+ if not addr:
+ pxe_boot_cmd = 'pxe boot'
+ else:
+ pxe_boot_cmd = 'pxe boot %x' % addr
+
+ with u_boot_console.enable_check(
+ chk_type, chk_pattern
+ ), u_boot_console.temporary_timeout(timeout):
+ try:
+ u_boot_console.run_command(pxe_boot_cmd, wait_for_prompt=False)
+ u_boot_console.wait_for(pattern)
+ finally:
+ u_boot_console.drain_console()
+ u_boot_console.cleanup_spawn()
+
+@pytest.mark.buildconfigspec('cmd_pxe')
+def test_net_pxe_boot_config(u_boot_console):
+ """Test the pxe boot command by selecting different combination of labels
+
+ A pxe configuration file is downloaded from the TFTP server and interpreted
+ to boot the images mentioned in pxe configuration file.
+
+ The details of the file to download are provided by the boardenv_* file;
+ see the comment at the beginning of this file.
+ """
+ if u_boot_console.config.env.get('env__pxe_boot_test_skip', True):
+ pytest.skip('PXE boot test is not enabled!')
+
+ f, bootfile = setup_pxe_boot(u_boot_console)
+ addr = f.get('addr', None)
+ timeout = f.get('timeout', u_boot_console.p.timeout)
+ fn = f['fn']
+ local_label = f['local_label']
+ empty_label = f['empty_label']
+ exp_str_local = f['exp_str_local']
+ exp_str_empty = f['exp_str_empty']
+
+ if addr:
+ u_boot_console.run_command('setenv pxefile_addr_r %x' % addr)
+
+ with u_boot_console.temporary_timeout(timeout):
+ output = u_boot_console.run_command('pxe get')
+
+ expected_text = 'Bytes transferred = '
+ sz = f.get('size', None)
+ if sz:
+ expected_text += '%d' % sz
+ assert 'TIMEOUT' not in output
+ assert expected_text in output
+ assert f"Config file '{bootfile}' found" in output
+
+ pattern = f.get('pattern')
+ chk_type = f.get('check_type', 'boot_error')
+ chk_pattern = re.compile(f.get('check_pattern', 'ERROR'))
+
+ if not addr:
+ pxe_boot_cmd = 'pxe boot'
+ else:
+ pxe_boot_cmd = 'pxe boot %x' % addr
+
+ with u_boot_console.enable_check(
+ chk_type, chk_pattern
+ ), u_boot_console.temporary_timeout(timeout):
+ try:
+ u_boot_console.run_command(pxe_boot_cmd, wait_for_prompt=False)
+
+ # pxe config is loaded where multiple labels are there and need to
+ # select particular label to boot and check for expected string
+ # In this case, local label is selected and it should look for
+ # localcmd env variable and if that variable is not defined it
+ # should not boot it and come out to u-boot prompt
+ u_boot_console.wait_for('Enter choice:')
+ u_boot_console.run_command(local_label, wait_for_prompt=False)
+ expected_str = u_boot_console.p.expect([exp_str_local])
+ assert (
+ expected_str == 0
+ ), f'Expected string: {exp_str_local} did not match!'
+
+ # In this case, empty label is selected and it should look for
+ # kernel image path and if it is not set it should fail it and load
+ # default label to boot
+ u_boot_console.run_command(pxe_boot_cmd, wait_for_prompt=False)
+ u_boot_console.wait_for('Enter choice:')
+ u_boot_console.run_command(empty_label, wait_for_prompt=False)
+ expected_str = u_boot_console.p.expect([exp_str_empty])
+ assert (
+ expected_str == 0
+ ), f'Expected string: {exp_str_empty} did not match!'
+
+ u_boot_console.wait_for(pattern)
+ finally:
+ u_boot_console.drain_console()
+ u_boot_console.cleanup_spawn()
+
+@pytest.mark.buildconfigspec('cmd_pxe')
+def test_net_pxe_boot_config_invalid(u_boot_console):
+ """Test the pxe boot command by selecting invalid label
+
+ A pxe configuration file is downloaded from the TFTP server and interpreted
+ to boot the images mentioned in pxe configuration file.
+
+ The details of the file to download are provided by the boardenv_* file;
+ see the comment at the beginning of this file.
+ """
+ if u_boot_console.config.env.get('env__pxe_boot_test_skip', True):
+ pytest.skip('PXE boot test is not enabled!')
+
+ f, bootfile = setup_pxe_boot(u_boot_console)
+ addr = f.get('addr', None)
+ timeout = f.get('timeout', u_boot_console.p.timeout)
+ fn = f['fn']
+ invalid_label = f['invalid_label']
+ exp_str_invalid = f['exp_str_invalid']
+
+ if addr:
+ u_boot_console.run_command('setenv pxefile_addr_r %x' % addr)
+
+ with u_boot_console.temporary_timeout(timeout):
+ output = u_boot_console.run_command('pxe get')
+
+ expected_text = 'Bytes transferred = '
+ sz = f.get('size', None)
+ if sz:
+ expected_text += '%d' % sz
+ assert 'TIMEOUT' not in output
+ assert expected_text in output
+ assert f"Config file '{bootfile}' found" in output
+
+ pattern = f.get('pattern')
+ if not addr:
+ pxe_boot_cmd = 'pxe boot'
+ else:
+ pxe_boot_cmd = 'pxe boot %x' % addr
+
+ with u_boot_console.temporary_timeout(timeout):
+ try:
+ u_boot_console.run_command(pxe_boot_cmd, wait_for_prompt=False)
+
+ # pxe config is loaded where multiple labels are there and need to
+ # select particular label to boot and check for expected string
+ # In this case invalid label is selected, it should load invalid
+ # label and if it fails it should load the default label to boot
+ u_boot_console.wait_for('Enter choice:')
+ u_boot_console.run_command(invalid_label, wait_for_prompt=False)
+ expected_str = u_boot_console.p.expect([exp_str_invalid])
+ assert (
+ expected_str == 0
+ ), f'Expected string: {exp_str_invalid} did not match!'
+
+ u_boot_console.wait_for(pattern)
+ finally:
+ u_boot_console.drain_console()
+ u_boot_console.cleanup_spawn()
diff --git a/test/py/tests/test_tpm2.py b/test/py/tests/test_tpm2.py
index 1d654cd..75f5d31 100644
--- a/test/py/tests/test_tpm2.py
+++ b/test/py/tests/test_tpm2.py
@@ -257,7 +257,7 @@
updates = int(re.findall(r'\d+', str)[0])
# Check the output value
- assert 'PCR #10 content' in read_pcr
+ assert 'PCR #10 sha256 32 byte content' in read_pcr
assert '00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00' in read_pcr
@pytest.mark.buildconfigspec('cmd_tpm_v2')
diff --git a/test/py/tests/test_trace.py b/test/py/tests/test_trace.py
index 7c5696c..ec1e624 100644
--- a/test/py/tests/test_trace.py
+++ b/test/py/tests/test_trace.py
@@ -12,7 +12,7 @@
TMPDIR = '/tmp/test_trace'
# Decode a function-graph line
-RE_LINE = re.compile(r'.*0\.\.\.\.\. \s*([0-9.]*): func.*[|](\s*)(\S.*)?([{};])$')
+RE_LINE = re.compile(r'.*0\.\.\.\.\.? \s*([0-9.]*): func.*[|](\s*)(\S.*)?([{};])$')
def collect_trace(cons):
@@ -175,7 +175,7 @@
# Then look for this:
# u-boot-1 0..... 282.101375: funcgraph_exit: 0.006 us | }
# Then check for this:
- # u-boot-1 0..... 282.101375: funcgraph_entry: 0.000 us | initcall_is_event();
+ # u-boot-1 0..... 282.101375: funcgraph_entry: 0.000 us | calc_reloc_ofs();
expected_indent = None
found_start = False
@@ -199,7 +199,7 @@
# The next function after initf_bootstage() exits should be
# initcall_is_event()
- assert upto == 'initcall_is_event()'
+ assert upto == 'calc_reloc_ofs()'
# Now look for initf_dm() and dm_timer_init() so we can check the bootstage
# time
diff --git a/test/py/tests/test_ut.py b/test/py/tests/test_ut.py
index c169c83..5820506 100644
--- a/test/py/tests/test_ut.py
+++ b/test/py/tests/test_ut.py
@@ -470,6 +470,7 @@
fh.write(data)
@pytest.mark.buildconfigspec('cmd_bootflow')
+@pytest.mark.buildconfigspec('sandbox')
def test_ut_dm_init_bootstd(u_boot_console):
"""Initialise data for bootflow tests"""
diff --git a/test/py/u_boot_console_base.py b/test/py/u_boot_console_base.py
index 3e01be1..76a550d 100644
--- a/test/py/u_boot_console_base.py
+++ b/test/py/u_boot_console_base.py
@@ -55,6 +55,32 @@
self.console.disable_check_count[self.check_type] -= 1
self.console.eval_bad_patterns()
+class ConsoleEnableCheck(object):
+ """Context manager (for Python's with statement) that temporarily enables
+ the specified console output error check. This is useful when executing a
+ command that might raise an extra bad pattern, beyond the default bad
+ patterns, in order to validate that the extra bad pattern is actually
+ detected. This class is used internally by ConsoleBase::enable_check(); it
+ is not intended for direct usage."""
+
+ def __init__(self, console, check_type, check_pattern):
+ self.console = console
+ self.check_type = check_type
+ self.check_pattern = check_pattern
+
+ def __enter__(self):
+ global bad_pattern_defs
+ self.default_bad_patterns = bad_pattern_defs
+ bad_pattern_defs += ((self.check_type, self.check_pattern),)
+ self.console.disable_check_count = {pat[PAT_ID]: 0 for pat in bad_pattern_defs}
+ self.console.eval_bad_patterns()
+
+ def __exit__(self, extype, value, traceback):
+ global bad_pattern_defs
+ bad_pattern_defs = self.default_bad_patterns
+ self.console.disable_check_count = {pat[PAT_ID]: 0 for pat in bad_pattern_defs}
+ self.console.eval_bad_patterns()
+
class ConsoleSetupTimeout(object):
"""Context manager (for Python's with statement) that temporarily sets up
timeout for specific command. This is useful when execution time is greater
@@ -492,6 +518,24 @@
return ConsoleDisableCheck(self, check_type)
+ def enable_check(self, check_type, check_pattern):
+ """Temporarily enable an error check of U-Boot's output.
+
+ Create a new context manager (for use with the "with" statement) which
+ temporarily enables a particular console output error check. The
+ arguments form a new element of bad_pattern_defs defined above.
+
+ Args:
+ check_type: The type of error-check or bad pattern to enable.
+ check_pattern: The regexes for text error pattern or bad pattern
+ to be checked.
+
+ Returns:
+ A context manager object.
+ """
+
+ return ConsoleEnableCheck(self, check_type, check_pattern)
+
def temporary_timeout(self, timeout):
"""Temporarily set up different timeout for commands.
diff --git a/test/py/u_boot_console_sandbox.py b/test/py/u_boot_console_sandbox.py
index 27c6db8..7bc44c7 100644
--- a/test/py/u_boot_console_sandbox.py
+++ b/test/py/u_boot_console_sandbox.py
@@ -58,7 +58,7 @@
if self.use_dtb:
cmd += ['-d', self.config.dtb]
cmd += self.sandbox_flags
- return Spawn(cmd, cwd=self.config.source_dir)
+ return Spawn(cmd, cwd=self.config.source_dir, decode_signal=True)
def restart_uboot_with_flags(self, flags, expect_reset=False, use_dtb=True):
"""Run U-Boot with the given command-line flags
diff --git a/test/py/u_boot_spawn.py b/test/py/u_boot_spawn.py
index 7c48d96..97e95e0 100644
--- a/test/py/u_boot_spawn.py
+++ b/test/py/u_boot_spawn.py
@@ -24,18 +24,20 @@
output: accumulated output from expect()
"""
- def __init__(self, args, cwd=None):
+ def __init__(self, args, cwd=None, decode_signal=False):
"""Spawn (fork/exec) the sub-process.
Args:
args: array of processs arguments. argv[0] is the command to
execute.
cwd: the directory to run the process in, or None for no change.
+ decode_signal (bool): True to indicate the exception number when
+ something goes wrong
Returns:
Nothing.
"""
-
+ self.decode_signal = decode_signal
self.waited = False
self.exit_code = 0
self.exit_info = ''
@@ -197,12 +199,12 @@
# With sandbox, try to detect when U-Boot exits when it
# shouldn't and explain why. This is much more friendly than
# just dying with an I/O error
- if err.errno == 5: # Input/output error
+ if self.decode_signal and err.errno == 5: # I/O error
alive, _, info = self.checkalive()
if alive:
raise err
raise ValueError('U-Boot exited with %s' % info)
- raise err
+ raise
if self.logfile_read:
self.logfile_read.write(c)
self.buf += c
diff --git a/tools/Kconfig b/tools/Kconfig
index 667807b..5c75af4 100644
--- a/tools/Kconfig
+++ b/tools/Kconfig
@@ -98,7 +98,7 @@
config TOOLS_MKEFICAPSULE
bool "Build efimkcapsule command"
- default y if EFI_CAPSULE_ON_DISK
+ default y if EFI_LOADER
help
This command allows users to create a UEFI capsule file and,
optionally sign that file. If you want to enable UEFI capsule
diff --git a/tools/binman/binman.rst b/tools/binman/binman.rst
index 230e055..872e974 100644
--- a/tools/binman/binman.rst
+++ b/tools/binman/binman.rst
@@ -711,6 +711,13 @@
information about what needs to be fixed. See missing-blob-help for the
message for each tag.
+assume-size:
+ Sets the assumed size of a blob entry if it is missing. This allows for a
+ check that the rest of the image fits into the available space, even when
+ the contents are not available. If the entry is missing, Binman will use
+ this assumed size for the entry size, including creating a fake file of that
+ size if requested.
+
no-expanded:
By default binman substitutes entries with expanded versions if available,
so that a `u-boot` entry type turns into `u-boot-expanded`, for example. The
diff --git a/tools/binman/btool/cst.py b/tools/binman/btool/cst.py
new file mode 100644
index 0000000..30e78bd
--- /dev/null
+++ b/tools/binman/btool/cst.py
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright 2024 Marek Vasut <marex@denx.de>
+#
+"""Bintool implementation for cst"""
+
+import re
+
+from binman import bintool
+
+class Bintoolcst(bintool.Bintool):
+ """Image generation for U-Boot
+
+ This bintool supports running `cst` with some basic parameters as
+ needed by binman.
+ """
+ def __init__(self, name):
+ super().__init__(name, 'Sign NXP i.MX image')
+
+ # pylint: disable=R0913
+ def run(self, output_fname=None):
+ """Run cst
+
+ Args:
+ output_fname: Output filename to write to
+ """
+ args = []
+ if output_fname:
+ args += ['-o', output_fname]
+ return self.run_cmd(*args)
+
+ def fetch(self, method):
+ """Fetch handler for cst
+
+ This installs cst using the apt utility.
+
+ Args:
+ method (FETCH_...): Method to use
+
+ Returns:
+ True if the file was fetched and now installed, None if a method
+ other than FETCH_BIN was requested
+
+ Raises:
+ Valuerror: Fetching could not be completed
+ """
+ if method != bintool.FETCH_BIN:
+ return None
+ return self.apt_install('imx-code-signing-tool')
diff --git a/tools/binman/entries.rst b/tools/binman/entries.rst
index 254afe7..bdda1ef 100644
--- a/tools/binman/entries.rst
+++ b/tools/binman/entries.rst
@@ -470,11 +470,11 @@
.. _etype_efi_capsule:
-Entry: capsule: Entry for generating EFI Capsule files
-------------------------------------------------------
+Entry: efi-capsule: Generate EFI capsules
+-----------------------------------------
-The parameters needed for generation of the capsules can be provided
-as properties in the entry.
+The parameters needed for generation of the capsules can
+be provided as properties in the entry.
Properties / Entry arguments:
- image-index: Unique number for identifying corresponding
@@ -495,9 +495,9 @@
file. Mandatory property for generating signed capsules.
- oem-flags - OEM flags to be passed through capsule header.
- Since this is a subclass of Entry_section, all properties of the parent
- class also apply here. Except for the properties stated as mandatory, the
- rest of the properties are optional.
+Since this is a subclass of Entry_section, all properties of the parent
+class also apply here. Except for the properties stated as mandatory, the
+rest of the properties are optional.
For more details on the description of the capsule format, and the capsule
update functionality, refer Section 8.5 and Chapter 23 in the `UEFI
@@ -510,17 +510,17 @@
A typical capsule entry node would then look something like this::
capsule {
- type = "efi-capsule";
- image-index = <0x1>;
- /* Image GUID for testing capsule update */
- image-guid = SANDBOX_UBOOT_IMAGE_GUID;
- hardware-instance = <0x0>;
- private-key = "path/to/the/private/key";
- public-key-cert = "path/to/the/public-key-cert";
- oem-flags = <0x8000>;
+ type = "efi-capsule";
+ image-index = <0x1>;
+ /* Image GUID for testing capsule update */
+ image-guid = SANDBOX_UBOOT_IMAGE_GUID;
+ hardware-instance = <0x0>;
+ private-key = "path/to/the/private/key";
+ public-key-cert = "path/to/the/public-key-cert";
+ oem-flags = <0x8000>;
- u-boot {
- };
+ u-boot {
+ };
};
In the above example, the capsule payload is the U-Boot image. The
@@ -534,8 +534,8 @@
.. _etype_efi_empty_capsule:
-Entry: efi-empty-capsule: Entry for generating EFI Empty Capsule files
-----------------------------------------------------------------------
+Entry: efi-empty-capsule: Generate EFI empty capsules
+-----------------------------------------------------
The parameters needed for generation of the empty capsules can
be provided as properties in the entry.
@@ -551,22 +551,22 @@
specification`_. For more information on the empty capsule, refer the
sections 2.3.2 and 2.3.3 in the `Dependable Boot specification`_.
-A typical accept empty capsule entry node would then look something
-like this::
+A typical accept empty capsule entry node would then look something like
+this::
empty-capsule {
- type = "efi-empty-capsule";
- /* GUID of the image being accepted */
- image-type-id = SANDBOX_UBOOT_IMAGE_GUID;
- capsule-type = "accept";
+ type = "efi-empty-capsule";
+ /* GUID of image being accepted */
+ image-type-id = SANDBOX_UBOOT_IMAGE_GUID;
+ capsule-type = "accept";
};
-A typical revert empty capsule entry node would then look something
-like this::
+A typical revert empty capsule entry node would then look something like
+this::
empty-capsule {
- type = "efi-empty-capsule";
- capsule-type = "revert";
+ type = "efi-empty-capsule";
+ capsule-type = "revert";
};
The empty capsules do not have any input payload image.
@@ -1519,7 +1519,29 @@
The contents are set by the containing section, e.g. the section's pad
byte.
+
+
+.. _etype_nxp_imx8mcst:
+Entry: nxp-imx8mcst: NXP i.MX8M CST .cfg file generator and cst invoker
+-----------------------------------------------------------------------
+
+Properties / Entry arguments:
+ - nxp,loader-address - loader address (SPL text base)
+
+
+
+.. _etype_nxp_imx8mimage:
+
+Entry: nxp-imx8mimage: NXP i.MX8M imx8mimage .cfg file generator and mkimage invoker
+------------------------------------------------------------------------------------
+
+Properties / Entry arguments:
+ - nxp,boot-from - device to boot from (e.g. 'sd')
+ - nxp,loader-address - loader address (SPL text base)
+ - nxp,rom-version - BootROM version ('2' for i.MX8M Nano and Plus)
+
+
.. _etype_opensbi:
@@ -1929,6 +1951,12 @@
- content: List of phandles to entries to sign
- keyfile: Filename of file containing key to sign binary with
- sha: Hash function to be used for signing
+ - auth-in-place: This is an integer field that contains two pieces
+ of information:
+
+ - Lower Byte - Remains 0x02 as per our use case
+ ( 0x02: Move the authenticated binary back to the header )
+ - Upper Byte - The Host ID of the core owning the firewall
Output files:
- input.<unique_name> - input file passed to openssl
@@ -1937,6 +1965,35 @@
- cert.<unique_name> - output file generated by openssl (which is
used as the entry contents)
+Depending on auth-in-place information in the inputs, we read the
+firewall nodes that describe the configurations of firewall that TIFS
+will be doing after reading the certificate.
+
+The syntax of the firewall nodes are as such::
+
+ firewall-257-0 {
+ id = <257>; /* The ID of the firewall being configured */
+ region = <0>; /* Region number to configure */
+
+ control = /* The control register */
+ <(FWCTRL_EN | FWCTRL_LOCK | FWCTRL_BG | FWCTRL_CACHE)>;
+
+ permissions = /* The permission registers */
+ <((FWPRIVID_ALL << FWPRIVID_SHIFT) |
+ FWPERM_SECURE_PRIV_RWCD |
+ FWPERM_SECURE_USER_RWCD |
+ FWPERM_NON_SECURE_PRIV_RWCD |
+ FWPERM_NON_SECURE_USER_RWCD)>;
+
+ /* More defines can be found in k3-security.h */
+
+ start_address = /* The Start Address of the firewall */
+ <0x0 0x0>;
+ end_address = /* The End Address of the firewall */
+ <0xff 0xffffffff>;
+ };
+
+
openssl signs the provided data, using the TI templated config file and
writes the signature in this entry. This allows verification that the
data is genuine.
diff --git a/tools/binman/entry.py b/tools/binman/entry.py
index 42e0b7b..219d5dc 100644
--- a/tools/binman/entry.py
+++ b/tools/binman/entry.py
@@ -315,6 +315,7 @@
self.overlap = fdt_util.GetBool(self._node, 'overlap')
if self.overlap:
self.required_props += ['offset', 'size']
+ self.assume_size = fdt_util.GetInt(self._node, 'assume-size', 0)
# This is only supported by blobs and sections at present
self.compress = fdt_util.GetString(self._node, 'compress', 'none')
@@ -812,7 +813,7 @@
as missing
"""
print('''Binman Entry Documentation
-===========================
+==========================
This file describes the entry types supported by binman. These entry types can
be placed in an image one by one to build up a final firmware image. It is
diff --git a/tools/binman/entry_test.py b/tools/binman/entry_test.py
index ac6582c..40d74d4 100644
--- a/tools/binman/entry_test.py
+++ b/tools/binman/entry_test.py
@@ -103,7 +103,7 @@
ent = entry.Entry.Create(None, self.GetNode(), 'missing',
missing_etype=True)
self.assertTrue(isinstance(ent, Entry_blob))
- self.assertEquals('missing', ent.etype)
+ self.assertEqual('missing', ent.etype)
def testDecompressData(self):
"""Test the DecompressData() method of the base class"""
@@ -111,8 +111,8 @@
base.compress = 'lz4'
bintools = {}
base.comp_bintool = base.AddBintool(bintools, '_testing')
- self.assertEquals(tools.get_bytes(0, 1024), base.CompressData(b'abc'))
- self.assertEquals(tools.get_bytes(0, 1024), base.DecompressData(b'abc'))
+ self.assertEqual(tools.get_bytes(0, 1024), base.CompressData(b'abc'))
+ self.assertEqual(tools.get_bytes(0, 1024), base.DecompressData(b'abc'))
def testLookupOffset(self):
"""Test the lookup_offset() method of the base class"""
diff --git a/tools/binman/etype/blob.py b/tools/binman/etype/blob.py
index 064fae5..041e112 100644
--- a/tools/binman/etype/blob.py
+++ b/tools/binman/etype/blob.py
@@ -48,11 +48,16 @@
self.external and (self.optional or self.section.GetAllowMissing()))
# Allow the file to be missing
if not self._pathname:
+ if not fake_size and self.assume_size:
+ fake_size = self.assume_size
self._pathname, faked = self.check_fake_fname(self._filename,
fake_size)
self.missing = True
if not faked:
- self.SetContents(b'')
+ content_size = 0
+ if self.assume_size: # Ensure we get test coverage on next line
+ content_size = self.assume_size
+ self.SetContents(tools.get_bytes(0, content_size))
return True
self.ReadBlobContents()
diff --git a/tools/binman/etype/efi_capsule.py b/tools/binman/etype/efi_capsule.py
index e320371..751f654 100644
--- a/tools/binman/etype/efi_capsule.py
+++ b/tools/binman/etype/efi_capsule.py
@@ -36,23 +36,23 @@
be provided as properties in the entry.
Properties / Entry arguments:
- - image-index: Unique number for identifying corresponding
- payload image. Number between 1 and descriptor count, i.e.
- the total number of firmware images that can be updated. Mandatory
- property.
- - image-guid: Image GUID which will be used for identifying the
- updatable image on the board. Mandatory property.
- - hardware-instance: Optional number for identifying unique
- hardware instance of a device in the system. Default value of 0
- for images where value is not to be used.
- - fw-version: Value of image version that can be put on the capsule
- through the Firmware Management Protocol(FMP) header.
- - monotonic-count: Count used when signing an image.
- - private-key: Path to PEM formatted .key private key file. Mandatory
- property for generating signed capsules.
- - public-key-cert: Path to PEM formatted .crt public key certificate
- file. Mandatory property for generating signed capsules.
- - oem-flags - OEM flags to be passed through capsule header.
+ - image-index: Unique number for identifying corresponding
+ payload image. Number between 1 and descriptor count, i.e.
+ the total number of firmware images that can be updated. Mandatory
+ property.
+ - image-guid: Image GUID which will be used for identifying the
+ updatable image on the board. Mandatory property.
+ - hardware-instance: Optional number for identifying unique
+ hardware instance of a device in the system. Default value of 0
+ for images where value is not to be used.
+ - fw-version: Value of image version that can be put on the capsule
+ through the Firmware Management Protocol(FMP) header.
+ - monotonic-count: Count used when signing an image.
+ - private-key: Path to PEM formatted .key private key file. Mandatory
+ property for generating signed capsules.
+ - public-key-cert: Path to PEM formatted .crt public key certificate
+ file. Mandatory property for generating signed capsules.
+ - oem-flags - OEM flags to be passed through capsule header.
Since this is a subclass of Entry_section, all properties of the parent
class also apply here. Except for the properties stated as mandatory, the
@@ -66,9 +66,9 @@
properties in the entry. The payload to be used in the capsule is to be
provided as a subnode of the capsule entry.
- A typical capsule entry node would then look something like this
+ A typical capsule entry node would then look something like this::
- capsule {
+ capsule {
type = "efi-capsule";
image-index = <0x1>;
/* Image GUID for testing capsule update */
@@ -80,7 +80,7 @@
u-boot {
};
- };
+ };
In the above example, the capsule payload is the U-Boot image. The
capsule entry would read the contents of the payload and put them
diff --git a/tools/binman/etype/efi_empty_capsule.py b/tools/binman/etype/efi_empty_capsule.py
index 064bf9a..1d99fbf 100644
--- a/tools/binman/etype/efi_empty_capsule.py
+++ b/tools/binman/etype/efi_empty_capsule.py
@@ -19,31 +19,33 @@
be provided as properties in the entry.
Properties / Entry arguments:
- - image-guid: Image GUID which will be used for identifying the
- updatable image on the board. Mandatory for accept capsule.
- - capsule-type - String to indicate type of capsule to generate. Valid
- values are 'accept' and 'revert'.
+ - image-guid: Image GUID which will be used for identifying the
+ updatable image on the board. Mandatory for accept capsule.
+ - capsule-type - String to indicate type of capsule to generate. Valid
+ values are 'accept' and 'revert'.
For more details on the description of the capsule format, and the capsule
update functionality, refer Section 8.5 and Chapter 23 in the `UEFI
specification`_. For more information on the empty capsule, refer the
sections 2.3.2 and 2.3.3 in the `Dependable Boot specification`_.
- A typical accept empty capsule entry node would then look something like this
+ A typical accept empty capsule entry node would then look something like
+ this::
- empty-capsule {
+ empty-capsule {
type = "efi-empty-capsule";
/* GUID of image being accepted */
image-type-id = SANDBOX_UBOOT_IMAGE_GUID;
capsule-type = "accept";
- };
+ };
- A typical revert empty capsule entry node would then look something like this
+ A typical revert empty capsule entry node would then look something like
+ this::
- empty-capsule {
+ empty-capsule {
type = "efi-empty-capsule";
capsule-type = "revert";
- };
+ };
The empty capsules do not have any input payload image.
diff --git a/tools/binman/etype/intel_descriptor.py b/tools/binman/etype/intel_descriptor.py
index 7fe88a9..3ce967f 100644
--- a/tools/binman/etype/intel_descriptor.py
+++ b/tools/binman/etype/intel_descriptor.py
@@ -59,7 +59,7 @@
if self.missing:
# Return zero offsets so that these entries get placed somewhere
if self.HasSibling('intel-me'):
- info['intel-me'] = [0, None]
+ info['intel-me'] = [0x1000, None]
return info
offset = self.data.find(FD_SIGNATURE)
if offset == -1:
diff --git a/tools/binman/etype/nxp_imx8mcst.py b/tools/binman/etype/nxp_imx8mcst.py
new file mode 100644
index 0000000..8221517
--- /dev/null
+++ b/tools/binman/etype/nxp_imx8mcst.py
@@ -0,0 +1,164 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright 2023-2024 Marek Vasut <marex@denx.de>
+# Written with much help from Simon Glass <sjg@chromium.org>
+#
+# Entry-type module for generating the i.MX8M code signing tool
+# input configuration file and invocation of cst on generated
+# input configuration file and input data to be signed.
+#
+
+import configparser
+import os
+import struct
+
+from collections import OrderedDict
+
+from binman.entry import Entry
+from binman.etype.mkimage import Entry_mkimage
+from binman.etype.section import Entry_section
+from binman import elf
+from dtoc import fdt_util
+from u_boot_pylib import tools
+
+MAGIC_NXP_IMX_IVT = 0x412000d1
+MAGIC_FITIMAGE = 0xedfe0dd0
+
+csf_config_template = """
+[Header]
+ Version = 4.3
+ Hash Algorithm = sha256
+ Engine = CAAM
+ Engine Configuration = 0
+ Certificate Format = X509
+ Signature Format = CMS
+
+[Install SRK]
+ File = "SRK_1_2_3_4_table.bin"
+ Source index = 0
+
+[Install CSFK]
+ File = "CSF1_1_sha256_4096_65537_v3_usr_crt.pem"
+
+[Authenticate CSF]
+
+[Unlock]
+ Engine = CAAM
+ Features = MID
+
+[Install Key]
+ Verification index = 0
+ Target Index = 2
+ File = "IMG1_1_sha256_4096_65537_v3_usr_crt.pem"
+
+[Authenticate Data]
+ Verification index = 2
+ Blocks = 0x1234 0x78 0xabcd "data.bin"
+"""
+
+class Entry_nxp_imx8mcst(Entry_mkimage):
+ """NXP i.MX8M CST .cfg file generator and cst invoker
+
+ Properties / Entry arguments:
+ - nxp,loader-address - loader address (SPL text base)
+ """
+
+ def __init__(self, section, etype, node):
+ super().__init__(section, etype, node)
+ self.required_props = ['nxp,loader-address']
+
+ def ReadNode(self):
+ super().ReadNode()
+ self.loader_address = fdt_util.GetInt(self._node, 'nxp,loader-address')
+ self.srk_table = os.getenv('SRK_TABLE', fdt_util.GetString(self._node, 'nxp,srk-table', 'SRK_1_2_3_4_table.bin'))
+ self.csf_crt = os.getenv('CSF_KEY', fdt_util.GetString(self._node, 'nxp,csf-crt', 'CSF1_1_sha256_4096_65537_v3_usr_crt.pem'))
+ self.img_crt = os.getenv('IMG_KEY', fdt_util.GetString(self._node, 'nxp,img-crt', 'IMG1_1_sha256_4096_65537_v3_usr_crt.pem'))
+ self.unlock = fdt_util.GetBool(self._node, 'nxp,unlock')
+ self.ReadEntries()
+
+ def BuildSectionData(self, required):
+ data, input_fname, uniq = self.collect_contents_to_file(
+ self._entries.values(), 'input')
+
+ # Parse the input data and figure out what it is that is being signed.
+ # - If it is mkimage'd imx8mimage, then extract to be signed data size
+ # from imx8mimage header, and calculate CSF blob offset right past
+ # the SPL from this information.
+ # - If it is fitImage, then pad the image to 4k, add generated IVT and
+ # sign the whole payload, then append CSF blob at the end right past
+ # the IVT.
+ signtype = struct.unpack('<I', data[:4])[0]
+ signbase = self.loader_address
+ signsize = 0
+ if signtype == MAGIC_NXP_IMX_IVT: # SPL/imx8mimage
+ # Sign the payload including imx8mimage header
+ # (extra 0x40 bytes before the payload)
+ signbase -= 0x40
+ signsize = struct.unpack('<I', data[24:28])[0] - signbase
+ # Remove mkimage generated padding from the end of data
+ data = data[:signsize]
+ elif signtype == MAGIC_FITIMAGE: # fitImage
+ # Align fitImage to 4k
+ signsize = tools.align(len(data), 0x1000)
+ data += tools.get_bytes(0, signsize - len(data))
+ # Add generated IVT
+ data += struct.pack('<I', MAGIC_NXP_IMX_IVT)
+ data += struct.pack('<I', signbase + signsize) # IVT base
+ data += struct.pack('<I', 0)
+ data += struct.pack('<I', 0)
+ data += struct.pack('<I', 0)
+ data += struct.pack('<I', signbase + signsize) # IVT base
+ data += struct.pack('<I', signbase + signsize + 0x20) # CSF base
+ data += struct.pack('<I', 0)
+ else:
+ # Unknown section type, pass input data through.
+ return data
+
+ # Write out customized data to be signed
+ output_dname = tools.get_output_filename(f'nxp.cst-input-data.{uniq}')
+ tools.write_file(output_dname, data)
+
+ # Generate CST configuration file used to sign payload
+ cfg_fname = tools.get_output_filename('nxp.csf-config-txt.%s' % uniq)
+ config = configparser.ConfigParser()
+ # Do not make key names lowercase
+ config.optionxform = str
+ # Load configuration template and modify keys of interest
+ config.read_string(csf_config_template)
+ config['Install SRK']['File'] = '"' + self.srk_table + '"'
+ config['Install CSFK']['File'] = '"' + self.csf_crt + '"'
+ config['Install Key']['File'] = '"' + self.img_crt + '"'
+ config['Authenticate Data']['Blocks'] = hex(signbase) + ' 0 ' + hex(len(data)) + ' "' + str(output_dname) + '"'
+ if not self.unlock:
+ config.remove_section('Unlock')
+ with open(cfg_fname, 'w') as cfgf:
+ config.write(cfgf)
+
+ output_fname = tools.get_output_filename(f'nxp.csf-output-blob.{uniq}')
+ args = ['-i', cfg_fname, '-o', output_fname]
+ if self.cst.run_cmd(*args) is not None:
+ outdata = tools.read_file(output_fname)
+ return data + outdata
+ else:
+ # Bintool is missing; just use the input data as the output
+ self.record_missing_bintool(self.cst)
+ return data
+
+ def SetImagePos(self, image_pos):
+ # Customized SoC specific SetImagePos which skips the mkimage etype
+ # implementation and removes the 0x48 offset introduced there. That
+ # offset is only used for uImage/fitImage, which is not the case in
+ # here.
+ upto = 0x00
+ for entry in super().GetEntries().values():
+ entry.SetOffsetSize(upto, None)
+
+ # Give up if any entries lack a size
+ if entry.size is None:
+ return
+ upto += entry.size
+
+ Entry_section.SetImagePos(self, image_pos)
+
+ def AddBintools(self, btools):
+ super().AddBintools(btools)
+ self.cst = self.AddBintool(btools, 'cst')
diff --git a/tools/binman/etype/ti_secure.py b/tools/binman/etype/ti_secure.py
index 704dcf8..420ee26 100644
--- a/tools/binman/etype/ti_secure.py
+++ b/tools/binman/etype/ti_secure.py
@@ -53,10 +53,11 @@
- keyfile: Filename of file containing key to sign binary with
- sha: Hash function to be used for signing
- auth-in-place: This is an integer field that contains two pieces
- of information
- Lower Byte - Remains 0x02 as per our use case
- ( 0x02: Move the authenticated binary back to the header )
- Upper Byte - The Host ID of the core owning the firewall
+ of information:
+
+ - Lower Byte - Remains 0x02 as per our use case
+ ( 0x02: Move the authenticated binary back to the header )
+ - Upper Byte - The Host ID of the core owning the firewall
Output files:
- input.<unique_name> - input file passed to openssl
@@ -69,29 +70,29 @@
firewall nodes that describe the configurations of firewall that TIFS
will be doing after reading the certificate.
- The syntax of the firewall nodes are as such:
+ The syntax of the firewall nodes are as such::
- firewall-257-0 {
- id = <257>; /* The ID of the firewall being configured */
- region = <0>; /* Region number to configure */
+ firewall-257-0 {
+ id = <257>; /* The ID of the firewall being configured */
+ region = <0>; /* Region number to configure */
- control = /* The control register */
- <(FWCTRL_EN | FWCTRL_LOCK | FWCTRL_BG | FWCTRL_CACHE)>;
+ control = /* The control register */
+ <(FWCTRL_EN | FWCTRL_LOCK | FWCTRL_BG | FWCTRL_CACHE)>;
- permissions = /* The permission registers */
- <((FWPRIVID_ALL << FWPRIVID_SHIFT) |
- FWPERM_SECURE_PRIV_RWCD |
- FWPERM_SECURE_USER_RWCD |
- FWPERM_NON_SECURE_PRIV_RWCD |
- FWPERM_NON_SECURE_USER_RWCD)>;
+ permissions = /* The permission registers */
+ <((FWPRIVID_ALL << FWPRIVID_SHIFT) |
+ FWPERM_SECURE_PRIV_RWCD |
+ FWPERM_SECURE_USER_RWCD |
+ FWPERM_NON_SECURE_PRIV_RWCD |
+ FWPERM_NON_SECURE_USER_RWCD)>;
- /* More defines can be found in k3-security.h */
+ /* More defines can be found in k3-security.h */
- start_address = /* The Start Address of the firewall */
- <0x0 0x0>;
- end_address = /* The End Address of the firewall */
- <0xff 0xffffffff>;
- };
+ start_address = /* The Start Address of the firewall */
+ <0x0 0x0>;
+ end_address = /* The End Address of the firewall */
+ <0xff 0xffffffff>;
+ };
openssl signs the provided data, using the TI templated config file and
diff --git a/tools/binman/fdt_test.py b/tools/binman/fdt_test.py
index 7ef8729..564c177 100644
--- a/tools/binman/fdt_test.py
+++ b/tools/binman/fdt_test.py
@@ -44,43 +44,43 @@
fname = self.GetCompiled('045_prop_test.dts')
dt = FdtScan(fname)
node = dt.GetNode('/binman/intel-me')
- self.assertEquals('intel-me', node.name)
+ self.assertEqual('intel-me', node.name)
val = fdt_util.GetString(node, 'filename')
- self.assertEquals(str, type(val))
- self.assertEquals('me.bin', val)
+ self.assertEqual(str, type(val))
+ self.assertEqual('me.bin', val)
prop = node.props['intval']
- self.assertEquals(fdt.Type.INT, prop.type)
- self.assertEquals(3, fdt_util.GetInt(node, 'intval'))
+ self.assertEqual(fdt.Type.INT, prop.type)
+ self.assertEqual(3, fdt_util.GetInt(node, 'intval'))
prop = node.props['intarray']
- self.assertEquals(fdt.Type.INT, prop.type)
- self.assertEquals(list, type(prop.value))
- self.assertEquals(2, len(prop.value))
- self.assertEquals([5, 6],
+ self.assertEqual(fdt.Type.INT, prop.type)
+ self.assertEqual(list, type(prop.value))
+ self.assertEqual(2, len(prop.value))
+ self.assertEqual([5, 6],
[fdt_util.fdt32_to_cpu(val) for val in prop.value])
prop = node.props['byteval']
- self.assertEquals(fdt.Type.BYTE, prop.type)
- self.assertEquals(chr(8), prop.value)
+ self.assertEqual(fdt.Type.BYTE, prop.type)
+ self.assertEqual(chr(8), prop.value)
prop = node.props['bytearray']
- self.assertEquals(fdt.Type.BYTE, prop.type)
- self.assertEquals(list, type(prop.value))
- self.assertEquals(str, type(prop.value[0]))
- self.assertEquals(3, len(prop.value))
- self.assertEquals([chr(1), '#', '4'], prop.value)
+ self.assertEqual(fdt.Type.BYTE, prop.type)
+ self.assertEqual(list, type(prop.value))
+ self.assertEqual(str, type(prop.value[0]))
+ self.assertEqual(3, len(prop.value))
+ self.assertEqual([chr(1), '#', '4'], prop.value)
prop = node.props['longbytearray']
- self.assertEquals(fdt.Type.INT, prop.type)
- self.assertEquals(0x090a0b0c, fdt_util.GetInt(node, 'longbytearray'))
+ self.assertEqual(fdt.Type.INT, prop.type)
+ self.assertEqual(0x090a0b0c, fdt_util.GetInt(node, 'longbytearray'))
prop = node.props['stringval']
- self.assertEquals(fdt.Type.STRING, prop.type)
- self.assertEquals('message2', fdt_util.GetString(node, 'stringval'))
+ self.assertEqual(fdt.Type.STRING, prop.type)
+ self.assertEqual('message2', fdt_util.GetString(node, 'stringval'))
prop = node.props['stringarray']
- self.assertEquals(fdt.Type.STRING, prop.type)
- self.assertEquals(list, type(prop.value))
- self.assertEquals(3, len(prop.value))
- self.assertEquals(['another', 'multi-word', 'message'], prop.value)
+ self.assertEqual(fdt.Type.STRING, prop.type)
+ self.assertEqual(list, type(prop.value))
+ self.assertEqual(3, len(prop.value))
+ self.assertEqual(['another', 'multi-word', 'message'], prop.value)
diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py
index 8a44bc0..e4da040 100644
--- a/tools/binman/ftest.py
+++ b/tools/binman/ftest.py
@@ -2095,7 +2095,7 @@
dtb.Scan()
props = self._GetPropTree(dtb, ['size', 'uncomp-size'])
orig = self._decompress(data)
- self.assertEquals(COMPRESS_DATA, orig)
+ self.assertEqual(COMPRESS_DATA, orig)
# Do a sanity check on various fields
image = control.images['image']
@@ -2809,9 +2809,9 @@
orig_entry = orig_image.GetEntries()['fdtmap']
entry = image.GetEntries()['fdtmap']
- self.assertEquals(orig_entry.offset, entry.offset)
- self.assertEquals(orig_entry.size, entry.size)
- self.assertEquals(orig_entry.image_pos, entry.image_pos)
+ self.assertEqual(orig_entry.offset, entry.offset)
+ self.assertEqual(orig_entry.size, entry.size)
+ self.assertEqual(orig_entry.image_pos, entry.image_pos)
def testReadImageNoHeader(self):
"""Test accessing an image's FDT map without an image header"""
@@ -3895,7 +3895,7 @@
mat = re_line.match(line)
vals[mat.group(1)].append(mat.group(2))
- self.assertEquals('FIT description: test-desc', lines[0])
+ self.assertEqual('FIT description: test-desc', lines[0])
self.assertIn('Created:', lines[1])
self.assertIn('Image 0 (kernel)', vals)
self.assertIn('Hash value', vals)
@@ -4012,7 +4012,7 @@
fit_pos,
fdt_util.fdt32_to_cpu(fnode.props['data-position'].value))
- self.assertEquals(expected_size, len(data))
+ self.assertEqual(expected_size, len(data))
actual_pos = len(U_BOOT_DATA) + fit_pos
self.assertEqual(U_BOOT_DATA + b'aa',
data[actual_pos:actual_pos + external_data_size])
@@ -4431,7 +4431,7 @@
props = self._GetPropTree(dtb, ['offset', 'image-pos', 'size',
'uncomp-size'])
orig = self._decompress(data)
- self.assertEquals(COMPRESS_DATA + U_BOOT_DATA, orig)
+ self.assertEqual(COMPRESS_DATA + U_BOOT_DATA, orig)
# Do a sanity check on various fields
image = control.images['image']
@@ -4475,7 +4475,7 @@
'uncomp-size'])
orig = self._decompress(data)
- self.assertEquals(COMPRESS_DATA + COMPRESS_DATA + U_BOOT_DATA, orig)
+ self.assertEqual(COMPRESS_DATA + COMPRESS_DATA + U_BOOT_DATA, orig)
# Do a sanity check on various fields
image = control.images['image']
@@ -4519,7 +4519,7 @@
props = self._GetPropTree(dtb, ['offset', 'image-pos', 'size',
'uncomp-size'])
orig = self._decompress(data)
- self.assertEquals(COMPRESS_DATA + U_BOOT_DATA, orig)
+ self.assertEqual(COMPRESS_DATA + U_BOOT_DATA, orig)
expected = {
'section/blob:offset': 0,
'section/blob:size': len(COMPRESS_DATA),
@@ -4545,7 +4545,7 @@
props = self._GetPropTree(dtb, ['offset', 'image-pos', 'size',
'uncomp-size'])
orig = self._decompress(data)
- self.assertEquals(COMPRESS_DATA + U_BOOT_DATA, orig)
+ self.assertEqual(COMPRESS_DATA + U_BOOT_DATA, orig)
expected = {
'section/blob:offset': 0,
'section/blob:size': len(COMPRESS_DATA),
@@ -4580,7 +4580,7 @@
'uncomp-size'])
base = data[len(U_BOOT_DATA):]
- self.assertEquals(U_BOOT_DATA, base[:len(U_BOOT_DATA)])
+ self.assertEqual(U_BOOT_DATA, base[:len(U_BOOT_DATA)])
rest = base[len(U_BOOT_DATA):]
# Check compressed data
@@ -4588,22 +4588,22 @@
expect1 = bintool.compress(COMPRESS_DATA + U_BOOT_DATA)
data1 = rest[:len(expect1)]
section1 = self._decompress(data1)
- self.assertEquals(expect1, data1)
- self.assertEquals(COMPRESS_DATA + U_BOOT_DATA, section1)
+ self.assertEqual(expect1, data1)
+ self.assertEqual(COMPRESS_DATA + U_BOOT_DATA, section1)
rest1 = rest[len(expect1):]
expect2 = bintool.compress(COMPRESS_DATA + COMPRESS_DATA)
data2 = rest1[:len(expect2)]
section2 = self._decompress(data2)
- self.assertEquals(expect2, data2)
- self.assertEquals(COMPRESS_DATA + COMPRESS_DATA, section2)
+ self.assertEqual(expect2, data2)
+ self.assertEqual(COMPRESS_DATA + COMPRESS_DATA, section2)
rest2 = rest1[len(expect2):]
expect_size = (len(U_BOOT_DATA) + len(U_BOOT_DATA) + len(expect1) +
len(expect2) + len(U_BOOT_DATA))
- #self.assertEquals(expect_size, len(data))
+ #self.assertEqual(expect_size, len(data))
- #self.assertEquals(U_BOOT_DATA, rest2)
+ #self.assertEqual(U_BOOT_DATA, rest2)
self.maxDiff = None
expected = {
@@ -4695,7 +4695,7 @@
u_boot = image.GetEntries()['section'].GetEntries()['u-boot']
- self.assertEquals(U_BOOT_DATA, u_boot.ReadData())
+ self.assertEqual(U_BOOT_DATA, u_boot.ReadData())
def testTplNoDtb(self):
"""Test that an image with tpl/u-boot-tpl-nodtb.bin can be created"""
@@ -5526,7 +5526,7 @@
segments, entry = elf.read_loadable_segments(elf_data)
# We assume there are two segments
- self.assertEquals(2, len(segments))
+ self.assertEqual(2, len(segments))
atf1 = dtb.GetNode('/images/atf-1')
_, start, data = segments[0]
@@ -6107,7 +6107,7 @@
data = bintool.compress(COMPRESS_DATA)
self.assertNotEqual(COMPRESS_DATA, data)
orig = bintool.decompress(data)
- self.assertEquals(COMPRESS_DATA, orig)
+ self.assertEqual(COMPRESS_DATA, orig)
def testCompUtilVersions(self):
"""Test tool version of compression algorithms"""
@@ -6125,7 +6125,7 @@
self.assertNotEqual(COMPRESS_DATA, data)
data += tools.get_bytes(0, 64)
orig = bintool.decompress(data)
- self.assertEquals(COMPRESS_DATA, orig)
+ self.assertEqual(COMPRESS_DATA, orig)
def testCompressDtbZstd(self):
"""Test that zstd compress of device-tree files failed"""
@@ -7460,5 +7460,33 @@
with self.assertRaises(ValueError) as e:
self._DoReadFile('323_capsule_accept_revert_missing.dts')
+ def test_assume_size(self):
+ """Test handling of the assume-size property for external blob"""
+ with self.assertRaises(ValueError) as e:
+ self._DoTestFile('326_assume_size.dts', allow_missing=True,
+ allow_fake_blobs=True)
+ self.assertIn("contents size 0xa (10) exceeds section size 0x9 (9)",
+ str(e.exception))
+
+ def test_assume_size_ok(self):
+ """Test handling of the assume-size where it fits OK"""
+ with test_util.capture_sys_output() as (stdout, stderr):
+ self._DoTestFile('327_assume_size_ok.dts', allow_missing=True,
+ allow_fake_blobs=True)
+ err = stderr.getvalue()
+ self.assertRegex(
+ err,
+ "Image '.*' has faked external blobs and is non-functional: .*")
+
+ def test_assume_size_no_fake(self):
+ """Test handling of the assume-size where it fits OK"""
+ with test_util.capture_sys_output() as (stdout, stderr):
+ self._DoTestFile('327_assume_size_ok.dts', allow_missing=True)
+ err = stderr.getvalue()
+ self.assertRegex(
+ err,
+ "Image '.*' is missing external blobs and is non-functional: .*")
+
+
if __name__ == "__main__":
unittest.main()
diff --git a/tools/binman/test/326_assume_size.dts b/tools/binman/test/326_assume_size.dts
new file mode 100644
index 0000000..4c5f8b4
--- /dev/null
+++ b/tools/binman/test/326_assume_size.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ size = <9>;
+ blob-ext {
+ filename = "assume_blob";
+ assume-size = <10>;
+ };
+ };
+};
diff --git a/tools/binman/test/327_assume_size_ok.dts b/tools/binman/test/327_assume_size_ok.dts
new file mode 100644
index 0000000..00ed726
--- /dev/null
+++ b/tools/binman/test/327_assume_size_ok.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ size = <10>;
+ blob-ext {
+ filename = "assume_blob";
+ assume-size = <10>;
+ };
+ };
+};
diff --git a/tools/buildman/bsettings.py b/tools/buildman/bsettings.py
index e225ac2..aea724f 100644
--- a/tools/buildman/bsettings.py
+++ b/tools/buildman/bsettings.py
@@ -29,7 +29,7 @@
settings.read(config_fname)
def add_file(data):
- settings.readfp(io.StringIO(data))
+ settings.read_file(io.StringIO(data))
def get_items(section):
"""Get the items from a section of the config.
diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py
index f35175b..c4384f5 100644
--- a/tools/buildman/builder.py
+++ b/tools/buildman/builder.py
@@ -256,14 +256,14 @@
def __init__(self, toolchains, base_dir, git_dir, num_threads, num_jobs,
gnu_make='make', checkout=True, show_unknown=True, step=1,
no_subdirs=False, full_path=False, verbose_build=False,
- mrproper=False, per_board_out_dir=False,
- config_only=False, squash_config_y=False,
- warnings_as_errors=False, work_in_output=False,
- test_thread_exceptions=False, adjust_cfg=None,
- allow_missing=False, no_lto=False, reproducible_builds=False,
- force_build=False, force_build_failures=False,
- force_reconfig=False, in_tree=False,
- force_config_on_failure=False, make_func=None):
+ mrproper=False, fallback_mrproper=False,
+ per_board_out_dir=False, config_only=False,
+ squash_config_y=False, warnings_as_errors=False,
+ work_in_output=False, test_thread_exceptions=False,
+ adjust_cfg=None, allow_missing=False, no_lto=False,
+ reproducible_builds=False, force_build=False,
+ force_build_failures=False, force_reconfig=False,
+ in_tree=False, force_config_on_failure=False, make_func=None):
"""Create a new Builder object
Args:
@@ -283,6 +283,7 @@
PATH
verbose_build: Run build with V=1 and don't use 'make -s'
mrproper: Always run 'make mrproper' when configuring
+ fallback_mrproper: Run 'make mrproper' and retry on build failure
per_board_out_dir: Build in a separate persistent directory per
board rather than a thread-specific directory
config_only: Only configure each build, don't build it
@@ -352,6 +353,7 @@
self.force_reconfig = force_reconfig
self.in_tree = in_tree
self.force_config_on_failure = force_config_on_failure
+ self.fallback_mrproper = fallback_mrproper
if not self.squash_config_y:
self.config_filenames += EXTRA_CONFIG_FILENAMES
diff --git a/tools/buildman/builderthread.py b/tools/buildman/builderthread.py
index a8599c0..bbe2f6f 100644
--- a/tools/buildman/builderthread.py
+++ b/tools/buildman/builderthread.py
@@ -240,7 +240,7 @@
return args, cwd, src_dir
def _reconfigure(self, commit, brd, cwd, args, env, config_args, config_out,
- cmd_list):
+ cmd_list, mrproper):
"""Reconfigure the build
Args:
@@ -251,11 +251,12 @@
env (dict): Environment strings
config_args (list of str): defconfig arg for this board
cmd_list (list of str): List to add the commands to, for logging
+ mrproper (bool): True to run mrproper first
Returns:
CommandResult object
"""
- if self.mrproper:
+ if mrproper:
result = self.make(commit, brd, 'mrproper', cwd, 'mrproper', *args,
env=env)
config_out.write(result.combined)
@@ -380,7 +381,7 @@
commit = 'current'
return commit
- def _config_and_build(self, commit_upto, brd, work_dir, do_config,
+ def _config_and_build(self, commit_upto, brd, work_dir, do_config, mrproper,
config_only, adjust_cfg, commit, out_dir, out_rel_dir,
result):
"""Do the build, configuring first if necessary
@@ -390,6 +391,7 @@
brd (Board): Board to create arguments for
work_dir (str): Directory to which the source will be checked out
do_config (bool): True to run a make <board>_defconfig on the source
+ mrproper (bool): True to run mrproper first
config_only (bool): Only configure the source, do not build it
adjust_cfg (list of str): See the cfgutil module and run_commit()
commit (Commit): Commit only being built
@@ -419,7 +421,8 @@
cmd_list = []
if do_config or adjust_cfg:
result = self._reconfigure(
- commit, brd, cwd, args, env, config_args, config_out, cmd_list)
+ commit, brd, cwd, args, env, config_args, config_out, cmd_list,
+ mrproper)
do_config = False # No need to configure next time
if adjust_cfg:
cfgutil.adjust_cfg_file(cfg_file, adjust_cfg)
@@ -445,9 +448,9 @@
result.cmd_list = cmd_list
return result, do_config
- def run_commit(self, commit_upto, brd, work_dir, do_config, config_only,
- force_build, force_build_failures, work_in_output,
- adjust_cfg):
+ def run_commit(self, commit_upto, brd, work_dir, do_config, mrproper,
+ config_only, force_build, force_build_failures,
+ work_in_output, adjust_cfg):
"""Build a particular commit.
If the build is already done, and we are not forcing a build, we skip
@@ -458,6 +461,7 @@
brd (Board): Board to build
work_dir (str): Directory to which the source will be checked out
do_config (bool): True to run a make <board>_defconfig on the source
+ mrproper (bool): True to run mrproper first
config_only (bool): Only configure the source, do not build it
force_build (bool): Force a build even if one was previously done
force_build_failures (bool): Force a bulid if the previous result
@@ -498,8 +502,9 @@
if self.toolchain:
commit = self._checkout(commit_upto, work_dir)
result, do_config = self._config_and_build(
- commit_upto, brd, work_dir, do_config, config_only,
- adjust_cfg, commit, out_dir, out_rel_dir, result)
+ commit_upto, brd, work_dir, do_config, mrproper,
+ config_only, adjust_cfg, commit, out_dir, out_rel_dir,
+ result)
result.already_done = False
result.toolchain = self.toolchain
@@ -688,19 +693,22 @@
force_build = False
for commit_upto in range(0, len(job.commits), job.step):
result, request_config = self.run_commit(commit_upto, brd,
- work_dir, do_config, self.builder.config_only,
+ work_dir, do_config, self.mrproper,
+ self.builder.config_only,
force_build or self.builder.force_build,
self.builder.force_build_failures,
job.work_in_output, job.adjust_cfg)
failed = result.return_code or result.stderr
did_config = do_config
- if failed and not do_config:
+ if failed and not do_config and not self.mrproper:
# If our incremental build failed, try building again
# with a reconfig.
if self.builder.force_config_on_failure:
result, request_config = self.run_commit(commit_upto,
- brd, work_dir, True, False, True, False,
- job.work_in_output, job.adjust_cfg)
+ brd, work_dir, True,
+ self.mrproper or self.builder.fallback_mrproper,
+ False, True, False, job.work_in_output,
+ job.adjust_cfg)
did_config = True
if not self.builder.force_reconfig:
do_config = request_config
@@ -744,7 +752,7 @@
else:
# Just build the currently checked-out build
result, request_config = self.run_commit(None, brd, work_dir, True,
- self.builder.config_only, True,
+ self.mrproper, self.builder.config_only, True,
self.builder.force_build_failures, job.work_in_output,
job.adjust_cfg)
result.commit_upto = 0
diff --git a/tools/buildman/buildman.rst b/tools/buildman/buildman.rst
index aae2477..b8ff3bf 100644
--- a/tools/buildman/buildman.rst
+++ b/tools/buildman/buildman.rst
@@ -995,7 +995,8 @@
first commit for each board. This reduces the amount of work 'make' does, and
hence speeds up the build. To force use of 'make mrproper', use -the -m flag.
This flag will slow down any buildman invocation, since it increases the amount
-of work done on any build.
+of work done on any build. An alternative is to use the --fallback-mrproper
+flag, which retries the build with 'make mrproper' only after a build failure.
One possible application of buildman is as part of a continual edit, build,
edit, build, ... cycle; repeatedly applying buildman to the same change or
@@ -1285,6 +1286,11 @@
should be reported. But you can use -T0 to disable threading and hopefully
figure out the root cause of the build failure.
+For situations where buildman is invoked from multiple running processes, it is
+sometimes useful to have buildman wait until the others have finished. Use the
+--process-limit option for this: --process-limit 1 will allow only one buildman
+to process jobs at a time.
+
Build summary
-------------
diff --git a/tools/buildman/cmdline.py b/tools/buildman/cmdline.py
index 03211bd..544a391 100644
--- a/tools/buildman/cmdline.py
+++ b/tools/buildman/cmdline.py
@@ -90,7 +90,9 @@
parser.add_argument('--list-tool-chains', action='store_true', default=False,
help='List available tool chains (use -v to see probing detail)')
parser.add_argument('-m', '--mrproper', action='store_true',
- default=False, help="Run 'make mrproper before reconfiguring")
+ default=False, help="Run 'make mrproper' before reconfiguring")
+ parser.add_argument('--fallback-mrproper', action='store_true',
+ default=False, help="Run 'make mrproper' and retry on build failure")
parser.add_argument(
'-M', '--allow-missing', action='store_true', default=False,
help='Tell binman to allow missing blobs and generate fake ones as needed')
@@ -127,6 +129,8 @@
default=False, help="Use an O= (output) directory per board rather than per thread")
parser.add_argument('--print-arch', action='store_true',
default=False, help="Print the architecture for a board (ARCH=)")
+ parser.add_argument('--process-limit', type=int,
+ default=0, help='Limit to number of buildmans running at once')
parser.add_argument('-r', '--reproducible-builds', action='store_true',
help='Set SOURCE_DATE_EPOCH=0 to suuport a reproducible build')
parser.add_argument('-R', '--regen-board-list', type=str,
diff --git a/tools/buildman/control.py b/tools/buildman/control.py
index 8f6850c..464835c 100644
--- a/tools/buildman/control.py
+++ b/tools/buildman/control.py
@@ -7,10 +7,13 @@
This holds the main control logic for buildman, when not running tests.
"""
+import getpass
import multiprocessing
import os
import shutil
import sys
+import tempfile
+import time
from buildman import boards
from buildman import bsettings
@@ -21,10 +24,23 @@
from patman import patchstream
from u_boot_pylib import command
from u_boot_pylib import terminal
-from u_boot_pylib.terminal import tprint
+from u_boot_pylib import tools
+from u_boot_pylib.terminal import print_clear, tprint
TEST_BUILDER = None
+# Space-separated list of buildman process IDs currently running jobs
+RUNNING_FNAME = f'buildmanq.{getpass.getuser()}'
+
+# Lock file for access to RUNNING_FILE
+LOCK_FNAME = f'{RUNNING_FNAME}.lock'
+
+# Wait time for access to lock (seconds)
+LOCK_WAIT_S = 10
+
+# Wait time to start running
+RUN_WAIT_S = 300
+
def get_plural(count):
"""Returns a plural 's' if count is not 1"""
return 's' if count != 1 else ''
@@ -577,6 +593,125 @@
adjust_cfg['LOCALVERSION_AUTO'] = '~'
return adjust_cfg
+
+def read_procs(tmpdir=tempfile.gettempdir()):
+ """Read the list of running buildman processes
+
+ If the list is corrupted, returns an empty list
+
+ Args:
+ tmpdir (str): Temporary directory to use (for testing only)
+ """
+ running_fname = os.path.join(tmpdir, RUNNING_FNAME)
+ procs = []
+ if os.path.exists(running_fname):
+ items = tools.read_file(running_fname, binary=False).split()
+ try:
+ procs = [int(x) for x in items]
+ except ValueError: # Handle invalid format
+ pass
+ return procs
+
+
+def check_pid(pid):
+ """Check for existence of a unix PID
+
+ https://stackoverflow.com/questions/568271/how-to-check-if-there-exists-a-process-with-a-given-pid-in-python
+
+ Args:
+ pid (int): PID to check
+
+ Returns:
+ True if it exists, else False
+ """
+ try:
+ os.kill(pid, 0)
+ except OSError:
+ return False
+ else:
+ return True
+
+
+def write_procs(procs, tmpdir=tempfile.gettempdir()):
+ """Write the list of running buildman processes
+
+ Args:
+ tmpdir (str): Temporary directory to use (for testing only)
+ """
+ running_fname = os.path.join(tmpdir, RUNNING_FNAME)
+ tools.write_file(running_fname, ' '.join([str(p) for p in procs]),
+ binary=False)
+
+ # Allow another user to access the file
+ os.chmod(running_fname, 0o666)
+
+def wait_for_process_limit(limit, tmpdir=tempfile.gettempdir(),
+ pid=os.getpid()):
+ """Wait until the number of buildman processes drops to the limit
+
+ This uses FileLock to protect a 'running' file, which contains a list of
+ PIDs of running buildman processes. The number of PIDs in the file indicates
+ the number of running processes.
+
+ When buildman starts up, it calls this function to wait until it is OK to
+ start the build.
+
+ On exit, no attempt is made to remove the PID from the file, since other
+ buildman processes will notice that the PID is no-longer valid, and ignore
+ it.
+
+ Two timeouts are provided:
+ LOCK_WAIT_S: length of time to wait for the lock; if this occurs, the
+ lock is busted / removed before trying again
+ RUN_WAIT_S: length of time to wait to be allowed to run; if this occurs,
+ the build starts, with the PID being added to the file.
+
+ Args:
+ limit (int): Maximum number of buildman processes, including this one;
+ must be > 0
+ tmpdir (str): Temporary directory to use (for testing only)
+ pid (int): Current process ID (for testing only)
+ """
+ from filelock import Timeout, FileLock
+
+ running_fname = os.path.join(tmpdir, RUNNING_FNAME)
+ lock_fname = os.path.join(tmpdir, LOCK_FNAME)
+ lock = FileLock(lock_fname)
+
+ # Allow another user to access the file
+ col = terminal.Color()
+ tprint('Waiting for other buildman processes...', newline=False,
+ colour=col.RED)
+
+ claimed = False
+ deadline = time.time() + RUN_WAIT_S
+ while True:
+ try:
+ with lock.acquire(timeout=LOCK_WAIT_S):
+ os.chmod(lock_fname, 0o666)
+ procs = read_procs(tmpdir)
+
+ # Drop PIDs which are not running
+ procs = list(filter(check_pid, procs))
+
+ # If we haven't hit the limit, add ourself
+ if len(procs) < limit:
+ tprint('done...', newline=False)
+ claimed = True
+ if time.time() >= deadline:
+ tprint('timeout...', newline=False)
+ claimed = True
+ if claimed:
+ write_procs(procs + [pid], tmpdir)
+ break
+
+ except Timeout:
+ tprint('failed to get lock: busting...', newline=False)
+ os.remove(lock_fname)
+
+ time.sleep(1)
+ tprint('starting build', newline=False)
+ print_clear()
def do_buildman(args, toolchains=None, make_func=None, brds=None,
clean_dir=False, test_thread_exceptions=False):
@@ -656,6 +791,7 @@
no_subdirs=args.no_subdirs, full_path=args.full_path,
verbose_build=args.verbose_build,
mrproper=args.mrproper,
+ fallback_mrproper=args.fallback_mrproper,
per_board_out_dir=args.per_board_out_dir,
config_only=args.config_only,
squash_config_y=not args.preserve_config_y,
@@ -676,5 +812,8 @@
TEST_BUILDER = builder
+ if args.process_limit:
+ wait_for_process_limit(args.process_limit)
+
return run_builder(builder, series.commits if series else None,
brds.get_selected_dict(), args)
diff --git a/tools/buildman/func_test.py b/tools/buildman/func_test.py
index 6b88ed8..0ac9fc7 100644
--- a/tools/buildman/func_test.py
+++ b/tools/buildman/func_test.py
@@ -807,27 +807,27 @@
params, warnings = self._boards.scan_defconfigs(src, src)
# We should get two boards
- self.assertEquals(2, len(params))
+ self.assertEqual(2, len(params))
self.assertFalse(warnings)
first = 0 if params[0]['target'] == 'board0' else 1
board0 = params[first]
board2 = params[1 - first]
- self.assertEquals('arm', board0['arch'])
- self.assertEquals('armv7', board0['cpu'])
- self.assertEquals('-', board0['soc'])
- self.assertEquals('Tester', board0['vendor'])
- self.assertEquals('ARM Board 0', board0['board'])
- self.assertEquals('config0', board0['config'])
- self.assertEquals('board0', board0['target'])
+ self.assertEqual('arm', board0['arch'])
+ self.assertEqual('armv7', board0['cpu'])
+ self.assertEqual('-', board0['soc'])
+ self.assertEqual('Tester', board0['vendor'])
+ self.assertEqual('ARM Board 0', board0['board'])
+ self.assertEqual('config0', board0['config'])
+ self.assertEqual('board0', board0['target'])
- self.assertEquals('powerpc', board2['arch'])
- self.assertEquals('ppc', board2['cpu'])
- self.assertEquals('mpc85xx', board2['soc'])
- self.assertEquals('Tester', board2['vendor'])
- self.assertEquals('PowerPC board 1', board2['board'])
- self.assertEquals('config2', board2['config'])
- self.assertEquals('board2', board2['target'])
+ self.assertEqual('powerpc', board2['arch'])
+ self.assertEqual('ppc', board2['cpu'])
+ self.assertEqual('mpc85xx', board2['soc'])
+ self.assertEqual('Tester', board2['vendor'])
+ self.assertEqual('PowerPC board 1', board2['board'])
+ self.assertEqual('config2', board2['config'])
+ self.assertEqual('board2', board2['target'])
def test_output_is_new(self):
"""Test detecting new changes to Kconfig"""
@@ -898,7 +898,7 @@
params_list, warnings = self._boards.build_board_list(config_dir, src)
# There should be two boards no warnings
- self.assertEquals(2, len(params_list))
+ self.assertEqual(2, len(params_list))
self.assertFalse(warnings)
# Set an invalid status line in the file
@@ -907,12 +907,12 @@
for line in orig_data.splitlines(keepends=True)]
tools.write_file(main, ''.join(lines), binary=False)
params_list, warnings = self._boards.build_board_list(config_dir, src)
- self.assertEquals(2, len(params_list))
+ self.assertEqual(2, len(params_list))
params = params_list[0]
if params['target'] == 'board2':
params = params_list[1]
- self.assertEquals('-', params['status'])
- self.assertEquals(["WARNING: Other: unknown status for 'board0'"],
+ self.assertEqual('-', params['status'])
+ self.assertEqual(["WARNING: Other: unknown status for 'board0'"],
warnings)
# Remove the status line (S:) from a file
@@ -920,39 +920,39 @@
if not line.startswith('S:')]
tools.write_file(main, ''.join(lines), binary=False)
params_list, warnings = self._boards.build_board_list(config_dir, src)
- self.assertEquals(2, len(params_list))
- self.assertEquals(["WARNING: -: unknown status for 'board0'"], warnings)
+ self.assertEqual(2, len(params_list))
+ self.assertEqual(["WARNING: -: unknown status for 'board0'"], warnings)
# Remove the configs/ line (F:) from a file - this is the last line
data = ''.join(orig_data.splitlines(keepends=True)[:-1])
tools.write_file(main, data, binary=False)
params_list, warnings = self._boards.build_board_list(config_dir, src)
- self.assertEquals(2, len(params_list))
- self.assertEquals(["WARNING: no maintainers for 'board0'"], warnings)
+ self.assertEqual(2, len(params_list))
+ self.assertEqual(["WARNING: no maintainers for 'board0'"], warnings)
# Mark a board as orphaned - this should give a warning
lines = ['S: Orphaned' if line.startswith('S') else line
for line in orig_data.splitlines(keepends=True)]
tools.write_file(main, ''.join(lines), binary=False)
params_list, warnings = self._boards.build_board_list(config_dir, src)
- self.assertEquals(2, len(params_list))
- self.assertEquals(["WARNING: no maintainers for 'board0'"], warnings)
+ self.assertEqual(2, len(params_list))
+ self.assertEqual(["WARNING: no maintainers for 'board0'"], warnings)
# Change the maintainer to '-' - this should give a warning
lines = ['M: -' if line.startswith('M') else line
for line in orig_data.splitlines(keepends=True)]
tools.write_file(main, ''.join(lines), binary=False)
params_list, warnings = self._boards.build_board_list(config_dir, src)
- self.assertEquals(2, len(params_list))
- self.assertEquals(["WARNING: -: unknown status for 'board0'"], warnings)
+ self.assertEqual(2, len(params_list))
+ self.assertEqual(["WARNING: -: unknown status for 'board0'"], warnings)
# Remove the maintainer line (M:) from a file
lines = [line for line in orig_data.splitlines(keepends=True)
if not line.startswith('M:')]
tools.write_file(main, ''.join(lines), binary=False)
params_list, warnings = self._boards.build_board_list(config_dir, src)
- self.assertEquals(2, len(params_list))
- self.assertEquals(["WARNING: no maintainers for 'board0'"], warnings)
+ self.assertEqual(2, len(params_list))
+ self.assertEqual(["WARNING: no maintainers for 'board0'"], warnings)
# Move the contents of the second file into this one, removing the
# second file, to check multiple records in a single file.
@@ -960,14 +960,14 @@
tools.write_file(main, both_data, binary=False)
os.remove(other)
params_list, warnings = self._boards.build_board_list(config_dir, src)
- self.assertEquals(2, len(params_list))
+ self.assertEqual(2, len(params_list))
self.assertFalse(warnings)
# Add another record, this should be ignored with a warning
extra = '\n\nAnother\nM: Fred\nF: configs/board9_defconfig\nS: other\n'
tools.write_file(main, both_data + extra, binary=False)
params_list, warnings = self._boards.build_board_list(config_dir, src)
- self.assertEquals(2, len(params_list))
+ self.assertEqual(2, len(params_list))
self.assertFalse(warnings)
# Add another TARGET to the Kconfig
@@ -983,8 +983,8 @@
tools.write_file(kc_file, orig_kc_data + extra)
params_list, warnings = self._boards.build_board_list(config_dir, src,
warn_targets=True)
- self.assertEquals(2, len(params_list))
- self.assertEquals(
+ self.assertEqual(2, len(params_list))
+ self.assertEqual(
['WARNING: board2_defconfig: Duplicate TARGET_xxx: board2 and other'],
warnings)
@@ -994,8 +994,8 @@
tools.write_file(kc_file, b''.join(lines))
params_list, warnings = self._boards.build_board_list(config_dir, src,
warn_targets=True)
- self.assertEquals(2, len(params_list))
- self.assertEquals(
+ self.assertEqual(2, len(params_list))
+ self.assertEqual(
['WARNING: board2_defconfig: No TARGET_BOARD2 enabled'],
warnings)
tools.write_file(kc_file, orig_kc_data)
@@ -1004,7 +1004,7 @@
data = ''.join(both_data.splitlines(keepends=True)[:-1])
tools.write_file(main, data + 'N: oa.*2\n', binary=False)
params_list, warnings = self._boards.build_board_list(config_dir, src)
- self.assertEquals(2, len(params_list))
+ self.assertEqual(2, len(params_list))
self.assertFalse(warnings)
def testRegenBoards(self):
diff --git a/tools/buildman/pyproject.toml b/tools/buildman/pyproject.toml
index fe0f642..68bfa45 100644
--- a/tools/buildman/pyproject.toml
+++ b/tools/buildman/pyproject.toml
@@ -8,7 +8,11 @@
authors = [
{ name="Simon Glass", email="sjg@chromium.org" },
]
-dependencies = ["u_boot_pylib >= 0.0.6", "patch-manager >= 0.0.6"]
+dependencies = [
+ "filelock >= 3.0.12",
+ "u_boot_pylib >= 0.0.6",
+ "patch-manager >= 0.0.6"
+]
description = "Buildman build tool for U-Boot"
readme = "README.rst"
requires-python = ">=3.7"
diff --git a/tools/buildman/requirements.txt b/tools/buildman/requirements.txt
index 4a31e69..052d0ed 100644
--- a/tools/buildman/requirements.txt
+++ b/tools/buildman/requirements.txt
@@ -1,3 +1,5 @@
+coverage==6.2
jsonschema==4.17.3
+pycryptodome==3.20
pyyaml==6.0
yamllint==1.26.3
diff --git a/tools/buildman/test.py b/tools/buildman/test.py
index f92add7..bfad309 100644
--- a/tools/buildman/test.py
+++ b/tools/buildman/test.py
@@ -2,12 +2,14 @@
# Copyright (c) 2012 The Chromium OS Authors.
#
+from filelock import FileLock
import os
import shutil
import sys
import tempfile
import time
import unittest
+from unittest.mock import patch
from buildman import board
from buildman import boards
@@ -156,6 +158,11 @@
if not os.path.isdir(self.base_dir):
os.mkdir(self.base_dir)
+ self.cur_time = 0
+ self.valid_pids = []
+ self.finish_time = None
+ self.finish_pid = None
+
def tearDown(self):
shutil.rmtree(self.base_dir)
@@ -584,7 +591,7 @@
if use_network:
with test_util.capture_sys_output() as (stdout, stderr):
url = self.toolchains.LocateArchUrl('arm')
- self.assertRegexpMatches(url, 'https://www.kernel.org/pub/tools/'
+ self.assertRegex(url, 'https://www.kernel.org/pub/tools/'
'crosstool/files/bin/x86_64/.*/'
'x86_64-gcc-.*-nolibc[-_]arm-.*linux-gnueabi.tar.xz')
@@ -747,6 +754,120 @@
self.assertEqual([
['MARY="mary"', 'Missing expected line: CONFIG_MARY="mary"']], result)
+ def get_procs(self):
+ running_fname = os.path.join(self.base_dir, control.RUNNING_FNAME)
+ items = tools.read_file(running_fname, binary=False).split()
+ return [int(x) for x in items]
+
+ def get_time(self):
+ return self.cur_time
+
+ def inc_time(self, amount):
+ self.cur_time += amount
+
+ # Handle a process exiting
+ if self.finish_time == self.cur_time:
+ self.valid_pids = [pid for pid in self.valid_pids
+ if pid != self.finish_pid]
+
+ def kill(self, pid, signal):
+ if pid not in self.valid_pids:
+ raise OSError('Invalid PID')
+
+ def test_process_limit(self):
+ """Test wait_for_process_limit() function"""
+ tmpdir = self.base_dir
+
+ with (patch('time.time', side_effect=self.get_time),
+ patch('time.sleep', side_effect=self.inc_time),
+ patch('os.kill', side_effect=self.kill)):
+ # Grab the process. Since there is no other profcess, this should
+ # immediately succeed
+ control.wait_for_process_limit(1, tmpdir=tmpdir, pid=1)
+ lines = terminal.get_print_test_lines()
+ self.assertEqual(0, self.cur_time)
+ self.assertEqual('Waiting for other buildman processes...',
+ lines[0].text)
+ self.assertEqual(self._col.RED, lines[0].colour)
+ self.assertEqual(False, lines[0].newline)
+ self.assertEqual(True, lines[0].bright)
+
+ self.assertEqual('done...', lines[1].text)
+ self.assertEqual(None, lines[1].colour)
+ self.assertEqual(False, lines[1].newline)
+ self.assertEqual(True, lines[1].bright)
+
+ self.assertEqual('starting build', lines[2].text)
+ self.assertEqual([1], control.read_procs(tmpdir))
+ self.assertEqual(None, lines[2].colour)
+ self.assertEqual(False, lines[2].newline)
+ self.assertEqual(True, lines[2].bright)
+
+ # Try again, with a different PID...this should eventually timeout
+ # and start the build anyway
+ self.cur_time = 0
+ self.valid_pids = [1]
+ control.wait_for_process_limit(1, tmpdir=tmpdir, pid=2)
+ lines = terminal.get_print_test_lines()
+ self.assertEqual('Waiting for other buildman processes...',
+ lines[0].text)
+ self.assertEqual('timeout...', lines[1].text)
+ self.assertEqual(None, lines[1].colour)
+ self.assertEqual(False, lines[1].newline)
+ self.assertEqual(True, lines[1].bright)
+ self.assertEqual('starting build', lines[2].text)
+ self.assertEqual([1, 2], control.read_procs(tmpdir))
+ self.assertEqual(control.RUN_WAIT_S, self.cur_time)
+
+ # Check lock-busting
+ self.cur_time = 0
+ self.valid_pids = [1, 2]
+ lock_fname = os.path.join(tmpdir, control.LOCK_FNAME)
+ lock = FileLock(lock_fname)
+ lock.acquire(timeout=1)
+ control.wait_for_process_limit(1, tmpdir=tmpdir, pid=3)
+ lines = terminal.get_print_test_lines()
+ self.assertEqual('Waiting for other buildman processes...',
+ lines[0].text)
+ self.assertEqual('failed to get lock: busting...', lines[1].text)
+ self.assertEqual(None, lines[1].colour)
+ self.assertEqual(False, lines[1].newline)
+ self.assertEqual(True, lines[1].bright)
+ self.assertEqual('timeout...', lines[2].text)
+ self.assertEqual('starting build', lines[3].text)
+ self.assertEqual([1, 2, 3], control.read_procs(tmpdir))
+ self.assertEqual(control.RUN_WAIT_S, self.cur_time)
+ lock.release()
+
+ # Check handling of dead processes. Here we have PID 2 as a running
+ # process, even though the PID file contains 1, 2 and 3. So we can
+ # add one more PID, to make 2 and 4
+ self.cur_time = 0
+ self.valid_pids = [2]
+ control.wait_for_process_limit(2, tmpdir=tmpdir, pid=4)
+ lines = terminal.get_print_test_lines()
+ self.assertEqual('Waiting for other buildman processes...',
+ lines[0].text)
+ self.assertEqual('done...', lines[1].text)
+ self.assertEqual('starting build', lines[2].text)
+ self.assertEqual([2, 4], control.read_procs(tmpdir))
+ self.assertEqual(0, self.cur_time)
+
+ # Try again, with PID 2 quitting at time 50. This allows the new
+ # build to start
+ self.cur_time = 0
+ self.valid_pids = [2, 4]
+ self.finish_pid = 2
+ self.finish_time = 50
+ control.wait_for_process_limit(2, tmpdir=tmpdir, pid=5)
+ lines = terminal.get_print_test_lines()
+ self.assertEqual('Waiting for other buildman processes...',
+ lines[0].text)
+ self.assertEqual('done...', lines[1].text)
+ self.assertEqual('starting build', lines[2].text)
+ self.assertEqual([4, 5], control.read_procs(tmpdir))
+ self.assertEqual(self.finish_time, self.cur_time)
+
if __name__ == "__main__":
unittest.main()
diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py
index 79c7c11..324ad0e 100644
--- a/tools/buildman/toolchain.py
+++ b/tools/buildman/toolchain.py
@@ -175,9 +175,9 @@
def MakeEnvironment(self, full_path):
"""Returns an environment for using the toolchain.
- Thie takes the current environment and adds CROSS_COMPILE so that
+ This takes the current environment and adds CROSS_COMPILE so that
the tool chain will operate correctly. This also disables localized
- output and possibly unicode encoded output of all build tools by
+ output and possibly Unicode encoded output of all build tools by
adding LC_ALL=C.
Note that os.environb is used to obtain the environment, since in some
diff --git a/tools/image-host.c b/tools/image-host.c
index 7bfc0cb..49ce743 100644
--- a/tools/image-host.c
+++ b/tools/image-host.c
@@ -730,7 +730,7 @@
int *lenp, int *allow_missingp)
{
static const char default_list[] = FIT_KERNEL_PROP "\0"
- FIT_FDT_PROP;
+ FIT_FDT_PROP "\0" FIT_SCRIPT_PROP;
const char *prop;
/* If there is an "sign-image" property, use that */
diff --git a/tools/mkfwumdata.c b/tools/mkfwumdata.c
index 9732a8d..fbc2067 100644
--- a/tools/mkfwumdata.c
+++ b/tools/mkfwumdata.c
@@ -10,28 +10,35 @@
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
-#include <u-boot/crc.h>
#include <unistd.h>
+#include <generated/autoconf.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <u-boot/crc.h>
#include <uuid/uuid.h>
-/* This will dynamically allocate the fwu_mdata */
-#define CONFIG_FWU_NUM_BANKS 0
-#define CONFIG_FWU_NUM_IMAGES_PER_BANK 0
-
-/* Since we can not include fwu.h, redefine version here. */
-#define FWU_MDATA_VERSION 1
-
typedef uint8_t u8;
typedef int16_t s16;
typedef uint16_t u16;
typedef uint32_t u32;
typedef uint64_t u64;
-#include <fwu_mdata.h>
+#undef CONFIG_FWU_NUM_BANKS
+#undef CONFIG_FWU_NUM_IMAGES_PER_BANK
-/* TODO: Endianness conversion may be required for some arch. */
+/* This will dynamically allocate the fwu_mdata */
+#define CONFIG_FWU_NUM_BANKS 0
+#define CONFIG_FWU_NUM_IMAGES_PER_BANK 0
+
+/* version 2 supports maximum of 4 banks */
+#define MAX_BANKS_V2 4
+
+#define BANK_INVALID (u8)0xFF
+#define BANK_ACCEPTED (u8)0xFC
-static const char *opts_short = "b:i:a:p:gh";
+#include <fwu_mdata.h>
+
+static const char *opts_short = "b:i:a:p:v:V:gh";
static struct option options[] = {
{"banks", required_argument, NULL, 'b'},
@@ -39,6 +46,8 @@
{"guid", required_argument, NULL, 'g'},
{"active-bank", required_argument, NULL, 'a'},
{"previous-bank", required_argument, NULL, 'p'},
+ {"version", required_argument, NULL, 'v'},
+ {"vendor-file", required_argument, NULL, 'V'},
{"help", no_argument, NULL, 'h'},
{NULL, 0, NULL, 0},
};
@@ -49,9 +58,11 @@
fprintf(stderr, "Options:\n"
"\t-i, --images <num> Number of images (mandatory)\n"
"\t-b, --banks <num> Number of banks (mandatory)\n"
+ "\t-v, --version Metadata version (mandatory)\n"
"\t-a, --active-bank <num> Active bank (default=0)\n"
"\t-p, --previous-bank <num> Previous active bank (default=active_bank - 1)\n"
"\t-g, --guid Use GUID instead of UUID\n"
+ "\t-V, --vendor-file Vendor data file to append to the metadata\n"
"\t-h, --help print a help message\n"
);
fprintf(stderr, " UUIDs list syntax:\n"
@@ -70,13 +81,28 @@
size_t images;
size_t banks;
size_t size;
+ u8 version;
+ size_t vsize;
+ void *vbuf;
struct fwu_mdata *mdata;
};
static int previous_bank, active_bank;
static bool __use_guid;
+static bool supported_mdata_version(unsigned long version)
+{
+ switch (version) {
+ case 1:
+ case 2:
+ return true;
+ default:
+ return false;
+ }
+}
+
-static struct fwu_mdata_object *fwu_alloc_mdata(size_t images, size_t banks)
+static struct fwu_mdata_object *fwu_alloc_mdata(size_t images, size_t banks,
+ u8 version, size_t vendor_size)
{
struct fwu_mdata_object *mobj;
@@ -84,19 +110,40 @@
if (!mobj)
return NULL;
+ if (version == 1) {
+ mobj->size = sizeof(struct fwu_mdata) +
+ (sizeof(struct fwu_image_entry) +
+ sizeof(struct fwu_image_bank_info) * banks) * images;
+ } else {
+ mobj->size = sizeof(struct fwu_mdata) +
+ sizeof(struct fwu_fw_store_desc) +
+ (sizeof(struct fwu_image_entry) +
+ sizeof(struct fwu_image_bank_info) * banks) * images;
+
- mobj->size = sizeof(struct fwu_mdata) +
- (sizeof(struct fwu_image_entry) +
- sizeof(struct fwu_image_bank_info) * banks) * images;
+ mobj->size += vendor_size;
+ mobj->vsize = vendor_size;
+ }
+
mobj->images = images;
mobj->banks = banks;
+ mobj->version = version;
mobj->mdata = calloc(1, mobj->size);
- if (!mobj->mdata) {
- free(mobj);
- return NULL;
+ if (!mobj->mdata)
+ goto alloc_err;
+
+ if (vendor_size) {
+ mobj->vbuf = calloc(1, mobj->vsize);
+ if (!mobj->vbuf)
+ goto alloc_err;
}
return mobj;
+
+alloc_err:
+ free(mobj->mdata);
+ free(mobj);
+ return NULL;
}
static struct fwu_image_entry *
@@ -104,9 +151,18 @@
{
size_t offset;
- offset = sizeof(struct fwu_mdata) +
- (sizeof(struct fwu_image_entry) +
- sizeof(struct fwu_image_bank_info) * mobj->banks) * idx;
+ if (mobj->version == 1) {
+ offset = sizeof(struct fwu_mdata) +
+ (sizeof(struct fwu_image_entry) +
+ sizeof(struct fwu_image_bank_info) * mobj->banks) *
+ idx;
+ } else {
+ offset = sizeof(struct fwu_mdata) +
+ sizeof(struct fwu_fw_store_desc) +
+ (sizeof(struct fwu_image_entry) +
+ sizeof(struct fwu_image_bank_info) * mobj->banks) *
+ idx;
+ }
return (struct fwu_image_entry *)((char *)mobj->mdata + offset);
}
@@ -116,11 +172,20 @@
{
size_t offset;
- offset = sizeof(struct fwu_mdata) +
- (sizeof(struct fwu_image_entry) +
- sizeof(struct fwu_image_bank_info) * mobj->banks) * img_idx +
- sizeof(struct fwu_image_entry) +
- sizeof(struct fwu_image_bank_info) * bnk_idx;
+ if (mobj->version == 1) {
+ offset = sizeof(struct fwu_mdata) +
+ (sizeof(struct fwu_image_entry) +
+ sizeof(struct fwu_image_bank_info) * mobj->banks) *
+ img_idx + sizeof(struct fwu_image_entry) +
+ sizeof(struct fwu_image_bank_info) * bnk_idx;
+ } else {
+ offset = sizeof(struct fwu_mdata) +
+ sizeof(struct fwu_fw_store_desc) +
+ (sizeof(struct fwu_image_entry) +
+ sizeof(struct fwu_image_bank_info) * mobj->banks) *
+ img_idx + sizeof(struct fwu_image_entry) +
+ sizeof(struct fwu_image_bank_info) * bnk_idx;
+ }
return (struct fwu_image_bank_info *)((char *)mobj->mdata + offset);
}
@@ -188,7 +253,7 @@
return -EINVAL;
if (strcmp(uuid, "0") &&
- uuid_guid_parse(uuid, (unsigned char *)&image->location_uuid) < 0)
+ uuid_guid_parse(uuid, (unsigned char *)&image->location_guid) < 0)
return -EINVAL;
/* Image type UUID */
@@ -196,7 +261,7 @@
if (!uuid)
return -EINVAL;
- if (uuid_guid_parse(uuid, (unsigned char *)&image->image_type_uuid) < 0)
+ if (uuid_guid_parse(uuid, (unsigned char *)&image->image_type_guid) < 0)
return -EINVAL;
/* Fill bank image-UUID */
@@ -210,45 +275,118 @@
return -EINVAL;
if (strcmp(uuid, "0") &&
- uuid_guid_parse(uuid, (unsigned char *)&bank->image_uuid) < 0)
+ uuid_guid_parse(uuid, (unsigned char *)&bank->image_guid) < 0)
return -EINVAL;
}
return 0;
}
+
+#if defined(CONFIG_FWU_MDATA_V1)
+static void fwu_fill_version_specific_mdata(struct fwu_mdata_object *mobj)
+{
+}
+#else
+static void fwu_fill_version_specific_mdata(struct fwu_mdata_object *mobj)
+{
+ int i;
+ struct fwu_fw_store_desc *fw_desc;
+ struct fwu_mdata *mdata = mobj->mdata;
+
+ mdata->metadata_size = mobj->size;
+ mdata->desc_offset = sizeof(struct fwu_mdata);
+
+ for (i = 0; i < MAX_BANKS_V2; i++)
+ mdata->bank_state[i] = i < mobj->banks ?
+ BANK_ACCEPTED : BANK_INVALID;
+
+ fw_desc = (struct fwu_fw_store_desc *)((u8 *)mdata + sizeof(*mdata));
+ fw_desc->num_banks = mobj->banks;
+ fw_desc->num_images = mobj->images;
+ fw_desc->img_entry_size = sizeof(struct fwu_image_entry) +
+ (sizeof(struct fwu_image_bank_info) * mobj->banks);
+ fw_desc->bank_info_entry_size =
+ sizeof(struct fwu_image_bank_info);
+}
+#endif /* CONFIG_FWU_MDATA_V1 */
/* Caller must ensure that @uuids[] has @mobj->images entries. */
static int fwu_parse_fill_uuids(struct fwu_mdata_object *mobj, char *uuids[])
{
struct fwu_mdata *mdata = mobj->mdata;
+ char *vdata;
int i, ret;
- mdata->version = FWU_MDATA_VERSION;
+ mdata->version = mobj->version;
mdata->active_index = active_bank;
mdata->previous_active_index = previous_bank;
+ fwu_fill_version_specific_mdata(mobj);
+
for (i = 0; i < mobj->images; i++) {
ret = fwu_parse_fill_image_uuid(mobj, i, uuids[i]);
if (ret < 0)
return ret;
}
+ if (mobj->vsize) {
+ vdata = (char *)mobj->mdata + (mobj->size - mobj->vsize);
+ memcpy(vdata, mobj->vbuf, mobj->vsize);
+ }
+
mdata->crc32 = crc32(0, (const unsigned char *)&mdata->version,
mobj->size - sizeof(uint32_t));
return 0;
}
-static int
-fwu_make_mdata(size_t images, size_t banks, char *uuids[], char *output)
+static int fwu_read_vendor_data(struct fwu_mdata_object *mobj,
+ const char *vendor_file)
{
- struct fwu_mdata_object *mobj;
- FILE *file;
+ int ret = 0;
+ FILE *vfile = NULL;
+
+ vfile = fopen(vendor_file, "r");
+ if (!vfile) {
+ ret = -1;
+ goto out;
+ }
+
+ if (fread(mobj->vbuf, 1, mobj->vsize, vfile) != mobj->vsize)
+ ret = -1;
+
+out:
+ fclose(vfile);
+ return ret;
+}
+
+static int fwu_make_mdata(size_t images, size_t banks, u8 version,
+ const char *vendor_file, char *uuids[],
+ char *output)
+{
int ret;
+ FILE *file;
+ struct stat sbuf;
+ size_t vendor_size = 0;
+ struct fwu_mdata_object *mobj;
+
+ if (vendor_file) {
+ ret = stat(vendor_file, &sbuf);
+ if (ret)
+ return -errno;
- mobj = fwu_alloc_mdata(images, banks);
+ vendor_size = sbuf.st_size;
+ }
+
+ mobj = fwu_alloc_mdata(images, banks, version, vendor_size);
if (!mobj)
return -ENOMEM;
+ if (vendor_file) {
+ ret = fwu_read_vendor_data(mobj, vendor_file);
+ if (ret)
+ goto done_make;
+ }
+
ret = fwu_parse_fill_uuids(mobj, uuids);
if (ret < 0)
goto done_make;
@@ -259,7 +397,7 @@
goto done_make;
}
- ret = fwrite(mobj->mdata, mobj->size, 1, file);
+ ret = fwrite(mobj->mdata, 1, mobj->size, file);
if (ret != mobj->size)
ret = -errno;
else
@@ -269,6 +407,7 @@
done_make:
free(mobj->mdata);
+ free(mobj->vbuf);
free(mobj);
return ret;
@@ -276,13 +415,15 @@
int main(int argc, char *argv[])
{
- unsigned long banks = 0, images = 0;
+ unsigned long banks = 0, images = 0, version = 0;
int c, ret;
+ const char *vendor_file;
/* Explicitly initialize defaults */
active_bank = 0;
__use_guid = false;
previous_bank = INT_MAX;
+ vendor_file = NULL;
do {
c = getopt_long(argc, argv, opts_short, options, NULL);
@@ -305,6 +446,12 @@
case 'a':
active_bank = strtoul(optarg, NULL, 0);
break;
+ case 'v':
+ version = strtoul(optarg, NULL, 0);
+ break;
+ case 'V':
+ vendor_file = optarg;
+ break;
}
} while (c != -1);
@@ -313,6 +460,17 @@
return -EINVAL;
}
+ if (!version || !supported_mdata_version(version)) {
+ fprintf(stderr, "Error: Version value can only be either 1 or 2, not %ld.\n",
+ version);
+ return -EINVAL;
+ }
+
+ if (version == 1 && vendor_file) {
+ fprintf(stderr, "Error: Vendor Data can only be appended in version 2 of FWU Metadata.\n");
+ return -EINVAL;
+ }
+
/* This command takes UUIDs * images and output file. */
if (optind + images + 1 != argc) {
fprintf(stderr, "Error: UUID list or output file is not specified or too much.\n");
@@ -325,7 +483,8 @@
previous_bank = active_bank > 0 ? active_bank - 1 : banks - 1;
}
- ret = fwu_make_mdata(images, banks, argv + optind, argv[argc - 1]);
+ ret = fwu_make_mdata(images, banks, (u8)version, vendor_file,
+ argv + optind, argv[argc - 1]);
if (ret < 0)
fprintf(stderr, "Error: Failed to parse and write image: %s\n",
strerror(-ret));
diff --git a/tools/patman/func_test.py b/tools/patman/func_test.py
index e391849..af6c025 100644
--- a/tools/patman/func_test.py
+++ b/tools/patman/func_test.py
@@ -211,6 +211,7 @@
'u-boot': ['u-boot@lists.denx.de'],
'simon': [self.leb],
'fred': [self.fred],
+ 'joe': [self.joe],
}
text = self._get_text('test01.txt')
@@ -259,6 +260,7 @@
self.assertEqual('Postfix:\t some-branch', next(lines))
self.assertEqual('Cover: 4 lines', next(lines))
self.assertEqual(' Cc: %s' % self.fred, next(lines))
+ self.assertEqual(' Cc: %s' % self.joe, next(lines))
self.assertEqual(' Cc: %s' % self.leb,
next(lines))
self.assertEqual(' Cc: %s' % mel, next(lines))
@@ -272,7 +274,8 @@
self.assertEqual(('%s %s\0%s' % (args[0], rick, stefan)), cc_lines[0])
self.assertEqual(
- '%s %s\0%s\0%s\0%s' % (args[1], self.fred, self.leb, rick, stefan),
+ '%s %s\0%s\0%s\0%s\0%s' % (args[1], self.fred, self.joe, self.leb,
+ rick, stefan),
cc_lines[1])
expected = '''
@@ -290,6 +293,7 @@
change
- Some changes
- Some notes for the cover letter
+- fdt: Correct cast for sandbox in fdtdec_setup_mem_size_base()
Simon Glass (2):
pci: Correct cast for sandbox
@@ -339,6 +343,7 @@
- Multi
line
change
+- New
- Some changes
Changes in v2:
@@ -540,7 +545,8 @@
with open('.patman', 'w', buffering=1) as f:
f.write('[settings]\n'
'get_maintainer_script: dummy-script.sh\n'
- 'check_patch: False\n')
+ 'check_patch: False\n'
+ 'add_maintainers: True\n')
with open('dummy-script.sh', 'w', buffering=1) as f:
f.write('#!/usr/bin/env python\n'
'print("hello@there.com")\n')
diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py
index e2e2a83..a09ae9c 100644
--- a/tools/patman/patchstream.py
+++ b/tools/patman/patchstream.py
@@ -475,6 +475,13 @@
elif name == 'changes':
self.in_change = 'Commit'
self.change_version = self._parse_version(value, line)
+ elif name == 'cc':
+ self.commit.add_cc(value.split(','))
+ elif name == 'added-in':
+ version = self._parse_version(value, line)
+ self.commit.add_change(version, '- New')
+ self.series.AddChange(version, None, '- %s' %
+ self.commit.subject)
else:
self._add_warn('Line %d: Ignoring Commit-%s' %
(self.linenum, name))
diff --git a/tools/patman/patman.rst b/tools/patman/patman.rst
index f4588c0..63b95a6 100644
--- a/tools/patman/patman.rst
+++ b/tools/patman/patman.rst
@@ -350,7 +350,20 @@
- This line will only appear in the cover letter
<blank line>
-Patch-cc: Their Name <email>
+Commit-added-in: n
+ Add a change noting the version this commit was added in. This is
+ equivalent to::
+
+ Commit-changes: n
+ - New
+
+ Cover-changes: n
+ - <commit subject>
+
+ It is a convenient shorthand for suppressing the '(no changes in vN)'
+ message.
+
+Patch-cc / Commit-cc: Their Name <email>
This copies a single patch to another email address. Note that the
Cc: used by git send-email is ignored by patman, but will be
interpreted by git send-email if you use it.
diff --git a/tools/patman/settings.py b/tools/patman/settings.py
index 636983e..68c93e3 100644
--- a/tools/patman/settings.py
+++ b/tools/patman/settings.py
@@ -59,25 +59,25 @@
# Check to make sure that bogus project gets general alias.
>>> config = _ProjectConfigParser("zzz")
- >>> config.readfp(StringIO(sample_config))
+ >>> config.read_file(StringIO(sample_config))
>>> str(config.get("alias", "enemies"))
'Evil <evil@example.com>'
# Check to make sure that alias gets overridden by project.
>>> config = _ProjectConfigParser("sm")
- >>> config.readfp(StringIO(sample_config))
+ >>> config.read_file(StringIO(sample_config))
>>> str(config.get("alias", "enemies"))
'Green G. <ugly@example.com>'
# Check to make sure that settings get merged with project.
>>> config = _ProjectConfigParser("linux")
- >>> config.readfp(StringIO(sample_config))
+ >>> config.read_file(StringIO(sample_config))
>>> sorted((str(a), str(b)) for (a, b) in config.items("settings"))
[('am_hero', 'True'), ('check_patch_use_tree', 'True'), ('process_tags', 'False')]
# Check to make sure that settings works with unknown project.
>>> config = _ProjectConfigParser("unknown")
- >>> config.readfp(StringIO(sample_config))
+ >>> config.read_file(StringIO(sample_config))
>>> sorted((str(a), str(b)) for (a, b) in config.items("settings"))
[('am_hero', 'True')]
"""
diff --git a/tools/patman/test/0002-fdt-Correct-cast-for-sandbox-in-fdtdec_setup_mem_siz.patch b/tools/patman/test/0002-fdt-Correct-cast-for-sandbox-in-fdtdec_setup_mem_siz.patch
index 56278a6..48ea179 100644
--- a/tools/patman/test/0002-fdt-Correct-cast-for-sandbox-in-fdtdec_setup_mem_siz.patch
+++ b/tools/patman/test/0002-fdt-Correct-cast-for-sandbox-in-fdtdec_setup_mem_siz.patch
@@ -21,7 +21,9 @@
Cover-letter-cc: Lord Mëlchett <clergy@palace.gov>
Series-version: 3
Patch-cc: fred
+Commit-cc: joe
Series-process-log: sort, uniq
+Commit-added-in: 4
Series-changes: 4
- Some changes
- Multi
diff --git a/tools/patman/test/test01.txt b/tools/patman/test/test01.txt
index fc3066e..b2d73c5 100644
--- a/tools/patman/test/test01.txt
+++ b/tools/patman/test/test01.txt
@@ -49,7 +49,9 @@
Cover-letter-cc: Lord Mëlchett <clergy@palace.gov>
Series-version: 3
Patch-cc: fred
+ Commit-cc: joe
Series-process-log: sort, uniq
+ Commit-added-in: 4
Series-changes: 4
- Some changes
- Multi
diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 12c27b3..3e52236 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -470,7 +470,7 @@
* If no 'imagename' is specified via the commandline (e.g. if this is
* 'dumpimage -l' w/o any further constraints), we accept any spl_info.
*/
- if (params->imagename == NULL)
+ if (params->imagename == NULL || !strlen(params->imagename))
return 0;
/* Match the 'imagename' against the 'spl_hdr' found */
diff --git a/tools/u_boot_pylib/terminal.py b/tools/u_boot_pylib/terminal.py
index 40d79f8..2cd5a54 100644
--- a/tools/u_boot_pylib/terminal.py
+++ b/tools/u_boot_pylib/terminal.py
@@ -164,8 +164,11 @@
global last_print_len
if last_print_len:
- print('\r%s\r' % (' '* last_print_len), end='', flush=True)
- last_print_len = None
+ if print_test_mode:
+ print_test_list.append(PrintLine(None, None, None, None))
+ else:
+ print('\r%s\r' % (' '* last_print_len), end='', flush=True)
+ last_print_len = None
def set_print_test_mode(enable=True):
"""Go into test mode, where all printing is recorded"""
diff --git a/tools/u_boot_pylib/test_util.py b/tools/u_boot_pylib/test_util.py
index f18d385..857ce58 100644
--- a/tools/u_boot_pylib/test_util.py
+++ b/tools/u_boot_pylib/test_util.py
@@ -60,12 +60,17 @@
prefix = ''
if build_dir:
prefix = 'PYTHONPATH=$PYTHONPATH:%s/sandbox_spl/tools ' % build_dir
- cmd = ('%spython3-coverage run '
- '--omit "%s" %s %s %s %s' % (prefix, ','.join(glob_list),
+
+ # Detect a Python virtualenv and use 'coverage' instead
+ covtool = ('python3-coverage' if sys.prefix == sys.base_prefix else
+ 'coverage')
+
+ cmd = ('%s%s run '
+ '--omit "%s" %s %s %s %s' % (prefix, covtool, ','.join(glob_list),
prog, extra_args or '', test_cmd,
single_thread or '-P1'))
os.system(cmd)
- stdout = command.output('python3-coverage', 'report')
+ stdout = command.output(covtool, 'report')
lines = stdout.splitlines()
if required:
# Convert '/path/to/name.py' just the module name 'name'
