xpl: Rename spl_phase() to xpl_phase()
Rename this function to indicate that it refers to any xPL phase.
Signed-off-by: Simon Glass <sjg@chromium.org>
diff --git a/arch/x86/cpu/apollolake/cpu_spl.c b/arch/x86/cpu/apollolake/cpu_spl.c
index 8798fa7..8198667 100644
--- a/arch/x86/cpu/apollolake/cpu_spl.c
+++ b/arch/x86/cpu/apollolake/cpu_spl.c
@@ -184,9 +184,9 @@
{
int ret = 0;
- if (spl_phase() == PHASE_TPL)
+ if (xpl_phase() == PHASE_TPL)
ret = arch_cpu_init_tpl();
- else if (spl_phase() == PHASE_SPL)
+ else if (xpl_phase() == PHASE_SPL)
ret = arch_cpu_init_spl();
if (ret)
printf("%s: Error %d\n", __func__, ret);
diff --git a/arch/x86/cpu/apollolake/hostbridge.c b/arch/x86/cpu/apollolake/hostbridge.c
index 9ee3622..039236d 100644
--- a/arch/x86/cpu/apollolake/hostbridge.c
+++ b/arch/x86/cpu/apollolake/hostbridge.c
@@ -255,7 +255,7 @@
static int apl_hostbridge_probe(struct udevice *dev)
{
- if (spl_phase() == PHASE_TPL)
+ if (xpl_phase() == PHASE_TPL)
return apl_hostbridge_early_init(dev);
return 0;
diff --git a/arch/x86/cpu/apollolake/lpc.c b/arch/x86/cpu/apollolake/lpc.c
index 531ff1c..f34c199 100644
--- a/arch/x86/cpu/apollolake/lpc.c
+++ b/arch/x86/cpu/apollolake/lpc.c
@@ -80,7 +80,7 @@
lgir_reg_num = find_unused_pmio_window();
if (lgir_reg_num < 0) {
- if (spl_phase() > PHASE_TPL) {
+ if (xpl_phase() > PHASE_TPL) {
log_err("LPC: Cannot open IO window: %lx size %lx\n",
bridge_base, size - bridged_size);
log_err("No more IO windows\n");
diff --git a/arch/x86/cpu/apollolake/pch.c b/arch/x86/cpu/apollolake/pch.c
index 3219031..07ef26f 100644
--- a/arch/x86/cpu/apollolake/pch.c
+++ b/arch/x86/cpu/apollolake/pch.c
@@ -12,7 +12,7 @@
static int apl_set_spi_protect(struct udevice *dev, bool protect)
{
- if (spl_phase() == PHASE_SPL)
+ if (xpl_phase() == PHASE_SPL)
return lpc_set_spi_protect(dev, BIOS_CTRL, protect);
return 0;
diff --git a/arch/x86/cpu/apollolake/pmc.c b/arch/x86/cpu/apollolake/pmc.c
index 32fd034..bfb8a07 100644
--- a/arch/x86/cpu/apollolake/pmc.c
+++ b/arch/x86/cpu/apollolake/pmc.c
@@ -115,7 +115,7 @@
ARRAY_SIZE(base));
if (ret)
return log_msg_ret("Missing/short early-regs", ret);
- if (spl_phase() == PHASE_TPL) {
+ if (xpl_phase() == PHASE_TPL) {
upriv->pmc_bar0 = (void *)base[0];
upriv->pmc_bar2 = (void *)base[2];
@@ -186,7 +186,7 @@
static int apl_pmc_probe(struct udevice *dev)
{
- if (spl_phase() == PHASE_TPL) {
+ if (xpl_phase() == PHASE_TPL) {
return enable_pmcbar(dev);
} else {
struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
diff --git a/arch/x86/cpu/apollolake/punit.c b/arch/x86/cpu/apollolake/punit.c
index b1503c2..9c708e9 100644
--- a/arch/x86/cpu/apollolake/punit.c
+++ b/arch/x86/cpu/apollolake/punit.c
@@ -77,7 +77,7 @@
static int apl_punit_probe(struct udevice *dev)
{
- if (spl_phase() == PHASE_SPL)
+ if (xpl_phase() == PHASE_SPL)
return punit_init(dev);
return 0;
diff --git a/arch/x86/cpu/apollolake/spl.c b/arch/x86/cpu/apollolake/spl.c
index b351d73..510f8c4 100644
--- a/arch/x86/cpu/apollolake/spl.c
+++ b/arch/x86/cpu/apollolake/spl.c
@@ -116,7 +116,7 @@
return ret;
spl_image->size = CONFIG_SYS_MONITOR_LEN; /* We don't know SPL size */
- spl_image->entry_point = spl_phase() == PHASE_TPL ?
+ spl_image->entry_point = xpl_phase() == PHASE_TPL ?
CONFIG_SPL_TEXT_BASE : CONFIG_TEXT_BASE;
spl_image->load_addr = spl_image->entry_point;
spl_image->os = IH_OS_U_BOOT;
diff --git a/arch/x86/cpu/broadwell/cpu.c b/arch/x86/cpu/broadwell/cpu.c
index dc6717e..8746374 100644
--- a/arch/x86/cpu/broadwell/cpu.c
+++ b/arch/x86/cpu/broadwell/cpu.c
@@ -68,7 +68,7 @@
post_code(POST_CPU_INIT);
/* Do a mini-init if TPL has already done the full init */
- if (IS_ENABLED(CONFIG_TPL) && spl_phase() != PHASE_TPL)
+ if (IS_ENABLED(CONFIG_TPL) && xpl_phase() != PHASE_TPL)
return x86_cpu_reinit_f();
else
return x86_cpu_init_f();
diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c
index 934e98a..d837fb9 100644
--- a/arch/x86/cpu/i386/cpu.c
+++ b/arch/x86/cpu/i386/cpu.c
@@ -271,7 +271,7 @@
* Do a quick and dirty check to save space - Intel and AMD only and
* just the vendor. This is enough for most TPL code.
*/
- if (spl_phase() == PHASE_TPL) {
+ if (xpl_phase() == PHASE_TPL) {
struct cpuid_result result;
result = cpuid(0x00000000);
diff --git a/arch/x86/cpu/intel_common/mrc.c b/arch/x86/cpu/intel_common/mrc.c
index c834c05..baa1f0e 100644
--- a/arch/x86/cpu/intel_common/mrc.c
+++ b/arch/x86/cpu/intel_common/mrc.c
@@ -259,7 +259,7 @@
return ret;
delay = dev_read_u32_default(dev, "fspm,training-delay", 0);
- if (spl_phase() == PHASE_SPL) {
+ if (xpl_phase() == PHASE_SPL) {
if (delay)
printf("SDRAM training (%d seconds)...", delay);
else
diff --git a/arch/x86/cpu/intel_common/p2sb.c b/arch/x86/cpu/intel_common/p2sb.c
index 7aad8f8..406c410 100644
--- a/arch/x86/cpu/intel_common/p2sb.c
+++ b/arch/x86/cpu/intel_common/p2sb.c
@@ -96,7 +96,7 @@
return log_msg_ret("Missing/short early-regs", ret);
plat->mmio_base = base[0];
/* TPL sets up the initial BAR */
- if (spl_phase() == PHASE_TPL) {
+ if (xpl_phase() == PHASE_TPL) {
plat->bdf = pci_get_devfn(dev);
if (plat->bdf < 0)
return log_msg_ret("Cannot get p2sb PCI address",
@@ -114,9 +114,9 @@
static int p2sb_probe(struct udevice *dev)
{
- if (spl_phase() == PHASE_TPL)
+ if (xpl_phase() == PHASE_TPL)
return p2sb_early_init(dev);
- else if (spl_phase() == PHASE_SPL)
+ else if (xpl_phase() == PHASE_SPL)
return p2sb_spl_init(dev);
return 0;