x86: ivybridge: Move graphics init much later
We don't need to init the graphics controller so early. Move it alongside
the other graphics setup, just before we run the ROM.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff --git a/arch/x86/cpu/ivybridge/early_init.c b/arch/x86/cpu/ivybridge/early_init.c
index 029f5ef..83ef7b7 100644
--- a/arch/x86/cpu/ivybridge/early_init.c
+++ b/arch/x86/cpu/ivybridge/early_init.c
@@ -53,83 +53,6 @@
dm_pci_write_config8(dev, PAM6, 0x33);
}
-static void sandybridge_setup_graphics(pci_dev_t pch_dev, pci_dev_t video_dev)
-{
- u32 reg32;
- u16 reg16;
- u8 reg8;
-
- reg16 = x86_pci_read_config16(video_dev, PCI_DEVICE_ID);
- switch (reg16) {
- case 0x0102: /* GT1 Desktop */
- case 0x0106: /* GT1 Mobile */
- case 0x010a: /* GT1 Server */
- case 0x0112: /* GT2 Desktop */
- case 0x0116: /* GT2 Mobile */
- case 0x0122: /* GT2 Desktop >=1.3GHz */
- case 0x0126: /* GT2 Mobile >=1.3GHz */
- case 0x0156: /* IvyBridge */
- case 0x0166: /* IvyBridge */
- break;
- default:
- debug("Graphics not supported by this CPU/chipset\n");
- return;
- }
-
- debug("Initialising Graphics\n");
-
- /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */
- reg16 = x86_pci_read_config16(pch_dev, GGC);
- reg16 &= ~0x00f8;
- reg16 |= 1 << 3;
- /* Program GTT memory by setting GGC[9:8] = 2MB */
- reg16 &= ~0x0300;
- reg16 |= 2 << 8;
- /* Enable VGA decode */
- reg16 &= ~0x0002;
- x86_pci_write_config16(pch_dev, GGC, reg16);
-
- /* Enable 256MB aperture */
- reg8 = x86_pci_read_config8(video_dev, MSAC);
- reg8 &= ~0x06;
- reg8 |= 0x02;
- x86_pci_write_config8(video_dev, MSAC, reg8);
-
- /* Erratum workarounds */
- reg32 = readl(MCHBAR_REG(0x5f00));
- reg32 |= (1 << 9) | (1 << 10);
- writel(reg32, MCHBAR_REG(0x5f00));
-
- /* Enable SA Clock Gating */
- reg32 = readl(MCHBAR_REG(0x5f00));
- writel(reg32 | 1, MCHBAR_REG(0x5f00));
-
- /* GPU RC6 workaround for sighting 366252 */
- reg32 = readl(MCHBAR_REG(0x5d14));
- reg32 |= (1 << 31);
- writel(reg32, MCHBAR_REG(0x5d14));
-
- /* VLW */
- reg32 = readl(MCHBAR_REG(0x6120));
- reg32 &= ~(1 << 0);
- writel(reg32, MCHBAR_REG(0x6120));
-
- reg32 = readl(MCHBAR_REG(0x5418));
- reg32 |= (1 << 4) | (1 << 5);
- writel(reg32, MCHBAR_REG(0x5418));
-}
-
-void sandybridge_early_init(int chipset_type)
-{
- pci_dev_t pch_dev = PCH_DEV;
- pci_dev_t video_dev = PCH_VIDEO_DEV;
-
- /* Device Enable */
- x86_pci_write_config32(pch_dev, DEVEN, DEVEN_HOST | DEVEN_IGD);
-
- sandybridge_setup_graphics(pch_dev, video_dev);
-}
-
static int bd82x6x_northbridge_probe(struct udevice *dev)
{
const int chipset_type = SANDYBRIDGE_MOBILE;
@@ -155,6 +78,9 @@
sandybridge_setup_northbridge_bars(dev);
+ /* Device Enable */
+ dm_pci_write_config32(dev, DEVEN, DEVEN_HOST | DEVEN_IGD);
+
return 0;
}