| commit | d48aed204aa5b09ac3ce0f3dc8f9031d352ffd61 | [log] [tgz] |
|---|---|---|
| author | Fabio Estevam <festevam@gmail.com> | Fri Aug 19 03:28:10 2011 +0000 |
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | Sun Sep 04 11:36:11 2011 +0200 |
| tree | 9e1476e7354da652274b1f7b95fbed7c59ce766c | |
| parent | 088b338d626085a7acbcb1d8a41e460e52614298 [diff] |
mx53: ddr3: Update DD3 initialization Updated mx53 ddr3 script in order to align with the latest Freescale version from July 8, 2011: -change ESDREF[REF_SEL]=01 (for 32KHz), from incorrect setting of 00 (64KHz) -change DDR3 MR0 write to "setmem /32 0x63fd901c = 0x052080b0" from "0x092080b0". This changes write recovery from 8 clocks to 6 clocks (in line with ESDCFG1[tWR]) Signed-off-by: Lily Zhang <r58066@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>