diff --git a/MAINTAINERS b/MAINTAINERS
index b387207..9d447ea 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -126,8 +126,8 @@
 F:	arch/arm/include/asm/arch-s3c24x0/
 
 ARM STM SPEAR
-M:	Vipin Kumar <vipin.kumar@st.com>
-S:	Maintained
+#M:	Vipin Kumar <vipin.kumar@st.com>
+S:	Orphaned (Since 2016-02)
 T:	git git://git.denx.de/u-boot-stm.git
 F:	arch/arm/cpu/arm926ejs/spear/
 F:	arch/arm/include/asm/arch-spear/
@@ -309,8 +309,8 @@
 F:	arch/powerpc/cpu/mpc82*/
 
 POWERPC MPC83XX
-M:	Kim Phillips <kim.phillips@freescale.com>
-S:	Maintained
+#M:	Kim Phillips <kim.phillips@freescale.com>
+S:	Orphaned (Since 2016-02)
 T:	git git://git.denx.de/u-boot-mpc83xx.git
 F:	arch/powerpc/cpu/mpc83xx/
 F:	arch/powerpc/include/asm/arch-mpc83xx/
@@ -376,8 +376,8 @@
 F:	arch/sh/
 
 SPARC
-M:	Francois Retief <fgretief@spaceteq.co.za>
-S:	Maintained
+#M:	Francois Retief <fgretief@spaceteq.co.za>
+S:	Orphaned (Since 2016-02)
 T:	git git://git.denx.de/u-boot-sparc.git
 F:	arch/sparc/
 
@@ -390,8 +390,8 @@
 F:	include/spi*
 
 TQ GROUP
-M:	Martin Krause <martin.krause@tq-systems.de>
-S:	Maintained
+#M:	Martin Krause <martin.krause@tq-systems.de>
+S:	Orphaned (Since 2016-02)
 T:	git git://git.denx.de/u-boot-tq-group.git
 
 UBI
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 79ae883..b1b0c71 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -9,6 +9,43 @@
 #include <asm/io.h>
 #include <asm/arch/immap_ls102xa.h>
 #include <asm/arch/ls102xa_soc.h>
+#include <asm/arch/ls102xa_stream_id.h>
+
+struct liodn_id_table sec_liodn_tbl[] = {
+	SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
+	SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
+	SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
+	SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
+	SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
+	SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
+	SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
+	SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
+	SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
+	SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
+	SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
+	SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
+	SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
+	SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
+	SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
+	SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
+};
+
+struct smmu_stream_id dev_stream_id[] = {
+	{ 0x100, 0x01, "ETSEC MAC1" },
+	{ 0x104, 0x02, "ETSEC MAC2" },
+	{ 0x108, 0x03, "ETSEC MAC3" },
+	{ 0x10c, 0x04, "PEX1" },
+	{ 0x110, 0x05, "PEX2" },
+	{ 0x114, 0x06, "qDMA" },
+	{ 0x118, 0x07, "SATA" },
+	{ 0x11c, 0x08, "USB3" },
+	{ 0x120, 0x09, "QE" },
+	{ 0x124, 0x0a, "eSDHC" },
+	{ 0x128, 0x0b, "eMA" },
+	{ 0x14c, 0x0c, "2D-ACE" },
+	{ 0x150, 0x0d, "USB2" },
+	{ 0x18c, 0x0e, "DEBUG" },
+};
 
 unsigned int get_soc_major_rev(void)
 {
@@ -88,3 +125,14 @@
 
 	return 0;
 }
+
+int ls102xa_smmu_stream_id_init(void)
+{
+	ls1021x_config_caam_stream_id(sec_liodn_tbl,
+				      ARRAY_SIZE(sec_liodn_tbl));
+
+	ls102xa_config_smmu_stream_id(dev_stream_id,
+				      ARRAY_SIZE(dev_stream_id));
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 4e4861d..9c18fd7 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -14,6 +14,9 @@
 #ifdef CONFIG_FSL_ESDHC
 #include <fsl_esdhc.h>
 #endif
+#ifdef CONFIG_SYS_DPAA_FMAN
+#include <fsl_fman.h>
+#endif
 #ifdef CONFIG_MP
 #include <asm/arch/mp.h>
 #endif
@@ -204,4 +207,8 @@
 #ifdef CONFIG_FSL_LSCH3
 	fdt_fixup_smmu(blob);
 #endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+	fdt_fixup_fman_firmware(blob);
+#endif
 }
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 7ff0148..213ce3a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -213,6 +213,24 @@
 #endif
 }
 
+/*
+ * This erratum requires setting a value to eddrtqcr1 to optimal
+ * the DDR performance. The eddrtqcr1 register is in SCFG space
+ * of LS1043A and the offset is 0x157_020c.
+ */
+#if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
+	&& defined(CONFIG_SYS_FSL_ERRATUM_A008514)
+#error A009660 and A008514 can not be both enabled.
+#endif
+
+static void erratum_a009660(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009660
+	u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
+	out_be32(eddrtqcr1, 0x63b20042);
+#endif
+}
+
 void fsl_lsch2_early_init_f(void)
 {
 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
@@ -238,6 +256,7 @@
 
 	/* Erratum */
 	erratum_a009929();
+	erratum_a009660();
 }
 #endif
 
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b574284..578038b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -96,7 +96,8 @@
 dtb-$(CONFIG_TARGET_BEAGLE_X15) += am57xx-beagle-x15.dtb
 dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
 
-dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \
+dtb-$(CONFIG_LS102XA) += ls1021a-qds-duart.dtb \
+	ls1021a-qds-lpuart.dtb \
 	ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb
 dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
 	fsl-ls2080a-rdb.dtb
diff --git a/arch/arm/dts/ls1021a-qds-duart.dts b/arch/arm/dts/ls1021a-qds-duart.dts
new file mode 100644
index 0000000..bc56867
--- /dev/null
+++ b/arch/arm/dts/ls1021a-qds-duart.dts
@@ -0,0 +1,16 @@
+/*
+ * Freescale ls1021a QDS board common device tree source
+ *
+ * Copyright 2013-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+#include "ls1021a-qds.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &uart0;
+	};
+};
diff --git a/arch/arm/dts/ls1021a-qds-lpuart.dts b/arch/arm/dts/ls1021a-qds-lpuart.dts
new file mode 100644
index 0000000..1d16ffd
--- /dev/null
+++ b/arch/arm/dts/ls1021a-qds-lpuart.dts
@@ -0,0 +1,16 @@
+/*
+ * Freescale ls1021a QDS board common device tree source
+ *
+ * Copyright 2013-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+#include "ls1021a-qds.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &lpuart0;
+	};
+};
diff --git a/arch/arm/dts/ls1021a-qds.dts b/arch/arm/dts/ls1021a-qds.dtsi
similarity index 97%
rename from arch/arm/dts/ls1021a-qds.dts
rename to arch/arm/dts/ls1021a-qds.dtsi
index e634292..ca9e835 100644
--- a/arch/arm/dts/ls1021a-qds.dts
+++ b/arch/arm/dts/ls1021a-qds.dtsi
@@ -1,12 +1,11 @@
 /*
- * Freescale ls1021a QDS board device tree source
+ * Freescale ls1021a QDS board common device tree source
  *
  * Copyright 2013-2015 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-/dts-v1/;
 #include "ls1021a.dtsi"
 
 / {
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index ff3b1be..0ef7c9d 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -177,6 +177,8 @@
 
 #define CONFIG_SYS_FSL_ERRATUM_A009663
 #define CONFIG_SYS_FSL_ERRATUM_A009929
+#define CONFIG_SYS_FSL_ERRATUM_A009942
+#define CONFIG_SYS_FSL_ERRATUM_A009660
 #else
 #error SoC not defined
 #endif
diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h
index f10cb91..a354684 100644
--- a/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h
+++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h
@@ -9,4 +9,6 @@
 
 unsigned int get_soc_major_rev(void);
 int arch_soc_init(void);
+int ls102xa_smmu_stream_id_init(void);
+
 #endif /* __FSL_LS102XA_SOC_H */
diff --git a/arch/arm/include/asm/arch-stm32f1/stm32.h b/arch/arm/include/asm/arch-stm32f1/stm32.h
index 4094a75..1af73c5 100644
--- a/arch/arm/include/asm/arch-stm32f1/stm32.h
+++ b/arch/arm/include/asm/arch-stm32f1/stm32.h
@@ -24,6 +24,14 @@
 
 #define STM32_BUS_MASK		0xFFFF0000
 
+#define STM32_GPIOA_BASE	(STM32_APB2PERIPH_BASE + 0x0800)
+#define STM32_GPIOB_BASE	(STM32_APB2PERIPH_BASE + 0x0C00)
+#define STM32_GPIOC_BASE	(STM32_APB2PERIPH_BASE + 0x1000)
+#define STM32_GPIOD_BASE	(STM32_APB2PERIPH_BASE + 0x1400)
+#define STM32_GPIOE_BASE	(STM32_APB2PERIPH_BASE + 0x1800)
+#define STM32_GPIOF_BASE	(STM32_APB2PERIPH_BASE + 0x1C00)
+#define STM32_GPIOG_BASE	(STM32_APB2PERIPH_BASE + 0x2000)
+
 /*
  * Register maps
  */
diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h b/arch/arm/include/asm/arch-stm32f4/stm32.h
index 6b64d03..7d6331b 100644
--- a/arch/arm/include/asm/arch-stm32f4/stm32.h
+++ b/arch/arm/include/asm/arch-stm32f4/stm32.h
@@ -23,6 +23,16 @@
 
 #define STM32_BUS_MASK		0xFFFF0000
 
+#define STM32_GPIOA_BASE	(STM32_AHB1PERIPH_BASE + 0x0000)
+#define STM32_GPIOB_BASE	(STM32_AHB1PERIPH_BASE + 0x0400)
+#define STM32_GPIOC_BASE	(STM32_AHB1PERIPH_BASE + 0x0800)
+#define STM32_GPIOD_BASE	(STM32_AHB1PERIPH_BASE + 0x0C00)
+#define STM32_GPIOE_BASE	(STM32_AHB1PERIPH_BASE + 0x1000)
+#define STM32_GPIOF_BASE	(STM32_AHB1PERIPH_BASE + 0x1400)
+#define STM32_GPIOG_BASE	(STM32_AHB1PERIPH_BASE + 0x1800)
+#define STM32_GPIOH_BASE	(STM32_AHB1PERIPH_BASE + 0x1C00)
+#define STM32_GPIOI_BASE	(STM32_AHB1PERIPH_BASE + 0x2000)
+
 /*
  * Register maps
  */
diff --git a/arch/arm/include/asm/arch-stm32f4/stm32_periph.h b/arch/arm/include/asm/arch-stm32f4/stm32_periph.h
index a1af25c..38adc4e 100644
--- a/arch/arm/include/asm/arch-stm32f4/stm32_periph.h
+++ b/arch/arm/include/asm/arch-stm32f4/stm32_periph.h
@@ -22,6 +22,17 @@
 enum periph_clock {
 	USART1_CLOCK_CFG = 0,
 	USART2_CLOCK_CFG,
+	GPIO_A_CLOCK_CFG,
+	GPIO_B_CLOCK_CFG,
+	GPIO_C_CLOCK_CFG,
+	GPIO_D_CLOCK_CFG,
+	GPIO_E_CLOCK_CFG,
+	GPIO_F_CLOCK_CFG,
+	GPIO_G_CLOCK_CFG,
+	GPIO_H_CLOCK_CFG,
+	GPIO_I_CLOCK_CFG,
+	GPIO_J_CLOCK_CFG,
+	GPIO_K_CLOCK_CFG,
 };
 
 #endif /* __ASM_ARM_ARCH_PERIPH_H */
diff --git a/arch/arm/include/asm/arch-stm32f7/gpio.h b/arch/arm/include/asm/arch-stm32f7/gpio.h
new file mode 100644
index 0000000..2942cd9
--- /dev/null
+++ b/arch/arm/include/asm/arch-stm32f7/gpio.h
@@ -0,0 +1,113 @@
+/*
+ * (C) Copyright 2016
+ * Vikas Manocha, <vikas.manocha@st.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _STM32_GPIO_H_
+#define _STM32_GPIO_H_
+
+enum stm32_gpio_port {
+	STM32_GPIO_PORT_A = 0,
+	STM32_GPIO_PORT_B,
+	STM32_GPIO_PORT_C,
+	STM32_GPIO_PORT_D,
+	STM32_GPIO_PORT_E,
+	STM32_GPIO_PORT_F,
+	STM32_GPIO_PORT_G,
+	STM32_GPIO_PORT_H,
+	STM32_GPIO_PORT_I
+};
+
+enum stm32_gpio_pin {
+	STM32_GPIO_PIN_0 = 0,
+	STM32_GPIO_PIN_1,
+	STM32_GPIO_PIN_2,
+	STM32_GPIO_PIN_3,
+	STM32_GPIO_PIN_4,
+	STM32_GPIO_PIN_5,
+	STM32_GPIO_PIN_6,
+	STM32_GPIO_PIN_7,
+	STM32_GPIO_PIN_8,
+	STM32_GPIO_PIN_9,
+	STM32_GPIO_PIN_10,
+	STM32_GPIO_PIN_11,
+	STM32_GPIO_PIN_12,
+	STM32_GPIO_PIN_13,
+	STM32_GPIO_PIN_14,
+	STM32_GPIO_PIN_15
+};
+
+enum stm32_gpio_mode {
+	STM32_GPIO_MODE_IN = 0,
+	STM32_GPIO_MODE_OUT,
+	STM32_GPIO_MODE_AF,
+	STM32_GPIO_MODE_AN
+};
+
+enum stm32_gpio_otype {
+	STM32_GPIO_OTYPE_PP = 0,
+	STM32_GPIO_OTYPE_OD
+};
+
+enum stm32_gpio_speed {
+	STM32_GPIO_SPEED_2M = 0,
+	STM32_GPIO_SPEED_25M,
+	STM32_GPIO_SPEED_50M,
+	STM32_GPIO_SPEED_100M
+};
+
+enum stm32_gpio_pupd {
+	STM32_GPIO_PUPD_NO = 0,
+	STM32_GPIO_PUPD_UP,
+	STM32_GPIO_PUPD_DOWN
+};
+
+enum stm32_gpio_af {
+	STM32_GPIO_AF0 = 0,
+	STM32_GPIO_AF1,
+	STM32_GPIO_AF2,
+	STM32_GPIO_AF3,
+	STM32_GPIO_AF4,
+	STM32_GPIO_AF5,
+	STM32_GPIO_AF6,
+	STM32_GPIO_AF7,
+	STM32_GPIO_AF8,
+	STM32_GPIO_AF9,
+	STM32_GPIO_AF10,
+	STM32_GPIO_AF11,
+	STM32_GPIO_AF12,
+	STM32_GPIO_AF13,
+	STM32_GPIO_AF14,
+	STM32_GPIO_AF15
+};
+
+struct stm32_gpio_dsc {
+	enum stm32_gpio_port	port;
+	enum stm32_gpio_pin	pin;
+};
+
+struct stm32_gpio_ctl {
+	enum stm32_gpio_mode	mode;
+	enum stm32_gpio_otype	otype;
+	enum stm32_gpio_speed	speed;
+	enum stm32_gpio_pupd	pupd;
+	enum stm32_gpio_af	af;
+};
+
+static inline unsigned stm32_gpio_to_port(unsigned gpio)
+{
+	return gpio / 16;
+}
+
+static inline unsigned stm32_gpio_to_pin(unsigned gpio)
+{
+	return gpio % 16;
+}
+
+int stm32_gpio_config(const struct stm32_gpio_dsc *gpio_dsc,
+		const struct stm32_gpio_ctl *gpio_ctl);
+int stm32_gpout_set(const struct stm32_gpio_dsc *gpio_dsc, int state);
+
+#endif /* _STM32_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-stm32f7/gpt.h b/arch/arm/include/asm/arch-stm32f7/gpt.h
new file mode 100644
index 0000000..903bdf6
--- /dev/null
+++ b/arch/arm/include/asm/arch-stm32f7/gpt.h
@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2016
+ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _STM32_GPT_H
+#define _STM32_GPT_H
+
+#include <asm/arch/stm32.h>
+
+struct gpt_regs {
+	u32 cr1;
+	u32 cr2;
+	u32 smcr;
+	u32 dier;
+	u32 sr;
+	u32 egr;
+	u32 ccmr1;
+	u32 ccmr2;
+	u32 ccer;
+	u32 cnt;
+	u32 psc;
+	u32 arr;
+	u32 reserved;
+	u32 ccr1;
+	u32 ccr2;
+	u32 ccr3;
+	u32 ccr4;
+	u32 reserved1;
+	u32 dcr;
+	u32 dmar;
+	u32 tim2_5_or;
+};
+
+struct gpt_regs *const gpt1_regs_ptr =
+	(struct gpt_regs *)TIM2_BASE;
+
+/* Timer control1 register  */
+#define GPT_CR1_CEN			0x0001
+#define GPT_MODE_AUTO_RELOAD		(1 << 7)
+
+/* Auto reload register for free running config */
+#define GPT_FREE_RUNNING		0xFFFFFFFF
+
+/* Timer, HZ specific defines */
+#define CONFIG_STM32_HZ			1000
+
+/* Timer Event Generation registers */
+#define TIM_EGR_UG			(1 << 0)
+
+#endif
diff --git a/arch/arm/include/asm/arch-stm32f7/rcc.h b/arch/arm/include/asm/arch-stm32f7/rcc.h
new file mode 100644
index 0000000..8bfb7b6
--- /dev/null
+++ b/arch/arm/include/asm/arch-stm32f7/rcc.h
@@ -0,0 +1,64 @@
+/*
+ * (C) Copyright 2016
+ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _STM32_RCC_H
+#define _STM32_RCC_H
+
+#define RCC_CR		0x00	/* clock control */
+#define RCC_PLLCFGR	0x04	/* PLL configuration */
+#define RCC_CFGR	0x08	/* clock configuration */
+#define RCC_CIR		0x0C	/* clock interrupt */
+#define RCC_AHB1RSTR	0x10	/* AHB1 peripheral reset */
+#define RCC_AHB2RSTR	0x14	/* AHB2 peripheral reset */
+#define RCC_AHB3RSTR	0x18	/* AHB3 peripheral reset */
+#define RCC_APB1RSTR	0x20	/* APB1 peripheral reset */
+#define RCC_APB2RSTR	0x24	/* APB2 peripheral reset */
+#define RCC_AHB1ENR	0x30	/* AHB1 peripheral clock enable */
+#define RCC_AHB2ENR	0x34	/* AHB2 peripheral clock enable */
+#define RCC_AHB3ENR	0x38	/* AHB3 peripheral clock enable */
+#define RCC_APB1ENR	0x40	/* APB1 peripheral clock enable */
+#define RCC_APB2ENR	0x44	/* APB2 peripheral clock enable */
+#define RCC_AHB1LPENR	0x50	/* periph clk enable in low pwr mode */
+#define RCC_AHB2LPENR	0x54	/* AHB2 periph clk enable in low pwr mode */
+#define RCC_AHB3LPENR	0x58	/* AHB3 periph clk enable in low pwr mode */
+#define RCC_APB1LPENR	0x60	/* APB1 periph clk enable in low pwr mode */
+#define RCC_APB2LPENR	0x64	/* APB2 periph clk enable in low pwr mode */
+#define RCC_BDCR	0x70	/* Backup domain control */
+#define RCC_CSR		0x74	/* clock control & status */
+#define RCC_SSCGR	0x80	/* spread spectrum clock generation */
+#define RCC_PLLI2SCFGR	0x84	/* PLLI2S configuration */
+#define RCC_PLLSAICFG	0x88	/* PLLSAI configuration */
+#define RCC_DCKCFG1	0x8C	/* dedicated clocks configuration register */
+#define RCC_DCKCFG2	0x90	/* dedicated clocks configuration register */
+
+#define RCC_APB1ENR_TIM2EN		(1 << 0)
+#define RCC_APB1ENR_PWREN		(1 << 28)
+
+/*
+ * RCC USART specific definitions
+ */
+#define RCC_ENR_USART1EN		(1 << 4)
+#define RCC_ENR_USART2EN		(1 << 17)
+#define RCC_ENR_USART3EN		(1 << 18)
+#define RCC_ENR_USART6EN		(1 <<  5)
+
+/*
+ * RCC GPIO specific definitions
+ */
+#define RCC_ENR_GPIO_A_EN		(1 << 0)
+#define RCC_ENR_GPIO_B_EN		(1 << 1)
+#define RCC_ENR_GPIO_C_EN		(1 << 2)
+#define RCC_ENR_GPIO_D_EN		(1 << 3)
+#define RCC_ENR_GPIO_E_EN		(1 << 4)
+#define RCC_ENR_GPIO_F_EN		(1 << 5)
+#define RCC_ENR_GPIO_G_EN		(1 << 6)
+#define RCC_ENR_GPIO_H_EN		(1 << 7)
+#define RCC_ENR_GPIO_I_EN		(1 << 8)
+#define RCC_ENR_GPIO_J_EN		(1 << 9)
+#define RCC_ENR_GPIO_K_EN		(1 << 10)
+
+#endif
diff --git a/arch/arm/include/asm/arch-stm32f7/stm32.h b/arch/arm/include/asm/arch-stm32f7/stm32.h
new file mode 100644
index 0000000..713eb2e
--- /dev/null
+++ b/arch/arm/include/asm/arch-stm32f7/stm32.h
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2016
+ * Vikas Manocha, STMicroelectronics, <vikas.manocha@st.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_HARDWARE_H
+#define _ASM_ARCH_HARDWARE_H
+
+/* STM32F746 */
+#define ITCM_FLASH_BASE		0x00200000UL
+#define AXIM_FLASH_BASE		0x08000000UL
+
+#define ITCM_SRAM_BASE		0x00000000UL
+#define DTCM_SRAM_BASE		0x20000000UL
+#define SRAM1_BASE		0x20010000UL
+#define SRAM2_BASE		0x2004C000UL
+
+#define PERIPH_BASE		0x40000000UL
+
+#define APB1_PERIPH_BASE	(PERIPH_BASE + 0x00000000)
+#define APB2_PERIPH_BASE	(PERIPH_BASE + 0x00010000)
+#define AHB1_PERIPH_BASE	(PERIPH_BASE + 0x00020000)
+#define AHB2_PERIPH_BASE	(PERIPH_BASE + 0x10000000)
+#define AHB3_PERIPH_BASE	(PERIPH_BASE + 0x20000000)
+
+#define TIM2_BASE		(APB1_PERIPH_BASE + 0x0000)
+#define USART2_BASE		(APB1_PERIPH_BASE + 0x4400)
+#define USART3_BASE		(APB1_PERIPH_BASE + 0x4800)
+#define PWR_BASE		(APB1_PERIPH_BASE + 0x7000)
+
+#define USART1_BASE		(APB2_PERIPH_BASE + 0x1000)
+#define USART6_BASE		(APB2_PERIPH_BASE + 0x1400)
+
+#define STM32_GPIOA_BASE	(AHB1_PERIPH_BASE + 0x0000)
+#define STM32_GPIOB_BASE	(AHB1_PERIPH_BASE + 0x0400)
+#define STM32_GPIOC_BASE	(AHB1_PERIPH_BASE + 0x0800)
+#define STM32_GPIOD_BASE	(AHB1_PERIPH_BASE + 0x0C00)
+#define STM32_GPIOE_BASE	(AHB1_PERIPH_BASE + 0x1000)
+#define STM32_GPIOF_BASE	(AHB1_PERIPH_BASE + 0x1400)
+#define STM32_GPIOG_BASE	(AHB1_PERIPH_BASE + 0x1800)
+#define STM32_GPIOH_BASE	(AHB1_PERIPH_BASE + 0x1C00)
+#define STM32_GPIOI_BASE	(AHB1_PERIPH_BASE + 0x2000)
+#define STM32_GPIOJ_BASE	(AHB1_PERIPH_BASE + 0x2400)
+#define STM32_GPIOK_BASE	(AHB1_PERIPH_BASE + 0x2800)
+#define RCC_BASE		(AHB1_PERIPH_BASE + 0x3800)
+#define FLASH_CNTL_BASE		(AHB1_PERIPH_BASE + 0x3C00)
+
+
+#define SDRAM_FMC_BASE		(AHB3_PERIPH_BASE + 0x4A0000140)
+
+enum clock {
+	CLOCK_CORE,
+	CLOCK_AHB,
+	CLOCK_APB1,
+	CLOCK_APB2
+};
+#define STM32_BUS_MASK          0xFFFF0000
+
+int configure_clocks(void);
+
+#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-stm32f7/stm32_defs.h b/arch/arm/include/asm/arch-stm32f7/stm32_defs.h
new file mode 100644
index 0000000..29b98ae
--- /dev/null
+++ b/arch/arm/include/asm/arch-stm32f7/stm32_defs.h
@@ -0,0 +1,15 @@
+/*
+ * (C) Copyright 2016
+ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __STM32_DEFS_H__
+#define __STM32_DEFS_H__
+#include <asm/arch/stm32_periph.h>
+
+int clock_setup(enum periph_clock);
+
+#endif
+
diff --git a/arch/arm/include/asm/arch-stm32f7/stm32_periph.h b/arch/arm/include/asm/arch-stm32f7/stm32_periph.h
new file mode 100644
index 0000000..38adc4e
--- /dev/null
+++ b/arch/arm/include/asm/arch-stm32f7/stm32_periph.h
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2016
+ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_PERIPH_H
+#define __ASM_ARM_ARCH_PERIPH_H
+
+/*
+ * Peripherals required for pinmux configuration. List will
+ * grow with support for more devices getting added.
+ * Numbering based on interrupt table.
+ *
+ */
+enum periph_id {
+	UART1_GPIOA_9_10 = 0,
+	UART2_GPIOD_5_6,
+};
+
+enum periph_clock {
+	USART1_CLOCK_CFG = 0,
+	USART2_CLOCK_CFG,
+	GPIO_A_CLOCK_CFG,
+	GPIO_B_CLOCK_CFG,
+	GPIO_C_CLOCK_CFG,
+	GPIO_D_CLOCK_CFG,
+	GPIO_E_CLOCK_CFG,
+	GPIO_F_CLOCK_CFG,
+	GPIO_G_CLOCK_CFG,
+	GPIO_H_CLOCK_CFG,
+	GPIO_I_CLOCK_CFG,
+	GPIO_J_CLOCK_CFG,
+	GPIO_K_CLOCK_CFG,
+};
+
+#endif /* __ASM_ARM_ARCH_PERIPH_H */
diff --git a/arch/arm/mach-bcm283x/include/mach/mbox.h b/arch/arm/mach-bcm283x/include/mach/mbox.h
index af94dff..4a14391 100644
--- a/arch/arm/mach-bcm283x/include/mach/mbox.h
+++ b/arch/arm/mach-bcm283x/include/mach/mbox.h
@@ -150,6 +150,17 @@
 	} body;
 };
 
+#define BCM2835_MBOX_TAG_GET_BOARD_SERIAL	0x00010004
+
+struct bcm2835_mbox_tag_get_board_serial {
+	struct bcm2835_mbox_tag_hdr tag_hdr;
+	union {
+		struct __packed {
+			u64 serial;
+		} resp;
+	} body;
+};
+
 #define BCM2835_MBOX_TAG_GET_ARM_MEMORY		0x00010005
 
 struct bcm2835_mbox_tag_get_arm_mem {
diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig
index 7dbeb04..ec6b3ff 100644
--- a/arch/arm/mach-stm32/Kconfig
+++ b/arch/arm/mach-stm32/Kconfig
@@ -6,7 +6,11 @@
 config STM32F1
 	bool "stm32f1 family"
 
+config STM32F7
+	bool "stm32f7 family"
+
 source "arch/arm/mach-stm32/stm32f4/Kconfig"
 source "arch/arm/mach-stm32/stm32f1/Kconfig"
+source "arch/arm/mach-stm32/stm32f7/Kconfig"
 
 endif
diff --git a/arch/arm/mach-stm32/Makefile b/arch/arm/mach-stm32/Makefile
index ea06034..ffc537f 100644
--- a/arch/arm/mach-stm32/Makefile
+++ b/arch/arm/mach-stm32/Makefile
@@ -7,3 +7,4 @@
 
 obj-$(CONFIG_STM32F1) += stm32f1/
 obj-$(CONFIG_STM32F4) += stm32f4/
+obj-$(CONFIG_STM32F7) += stm32f7/
diff --git a/arch/arm/mach-stm32/stm32f4/clock.c b/arch/arm/mach-stm32/stm32f4/clock.c
index 576d3e6..631f36a 100644
--- a/arch/arm/mach-stm32/stm32f4/clock.c
+++ b/arch/arm/mach-stm32/stm32f4/clock.c
@@ -71,6 +71,21 @@
 #define FLASH_ACR_ICEN		(1 << 9)
 #define FLASH_ACR_DCEN		(1 << 10)
 
+/*
+ * RCC GPIO specific definitions
+ */
+#define RCC_ENR_GPIO_A_EN	(1 << 0)
+#define RCC_ENR_GPIO_B_EN	(1 << 1)
+#define RCC_ENR_GPIO_C_EN	(1 << 2)
+#define RCC_ENR_GPIO_D_EN	(1 << 3)
+#define RCC_ENR_GPIO_E_EN	(1 << 4)
+#define RCC_ENR_GPIO_F_EN	(1 << 5)
+#define RCC_ENR_GPIO_G_EN	(1 << 6)
+#define RCC_ENR_GPIO_H_EN	(1 << 7)
+#define RCC_ENR_GPIO_I_EN	(1 << 8)
+#define RCC_ENR_GPIO_J_EN	(1 << 9)
+#define RCC_ENR_GPIO_K_EN	(1 << 10)
+
 struct pll_psc {
 	u8	pll_m;
 	u16	pll_n;
@@ -237,6 +252,39 @@
 	case USART1_CLOCK_CFG:
 		setbits_le32(&STM32_RCC->apb2enr, RCC_ENR_USART1EN);
 		break;
+	case GPIO_A_CLOCK_CFG:
+		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_A_EN);
+		break;
+	case GPIO_B_CLOCK_CFG:
+		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_B_EN);
+		break;
+	case GPIO_C_CLOCK_CFG:
+		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_C_EN);
+		break;
+	case GPIO_D_CLOCK_CFG:
+		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_D_EN);
+		break;
+	case GPIO_E_CLOCK_CFG:
+		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_E_EN);
+		break;
+	case GPIO_F_CLOCK_CFG:
+		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_F_EN);
+		break;
+	case GPIO_G_CLOCK_CFG:
+		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_G_EN);
+		break;
+	case GPIO_H_CLOCK_CFG:
+		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_H_EN);
+		break;
+	case GPIO_I_CLOCK_CFG:
+		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_I_EN);
+		break;
+	case GPIO_J_CLOCK_CFG:
+		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_J_EN);
+		break;
+	case GPIO_K_CLOCK_CFG:
+		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_K_EN);
+		break;
 	default:
 		break;
 	}
diff --git a/arch/arm/mach-stm32/stm32f7/Kconfig b/arch/arm/mach-stm32/stm32f7/Kconfig
new file mode 100644
index 0000000..287e5ad
--- /dev/null
+++ b/arch/arm/mach-stm32/stm32f7/Kconfig
@@ -0,0 +1,8 @@
+if STM32F7
+
+config TARGET_STM32F746_DISCO
+	bool "STM32F746 Discovery board"
+
+source "board/st/stm32f746-disco/Kconfig"
+
+endif
diff --git a/arch/arm/mach-stm32/stm32f7/Makefile b/arch/arm/mach-stm32/stm32f7/Makefile
new file mode 100644
index 0000000..40f1ad3
--- /dev/null
+++ b/arch/arm/mach-stm32/stm32f7/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2016
+# Vikas Manocha, <vikas.manocha@gmail.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += timer.o clock.o
diff --git a/arch/arm/mach-stm32/stm32f7/clock.c b/arch/arm/mach-stm32/stm32f7/clock.c
new file mode 100644
index 0000000..17a715b
--- /dev/null
+++ b/arch/arm/mach-stm32/stm32f7/clock.c
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2016
+ * Vikas Manocha, <vikas.manocha@st.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/rcc.h>
+#include <asm/arch/stm32.h>
+#include <asm/arch/stm32_periph.h>
+
+void clock_setup(int peripheral)
+{
+	switch (peripheral) {
+	case USART1_CLOCK_CFG:
+		setbits_le32(RCC_BASE + RCC_APB2ENR, RCC_ENR_USART1EN);
+		break;
+	case GPIO_A_CLOCK_CFG:
+		setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_A_EN);
+		break;
+	case GPIO_B_CLOCK_CFG:
+		setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_B_EN);
+		break;
+	case GPIO_C_CLOCK_CFG:
+		setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_C_EN);
+		break;
+	case GPIO_D_CLOCK_CFG:
+		setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_D_EN);
+		break;
+	case GPIO_E_CLOCK_CFG:
+		setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_E_EN);
+		break;
+	case GPIO_F_CLOCK_CFG:
+		setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_F_EN);
+		break;
+	case GPIO_G_CLOCK_CFG:
+		setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_G_EN);
+		break;
+	case GPIO_H_CLOCK_CFG:
+		setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_H_EN);
+		break;
+	case GPIO_I_CLOCK_CFG:
+		setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_I_EN);
+		break;
+	case GPIO_J_CLOCK_CFG:
+		setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_J_EN);
+		break;
+	case GPIO_K_CLOCK_CFG:
+		setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_K_EN);
+		break;
+	default:
+		break;
+	}
+}
diff --git a/arch/arm/mach-stm32/stm32f7/timer.c b/arch/arm/mach-stm32/stm32f7/timer.c
new file mode 100644
index 0000000..a7dee10
--- /dev/null
+++ b/arch/arm/mach-stm32/stm32f7/timer.c
@@ -0,0 +1,112 @@
+/*
+ * (C) Copyright 2016
+ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/stm32.h>
+#include <asm/arch/gpt.h>
+#include <asm/arch/rcc.h>
+
+#define READ_TIMER()	(readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING)
+#define GPT_RESOLUTION	(CONFIG_SYS_HZ_CLOCK/CONFIG_STM32_HZ)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd->arch.tbl
+#define lastdec gd->arch.lastinc
+
+int timer_init(void)
+{
+	/* Timer2 clock configuration */
+	setbits_le32(RCC_BASE + RCC_APB1ENR, RCC_APB1ENR_TIM2EN);
+	/* Stop the timer */
+	writel(readl(&gpt1_regs_ptr->cr1) & ~GPT_CR1_CEN, &gpt1_regs_ptr->cr1);
+
+	writel((CONFIG_SYS_CLK_FREQ/CONFIG_SYS_HZ_CLOCK) - 1,
+						&gpt1_regs_ptr->psc);
+
+	/* Configure timer for auto-reload */
+	writel(readl(&gpt1_regs_ptr->cr1) | GPT_MODE_AUTO_RELOAD,
+						&gpt1_regs_ptr->cr1);
+
+	/* load value for free running */
+	writel(GPT_FREE_RUNNING, &gpt1_regs_ptr->arr);
+
+	/* start timer */
+	writel(readl(&gpt1_regs_ptr->cr1) | GPT_CR1_CEN, &gpt1_regs_ptr->cr1);
+
+	writel(readl(&gpt1_regs_ptr->egr) | TIM_EGR_UG, &gpt1_regs_ptr->egr);
+
+	/* Reset the timer */
+	lastdec = READ_TIMER();
+	timestamp = 0;
+
+	return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+ulong get_timer(ulong base)
+{
+	return (get_timer_masked() / GPT_RESOLUTION) - base;
+}
+
+void __udelay(unsigned long usec)
+{
+	ulong tmo;
+	ulong start = get_timer_masked();
+	ulong tenudelcnt = CONFIG_SYS_HZ_CLOCK / (1000 * 100);
+	ulong rndoff;
+
+	rndoff = (usec % 10) ? 1 : 0;
+
+	/* tenudelcnt timer tick gives 10 microsecconds delay */
+	tmo = ((usec / 10) + rndoff) * tenudelcnt;
+
+	while ((ulong) (get_timer_masked() - start) < tmo)
+		;
+}
+
+ulong get_timer_masked(void)
+{
+	ulong now = READ_TIMER();
+
+	if (now >= lastdec) {
+		/* normal mode */
+		timestamp += now - lastdec;
+	} else {
+		/* we have an overflow ... */
+		timestamp += now + GPT_FREE_RUNNING - lastdec;
+	}
+	lastdec = now;
+
+	return timestamp;
+}
+
+void udelay_masked(unsigned long usec)
+{
+	return udelay(usec);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return CONFIG_STM32_HZ;
+}
diff --git a/arch/microblaze/dts/microblaze-generic.dts b/arch/microblaze/dts/microblaze-generic.dts
index 2033309..08a1396 100644
--- a/arch/microblaze/dts/microblaze-generic.dts
+++ b/arch/microblaze/dts/microblaze-generic.dts
@@ -4,4 +4,6 @@
 	#size-cells = <1>;
 	aliases {
 	} ;
+	chosen {
+	} ;
 } ;
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 80bbc18..f168375 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -37,6 +37,10 @@
 #ifdef CONFIG_FSL_CAAM
 #include <fsl_sec.h>
 #endif
+#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)
+#include <asm/fsl_pamu.h>
+#include <fsl_secboot_err.h>
+#endif
 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #include <nand.h>
 #include <errno.h>
@@ -44,7 +48,7 @@
 
 #include "../../../../drivers/block/fsl_sata.h"
 #ifdef CONFIG_U_QE
-#include "../../../../drivers/qe/qe.h"
+#include <fsl_qe.h>
 #endif
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -432,8 +436,7 @@
 ulong cpu_init_f(void)
 {
 	extern void m8560_cpm_reset (void);
-#if defined(CONFIG_SYS_DCSRBAR_PHYS) || \
-	(defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET))
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif
 #if defined(CONFIG_SECURE_BOOT)
@@ -465,12 +468,6 @@
 #if defined(CONFIG_SYS_CPC_REINIT_F)
 	disable_cpc_sram();
 #endif
-
-#if defined(CONFIG_FSL_CORENET)
-	/* Put PAMU in bypass mode */
-	out_be32(&gur->pamubypenr, FSL_CORENET_PAMU_BYPASS);
-#endif
-
 #endif
 
 #ifdef CONFIG_CPM2
@@ -954,6 +951,11 @@
 	fman_enet_init();
 #endif
 
+#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)
+	if (pamu_init() < 0)
+		fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT);
+#endif
+
 #ifdef CONFIG_FSL_CAAM
 	sec_init();
 #endif
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 7270be1..ced216c 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -19,7 +19,9 @@
 #ifdef CONFIG_FSL_ESDHC
 #include <fsl_esdhc.h>
 #endif
-#include "../../../../drivers/qe/qe.h"		/* For struct qe_firmware */
+#ifdef CONFIG_SYS_DPAA_FMAN
+#include <fsl_fman.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -488,125 +490,6 @@
 }
 #endif
 
-/**
- * fdt_fixup_fman_firmware -- insert the Fman firmware into the device tree
- *
- * The binding for an Fman firmware node is documented in
- * Documentation/powerpc/dts-bindings/fsl/dpaa/fman.txt.  This node contains
- * the actual Fman firmware binary data.  The operating system is expected to
- * be able to parse the binary data to determine any attributes it needs.
- */
-#ifdef CONFIG_SYS_DPAA_FMAN
-void fdt_fixup_fman_firmware(void *blob)
-{
-	int rc, fmnode, fwnode = -1;
-	uint32_t phandle;
-	struct qe_firmware *fmanfw;
-	const struct qe_header *hdr;
-	unsigned int length;
-	uint32_t crc;
-	const char *p;
-
-	/* The first Fman we find will contain the actual firmware. */
-	fmnode = fdt_node_offset_by_compatible(blob, -1, "fsl,fman");
-	if (fmnode < 0)
-		/* Exit silently if there are no Fman devices */
-		return;
-
-	/* If we already have a firmware node, then also exit silently. */
-	if (fdt_node_offset_by_compatible(blob, -1, "fsl,fman-firmware") > 0)
-		return;
-
-	/* If the environment variable is not set, then exit silently */
-	p = getenv("fman_ucode");
-	if (!p)
-		return;
-
-	fmanfw = (struct qe_firmware *) simple_strtoul(p, NULL, 16);
-	if (!fmanfw)
-		return;
-
-	hdr = &fmanfw->header;
-	length = be32_to_cpu(hdr->length);
-
-	/* Verify the firmware. */
-	if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
-		(hdr->magic[2] != 'F')) {
-		printf("Data at %p is not an Fman firmware\n", fmanfw);
-		return;
-	}
-
-	if (length > CONFIG_SYS_QE_FMAN_FW_LENGTH) {
-		printf("Fman firmware at %p is too large (size=%u)\n",
-		       fmanfw, length);
-		return;
-	}
-
-	length -= sizeof(u32);	/* Subtract the size of the CRC */
-	crc = be32_to_cpu(*(u32 *)((void *)fmanfw + length));
-	if (crc != crc32_no_comp(0, (void *)fmanfw, length)) {
-		printf("Fman firmware at %p has invalid CRC\n", fmanfw);
-		return;
-	}
-
-	/* Increase the size of the fdt to make room for the node. */
-	rc = fdt_increase_size(blob, fmanfw->header.length);
-	if (rc < 0) {
-		printf("Unable to make room for Fman firmware: %s\n",
-			fdt_strerror(rc));
-		return;
-	}
-
-	/* Create the firmware node. */
-	fwnode = fdt_add_subnode(blob, fmnode, "fman-firmware");
-	if (fwnode < 0) {
-		char s[64];
-		fdt_get_path(blob, fmnode, s, sizeof(s));
-		printf("Could not add firmware node to %s: %s\n", s,
-		       fdt_strerror(fwnode));
-		return;
-	}
-	rc = fdt_setprop_string(blob, fwnode, "compatible", "fsl,fman-firmware");
-	if (rc < 0) {
-		char s[64];
-		fdt_get_path(blob, fwnode, s, sizeof(s));
-		printf("Could not add compatible property to node %s: %s\n", s,
-		       fdt_strerror(rc));
-		return;
-	}
-	phandle = fdt_create_phandle(blob, fwnode);
-	if (!phandle) {
-		char s[64];
-		fdt_get_path(blob, fwnode, s, sizeof(s));
-		printf("Could not add phandle property to node %s: %s\n", s,
-		       fdt_strerror(rc));
-		return;
-	}
-	rc = fdt_setprop(blob, fwnode, "fsl,firmware", fmanfw, fmanfw->header.length);
-	if (rc < 0) {
-		char s[64];
-		fdt_get_path(blob, fwnode, s, sizeof(s));
-		printf("Could not add firmware property to node %s: %s\n", s,
-		       fdt_strerror(rc));
-		return;
-	}
-
-	/* Find all other Fman nodes and point them to the firmware node. */
-	while ((fmnode = fdt_node_offset_by_compatible(blob, fmnode, "fsl,fman")) > 0) {
-		rc = fdt_setprop_cell(blob, fmnode, "fsl,firmware-phandle", phandle);
-		if (rc < 0) {
-			char s[64];
-			fdt_get_path(blob, fmnode, s, sizeof(s));
-			printf("Could not add pointer property to node %s: %s\n",
-			       s, fdt_strerror(rc));
-			return;
-		}
-	}
-}
-#else
-#define fdt_fixup_fman_firmware(x)
-#endif
-
 #if defined(CONFIG_PPC_P4080)
 static void fdt_fixup_usb(void *fdt)
 {
@@ -752,7 +635,9 @@
 	ft_fixup_qe_snum(blob);
 #endif
 
+#ifdef CONFIG_SYS_DPAA_FMAN
 	fdt_fixup_fman_firmware(blob);
+#endif
 
 #ifdef CONFIG_SYS_NS16550
 	do_fixup_by_compat_u32(blob, "ns16550",
diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile
index ac45e0e..c5592cd 100644
--- a/arch/powerpc/cpu/mpc8xxx/Makefile
+++ b/arch/powerpc/cpu/mpc8xxx/Makefile
@@ -24,5 +24,6 @@
 obj-$(CONFIG_FSL_LBC) += fsl_lbc.o
 obj-$(CONFIG_SYS_SRIO) += srio.o
 obj-$(CONFIG_FSL_LAW) += law.o
+obj-$(CONFIG_FSL_CORENET) += fsl_pamu.o pamu_table.o
 
 endif
diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
new file mode 100644
index 0000000..9421f1e
--- /dev/null
+++ b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
@@ -0,0 +1,433 @@
+/*
+ * FSL PAMU driver
+ *
+ * Copyright 2012-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/log2.h>
+#include <malloc.h>
+#include <asm/fsl_pamu.h>
+
+struct paace *ppaact;
+struct paace *sec;
+unsigned long fspi;
+
+static inline int __ilog2_roundup_64(uint64_t val)
+{
+	if ((val & (val - 1)) == 0)
+		return __ilog2_u64(val);
+	else
+		return  __ilog2_u64(val) + 1;
+}
+
+
+static inline int count_lsb_zeroes(unsigned long val)
+{
+	return ffs(val) - 1;
+}
+
+static unsigned int map_addrspace_size_to_wse(uint64_t addrspace_size)
+{
+	/* window size is 2^(WSE+1) bytes */
+	return count_lsb_zeroes(addrspace_size >> PAMU_PAGE_SHIFT) +
+		PAMU_PAGE_SHIFT - 1;
+}
+
+static unsigned int map_subwindow_cnt_to_wce(uint32_t subwindow_cnt)
+{
+       /* window count is 2^(WCE+1) bytes */
+	return count_lsb_zeroes(subwindow_cnt) - 1;
+}
+
+static void pamu_setup_default_xfer_to_host_ppaace(struct paace *ppaace)
+{
+	set_bf(ppaace->addr_bitfields, PAACE_AF_PT, PAACE_PT_PRIMARY);
+	set_bf(ppaace->domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR,
+	       PAACE_M_COHERENCE_REQ);
+}
+
+static void pamu_setup_default_xfer_to_host_spaace(struct paace *spaace)
+{
+	set_bf(spaace->addr_bitfields, PAACE_AF_PT, PAACE_PT_SECONDARY);
+	set_bf(spaace->domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR,
+	       PAACE_M_COHERENCE_REQ);
+}
+
+/** Sets up PPAACE entry for specified liodn
+ *
+ * @param[in] liodn      Logical IO device number
+ * @param[in] win_addr   starting address of DSA window
+ * @param[in] win-size   size of DSA window
+ * @param[in] omi        Operation mapping index -- if ~omi == 0 then omi
+				not defined
+ * @param[in] stashid    cache stash id for associated cpu -- if ~stashid == 0
+				then stashid not defined
+ * @param[in] snoopid    snoop id for hardware coherency -- if ~snoopid == 0
+				then snoopid not defined
+ * @param[in] subwin_cnt number of sub-windows
+ *
+ * @return Returns 0 upon success else error code < 0 returned
+ */
+static int pamu_config_ppaace(uint32_t liodn, uint64_t win_addr,
+	uint64_t win_size, uint32_t omi,
+	uint32_t snoopid, uint32_t stashid,
+	uint32_t subwin_cnt)
+{
+	struct paace *ppaace;
+
+	if ((win_size & (win_size - 1)) || win_size < PAMU_PAGE_SIZE)
+		return -1;
+
+	if (win_addr & (win_size - 1))
+		return -2;
+
+	if (liodn > NUM_PPAACT_ENTRIES) {
+		printf("Entries in PPACT not sufficient\n");
+		return -3;
+	}
+
+	ppaace = &ppaact[liodn];
+
+	/* window size is 2^(WSE+1) bytes */
+	set_bf(ppaace->addr_bitfields, PPAACE_AF_WSE,
+	       map_addrspace_size_to_wse(win_size));
+
+	pamu_setup_default_xfer_to_host_ppaace(ppaace);
+
+	if (sizeof(phys_addr_t) > 4)
+		ppaace->wbah = (u64)win_addr >> (PAMU_PAGE_SHIFT + 20);
+	else
+		ppaace->wbah = 0;
+
+	set_bf(ppaace->addr_bitfields, PPAACE_AF_WBAL,
+	       (win_addr >> PAMU_PAGE_SHIFT));
+
+	/* set up operation mapping if it's configured */
+	if (omi < OME_NUMBER_ENTRIES) {
+		set_bf(ppaace->impl_attr, PAACE_IA_OTM, PAACE_OTM_INDEXED);
+		ppaace->op_encode.index_ot.omi = omi;
+	} else if (~omi != 0) {
+		return -3;
+	}
+
+	/* configure stash id */
+	if (~stashid != 0)
+		set_bf(ppaace->impl_attr, PAACE_IA_CID, stashid);
+
+	/* configure snoop id */
+	if (~snoopid != 0)
+		ppaace->domain_attr.to_host.snpid = snoopid;
+
+	if (subwin_cnt) {
+		/* window count is 2^(WCE+1) bytes */
+		set_bf(ppaace->impl_attr, PAACE_IA_WCE,
+		       map_subwindow_cnt_to_wce(subwin_cnt));
+		set_bf(ppaace->addr_bitfields, PPAACE_AF_MW, 0x1);
+		ppaace->fspi = fspi;
+		fspi = fspi + DEFAULT_NUM_SUBWINDOWS - 1;
+	} else {
+		set_bf(ppaace->addr_bitfields, PAACE_AF_AP, PAACE_AP_PERMS_ALL);
+	}
+
+	asm volatile("sync" : : : "memory");
+	/* Mark the ppace entry valid */
+	ppaace->addr_bitfields |= PAACE_V_VALID;
+	asm volatile("sync" : : : "memory");
+
+	return 0;
+}
+
+static int pamu_config_spaace(uint32_t liodn,
+	uint64_t subwin_size, uint64_t subwin_addr, uint64_t size,
+	uint32_t omi, uint32_t snoopid, uint32_t stashid)
+{
+	struct paace *paace;
+	/* Align start addr of subwin to subwindoe size */
+	uint64_t sec_addr = subwin_addr & ~(subwin_size - 1);
+	uint64_t end_addr = subwin_addr + size;
+	int size_shift = __ilog2_u64(subwin_size);
+	uint64_t win_size = 0;
+	uint32_t index, swse;
+	unsigned long fspi_idx;
+
+	/* Recalculate the size */
+	size = end_addr - sec_addr;
+
+	if (!subwin_size)
+		return -1;
+
+	if (liodn > NUM_PPAACT_ENTRIES) {
+		printf("LIODN No programmed %d > no. of PPAACT entries %d\n",
+		       liodn, NUM_PPAACT_ENTRIES);
+		return -1;
+	}
+
+	while (sec_addr < end_addr) {
+		debug("sec_addr < end_addr is %llx < %llx\n", sec_addr,
+		      end_addr);
+		paace = &ppaact[liodn];
+		if (!paace)
+			return -1;
+		fspi_idx = paace->fspi;
+
+		/* Calculating the win_size here as if we map in index 0,
+			paace entry woudl need to  be programmed for SWSE */
+		win_size = end_addr - sec_addr;
+		win_size = 1 << __ilog2_roundup_64(win_size);
+
+		if (win_size > subwin_size)
+			win_size = subwin_size;
+		else if (win_size < PAMU_PAGE_SIZE)
+			win_size = PAMU_PAGE_SIZE;
+
+		debug("win_size is %llx\n", win_size);
+
+		swse = map_addrspace_size_to_wse(win_size);
+		index = sec_addr >> size_shift;
+
+		if (index == 0) {
+			set_bf(paace->win_bitfields, PAACE_WIN_SWSE, swse);
+			set_bf(paace->addr_bitfields, PAACE_AF_AP,
+			       PAACE_AP_PERMS_ALL);
+			sec_addr += subwin_size;
+			continue;
+		}
+
+		paace = sec + fspi_idx + index - 1;
+
+		debug("SPAACT:Writing at location %p, index %d\n", paace,
+		      index);
+
+		pamu_setup_default_xfer_to_host_spaace(paace);
+		set_bf(paace->addr_bitfields, SPAACE_AF_LIODN, liodn);
+		set_bf(paace->addr_bitfields, PAACE_AF_AP, PAACE_AP_PERMS_ALL);
+
+		/* configure snoop id */
+		if (~snoopid != 0)
+			paace->domain_attr.to_host.snpid = snoopid;
+
+		if (paace->addr_bitfields & PAACE_V_VALID) {
+			debug("Reached overlap condition\n");
+			debug("%d < %d\n", get_bf(paace->win_bitfields,
+						  PAACE_WIN_SWSE), swse);
+			if (get_bf(paace->win_bitfields, PAACE_WIN_SWSE) < swse)
+				set_bf(paace->win_bitfields, PAACE_WIN_SWSE,
+				       swse);
+		} else {
+			set_bf(paace->win_bitfields, PAACE_WIN_SWSE, swse);
+		}
+
+		paace->addr_bitfields |= PAACE_V_VALID;
+		sec_addr += subwin_size;
+	}
+
+	return 0;
+}
+
+int pamu_init(void)
+{
+	u32 base_addr = CONFIG_SYS_PAMU_ADDR;
+	struct ccsr_pamu *regs;
+	u32 i = 0;
+	u64 ppaact_phys, ppaact_lim, ppaact_size;
+	u64 spaact_phys, spaact_lim, spaact_size;
+
+	ppaact_size = sizeof(struct paace) * NUM_PPAACT_ENTRIES;
+	spaact_size = sizeof(struct paace) * NUM_SPAACT_ENTRIES;
+
+	/* Allocate space for Primary PAACT Table */
+	ppaact = memalign(PAMU_TABLE_ALIGNMENT, ppaact_size);
+	if (!ppaact)
+		return -1;
+	memset(ppaact, 0, ppaact_size);
+
+	/* Allocate space for Secondary PAACT Table */
+	sec = memalign(PAMU_TABLE_ALIGNMENT, spaact_size);
+	if (!sec)
+		return -1;
+	memset(sec, 0, spaact_size);
+
+	ppaact_phys = virt_to_phys((void *)ppaact);
+	ppaact_lim = ppaact_phys + ppaact_size;
+
+	spaact_phys = (uint64_t)virt_to_phys((void *)sec);
+	spaact_lim = spaact_phys + spaact_size;
+
+	/* Configure all PAMU's */
+	for (i = 0; i < CONFIG_NUM_PAMU; i++) {
+		regs = (struct ccsr_pamu *)base_addr;
+
+		out_be32(&regs->ppbah, ppaact_phys >> 32);
+		out_be32(&regs->ppbal, (uint32_t)ppaact_phys);
+
+		out_be32(&regs->pplah, (ppaact_lim) >> 32);
+		out_be32(&regs->pplal, (uint32_t)ppaact_lim);
+
+		if (sec != NULL) {
+			out_be32(&regs->spbah, spaact_phys >> 32);
+			out_be32(&regs->spbal, (uint32_t)spaact_phys);
+			out_be32(&regs->splah, spaact_lim >> 32);
+			out_be32(&regs->splal, (uint32_t)spaact_lim);
+		}
+		asm volatile("sync" : : : "memory");
+
+		base_addr += PAMU_OFFSET;
+	}
+
+	return 0;
+}
+
+void pamu_enable(void)
+{
+	u32 i = 0;
+	u32 base_addr = CONFIG_SYS_PAMU_ADDR;
+	for (i = 0; i < CONFIG_NUM_PAMU; i++) {
+		setbits_be32((void *)base_addr + PAMU_PCR_OFFSET,
+			     PAMU_PCR_PE);
+		asm volatile("sync" : : : "memory");
+		base_addr += PAMU_OFFSET;
+	}
+}
+
+void pamu_reset(void)
+{
+	u32 i  = 0;
+	u32 base_addr = CONFIG_SYS_PAMU_ADDR;
+	struct ccsr_pamu *regs;
+
+	for (i = 0; i < CONFIG_NUM_PAMU; i++) {
+		regs = (struct ccsr_pamu *)base_addr;
+	/* Clear PPAACT Base register */
+		out_be32(&regs->ppbah, 0);
+		out_be32(&regs->ppbal, 0);
+		out_be32(&regs->pplah, 0);
+		out_be32(&regs->pplal, 0);
+		out_be32(&regs->spbah, 0);
+		out_be32(&regs->spbal, 0);
+		out_be32(&regs->splah, 0);
+		out_be32(&regs->splal, 0);
+
+		clrbits_be32((void *)regs + PAMU_PCR_OFFSET, PAMU_PCR_PE);
+		asm volatile("sync" : : : "memory");
+		base_addr += PAMU_OFFSET;
+	}
+}
+
+void pamu_disable(void)
+{
+	u32 i  = 0;
+	u32 base_addr = CONFIG_SYS_PAMU_ADDR;
+
+
+	for (i = 0; i < CONFIG_NUM_PAMU; i++) {
+		clrbits_be32((void *)base_addr + PAMU_PCR_OFFSET, PAMU_PCR_PE);
+		asm volatile("sync" : : : "memory");
+		base_addr += PAMU_OFFSET;
+	}
+}
+
+
+static uint64_t find_max(uint64_t arr[], int num)
+{
+	int i = 0;
+	int max = 0;
+	for (i = 1 ; i < num; i++)
+		if (arr[max] < arr[i])
+			max = i;
+
+	return arr[max];
+}
+
+static uint64_t find_min(uint64_t arr[], int num)
+{
+	int i = 0;
+	int min = 0;
+	for (i = 1 ; i < num; i++)
+		if (arr[min] > arr[i])
+			min = i;
+
+	return arr[min];
+}
+
+static uint32_t get_win_cnt(uint64_t size)
+{
+	uint32_t win_cnt = DEFAULT_NUM_SUBWINDOWS;
+
+	while (win_cnt && (size/win_cnt) < PAMU_PAGE_SIZE)
+		win_cnt >>= 1;
+
+	return win_cnt;
+}
+
+int config_pamu(struct pamu_addr_tbl *tbl, int num_entries, uint32_t liodn)
+{
+	int i = 0;
+	int ret = 0;
+	uint32_t num_sec_windows = 0;
+	uint32_t num_windows = 0;
+	uint64_t min_addr, max_addr;
+	uint64_t size;
+	uint64_t subwin_size;
+	int sizebit;
+
+	min_addr = find_min(tbl->start_addr, num_entries);
+	max_addr = find_max(tbl->end_addr, num_entries);
+	size = max_addr - min_addr + 1;
+
+	if (!size)
+		return -1;
+
+	sizebit = __ilog2_roundup_64(size);
+	size = 1 << sizebit;
+	debug("min start_addr is %llx\n", min_addr);
+	debug("max end_addr is %llx\n", max_addr);
+	debug("size found is  %llx\n", size);
+
+	if (size < PAMU_PAGE_SIZE)
+		size = PAMU_PAGE_SIZE;
+
+	while (1) {
+		min_addr = min_addr & ~(size - 1);
+		if (min_addr + size > max_addr)
+			break;
+		size <<= 1;
+		if (!size)
+			return -1;
+	}
+	debug("PAACT :Base addr is %llx\n", min_addr);
+	debug("PAACT : Size is %llx\n", size);
+	num_windows = get_win_cnt(size);
+	/* For a single window, no spaact entries are required
+	 * sec_sub_window count = 0 */
+	if (num_windows > 1)
+		num_sec_windows = num_windows;
+	else
+		num_sec_windows = 0;
+
+	ret = pamu_config_ppaace(liodn, min_addr,
+			size , -1, -1, -1, num_sec_windows);
+
+	if (ret < 0)
+		return ret;
+
+	debug("configured ppace\n");
+
+	if (num_sec_windows) {
+		subwin_size = size >> count_lsb_zeroes(num_sec_windows);
+		debug("subwin_size is %llx\n", subwin_size);
+
+		for (i = 0; i < num_entries; i++) {
+			ret = pamu_config_spaace(liodn,
+				subwin_size, tbl->start_addr[i] - min_addr,
+				tbl->size[i], -1, -1, -1);
+
+			if (ret < 0)
+				return ret;
+		}
+	}
+
+	return ret;
+}
diff --git a/arch/powerpc/cpu/mpc8xxx/pamu_table.c b/arch/powerpc/cpu/mpc8xxx/pamu_table.c
new file mode 100644
index 0000000..26c5ea4
--- /dev/null
+++ b/arch/powerpc/cpu/mpc8xxx/pamu_table.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2012-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_pamu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void construct_pamu_addr_table(struct pamu_addr_tbl *tbl, int *num_entries)
+{
+	int i = 0;
+	int j;
+
+	tbl->start_addr[i] =
+			(uint64_t)virt_to_phys((void *)CONFIG_SYS_SDRAM_BASE);
+	tbl->size[i] = (phys_size_t)(min(gd->ram_size, CONFIG_MAX_MEM_MAPPED));
+	tbl->end_addr[i] = tbl->start_addr[i] +  tbl->size[i] - 1;
+
+	i++;
+#ifdef CONFIG_SYS_FLASH_BASE_PHYS
+	tbl->start_addr[i] =
+		(uint64_t)virt_to_phys((void *)CONFIG_SYS_FLASH_BASE_PHYS);
+	tbl->size[i] = 256 * 1024 * 1024; /* 256MB flash */
+	tbl->end_addr[i] = tbl->start_addr[i] +  tbl->size[i] - 1;
+
+	i++;
+#endif
+	debug("PAMU address\t\t\tsize\n");
+	for (j = 0; j < i ; j++)
+		debug("%llx \t\t\t%llx\n",  tbl->start_addr[j],  tbl->size[j]);
+
+	*num_entries = i;
+}
+
+int sec_config_pamu_table(uint32_t liodn_ns, uint32_t liodn_s)
+{
+	struct pamu_addr_tbl tbl;
+	int num_entries = 0;
+	int ret = 0;
+
+	construct_pamu_addr_table(&tbl, &num_entries);
+
+	ret = config_pamu(&tbl, num_entries, liodn_ns);
+	if (ret)
+		return ret;
+
+	ret = config_pamu(&tbl, num_entries, liodn_s);
+	if (ret)
+		return ret;
+
+	return ret;
+}
diff --git a/arch/powerpc/include/asm/fsl_pamu.h b/arch/powerpc/include/asm/fsl_pamu.h
new file mode 100644
index 0000000..93a7cae
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_pamu.h
@@ -0,0 +1,169 @@
+/*
+ * Copyright 2012-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __PAMU_H
+#define __PAMU_H
+
+#define CONFIG_NUM_PAMU		16
+#define NUM_PPAACT_ENTRIES	512
+#define NUM_SPAACT_ENTRIES	256
+
+/* PAMU_OFFSET to the next pamu space in ccsr */
+#define PAMU_OFFSET 0x1000
+
+#define PAMU_TABLE_ALIGNMENT 0x00001000
+
+#define PAMU_PAGE_SHIFT 12
+#define PAMU_PAGE_SIZE  4096U
+
+#define PAACE_M_COHERENCE_REQ   0x01
+
+#define PAACE_DA_HOST_CR                0x80
+#define PAACE_DA_HOST_CR_SHIFT          7
+
+#define PAACE_AF_PT                     0x00000002
+#define PAACE_AF_PT_SHIFT               1
+
+#define PAACE_PT_PRIMARY       0x0
+#define PAACE_PT_SECONDARY     0x1
+
+#define PPAACE_AF_WBAL			0xfffff000
+#define PPAACE_AF_WBAL_SHIFT		12
+
+#define	OME_NUMBER_ENTRIES      16   /* based on P4080 2.0 silicon plan */
+
+#define PAACE_IA_CID			0x00FF0000
+#define PAACE_IA_CID_SHIFT		16
+#define PAACE_IA_WCE			0x000000F0
+#define PAACE_IA_WCE_SHIFT		4
+#define PAACE_IA_ATM			0x0000000C
+#define PAACE_IA_ATM_SHIFT		2
+#define PAACE_IA_OTM			0x00000003
+#define PAACE_IA_OTM_SHIFT		0
+
+#define PAACE_OTM_NO_XLATE      0x00
+#define PAACE_OTM_IMMEDIATE     0x01
+#define PAACE_OTM_INDEXED       0x02
+#define PAACE_OTM_RESERVED      0x03
+#define PAACE_ATM_NO_XLATE      0x00
+#define PAACE_ATM_WINDOW_XLATE  0x01
+#define PAACE_ATM_PAGE_XLATE    0x02
+#define PAACE_ATM_WIN_PG_XLATE  \
+	(PAACE_ATM_WINDOW_XLATE | PAACE_ATM_PAGE_XLATE)
+#define PAACE_WIN_TWBAL			0xfffff000
+#define PAACE_WIN_TWBAL_SHIFT		12
+#define PAACE_WIN_SWSE			0x00000fc0
+#define PAACE_WIN_SWSE_SHIFT		6
+
+#define PAACE_AF_AP			0x00000018
+#define PAACE_AF_AP_SHIFT		3
+#define PAACE_AF_DD			0x00000004
+#define PAACE_AF_DD_SHIFT		2
+#define PAACE_AF_PT			0x00000002
+#define PAACE_AF_PT_SHIFT		1
+#define PAACE_AF_V			0x00000001
+#define PAACE_AF_V_SHIFT		0
+#define PPAACE_AF_WSE			0x00000fc0
+#define PPAACE_AF_WSE_SHIFT		6
+#define PPAACE_AF_MW			0x00000020
+#define PPAACE_AF_MW_SHIFT		5
+
+#define PAACE_AP_PERMS_DENIED  0x0
+#define PAACE_AP_PERMS_QUERY   0x1
+#define PAACE_AP_PERMS_UPDATE  0x2
+#define PAACE_AP_PERMS_ALL     0x3
+
+#define SPAACE_AF_LIODN			0xffff0000
+#define SPAACE_AF_LIODN_SHIFT		16
+#define PAACE_V_VALID          0x1
+
+#define set_bf(v, m, x)             (v = ((v) & ~(m)) | (((x) << \
+					(m##_SHIFT)) & (m)))
+#define get_bf(v, m)            (((v) & (m)) >> (m##_SHIFT))
+
+#define DEFAULT_NUM_SUBWINDOWS		128
+#define PAMU_PCR_OFFSET 0xc10
+#define PAMU_PCR_PE	0x40000000
+
+struct pamu_addr_tbl {
+	phys_addr_t start_addr[10];
+	phys_addr_t end_addr[10];
+	phys_size_t size[10];
+};
+
+struct paace {
+	/* PAACE Offset 0x00 */
+	uint32_t wbah;			/* only valid for Primary PAACE */
+	uint32_t addr_bitfields;	/* See P/S PAACE_AF_* */
+
+	/* PAACE Offset 0x08 */
+	/* Interpretation of first 32 bits dependent on DD above */
+	union {
+		struct {
+			/* Destination ID, see PAACE_DID_* defines */
+			uint8_t did;
+			/* Partition ID */
+			uint8_t pid;
+			/* Snoop ID */
+			uint8_t snpid;
+			/* coherency_required : 1 reserved : 7 */
+			uint8_t coherency_required; /* See PAACE_DA_* */
+		} to_host;
+		struct {
+			/* Destination ID, see PAACE_DID_* defines */
+			uint8_t  did;
+			uint8_t  reserved1;
+			uint16_t reserved2;
+		} to_io;
+	} domain_attr;
+
+	/* Implementation attributes + window count + address & operation
+	 * translation modes
+	 */
+	uint32_t impl_attr;			/* See PAACE_IA_* */
+
+	/* PAACE Offset 0x10 */
+	/* Translated window base address */
+	uint32_t twbah;
+	uint32_t win_bitfields;			/* See PAACE_WIN_* */
+
+	/* PAACE Offset 0x18 */
+	/* first secondary paace entry */
+	uint32_t fspi;			/* only valid for Primary PAACE */
+	union {
+		struct {
+			uint8_t ioea;
+			uint8_t moea;
+			uint8_t ioeb;
+			uint8_t moeb;
+		} immed_ot;
+		struct {
+			uint16_t reserved;
+			uint16_t omi;
+		} index_ot;
+	} op_encode;
+
+	/* PAACE Offset 0x20 */
+	uint32_t reserved1[2];			/* not currently implemented */
+
+	/* PAACE Offset 0x28 */
+	uint32_t reserved2[2];			/* not currently implemented */
+
+	/* PAACE Offset 0x30 */
+	uint32_t reserved3[2];			/* not currently implemented */
+
+	/* PAACE Offset 0x38 */
+	uint32_t reserved4[2];			/* not currently implemented */
+
+};
+
+int pamu_init(void);
+void pamu_enable(void);
+void pamu_disable(void);
+int config_pamu(struct pamu_addr_tbl *tbl, int num_entries, uint32_t liodn);
+int sec_config_pamu_table(uint32_t liodn_ns, uint32_t liodn_s);
+
+#endif
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index fd8aba4..53ca6d9 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1935,7 +1935,6 @@
 	u8	res24[64];
 	u32	pblsr;		/* Preboot loader status */
 	u32	pamubypenr;	/* PAMU bypass enable */
-#define FSL_CORENET_PAMU_BYPASS		0xffff0000
 	u32	dmacr1;		/* DMA control */
 	u8	res25[4];
 	u32	gensr1;		/* General status */
@@ -2774,6 +2773,21 @@
 	u8	res4[0x400];
 } ccsr_pme_t;
 
+struct ccsr_pamu {
+	u32 ppbah;
+	u32 ppbal;
+	u32 pplah;
+	u32 pplal;
+	u32 spbah;
+	u32 spbal;
+	u32 splah;
+	u32 splal;
+	u32 obah;
+	u32 obal;
+	u32 olah;
+	u32 olal;
+};
+
 #ifdef CONFIG_SYS_FSL_RAID_ENGINE
 struct ccsr_raide {
 	u8	res0[0x543];
@@ -2854,6 +2868,7 @@
 #define CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET	0xED000
 #define CONFIG_SYS_FSL_CPC_OFFSET		0x10000
 #define CONFIG_SYS_FSL_SCFG_OFFSET		0xFC000
+#define CONFIG_SYS_FSL_PAMU_OFFSET		0x20000
 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET		0x100000
 #define CONFIG_SYS_MPC85xx_DMA2_OFFSET		0x101000
 #define CONFIG_SYS_MPC85xx_DMA3_OFFSET		0x102000
@@ -3067,6 +3082,8 @@
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET)
 #define CONFIG_SYS_FSL_SRIO_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET)
+#define CONFIG_SYS_PAMU_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_PAMU_OFFSET)
 
 #define CONFIG_SYS_PCI1_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET)
diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c
index 441465c..ce4acc1 100644
--- a/board/BuR/common/common.c
+++ b/board/BuR/common/common.c
@@ -12,7 +12,6 @@
 #include <version.h>
 #include <common.h>
 #include <errno.h>
-#include <spl.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/omap.h>
@@ -640,8 +639,7 @@
 };
 #endif /* CONFIG_DRIVER_TI_CPSW, ... */
 
-#if defined(CONFIG_DRIVER_TI_CPSW)
-
+#if defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)
 int board_eth_init(bd_t *bis)
 {
 	int rv = 0;
@@ -658,8 +656,6 @@
 	mac_addr[4] = mac_lo & 0xFF;
 	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 
-#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
-	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 	if (!getenv("ethaddr")) {
 		#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_USE_FDT)
 		printf("<ethaddr> not set. trying DTB ... ");
@@ -685,10 +681,9 @@
 		printf("Error %d registering CPSW switch\n", rv);
 		return 0;
 	}
-#endif /* CONFIG_DRIVER_TI_CPSW, ... */
 	return rv;
 }
-#endif /* CONFIG_DRIVER_TI_CPSW */
+#endif /* defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD) */
 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
 int board_mmc_init(bd_t *bis)
 {
diff --git a/board/compulab/cm_t43/Makefile b/board/compulab/cm_t43/Makefile
index 3993689..c749659 100644
--- a/board/compulab/cm_t43/Makefile
+++ b/board/compulab/cm_t43/Makefile
@@ -6,4 +6,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y	+= board.o mux.o
+ifdef CONFIG_SPL_BUILD
+obj-y	+= spl.o mux.o
+else
+obj-y	+= cm_t43.o mux.o
+endif
diff --git a/board/compulab/cm_t43/board.c b/board/compulab/cm_t43/board.c
deleted file mode 100644
index 4272c45..0000000
--- a/board/compulab/cm_t43/board.c
+++ /dev/null
@@ -1,272 +0,0 @@
-/*
- * Copyright (C) 2015 Compulab, Ltd.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <cpsw.h>
-#include <spl.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/errno.h>
-#include <asm/gpio.h>
-#include <asm/emif.h>
-#include <power/pmic.h>
-#include <power/tps65218.h>
-#include "board.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-
-const struct dpll_params dpll_mpu  = { 800,  24, 1,  -1, -1, -1, -1 };
-const struct dpll_params dpll_core = { 1000, 24, -1, -1, 10,  8,  4 };
-const struct dpll_params dpll_per  = { 960,  24, 5,  -1, -1, -1, -1 };
-const struct dpll_params dpll_ddr  = { 400,  23, 1,  -1,  1, -1, -1 };
-
-const struct ctrl_ioregs ioregs_ddr3 = {
-	.cm0ioctl		= DDR3_ADDRCTRL_IOCTRL_VALUE,
-	.cm1ioctl		= DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
-	.cm2ioctl		= DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
-	.dt0ioctl		= DDR3_DATA0_IOCTRL_VALUE,
-	.dt1ioctl		= DDR3_DATA0_IOCTRL_VALUE,
-	.dt2ioctrl		= DDR3_DATA0_IOCTRL_VALUE,
-	.dt3ioctrl		= DDR3_DATA0_IOCTRL_VALUE,
-	.emif_sdram_config_ext	= 0x0143,
-};
-
-/* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
-struct emif_regs ddr3_emif_regs = {
-	.sdram_config			= 0x638413B2,
-	.ref_ctrl			= 0x00000C30,
-	.sdram_tim1			= 0xEAAAD4DB,
-	.sdram_tim2			= 0x266B7FDA,
-	.sdram_tim3			= 0x107F8678,
-	.read_idle_ctrl			= 0x00050000,
-	.zq_config			= 0x50074BE4,
-	.temp_alert_config		= 0x0,
-	.emif_ddr_phy_ctlr_1		= 0x0E004008,
-	.emif_ddr_ext_phy_ctrl_1	= 0x08020080,
-	.emif_ddr_ext_phy_ctrl_2	= 0x00000066,
-	.emif_ddr_ext_phy_ctrl_3	= 0x00000091,
-	.emif_ddr_ext_phy_ctrl_4	= 0x000000B9,
-	.emif_ddr_ext_phy_ctrl_5	= 0x000000E6,
-	.emif_rd_wr_exec_thresh		= 0x80000405,
-	.emif_prio_class_serv_map	= 0x80000001,
-	.emif_connect_id_serv_1_map	= 0x80000094,
-	.emif_connect_id_serv_2_map	= 0x00000000,
-	.emif_cos_config		= 0x000FFFFF
-};
-
-const u32 ext_phy_ctrl_const_base_ddr3[] = {
-	0x00000000,
-	0x00000044,
-	0x00000044,
-	0x00000046,
-	0x00000046,
-	0x00000000,
-	0x00000059,
-	0x00000077,
-	0x00000093,
-	0x000000A8,
-	0x00000000,
-	0x00000019,
-	0x00000037,
-	0x00000053,
-	0x00000068,
-	0x00000000,
-	0x0,
-	0x0,
-	0x40000000,
-	0x08102040
-};
-
-void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
-{
-	*regs = ext_phy_ctrl_const_base_ddr3;
-	*size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3);
-}
-
-const struct dpll_params *get_dpll_ddr_params(void)
-{
-	return &dpll_ddr;
-}
-
-const struct dpll_params *get_dpll_mpu_params(void)
-{
-	return &dpll_mpu;
-}
-
-const struct dpll_params *get_dpll_core_params(void)
-{
-	return &dpll_core;
-}
-
-const struct dpll_params *get_dpll_per_params(void)
-{
-	return &dpll_per;
-}
-
-static void enable_vtt_regulator(void)
-{
-	u32 temp;
-
-	writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
-	writel(GPIO_SETDATAOUT(7), AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
-	temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
-	temp = temp & ~(GPIO_OE_ENABLE(7));
-	writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
-}
-
-void sdram_init(void)
-{
-	unsigned long ram_size;
-
-	enable_vtt_regulator();
-	config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0);
-	ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (ram_size == 0x80000000 ||
-	    ram_size == 0x40000000 ||
-	    ram_size == 0x20000000)
-		return;
-
-	ddr3_emif_regs.sdram_config = 0x638453B2;
-	config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0);
-	ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (ram_size == 0x08000000)
-		return;
-
-	hang();
-}
-#endif
-
-/* setup board specific PMIC */
-int power_init_board(void)
-{
-	struct pmic *p;
-
-	power_tps65218_init(I2C_PMIC);
-	p = pmic_get("TPS65218_PMIC");
-	if (p && !pmic_probe(p))
-		puts("PMIC:  TPS65218\n");
-
-	return 0;
-}
-
-int board_init(void)
-{
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-	gpmc_init();
-	set_i2c_pin_mux();
-	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
-	i2c_probe(TPS65218_CHIP_PM);
-
-	return 0;
-}
-
-#ifdef CONFIG_DRIVER_TI_CPSW
-
-static void cpsw_control(int enabled)
-{
-	return;
-}
-
-static struct cpsw_slave_data cpsw_slaves[] = {
-	{
-		.slave_reg_ofs	= 0x208,
-		.sliver_reg_ofs	= 0xd80,
-		.phy_addr	= 0,
-		.phy_if		= PHY_INTERFACE_MODE_RGMII,
-	},
-	{
-		.slave_reg_ofs	= 0x308,
-		.sliver_reg_ofs	= 0xdc0,
-		.phy_addr	= 1,
-		.phy_if		= PHY_INTERFACE_MODE_RGMII,
-	},
-};
-
-static struct cpsw_platform_data cpsw_data = {
-	.mdio_base		= CPSW_MDIO_BASE,
-	.cpsw_base		= CPSW_BASE,
-	.mdio_div		= 0xff,
-	.channels		= 8,
-	.cpdma_reg_ofs		= 0x800,
-	.slaves			= 2,
-	.slave_data		= cpsw_slaves,
-	.ale_reg_ofs		= 0xd00,
-	.ale_entries		= 1024,
-	.host_port_reg_ofs	= 0x108,
-	.hw_stats_reg_ofs	= 0x900,
-	.bd_ram_ofs		= 0x2000,
-	.mac_control		= (1 << 5),
-	.control		= cpsw_control,
-	.host_port_num		= 0,
-	.version		= CPSW_CTRL_VERSION_2,
-};
-
-#define GPIO_PHY1_RST		170
-#define GPIO_PHY2_RST		168
-
-int board_phy_config(struct phy_device *phydev)
-{
-	unsigned short val;
-
-	/* introduce tx clock delay */
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
-	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
-	val |= 0x0100;
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
-
-	if (phydev->drv->config)
-		return phydev->drv->config(phydev);
-
-	return 0;
-}
-
-static void board_phy_init(void)
-{
-	set_mdio_pin_mux();
-	writel(0x40003, 0x44e10a74); /* Mux pin as clkout2 */
-	writel(0x10006, 0x44df4108); /* Select EXTDEV as clock source */
-	writel(0x4, 0x44df2e60); /* Set EXTDEV as MNbypass */
-
-	/* For revision A */
-	writel(0x2000009, 0x44df2e6c);
-	writel(0x38a, 0x44df2e70);
-
-	mdelay(10);
-
-	gpio_request(GPIO_PHY1_RST, "phy1_rst");
-	gpio_request(GPIO_PHY2_RST, "phy2_rst");
-	gpio_direction_output(GPIO_PHY1_RST, 0);
-	gpio_direction_output(GPIO_PHY2_RST, 0);
-	mdelay(2);
-
-	gpio_set_value(GPIO_PHY1_RST, 1);
-	gpio_set_value(GPIO_PHY2_RST, 1);
-	mdelay(2);
-}
-
-int board_eth_init(bd_t *bis)
-{
-	int rv;
-
-	set_rgmii_pin_mux();
-	writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel);
-	board_phy_init();
-
-	rv = cpsw_register(&cpsw_data);
-	if (rv < 0)
-		printf("Error %d registering CPSW switch\n", rv);
-
-	return rv;
-}
-#endif
diff --git a/board/compulab/cm_t43/cm_t43.c b/board/compulab/cm_t43/cm_t43.c
new file mode 100644
index 0000000..0d5da6f
--- /dev/null
+++ b/board/compulab/cm_t43/cm_t43.c
@@ -0,0 +1,151 @@
+/*
+ * Copyright (C) 2015 Compulab, Ltd.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <asm/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/emif.h>
+#include <power/pmic.h>
+#include <power/tps65218.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+/* setup board specific PMIC */
+int power_init_board(void)
+{
+	struct pmic *p;
+	uchar tps_status = 0;
+
+	power_tps65218_init(I2C_PMIC);
+	p = pmic_get("TPS65218_PMIC");
+	if (p && !pmic_probe(p)) {
+		puts("PMIC:  TPS65218\n");
+		/* We don't care if fseal is locked, but we do need it set */
+		tps65218_lock_fseal();
+		tps65218_reg_read(TPS65218_STATUS, &tps_status);
+		if (!(tps_status & TPS65218_FSEAL))
+			printf("WARNING: RTC not backed by battery!\n");
+	}
+
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gpmc_init();
+	set_i2c_pin_mux();
+	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+	i2c_probe(TPS65218_CHIP_PM);
+
+	return 0;
+}
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+
+static void cpsw_control(int enabled)
+{
+	return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+	{
+		.slave_reg_ofs	= 0x208,
+		.sliver_reg_ofs	= 0xd80,
+		.phy_addr	= 0,
+		.phy_if		= PHY_INTERFACE_MODE_RGMII,
+	},
+	{
+		.slave_reg_ofs	= 0x308,
+		.sliver_reg_ofs	= 0xdc0,
+		.phy_addr	= 1,
+		.phy_if		= PHY_INTERFACE_MODE_RGMII,
+	},
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 8,
+	.cpdma_reg_ofs		= 0x800,
+	.slaves			= 2,
+	.slave_data		= cpsw_slaves,
+	.ale_reg_ofs		= 0xd00,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x108,
+	.hw_stats_reg_ofs	= 0x900,
+	.bd_ram_ofs		= 0x2000,
+	.mac_control		= (1 << 5),
+	.control		= cpsw_control,
+	.host_port_num		= 0,
+	.version		= CPSW_CTRL_VERSION_2,
+};
+
+#define GPIO_PHY1_RST		170
+#define GPIO_PHY2_RST		168
+
+int board_phy_config(struct phy_device *phydev)
+{
+	unsigned short val;
+
+	/* introduce tx clock delay */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+	val |= 0x0100;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+	if (phydev->drv->config)
+		return phydev->drv->config(phydev);
+
+	return 0;
+}
+
+static void board_phy_init(void)
+{
+	set_mdio_pin_mux();
+	writel(0x40003, 0x44e10a74); /* Mux pin as clkout2 */
+	writel(0x10006, 0x44df4108); /* Select EXTDEV as clock source */
+	writel(0x4, 0x44df2e60); /* Set EXTDEV as MNbypass */
+
+	/* For revision A */
+	writel(0x2000009, 0x44df2e6c);
+	writel(0x38a, 0x44df2e70);
+
+	mdelay(10);
+
+	gpio_request(GPIO_PHY1_RST, "phy1_rst");
+	gpio_request(GPIO_PHY2_RST, "phy2_rst");
+	gpio_direction_output(GPIO_PHY1_RST, 0);
+	gpio_direction_output(GPIO_PHY2_RST, 0);
+	mdelay(2);
+
+	gpio_set_value(GPIO_PHY1_RST, 1);
+	gpio_set_value(GPIO_PHY2_RST, 1);
+	mdelay(2);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rv;
+
+	set_rgmii_pin_mux();
+	writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel);
+	board_phy_init();
+
+	rv = cpsw_register(&cpsw_data);
+	if (rv < 0)
+		printf("Error %d registering CPSW switch\n", rv);
+
+	return rv;
+}
+#endif
diff --git a/board/compulab/cm_t43/spl.c b/board/compulab/cm_t43/spl.c
new file mode 100644
index 0000000..b7d118e
--- /dev/null
+++ b/board/compulab/cm_t43/spl.c
@@ -0,0 +1,137 @@
+/*
+ * Copyright (C) 2016 Compulab, Ltd.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <i2c.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/gpio.h>
+#include <power/pmic.h>
+#include <power/tps65218.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct dpll_params dpll_mpu  = { 800,  24, 1,  -1, -1, -1, -1 };
+const struct dpll_params dpll_core = { 1000, 24, -1, -1, 10,  8,  4 };
+const struct dpll_params dpll_per  = { 960,  24, 5,  -1, -1, -1, -1 };
+const struct dpll_params dpll_ddr  = { 400,  23, 1,  -1,  1, -1, -1 };
+
+const struct ctrl_ioregs ioregs_ddr3 = {
+	.cm0ioctl		= DDR3_ADDRCTRL_IOCTRL_VALUE,
+	.cm1ioctl		= DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
+	.cm2ioctl		= DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
+	.dt0ioctl		= DDR3_DATA0_IOCTRL_VALUE,
+	.dt1ioctl		= DDR3_DATA0_IOCTRL_VALUE,
+	.dt2ioctrl		= DDR3_DATA0_IOCTRL_VALUE,
+	.dt3ioctrl		= DDR3_DATA0_IOCTRL_VALUE,
+	.emif_sdram_config_ext	= 0x0143,
+};
+
+/* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
+struct emif_regs ddr3_emif_regs = {
+	.sdram_config			= 0x638413B2,
+	.ref_ctrl			= 0x00000C30,
+	.sdram_tim1			= 0xEAAAD4DB,
+	.sdram_tim2			= 0x266B7FDA,
+	.sdram_tim3			= 0x107F8678,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x50074BE4,
+	.temp_alert_config		= 0x0,
+	.emif_ddr_phy_ctlr_1		= 0x0E004008,
+	.emif_ddr_ext_phy_ctrl_1	= 0x08020080,
+	.emif_ddr_ext_phy_ctrl_2	= 0x00000066,
+	.emif_ddr_ext_phy_ctrl_3	= 0x00000091,
+	.emif_ddr_ext_phy_ctrl_4	= 0x000000B9,
+	.emif_ddr_ext_phy_ctrl_5	= 0x000000E6,
+	.emif_rd_wr_exec_thresh		= 0x80000405,
+	.emif_prio_class_serv_map	= 0x80000001,
+	.emif_connect_id_serv_1_map	= 0x80000094,
+	.emif_connect_id_serv_2_map	= 0x00000000,
+	.emif_cos_config		= 0x000FFFFF
+};
+
+const u32 ext_phy_ctrl_const_base_ddr3[] = {
+	0x00000000,
+	0x00000044,
+	0x00000044,
+	0x00000046,
+	0x00000046,
+	0x00000000,
+	0x00000059,
+	0x00000077,
+	0x00000093,
+	0x000000A8,
+	0x00000000,
+	0x00000019,
+	0x00000037,
+	0x00000053,
+	0x00000068,
+	0x00000000,
+	0x0,
+	0x0,
+	0x40000000,
+	0x08102040
+};
+
+void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
+{
+	*regs = ext_phy_ctrl_const_base_ddr3;
+	*size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	return &dpll_ddr;
+}
+
+const struct dpll_params *get_dpll_mpu_params(void)
+{
+	return &dpll_mpu;
+}
+
+const struct dpll_params *get_dpll_core_params(void)
+{
+	return &dpll_core;
+}
+
+const struct dpll_params *get_dpll_per_params(void)
+{
+	return &dpll_per;
+}
+
+void scale_vcores(void)
+{
+	set_i2c_pin_mux();
+	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+	if (i2c_probe(TPS65218_CHIP_PM))
+		return;
+
+	tps65218_voltage_update(TPS65218_DCDC1, TPS65218_DCDC_VOLT_SEL_1100MV);
+	tps65218_voltage_update(TPS65218_DCDC2, TPS65218_DCDC_VOLT_SEL_1100MV);
+}
+
+void sdram_init(void)
+{
+	unsigned long ram_size;
+
+	config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0);
+	ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	if (ram_size == 0x80000000 ||
+	    ram_size == 0x40000000 ||
+	    ram_size == 0x20000000)
+		return;
+
+	ddr3_emif_regs.sdram_config = 0x638453B2;
+	config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0);
+	ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	if (ram_size == 0x08000000)
+		return;
+
+	hang();
+}
+
diff --git a/board/freescale/common/arm_sleep.c b/board/freescale/common/arm_sleep.c
index a498c65..71ed15e 100644
--- a/board/freescale/common/arm_sleep.c
+++ b/board/freescale/common/arm_sleep.c
@@ -19,7 +19,7 @@
 
 #include "sleep.h"
 #ifdef CONFIG_U_QE
-#include "../../../drivers/qe/qe.h"
+#include <fsl_qe.h>
 #endif
 
 DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/freescale/common/mpc85xx_sleep.c b/board/freescale/common/mpc85xx_sleep.c
index e9cbd51..498d770 100644
--- a/board/freescale/common/mpc85xx_sleep.c
+++ b/board/freescale/common/mpc85xx_sleep.c
@@ -8,7 +8,7 @@
 #include <asm/immap_85xx.h>
 #include "sleep.h"
 #ifdef CONFIG_U_QE
-#include "../../../drivers/qe/qe.h"
+#include <fsl_qe.h>
 #endif
 
 DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/freescale/ls1021aqds/MAINTAINERS b/board/freescale/ls1021aqds/MAINTAINERS
index 820d322..c37ab99 100644
--- a/board/freescale/ls1021aqds/MAINTAINERS
+++ b/board/freescale/ls1021aqds/MAINTAINERS
@@ -8,6 +8,7 @@
 F:	configs/ls1021aqds_ddr4_nor_lpuart_defconfig
 F:	configs/ls1021aqds_nor_SECURE_BOOT_defconfig
 F:	configs/ls1021aqds_nor_lpuart_defconfig
-F:	configs/ls1021aqds_sdcard_defconfig
+F:	configs/ls1021aqds_sdcard_ifc_defconfig
+F:	configs/ls1021aqds_sdcard_qspi_defconfig
 F:	configs/ls1021aqds_qspi_defconfig
 F:	configs/ls1021aqds_nand_defconfig
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index 5f4ec9d..dbea0bf 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -10,7 +10,6 @@
 #include <asm/arch/immap_ls102xa.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/fsl_serdes.h>
-#include <asm/arch/ls102xa_stream_id.h>
 #include <asm/arch/ls102xa_soc.h>
 #include <asm/arch/ls102xa_devdis.h>
 #include <asm/arch/ls102xa_sata.h>
@@ -28,7 +27,7 @@
 #include "../common/qixis.h"
 #include "ls1021aqds_qixis.h"
 #ifdef CONFIG_U_QE
-#include "../../../drivers/qe/qe.h"
+#include <fsl_qe.h>
 #endif
 
 #define PIN_MUX_SEL_CAN		0x03
@@ -61,7 +60,7 @@
 
 int checkboard(void)
 {
-#ifndef CONFIG_QSPI_BOOT
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 	char buf[64];
 #endif
 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
@@ -90,7 +89,7 @@
 		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 #endif
 
-#ifndef CONFIG_QSPI_BOOT
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 	printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
 	       QIXIS_READ(id), QIXIS_READ(arch));
 
@@ -426,42 +425,6 @@
 	return 0;
 }
 
-struct liodn_id_table sec_liodn_tbl[] = {
-	SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
-	SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
-	SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
-	SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
-	SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
-	SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
-	SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
-	SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
-	SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
-	SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
-	SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
-	SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
-	SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
-	SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
-	SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
-	SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
-};
-
-struct smmu_stream_id dev_stream_id[] = {
-	{ 0x100, 0x01, "ETSEC MAC1" },
-	{ 0x104, 0x02, "ETSEC MAC2" },
-	{ 0x108, 0x03, "ETSEC MAC3" },
-	{ 0x10c, 0x04, "PEX1" },
-	{ 0x110, 0x05, "PEX2" },
-	{ 0x114, 0x06, "qDMA" },
-	{ 0x118, 0x07, "SATA" },
-	{ 0x11c, 0x08, "USB3" },
-	{ 0x120, 0x09, "QE" },
-	{ 0x124, 0x0a, "eSDHC" },
-	{ 0x128, 0x0b, "eMA" },
-	{ 0x14c, 0x0c, "2D-ACE" },
-	{ 0x150, 0x0d, "USB2" },
-	{ 0x18c, 0x0e, "DEBUG" },
-};
-
 int board_init(void)
 {
 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
@@ -481,10 +444,7 @@
 	config_serdes_mux();
 #endif
 
-	ls1021x_config_caam_stream_id(sec_liodn_tbl,
-				      ARRAY_SIZE(sec_liodn_tbl));
-	ls102xa_config_smmu_stream_id(dev_stream_id,
-				      ARRAY_SIZE(dev_stream_id));
+	ls102xa_smmu_stream_id_init();
 
 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 	enable_layerscape_ns_access();
diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
similarity index 100%
rename from board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg
rename to board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
new file mode 100644
index 0000000..2bd398c
--- /dev/null
+++ b/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
@@ -0,0 +1,14 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+
+#enable IFC, disable QSPI and DSPI
+#0608000a 00000000 00000000 00000000
+#60000000 00407900 60040a00 21046000
+#00000000 00000000 00000000 00038000
+#00000000 001b7200 00000000 00000000
+
+#disable IFC, enable QSPI and DSPI
+0608000a 00000000 00000000 00000000
+60000000 00407900 60040a00 21046000
+00000000 00000000 00000000 00038000
+20024800 001b7200 00000000 00000000
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index 616e0bf..c69c9cb 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -10,7 +10,6 @@
 #include <asm/arch/immap_ls102xa.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/fsl_serdes.h>
-#include <asm/arch/ls102xa_stream_id.h>
 #include <asm/arch/ls102xa_devdis.h>
 #include <asm/arch/ls102xa_soc.h>
 #include <asm/arch/ls102xa_sata.h>
@@ -28,7 +27,7 @@
 #include <spl.h>
 #include "../common/sleep.h"
 #ifdef CONFIG_U_QE
-#include "../../../drivers/qe/qe.h"
+#include <fsl_qe.h>
 #endif
 #include <fsl_validate.h>
 
@@ -448,43 +447,6 @@
 }
 #endif
 
-
-struct liodn_id_table sec_liodn_tbl[] = {
-	SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
-	SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
-	SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
-	SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
-	SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
-	SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
-	SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
-	SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
-	SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
-	SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
-	SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
-	SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
-	SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
-	SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
-	SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
-	SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
-};
-
-struct smmu_stream_id dev_stream_id[] = {
-	{ 0x100, 0x01, "ETSEC MAC1" },
-	{ 0x104, 0x02, "ETSEC MAC2" },
-	{ 0x108, 0x03, "ETSEC MAC3" },
-	{ 0x10c, 0x04, "PEX1" },
-	{ 0x110, 0x05, "PEX2" },
-	{ 0x114, 0x06, "qDMA" },
-	{ 0x118, 0x07, "SATA" },
-	{ 0x11c, 0x08, "USB3" },
-	{ 0x120, 0x09, "QE" },
-	{ 0x124, 0x0a, "eSDHC" },
-	{ 0x128, 0x0b, "eMA" },
-	{ 0x14c, 0x0c, "2D-ACE" },
-	{ 0x150, 0x0d, "USB2" },
-	{ 0x18c, 0x0e, "DEBUG" },
-};
-
 #ifdef CONFIG_DEEP_SLEEP
 /* program the regulator (MC34VR500) to support deep sleep */
 void ls1twr_program_regulator(void)
@@ -525,10 +487,7 @@
 #endif
 #endif
 
-	ls1021x_config_caam_stream_id(sec_liodn_tbl,
-				      ARRAY_SIZE(sec_liodn_tbl));
-	ls102xa_config_smmu_stream_id(dev_stream_id,
-				      ARRAY_SIZE(dev_stream_id));
+	ls102xa_smmu_stream_id_init();
 
 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 	enable_layerscape_ns_access();
diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c
index 01db078..a72fe52 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -223,10 +223,25 @@
 
 int board_early_init_f(void)
 {
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+	u32 usb_pwrfault;
+#endif
 #ifdef CONFIG_LPUART
 	u8 uart;
 #endif
 	fsl_lsch2_early_init_f();
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+	out_be32(&scfg->rcwpmuxcr0, 0x3333);
+	out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
+	usb_pwrfault =
+		(SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB3_SHIFT) |
+		(SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB2_SHIFT) |
+		(SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
+	out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
+#endif
+
 #ifdef CONFIG_LPUART
 	/* We use lpuart0 as system console */
 	uart = QIXIS_READ(brdcfg[14]);
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
index c8f723a..66d974a 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -21,6 +21,10 @@
 #include <environment.h>
 #include <fsl_sec.h>
 #include "cpld.h"
+#ifdef CONFIG_U_QE
+#include <fsl_qe.h>
+#endif
+
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -71,23 +75,8 @@
 
 int board_early_init_f(void)
 {
-	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
-	u32 usb_pwrfault;
-
 	fsl_lsch2_early_init_f();
 
-#ifdef CONFIG_HAS_FSL_XHCI_USB
-	out_be32(&scfg->rcwpmuxcr0, 0x3333);
-	out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
-	usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
-			SCFG_USBPWRFAULT_USB3_SHIFT) |
-			(SCFG_USBPWRFAULT_DEDICATED <<
-			SCFG_USBPWRFAULT_USB2_SHIFT) |
-			(SCFG_USBPWRFAULT_SHARED <<
-			 SCFG_USBPWRFAULT_USB1_SHIFT);
-	out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
-#endif
-
 	return 0;
 }
 
@@ -113,11 +102,36 @@
 	enable_layerscape_ns_access();
 #endif
 
+#ifdef CONFIG_U_QE
+	u_qe_init();
+#endif
+
 	return 0;
 }
 
 int config_board_mux(void)
 {
+	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+	u32 usb_pwrfault;
+
+	if (hwconfig("qe-hdlc")) {
+		out_be32(&scfg->rcwpmuxcr0,
+			 (in_be32(&scfg->rcwpmuxcr0) & ~0xff00) | 0x6600);
+		printf("Assign to qe-hdlc clk, rcwpmuxcr0=%x\n",
+		       in_be32(&scfg->rcwpmuxcr0));
+	} else {
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+		out_be32(&scfg->rcwpmuxcr0, 0x3333);
+		out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
+		usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
+				SCFG_USBPWRFAULT_USB3_SHIFT) |
+				(SCFG_USBPWRFAULT_DEDICATED <<
+				SCFG_USBPWRFAULT_USB2_SHIFT) |
+				(SCFG_USBPWRFAULT_SHARED <<
+				 SCFG_USBPWRFAULT_USB1_SHIFT);
+		out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
+#endif
+	}
 	return 0;
 }
 
@@ -144,6 +158,16 @@
 }
 #endif
 
+void fdt_del_qe(void *blob)
+{
+	int nodeoff = 0;
+
+	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
+				"fsl,qe")) >= 0) {
+		fdt_del_node(blob, nodeoff);
+	}
+}
+
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	u64 base[CONFIG_NR_DRAM_BANKS];
@@ -161,6 +185,23 @@
 #ifdef CONFIG_SYS_DPAA_FMAN
 	fdt_fixup_fman_ethernet(blob);
 #endif
+
+	/*
+	 * qe-hdlc and usb multi-use the pins,
+	 * when set hwconfig to qe-hdlc, delete usb node.
+	 */
+	if (hwconfig("qe-hdlc"))
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+		fdt_del_node_and_alias(blob, "usb1");
+#endif
+	/*
+	 * qe just support qe-uart and qe-hdlc,
+	 * if qe-uart and qe-hdlc are not set in hwconfig,
+	 * delete qe node.
+	 */
+	if (!hwconfig("qe-uart") && !hwconfig("qe-hdlc"))
+		fdt_del_qe(blob);
+
 	return 0;
 }
 
diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c
index b5c44f9..668f684 100644
--- a/board/logicpd/omap3som/omap3logic.c
+++ b/board/logicpd/omap3som/omap3logic.c
@@ -228,6 +228,30 @@
 	return 0;
 }
 
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	switch (gd->bd->bi_arch_number) {
+	case MACH_TYPE_DM3730_TORPEDO:
+		setenv("fdtimage", "logicpd-torpedo-37xx-devkit.dtb");
+		break;
+	case MACH_TYPE_DM3730_SOM_LV:
+		setenv("fdtimage", "logicpd-som-lv-37xx-devkit.dtb");
+		break;
+	case MACH_TYPE_OMAP3_TORPEDO:
+		setenv("fdtimage", "logicpd-torpedo-35xx-devkit.dtb");
+		break;
+	case MACH_TYPE_OMAP3530_LV_SOM:
+		setenv("fdtimage", "logicpd-som-lv-35xx-devkit.dtb");
+		break;
+	default:
+		/* unknown machine type */
+		break;
+	}
+	return 0;
+}
+#endif
+
 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
 int board_mmc_init(bd_t *bis)
 {
diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
index 7f4fe64..1d3a4e0 100644
--- a/board/raspberrypi/rpi/rpi.c
+++ b/board/raspberrypi/rpi/rpi.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <inttypes.h>
 #include <config.h>
 #include <dm.h>
 #include <fdt_support.h>
@@ -56,6 +57,12 @@
 	u32 end_tag;
 };
 
+struct msg_get_board_serial {
+	struct bcm2835_mbox_hdr hdr;
+	struct bcm2835_mbox_tag_get_board_serial get_board_serial;
+	u32 end_tag;
+};
+
 struct msg_get_mac_address {
 	struct bcm2835_mbox_hdr hdr;
 	struct bcm2835_mbox_tag_get_mac_address get_mac_address;
@@ -281,6 +288,30 @@
 }
 #endif /* CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG */
 
+static void set_serial_number(void)
+{
+	ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_board_serial, msg, 1);
+	int ret;
+	char serial_string[17] = { 0 };
+
+	if (getenv("serial#"))
+		return;
+
+	BCM2835_MBOX_INIT_HDR(msg);
+	BCM2835_MBOX_INIT_TAG_NO_REQ(&msg->get_board_serial, GET_BOARD_SERIAL);
+
+	ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
+	if (ret) {
+		printf("bcm2835: Could not query board serial\n");
+		/* Ignore error; not critical */
+		return;
+	}
+
+	snprintf(serial_string, sizeof(serial_string), "%016" PRIx64,
+		 msg->get_board_serial.body.resp.serial);
+	setenv("serial#", serial_string);
+}
+
 int misc_init_r(void)
 {
 	set_fdtfile();
@@ -288,6 +319,8 @@
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 	set_board_info();
 #endif
+	set_serial_number();
+
 	return 0;
 }
 
diff --git a/board/samsung/origen/tools/mkorigenspl.c b/board/samsung/origen/tools/mkorigenspl.c
index 8b0c3ac..7b5d93b 100644
--- a/board/samsung/origen/tools/mkorigenspl.c
+++ b/board/samsung/origen/tools/mkorigenspl.c
@@ -83,8 +83,8 @@
 	for (i = 0; i < IMG_SIZE - SPL_HEADER_SIZE; i++)
 		checksum += buffer[i+16];
 
-	*(ulong *)buffer ^= 0x1f;
-	*(ulong *)(buffer+4) ^= checksum;
+	*(unsigned long *)buffer ^= 0x1f;
+	*(unsigned long *)(buffer+4) ^= checksum;
 
 	for (i = 1; i < SPL_HEADER_SIZE; i++)
 		buffer[i] ^= buffer[i-1];
diff --git a/board/st/stm32f429-discovery/stm32f429-discovery.c b/board/st/stm32f429-discovery/stm32f429-discovery.c
index fb8475f..d16d73f 100644
--- a/board/st/stm32f429-discovery/stm32f429-discovery.c
+++ b/board/st/stm32f429-discovery/stm32f429-discovery.c
@@ -50,6 +50,7 @@
 	int i;
 	int rv = 0;
 
+	clock_setup(GPIO_A_CLOCK_CFG);
 	for (i = 0; i < ARRAY_SIZE(usart_gpio); i++) {
 		rv = stm32_gpio_config(&usart_gpio[i], &gpio_ctl_usart);
 		if (rv)
@@ -115,6 +116,13 @@
 	int rv = 0;
 	int i;
 
+	clock_setup(GPIO_B_CLOCK_CFG);
+	clock_setup(GPIO_C_CLOCK_CFG);
+	clock_setup(GPIO_D_CLOCK_CFG);
+	clock_setup(GPIO_E_CLOCK_CFG);
+	clock_setup(GPIO_F_CLOCK_CFG);
+	clock_setup(GPIO_G_CLOCK_CFG);
+
 	for (i = 0; i < ARRAY_SIZE(ext_ram_fmc_gpio); i++) {
 		rv = stm32_gpio_config(&ext_ram_fmc_gpio[i],
 				&gpio_ctl_fmc);
diff --git a/board/st/stm32f746-disco/Kconfig b/board/st/stm32f746-disco/Kconfig
new file mode 100644
index 0000000..09289d2
--- /dev/null
+++ b/board/st/stm32f746-disco/Kconfig
@@ -0,0 +1,19 @@
+if TARGET_STM32F746_DISCO
+
+config SYS_BOARD
+	string
+	default "stm32f746-disco"
+
+config SYS_VENDOR
+	string
+	default "st"
+
+config SYS_SOC
+	string
+	default "stm32f7"
+
+config SYS_CONFIG_NAME
+	string
+	default "stm32f746-disco"
+
+endif
diff --git a/board/st/stm32f746-disco/MAINTAINERS b/board/st/stm32f746-disco/MAINTAINERS
new file mode 100644
index 0000000..2df0a65
--- /dev/null
+++ b/board/st/stm32f746-disco/MAINTAINERS
@@ -0,0 +1,6 @@
+STM32F746 DISCOVERY BOARD
+M:	Vikas Manocha <vikas.manocha@st.com>
+S:	Maintained
+F:	board/st/stm32f746-disco
+F:	include/configs/stm32f746-disco.h
+F:	configs/stm32f746-disco_defconfig
diff --git a/board/st/stm32f746-disco/Makefile b/board/st/stm32f746-disco/Makefile
new file mode 100644
index 0000000..db8a0a4
--- /dev/null
+++ b/board/st/stm32f746-disco/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2016
+# Vikas Manocha <vikas.manocha@st.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= stm32f746-disco.o
diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c
new file mode 100644
index 0000000..0e04d14
--- /dev/null
+++ b/board/st/stm32f746-disco/stm32f746-disco.c
@@ -0,0 +1,99 @@
+/*
+ * (C) Copyright 2016
+ * Vikas Manocha, <vikas.manocha@st.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/armv7m.h>
+#include <asm/arch/stm32.h>
+#include <asm/arch/gpio.h>
+#include <dm/platdata.h>
+#include <dm/platform_data/serial_stm32x7.h>
+#include <asm/arch/stm32_periph.h>
+#include <asm/arch/stm32_defs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct stm32_gpio_ctl gpio_ctl_gpout = {
+	.mode = STM32_GPIO_MODE_OUT,
+	.otype = STM32_GPIO_OTYPE_PP,
+	.speed = STM32_GPIO_SPEED_50M,
+	.pupd = STM32_GPIO_PUPD_NO,
+	.af = STM32_GPIO_AF0
+};
+
+const struct stm32_gpio_ctl gpio_ctl_usart = {
+	.mode = STM32_GPIO_MODE_AF,
+	.otype = STM32_GPIO_OTYPE_PP,
+	.speed = STM32_GPIO_SPEED_50M,
+	.pupd = STM32_GPIO_PUPD_UP,
+	.af = STM32_GPIO_AF7
+};
+
+static const struct stm32_gpio_dsc usart_gpio[] = {
+	{STM32_GPIO_PORT_A, STM32_GPIO_PIN_9},	/* TX */
+	{STM32_GPIO_PORT_B, STM32_GPIO_PIN_7},	/* RX */
+};
+
+int uart_setup_gpio(void)
+{
+	int i;
+	int rv = 0;
+
+	clock_setup(GPIO_A_CLOCK_CFG);
+	clock_setup(GPIO_B_CLOCK_CFG);
+	for (i = 0; i < ARRAY_SIZE(usart_gpio); i++) {
+		rv = stm32_gpio_config(&usart_gpio[i], &gpio_ctl_usart);
+		if (rv)
+			goto out;
+	}
+
+out:
+	return rv;
+}
+
+static const struct stm32x7_serial_platdata serial_platdata = {
+	.base = (struct stm32_usart *)USART1_BASE,
+	.clock = CONFIG_SYS_CLK_FREQ,
+};
+
+U_BOOT_DEVICE(stm32x7_serials) = {
+	.name = "serial_stm32x7",
+	.platdata = &serial_platdata,
+};
+
+u32 get_board_rev(void)
+{
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	int res;
+
+	res = uart_setup_gpio();
+	clock_setup(USART1_CLOCK_CFG);
+	if (res)
+		return res;
+
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
+	gd->bd->bi_dram[0].size  = CONFIG_SYS_RAM_SIZE;
+
+	gd->ram_size = CONFIG_SYS_RAM_SIZE;
+	return 0;
+}
diff --git a/cmd/bootm.c b/cmd/bootm.c
index 48738ac..555ccbc 100644
--- a/cmd/bootm.c
+++ b/cmd/bootm.c
@@ -755,15 +755,15 @@
 #ifdef CONFIG_SYS_LONGHELP
 static char booti_help_text[] =
 	"[addr [initrd[:size]] [fdt]]\n"
-	"    - boot Linux Image stored in memory\n"
+	"    - boot arm64 Linux Image stored in memory\n"
 	"\tThe argument 'initrd' is optional and specifies the address\n"
-	"\tof the initrd in memory. The optional argument ':size' allows\n"
-	"\tspecifying the size of RAW initrd.\n"
+	"\tof an initrd in memory. The optional parameter ':size' allows\n"
+	"\tspecifying the size of a RAW initrd.\n"
 #if defined(CONFIG_OF_LIBFDT)
-	"\tSince booting a Linux kernelrequires a flat device-tree\n"
-	"\ta third argument is required which is the address of the\n"
-	"\tdevice-tree blob. To boot that kernel without an initrd image,\n"
-	"\tuse a '-' for the second argument.\n"
+	"\tSince booting a Linux kernel requires a flat device-tree, a\n"
+	"\tthird argument providing the address of the device-tree blob\n"
+	"\tis required. To boot a kernel with a device-tree blob but\n"
+	"\twithout an initrd image, use a '-' for the initrd argument.\n"
 #endif
 	"";
 #endif
diff --git a/cmd/mem.c b/cmd/mem.c
index efa3929..a690957 100644
--- a/cmd/mem.c
+++ b/cmd/mem.c
@@ -1038,7 +1038,7 @@
 		return -1;
 	}
 
-	printf("Testing %08x ... %08x:\n", (uint)start, (uint)end);
+	printf("Testing %08lx ... %08lx:\n", start, end);
 	debug("%s:%d: start %#08lx end %#08lx\n", __func__, __LINE__,
 	      start, end);
 
diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig
index 6044ae9..d1da759 100644
--- a/configs/cm_t43_defconfig
+++ b/configs/cm_t43_defconfig
@@ -2,6 +2,7 @@
 CONFIG_TARGET_CM_T43=y
 CONFIG_DM_GPIO=y
 CONFIG_SPL=y
+CONFIG_SYS_PROMPT="CM-T43 # "
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
@@ -10,3 +11,15 @@
 # CONFIG_CMD_NFS is not set
 CONFIG_DM=y
 CONFIG_SYS_NS16550=y
+CONFIG_DM_SERIAL=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/kwb_defconfig b/configs/kwb_defconfig
index 10d39eb..4d2aa6c 100644
--- a/configs/kwb_defconfig
+++ b/configs/kwb_defconfig
@@ -2,7 +2,7 @@
 CONFIG_TARGET_KWB=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
-CONFIG_SYS_PROMPT="U-Boot (BuR V2.0)# "
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_BOOTM is not set
 # CONFIG_CMD_GO is not set
@@ -14,9 +14,18 @@
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_NETCONSOLE=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_STORAGE=y
diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig
index 2f16339..842f645 100644
--- a/configs/ls1021aqds_ddr4_nor_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_defconfig
@@ -1,7 +1,11 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_DM_SERIAL=y
+CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
index 44b2a0d..0e1a59d 100644
--- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
@@ -1,7 +1,11 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART"
+CONFIG_DM_SERIAL=y
+CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_FSL_LPUART=y
diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig
index 6878df4..f4c81e2 100644
--- a/configs/ls1021aqds_nor_defconfig
+++ b/configs/ls1021aqds_nor_defconfig
@@ -1,6 +1,10 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig
index 1186af2..e81448d 100644
--- a/configs/ls1021aqds_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_nor_lpuart_defconfig
@@ -1,7 +1,11 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
 CONFIG_SYS_EXTRA_OPTIONS="LPUART"
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_FSL_LPUART=y
diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig
index 0f740fd..2e98d6c 100644
--- a/configs/ls1021aqds_qspi_defconfig
+++ b/configs/ls1021aqds_qspi_defconfig
@@ -1,7 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
 CONFIG_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds"
+CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
 CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/ls1021aqds_sdcard_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig
similarity index 71%
rename from configs/ls1021aqds_sdcard_defconfig
rename to configs/ls1021aqds_sdcard_ifc_defconfig
index 3249b48..e283f69 100644
--- a/configs/ls1021aqds_sdcard_defconfig
+++ b/configs/ls1021aqds_sdcard_ifc_defconfig
@@ -1,8 +1,11 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
+CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig
new file mode 100644
index 0000000..cd75af6
--- /dev/null
+++ b/configs/ls1021aqds_sdcard_qspi_defconfig
@@ -0,0 +1,16 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1021AQDS=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
+CONFIG_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_DSPI=y
+CONFIG_FSL_QSPI=y
diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig
new file mode 100644
index 0000000..7cfed4a
--- /dev/null
+++ b/configs/stm32f746-disco_defconfig
@@ -0,0 +1,9 @@
+CONFIG_ARM=y
+CONFIG_STM32=y
+CONFIG_STM32F7=y
+CONFIG_TARGET_STM32F746_DISCO=y
+CONFIG_SYS_PROMPT="U-Boot > "
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
+# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/tseries_mmc_defconfig b/configs/tseries_mmc_defconfig
index 7518774..168e379 100644
--- a/configs/tseries_mmc_defconfig
+++ b/configs/tseries_mmc_defconfig
@@ -2,7 +2,7 @@
 CONFIG_TARGET_TSERIES=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,EMMC_BOOT"
-CONFIG_SYS_PROMPT="U-Boot (BuR V2.0)# "
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
@@ -11,9 +11,18 @@
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_NETCONSOLE=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_STORAGE=y
diff --git a/configs/tseries_nand_defconfig b/configs/tseries_nand_defconfig
index 65d514a..8151caf 100644
--- a/configs/tseries_nand_defconfig
+++ b/configs/tseries_nand_defconfig
@@ -2,7 +2,7 @@
 CONFIG_TARGET_TSERIES=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
-CONFIG_SYS_PROMPT="U-Boot (BuR V2.0)# "
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
@@ -11,9 +11,19 @@
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_NETCONSOLE=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_STORAGE=y
diff --git a/configs/tseries_spi_defconfig b/configs/tseries_spi_defconfig
index 11e4e6b..901c55e 100644
--- a/configs/tseries_spi_defconfig
+++ b/configs/tseries_spi_defconfig
@@ -2,7 +2,7 @@
 CONFIG_TARGET_TSERIES=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT"
-CONFIG_SYS_PROMPT="U-Boot (BuR V2.0)# "
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
@@ -11,11 +11,23 @@
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_NETCONSOLE=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_STORAGE=y
diff --git a/doc/driver-model/serial-howto.txt b/doc/driver-model/serial-howto.txt
index 61f2da3..cddfb9f 100644
--- a/doc/driver-model/serial-howto.txt
+++ b/doc/driver-model/serial-howto.txt
@@ -4,7 +4,6 @@
 Almost all of the serial drivers have been converted as at January 2016. These
 ones remain:
 
-   arm_dcc.c
    mcfuart.c
    serial_bfin.c
    serial_pxa.c
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index b553e3c..b766470 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -12,6 +12,9 @@
 #include "jr.h"
 #include "jobdesc.h"
 #include "desc_constr.h"
+#ifdef CONFIG_FSL_CORENET
+#include <asm/fsl_pamu.h>
+#endif
 
 #define CIRC_CNT(head, tail, size)	(((head) - (tail)) & (size - 1))
 #define CIRC_SPACE(head, tail, size)	CIRC_CNT((tail), (head) + 1, (size))
@@ -95,14 +98,16 @@
 				JR_SIZE * sizeof(dma_addr_t));
 	if (!jr.input_ring)
 		return -1;
+
+	jr.op_size = roundup(JR_SIZE * sizeof(struct op_ring),
+			     ARCH_DMA_MINALIGN);
 	jr.output_ring =
-	    (struct op_ring *)memalign(ARCH_DMA_MINALIGN,
-				JR_SIZE * sizeof(struct op_ring));
+	    (struct op_ring *)memalign(ARCH_DMA_MINALIGN, jr.op_size);
 	if (!jr.output_ring)
 		return -1;
 
 	memset(jr.input_ring, 0, JR_SIZE * sizeof(dma_addr_t));
-	memset(jr.output_ring, 0, JR_SIZE * sizeof(struct op_ring));
+	memset(jr.output_ring, 0, jr.op_size);
 
 	start_jr0();
 
@@ -190,8 +195,8 @@
 
 	unsigned long start = (unsigned long)&jr.info[head] &
 					~(ARCH_DMA_MINALIGN - 1);
-	unsigned long end = ALIGN(start + sizeof(struct jr_info),
-					ARCH_DMA_MINALIGN);
+	unsigned long end = ALIGN((unsigned long)&jr.info[head] +
+				  sizeof(struct jr_info), ARCH_DMA_MINALIGN);
 	flush_dcache_range(start, end);
 
 #ifdef CONFIG_PHYS_64BIT
@@ -216,11 +221,19 @@
 #endif /* ifdef CONFIG_PHYS_64BIT */
 
 	start = (unsigned long)&jr.input_ring[head] & ~(ARCH_DMA_MINALIGN - 1);
-	end = ALIGN(start + sizeof(phys_addr_t), ARCH_DMA_MINALIGN);
+	end = ALIGN((unsigned long)&jr.input_ring[head] +
+		     sizeof(dma_addr_t), ARCH_DMA_MINALIGN);
 	flush_dcache_range(start, end);
 
 	jr.head = (head + 1) & (jr.size - 1);
 
+	/* Invalidate output ring */
+	start = (unsigned long)jr.output_ring &
+					~(ARCH_DMA_MINALIGN - 1);
+	end = ALIGN((unsigned long)jr.output_ring + jr.op_size,
+		     ARCH_DMA_MINALIGN);
+	invalidate_dcache_range(start, end);
+
 	sec_out32(&regs->irja, 1);
 
 	return 0;
@@ -241,12 +254,6 @@
 #endif
 
 	while (sec_in32(&regs->orsf) && CIRC_CNT(jr.head, jr.tail, jr.size)) {
-		unsigned long start = (unsigned long)jr.output_ring &
-					~(ARCH_DMA_MINALIGN - 1);
-		unsigned long end = ALIGN(start +
-					  sizeof(struct op_ring)*JR_SIZE,
-					  ARCH_DMA_MINALIGN);
-		invalidate_dcache_range(start, end);
 
 		found = 0;
 
@@ -530,18 +537,38 @@
 	uint32_t mcr = sec_in32(&sec->mcfgr);
 	int ret = 0;
 
+#ifdef CONFIG_FSL_CORENET
+	uint32_t liodnr;
+	uint32_t liodn_ns;
+	uint32_t liodn_s;
+#endif
+
 	mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT);
 #ifdef CONFIG_PHYS_64BIT
 	mcr |= (1 << MCFGR_PS_SHIFT);
 #endif
 	sec_out32(&sec->mcfgr, mcr);
 
+#ifdef CONFIG_FSL_CORENET
+	liodnr = sec_in32(&sec->jrliodnr[0].ls);
+	liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT;
+	liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
+#endif
+
 	ret = jr_init();
 	if (ret < 0) {
 		printf("SEC initialization failed\n");
 		return -1;
 	}
 
+#ifdef CONFIG_FSL_CORENET
+	ret = sec_config_pamu_table(liodn_ns, liodn_s);
+	if (ret < 0)
+		return -1;
+
+	pamu_enable();
+#endif
+
 	if (get_rng_vid() >= 4) {
 		if (rng_init() < 0) {
 			printf("RNG instantiation failed\n");
diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h
index 5899696..545d964 100644
--- a/drivers/crypto/fsl/jr.h
+++ b/drivers/crypto/fsl/jr.h
@@ -72,6 +72,8 @@
 	int write_idx;
 	/* Size of the rings. */
 	int size;
+	/* Op ring size aligned to cache line size */
+	int op_size;
 	/* The ip and output rings have to be accessed by SEC. So the
 	 * pointers will ahve to point to the housekeeping region provided
 	 * by SEC
diff --git a/drivers/gpio/stm32_gpio.c b/drivers/gpio/stm32_gpio.c
index 75a84e1..50f86d3 100644
--- a/drivers/gpio/stm32_gpio.c
+++ b/drivers/gpio/stm32_gpio.c
@@ -19,17 +19,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if defined(CONFIG_STM32F4)
-#define STM32_GPIOA_BASE	(STM32_AHB1PERIPH_BASE + 0x0000)
-#define STM32_GPIOB_BASE	(STM32_AHB1PERIPH_BASE + 0x0400)
-#define STM32_GPIOC_BASE	(STM32_AHB1PERIPH_BASE + 0x0800)
-#define STM32_GPIOD_BASE	(STM32_AHB1PERIPH_BASE + 0x0C00)
-#define STM32_GPIOE_BASE	(STM32_AHB1PERIPH_BASE + 0x1000)
-#define STM32_GPIOF_BASE	(STM32_AHB1PERIPH_BASE + 0x1400)
-#define STM32_GPIOG_BASE	(STM32_AHB1PERIPH_BASE + 0x1800)
-#define STM32_GPIOH_BASE	(STM32_AHB1PERIPH_BASE + 0x1C00)
-#define STM32_GPIOI_BASE	(STM32_AHB1PERIPH_BASE + 0x2000)
-
+#if defined(CONFIG_STM32F4) || defined(CONFIG_STM32F7)
 static const unsigned long io_base[] = {
 	STM32_GPIOA_BASE, STM32_GPIOB_BASE, STM32_GPIOC_BASE,
 	STM32_GPIOD_BASE, STM32_GPIOE_BASE, STM32_GPIOF_BASE,
@@ -70,8 +60,6 @@
 
 	gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
 
-	setbits_le32(&STM32_RCC->ahb1enr, 1 << dsc->port);
-
 	i = (dsc->pin & 0x07) * 4;
 	clrsetbits_le32(&gpio_regs->afr[dsc->pin >> 3], 0xF << i, ctl->af << i);
 
@@ -87,14 +75,6 @@
 	return rv;
 }
 #elif defined(CONFIG_STM32F1)
-#define STM32_GPIOA_BASE	(STM32_APB2PERIPH_BASE + 0x0800)
-#define STM32_GPIOB_BASE	(STM32_APB2PERIPH_BASE + 0x0C00)
-#define STM32_GPIOC_BASE	(STM32_APB2PERIPH_BASE + 0x1000)
-#define STM32_GPIOD_BASE	(STM32_APB2PERIPH_BASE + 0x1400)
-#define STM32_GPIOE_BASE	(STM32_APB2PERIPH_BASE + 0x1800)
-#define STM32_GPIOF_BASE	(STM32_APB2PERIPH_BASE + 0x1C00)
-#define STM32_GPIOG_BASE	(STM32_APB2PERIPH_BASE + 0x2000)
-
 static const unsigned long io_base[] = {
 	STM32_GPIOA_BASE, STM32_GPIOB_BASE, STM32_GPIOC_BASE,
 	STM32_GPIOD_BASE, STM32_GPIOE_BASE, STM32_GPIOF_BASE,
@@ -141,9 +121,6 @@
 
 	gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
 
-	/* Enable clock for GPIO port */
-	setbits_le32(&STM32_RCC->apb2enr, 0x04 << dsc->port);
-
 	if (p < 8) {
 		cr = &gpio_regs->crl;
 		crp = p;
@@ -230,7 +207,7 @@
 
 	dsc.port = stm32_gpio_to_port(gpio);
 	dsc.pin = stm32_gpio_to_pin(gpio);
-#if defined(CONFIG_STM32F4)
+#if defined(CONFIG_STM32F4) || defined(CONFIG_STM32F7)
 	ctl.af = STM32_GPIO_AF0;
 	ctl.mode = STM32_GPIO_MODE_IN;
 	ctl.otype = STM32_GPIO_OTYPE_PP;
@@ -256,7 +233,7 @@
 
 	dsc.port = stm32_gpio_to_port(gpio);
 	dsc.pin = stm32_gpio_to_pin(gpio);
-#if defined(CONFIG_STM32F4)
+#if defined(CONFIG_STM32F4) || defined(CONFIG_STM32F7)
 	ctl.af = STM32_GPIO_AF0;
 	ctl.mode = STM32_GPIO_MODE_OUT;
 	ctl.pupd = STM32_GPIO_PUPD_NO;
diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile
index a3c9f99..493cdc6 100644
--- a/drivers/net/fm/Makefile
+++ b/drivers/net/fm/Makefile
@@ -6,6 +6,7 @@
 
 obj-y += dtsec.o
 obj-y += eth.o
+obj-y += fdt.o
 obj-y += fm.o
 obj-y += init.o
 obj-y += tgec.o
diff --git a/drivers/net/fm/fdt.c b/drivers/net/fm/fdt.c
new file mode 100644
index 0000000..9918d80
--- /dev/null
+++ b/drivers/net/fm/fdt.c
@@ -0,0 +1,129 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <asm/io.h>
+#include <fsl_qe.h>	/* For struct qe_firmware */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+/**
+ * fdt_fixup_fman_firmware -- insert the Fman firmware into the device tree
+ *
+ * The binding for an Fman firmware node is documented in
+ * Documentation/powerpc/dts-bindings/fsl/dpaa/fman.txt.  This node contains
+ * the actual Fman firmware binary data.  The operating system is expected to
+ * be able to parse the binary data to determine any attributes it needs.
+ */
+void fdt_fixup_fman_firmware(void *blob)
+{
+	int rc, fmnode, fwnode = -1;
+	uint32_t phandle;
+	struct qe_firmware *fmanfw;
+	const struct qe_header *hdr;
+	unsigned int length;
+	uint32_t crc;
+	const char *p;
+
+	/* The first Fman we find will contain the actual firmware. */
+	fmnode = fdt_node_offset_by_compatible(blob, -1, "fsl,fman");
+	if (fmnode < 0)
+		/* Exit silently if there are no Fman devices */
+		return;
+
+	/* If we already have a firmware node, then also exit silently. */
+	if (fdt_node_offset_by_compatible(blob, -1, "fsl,fman-firmware") > 0)
+		return;
+
+	/* If the environment variable is not set, then exit silently */
+	p = getenv("fman_ucode");
+	if (!p)
+		return;
+
+	fmanfw = (struct qe_firmware *)simple_strtoul(p, NULL, 16);
+	if (!fmanfw)
+		return;
+
+	hdr = &fmanfw->header;
+	length = fdt32_to_cpu(hdr->length);
+
+	/* Verify the firmware. */
+	if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
+	    (hdr->magic[2] != 'F')) {
+		printf("Data at %p is not an Fman firmware\n", fmanfw);
+		return;
+	}
+
+	if (length > CONFIG_SYS_QE_FMAN_FW_LENGTH) {
+		printf("Fman firmware at %p is too large (size=%u)\n",
+		       fmanfw, length);
+		return;
+	}
+
+	length -= sizeof(u32);	/* Subtract the size of the CRC */
+	crc = fdt32_to_cpu(*(u32 *)((void *)fmanfw + length));
+	if (crc != crc32_no_comp(0, (void *)fmanfw, length)) {
+		printf("Fman firmware at %p has invalid CRC\n", fmanfw);
+		return;
+	}
+
+	length += sizeof(u32);
+
+	/* Increase the size of the fdt to make room for the node. */
+	rc = fdt_increase_size(blob, length);
+	if (rc < 0) {
+		printf("Unable to make room for Fman firmware: %s\n",
+		       fdt_strerror(rc));
+		return;
+	}
+
+	/* Create the firmware node. */
+	fwnode = fdt_add_subnode(blob, fmnode, "fman-firmware");
+	if (fwnode < 0) {
+		char s[64];
+		fdt_get_path(blob, fmnode, s, sizeof(s));
+		printf("Could not add firmware node to %s: %s\n", s,
+		       fdt_strerror(fwnode));
+		return;
+	}
+	rc = fdt_setprop_string(blob, fwnode, "compatible",
+					"fsl,fman-firmware");
+	if (rc < 0) {
+		char s[64];
+		fdt_get_path(blob, fwnode, s, sizeof(s));
+		printf("Could not add compatible property to node %s: %s\n", s,
+		       fdt_strerror(rc));
+		return;
+	}
+	phandle = fdt_create_phandle(blob, fwnode);
+	if (!phandle) {
+		char s[64];
+		fdt_get_path(blob, fwnode, s, sizeof(s));
+		printf("Could not add phandle property to node %s: %s\n", s,
+		       fdt_strerror(rc));
+		return;
+	}
+	rc = fdt_setprop(blob, fwnode, "fsl,firmware", fmanfw, length);
+	if (rc < 0) {
+		char s[64];
+		fdt_get_path(blob, fwnode, s, sizeof(s));
+		printf("Could not add firmware property to node %s: %s\n", s,
+		       fdt_strerror(rc));
+		return;
+	}
+
+	/* Find all other Fman nodes and point them to the firmware node. */
+	while ((fmnode = fdt_node_offset_by_compatible(blob, fmnode,
+		"fsl,fman")) > 0) {
+		rc = fdt_setprop_cell(blob, fmnode, "fsl,firmware-phandle",
+				      phandle);
+		if (rc < 0) {
+			char s[64];
+			fdt_get_path(blob, fmnode, s, sizeof(s));
+			printf("Could not add pointer property to node %s: %s\n",
+			       s, fdt_strerror(rc));
+			return;
+		}
+	}
+}
+#endif
diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index 40fbf19..e2a8ed3 100644
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c
@@ -10,7 +10,7 @@
 #include <asm/errno.h>
 
 #include "fm.h"
-#include "../../qe/qe.h"		/* For struct qe_firmware */
+#include <fsl_qe.h>		/* For struct qe_firmware */
 
 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #include <nand.h>
diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
index d5bf6f4..9eb605b 100644
--- a/drivers/pci/pci_rom.c
+++ b/drivers/pci/pci_rom.c
@@ -266,7 +266,7 @@
 			int exec_method)
 {
 	struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
-	struct pci_rom_header *rom, *ram = NULL;
+	struct pci_rom_header *rom = NULL, *ram = NULL;
 	int vesa_mode = -1;
 	bool emulate, alloced;
 	int ret;
diff --git a/drivers/power/pmic/pmic_tps65218.c b/drivers/power/pmic/pmic_tps65218.c
index dbc7a73..0fd0ad4 100644
--- a/drivers/power/pmic/pmic_tps65218.c
+++ b/drivers/power/pmic/pmic_tps65218.c
@@ -11,6 +11,20 @@
 #include <power/pmic.h>
 #include <power/tps65218.h>
 
+int tps65218_reg_read(uchar dest_reg, uchar *dest_val)
+{
+	uchar read_val;
+	int ret;
+
+	ret = i2c_read(TPS65218_CHIP_PM, dest_reg, 1, &read_val, 1);
+	if (ret)
+		return ret;
+
+	*dest_val = read_val;
+
+	return 0;
+}
+
 /**
  *  tps65218_reg_write() - Generic function that can write a TPS65218 PMIC
  *			   register or bit field regardless of protection
@@ -98,6 +112,48 @@
 	return 0;
 }
 
+/**
+ * tps65218_toggle_fseal() - Perform the sequence that toggles the FSEAL bit.
+ *
+ * @return:		     0 on success, -EBADE if the sequence was broken
+ */
+int tps65218_toggle_fseal(void)
+{
+	if (tps65218_reg_write(TPS65218_PROT_LEVEL_NONE, TPS65218_PASSWORD,
+			       0xb1, TPS65218_MASK_ALL_BITS))
+		return -EBADE;
+
+	if (tps65218_reg_write(TPS65218_PROT_LEVEL_NONE, TPS65218_PASSWORD,
+			       0xfe, TPS65218_MASK_ALL_BITS))
+		return -EBADE;
+
+	if (tps65218_reg_write(TPS65218_PROT_LEVEL_NONE, TPS65218_PASSWORD,
+			       0xa3, TPS65218_MASK_ALL_BITS))
+		return -EBADE;
+
+	return 0;
+}
+
+/**
+ * tps65218_lock_fseal() - Perform the sequence that locks the FSEAL bit to 1.
+ *
+ * The FSEAL bit prevents the PMIC from turning off DCDC5 and DCDC6. It can be
+ * toggled at most 3 times: 0->1, 1->0, and finally 0->1. After the third switch
+ * its value is locked and can only be reset by powering off the PMIC entirely.
+ *
+ * @return:		   0 on success, -EBADE if the sequence was broken
+ */
+int tps65218_lock_fseal(void)
+{
+	int i;
+
+	for (i = 0; i < 3; i++)
+		if (tps65218_toggle_fseal())
+			return -EBADE;
+
+	return 0;
+}
+
 int power_tps65218_init(unsigned char bus)
 {
 	static const char name[] = "TPS65218_PMIC";
diff --git a/drivers/qe/fdt.c b/drivers/qe/fdt.c
index dfae4bf..4f48f98 100644
--- a/drivers/qe/fdt.c
+++ b/drivers/qe/fdt.c
@@ -10,7 +10,7 @@
 #include <common.h>
 #include <libfdt.h>
 #include <fdt_support.h>
-#include "qe.h"
+#include <fsl_qe.h>
 
 #ifdef CONFIG_QE
 DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 08620b2..2b98984 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -12,7 +12,7 @@
 #include "asm/errno.h"
 #include "asm/io.h"
 #include "linux/immap_qe.h"
-#include "qe.h"
+#include <fsl_qe.h>
 #ifdef CONFIG_LS102XA
 #include <asm/arch/immap_ls102xa.h>
 #endif
@@ -20,7 +20,9 @@
 #define MPC85xx_DEVDISR_QE_DISABLE	0x1
 
 qe_map_t		*qe_immr = NULL;
+#ifdef CONFIG_QE
 static qe_snum_t	snums[QE_NUM_OF_SNUM];
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -81,6 +83,7 @@
 	return (void *)&qe_immr->muram[offset];
 }
 
+#ifdef CONFIG_QE
 static void qe_sdma_init(void)
 {
 	volatile sdma_t	*p;
@@ -184,12 +187,12 @@
 	qe_sdma_init();
 	qe_snums_init();
 }
+#endif
 
 #ifdef CONFIG_U_QE
 void u_qe_init(void)
 {
-	uint qe_base = CONFIG_SYS_IMMR + 0x01400000; /* QE immr base */
-	qe_immr = (qe_map_t *)qe_base;
+	qe_immr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET);
 
 	u_qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR);
 	out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
@@ -200,9 +203,8 @@
 void u_qe_resume(void)
 {
 	qe_map_t *qe_immrr;
-	uint qe_base = CONFIG_SYS_IMMR + QE_IMMR_OFFSET; /* QE immr base */
-	qe_immrr = (qe_map_t *)qe_base;
 
+	qe_immrr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET);
 	u_qe_firmware_resume((const void *)CONFIG_SYS_QE_FW_ADDR, qe_immrr);
 	out_be32(&qe_immrr->iram.iready, QE_IRAM_READY);
 }
@@ -214,6 +216,7 @@
 			 (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
 }
 
+#ifdef CONFIG_QE
 void qe_assign_page(uint snum, uint para_ram_base)
 {
 	u32	cecr;
@@ -229,6 +232,7 @@
 
 	return;
 }
+#endif
 
 /*
  * brg: 0~15 as BRG1~BRG16
diff --git a/drivers/qe/uccf.c b/drivers/qe/uccf.c
index 85386bf..e011886 100644
--- a/drivers/qe/uccf.c
+++ b/drivers/qe/uccf.c
@@ -12,8 +12,8 @@
 #include "asm/errno.h"
 #include "asm/io.h"
 #include "linux/immap_qe.h"
-#include "qe.h"
 #include "uccf.h"
+#include <fsl_qe.h>
 
 void ucc_fast_transmit_on_demand(ucc_fast_private_t *uccf)
 {
diff --git a/drivers/qe/uccf.h b/drivers/qe/uccf.h
index 55941e4..aa817e7 100644
--- a/drivers/qe/uccf.h
+++ b/drivers/qe/uccf.h
@@ -11,8 +11,8 @@
 #define __UCCF_H__
 
 #include "common.h"
-#include "qe.h"
 #include "linux/immap_qe.h"
+#include <fsl_qe.h>
 
 /* Fast or Giga ethernet
 */
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index e0ab04a..40cccc2 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -12,11 +12,11 @@
 #include "asm/errno.h"
 #include "asm/io.h"
 #include "linux/immap_qe.h"
-#include "qe.h"
 #include "uccf.h"
 #include "uec.h"
 #include "uec_phy.h"
 #include "miiphy.h"
+#include <fsl_qe.h>
 #include <phy.h>
 
 /* Default UTBIPAR SMI address */
diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h
index 6b559f7..22e248f 100644
--- a/drivers/qe/uec.h
+++ b/drivers/qe/uec.h
@@ -10,8 +10,8 @@
 #ifndef __UEC_H__
 #define __UEC_H__
 
-#include "qe.h"
 #include "uccf.h"
+#include <fsl_qe.h>
 #include <phy.h>
 
 #define MAX_TX_THREADS				8
diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c
index e701787..272874d 100644
--- a/drivers/qe/uec_phy.c
+++ b/drivers/qe/uec_phy.c
@@ -16,11 +16,11 @@
 #include "asm/errno.h"
 #include "linux/immap_qe.h"
 #include "asm/io.h"
-#include "qe.h"
 #include "uccf.h"
 #include "uec.h"
 #include "uec_phy.h"
 #include "miiphy.h"
+#include <fsl_qe.h>
 #include <phy.h>
 
 #define ugphy_printk(format, arg...)  \
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index c63999a..05bdf56 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -37,6 +37,7 @@
 obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
 obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o
 obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o
+obj-$(CONFIG_STM32X7_SERIAL) += serial_stm32x7.o
 
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/serial_stm32x7.c b/drivers/serial/serial_stm32x7.c
new file mode 100644
index 0000000..cfbfab7
--- /dev/null
+++ b/drivers/serial/serial_stm32x7.c
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2016
+ * Vikas Manocha, <vikas.manocha@st.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <serial.h>
+#include <dm/platform_data/serial_stm32x7.h>
+#include "serial_stm32x7.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
+{
+	struct stm32x7_serial_platdata *plat = dev->platdata;
+	struct stm32_usart *const usart = plat->base;
+	writel(plat->clock/baudrate, &usart->brr);
+
+	return 0;
+}
+
+static int stm32_serial_getc(struct udevice *dev)
+{
+	struct stm32x7_serial_platdata *plat = dev->platdata;
+	struct stm32_usart *const usart = plat->base;
+
+	if ((readl(&usart->sr) & USART_SR_FLAG_RXNE) == 0)
+		return -EAGAIN;
+
+	return readl(&usart->rd_dr);
+}
+
+static int stm32_serial_putc(struct udevice *dev, const char c)
+{
+	struct stm32x7_serial_platdata *plat = dev->platdata;
+	struct stm32_usart *const usart = plat->base;
+
+	if ((readl(&usart->sr) & USART_SR_FLAG_TXE) == 0)
+		return -EAGAIN;
+
+	writel(c, &usart->tx_dr);
+
+	return 0;
+}
+
+static int stm32_serial_pending(struct udevice *dev, bool input)
+{
+	struct stm32x7_serial_platdata *plat = dev->platdata;
+	struct stm32_usart *const usart = plat->base;
+
+	if (input)
+		return readl(&usart->sr) & USART_SR_FLAG_RXNE ? 1 : 0;
+	else
+		return readl(&usart->sr) & USART_SR_FLAG_TXE ? 0 : 1;
+}
+
+static int stm32_serial_probe(struct udevice *dev)
+{
+	struct stm32x7_serial_platdata *plat = dev->platdata;
+	struct stm32_usart *const usart = plat->base;
+	setbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE);
+
+	return 0;
+}
+
+static const struct dm_serial_ops stm32_serial_ops = {
+	.putc = stm32_serial_putc,
+	.pending = stm32_serial_pending,
+	.getc = stm32_serial_getc,
+	.setbrg = stm32_serial_setbrg,
+};
+
+U_BOOT_DRIVER(serial_stm32) = {
+	.name = "serial_stm32x7",
+	.id = UCLASS_SERIAL,
+	.ops = &stm32_serial_ops,
+	.probe = stm32_serial_probe,
+	.flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/serial/serial_stm32x7.h b/drivers/serial/serial_stm32x7.h
new file mode 100644
index 0000000..6190d67
--- /dev/null
+++ b/drivers/serial/serial_stm32x7.h
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2016
+ * Vikas Manocha, <vikas.manocha@st.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SERIAL_STM32_X7_
+#define _SERIAL_STM32_X7_
+
+struct stm32_usart {
+	u32 cr1;
+	u32 cr2;
+	u32 cr3;
+	u32 brr;
+	u32 gtpr;
+	u32 rtor;
+	u32 rqr;
+	u32 sr;
+	u32 icr;
+	u32 rd_dr;
+	u32 tx_dr;
+};
+
+
+#define USART_CR1_RE			(1 << 2)
+#define USART_CR1_TE			(1 << 3)
+#define USART_CR1_UE			(1 << 0)
+
+#define USART_SR_FLAG_RXNE		(1 << 5)
+#define USART_SR_FLAG_TXE		(1 << 7)
+
+#define USART_BRR_F_MASK		0xFF
+#define USART_BRR_M_SHIFT		4
+#define USART_BRR_M_MASK		0xFFF0
+
+#endif
diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h
index ffc6811..a94b1e2 100644
--- a/include/configs/bur_am335x_common.h
+++ b/include/configs/bur_am335x_common.h
@@ -3,7 +3,7 @@
  *
  * common parts used by B&R AM335x based boards
  *
- * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> -
+ * Copyright (C) 2016 Hannes Schmelzer <oe5hpm@oevsv.at> -
  * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
  *
  * SPDX-License-Identifier:        GPL-2.0+
@@ -12,25 +12,9 @@
 #ifndef __BUR_AM335X_COMMON_H__
 #define __BUR_AM335X_COMMON_H__
 /* ------------------------------------------------------------------------- */
-#define BUR_COMMON_ENV \
-"usbscript=usb start && fatload usb 0 0x80000000 usbscript.img && source\0" \
-"brdefaultip=if test -r ${ipaddr}; then; else" \
-" setenv ipaddr 192.168.60.1; setenv serverip 192.168.60.254;" \
-" setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0; fi;\0" \
-"netconsole=echo switching to network console ...; " \
-"if dhcp; then; else run brdefaultip; fi; setenv ncip ${serverip}; " \
-"setcurs 1 9; lcdputs myip; setcurs 10 9; lcdputs ${ipaddr};" \
-"setcurs 1 10;lcdputs serverip; setcurs 10 10; lcdputs ${serverip};" \
-"setenv stdout nc;setenv stdin nc;setenv stderr nc\0"
-
-#define CONFIG_PREBOOT			"run brdefaultip"
-#define CONFIG_CMD_TIME
-
-
 #define CONFIG_AM33XX
 #define CONFIG_OMAP
 #define CONFIG_OMAP_COMMON
-#define CONFIG_BOARD_LATE_INIT
 #define CONFIG_SYS_CACHELINE_SIZE	64
 #define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
 
@@ -53,24 +37,11 @@
 #define CONFIG_BAUDRATE			115200
 
 /* Network defines */
-#define CONFIG_CMD_DHCP
-#define CONFIG_BOOTP_DNS		/* Configurable parts of CMD_DHCP */
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_NET_RETRY_COUNT		2
-#define CONFIG_CMD_PING
 #define CONFIG_DRIVER_TI_CPSW		/* Driver for IP block */
 #define CONFIG_MII			/* Required in net/eth.c */
-#define CONFIG_SPL_ETH_SUPPORT
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_NATSEMI
-#define CONFIG_SPL_NET_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT		/* used for a fetching MAC-Address */
-#define CONFIG_SPL_NET_VCI_STRING	"AM335x U-Boot SPL"
-/* Network console */
-#define CONFIG_NETCONSOLE			1
-#define CONFIG_BOOTP_MAY_FAIL		/* if we don't have DHCP environment */
+
 /*
  * SPL related defines.  The Public RAM memory map the ROM defines the
  * area between 0x402F0400 and 0x4030B800 as a download area and
@@ -109,42 +80,8 @@
 #define CONFIG_SYS_OMAP24_I2C_SPEED	100000
 #define CONFIG_SYS_OMAP24_I2C_SLAVE	1
 #define CONFIG_SYS_I2C_OMAP24XX
-#define CONFIG_CMD_I2C
 /* GPIO */
 #define CONFIG_OMAP_GPIO
-/*
- * ----------------------------------------------------------------------------
- * The following are general good-enough settings for U-Boot.  We set a
- * large malloc pool as we generally have a lot of DDR, and we opt for
- * function over binary size in the main portion of U-Boot as this is
- * generally easily constrained later if needed.  We enable the config
- * options that give us information in the environment about what board
- * we are on so we do not need to rely on the command prompt.  We set a
- * console baudrate of 115200 and use the default baud rate table.
- */
-#define CONFIG_SYS_MALLOC_LEN		(5120 << 10)
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-#define CONFIG_ENV_OVERWRITE		/* Overwrite ethaddr / serial# */
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-
-/* As stated above, the following choices are optional. */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_VERSION_VARIABLE
-
-/* We set the max number of command args high to avoid HUSH bugs. */
-#define CONFIG_SYS_MAXARGS		64
-
-/* Console I/O Buffer Size */
-#define CONFIG_SYS_CBSIZE		512
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE +\
-					sizeof(CONFIG_SYS_PROMPT) + 16)
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 
 /*
  * Our platforms make use of SPL to initalize the hardware (primarily
diff --git a/include/configs/bur_cfg_common.h b/include/configs/bur_cfg_common.h
new file mode 100644
index 0000000..f183775
--- /dev/null
+++ b/include/configs/bur_cfg_common.h
@@ -0,0 +1,64 @@
+/*
+ * bur_cfg_common.h
+ *
+ * common parts used over all B&R boards
+ *
+ * Copyright (C) 2016 Hannes Schmelzer <oe5hpm@oevsv.at> -
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier:        GPL-2.0+
+ */
+
+#ifndef __BUR_CFG_COMMON_H__
+#define __BUR_CFG_COMMON_H__
+/* ------------------------------------------------------------------------- */
+#define BUR_COMMON_ENV \
+"usbscript=usb start && fatload usb 0 ${scradr} usbscript.img &&" \
+" source ${scradr}\0" \
+"brdefaultip=if test -r ${ipaddr}; then; else" \
+" setenv ipaddr 192.168.60.1; setenv serverip 192.168.60.254;" \
+" setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0; fi;\0" \
+"netconsole=echo switching to network console ...; " \
+"if dhcp; then; else run brdefaultip; fi; setenv ncip ${serverip}; " \
+"setcurs 1 9; lcdputs myip; setcurs 10 9; lcdputs ${ipaddr};" \
+"setcurs 1 10;lcdputs serverip; setcurs 10 10; lcdputs ${serverip};" \
+"setenv stdout nc;setenv stdin nc;setenv stderr nc\0"
+
+#define CONFIG_PREBOOT			"run cfgscr; run brdefaultip"
+
+#define CONFIG_BOARD_LATE_INIT
+
+/* Network defines */
+#define CONFIG_BOOTP_DNS		/* Configurable parts of CMD_DHCP */
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_NET_RETRY_COUNT		2
+
+/* Network console */
+#define CONFIG_NETCONSOLE		1
+#define CONFIG_BOOTP_MAY_FAIL		/* if we don't have DHCP environment */
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_ENV_OVERWRITE		/* Overwrite ethaddr / serial# */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+
+/* As stated above, the following choices are optional. */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_VERSION_VARIABLE
+
+/* We set the max number of command args high to avoid HUSH bugs. */
+#define CONFIG_SYS_MAXARGS		64
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		512
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE +\
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#endif	/* __BUR_CFG_COMMON_H__ */
diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h
index d3cd38d..1c1951c 100644
--- a/include/configs/cm_t43.h
+++ b/include/configs/cm_t43.h
@@ -18,10 +18,12 @@
 #include <asm/arch/omap.h>
 
 /* Serial support */
-#define CONFIG_DM_SERIAL
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_CLK		48000000
 #define CONFIG_SYS_NS16550_COM1		0x44e09000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#endif
 
 /* NAND support */
 #define CONFIG_NAND
@@ -68,9 +70,7 @@
 #define CONFIG_AM437X_USB2PHY2_HOST
 
 /* SPI Flash support */
-#define CONFIG_SPI_FLASH
 #define CONFIG_TI_SPI_MMAP
-#define CONFIG_SPI_FLASH_BAR
 #define CONFIG_SF_DEFAULT_SPEED		48000000
 #define CONFIG_DEFAULT_SPI_MODE		SPI_MODE_3
 
@@ -98,9 +98,8 @@
 #undef CONFIG_SPL_OS_BOOT
 #undef CONFIG_SPL_GPIO_SUPPORT
 #undef CONFIG_SPL_NAND_SUPPORT
-#undef CONFIG_SPL_BOARD_INIT
-#undef CONFIG_BOOTDELAY
-#include <config_distro_defaults.h>
+#undef CONFIG_SYS_MONITOR_LEN
+#undef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
 #define CONFIG_ZERO_BOOTDELAY_CHECK
 #undef CONFIG_CMD_IMLS
 
@@ -165,8 +164,12 @@
 #define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_SDRAM_BASE + (128 << 20))
 #define CONFIG_SPL_POWER_SUPPORT
 #define CONFIG_SYS_SPI_U_BOOT_OFFS	(256 * 1024)
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x480
 #define CONFIG_SPL_SPI_SUPPORT
 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 #define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_POWER_SUPPORT
 
 #endif	/* __CONFIG_CM_T43_H */
diff --git a/include/configs/kwb.h b/include/configs/kwb.h
index 45253b8..60e6496 100644
--- a/include/configs/kwb.h
+++ b/include/configs/kwb.h
@@ -12,6 +12,7 @@
 #ifndef __CONFIG_KWB_H__
 #define __CONFIG_KWB_H__
 
+#include <configs/bur_cfg_common.h>
 #include <configs/bur_am335x_common.h>
 /* ------------------------------------------------------------------------- */
 #define CONFIG_AM335X_LCD
@@ -27,6 +28,9 @@
 #define CONFIG_BMP_24BMP
 #define CONFIG_BMP_32BPP
 
+/* memory */
+#define CONFIG_SYS_MALLOC_LEN		(5 * 1024 * 1024)
+
 /* Clock Defines */
 #define V_OSCK				26000000  /* Clock output from T2 */
 #define V_SCLK				(V_OSCK)
@@ -103,10 +107,9 @@
 #define CONFIG_BOOTDELAY		0
 
 /* undefine command which we not need here */
-#undef	CONFIG_BOOTM_NETBSD
-#undef	CONFIG_BOOTM_PLAN9
-#undef	CONFIG_BOOTM_RTEMS
-#undef CONFIG_CMD_CRC32
+#undef CONFIG_BOOTM_NETBSD
+#undef CONFIG_BOOTM_PLAN9
+#undef CONFIG_BOOTM_RTEMS
 
 /* Support both device trees and ATAGs. */
 #define CONFIG_OF_LIBFDT
@@ -122,17 +125,11 @@
 #define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
 /* attention! not only for gadget, enables also highspeed in hostmode */
 #define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_MUSB_HOST
 #define CONFIG_AM335X_USB0
 #define CONFIG_AM335X_USB0_MODE	MUSB_HOST
 #define CONFIG_AM335X_USB1
 #define CONFIG_AM335X_USB1_MODE	MUSB_HOST
 
-#ifdef CONFIG_USB_MUSB_HOST
-#define CONFIG_CMD_USB
-#define CONFIG_USB_STORAGE
-#endif /* CONFIG_USB_MUSB_HOST */
-
 #undef CONFIG_ENV_IS_NOWHERE
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV		0
@@ -151,4 +148,4 @@
 #define CONFIG_CMD_FS_GENERIC
 #endif /* CONFIG_MMC, ... */
 
-#endif	/* ! __CONFIG_TSERIES_H__ */
+#endif	/* __CONFIG_KWB_H__ */
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index f6efc55..39d747f 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -42,7 +42,7 @@
 unsigned long get_board_ddr_clk(void);
 #endif
 
-#ifdef CONFIG_QSPI_BOOT
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 #define CONFIG_SYS_CLK_FREQ		100000000
 #define CONFIG_DDR_CLK_FREQ		100000000
 #define CONFIG_QIXIS_I2C_ACCESS
@@ -56,7 +56,13 @@
 #endif
 
 #ifdef CONFIG_SD_BOOT
-#define CONFIG_SYS_FSL_PBL_RCW	board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg
+#ifdef CONFIG_SD_BOOT_QSPI
+#define CONFIG_SYS_FSL_PBL_RCW	\
+	board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
+#else
+#define CONFIG_SYS_FSL_PBL_RCW	\
+	board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
+#endif
 #define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_LDSCRIPT	"arch/$(ARCH)/cpu/u-boot-spl.lds"
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
@@ -87,6 +93,9 @@
 
 #ifdef CONFIG_QSPI_BOOT
 #define CONFIG_SYS_TEXT_BASE		0x40010000
+#endif
+
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 #define CONFIG_SYS_NO_FLASH
 #endif
 
@@ -162,7 +171,7 @@
 /*
  * IFC Definitions
  */
-#ifndef CONFIG_QSPI_BOOT
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 #define CONFIG_FSL_IFC
 #define CONFIG_SYS_FLASH_BASE		0x60000000
 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
@@ -375,7 +384,9 @@
 #else
 #define CONFIG_CONS_INDEX		1
 #define CONFIG_SYS_NS16550_SERIAL
+#ifndef CONFIG_DM_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
+#endif
 #define CONFIG_SYS_NS16550_CLK		get_serial_clock()
 #endif
 
@@ -410,7 +421,7 @@
 #define CONFIG_DOS_PARTITION
 
 /* SPI */
-#ifdef CONFIG_QSPI_BOOT
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 /* QSPI */
 #define QSPI0_AMBA_BASE			0x40000000
 #define FSL_QSPI_FLASH_SIZE		(1 << 24)
@@ -555,6 +566,10 @@
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_CMDLINE_EDITING
 
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#undef CONFIG_CMD_IMLS
+#endif
+
 #define CONFIG_ARMV7_NONSEC
 #define CONFIG_ARMV7_VIRT
 #define CONFIG_PEN_ADDR_BIG_ENDIAN
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index 4ab8e13..158cf02 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -379,6 +379,19 @@
 #endif
 #endif
 
+/* USB */
+#define CONFIG_HAS_FSL_XHCI_USB
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_MAX_CONTROLLER_COUNT		3
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_EXT2
+#endif
+
 /*
  * Miscellaneous configurable options
  */
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index 506f50d..bc40b06 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -268,6 +268,13 @@
 #define CONFIG_ETHPRIME			"FM1@DTSEC3"
 #endif
 
+/* QE */
+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
+	!defined(CONFIG_QSPI_BOOT)
+#define CONFIG_U_QE
+#endif
+#define CONFIG_SYS_QE_FW_ADDR     0x60600000
+
 /* USB */
 #define CONFIG_HAS_FSL_XHCI_USB
 #ifdef CONFIG_HAS_FSL_XHCI_USB
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index def0a6f..64b82e8 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -264,14 +264,17 @@
 	"kernel_start=0x581200000\0"		\
 	"kernel_load=0xa0000000\0"		\
 	"kernel_size=0x2800000\0"		\
-	"console=ttyAMA0,38400n8\0"
+	"console=ttyAMA0,38400n8\0"		\
+	"mcinitcmd=fsl_mc start mc 0x580300000"	\
+	" 0x580800000 \0"
 
 #define CONFIG_BOOTARGS		"console=ttyS0,115200 root=/dev/ram0 " \
 				"earlycon=uart8250,mmio,0x21c0500" \
 				"ramdisk_size=0x2000000 default_hugepagesz=2m" \
-				" hugepagesz=2m hugepages=16"
-#define CONFIG_BOOTCOMMAND		"cp.b $kernel_start $kernel_load "     \
-					"$kernel_size && bootm $kernel_load"
+				" hugepagesz=2m hugepages=256"
+#define CONFIG_BOOTCOMMAND	"fsl_mc apply dpl 0x580700000 &&" \
+				" cp.b $kernel_start $kernel_load" \
+				" $kernel_size && bootm $kernel_load"
 #define CONFIG_BOOTDELAY		10
 
 /* Monitor Command Prompt */
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index a402c06..dab3820 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -346,7 +346,9 @@
 	"initrd_high=0xffffffffffffffff\0"	\
 	"kernel_start=0x581100000\0"		\
 	"kernel_load=0xa0000000\0"		\
-	"kernel_size=0x2800000\0"
+	"kernel_size=0x2800000\0"		\
+	"mcinitcmd=fsl_mc start mc 0x580300000"	\
+	" 0x580800000 \0"
 
 #ifdef CONFIG_FSL_MC_ENET
 #define CONFIG_FSL_MEMAC
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index 116dbcd..b2c0181 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -327,13 +327,15 @@
 	"initrd_high=0xffffffffffffffff\0"	\
 	"kernel_start=0x581100000\0"		\
 	"kernel_load=0xa0000000\0"		\
-	"kernel_size=0x2800000\0"
+	"kernel_size=0x2800000\0"		\
+	"mcinitcmd=fsl_mc start mc 0x580300000"	\
+	" 0x580800000 \0"
 
 #undef CONFIG_BOOTARGS
 #define CONFIG_BOOTARGS		"console=ttyS1,115200 root=/dev/ram0 " \
 				"earlycon=uart8250,mmio,0x21c0600" \
 				"ramdisk_size=0x2000000 default_hugepagesz=2m" \
-				" hugepagesz=2m hugepages=16"
+				" hugepagesz=2m hugepages=256"
 
 /* MAC/PHY configuration */
 #ifdef CONFIG_FSL_MC_ENET
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
index fba2a12..0fc9d1c 100644
--- a/include/configs/omap3_logic.h
+++ b/include/configs/omap3_logic.h
@@ -40,7 +40,7 @@
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
-
+#define CONFIG_BOARD_LATE_INIT
 #define CONFIG_MISC_INIT_R		/* misc_init_r dumps the die id */
 #define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
 #define CONFIG_SETUP_MEMORY_TAGS
diff --git a/include/configs/rpi-common.h b/include/configs/rpi-common.h
index 97e5d2c..e07fa65 100644
--- a/include/configs/rpi-common.h
+++ b/include/configs/rpi-common.h
@@ -68,6 +68,7 @@
 #define CONFIG_FB_ADDR			0
 #define CONFIG_VIDEO_BCM2835
 #define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_CONSOLE_SCROLL_LINES	10
 
 /* SD/MMC configuration */
 #define CONFIG_GENERIC_MMC
diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h
new file mode 100644
index 0000000..e1b8bcb
--- /dev/null
+++ b/include/configs/stm32f746-disco.h
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2016
+ * Vikas Manocha, <vikas.manocha@st.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_THUMB_BUILD
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_SYS_FLASH_BASE		0x08000000
+#define CONFIG_SYS_INIT_SP_ADDR		0x20050000
+#define CONFIG_SYS_TEXT_BASE		0x08000000
+
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
+
+/*
+ * Configuration of the external SDRAM memory
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_RAM_SIZE		((64 + 192) << 10)
+#define CONFIG_SYS_RAM_CS		1
+#define CONFIG_SYS_RAM_FREQ_DIV		2
+#define CONFIG_SYS_RAM_BASE		0x20000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_RAM_BASE
+#define CONFIG_SYS_LOAD_ADDR		0x20000000
+#define CONFIG_LOADADDR			0x20000000
+
+#define CONFIG_SYS_MAX_FLASH_SECT	12
+#define CONFIG_SYS_MAX_FLASH_BANKS	2
+
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_IN_FLASH
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+#define CONFIG_ENV_SIZE			(8 << 10)
+
+#define CONFIG_STM32_GPIO
+#define CONFIG_STM32X7_SERIAL
+
+#define CONFIG_SYS_CLK_FREQ		16*1000*1000 /* 180 MHz */
+#define CONFIG_SYS_HZ_CLOCK		1000000	/* Timer is clocked at 1MHz */
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_SYS_CBSIZE		1024
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE \
+					+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_MALLOC_LEN		(16 * 1024)
+#define CONFIG_STACKSIZE		(64 << 10)
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
+#define CONFIG_BOOTCOMMAND						\
+	"run bootcmd_romfs"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \
+	"bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \
+	"bootm 0x08044000 - 0x08042000\0"
+
+#define CONFIG_BOOTDELAY		3
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_CMD_MEM
+#define CONFIG_CMD_TIMER
+#undef CONFIG_CMD_IMLS
+#endif /* __CONFIG_H */
diff --git a/include/configs/tseries.h b/include/configs/tseries.h
index 93e3454..43cf965 100644
--- a/include/configs/tseries.h
+++ b/include/configs/tseries.h
@@ -12,6 +12,7 @@
 #ifndef __CONFIG_TSERIES_H__
 #define __CONFIG_TSERIES_H__
 
+#include <configs/bur_cfg_common.h>
 #include <configs/bur_am335x_common.h>
 /* ------------------------------------------------------------------------- */
 #define CONFIG_AM335X_LCD
@@ -30,6 +31,10 @@
 #define CONFIG_SYS_BOOTCOUNT_ADDR	0x44E3E000
 #define CONFIG_BOOTCOUNT_LIMIT
 #define CONFIG_BOOTCOUNT_AM33XX
+
+/* memory */
+#define CONFIG_SYS_MALLOC_LEN		(5 * 1024 * 1024)
+
 /* Clock Defines */
 #define V_OSCK				26000000  /* Clock output from T2 */
 #define V_SCLK				(V_OSCK)
@@ -204,7 +209,6 @@
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_SYS_NAND_BASE		0x8000000
 #define CONFIG_NAND_OMAP_GPMC
-#define CONFIG_CMD_NAND
 /* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */
 #define CONFIG_NAND_OMAP_ELM
 #define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
@@ -249,23 +253,15 @@
 #define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
 /* attention! not only for gadget, enables also highspeed in hostmode */
 #define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_MUSB_HOST
 #define CONFIG_AM335X_USB0
 #define CONFIG_AM335X_USB0_MODE	MUSB_HOST
 #define CONFIG_AM335X_USB1
 #define CONFIG_AM335X_USB1_MODE MUSB_HOST
 
-#ifdef CONFIG_USB_MUSB_HOST
-#define CONFIG_CMD_USB
-#define CONFIG_USB_STORAGE
-#endif /* CONFIG_USB_MUSB_HOST */
-
 #if defined(CONFIG_SPI_BOOT)
 /* McSPI IP block */
 #define CONFIG_SPI
 #define CONFIG_OMAP3_SPI
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_SPEED		24000000
 
 #define CONFIG_SPL_SPI_SUPPORT
diff --git a/include/dm/platform_data/serial_stm32x7.h b/include/dm/platform_data/serial_stm32x7.h
new file mode 100644
index 0000000..328a8a3
--- /dev/null
+++ b/include/dm/platform_data/serial_stm32x7.h
@@ -0,0 +1,17 @@
+/*
+ * (C) Copyright 2016
+ * Vikas Manocha, <vikas.manocha@st.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __SERIAL_STM32x7_H
+#define __SERIAL_STM32x7_H
+
+/* Information about a serial port */
+struct stm32x7_serial_platdata {
+	struct stm32_usart *base;  /* address of registers in physical memory */
+	unsigned int clock;
+};
+
+#endif /* __SERIAL_STM32x7_H */
diff --git a/include/fsl_fman.h b/include/fsl_fman.h
index 4d04415..f3e35f8 100644
--- a/include/fsl_fman.h
+++ b/include/fsl_fman.h
@@ -460,4 +460,5 @@
 	u8			res5[4*1024];
 } ccsr_fman_t;
 
+void fdt_fixup_fman_firmware(void *blob);
 #endif /*__FSL_FMAN_H__*/
diff --git a/drivers/qe/qe.h b/include/fsl_qe.h
similarity index 100%
rename from drivers/qe/qe.h
rename to include/fsl_qe.h
diff --git a/include/power/tps65218.h b/include/power/tps65218.h
index 63fc7b3..4d68faa 100644
--- a/include/power/tps65218.h
+++ b/include/power/tps65218.h
@@ -8,6 +8,8 @@
 #ifndef __POWER_TPS65218_H__
 #define __POWER_TPS65218_H__
 
+#include <linux/bitops.h>
+
 /* I2C chip address */
 #define TPS65218_CHIP_PM			0x24
 
@@ -60,8 +62,18 @@
 #define TPS65218_DCDC_VOLT_SEL_1260MV		0x29
 #define TPS65218_DCDC_VOLT_SEL_1330MV		0x30
 
+#define TPS65218_CC_STAT	(BIT(0) | BIT(1))
+#define TPS65218_STATE		(BIT(2) | BIT(3))
+#define TPS65218_PB_STATE	BIT(4)
+#define TPS65218_AC_STATE	BIT(5)
+#define TPS65218_EE		BIT(6)
+#define TPS65218_FSEAL		BIT(7)
+
+int tps65218_reg_read(uchar dest_reg, uchar *dest_val);
 int tps65218_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val,
 		       uchar mask);
 int tps65218_voltage_update(uchar dc_cntrl_reg, uchar volt_sel);
+int tps65218_toggle_fseal(void);
+int tps65218_lock_fseal(void);
 int power_tps65218_init(unsigned char bus);
 #endif	/* __POWER_TPS65218_H__ */
diff --git a/test/py/u_boot_console_base.py b/test/py/u_boot_console_base.py
index bc2bd76..d6502c6 100644
--- a/test/py/u_boot_console_base.py
+++ b/test/py/u_boot_console_base.py
@@ -303,8 +303,13 @@
             if not self.config.gdbserver:
                 self.p.timeout = 30000
             self.p.logfile_read = self.logstream
-            if self.config.buildconfig.get('config_spl', False) == 'y':
-                m = self.p.expect([pattern_u_boot_spl_signon] + self.bad_patterns)
+            bcfg = self.config.buildconfig
+            config_spl = bcfg.get('config_spl', 'n') == 'y'
+            config_spl_serial_support = bcfg.get('config_spl_serial_support',
+                                                 'n') == 'y'
+            if config_spl and config_spl_serial_support:
+                m = self.p.expect([pattern_u_boot_spl_signon] +
+                                  self.bad_patterns)
                 if m != 0:
                     raise Exception('Bad pattern found on console: ' +
                                     self.bad_pattern_ids[m - 1])
diff --git a/tools/Makefile b/tools/Makefile
index 1382b05..2881a7c 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -129,6 +129,14 @@
 ifneq ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_FIT_SIGNATURE),)
 HOSTLOADLIBES_mkimage += \
 	$(shell pkg-config --libs libssl libcrypto 2> /dev/null || echo "-lssl -lcrypto")
+
+# OS X deprecate openssl in favour of CommonCrypto, supress deprecation
+# warnings on those systems
+ifeq ($(HOSTOS),darwin)
+HOSTCFLAGS_mxsimage.o += -Wno-deprecated-declarations
+HOSTCFLAGS_image-sig.o += -Wno-deprecated-declarations
+HOSTCFLAGS_rsa-sign.o += -Wno-deprecated-declarations
+endif
 endif
 
 HOSTLOADLIBES_dumpimage := $(HOSTLOADLIBES_mkimage)
diff --git a/tools/buildman/README b/tools/buildman/README
index 66502af..6f41008 100644
--- a/tools/buildman/README
+++ b/tools/buildman/README
@@ -157,7 +157,7 @@
 x86: i386
 blackfin: bfin
 nds32: nds32le
-openrisc: or32
+openrisc: or1k
 
 
 This selects the available toolchain paths. Add the base directory for
@@ -362,6 +362,10 @@
 sh: http://sourcery.mentor.com/public/gnu_toolchain/sh-linux-gnu/
     renesas-4.4-200-sh-linux-gnu-i686-pc-linux-gnu.tar.bz2
 
+Note openrisc kernel.org toolchain is out of date, download latest one from
+http://opencores.org/or1k/OpenRISC_GNU_tool_chain#Prebuilt_versions, eg:
+ftp://ocuser:ocuser@openrisc.opencores.org/toolchain/gcc-or1k-elf-4.8.1-x86.tar.bz2.
+
 Buildman should now be set up to use your new toolchain.
 
 At the time of writing, U-Boot has these architectures:
diff --git a/tools/mkimage.c b/tools/mkimage.c
index 8f8b6df..facebcd 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -129,7 +129,7 @@
 			case 'a':
 				if (--argc <= 0)
 					usage ();
-				params.addr = strtoul (*++argv, &ptr, 16);
+				params.addr = strtoull(*++argv, &ptr, 16);
 				if (*ptr) {
 					fprintf (stderr,
 						"%s: invalid load address %s\n",
@@ -146,7 +146,7 @@
 			case 'e':
 				if (--argc <= 0)
 					usage ();
-				params.ep = strtoul (*++argv, &ptr, 16);
+				params.ep = strtoull(*++argv, &ptr, 16);
 				if (*ptr) {
 					fprintf (stderr,
 						"%s: invalid entry point %s\n",
diff --git a/tools/moveconfig.py b/tools/moveconfig.py
index 1b53f95..6f71b55 100755
--- a/tools/moveconfig.py
+++ b/tools/moveconfig.py
@@ -184,6 +184,9 @@
 # nds32: http://osdk.andestech.com/packages/nds32le-linux-glibc-v1.tgz
 # nios2: https://sourcery.mentor.com/GNUToolchain/subscription42545
 # sh: http://sourcery.mentor.com/public/gnu_toolchain/sh-linux-gnu
+#
+# openrisc kernel.org toolchain is out of date, download latest one from
+# http://opencores.org/or1k/OpenRISC_GNU_tool_chain#Prebuilt_versions
 CROSS_COMPILE = {
     'arc': 'arc-linux-',
     'aarch64': 'aarch64-linux-',
@@ -195,7 +198,7 @@
     'mips': 'mips-linux-',
     'nds32': 'nds32le-linux-',
     'nios2': 'nios2-linux-gnu-',
-    'openrisc': 'or32-linux-',
+    'openrisc': 'or1k-elf-',
     'powerpc': 'powerpc-linux-',
     'sh': 'sh-linux-gnu-',
     'sparc': 'sparc-linux-',