diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c
index 7637c9b..a133a5d 100644
--- a/arch/x86/cpu/mp_init.c
+++ b/arch/x86/cpu/mp_init.c
@@ -69,12 +69,12 @@
  * CPUS are numbered sequentially from 0 using the device tree:
  *
  *	cpus {
- *		u-boot,dm-pre-reloc;
+ *		bootph-all;
  *		#address-cells = <1>;
  *		#size-cells = <0>;
  *
  *		cpu@0 {
- *			u-boot,dm-pre-reloc;
+ *			bootph-all;
  *			device_type = "cpu";
  *			compatible = "intel,apl-cpu";
  *			reg = <0>;
diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index b92729d..b197e4b 100644
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -92,7 +92,7 @@
 		compatible = "pci-x86";
 		#address-cells = <3>;
 		#size-cells = <2>;
-		u-boot,dm-pre-reloc;
+		bootph-all;
 		ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
 			  0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
 			  0x01000000 0x0 0x2000 0x2000 0 0xe000>;
@@ -189,7 +189,7 @@
 
 			gpioa {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0 0x20>;
 				bank-name = "A";
 				use-lvl-write-cache;
@@ -197,7 +197,7 @@
 
 			gpiob {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0x20 0x20>;
 				bank-name = "B";
 				use-lvl-write-cache;
@@ -205,7 +205,7 @@
 
 			gpioc {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0x40 0x20>;
 				bank-name = "C";
 				use-lvl-write-cache;
@@ -213,7 +213,7 @@
 
 			gpiod {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0x60 0x20>;
 				bank-name = "D";
 				use-lvl-write-cache;
@@ -221,7 +221,7 @@
 
 			gpioe {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0x80 0x20>;
 				bank-name = "E";
 				use-lvl-write-cache;
@@ -229,7 +229,7 @@
 
 			gpiof {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0xA0 0x20>;
 				bank-name = "F";
 				use-lvl-write-cache;
diff --git a/arch/x86/dts/baytrail_som-db5800-som-6867.dts b/arch/x86/dts/baytrail_som-db5800-som-6867.dts
index e9b56de..4380dde 100644
--- a/arch/x86/dts/baytrail_som-db5800-som-6867.dts
+++ b/arch/x86/dts/baytrail_som-db5800-som-6867.dts
@@ -116,7 +116,7 @@
 		compatible = "intel,pci-baytrail", "pci-x86";
 		#address-cells = <3>;
 		#size-cells = <2>;
-		u-boot,dm-pre-reloc;
+		bootph-all;
 		ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
 			  0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
 			  0x01000000 0x0 0x2000 0x2000 0 0xe000>;
@@ -213,7 +213,7 @@
 
 			gpioa {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0 0x20>;
 				bank-name = "A";
 				use-lvl-write-cache;
@@ -221,7 +221,7 @@
 
 			gpiob {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0x20 0x20>;
 				bank-name = "B";
 				use-lvl-write-cache;
@@ -229,7 +229,7 @@
 
 			gpioc {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0x40 0x20>;
 				bank-name = "C";
 				use-lvl-write-cache;
@@ -237,7 +237,7 @@
 
 			gpiod {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0x60 0x20>;
 				bank-name = "D";
 				use-lvl-write-cache;
@@ -245,7 +245,7 @@
 
 			gpioe {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0x80 0x20>;
 				bank-name = "E";
 				use-lvl-write-cache;
@@ -253,7 +253,7 @@
 
 			gpiof {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0xA0 0x20>;
 				bank-name = "F";
 				use-lvl-write-cache;
diff --git a/arch/x86/dts/cherryhill.dts b/arch/x86/dts/cherryhill.dts
index 7a27367..3d35e46 100644
--- a/arch/x86/dts/cherryhill.dts
+++ b/arch/x86/dts/cherryhill.dts
@@ -70,7 +70,7 @@
 		compatible = "pci-x86";
 		#address-cells = <3>;
 		#size-cells = <2>;
-		u-boot,dm-pre-reloc;
+		bootph-all;
 		ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
 			  0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
 			  0x01000000 0x0 0x2000 0x2000 0 0xe000>;
diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts
index 69a1c1c..8bfb2c0 100644
--- a/arch/x86/dts/chromebook_coral.dts
+++ b/arch/x86/dts/chromebook_coral.dts
@@ -113,17 +113,17 @@
 	clk: clock {
 		compatible = "intel,apl-clk";
 		#clock-cells = <1>;
-		u-boot,dm-pre-proper;
+		bootph-some-ram;
 	};
 
 	cpus {
-		u-boot,dm-pre-proper;
+		bootph-some-ram;
 		#address-cells = <1>;
 		#size-cells = <0>;
 
 		cpu_0: cpu@0 {
-			u-boot,dm-pre-proper;
-			u-boot,dm-spl;
+			bootph-some-ram;
+			bootph-pre-ram;
 			device_type = "cpu";
 			compatible = "intel,apl-cpu";
 			reg = <0>;
@@ -154,7 +154,7 @@
 	};
 
 	acpi_gpe: general-purpose-events {
-		u-boot,dm-pre-proper;
+		bootph-some-ram;
 		reg = <IOMAP_ACPI_BASE IOMAP_ACPI_SIZE>;
 		compatible = "intel,acpi-gpe";
 		interrupt-controller;
@@ -174,14 +174,14 @@
 		compatible = "pci-x86";
 		#address-cells = <3>;
 		#size-cells = <2>;
-		u-boot,dm-pre-reloc;
+		bootph-all;
 		ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
 			0x42000000 0x0 0xb0000000 0xb0000000 0 0x10000000
 			0x01000000 0x0 0x1000 0x1000 0 0xefff>;
 		u-boot,skip-auto-config-until-reloc;
 
 		host_bridge: host-bridge@0,0 {
-			u-boot,dm-pre-reloc;
+			bootph-all;
 			reg = <0x00000000 0 0 0 0>;
 			compatible = "intel,apl-hostbridge";
 			pciex-region-size = <0x10000000>;
@@ -197,7 +197,7 @@
 			fsp_s: fsp-s {
 			};
 			fsp_m: fsp-m {
-				u-boot,dm-spl;
+				bootph-pre-ram;
 			};
 
 			nhlt {
@@ -206,20 +206,20 @@
 		};
 
 		punit@0,1 {
-			u-boot,dm-pre-proper;
-			u-boot,dm-spl;
+			bootph-some-ram;
+			bootph-pre-ram;
 			reg = <0x00000800 0 0 0 0>;
 			compatible = "intel,apl-punit";
 		};
 
 		gma@2,0 {
-			u-boot,dm-pre-proper;
+			bootph-some-ram;
 			reg = <0x00001000 0 0 0 0>;
 			compatible = "fsp-fb";
 		};
 
 		p2sb: p2sb@d,0 {
-			u-boot,dm-pre-reloc;
+			bootph-all;
 			reg = <0x02006810 0 0 0 0>;
 			compatible = "intel,p2sb";
 			early-regs = <IOMAP_P2SB_BAR 0x100000>;
@@ -227,12 +227,12 @@
 
 			n {
 				compatible = "intel,apl-pinctrl";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				intel,p2sb-port-id = <PID_GPIO_N>;
 				acpi,path = "\\_SB.GPO0";
 				gpio_n: gpio-n {
 					compatible = "intel,gpio";
-					u-boot,dm-pre-reloc;
+					bootph-all;
 					gpio-controller;
 					#gpio-cells = <2>;
 					linux-name = "INT3452:00";
@@ -240,14 +240,14 @@
 			};
 
 			nw {
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				compatible = "intel,apl-pinctrl";
 				intel,p2sb-port-id = <PID_GPIO_NW>;
 				#gpio-cells = <2>;
 				acpi,path = "\\_SB.GPO1";
 				gpio_nw: gpio-nw {
 					compatible = "intel,gpio";
-					u-boot,dm-pre-reloc;
+					bootph-all;
 					gpio-controller;
 					#gpio-cells = <2>;
 					linux-name = "INT3452:01";
@@ -255,14 +255,14 @@
 			};
 
 			w {
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				compatible = "intel,apl-pinctrl";
 				intel,p2sb-port-id = <PID_GPIO_W>;
 				#gpio-cells = <2>;
 				acpi,path = "\\_SB.GPO2";
 				gpio_w: gpio-w {
 					compatible = "intel,gpio";
-					u-boot,dm-pre-reloc;
+					bootph-all;
 					gpio-controller;
 					#gpio-cells = <2>;
 					linux-name = "INT3452:02";
@@ -270,14 +270,14 @@
 			};
 
 			sw {
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				compatible = "intel,apl-pinctrl";
 				intel,p2sb-port-id = <PID_GPIO_SW>;
 				#gpio-cells = <2>;
 				acpi,path = "\\_SB.GPO3";
 				gpio_sw: gpio-sw {
 					compatible = "intel,gpio";
-					u-boot,dm-pre-reloc;
+					bootph-all;
 					gpio-controller;
 					#gpio-cells = <2>;
 					linux-name = "INT3452:03";
@@ -285,7 +285,7 @@
 			};
 
 			itss {
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				compatible = "intel,itss";
 				intel,p2sb-port-id = <PID_ITSS>;
 				intel,pmc-routes = <
@@ -301,7 +301,7 @@
 		};
 
 		pmc@d,1 {
-			u-boot,dm-pre-reloc;
+			bootph-all;
 			reg = <0x6900 0 0 0 0>;
 
 			/*
@@ -348,8 +348,8 @@
 		};
 
 		spi: fast-spi@d,2 {
-			u-boot,dm-pre-proper;
-			u-boot,dm-spl;
+			bootph-some-ram;
+			bootph-pre-ram;
 			reg = <0x02006a10 0 0 0 0>;
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -360,8 +360,8 @@
 			fwstore_spi: spi-flash@0 {
 				#size-cells = <1>;
 				#address-cells = <1>;
-				u-boot,dm-pre-proper;
-				u-boot,dm-spl;
+				bootph-some-ram;
+				bootph-pre-ram;
 				reg = <0>;
 				m25p,fast-read;
 				compatible = "winbond,w25q128fw",
@@ -369,12 +369,12 @@
 				rw-mrc-cache {
 					label = "rw-mrc-cache";
 					reg = <0x008e0000 0x00010000>;
-					u-boot,dm-pre-reloc;
+					bootph-all;
 				};
 				rw-var-mrc-cache {
 					label = "rw-mrc-cache";
 					reg = <0x008f0000 0x0001000>;
-					u-boot,dm-pre-reloc;
+					bootph-all;
 				};
 			};
 		};
@@ -442,7 +442,7 @@
 			compatible = "intel,apl-i2c", "snps,designware-i2c-pci";
 			reg = <0x0200b210 0 0 0 0>;
 			early-regs = <IOMAP_I2C2_BASE 0x1000>;
-			u-boot,dm-pre-proper;
+			bootph-some-ram;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			clock-frequency = <400000>;
@@ -453,7 +453,7 @@
 			tpm: tpm@50 {
 				reg = <0x50>;
 				compatible = "google,cr50";
-				u-boot,dm-pre-proper;
+				bootph-some-ram;
 				u-boot,i2c-offset-len = <0>;
 				ready-gpios = <&gpio_n 28 GPIO_ACTIVE_LOW>;
 				interrupts-extended = <&acpi_gpe GPIO_28_IRQ
@@ -577,7 +577,7 @@
 
 		serial: serial@18,2 {
 			reg = <0x0200c210 0 0 0 0>;
-			u-boot,dm-pre-reloc;
+			bootph-all;
 			compatible = "intel,apl-ns16550";
 			early-regs = <0xde000000 0x20>;
 			reg-shift = <2>;
@@ -603,7 +603,7 @@
 		pch: pch@1f,0 {
 			reg = <0x0000f800 0 0 0 0>;
 			compatible = "intel,apl-pch";
-			u-boot,dm-pre-reloc;
+			bootph-all;
 			#address-cells = <1>;
 			#size-cells = <1>;
 
@@ -611,10 +611,10 @@
 				compatible = "intel,apl-lpc";
 				#address-cells = <1>;
 				#size-cells = <0>;
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				cros_ec: cros-ec {
-					u-boot,dm-pre-proper;
-					u-boot,dm-vpl;
+					bootph-some-ram;
+					bootph-verify;
 					compatible = "google,cros-ec-lpc";
 					reg = <0x204 1 0x200 1 0x880 0x80>;
 
@@ -785,7 +785,7 @@
 };
 
 &fsp_s {
-	u-boot,dm-pre-proper;
+	bootph-some-ram;
 
 	fsps,ish-enable = <0>;
 	fsps,enable-sata = <0>;
@@ -1253,5 +1253,5 @@
 &rtc {
 	#address-cells = <1>;
 	#size-cells = <0>;
-	u-boot,dm-pre-proper;
+	bootph-some-ram;
 };
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index 11ff520..36956f4 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -71,7 +71,7 @@
 
 	pch_pinctrl {
 		compatible = "intel,x86-pinctrl";
-		u-boot,dm-pre-reloc;
+		bootph-all;
 		reg = <0 0>;
 
 		gpio_a0 {
@@ -127,7 +127,7 @@
 		};
 
 		gpio_a10 {
-			u-boot,dm-pre-reloc;
+			bootph-all;
 			gpio-offset = <0 10>;
 			mode-gpio;
 			direction = <PIN_INPUT>;
@@ -187,21 +187,21 @@
 		};
 
 		gpio_b9 {
-			u-boot,dm-pre-reloc;
+			bootph-all;
 			gpio-offset = <0x30 9>;
 			mode-gpio;
 			direction = <PIN_INPUT>;
 		};
 
 		gpio_b10 {
-			u-boot,dm-pre-reloc;
+			bootph-all;
 			gpio-offset = <0x30 10>;
 			mode-gpio;
 			direction = <PIN_INPUT>;
 		};
 
 		gpio_b11 {
-			u-boot,dm-pre-reloc;
+			bootph-all;
 			gpio-offset = <0x30 11>;
 			mode-gpio;
 			direction = <PIN_INPUT>;
@@ -226,23 +226,23 @@
 		compatible = "pci-x86";
 		#address-cells = <3>;
 		#size-cells = <2>;
-		u-boot,dm-pre-reloc;
+		bootph-all;
 		ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
 			0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
 			0x01000000 0x0 0x1000 0x1000 0 0xefff>;
 
 		northbridge@0,0 {
 			reg = <0x00000000 0 0 0 0>;
-			u-boot,dm-pre-reloc;
+			bootph-all;
 			compatible = "intel,bd82x6x-northbridge";
 			board-id-gpios = <&gpio_b 9 0>, <&gpio_b 10 0>,
 					<&gpio_b 11 0>, <&gpio_a 10 0>;
 			spd {
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				elpida_4Gb_1600_x16 {
-					u-boot,dm-pre-reloc;
+					bootph-all;
 					reg = <0>;
 					data = [92 10 0b 03 04 19 02 02
 						03 52 01 08 0a 00 fe 00
@@ -278,7 +278,7 @@
 						00 00 00 00 00 00 00 00];
 				};
 				samsung_4Gb_1600_1.35v_x16 {
-					u-boot,dm-pre-reloc;
+					bootph-all;
 					reg = <1>;
 					data = [92 11 0b 03 04 19 02 02
 						03 11 01 08 0a 00 fe 00
@@ -368,7 +368,7 @@
 		me@16,0 {
 			reg = <0x0000b000 0 0 0 0>;
 			compatible = "intel,me";
-			u-boot,dm-pre-reloc;
+			bootph-all;
 		};
 
 		usb_1: usb@1a,0 {
@@ -410,7 +410,7 @@
 		pch@1f,0 {
 			reg = <0x0000f800 0 0 0 0>;
 			compatible = "intel,bd82x6x", "intel,pch9";
-			u-boot,dm-pre-reloc;
+			bootph-all;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
@@ -424,11 +424,11 @@
 				#address-cells = <1>;
 				#size-cells = <0>;
 				compatible = "intel,ich9-spi";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				spi-flash@0 {
 					#size-cells = <1>;
 					#address-cells = <1>;
-					u-boot,dm-pre-reloc;
+					bootph-all;
 					reg = <0>;
 					m25p,fast-read;
 					compatible = "winbond,w25q64",
@@ -437,14 +437,14 @@
 					rw-mrc-cache {
 						label = "rw-mrc-cache";
 						reg = <0x003e0000 0x00010000>;
-						u-boot,dm-pre-reloc;
+						bootph-all;
 					};
 				};
 			};
 
 			gpio_a: gpioa {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				#gpio-cells = <2>;
 				gpio-controller;
 				reg = <0 0x10>;
@@ -453,7 +453,7 @@
 
 			gpio_b: gpiob {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				#gpio-cells = <2>;
 				gpio-controller;
 				reg = <0x30 0x10>;
@@ -462,7 +462,7 @@
 
 			gpio_c: gpioc {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				#gpio-cells = <2>;
 				gpio-controller;
 				reg = <0x40 0x10>;
@@ -473,7 +473,7 @@
 				compatible = "intel,bd82x6x-lpc";
 				#address-cells = <1>;
 				#size-cells = <0>;
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
 				cros-ec@200 {
 					compatible = "google,cros-ec";
@@ -496,7 +496,7 @@
 		sata@1f,2 {
 			compatible = "intel,pantherpoint-ahci";
 			reg = <0x0000fa00 0 0 0 0>;
-			u-boot,dm-pre-reloc;
+			bootph-all;
 			intel,sata-mode = "ahci";
 			intel,sata-port-map = <1>;
 			intel,sata-port0-gen3-tx = <0x00880a7f>;
@@ -505,7 +505,7 @@
 		smbus: smbus@1f,3 {
 			compatible = "intel,ich-i2c";
 			reg = <0x0000fb00 0 0 0 0>;
-			u-boot,dm-pre-reloc;
+			bootph-all;
 		};
 	};
 
@@ -515,9 +515,9 @@
 	};
 
 	microcode {
-		u-boot,dm-pre-reloc;
+		bootph-all;
 		update@0 {
-			u-boot,dm-pre-reloc;
+			bootph-all;
 #include "microcode/m12306a9_0000001b.dtsi"
 		};
 	};
diff --git a/arch/x86/dts/chromebook_samus.dts b/arch/x86/dts/chromebook_samus.dts
index 930ec1a..96705ce 100644
--- a/arch/x86/dts/chromebook_samus.dts
+++ b/arch/x86/dts/chromebook_samus.dts
@@ -77,12 +77,12 @@
 
 	pch_pinctrl {
 		compatible = "intel,x86-broadwell-pinctrl";
-		u-boot,dm-pre-reloc;
+		bootph-all;
 		reg = <0 0>;
 
 		/* Put this first: it is the default */
 		gpio_unused: gpio-unused {
-			u-boot,dm-pre-reloc;
+			bootph-all;
 			mode-gpio;
 			direction = <PIN_INPUT>;
 			owner = <OWNER_GPIO>;
@@ -90,7 +90,7 @@
 		};
 
 		gpio_acpi_sci: acpi-sci {
-			u-boot,dm-pre-reloc;
+			bootph-all;
 			mode-gpio;
 			direction = <PIN_INPUT>;
 			invert;
@@ -98,7 +98,7 @@
 		};
 
 		gpio_acpi_smi: acpi-smi {
-			u-boot,dm-pre-reloc;
+			bootph-all;
 			mode-gpio;
 			direction = <PIN_INPUT>;
 			invert;
@@ -106,14 +106,14 @@
 		};
 
 		gpio_input: gpio-input {
-			u-boot,dm-pre-reloc;
+			bootph-all;
 			mode-gpio;
 			direction = <PIN_INPUT>;
 			owner = <OWNER_GPIO>;
 		};
 
 		gpio_input_invert: gpio-input-invert {
-			u-boot,dm-pre-reloc;
+			bootph-all;
 			mode-gpio;
 			direction = <PIN_INPUT>;
 			owner = <OWNER_GPIO>;
@@ -121,11 +121,11 @@
 		};
 
 		gpio_native: gpio-native {
-			u-boot,dm-pre-reloc;
+			bootph-all;
 		};
 
 		gpio_out_high: gpio-out-high {
-			u-boot,dm-pre-reloc;
+			bootph-all;
 			mode-gpio;
 			direction = <PIN_OUTPUT>;
 			output-value = <1>;
@@ -134,7 +134,7 @@
 		};
 
 		gpio_out_low: gpio-out-low {
-			u-boot,dm-pre-reloc;
+			bootph-all;
 			mode-gpio;
 			direction = <PIN_OUTPUT>;
 			output-value = <0>;
@@ -143,7 +143,7 @@
 		};
 
 		gpio_pirq: gpio-pirq {
-			u-boot,dm-pre-reloc;
+			bootph-all;
 			mode-gpio;
 			direction = <PIN_INPUT>;
 			owner = <OWNER_GPIO>;
@@ -151,7 +151,7 @@
 		};
 
 		soc_gpio@0 {
-			u-boot,dm-pre-reloc;
+			bootph-all;
 			config =
 				<0 &gpio_unused 0>,	/* unused */
 				<1 &gpio_unused 0>,	/* unused */
@@ -255,7 +255,7 @@
 		compatible = "pci-x86";
 		#address-cells = <3>;
 		#size-cells = <2>;
-		u-boot,dm-pre-reloc;
+		bootph-all;
 		ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
 			0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
 			0x01000000 0x0 0x1000 0x1000 0 0xefff>;
@@ -265,14 +265,14 @@
 			compatible = "intel,broadwell-northbridge";
 			board-id-gpios = <&gpio_c 5 0>, <&gpio_c 4 0>,
 					<&gpio_c 3 0>, <&gpio_c 1 0>;
-			u-boot,dm-pre-reloc;
+			bootph-all;
 			spd {
 				#address-cells = <1>;
 				#size-cells = <0>;
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				samsung_4 {
 					reg = <6>;
-					u-boot,dm-pre-reloc;
+					bootph-all;
 					data = [91 20 f1 03 04 11 05 0b
 						03 11 01 08 0a 00 50 01
 						78 78 90 50 90 11 50 e0
@@ -312,7 +312,7 @@
 					 * columns 10, density 4096 mb, x32
 					 */
 					reg = <8>;
-					u-boot,dm-pre-reloc;
+					bootph-all;
 					data = [91 20 f1 03 04 11 05 0b
 						03 11 01 08 0a 00 50 01
 						78 78 90 50 90 11 50 e0
@@ -348,7 +348,7 @@
 					};
 				samsung_8 {
 					reg = <10>;
-					u-boot,dm-pre-reloc;
+					bootph-all;
 					data = [91 20 f1 03 04 12 05 0a
 						03 11 01 08 0a 00 50 01
 						78 78 90 50 90 11 50 e0
@@ -388,7 +388,7 @@
 					 * columns 11, density 4096 mb, x16
 					 */
 					reg = <12>;
-					u-boot,dm-pre-reloc;
+					bootph-all;
 					data = [91 20 f1 03 04 12 05 0a
 						03 11 01 08 0a 00 50 01
 						78 78 90 50 90 11 50 e0
@@ -428,7 +428,7 @@
 					 * columns 11, density 8192 mb, x16
 					 */
 					reg = <13>;
-					u-boot,dm-pre-reloc;
+					bootph-all;
 					data = [91 20 f1 03 05 1a 05 0a
 						03 11 01 08 0a 00 50 01
 						78 78 90 50 90 11 50 e0
@@ -468,7 +468,7 @@
 					 * columns 11, density 8192 mb, x16
 					 */
 					reg = <15>;
-					u-boot,dm-pre-reloc;
+					bootph-all;
 					data = [91 20 f1 03 05 1a 05 0a
 						03 11 01 08 0a 00 50 01
 						78 78 90 50 90 11 50 e0
@@ -557,7 +557,7 @@
 		me@16,0 {
 			reg = <0x0000b000 0 0 0 0>;
 			compatible = "intel,me";
-			u-boot,dm-pre-reloc;
+			bootph-all;
 		};
 
 		usb_0: usb@1d,0 {
@@ -569,7 +569,7 @@
 		pch: pch@1f,0 {
 			reg = <0x0000f800 0 0 0 0>;
 			compatible = "intel,broadwell-pch";
-			u-boot,dm-pre-reloc;
+			bootph-all;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
@@ -585,12 +585,12 @@
 			power-enable-gpio = <&gpio_a 23 0>;
 
 			spi: spi {
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				compatible = "intel,ich9-spi";
 				fwstore_spi: spi-flash@0 {
-					u-boot,dm-pre-reloc;
+					bootph-all;
 					#size-cells = <1>;
 					#address-cells = <1>;
 					reg = <0>;
@@ -599,7 +599,7 @@
 							"jedec,spi-nor";
 					memory-map = <0xff800000 0x00800000>;
 					rw-mrc-cache {
-						u-boot,dm-pre-reloc;
+						bootph-all;
 						label = "rw-mrc-cache";
 						reg = <0x003e0000 0x00010000>;
 					};
@@ -608,7 +608,7 @@
 
 			gpio_a: gpioa {
 				compatible = "intel,broadwell-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				#gpio-cells = <2>;
 				gpio-controller;
 				reg = <0 0>;
@@ -617,7 +617,7 @@
 
 			gpio_b: gpiob {
 				compatible = "intel,broadwell-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				#gpio-cells = <2>;
 				gpio-controller;
 				reg = <1 0>;
@@ -626,7 +626,7 @@
 
 			gpio_c: gpioc {
 				compatible = "intel,broadwell-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				#gpio-cells = <2>;
 				gpio-controller;
 				reg = <2 0>;
@@ -637,10 +637,10 @@
 				compatible = "intel,broadwell-lpc";
 				#address-cells = <1>;
 				#size-cells = <0>;
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
 				cros_ec: cros-ec {
-					u-boot,dm-pre-reloc;
+					bootph-all;
 					compatible = "google,cros-ec-lpc";
 					reg = <0x204 1 0x200 1 0x880 0x80>;
 
@@ -661,7 +661,7 @@
 		sata@1f,2 {
 			compatible = "intel,wildcatpoint-ahci";
 			reg = <0x0000fa00 0 0 0 0>;
-			u-boot,dm-pre-proper;
+			bootph-some-ram;
 			intel,sata-mode = "ahci";
 			intel,sata-port-map = <1>;
 			intel,sata-port0-gen3-tx = <0x72>;
@@ -671,24 +671,24 @@
 		smbus: smbus@1f,3 {
 			compatible = "intel,ich-i2c";
 			reg = <0x0000fb00 0 0 0 0>;
-			u-boot,dm-pre-reloc;
+			bootph-all;
 		};
 	};
 
 	tpm {
-		u-boot,dm-pre-reloc;
+		bootph-all;
 		reg = <0xfed40000 0x5000>;
 		compatible = "infineon,slb9635lpc";
 		secdata {
-			u-boot,dm-pre-reloc;
+			bootph-all;
 			compatible = "google,tpm-secdata";
 		};
 	};
 
 	microcode {
-		u-boot,dm-pre-reloc;
+		bootph-all;
 		update@0 {
-			u-boot,dm-pre-reloc;
+			bootph-all;
 #include "microcode/mc0306d4_00000018.dtsi"
 		};
 	};
@@ -711,7 +711,7 @@
 	#address-cells = <1>;
 	#size-cells = <0>;
 	nvdata {
-		u-boot,dm-pre-reloc;
+		bootph-all;
 		compatible = "google,cmos-nvdata";
 		reg = <0x26>;
 	};
diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts
index b25f759..242d852 100644
--- a/arch/x86/dts/chromebox_panther.dts
+++ b/arch/x86/dts/chromebox_panther.dts
@@ -29,7 +29,7 @@
 		compatible = "pci-x86";
 		#address-cells = <3>;
 		#size-cells = <2>;
-		u-boot,dm-pre-reloc;
+		bootph-all;
 		ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
 			0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
 			0x01000000 0x0 0x1000 0x1000 0 0xf000>;
@@ -61,21 +61,21 @@
 
 			gpioa {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0 0x10>;
 				bank-name = "A";
 			};
 
 			gpiob {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0x30 0x10>;
 				bank-name = "B";
 			};
 
 			gpioc {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0x40 0x10>;
 				bank-name = "C";
 			};
diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
index 705157c..8230639 100644
--- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts
+++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
@@ -103,7 +103,7 @@
 		compatible = "intel,pci-baytrail", "pci-x86";
 		#address-cells = <3>;
 		#size-cells = <2>;
-		u-boot,dm-pre-reloc;
+		bootph-all;
 		ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
 			  0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
 			  0x01000000 0x0 0x2000 0x2000 0 0xe000>;
@@ -200,7 +200,7 @@
 
 			gpioa {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0 0x20>;
 				bank-name = "A";
 				use-lvl-write-cache;
@@ -208,7 +208,7 @@
 
 			gpiob {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0x20 0x20>;
 				bank-name = "B";
 				use-lvl-write-cache;
@@ -216,7 +216,7 @@
 
 			gpioc {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0x40 0x20>;
 				bank-name = "C";
 				use-lvl-write-cache;
@@ -224,7 +224,7 @@
 
 			gpiod {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0x60 0x20>;
 				bank-name = "D";
 				use-lvl-write-cache;
@@ -232,7 +232,7 @@
 
 			gpioe {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0x80 0x20>;
 				bank-name = "E";
 				use-lvl-write-cache;
@@ -240,7 +240,7 @@
 
 			gpiof {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0xA0 0x20>;
 				bank-name = "F";
 				use-lvl-write-cache;
diff --git a/arch/x86/dts/coreboot.dts b/arch/x86/dts/coreboot.dts
index d21978d..f9ff534 100644
--- a/arch/x86/dts/coreboot.dts
+++ b/arch/x86/dts/coreboot.dts
@@ -33,11 +33,11 @@
 
 	pci {
 		compatible = "pci-x86";
-		u-boot,dm-pre-reloc;
+		bootph-all;
 	};
 
 	serial: serial {
-		u-boot,dm-pre-reloc;
+		bootph-all;
 		compatible = "coreboot-serial";
 	};
 
diff --git a/arch/x86/dts/cougarcanyon2.dts b/arch/x86/dts/cougarcanyon2.dts
index 58395b5..4833aab 100644
--- a/arch/x86/dts/cougarcanyon2.dts
+++ b/arch/x86/dts/cougarcanyon2.dts
@@ -92,7 +92,7 @@
 		#address-cells = <3>;
 		#size-cells = <2>;
 		compatible = "pci-x86";
-		u-boot,dm-pre-reloc;
+		bootph-all;
 		ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
 			  0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
 			  0x01000000 0x0 0x2000 0x2000 0 0xe000>;
@@ -100,7 +100,7 @@
 		pch@1f,0 {
 			reg = <0x0000f800 0 0 0 0>;
 			compatible = "intel,bd82x6x";
-			u-boot,dm-pre-reloc;
+			bootph-all;
 			#address-cells = <1>;
 			#size-cells = <1>;
 
@@ -164,21 +164,21 @@
 
 			gpioa {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0 0x10>;
 				bank-name = "A";
 			};
 
 			gpiob {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0x30 0x10>;
 				bank-name = "B";
 			};
 
 			gpioc {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0x40 0x10>;
 				bank-name = "C";
 			};
diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
index 5768352..6428230 100644
--- a/arch/x86/dts/crownbay.dts
+++ b/arch/x86/dts/crownbay.dts
@@ -71,7 +71,7 @@
 		#address-cells = <3>;
 		#size-cells = <2>;
 		compatible = "pci-x86";
-		u-boot,dm-pre-reloc;
+		bootph-all;
 		ranges = <0x02000000 0x0 0x40000000 0x40000000 0 0x80000000
 			  0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
 			  0x01000000 0x0 0x2000 0x2000 0 0xe000>;
@@ -80,14 +80,14 @@
 			#address-cells = <3>;
 			#size-cells = <2>;
 			compatible = "pci-bridge";
-			u-boot,dm-pre-reloc;
+			bootph-all;
 			reg = <0x0000b800 0x0 0x0 0x0 0x0>;
 
 			topcliff@0,0 {
 				#address-cells = <3>;
 				#size-cells = <2>;
 				compatible = "pci-bridge";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0x00010000 0x0 0x0 0x0 0x0>;
 
 				pciuart0: uart@a,1 {
@@ -96,7 +96,7 @@
 							"pciclass,070002",
 							"pciclass,0700",
 							"ns16550";
-					u-boot,dm-pre-reloc;
+					bootph-all;
 					reg = <0x00025100 0x0 0x0 0x0 0x0
 					       0x01025110 0x0 0x0 0x0 0x0>;
 					reg-shift = <0>;
@@ -110,7 +110,7 @@
 							"pciclass,070002",
 							"pciclass,0700",
 							"ns16550";
-					u-boot,dm-pre-reloc;
+					bootph-all;
 					reg = <0x00025200 0x0 0x0 0x0 0x0
 					       0x01025210 0x0 0x0 0x0 0x0>;
 					reg-shift = <0>;
@@ -124,7 +124,7 @@
 							"pciclass,070002",
 							"pciclass,0700",
 							"ns16550";
-					u-boot,dm-pre-reloc;
+					bootph-all;
 					reg = <0x00025300 0x0 0x0 0x0 0x0
 					       0x01025310 0x0 0x0 0x0 0x0>;
 					reg-shift = <0>;
@@ -138,7 +138,7 @@
 							"pciclass,070002",
 							"pciclass,0700",
 							"ns16550";
-					u-boot,dm-pre-reloc;
+					bootph-all;
 					reg = <0x00025400 0x0 0x0 0x0 0x0
 					       0x01025410 0x0 0x0 0x0 0x0>;
 					reg-shift = <0>;
@@ -233,14 +233,14 @@
 
 			gpioa {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0 0x20>;
 				bank-name = "A";
 			};
 
 			gpiob {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0x20 0x20>;
 				bank-name = "B";
 			};
diff --git a/arch/x86/dts/dfi-bt700.dtsi b/arch/x86/dts/dfi-bt700.dtsi
index dff2345..9193e51 100644
--- a/arch/x86/dts/dfi-bt700.dtsi
+++ b/arch/x86/dts/dfi-bt700.dtsi
@@ -101,7 +101,7 @@
 		compatible = "intel,pci-baytrail", "pci-x86";
 		#address-cells = <3>;
 		#size-cells = <2>;
-		u-boot,dm-pre-reloc;
+		bootph-all;
 		ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
 			  0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
 			  0x01000000 0x0 0x2000 0x2000 0 0xe000>;
@@ -112,7 +112,7 @@
 					"pciclass,070002",
 					"pciclass,0700",
 					"ns16550";
-			u-boot,dm-pre-reloc;
+			bootph-all;
 			reg = <0x0200f310 0x0 0x0 0x0 0x0>;
 			reg-shift = <2>;
 			clock-frequency = <58982400>;
@@ -211,7 +211,7 @@
 
 			gpioa {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0 0x20>;
 				bank-name = "A";
 				use-lvl-write-cache;
@@ -219,7 +219,7 @@
 
 			gpiob {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0x20 0x20>;
 				bank-name = "B";
 				use-lvl-write-cache;
@@ -227,7 +227,7 @@
 
 			gpioc {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0x40 0x20>;
 				bank-name = "C";
 				use-lvl-write-cache;
@@ -235,7 +235,7 @@
 
 			gpiod {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0x60 0x20>;
 				bank-name = "D";
 				use-lvl-write-cache;
@@ -243,7 +243,7 @@
 
 			gpioe {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0x80 0x20>;
 				bank-name = "E";
 				use-lvl-write-cache;
@@ -251,7 +251,7 @@
 
 			gpiof {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0xA0 0x20>;
 				bank-name = "F";
 				use-lvl-write-cache;
diff --git a/arch/x86/dts/edison.dts b/arch/x86/dts/edison.dts
index b3658b8..7af8507 100644
--- a/arch/x86/dts/edison.dts
+++ b/arch/x86/dts/edison.dts
@@ -55,7 +55,7 @@
 		compatible = "pci-x86";
 		#address-cells = <3>;
 		#size-cells = <2>;
-		u-boot,dm-pre-reloc;
+		bootph-all;
 		ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
 			  0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
 			  0x01000000 0x0 0x2000 0x2000 0 0xe000>;
@@ -130,7 +130,7 @@
 
 	reset {
 		compatible = "intel,reset-tangier";
-		u-boot,dm-pre-reloc;
+		bootph-all;
 	};
 
 	pinctrl {
diff --git a/arch/x86/dts/efi-x86_app.dts b/arch/x86/dts/efi-x86_app.dts
index a5316e2..6d843a9 100644
--- a/arch/x86/dts/efi-x86_app.dts
+++ b/arch/x86/dts/efi-x86_app.dts
@@ -23,7 +23,7 @@
 
 	reset {
 		compatible = "efi,reset";
-		u-boot,dm-pre-reloc;
+		bootph-all;
 	};
 	efi-fb {
 		compatible = "efi-fb";
diff --git a/arch/x86/dts/efi-x86_payload.dts b/arch/x86/dts/efi-x86_payload.dts
index 087865f..1a6dd7d 100644
--- a/arch/x86/dts/efi-x86_payload.dts
+++ b/arch/x86/dts/efi-x86_payload.dts
@@ -33,7 +33,7 @@
 
 	pci {
 		compatible = "pci-x86";
-		u-boot,dm-pre-reloc;
+		bootph-all;
 	};
 
 	efi-fb {
diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts
index 4120e8f..08be190 100644
--- a/arch/x86/dts/galileo.dts
+++ b/arch/x86/dts/galileo.dts
@@ -69,7 +69,7 @@
 		#address-cells = <3>;
 		#size-cells = <2>;
 		compatible = "pci-x86";
-		u-boot,dm-pre-reloc;
+		bootph-all;
 		ranges = <0x02000000 0x0 0x90000000 0x90000000 0 0x20000000
 			  0x42000000 0x0 0xb0000000 0xb0000000 0 0x20000000
 			  0x01000000 0x0 0x2000 0x2000 0 0xe000>;
@@ -80,7 +80,7 @@
 					"pciclass,070002",
 					"pciclass,0700",
 					"ns16550";
-			u-boot,dm-pre-reloc;
+			bootph-all;
 			reg = <0x0000a500 0x0 0x0 0x0 0x0
 			       0x0200a510 0x0 0x0 0x0 0x0>;
 			reg-shift = <2>;
@@ -147,14 +147,14 @@
 
 			gpioa {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0 0x20>;
 				bank-name = "A";
 			};
 
 			gpiob {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0x20 0x20>;
 				bank-name = "B";
 			};
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index 68e0510..1182b4b 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -116,7 +116,7 @@
 		compatible = "intel,pci-baytrail", "pci-x86";
 		#address-cells = <3>;
 		#size-cells = <2>;
-		u-boot,dm-pre-reloc;
+		bootph-all;
 		ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
 			  0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
 			  0x01000000 0x0 0x2000 0x2000 0 0xe000>;
@@ -213,7 +213,7 @@
 
 			gpioa {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0 0x20>;
 				bank-name = "A";
 				use-lvl-write-cache;
@@ -221,7 +221,7 @@
 
 			gpiob {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0x20 0x20>;
 				bank-name = "B";
 				use-lvl-write-cache;
@@ -229,7 +229,7 @@
 
 			gpioc {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0x40 0x20>;
 				bank-name = "C";
 				use-lvl-write-cache;
@@ -237,7 +237,7 @@
 
 			gpiod {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0x60 0x20>;
 				bank-name = "D";
 				use-lvl-write-cache;
@@ -245,7 +245,7 @@
 
 			gpioe {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0x80 0x20>;
 				bank-name = "E";
 				use-lvl-write-cache;
@@ -253,7 +253,7 @@
 
 			gpiof {
 				compatible = "intel,ich6-gpio";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				reg = <0xA0 0x20>;
 				bank-name = "F";
 				use-lvl-write-cache;
diff --git a/arch/x86/dts/qemu-x86_i440fx.dts b/arch/x86/dts/qemu-x86_i440fx.dts
index 6556e9e..3bb2f12 100644
--- a/arch/x86/dts/qemu-x86_i440fx.dts
+++ b/arch/x86/dts/qemu-x86_i440fx.dts
@@ -31,12 +31,12 @@
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
-		u-boot,dm-pre-reloc;
+		bootph-all;
 
 		cpu@0 {
 			device_type = "cpu";
 			compatible = "cpu-qemu";
-			u-boot,dm-pre-reloc;
+			bootph-all;
 			reg = <0>;
 			intel,apic-id = <0>;
 		};
@@ -46,7 +46,7 @@
 		compatible = "pci-x86";
 		#address-cells = <3>;
 		#size-cells = <2>;
-		u-boot,dm-pre-reloc;
+		bootph-all;
 		ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
 			0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
 			0x01000000 0x0 0x2000 0x2000 0 0xe000>;
@@ -54,11 +54,11 @@
 		pch@1,0 {
 			reg = <0x00000800 0 0 0 0>;
 			compatible = "intel,pch7";
-			u-boot,dm-pre-reloc;
+			bootph-all;
 
 			irq-router {
 				compatible = "intel,irq-router";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				intel,pirq-config = "pci";
 				intel,pirq-link = <0x60 4>;
 				intel,pirq-mask = <0x0e40>;
diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts
index d083089..63931cd 100644
--- a/arch/x86/dts/qemu-x86_q35.dts
+++ b/arch/x86/dts/qemu-x86_q35.dts
@@ -42,12 +42,12 @@
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
-		u-boot,dm-pre-reloc;
+		bootph-all;
 
 		cpu@0 {
 			device_type = "cpu";
 			compatible = "cpu-qemu";
-			u-boot,dm-pre-reloc;
+			bootph-all;
 			reg = <0>;
 			intel,apic-id = <0>;
 		};
@@ -57,7 +57,7 @@
 		compatible = "pci-x86";
 		#address-cells = <3>;
 		#size-cells = <2>;
-		u-boot,dm-pre-reloc;
+		bootph-all;
 		ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
 			0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
 			0x01000000 0x0 0x2000 0x2000 0 0xe000>;
@@ -65,11 +65,11 @@
 		pch@1f,0 {
 			reg = <0x0000f800 0 0 0 0>;
 			compatible = "intel,pch9";
-			u-boot,dm-pre-reloc;
+			bootph-all;
 
 			irq-router {
 				compatible = "intel,irq-router";
-				u-boot,dm-pre-reloc;
+				bootph-all;
 				intel,pirq-config = "pci";
 				intel,actl-8bit;
 				intel,actl-addr = <0x44>;
diff --git a/arch/x86/dts/reset.dtsi b/arch/x86/dts/reset.dtsi
index f2ba2fb..1f1ff9f 100644
--- a/arch/x86/dts/reset.dtsi
+++ b/arch/x86/dts/reset.dtsi
@@ -1,6 +1,6 @@
 / {
 	reset: reset {
 		compatible = "x86,reset";
-		u-boot,dm-pre-proper;
+		bootph-some-ram;
 	};
 };
diff --git a/arch/x86/dts/rtc.dtsi b/arch/x86/dts/rtc.dtsi
index 942cc93..1c2eb28 100644
--- a/arch/x86/dts/rtc.dtsi
+++ b/arch/x86/dts/rtc.dtsi
@@ -1,7 +1,7 @@
 / {
 	rtc: rtc {
 		compatible = "motorola,mc146818";
-		u-boot,dm-pre-proper;
+		bootph-some-ram;
 		reg = <0x70 2>;
 	};
 };
diff --git a/arch/x86/dts/serial.dtsi b/arch/x86/dts/serial.dtsi
index 22f7b54..99022eb 100644
--- a/arch/x86/dts/serial.dtsi
+++ b/arch/x86/dts/serial.dtsi
@@ -1,6 +1,6 @@
 / {
 	serial: serial {
-		u-boot,dm-pre-reloc;
+		bootph-all;
 		compatible = "ns16550";
 		reg = <0x3f8 8>;
 		reg-shift = <0>;
diff --git a/arch/x86/dts/tsc_timer.dtsi b/arch/x86/dts/tsc_timer.dtsi
index 4df8e9d..9d098df 100644
--- a/arch/x86/dts/tsc_timer.dtsi
+++ b/arch/x86/dts/tsc_timer.dtsi
@@ -2,6 +2,6 @@
 	tsc-timer {
 		compatible = "x86,tsc-timer";
 		clock-frequency = <CONFIG_X86_TSC_TIMER_FREQ>;
-		u-boot,dm-pre-reloc;
+		bootph-all;
 	};
 };