dm: dts: Convert driver model tags to use new schema
Now that Linux has accepted these tags, move the device tree files in
U-Boot over to use them.
Signed-off-by: Simon Glass <sjg@chromium.org>
diff --git a/arch/riscv/dts/ae350-u-boot.dtsi b/arch/riscv/dts/ae350-u-boot.dtsi
index 7011f59..aef9159 100644
--- a/arch/riscv/dts/ae350-u-boot.dtsi
+++ b/arch/riscv/dts/ae350-u-boot.dtsi
@@ -2,51 +2,51 @@
/ {
cpus {
- u-boot,dm-spl;
+ bootph-pre-ram;
CPU0: cpu@0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
CPU0_intc: interrupt-controller {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
CPU1: cpu@1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
CPU1_intc: interrupt-controller {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
CPU2: cpu@2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
CPU2_intc: interrupt-controller {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
CPU3: cpu@3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
CPU3_intc: interrupt-controller {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
};
memory@0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
soc {
- u-boot,dm-spl;
+ bootph-pre-ram;
plicsw: interrupt-controller@e6400000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
plmt0@e6000000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
serial0: serial@f0300000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi
index b7cd600..360679a 100644
--- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
@@ -9,47 +9,47 @@
cpus {
assigned-clocks = <&prci PRCI_CLK_COREPLL>;
assigned-clock-rates = <1000000000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
cpu0: cpu@0 {
clocks = <&prci PRCI_CLK_COREPLL>;
- u-boot,dm-spl;
+ bootph-pre-ram;
status = "okay";
cpu0_intc: interrupt-controller {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
cpu1: cpu@1 {
clocks = <&prci PRCI_CLK_COREPLL>;
- u-boot,dm-spl;
+ bootph-pre-ram;
cpu1_intc: interrupt-controller {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
cpu2: cpu@2 {
clocks = <&prci PRCI_CLK_COREPLL>;
- u-boot,dm-spl;
+ bootph-pre-ram;
cpu2_intc: interrupt-controller {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
cpu3: cpu@3 {
clocks = <&prci PRCI_CLK_COREPLL>;
- u-boot,dm-spl;
+ bootph-pre-ram;
cpu3_intc: interrupt-controller {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
cpu4: cpu@4 {
clocks = <&prci PRCI_CLK_COREPLL>;
- u-boot,dm-spl;
+ bootph-pre-ram;
cpu4_intc: interrupt-controller {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
};
soc {
- u-boot,dm-spl;
+ bootph-pre-ram;
otp: otp@10070000 {
compatible = "sifive,fu540-c000-otp";
reg = <0x0 0x10070000 0x0 0x1000>;
@@ -63,7 +63,7 @@
&cpu3_intc 3 &cpu3_intc 7
&cpu4_intc 3 &cpu4_intc 7>;
reg = <0x0 0x2000000 0x0 0x10000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
prci: clock-controller@10000000 {
#reset-cells = <1>;
@@ -82,21 +82,21 @@
0x0 0x100b8000 0x0 0x1000>;
clocks = <&prci PRCI_CLK_DDRPLL>;
clock-frequency = <933333324>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
};
&prci {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&uart0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&qspi2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
ð0 {
diff --git a/arch/riscv/dts/fu740-c000-u-boot.dtsi b/arch/riscv/dts/fu740-c000-u-boot.dtsi
index 917e9bf..706224b 100644
--- a/arch/riscv/dts/fu740-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu740-c000-u-boot.dtsi
@@ -9,47 +9,47 @@
cpus {
assigned-clocks = <&prci FU740_PRCI_CLK_COREPLL>;
assigned-clock-rates = <1200000000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
cpu0: cpu@0 {
clocks = <&prci FU740_PRCI_CLK_COREPLL>;
- u-boot,dm-spl;
+ bootph-pre-ram;
status = "okay";
cpu0_intc: interrupt-controller {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
cpu1: cpu@1 {
clocks = <&prci FU740_PRCI_CLK_COREPLL>;
- u-boot,dm-spl;
+ bootph-pre-ram;
cpu1_intc: interrupt-controller {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
cpu2: cpu@2 {
clocks = <&prci FU740_PRCI_CLK_COREPLL>;
- u-boot,dm-spl;
+ bootph-pre-ram;
cpu2_intc: interrupt-controller {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
cpu3: cpu@3 {
clocks = <&prci FU740_PRCI_CLK_COREPLL>;
- u-boot,dm-spl;
+ bootph-pre-ram;
cpu3_intc: interrupt-controller {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
cpu4: cpu@4 {
clocks = <&prci FU740_PRCI_CLK_COREPLL>;
- u-boot,dm-spl;
+ bootph-pre-ram;
cpu4_intc: interrupt-controller {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
};
soc {
- u-boot,dm-spl;
+ bootph-pre-ram;
clint: clint@2000000 {
compatible = "riscv,clint0";
interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
@@ -58,7 +58,7 @@
&cpu3_intc 3 &cpu3_intc 7
&cpu4_intc 3 &cpu4_intc 7>;
reg = <0x0 0x2000000 0x0 0x10000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
prci: clock-controller@10000000 {
#reset-cells = <1>;
@@ -78,25 +78,25 @@
0x0 0x100b8000 0x0 0x1000>;
clocks = <&prci FU740_PRCI_CLK_DDRPLL>;
clock-frequency = <933333324>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
};
&prci {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&uart0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&spi0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
ð0 {
diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
index 51b5661..e89b7d0 100644
--- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
+++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
@@ -22,15 +22,15 @@
};
memory@80000000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
hfclk {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
rtcclk {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
@@ -40,19 +40,19 @@
};
&qspi0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
flash@0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&qspi2 {
mmc@0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&gpio {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
diff --git a/arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi
index 1ee8ab1..39d6277 100644
--- a/arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi
+++ b/arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi
@@ -13,7 +13,7 @@
};
memory@80000000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
config {
@@ -21,11 +21,11 @@
};
hfclk {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
rtcclk {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
@@ -35,18 +35,18 @@
};
&qspi0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
flash@0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&spi0 {
mmc@0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&gpio {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
diff --git a/arch/riscv/dts/k210.dtsi b/arch/riscv/dts/k210.dtsi
index 3cc8379..6b85860 100644
--- a/arch/riscv/dts/k210.dtsi
+++ b/arch/riscv/dts/k210.dtsi
@@ -91,7 +91,7 @@
<&sysclk K210_CLK_SRAM1>,
<&sysclk K210_CLK_AI>;
clock-names = "sram0", "sram1", "aisram";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
clocks {
@@ -99,7 +99,7 @@
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
@@ -521,7 +521,7 @@
clocks = <&sysclk K210_CLK_APB1>;
clock-names = "pclk";
reg-io-width = <4>;
- u-boot,dm-pre-reloc;
+ bootph-all;
sysclk: clock-controller {
#clock-cells = <1>;
@@ -529,7 +529,7 @@
clocks = <&in0>;
assigned-clocks = <&sysclk K210_CLK_PLL1>;
assigned-clock-rates = <390000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
sysrst: reset-controller {
diff --git a/arch/riscv/dts/openpiton-riscv64.dts b/arch/riscv/dts/openpiton-riscv64.dts
index abc6016..e0553d5 100644
--- a/arch/riscv/dts/openpiton-riscv64.dts
+++ b/arch/riscv/dts/openpiton-riscv64.dts
@@ -32,7 +32,7 @@
CPU0: cpu@0 {
clocks = <&clk0>;
- u-boot,dm-spl;
+ bootph-pre-ram;
device_type = "cpu";
reg = <0>;
compatible = "openhwgroup,cva6", "riscv";
@@ -74,7 +74,7 @@
};
memory@80000000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
device_type = "memory";
reg = < 0x00000000 0x80000000 0x00000000 0x40000000 >;
};
@@ -121,7 +121,7 @@
};
sdhci_0: sdhci@f000000000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
compatible = "openpiton,piton-mmc", "openpiton,mmc";
reg = < 0x000000f0 0x00000000 0x00000000 0x00300000 >;
};
@@ -137,7 +137,7 @@
};
PLIC0: plic@fff1100000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
#interrupt-cells = <1>;
compatible = "sifive,plic-1.0.0", "openpiton,plic";
interrupt-controller;