diff --git a/arch/arm/dts/k3-j721e-sk-u-boot.dtsi b/arch/arm/dts/k3-j721e-sk-u-boot.dtsi
index 2d65e2d..0949caa 100644
--- a/arch/arm/dts/k3-j721e-sk-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-sk-u-boot.dtsi
@@ -31,26 +31,26 @@
 };
 
 &cbass_main{
-	u-boot,dm-spl;
+	bootph-pre-ram;
 
 	main_navss {
-		u-boot,dm-spl;
+		bootph-pre-ram;
 	};
 };
 
 &cbass_mcu_wakeup {
-	u-boot,dm-spl;
+	bootph-pre-ram;
 
 	timer1: timer@40400000 {
 		compatible = "ti,omap5430-timer";
 		reg = <0x0 0x40400000 0x0 0x80>;
 		ti,timer-alwon;
 		clock-frequency = <25000000>;
-		u-boot,dm-spl;
+		bootph-pre-ram;
 	};
 
 	mcu-navss {
-		u-boot,dm-spl;
+		bootph-pre-ram;
 
 		ringacc@2b800000 {
 			reg =	<0x0 0x2b800000 0x0 0x400000>,
@@ -59,7 +59,7 @@
 				<0x0 0x2a500000 0x0 0x40000>,
 				<0x0 0x28440000 0x0 0x40000>;
 			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
-			u-boot,dm-spl;
+			bootph-pre-ram;
 		};
 
 		dma-controller@285c0000 {
@@ -71,53 +71,53 @@
 				<0x0 0x28400000 0x0 0x2000>;
 			reg-names = "gcfg", "rchan", "rchanrt", "tchan",
 					    "tchanrt", "rflow";
-			u-boot,dm-spl;
+			bootph-pre-ram;
 		};
 	};
 
 	chipid@43000014 {
-		u-boot,dm-spl;
+		bootph-pre-ram;
 	};
 };
 
 &secure_proxy_main {
-	u-boot,dm-spl;
+	bootph-pre-ram;
 };
 
 &dmsc {
-	u-boot,dm-spl;
+	bootph-pre-ram;
 	k3_sysreset: sysreset-controller {
 		compatible = "ti,sci-sysreset";
-		u-boot,dm-spl;
+		bootph-pre-ram;
 	};
 };
 
 &k3_pds {
-	u-boot,dm-spl;
+	bootph-pre-ram;
 };
 
 &k3_clks {
-	u-boot,dm-spl;
+	bootph-pre-ram;
 };
 
 &k3_reset {
-	u-boot,dm-spl;
+	bootph-pre-ram;
 };
 
 &wkup_pmx0 {
-	u-boot,dm-spl;
+	bootph-pre-ram;
 };
 
 &main_pmx0 {
-	u-boot,dm-spl;
+	bootph-pre-ram;
 };
 
 &main_uart0 {
-	u-boot,dm-spl;
+	bootph-pre-ram;
 };
 
 &mcu_uart0 {
-	u-boot,dm-spl;
+	bootph-pre-ram;
 };
 
 &main_sdhci0 {
@@ -125,7 +125,7 @@
 };
 
 &main_sdhci1 {
-	u-boot,dm-spl;
+	bootph-pre-ram;
 };
 
 &wiz3_pll1_refclk {
@@ -134,16 +134,16 @@
 };
 
 &main_usbss0_pins_default {
-	u-boot,dm-spl;
+	bootph-pre-ram;
 };
 
 &usbss0 {
-	u-boot,dm-spl;
+	bootph-pre-ram;
 };
 
 &usb0 {
 	dr_mode = "host";
-	u-boot,dm-spl;
+	bootph-pre-ram;
 };
 
 &wiz2_pll1_refclk {
@@ -152,16 +152,16 @@
 };
 
 &main_usbss1_pins_default {
-	u-boot,dm-spl;
+	bootph-pre-ram;
 };
 
 &usbss1 {
-	u-boot,dm-spl;
+	bootph-pre-ram;
 };
 
 &usb1 {
 	dr_mode = "host";
-	u-boot,dm-spl;
+	bootph-pre-ram;
 };
 
 &mcu_cpsw {
@@ -178,19 +178,19 @@
 };
 
 &main_mmc1_pins_default {
-	u-boot,dm-spl;
+	bootph-pre-ram;
 };
 
 &wkup_i2c0_pins_default {
-	u-boot,dm-spl;
+	bootph-pre-ram;
 };
 
 &wkup_i2c0 {
-	u-boot,dm-spl;
+	bootph-pre-ram;
 };
 
 &mcu_i2c0 {
-	u-boot,dm-spl;
+	bootph-pre-ram;
 };
 
 &mcu_i2c1 {
@@ -226,27 +226,27 @@
 };
 
 &mcu_i2c0_pins_default {
-	u-boot,dm-spl;
+	bootph-pre-ram;
 };
 
 &mcu_fss0_ospi0_pins_default {
-	u-boot,dm-spl;
+	bootph-pre-ram;
 };
 
 &fss {
-	u-boot,dm-spl;
+	bootph-pre-ram;
 };
 
 &ospi0 {
-	u-boot,dm-spl;
+	bootph-pre-ram;
 
 	flash@0 {
-		u-boot,dm-spl;
+		bootph-pre-ram;
 
 		partition@3fc0000 {
 			label = "ospi.phypattern";
 			reg = <0x3fc0000 0x40000>;
-			u-boot,dm-spl;
+			bootph-pre-ram;
 		};
 	};
 };