commit d35f3383c2289719a902d306475153fdb4cd581e
author Simon Glass <sjg@chromium.org> Thu Apr 06 12:47:05 2017 -0600
committer Tom Rini <trini@konsulko.com> Thu Apr 13 09:40:57 2017 -0400
tree e60233acce1fb476d8d79cecd6252d50ed456b32
parent 0e0ac2086e5498cd3aa8d93901f2b3af7bcd9b43

board_f: Rename initdram() to dram_init()

This allows us to use the same DRAM init function on all archs. Add a
dummy function for arc, which does not use DRAM init here.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Dummy function on nios2]
Signed-off-by: Tom Rini <trini@konsulko.com>

board/esd/mecp5123/mecp5123.c

diff --git a/board/esd/mecp5123/mecp5123.c b/board/esd/mecp5123/mecp5123.c
index 80963fe..66dc407 100644
--- a/board/esd/mecp5123/mecp5123.c
+++ b/board/esd/mecp5123/mecp5123.c
@@ -62,7 +62,7 @@
 	return 0;
 }
 
-int initdram(void)
+int dram_init(void)
 {
 	gd->ram_size = get_ram_size(0, fixed_sdram(NULL, NULL, 0));
 

board/esd/pmc440/sdram.c

diff --git a/board/esd/pmc440/sdram.c b/board/esd/pmc440/sdram.c
index e962d4c..c379e77 100644
--- a/board/esd/pmc440/sdram.c
+++ b/board/esd/pmc440/sdram.c
@@ -42,7 +42,7 @@
 };
 
 /*
- * initdram -- 440EPx's DDR controller is a DENALI Core
+ * dram_init -- 440EPx's DDR controller is a DENALI Core
  */
 int initdram_by_rb(int rows, int banks)
 {
@@ -107,7 +107,7 @@
 	return 0;
 }
 
-int initdram(void)
+int dram_init(void)
 {
 	phys_size_t size;
 	int n;

board/esd/vme8349/vme8349.c

diff --git a/board/esd/vme8349/vme8349.c b/board/esd/vme8349/vme8349.c
index 0e7f8b1..36a5519 100644
--- a/board/esd/vme8349/vme8349.c
+++ b/board/esd/vme8349/vme8349.c
@@ -30,7 +30,7 @@
 
 void ddr_enable_ecc(unsigned int dram_size);
 
-int initdram(void)
+int dram_init(void)
 {
 	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	u32 msize = 0;