sunxi: add clock code for H6
The new Allwinner H6 SoC has a brand new CCU layout.
Add clock code for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index 4c75249..97a4f22 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -26,6 +26,7 @@
obj-$(CONFIG_MACH_SUN8I) += clock_sun6i.o
endif
obj-$(CONFIG_MACH_SUN9I) += clock_sun9i.o gtbus_sun9i.o
+obj-$(CONFIG_MACH_SUN50I_H6) += clock_sun50i_h6.o
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_DRAM_SUN4I) += dram_sun4i.o
diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c
new file mode 100644
index 0000000..ba8a26e
--- /dev/null
+++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
@@ -0,0 +1,94 @@
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+
+#ifdef CONFIG_SPL_BUILD
+void clock_init_safe(void)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ clock_set_pll1(408000000);
+
+ writel(CCM_PLL6_DEFAULT, &ccm->pll6_cfg);
+ while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_LOCK))
+ ;
+
+ clrsetbits_le32(&ccm->cpu_axi_cfg, CCM_CPU_AXI_APB_MASK | CCM_CPU_AXI_AXI_MASK,
+ CCM_CPU_AXI_DEFAULT_FACTORS);
+
+ writel(CCM_PSI_AHB1_AHB2_DEFAULT, &ccm->psi_ahb1_ahb2_cfg);
+ writel(CCM_AHB3_DEFAULT, &ccm->ahb3_cfg);
+ writel(CCM_APB1_DEFAULT, &ccm->apb1_cfg);
+
+ /*
+ * The mux and factor are set, but the clock will be enabled in
+ * DRAM initialization code.
+ */
+ writel(MBUS_CLK_SRC_PLL6X2 | MBUS_CLK_M(3), &ccm->mbus_cfg);
+}
+#endif
+
+void clock_init_uart(void)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ /* uart clock source is apb2 */
+ writel(APB2_CLK_SRC_OSC24M|
+ APB2_CLK_RATE_N_1|
+ APB2_CLK_RATE_M(1),
+ &ccm->apb2_cfg);
+
+ /* open the clock for uart */
+ setbits_le32(&ccm->uart_gate_reset,
+ 1 << (CONFIG_CONS_INDEX - 1));
+
+ /* deassert uart reset */
+ setbits_le32(&ccm->uart_gate_reset,
+ 1 << (RESET_SHIFT + CONFIG_CONS_INDEX - 1));
+}
+
+#ifdef CONFIG_SPL_BUILD
+void clock_set_pll1(unsigned int clk)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ u32 val;
+
+ /* Do not support clocks < 288MHz as they need factor P */
+ if (clk < 288000000) clk = 288000000;
+
+ /* Switch to 24MHz clock while changing PLL1 */
+ val = readl(&ccm->cpu_axi_cfg);
+ val &= ~CCM_CPU_AXI_MUX_MASK;
+ val |= CCM_CPU_AXI_MUX_OSC24M;
+ writel(val, &ccm->cpu_axi_cfg);
+
+ /* clk = 24*n/p, p is ignored if clock is >288MHz */
+ writel(CCM_PLL1_CTRL_EN | CCM_PLL1_LOCK_EN | CCM_PLL1_CLOCK_TIME_2 |
+ CCM_PLL1_CTRL_N(clk / 24000000), &ccm->pll1_cfg);
+ while (!(readl(&ccm->pll1_cfg) & CCM_PLL1_LOCK)) {}
+
+ /* Switch CPU to PLL1 */
+ val = readl(&ccm->cpu_axi_cfg);
+ val &= ~CCM_CPU_AXI_MUX_MASK;
+ val |= CCM_CPU_AXI_MUX_PLL_CPUX;
+ writel(val, &ccm->cpu_axi_cfg);
+}
+#endif
+
+unsigned int clock_get_pll6(void)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ uint32_t rval = readl(&ccm->pll6_cfg);
+ int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT);
+ int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >>
+ CCM_PLL6_CTRL_DIV1_SHIFT) + 1;
+ int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >>
+ CCM_PLL6_CTRL_DIV2_SHIFT) + 1;
+ /* The register defines PLL6-4X, not plain PLL6 */
+ return 24000000 / 4 * n / div1 / div2;
+}