tree 96f0477552ff68214b03adb54ff14152220ea239
parent 2b90494e05ce846573f3a9c44c966ae8a23302ca
author Felix Radensky <felix@embedded-sol.com> 1243791855 +0300
committer Ben Warren <biggerbadderben@gmail.com> 1244527041 -0700

ppc4xx/net: Fix MDIO clock setup

This patch fixes MDIO clock setup in case when OPB frequency is 100MHz.
Current code assumes that the value of sysinfo.freqOPB is 100000000
when OPB frequency is 100MHz. In reality it is 100000001. As a result
MDIO clock is set to incorrect value, larger than 2.5MHz, thus violating
the standard. This in not a problem on boards equipped with Marvell PHYs
(e.g. Canyonlands), since those PHYs support MDIO clocks up to 8.3MHz,
but can be a problem for other PHYs (e.g. Realtek ones).

Signed-off-by: Felix Radensky <felix@embedded-sol.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>