arm64: renesas: Add Renesas R-Car V4H SPL implementation
Add support for building U-Boot SPL for Renesas R-Car Gen4 R8A779G0 V4H SoC.
The SPL initializes the DBSC5 DRAM controller, RT-VRAM and loads and starts
U-Boot proper on the Cortex-A76 core.
The SoC BootROM can not boot the CA76 core directly, instead the SPL starts
on the CR52 core which immediately brings up the CA76 core, which in turn
starts executing the actual SPL. This is achieved by placing a tiny bit of
precompiled Aarch32 code at the very beginning of the SPL. The code consists
of some 32 instructions, uses APMU to configure CA76 start address to offset
0x80 Bytes from start of the SPL, and uses APMU to start the CA76 core. The
code parts the CR52 core in an endless loop once the CA76 core got started.
The 32 instructions are completely arbitrary number, so is the offset 0x80
Bytes from start of SPL, because 0x80 = 128 decimal and 128 / 4 bytes per
instruction is 32 instructions. The 32 instructions turned out to be enough
to started the CA76 and 0x80 is nicely aligned.
Once the SPL completes hardware initialization, the SPL loads U-Boot proper.
The u-boot.itb proper fitImage contains 64bit build on u-boot-nodtb.bin and
a DT for R8A779G0 V4H White Hawk board and is generated by binman. The
u-boot.itb is loaded from SPI NOR offset 0x80000.
In order to install this setup on an existing R8A779G0 V4H White Hawk board,
build using r8a779g0_whitehawk_defconfig, generate SPI NOR image flash.bin
and write flash.bin to SPI NOR offset 0x0 . Finally, configure board MD pin
switches according to the R8A779G0 V4H White Hawk board documentation for
40 MHz SPI NOR boot using DMA and restart the board.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
diff --git a/arch/arm/dts/r8a779g0-u-boot.dtsi b/arch/arm/dts/r8a779g0-u-boot.dtsi
index 42df321..90f0212 100644
--- a/arch/arm/dts/r8a779g0-u-boot.dtsi
+++ b/arch/arm/dts/r8a779g0-u-boot.dtsi
@@ -7,12 +7,160 @@
#include "r8a779x-u-boot.dtsi"
+/ {
+ binman: binman {
+ multiple-images;
+
+ section {
+ filename = "flash.bin";
+ pad-byte = <0xff>;
+
+ /* Offset 0x0000 set to 0x0000_0000 */
+ fill@0 {
+ offset = <0x0>;
+ size = <0x4>;
+ fill-byte = [00];
+ };
+
+ /* Offset 0x300c set to 0x0000_0000 */
+ fill@300c {
+ offset = <0x300c>;
+ size = <0x4>;
+ fill-byte = [00];
+ };
+
+ /* Offset 0x3154 set to 0xeb21_0000 */
+ fill@3154 {
+ offset = <0x3154>;
+ size = <0x2>;
+ fill-byte = [00];
+ };
+
+ fill@3156 {
+ offset = <0x3156>;
+ size = <0x1>;
+ fill-byte = [21];
+ };
+
+ fill@3157 {
+ offset = <0x3157>;
+ size = <0x1>;
+ fill-byte = [eb];
+ };
+
+ /* Offset 0x3264 set to 0x0003_b000 */
+ fill@3264 {
+ offset = <0x3264>;
+ size = <0x1>;
+ fill-byte = [00];
+ };
+
+ fill@3265 {
+ offset = <0x3265>;
+ size = <0x1>;
+ fill-byte = [b0];
+ };
+
+ fill@3266 {
+ offset = <0x3266>;
+ size = <0x1>;
+ fill-byte = [03];
+ };
+
+ fill@3267 {
+ offset = <0x3267>;
+ size = <0x1>;
+ fill-byte = [00];
+ };
+
+ u-boot-spl {
+ offset = <0x40000>;
+ align-end = <4>;
+ };
+
+ u-boot {
+ offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>;
+ filename = "u-boot.itb";
+
+ fit {
+ description = "U-Boot mainline";
+ fit,fdt-list = "of-list";
+ #address-cells = <1>;
+
+ images {
+ uboot {
+ arch = "arm64";
+ compression = "none";
+ description = "U-Boot (64-bit)";
+ type = "standalone";
+ /*
+ * This is in DRAM. We cannot
+ * use TEXT_BASE here because
+ * this system uses PIE build
+ * and TEXT_BASE=0x0 .
+ */
+ entry = <0x44100000>;
+ load = <0x44100000>;
+
+ uboot-blob {
+ filename = "u-boot-nodtb.bin";
+ type = "blob-ext";
+ };
+ };
+
+ @fdt-SEQ {
+ compression = "none";
+ description = "NAME";
+ type = "flat_dt";
+
+ uboot-fdt-blob {
+ filename = "u-boot.dtb";
+ type = "blob-ext";
+ };
+ };
+ };
+
+ configurations {
+ default = "@config-DEFAULT-SEQ";
+
+ @config-SEQ {
+ description = "NAME";
+ fdt = "fdt-SEQ";
+ firmware = "uboot";
+ };
+ };
+ };
+ };
+ };
+ };
+};
+
+&cpg {
+ bootph-all;
+};
+
+&extalr_clk {
+ bootph-all;
+};
+
+&hscif0 {
+ bootph-all;
+};
+
+&hscif0_pins {
+ bootph-all;
+};
+
+&pfc {
+ bootph-all;
+};
+
&rpc {
bank-width = <2>;
num-cs = <1>;
};
-&extalr_clk {
+&rst {
bootph-all;
};
diff --git a/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi b/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi
index 531767c..85e3220 100644
--- a/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi
+++ b/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi
@@ -22,8 +22,14 @@
};
&rpc {
+ bootph-all;
flash@0 {
+ bootph-all;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};
};
+
+&qspi0_pins {
+ bootph-all;
+};
diff --git a/arch/arm/mach-renesas/Kconfig.rcar4 b/arch/arm/mach-renesas/Kconfig.rcar4
index e80dce1..c2812fd 100644
--- a/arch/arm/mach-renesas/Kconfig.rcar4
+++ b/arch/arm/mach-renesas/Kconfig.rcar4
@@ -17,6 +17,16 @@
config R8A779G0
bool "Renesas SoC R8A779G0"
select GICV3
+ select BINMAN
+ select SUPPORT_SPL
+ imply SPL
+ imply SPL_BOARD_INIT
+ imply SPL_LIBCOMMON_SUPPORT
+ imply SPL_LIBGENERIC_SUPPORT
+ imply SPL_SERIAL
+ imply SPL_SYS_MALLOC_SIMPLE
+ imply SPL_TINY_MEMSET
+ imply SPL_USE_TINY_PRINTF
imply CLK_R8A779G0
imply PINCTRL_PFC_R8A779G0
diff --git a/arch/arm/mach-renesas/include/mach/boot0.h b/arch/arm/mach-renesas/include/mach/boot0.h
index 2128ecc..1bbfec9 100644
--- a/arch/arm/mach-renesas/include/mach/boot0.h
+++ b/arch/arm/mach-renesas/include/mach/boot0.h
@@ -6,6 +6,7 @@
#ifndef __BOOT0_H
#define __BOOT0_H
+#if IS_ENABLED(CONFIG_RCAR_GEN2)
_start:
ARM_VECTORS
@@ -19,5 +20,62 @@
.word 0x0badc0d3;
.word 0x0badc0d3;
#endif
+#endif
+
+#if IS_ENABLED(CONFIG_R8A779G0)
+
+#ifdef CONFIG_XPL_BUILD
+ /* r1=0xe6170800 */
+ .inst 0xe3a004e6 /* mov r0, #0xe6000000 */
+ .inst 0xe3801817 /* orr r1, r0, #0x170000 */
+ .inst 0xe3811b02 /* orr r1, r1, #0x800 */
+
+ /* r0=0xe6280000 */
+ .inst 0xe380070a /* orr r0, r0, #0x280000 */
+
+ /* APMU_RVBARPLC0 = (address of 'b reset' below) | CA_CORE0_VLD_RVBARP */
+ .inst 0xe28f3068 /* add r3, pc, #0x68 */
+ .inst 0xe3833001 /* orr r3, r3, #1 */
+ .inst 0xe5813038 /* str r3, [r1, #56] @ 0x38 */
+
+ /* APMU_RVBARPHC0 = 0 */
+ .inst 0xe3a03000 /* mov r3, #0 */
+ .inst 0xe581303c /* str r3, [r1, #60] @ 0x3c */
+
+ /* PRR & 0xff00 ?= 0x5c00, test if this is V4H or V4M */
+ .inst 0xe3a024ff /* mov r2, #0xff000000 */
+ .inst 0xe382260f /* orr r2, r2, #0xf00000 */
+ .inst 0xe5923044 /* ldr r3, [r2, #68] @ 0x44 */
+ .inst 0xe2033cff /* and r3, r3, #0xff00 */
+ .inst 0xe3530b17 /* cmp r3, #0x5c00 */
+ .inst 0x1a00000a /* bne 68 <reset-0x18> */
+ /* if (SoC is V4H) { */
+ /* AP_CORE_APSREG_AP_CLUSTER_N_AUX0 |= AP_CORE_APSREG_AP_CLUSTER_N_AUX0_INIT */
+ .inst 0xe5903010 /* ldr r3, [r0, #16] */
+ .inst 0xe3833003 /* orr r3, r3, #3 */
+ .inst 0xe5803010 /* str r3, [r0, #16] */
+ /* AP_CORE_APSREG_CCI500_AUX |= AP_CORE_APSREG_CCI500_AUX_ACTDIS */
+ .inst 0xe3800a09 /* orr r0, r0, #36864 @ 0x9000 */
+ .inst 0xe5903010 /* ldr r3, [r0, #16] */
+ .inst 0xe3833001 /* orr r3, r3, #1 */
+ .inst 0xe5803010 /* str r3, [r0, #16] */
+ /* AP_CORE_APSREG_P_CCI500_AUX |= AP_CORE_APSREG_P_CCI500_AUX_ASPRTM */
+ .inst 0xe3800802 /* orr r0, r0, #131072 @ 0x20000 */
+ .inst 0xe5903010 /* ldr r3, [r0, #16] */
+ .inst 0xe3833002 /* orr r3, r3, #2 */
+ .inst 0xe5803010 /* str r3, [r0, #16] */
+ /* } */
+ /* APMU_PWRCTRLC0 = CA_CORE0_WUP_REQ */
+ .inst 0xe3a03001 /* mov r3, #1 */
+ .inst 0xe5813000 /* str r3, [r1] */
+ /* Endless loop */
+ .inst 0xe1a00000 /* nop @ (mov r0, r0) */
+ .inst 0xeafffffd /* b 70 <reset-0x10> */
+ .inst 0xe1a00000 /* nop @ (mov r0, r0) */
+ .inst 0xe1a00000 /* nop @ (mov r0, r0) */
+ /* Offset 0x80 */
+#endif
+ b reset
+#endif
#endif /* __BOOT0_H */