| commit | 4f81bd3ef08ca990bd5654cef9e1e2c6dbbe9638 | [log] [tgz] |
|---|---|---|
| author | Benoît Thébaudeau <benoit.thebaudeau@advansee.com> | Wed Jan 30 11:19:16 2013 +0000 |
| committer | Stefano Babic <sbabic@denx.de> | Tue Feb 12 13:52:31 2013 +0100 |
| tree | 01d05a71d77785352afd7c0e006f26b1effa0c19 | |
| parent | 6e4651df7df1bb5eda475bc75a6a5187b4e71e70 [diff] |
imx: mx6q DDR3 init: Fix RST_to_CKE MMDC1_MDOR.RST_to_CKE should be set to 500 µs according to the JEDEC specification for DDR3. With a cycle of 15.258 µs, this gives 33 cycles encoded as 0x23 for the bit-field MMDC1_MDOR[5:0]. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>