ram: rockchip: Add rv1126 ddr driver support
Add DDR driver for Rockchip RV1126 SoC.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index a14b37c..e53e5a9 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -15,6 +15,210 @@
#define MIN(a, b) (((a) > (b)) ? (b) : (a))
#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+/* get head info for initial */
+#define DDR_FREQ_F0_SHIFT (0)
+#define DDR_FREQ_F1_SHIFT (12)
+#define DDR_FREQ_F2_SHIFT (0)
+#define DDR_FREQ_F3_SHIFT (12)
+#define DDR_FREQ_F4_SHIFT (0)
+#define DDR_FREQ_F5_SHIFT (12)
+#define DDR_FREQ_MASK (0xfff)
+
+#define UART_INFO_ID_SHIFT (28)
+#define UART_INFO_IOMUX_SHIFT (24)
+#define UART_INFO_BAUD_SHIFT (0)
+#define UART_INFO_ID(n) (((n) >> 28) & 0xf)
+#define UART_INFO_IOMUX(n) (((n) >> 24) & 0xf)
+#define UART_INFO_BAUD(n) ((n) & 0xffffff)
+
+/* g_ch_info[15:0]: g_stdby_idle */
+#define STANDBY_IDLE(n) ((n) & 0xffff)
+
+#define SR_INFO(n) (((n) >> 16) & 0xffff)
+#define PD_INFO(n) ((n) & 0xffff)
+
+#define FIRST_SCAN_CH(n) (((n) >> 28) & 0xf)
+#define CHANNEL_MASK(n) (((n) >> 24) & 0xf)
+#define STRIDE_TYPE(n) (((n) >> 16) & 0xff)
+
+#define DDR_2T_INFO(n) ((n) & 1)
+#define PLL_SSMOD_SPREAD(n) (((n) >> 1) & 0xff)
+#define PLL_SSMOD_DIV(n) (((n) >> 9) & 0xff)
+#define PLL_SSMOD_DOWNSPREAD(n) (((n) >> 17) & 0x3)
+
+/* sdram_head_info_v2 define */
+/* for *_drv_odten and *_drv_odtoff */
+#define PHY_DQ_DRV_SHIFT 0
+#define PHY_CA_DRV_SHIFT 8
+#define PHY_CLK_DRV_SHIFT 16
+#define DRAM_DQ_DRV_SHIFT 24
+#define DRV_INFO_PHY_DQ_DRV(n) ((n) & 0xff)
+#define DRV_INFO_PHY_CA_DRV(n) (((n) >> PHY_CA_DRV_SHIFT) & 0xff)
+#define DRV_INFO_PHY_CLK_DRV(n) (((n) >> PHY_CLK_DRV_SHIFT) & 0xff)
+#define DRV_INFO_DRAM_DQ_DRV(n) (((n) >> DRAM_DQ_DRV_SHIFT) & 0xff)
+
+/* for *_odt_info */
+#define DRAM_ODT_SHIFT 0
+#define PHY_ODT_SHIFT 8
+#define PHY_ODT_PUUP_EN_SHIFT 18
+#define PHY_ODT_PUDN_EN_SHIFT 19
+#define ODT_INFO_DRAM_ODT(n) (((n) >> DRAM_ODT_SHIFT) & 0xff)
+#define ODT_INFO_PHY_ODT(n) (((n) >> PHY_ODT_SHIFT) & 0x3ff)
+#define ODT_INFO_PULLUP_EN(n) (((n) >> PHY_ODT_PUUP_EN_SHIFT) & 1)
+#define ODT_INFO_PULLDOWN_EN(n) (((n) >> PHY_ODT_PUDN_EN_SHIFT) & 1)
+
+/* for *odt_en_freq; */
+#define DRAM_ODT_EN_FREQ_SHIFT 0
+#define PHY_ODT_EN_FREQ_SHIFT 12
+#define DRAMODT_EN_FREQ(n) (((n) >> DRAM_ODT_EN_FREQ_SHIFT) & \
+ 0xfff)
+#define PHYODT_EN_FREQ(n) (((n) >> PHY_ODT_EN_FREQ_SHIFT) & 0xfff)
+
+#define PHY_DQ_SR_SHIFT 0
+#define PHY_CA_SR_SHIFT 8
+#define PHY_CLK_SR_SHIFT 16
+#define DQ_SR_INFO(n) (((n) >> PHY_DQ_SR_SHIFT) & 0xff)
+#define CA_SR_INFO(n) (((n) >> PHY_CA_SR_SHIFT) & 0xff)
+#define CLK_SR_INFO(n) (((n) >> PHY_CLK_SR_SHIFT) & 0xff)
+
+/* LP4 */
+#define LP4_CA_ODT_SHIFT (18)
+#define LP4_DRV_PU_CAL_ODTEN_SHIFT (26)
+#define LP4_DRV_PU_CAL_ODTOFF_SHIFT (27)
+#define PHY_LP4_DRV_PULLDOWN_EN_ODTEN_SHIFT (28)
+#define PHY_LP4_DRV_PULLDOWN_EN_ODTOFF_SHIFT (29)
+#define ODT_INFO_LP4_CA_ODT(n) (((n) >> LP4_CA_ODT_SHIFT) & \
+ 0xff)
+#define LP4_DRV_PU_CAL_ODTEN(n) \
+ (((n) >> LP4_DRV_PU_CAL_ODTEN_SHIFT) & 1)
+#define LP4_DRV_PU_CAL_ODTOFF(n) \
+ (((n) >> LP4_DRV_PU_CAL_ODTOFF_SHIFT) & 1)
+#define PHY_LP4_DRV_PULLDOWN_EN_ODTEN(n) \
+ (((n) >> PHY_LP4_DRV_PULLDOWN_EN_ODTEN_SHIFT) & 1)
+#define PHY_LP4_DRV_PULLDOWN_EN_ODTOFF(n) \
+ (((n) >> PHY_LP4_DRV_PULLDOWN_EN_ODTOFF_SHIFT) & 1)
+
+#define PHY_LP4_CS_DRV_ODTEN_SHIFT (0)
+#define PHY_LP4_CS_DRV_ODTOFF_SHIFT (8)
+#define LP4_ODTE_CK_SHIFT (16)
+#define LP4_ODTE_CS_EN_SHIFT (17)
+#define LP4_ODTD_CA_EN_SHIFT (18)
+#define PHY_LP4_CS_DRV_ODTEN(n) \
+ (((n) >> PHY_LP4_CS_DRV_ODTEN_SHIFT) & 0xff)
+#define PHY_LP4_CS_DRV_ODTOFF(n) \
+ (((n) >> PHY_LP4_CS_DRV_ODTOFF_SHIFT) & 0xff)
+#define LP4_ODTE_CK_EN(n) (((n) >> LP4_ODTE_CK_SHIFT) & 1)
+#define LP4_ODTE_CS_EN(n) (((n) >> LP4_ODTE_CS_EN_SHIFT) & 1)
+#define LP4_ODTD_CA_EN(n) (((n) >> LP4_ODTD_CA_EN_SHIFT) & 1)
+
+#define PHY_LP4_DQ_VREF_SHIFT (0)
+#define LP4_DQ_VREF_SHIFT (10)
+#define LP4_CA_VREF_SHIFT (20)
+
+#define PHY_LP4_DQ_VREF(n) \
+ (((n) >> PHY_LP4_DQ_VREF_SHIFT) & 0x3ff)
+#define LP4_DQ_VREF(n) (((n) >> LP4_DQ_VREF_SHIFT) & 0x3ff)
+#define LP4_CA_VREF(n) (((n) >> LP4_CA_VREF_SHIFT) & 0x3ff)
+
+#define LP4_DQ_ODT_EN_FREQ_SHIFT (0)
+#define PHY_LP4_ODT_EN_FREQ_SHIFT (12)
+#define LP4_CA_ODT_EN_FREQ_SHIFT (0)
+#define PHY_LP4_ODT_EN_FREQ(n) \
+ (((n) >> PHY_LP4_ODT_EN_FREQ_SHIFT) & 0xfff)
+#define LP4_DQ_ODT_EN_FREQ(n) \
+ (((n) >> LP4_DQ_ODT_EN_FREQ_SHIFT) & 0xfff)
+#define LP4_CA_ODT_EN_FREQ(n) \
+ (((n) >> LP4_CA_ODT_EN_FREQ_SHIFT) & 0xfff)
+
+struct sdram_head_info_v0 {
+ u32 start_tag;
+ u32 version_info;
+ u32 gcpu_gen_freq;
+ u32 g_d2_lp2_freq;
+ u32 g_d3_lp3_freq;
+ u32 g_d4_lp4_freq;
+ u32 g_uart_info;
+ u32 g_sr_pd_idle;
+ u32 g_ch_info;
+ u32 g_2t_info;
+ u32 reserved11;
+ u32 reserved12;
+ u32 reserved13;
+};
+
+struct index_info {
+ u8 offset;
+ u8 size;
+};
+
+struct sdram_head_info_index_v2 {
+ u32 start_tag;
+ u32 version_info;
+ struct index_info cpu_gen_index;
+ struct index_info global_index;
+
+ struct index_info ddr2_index;
+ struct index_info ddr3_index;
+
+ struct index_info ddr4_index;
+ struct index_info ddr5_index;
+
+ struct index_info lp2_index;
+ struct index_info lp3_index;
+
+ struct index_info lp4_index;
+ struct index_info lp5_index;
+
+ struct index_info skew_index;
+ struct index_info dq_map_index;
+
+ struct index_info lp4x_index;
+ struct index_info reserved;
+};
+
+struct global_info {
+ u32 uart_info;
+ u32 sr_pd_info;
+ u32 ch_info;
+ u32 info_2t;
+ u32 reserved[4];
+};
+
+struct ddr2_3_4_lp2_3_info {
+ u32 ddr_freq0_1;
+ u32 ddr_freq2_3;
+ u32 ddr_freq4_5;
+ u32 drv_when_odten;
+ u32 drv_when_odtoff;
+ u32 odt_info;
+ u32 odten_freq;
+ u32 sr_when_odten;
+ u32 sr_when_odtoff;
+};
+
+struct lp4_info {
+ u32 ddr_freq0_1;
+ u32 ddr_freq2_3;
+ u32 ddr_freq4_5;
+ u32 drv_when_odten;
+ u32 drv_when_odtoff;
+ u32 odt_info;
+ u32 dq_odten_freq;
+ u32 sr_when_odten;
+ u32 sr_when_odtoff;
+ u32 ca_odten_freq;
+ u32 cs_drv_ca_odt_info;
+ u32 vref_when_odten;
+ u32 vref_when_odtoff;
+};
+
+struct dq_map_info {
+ u32 byte_map[2];
+ u32 lp3_dq0_7_map;
+ u32 lp2_dq0_7_map;
+ u32 ddr4_dq_map[4];
+};
+
struct sdram_cap_info {
unsigned int rank;
/* dram column number, 0 means this channel is invalid */
@@ -46,6 +250,14 @@
};
#define DDR_SYS_REG_VERSION (0x2)
+/* for modify tRFC and related timing */
+#define DIE_CAP_512MBIT 64
+#define DIE_CAP_1GBIT 128
+#define DIE_CAP_2GBIT 256
+#define DIE_CAP_4GBIT 512
+#define DIE_CAP_8GBIT 1024
+#define DIE_CAP_16GBIT 2048
+#define DIE_CAP_32GBIT 4096
/*
* sys_reg2 bitfield struct
* [31] row_3_4_ch1