Merge https://source.denx.de/u-boot/custodians/u-boot-cfi-flash
- mtd: cfi: Fix PPB lock status readout (Marek)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index aec5020..a5cae01 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -236,7 +236,9 @@
armada-xp-gp.dtb \
armada-xp-maxbcm.dtb \
armada-xp-synology-ds414.dtb \
- armada-xp-theadorable.dtb
+ armada-xp-theadorable.dtb \
+ cn9130-crb-A.dtb \
+ cn9130-crb-B.dtb
dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \
uniphier-ld11-global.dtb \
diff --git a/arch/arm/dts/armada-3720-db.dts b/arch/arm/dts/armada-3720-db.dts
index 1b1b66b..42e7ddd 100644
--- a/arch/arm/dts/armada-3720-db.dts
+++ b/arch/arm/dts/armada-3720-db.dts
@@ -70,13 +70,13 @@
&comphy {
phy0 {
- phy-type = <PHY_TYPE_PEX0>;
- phy-speed = <PHY_SPEED_2_5G>;
+ phy-type = <COMPHY_TYPE_USB3_HOST0>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
phy1 {
- phy-type = <PHY_TYPE_USB3_HOST0>;
- phy-speed = <PHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_PEX0>;
+ phy-speed = <COMPHY_SPEED_2_5G>;
};
};
diff --git a/arch/arm/dts/armada-3720-espressobin.dts b/arch/arm/dts/armada-3720-espressobin.dts
index 96a4b3d..d86d8f0 100644
--- a/arch/arm/dts/armada-3720-espressobin.dts
+++ b/arch/arm/dts/armada-3720-espressobin.dts
@@ -83,18 +83,18 @@
&comphy {
max-lanes = <3>;
phy0 {
- phy-type = <PHY_TYPE_USB3_HOST0>;
- phy-speed = <PHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_USB3_HOST0>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
phy1 {
- phy-type = <PHY_TYPE_PEX0>;
- phy-speed = <PHY_SPEED_2_5G>;
+ phy-type = <COMPHY_TYPE_PEX0>;
+ phy-speed = <COMPHY_SPEED_2_5G>;
};
phy2 {
- phy-type = <PHY_TYPE_SATA0>;
- phy-speed = <PHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_SATA0>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
};
diff --git a/arch/arm/dts/armada-3720-turris-mox.dts b/arch/arm/dts/armada-3720-turris-mox.dts
index 974270c..8e0ebf5 100644
--- a/arch/arm/dts/armada-3720-turris-mox.dts
+++ b/arch/arm/dts/armada-3720-turris-mox.dts
@@ -73,18 +73,18 @@
&comphy {
max-lanes = <3>;
phy0 {
- phy-type = <PHY_TYPE_SGMII1>;
- phy-speed = <PHY_SPEED_3_125G>;
+ phy-type = <COMPHY_TYPE_SGMII1>;
+ phy-speed = <COMPHY_SPEED_3_125G>;
};
phy1 {
- phy-type = <PHY_TYPE_PEX0>;
- phy-speed = <PHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_PEX0>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
phy2 {
- phy-type = <PHY_TYPE_USB3_HOST0>;
- phy-speed = <PHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_USB3_HOST0>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
};
diff --git a/arch/arm/dts/armada-3720-uDPU.dts b/arch/arm/dts/armada-3720-uDPU.dts
index 7f4b822..4b30f3c 100644
--- a/arch/arm/dts/armada-3720-uDPU.dts
+++ b/arch/arm/dts/armada-3720-uDPU.dts
@@ -108,18 +108,19 @@
&comphy {
phy0 {
- phy-type = <PHY_TYPE_SGMII1>;
- phy-speed = <PHY_SPEED_3_125G>;
+ phy-type = <COMPHY_TYPE_SGMII1>;
+ phy-speed = <COMPHY_SPEED_1_25G>;
};
- phy1 {
- phy-type = <PHY_TYPE_SGMII0>;
- phy-speed = <PHY_SPEED_3_125G>;
- };
- phy2 {
- phy-type = <PHY_TYPE_USB3_HOST1>;
- phy-speed = <PHY_SPEED_5G>;
- };
+ phy1 {
+ phy-type = <COMPHY_TYPE_SGMII0>;
+ phy-speed = <COMPHY_SPEED_1_25G>;
+ };
+
+ phy2 {
+ phy-type = <COMPHY_TYPE_USB3_HOST1>;
+ phy-speed = <COMPHY_SPEED_5G>;
+ };
};
ð0 {
diff --git a/arch/arm/dts/armada-7040-db-nand.dts b/arch/arm/dts/armada-7040-db-nand.dts
index 3a9df21..ccf470b 100644
--- a/arch/arm/dts/armada-7040-db-nand.dts
+++ b/arch/arm/dts/armada-7040-db-nand.dts
@@ -1,43 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Marvell Technology Group Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * Copyright (C) 2016- 2021 Marvell International Ltd.
*/
/*
@@ -58,8 +21,8 @@
};
aliases {
- i2c0 = &cpm_i2c0;
- spi0 = &cpm_spi1;
+ i2c0 = &cp0_i2c0;
+ spi0 = &cp0_spi1;
};
memory@00000000 {
@@ -83,18 +46,18 @@
};
-&cpm_pcie2 {
+&cp0_pcie2 {
status = "okay";
};
-&cpm_i2c0 {
+&cp0_i2c0 {
pinctrl-names = "default";
- pinctrl-0 = <&cpm_i2c0_pins>;
+ pinctrl-0 = <&cp0_i2c0_pins>;
status = "okay";
clock-frequency = <100000>;
};
-&cpm_pinctl {
+&cp0_pinctl {
/* MPP Bus:
* AUDIO [0-5]
* GBE [6-11]
@@ -122,9 +85,9 @@
0xe 0xe 0x0>;
};
-&cpm_spi1 {
+&cp0_spi1 {
pinctrl-names = "default";
- pinctrl-0 = <&cpm_spi0_pins>;
+ pinctrl-0 = <&cp0_spi0_pins>;
status = "disabled";
spi-flash@0 {
@@ -152,59 +115,59 @@
};
};
-&cpm_sata0 {
+&cp0_sata0 {
status = "okay";
};
-&cpm_usb3_0 {
+&cp0_usb3_0 {
status = "okay";
};
-&cpm_usb3_1 {
+&cp0_usb3_1 {
status = "okay";
};
-&cpm_comphy {
+&cp0_comphy {
phy0 {
- phy-type = <PHY_TYPE_SGMII2>;
- phy-speed = <PHY_SPEED_3_125G>;
+ phy-type = <COMPHY_TYPE_SGMII2>;
+ phy-speed = <COMPHY_SPEED_3_125G>;
};
phy1 {
- phy-type = <PHY_TYPE_USB3_HOST0>;
- phy-speed = <PHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_USB3_HOST0>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
phy2 {
- phy-type = <PHY_TYPE_SGMII0>;
- phy-speed = <PHY_SPEED_1_25G>;
+ phy-type = <COMPHY_TYPE_SGMII0>;
+ phy-speed = <COMPHY_SPEED_1_25G>;
};
phy3 {
- phy-type = <PHY_TYPE_SATA1>;
- phy-speed = <PHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_SATA1>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
phy4 {
- phy-type = <PHY_TYPE_USB3_HOST1>;
- phy-speed = <PHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_USB3_HOST1>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
phy5 {
- phy-type = <PHY_TYPE_PEX2>;
- phy-speed = <PHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_PEX2>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
};
-&cpm_nand {
+&cp0_nand {
status = "okay";
};
-&cpm_utmi0 {
+&cp0_utmi0 {
status = "okay";
};
-&cpm_utmi1 {
+&cp0_utmi1 {
status = "okay";
};
@@ -215,7 +178,7 @@
non-removable;
};
-&cpm_sdhci0 {
+&cp0_sdhci0 {
status = "okay";
bus-width = <4>;
no-1-8-v;
diff --git a/arch/arm/dts/armada-7040-db.dts b/arch/arm/dts/armada-7040-db.dts
index cfd2b4b..b158f92 100644
--- a/arch/arm/dts/armada-7040-db.dts
+++ b/arch/arm/dts/armada-7040-db.dts
@@ -1,43 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * Copyright (C) 2016- 2021 Marvell International Ltd.
*/
/*
@@ -57,8 +20,8 @@
};
aliases {
- i2c0 = &cpm_i2c0;
- spi0 = &cpm_spi1;
+ i2c0 = &cp0_i2c0;
+ spi0 = &cp0_spi1;
};
memory@00000000 {
@@ -82,18 +45,18 @@
};
-&cpm_pcie2 {
+&cp0_pcie2 {
status = "okay";
};
-&cpm_i2c0 {
+&cp0_i2c0 {
pinctrl-names = "default";
- pinctrl-0 = <&cpm_i2c0_pins>;
+ pinctrl-0 = <&cp0_i2c0_pins>;
status = "okay";
clock-frequency = <100000>;
};
-&cpm_pinctl {
+&cp0_pinctl {
/* MPP Bus:
* TDM [0-11]
* SPI [13-16]
@@ -115,9 +78,9 @@
0xE 0xE 0xE >;
};
-&cpm_spi1 {
+&cp0_spi1 {
pinctrl-names = "default";
- pinctrl-0 = <&cpm_spi0_pins>;
+ pinctrl-0 = <&cp0_spi0_pins>;
status = "okay";
spi-flash@0 {
@@ -145,54 +108,55 @@
};
};
-&cpm_sata0 {
+&cp0_sata0 {
status = "okay";
};
-&cpm_usb3_0 {
+&cp0_usb3_0 {
status = "okay";
};
-&cpm_usb3_1 {
+&cp0_usb3_1 {
status = "okay";
};
-&cpm_comphy {
+&cp0_comphy {
phy0 {
- phy-type = <PHY_TYPE_SGMII1>;
- phy-speed = <PHY_SPEED_1_25G>;
+ phy-type = <COMPHY_TYPE_SGMII1>;
+ phy-speed = <COMPHY_SPEED_1_25G>;
};
phy1 {
- phy-type = <PHY_TYPE_USB3_HOST0>;
- phy-speed = <PHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_USB3_HOST0>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
phy2 {
- phy-type = <PHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI0>;
+ phy-speed = <COMPHY_SPEED_10_3125G>;
};
phy3 {
- phy-type = <PHY_TYPE_SATA1>;
- phy-speed = <PHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_SATA1>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
phy4 {
- phy-type = <PHY_TYPE_USB3_HOST1>;
- phy-speed = <PHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_USB3_HOST1>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
phy5 {
- phy-type = <PHY_TYPE_PEX2>;
- phy-speed = <PHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_PEX2>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
};
-&cpm_utmi0 {
+&cp0_utmi0 {
status = "okay";
};
-&cpm_utmi1 {
+&cp0_utmi1 {
status = "okay";
};
@@ -203,14 +167,14 @@
non-removable;
};
-&cpm_sdhci0 {
+&cp0_sdhci0 {
status = "okay";
bus-width = <4>;
no-1-8-v;
non-removable;
};
-&cpm_mdio {
+&cp0_mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
@@ -219,22 +183,22 @@
};
};
-&cpm_ethernet {
+&cp0_ethernet {
status = "okay";
};
-&cpm_eth0 {
+&cp0_eth0 {
status = "okay";
phy-mode = "sfi"; /* lane-2 */
};
-&cpm_eth1 {
+&cp0_eth1 {
status = "okay";
phy = <&phy0>;
phy-mode = "sgmii";
};
-&cpm_eth2 {
+&cp0_eth2 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
diff --git a/arch/arm/dts/armada-7040.dtsi b/arch/arm/dts/armada-7040.dtsi
index b5be0c4..039d30c 100644
--- a/arch/arm/dts/armada-7040.dtsi
+++ b/arch/arm/dts/armada-7040.dtsi
@@ -1,43 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * Copyright (C) 2016- 2021 Marvell International Ltd.
*/
/*
@@ -46,11 +9,57 @@
*/
#include <dt-bindings/gpio/gpio.h>
-#include "armada-ap806-quad.dtsi"
-#include "armada-cp110-master.dtsi"
+#include "armada-common.dtsi"
+#include "armada-8k.dtsi"
+#include "armada-ap806.dtsi"
+#include "armada-ap80x-quad.dtsi"
+
+/* CP110-0 Settings */
+#define CP110_NAME cp0
+#define CP110_NUM 0
+
+#include "armada-cp110.dtsi"
+
+#undef CP110_NAME
+#undef CP110_NUM
/ {
model = "Marvell Armada 7040";
compatible = "marvell,armada7040", "marvell,armada-ap806-quad",
"marvell,armada-ap806";
};
+
+&cp0_pinctl {
+ compatible = "marvell,mvebu-pinctrl", "marvell,7k-pinctrl";
+ bank-name ="cp0-110";
+
+ cp0_i2c0_pins: cp0-i2c-pins-0 {
+ marvell,pins = < 37 38 >;
+ marvell,function = <2>;
+ };
+ cp0_i2c1_pins: cp0-i2c-pins-1 {
+ marvell,pins = < 35 36 >;
+ marvell,function = <2>;
+ };
+ cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
+ marvell,pins = < 0 1 2 3 4 5 6 7 8 9 10 11>;
+ marvell,function = <3>;
+ };
+ cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
+ marvell,pins = < 44 45 46 47 48 49 50 51
+ 52 53 54 55 >;
+ marvell,function = <1>;
+ };
+ cp0_pca0_pins: cp0-pca0_pins {
+ marvell,pins = <62>;
+ marvell,function = <0>;
+ };
+ cp0_sdhci_pins: cp0-sdhi-pins-0 {
+ marvell,pins = < 56 57 58 59 60 61 >;
+ marvell,function = <14>;
+ };
+ cp0_spi0_pins: cp0-spi-pins-0 {
+ marvell,pins = < 13 14 15 16 >;
+ marvell,function = <3>;
+ };
+};
diff --git a/arch/arm/dts/armada-8020.dtsi b/arch/arm/dts/armada-8020.dtsi
deleted file mode 100644
index 048e5cf..0000000
--- a/arch/arm/dts/armada-8020.dtsi
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Device Tree file for the Armada 8020 SoC, made of an AP806 Dual and
- * two CP110.
- */
-
-#include "armada-ap806-dual.dtsi"
-#include "armada-cp110-master.dtsi"
-#include "armada-cp110-slave.dtsi"
-
-/ {
- model = "Marvell Armada 8020";
- compatible = "marvell,armada8020", "marvell,armada-ap806-dual",
- "marvell,armada-ap806";
-};
diff --git a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts
index 720c950..6a586db 100644
--- a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts
+++ b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts
@@ -15,9 +15,9 @@
};
aliases {
- i2c0 = &cpm_i2c0;
- i2c1 = &cpm_i2c1;
- spi0 = &cps_spi1;
+ i2c0 = &cp0_i2c0;
+ i2c1 = &cp0_i2c1;
+ spi0 = &cp1_spi1;
};
memory@00000000 {
@@ -31,14 +31,14 @@
reg_usb3h0_vbus: usb3-vbus0 {
compatible = "regulator-fixed";
pinctrl-names = "default";
- pinctrl-0 = <&cpm_xhci_vbus_pins>;
+ pinctrl-0 = <&cp0_xhci_vbus_pins>;
regulator-name = "reg-usb3h0-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
startup-delay-us = <300000>;
shutdown-delay-us = <500000>;
regulator-force-boot-off;
- gpio = <&cpm_gpio1 15 GPIO_ACTIVE_LOW>; /* GPIO[47] */
+ gpio = <&cp0_gpio1 15 GPIO_ACTIVE_LOW>; /* GPIO[47] */
};
};
};
@@ -66,7 +66,7 @@
status = "okay";
};
-&cpm_pinctl {
+&cp0_pinctl {
/*
* MPP Bus:
* [0-31] = 0xff: Keep default CP0_shared_pins:
@@ -99,111 +99,111 @@
0 0 0 0 0 0 0xe 0xe 0xe 0xe
0xe 0xe 0 >;
- cpm_pcie_reset_pins: cpm-pcie-reset-pins {
+ cp0_pcie_reset_pins: cp0-pcie-reset-pins {
marvell,pins = < 32 >;
marvell,function = <0>;
};
- cpm_xhci_vbus_pins: cpm-xhci-vbus-pins {
+ cp0_xhci_vbus_pins: cp0-xhci-vbus-pins {
marvell,pins = < 47 >;
marvell,function = <0>;
};
- cps_1g_phy_reset: cps-1g-phy-reset {
+ cp1_1g_phy_reset: cp1-1g-phy-reset {
marvell,pins = < 43 >;
marvell,function = <0>;
};
};
/* uSD slot */
-&cpm_sdhci0 {
+&cp0_sdhci0 {
pinctrl-names = "default";
- pinctrl-0 = <&cpm_sdhci_pins>;
+ pinctrl-0 = <&cp0_sdhci_pins>;
bus-width = <4>;
status = "okay";
};
-&cpm_pcie0 {
+&cp0_pcie0 {
num-lanes = <1>;
pinctrl-names = "default";
- pinctrl-0 = <&cpm_pcie_reset_pins>;
- marvell,reset-gpio = <&cpm_gpio1 0 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&cp0_pcie_reset_pins>;
+ marvell,reset-gpio = <&cp0_gpio1 0 GPIO_ACTIVE_LOW>;
status = "okay";
};
-&cpm_i2c0 {
+&cp0_i2c0 {
pinctrl-names = "default";
- pinctrl-0 = <&cpm_i2c0_pins>;
+ pinctrl-0 = <&cp0_i2c0_pins>;
status = "okay";
clock-frequency = <100000>;
};
-&cpm_i2c1 {
+&cp0_i2c1 {
pinctrl-names = "default";
- pinctrl-0 = <&cpm_i2c1_pins>;
+ pinctrl-0 = <&cp0_i2c1_pins>;
status = "okay";
clock-frequency = <100000>;
};
-&cpm_sata0 {
+&cp0_sata0 {
status = "okay";
};
-&cpm_comphy {
+&cp0_comphy {
/*
* CP0 Serdes Configuration:
* Lane 0: PCIe0 (x1)
* Lane 1: Not connected
- * Lane 2: SFI (10G)
+ * Lane 2: SFI0 (10G)
* Lane 3: Not connected
* Lane 4: USB 3.0 host port1 (can be PCIe)
* Lane 5: Not connected
*/
phy0 {
- phy-type = <PHY_TYPE_PEX0>;
+ phy-type = <COMPHY_TYPE_PEX0>;
};
phy1 {
- phy-type = <PHY_TYPE_UNCONNECTED>;
+ phy-type = <COMPHY_TYPE_UNCONNECTED>;
};
phy2 {
- phy-type = <PHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI0>;
};
phy3 {
- phy-type = <PHY_TYPE_UNCONNECTED>;
+ phy-type = <COMPHY_TYPE_UNCONNECTED>;
};
phy4 {
- phy-type = <PHY_TYPE_USB3_HOST1>;
+ phy-type = <COMPHY_TYPE_USB3_HOST1>;
};
phy5 {
- phy-type = <PHY_TYPE_UNCONNECTED>;
+ phy-type = <COMPHY_TYPE_UNCONNECTED>;
};
};
-&cpm_ethernet {
+&cp0_ethernet {
pinctrl-names = "default";
status = "okay";
};
/* 10G SFI SFP */
-&cpm_eth0 {
+&cp0_eth0 {
status = "okay";
phy-mode = "sfi";
};
-&cps_sata0 {
+&cp1_sata0 {
status = "okay";
};
-&cps_usb3_0 {
+&cp1_usb3_0 {
vbus-supply = <®_usb3h0_vbus>;
status = "okay";
};
-&cps_utmi0 {
+&cp1_utmi0 {
status = "okay";
};
-&cps_pinctl {
+&cp1_pinctl {
/*
* MPP Bus:
* [0-5] TDM
@@ -234,9 +234,9 @@
0xff 0xff 0xff>;
};
-&cps_spi1 {
+&cp1_spi1 {
pinctrl-names = "default";
- pinctrl-0 = <&cps_spi1_pins>;
+ pinctrl-0 = <&cp1_spi1_pins>;
status = "okay";
spi-flash@0 {
@@ -261,7 +261,7 @@
};
};
-&cps_comphy {
+&cp1_comphy {
/*
* CP1 Serdes Configuration:
* Lane 0: SATA 1 (RX swapped). Can be PCIe0
@@ -272,52 +272,52 @@
* Lane 5: SGMII2 - Connected to Topaz switch
*/
phy0 {
- phy-type = <PHY_TYPE_SATA1>;
- phy-invert = <PHY_POLARITY_RXD_INVERT>;
+ phy-type = <COMPHY_TYPE_SATA1>;
+ phy-invert = <COMPHY_POLARITY_RXD_INVERT>;
};
phy1 {
- phy-type = <PHY_TYPE_UNCONNECTED>;
+ phy-type = <COMPHY_TYPE_UNCONNECTED>;
};
phy2 {
- phy-type = <PHY_TYPE_USB3_HOST0>;
+ phy-type = <COMPHY_TYPE_USB3_HOST0>;
};
phy3 {
- phy-type = <PHY_TYPE_SGMII1>;
- phy-speed = <PHY_SPEED_1_25G>;
+ phy-type = <COMPHY_TYPE_SGMII1>;
+ phy-speed = <COMPHY_SPEED_1_25G>;
};
phy4 {
- phy-type = <PHY_TYPE_UNCONNECTED>;
+ phy-type = <COMPHY_TYPE_UNCONNECTED>;
};
phy5 {
- phy-type = <PHY_TYPE_SGMII2>;
- phy-speed = <PHY_SPEED_3_125G>;
+ phy-type = <COMPHY_TYPE_SGMII2>;
+ phy-speed = <COMPHY_SPEED_3_125G>;
};
};
-&cps_mdio {
+&cp1_mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
};
-&cps_ethernet {
+&cp1_ethernet {
pinctrl-names = "default";
- pinctrl-0 = <&cps_1g_phy_reset>;
+ pinctrl-0 = <&cp1_1g_phy_reset>;
status = "okay";
};
/* 1G SGMII */
-&cps_eth1 {
+&cp1_eth1 {
status = "okay";
phy-mode = "sgmii";
phy = <&phy0>;
- phy-reset-gpios = <&cpm_gpio1 11 GPIO_ACTIVE_LOW>;
+ phy-reset-gpios = <&cp0_gpio1 11 GPIO_ACTIVE_LOW>;
};
/* 2.5G to Topaz switch */
-&cps_eth2 {
+&cp1_eth2 {
status = "okay";
phy-mode = "sgmii";
phy-speed = <2500>;
- phy-reset-gpios = <&cps_gpio0 24 GPIO_ACTIVE_LOW>;
+ phy-reset-gpios = <&cp1_gpio0 24 GPIO_ACTIVE_LOW>;
};
diff --git a/arch/arm/dts/armada-8040-db.dts b/arch/arm/dts/armada-8040-db.dts
index 65b30bb..51c2f23 100644
--- a/arch/arm/dts/armada-8040-db.dts
+++ b/arch/arm/dts/armada-8040-db.dts
@@ -1,43 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * Copyright (C) 2016 - 2021 Marvell International Ltd.
*/
/*
@@ -56,8 +19,8 @@
};
aliases {
- i2c0 = &cpm_i2c0;
- spi0 = &cps_spi1;
+ i2c0 = &cp0_i2c0;
+ spi0 = &cp1_spi1;
};
memory@00000000 {
@@ -88,7 +51,7 @@
status = "okay";
};
-&cpm_pinctl {
+&cp0_pinctl {
/* MPP Bus:
* [0-31] = 0xff: Keep default CP0_shared_pins
* [11] CLKOUT_MPP_11 (out)
@@ -116,7 +79,7 @@
0xe 0xe 0xe>;
};
-&cpm_comphy {
+&cp0_comphy {
/* Serdes Configuration:
* Lane 0: PCIe0 (x1)
* Lane 1: SATA0
@@ -126,77 +89,77 @@
* Lane 5: PCIe2 (x1)
*/
phy0 {
- phy-type = <PHY_TYPE_PEX0>;
+ phy-type = <COMPHY_TYPE_PEX0>;
};
phy1 {
- phy-type = <PHY_TYPE_SATA0>;
+ phy-type = <COMPHY_TYPE_SATA0>;
};
phy2 {
- phy-type = <PHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI0>;
};
phy3 {
- phy-type = <PHY_TYPE_SATA1>;
+ phy-type = <COMPHY_TYPE_SATA1>;
};
phy4 {
- phy-type = <PHY_TYPE_USB3_HOST1>;
+ phy-type = <COMPHY_TYPE_USB3_HOST1>;
};
phy5 {
- phy-type = <PHY_TYPE_PEX2>;
+ phy-type = <COMPHY_TYPE_PEX2>;
};
};
/* CON6 on CP0 expansion */
-&cpm_pcie0 {
+&cp0_pcie0 {
status = "okay";
};
-&cpm_pcie1 {
+&cp0_pcie1 {
status = "disabled";
};
/* CON5 on CP0 expansion */
-&cpm_pcie2 {
+&cp0_pcie2 {
status = "okay";
};
-&cpm_i2c0 {
+&cp0_i2c0 {
pinctrl-names = "default";
- pinctrl-0 = <&cpm_i2c0_pins>;
+ pinctrl-0 = <&cp0_i2c0_pins>;
status = "okay";
clock-frequency = <100000>;
};
/* CON4 on CP0 expansion */
-&cpm_sata0 {
+&cp0_sata0 {
status = "okay";
};
/* CON9 on CP0 expansion */
-&cpm_usb3_0 {
+&cp0_usb3_0 {
status = "okay";
};
/* CON10 on CP0 expansion */
-&cpm_usb3_1 {
+&cp0_usb3_1 {
status = "okay";
};
-&cpm_utmi0 {
+&cp0_utmi0 {
status = "okay";
};
-&cpm_utmi1 {
+&cp0_utmi1 {
status = "okay";
};
-&cpm_sdhci0 {
+&cp0_sdhci0 {
pinctrl-names = "default";
- pinctrl-0 = <&cpm_sdhci_pins>;
+ pinctrl-0 = <&cp0_sdhci_pins>;
bus-width = <4>;
status = "okay";
};
-&cps_pinctl {
+&cp1_pinctl {
/* MPP Bus:
* [0-11] RGMII0
* [13-16] SPI1
@@ -215,7 +178,7 @@
0xff 0xff 0xff>;
};
-&cps_comphy {
+&cp1_comphy {
/* Serdes Configuration:
* Lane 0: PCIe0 (x1)
* Lane 1: SATA0
@@ -225,42 +188,42 @@
* Lane 5: PCIe2 (x1)
*/
phy0 {
- phy-type = <PHY_TYPE_PEX0>;
+ phy-type = <COMPHY_TYPE_PEX0>;
};
phy1 {
- phy-type = <PHY_TYPE_SATA0>;
+ phy-type = <COMPHY_TYPE_SATA0>;
};
phy2 {
- phy-type = <PHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI0>;
};
phy3 {
- phy-type = <PHY_TYPE_SATA1>;
+ phy-type = <COMPHY_TYPE_SATA1>;
};
phy4 {
- phy-type = <PHY_TYPE_PEX1>;
+ phy-type = <COMPHY_TYPE_PEX1>;
};
phy5 {
- phy-type = <PHY_TYPE_PEX2>;
+ phy-type = <COMPHY_TYPE_PEX2>;
};
};
/* CON6 on CP1 expansion */
-&cps_pcie0 {
+&cp1_pcie0 {
status = "okay";
};
-&cps_pcie1 {
+&cp1_pcie1 {
status = "okay";
};
/* CON5 on CP1 expansion */
-&cps_pcie2 {
+&cp1_pcie2 {
status = "okay";
};
-&cps_spi1 {
+&cp1_spi1 {
pinctrl-names = "default";
- pinctrl-0 = <&cps_spi1_pins>;
+ pinctrl-0 = <&cp1_spi1_pins>;
status = "okay";
spi-flash@0 {
@@ -288,35 +251,35 @@
};
/* CON4 on CP1 expansion */
-&cps_sata0 {
+&cp1_sata0 {
status = "okay";
};
/* CON9 on CP1 expansion */
-&cps_usb3_0 {
+&cp1_usb3_0 {
status = "okay";
};
/* CON10 on CP1 expansion */
-&cps_usb3_1 {
+&cp1_usb3_1 {
status = "okay";
};
-&cps_utmi0 {
+&cp1_utmi0 {
status = "okay";
};
-&cpm_mdio {
+&cp0_mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
-&cpm_ethernet {
+&cp0_ethernet {
status = "okay";
};
-&cpm_eth2 {
+&cp0_eth2 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts
index 5a046d9..2184648 100644
--- a/arch/arm/dts/armada-8040-mcbin.dts
+++ b/arch/arm/dts/armada-8040-mcbin.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016 Marvell International Ltd.
+ * Copyright (C) 2016 - 2021 Marvell International Ltd.
*/
#include "armada-8040.dtsi" /* include SoC device tree */
@@ -15,12 +15,12 @@
};
aliases {
- i2c0 = &cpm_i2c0;
- i2c1 = &cpm_i2c1;
- spi0 = &cps_spi1;
+ i2c0 = &cp0_i2c0;
+ i2c1 = &cp0_i2c1;
+ spi0 = &cp1_spi1;
gpio0 = &ap_gpio0;
- gpio1 = &cpm_gpio0;
- gpio2 = &cpm_gpio1;
+ gpio1 = &cp0_gpio0;
+ gpio2 = &cp0_gpio1;
};
memory@00000000 {
@@ -36,7 +36,7 @@
reg_usb3h0_vbus: usb3-vbus0 {
compatible = "regulator-fixed";
pinctrl-names = "default";
- pinctrl-0 = <&cpm_xhci_vbus_pins>;
+ pinctrl-0 = <&cp0_xhci_vbus_pins>;
regulator-name = "reg-usb3h0-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
@@ -44,7 +44,7 @@
enable-active-high;
regulator-always-on;
regulator-boot-on;
- gpio = <&cpm_gpio1 15 GPIO_ACTIVE_HIGH>; /* GPIO[47] */
+ gpio = <&cp0_gpio1 15 GPIO_ACTIVE_HIGH>; /* GPIO[47] */
};
};
};
@@ -73,7 +73,7 @@
status = "okay";
};
-&cpm_pinctl {
+&cp0_pinctl {
/*
* MPP Bus:
* [0-31] = 0xff: Keep default CP0_shared_pins:
@@ -108,59 +108,59 @@
0 0 0 0 0 0 0xe 0xe 0xe 0xe
0xe 0xe 0 >;
- cpm_xhci_vbus_pins: cpm-xhci-vbus-pins {
+ cp0_xhci_vbus_pins: cp0-xhci-vbus-pins {
marvell,pins = < 47 >;
marvell,function = <0>;
};
- cpm_pcie_reset_pins: cpm-pcie-reset-pins {
+ cp0_pcie_reset_pins: cp0-pcie-reset-pins {
marvell,pins = < 52 >;
marvell,function = <0>;
};
};
/* uSD slot */
-&cpm_sdhci0 {
+&cp0_sdhci0 {
pinctrl-names = "default";
- pinctrl-0 = <&cpm_sdhci_pins>;
+ pinctrl-0 = <&cp0_sdhci_pins>;
bus-width= <4>;
status = "okay";
};
/* PCIe x4 */
-&cpm_pcie0 {
+&cp0_pcie0 {
num-lanes = <4>;
pinctrl-names = "default";
- pinctrl-0 = <&cpm_pcie_reset_pins>;
- marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>; /* GPIO[52] */
+ pinctrl-0 = <&cp0_pcie_reset_pins>;
+ marvell,reset-gpio = <&cp0_gpio1 20 GPIO_ACTIVE_LOW>; /* GPIO[52] */
status = "okay";
};
-&cpm_i2c0 {
+&cp0_i2c0 {
pinctrl-names = "default";
- pinctrl-0 = <&cpm_i2c0_pins>;
+ pinctrl-0 = <&cp0_i2c0_pins>;
status = "okay";
clock-frequency = <100000>;
};
-&cpm_i2c1 {
+&cp0_i2c1 {
pinctrl-names = "default";
- pinctrl-0 = <&cpm_i2c1_pins>;
+ pinctrl-0 = <&cp0_i2c1_pins>;
status = "okay";
clock-frequency = <100000>;
};
-&cpm_sata0 {
+&cp0_sata0 {
status = "okay";
};
-&cpm_mdio {
+&cp0_mdio {
ge_phy: ethernet-phy@0 {
reg = <0>;
};
};
-&cpm_comphy {
+&cp0_comphy {
/*
* CP0 Serdes Configuration:
* Lane 0: PCIe0 (x4)
@@ -171,49 +171,49 @@
* Lane 5: SATA1
*/
phy0 {
- phy-type = <PHY_TYPE_PEX0>;
+ phy-type = <COMPHY_TYPE_PEX0>;
};
phy1 {
- phy-type = <PHY_TYPE_PEX0>;
+ phy-type = <COMPHY_TYPE_PEX0>;
};
phy2 {
- phy-type = <PHY_TYPE_PEX0>;
+ phy-type = <COMPHY_TYPE_PEX0>;
};
phy3 {
- phy-type = <PHY_TYPE_PEX0>;
+ phy-type = <COMPHY_TYPE_PEX0>;
};
phy4 {
- phy-type = <PHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI0>;
};
phy5 {
- phy-type = <PHY_TYPE_SATA1>;
+ phy-type = <COMPHY_TYPE_SATA1>;
};
};
-&cps_sata0 {
+&cp1_sata0 {
status = "okay";
};
-&cps_usb3_0 {
+&cp1_usb3_0 {
vbus-supply = <®_usb3h0_vbus>;
status = "okay";
};
-&cps_utmi0 {
+&cp1_utmi0 {
status = "okay";
};
-&cps_ethernet {
+&cp1_ethernet {
status = "okay";
};
-&cps_eth1 {
+&cp1_eth1 {
status = "okay";
phy = <&ge_phy>;
phy-mode = "sgmii";
};
-&cps_pinctl {
+&cp1_pinctl {
/*
* MPP Bus:
* [0-5] TDM
@@ -246,9 +246,9 @@
0xff 0xff 0xff>;
};
-&cps_spi1 {
+&cp1_spi1 {
pinctrl-names = "default";
- pinctrl-0 = <&cps_spi1_pins>;
+ pinctrl-0 = <&cp1_spi1_pins>;
status = "okay";
spi-flash@0 {
@@ -275,7 +275,7 @@
};
};
-&cps_comphy {
+&cp1_comphy {
/*
* CP1 Serdes Configuration:
* Lane 0: SGMII1
@@ -286,22 +286,23 @@
* Lane 5: SGMII3
*/
phy0 {
- phy-type = <PHY_TYPE_SGMII1>;
- phy-speed = <PHY_SPEED_1_25G>;
+ phy-type = <COMPHY_TYPE_SGMII1>;
+ phy-speed = <COMPHY_SPEED_1_25G>;
};
phy1 {
- phy-type = <PHY_TYPE_SATA0>;
+ phy-type = <COMPHY_TYPE_SATA0>;
};
phy2 {
- phy-type = <PHY_TYPE_USB3_HOST0>;
+ phy-type = <COMPHY_TYPE_USB3_HOST0>;
};
phy3 {
- phy-type = <PHY_TYPE_SATA1>;
+ phy-type = <COMPHY_TYPE_SATA1>;
};
phy4 {
- phy-type = <PHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI0>;
};
phy5 {
- phy-type = <PHY_TYPE_SGMII3>;
+ phy-type = <COMPHY_TYPE_SGMII2>;
+ phy-speed = <COMPHY_SPEED_3_125G>;
};
};
diff --git a/arch/arm/dts/armada-8040-puzzle-m801.dts b/arch/arm/dts/armada-8040-puzzle-m801.dts
index 58edb5b..510fb84 100644
--- a/arch/arm/dts/armada-8040-puzzle-m801.dts
+++ b/arch/arm/dts/armada-8040-puzzle-m801.dts
@@ -16,14 +16,14 @@
};
aliases {
- i2c0 = &i2c0;
- i2c1 = &cpm_i2c0;
- i2c2 = &cpm_i2c1;
+ i2c0 = &ap_i2c0;
+ i2c1 = &cp0_i2c0;
+ i2c2 = &cp0_i2c1;
i2c3 = &i2c_switch;
- spi0 = &spi0;
+ spi0 = &ap_spi0;
gpio0 = &ap_gpio0;
- gpio1 = &cpm_gpio0;
- gpio2 = &cpm_gpio1;
+ gpio1 = &cp0_gpio0;
+ gpio2 = &cp0_gpio1;
gpio3 = &sfpplus_gpio;
};
@@ -40,7 +40,7 @@
reg_usb3h0_vbus: usb3-vbus0 {
compatible = "regulator-fixed";
pinctrl-names = "default";
- pinctrl-0 = <&cpm_xhci_vbus_pins>;
+ pinctrl-0 = <&cp0_xhci_vbus_pins>;
regulator-name = "reg-usb3h0-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
@@ -48,12 +48,12 @@
enable-active-high;
regulator-always-on;
regulator-boot-on;
- gpio = <&cpm_gpio1 15 GPIO_ACTIVE_HIGH>; /* GPIO[47] */
+ gpio = <&cp0_gpio1 15 GPIO_ACTIVE_HIGH>; /* GPIO[47] */
};
};
};
-&i2c0 {
+&ap_i2c0 {
status = "okay";
clock-frequency = <100000>;
@@ -83,7 +83,7 @@
0 3 0 0 0 0 0 0 0 3 >;
};
-&cpm_pinctl {
+&cp0_pinctl {
/*
* MPP Bus:
* [0-31] = 0xff: Keep default CP0_shared_pins:
@@ -118,35 +118,35 @@
0 0 0 0 0 0 0xe 0xe 0xe 0xe
0xe 0xe 0 >;
- cpm_xhci_vbus_pins: cpm-xhci-vbus-pins {
+ cp0_xhci_vbus_pins: cpm-xhci-vbus-pins {
marvell,pins = < 47 >;
marvell,function = <0>;
};
- cpm_pcie_reset_pins: cpm-pcie-reset-pins {
+ cp0_pcie_reset_pins: cpm-pcie-reset-pins {
marvell,pins = < 52 >;
marvell,function = <0>;
};
};
-&cpm_sdhci0 {
+&cp0_sdhci0 {
pinctrl-names = "default";
- pinctrl-0 = <&cpm_sdhci_pins>;
+ pinctrl-0 = <&cp0_sdhci_pins>;
bus-width= <4>;
status = "okay";
};
-&cpm_pcie0 {
+&cp0_pcie0 {
num-lanes = <1>;
pinctrl-names = "default";
- pinctrl-0 = <&cpm_pcie_reset_pins>;
- marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>; /* GPIO[52] */
+ pinctrl-0 = <&cp0_pcie_reset_pins>;
+ marvell,reset-gpio = <&cp0_gpio1 20 GPIO_ACTIVE_LOW>; /* GPIO[52] */
status = "okay";
};
-&cpm_i2c0 {
+&cp0_i2c0 {
pinctrl-names = "default";
- pinctrl-0 = <&cpm_i2c0_pins>;
+ pinctrl-0 = <&cp0_i2c0_pins>;
status = "okay";
clock-frequency = <100000>;
@@ -158,9 +158,9 @@
};
};
-&cpm_i2c1 {
+&cp0_i2c1 {
pinctrl-names = "default";
- pinctrl-0 = <&cpm_i2c1_pins>;
+ pinctrl-0 = <&cp0_i2c1_pins>;
status = "okay";
clock-frequency = <100000>;
@@ -172,44 +172,44 @@
};
};
-&cpm_sata0 {
+&cp0_sata0 {
status = "okay";
};
-&cpm_ethernet {
+&cp0_ethernet {
pinctrl-names = "default";
status = "okay";
};
-&cpm_mdio {
+&cp0_mdio {
status = "okay";
- cpm_ge_phy0: ethernet-phy@1 {
+ cp0_ge_phy0: ethernet-phy@1 {
reg = <0>;
};
- cpm_ge_phy1: ethernet-phy@2 {
+ cp0_ge_phy1: ethernet-phy@2 {
reg = <1>;
};
};
-&cpm_eth0 {
+&cp0_eth0 {
status = "okay";
phy-mode = "sfi";
};
-&cpm_eth1 {
+&cp0_eth1 {
status = "okay";
phy-mode = "sgmii";
- phy = <&cpm_ge_phy0>;
+ phy = <&cp0_ge_phy0>;
};
-&cpm_eth2 {
+&cp0_eth2 {
status = "okay";
phy-mode = "sgmii";
- phy = <&cpm_ge_phy1>;
+ phy = <&cp0_ge_phy1>;
};
-&cpm_comphy {
+&cp0_comphy {
/*
* CP0 Serdes Configuration:
* Lane 0: PCIe0 (x1)
@@ -220,75 +220,75 @@
* Lane 5: SATA1
*/
phy0 {
- phy-type = <PHY_TYPE_PEX0>;
+ phy-type = <COMPHY_TYPE_PEX0>;
};
phy1 {
- phy-type = <PHY_TYPE_SGMII2>;
- phy-speed = <PHY_SPEED_1_25G>;
+ phy-type = <COMPHY_TYPE_SGMII2>;
+ phy-speed = <COMPHY_SPEED_1_25G>;
};
phy2 {
- phy-type = <PHY_TYPE_SATA0>;
+ phy-type = <COMPHY_TYPE_SATA0>;
};
phy3 {
- phy-type = <PHY_TYPE_SGMII1>;
- phy-speed = <PHY_SPEED_1_25G>;
+ phy-type = <COMPHY_TYPE_SGMII1>;
+ phy-speed = <COMPHY_SPEED_1_25G>;
};
phy4 {
- phy-type = <PHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI0>;
};
phy5 {
- phy-type = <PHY_TYPE_SATA1>;
+ phy-type = <COMPHY_TYPE_SATA1>;
};
};
-&cps_mdio {
+&cp1_mdio {
status = "okay";
- cps_ge_phy0: ethernet-phy@3 {
+ cp1_ge_phy0: ethernet-phy@3 {
reg = <1>;
};
- cps_ge_phy1: ethernet-phy@4 {
+ cp1_ge_phy1: ethernet-phy@4 {
reg = <0>;
};
};
-&cps_pcie0 {
+&cp1_pcie0 {
num-lanes = <2>;
pinctrl-names = "default";
status = "okay";
};
-&cps_usb3_0 {
+&cp1_usb3_0 {
vbus-supply = <®_usb3h0_vbus>;
status = "okay";
};
-&cps_utmi0 {
+&cp1_utmi0 {
status = "okay";
};
-&cps_ethernet {
+&cp1_ethernet {
status = "okay";
};
-&cps_eth0 {
+&cp1_eth0 {
status = "okay";
phy-mode = "sfi";
};
-&cps_eth1 {
+&cp1_eth1 {
status = "okay";
- phy = <&cps_ge_phy0>;
+ phy = <&cp1_ge_phy0>;
phy-mode = "sgmii";
};
-&cps_eth2 {
+&cp1_eth2 {
status = "okay";
- phy = <&cps_ge_phy1>;
+ phy = <&cp1_ge_phy1>;
phy-mode = "sgmii";
};
-&cps_pinctl {
+&cp1_pinctl {
/*
* MPP Bus:
* [0-5] TDM
@@ -321,7 +321,7 @@
0xff 0xff 0xff>;
};
-&spi0 {
+&ap_spi0 {
status = "okay";
spi-flash@0 {
@@ -356,7 +356,7 @@
};
};
-&cps_comphy {
+&cp1_comphy {
/*
* CP1 Serdes Configuration:
* Lane 0: PCIe0 (x2)
@@ -367,23 +367,23 @@
* Lane 5: SGMII2
*/
phy0 {
- phy-type = <PHY_TYPE_PEX0>;
+ phy-type = <COMPHY_TYPE_PEX0>;
};
phy1 {
- phy-type = <PHY_TYPE_PEX0>;
+ phy-type = <COMPHY_TYPE_PEX0>;
};
phy2 {
- phy-type = <PHY_TYPE_USB3_HOST0>;
+ phy-type = <COMPHY_TYPE_USB3_HOST0>;
};
phy3 {
- phy-type = <PHY_TYPE_SGMII1>;
- phy-speed = <PHY_SPEED_1_25G>;
+ phy-type = <COMPHY_TYPE_SGMII1>;
+ phy-speed = <COMPHY_SPEED_1_25G>;
};
phy4 {
- phy-type = <PHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI0>;
};
phy5 {
- phy-type = <PHY_TYPE_SGMII2>;
- phy-speed = <PHY_SPEED_1_25G>;
+ phy-type = <COMPHY_TYPE_SGMII2>;
+ phy-speed = <COMPHY_SPEED_1_25G>;
};
};
diff --git a/arch/arm/dts/armada-8040.dtsi b/arch/arm/dts/armada-8040.dtsi
index 96cc112..5123742 100644
--- a/arch/arm/dts/armada-8040.dtsi
+++ b/arch/arm/dts/armada-8040.dtsi
@@ -1,43 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * Copyright (C) 2016- 2021 Marvell International Ltd.
*/
/*
@@ -46,12 +9,81 @@
*/
#include <dt-bindings/gpio/gpio.h>
-#include "armada-ap806-quad.dtsi"
-#include "armada-cp110-master.dtsi"
-#include "armada-cp110-slave.dtsi"
+#include "armada-common.dtsi"
+#include "armada-8k.dtsi"
+#include "armada-ap806.dtsi"
+#include "armada-ap80x-quad.dtsi"
+
+/* CP110-0 Settings */
+#define CP110_NAME cp0
+#define CP110_NUM 0
+
+#include "armada-cp110.dtsi"
+
+#undef CP110_NAME
+#undef CP110_NUM
+
+/* CP110-1 Settings */
+#define CP110_NAME cp1
+#define CP110_NUM 1
+
+#include "armada-cp110.dtsi"
+
+#undef CP110_NAME
+#undef CP110_NUM
+
/ {
model = "Marvell Armada 8040";
compatible = "marvell,armada8040", "marvell,armada-ap806-quad",
"marvell,armada-ap806";
};
+
+&cp0_pinctl {
+ compatible = "marvell,mvebu-pinctrl", "marvell,8k-cpm-pinctrl";
+ bank-name ="cp0-110";
+
+ cp0_i2c0_pins: cp0-i2c-pins-0 {
+ marvell,pins = < 37 38 >;
+ marvell,function = <2>;
+ };
+ cp0_i2c1_pins: cp0-i2c-pins-1 {
+ marvell,pins = < 35 36 >;
+ marvell,function = <2>;
+ };
+ cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
+ marvell,pins = < 0 1 2 3 4 5 6 7 8 9 10 11>;
+ marvell,function = <3>;
+ };
+ cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
+ marvell,pins = < 44 45 46 47 48 49 50 51
+ 52 53 54 55 >;
+ marvell,function = <1>;
+ };
+ cp0_pca0_pins: cp0-pca0_pins {
+ marvell,pins = <62>;
+ marvell,function = <0>;
+ };
+ cp0_sdhci_pins: cp0-sdhi-pins-0 {
+ marvell,pins = < 56 57 58 59 60 61 >;
+ marvell,function = <14>;
+ };
+ cp0_spi0_pins: cp0-spi-pins-0 {
+ marvell,pins = < 13 14 15 16 >;
+ marvell,function = <3>;
+ };
+};
+
+&cp1_pinctl {
+ compatible = "marvell,mvebu-pinctrl", "marvell,8k-cps-pinctrl";
+ bank-name ="cp1-110";
+
+ cp1_ge1_rgmii_pins: cp1-ge-rgmii-pins-0 {
+ marvell,pins = < 0 1 2 3 4 5 6 7 8 9 10 11 >;
+ marvell,function = <3>;
+ };
+ cp1_spi1_pins: cp1-spi-pins-1 {
+ marvell,pins = < 13 14 15 16 >;
+ marvell,function = <3>;
+ };
+};
diff --git a/arch/arm/dts/armada-8k.dtsi b/arch/arm/dts/armada-8k.dtsi
new file mode 100644
index 0000000..c6af9ce
--- /dev/null
+++ b/arch/arm/dts/armada-8k.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 - 2021 Marvell International Ltd.
+ */
+/* Common definitions used by Armada 8K DTs */
+
+/* This defines used to calculate the base address of each CP */
+#define CP110_BASE_OFFSET (0xf2000000)
+#define CP110_SPACE_SIZE (0x02000000)
+#define CP110_BASE (CP110_BASE_OFFSET + \
+ ((CP110_NUM % 2) * CP110_SPACE_SIZE))
+
+#define CP110_PCIE_MEM_SIZE(iface) (0xf00000)
+#define CP110_PCIEx_CPU_MEM_BASE(iface) \
+ (0xf6000000 + (CP110_NUM % 2) * 0x4000000 + (iface) * 0x1000000)
+#define CP110_PCIEx_BUS_MEM_BASE(iface) \
+ (CP110_PCIEx_CPU_MEM_BASE(iface))
+#define CP110_PCIE_BUS_MEM_CFG (0x82000000)
diff --git a/arch/arm/dts/armada-ap806-quad.dtsi b/arch/arm/dts/armada-ap806-quad.dtsi
deleted file mode 100644
index ba43a43..0000000
--- a/arch/arm/dts/armada-ap806-quad.dtsi
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Device Tree file for Marvell Armada AP806.
- */
-
-#include "armada-ap806.dtsi"
-
-/ {
- model = "Marvell Armada AP806 Quad";
- compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806";
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@000 {
- device_type = "cpu";
- compatible = "arm,cortex-a72", "arm,armv8";
- reg = <0x000>;
- enable-method = "psci";
- };
- cpu@001 {
- device_type = "cpu";
- compatible = "arm,cortex-a72", "arm,armv8";
- reg = <0x001>;
- enable-method = "psci";
- };
- cpu@100 {
- device_type = "cpu";
- compatible = "arm,cortex-a72", "arm,armv8";
- reg = <0x100>;
- enable-method = "psci";
- };
- cpu@101 {
- device_type = "cpu";
- compatible = "arm,cortex-a72", "arm,armv8";
- reg = <0x101>;
- enable-method = "psci";
- };
- };
-};
diff --git a/arch/arm/dts/armada-ap806.dtsi b/arch/arm/dts/armada-ap806.dtsi
index 713c2db..f432089 100644
--- a/arch/arm/dts/armada-ap806.dtsi
+++ b/arch/arm/dts/armada-ap806.dtsi
@@ -1,274 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * Copyright (C) 2020 Marvell International Ltd.
*/
/*
* Device Tree file for Marvell Armada AP806.
*/
-#include <dt-bindings/interrupt-controller/arm-gic.h>
+/* AP806 Settings */
+#define AP_NAME ap806
-/dts-v1/;
+#include "armada-ap80x.dtsi"
/ {
model = "Marvell Armada AP806";
- compatible = "marvell,armada-ap806";
- #address-cells = <2>;
- #size-cells = <2>;
- aliases {
- serial0 = &uart0;
- serial1 = &uart1;
- };
-
- psci {
- compatible = "arm,psci-0.2";
- method = "smc";
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- psci-area@4000000 {
- reg = <0x0 0x4000000 0x0 0x200000>;
- no-map;
- };
- };
-
- ap806 {
- #address-cells = <2>;
- #size-cells = <2>;
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
- ranges;
-
+ AP_NAME {
config-space {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- ranges = <0x0 0x0 0xf0000000 0x1000000>;
-
- gic: interrupt-controller@210000 {
- compatible = "arm,gic-400";
- #interrupt-cells = <3>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- interrupt-controller;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
- reg = <0x210000 0x10000>,
- <0x220000 0x20000>,
- <0x240000 0x20000>,
- <0x260000 0x20000>;
-
- gic_v2m0: v2m@280000 {
- compatible = "arm,gic-v2m-frame";
- msi-controller;
- reg = <0x280000 0x1000>;
- arm,msi-base-spi = <160>;
- arm,msi-num-spis = <32>;
- };
- gic_v2m1: v2m@290000 {
- compatible = "arm,gic-v2m-frame";
- msi-controller;
- reg = <0x290000 0x1000>;
- arm,msi-base-spi = <192>;
- arm,msi-num-spis = <32>;
- };
- gic_v2m2: v2m@2a0000 {
- compatible = "arm,gic-v2m-frame";
- msi-controller;
- reg = <0x2a0000 0x1000>;
- arm,msi-base-spi = <224>;
- arm,msi-num-spis = <32>;
- };
- gic_v2m3: v2m@2b0000 {
- compatible = "arm,gic-v2m-frame";
- msi-controller;
- reg = <0x2b0000 0x1000>;
- arm,msi-base-spi = <256>;
- arm,msi-num-spis = <32>;
- };
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
- };
-
- odmi: odmi@300000 {
- compatible = "marvell,odmi-controller";
- interrupt-controller;
- msi-controller;
- marvell,odmi-frames = <4>;
- reg = <0x300000 0x4000>,
- <0x304000 0x4000>,
- <0x308000 0x4000>,
- <0x30C000 0x4000>;
- marvell,spi-base = <128>, <136>, <144>, <152>;
- };
-
- ap_pinctl: ap-pinctl@6F4000 {
- compatible = "marvell,ap806-pinctrl";
- bank-name ="apn-806";
- reg = <0x6F4000 0x10>;
- pin-count = <20>;
- max-func = <3>;
-
- ap_i2c0_pins: i2c-pins-0 {
- marvell,pins = < 4 5 >;
- marvell,function = <3>;
- };
- ap_emmc_pins: emmc-pins-0 {
- marvell,pins = < 0 1 2 3 4 5 6 7
- 8 9 10 >;
- marvell,function = <1>;
- };
- };
-
- ap_gpio0: gpio@6F5040 {
- compatible = "marvell,orion-gpio";
- reg = <0x6F5040 0x40>;
- ngpios = <20>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- xor@400000 {
- compatible = "marvell,mv-xor-v2";
- reg = <0x400000 0x1000>,
- <0x410000 0x1000>;
- msi-parent = <&gic_v2m0>;
- dma-coherent;
+ sar-reg {
+ compatible = "marvell,sample-at-reset-common",
+ "marvell,sample-at-reset-ap806";
+ reg = <0x6F8200 0x8>;
+ sar-driver = "ap806_sar";
+ sar-name = "ap806_sar";
+ status = "okay";
};
- xor@420000 {
- compatible = "marvell,mv-xor-v2";
- reg = <0x420000 0x1000>,
- <0x430000 0x1000>;
- msi-parent = <&gic_v2m0>;
- dma-coherent;
- };
-
- xor@440000 {
- compatible = "marvell,mv-xor-v2";
- reg = <0x440000 0x1000>,
- <0x450000 0x1000>;
- msi-parent = <&gic_v2m0>;
- dma-coherent;
- };
-
- xor@460000 {
- compatible = "marvell,mv-xor-v2";
- reg = <0x460000 0x1000>,
- <0x470000 0x1000>;
- msi-parent = <&gic_v2m0>;
- dma-coherent;
- };
-
- spi0: spi@510600 {
- compatible = "marvell,armada-380-spi";
- reg = <0x510600 0x50>;
- #address-cells = <1>;
- #size-cells = <0>;
- cell-index = <0>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ap_syscon 3>;
- status = "disabled";
- };
-
- i2c0: i2c@511000 {
- compatible = "marvell,mv78230-i2c";
- reg = <0x511000 0x20>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- timeout-ms = <1000>;
- clocks = <&ap_syscon 3>;
- status = "disabled";
- };
-
- uart0: serial@512000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x512000 0x100>;
- reg-shift = <2>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- reg-io-width = <1>;
- clocks = <&ap_syscon 3>;
- status = "disabled";
- clock-frequency = <200000000>;
- };
-
- uart1: serial@512100 {
- compatible = "snps,dw-apb-uart";
- reg = <0x512100 0x100>;
- reg-shift = <2>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
- reg-io-width = <1>;
- clocks = <&ap_syscon 3>;
- status = "disabled";
-
- };
-
- ap_sdhci0: sdhci@6e0000 {
- compatible = "marvell,armada-8k-sdhci";
- reg = <0x6e0000 0x300>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- dma-coherent;
- status = "disabled";
- };
-
- ap_syscon: system-controller@6f4000 {
- compatible = "marvell,ap806-system-controller",
- "syscon";
- #clock-cells = <1>;
- clock-output-names = "ap-cpu-cluster-0",
- "ap-cpu-cluster-1",
- "ap-fixed", "ap-mss";
- reg = <0x6f4000 0x1000>;
+ thermal: thermal@6f8084 {
+ compatible = "marvell,mvebu-thermal",
+ "marvell,thermal-ext-sensor";
+ reg = <0x6f8084 0x12>;
+ gain = <425>;
+ offset = <153400>;
+ divisor = <1000>;
+ status = "okay";
};
};
};
diff --git a/arch/arm/dts/armada-ap807.dtsi b/arch/arm/dts/armada-ap807.dtsi
new file mode 100644
index 0000000..a5309f3
--- /dev/null
+++ b/arch/arm/dts/armada-ap807.dtsi
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+/*
+ * Device Tree file for Marvell Armada AP807.
+ */
+
+/* AP807 Settings */
+#define AP_NAME ap807
+
+#include "armada-ap80x.dtsi"
+
+/ {
+ model = "Marvell Armada AP807";
+
+ AP_NAME {
+ config-space {
+ sar-reg {
+ compatible = "marvell,sample-at-reset-common",
+ "marvell,sample-at-reset-ap807";
+ reg = <0x6F8200 0x8>;
+ sar-driver = "ap807_sar";
+ sar-name = "ap807_sar";
+ status = "okay";
+ };
+
+ thermal: thermal@6f8084 {
+ compatible = "marvell,mvebu-thermal",
+ "marvell,thermal-ext-sensor";
+ reg = <0x6f8084 0x12>;
+ gain = <394>;
+ offset = <128900>;
+ divisor = <1000>;
+ status = "okay";
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/armada-ap80x-quad.dtsi b/arch/arm/dts/armada-ap80x-quad.dtsi
new file mode 100644
index 0000000..1220e98
--- /dev/null
+++ b/arch/arm/dts/armada-ap80x-quad.dtsi
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ */
+
+/*
+ * Device Tree file for Marvell Armada AP806/AP807.
+ */
+
+/ {
+ model = "Marvell Armada AP80X Quad";
+ compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@000 {
+ clocks;
+ u-boot,dm-pre-reloc;
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x000>;
+ enable-method = "psci";
+ };
+ cpu@001 {
+ clocks;
+ u-boot,dm-pre-reloc;
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x001>;
+ enable-method = "psci";
+ };
+ cpu@100 {
+ clocks;
+ u-boot,dm-pre-reloc;
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x100>;
+ enable-method = "psci";
+ };
+ cpu@101 {
+ clocks;
+ u-boot,dm-pre-reloc;
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x101>;
+ enable-method = "psci";
+ };
+ };
+};
diff --git a/arch/arm/dts/armada-ap80x.dtsi b/arch/arm/dts/armada-ap80x.dtsi
new file mode 100644
index 0000000..8787a87
--- /dev/null
+++ b/arch/arm/dts/armada-ap80x.dtsi
@@ -0,0 +1,211 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ *
+ */
+
+/*
+ * Device Tree file for Marvell Armada AP806/AP807.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/dts-v1/;
+
+/ {
+ compatible = "marvell,armada-ap806";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ psci-area@4000000 {
+ reg = <0x0 0x4000000 0x0 0x200000>;
+ no-map;
+ };
+ };
+
+ AP_NAME {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ config-space {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0x0 0xf0000000 0x1000000>;
+
+ gic: interrupt-controller@210000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ reg = <0x210000 0x10000>,
+ <0x220000 0x20000>,
+ <0x240000 0x20000>,
+ <0x260000 0x20000>;
+
+ gic_v2m0: v2m@280000 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0x280000 0x1000>;
+ arm,msi-base-spi = <160>;
+ arm,msi-num-spis = <32>;
+ };
+ gic_v2m1: v2m@290000 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0x290000 0x1000>;
+ arm,msi-base-spi = <192>;
+ arm,msi-num-spis = <32>;
+ };
+ gic_v2m2: v2m@2a0000 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0x2a0000 0x1000>;
+ arm,msi-base-spi = <224>;
+ arm,msi-num-spis = <32>;
+ };
+ gic_v2m3: v2m@2b0000 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0x2b0000 0x1000>;
+ arm,msi-base-spi = <256>;
+ arm,msi-num-spis = <32>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
+ };
+
+ odmi: odmi@300000 {
+ compatible = "marvell,odmi-controller";
+ interrupt-controller;
+ msi-controller;
+ marvell,odmi-frames = <4>;
+ reg = <0x300000 0x4000>,
+ <0x304000 0x4000>,
+ <0x308000 0x4000>,
+ <0x30C000 0x4000>;
+ marvell,spi-base = <128>, <136>, <144>, <152>;
+ };
+
+ ap_pinctl: ap-pinctl@6F4000 {
+ compatible = "marvell,ap806-pinctrl";
+ bank-name ="apn-806";
+ reg = <0x6F4000 0x10>;
+ pin-count = <20>;
+ max-func = <3>;
+
+ ap_i2c0_pins: i2c-pins-0 {
+ marvell,pins = < 4 5 >;
+ marvell,function = <3>;
+ };
+ ap_emmc_pins: emmc-pins-0 {
+ marvell,pins = < 0 1 2 3 4 5 6 7
+ 8 9 10 12 >;
+ marvell,function = <1>;
+ };
+ };
+
+ ap_gpio0: gpio@6F5040 {
+ compatible = "marvell,orion-gpio";
+ reg = <0x6F5040 0x40>;
+ ngpios = <20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ ap_spi0: spi@510600 {
+ compatible = "marvell,armada-380-spi";
+ reg = <0x510600 0x50>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ap_syscon 3>;
+ status = "disabled";
+ };
+
+ ap_i2c0: i2c@511000 {
+ compatible = "marvell,mv78230-i2c";
+ reg = <0x511000 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ timeout-ms = <1000>;
+ clocks = <&ap_syscon 3>;
+ status = "disabled";
+ };
+
+ uart0: serial@512000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x512000 0x100>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ clocks = <&ap_syscon 3>;
+ status = "disabled";
+ clock-frequency = <200000000>;
+ };
+
+ uart1: serial@512100 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x512100 0x100>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ clocks = <&ap_syscon 3>;
+ status = "disabled";
+
+ };
+
+ watchdog: watchdog@610000 {
+ compatible = "arm,sbsa-gwdt";
+ reg = <0x610000 0x1000>, <0x600000 0x1000>;
+ };
+
+ ap_sdhci0: sdhci@6e0000 {
+ compatible = "marvell,armada-8k-sdhci";
+ reg = <0x6e0000 0x300>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ ap_syscon: system-controller@6f4000 {
+ compatible = "marvell,ap806-system-controller",
+ "syscon";
+ #clock-cells = <1>;
+ clock-output-names = "ap-cpu-cluster-0",
+ "ap-cpu-cluster-1",
+ "ap-fixed", "ap-mss";
+ reg = <0x6f4000 0x1000>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/armada-common.dtsi b/arch/arm/dts/armada-common.dtsi
new file mode 100644
index 0000000..b7dfbda
--- /dev/null
+++ b/arch/arm/dts/armada-common.dtsi
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 Marvell International Ltd.
+ */
+
+/* Common definitions used by Armada 7K/8K DTs */
+#define PASTER(x, y) x ## _ ## y
+#define EVALUATOR(x, y) PASTER(x, y)
+
+/* This define used to create die label:
+ * For example:
+ * CP110 master:
+ * CP110_LABEL(spi0) -> cp0_spi0
+ * CP110 slave:
+ * CP110_LABEL(usb0) -> cp1_usb0
+ */
+#define CP110_LABEL(name) EVALUATOR(CP110_NAME, name)
+
+#define APPEND_NX(A, B) A ##-## B
+#define APPEND(A, B) APPEND_NX(A, B)
+
+#define STRINGIZE_NX(x) #x
+#define STRINGIZE(x) STRINGIZE_NX(x)
+
+/* Same idea here, but this define convert the name to string:
+ * For example:
+ * master: CP110_STRING_LABEL(ppv2) -> "cp0-ppv2"
+ * slave: CP110_STRING_LABEL(ppv2) -> "cp1-ppv2"
+ */
+#define CP110_STRING_LABEL(name) STRINGIZE(APPEND(CP110_NAME, name))
diff --git a/arch/arm/dts/armada-cp110-master.dtsi b/arch/arm/dts/armada-cp110-master.dtsi
deleted file mode 100644
index 7d0d31d..0000000
--- a/arch/arm/dts/armada-cp110-master.dtsi
+++ /dev/null
@@ -1,382 +0,0 @@
-/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Device Tree file for Marvell Armada CP110 Master.
- */
-
-#include <dt-bindings/comphy/comphy_data.h>
-
-/ {
- cp110-master {
- #address-cells = <2>;
- #size-cells = <2>;
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
- ranges;
-
- config-space {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
- ranges = <0x0 0x0 0xf2000000 0x2000000>;
-
- cpm_ethernet: ethernet@0 {
- compatible = "marvell,armada-7k-pp22";
- reg = <0x0 0x100000>, <0x129000 0xb000>;
- clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>, <&cpm_syscon0 1 5>;
- clock-names = "pp_clk", "gop_clk", "mg_clk";
- status = "disabled";
- dma-coherent;
-
- cpm_eth0: eth0 {
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- port-id = <0>;
- gop-port-id = <0>;
- status = "disabled";
- };
-
- cpm_eth1: eth1 {
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
- port-id = <1>;
- gop-port-id = <2>;
- status = "disabled";
- };
-
- cpm_eth2: eth2 {
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
- port-id = <2>;
- gop-port-id = <3>;
- status = "disabled";
- };
- };
-
- cpm_mdio: mdio@12a200 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "marvell,orion-mdio";
- reg = <0x12a200 0x10>;
- device-name = "cpm-mdio";
- };
-
- cpm_xmdio: mdio@12a600 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "marvell,xmdio";
- reg = <0x12a600 0x16>;
- status = "disabled";
- device-name = "cpm-xmdio";
- };
-
- cpm_syscon0: system-controller@440000 {
- compatible = "marvell,cp110-system-controller0",
- "syscon";
- reg = <0x440000 0x1000>;
- #clock-cells = <2>;
- core-clock-output-names =
- "cpm-apll", "cpm-ppv2-core", "cpm-eip",
- "cpm-core", "cpm-nand-core";
- gate-clock-output-names =
- "cpm-audio", "cpm-communit", "cpm-nand",
- "cpm-ppv2", "cpm-sdio", "cpm-mg-domain",
- "cpm-mg-core", "cpm-xor1", "cpm-xor0",
- "cpm-gop-dp", "none", "cpm-pcie_x10",
- "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor",
- "cpm-sata", "cpm-sata-usb", "cpm-main",
- "cpm-sd-mmc", "none", "none",
- "cpm-slow-io", "cpm-usb3h0", "cpm-usb3h1",
- "cpm-usb3dev", "cpm-eip150", "cpm-eip197";
- };
-
- cpm_pinctl: cpm-pinctl@440000 {
- compatible = "marvell,mvebu-pinctrl",
- "marvell,armada-7k-pinctrl",
- "marvell,armada-8k-cpm-pinctrl";
- bank-name ="cp0-110";
- reg = <0x440000 0x20>;
- pin-count = <63>;
- max-func = <0xf>;
-
- cpm_i2c0_pins: cpm-i2c-pins-0 {
- marvell,pins = < 37 38 >;
- marvell,function = <2>;
- };
- cpm_i2c1_pins: cpm-i2c-pins-1 {
- marvell,pins = < 35 36 >;
- marvell,function = <2>;
- };
- cpm_ge2_rgmii_pins: cpm-ge-rgmii-pins-0 {
- marvell,pins = < 44 45 46 47 48 49 50 51
- 52 53 54 55 >;
- marvell,function = <1>;
- };
- pca0_pins: cpm-pca0_pins {
- marvell,pins = <62>;
- marvell,function = <0>;
- };
- cpm_sdhci_pins: cpm-sdhi-pins-0 {
- marvell,pins = < 56 57 58 59 60 61 >;
- marvell,function = <14>;
- };
- cpm_spi0_pins: cpm-spi-pins-0 {
- marvell,pins = < 13 14 15 16 >;
- marvell,function = <3>;
- };
- };
-
- cpm_gpio0: gpio@440100 {
- compatible = "marvell,orion-gpio";
- reg = <0x440100 0x40>;
- ngpios = <32>;
- gpiobase = <20>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- cpm_gpio1: gpio@440140 {
- compatible = "marvell,orion-gpio";
- reg = <0x440140 0x40>;
- ngpios = <31>;
- gpiobase = <52>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- cpm_sata0: sata@540000 {
- compatible = "marvell,armada-8k-ahci";
- reg = <0x540000 0x30000>;
- interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpm_syscon0 1 15>;
- status = "disabled";
- };
-
- cpm_usb3_0: usb3@500000 {
- compatible = "marvell,armada-8k-xhci",
- "generic-xhci";
- reg = <0x500000 0x4000>;
- dma-coherent;
- interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpm_syscon0 1 22>;
- status = "disabled";
- };
-
- cpm_usb3_1: usb3@510000 {
- compatible = "marvell,armada-8k-xhci",
- "generic-xhci";
- reg = <0x510000 0x4000>;
- dma-coherent;
- interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpm_syscon0 1 23>;
- status = "disabled";
- };
-
- cpm_spi0: spi@700600 {
- compatible = "marvell,armada-380-spi";
- reg = <0x700600 0x50>;
- #address-cells = <0x1>;
- #size-cells = <0x0>;
- cell-index = <1>;
- clocks = <&cpm_syscon0 0 3>;
- status = "disabled";
- };
-
- cpm_spi1: spi@700680 {
- compatible = "marvell,armada-380-spi";
- reg = <0x700680 0x50>;
- #address-cells = <1>;
- #size-cells = <0>;
- cell-index = <2>;
- clocks = <&cpm_syscon0 1 21>;
- status = "disabled";
- };
-
- cpm_i2c0: i2c@701000 {
- compatible = "marvell,mv78230-i2c";
- reg = <0x701000 0x20>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpm_syscon0 1 21>;
- status = "disabled";
- };
-
- cpm_i2c1: i2c@701100 {
- compatible = "marvell,mv78230-i2c";
- reg = <0x701100 0x20>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpm_syscon0 1 21>;
- status = "disabled";
- };
-
- cpm_comphy: comphy@441000 {
- compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110";
- reg = <0x441000 0x8>,
- <0x120000 0x8>;
- mux-bitcount = <4>;
- max-lanes = <6>;
- };
-
- cpm_utmi0: utmi@580000 {
- compatible = "marvell,mvebu-utmi-2.6.0";
- reg = <0x580000 0x1000>, /* utmi-unit */
- <0x440420 0x4>, /* usb-cfg */
- <0x440440 0x4>; /* utmi-cfg */
- utmi-port = <UTMI_PHY_TO_USB3_HOST0>;
- status = "disabled";
- };
-
- cpm_utmi1: utmi@581000 {
- compatible = "marvell,mvebu-utmi-2.6.0";
- reg = <0x581000 0x1000>, /* utmi-unit */
- <0x440420 0x4>, /* usb-cfg */
- <0x440444 0x4>; /* utmi-cfg */
- utmi-port = <UTMI_PHY_TO_USB3_HOST1>;
- status = "disabled";
- };
-
- cpm_sdhci0: sdhci@780000 {
- compatible = "marvell,armada-8k-sdhci";
- reg = <0x780000 0x300>;
- interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- dma-coherent;
- status = "disabled";
- };
-
- cpm_nand: nand@720000 {
- compatible = "marvell,armada-8k-nand-controller",
- "marvell,armada370-nand-controller";
- reg = <0x720000 0x54>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "core", "reg";
- clocks = <&cpm_syscon0 1 2>,
- <&cpm_syscon0 1 17>;
- marvell,system-controller = <&cpm_syscon0>;
- nand-enable-arbiter;
- num-cs = <1>;
- status = "disabled";
- };
-
- };
-
- cpm_pcie0: pcie@f2600000 {
- compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
- reg = <0 0xf2600000 0 0x10000>,
- <0 0xf6f00000 0 0x80000>;
- reg-names = "ctrl", "config";
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- device_type = "pci";
- dma-coherent;
-
- bus-range = <0 0xff>;
- ranges =
- /* downstream I/O */
- <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000
- /* non-prefetchable memory */
- 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- num-lanes = <1>;
- clocks = <&cpm_syscon0 1 13>;
- status = "disabled";
- };
-
- cpm_pcie1: pcie@f2620000 {
- compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
- reg = <0 0xf2620000 0 0x10000>,
- <0 0xf7f00000 0 0x80000>;
- reg-names = "ctrl", "config";
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- device_type = "pci";
- dma-coherent;
-
- bus-range = <0 0xff>;
- ranges =
- /* downstream I/O */
- <0x81000000 0 0xf9010000 0 0xf9010000 0 0x10000
- /* non-prefetchable memory */
- 0x82000000 0 0xf7000000 0 0xf7000000 0 0xf00000>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
-
- num-lanes = <1>;
- clocks = <&cpm_syscon0 1 11>;
- status = "disabled";
- };
-
- cpm_pcie2: pcie@f2640000 {
- compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
- reg = <0 0xf2640000 0 0x10000>,
- <0 0xf8f00000 0 0x80000>;
- reg-names = "ctrl", "config";
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- device_type = "pci";
- dma-coherent;
-
- bus-range = <0 0xff>;
- ranges =
- /* downstream I/O */
- <0x81000000 0 0xf9020000 0 0xf9020000 0 0x10000
- /* non-prefetchable memory */
- 0x82000000 0 0xf8000000 0 0xf8000000 0 0xf00000>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
-
- num-lanes = <1>;
- clocks = <&cpm_syscon0 1 12>;
- status = "disabled";
- };
- };
-};
diff --git a/arch/arm/dts/armada-cp110-slave.dtsi b/arch/arm/dts/armada-cp110-slave.dtsi
deleted file mode 100644
index 6cf2177..0000000
--- a/arch/arm/dts/armada-cp110-slave.dtsi
+++ /dev/null
@@ -1,368 +0,0 @@
-/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Device Tree file for Marvell Armada CP110 Slave.
- */
-
-#include <dt-bindings/comphy/comphy_data.h>
-
-/ {
- cp110-slave {
- #address-cells = <2>;
- #size-cells = <2>;
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
- ranges;
-
- config-space {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
- ranges = <0x0 0x0 0xf4000000 0x2000000>;
-
- cps_ethernet: ethernet@0 {
- compatible = "marvell,armada-7k-pp22";
- reg = <0x0 0x100000>, <0x129000 0xb000>;
- clocks = <&cps_syscon0 1 3>, <&cps_syscon0 1 9>, <&cps_syscon0 1 5>;
- clock-names = "pp_clk", "gop_clk", "mg_clk";
- status = "disabled";
- dma-coherent;
-
- cps_eth0: eth0 {
- interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
- port-id = <0>;
- gop-port-id = <0>;
- status = "disabled";
- };
-
- cps_eth1: eth1 {
- interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
- port-id = <1>;
- gop-port-id = <2>;
- status = "disabled";
- };
-
- cps_eth2: eth2 {
- interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
- port-id = <2>;
- gop-port-id = <3>;
- status = "disabled";
- };
- };
-
- cps_mdio: mdio@12a200 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "marvell,orion-mdio";
- reg = <0x12a200 0x10>;
- device-name = "cps-mdio";
- };
-
- cps_xmdio: mdio@12a600 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "marvell,xmdio";
- reg = <0x12a600 0x16>;
- status = "disabled";
- device-name = "cps-xmdio";
- };
-
- cps_syscon0: system-controller@440000 {
- compatible = "marvell,cp110-system-controller0",
- "syscon";
- reg = <0x440000 0x1000>;
- #clock-cells = <2>;
- core-clock-output-names =
- "cps-apll", "cps-ppv2-core", "cps-eip",
- "cps-core", "cps-nand-core";
- gate-clock-output-names =
- "cps-audio", "cps-communit", "cps-nand",
- "cps-ppv2", "cps-sdio", "cps-mg-domain",
- "cps-mg-core", "cps-xor1", "cps-xor0",
- "cps-gop-dp", "none", "cps-pcie_x10",
- "cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor",
- "cps-sata", "cps-sata-usb", "cps-main",
- "cps-sd-mmc", "none", "none",
- "cps-slow-io", "cps-usb3h0", "cps-usb3h1",
- "cps-usb3dev", "cps-eip150", "cps-eip197";
- };
-
- cps_pinctl: cps-pinctl@440000 {
- compatible = "marvell,mvebu-pinctrl",
- "marvell,armada-8k-cps-pinctrl";
- bank-name ="cp1-110";
- reg = <0x440000 0x20>;
- pin-count = <63>;
- max-func = <0xf>;
-
- cps_ge1_rgmii_pins: cps-ge-rgmii-pins-0 {
- marvell,pins = < 0 1 2 3 4 5 6 7
- 8 9 10 11 >;
- marvell,function = <3>;
- };
- cps_spi1_pins: cps-spi-pins-1 {
- marvell,pins = < 13 14 15 16 >;
- marvell,function = <3>;
- };
- };
-
- cps_gpio0: gpio@440100 {
- compatible = "marvell,orion-gpio";
- reg = <0x440100 0x40>;
- ngpios = <32>;
- gpiobase = <20>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- cps_gpio1: gpio@440140 {
- compatible = "marvell,orion-gpio";
- reg = <0x440140 0x40>;
- ngpios = <31>;
- gpiobase = <52>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- cps_sata0: sata@540000 {
- compatible = "marvell,armada-8k-ahci";
- reg = <0x540000 0x30000>;
- interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cps_syscon0 1 15>;
- status = "disabled";
- };
-
- cps_usb3_0: usb3@500000 {
- compatible = "marvell,armada-8k-xhci",
- "generic-xhci";
- reg = <0x500000 0x4000>;
- dma-coherent;
- interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cps_syscon0 1 22>;
- status = "disabled";
- };
-
- cps_usb3_1: usb3@510000 {
- compatible = "marvell,armada-8k-xhci",
- "generic-xhci";
- reg = <0x510000 0x4000>;
- dma-coherent;
- interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cps_syscon0 1 23>;
- status = "disabled";
- };
-
- cps_xor0: xor@6a0000 {
- compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
- reg = <0x6a0000 0x1000>,
- <0x6b0000 0x1000>;
- dma-coherent;
- msi-parent = <&gic_v2m0>;
- clocks = <&cps_syscon0 1 8>;
- };
-
- cps_xor1: xor@6c0000 {
- compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
- reg = <0x6c0000 0x1000>,
- <0x6d0000 0x1000>;
- dma-coherent;
- msi-parent = <&gic_v2m0>;
- clocks = <&cps_syscon0 1 7>;
- };
-
- cps_spi0: spi@700600 {
- compatible = "marvell,armada-380-spi";
- reg = <0x700600 0x50>;
- #address-cells = <0x1>;
- #size-cells = <0x0>;
- cell-index = <1>;
- clocks = <&cps_syscon0 0 3>;
- status = "disabled";
- };
-
- cps_spi1: spi@700680 {
- compatible = "marvell,armada-380-spi";
- reg = <0x700680 0x50>;
- #address-cells = <1>;
- #size-cells = <0>;
- cell-index = <2>;
- clocks = <&cps_syscon0 1 21>;
- status = "disabled";
- };
-
- cps_i2c0: i2c@701000 {
- compatible = "marvell,mv78230-i2c";
- reg = <0x701000 0x20>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cps_syscon0 1 21>;
- status = "disabled";
- };
-
- cps_i2c1: i2c@701100 {
- compatible = "marvell,mv78230-i2c";
- reg = <0x701100 0x20>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cps_syscon0 1 21>;
- status = "disabled";
- };
-
- cps_comphy: comphy@441000 {
- compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110";
- reg = <0x441000 0x8>,
- <0x120000 0x8>;
- mux-bitcount = <4>;
- max-lanes = <6>;
- };
-
- cps_utmi0: utmi@580000 {
- compatible = "marvell,mvebu-utmi-2.6.0";
- reg = <0x580000 0x1000>, /* utmi-unit */
- <0x440420 0x4>, /* usb-cfg */
- <0x440440 0x4>; /* utmi-cfg */
- utmi-port = <UTMI_PHY_TO_USB3_HOST0>;
- status = "disabled";
- };
-
- cps_nand: nand@720000 {
- compatible = "marvell,armada-8k-nand-controller",
- "marvell,armada370-nand-controller";
- reg = <0x720000 0x54>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "core", "reg";
- clocks = <&cps_syscon0 1 2>,
- <&cps_syscon0 1 17>;
- marvell,system-controller = <&cps_syscon0>;
- nand-enable-arbiter;
- num-cs = <1>;
- status = "disabled";
- };
- };
-
- cps_pcie0: pcie@f4600000 {
- compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
- reg = <0 0xf4600000 0 0x10000>,
- <0 0xfaf00000 0 0x80000>;
- reg-names = "ctrl", "config";
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- device_type = "pci";
- dma-coherent;
- msi-parent = <&gic_v2m0>;
-
- bus-range = <0 0xff>;
- ranges =
- /* downstream I/O */
- <0x81000000 0 0xfd000000 0 0xfd000000 0 0x10000
- /* non-prefetchable memory */
- 0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
- num-lanes = <1>;
- clocks = <&cps_syscon0 1 13>;
- status = "disabled";
- };
-
- cps_pcie1: pcie@f4620000 {
- compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
- reg = <0 0xf4620000 0 0x10000>,
- <0 0xfbf00000 0 0x80000>;
- reg-names = "ctrl", "config";
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- device_type = "pci";
- dma-coherent;
- msi-parent = <&gic_v2m0>;
-
- bus-range = <0 0xff>;
- ranges =
- /* downstream I/O */
- <0x81000000 0 0xfd010000 0 0xfd010000 0 0x10000
- /* non-prefetchable memory */
- 0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
-
- num-lanes = <1>;
- clocks = <&cps_syscon0 1 11>;
- status = "disabled";
- };
-
- cps_pcie2: pcie@f4640000 {
- compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
- reg = <0 0xf4640000 0 0x10000>,
- <0 0xfcf00000 0 0x80000>;
- reg-names = "ctrl", "config";
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- device_type = "pci";
- dma-coherent;
- msi-parent = <&gic_v2m0>;
-
- bus-range = <0 0xff>;
- ranges =
- /* downstream I/O */
- <0x81000000 0 0xfd020000 0 0xfd020000 0 0x10000
- /* non-prefetchable memory */
- 0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
-
- num-lanes = <1>;
- clocks = <&cps_syscon0 1 12>;
- status = "disabled";
- };
- };
-};
diff --git a/arch/arm/dts/armada-cp110.dtsi b/arch/arm/dts/armada-cp110.dtsi
new file mode 100644
index 0000000..abf1e4e
--- /dev/null
+++ b/arch/arm/dts/armada-cp110.dtsi
@@ -0,0 +1,359 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016- 2021 Marvell International Ltd.
+ */
+
+/*
+ * Generic Device Tree describing Marvell Armada CP-110 device
+ */
+
+#include <dt-bindings/comphy/comphy_data.h>
+
+#define U64_TO_U32_H(addr) (((addr) >> 32) & 0xffffffff)
+#define U64_TO_U32_L(addr) ((addr) & 0xffffffff)
+
+#define CP110_PCIEx_REG0_BASE(iface) \
+ (CP110_BASE + 0x600000 + (iface) * 0x20000)
+#define CP110_PCIEx_REG1_BASE(iface) \
+ (CP110_PCIEx_CPU_MEM_BASE(iface) + CP110_PCIE_MEM_SIZE(iface))
+#define CP110_PCIE_EP_REG_BASE(iface) (CP110_BASE + 0x600000 + \
+ (iface) * 0x4000)
+
+/ {
+ CP110_NAME {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ config-space {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges = <0x0 U64_TO_U32_H(CP110_BASE) U64_TO_U32_L(CP110_BASE) 0x2000000>;
+
+ CP110_LABEL(mdio): mdio@12a200 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "marvell,orion-mdio";
+ reg = <0x12a200 0x10>;
+ device-name = CP110_STRING_LABEL(mdio);
+ status = "disabled";
+ };
+
+ CP110_LABEL(xmdio): mdio@12a600 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "marvell,xmdio";
+ reg = <0x12a600 0x200>;
+ device-name = CP110_STRING_LABEL(xmdio);
+ status = "disabled";
+ };
+
+ CP110_LABEL(sar-reg) {
+ compatible = "marvell,sample-at-reset-common",
+ "marvell,sample-at-reset-cp110";
+ reg = <0x400200 0x8>;
+ sar-driver = "cp110_sar";
+ sar-name = CP110_STRING_LABEL(sar);
+ status = "okay";
+ };
+
+ CP110_LABEL(syscon0): system-controller@440000 {
+ compatible = "marvell,cp110-system-controller0",
+ "syscon";
+ reg = <0x440000 0x1000>;
+ #clock-cells = <2>;
+ core-clock-output-names =
+ "cpm-apll", "cpm-ppv2-core", "cpm-eip",
+ "cpm-core", "cpm-nand-core";
+ gate-clock-output-names =
+ "cpm-audio", "cpm-communit", "cpm-nand",
+ "cpm-ppv2", "cpm-sdio", "cpm-mg-domain",
+ "cpm-mg-core", "cpm-xor1", "cpm-xor0",
+ "cpm-gop-dp", "none", "cpm-pcie_x10",
+ "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor",
+ "cpm-sata", "cpm-sata-usb", "cpm-main",
+ "cpm-sd-mmc", "none", "none",
+ "cpm-slow-io", "cpm-usb3h0", "cpm-usb3h1",
+ "cpm-usb3dev", "cpm-eip150", "cpm-eip197";
+ };
+
+ CP110_LABEL(pinctl): pinctl@440000 {
+ compatible = "marvell,mvebu-pinctrl";
+ reg = <0x440000 0x20>;
+ pin-count = <63>;
+ max-func = <0xf>;
+ };
+
+ CP110_LABEL(gpio0): gpio@440100 {
+ compatible = "marvell,orion-gpio";
+ reg = <0x440100 0x40>;
+ ngpios = <32>;
+ gpiobase = <20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ CP110_LABEL(gpio1): gpio@440140 {
+ compatible = "marvell,orion-gpio";
+ reg = <0x440140 0x40>;
+ ngpios = <31>;
+ gpiobase = <52>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ CP110_LABEL(sata0): sata@540000 {
+ compatible = "marvell,armada-8k-ahci";
+ reg = <0x540000 0x30000>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&CP110_LABEL(syscon0) 1 15>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(usb3_0): usb3@500000 {
+ compatible = "marvell,armada-8k-xhci",
+ "generic-xhci";
+ reg = <0x500000 0x4000>;
+ dma-coherent;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&CP110_LABEL(syscon0) 1 22>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(usb3_1): usb3@510000 {
+ compatible = "marvell,armada-8k-xhci",
+ "generic-xhci";
+ reg = <0x510000 0x4000>;
+ dma-coherent;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&CP110_LABEL(syscon0) 1 23>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(spi0): spi@700600 {
+ compatible = "marvell,armada-380-spi";
+ reg = <0x700600 0x50>;
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ cell-index = <1>;
+ spi-max-frequency = <50000000>;
+ clocks = <&CP110_LABEL(syscon0) 0 3>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(spi1): spi@700680 {
+ compatible = "marvell,armada-380-spi";
+ reg = <0x700680 0x50>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <2>;
+ spi-max-frequency = <50000000>;
+ clocks = <&CP110_LABEL(syscon0) 1 21>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(i2c0): i2c@701000 {
+ compatible = "marvell,mv78230-i2c";
+ reg = <0x701000 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&CP110_LABEL(syscon0) 1 21>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(i2c1): i2c@701100 {
+ compatible = "marvell,mv78230-i2c";
+ reg = <0x701100 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&CP110_LABEL(syscon0) 1 21>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(mss_i2c0): i2c@211000 {
+ compatible = "marvell,mv78230-i2c";
+ reg = <0x211000 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(comphy): comphy@441000 {
+ compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110";
+ reg = <0x441000 0x8>,
+ <0x120000 0x8>;
+ mux-bitcount = <4>;
+ max-lanes = <6>;
+ };
+
+ CP110_LABEL(utmi): utmi@580000 {
+ compatible = "marvell,mvebu-utmi";
+ reg = <0x580000 0xc>; /* utmi-common-pll */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ CP110_LABEL(utmi0): utmi@58000c {
+ compatible = "marvell,mvebu-utmi-2.6.0";
+ reg = <0x58000c 0x100>,/* utmi-unit */
+ <0x440420 0x4>, /* usb-cfg */
+ <0x440440 0x4>; /* utmi-cfg */
+ utmi-port = <UTMI_PHY_TO_USB3_HOST0>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(utmi1): utmi@58100c {
+ compatible = "marvell,mvebu-utmi-2.6.0";
+ reg = <0x58100c 0x100>,/* utmi-unit */
+ <0x440420 0x4>, /* usb-cfg */
+ <0x440444 0x4>; /* utmi-cfg */
+ utmi-port = <UTMI_PHY_TO_USB3_HOST1>;
+ status = "disabled";
+ };
+ };
+
+ CP110_LABEL(sdhci0): sdhci@780000 {
+ compatible = "marvell,armada-8k-sdhci";
+ reg = <0x780000 0x300>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ CP110_LABEL(nand): nand@720000 {
+ compatible = "marvell,armada-8k-nand-controller",
+ "marvell,armada370-nand-controller";
+ reg = <0x720000 0x54>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&CP110_LABEL(syscon0) 1 2>;
+ nand-enable-arbiter;
+ num-cs = <1>;
+ nand-ecc-strength = <8>;
+ nand-ecc-step-size = <512>;
+ marvell,system-controller = <&CP110_LABEL(syscon0)>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(ethernet): ethernet@0 {
+ compatible = "marvell,armada-7k-pp22";
+ reg = <0x0 0x100000>, <0x129000 0xb000>;
+ clocks = <&CP110_LABEL(syscon0) 1 3>, <&CP110_LABEL(syscon0) 1 9>, <&CP110_LABEL(syscon0) 1 5>;
+ clock-names = "pp_clk", "gop_clk", "mg_clk";
+ status = "disabled";
+ dma-coherent;
+
+ CP110_LABEL(eth0): eth0 {
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ port-id = <0>;
+ gop-port-id = <0>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(eth1): eth1 {
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ port-id = <1>;
+ gop-port-id = <2>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(eth2): eth2 {
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ port-id = <2>;
+ gop-port-id = <3>;
+ status = "disabled";
+ };
+ };
+ };
+
+ CP110_LABEL(pcie0): pcie0@600000 {
+ compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+ reg =
+ <U64_TO_U32_H(CP110_PCIEx_REG0_BASE(0)) U64_TO_U32_L(CP110_PCIEx_REG0_BASE(0)) 0 0x10000>,
+ /* Last 512KB of mem space */
+ <U64_TO_U32_H(CP110_PCIEx_REG1_BASE(0)) U64_TO_U32_L(CP110_PCIEx_REG1_BASE(0)) 0 0x80000>;
+ reg-names = "ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ dma-coherent;
+
+ bus-range = <0 0xff>;
+ ranges =
+ /* non-prefetchable memory */
+ <CP110_PCIE_BUS_MEM_CFG U64_TO_U32_H(CP110_PCIEx_BUS_MEM_BASE(0))
+ U64_TO_U32_L(CP110_PCIEx_BUS_MEM_BASE(0)) U64_TO_U32_H(CP110_PCIEx_CPU_MEM_BASE(0))
+ U64_TO_U32_L(CP110_PCIEx_CPU_MEM_BASE(0))
+ U64_TO_U32_H(CP110_PCIE_MEM_SIZE(0)) U64_TO_U32_L(CP110_PCIE_MEM_SIZE(0))>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ num-lanes = <1>;
+ clocks = <&CP110_LABEL(syscon0) 1 13>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(pcie1): pcie1@620000 {
+ compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+ reg =
+ <U64_TO_U32_H(CP110_PCIEx_REG0_BASE(1)) U64_TO_U32_L(CP110_PCIEx_REG0_BASE(1)) 0 0x10000>,
+ /* Last 512KB of mem space */
+ <U64_TO_U32_H(CP110_PCIEx_REG1_BASE(1)) U64_TO_U32_L(CP110_PCIEx_REG1_BASE(1)) 0 0x80000>;
+ reg-names = "ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ dma-coherent;
+
+ bus-range = <0 0xff>;
+ ranges =
+ /* non-prefetchable memory */
+ <CP110_PCIE_BUS_MEM_CFG U64_TO_U32_H(CP110_PCIEx_BUS_MEM_BASE(1))
+ U64_TO_U32_L(CP110_PCIEx_BUS_MEM_BASE(1)) U64_TO_U32_H(CP110_PCIEx_CPU_MEM_BASE(1))
+ U64_TO_U32_L(CP110_PCIEx_CPU_MEM_BASE(1)) U64_TO_U32_H(CP110_PCIE_MEM_SIZE(1))
+ U64_TO_U32_L(CP110_PCIE_MEM_SIZE(1))>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+
+ num-lanes = <1>;
+ clocks = <&CP110_LABEL(syscon0) 1 11>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(pcie2): pcie2@640000 {
+ compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+ reg =
+ <U64_TO_U32_H(CP110_PCIEx_REG0_BASE(2)) U64_TO_U32_L(CP110_PCIEx_REG0_BASE(2)) 0 0x10000>,
+ /* Last 64KB of mem space */
+ <U64_TO_U32_H(CP110_PCIEx_REG1_BASE(2)) U64_TO_U32_L(CP110_PCIEx_REG1_BASE(2)) 0 0x80000>;
+ reg-names = "ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ dma-coherent;
+
+ bus-range = <0 0xff>;
+ ranges =
+ /* non-prefetchable memory */
+ <CP110_PCIE_BUS_MEM_CFG U64_TO_U32_H(CP110_PCIEx_BUS_MEM_BASE(2))
+ U64_TO_U32_L(CP110_PCIEx_BUS_MEM_BASE(2)) U64_TO_U32_H(CP110_PCIEx_CPU_MEM_BASE(2))
+ U64_TO_U32_L(CP110_PCIEx_CPU_MEM_BASE(2)) U64_TO_U32_H(CP110_PCIE_MEM_SIZE(2))
+ U64_TO_U32_L(CP110_PCIE_MEM_SIZE(2))>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+
+ num-lanes = <1>;
+ clocks = <&CP110_LABEL(syscon0) 1 12>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/dts/cn9130-crb-A.dts b/arch/arm/dts/cn9130-crb-A.dts
new file mode 100644
index 0000000..fcfcd15
--- /dev/null
+++ b/arch/arm/dts/cn9130-crb-A.dts
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ */
+
+#include "cn9130-crb.dtsi"
+
+/ {
+ model = "CN9130-CRB-A";
+ compatible = "marvell,cn9130-crb-A",
+ "marvell,cn9130",
+ "marvell,armada-ap806-quad",
+ "marvell,armada-ap806";
+};
+
+&cp0_comphy {
+ phy0 {
+ phy-type = <COMPHY_TYPE_PEX0>;
+ };
+
+ phy1 {
+ phy-type = <COMPHY_TYPE_PEX0>;
+ };
+
+ phy2 {
+ phy-type = <COMPHY_TYPE_PEX0>;
+ };
+
+ phy3 {
+ phy-type = <COMPHY_TYPE_PEX0>;
+ };
+
+ phy4 {
+ phy-type = <COMPHY_TYPE_SFI0>;
+ phy-speed = <COMPHY_SPEED_10_3125G>;
+ };
+
+ phy5 {
+ phy-type = <COMPHY_TYPE_SGMII2>;
+ phy-speed = <COMPHY_SPEED_3_125G>;
+ };
+};
+
+&cp0_pcie0 {
+ num-lanes = <4>;
+ /* non-prefetchable memory */
+ ranges =<0x82000000 0 0xc0000000 0 0xc0000000 0 0x2000000>;
+ status = "disabled";
+};
+
+&cp0_usb3_0 {
+ status = "okay";
+};
+
+&cp0_usb3_1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/cn9130-crb-B.dts b/arch/arm/dts/cn9130-crb-B.dts
new file mode 100644
index 0000000..b681b60
--- /dev/null
+++ b/arch/arm/dts/cn9130-crb-B.dts
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ */
+
+#include "cn9130-crb.dtsi"
+
+/ {
+ model = "CN9130-CRB-B";
+ compatible = "marvell,cn9130-crb-B",
+ "marvell,cn9130",
+ "marvell,armada-ap806-quad",
+ "marvell,armada-ap806";
+};
+
+&cp0_comphy {
+ phy0 {
+ phy-type = <COMPHY_TYPE_PEX0>;
+ };
+
+ phy1 {
+ phy-type = <COMPHY_TYPE_USB3_HOST0>;
+ };
+
+ phy2 {
+ phy-type = <COMPHY_TYPE_SATA0>;
+ };
+
+ phy3 {
+ phy-type = <COMPHY_TYPE_USB3_HOST1>;
+ };
+
+ phy4 {
+ phy-type = <COMPHY_TYPE_SFI0>;
+ phy-speed = <COMPHY_SPEED_10_3125G>;
+ };
+
+ phy5 {
+ phy-type = <COMPHY_TYPE_SGMII2>;
+ phy-speed = <COMPHY_SPEED_3_125G>;
+ };
+};
+
+&cp0_sata0 {
+ status = "okay";
+};
+
+&cp0_pcie0 {
+ num-lanes = <1>;
+ /* non-prefetchable memory */
+ ranges =<0x82000000 0 0xc0000000 0 0xc0000000 0 0x2000000>;
+ status = "disabled";
+};
+
+&cp0_usb3_0 {
+ status = "okay";
+};
+
+&cp0_usb3_1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/cn9130-crb.dtsi b/arch/arm/dts/cn9130-crb.dtsi
new file mode 100644
index 0000000..b229725
--- /dev/null
+++ b/arch/arm/dts/cn9130-crb.dtsi
@@ -0,0 +1,257 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ */
+
+#include "cn9130.dtsi" /* include SoC device tree */
+
+/ {
+ model = "CN9130-CRB";
+ compatible = "marvell,cn9130-crb",
+ "marvell,cn9130",
+ "marvell,armada-ap806-quad",
+ "marvell,armada-ap806";
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ i2c0 = &cp0_i2c0;
+ spi0 = &cp0_spi1;
+ gpio0 = &ap_gpio0;
+ gpio1 = &cp0_gpio0;
+ gpio2 = &cp0_gpio1;
+ };
+
+ memory@00000000 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ cp0 {
+ config-space {
+ sdhci@780000 {
+ vqmmc-supply = <&cp0_reg_sd_vccq>;
+ vmmc-supply = <&cp0_reg_sd_vcc>;
+ };
+ cp0_reg_sd_vccq: cp0_sd_vccq@0 {
+ compatible = "regulator-gpio";
+ regulator-name = "cp0_sd_vccq";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&cp0_gpio1 18 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ };
+ cp0_reg_sd_vcc: cp0_sd_vcc@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp0_sd_vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&cp0_gpio1 22 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+/*
+ * AP related configuration
+ */
+&ap_pinctl {
+ /* MPP Bus:
+ * SDIO [0-10, 12]
+ * UART0 [11,19]
+ */
+ /* 0 1 2 3 4 5 6 7 8 9 */
+ pin-func = < 1 1 1 1 1 1 1 1 1 1
+ 1 3 1 0 0 0 0 0 0 3 >;
+};
+
+/* on-board eMMC - U6 */
+&ap_sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ap_emmc_pins>;
+ bus-width = <8>;
+ status = "okay";
+};
+
+/*
+ * CP related configuration
+ */
+&cp0_pinctl {
+ /* MPP Bus:
+ * [0-11] RGMII1
+ * [12] GPIO
+ * [13-16] SPI1
+ * [17-32] GPIO
+ * [33] SD_PWR_OFF
+ * [34] CP_PCIE0_CLKREQn
+ * [35-38] I2C1 I2C0
+ * [39] GPIO
+ * [40-43] SMI/XSMI
+ * [44-46] GPIO
+ * [47] UART1_TX
+ * [48] GPIO
+ * [49] SD_HST_18_EN
+ * [50] GPIO
+ * [51] SD_PWR_0
+ * [52] PCIE_RSTn
+ * [53] UART1_RX
+ * [54] GPIO
+ * [55] SD_DT
+ * [56-61] SDIO
+ *
+ * Note that CRB board revisions have different MPP configurations.
+ * r1p2 has SPI flash on MPP[30:27] and r1p3.1, which is the latest
+ * board revision, has it mapped to MPP[16:13].
+ */
+ /* 0 1 2 3 4 5 6 7 8 9 */
+ pin-func = < 3 3 3 3 3 3 3 3 3 3
+ 3 3 0 3 3 3 3 0 0 0
+ 0 0 0 0 0 0 0 0 0 0
+ 0 0 0 6 9 2 2 2 2 0
+ 8 8 8 8 0 0 0 7 0 0xa
+ 0 0xa 9 7 0 0xb 0xe 0xe 0xe 0xe
+ 0xe 0xe 0xe>;
+
+ cp0_sdhci_cd_pins_crb: cp0-sdhci-cd-pins-crb {
+ marvell,pins = < 55 >;
+ marvell,function = <0>;
+ };
+
+ cp0_spi1_pins_crb: cp0-spi-pins-crb {
+ marvell,pins = < 13 14 15 16 >;
+ marvell,function = <3>;
+ };
+
+ cp0_smi_pins_crb: cp0-smi-pins-crb {
+ marvell,pins = < 40 41 >;
+ marvell,function = <8>;
+ };
+
+ cp0_xsmi_pins_crb: cp0-xsmi-pins-crb {
+ marvell,pins = < 42 43 >;
+ marvell,function = <8>;
+ };
+
+};
+
+/*
+ * CP0
+ */
+&cp0_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_i2c0_pins>;
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+&cp0_i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_i2c1_pins>;
+ status = "okay";
+};
+
+&cp0_sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_sdhci_pins
+ &cp0_sdhci_cd_pins_crb>;
+ bus-width = <4>;
+ vqmmc-supply = <&cp0_reg_sd_vccq>;
+ vmmc-supply = <&cp0_reg_sd_vcc>;
+ status = "okay";
+};
+
+&cp0_spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_spi1_pins_crb>;
+ reg = <0x700680 0x50>, /* control */
+ <0x2000000 0x1000000>, /* CS0 */
+ <0 0xffffffff>, /* CS1 */
+ <0 0xffffffff>, /* CS2 */
+ <0 0xffffffff>; /* CS3 */
+ status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "jedec,spi-nor", "spi-flash";
+ reg = <0x0>;
+ /* On-board MUX does not allow higher frequencies */
+ spi-max-frequency = <40000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0x0 0x200000>;
+ };
+
+ partition@400000 {
+ label = "Filesystem";
+ reg = <0x200000 0xe00000>;
+ };
+ };
+ };
+};
+
+&cp0_utmi0 {
+ status = "okay";
+};
+
+&cp0_utmi1 {
+ status = "okay";
+};
+
+&cp0_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_smi_pins_crb>;
+ status = "okay";
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ switch6: ethernet-switch@6 {
+ reg = <6>;
+ };
+};
+
+&cp0_xmdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_xsmi_pins_crb>;
+ status = "okay";
+ nbaset_phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+&cp0_ethernet {
+ status = "okay";
+};
+
+&cp0_eth0 {
+ status = "okay";
+ phy-mode = "sfi";
+};
+
+&cp0_eth1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_ge1_rgmii_pins>;
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+};
+
+&cp0_eth2 {
+ /* Disable it for now, as mainline does not support this IF yet */
+ status = "disabled";
+ phy = <&nbaset_phy0>;
+};
diff --git a/arch/arm/dts/cn9130.dtsi b/arch/arm/dts/cn9130.dtsi
new file mode 100644
index 0000000..68b767a
--- /dev/null
+++ b/arch/arm/dts/cn9130.dtsi
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ */
+
+/*
+ * Device Tree file for the CN 9030 SoC, made of an AP806 Quad and
+ * one CP110.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include "armada-common.dtsi"
+#include "armada-ap807.dtsi"
+#include "armada-ap80x-quad.dtsi"
+
+/* This defines used to calculate the base address of each CP */
+#define CP110_BASE_OFFSET (0xf2000000)
+#define CP110_SPACE_SIZE (0x02000000)
+#define CP110_BASE (CP110_BASE_OFFSET + \
+ (CP110_NUM * CP110_SPACE_SIZE))
+
+#define CP110_PCIE_MEM_SIZE(iface) ((iface == 0) ? 0x1ff00000 : 0xf00000)
+#define CP110_PCIE_BUS_MEM_CFG (0x82000000)
+
+/* CP110-0 Settings */
+#define CP110_NAME cp0
+#define CP110_NUM 0
+#define CP110_PCIEx_CPU_MEM_BASE(iface) ((iface == 0) ? 0xc0000000 : \
+ (0xe0000000 + (iface - 1) * 0x1000000))
+#define CP110_PCIEx_BUS_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface))
+
+#include "armada-cp110.dtsi"
+
+/ {
+ model = "Marvell CN 9030";
+ compatible = "marvell,armada70x0", "marvell,armada-ap806-quad",
+ "marvell,armada-ap806";
+};
+
+&cp0_pinctl {
+ compatible = "marvell,mvebu-pinctrl", "marvell,armada-8k-cpm-pinctrl";
+ bank-name ="cp0-110";
+
+ cp0_i2c0_pins: cp0-i2c-pins-0 {
+ marvell,pins = < 37 38 >;
+ marvell,function = <2>;
+ };
+ cp0_i2c1_pins: cp0-i2c-pins-1 {
+ marvell,pins = < 35 36 >;
+ marvell,function = <2>;
+ };
+ cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
+ marvell,pins = < 0 1 2 3 4 5 6 7 8 9 10 11>;
+ marvell,function = <3>;
+ };
+ cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
+ marvell,pins = < 44 45 46 47 48 49 50 51
+ 52 53 54 55 >;
+ marvell,function = <1>;
+ };
+ cp0_pca0_pins: cp0-pca0_pins {
+ marvell,pins = <62>;
+ marvell,function = <0>;
+ };
+ cp0_sdhci_pins: cp0-sdhi-pins-0 {
+ marvell,pins = < 56 57 58 59 60 61 >;
+ marvell,function = <14>;
+ };
+ cp0_spi0_pins: cp0-spi-pins-0 {
+ marvell,pins = < 13 14 15 16 >;
+ marvell,function = <3>;
+ };
+};
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 0299611..cda65f7 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -141,6 +141,13 @@
select BOARD_LATE_INIT
imply SCSI
+config TARGET_OCTEONTX2_CN913x
+ bool "Support CN913x platforms"
+ select ARMADA_8K
+ imply BOARD_EARLY_INIT_R
+ select BOARD_LATE_INIT
+ imply SCSI
+
config TARGET_DB_MV784MP_GP
bool "Support db-mv784mp-gp"
select MV78460
@@ -187,6 +194,7 @@
default "turris_omnia" if TARGET_TURRIS_OMNIA
default "turris_mox" if TARGET_TURRIS_MOX
default "mvebu_armada-8k" if TARGET_MVEBU_ARMADA_8K
+ default "octeontx2_cn913x" if TARGET_OCTEONTX2_CN913x
default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
default "ds414" if TARGET_DS414
default "maxbcm" if TARGET_MAXBCM
@@ -204,6 +212,7 @@
default "db-88f6820-gp" if TARGET_DB_88F6820_GP
default "db-88f6820-amc" if TARGET_DB_88F6820_AMC
default "mvebu_armada-8k" if TARGET_MVEBU_ARMADA_8K
+ default "mvebu_armada-8k" if TARGET_OCTEONTX2_CN913x
default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
default "ds414" if TARGET_DS414
default "maxbcm" if TARGET_MAXBCM
@@ -222,6 +231,7 @@
default "Marvell" if TARGET_DB_88F6820_GP
default "Marvell" if TARGET_DB_88F6820_AMC
default "Marvell" if TARGET_MVEBU_ARMADA_8K
+ default "Marvell" if TARGET_OCTEONTX2_CN913x
default "Marvell" if TARGET_DB_XC3_24G4XG
default "Marvell" if TARGET_MVEBU_DB_88F7040
default "solidrun" if TARGET_CLEARFOG
diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c
index 486680a..15cbf92 100644
--- a/board/CZ.NIC/turris_mox/turris_mox.c
+++ b/board/CZ.NIC/turris_mox/turris_mox.c
@@ -216,13 +216,13 @@
if (sfpindex >= 0 && swindex >= 0) {
if (sfpindex < swindex)
- serdes_map[0].speed = PHY_SPEED_1_25G;
+ serdes_map[0].speed = COMPHY_SPEED_1_25G;
else
- serdes_map[0].speed = PHY_SPEED_3_125G;
+ serdes_map[0].speed = COMPHY_SPEED_3_125G;
} else if (sfpindex >= 0) {
- serdes_map[0].speed = PHY_SPEED_1_25G;
+ serdes_map[0].speed = COMPHY_SPEED_1_25G;
} else if (swindex >= 0) {
- serdes_map[0].speed = PHY_SPEED_3_125G;
+ serdes_map[0].speed = COMPHY_SPEED_3_125G;
}
return 0;
diff --git a/board/Marvell/octeontx2_cn913x/MAINTAINERS b/board/Marvell/octeontx2_cn913x/MAINTAINERS
new file mode 100644
index 0000000..d469e16
--- /dev/null
+++ b/board/Marvell/octeontx2_cn913x/MAINTAINERS
@@ -0,0 +1,5 @@
+OCTEONTX2_CN913x BOARD
+M: Kostya Porotchkin <kostap@marvell.com>
+S: Maintained
+F: board/Marvell/octeontx2_cn913x/
+F: configs/mvebu_crb_cn9130_defconfig
diff --git a/board/Marvell/octeontx2_cn913x/Makefile b/board/Marvell/octeontx2_cn913x/Makefile
new file mode 100644
index 0000000..8c6ffb9
--- /dev/null
+++ b/board/Marvell/octeontx2_cn913x/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2016 Stefan Roese <sr@denx.de>
+# Copyright (C) 2019 Marvell International Ltd.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := board.o
diff --git a/board/Marvell/octeontx2_cn913x/board.c b/board/Marvell/octeontx2_cn913x/board.c
new file mode 100644
index 0000000..953e9db
--- /dev/null
+++ b/board/Marvell/octeontx2_cn913x/board.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#include <dm.h>
+#include <power/regulator.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+__weak int soc_early_init_f(void)
+{
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ soc_early_init_f();
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ if (CONFIG_IS_ENABLED(DM_REGULATOR)) {
+ /* Check if any existing regulator should be turned down */
+ regulators_enable_boot_off(false);
+ }
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ return 0;
+}
diff --git a/cmd/mvebu/Kconfig b/cmd/mvebu/Kconfig
index ad10a57..f0e4f88 100644
--- a/cmd/mvebu/Kconfig
+++ b/cmd/mvebu/Kconfig
@@ -33,7 +33,7 @@
config MVEBU_MMC_BOOT
bool "eMMC flash boot"
- depends on MVEBU_MMC
+ depends on MVEBU_MMC || MMC_SDHCI_XENON
help
Enable boot from eMMC boot partition
Allow usage of eMMC/SD device as a target for "bubt" command
@@ -49,4 +49,11 @@
This option should contain a default file name to be used with
MVEBU "bubt" command if the source file name is omitted
+config CMD_MVEBU_RX_TRAINING
+ bool "rx_training"
+ depends on TARGET_MVEBU_ARMADA_8K
+ default n
+ help
+ Perform RX training sequence
+
endmenu
diff --git a/cmd/mvebu/Makefile b/cmd/mvebu/Makefile
index 96829c4..79299b0 100644
--- a/cmd/mvebu/Makefile
+++ b/cmd/mvebu/Makefile
@@ -4,5 +4,5 @@
#
# https://spdx.org/licenses
-
obj-$(CONFIG_CMD_MVEBU_BUBT) += bubt.o
+obj-$(CONFIG_CMD_MVEBU_RX_TRAINING) += rx_training.o
diff --git a/cmd/mvebu/bubt.c b/cmd/mvebu/bubt.c
index b649963..5cd520e 100644
--- a/cmd/mvebu/bubt.c
+++ b/cmd/mvebu/bubt.c
@@ -798,7 +798,7 @@
#define DEFAULT_BUBT_DST "nand"
#elif defined(CONFIG_MVEBU_MMC_BOOT)
#define DEFAULT_BUBT_DST "mmc"
-else
+#else
#define DEFAULT_BUBT_DST "error"
#endif
#endif /* DEFAULT_BUBT_DST */
diff --git a/cmd/mvebu/rx_training.c b/cmd/mvebu/rx_training.c
new file mode 100644
index 0000000..4bae765
--- /dev/null
+++ b/cmd/mvebu/rx_training.c
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <command.h>
+#include <console.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <dm/device-internal.h>
+#include <mvebu/comphy.h>
+
+int rx_training_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ struct udevice *dev;
+ struct uclass *uc;
+ int ret, cp_index, comphy_index, i = 0;
+
+ if (argc != 3) {
+ printf("missing arguments\n");
+ return -1;
+ }
+
+ cp_index = simple_strtoul(argv[1], NULL, 16);
+ comphy_index = simple_strtoul(argv[2], NULL, 16);
+
+ ret = uclass_get(UCLASS_MISC, &uc);
+ if (ret) {
+ printf("Couldn't find UCLASS_MISC\n");
+ return ret;
+ }
+
+ uclass_foreach_dev(dev, uc) {
+ if (!(memcmp(dev->name, "comphy", 5))) {
+ if (i == cp_index) {
+ comphy_rx_training(dev, comphy_index);
+ return 0;
+ }
+
+ i++;
+ }
+ }
+
+ printf("Coudn't find comphy %d\n", cp_index);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ rx_training, 3, 0, rx_training_cmd,
+ "rx_training <cp id> <comphy id>\n",
+ "\n\tRun RX training sequence, the user must state CP index (0/1) and comphy ID (0/5)"
+);
diff --git a/configs/mvebu_crb_cn9130_defconfig b/configs/mvebu_crb_cn9130_defconfig
new file mode 100644
index 0000000..03bc44b
--- /dev/null
+++ b/configs/mvebu_crb_cn9130_defconfig
@@ -0,0 +1,84 @@
+CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_TARGET_OCTEONTX2_CN913x=y
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x3f0000
+CONFIG_DEBUG_UART_BASE=0xf0512000
+CONFIG_DEBUG_UART_CLOCK=200000000
+CONFIG_DEFAULT_DEVICE_TREE="cn9130-crb-A"
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_ARCH_EARLY_INIT_R=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SYS_PROMPT="Marvell>> "
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_MVEBU_BUBT=y
+CONFIG_MVEBU_MMC_BOOT=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_AHCI_MVEBU=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_MISC=y
+CONFIG_MMC_BROKEN_CD=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_XENON=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_GIGE=y
+CONFIG_MVPP2=y
+CONFIG_NVME=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCIE_DW_MVEBU=y
+CONFIG_MVEBU_COMPHY_SUPPORT=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_ARMADA_8K=y
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_SYS_NS16550=y
+CONFIG_KIRKWOOD_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig
index a6bbe1a..95019b7 100644
--- a/configs/mvebu_db-88f3720_defconfig
+++ b/configs/mvebu_db-88f3720_defconfig
@@ -6,7 +6,7 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_TARGET_MVEBU_ARMADA_37XX=y
CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_OFFSET=0x180000
+CONFIG_ENV_OFFSET=0x3f0000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DM_GPIO=y
CONFIG_DEBUG_UART_BASE=0xd0012000
diff --git a/configs/mvebu_db_armada8k_defconfig b/configs/mvebu_db_armada8k_defconfig
index 5d8a1b6..96baea7 100644
--- a/configs/mvebu_db_armada8k_defconfig
+++ b/configs/mvebu_db_armada8k_defconfig
@@ -6,7 +6,7 @@
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_MVEBU_ARMADA_8K=y
CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_OFFSET=0x180000
+CONFIG_ENV_OFFSET=0x3f0000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEBUG_UART_BASE=0xf0512000
CONFIG_DEBUG_UART_CLOCK=200000000
@@ -32,6 +32,7 @@
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_MVEBU_BUBT=y
+CONFIG_CMD_MVEBU_RX_TRAINING=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_MAC_PARTITION=y
CONFIG_ENV_OVERWRITE=y
diff --git a/doc/device-tree-bindings/phy/mvebu_comphy.txt b/doc/device-tree-bindings/phy/mvebu_comphy.txt
new file mode 100644
index 0000000..65b8384
--- /dev/null
+++ b/doc/device-tree-bindings/phy/mvebu_comphy.txt
@@ -0,0 +1,68 @@
+Marvell COMPHY SerDes lane bindings
+=====================================
+
+The COMPHY node includes a description of the COMPHY SerDes lane configuration.
+The COMPHY driver initializes the MUX of the SerDes lanes, and powers up the SerDes
+by dependencies on the FDT blob configurations
+
+Mandatory properties:
+SoC specific:
+ - compatible:
+ The compatible should include "marvell,mvebu-comphy"
+ and the COMPHY per chip compatible:
+ "marvell,comphy-cp110" for CP110 available in Aramda70x0/80x0.
+ The COMPHY per chip used to set which MUX configuration to use, and COMPHY power-up revision.
+ - reg: Base address and size of the COMPHY and hpipe units.
+ - max-lanes: Maximum number of comphy lanes.
+ - mux-bitcount: Number of bits that are allocated for every MUX in the COMPHY-selector register.
+Board specific:
+ - PHY: Entry that include the configuration of the PHY.
+ Every PHY should have the below parameters:
+ - phy-type: the mode of the PHY
+ Possible modes located in include/dt-bindings/comphy/comphy_data.h
+ Optional properties:
+ - phy-speed: the speed of the PHY
+ Possible speeds values located in include/dt-bindings/comphy/comphy_data.h
+ - phy-invert: Polarity invert (COMPHY_POLARITY_TXD_INVERT/COMPHY_POLARITY_RXD_INVERT)
+ the possible bits under include/dt-bindings/comphy/comphy_data.h
+ - clk-src: Set the clock source of PCIe, if configured to PCIe clock output
+ This relevant for SerDes lane 5 only (by default, lane 4 is the clock source)
+ for Armada-7040 boards.
+ - endpoint: Optional boolean specifying this SerDes should be configured as PCIe endpoint.
+
+Example:
+ cpm_comphy: comphy@441000 {
+ compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110";
+ reg = <0x441000 0x8>, <0x120000 0x8>;
+ mux-bitcount = <4>;
+ max-lanes = <6>;
+
+ /*
+ * CP110 Serdes Configuration:
+ * Lane 0: SGMII1
+ * Lane 1: SATA 0
+ * Lane 2: USB HOST 0
+ * Lane 3: SATA1
+ * Lane 4: SFI (10G)
+ * Lane 5: SGMII2
+ */
+ phy0 {
+ phy-type = <COMPHY_TYPE_SGMII1>;
+ phy-speed = <COMPHY_SPEED_1_25G>;
+ };
+ phy1 {
+ phy-type = <COMPHY_TYPE_SATA0>;
+ };
+ phy2 {
+ phy-type = <COMPHY_TYPE_USB3_HOST0>;
+ };
+ phy3 {
+ phy-type = <COMPHY_TYPE_SATA1>;
+ };
+ phy4 {
+ phy-type = <COMPHY_TYPE_SFI>;
+ };
+ phy5 {
+ phy-type = <COMPHY_TYPE_SGMII2>;
+ };
+ };
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index b8ba00b..5d92257 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -91,9 +91,8 @@
}
#if defined(CONFIG_DM_ETH) && CONFIG_IS_ENABLED(DM_GPIO)
-static int dw_mdio_reset(struct mii_dev *bus)
+static int __dw_mdio_reset(struct udevice *dev)
{
- struct udevice *dev = bus->priv;
struct dw_eth_dev *priv = dev_get_priv(dev);
struct dw_eth_pdata *pdata = dev_get_plat(dev);
int ret;
@@ -122,6 +121,13 @@
return 0;
}
+
+static int dw_mdio_reset(struct mii_dev *bus)
+{
+ struct udevice *dev = bus->priv;
+
+ return __dw_mdio_reset(dev);
+}
#endif
#if IS_ENABLED(CONFIG_DM_MDIO)
@@ -142,9 +148,10 @@
#if CONFIG_IS_ENABLED(DM_GPIO)
int designware_eth_mdio_reset(struct udevice *mdio_dev)
{
- struct mdio_perdev_priv *pdata = dev_get_uclass_priv(mdio_dev);
+ struct mdio_perdev_priv *mdio_pdata = dev_get_uclass_priv(mdio_dev);
+ struct udevice *dev = mdio_pdata->mii_bus->priv;
- return dw_mdio_reset(pdata->mii_bus);
+ return __dw_mdio_reset(dev->parent);
}
#endif
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
index 3b9309f..c43d4f3 100644
--- a/drivers/pci/pci-aardvark.c
+++ b/drivers/pci/pci-aardvark.c
@@ -132,8 +132,9 @@
PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where))
/* PCIe Retries & Timeout definitions */
-#define MAX_RETRIES 10
-#define PIO_WAIT_TIMEOUT 100
+#define PIO_MAX_RETRIES 1500
+#define PIO_WAIT_TIMEOUT 1000
+#define LINK_MAX_RETRIES 10
#define LINK_WAIT_TIMEOUT 100000
#define CFG_RD_UR_VAL 0xFFFFFFFF
@@ -192,7 +193,7 @@
*
* @pcie: The PCI device to access
*
- * Wait up to 1 micro second for PIO access to be accomplished.
+ * Wait up to 1.5 seconds for PIO access to be accomplished.
*
* Return 1 (true) if PIO access is accomplished.
* Return 0 (false) if PIO access is timed out.
@@ -202,7 +203,7 @@
uint start, isr;
uint count;
- for (count = 0; count < MAX_RETRIES; count++) {
+ for (count = 0; count < PIO_MAX_RETRIES; count++) {
start = advk_readl(pcie, PIO_START);
isr = advk_readl(pcie, PIO_ISR);
if (!start && isr)
@@ -214,7 +215,7 @@
udelay(PIO_WAIT_TIMEOUT);
}
- dev_err(pcie->dev, "config read/write timed out\n");
+ dev_err(pcie->dev, "PIO read/write transfer time out\n");
return 0;
}
@@ -323,9 +324,14 @@
return 0;
}
- /* Start PIO */
- advk_writel(pcie, 0, PIO_START);
- advk_writel(pcie, 1, PIO_ISR);
+ if (advk_readl(pcie, PIO_START)) {
+ dev_err(pcie->dev,
+ "Previous PIO read/write transfer is still running\n");
+ if (offset != PCI_VENDOR_ID)
+ return -EINVAL;
+ *valuep = CFG_RD_CRS_VAL;
+ return 0;
+ }
/* Program the control register */
reg = advk_readl(pcie, PIO_CTRL);
@@ -342,10 +348,15 @@
advk_writel(pcie, 0, PIO_ADDR_MS);
/* Start the transfer */
+ advk_writel(pcie, 1, PIO_ISR);
advk_writel(pcie, 1, PIO_START);
- if (!pcie_advk_wait_pio(pcie))
- return -EINVAL;
+ if (!pcie_advk_wait_pio(pcie)) {
+ if (offset != PCI_VENDOR_ID)
+ return -EINVAL;
+ *valuep = CFG_RD_CRS_VAL;
+ return 0;
+ }
/* Check PIO status and get the read result */
ret = pcie_advk_check_pio_status(pcie, true, ®);
@@ -420,9 +431,11 @@
return 0;
}
- /* Start PIO */
- advk_writel(pcie, 0, PIO_START);
- advk_writel(pcie, 1, PIO_ISR);
+ if (advk_readl(pcie, PIO_START)) {
+ dev_err(pcie->dev,
+ "Previous PIO read/write transfer is still running\n");
+ return -EINVAL;
+ }
/* Program the control register */
reg = advk_readl(pcie, PIO_CTRL);
@@ -450,6 +463,7 @@
dev_dbg(pcie->dev, "\tPIO req. - strb = 0x%02x\n", reg);
/* Start the transfer */
+ advk_writel(pcie, 1, PIO_ISR);
advk_writel(pcie, 1, PIO_START);
if (!pcie_advk_wait_pio(pcie)) {
@@ -494,7 +508,7 @@
int retries;
/* check if the link is up or not */
- for (retries = 0; retries < MAX_RETRIES; retries++) {
+ for (retries = 0; retries < LINK_MAX_RETRIES; retries++) {
if (pcie_advk_link_up(pcie)) {
printf("PCIE-%d: Link up\n", pcie->first_busno);
return 0;
diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c
index 12523d1..06822d1 100644
--- a/drivers/phy/marvell/comphy_a3700.c
+++ b/drivers/phy/marvell/comphy_a3700.c
@@ -17,33 +17,33 @@
DECLARE_GLOBAL_DATA_PTR;
struct comphy_mux_data a3700_comphy_mux_data[] = {
-/* Lane 0 */
+ /* Lane 0 */
{
4,
{
- { PHY_TYPE_UNCONNECTED, 0x0 },
- { PHY_TYPE_SGMII1, 0x0 },
- { PHY_TYPE_USB3_HOST0, 0x1 },
- { PHY_TYPE_USB3_DEVICE, 0x1 }
+ { COMPHY_TYPE_UNCONNECTED, 0x0 },
+ { COMPHY_TYPE_SGMII1, 0x0 },
+ { COMPHY_TYPE_USB3_HOST0, 0x1 },
+ { COMPHY_TYPE_USB3_DEVICE, 0x1 }
}
},
-/* Lane 1 */
+ /* Lane 1 */
{
3,
{
- { PHY_TYPE_UNCONNECTED, 0x0},
- { PHY_TYPE_SGMII0, 0x0},
- { PHY_TYPE_PEX0, 0x1}
+ { COMPHY_TYPE_UNCONNECTED, 0x0},
+ { COMPHY_TYPE_SGMII0, 0x0},
+ { COMPHY_TYPE_PEX0, 0x1}
}
},
-/* Lane 2 */
+ /* Lane 2 */
{
4,
{
- { PHY_TYPE_UNCONNECTED, 0x0},
- { PHY_TYPE_SATA0, 0x0},
- { PHY_TYPE_USB3_HOST0, 0x1},
- { PHY_TYPE_USB3_DEVICE, 0x1}
+ { COMPHY_TYPE_UNCONNECTED, 0x0},
+ { COMPHY_TYPE_SATA0, 0x0},
+ { COMPHY_TYPE_USB3_HOST0, 0x1},
+ { COMPHY_TYPE_USB3_DEVICE, 0x1}
}
},
};
@@ -228,10 +228,10 @@
/*
* 10. Check the Polarity invert bit
*/
- if (invert & PHY_POLARITY_TXD_INVERT)
+ if (invert & COMPHY_POLARITY_TXD_INVERT)
reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_txd_inv, 0);
- if (invert & PHY_POLARITY_RXD_INVERT)
+ if (invert & COMPHY_POLARITY_RXD_INVERT)
reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_rxd_inv, 0);
/*
@@ -284,10 +284,10 @@
/*
* 0. Check the Polarity invert bits
*/
- if (invert & PHY_POLARITY_TXD_INVERT)
+ if (invert & COMPHY_POLARITY_TXD_INVERT)
data |= bs_txd_inv;
- if (invert & PHY_POLARITY_RXD_INVERT)
+ if (invert & COMPHY_POLARITY_RXD_INVERT)
data |= bs_rxd_inv;
reg_set_indirect(vphy_sync_pattern_reg, data, bs_txd_inv | bs_rxd_inv);
@@ -465,10 +465,10 @@
/*
* 9. Check the Polarity invert bit
*/
- if (invert & PHY_POLARITY_TXD_INVERT)
+ if (invert & COMPHY_POLARITY_TXD_INVERT)
usb3_reg_set16(SYNC_PATTERN, phy_txd_inv, 0, lane);
- if (invert & PHY_POLARITY_RXD_INVERT)
+ if (invert & COMPHY_POLARITY_RXD_INVERT)
usb3_reg_set16(SYNC_PATTERN, phy_rxd_inv, 0, lane);
/*
@@ -513,7 +513,7 @@
* Set Soft ID for Host mode (Device mode works with Hard ID
* detection)
*/
- if (type == PHY_TYPE_USB3_HOST0) {
+ if (type == COMPHY_TYPE_USB3_HOST0) {
/*
* set BIT0: set ID_MODE of Host/Device = "Soft ID" (BIT1)
* clear BIT1: set SOFT_ID = Host
@@ -685,8 +685,8 @@
* comparison to 3.125 Gbps values. These register values are
* stored in "sgmii_phy_init_fix" array.
*/
- if ((speed != PHY_SPEED_1_25G) &&
- (sgmii_phy_init_fix[fix_idx].addr == addr)) {
+ if (speed != COMPHY_SPEED_1_25G &&
+ sgmii_phy_init_fix[fix_idx].addr == addr) {
/* Use new value */
val = sgmii_phy_init_fix[fix_idx].value;
if (fix_idx < fix_arr_sz)
@@ -737,13 +737,13 @@
* 7. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide
* COMPHY bit rate
*/
- if (speed == PHY_SPEED_3_125G) { /* 3.125 GHz */
+ if (speed == COMPHY_SPEED_3_125G) { /* 3.125 GHz */
reg_set(COMPHY_PHY_CFG1_ADDR(lane),
(0x8 << rf_gen_rx_sel_shift) |
(0x8 << rf_gen_tx_sel_shift),
rf_gen_rx_select | rf_gen_tx_select);
- } else if (speed == PHY_SPEED_1_25G) { /* 1.25 GHz */
+ } else if (speed == COMPHY_SPEED_1_25G) { /* 1.25 GHz */
reg_set(COMPHY_PHY_CFG1_ADDR(lane),
(0x6 << rf_gen_rx_sel_shift) |
(0x6 << rf_gen_tx_sel_shift),
@@ -819,7 +819,7 @@
* registers are OK.
*/
debug("Running C-DPI phy init %s mode\n",
- speed == PHY_SPEED_3_125G ? "2G5" : "1G");
+ speed == COMPHY_SPEED_3_125G ? "2G5" : "1G");
if (get_ref_clk() == 40)
comphy_sgmii_phy_init(lane, speed);
@@ -837,10 +837,10 @@
/*
* 18. Check the PHY Polarity invert bit
*/
- if (invert & PHY_POLARITY_TXD_INVERT)
+ if (invert & COMPHY_POLARITY_TXD_INVERT)
reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_txd_inv, 0);
- if (invert & PHY_POLARITY_RXD_INVERT)
+ if (invert & COMPHY_POLARITY_RXD_INVERT)
reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_rxd_inv, 0);
/*
@@ -976,30 +976,30 @@
comphy_map->type, comphy_map->invert);
switch (comphy_map->type) {
- case PHY_TYPE_UNCONNECTED:
+ case COMPHY_TYPE_UNCONNECTED:
continue;
break;
- case PHY_TYPE_PEX0:
+ case COMPHY_TYPE_PEX0:
ret = comphy_pcie_power_up(comphy_map->speed,
comphy_map->invert);
break;
- case PHY_TYPE_USB3_HOST0:
- case PHY_TYPE_USB3_DEVICE:
+ case COMPHY_TYPE_USB3_HOST0:
+ case COMPHY_TYPE_USB3_DEVICE:
ret = comphy_usb3_power_up(lane,
comphy_map->type,
comphy_map->speed,
comphy_map->invert);
break;
- case PHY_TYPE_SGMII0:
- case PHY_TYPE_SGMII1:
+ case COMPHY_TYPE_SGMII0:
+ case COMPHY_TYPE_SGMII1:
ret = comphy_sgmii_power_up(lane, comphy_map->speed,
comphy_map->invert);
break;
- case PHY_TYPE_SATA0:
+ case COMPHY_TYPE_SATA0:
ret = comphy_sata_power_up(comphy_map->invert);
break;
diff --git a/drivers/phy/marvell/comphy_a3700.h b/drivers/phy/marvell/comphy_a3700.h
index b0941ff..8748c6c 100644
--- a/drivers/phy/marvell/comphy_a3700.h
+++ b/drivers/phy/marvell/comphy_a3700.h
@@ -7,7 +7,6 @@
#define _COMPHY_A3700_H_
#include "comphy_core.h"
-#include "comphy_hpipe.h"
#define MVEBU_REG(offs) \
((void __iomem *)(ulong)MVEBU_REGISTER(offs))
diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c
index cd54e7f..2c9d7b2 100644
--- a/drivers/phy/marvell/comphy_core.c
+++ b/drivers/phy/marvell/comphy_core.c
@@ -24,12 +24,12 @@
static const char *get_speed_string(u32 speed)
{
static const char * const speed_strings[] = {
- "1.25 Gbps", "1.5 Gbps", "2.5 Gbps",
- "3.0 Gbps", "3.125 Gbps", "5 Gbps", "6 Gbps",
- "6.25 Gbps", "10.31 Gbps"
+ "1.25 Gbps", "2.5 Gbps", "3.125 Gbps",
+ "5 Gbps", "5.125 Gpbs", "6 Gbps",
+ "10.3125 Gbps"
};
- if (speed < 0 || speed > PHY_SPEED_MAX)
+ if (speed < 0 || speed > COMPHY_SPEED_MAX)
return "invalid";
return speed_strings[speed];
@@ -39,14 +39,13 @@
{
static const char * const type_strings[] = {
"UNCONNECTED", "PEX0", "PEX1", "PEX2", "PEX3",
- "SATA0", "SATA1", "SATA2", "SATA3", "SGMII0",
- "SGMII1", "SGMII2", "SGMII3", "QSGMII",
- "USB3_HOST0", "USB3_HOST1", "USB3_DEVICE",
- "XAUI0", "XAUI1", "XAUI2", "XAUI3",
- "RXAUI0", "RXAUI1", "SFI", "IGNORE"
+ "SATA0", "SATA1", "SGMII0", "SGMII1", "SGMII2",
+ "USB3", "USB3_HOST0", "USB3_HOST1",
+ "USB3_DEVICE", "RXAUI0", "RXAUI1", "SFI0", "SFI1", "AP",
+ "IGNORE"
};
- if (type < 0 || type > PHY_TYPE_MAX)
+ if (type < 0 || type > COMPHY_TYPE_MAX)
return "invalid";
return type_strings[type];
@@ -59,7 +58,7 @@
for (lane = 0; lane < chip_cfg->comphy_lanes_count;
lane++, comphy_map_data++) {
- if (comphy_map_data->speed == PHY_SPEED_INVALID) {
+ if (comphy_map_data->speed == COMPHY_SPEED_INVALID) {
printf("Comphy-%d: %-13s\n", lane,
get_type_string(comphy_map_data->type));
} else {
@@ -70,6 +69,16 @@
}
}
+int comphy_rx_training(struct udevice *dev, u32 lane)
+{
+ struct chip_serdes_phy_config *chip_cfg = dev_get_priv(dev);
+
+ if (chip_cfg->rx_training)
+ return chip_cfg->rx_training(chip_cfg, lane);
+
+ return 0;
+}
+
__weak int comphy_update_map(struct comphy_map *serdes_map, int count)
{
return 0;
@@ -80,7 +89,6 @@
const void *blob = gd->fdt_blob;
int node = dev_of_offset(dev);
struct chip_serdes_phy_config *chip_cfg = dev_get_priv(dev);
- struct comphy_map comphy_map_data[MAX_LANE_OPTIONS];
int subnode;
int lane;
int last_idx = 0;
@@ -114,11 +122,15 @@
fdtdec_locate_array(blob, node, "mux-lane-order",
chip_cfg->comphy_lanes_count);
- if (device_is_compatible(dev, "marvell,comphy-armada-3700"))
+ if (device_is_compatible(dev, "marvell,comphy-armada-3700")) {
chip_cfg->ptr_comphy_chip_init = comphy_a3700_init;
+ chip_cfg->rx_training = NULL;
+ }
- if (device_is_compatible(dev, "marvell,comphy-cp110"))
+ if (device_is_compatible(dev, "marvell,comphy-cp110")) {
chip_cfg->ptr_comphy_chip_init = comphy_cp110_init;
+ chip_cfg->rx_training = comphy_cp110_sfi_rx_training;
+ }
/*
* Bail out if no chip_init function is defined, e.g. no
@@ -135,36 +147,45 @@
if (!fdtdec_get_is_enabled(blob, subnode))
continue;
+ chip_cfg->comphy_map_data[lane].type =
+ fdtdec_get_int(blob, subnode, "phy-type",
+ COMPHY_TYPE_INVALID);
+
- comphy_map_data[lane].speed = fdtdec_get_int(
- blob, subnode, "phy-speed", PHY_TYPE_INVALID);
- comphy_map_data[lane].type = fdtdec_get_int(
- blob, subnode, "phy-type", PHY_SPEED_INVALID);
- comphy_map_data[lane].invert = fdtdec_get_int(
- blob, subnode, "phy-invert", PHY_POLARITY_NO_INVERT);
- comphy_map_data[lane].clk_src = fdtdec_get_bool(blob, subnode,
- "clk-src");
- comphy_map_data[lane].end_point = fdtdec_get_bool(blob, subnode,
- "end_point");
- if (comphy_map_data[lane].type == PHY_TYPE_INVALID) {
+ if (chip_cfg->comphy_map_data[lane].type ==
+ COMPHY_TYPE_INVALID) {
printf("no phy type for lane %d, setting lane as unconnected\n",
lane + 1);
+ continue;
}
+ chip_cfg->comphy_map_data[lane].speed =
+ fdtdec_get_int(blob, subnode, "phy-speed",
+ COMPHY_SPEED_INVALID);
+
+ chip_cfg->comphy_map_data[lane].invert =
+ fdtdec_get_int(blob, subnode, "phy-invert",
+ COMPHY_POLARITY_NO_INVERT);
+
+ chip_cfg->comphy_map_data[lane].clk_src =
+ fdtdec_get_bool(blob, subnode, "clk-src");
+
+ chip_cfg->comphy_map_data[lane].end_point =
+ fdtdec_get_bool(blob, subnode, "end_point");
+
lane++;
}
- res = comphy_update_map(comphy_map_data, chip_cfg->comphy_lanes_count);
+ res = comphy_update_map(chip_cfg->comphy_map_data, chip_cfg->comphy_lanes_count);
if (res < 0)
return res;
/* Save CP index for MultiCP devices (A8K) */
chip_cfg->cp_index = current_idx++;
/* PHY power UP sequence */
- chip_cfg->ptr_comphy_chip_init(chip_cfg, comphy_map_data);
+ chip_cfg->ptr_comphy_chip_init(chip_cfg, chip_cfg->comphy_map_data);
/* PHY print SerDes status */
- if (of_machine_is_compatible("marvell,armada8040"))
- printf("Comphy chip #%d:\n", chip_cfg->cp_index);
- comphy_print(chip_cfg, comphy_map_data);
+ printf("Comphy chip #%d:\n", chip_cfg->cp_index);
+ comphy_print(chip_cfg, chip_cfg->comphy_map_data);
/*
* Only run the dedicated PHY init code once, in the last PHY init call
diff --git a/drivers/phy/marvell/comphy_core.h b/drivers/phy/marvell/comphy_core.h
index 12ab921..ba64491 100644
--- a/drivers/phy/marvell/comphy_core.h
+++ b/drivers/phy/marvell/comphy_core.h
@@ -17,58 +17,8 @@
#define debug_exit()
#endif
-/* COMPHY registers */
-#define COMMON_PHY_CFG1_REG 0x0
-#define COMMON_PHY_CFG1_PWR_UP_OFFSET 1
-#define COMMON_PHY_CFG1_PWR_UP_MASK \
- (0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET)
-#define COMMON_PHY_CFG1_PIPE_SELECT_OFFSET 2
-#define COMMON_PHY_CFG1_PIPE_SELECT_MASK \
- (0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET)
-#define COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET 13
-#define COMMON_PHY_CFG1_PWR_ON_RESET_MASK \
- (0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET)
-#define COMMON_PHY_CFG1_CORE_RSTN_OFFSET 14
-#define COMMON_PHY_CFG1_CORE_RSTN_MASK \
- (0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET)
-#define COMMON_PHY_PHY_MODE_OFFSET 15
-#define COMMON_PHY_PHY_MODE_MASK \
- (0x1 << COMMON_PHY_PHY_MODE_OFFSET)
-
-#define COMMON_PHY_CFG6_REG 0x14
-#define COMMON_PHY_CFG6_IF_40_SEL_OFFSET 18
-#define COMMON_PHY_CFG6_IF_40_SEL_MASK \
- (0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET)
-
-#define COMMON_SELECTOR_PHY_OFFSET 0x140
-#define COMMON_SELECTOR_PIPE_OFFSET 0x144
-
-#define COMMON_PHY_SD_CTRL1 0x148
-#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET 0
-#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK 0xFFFF
-#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET 24
-#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK \
- (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET)
-#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET 25
-#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK \
- (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET)
-#define COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET 26
-#define COMMON_PHY_SD_CTRL1_RXAUI1_MASK \
- (0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET)
-#define COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET 27
-#define COMMON_PHY_SD_CTRL1_RXAUI0_MASK \
- (0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET)
-
-/* ToDo: Get this address via DT */
-#define MVEBU_CP0_REGS_BASE 0xF2000000UL
-
-#define DFX_DEV_GEN_CTRL12 (MVEBU_CP0_REGS_BASE + 0x400280)
-#define DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET 7
-#define DFX_DEV_GEN_PCIE_CLK_SRC_MASK \
- (0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET)
-
#define MAX_LANE_OPTIONS 10
-#define MAX_UTMI_PHY_COUNT 3
+#define MAX_UTMI_PHY_COUNT 6
struct comphy_mux_options {
u32 type;
@@ -84,12 +34,14 @@
struct comphy_mux_data *mux_data;
int (*ptr_comphy_chip_init)(struct chip_serdes_phy_config *,
struct comphy_map *);
+ int (*rx_training)(struct chip_serdes_phy_config *, u32);
void __iomem *comphy_base_addr;
void __iomem *hpipe3_base_addr;
u32 comphy_lanes_count;
u32 comphy_mux_bitcount;
const fdt32_t *comphy_mux_lane_order;
u32 cp_index;
+ struct comphy_map comphy_map_data[MAX_LANE_OPTIONS];
};
/* Register helper functions */
@@ -150,6 +102,8 @@
#ifdef CONFIG_ARMADA_8K
int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
struct comphy_map *serdes_map);
+int comphy_cp110_sfi_rx_training(struct chip_serdes_phy_config *ptr_chip_cfg,
+ u32 lane);
#else
static inline int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
struct comphy_map *serdes_map)
@@ -160,6 +114,17 @@
*/
return -1;
}
+
+static inline int comphy_cp110_sfi_rx_training(
+ struct chip_serdes_phy_config *ptr_chip_cfg,
+ u32 lane)
+{
+ /*
+ * This function should never be called in this configuration, so
+ * lets return an error here.
+ */
+ return -1;
+}
#endif
void comphy_dedicated_phys_init(void);
diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c
index a323de7..418318d 100644
--- a/drivers/phy/marvell/comphy_cp110.c
+++ b/drivers/phy/marvell/comphy_cp110.c
@@ -14,20 +14,16 @@
#include <linux/delay.h>
#include "comphy_core.h"
-#include "comphy_hpipe.h"
#include "sata.h"
#include "utmi_phy.h"
DECLARE_GLOBAL_DATA_PTR;
-#define SD_ADDR(base, lane) (base + 0x1000 * lane)
-#define HPIPE_ADDR(base, lane) (SD_ADDR(base, lane) + 0x800)
-#define COMPHY_ADDR(base, lane) (base + 0x28 * lane)
-
/* Firmware related definitions used for SMC calls */
#define MV_SIP_COMPHY_POWER_ON 0x82000001
#define MV_SIP_COMPHY_POWER_OFF 0x82000002
#define MV_SIP_COMPHY_PLL_LOCK 0x82000003
+#define MV_SIP_COMPHY_XFI_TRAIN 0x82000004
/* Used to distinguish between different possible callers (U-boot/Linux) */
#define COMPHY_CALLER_UBOOT (0x1 << 21)
@@ -59,52 +55,13 @@
#define COMPHY_UNIT_ID3 3
struct utmi_phy_data {
+ void __iomem *utmi_pll_addr;
void __iomem *utmi_base_addr;
void __iomem *usb_cfg_addr;
void __iomem *utmi_cfg_addr;
u32 utmi_phy_port;
};
-/*
- * For CP-110 we have 2 Selector registers "PHY Selectors",
- * and "PIPE Selectors".
- * PIPE selector include USB and PCIe options.
- * PHY selector include the Ethernet and SATA options, every Ethernet
- * option has different options, for example: serdes lane2 had option
- * Eth_port_0 that include (SGMII0, RXAUI0, SFI)
- */
-struct comphy_mux_data cp110_comphy_phy_mux_data[] = {
- {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII1, 0x1}, /* Lane 0 */
- {PHY_TYPE_SATA1, 0x4} } },
- {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 1 */
- {PHY_TYPE_SATA0, 0x4} } },
- {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 2 */
- {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_SFI, 0x1},
- {PHY_TYPE_SATA0, 0x4} } },
- {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_RXAUI1, 0x1}, /* Lane 3 */
- {PHY_TYPE_SGMII1, 0x2}, {PHY_TYPE_SATA1, 0x4} } },
- {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, /* Lane 4 */
- {PHY_TYPE_RXAUI0, 0x2}, {PHY_TYPE_SFI, 0x2},
- {PHY_TYPE_SGMII1, 0x1} } },
- {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 5 */
- {PHY_TYPE_RXAUI1, 0x2}, {PHY_TYPE_SATA1, 0x4} } },
-};
-
-struct comphy_mux_data cp110_comphy_pipe_mux_data[] = {
- {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX0, 0x4} } }, /* Lane 0 */
- {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 1 */
- {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_USB3_DEVICE, 0x2},
- {PHY_TYPE_PEX0, 0x4} } },
- {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 2 */
- {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_PEX0, 0x4} } },
- {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 3 */
- {PHY_TYPE_USB3_HOST1, 0x1}, {PHY_TYPE_PEX0, 0x4} } },
- {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 4 */
- {PHY_TYPE_USB3_HOST1, 0x1},
- {PHY_TYPE_USB3_DEVICE, 0x2}, {PHY_TYPE_PEX1, 0x4} } },
- {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX2, 0x4} } }, /* Lane 5 */
-};
-
static u32 polling_with_timeout(void __iomem *addr, u32 val,
u32 mask, unsigned long usec_timout)
{
@@ -121,128 +78,6 @@
return 0;
}
-static int comphy_usb3_power_up(u32 lane, void __iomem *hpipe_base,
- void __iomem *comphy_base)
-{
- u32 mask, data, ret = 1;
- void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
- void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane);
- void __iomem *addr;
-
- debug_enter();
- debug("stage: RFU configurations - hard reset comphy\n");
- /* RFU configurations - hard reset comphy */
- mask = COMMON_PHY_CFG1_PWR_UP_MASK;
- data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
- mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
- data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
- mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
- data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
- mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
- data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
- mask |= COMMON_PHY_PHY_MODE_MASK;
- data |= 0x1 << COMMON_PHY_PHY_MODE_OFFSET;
- reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
-
- /* release from hard reset */
- mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
- data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
- mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
- data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
- reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
-
- /* Wait 1ms - until band gap and ref clock ready */
- mdelay(1);
-
- /* Start comphy Configuration */
- debug("stage: Comphy configuration\n");
- /* Set PIPE soft reset */
- mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK;
- data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET;
- /* Set PHY datapath width mode for V0 */
- mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK;
- data |= 0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET;
- /* Set Data bus width USB mode for V0 */
- mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK;
- data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET;
- /* Set CORE_CLK output frequency for 250Mhz */
- mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK;
- data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET;
- reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask);
- /* Set PLL ready delay for 0x2 */
- reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG,
- 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET,
- HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK);
- /* Set reference clock to come from group 1 - 25Mhz */
- reg_set(hpipe_addr + HPIPE_MISC_REG,
- 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET,
- HPIPE_MISC_REFCLK_SEL_MASK);
- /* Set reference frequcency select - 0x2 */
- mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
- data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
- /* Set PHY mode to USB - 0x5 */
- mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
- data |= 0x5 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
- reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
- /* Set the amount of time spent in the LoZ state - set for 0x7 */
- reg_set(hpipe_addr + HPIPE_GLOBAL_PM_CTRL,
- 0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET,
- HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK);
- /* Set max PHY generation setting - 5Gbps */
- reg_set(hpipe_addr + HPIPE_INTERFACE_REG,
- 0x1 << HPIPE_INTERFACE_GEN_MAX_OFFSET,
- HPIPE_INTERFACE_GEN_MAX_MASK);
- /* Set select data width 20Bit (SEL_BITS[2:0]) */
- reg_set(hpipe_addr + HPIPE_LOOPBACK_REG,
- 0x1 << HPIPE_LOOPBACK_SEL_OFFSET,
- HPIPE_LOOPBACK_SEL_MASK);
- /* select de-emphasize 3.5db */
- reg_set(hpipe_addr + HPIPE_LANE_CONFIG0_REG,
- 0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET,
- HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK);
- /* override tx margining from the MAC */
- reg_set(hpipe_addr + HPIPE_TST_MODE_CTRL_REG,
- 0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET,
- HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK);
-
- /* Start analog paramters from ETP(HW) */
- debug("stage: Analog paramters from ETP(HW)\n");
- /* Set Pin DFE_PAT_DIS -> Bit[1]: PIN_DFE_PAT_DIS = 0x0 */
- mask = HPIPE_LANE_CFG4_DFE_CTRL_MASK;
- data = 0x1 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET;
- /* Set Override PHY DFE control pins for 0x1 */
- mask |= HPIPE_LANE_CFG4_DFE_OVER_MASK;
- data |= 0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET;
- /* Set Spread Spectrum Clock Enable fot 0x1 */
- mask |= HPIPE_LANE_CFG4_SSC_CTRL_MASK;
- data |= 0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET;
- reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask);
- /* End of analog parameters */
-
- debug("stage: Comphy power up\n");
- /* Release from PIPE soft reset */
- reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG,
- 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET,
- HPIPE_RST_CLK_CTRL_PIPE_RST_MASK);
-
- /* wait 15ms - for comphy calibration done */
- debug("stage: Check PLL\n");
- /* Read lane status */
- addr = hpipe_addr + HPIPE_LANE_STATUS1_REG;
- data = HPIPE_LANE_STATUS1_PCLK_EN_MASK;
- mask = data;
- data = polling_with_timeout(addr, data, mask, 15000);
- if (data != 0) {
- debug("Read from reg = %p - value = 0x%x\n",
- hpipe_addr + HPIPE_LANE_STATUS1_REG, data);
- pr_err("HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n");
- ret = 0;
- }
-
- debug_exit();
- return ret;
-}
-
static int comphy_smc(u32 function_id, void __iomem *comphy_base_addr,
u32 lane, u32 mode)
{
@@ -263,6 +98,35 @@
return pregs.regs[0] ? 0 : 1;
}
+/* This function performs RX training for all FFE possible values.
+ * We get the result for each FFE and eventually the best FFE will
+ * be used and set to the HW.
+ *
+ * Return '1' on succsess.
+ * Return '0' on failure.
+ */
+int comphy_cp110_sfi_rx_training(struct chip_serdes_phy_config *ptr_chip_cfg,
+ u32 lane)
+{
+ int ret;
+ u32 type = ptr_chip_cfg->comphy_map_data[lane].type;
+
+ debug_enter();
+
+ if (type != COMPHY_TYPE_SFI0 && type != COMPHY_TYPE_SFI1) {
+ pr_err("Comphy %d isn't configured to SFI\n", lane);
+ return 0;
+ }
+
+ /* Mode is not relevant for xfi training */
+ ret = comphy_smc(MV_SIP_COMPHY_XFI_TRAIN,
+ ptr_chip_cfg->comphy_base_addr, lane, 0);
+
+ debug_exit();
+
+ return ret;
+}
+
static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base,
void __iomem *comphy_base_addr, int cp_index,
u32 type)
@@ -357,184 +221,6 @@
return ret;
}
-static int comphy_rxauii_power_up(u32 lane, void __iomem *hpipe_base,
- void __iomem *comphy_base)
-{
- u32 mask, data, ret = 1;
- void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
- void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane);
- void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane);
- void __iomem *addr;
-
- debug_enter();
- debug("stage: RFU configurations - hard reset comphy\n");
- /* RFU configurations - hard reset comphy */
- mask = COMMON_PHY_CFG1_PWR_UP_MASK;
- data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
- mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
- data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
- reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
-
- if (lane == 2) {
- reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
- 0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET,
- COMMON_PHY_SD_CTRL1_RXAUI0_MASK);
- }
- if (lane == 4) {
- reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
- 0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET,
- COMMON_PHY_SD_CTRL1_RXAUI1_MASK);
- }
-
- /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */
- mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
- data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
- mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK;
- data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET;
- mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK;
- data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET;
- mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
- data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
- mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
- data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
- mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK;
- data |= 0x0 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET;
- mask |= SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK;
- data |= 0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET;
- reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
-
- /* release from hard reset */
- mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
- data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
- mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
- data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
- mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
- data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
- reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
-
- mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
- data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
- mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
- data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
- reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
-
- /* Wait 1ms - until band gap and ref clock ready */
- mdelay(1);
-
- /* Start comphy Configuration */
- debug("stage: Comphy configuration\n");
- /* set reference clock */
- reg_set(hpipe_addr + HPIPE_MISC_REG,
- 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET,
- HPIPE_MISC_REFCLK_SEL_MASK);
- /* Power and PLL Control */
- mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
- data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
- mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
- data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
- reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
- /* Loopback register */
- reg_set(hpipe_addr + HPIPE_LOOPBACK_REG,
- 0x1 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK);
- /* rx control 1 */
- mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK;
- data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET;
- mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK;
- data |= 0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET;
- reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask);
- /* DTL Control */
- reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG,
- 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET,
- HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK);
-
- /* Set analog paramters from ETP(HW) */
- debug("stage: Analog paramters from ETP(HW)\n");
- /* SERDES External Configuration 2 */
- reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG,
- 0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET,
- SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK);
- /* 0x7-DFE Resolution control */
- reg_set(hpipe_addr + HPIPE_DFE_REG0, 0x1 << HPIPE_DFE_RES_FORCE_OFFSET,
- HPIPE_DFE_RES_FORCE_MASK);
- /* 0xd-G1_Setting_0 */
- reg_set(hpipe_addr + HPIPE_G1_SET_0_REG,
- 0xd << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET,
- HPIPE_G1_SET_0_G1_TX_EMPH1_MASK);
- /* 0xE-G1_Setting_1 */
- mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
- data = 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
- mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK;
- data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
- mask |= HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK;
- data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET;
- reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask);
- /* 0xA-DFE_Reg3 */
- mask = HPIPE_DFE_F3_F5_DFE_EN_MASK;
- data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET;
- mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK;
- data |= 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET;
- reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask);
-
- /* 0x111-G1_Setting_4 */
- mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK;
- data = 0x1 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET;
- reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask);
-
- debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n");
- /* SERDES External Configuration */
- mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
- data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
- mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
- data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
- mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
- data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
- reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
-
-
- /* check PLL rx & tx ready */
- addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
- data = SD_EXTERNAL_STATUS0_PLL_RX_MASK |
- SD_EXTERNAL_STATUS0_PLL_TX_MASK;
- mask = data;
- data = polling_with_timeout(addr, data, mask, 15000);
- if (data != 0) {
- debug("Read from reg = %p - value = 0x%x\n",
- sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data);
- pr_err("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n",
- (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK),
- (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK));
- ret = 0;
- }
-
- /* RX init */
- reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG,
- 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET,
- SD_EXTERNAL_CONFIG1_RX_INIT_MASK);
-
- /* check that RX init done */
- addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
- data = SD_EXTERNAL_STATUS0_RX_INIT_MASK;
- mask = data;
- data = polling_with_timeout(addr, data, mask, 100);
- if (data != 0) {
- debug("Read from reg = %p - value = 0x%x\n",
- sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data);
- pr_err("SD_EXTERNAL_STATUS0_RX_INIT is 0\n");
- ret = 0;
- }
-
- debug("stage: RF Reset\n");
- /* RF Reset */
- mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
- data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
- mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
- data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
- reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
-
- debug_exit();
- return ret;
-}
-
static void comphy_utmi_power_down(u32 utmi_index, void __iomem *utmi_base_addr,
void __iomem *usb_cfg_addr,
void __iomem *utmi_cfg_addr,
@@ -580,7 +266,8 @@
return;
}
-static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_base_addr,
+static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_pll_addr,
+ void __iomem *utmi_base_addr,
void __iomem *usb_cfg_addr,
void __iomem *utmi_cfg_addr,
u32 utmi_phy_port)
@@ -598,27 +285,37 @@
/* Select LPFR - 0x0 for 25Mhz/5=5Mhz*/
mask |= UTMI_PLL_CTRL_SEL_LPFR_MASK;
data |= 0x0 << UTMI_PLL_CTRL_SEL_LPFR_OFFSET;
- reg_set(utmi_base_addr + UTMI_PLL_CTRL_REG, data, mask);
+ reg_set(utmi_pll_addr + UTMI_PLL_CTRL_REG, data, mask);
/* Impedance Calibration Threshold Setting */
- reg_set(utmi_base_addr + UTMI_CALIB_CTRL_REG,
- 0x6 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET,
- UTMI_CALIB_CTRL_IMPCAL_VTH_MASK);
+ mask = UTMI_CALIB_CTRL_IMPCAL_VTH_MASK;
+ data = 0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET;
+ reg_set(utmi_pll_addr + UTMI_CALIB_CTRL_REG, data, mask);
+
+ /* Start Impedance and PLL Calibration */
+ mask = UTMI_CALIB_CTRL_PLLCAL_START_MASK;
+ data = (0x1 << UTMI_CALIB_CTRL_PLLCAL_START_OFFSET);
+ mask |= UTMI_CALIB_CTRL_IMPCAL_START_MASK;
+ data |= (0x1 << UTMI_CALIB_CTRL_IMPCAL_START_OFFSET);
+ reg_set(utmi_pll_addr + UTMI_CALIB_CTRL_REG, data, mask);
/* Set LS TX driver strength coarse control */
- mask = UTMI_TX_CH_CTRL_DRV_EN_LS_MASK;
- data = 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET;
- /* Set LS TX driver fine adjustment */
+ mask = UTMI_TX_CH_CTRL_AMP_MASK;
+ data = 0x4 << UTMI_TX_CH_CTRL_AMP_OFFSET;
mask |= UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK;
data |= 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET;
+ mask |= UTMI_TX_CH_CTRL_DRV_EN_LS_MASK;
+ data |= 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET;
reg_set(utmi_base_addr + UTMI_TX_CH_CTRL_REG, data, mask);
/* Enable SQ */
mask = UTMI_RX_CH_CTRL0_SQ_DET_MASK;
- data = 0x0 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET;
+ data = 0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET;
/* Enable analog squelch detect */
mask |= UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK;
- data |= 0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET;
+ data |= 0x0 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET;
+ mask |= UTMI_RX_CH_CTRL0_DISCON_THRESH_MASK;
+ data |= 0x0 << UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET;
reg_set(utmi_base_addr + UTMI_RX_CH_CTRL0_REG, data, mask);
/* Set External squelch calibration number */
@@ -641,7 +338,8 @@
return;
}
-static int comphy_utmi_power_up(u32 utmi_index, void __iomem *utmi_base_addr,
+static int comphy_utmi_power_up(u32 utmi_index, void __iomem *utmi_pll_addr,
+ void __iomem *utmi_base_addr,
void __iomem *usb_cfg_addr,
void __iomem *utmi_cfg_addr, u32 utmi_phy_port)
{
@@ -660,7 +358,7 @@
UTMI_CTRL_STATUS0_TEST_SEL_MASK);
debug("stage: Polling for PLL and impedance calibration done, and PLL ready done\n");
- addr = utmi_base_addr + UTMI_CALIB_CTRL_REG;
+ addr = utmi_pll_addr + UTMI_CALIB_CTRL_REG;
data = UTMI_CALIB_CTRL_IMPCAL_DONE_MASK;
mask = data;
data = polling_with_timeout(addr, data, mask, 100);
@@ -679,7 +377,7 @@
ret = 0;
}
- addr = utmi_base_addr + UTMI_PLL_CTRL_REG;
+ addr = utmi_pll_addr + UTMI_PLL_CTRL_REG;
data = UTMI_PLL_CTRL_PLL_RDY_MASK;
mask = data;
data = polling_with_timeout(addr, data, mask, 100);
@@ -703,7 +401,7 @@
* the init split in 3 parts:
* 1. Power down transceiver and PLL
* 2. UTMI PHY configure
- * 3. Powe up transceiver and PLL
+ * 3. Power up transceiver and PLL
* Note: - Power down/up should be once for both UTMI PHYs
* - comphy_dedicated_phys_init call this function if at least there is
* one UTMI PHY exists in FDT blob. access to cp110_utmi_data[0] is
@@ -730,14 +428,16 @@
}
/* UTMI configure */
for (i = 0; i < utmi_phy_count; i++) {
- comphy_utmi_phy_config(i, cp110_utmi_data[i].utmi_base_addr,
+ comphy_utmi_phy_config(i, cp110_utmi_data[i].utmi_pll_addr,
+ cp110_utmi_data[i].utmi_base_addr,
cp110_utmi_data[i].usb_cfg_addr,
cp110_utmi_data[i].utmi_cfg_addr,
cp110_utmi_data[i].utmi_phy_port);
}
/* UTMI Power up */
for (i = 0; i < utmi_phy_count; i++) {
- if (!comphy_utmi_power_up(i, cp110_utmi_data[i].utmi_base_addr,
+ if (!comphy_utmi_power_up(i, cp110_utmi_data[i].utmi_pll_addr,
+ cp110_utmi_data[i].utmi_base_addr,
cp110_utmi_data[i].usb_cfg_addr,
cp110_utmi_data[i].utmi_cfg_addr,
cp110_utmi_data[i].utmi_phy_port)) {
@@ -770,45 +470,61 @@
void comphy_dedicated_phys_init(void)
{
struct utmi_phy_data cp110_utmi_data[MAX_UTMI_PHY_COUNT];
- int node;
- int i;
+ int node = -1;
+ int node_idx;
+ int parent = -1;
debug_enter();
debug("Initialize USB UTMI PHYs\n");
- /* Find the UTMI phy node in device tree and go over them */
- node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
- "marvell,mvebu-utmi-2.6.0");
+ for (node_idx = 0; node_idx < MAX_UTMI_PHY_COUNT;) {
+ /* Find the UTMI phy node in device tree */
+ node = fdt_node_offset_by_compatible(gd->fdt_blob, node,
+ "marvell,mvebu-utmi-2.6.0");
+ if (node <= 0)
+ break;
+
+ /* check if node is enabled */
+ if (!fdtdec_get_is_enabled(gd->fdt_blob, node))
+ continue;
+
+ parent = fdt_parent_offset(gd->fdt_blob, node);
+ if (parent <= 0)
+ break;
+
+ /* get base address of UTMI PLL */
+ cp110_utmi_data[node_idx].utmi_pll_addr =
+ (void __iomem *)fdtdec_get_addr_size_auto_noparent(
+ gd->fdt_blob, parent, "reg", 0, NULL, true);
+ if (!cp110_utmi_data[node_idx].utmi_pll_addr) {
+ pr_err("UTMI PHY PLL address is invalid\n");
+ continue;
+ }
- i = 0;
- while (node > 0) {
/* get base address of UTMI phy */
- cp110_utmi_data[i].utmi_base_addr =
+ cp110_utmi_data[node_idx].utmi_base_addr =
(void __iomem *)fdtdec_get_addr_size_auto_noparent(
gd->fdt_blob, node, "reg", 0, NULL, true);
- if (cp110_utmi_data[i].utmi_base_addr == NULL) {
+ if (!cp110_utmi_data[node_idx].utmi_base_addr) {
pr_err("UTMI PHY base address is invalid\n");
- i++;
continue;
}
/* get usb config address */
- cp110_utmi_data[i].usb_cfg_addr =
+ cp110_utmi_data[node_idx].usb_cfg_addr =
(void __iomem *)fdtdec_get_addr_size_auto_noparent(
gd->fdt_blob, node, "reg", 1, NULL, true);
- if (cp110_utmi_data[i].usb_cfg_addr == NULL) {
+ if (!cp110_utmi_data[node_idx].usb_cfg_addr) {
pr_err("UTMI PHY base address is invalid\n");
- i++;
continue;
}
/* get UTMI config address */
- cp110_utmi_data[i].utmi_cfg_addr =
+ cp110_utmi_data[node_idx].utmi_cfg_addr =
(void __iomem *)fdtdec_get_addr_size_auto_noparent(
gd->fdt_blob, node, "reg", 2, NULL, true);
- if (cp110_utmi_data[i].utmi_cfg_addr == NULL) {
+ if (!cp110_utmi_data[node_idx].utmi_cfg_addr) {
pr_err("UTMI PHY base address is invalid\n");
- i++;
continue;
}
@@ -816,70 +532,30 @@
* get the port number (to check if the utmi connected to
* host/device)
*/
- cp110_utmi_data[i].utmi_phy_port = fdtdec_get_int(
+ cp110_utmi_data[node_idx].utmi_phy_port = fdtdec_get_int(
gd->fdt_blob, node, "utmi-port", UTMI_PHY_INVALID);
- if (cp110_utmi_data[i].utmi_phy_port == UTMI_PHY_INVALID) {
+ if (cp110_utmi_data[node_idx].utmi_phy_port ==
+ UTMI_PHY_INVALID) {
pr_err("UTMI PHY port type is invalid\n");
- i++;
continue;
}
- node = fdt_node_offset_by_compatible(
- gd->fdt_blob, node, "marvell,mvebu-utmi-2.6.0");
- i++;
+ /* count valid UTMI unit */
+ node_idx++;
}
- if (i > 0)
- comphy_utmi_phy_init(i, cp110_utmi_data);
+ if (node_idx > 0)
+ comphy_utmi_phy_init(node_idx, cp110_utmi_data);
debug_exit();
}
-static void comphy_mux_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
- struct comphy_map *serdes_map)
-{
- void __iomem *comphy_base_addr;
- struct comphy_map comphy_map_pipe_data[MAX_LANE_OPTIONS];
- struct comphy_map comphy_map_phy_data[MAX_LANE_OPTIONS];
- u32 lane, comphy_max_count;
-
- comphy_max_count = ptr_chip_cfg->comphy_lanes_count;
- comphy_base_addr = ptr_chip_cfg->comphy_base_addr;
-
- /*
- * Copy the SerDes map configuration for PIPE map and PHY map
- * the comphy_mux_init modify the type of the lane if the type
- * is not valid because we have 2 selectores run the
- * comphy_mux_init twice and after that update the original
- * serdes_map
- */
- for (lane = 0; lane < comphy_max_count; lane++) {
- comphy_map_pipe_data[lane].type = serdes_map[lane].type;
- comphy_map_pipe_data[lane].speed = serdes_map[lane].speed;
- comphy_map_phy_data[lane].type = serdes_map[lane].type;
- comphy_map_phy_data[lane].speed = serdes_map[lane].speed;
- }
- ptr_chip_cfg->mux_data = cp110_comphy_phy_mux_data;
- comphy_mux_init(ptr_chip_cfg, comphy_map_phy_data,
- comphy_base_addr + COMMON_SELECTOR_PHY_OFFSET);
-
- ptr_chip_cfg->mux_data = cp110_comphy_pipe_mux_data;
- comphy_mux_init(ptr_chip_cfg, comphy_map_pipe_data,
- comphy_base_addr + COMMON_SELECTOR_PIPE_OFFSET);
- /* Fix the type after check the PHY and PIPE configuration */
- for (lane = 0; lane < comphy_max_count; lane++) {
- if ((comphy_map_pipe_data[lane].type == PHY_TYPE_UNCONNECTED) &&
- (comphy_map_phy_data[lane].type == PHY_TYPE_UNCONNECTED))
- serdes_map[lane].type = PHY_TYPE_UNCONNECTED;
- }
-}
-
int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
struct comphy_map *serdes_map)
{
struct comphy_map *ptr_comphy_map;
void __iomem *comphy_base_addr, *hpipe_base_addr;
- u32 comphy_max_count, lane, ret = 0;
+ u32 comphy_max_count, lane, id, ret = 0;
u32 pcie_width = 0;
u32 mode;
@@ -889,13 +565,10 @@
comphy_base_addr = ptr_chip_cfg->comphy_base_addr;
hpipe_base_addr = ptr_chip_cfg->hpipe3_base_addr;
- /* Config Comphy mux configuration */
- comphy_mux_cp110_init(ptr_chip_cfg, serdes_map);
-
/* Check if the first 4 lanes configured as By-4 */
for (lane = 0, ptr_comphy_map = serdes_map; lane < 4;
lane++, ptr_comphy_map++) {
- if (ptr_comphy_map->type != PHY_TYPE_PEX0)
+ if (ptr_comphy_map->type != COMPHY_TYPE_PEX0)
break;
pcie_width++;
}
@@ -912,14 +585,18 @@
pcie_width = 1;
}
switch (ptr_comphy_map->type) {
- case PHY_TYPE_UNCONNECTED:
- case PHY_TYPE_IGNORE:
+ case COMPHY_TYPE_UNCONNECTED:
+ mode = COMPHY_TYPE_UNCONNECTED | COMPHY_CALLER_UBOOT;
+ ret = comphy_smc(MV_SIP_COMPHY_POWER_OFF,
+ ptr_chip_cfg->comphy_base_addr,
+ lane, mode);
+ case COMPHY_TYPE_IGNORE:
continue;
break;
- case PHY_TYPE_PEX0:
- case PHY_TYPE_PEX1:
- case PHY_TYPE_PEX2:
- case PHY_TYPE_PEX3:
+ case COMPHY_TYPE_PEX0:
+ case COMPHY_TYPE_PEX1:
+ case COMPHY_TYPE_PEX2:
+ case COMPHY_TYPE_PEX3:
mode = COMPHY_FW_PCIE_FORMAT(pcie_width,
ptr_comphy_map->clk_src,
COMPHY_PCIE_MODE,
@@ -928,71 +605,61 @@
ptr_chip_cfg->comphy_base_addr, lane,
mode);
break;
- case PHY_TYPE_SATA0:
- case PHY_TYPE_SATA1:
- case PHY_TYPE_SATA2:
- case PHY_TYPE_SATA3:
+ case COMPHY_TYPE_SATA0:
+ case COMPHY_TYPE_SATA1:
mode = COMPHY_FW_MODE_FORMAT(COMPHY_SATA_MODE);
ret = comphy_sata_power_up(lane, hpipe_base_addr,
comphy_base_addr,
ptr_chip_cfg->cp_index,
mode);
break;
- case PHY_TYPE_USB3_HOST0:
- case PHY_TYPE_USB3_HOST1:
- case PHY_TYPE_USB3_DEVICE:
- ret = comphy_usb3_power_up(lane, hpipe_base_addr,
- comphy_base_addr);
+ case COMPHY_TYPE_USB3_HOST0:
+ case COMPHY_TYPE_USB3_HOST1:
+ mode = COMPHY_FW_MODE_FORMAT(COMPHY_USB3H_MODE);
+ ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
+ ptr_chip_cfg->comphy_base_addr, lane,
+ mode);
break;
- case PHY_TYPE_SGMII0:
- case PHY_TYPE_SGMII1:
- if (ptr_comphy_map->speed == PHY_SPEED_INVALID) {
- debug("Warning: ");
- debug("SGMII PHY speed in lane %d is invalid,",
- lane);
- debug(" set PHY speed to 1.25G\n");
- ptr_comphy_map->speed = PHY_SPEED_1_25G;
- }
-
- /*
- * UINIT_ID not relevant for SGMII0 and SGMII1 - will be
- * ignored by firmware
- */
- mode = COMPHY_FW_FORMAT(COMPHY_SGMII_MODE,
- COMPHY_UNIT_ID0,
- ptr_comphy_map->speed);
+ case COMPHY_TYPE_USB3_DEVICE:
+ mode = COMPHY_FW_MODE_FORMAT(COMPHY_USB3D_MODE);
ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
ptr_chip_cfg->comphy_base_addr, lane,
mode);
break;
- case PHY_TYPE_SGMII2:
- case PHY_TYPE_SGMII3:
- if (ptr_comphy_map->speed == PHY_SPEED_INVALID) {
+ case COMPHY_TYPE_SGMII0:
+ case COMPHY_TYPE_SGMII1:
+ case COMPHY_TYPE_SGMII2:
+ /* Calculate SGMII ID */
+ id = ptr_comphy_map->type - COMPHY_TYPE_SGMII0;
+
+ if (ptr_comphy_map->speed == COMPHY_SPEED_INVALID) {
debug("Warning: SGMII PHY speed in lane %d is invalid, set PHY speed to 1.25G\n",
lane);
- ptr_comphy_map->speed = PHY_SPEED_1_25G;
+ ptr_comphy_map->speed = COMPHY_SPEED_1_25G;
}
- mode = COMPHY_FW_FORMAT(COMPHY_SGMII_MODE,
- COMPHY_UNIT_ID2,
+ mode = COMPHY_FW_FORMAT(COMPHY_SGMII_MODE, id,
ptr_comphy_map->speed);
ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
ptr_chip_cfg->comphy_base_addr, lane,
mode);
break;
- case PHY_TYPE_SFI:
- mode = COMPHY_FW_FORMAT(COMPHY_SFI_MODE,
- COMPHY_UNIT_ID0,
+ case COMPHY_TYPE_SFI0:
+ case COMPHY_TYPE_SFI1:
+ /* Calculate SFI id */
+ id = ptr_comphy_map->type - COMPHY_TYPE_SFI0;
+ mode = COMPHY_FW_FORMAT(COMPHY_SFI_MODE, id,
ptr_comphy_map->speed);
ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
+ ptr_chip_cfg->comphy_base_addr, lane, mode);
+ break;
+ case COMPHY_TYPE_RXAUI0:
+ case COMPHY_TYPE_RXAUI1:
+ mode = COMPHY_FW_MODE_FORMAT(COMPHY_RXAUI_MODE);
+ ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
ptr_chip_cfg->comphy_base_addr, lane,
mode);
break;
- case PHY_TYPE_RXAUI0:
- case PHY_TYPE_RXAUI1:
- ret = comphy_rxauii_power_up(lane, hpipe_base_addr,
- comphy_base_addr);
- break;
default:
debug("Unknown SerDes type, skip initialize SerDes %d\n",
lane);
@@ -1001,9 +668,9 @@
if (ret == 0) {
/*
* If interface wans't initialized, set the lane to
- * PHY_TYPE_UNCONNECTED state.
+ * COMPHY_TYPE_UNCONNECTED state.
*/
- ptr_comphy_map->type = PHY_TYPE_UNCONNECTED;
+ ptr_comphy_map->type = COMPHY_TYPE_UNCONNECTED;
pr_err("PLL is not locked - Failed to initialize lane %d\n",
lane);
}
diff --git a/drivers/phy/marvell/comphy_hpipe.h b/drivers/phy/marvell/comphy_hpipe.h
deleted file mode 100644
index a692035..0000000
--- a/drivers/phy/marvell/comphy_hpipe.h
+++ /dev/null
@@ -1,660 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2015-2016 Marvell International Ltd.
- */
-
-#ifndef _COMPHY_HPIPE_H_
-#define _COMPHY_HPIPE_H_
-
-/* SerDes IP register */
-#define SD_EXTERNAL_CONFIG0_REG 0
-#define SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET 1
-#define SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK \
- (1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET)
-#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET 3
-#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK \
- (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET)
-#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET 7
-#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK \
- (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET)
-#define SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET 11
-#define SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK \
- (1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET)
-#define SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET 12
-#define SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK \
- (1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET)
-#define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET 14
-#define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK \
- (1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET)
-#define SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET 15
-#define SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK \
- (0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET)
-
-#define SD_EXTERNAL_CONFIG1_REG 0x4
-#define SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET 3
-#define SD_EXTERNAL_CONFIG1_RESET_IN_MASK \
- (0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET)
-#define SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET 4
-#define SD_EXTERNAL_CONFIG1_RX_INIT_MASK \
- (0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET)
-#define SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET 5
-#define SD_EXTERNAL_CONFIG1_RESET_CORE_MASK \
- (0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET)
-#define SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET 6
-#define SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK \
- (0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET)
-
-#define SD_EXTERNAL_CONFIG2_REG 0x8
-#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET 4
-#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK \
- (0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET)
-#define SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET 7
-#define SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK \
- (0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET)
-
-#define SD_EXTERNAL_STATUS0_REG 0x18
-#define SD_EXTERNAL_STATUS0_PLL_TX_OFFSET 2
-#define SD_EXTERNAL_STATUS0_PLL_TX_MASK \
- (0x1 << SD_EXTERNAL_STATUS0_PLL_TX_OFFSET)
-#define SD_EXTERNAL_STATUS0_PLL_RX_OFFSET 3
-#define SD_EXTERNAL_STATUS0_PLL_RX_MASK \
- (0x1 << SD_EXTERNAL_STATUS0_PLL_RX_OFFSET)
-#define SD_EXTERNAL_STATUS0_RX_INIT_OFFSET 4
-#define SD_EXTERNAL_STATUS0_RX_INIT_MASK \
- (0x1 << SD_EXTERNAL_STATUS0_RX_INIT_OFFSET)
-#define SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET 6
-#define SD_EXTERNAL_STATUS0_RF_RESET_IN_MASK \
- (0x1 << SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET)
-
-/* HPIPE register */
-#define HPIPE_PWR_PLL_REG 0x4
-#define HPIPE_PWR_PLL_REF_FREQ_OFFSET 0
-#define HPIPE_PWR_PLL_REF_FREQ_MASK \
- (0x1f << HPIPE_PWR_PLL_REF_FREQ_OFFSET)
-#define HPIPE_PWR_PLL_PHY_MODE_OFFSET 5
-#define HPIPE_PWR_PLL_PHY_MODE_MASK \
- (0x7 << HPIPE_PWR_PLL_PHY_MODE_OFFSET)
-
-#define HPIPE_KVCO_CALIB_CTRL_REG 0x8
-#define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET 12
-#define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_MASK \
- (0x1 << HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET)
-
-#define HPIPE_CAL_REG1_REG 0xc
-#define HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET 10
-#define HPIPE_CAL_REG_1_EXT_TXIMP_MASK \
- (0x1f << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET)
-#define HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET 15
-#define HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK \
- (0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET)
-
-#define HPIPE_SQUELCH_FFE_SETTING_REG 0x018
-
-#define HPIPE_DFE_REG0 0x01C
-#define HPIPE_DFE_RES_FORCE_OFFSET 15
-#define HPIPE_DFE_RES_FORCE_MASK \
- (0x1 << HPIPE_DFE_RES_FORCE_OFFSET)
-
-#define HPIPE_DFE_F3_F5_REG 0x028
-#define HPIPE_DFE_F3_F5_DFE_EN_OFFSET 14
-#define HPIPE_DFE_F3_F5_DFE_EN_MASK \
- (0x1 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET)
-#define HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET 15
-#define HPIPE_DFE_F3_F5_DFE_CTRL_MASK \
- (0x1 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET)
-
-#define HPIPE_G1_SET_0_REG 0x034
-#define HPIPE_G1_SET_0_G1_TX_AMP_OFFSET 1
-#define HPIPE_G1_SET_0_G1_TX_AMP_MASK \
- (0x1f << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET)
-#define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET 6
-#define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK \
- (0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET)
-#define HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET 7
-#define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK \
- (0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET)
-#define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET 11
-#define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK \
- (0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET)
-
-#define HPIPE_G1_SET_1_REG 0x038
-#define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET 0
-#define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK \
- (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET)
-#define HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET 3
-#define HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK \
- (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET)
-#define HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET 6
-#define HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK \
- (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET)
-#define HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET 8
-#define HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK \
- (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET)
-#define HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET 10
-#define HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK \
- (0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET)
-
-#define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET 11
-#define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK \
- (0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET)
-
-#define HPIPE_G2_SET_0_REG 0x3c
-#define HPIPE_G2_SET_0_G2_TX_AMP_OFFSET 1
-#define HPIPE_G2_SET_0_G2_TX_AMP_MASK \
- (0x1f << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET)
-#define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET 6
-#define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK \
- (0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET)
-#define HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET 7
-#define HPIPE_G2_SET_0_G2_TX_EMPH1_MASK \
- (0xf << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET)
-#define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET 11
-#define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK \
- (0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET)
-
-#define HPIPE_G2_SET_1_REG 0x040
-#define HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET 0
-#define HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK \
- (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET)
-#define HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET 3
-#define HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK \
- (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET)
-#define HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET 6
-#define HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK \
- (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET)
-#define HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET 8
-#define HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK \
- (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET)
-#define HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET 10
-#define HPIPE_G2_SET_1_G2_RX_DFE_EN_MASK \
- (0x1 << HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET)
-#define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET 11
-#define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK \
- (0x3 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET)
-
-#define HPIPE_G3_SET_0_REG 0x44
-#define HPIPE_G3_SET_0_G3_TX_AMP_OFFSET 1
-#define HPIPE_G3_SET_0_G3_TX_AMP_MASK \
- (0x1f << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET)
-#define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET 6
-#define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK \
- (0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET)
-#define HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET 7
-#define HPIPE_G3_SET_0_G3_TX_EMPH1_MASK \
- (0xf << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET)
-#define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET 11
-#define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK \
- (0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET)
-#define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET 12
-#define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK \
- (0x7 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET)
-#define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET 15
-#define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK \
- (0x1 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET)
-
-#define HPIPE_G3_SET_1_REG 0x048
-#define HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET 0
-#define HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK \
- (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET)
-#define HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET 3
-#define HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK \
- (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET)
-#define HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET 6
-#define HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK \
- (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET)
-#define HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET 8
-#define HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK \
- (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET)
-#define HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET 10
-#define HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK \
- (0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET)
-#define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET 11
-#define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK \
- (0x3 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET)
-#define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET 13
-#define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK \
- (0x1 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET)
-
-#define HPIPE_LOOPBACK_REG 0x08c
-#define HPIPE_LOOPBACK_SEL_OFFSET 1
-#define HPIPE_LOOPBACK_SEL_MASK \
- (0x7 << HPIPE_LOOPBACK_SEL_OFFSET)
-
-#define HPIPE_SYNC_PATTERN_REG 0x090
-#define HPIPE_SYNC_PATTERN_TXD_SWAP_OFFSET 10
-#define HPIPE_SYNC_PATTERN_TXD_SWAP_MASK \
- (0x1 << HPIPE_SYNC_PATTERN_TXD_SWAP_OFFSET)
-#define HPIPE_SYNC_PATTERN_RXD_SWAP_OFFSET 11
-#define HPIPE_SYNC_PATTERN_RXD_SWAP_MASK \
- (0x1 << HPIPE_SYNC_PATTERN_RXD_SWAP_OFFSET)
-
-#define HPIPE_INTERFACE_REG 0x94
-#define HPIPE_INTERFACE_GEN_MAX_OFFSET 10
-#define HPIPE_INTERFACE_GEN_MAX_MASK \
- (0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET)
-#define HPIPE_INTERFACE_DET_BYPASS_OFFSET 12
-#define HPIPE_INTERFACE_DET_BYPASS_MASK \
- (0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET)
-#define HPIPE_INTERFACE_LINK_TRAIN_OFFSET 14
-#define HPIPE_INTERFACE_LINK_TRAIN_MASK \
- (0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET)
-
-#define HPIPE_ISOLATE_MODE_REG 0x98
-#define HPIPE_ISOLATE_MODE_GEN_RX_OFFSET 0
-#define HPIPE_ISOLATE_MODE_GEN_RX_MASK \
- (0xf << HPIPE_ISOLATE_MODE_GEN_RX_OFFSET)
-#define HPIPE_ISOLATE_MODE_GEN_TX_OFFSET 4
-#define HPIPE_ISOLATE_MODE_GEN_TX_MASK \
- (0xf << HPIPE_ISOLATE_MODE_GEN_TX_OFFSET)
-
-#define HPIPE_G1_SET_2_REG 0xf4
-#define HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET 0
-#define HPIPE_G1_SET_2_G1_TX_EMPH0_MASK \
- (0xf << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET)
-#define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET 4
-#define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK \
- (0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_MASK)
-
-#define HPIPE_VTHIMPCAL_CTRL_REG 0x104
-
-#define HPIPE_VDD_CAL_CTRL_REG 0x114
-#define HPIPE_EXT_SELLV_RXSAMPL_OFFSET 5
-#define HPIPE_EXT_SELLV_RXSAMPL_MASK \
- (0x1f << HPIPE_EXT_SELLV_RXSAMPL_OFFSET)
-
-#define HPIPE_VDD_CAL_0_REG 0x108
-#define HPIPE_CAL_VDD_CONT_MODE_OFFSET 15
-#define HPIPE_CAL_VDD_CONT_MODE_MASK \
- (0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET)
-
-#define HPIPE_PCIE_REG0 0x120
-#define HPIPE_PCIE_IDLE_SYNC_OFFSET 12
-#define HPIPE_PCIE_IDLE_SYNC_MASK \
- (0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET)
-#define HPIPE_PCIE_SEL_BITS_OFFSET 13
-#define HPIPE_PCIE_SEL_BITS_MASK \
- (0x3 << HPIPE_PCIE_SEL_BITS_OFFSET)
-
-#define HPIPE_LANE_ALIGN_REG 0x124
-#define HPIPE_LANE_ALIGN_OFF_OFFSET 12
-#define HPIPE_LANE_ALIGN_OFF_MASK \
- (0x1 << HPIPE_LANE_ALIGN_OFF_OFFSET)
-
-#define HPIPE_MISC_REG 0x13C
-#define HPIPE_MISC_CLK100M_125M_OFFSET 4
-#define HPIPE_MISC_CLK100M_125M_MASK \
- (0x1 << HPIPE_MISC_CLK100M_125M_OFFSET)
-#define HPIPE_MISC_ICP_FORCE_OFFSET 5
-#define HPIPE_MISC_ICP_FORCE_MASK \
- (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET)
-#define HPIPE_MISC_TXDCLK_2X_OFFSET 6
-#define HPIPE_MISC_TXDCLK_2X_MASK \
- (0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET)
-#define HPIPE_MISC_CLK500_EN_OFFSET 7
-#define HPIPE_MISC_CLK500_EN_MASK \
- (0x1 << HPIPE_MISC_CLK500_EN_OFFSET)
-#define HPIPE_MISC_REFCLK_SEL_OFFSET 10
-#define HPIPE_MISC_REFCLK_SEL_MASK \
- (0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET)
-
-#define HPIPE_RX_CONTROL_1_REG 0x140
-#define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET 11
-#define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK \
- (0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET)
-#define HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET 12
-#define HPIPE_RX_CONTROL_1_CLK8T_EN_MASK \
- (0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET)
-
-#define HPIPE_PWR_CTR_REG 0x148
-#define HPIPE_PWR_CTR_RST_DFE_OFFSET 0
-#define HPIPE_PWR_CTR_RST_DFE_MASK \
- (0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET)
-#define HPIPE_PWR_CTR_SFT_RST_OFFSET 10
-#define HPIPE_PWR_CTR_SFT_RST_MASK \
- (0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET)
-
-#define HPIPE_SPD_DIV_FORCE_REG 0x154
-#define HPIPE_TXDIGCK_DIV_FORCE_OFFSET 7
-#define HPIPE_TXDIGCK_DIV_FORCE_MASK \
- (0x1 << HPIPE_TXDIGCK_DIV_FORCE_OFFSET)
-#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET 8
-#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK \
- (0x3 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET)
-#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET 10
-#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK \
- (0x1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET)
-#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET 13
-#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK \
- (0x3 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET)
-#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET 15
-#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK \
- (0x1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET)
-
-#define HPIPE_PLLINTP_REG1 0x150
-
-#define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C
-#define HPIPE_RX_SAMPLER_OS_GAIN_OFFSET 6
-#define HPIPE_RX_SAMPLER_OS_GAIN_MASK \
- (0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET)
-#define HPIPE_SMAPLER_OFFSET 12
-#define HPIPE_SMAPLER_MASK \
- (0x1 << HPIPE_SMAPLER_OFFSET)
-
-#define HPIPE_TX_REG1_REG 0x174
-#define HPIPE_TX_REG1_TX_EMPH_RES_OFFSET 5
-#define HPIPE_TX_REG1_TX_EMPH_RES_MASK \
- (0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET)
-#define HPIPE_TX_REG1_SLC_EN_OFFSET 10
-#define HPIPE_TX_REG1_SLC_EN_MASK \
- (0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET)
-
-#define HPIPE_PWR_CTR_DTL_REG 0x184
-#define HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET 0
-#define HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK \
- (0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET)
-#define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET 1
-#define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK \
- (0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET)
-#define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 2
-#define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK \
- (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET)
-#define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET 4
-#define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK \
- (0x7 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET)
-#define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET 10
-#define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK \
- (0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET)
-#define HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET 12
-#define HPIPE_PWR_CTR_DTL_CLK_MODE_MASK \
- (0x3 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET)
-#define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET 14
-#define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK \
- (1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET)
-
-#define HPIPE_PHASE_CONTROL_REG 0x188
-#define HPIPE_OS_PH_OFFSET_OFFSET 0
-#define HPIPE_OS_PH_OFFSET_MASK \
- (0x7f << HPIPE_OS_PH_OFFSET_OFFSET)
-#define HPIPE_OS_PH_OFFSET_FORCE_OFFSET 7
-#define HPIPE_OS_PH_OFFSET_FORCE_MASK \
- (0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET)
-#define HPIPE_OS_PH_VALID_OFFSET 8
-#define HPIPE_OS_PH_VALID_MASK \
- (0x1 << HPIPE_OS_PH_VALID_OFFSET)
-
-#define HPIPE_FRAME_DETECT_CTRL_0_REG 0x214
-#define HPIPE_TRAIN_PAT_NUM_OFFSET 0x7
-#define HPIPE_TRAIN_PAT_NUM_MASK \
- (0x1FF << HPIPE_TRAIN_PAT_NUM_OFFSET)
-
-#define HPIPE_FRAME_DETECT_CTRL_3_REG 0x220
-#define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET 12
-#define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK \
- (0x1 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET)
-
-#define HPIPE_DME_REG 0x228
-#define HPIPE_DME_ETHERNET_MODE_OFFSET 7
-#define HPIPE_DME_ETHERNET_MODE_MASK \
- (0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET)
-
-#define HPIPE_TX_TRAIN_CTRL_0_REG 0x268
-#define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET 15
-#define HPIPE_TX_TRAIN_P2P_HOLD_MASK \
- (0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET)
-
-#define HPIPE_TX_TRAIN_CTRL_REG 0x26C
-#define HPIPE_TX_TRAIN_CTRL_G1_OFFSET 0
-#define HPIPE_TX_TRAIN_CTRL_G1_MASK \
- (0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET)
-#define HPIPE_TX_TRAIN_CTRL_GN1_OFFSET 1
-#define HPIPE_TX_TRAIN_CTRL_GN1_MASK \
- (0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET)
-#define HPIPE_TX_TRAIN_CTRL_G0_OFFSET 2
-#define HPIPE_TX_TRAIN_CTRL_G0_MASK \
- (0x1 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET)
-
-#define HPIPE_TX_TRAIN_CTRL_4_REG 0x278
-#define HPIPE_TRX_TRAIN_TIMER_OFFSET 0
-#define HPIPE_TRX_TRAIN_TIMER_MASK \
- (0x3FF << HPIPE_TRX_TRAIN_TIMER_OFFSET)
-
-#define HPIPE_PCIE_REG1 0x288
-#define HPIPE_PCIE_REG3 0x290
-
-#define HPIPE_TX_TRAIN_CTRL_5_REG 0x2A4
-#define HPIPE_RX_TRAIN_TIMER_OFFSET 0
-#define HPIPE_RX_TRAIN_TIMER_MASK \
- (0x3ff << HPIPE_RX_TRAIN_TIMER_OFFSET)
-#define HPIPE_TX_TRAIN_START_SQ_EN_OFFSET 11
-#define HPIPE_TX_TRAIN_START_SQ_EN_MASK \
- (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET)
-#define HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET 12
-#define HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK \
- (0x1 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET)
-#define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET 13
-#define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK \
- (0x1 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET)
-#define HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET 14
-#define HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK \
- (0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET)
-
-#define HPIPE_TX_TRAIN_REG 0x31C
-#define HPIPE_TX_TRAIN_CHK_INIT_OFFSET 4
-#define HPIPE_TX_TRAIN_CHK_INIT_MASK \
- (0x1 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET)
-#define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7
-#define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK \
- (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET)
-#define HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET 8
-#define HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK \
- (0x1 << HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET)
-#define HPIPE_TX_TRAIN_PAT_SEL_OFFSET 9
-#define HPIPE_TX_TRAIN_PAT_SEL_MASK \
- (0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET)
-
-#define HPIPE_CDR_CONTROL_REG 0x418
-#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET 12
-#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK \
- (0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET)
-#define HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET 9
-#define HPIPE_CDR_MAX_DFE_ADAPT_0_MASK \
- (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET)
-#define HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET 6
-#define HPIPE_CDR_MAX_DFE_ADAPT_1_MASK \
- (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET)
-
-#define HPIPE_TX_TRAIN_CTRL_11_REG 0x438
-#define HPIPE_TX_STATUS_CHECK_MODE_OFFSET 6
-#define HPIPE_TX_TX_STATUS_CHECK_MODE_MASK \
- (0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET)
-#define HPIPE_TX_NUM_OF_PRESET_OFFSET 10
-#define HPIPE_TX_NUM_OF_PRESET_MASK \
- (0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET)
-#define HPIPE_TX_SWEEP_PRESET_EN_OFFSET 15
-#define HPIPE_TX_SWEEP_PRESET_EN_MASK \
- (0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET)
-
-#define HPIPE_G1_SETTINGS_3_REG 0x440
-#define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET 0
-#define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK \
- (0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET)
-#define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET 4
-#define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK \
- (0x7 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET)
-#define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET 7
-#define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK \
- (0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET)
-#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET 9
-#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK \
- (0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET)
-#define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET 12
-#define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK \
- (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET)
-#define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET 14
-#define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK \
- (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET)
-
-#define HPIPE_G1_SETTINGS_4_REG 0x444
-#define HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET 8
-#define HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK \
- (0x3 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET)
-
-#define HPIPE_G2_SETTINGS_3_REG 0x448
-
-#define HPIPE_G2_SETTINGS_4_REG 0x44c
-#define HPIPE_G2_DFE_RES_OFFSET 8
-#define HPIPE_G2_DFE_RES_MASK \
- (0x3 << HPIPE_G2_DFE_RES_OFFSET)
-
-#define HPIPE_G3_SETTING_3_REG 0x450
-#define HPIPE_G3_FFE_CAP_SEL_OFFSET 0
-#define HPIPE_G3_FFE_CAP_SEL_MASK \
- (0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET)
-#define HPIPE_G3_FFE_RES_SEL_OFFSET 4
-#define HPIPE_G3_FFE_RES_SEL_MASK \
- (0x7 << HPIPE_G3_FFE_RES_SEL_OFFSET)
-#define HPIPE_G3_FFE_SETTING_FORCE_OFFSET 7
-#define HPIPE_G3_FFE_SETTING_FORCE_MASK \
- (0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET)
-#define HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET 12
-#define HPIPE_G3_FFE_DEG_RES_LEVEL_MASK \
- (0x3 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET)
-#define HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET 14
-#define HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK \
- (0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET)
-
-#define HPIPE_G3_SETTING_4_REG 0x454
-#define HPIPE_G3_DFE_RES_OFFSET 8
-#define HPIPE_G3_DFE_RES_MASK \
- (0x3 << HPIPE_G3_DFE_RES_OFFSET)
-
-#define HPIPE_TX_PRESET_INDEX_REG 0x468
-#define HPIPE_TX_PRESET_INDEX_OFFSET 0
-#define HPIPE_TX_PRESET_INDEX_MASK \
- (0xf << HPIPE_TX_PRESET_INDEX_OFFSET)
-
-#define HPIPE_DFE_CONTROL_REG 0x470
-#define HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET 14
-#define HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK \
- (0x3 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET)
-
-#define HPIPE_DFE_CTRL_28_REG 0x49C
-#define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7
-#define HPIPE_DFE_CTRL_28_PIPE4_MASK \
- (0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET)
-
-#define HPIPE_G1_SETTING_5_REG 0x538
-#define HPIPE_G1_SETTING_5_G1_ICP_OFFSET 0
-#define HPIPE_G1_SETTING_5_G1_ICP_MASK \
- (0xf << HPIPE_G1_SETTING_5_G1_ICP_OFFSET)
-
-#define HPIPE_G3_SETTING_5_REG 0x548
-#define HPIPE_G3_SETTING_5_G3_ICP_OFFSET 0
-#define HPIPE_G3_SETTING_5_G3_ICP_MASK \
- (0xf << HPIPE_G3_SETTING_5_G3_ICP_OFFSET)
-
-#define HPIPE_LANE_CONFIG0_REG 0x600
-#define HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET 0
-#define HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK \
- (0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET)
-
-#define HPIPE_LANE_CONFIG1_REG 0x604
-#define HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET 9
-#define HPIPE_LANE_CONFIG1_MAX_PLL_MASK \
- (0x1 << HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET)
-#define HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET 10
-#define HPIPE_LANE_CONFIG1_GEN2_PLL_MASK \
- (0x1 << HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET)
-
-#define HPIPE_LANE_STATUS1_REG 0x60C
-#define HPIPE_LANE_STATUS1_PCLK_EN_OFFSET 0
-#define HPIPE_LANE_STATUS1_PCLK_EN_MASK \
- (0x1 << HPIPE_LANE_STATUS1_PCLK_EN_OFFSET)
-
-#define HPIPE_LANE_CFG4_REG 0x620
-#define HPIPE_LANE_CFG4_DFE_CTRL_OFFSET 0
-#define HPIPE_LANE_CFG4_DFE_CTRL_MASK \
- (0x7 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET)
-#define HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET 3
-#define HPIPE_LANE_CFG4_DFE_EN_SEL_MASK \
- (0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET)
-#define HPIPE_LANE_CFG4_DFE_OVER_OFFSET 6
-#define HPIPE_LANE_CFG4_DFE_OVER_MASK \
- (0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET)
-#define HPIPE_LANE_CFG4_SSC_CTRL_OFFSET 7
-#define HPIPE_LANE_CFG4_SSC_CTRL_MASK \
- (0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET)
-
-#define HPIPE_LANE_EQU_CONFIG_0_REG 0x69C
-#define HPIPE_CFG_PHY_RC_EP_OFFSET 12
-#define HPIPE_CFG_PHY_RC_EP_MASK \
- (0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET)
-
-#define HPIPE_LANE_EQ_CFG1_REG 0x6a0
-#define HPIPE_CFG_UPDATE_POLARITY_OFFSET 12
-#define HPIPE_CFG_UPDATE_POLARITY_MASK \
- (0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET)
-
-#define HPIPE_LANE_EQ_REMOTE_SETTING_REG 0x6f8
-#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET 0
-#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK \
- (0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET)
-#define HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET 1
-#define HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK \
- (0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET)
-#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET 2
-#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK \
- (0xf << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET)
-
-#define HPIPE_RST_CLK_CTRL_REG 0x704
-#define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0
-#define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK \
- (0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET)
-#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET 2
-#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK \
- (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET)
-#define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET 3
-#define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK \
- (0x1 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET)
-#define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET 9
-#define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK \
- (0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET)
-
-#define HPIPE_TST_MODE_CTRL_REG 0x708
-#define HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET 2
-#define HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK \
- (0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET)
-
-#define HPIPE_CLK_SRC_LO_REG 0x70c
-#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET 1
-#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK \
- (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET)
-#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET 2
-#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK \
- (0x3 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET)
-#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET 5
-#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK \
- (0x7 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET)
-
-#define HPIPE_CLK_SRC_HI_REG 0x710
-#define HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET 0
-#define HPIPE_CLK_SRC_HI_LANE_STRT_MASK \
- (0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET)
-#define HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET 1
-#define HPIPE_CLK_SRC_HI_LANE_BREAK_MASK \
- (0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET)
-#define HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET 2
-#define HPIPE_CLK_SRC_HI_LANE_MASTER_MASK \
- (0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET)
-#define HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET 7
-#define HPIPE_CLK_SRC_HI_MODE_PIPE_MASK \
- (0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET)
-
-#define HPIPE_GLOBAL_MISC_CTRL 0x718
-#define HPIPE_GLOBAL_PM_CTRL 0x740
-#define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET 0
-#define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK \
- (0xFF << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET)
-
-#endif /* _COMPHY_HPIPE_H_ */
-
diff --git a/drivers/phy/marvell/comphy_mux.c b/drivers/phy/marvell/comphy_mux.c
index 9832755..10981d2 100644
--- a/drivers/phy/marvell/comphy_mux.c
+++ b/drivers/phy/marvell/comphy_mux.c
@@ -8,14 +8,13 @@
#include <asm/io.h>
#include "comphy_core.h"
-#include "comphy_hpipe.h"
/*
* comphy_mux_check_config()
* description: this function passes over the COMPHY lanes and check if the type
* is valid for specific lane. If the type is not valid,
* the function update the struct and set the type of the lane as
- * PHY_TYPE_UNCONNECTED
+ * COMPHY_TYPE_UNCONNECTED
*/
static void comphy_mux_check_config(struct comphy_mux_data *mux_data,
struct comphy_map *comphy_map_data, int comphy_max_lanes)
@@ -28,7 +27,7 @@
for (lane = 0; lane < comphy_max_lanes;
lane++, comphy_map_data++, mux_data++) {
/* Don't check ignored COMPHYs */
- if (comphy_map_data->type == PHY_TYPE_IGNORE)
+ if (comphy_map_data->type == COMPHY_TYPE_IGNORE)
continue;
mux_opt = mux_data->mux_values;
@@ -43,8 +42,8 @@
debug("lane number %d, had invalid type %d\n",
lane, comphy_map_data->type);
debug("set lane %d as type %d\n", lane,
- PHY_TYPE_UNCONNECTED);
- comphy_map_data->type = PHY_TYPE_UNCONNECTED;
+ COMPHY_TYPE_UNCONNECTED);
+ comphy_map_data->type = COMPHY_TYPE_UNCONNECTED;
} else {
debug("lane number %d, has type %d\n",
lane, comphy_map_data->type);
@@ -88,7 +87,7 @@
for (lane = 0; lane < comphy_max_lanes;
lane++, comphy_map_data++, mux_data++) {
- if (comphy_map_data->type == PHY_TYPE_IGNORE)
+ if (comphy_map_data->type == COMPHY_TYPE_IGNORE)
continue;
/*
diff --git a/drivers/phy/marvell/utmi_phy.h b/drivers/phy/marvell/utmi_phy.h
index 682a3ac..8a570ba 100644
--- a/drivers/phy/marvell/utmi_phy.h
+++ b/drivers/phy/marvell/utmi_phy.h
@@ -38,6 +38,12 @@
#define UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET 8
#define UTMI_CALIB_CTRL_IMPCAL_VTH_MASK \
(0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET)
+#define UTMI_CALIB_CTRL_IMPCAL_START_OFFSET 13
+#define UTMI_CALIB_CTRL_IMPCAL_START_MASK \
+ (0x1 << UTMI_CALIB_CTRL_IMPCAL_START_OFFSET)
+#define UTMI_CALIB_CTRL_PLLCAL_START_OFFSET 22
+#define UTMI_CALIB_CTRL_PLLCAL_START_MASK \
+ (0x1 << UTMI_CALIB_CTRL_PLLCAL_START_OFFSET)
#define UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET 23
#define UTMI_CALIB_CTRL_IMPCAL_DONE_MASK \
(0x1 << UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET)
@@ -45,15 +51,21 @@
#define UTMI_CALIB_CTRL_PLLCAL_DONE_MASK \
(0x1 << UTMI_CALIB_CTRL_PLLCAL_DONE_OFFSET)
-#define UTMI_TX_CH_CTRL_REG 0xC
+#define UTMI_TX_CH_CTRL_REG 0x0
#define UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET 12
#define UTMI_TX_CH_CTRL_DRV_EN_LS_MASK \
(0xf << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET)
#define UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET 16
#define UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK \
(0xf << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET)
+#define UTMI_TX_CH_CTRL_AMP_OFFSET 20
+#define UTMI_TX_CH_CTRL_AMP_MASK \
+ (0x7 << UTMI_TX_CH_CTRL_AMP_OFFSET)
-#define UTMI_RX_CH_CTRL0_REG 0x14
+#define UTMI_RX_CH_CTRL0_REG 0x8
+#define UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET 8
+#define UTMI_RX_CH_CTRL0_DISCON_THRESH_MASK \
+ (0x3 << UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET)
#define UTMI_RX_CH_CTRL0_SQ_DET_OFFSET 15
#define UTMI_RX_CH_CTRL0_SQ_DET_MASK \
(0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET)
@@ -61,15 +73,15 @@
#define UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK \
(0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET)
-#define UTMI_RX_CH_CTRL1_REG 0x18
+#define UTMI_RX_CH_CTRL1_REG 0xc
#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET 0
#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK \
- (0x3 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET)
+ (0x7 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET)
#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET 3
#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK \
(0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET)
-#define UTMI_CTRL_STATUS0_REG 0x24
+#define UTMI_CTRL_STATUS0_REG 0x18
#define UTMI_CTRL_STATUS0_SUSPENDM_OFFSET 22
#define UTMI_CTRL_STATUS0_SUSPENDM_MASK \
(0x1 << UTMI_CTRL_STATUS0_SUSPENDM_OFFSET)
@@ -77,7 +89,7 @@
#define UTMI_CTRL_STATUS0_TEST_SEL_MASK \
(0x1 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET)
-#define UTMI_CHGDTC_CTRL_REG 0x38
+#define UTMI_CHGDTC_CTRL_REG 0x2c
#define UTMI_CHGDTC_CTRL_VDAT_OFFSET 8
#define UTMI_CHGDTC_CTRL_VDAT_MASK \
(0x3 << UTMI_CHGDTC_CTRL_VDAT_OFFSET)
diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c
index 4d2e730..fac9606 100644
--- a/drivers/power/regulator/regulator-uclass.c
+++ b/drivers/power/regulator/regulator-uclass.c
@@ -311,6 +311,17 @@
return ret;
}
+int regulator_unset(struct udevice *dev)
+{
+ struct dm_regulator_uclass_plat *uc_pdata;
+
+ uc_pdata = dev_get_uclass_plat(dev);
+ if (uc_pdata && uc_pdata->force_off)
+ return regulator_set_enable(dev, false);
+
+ return -EMEDIUMTYPE;
+}
+
static void regulator_show(struct udevice *dev, int ret)
{
struct dm_regulator_uclass_plat *uc_pdata;
@@ -443,6 +454,7 @@
uc_pdata->boot_on = dev_read_bool(dev, "regulator-boot-on");
uc_pdata->ramp_delay = dev_read_u32_default(dev, "regulator-ramp-delay",
0);
+ uc_pdata->force_off = dev_read_bool(dev, "regulator-force-boot-off");
node = dev_read_subnode(dev, "regulator-state-mem");
if (ofnode_valid(node)) {
@@ -495,6 +507,32 @@
return ret;
}
+int regulators_enable_boot_off(bool verbose)
+{
+ struct udevice *dev;
+ struct uclass *uc;
+ int ret;
+
+ ret = uclass_get(UCLASS_REGULATOR, &uc);
+ if (ret)
+ return ret;
+ for (uclass_first_device(UCLASS_REGULATOR, &dev);
+ dev;
+ uclass_next_device(&dev)) {
+ ret = regulator_unset(dev);
+ if (ret == -EMEDIUMTYPE) {
+ ret = 0;
+ continue;
+ }
+ if (verbose)
+ regulator_show(dev, ret);
+ if (ret == -ENOSYS)
+ ret = 0;
+ }
+
+ return ret;
+}
+
UCLASS_DRIVER(regulator) = {
.id = UCLASS_REGULATOR,
.name = "regulator",
diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index 7642a31..06be9de 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -265,6 +265,8 @@
}
#endif
+#if !defined(CONFIG_PHY)
+/* Should be done in the MXS PHY driver */
static void usb_oc_config(struct usbnc_regs *usbnc, int index)
{
void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
@@ -285,6 +287,7 @@
clrbits_le32(ctrl, UCTRL_PWR_POL);
#endif
}
+#endif
#if !CONFIG_IS_ENABLED(DM_USB)
/**
@@ -432,10 +435,12 @@
struct clk clk;
struct phy phy;
enum usb_init_type init_type;
+#if !defined(CONFIG_PHY)
int portnr;
void __iomem *phy_addr;
void __iomem *misc_addr;
void __iomem *anatop_addr;
+#endif
};
static int mx6_init_after_reset(struct ehci_ctrl *dev)
@@ -448,14 +453,14 @@
usb_power_config_mx6(priv->anatop_addr, priv->portnr);
usb_power_config_mx7(priv->misc_addr);
usb_power_config_mx7ulp(priv->phy_addr);
-#endif
usb_oc_config(priv->misc_addr, priv->portnr);
-#if !defined(CONFIG_PHY) && (defined(CONFIG_MX6) || defined(CONFIG_MX7ULP))
+#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
usb_internal_phy_clock_gate(priv->phy_addr, 1);
usb_phy_enable(ehci, priv->phy_addr);
#endif
+#endif
#if CONFIG_IS_ENABLED(DM_REGULATOR)
if (priv->vbus_supply) {
@@ -558,6 +563,7 @@
static int mx6_parse_dt_addrs(struct udevice *dev)
{
+#if !defined(CONFIG_PHY)
struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
int phy_off, misc_off;
const void *blob = gd->fdt_blob;
@@ -594,7 +600,7 @@
priv->misc_addr = addr;
-#if !defined(CONFIG_PHY) && defined(CONFIG_MX6)
+#if defined(CONFIG_MX6)
int anatop_off;
/* Resolve ANATOP offset through USB PHY node */
@@ -608,6 +614,7 @@
priv->anatop_addr = addr;
#endif
+#endif
return 0;
}
@@ -661,14 +668,14 @@
usb_power_config_mx6(priv->anatop_addr, priv->portnr);
usb_power_config_mx7(priv->misc_addr);
usb_power_config_mx7ulp(priv->phy_addr);
-#endif
usb_oc_config(priv->misc_addr, priv->portnr);
-#if !defined(CONFIG_PHY) && (defined(CONFIG_MX6) || defined(CONFIG_MX7ULP))
+#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
usb_internal_phy_clock_gate(priv->phy_addr, 1);
usb_phy_enable(ehci, priv->phy_addr);
#endif
+#endif
#if CONFIG_IS_ENABLED(DM_REGULATOR)
if (priv->vbus_supply) {
diff --git a/include/dt-bindings/comphy/comphy_data.h b/include/dt-bindings/comphy/comphy_data.h
index 4f7e282..8353a78 100644
--- a/include/dt-bindings/comphy/comphy_data.h
+++ b/include/dt-bindings/comphy/comphy_data.h
@@ -6,52 +6,44 @@
#ifndef _COMPHY_DATA_H_
#define _COMPHY_DATA_H_
-#define PHY_SPEED_1_25G 0
-#define PHY_SPEED_1_5G 1
-#define PHY_SPEED_2_5G 2
-#define PHY_SPEED_3G 3
-#define PHY_SPEED_3_125G 4
-#define PHY_SPEED_5G 5
-#define PHY_SPEED_5_15625G 6
-#define PHY_SPEED_6G 7
-#define PHY_SPEED_6_25G 8
-#define PHY_SPEED_10_3125G 9
-#define PHY_SPEED_MAX 10
-#define PHY_SPEED_INVALID 0xff
+#define COMPHY_SPEED_1_25G 0
+#define COMPHY_SPEED_2_5G 1
+#define COMPHY_SPEED_3_125G 2
+#define COMPHY_SPEED_5G 3
+#define COMPHY_SPEED_5_15625G 4
+#define COMPHY_SPEED_6G 5
+#define COMPHY_SPEED_10_3125G 6
+#define COMPHY_SPEED_MAX 7
+#define COMPHY_SPEED_INVALID 0xff
-#define PHY_TYPE_UNCONNECTED 0
-#define PHY_TYPE_PEX0 1
-#define PHY_TYPE_PEX1 2
-#define PHY_TYPE_PEX2 3
-#define PHY_TYPE_PEX3 4
-#define PHY_TYPE_SATA0 5
-#define PHY_TYPE_SATA1 6
-#define PHY_TYPE_SATA2 7
-#define PHY_TYPE_SATA3 8
-#define PHY_TYPE_SGMII0 9
-#define PHY_TYPE_SGMII1 10
-#define PHY_TYPE_SGMII2 11
-#define PHY_TYPE_SGMII3 12
-#define PHY_TYPE_QSGMII 13
-#define PHY_TYPE_USB3_HOST0 14
-#define PHY_TYPE_USB3_HOST1 15
-#define PHY_TYPE_USB3_DEVICE 16
-#define PHY_TYPE_XAUI0 17
-#define PHY_TYPE_XAUI1 18
-#define PHY_TYPE_XAUI2 19
-#define PHY_TYPE_XAUI3 20
-#define PHY_TYPE_RXAUI0 21
-#define PHY_TYPE_RXAUI1 22
-#define PHY_TYPE_SFI 23
-#define PHY_TYPE_IGNORE 24
-#define PHY_TYPE_MAX 25
-#define PHY_TYPE_INVALID 0xff
+#define COMPHY_TYPE_UNCONNECTED 0
+#define COMPHY_TYPE_PEX0 1
+#define COMPHY_TYPE_PEX1 2
+#define COMPHY_TYPE_PEX2 3
+#define COMPHY_TYPE_PEX3 4
+#define COMPHY_TYPE_SATA0 5
+#define COMPHY_TYPE_SATA1 6
+#define COMPHY_TYPE_SGMII0 7
+#define COMPHY_TYPE_SGMII1 8
+#define COMPHY_TYPE_SGMII2 9
+#define COMPHY_TYPE_USB3 10
+#define COMPHY_TYPE_USB3_HOST0 11
+#define COMPHY_TYPE_USB3_HOST1 12
+#define COMPHY_TYPE_USB3_DEVICE 13
+#define COMPHY_TYPE_RXAUI0 14
+#define COMPHY_TYPE_RXAUI1 15
+#define COMPHY_TYPE_SFI0 16
+#define COMPHY_TYPE_SFI1 17
+#define COMPHY_TYPE_AP 18
+#define COMPHY_TYPE_IGNORE 19
+#define COMPHY_TYPE_MAX 20
+#define COMPHY_TYPE_INVALID 0xff
-#define PHY_POLARITY_NO_INVERT 0
-#define PHY_POLARITY_TXD_INVERT 1
-#define PHY_POLARITY_RXD_INVERT 2
-#define PHY_POLARITY_ALL_INVERT \
- (PHY_POLARITY_TXD_INVERT | PHY_POLARITY_RXD_INVERT)
+#define COMPHY_POLARITY_NO_INVERT 0
+#define COMPHY_POLARITY_TXD_INVERT 1
+#define COMPHY_POLARITY_RXD_INVERT 2
+#define COMPHY_POLARITY_ALL_INVERT \
+ (COMPHY_POLARITY_TXD_INVERT | COMPHY_POLARITY_RXD_INVERT)
#define UTMI_PHY_TO_USB3_HOST0 0
#define UTMI_PHY_TO_USB3_HOST1 1
diff --git a/include/mvebu/comphy.h b/include/mvebu/comphy.h
index cde7a02..4d1b703 100644
--- a/include/mvebu/comphy.h
+++ b/include/mvebu/comphy.h
@@ -16,7 +16,7 @@
bool end_point;
};
+int comphy_rx_training(struct udevice *dev, u32 lane);
int comphy_update_map(struct comphy_map *serdes_map, int count);
#endif /* _MVEBU_COMPHY_H_ */
-
diff --git a/include/power/regulator.h b/include/power/regulator.h
index da9a065..fad87c9 100644
--- a/include/power/regulator.h
+++ b/include/power/regulator.h
@@ -151,6 +151,7 @@
* @max_uA* - maximum amperage (micro Amps)
* @always_on* - bool type, true or false
* @boot_on* - bool type, true or false
+ * @force_off* - bool type, true or false
* TODO(sjg@chromium.org): Consider putting the above two into @flags
* @ramp_delay - Time to settle down after voltage change (unit: uV/us)
* @flags: - flags value (see REGULATOR_FLAG_...)
@@ -176,6 +177,7 @@
unsigned int ramp_delay;
bool always_on;
bool boot_on;
+ bool force_off;
const char *name;
int flags;
u8 ctrl_reg;
@@ -421,6 +423,15 @@
int regulators_enable_boot_on(bool verbose);
/**
+ * regulators_enable_boot_off() - disable regulators needed for boot
+ *
+ * This disables all regulators which are marked to be off at boot time.
+ *
+ * This effectively calls regulator_unset() for every regulator.
+ */
+int regulators_enable_boot_off(bool verbose);
+
+/**
* regulator_autoset: setup the voltage/current on a regulator
*
* The setup depends on constraints found in device's uclass's platform data
@@ -440,6 +451,18 @@
int regulator_autoset(struct udevice *dev);
/**
+ * regulator_unset: turn off a regulator
+ *
+ * The setup depends on constraints found in device's uclass's platform data
+ * (struct dm_regulator_uclass_platdata):
+ *
+ * - Disable - will set - if 'force_off' is set to true,
+ *
+ * The function returns on the first-encountered error.
+ */
+int regulator_unset(struct udevice *dev);
+
+/**
* regulator_autoset_by_name: setup the regulator given by its uclass's
* platform data name field. The setup depends on constraints found in device's
* uclass's platform data (struct dm_regulator_uclass_plat):