tree 29505cad383e11e624d7fa6c94350344d29f3307
parent 35620498131dc7d6d2185d7dfba8f3239af52505
author maxims@google.com <maxims@google.com> 1485804904 -0800
committer Tom Rini <trini@konsulko.com> 1486587390 -0500

aspeed: ast2500: Fix H-PLL and M-PLL clock rate calculation

Fix H-PLL and M-PLL rate calculation in ast2500 clock driver.
Without this fix, valid setting can lead to division by zero
when requesting the rate of H-PLL or M-PLL clocks.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>