diff --git a/Kbuild b/Kbuild
index ef97787..465b930 100644
--- a/Kbuild
+++ b/Kbuild
@@ -4,39 +4,47 @@
 # 1) Generate generic-asm-offsets.h
 # 2) Generate asm-offsets.h
 
-#####
-# 1) Generate generic-asm-offsets.h
-
-generic-offsets-file := include/generated/generic-asm-offsets.h
-
-always  := $(generic-offsets-file)
-targets := $(generic-offsets-file) lib/asm-offsets.s
+# Default sed regexp - multiline due to syntax constraints
+define sed-y
+	"s:[[:space:]]*\.ascii[[:space:]]*\"\(.*\)\":\1:; \
+	/^->/{s:->#\(.*\):/* \1 */:; \
+	s:^->\([^ ]*\) [\$$#]*\([-0-9]*\) \(.*\):#define \1 \2 /* \3 */:; \
+	s:^->\([^ ]*\) [\$$#]*\([^ ]*\) \(.*\):#define \1 \2 /* \3 */:; \
+	s:->::; p;}"
+endef
 
-quiet_cmd_generic-offsets = GEN     $@
-define cmd_generic-offsets
+# Use filechk to avoid rebuilds when a header changes, but the resulting file
+# does not
+define filechk_offsets
 	(set -e; \
-	 echo "#ifndef __GENERIC_ASM_OFFSETS_H__"; \
-	 echo "#define __GENERIC_ASM_OFFSETS_H__"; \
+	 echo "#ifndef $2"; \
+	 echo "#define $2"; \
 	 echo "/*"; \
 	 echo " * DO NOT MODIFY."; \
 	 echo " *"; \
 	 echo " * This file was generated by Kbuild"; \
-	 echo " *"; \
 	 echo " */"; \
 	 echo ""; \
-	 sed -ne $(sed-y) $<; \
+	 sed -ne $(sed-y); \
 	 echo ""; \
-	 echo "#endif" ) > $@
+	 echo "#endif" )
 endef
 
+#####
+# 1) Generate generic-asm-offsets.h
+
+generic-offsets-file := include/generated/generic-asm-offsets.h
+
+always  := $(generic-offsets-file)
+targets := $(generic-offsets-file) lib/asm-offsets.s
+
 # We use internal kbuild rules to avoid the "is up to date" message from make
 lib/asm-offsets.s: lib/asm-offsets.c FORCE
 	$(Q)mkdir -p $(dir $@)
 	$(call if_changed_dep,cc_s_c)
 
-$(obj)/$(generic-offsets-file): lib/asm-offsets.s Kbuild
-	$(Q)mkdir -p $(dir $@)
-	$(call cmd,generic-offsets)
+$(obj)/$(generic-offsets-file): lib/asm-offsets.s FORCE
+	$(call filechk,offsets,__GENERIC_ASM_OFFSETS_H__)
 
 #####
 # 2) Generate asm-offsets.h
@@ -50,39 +58,12 @@
 targets += $(offsets-file)
 targets += arch/$(ARCH)/lib/asm-offsets.s
 
-
-# Default sed regexp - multiline due to syntax constraints
-define sed-y
-	"s:[[:space:]]*\.ascii[[:space:]]*\"\(.*\)\":\1:; \
-	/^->/{s:->#\(.*\):/* \1 */:; \
-	s:^->\([^ ]*\) [\$$#]*\([-0-9]*\) \(.*\):#define \1 \2 /* \3 */:; \
-	s:^->\([^ ]*\) [\$$#]*\([^ ]*\) \(.*\):#define \1 \2 /* \3 */:; \
-	s:->::; p;}"
-endef
-
 CFLAGS_asm-offsets.o := -DDO_DEPS_ONLY
 
-quiet_cmd_offsets = GEN     $@
-define cmd_offsets
-	(set -e; \
-	 echo "#ifndef __ASM_OFFSETS_H__"; \
-	 echo "#define __ASM_OFFSETS_H__"; \
-	 echo "/*"; \
-	 echo " * DO NOT MODIFY."; \
-	 echo " *"; \
-	 echo " * This file was generated by Kbuild"; \
-	 echo " *"; \
-	 echo " */"; \
-	 echo ""; \
-	 sed -ne $(sed-y) $<; \
-	 echo ""; \
-	 echo "#endif" ) > $@
-endef
-
 # We use internal kbuild rules to avoid the "is up to date" message from make
 arch/$(ARCH)/lib/asm-offsets.s: arch/$(ARCH)/lib/asm-offsets.c FORCE
 	$(Q)mkdir -p $(dir $@)
 	$(call if_changed_dep,cc_s_c)
 
-$(obj)/$(offsets-file): arch/$(ARCH)/lib/asm-offsets.s Kbuild
-	$(call cmd,offsets)
+$(obj)/$(offsets-file): arch/$(ARCH)/lib/asm-offsets.s FORCE
+	$(call filechk,offsets,__ASM_OFFSETS_H__)
diff --git a/Kconfig b/Kconfig
index 8f96c94..41d4784 100644
--- a/Kconfig
+++ b/Kconfig
@@ -54,7 +54,7 @@
 
 config SYS_MALLOC_F
 	bool "Enable malloc() pool before relocation"
-	default 0x400
+	default y if DM
 	help
 	  Before relocation memory is very limited on many platforms. Still,
 	  we can provide a small malloc() pool if needed. Driver model in
@@ -184,7 +184,7 @@
 	  TODO: Move CONFIG_SYS_TEXT_BASE for all the architecture
 
 config SYS_CLK_FREQ
-	depends on ARC
+	depends on ARC || ARCH_SUNXI
 	int "CPU clock frequency"
 	help
 	  TODO: Move CONFIG_SYS_CLK_FREQ for all the architecture
diff --git a/Makefile b/Makefile
index 1b3ebe7..0d160c9 100644
--- a/Makefile
+++ b/Makefile
@@ -469,10 +469,10 @@
 export KBUILD_DEFCONFIG KBUILD_KCONFIG
 
 config: scripts_basic outputmakefile FORCE
-	+$(Q)$(CONFIG_SHELL) $(srctree)/scripts/multiconfig.sh $@
+	$(Q)$(MAKE) $(build)=scripts/kconfig $@
 
 %config: scripts_basic outputmakefile FORCE
-	+$(Q)$(CONFIG_SHELL) $(srctree)/scripts/multiconfig.sh $@
+	$(Q)$(MAKE) $(build)=scripts/kconfig $@
 
 else
 # ===========================================================================
@@ -496,6 +496,15 @@
 # we execute the config step to be sure to catch updated Kconfig files
 include/config/%.conf: $(KCONFIG_CONFIG) include/config/auto.conf.cmd
 	$(Q)$(MAKE) -f $(srctree)/Makefile silentoldconfig
+	@# If the following part fails, include/config/auto.conf should be
+	@# deleted so "make silentoldconfig" will be re-run on the next build.
+	$(Q)$(MAKE) -f $(srctree)/scripts/Makefile.autoconf || \
+		{ rm -f include/config/auto.conf; false; }
+	@# include/config.h has been updated after "make silentoldconfig".
+	@# We need to touch include/config/auto.conf so it gets newer
+	@# than include/config.h.
+	@# Otherwise, 'make silentoldconfig' would be invoked twice.
+	$(Q)touch include/config/auto.conf
 
 -include include/autoconf.mk
 -include include/autoconf.mk.dep
@@ -1154,7 +1163,7 @@
 
 prepare1: prepare2 $(version_h) $(timestamp_h) \
                    include/config/auto.conf
-ifeq ($(__HAVE_ARCH_GENERIC_BOARD),)
+ifeq ($(CONFIG_HAVE_GENERIC_BOARD),)
 ifeq ($(CONFIG_SYS_GENERIC_BOARD),y)
 	@echo >&2 "  Your architecture does not support generic board."
 	@echo >&2 "  Please undefine CONFIG_SYS_GENERIC_BOARD in your board config file."
diff --git a/README b/README
index b0124d6..5d57eb9 100644
--- a/README
+++ b/README
@@ -4190,9 +4190,9 @@
 	to this new framework over time. Defining this will disable the
 	arch/foo/lib/board.c file and use common/board_f.c and
 	common/board_r.c instead. To use this option your architecture
-	must support it (i.e. must define __HAVE_ARCH_GENERIC_BOARD in
-	its config.mk file). If you find problems enabling this option on
-	your board please report the problem and send patches!
+	must support it (i.e. must select HAVE_GENERIC_BOARD in arch/Kconfig).
+	If you find problems enabling this option on your board please report
+	the problem and send patches!
 
 - CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC (OMAP only)
 	This is set by OMAP boards for the max time that reset should
diff --git a/arch/Kconfig b/arch/Kconfig
index 3d419bc..ca617e7 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -1,3 +1,10 @@
+config HAVE_GENERIC_BOARD
+	bool
+
+config SYS_GENERIC_BOARD
+	bool
+	depends on HAVE_GENERIC_BOARD
+
 choice
 	prompt "Architecture select"
 	default SANDBOX
@@ -5,34 +12,48 @@
 config ARC
 	bool "ARC architecture"
 	select HAVE_PRIVATE_LIBGCC
+	select HAVE_GENERIC_BOARD
+	select SYS_GENERIC_BOARD
 
 config ARM
 	bool "ARM architecture"
 	select HAVE_PRIVATE_LIBGCC
+	select HAVE_GENERIC_BOARD
 	select SUPPORT_OF_CONTROL
 
 config AVR32
 	bool "AVR32 architecture"
+	select HAVE_GENERIC_BOARD
 
 config BLACKFIN
 	bool "Blackfin architecture"
+	select HAVE_GENERIC_BOARD
+	select SYS_GENERIC_BOARD
 
 config M68K
 	bool "M68000 architecture"
+	select HAVE_GENERIC_BOARD
+	select SYS_GENERIC_BOARD
 
 config MICROBLAZE
 	bool "MicroBlaze architecture"
+	select HAVE_GENERIC_BOARD
+	select SYS_GENERIC_BOARD
 	select SUPPORT_OF_CONTROL
 
 config MIPS
 	bool "MIPS architecture"
 	select HAVE_PRIVATE_LIBGCC
+	select HAVE_GENERIC_BOARD
+	select SYS_GENERIC_BOARD
 
 config NDS32
 	bool "NDS32 architecture"
 
 config NIOS2
 	bool "Nios II architecture"
+	select HAVE_GENERIC_BOARD
+	select SYS_GENERIC_BOARD
 
 config OPENRISC
 	bool "OpenRISC architecture"
@@ -40,10 +61,13 @@
 config PPC
 	bool "PowerPC architecture"
 	select HAVE_PRIVATE_LIBGCC
+	select HAVE_GENERIC_BOARD
 	select SUPPORT_OF_CONTROL
 
 config SANDBOX
 	bool "Sandbox"
+	select HAVE_GENERIC_BOARD
+	select SYS_GENERIC_BOARD
 	select SUPPORT_OF_CONTROL
 
 config SH
@@ -56,6 +80,8 @@
 config X86
 	bool "x86 architecture"
 	select HAVE_PRIVATE_LIBGCC
+	select HAVE_GENERIC_BOARD
+	select SYS_GENERIC_BOARD
 	select SUPPORT_OF_CONTROL
 
 endchoice
diff --git a/arch/arc/config.mk b/arch/arc/config.mk
index 4fcd407..04c034b 100644
--- a/arch/arc/config.mk
+++ b/arch/arc/config.mk
@@ -57,6 +57,3 @@
 
 # Load address for standalone apps
 CONFIG_STANDALONE_LOAD_ADDR ?= 0x82000000
-
-# Support generic board on ARC
-__HAVE_ARCH_GENERIC_BOARD := y
diff --git a/arch/arc/include/asm/config.h b/arch/arc/include/asm/config.h
index b4e9099..8936f5c 100644
--- a/arch/arc/include/asm/config.h
+++ b/arch/arc/include/asm/config.h
@@ -7,7 +7,6 @@
 #ifndef __ASM_ARC_CONFIG_H_
 #define __ASM_ARC_CONFIG_H_
 
-#define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_SYS_GENERIC_GLOBAL_DATA
 #define CONFIG_SYS_BOOT_RAMDISK_HIGH
 #define CONFIG_ARCH_EARLY_INIT_R
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c0a0fd8..80b0d34 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -286,13 +286,8 @@
 	bool "Support mx35pdk"
 	select CPU_ARM1136
 
-config TARGET_RPI
-	bool "Support rpi"
-	select CPU_ARM1176
-
-config TARGET_RPI_2
-	bool "Support rpi_2"
-	select CPU_V7
+config ARCH_BCM283X
+	bool "Broadcom BCM283X family"
 
 config TARGET_INTEGRATORAP_CM946ES
 	bool "Support integratorap_cm946es"
@@ -727,9 +722,9 @@
 
 source "arch/arm/mach-at91/Kconfig"
 
-source "arch/arm/mach-davinci/Kconfig"
+source "arch/arm/mach-bcm283x/Kconfig"
 
-source "arch/arm/cpu/arm1176/bcm2835/Kconfig"
+source "arch/arm/mach-davinci/Kconfig"
 
 source "arch/arm/cpu/armv7/exynos/Kconfig"
 
@@ -842,8 +837,6 @@
 source "board/phytec/pcm051/Kconfig"
 source "board/ppcag/bg0900/Kconfig"
 source "board/pxa255_idp/Kconfig"
-source "board/raspberrypi/rpi/Kconfig"
-source "board/raspberrypi/rpi_2/Kconfig"
 source "board/samsung/smdk2410/Kconfig"
 source "board/sandisk/sansa_fuze_plus/Kconfig"
 source "board/scb9328/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 08946de..bac3cb2 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -5,6 +5,7 @@
 # Machine directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
 machine-$(CONFIG_ARCH_AT91)		+= at91
+machine-$(CONFIG_ARCH_BCM283X)		+= bcm283x
 machine-$(CONFIG_ARCH_DAVINCI)		+= davinci
 machine-$(CONFIG_ARCH_HIGHBANK)		+= highbank
 machine-$(CONFIG_ARCH_KEYSTONE)		+= keystone
diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index 0667984..c005ce4 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -19,9 +19,6 @@
 PLATFORM_RELFLAGS += $(call cc-option, -msoft-float) \
       $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
 
-# Support generic board on ARM
-__HAVE_ARCH_GENERIC_BOARD := y
-
 PLATFORM_CPPFLAGS += -D__ARM__
 
 # Choose between ARM/Thumb instruction sets
diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S
index 1cfcca9..1ec79a6 100644
--- a/arch/arm/cpu/arm1136/start.S
+++ b/arch/arm/cpu/arm1136/start.S
@@ -14,7 +14,6 @@
 
 #include <asm-offsets.h>
 #include <config.h>
-#include <version.h>
 
 /*
  *************************************************************************
diff --git a/arch/arm/cpu/arm1176/Makefile b/arch/arm/cpu/arm1176/Makefile
index 480e130..deec427 100644
--- a/arch/arm/cpu/arm1176/Makefile
+++ b/arch/arm/cpu/arm1176/Makefile
@@ -10,5 +10,3 @@
 
 extra-y	= start.o
 obj-y	= cpu.o
-
-obj-$(CONFIG_BCM2835) += bcm2835/
diff --git a/arch/arm/cpu/arm1176/bcm2835/Kconfig b/arch/arm/cpu/arm1176/bcm2835/Kconfig
deleted file mode 100644
index 73cc72b..0000000
--- a/arch/arm/cpu/arm1176/bcm2835/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_RPI || TARGET_RPI_2
-
-config DM
-	default y
-
-config DM_SERIAL
-	default y
-
-config DM_GPIO
-	default y
-
-endif
diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S
index ac937bf..4c0ab4d 100644
--- a/arch/arm/cpu/arm1176/start.S
+++ b/arch/arm/cpu/arm1176/start.S
@@ -16,7 +16,6 @@
 
 #include <asm-offsets.h>
 #include <config.h>
-#include <version.h>
 
 #ifndef CONFIG_SYS_PHY_UBOOT_BASE
 #define CONFIG_SYS_PHY_UBOOT_BASE	CONFIG_SYS_UBOOT_BASE
diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S
index 01c85be..ec8e88d 100644
--- a/arch/arm/cpu/arm720t/start.S
+++ b/arch/arm/cpu/arm720t/start.S
@@ -9,7 +9,6 @@
 
 #include <asm-offsets.h>
 #include <config.h>
-#include <version.h>
 #include <asm/hardware.h>
 
 /*
diff --git a/arch/arm/cpu/arm926ejs/mxs/start.S b/arch/arm/cpu/arm926ejs/mxs/start.S
index 9b60436..48abcd5 100644
--- a/arch/arm/cpu/arm926ejs/mxs/start.S
+++ b/arch/arm/cpu/arm926ejs/mxs/start.S
@@ -22,7 +22,6 @@
 #include <asm-offsets.h>
 #include <config.h>
 #include <common.h>
-#include <version.h>
 
 /*
  *************************************************************************
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
index 8eb2494..82cc1c9 100644
--- a/arch/arm/cpu/arm926ejs/start.S
+++ b/arch/arm/cpu/arm926ejs/start.S
@@ -18,7 +18,6 @@
 #include <asm-offsets.h>
 #include <config.h>
 #include <common.h>
-#include <version.h>
 
 /*
  *************************************************************************
diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S
index 4112371..b55395a 100644
--- a/arch/arm/cpu/arm946es/start.S
+++ b/arch/arm/cpu/arm946es/start.S
@@ -17,7 +17,6 @@
 
 #include <asm-offsets.h>
 #include <config.h>
-#include <version.h>
 
 /*
  *************************************************************************
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 1312a9d..21fc03b 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -39,7 +39,6 @@
 
 obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/
 obj-$(if $(filter armada-xp,$(SOC)),y) += armada-xp/
-obj-$(CONFIG_BCM2835) += bcm2835/
 obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/
 obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/
 obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/
diff --git a/arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S b/arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S
index 1febd7b..f4a7012 100644
--- a/arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S
+++ b/arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S
@@ -3,7 +3,6 @@
  */
 
 #include <config.h>
-#include <version.h>
 #include <linux/linkage.h>
 
 ENTRY(save_boot_params)
diff --git a/arch/arm/cpu/armv7/bcm2835/Makefile b/arch/arm/cpu/armv7/bcm2835/Makefile
deleted file mode 100644
index ed1ee47..0000000
--- a/arch/arm/cpu/armv7/bcm2835/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# (C) Copyright 2012 Stephen Warren
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-src_dir := ../../arm1176/bcm2835/
-
-obj-y	:=
-obj-y	+= $(src_dir)/init.o
-obj-y	+= $(src_dir)/reset.o
-obj-y	+= $(src_dir)/timer.o
-obj-y	+= $(src_dir)/mbox.o
diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig
index eb86a7f..bd7540a 100644
--- a/arch/arm/cpu/armv7/exynos/Kconfig
+++ b/arch/arm/cpu/armv7/exynos/Kconfig
@@ -80,12 +80,6 @@
 config DM_GPIO
 	default y
 
-config SYS_MALLOC_F
-	default y
-
-config SYS_MALLOC_F_LEN
-	default 0x400
-
 source "board/samsung/smdkv310/Kconfig"
 source "board/samsung/trats/Kconfig"
 source "board/samsung/universal_c210/Kconfig"
diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos4.c b/arch/arm/cpu/armv7/exynos/clock_init_exynos4.c
index 3161090..584e4ba 100644
--- a/arch/arm/cpu/armv7/exynos/clock_init_exynos4.c
+++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos4.c
@@ -25,7 +25,6 @@
 
 #include <common.h>
 #include <config.h>
-#include <version.h>
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/clk.h>
diff --git a/arch/arm/cpu/armv7/exynos/exynos4_setup.h b/arch/arm/cpu/armv7/exynos/exynos4_setup.h
index b633e56..9f29d94 100644
--- a/arch/arm/cpu/armv7/exynos/exynos4_setup.h
+++ b/arch/arm/cpu/armv7/exynos/exynos4_setup.h
@@ -10,7 +10,6 @@
 #define _ORIGEN_SETUP_H
 
 #include <config.h>
-#include <version.h>
 #include <asm/arch/cpu.h>
 
 #ifdef CONFIG_CLK_800_330_165
diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig
index 65da6e2..1f96498 100644
--- a/arch/arm/cpu/armv7/omap3/Kconfig
+++ b/arch/arm/cpu/armv7/omap3/Kconfig
@@ -106,12 +106,6 @@
 config DM_SERIAL
 	default y if DM
 
-config SYS_MALLOC_F
-	default y if DM
-
-config SYS_MALLOC_F_LEN
-	default 0x400 if DM
-
 config SYS_SOC
 	default "omap3"
 
diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
index 7a69151..2497613 100644
--- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
@@ -12,7 +12,6 @@
  */
 
 #include <config.h>
-#include <version.h>
 #include <asm/arch/mem.h>
 #include <asm/arch/clocks_omap3.h>
 #include <linux/linkage.h>
diff --git a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S
index afed773..b4d0627 100644
--- a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S
@@ -5,7 +5,6 @@
  */
 
 #include <config.h>
-#include <version.h>
 
 /* Set up the platform, once the cpu has been initialized */
 .globl lowlevel_init
diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c
index bd9f338..6a8c15d 100644
--- a/arch/arm/cpu/armv7/socfpga/spl.c
+++ b/arch/arm/cpu/armv7/socfpga/spl.c
@@ -8,7 +8,6 @@
 #include <asm/io.h>
 #include <asm/u-boot.h>
 #include <asm/utils.h>
-#include <version.h>
 #include <image.h>
 #include <asm/arch/reset_manager.h>
 #include <spl.h>
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 5050021..5ed0f45 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -15,7 +15,6 @@
 
 #include <asm-offsets.h>
 #include <config.h>
-#include <version.h>
 #include <asm/system.h>
 #include <linux/linkage.h>
 
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
index 49f4032..c3e04af 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
@@ -100,22 +100,23 @@
 	unsigned int freq;
 } pll1_para[] = {
 	/* This array must be ordered by frequency. */
-	{ PLL1_CFG(16, 0, 0, 0), 384000000 },
-	{ PLL1_CFG(16, 1, 0, 0), 768000000 },
-	{ PLL1_CFG(20, 1, 0, 0), 960000000 },
-	{ PLL1_CFG(21, 1, 0, 0), 1008000000},
-	{ PLL1_CFG(22, 1, 0, 0), 1056000000},
-	{ PLL1_CFG(23, 1, 0, 0), 1104000000},
-	{ PLL1_CFG(24, 1, 0, 0), 1152000000},
-	{ PLL1_CFG(25, 1, 0, 0), 1200000000},
-	{ PLL1_CFG(26, 1, 0, 0), 1248000000},
-	{ PLL1_CFG(27, 1, 0, 0), 1296000000},
-	{ PLL1_CFG(28, 1, 0, 0), 1344000000},
-	{ PLL1_CFG(29, 1, 0, 0), 1392000000},
-	{ PLL1_CFG(30, 1, 0, 0), 1440000000},
 	{ PLL1_CFG(31, 1, 0, 0), 1488000000},
-	/* Final catchall entry */
-	{ PLL1_CFG(31, 1, 0, 0), ~0},
+	{ PLL1_CFG(30, 1, 0, 0), 1440000000},
+	{ PLL1_CFG(29, 1, 0, 0), 1392000000},
+	{ PLL1_CFG(28, 1, 0, 0), 1344000000},
+	{ PLL1_CFG(27, 1, 0, 0), 1296000000},
+	{ PLL1_CFG(26, 1, 0, 0), 1248000000},
+	{ PLL1_CFG(25, 1, 0, 0), 1200000000},
+	{ PLL1_CFG(24, 1, 0, 0), 1152000000},
+	{ PLL1_CFG(23, 1, 0, 0), 1104000000},
+	{ PLL1_CFG(22, 1, 0, 0), 1056000000},
+	{ PLL1_CFG(21, 1, 0, 0), 1008000000},
+	{ PLL1_CFG(20, 1, 0, 0), 960000000 },
+	{ PLL1_CFG(19, 1, 0, 0), 912000000 },
+	{ PLL1_CFG(16, 1, 0, 0), 768000000 },
+	/* Final catchall entry 384MHz*/
+	{ PLL1_CFG(16, 0, 0, 0), 0 },
+
 };
 
 void clock_set_pll1(unsigned int hz)
@@ -126,10 +127,12 @@
 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
 	/* Find target frequency */
-	while (pll1_para[i].freq < hz)
+	while (pll1_para[i].freq > hz)
 		i++;
 
 	hz = pll1_para[i].freq;
+	if (! hz)
+		hz = 384000000;
 
 	/* Calculate system clock divisors */
 	axi = DIV_ROUND_UP(hz, 432000000);	/* Max 450MHz */
diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S
index 5be497b..e0a524e 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.S
+++ b/arch/arm/cpu/armv7/sunxi/psci.S
@@ -37,7 +37,7 @@
 
 	.arch_extension sec
 
-#define	ONE_MS			(CONFIG_SYS_CLK_FREQ / 1000)
+#define	ONE_MS			(CONFIG_TIMER_CLK_FREQ / 1000)
 #define	TEN_MS			(10 * ONE_MS)
 #define	GICD_BASE		0x1c81000
 #define	GICC_BASE		0x1c82000
diff --git a/arch/arm/cpu/armv7/sunxi/usbc.c b/arch/arm/cpu/armv7/sunxi/usbc.c
index 14de9f9..524f25c 100644
--- a/arch/arm/cpu/armv7/sunxi/usbc.c
+++ b/arch/arm/cpu/armv7/sunxi/usbc.c
@@ -182,6 +182,13 @@
 	return;
 }
 
+void sunxi_usbc_enable_squelch_detect(int index, int enable)
+{
+	struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index];
+
+	usb_phy_write(sunxi_usbc, 0x3c, enable ? 0 : 2, 2);
+}
+
 int sunxi_usbc_request_resources(int index)
 {
 	struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index];
diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S
index fa447bc..d846236 100644
--- a/arch/arm/cpu/armv8/cache.S
+++ b/arch/arm/cpu/armv8/cache.S
@@ -9,7 +9,6 @@
 
 #include <asm-offsets.h>
 #include <config.h>
-#include <version.h>
 #include <asm/macro.h>
 #include <linux/linkage.h>
 
diff --git a/arch/arm/cpu/armv8/exceptions.S b/arch/arm/cpu/armv8/exceptions.S
index b91a1b6..baf9401 100644
--- a/arch/arm/cpu/armv8/exceptions.S
+++ b/arch/arm/cpu/armv8/exceptions.S
@@ -7,7 +7,6 @@
 
 #include <asm-offsets.h>
 #include <config.h>
-#include <version.h>
 #include <asm/ptrace.h>
 #include <asm/macro.h>
 #include <linux/linkage.h>
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index b4eab0b..e5f2766 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -7,7 +7,6 @@
 
 #include <asm-offsets.h>
 #include <config.h>
-#include <version.h>
 #include <linux/linkage.h>
 #include <asm/macro.h>
 #include <asm/armv8/mmu.h>
diff --git a/arch/arm/cpu/armv8/tlb.S b/arch/arm/cpu/armv8/tlb.S
index f840b04..945445b 100644
--- a/arch/arm/cpu/armv8/tlb.S
+++ b/arch/arm/cpu/armv8/tlb.S
@@ -7,7 +7,6 @@
 
 #include <asm-offsets.h>
 #include <config.h>
-#include <version.h>
 #include <linux/linkage.h>
 #include <asm/macro.h>
 
diff --git a/arch/arm/cpu/armv8/transition.S b/arch/arm/cpu/armv8/transition.S
index ade1cde..253a39b 100644
--- a/arch/arm/cpu/armv8/transition.S
+++ b/arch/arm/cpu/armv8/transition.S
@@ -7,7 +7,6 @@
 
 #include <asm-offsets.h>
 #include <config.h>
-#include <version.h>
 #include <linux/linkage.h>
 #include <asm/macro.h>
 
diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S
index c77d51e..879390b 100644
--- a/arch/arm/cpu/pxa/start.S
+++ b/arch/arm/cpu/pxa/start.S
@@ -21,7 +21,6 @@
 
 #include <asm-offsets.h>
 #include <config.h>
-#include <version.h>
 
 /*
  *************************************************************************
diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S
index 78e0cb8..eebff66 100644
--- a/arch/arm/cpu/sa1100/start.S
+++ b/arch/arm/cpu/sa1100/start.S
@@ -11,7 +11,6 @@
 
 #include <asm-offsets.h>
 #include <config.h>
-#include <version.h>
 
 /*
  *************************************************************************
diff --git a/arch/arm/include/asm/arch-sunxi/usbc.h b/arch/arm/include/asm/arch-sunxi/usbc.h
index cb538cd..1330733 100644
--- a/arch/arm/include/asm/arch-sunxi/usbc.h
+++ b/arch/arm/include/asm/arch-sunxi/usbc.h
@@ -20,3 +20,4 @@
 void sunxi_usbc_disable(int index);
 void sunxi_usbc_vbus_enable(int index);
 void sunxi_usbc_vbus_disable(int index);
+void sunxi_usbc_enable_squelch_detect(int index, int enable);
diff --git a/arch/arm/include/asm/semihosting.h b/arch/arm/include/asm/semihosting.h
deleted file mode 100644
index 835ca7e..0000000
--- a/arch/arm/include/asm/semihosting.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright 2014 Broadcom Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __SEMIHOSTING_H__
-#define __SEMIHOSTING_H__
-
-/*
- * ARM semihosting functions for loading images to memory. See the source
- * code for more information.
- */
-int smh_load(const char *fname, void *memp, int avail, int verbose);
-long smh_len(const char *fname);
-
-#endif /* __SEMIHOSTING_H__ */
diff --git a/arch/arm/lib/semihosting.c b/arch/arm/lib/semihosting.c
index fd6d857..c3e964e 100644
--- a/arch/arm/lib/semihosting.c
+++ b/arch/arm/lib/semihosting.c
@@ -13,7 +13,7 @@
  * for them.
  */
 #include <common.h>
-#include <asm/semihosting.h>
+#include <command.h>
 
 #define SYSOPEN		0x01
 #define SYSCLOSE	0x02
@@ -26,7 +26,7 @@
 /*
  * Call the handler
  */
-static long smh_trap(unsigned int sysnum, void *addr)
+static noinline long smh_trap(unsigned int sysnum, void *addr)
 {
 	register long result asm("r0");
 #if defined(CONFIG_ARM64)
@@ -144,93 +144,71 @@
 	return ret;
 }
 
-/*
- * Open, load a file into memory, and close it. Check that the available space
- * is sufficient to store the entire file. Return the bytes actually read from
- * the file as seen by the read function. The verbose flag enables some extra
- * printing of successful read status.
- */
-int smh_load(const char *fname, void *memp, int avail, int verbose)
+static int smh_load_file(const char * const name, ulong load_addr,
+			 ulong *end_addr)
 {
-	long ret;
 	long fd;
-	size_t len;
-
-	ret = -1;
-
-	debug("%s: fname \'%s\', avail %u, memp %p\n", __func__, fname,
-	      avail, memp);
+	long len;
+	long ret;
 
-	/* Open the file */
-	fd = smh_open(fname, "rb");
+	fd = smh_open(name, "rb");
 	if (fd == -1)
 		return -1;
-
-	/* Get the file length */
-	ret = smh_len_fd(fd);
-	if (ret == -1) {
-		smh_close(fd);
-		return -1;
-	}
 
-	/* Check that the file will fit in the supplied buffer */
-	if (ret > avail) {
-		printf("%s: ERROR ret %ld, avail %u\n", __func__, ret,
-		       avail);
+	len = smh_len_fd(fd);
+	if (len < 0) {
 		smh_close(fd);
 		return -1;
 	}
 
-	len = ret;
+	ret = smh_read(fd, (void *)load_addr, len);
+	smh_close(fd);
 
-	/* Read the file into the buffer */
-	ret = smh_read(fd, memp, len);
 	if (ret == 0) {
-		/* Print successful load information if requested */
-		if (verbose) {
-			printf("\n%s\n", fname);
-			printf("    0x%8p dest\n", memp);
-			printf("    0x%08lx size\n", len);
-			printf("    0x%08x avail\n", avail);
-		}
+		*end_addr = load_addr + len - 1;
+		printf("loaded file %s from %08lX to %08lX, %08lX bytes\n",
+		       name,
+		       load_addr,
+		       *end_addr,
+		       len);
+	} else {
+		printf("read failed\n");
+		return 0;
 	}
 
-	/* Close the file */
-	smh_close(fd);
-
-	return ret;
+	return 0;
 }
 
-/*
- * Get the file length from the filename
- */
-long smh_len(const char *fname)
+static int do_smhload(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	long ret;
-	long fd;
-	long len;
+	if (argc == 3 || argc == 4) {
+		ulong load_addr;
+		ulong end_addr = 0;
+		ulong ret;
+		char end_str[64];
 
-	debug("%s: file \'%s\'\n", __func__, fname);
+		load_addr = simple_strtoul(argv[2], NULL, 16);
+		if (!load_addr)
+			return -1;
 
-	/* Open the file */
-	fd = smh_open(fname, "rb");
-	if (fd < 0)
-		return fd;
+		ret = smh_load_file(argv[1], load_addr, &end_addr);
+		if (ret < 0)
+			return 1;
 
-	/* Get the file length */
-	len = smh_len_fd(fd);
-	if (len < 0) {
-		smh_close(fd);
-		return len;
+		/* Optionally save returned end to the environment */
+		if (argc == 4) {
+			sprintf(end_str, "0x%08lx", end_addr);
+			setenv(argv[3], end_str);
+		}
+	} else {
+		return CMD_RET_USAGE;
 	}
-
-	/* Close the file */
-	ret = smh_close(fd);
-	if (ret < 0)
-		return ret;
-
-	debug("%s: returning len %ld\n", __func__, len);
-
-	/* Return the file length (or -1 error indication) */
-	return len;
+	return 0;
 }
+
+U_BOOT_CMD(smhload, 4, 0, do_smhload, "load a file using semihosting",
+	   "<file> 0x<address> [end var]\n"
+	   "    - load a semihosted file to the address specified\n"
+	   "      if the optional [end var] is specified, the end\n"
+	   "      address of the file will be stored in this environment\n"
+	   "      variable.\n");
diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
new file mode 100644
index 0000000..b43f2d9
--- /dev/null
+++ b/arch/arm/mach-bcm283x/Kconfig
@@ -0,0 +1,40 @@
+menu "Broadcom BCM283X family"
+	depends on ARCH_BCM283X
+
+choice
+	prompt "Broadcom BCM283X board select"
+
+config TARGET_RPI
+	bool "Raspberry Pi"
+	select CPU_ARM1176
+
+config TARGET_RPI_2
+	bool "Raspberry Pi 2"
+	select CPU_V7
+
+endchoice
+
+config DM
+	default y
+
+config DM_SERIAL
+	default y
+
+config DM_GPIO
+	default y
+
+config SYS_BOARD
+	default "rpi" if TARGET_RPI
+	default "rpi_2" if TARGET_RPI_2
+
+config SYS_VENDOR
+	default "raspberrypi"
+
+config SYS_SOC
+	default "bcm283x"
+
+config SYS_CONFIG_NAME
+	default "rpi" if TARGET_RPI
+	default "rpi_2" if TARGET_RPI_2
+
+endmenu
diff --git a/arch/arm/cpu/arm1176/bcm2835/Makefile b/arch/arm/mach-bcm283x/Makefile
similarity index 72%
rename from arch/arm/cpu/arm1176/bcm2835/Makefile
rename to arch/arm/mach-bcm283x/Makefile
index 7e5dbe1..2505428 100644
--- a/arch/arm/cpu/arm1176/bcm2835/Makefile
+++ b/arch/arm/mach-bcm283x/Makefile
@@ -4,5 +4,5 @@
 # SPDX-License-Identifier:	GPL-2.0
 #
 
-obj-y	:= lowlevel_init.o
+obj-$(CONFIG_TARGET_RPI) += lowlevel_init.o
 obj-y	+= init.o reset.o timer.o mbox.o
diff --git a/arch/arm/include/asm/arch-bcm2835/gpio.h b/arch/arm/mach-bcm283x/include/mach/gpio.h
similarity index 100%
rename from arch/arm/include/asm/arch-bcm2835/gpio.h
rename to arch/arm/mach-bcm283x/include/mach/gpio.h
diff --git a/arch/arm/include/asm/arch-bcm2835/mbox.h b/arch/arm/mach-bcm283x/include/mach/mbox.h
similarity index 100%
rename from arch/arm/include/asm/arch-bcm2835/mbox.h
rename to arch/arm/mach-bcm283x/include/mach/mbox.h
diff --git a/arch/arm/include/asm/arch-bcm2835/sdhci.h b/arch/arm/mach-bcm283x/include/mach/sdhci.h
similarity index 100%
rename from arch/arm/include/asm/arch-bcm2835/sdhci.h
rename to arch/arm/mach-bcm283x/include/mach/sdhci.h
diff --git a/arch/arm/include/asm/arch-bcm2835/timer.h b/arch/arm/mach-bcm283x/include/mach/timer.h
similarity index 100%
rename from arch/arm/include/asm/arch-bcm2835/timer.h
rename to arch/arm/mach-bcm283x/include/mach/timer.h
diff --git a/arch/arm/include/asm/arch-bcm2835/wdog.h b/arch/arm/mach-bcm283x/include/mach/wdog.h
similarity index 100%
rename from arch/arm/include/asm/arch-bcm2835/wdog.h
rename to arch/arm/mach-bcm283x/include/mach/wdog.h
diff --git a/arch/arm/cpu/arm1176/bcm2835/init.c b/arch/arm/mach-bcm283x/init.c
similarity index 100%
rename from arch/arm/cpu/arm1176/bcm2835/init.c
rename to arch/arm/mach-bcm283x/init.c
diff --git a/arch/arm/cpu/arm1176/bcm2835/lowlevel_init.S b/arch/arm/mach-bcm283x/lowlevel_init.S
similarity index 100%
rename from arch/arm/cpu/arm1176/bcm2835/lowlevel_init.S
rename to arch/arm/mach-bcm283x/lowlevel_init.S
diff --git a/arch/arm/cpu/arm1176/bcm2835/mbox.c b/arch/arm/mach-bcm283x/mbox.c
similarity index 100%
rename from arch/arm/cpu/arm1176/bcm2835/mbox.c
rename to arch/arm/mach-bcm283x/mbox.c
diff --git a/arch/arm/cpu/arm1176/bcm2835/reset.c b/arch/arm/mach-bcm283x/reset.c
similarity index 100%
rename from arch/arm/cpu/arm1176/bcm2835/reset.c
rename to arch/arm/mach-bcm283x/reset.c
diff --git a/arch/arm/cpu/arm1176/bcm2835/timer.c b/arch/arm/mach-bcm283x/timer.c
similarity index 100%
rename from arch/arm/cpu/arm1176/bcm2835/timer.c
rename to arch/arm/mach-bcm283x/timer.c
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index fccfd79..fce1c1d 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -17,9 +17,6 @@
 
 endchoice
 
-config SYS_MALLOC_F
-	default y
-
 config SYS_MALLOC_F_LEN
 	default 0x1800
 
diff --git a/arch/arm/mach-tegra/lowlevel_init.S b/arch/arm/mach-tegra/lowlevel_init.S
index a211bb3..4bc0a3f 100644
--- a/arch/arm/mach-tegra/lowlevel_init.S
+++ b/arch/arm/mach-tegra/lowlevel_init.S
@@ -8,7 +8,6 @@
  */
 
 #include <config.h>
-#include <version.h>
 #include <linux/linkage.h>
 
 	.align	5
diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig
index 8335685..288e6ab 100644
--- a/arch/arm/mach-uniphier/Kconfig
+++ b/arch/arm/mach-uniphier/Kconfig
@@ -1,9 +1,6 @@
 menu "Panasonic UniPhier platform"
 	depends on ARCH_UNIPHIER
 
-config SYS_SOC
-	default "uniphier"
-
 config SYS_CONFIG_NAME
 	default "uniphier"
 
@@ -48,12 +45,6 @@
 
 endchoice
 
-config SYS_MALLOC_F
-	default y
-
-config SYS_MALLOC_F_LEN
-	default 0x400
-
 config CMD_PINMON
 	bool "Enable boot mode pins monitor command"
 	default y
diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile
index e7a801b..24591d6 100644
--- a/arch/arm/mach-uniphier/Makefile
+++ b/arch/arm/mach-uniphier/Makefile
@@ -12,6 +12,7 @@
 
 else
 
+obj-y += late_lowlevel_init.o
 obj-$(CONFIG_BOARD_EARLY_INIT_F) += board_early_init_f.o
 obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o
 obj-$(CONFIG_MISC_INIT_F) += print_misc_info.o
@@ -21,7 +22,6 @@
 obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o
 obj-y += reset.o
 obj-y += cache_uniphier.o
-obj-$(CONFIG_UNIPHIER_SMP) += smp.o
 obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o
 obj-$(CONFIG_CMD_DDRPHY_DUMP) += cmd_ddrphy.o
 
diff --git a/arch/arm/mach-uniphier/cache_uniphier.c b/arch/arm/mach-uniphier/cache_uniphier.c
index 52f3c7c..d8b8228 100644
--- a/arch/arm/mach-uniphier/cache_uniphier.c
+++ b/arch/arm/mach-uniphier/cache_uniphier.c
@@ -1,6 +1,7 @@
 /*
  * Copyright (C) 2012-2014 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2015      Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -119,36 +120,7 @@
 	writel(tmp, SSCC);
 }
 
-void wakeup_secondary(void);
-
 void enable_caches(void)
 {
-	uint32_t reg;
-
-#ifdef CONFIG_UNIPHIER_SMP
-	/*
-	 * The secondary CPU must move to DDR,
-	 * before L2 disable.
-	 * On SPL, the Page Table is located on the L2.
-	 */
-	wakeup_secondary();
-#endif
-	/*
-	 * UniPhier SoCs must use L2 cache for init stack pointer.
-	 * We disable L2 and L1 in this order.
-	 * If CONFIG_SYS_DCACHE_OFF is not defined,
-	 * caches are enabled again with a new page table.
-	 */
-
-	/* L2 disable */
-	v7_outer_cache_disable();
-
-	/* L1 disable */
-	reg = get_cr();
-	reg &= ~(CR_C | CR_M);
-	set_cr(reg);
-
-#ifndef CONFIG_SYS_DCACHE_OFF
 	dcache_enable();
-#endif
 }
diff --git a/arch/arm/mach-uniphier/init_page_table.S b/arch/arm/mach-uniphier/init_page_table.S
index 2638bcd..ac2959a 100644
--- a/arch/arm/mach-uniphier/init_page_table.S
+++ b/arch/arm/mach-uniphier/init_page_table.S
@@ -1,3 +1,11 @@
+/*
+ * Copyright (C) 2015 Panasonic Corporation
+ * Copyright (C) 2015 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
 #include <config.h>
 #include <linux/linkage.h>
 
@@ -8,7 +16,7 @@
 #define NORMAL	0x0000000e /* Normal Memory Write-Back, No Write-Allocate */
 
 #define TEXT_SECTION	((CONFIG_SPL_TEXT_BASE) >> (SECTION_SHIFT))
-#define STACK_SECTION	((CONFIG_SYS_INIT_SP_ADDR) >> (SECTION_SHIFT))
+#define STACK_SECTION	((CONFIG_SPL_STACK) >> (SECTION_SHIFT))
 
 	.section ".rodata"
 	.align 14
diff --git a/arch/arm/mach-uniphier/late_lowlevel_init.S b/arch/arm/mach-uniphier/late_lowlevel_init.S
new file mode 100644
index 0000000..1363364
--- /dev/null
+++ b/arch/arm/mach-uniphier/late_lowlevel_init.S
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2015 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/linkage.h>
+#include <mach/ssc-regs.h>
+
+ENTRY(lowlevel_init)
+	ldr	r1, = SSCC
+	ldr	r0, [r1]
+	bic	r0, r0, #SSCC_ON	@ L2 disable
+	str	r0, [r1]
+	mov	pc, lr
+ENDPROC(lowlevel_init)
diff --git a/arch/arm/mach-uniphier/lowlevel_init.S b/arch/arm/mach-uniphier/lowlevel_init.S
index 92299fe..825b160 100644
--- a/arch/arm/mach-uniphier/lowlevel_init.S
+++ b/arch/arm/mach-uniphier/lowlevel_init.S
@@ -1,6 +1,7 @@
 /*
- * Copyright (C) 2012-2014 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2012-2015 Panasonic Corporation
+ * Copyright (C) 2015      Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -24,8 +25,8 @@
 	 * First we need to turn on MMU and Dcache again to get back
 	 * data access to L2.
 	 */
-	mrc	p15, 0, r0, c1, c0, 0		@ SCTLR (System Contrl Register)
-	orr	r0, r0, #(CR_C | CR_M)		@ enable MMU and Dcache
+	mrc	p15, 0, r0, c1, c0, 0	@ SCTLR (System Control Register)
+	orr	r0, r0, #(CR_C | CR_M)	@ enable MMU and Dcache
 	mcr	p15, 0, r0, c1, c0, 0
 
 #ifdef CONFIG_DEBUG_LL
@@ -40,13 +41,32 @@
 	ldr	r3, =init_page_table	@ page table must be 16KB aligned
 
 	/* Disable MMU and Dcache before switching Page Table */
-	mrc	p15, 0, r0, c1, c0, 0	@ SCTLR (System Contrl Register)
+	mrc	p15, 0, r0, c1, c0, 0	@ SCTLR (System Control Register)
 	bic	r0, r0, #(CR_C | CR_M)	@ disable MMU and Dcache
 	mcr	p15, 0, r0, c1, c0, 0
 
 	bl	enable_mmu
 
 #ifdef CONFIG_UNIPHIER_SMP
+secondary_startup:
+	/*
+	 * Entry point for secondary CPUs
+	 *
+	 * The Boot ROM has already enabled MMU for the secondary CPUs as well
+	 * as for the primary one.  The MMU table embedded in the Boot ROM
+	 * prohibits the DRAM access, so it is impossible to bring the
+	 * secondary CPUs into DRAM directly.  They must jump here into SPL,
+	 * which is run on L2 cache.
+	 *
+	 * Boot Sequence
+	 *  [primary CPU]                    [secondary CPUs]
+	 *  start from Boot ROM             start from Boot ROM
+	 *     jump to SPL                    sleep in Boot ROM
+	 *  kick secondaries   ---(sev)--->    jump to SPL
+	 *  jump to U-Boot main               sleep in SPL
+	 *  jump to Linux
+	 *  kick secondaries   ---(sev)--->    jump to Linux
+	 */
 	/*
 	 * ACTLR (Auxiliary Control Register) for Cortex-A9
 	 * bit[9]  Parity on
@@ -54,7 +74,7 @@
 	 * bit[7]  EXCL (Exclusive cache bit)
 	 * bit[6]  SMP
 	 * bit[3]  Write full line of zeros mode
-	 * bit[2]  L1 Prefetch enable
+	 * bit[2]  L1 prefetch enable
 	 * bit[1]  L2 prefetch enable
 	 * bit[0]  FW (Cache and TLB maintenance broadcast)
 	 */
@@ -67,20 +87,31 @@
 	and  	r0, r0, #0x3
 	cmp	r0, #0x0
 	beq	primary_cpu
-	ldr	r1, =ROM_BOOT_ROMRSV2
+	/* only for secondary CPUs */
+	ldr	r1, =ROM_BOOT_ROMRSV2	@ The last data access to L2 cache
+	mrc	p15, 0, r0, c1, c0, 0	@ SCTLR (System Control Register)
+	orr	r0, r0, #CR_I		@ Enable ICache
+	bic	r0, r0, #(CR_C | CR_M)	@ MMU and Dcache must be disabled
+	mcr	p15, 0, r0, c1, c0, 0	@ before jumping to Linux
 	mov	r0, #0
 	str	r0, [r1]
-0:	wfe
-	ldr	r0, [r1]
+	b	1f
+	/*
+	 * L2 cache is shared among all the CPUs and it might be disabled by
+	 * the primary one.  Before that, the following 5 lines must be cached
+	 * on the Icaches of the secondary CPUs.
+	 */
+0:	wfe				@ kicked by Linux
+1:	ldr	r0, [r1]
 	cmp	r0, #0
-	beq	0b
-	bx	r0			@ r0: entry point of U-Boot main for the secondary CPU
+	bxne	r0			@ r0: Linux entry for secondary CPUs
+	b	0b
 primary_cpu:
 	ldr	r1, =ROM_BOOT_ROMRSV2
-	ldr	r0, =_start		@ entry for the secondary CPU
+	ldr	r0, =secondary_startup
 	str	r0, [r1]
 	ldr	r0, [r1]		@ make sure str is complete before sev
-	sev				@ kick the sedoncary CPU
+	sev				@ kick the secondary CPU
 	mrc	p15, 4, r1, c15, c0, 0	@ Configuration Base Address Register
 	bfc	r1, #0, #13		@ clear bit 12-0
 	mov	r0, #-1
@@ -117,7 +148,7 @@
 	 * TLBs was already invalidated in "../start.S"
 	 * So, we don't need to invalidate it here.
 	 */
-	mrc	p15, 0, r0, c1, c0, 0	@ SCTLR (System Contrl Register)
+	mrc	p15, 0, r0, c1, c0, 0	@ SCTLR (System Control Register)
 	orr	r0, r0, #(CR_C | CR_M)	@ MMU and Dcache enable
 	mcr	p15, 0, r0, c1, c0, 0
 
@@ -142,7 +173,7 @@
 	ldr	r0, = 0x00408006	@ touch to zero with address range
 	ldr	r1, = SSCOQM
 	str	r0, [r1]
-	ldr	r0, = (CONFIG_SYS_INIT_SP_ADDR - BOOT_RAM_SIZE)	@ base address
+	ldr	r0, = (CONFIG_SPL_STACK - BOOT_RAM_SIZE)	@ base address
 	ldr	r1, = SSCOQAD
 	str	r0, [r1]
 	ldr	r0, = BOOT_RAM_SIZE
@@ -154,7 +185,7 @@
 	ldr	r1, = SSCOPPQSEF
 	ldr	r0, [r1]
 	cmp	r0, #0			@ check if the command is successfully set
-	bne	0b			@ try again if an error occurres
+	bne	0b			@ try again if an error occurs
 
 	ldr	r1, = SSCOLPQS
 1:
diff --git a/arch/arm/mach-uniphier/ph1-ld4/Makefile b/arch/arm/mach-uniphier/ph1-ld4/Makefile
index 5ce3d8a..af815c3 100644
--- a/arch/arm/mach-uniphier/ph1-ld4/Makefile
+++ b/arch/arm/mach-uniphier/ph1-ld4/Makefile
@@ -5,12 +5,12 @@
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
 obj-y += bcu_init.o sg_init.o pll_init.o early_clkrst_init.o \
-	pll_spectrum.o umc_init.o ddrphy_init.o
+	early_pinctrl.o pll_spectrum.o umc_init.o ddrphy_init.o
 obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
 obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
+obj-$(CONFIG_SPL_DM) += platdevice.o
 else
 obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
-obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
 endif
 
 obj-y += boot-mode.o
diff --git a/arch/arm/mach-uniphier/ph1-ld4/early_pinctrl.c b/arch/arm/mach-uniphier/ph1-ld4/early_pinctrl.c
new file mode 100644
index 0000000..e5e86bb
--- /dev/null
+++ b/arch/arm/mach-uniphier/ph1-ld4/early_pinctrl.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2011-2015 Panasonic Corporation
+ * Copyright (C) 2015      Socionext Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <mach/sg-regs.h>
+
+void early_pin_init(void)
+{
+	/* Comment format:    PAD Name -> Function Name */
+
+#ifdef CONFIG_UNIPHIER_SERIAL
+	sg_set_pinsel(85, 1);	/* HSDOUT3 -> RXD0 */
+	sg_set_pinsel(88, 1);	/* HDDOUT6 -> TXD0 */
+
+	sg_set_pinsel(69, 23);	/* PCIOWR -> TXD1 */
+	sg_set_pinsel(70, 23);	/* PCIORD -> RXD1 */
+
+	sg_set_pinsel(128, 13);	/* XIRQ6 -> TXD2 */
+	sg_set_pinsel(129, 13);	/* XIRQ7 -> RXD2 */
+
+	sg_set_pinsel(110, 1);	/* SBO0 -> TXD3 */
+	sg_set_pinsel(111, 1);	/* SBI0 -> RXD3 */
+#endif
+}
diff --git a/arch/arm/mach-uniphier/ph1-ld4/pinctrl.c b/arch/arm/mach-uniphier/ph1-ld4/pinctrl.c
index 15d81eb..3074d0a 100644
--- a/arch/arm/mach-uniphier/ph1-ld4/pinctrl.c
+++ b/arch/arm/mach-uniphier/ph1-ld4/pinctrl.c
@@ -1,10 +1,10 @@
 /*
- * Copyright (C) 2011-2014 Panasonic Corporation
+ * Copyright (C) 2011-2015 Panasonic Corporation
+ * Copyright (C) 2015      Socionext Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include <common.h>
 #include <asm/io.h>
 #include <mach/sg-regs.h>
 
@@ -14,20 +14,6 @@
 
 	/* Comment format:    PAD Name -> Function Name */
 
-#ifdef CONFIG_UNIPHIER_SERIAL
-	sg_set_pinsel(85, 1);	/* HSDOUT3 -> RXD0 */
-	sg_set_pinsel(88, 1);	/* HDDOUT6 -> TXD0 */
-
-	sg_set_pinsel(69, 23);	/* PCIOWR -> TXD1 */
-	sg_set_pinsel(70, 23);	/* PCIORD -> RXD1 */
-
-	sg_set_pinsel(128, 13);	/* XIRQ6 -> TXD2 */
-	sg_set_pinsel(129, 13);	/* XIRQ7 -> RXD2 */
-
-	sg_set_pinsel(110, 1);	/* SBO0 -> TXD3 */
-	sg_set_pinsel(111, 1);	/* SBI0 -> RXD3 */
-#endif
-
 #ifdef CONFIG_NAND_DENALI
 	sg_set_pinsel(158, 0);	/* XNFRE -> XNFRE_GB */
 	sg_set_pinsel(159, 0);	/* XNFWE -> XNFWE_GB */
diff --git a/arch/arm/mach-uniphier/ph1-pro4/Makefile b/arch/arm/mach-uniphier/ph1-pro4/Makefile
index b88525c..f6a584e 100644
--- a/arch/arm/mach-uniphier/ph1-pro4/Makefile
+++ b/arch/arm/mach-uniphier/ph1-pro4/Makefile
@@ -5,12 +5,12 @@
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
 obj-y += sg_init.o pll_init.o early_clkrst_init.o \
-	pll_spectrum.o umc_init.o ddrphy_init.o
+	early_pinctrl.o pll_spectrum.o umc_init.o ddrphy_init.o
 obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
 obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
+obj-$(CONFIG_SPL_DM) += platdevice.o
 else
 obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
-obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
 endif
 
 obj-y += boot-mode.o
diff --git a/arch/arm/mach-uniphier/ph1-pro4/early_pinctrl.c b/arch/arm/mach-uniphier/ph1-pro4/early_pinctrl.c
new file mode 100644
index 0000000..85bb6a0
--- /dev/null
+++ b/arch/arm/mach-uniphier/ph1-pro4/early_pinctrl.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2011-2015 Panasonic Corporation
+ * Copyright (C) 2015      Socionext Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <mach/sg-regs.h>
+
+void early_pin_init(void)
+{
+	/* Comment format:    PAD Name -> Function Name */
+
+#ifdef CONFIG_UNIPHIER_SERIAL
+	sg_set_pinsel(127, 0);	/* RXD0 -> RXD0 */
+	sg_set_pinsel(128, 0);	/* TXD0 -> TXD0 */
+	sg_set_pinsel(129, 0);	/* RXD1 -> RXD1 */
+	sg_set_pinsel(130, 0);	/* TXD1 -> TXD1 */
+	sg_set_pinsel(131, 0);	/* RXD2 -> RXD2 */
+	sg_set_pinsel(132, 0);	/* TXD2 -> TXD2 */
+	sg_set_pinsel(88, 2);	/* CH6CLK -> RXD3 */
+	sg_set_pinsel(89, 2);	/* CH6VAL -> TXD3 */
+#endif
+
+	writel(1, SG_LOADPINCTRL);
+}
diff --git a/arch/arm/mach-uniphier/ph1-pro4/pinctrl.c b/arch/arm/mach-uniphier/ph1-pro4/pinctrl.c
index f382ef4..4df9098e 100644
--- a/arch/arm/mach-uniphier/ph1-pro4/pinctrl.c
+++ b/arch/arm/mach-uniphier/ph1-pro4/pinctrl.c
@@ -1,10 +1,10 @@
 /*
- * Copyright (C) 2011-2014 Panasonic Corporation
+ * Copyright (C) 2011-2015 Panasonic Corporation
+ * Copyright (C) 2015      Socionext Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include <common.h>
 #include <asm/io.h>
 #include <mach/sg-regs.h>
 
@@ -12,17 +12,6 @@
 {
 	/* Comment format:    PAD Name -> Function Name */
 
-#ifdef CONFIG_UNIPHIER_SERIAL
-	sg_set_pinsel(127, 0);	/* RXD0 -> RXD0 */
-	sg_set_pinsel(128, 0);	/* TXD0 -> TXD0 */
-	sg_set_pinsel(129, 0);	/* RXD1 -> RXD1 */
-	sg_set_pinsel(130, 0);	/* TXD1 -> TXD1 */
-	sg_set_pinsel(131, 0);	/* RXD2 -> RXD2 */
-	sg_set_pinsel(132, 0);	/* TXD2 -> TXD2 */
-	sg_set_pinsel(88, 2);	/* CH6CLK -> RXD3 */
-	sg_set_pinsel(89, 2);	/* CH6VAL -> TXD3 */
-#endif
-
 #ifdef CONFIG_NAND_DENALI
 	sg_set_pinsel(40, 0);	/* NFD0   -> NFD0 */
 	sg_set_pinsel(41, 0);	/* NFD1   -> NFD1 */
diff --git a/arch/arm/mach-uniphier/ph1-sld8/Makefile b/arch/arm/mach-uniphier/ph1-sld8/Makefile
index 5ce3d8a..8eb575e 100644
--- a/arch/arm/mach-uniphier/ph1-sld8/Makefile
+++ b/arch/arm/mach-uniphier/ph1-sld8/Makefile
@@ -1,16 +1 @@
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
-obj-y += bcu_init.o sg_init.o pll_init.o early_clkrst_init.o \
-	pll_spectrum.o umc_init.o ddrphy_init.o
-obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
-obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
-else
-obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
-obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
-endif
-
-obj-y += boot-mode.o
+include $(src)/../ph1-ld4/Makefile
diff --git a/arch/arm/mach-uniphier/ph1-sld8/early_pinctrl.c b/arch/arm/mach-uniphier/ph1-sld8/early_pinctrl.c
new file mode 100644
index 0000000..28cc429
--- /dev/null
+++ b/arch/arm/mach-uniphier/ph1-sld8/early_pinctrl.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2011-2015 Panasonic Corporation
+ * Copyright (C) 2015      Socionext Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <mach/sg-regs.h>
+
+void early_pin_init(void)
+{
+	/* Comment format:    PAD Name -> Function Name */
+
+#ifdef CONFIG_UNIPHIER_SERIAL
+	sg_set_pinsel(70, 3);	/* HDDOUT0 -> TXD0 */
+	sg_set_pinsel(71, 3);	/* HSDOUT1 -> RXD0 */
+
+	sg_set_pinsel(114, 0);	/* TXD1 -> TXD1 */
+	sg_set_pinsel(115, 0);	/* RXD1 -> RXD1 */
+
+	sg_set_pinsel(112, 1);	/* SBO1 -> TXD2 */
+	sg_set_pinsel(113, 1);	/* SBI1 -> RXD2 */
+
+	sg_set_pinsel(110, 1);	/* SBO0 -> TXD3 */
+	sg_set_pinsel(111, 1);	/* SBI0 -> RXD3 */
+#endif
+}
diff --git a/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c b/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c
index 4c494ff..57a8093 100644
--- a/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c
+++ b/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c
@@ -1,10 +1,10 @@
 /*
- * Copyright (C) 2011-2014 Panasonic Corporation
+ * Copyright (C) 2011-2015 Panasonic Corporation
+ * Copyright (C) 2015      Socionext Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include <common.h>
 #include <asm/io.h>
 #include <mach/sg-regs.h>
 
@@ -12,20 +12,6 @@
 {
 	/* Comment format:    PAD Name -> Function Name */
 
-#ifdef CONFIG_UNIPHIER_SERIAL
-	sg_set_pinsel(70, 3);	/* HDDOUT0 -> TXD0 */
-	sg_set_pinsel(71, 3);	/* HSDOUT1 -> RXD0 */
-
-	sg_set_pinsel(114, 0);	/* TXD1 -> TXD1 */
-	sg_set_pinsel(115, 0);	/* RXD1 -> RXD1 */
-
-	sg_set_pinsel(112, 1);	/* SBO1 -> TXD2 */
-	sg_set_pinsel(113, 1);	/* SBI1 -> RXD2 */
-
-	sg_set_pinsel(110, 1);	/* SBO0 -> TXD3 */
-	sg_set_pinsel(111, 1);	/* SBI0 -> RXD3 */
-#endif
-
 #ifdef CONFIG_SYS_I2C_UNIPHIER
 	{
 		u32 tmp;
diff --git a/arch/arm/mach-uniphier/smp.S b/arch/arm/mach-uniphier/smp.S
deleted file mode 100644
index 18e3a9d..0000000
--- a/arch/arm/mach-uniphier/smp.S
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright (C) 2013 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-#include <linux/linkage.h>
-#include <asm/system.h>
-#include <mach/led.h>
-#include <mach/sbc-regs.h>
-
-/* Entry point of U-Boot main program for the secondary CPU */
-LENTRY(secondary_entry)
-	mrc	p15, 0, r0, c1, c0, 0	@ SCTLR (System Contrl Register)
-	bic	r0, r0, #(CR_C | CR_M)	@ MMU and Dcache disable
-	mcr	p15, 0, r0, c1, c0, 0
-	mcr	p15, 0, r0, c8, c7, 0	@ invalidate TLBs
-	mcr	p15, 0, r0, c7, c5, 0	@ invalidate icache
-	dsb
-	led_write(C,0,,)
-	ldr	r1, =ROM_BOOT_ROMRSV2
-	mov	r0, #0
-	str	r0, [r1]
-0:	wfe
-	ldr	r4, [r1]		@ r4: entry point for secondary CPUs
-	cmp	r4, #0
-	beq	0b
-	led_write(C, P, U, 1)
-	bx	r4			@ secondary CPUs jump to linux
-ENDPROC(secondary_entry)
-
-ENTRY(wakeup_secondary)
-	ldr	r1, =ROM_BOOT_ROMRSV2
-0:	ldr	r0, [r1]
-	cmp	r0, #0
-	bne	0b
-
-	/* set entry address and send event to the secondary CPU */
-	ldr	r0, =secondary_entry
-	str	r0, [r1]
-	ldr	r0, [r1]	@ make sure store is complete
-	mov	r0, #0x100
-0:	subs	r0, r0, #1	@ I don't know the reason, but without this wait
-	bne	0b		@ fails to wake up the secondary CPU
-	sev
-
-	/* wait until the secondary CPU reach to secondary_entry */
-0:	ldr	r0, [r1]
-	cmp	r0, #0
-	bne	0b
-	bx	lr
-ENDPROC(wakeup_secondary)
diff --git a/arch/arm/mach-uniphier/spl.c b/arch/arm/mach-uniphier/spl.c
index c3d90d0..a34d3a1 100644
--- a/arch/arm/mach-uniphier/spl.c
+++ b/arch/arm/mach-uniphier/spl.c
@@ -1,6 +1,7 @@
 /*
  * Copyright (C) 2013-2015 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2015      Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -20,6 +21,7 @@
 void pin_init(void);
 void memconf_init(void);
 void early_clkrst_init(void);
+void early_pin_init(void);
 int umc_init(void);
 void enable_dpll_ssc(void);
 
@@ -47,6 +49,16 @@
 
 	led_write(L, 2, , );
 
+	early_pin_init();
+
+	led_write(L, 3, , );
+
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+	preloader_console_init();
+#endif
+
+	led_write(L, 4, , );
+
 	{
 		int res;
 
@@ -56,9 +68,9 @@
 				;
 		}
 	}
-	led_write(L, 3, , );
+	led_write(L, 5, , );
 
 	enable_dpll_ssc();
 
-	led_write(L, 4, , );
+	led_write(L, 6, , );
 }
diff --git a/arch/arm/mach-uniphier/support_card.c b/arch/arm/mach-uniphier/support_card.c
index e7b4158..77cc794 100644
--- a/arch/arm/mach-uniphier/support_card.c
+++ b/arch/arm/mach-uniphier/support_card.c
@@ -1,6 +1,7 @@
 /*
- * Copyright (C) 2012-2014 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2012-2015 Panasonic Corporation
+ * Copyright (C) 2015      Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -94,7 +95,7 @@
 	/*
 	 * After power on, we need to keep the LAN controller in reset state
 	 * for a while. (200 usec)
-	 * Fortunatelly, enough wait time is already inserted in pll_init()
+	 * Fortunately, enough wait time is already inserted in pll_init()
 	 * function. So we do not have to wait here.
 	 */
 	support_card_reset_deassert();
@@ -213,11 +214,11 @@
 
 	debug("number of flash banks: %d\n", cfi_flash_num_flash_banks);
 }
-#else /* ONFIG_SYS_NO_FLASH */
+#else /* CONFIG_SYS_NO_FLASH */
 void detect_num_flash_banks(void)
 {
 };
-#endif /* ONFIG_SYS_NO_FLASH */
+#endif /* CONFIG_SYS_NO_FLASH */
 
 void support_card_late_init(void)
 {
diff --git a/arch/avr32/config.mk b/arch/avr32/config.mk
index 8252f59..469185e 100644
--- a/arch/avr32/config.mk
+++ b/arch/avr32/config.mk
@@ -9,9 +9,6 @@
 CROSS_COMPILE := avr32-linux-
 endif
 
-# avr32 has generic board support
-__HAVE_ARCH_GENERIC_BOARD := y
-
 CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000
 
 PLATFORM_RELFLAGS	+= -ffixed-r5 -fPIC -mno-init-got -mrelax
diff --git a/arch/blackfin/config.mk b/arch/blackfin/config.mk
index 584b38b..7b17b75 100644
--- a/arch/blackfin/config.mk
+++ b/arch/blackfin/config.mk
@@ -20,9 +20,6 @@
 endif
 CONFIG_BFIN_BOOT_MODE := $(strip $(CONFIG_BFIN_BOOT_MODE:"%"=%))
 
-# Support generic board on Blackfin
-__HAVE_ARCH_GENERIC_BOARD := y
-
 PLATFORM_RELFLAGS += -ffixed-P3 -fomit-frame-pointer -mno-fdpic
 
 LDFLAGS_FINAL += --gc-sections
diff --git a/arch/blackfin/include/asm/config.h b/arch/blackfin/include/asm/config.h
index 73cbfa2..d2cf71b 100644
--- a/arch/blackfin/include/asm/config.h
+++ b/arch/blackfin/include/asm/config.h
@@ -174,7 +174,6 @@
 	}
 #endif
 
-#define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_ARCH_MISC_INIT
 
diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
index 53c4aab..69cb0f7 100644
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -4,71 +4,200 @@
 config SYS_ARCH
 	default "m68k"
 
+# processor family
+config MCF520x
+	bool
+
+config MCF52x2
+	bool
+
+config MCF523x
+	bool
+
+config MCF530x
+	bool
+
+config MCF5301x
+	bool
+
+config MCF532x
+	bool
+
+config MCF537x
+	bool
+
+config MCF5441x
+	bool
+
+config MCF5445x
+	bool
+
+config MCF5227x
+	bool
+
+config MCF547x_8x
+	bool
+
+# processor type
+config M5208
+	bool
+	select MCF520x
+
+config M5235
+	bool
+	select MCF523x
+
+config M5249
+	bool
+	select MCF52x2
+
+config M5253
+	bool
+	select MCF52x2
+
+config M5271
+	bool
+	select MCF52x2
+
+config M5272
+	bool
+	select MCF52x2
+
+config M5275
+	bool
+	select MCF52x2
+
+config M5282
+	bool
+	select MCF52x2
+
+config M5307
+	bool
+	select MCF530x
+
+config M53015
+	bool
+	select MCF5301x
+
+config M5329
+	bool
+	select MCF532x
+
+config M5373
+	bool
+	select MCF532x
+	select MCF537x
+
+config M54418
+	bool
+	select MCF5441x
+
+config M54451
+	bool
+	select MCF5445x
+
+config M54455
+	bool
+	select MCF5445x
+
+config M52277
+	bool
+	select MCF5227x
+
+config M547x
+	bool
+	select MCF547x_8x
+
+config M548x
+	bool
+	select MCF547x_8x
+
 choice
 	prompt "Target select"
 
 config TARGET_M52277EVB
 	bool "Support M52277EVB"
+	select M52277
 
 config TARGET_M5235EVB
 	bool "Support M5235EVB"
+	select M5235
 
 config TARGET_COBRA5272
 	bool "Support cobra5272"
+	select M5272
 
 config TARGET_EB_CPU5282
 	bool "Support eb_cpu5282"
+	select M5282
 
 config TARGET_M5208EVBE
 	bool "Support M5208EVBE"
+	select M5208
 
 config TARGET_M5249EVB
 	bool "Support M5249EVB"
+	select M5249
 
 config TARGET_M5253DEMO
 	bool "Support M5253DEMO"
+	select M5253
 
 config TARGET_M5253EVBE
 	bool "Support M5253EVBE"
+	select M5253
 
 config TARGET_M5272C3
 	bool "Support M5272C3"
+	select M5272
 
 config TARGET_M5275EVB
 	bool "Support M5275EVB"
+	select M5275
 
 config TARGET_M5282EVB
 	bool "Support M5282EVB"
+	select M5282
 
 config TARGET_ASTRO_MCF5373L
 	bool "Support astro_mcf5373l"
+	select M5373
 
 config TARGET_M53017EVB
 	bool "Support M53017EVB"
+	select M53015
 
 config TARGET_M5329EVB
 	bool "Support M5329EVB"
+	select M5329
 
 config TARGET_M5373EVB
 	bool "Support M5373EVB"
+	select M5373
 
 config TARGET_M54418TWR
 	bool "Support M54418TWR"
+	select M54418
 
 config TARGET_M54451EVB
 	bool "Support M54451EVB"
+	select M54451
 
 config TARGET_M54455EVB
 	bool "Support M54455EVB"
+	select M54455
 
 config TARGET_M5475EVB
 	bool "Support M5475EVB"
+	select M547x
 
 config TARGET_M5485EVB
 	bool "Support M5485EVB"
+	select M548x
 
 config TARGET_AMCORE
 	bool "Support AMCORE"
+	select M5307
 
 endchoice
 
diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile
index aa3d2fa..e6f3b48 100644
--- a/arch/m68k/Makefile
+++ b/arch/m68k/Makefile
@@ -6,3 +6,32 @@
 
 libs-y += arch/m68k/cpu/$(CPU)/
 libs-y += arch/m68k/lib/
+
+cpuflags-$(CONFIG_M5208)	:= -mcpu=5208
+cpuflags-$(CONFIG_M5235)	:= -mcpu=5235 -fPIC
+cpuflags-$(CONFIG_M52277)	:= -mcpu=52277 -fPIC
+cpuflags-$(CONFIG_M5249)	:= -mcpu=5249
+cpuflags-$(CONFIG_M5253)	:= -mcpu=5253
+cpuflags-$(CONFIG_M5271)	:= -mcpu=5271
+cpuflags-$(CONFIG_M5272)	:= -mcpu=5272
+cpuflags-$(CONFIG_M5275)	:= -mcpu=5275
+cpuflags-$(CONFIG_M5282)	:= -mcpu=5282
+cpuflags-$(CONFIG_M5307)	:= -mcpu=5307
+cpuflags-$(CONFIG_MCF5301x)	:= -mcpu=53015 -fPIC
+cpuflags-$(CONFIG_MCF532x)	:= -mcpu=5329 -fPIC
+cpuflags-$(CONFIG_MCF5441x)	:= -mcpu=54418 -fPIC
+cpuflags-$(CONFIG_MCF5445x)	:= -mcpu=54455 -fPIC
+cpuflags-$(CONFIG_MCF547x_8x)	:= -mcpu=5485 -fPIC
+
+PLATFORM_CPPFLAGS += $(cpuflags-y)
+
+
+ldflags-$(CONFIG_MCF5441x)	:= --got=single
+ldflags-$(CONFIG_MCF5445x)	:= --got=single
+ldflags-$(CONFIG_MCF547x_8x)	:= --got=single
+
+ifneq (,$(findstring -linux-,$(shell $(CC) --version)))
+ifneq (,$(findstring GOT,$(shell $(LD) --help)))
+PLATFORM_LDFLAGS += $(ldflags-y)
+endif
+endif
diff --git a/arch/m68k/config.mk b/arch/m68k/config.mk
index a629b68..3b3a7e8 100644
--- a/arch/m68k/config.mk
+++ b/arch/m68k/config.mk
@@ -11,9 +11,6 @@
 
 CONFIG_STANDALONE_LOAD_ADDR ?= 0x20000
 
-# Support generic board on m68k
-__HAVE_ARCH_GENERIC_BOARD := y
-
 PLATFORM_CPPFLAGS += -D__M68K__
 PLATFORM_LDFLAGS  += -n
 PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
diff --git a/arch/m68k/cpu/mcf5227x/config.mk b/arch/m68k/cpu/mcf5227x/config.mk
deleted file mode 100644
index b5c26e4..0000000
--- a/arch/m68k/cpu/mcf5227x/config.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -mcpu=52277 -fPIC
diff --git a/arch/m68k/cpu/mcf523x/config.mk b/arch/m68k/cpu/mcf523x/config.mk
deleted file mode 100644
index c9435ab..0000000
--- a/arch/m68k/cpu/mcf523x/config.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -mcpu=5235 -fPIC
diff --git a/arch/m68k/cpu/mcf52x2/config.mk b/arch/m68k/cpu/mcf52x2/config.mk
deleted file mode 100644
index f66000b..0000000
--- a/arch/m68k/cpu/mcf52x2/config.mk
+++ /dev/null
@@ -1,39 +0,0 @@
-#
-# (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-cfg=$(srctree)/include/configs/$(CONFIG_SYS_CONFIG_NAME:"%"=%).h
-is5208:=$(shell grep CONFIG_M5208 $(cfg))
-is5249:=$(shell grep CONFIG_M5249 $(cfg))
-is5253:=$(shell grep CONFIG_M5253 $(cfg))
-is5271:=$(shell grep CONFIG_M5271 $(cfg))
-is5272:=$(shell grep CONFIG_M5272 $(cfg))
-is5275:=$(shell grep CONFIG_M5275 $(cfg))
-is5282:=$(shell grep CONFIG_M5282 $(cfg))
-
-ifneq (,$(findstring CONFIG_M5208,$(is5208)))
-PLATFORM_CPPFLAGS += -mcpu=5208
-endif
-ifneq (,$(findstring CONFIG_M5249,$(is5249)))
-PLATFORM_CPPFLAGS += -mcpu=5249
-endif
-ifneq (,$(findstring CONFIG_M5253,$(is5253)))
-PLATFORM_CPPFLAGS += -mcpu=5253
-endif
-ifneq (,$(findstring CONFIG_M5271,$(is5271)))
-PLATFORM_CPPFLAGS += -mcpu=5271
-endif
-ifneq (,$(findstring CONFIG_M5272,$(is5272)))
-PLATFORM_CPPFLAGS += -mcpu=5272
-endif
-ifneq (,$(findstring CONFIG_M5275,$(is5275)))
-PLATFORM_CPPFLAGS += -mcpu=5275
-endif
-ifneq (,$(findstring CONFIG_M5282,$(is5282)))
-PLATFORM_CPPFLAGS += -mcpu=5282
-endif
diff --git a/arch/m68k/cpu/mcf530x/config.mk b/arch/m68k/cpu/mcf530x/config.mk
deleted file mode 100644
index aef72d7..0000000
--- a/arch/m68k/cpu/mcf530x/config.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# (C) Copyright 2014  Angelo Dureghello <angelo@sysam.it>
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-cfg=$(srctree)/include/configs/$(CONFIG_SYS_CONFIG_NAME:"%"=%).h
-is5307:=$(shell grep CONFIG_M5307 $(cfg))
-
-ifneq (,$(findstring CONFIG_M5307,$(is5307)))
-PLATFORM_CPPFLAGS += -mcpu=5307
-endif
diff --git a/arch/m68k/cpu/mcf532x/config.mk b/arch/m68k/cpu/mcf532x/config.mk
deleted file mode 100644
index 2efb60f..0000000
--- a/arch/m68k/cpu/mcf532x/config.mk
+++ /dev/null
@@ -1,19 +0,0 @@
-#
-# (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-cfg=$(srctree)/include/configs/$(CONFIG_SYS_CONFIG_NAME:"%"=%).h
-is5301x:=$(shell grep CONFIG_MCF5301x $(cfg))
-is532x:=$(shell grep CONFIG_MCF532x $(cfg))
-
-ifneq (,$(findstring CONFIG_MCF5301x,$(is5301x)))
-PLATFORM_CPPFLAGS += -mcpu=53015 -fPIC
-endif
-ifneq (,$(findstring CONFIG_MCF532x,$(is532x)))
-PLATFORM_CPPFLAGS += -mcpu=5329 -fPIC
-endif
diff --git a/arch/m68k/cpu/mcf5445x/config.mk b/arch/m68k/cpu/mcf5445x/config.mk
deleted file mode 100644
index 13f8a9f..0000000
--- a/arch/m68k/cpu/mcf5445x/config.mk
+++ /dev/null
@@ -1,25 +0,0 @@
-#
-# (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright 2011-2012 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-cfg=$(srctree)/include/configs/$(CONFIG_SYS_CONFIG_NAME:"%"=%).h
-is5441x:=$(shell grep CONFIG_MCF5441x $(cfg))
-
-ifneq (,$(findstring CONFIG_MCF5441x,$(is5441x)))
-PLATFORM_CPPFLAGS += -mcpu=54418 -fPIC
-else
-PLATFORM_CPPFLAGS += -mcpu=54455 -fPIC
-endif
-
-ifneq (,$(findstring -linux-,$(shell $(CC) --version)))
-ifneq (,$(findstring GOT,$(shell $(LD) --help)))
-PLATFORM_LDFLAGS += --got=single
-endif
-endif
diff --git a/arch/m68k/cpu/mcf547x_8x/config.mk b/arch/m68k/cpu/mcf547x_8x/config.mk
deleted file mode 100644
index 825f6cc..0000000
--- a/arch/m68k/cpu/mcf547x_8x/config.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -mcpu=5485 -fPIC
-
-ifneq (,$(findstring -linux-,$(shell $(CC) --version)))
-ifneq (,$(findstring GOT,$(shell $(LD) --help)))
-PLATFORM_LDFLAGS += --got=single
-endif
-endif
diff --git a/arch/m68k/include/asm/config.h b/arch/m68k/include/asm/config.h
index 7590842..e1458ac 100644
--- a/arch/m68k/include/asm/config.h
+++ b/arch/m68k/include/asm/config.h
@@ -7,7 +7,6 @@
 #ifndef _ASM_CONFIG_H_
 #define _ASM_CONFIG_H_
 
-#define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_SYS_GENERIC_GLOBAL_DATA
 
 #define CONFIG_NEEDS_MANUAL_RELOC
diff --git a/arch/m68k/lib/Makefile b/arch/m68k/lib/Makefile
index d0e1a84..73d40bd 100644
--- a/arch/m68k/lib/Makefile
+++ b/arch/m68k/lib/Makefile
@@ -5,9 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-ifndef CONFIG_SYS_GENERIC_BOARD
-obj-y   += board.o
-endif
 obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-y	+= cache.o
 obj-y	+= interrupts.o
diff --git a/arch/m68k/lib/board.c b/arch/m68k/lib/board.c
deleted file mode 100644
index 9caff73..0000000
--- a/arch/m68k/lib/board.c
+++ /dev/null
@@ -1,642 +0,0 @@
-/*
- * (C) Copyright 2003
- * Josef Baumgartner <josef.baumgartner@telex.de>
- *
- * (C) Copyright 2000-2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <watchdog.h>
-#include <command.h>
-#include <malloc.h>
-#include <stdio_dev.h>
-#include <linux/compiler.h>
-
-#include <asm/immap.h>
-
-#if defined(CONFIG_CMD_IDE)
-#include <ide.h>
-#endif
-#if defined(CONFIG_CMD_SCSI)
-#include <scsi.h>
-#endif
-#if defined(CONFIG_CMD_KGDB)
-#include <kgdb.h>
-#endif
-#ifdef CONFIG_STATUS_LED
-#include <status_led.h>
-#endif
-#include <net.h>
-#include <serial.h>
-#ifdef CONFIG_SYS_ALLOC_DPRAM
-#include <commproc.h>
-#endif
-#include <version.h>
-
-#if defined(CONFIG_HARD_I2C) || \
-	defined(CONFIG_SYS_I2C)
-#include <i2c.h>
-#endif
-
-#ifdef CONFIG_CMD_SPI
-#include <spi.h>
-#endif
-
-#ifdef CONFIG_BITBANGMII
-#include <miiphy.h>
-#endif
-
-#include <nand.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static char *failed = "*** failed ***\n";
-
-#include <environment.h>
-
-extern ulong __init_end;
-extern ulong __bss_end;
-
-#if defined(CONFIG_WATCHDOG)
-# undef INIT_FUNC_WATCHDOG_INIT
-# define INIT_FUNC_WATCHDOG_INIT	watchdog_init,
-# define WATCHDOG_DISABLE		watchdog_disable
-
-extern int watchdog_init(void);
-extern int watchdog_disable(void);
-#else
-# define INIT_FUNC_WATCHDOG_INIT	/* undef */
-# define WATCHDOG_DISABLE		/* undef */
-#endif /* CONFIG_WATCHDOG */
-
-ulong monitor_flash_len;
-
-/************************************************************************
- * Utilities								*
- ************************************************************************
- */
-
-/*
- * All attempts to come up with a "common" initialization sequence
- * that works for all boards and architectures failed: some of the
- * requirements are just _too_ different. To get rid of the resulting
- * mess of board dependend #ifdef'ed code we now make the whole
- * initialization sequence configurable to the user.
- *
- * The requirements for any new initalization function is simple: it
- * receives a pointer to the "global data" structure as it's only
- * argument, and returns an integer return code, where 0 means
- * "continue" and != 0 means "fatal error, hang the system".
- */
-typedef int (init_fnc_t) (void);
-
-/************************************************************************
- * Init Utilities
- ************************************************************************
- * Some of this code should be moved into the core functions,
- * but let's get it working (again) first...
- */
-
-static int init_baudrate (void)
-{
-	gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
-	return 0;
-}
-
-/***********************************************************************/
-
-static int init_func_ram (void)
-{
-	int board_type = 0;	/* use dummy arg */
-	puts ("DRAM:  ");
-
-	if ((gd->ram_size = initdram (board_type)) > 0) {
-		print_size (gd->ram_size, "\n");
-		return (0);
-	}
-	puts (failed);
-	return (1);
-}
-
-/***********************************************************************/
-
-#if defined(CONFIG_HARD_I2C) ||	defined(CONFIG_SYS_I2C)
-static int init_func_i2c (void)
-{
-	puts ("I2C:   ");
-#ifdef CONFIG_SYS_I2C
-	i2c_init_all();
-#else
-	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-#endif
-	puts ("ready\n");
-	return (0);
-}
-#endif
-
-#if defined(CONFIG_HARD_SPI)
-static int init_func_spi (void)
-{
-	puts ("SPI:   ");
-	spi_init ();
-	puts ("ready\n");
-	return (0);
-}
-#endif
-
-/***********************************************************************/
-
-/************************************************************************
- * Initialization sequence						*
- ************************************************************************
- */
-
-init_fnc_t *init_sequence[] = {
-	get_clocks,
-	env_init,
-	init_baudrate,
-	serial_init,
-	console_init_f,
-	display_options,
-	checkcpu,
-	checkboard,
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
-	init_func_i2c,
-#endif
-#if defined(CONFIG_HARD_SPI)
-	init_func_spi,
-#endif
-	init_func_ram,
-#if defined(CONFIG_SYS_DRAM_TEST)
-	testdram,
-#endif /* CONFIG_SYS_DRAM_TEST */
-	INIT_FUNC_WATCHDOG_INIT
-	NULL,			/* Terminate this list */
-};
-
-
-/************************************************************************
- *
- * This is the first part of the initialization sequence that is
- * implemented in C, but still running from ROM.
- *
- * The main purpose is to provide a (serial) console interface as
- * soon as possible (so we can see any error messages), and to
- * initialize the RAM so that we can relocate the monitor code to
- * RAM.
- *
- * Be aware of the restrictions: global data is read-only, BSS is not
- * initialized, and stack space is limited to a few kB.
- *
- ************************************************************************
- */
-
-void
-board_init_f (ulong bootflag)
-{
-	bd_t *bd;
-	ulong len, addr, addr_sp;
-	ulong *paddr;
-	gd_t *id;
-	init_fnc_t **init_fnc_ptr;
-#ifdef CONFIG_PRAM
-	ulong reg;
-#endif
-
-	/* Pointer is writable since we allocated a register for it */
-	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
-	/* compiler optimization barrier needed for GCC >= 3.4 */
-	__asm__ __volatile__("": : :"memory");
-
-	/* Clear initial global data */
-	memset ((void *) gd, 0, sizeof (gd_t));
-
-	for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
-		if ((*init_fnc_ptr)() != 0) {
-			hang ();
-		}
-	}
-
-	/*
-	 * Now that we have DRAM mapped and working, we can
-	 * relocate the code and continue running from DRAM.
-	 *
-	 * Reserve memory at end of RAM for (top down in that order):
-	 *	- protected RAM
-	 *	- LCD framebuffer
-	 *	- monitor code
-	 *	- board info struct
-	 */
-	len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
-
-	addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size;
-
-#ifdef CONFIG_LOGBUFFER
-	/* reserve kernel log buffer */
-	addr -= (LOGBUFF_RESERVE);
-	debug ("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, addr);
-#endif
-
-#ifdef CONFIG_PRAM
-	/*
-	 * reserve protected RAM
-	 */
-	reg = getenv_ulong("pram", 10, CONFIG_PRAM);
-	addr -= (reg << 10);		/* size is in kB */
-	debug ("Reserving %ldk for protected RAM at %08lx\n", reg, addr);
-#endif /* CONFIG_PRAM */
-
-	/* round down to next 4 kB limit */
-	addr &= ~(4096 - 1);
-	debug ("Top of RAM usable for U-Boot at: %08lx\n", addr);
-
-#ifdef CONFIG_LCD
-#ifdef CONFIG_FB_ADDR
-	gd->fb_base = CONFIG_FB_ADDR;
-#else
-	/* reserve memory for LCD display (always full pages) */
-	addr = lcd_setmem (addr);
-	gd->fb_base = addr;
-#endif /* CONFIG_FB_ADDR */
-#endif /* CONFIG_LCD */
-
-	/*
-	 * reserve memory for U-Boot code, data & bss
-	 * round down to next 4 kB limit
-	 */
-	addr -= len;
-	addr &= ~(4096 - 1);
-
-	debug ("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr);
-
-	/*
-	 * reserve memory for malloc() arena
-	 */
-	addr_sp = addr - TOTAL_MALLOC_LEN;
-	debug ("Reserving %dk for malloc() at: %08lx\n",
-			TOTAL_MALLOC_LEN >> 10, addr_sp);
-
-	/*
-	 * (permanently) allocate a Board Info struct
-	 * and a permanent copy of the "global" data
-	 */
-	addr_sp -= sizeof (bd_t);
-	bd = (bd_t *) addr_sp;
-	gd->bd = bd;
-	debug ("Reserving %zu Bytes for Board Info at: %08lx\n",
-			sizeof (bd_t), addr_sp);
-	addr_sp -= sizeof (gd_t);
-	id = (gd_t *) addr_sp;
-	debug ("Reserving %zu Bytes for Global Data at: %08lx\n",
-			sizeof (gd_t), addr_sp);
-
-	/* Reserve memory for boot params. */
-	addr_sp -= CONFIG_SYS_BOOTPARAMS_LEN;
-	bd->bi_boot_params = addr_sp;
-	debug ("Reserving %dk for boot parameters at: %08lx\n",
-			CONFIG_SYS_BOOTPARAMS_LEN >> 10, addr_sp);
-
-	/*
-	 * Finally, we set up a new (bigger) stack.
-	 *
-	 * Leave some safety gap for SP, force alignment on 16 byte boundary
-	 * Clear initial stack frame
-	 */
-	addr_sp -= 16;
-	addr_sp &= ~0xF;
-
-	paddr = (ulong *)addr_sp;
-	*paddr-- = 0;
-	*paddr-- = 0;
-	addr_sp = (ulong)paddr;
-
-	debug ("Stack Pointer at: %08lx\n", addr_sp);
-
-	/*
-	 * Save local variables to board info struct
-	 */
-	bd->bi_memstart  = CONFIG_SYS_SDRAM_BASE;	/* start of  DRAM memory      */
-	bd->bi_memsize   = gd->ram_size;	/* size  of  DRAM memory in bytes */
-#ifdef CONFIG_SYS_INIT_RAM_ADDR
-	bd->bi_sramstart = CONFIG_SYS_INIT_RAM_ADDR;	/* start of  SRAM memory	*/
-	bd->bi_sramsize  = CONFIG_SYS_INIT_RAM_SIZE;	/* size  of  SRAM memory	*/
-#endif
-	bd->bi_mbar_base = CONFIG_SYS_MBAR;		/* base of internal registers */
-
-	bd->bi_bootflags = bootflag;		/* boot / reboot flag (for LynxOS)    */
-
-	WATCHDOG_RESET ();
-	bd->bi_intfreq = gd->cpu_clk;	/* Internal Freq, in Hz */
-	bd->bi_busfreq = gd->bus_clk;	/* Bus Freq,      in Hz */
-#ifdef CONFIG_PCI
-	bd->bi_pcifreq = gd->pci_clk;		/* PCI Freq in Hz */
-#endif
-#ifdef CONFIG_EXTRA_CLOCK
-	bd->bi_inpfreq = gd->arch.inp_clk;		/* input Freq in Hz */
-	bd->bi_vcofreq = gd->arch.vco_clk;		/* vco Freq in Hz */
-	bd->bi_flbfreq = gd->arch.flb_clk;		/* flexbus Freq in Hz */
-#endif
-
-#ifdef CONFIG_SYS_EXTBDINFO
-	strncpy (bd->bi_s_version, "1.2", sizeof (bd->bi_s_version));
-	strncpy (bd->bi_r_version, U_BOOT_VERSION, sizeof (bd->bi_r_version));
-#endif
-
-	WATCHDOG_RESET ();
-
-#ifdef CONFIG_POST
-	post_bootmode_init();
-	post_run (NULL, POST_ROM | post_bootmode_get(0));
-#endif
-
-	WATCHDOG_RESET();
-
-	memcpy (id, (void *)gd, sizeof (gd_t));
-
-	debug ("Start relocate of code from %08x to %08lx\n", CONFIG_SYS_MONITOR_BASE, addr);
-	relocate_code (addr_sp, id, addr);
-
-	/* NOTREACHED - jump_to_ram() does not return */
-}
-
-/************************************************************************
- *
- * This is the next part if the initialization sequence: we are now
- * running from RAM and have a "normal" C environment, i. e. global
- * data can be written, BSS has been cleared, the stack size in not
- * that critical any more, etc.
- *
- ************************************************************************
- */
-void board_init_r (gd_t *id, ulong dest_addr)
-{
-	char *s __maybe_unused;
-	bd_t *bd;
-
-#ifndef CONFIG_ENV_IS_NOWHERE
-	extern char * env_name_spec;
-#endif
-#ifndef CONFIG_SYS_NO_FLASH
-	ulong flash_size;
-#endif
-	gd = id;		/* initialize RAM version of global data */
-	bd = gd->bd;
-
-	gd->flags |= GD_FLG_RELOC;	/* tell others: relocation done */
-
-	WATCHDOG_RESET ();
-
-	gd->reloc_off =  dest_addr - CONFIG_SYS_MONITOR_BASE;
-
-	serial_initialize();
-
-	debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
-
-	monitor_flash_len = (ulong)&__init_end - dest_addr;
-
-#if defined(CONFIG_NEEDS_MANUAL_RELOC)
-	/*
-	 * We have to relocate the command table manually
-	 */
-	fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd),
-			ll_entry_count(cmd_tbl_t, cmd));
-#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
-
-	/* there are some other pointer constants we must deal with */
-#ifndef CONFIG_ENV_IS_NOWHERE
-	env_name_spec += gd->reloc_off;
-#endif
-
-	WATCHDOG_RESET ();
-
-#ifdef CONFIG_LOGBUFFER
-	logbuff_init_ptrs ();
-#endif
-#ifdef CONFIG_POST
-	post_output_backlog ();
-	post_reloc ();
-#endif
-	WATCHDOG_RESET();
-
-#if 0
-	/* instruction cache enabled in cpu_init_f() for faster relocation */
-	icache_enable ();	/* it's time to enable the instruction cache */
-#endif
-
-	/*
-	 * Setup trap handlers
-	 */
-	trap_init (CONFIG_SYS_SDRAM_BASE);
-
-	/* The Malloc area is immediately below the monitor copy in DRAM */
-	mem_malloc_init (CONFIG_SYS_MONITOR_BASE + gd->reloc_off -
-			TOTAL_MALLOC_LEN, TOTAL_MALLOC_LEN);
-
-#if !defined(CONFIG_SYS_NO_FLASH)
-	puts ("Flash: ");
-
-	if ((flash_size = flash_init ()) > 0) {
-# ifdef CONFIG_SYS_FLASH_CHECKSUM
-		print_size (flash_size, "");
-		/*
-		 * Compute and print flash CRC if flashchecksum is set to 'y'
-		 *
-		 * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
-		 */
-		if (getenv_yesno("flashchecksum") == 1) {
-			printf ("  CRC: %08X",
-					crc32 (0,
-						   (const unsigned char *) CONFIG_SYS_FLASH_BASE,
-						   flash_size)
-					);
-		}
-		putc ('\n');
-# else	/* !CONFIG_SYS_FLASH_CHECKSUM */
-		print_size (flash_size, "\n");
-# endif /* CONFIG_SYS_FLASH_CHECKSUM */
-	} else {
-		puts (failed);
-		hang ();
-	}
-
-	bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;	/* update start of FLASH memory    */
-	bd->bi_flashsize = flash_size;	/* size of FLASH memory (final value) */
-	bd->bi_flashoffset = 0;
-#else	/* CONFIG_SYS_NO_FLASH */
-	bd->bi_flashsize = 0;
-	bd->bi_flashstart = 0;
-	bd->bi_flashoffset = 0;
-#endif /* !CONFIG_SYS_NO_FLASH */
-
-	WATCHDOG_RESET ();
-
-	/* initialize higher level parts of CPU like time base and timers */
-	cpu_init_r ();
-
-	WATCHDOG_RESET ();
-
-#ifdef CONFIG_SPI
-# if !defined(CONFIG_ENV_IS_IN_EEPROM)
-	spi_init_f ();
-# endif
-	spi_init_r ();
-#endif
-
-#if defined(CONFIG_SYS_I2C)
-	/* Adjust I2C subsystem pointers after relocation */
-	i2c_reloc_fixup();
-#endif
-
-	/* relocate environment function pointers etc. */
-	env_relocate ();
-
-	WATCHDOG_RESET ();
-
-#if defined(CONFIG_PCI)
-	/*
-	 * Do pci configuration
-	 */
-	pci_init ();
-#endif
-
-	/** leave this here (after malloc(), environment and PCI are working) **/
-	/* Initialize stdio devices */
-	stdio_init ();
-
-	/* Initialize the jump table for applications */
-	jumptable_init ();
-
-	/* Initialize the console (after the relocation and devices init) */
-	console_init_r ();
-
-#if defined(CONFIG_MISC_INIT_R)
-	/* miscellaneous platform dependent initialisations */
-	misc_init_r ();
-#endif
-
-#if defined(CONFIG_CMD_KGDB)
-	WATCHDOG_RESET ();
-	puts ("KGDB:  ");
-	kgdb_init ();
-#endif
-
-	debug ("U-Boot relocated to %08lx\n", dest_addr);
-
-	/*
-	 * Enable Interrupts
-	 */
-	interrupt_init ();
-
-	/* Must happen after interrupts are initialized since
-	 * an irq handler gets installed
-	 */
-	timer_init();
-
-#ifdef CONFIG_STATUS_LED
-	status_led_set (STATUS_LED_BOOT, STATUS_LED_BLINKING);
-#endif
-
-	udelay (20);
-
-	/* Insert function pointers now that we have relocated the code */
-
-	/* Initialize from environment */
-	load_addr = getenv_ulong("loadaddr", 16, load_addr);
-
-	WATCHDOG_RESET ();
-
-#if defined(CONFIG_CMD_DOC)
-	WATCHDOG_RESET ();
-	puts ("DOC:   ");
-	doc_init ();
-#endif
-
-#if defined(CONFIG_CMD_NAND)
-	WATCHDOG_RESET ();
-	puts ("NAND:  ");
-	nand_init();		/* go init the NAND */
-#endif
-
-#ifdef CONFIG_BITBANGMII
-	bb_miiphy_init();
-#endif
-#if defined(CONFIG_CMD_NET)
-	WATCHDOG_RESET();
-#if defined(FEC_ENET)
-	eth_init(bd);
-#endif
-	puts ("Net:   ");
-	eth_initialize (bd);
-#endif
-
-#ifdef CONFIG_POST
-	post_run (NULL, POST_RAM | post_bootmode_get(0));
-#endif
-
-#if defined(CONFIG_CMD_PCMCIA) \
-    && !defined(CONFIG_CMD_IDE)
-	WATCHDOG_RESET ();
-	puts ("PCMCIA:");
-	pcmcia_init ();
-#endif
-
-#if defined(CONFIG_CMD_IDE)
-	WATCHDOG_RESET ();
-	puts ("IDE:   ");
-	ide_init ();
-#endif
-
-#ifdef CONFIG_LAST_STAGE_INIT
-	WATCHDOG_RESET ();
-	/*
-	 * Some parts can be only initialized if all others (like
-	 * Interrupts) are up and running (i.e. the PC-style ISA
-	 * keyboard).
-	 */
-	last_stage_init ();
-#endif
-
-#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER)
-	/*
-	 * Export available size of memory for Linux,
-	 * taking into account the protected RAM at top of memory
-	 */
-	{
-		ulong pram = 0;
-		char memsz[32];
-
-#ifdef CONFIG_PRAM
-		pram = getenv_ulong("pram", 10, CONFIG_PRAM);
-#endif
-#ifdef CONFIG_LOGBUFFER
-		/* Also take the logbuffer into account (pram is in kB) */
-		pram += (LOGBUFF_LEN+LOGBUFF_OVERHEAD)/1024;
-#endif
-		sprintf (memsz, "%ldk", (bd->bi_memsize / 1024) - pram);
-		setenv ("mem", memsz);
-	}
-#endif
-
-#ifdef CONFIG_WATCHDOG
-	/* disable watchdog if environment is set */
-	if ((s = getenv ("watchdog")) != NULL) {
-		if (strncmp (s, "off", 3) == 0) {
-			WATCHDOG_DISABLE ();
-		}
-	}
-#endif /* CONFIG_WATCHDOG*/
-
-
-	/* Initialization complete - start the monitor */
-
-	/* main_loop() can return to retry autoboot, if so just run it again. */
-	for (;;) {
-		WATCHDOG_RESET ();
-		main_loop ();
-	}
-
-	/* NOTREACHED - no way out of command loop except booting */
-}
diff --git a/arch/microblaze/config.mk b/arch/microblaze/config.mk
index 2b817be..e7a3477 100644
--- a/arch/microblaze/config.mk
+++ b/arch/microblaze/config.mk
@@ -19,4 +19,3 @@
 ifeq ($(CONFIG_SPL_BUILD),)
 PLATFORM_CPPFLAGS += -fPIC
 endif
-__HAVE_ARCH_GENERIC_BOARD := y
diff --git a/arch/microblaze/cpu/spl.c b/arch/microblaze/cpu/spl.c
index 2cc0a2d..f4bb091 100644
--- a/arch/microblaze/cpu/spl.c
+++ b/arch/microblaze/cpu/spl.c
@@ -9,7 +9,6 @@
 #include <common.h>
 #include <image.h>
 #include <spl.h>
-#include <version.h>
 #include <asm/io.h>
 #include <asm/u-boot.h>
 
diff --git a/arch/microblaze/include/asm/config.h b/arch/microblaze/include/asm/config.h
index 32fd636..4af408a 100644
--- a/arch/microblaze/include/asm/config.h
+++ b/arch/microblaze/include/asm/config.h
@@ -12,6 +12,5 @@
 #endif
 
 #define CONFIG_NR_DRAM_BANKS	1
-#define CONFIG_SYS_GENERIC_BOARD
 
 #endif
diff --git a/arch/mips/config.mk b/arch/mips/config.mk
index 4dc88f4..52e28f2 100644
--- a/arch/mips/config.mk
+++ b/arch/mips/config.mk
@@ -43,8 +43,6 @@
 
 PLATFORM_CPPFLAGS += -D__MIPS__
 
-__HAVE_ARCH_GENERIC_BOARD := y
-
 #
 # From Linux arch/mips/Makefile
 #
diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S
index 34db79d..0d96c52 100644
--- a/arch/nds32/cpu/n1213/start.S
+++ b/arch/nds32/cpu/n1213/start.S
@@ -13,7 +13,6 @@
 #include <config.h>
 #include <common.h>
 #include <asm/macro.h>
-#include <version.h>
 
 /*
  * Jump vector table for EVIC mode
diff --git a/arch/nios2/config.mk b/arch/nios2/config.mk
index 9b7c56d..82bd887 100644
--- a/arch/nios2/config.mk
+++ b/arch/nios2/config.mk
@@ -17,5 +17,3 @@
 
 LDFLAGS_FINAL += --gc-sections
 PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
-
-__HAVE_ARCH_GENERIC_BOARD := y
diff --git a/arch/nios2/include/asm/config.h b/arch/nios2/include/asm/config.h
index 476a32b..9c13848 100644
--- a/arch/nios2/include/asm/config.h
+++ b/arch/nios2/include/asm/config.h
@@ -7,7 +7,6 @@
 #ifndef _ASM_CONFIG_H_
 #define _ASM_CONFIG_H_
 
-#define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_SYS_GENERIC_GLOBAL_DATA
 
 #endif
diff --git a/arch/powerpc/config.mk b/arch/powerpc/config.mk
index fec02f2..83b49b5 100644
--- a/arch/powerpc/config.mk
+++ b/arch/powerpc/config.mk
@@ -12,13 +12,11 @@
 CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000
 LDFLAGS_FINAL += --gc-sections
 LDFLAGS_FINAL += --bss-plt
-PLATFORM_RELFLAGS += -fpic -mrelocatable -ffunction-sections -fdata-sections \
-								-meabi
-PLATFORM_CPPFLAGS += -D__powerpc__ -ffixed-r2
-PLATFORM_LDFLAGS  += -n
+PLATFORM_RELFLAGS += -fpic -mrelocatable -ffunction-sections \
+-fdata-sections -mcall-linux
 
-# Support generic board on PPC
-__HAVE_ARCH_GENERIC_BOARD := y
+PLATFORM_CPPFLAGS += -D__powerpc__ -ffixed-r2 -m32
+PLATFORM_LDFLAGS  += -m32 -melf32ppclinux
 
 #
 # When cross-compiling on NetBSD, we have to define __PPC__ or else we
diff --git a/arch/powerpc/cpu/mpc8260/kgdb.S b/arch/powerpc/cpu/mpc8260/kgdb.S
index 1432344..bc9c628 100644
--- a/arch/powerpc/cpu/mpc8260/kgdb.S
+++ b/arch/powerpc/cpu/mpc8260/kgdb.S
@@ -7,7 +7,6 @@
 #include <config.h>
 #include <command.h>
 #include <mpc8260.h>
-#include <version.h>
 
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S
index a2c0ad4..0e0daf5 100644
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -8,7 +8,6 @@
 #include <asm-offsets.h>
 #include <config.h>
 #include <mpc85xx.h>
-#include <version.h>
 
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
diff --git a/arch/powerpc/cpu/mpc86xx/cache.S b/arch/powerpc/cpu/mpc86xx/cache.S
index 0bb058b..536d9b9 100644
--- a/arch/powerpc/cpu/mpc86xx/cache.S
+++ b/arch/powerpc/cpu/mpc86xx/cache.S
@@ -1,6 +1,5 @@
 #include <config.h>
 #include <mpc86xx.h>
-#include <version.h>
 
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
diff --git a/arch/powerpc/cpu/mpc86xx/release.S b/arch/powerpc/cpu/mpc86xx/release.S
index 461f6ec..3977049 100644
--- a/arch/powerpc/cpu/mpc86xx/release.S
+++ b/arch/powerpc/cpu/mpc86xx/release.S
@@ -6,7 +6,6 @@
  */
 #include <config.h>
 #include <mpc86xx.h>
-#include <version.h>
 
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
diff --git a/arch/powerpc/cpu/mpc8xx/kgdb.S b/arch/powerpc/cpu/mpc8xx/kgdb.S
index e774d1e..0ea1a06 100644
--- a/arch/powerpc/cpu/mpc8xx/kgdb.S
+++ b/arch/powerpc/cpu/mpc8xx/kgdb.S
@@ -7,7 +7,6 @@
 #include <config.h>
 #include <command.h>
 #include <mpc8xx.h>
-#include <version.h>
 
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
diff --git a/arch/powerpc/cpu/ppc4xx/kgdb.S b/arch/powerpc/cpu/ppc4xx/kgdb.S
index f274c5d..31abd69 100644
--- a/arch/powerpc/cpu/ppc4xx/kgdb.S
+++ b/arch/powerpc/cpu/ppc4xx/kgdb.S
@@ -7,7 +7,6 @@
 #include <config.h>
 #include <command.h>
 #include <asm/ppc4xx.h>
-#include <version.h>
 
 #define CONFIG_405GP 1		/* needed for Linux kernel header files */
 
diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk
index 7b84f02..b05a90f 100644
--- a/arch/sandbox/config.mk
+++ b/arch/sandbox/config.mk
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 
 PLATFORM_CPPFLAGS += -D__SANDBOX__ -U_FORTIFY_SOURCE
-PLATFORM_CPPFLAGS += -DCONFIG_ARCH_MAP_SYSMEM -DCONFIG_SYS_GENERIC_BOARD
+PLATFORM_CPPFLAGS += -DCONFIG_ARCH_MAP_SYSMEM
 PLATFORM_LIBS += -lrt
 
 # Define this to avoid linking with SDL, which requires SDL libraries
@@ -16,9 +16,6 @@
 endif
 endif
 
-# Support generic board on sandbox
-__HAVE_ARCH_GENERIC_BOARD := y
-
 cmd_u-boot__ = $(CC) -o $@ -T u-boot.lds \
 	-Wl,--start-group $(u-boot-main) -Wl,--end-group \
 	$(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map
diff --git a/arch/sh/cpu/sh2/start.S b/arch/sh/cpu/sh2/start.S
index 5b92a01..ebf731a 100644
--- a/arch/sh/cpu/sh2/start.S
+++ b/arch/sh/cpu/sh2/start.S
@@ -7,7 +7,6 @@
 
 #include <asm-offsets.h>
 #include <config.h>
-#include <version.h>
 
 	.text
 	.align	2
diff --git a/arch/sh/cpu/sh3/start.S b/arch/sh/cpu/sh3/start.S
index c26a0b6..7a934e2 100644
--- a/arch/sh/cpu/sh3/start.S
+++ b/arch/sh/cpu/sh3/start.S
@@ -10,7 +10,6 @@
 
 #include <asm-offsets.h>
 #include <config.h>
-#include <version.h>
 
 	.text
 	.align	2
diff --git a/arch/sh/cpu/sh4/start.S b/arch/sh/cpu/sh4/start.S
index 238aa43..21644b5 100644
--- a/arch/sh/cpu/sh4/start.S
+++ b/arch/sh/cpu/sh4/start.S
@@ -7,7 +7,6 @@
 
 #include <asm-offsets.h>
 #include <config.h>
-#include <version.h>
 
 	.text
 	.align	2
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 35d24e4..da27115 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -76,9 +76,6 @@
 config DM_SERIAL
 	default y
 
-config SYS_MALLOC_F
-	default y
-
 config SYS_MALLOC_F_LEN
 	default 0x800
 
diff --git a/arch/x86/config.mk b/arch/x86/config.mk
index bb2da46..999143e 100644
--- a/arch/x86/config.mk
+++ b/arch/x86/config.mk
@@ -17,9 +17,6 @@
 PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm
 PLATFORM_CPPFLAGS += -march=i386 -m32
 
-# Support generic board on x86
-__HAVE_ARCH_GENERIC_BOARD := y
-
 PLATFORM_RELFLAGS += -ffunction-sections -fvisibility=hidden
 
 PLATFORM_LDFLAGS += --emit-relocs -Bsymbolic -Bsymbolic-functions -m elf_i386
diff --git a/arch/x86/cpu/quark/hte.c b/arch/x86/cpu/quark/hte.c
index 372815d..db601e4 100644
--- a/arch/x86/cpu/quark/hte.c
+++ b/arch/x86/cpu/quark/hte.c
@@ -20,9 +20,9 @@
  */
 static void hte_enable_all_errors(void)
 {
-	msg_port_write(HTE, 0x000200A2, 0xFFFFFFFF);
-	msg_port_write(HTE, 0x000200A3, 0x000000FF);
-	msg_port_write(HTE, 0x000200A4, 0x00000000);
+	msg_port_write(HTE, 0x000200a2, 0xffffffff);
+	msg_port_write(HTE, 0x000200a3, 0x000000ff);
+	msg_port_write(HTE, 0x000200a4, 0x00000000);
 }
 
 /**
@@ -32,7 +32,7 @@
  */
 static u32 hte_check_errors(void)
 {
-	return msg_port_read(HTE, 0x000200A7);
+	return msg_port_read(HTE, 0x000200a7);
 }
 
 /**
@@ -44,11 +44,11 @@
 
 	ENTERFN();
 
-	do {} while ((msg_port_read(HTE, 0x00020012) & BIT30) != 0);
+	do {} while ((msg_port_read(HTE, 0x00020012) & (1 << 30)) != 0);
 
 	tmp = msg_port_read(HTE, 0x00020011);
-	tmp |= BIT9;
-	tmp &= ~(BIT12 | BIT13);
+	tmp |= (1 << 9);
+	tmp &= ~((1 << 12) | (1 << 13));
 	msg_port_write(HTE, 0x00020011, tmp);
 
 	LEAVEFN();
@@ -65,9 +65,9 @@
 	 * Clear all HTE errors and enable error checking
 	 * for burst and chunk.
 	 */
-	tmp = msg_port_read(HTE, 0x000200A1);
-	tmp |= BIT8;
-	msg_port_write(HTE, 0x000200A1, tmp);
+	tmp = msg_port_read(HTE, 0x000200a1);
+	tmp |= (1 << 8);
+	msg_port_write(HTE, 0x000200a1, tmp);
 }
 
 /**
@@ -91,25 +91,25 @@
 	u32 offset;
 
 	if (first_run) {
-		msg_port_write(HTE, 0x00020020, 0x01B10021);
+		msg_port_write(HTE, 0x00020020, 0x01b10021);
 		msg_port_write(HTE, 0x00020021, 0x06000000);
 		msg_port_write(HTE, 0x00020022, addr >> 6);
 		msg_port_write(HTE, 0x00020062, 0x00800015);
-		msg_port_write(HTE, 0x00020063, 0xAAAAAAAA);
-		msg_port_write(HTE, 0x00020064, 0xCCCCCCCC);
-		msg_port_write(HTE, 0x00020065, 0xF0F0F0F0);
+		msg_port_write(HTE, 0x00020063, 0xaaaaaaaa);
+		msg_port_write(HTE, 0x00020064, 0xcccccccc);
+		msg_port_write(HTE, 0x00020065, 0xf0f0f0f0);
 		msg_port_write(HTE, 0x00020061, 0x00030008);
 
 		if (mode == WRITE_TRAIN)
-			pattern = 0xC33C0000;
+			pattern = 0xc33c0000;
 		else /* READ_TRAIN */
-			pattern = 0xAA5555AA;
+			pattern = 0xaa5555aa;
 
-		for (offset = 0x80; offset <= 0x8F; offset++)
+		for (offset = 0x80; offset <= 0x8f; offset++)
 			msg_port_write(HTE, offset, pattern);
 	}
 
-	msg_port_write(HTE, 0x000200A1, 0xFFFF1000);
+	msg_port_write(HTE, 0x000200a1, 0xffff1000);
 	msg_port_write(HTE, 0x00020011, 0x00011000);
 	msg_port_write(HTE, 0x00020011, 0x00011100);
 
@@ -119,7 +119,7 @@
 	 * Return bits 15:8 of HTE_CH0_ERR_XSTAT to check for
 	 * any bytelane errors.
 	 */
-	return (hte_check_errors() >> 8) & 0xFF;
+	return (hte_check_errors() >> 8) & 0xff;
 }
 
 /**
@@ -153,7 +153,7 @@
 		msg_port_write(HTE, 0x00020024, 0x06070000);
 		msg_port_write(HTE, 0x00020022, addr >> 6);
 		msg_port_write(HTE, 0x00020025, addr >> 6);
-		msg_port_write(HTE, 0x00020062, 0x0000002A);
+		msg_port_write(HTE, 0x00020062, 0x0000002a);
 		msg_port_write(HTE, 0x00020063, seed_victim);
 		msg_port_write(HTE, 0x00020064, seed_aggressor);
 		msg_port_write(HTE, 0x00020065, seed_victim);
@@ -163,21 +163,21 @@
 		 *
 		 * Start with bit0
 		 */
-		for (offset = 0x80; offset <= 0x8F; offset++) {
+		for (offset = 0x80; offset <= 0x8f; offset++) {
 			if ((offset % 8) == victim_bit)
 				msg_port_write(HTE, offset, 0x55555555);
 			else
-				msg_port_write(HTE, offset, 0xCCCCCCCC);
+				msg_port_write(HTE, offset, 0xcccccccc);
 		}
 
 		msg_port_write(HTE, 0x00020061, 0x00000000);
 		msg_port_write(HTE, 0x00020066, 0x03440000);
-		msg_port_write(HTE, 0x000200A1, 0xFFFF1000);
+		msg_port_write(HTE, 0x000200a1, 0xffff1000);
 	}
 
 	tmp = 0x10001000 | (loop_cnt << 16);
 	msg_port_write(HTE, 0x00020011, tmp);
-	msg_port_write(HTE, 0x00020011, tmp | BIT8);
+	msg_port_write(HTE, 0x00020011, tmp | (1 << 8));
 
 	hte_wait_for_complete();
 
@@ -185,7 +185,7 @@
 	 * Return bits 15:8 of HTE_CH0_ERR_XSTAT to check for
 	 * any bytelane errors.
 	 */
-	return (hte_check_errors() >> 8) & 0xFF;
+	return (hte_check_errors() >> 8) & 0xff;
 }
 
 /**
@@ -219,14 +219,14 @@
 
 	msg_port_write(HTE, 0x00020062, 0x00000015);
 
-	for (offset = 0x80; offset <= 0x8F; offset++)
-		msg_port_write(HTE, offset, ((offset & 1) ? 0xA55A : 0x5AA5));
+	for (offset = 0x80; offset <= 0x8f; offset++)
+		msg_port_write(HTE, offset, ((offset & 1) ? 0xa55a : 0x5aa5));
 
 	msg_port_write(HTE, 0x00020021, 0x00000000);
 	msg_port_write(HTE, 0x00020022, (mrc_params->mem_size >> 6) - 1);
-	msg_port_write(HTE, 0x00020063, 0xAAAAAAAA);
-	msg_port_write(HTE, 0x00020064, 0xCCCCCCCC);
-	msg_port_write(HTE, 0x00020065, 0xF0F0F0F0);
+	msg_port_write(HTE, 0x00020063, 0xaaaaaaaa);
+	msg_port_write(HTE, 0x00020064, 0xcccccccc);
+	msg_port_write(HTE, 0x00020065, 0xf0f0f0f0);
 	msg_port_write(HTE, 0x00020066, 0x03000000);
 
 	switch (flag) {
@@ -243,7 +243,7 @@
 		break;
 	default:
 		DPF(D_INFO, "Unknown parameter for flag: %d\n", flag);
-		return 0xFFFFFFFF;
+		return 0xffffffff;
 	}
 
 	DPF(D_INFO, "hte_mem_init");
@@ -379,16 +379,16 @@
 		msg_port_write(HTE, 0x00020021, 0x06000000);
 		msg_port_write(HTE, 0x00020022, addr >> 6);
 		msg_port_write(HTE, 0x00020062, 0x00800015);
-		msg_port_write(HTE, 0x00020063, 0xAAAAAAAA);
-		msg_port_write(HTE, 0x00020064, 0xCCCCCCCC);
-		msg_port_write(HTE, 0x00020065, 0xF0F0F0F0);
+		msg_port_write(HTE, 0x00020063, 0xaaaaaaaa);
+		msg_port_write(HTE, 0x00020064, 0xcccccccc);
+		msg_port_write(HTE, 0x00020065, 0xf0f0f0f0);
 		msg_port_write(HTE, 0x00020061, 0x00030008);
 
-		for (offset = 0x80; offset <= 0x8F; offset++)
-			msg_port_write(HTE, offset, 0xC33C0000);
+		for (offset = 0x80; offset <= 0x8f; offset++)
+			msg_port_write(HTE, offset, 0xc33c0000);
 	}
 
-	msg_port_write(HTE, 0x000200A1, 0xFFFF1000);
+	msg_port_write(HTE, 0x000200a1, 0xffff1000);
 	msg_port_write(HTE, 0x00020011, 0x00011000);
 	msg_port_write(HTE, 0x00020011, 0x00011100);
 
diff --git a/arch/x86/cpu/quark/hte.h b/arch/x86/cpu/quark/hte.h
index 6577796..e98c7ef 100644
--- a/arch/x86/cpu/quark/hte.h
+++ b/arch/x86/cpu/quark/hte.h
@@ -29,10 +29,10 @@
 #define HTE_LOOP_CNT		5
 
 /* random seed for victim */
-#define HTE_LFSR_VICTIM_SEED	0xF294BA21
+#define HTE_LFSR_VICTIM_SEED	0xf294ba21
 
 /* random seed for aggressor */
-#define HTE_LFSR_AGRESSOR_SEED	0xEBA7492D
+#define HTE_LFSR_AGRESSOR_SEED	0xeba7492d
 
 u32 hte_mem_init(struct mrc_params *mrc_params, u8 flag);
 u16 hte_basic_write_read(struct mrc_params *mrc_params, u32 addr,
diff --git a/arch/x86/cpu/quark/mrc.c b/arch/x86/cpu/quark/mrc.c
index 7eb34c5..6e774cb 100644
--- a/arch/x86/cpu/quark/mrc.c
+++ b/arch/x86/cpu/quark/mrc.c
@@ -34,6 +34,7 @@
  */
 
 #include <common.h>
+#include <version.h>
 #include <asm/arch/mrc.h>
 #include <asm/arch/msg_port.h>
 #include "mrc_util.h"
@@ -105,8 +106,8 @@
 	 * Column: 11 for 8Gbx8, else 10
 	 */
 	mrc_params->column_bits[0] =
-		((dram_params[0].density == 4) &&
-		(dram_width == X8)) ? (11) : (10);
+		(dram_params[0].density == 4) &&
+		(dram_width == X8) ? 11 : 10;
 
 	/*
 	 * Determine row bits:
@@ -117,9 +118,9 @@
 	 * 4Gbx16=15   4Gbx8=16
 	 * 8Gbx16=16   8Gbx8=16
 	 */
-	mrc_params->row_bits[0] = 12 + (dram_params[0].density) +
-		(((dram_params[0].density < 4) &&
-		(dram_width == X8)) ? (1) : (0));
+	mrc_params->row_bits[0] = 12 + dram_params[0].density +
+		(dram_params[0].density < 4) &&
+		(dram_width == X8) ? 1 : 0;
 
 	/*
 	 * Determine per-channel memory size:
@@ -137,7 +138,7 @@
 	 * 4Gb     x16   0x040000000 (1024MB)
 	 * 4Gb     x8    0x080000000 (2048MB)
 	 */
-	mrc_params->channel_size[0] = (1 << dram_params[0].density);
+	mrc_params->channel_size[0] = 1 << dram_params[0].density;
 	mrc_params->channel_size[0] *= (dram_width == X8) ? 2 : 1;
 	mrc_params->channel_size[0] *= (rank_enables == 0x3) ? 2 : 1;
 	mrc_params->channel_size[0] *= (channel_width == X16) ? 1 : 2;
@@ -192,7 +193,7 @@
 	ENTERFN();
 
 	DPF(D_INFO, "MRC Version %04x %s %s\n", MRC_VERSION,
-	    __DATE__, __TIME__);
+	    U_BOOT_DATE, U_BOOT_TIME);
 
 	/* Set up the data structures used by mrc_mem_init() */
 	mrc_adjust_params(mrc_params);
diff --git a/arch/x86/cpu/quark/mrc_util.c b/arch/x86/cpu/quark/mrc_util.c
index 3a79ae5..49d803d 100644
--- a/arch/x86/cpu/quark/mrc_util.c
+++ b/arch/x86/cpu/quark/mrc_util.c
@@ -18,14 +18,14 @@
 
 static const uint8_t vref_codes[64] = {
 	/* lowest to highest */
-	0x3F, 0x3E, 0x3D, 0x3C, 0x3B, 0x3A, 0x39, 0x38,
+	0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a, 0x39, 0x38,
 	0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30,
-	0x2F, 0x2E, 0x2D, 0x2C, 0x2B, 0x2A, 0x29, 0x28,
+	0x2f, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28,
 	0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x20,
 	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
-	0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
+	0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
 	0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
-	0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F
+	0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f
 };
 
 void mrc_write_mask(u32 unit, u32 addr, u32 data, u32 mask)
@@ -80,7 +80,7 @@
 	ENTERFN();
 
 	dco = msg_port_read(MEM_CTLR, DCO);
-	dco &= ~BIT28;
+	dco &= ~DCO_PMICTL;
 	msg_port_write(MEM_CTLR, DCO, dco);
 
 	LEAVEFN();
@@ -94,7 +94,7 @@
 	ENTERFN();
 
 	dco = msg_port_read(MEM_CTLR, DCO);
-	dco |= BIT28;
+	dco |= DCO_PMICTL;
 	msg_port_write(MEM_CTLR, DCO, dco);
 
 	LEAVEFN();
@@ -151,26 +151,25 @@
 	 * BL0 -> B01PTRCTL0[11:08] (0x0-0xF)
 	 * BL1 -> B01PTRCTL0[23:20] (0x0-0xF)
 	 */
-	reg = B01PTRCTL0 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
-		(channel * DDRIODQ_CH_OFFSET);
-	msk = (byte_lane & BIT0) ? (BIT23 | BIT22 | BIT21 | BIT20) :
-		(BIT11 | BIT10 | BIT9 | BIT8);
-	temp = (byte_lane & BIT0) ? ((pi_count / HALF_CLK) << 20) :
-		((pi_count / HALF_CLK) << 8);
+	reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET +
+		channel * DDRIODQ_CH_OFFSET;
+	msk = (byte_lane & 1) ? 0xf00000 : 0xf00;
+	temp = (byte_lane & 1) ? (pi_count / HALF_CLK) << 20 :
+		(pi_count / HALF_CLK) << 8;
 	mrc_alt_write_mask(DDRPHY, reg, temp, msk);
 
 	/* Adjust PI_COUNT */
-	pi_count -= ((pi_count / HALF_CLK) & 0xF) * HALF_CLK;
+	pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK;
 
 	/*
 	 * PI (1/64 MCLK, 1 PIs)
 	 * BL0 -> B0DLLPICODER0[29:24] (0x00-0x3F)
 	 * BL1 -> B1DLLPICODER0[29:24] (0x00-0x3F)
 	 */
-	reg = (byte_lane & BIT0) ? B1DLLPICODER0 : B0DLLPICODER0;
-	reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
-		(channel * DDRIODQ_CH_OFFSET));
-	msk = (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24);
+	reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0;
+	reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET +
+		channel * DDRIODQ_CH_OFFSET);
+	msk = 0x3f000000;
 	temp = pi_count << 24;
 	mrc_alt_write_mask(DDRPHY, reg, temp, msk);
 
@@ -179,25 +178,25 @@
 	 * BL0/1 -> B01DBCTL1[08/11] (+1 select)
 	 * BL0/1 -> B01DBCTL1[02/05] (enable)
 	 */
-	reg = B01DBCTL1 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
-		(channel * DDRIODQ_CH_OFFSET);
+	reg = B01DBCTL1 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET +
+		channel * DDRIODQ_CH_OFFSET;
 	msk = 0x00;
 	temp = 0x00;
 
 	/* enable */
-	msk |= (byte_lane & BIT0) ? BIT5 : BIT2;
+	msk |= (byte_lane & 1) ? (1 << 5) : (1 << 2);
 	if ((pi_count < EARLY_DB) || (pi_count > LATE_DB))
 		temp |= msk;
 
 	/* select */
-	msk |= (byte_lane & BIT0) ? BIT11 : BIT8;
+	msk |= (byte_lane & 1) ? (1 << 11) : (1 << 8);
 	if (pi_count < EARLY_DB)
 		temp |= msk;
 
 	mrc_alt_write_mask(DDRPHY, reg, temp, msk);
 
 	/* error check */
-	if (pi_count > 0x3F) {
+	if (pi_count > 0x3f) {
 		training_message(channel, rank, byte_lane);
 		mrc_post_code(0xee, 0xe0);
 	}
@@ -224,11 +223,11 @@
 	 * BL0 -> B01PTRCTL0[11:08] (0x0-0xF)
 	 * BL1 -> B01PTRCTL0[23:20] (0x0-0xF)
 	 */
-	reg = B01PTRCTL0 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
-		(channel * DDRIODQ_CH_OFFSET);
+	reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET +
+		channel * DDRIODQ_CH_OFFSET;
 	temp = msg_port_alt_read(DDRPHY, reg);
-	temp >>= (byte_lane & BIT0) ? 20 : 8;
-	temp &= 0xF;
+	temp >>= (byte_lane & 1) ? 20 : 8;
+	temp &= 0xf;
 
 	/* Adjust PI_COUNT */
 	pi_count = temp * HALF_CLK;
@@ -238,12 +237,12 @@
 	 * BL0 -> B0DLLPICODER0[29:24] (0x00-0x3F)
 	 * BL1 -> B1DLLPICODER0[29:24] (0x00-0x3F)
 	 */
-	reg = (byte_lane & BIT0) ? B1DLLPICODER0 : B0DLLPICODER0;
-	reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
-		(channel * DDRIODQ_CH_OFFSET));
+	reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0;
+	reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET +
+		channel * DDRIODQ_CH_OFFSET);
 	temp = msg_port_alt_read(DDRPHY, reg);
 	temp >>= 24;
-	temp &= 0x3F;
+	temp &= 0x3f;
 
 	/* Adjust PI_COUNT */
 	pi_count += temp;
@@ -275,10 +274,10 @@
 	 * BL0 -> B0RXDQSPICODE[06:00] (0x00-0x47)
 	 * BL1 -> B1RXDQSPICODE[06:00] (0x00-0x47)
 	 */
-	reg = (byte_lane & BIT0) ? B1RXDQSPICODE : B0RXDQSPICODE;
-	reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
-		(channel * DDRIODQ_CH_OFFSET));
-	msk = (BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0);
+	reg = (byte_lane & 1) ? B1RXDQSPICODE : B0RXDQSPICODE;
+	reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET +
+		channel * DDRIODQ_CH_OFFSET);
+	msk = 0x7f;
 	temp = pi_count << 0;
 	mrc_alt_write_mask(DDRPHY, reg, temp, msk);
 
@@ -310,13 +309,13 @@
 	 * BL0 -> B0RXDQSPICODE[06:00] (0x00-0x47)
 	 * BL1 -> B1RXDQSPICODE[06:00] (0x00-0x47)
 	 */
-	reg = (byte_lane & BIT0) ? B1RXDQSPICODE : B0RXDQSPICODE;
-	reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
-		(channel * DDRIODQ_CH_OFFSET));
+	reg = (byte_lane & 1) ? B1RXDQSPICODE : B0RXDQSPICODE;
+	reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET +
+		channel * DDRIODQ_CH_OFFSET);
 	temp = msg_port_alt_read(DDRPHY, reg);
 
 	/* Adjust PI_COUNT */
-	pi_count = temp & 0x7F;
+	pi_count = temp & 0x7f;
 
 	LEAVEFN();
 
@@ -346,26 +345,25 @@
 	 * BL0 -> B01PTRCTL0[07:04] (0x0-0xF)
 	 * BL1 -> B01PTRCTL0[19:16] (0x0-0xF)
 	 */
-	reg = B01PTRCTL0 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
-		(channel * DDRIODQ_CH_OFFSET);
-	msk = (byte_lane & BIT0) ? (BIT19 | BIT18 | BIT17 | BIT16) :
-		(BIT7 | BIT6 | BIT5 | BIT4);
+	reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET +
+		channel * DDRIODQ_CH_OFFSET;
+	msk = (byte_lane & 1) ? 0xf0000 : 0xf0;
 	temp = pi_count / HALF_CLK;
-	temp <<= (byte_lane & BIT0) ? 16 : 4;
+	temp <<= (byte_lane & 1) ? 16 : 4;
 	mrc_alt_write_mask(DDRPHY, reg, temp, msk);
 
 	/* Adjust PI_COUNT */
-	pi_count -= ((pi_count / HALF_CLK) & 0xF) * HALF_CLK;
+	pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK;
 
 	/*
 	 * PI (1/64 MCLK, 1 PIs)
 	 * BL0 -> B0DLLPICODER0[21:16] (0x00-0x3F)
 	 * BL1 -> B1DLLPICODER0[21:16] (0x00-0x3F)
 	 */
-	reg = (byte_lane & BIT0) ? B1DLLPICODER0 : B0DLLPICODER0;
-	reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
-		(channel * DDRIODQ_CH_OFFSET));
-	msk = (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16);
+	reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0;
+	reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET +
+		channel * DDRIODQ_CH_OFFSET);
+	msk = 0x3f0000;
 	temp = pi_count << 16;
 	mrc_alt_write_mask(DDRPHY, reg, temp, msk);
 
@@ -374,25 +372,25 @@
 	 * BL0/1 -> B01DBCTL1[07/10] (+1 select)
 	 * BL0/1 -> B01DBCTL1[01/04] (enable)
 	 */
-	reg = B01DBCTL1 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
-		(channel * DDRIODQ_CH_OFFSET);
+	reg = B01DBCTL1 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET +
+		channel * DDRIODQ_CH_OFFSET;
 	msk = 0x00;
 	temp = 0x00;
 
 	/* enable */
-	msk |= (byte_lane & BIT0) ? BIT4 : BIT1;
+	msk |= (byte_lane & 1) ? (1 << 4) : (1 << 1);
 	if ((pi_count < EARLY_DB) || (pi_count > LATE_DB))
 		temp |= msk;
 
 	/* select */
-	msk |= (byte_lane & BIT0) ? BIT10 : BIT7;
+	msk |= (byte_lane & 1) ? (1 << 10) : (1 << 7);
 	if (pi_count < EARLY_DB)
 		temp |= msk;
 
 	mrc_alt_write_mask(DDRPHY, reg, temp, msk);
 
 	/* error check */
-	if (pi_count > 0x3F) {
+	if (pi_count > 0x3f) {
 		training_message(channel, rank, byte_lane);
 		mrc_post_code(0xee, 0xe2);
 	}
@@ -419,11 +417,11 @@
 	 * BL0 -> B01PTRCTL0[07:04] (0x0-0xF)
 	 * BL1 -> B01PTRCTL0[19:16] (0x0-0xF)
 	 */
-	reg = B01PTRCTL0 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
-		(channel * DDRIODQ_CH_OFFSET);
+	reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET +
+		channel * DDRIODQ_CH_OFFSET;
 	temp = msg_port_alt_read(DDRPHY, reg);
-	temp >>= (byte_lane & BIT0) ? 16 : 4;
-	temp &= 0xF;
+	temp >>= (byte_lane & 1) ? 16 : 4;
+	temp &= 0xf;
 
 	/* Adjust PI_COUNT */
 	pi_count = (temp * HALF_CLK);
@@ -433,12 +431,12 @@
 	 * BL0 -> B0DLLPICODER0[21:16] (0x00-0x3F)
 	 * BL1 -> B1DLLPICODER0[21:16] (0x00-0x3F)
 	 */
-	reg = (byte_lane & BIT0) ? B1DLLPICODER0 : B0DLLPICODER0;
-	reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
-		(channel * DDRIODQ_CH_OFFSET));
+	reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0;
+	reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET +
+		channel * DDRIODQ_CH_OFFSET);
 	temp = msg_port_alt_read(DDRPHY, reg);
 	temp >>= 16;
-	temp &= 0x3F;
+	temp &= 0x3f;
 
 	/* Adjust PI_COUNT */
 	pi_count += temp;
@@ -471,26 +469,25 @@
 	 * BL0 -> B01PTRCTL0[03:00] (0x0-0xF)
 	 * BL1 -> B01PTRCTL0[15:12] (0x0-0xF)
 	 */
-	reg = B01PTRCTL0 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
-		(channel * DDRIODQ_CH_OFFSET);
-	msk = (byte_lane & BIT0) ? (BIT15 | BIT14 | BIT13 | BIT12) :
-		(BIT3 | BIT2 | BIT1 | BIT0);
+	reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET +
+		channel * DDRIODQ_CH_OFFSET;
+	msk = (byte_lane & 1) ? 0xf000 : 0xf;
 	temp = pi_count / HALF_CLK;
-	temp <<= (byte_lane & BIT0) ? 12 : 0;
+	temp <<= (byte_lane & 1) ? 12 : 0;
 	mrc_alt_write_mask(DDRPHY, reg, temp, msk);
 
 	/* Adjust PI_COUNT */
-	pi_count -= ((pi_count / HALF_CLK) & 0xF) * HALF_CLK;
+	pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK;
 
 	/*
 	 * PI (1/64 MCLK, 1 PIs)
 	 * BL0 -> B0DLLPICODER0[13:08] (0x00-0x3F)
 	 * BL1 -> B1DLLPICODER0[13:08] (0x00-0x3F)
 	 */
-	reg = (byte_lane & BIT0) ? B1DLLPICODER0 : B0DLLPICODER0;
-	reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
-		(channel * DDRIODQ_CH_OFFSET));
-	msk = (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8);
+	reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0;
+	reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET +
+		channel * DDRIODQ_CH_OFFSET);
+	msk = 0x3f00;
 	temp = pi_count << 8;
 	mrc_alt_write_mask(DDRPHY, reg, temp, msk);
 
@@ -499,25 +496,25 @@
 	 * BL0/1 -> B01DBCTL1[06/09] (+1 select)
 	 * BL0/1 -> B01DBCTL1[00/03] (enable)
 	 */
-	reg = B01DBCTL1 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
-		(channel * DDRIODQ_CH_OFFSET);
+	reg = B01DBCTL1 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET +
+		channel * DDRIODQ_CH_OFFSET;
 	msk = 0x00;
 	temp = 0x00;
 
 	/* enable */
-	msk |= (byte_lane & BIT0) ? BIT3 : BIT0;
+	msk |= (byte_lane & 1) ? (1 << 3) : (1 << 0);
 	if ((pi_count < EARLY_DB) || (pi_count > LATE_DB))
 		temp |= msk;
 
 	/* select */
-	msk |= (byte_lane & BIT0) ? BIT9 : BIT6;
+	msk |= (byte_lane & 1) ? (1 << 9) : (1 << 6);
 	if (pi_count < EARLY_DB)
 		temp |= msk;
 
 	mrc_alt_write_mask(DDRPHY, reg, temp, msk);
 
 	/* error check */
-	if (pi_count > 0x3F) {
+	if (pi_count > 0x3f) {
 		training_message(channel, rank, byte_lane);
 		mrc_post_code(0xee, 0xe3);
 	}
@@ -544,11 +541,11 @@
 	 * BL0 -> B01PTRCTL0[03:00] (0x0-0xF)
 	 * BL1 -> B01PTRCTL0[15:12] (0x0-0xF)
 	 */
-	reg = B01PTRCTL0 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
-		(channel * DDRIODQ_CH_OFFSET);
+	reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET +
+		channel * DDRIODQ_CH_OFFSET;
 	temp = msg_port_alt_read(DDRPHY, reg);
-	temp >>= (byte_lane & BIT0) ? (12) : (0);
-	temp &= 0xF;
+	temp >>= (byte_lane & 1) ? 12 : 0;
+	temp &= 0xf;
 
 	/* Adjust PI_COUNT */
 	pi_count = temp * HALF_CLK;
@@ -558,12 +555,12 @@
 	 * BL0 -> B0DLLPICODER0[13:08] (0x00-0x3F)
 	 * BL1 -> B1DLLPICODER0[13:08] (0x00-0x3F)
 	 */
-	reg = (byte_lane & BIT0) ? B1DLLPICODER0 : B0DLLPICODER0;
-	reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
-		(channel * DDRIODQ_CH_OFFSET));
+	reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0;
+	reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET +
+		channel * DDRIODQ_CH_OFFSET);
 	temp = msg_port_alt_read(DDRPHY, reg);
 	temp >>= 8;
-	temp &= 0x3F;
+	temp &= 0x3f;
 
 	/* Adjust PI_COUNT */
 	pi_count += temp;
@@ -589,14 +586,14 @@
 	 * RDPTR (1/2 MCLK, 64 PIs)
 	 * CMDPTRREG[11:08] (0x0-0xF)
 	 */
-	reg = CMDPTRREG + (channel * DDRIOCCC_CH_OFFSET);
-	msk = (BIT11 | BIT10 | BIT9 | BIT8);
+	reg = CMDPTRREG + channel * DDRIOCCC_CH_OFFSET;
+	msk = 0xf00;
 	temp = pi_count / HALF_CLK;
 	temp <<= 8;
 	mrc_alt_write_mask(DDRPHY, reg, temp, msk);
 
 	/* Adjust PI_COUNT */
-	pi_count -= ((pi_count / HALF_CLK) & 0xF) * HALF_CLK;
+	pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK;
 
 	/*
 	 * PI (1/64 MCLK, 1 PIs)
@@ -609,18 +606,13 @@
 	 * CMDDLLPICODER1[13:08] -> CMDSLICE R0 (unused)
 	 * CMDDLLPICODER1[05:00] -> CMDSLICE L0 (unused)
 	 */
-	reg = CMDDLLPICODER1 + (channel * DDRIOCCC_CH_OFFSET);
-
-	msk = (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24 |
-		BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16 |
-		BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8 |
-		BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0);
-
+	reg = CMDDLLPICODER1 + channel * DDRIOCCC_CH_OFFSET;
+	msk = 0x3f3f3f3f;
 	temp = (pi_count << 24) | (pi_count << 16) |
 		(pi_count << 8) | (pi_count << 0);
 
 	mrc_alt_write_mask(DDRPHY, reg, temp, msk);
-	reg = CMDDLLPICODER0 + (channel * DDRIOCCC_CH_OFFSET);	/* PO */
+	reg = CMDDLLPICODER0 + channel * DDRIOCCC_CH_OFFSET;	/* PO */
 	mrc_alt_write_mask(DDRPHY, reg, temp, msk);
 
 	/*
@@ -628,24 +620,24 @@
 	 * CMDCFGREG0[17] (+1 select)
 	 * CMDCFGREG0[16] (enable)
 	 */
-	reg = CMDCFGREG0 + (channel * DDRIOCCC_CH_OFFSET);
+	reg = CMDCFGREG0 + channel * DDRIOCCC_CH_OFFSET;
 	msk = 0x00;
 	temp = 0x00;
 
 	/* enable */
-	msk |= BIT16;
+	msk |= (1 << 16);
 	if ((pi_count < EARLY_DB) || (pi_count > LATE_DB))
 		temp |= msk;
 
 	/* select */
-	msk |= BIT17;
+	msk |= (1 << 17);
 	if (pi_count < EARLY_DB)
 		temp |= msk;
 
 	mrc_alt_write_mask(DDRPHY, reg, temp, msk);
 
 	/* error check */
-	if (pi_count > 0x3F)
+	if (pi_count > 0x3f)
 		mrc_post_code(0xee, 0xe4);
 
 	LEAVEFN();
@@ -667,10 +659,10 @@
 	 * RDPTR (1/2 MCLK, 64 PIs)
 	 * CMDPTRREG[11:08] (0x0-0xF)
 	 */
-	reg = CMDPTRREG + (channel * DDRIOCCC_CH_OFFSET);
+	reg = CMDPTRREG + channel * DDRIOCCC_CH_OFFSET;
 	temp = msg_port_alt_read(DDRPHY, reg);
 	temp >>= 8;
-	temp &= 0xF;
+	temp &= 0xf;
 
 	/* Adjust PI_COUNT */
 	pi_count = temp * HALF_CLK;
@@ -686,10 +678,10 @@
 	 * CMDDLLPICODER1[13:08] -> CMDSLICE R0 (unused)
 	 * CMDDLLPICODER1[05:00] -> CMDSLICE L0 (unused)
 	 */
-	reg = CMDDLLPICODER1 + (channel * DDRIOCCC_CH_OFFSET);
+	reg = CMDDLLPICODER1 + channel * DDRIOCCC_CH_OFFSET;
 	temp = msg_port_alt_read(DDRPHY, reg);
 	temp >>= 16;
-	temp &= 0x3F;
+	temp &= 0x3f;
 
 	/* Adjust PI_COUNT */
 	pi_count += temp;
@@ -716,13 +708,13 @@
 	 * CCPTRREG[15:12] -> CLK1 (0x0-0xF)
 	 * CCPTRREG[11:08] -> CLK0 (0x0-0xF)
 	 */
-	reg = CCPTRREG + (channel * DDRIOCCC_CH_OFFSET);
-	msk = (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8);
+	reg = CCPTRREG + channel * DDRIOCCC_CH_OFFSET;
+	msk = 0xff00;
 	temp = ((pi_count / HALF_CLK) << 12) | ((pi_count / HALF_CLK) << 8);
 	mrc_alt_write_mask(DDRPHY, reg, temp, msk);
 
 	/* Adjust PI_COUNT */
-	pi_count -= ((pi_count / HALF_CLK) & 0xF) * HALF_CLK;
+	pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK;
 
 	/*
 	 * PI (1/64 MCLK, 1 PIs)
@@ -731,16 +723,18 @@
 	 */
 	reg = rank ? ECCB1DLLPICODER0 : ECCB1DLLPICODER0;
 	reg += (channel * DDRIOCCC_CH_OFFSET);
-	msk = (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16 |
-		BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8);
+	msk = 0x3f3f00;
 	temp = (pi_count << 16) | (pi_count << 8);
 	mrc_alt_write_mask(DDRPHY, reg, temp, msk);
+
 	reg = rank ? ECCB1DLLPICODER1 : ECCB1DLLPICODER1;
 	reg += (channel * DDRIOCCC_CH_OFFSET);
 	mrc_alt_write_mask(DDRPHY, reg, temp, msk);
+
 	reg = rank ? ECCB1DLLPICODER2 : ECCB1DLLPICODER2;
 	reg += (channel * DDRIOCCC_CH_OFFSET);
 	mrc_alt_write_mask(DDRPHY, reg, temp, msk);
+
 	reg = rank ? ECCB1DLLPICODER3 : ECCB1DLLPICODER3;
 	reg += (channel * DDRIOCCC_CH_OFFSET);
 	mrc_alt_write_mask(DDRPHY, reg, temp, msk);
@@ -750,24 +744,24 @@
 	 * CCCFGREG1[11:08] (+1 select)
 	 * CCCFGREG1[03:00] (enable)
 	 */
-	reg = CCCFGREG1 + (channel * DDRIOCCC_CH_OFFSET);
+	reg = CCCFGREG1 + channel * DDRIOCCC_CH_OFFSET;
 	msk = 0x00;
 	temp = 0x00;
 
 	/* enable */
-	msk |= (BIT3 | BIT2 | BIT1 | BIT0);
+	msk |= 0xf;
 	if ((pi_count < EARLY_DB) || (pi_count > LATE_DB))
 		temp |= msk;
 
 	/* select */
-	msk |= (BIT11 | BIT10 | BIT9 | BIT8);
+	msk |= 0xf00;
 	if (pi_count < EARLY_DB)
 		temp |= msk;
 
 	mrc_alt_write_mask(DDRPHY, reg, temp, msk);
 
 	/* error check */
-	if (pi_count > 0x3F)
+	if (pi_count > 0x3f)
 		mrc_post_code(0xee, 0xe5);
 
 	LEAVEFN();
@@ -790,10 +784,10 @@
 	 * CCPTRREG[15:12] -> CLK1 (0x0-0xF)
 	 * CCPTRREG[11:08] -> CLK0 (0x0-0xF)
 	 */
-	reg = CCPTRREG + (channel * DDRIOCCC_CH_OFFSET);
+	reg = CCPTRREG + channel * DDRIOCCC_CH_OFFSET;
 	temp = msg_port_alt_read(DDRPHY, reg);
 	temp >>= rank ? 12 : 8;
-	temp &= 0xF;
+	temp &= 0xf;
 
 	/* Adjust PI_COUNT */
 	pi_count = temp * HALF_CLK;
@@ -807,7 +801,7 @@
 	reg += (channel * DDRIOCCC_CH_OFFSET);
 	temp = msg_port_alt_read(DDRPHY, reg);
 	temp >>= rank ? 16 : 8;
-	temp &= 0x3F;
+	temp &= 0x3f;
 
 	pi_count += temp;
 
@@ -835,28 +829,31 @@
 	 * CCPTRREG[31:28] (0x0-0xF)
 	 * CCPTRREG[27:24] (0x0-0xF)
 	 */
-	reg = CCPTRREG + (channel * DDRIOCCC_CH_OFFSET);
-	msk = (BIT31 | BIT30 | BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24);
+	reg = CCPTRREG + channel * DDRIOCCC_CH_OFFSET;
+	msk = 0xff000000;
 	temp = ((pi_count / HALF_CLK) << 28) | ((pi_count / HALF_CLK) << 24);
 	mrc_alt_write_mask(DDRPHY, reg, temp, msk);
 
 	/* Adjust PI_COUNT */
-	pi_count -= ((pi_count / HALF_CLK) & 0xF) * HALF_CLK;
+	pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK;
 
 	/*
 	 * PI (1/64 MCLK, 1 PIs)
 	 * ECCB1DLLPICODER?[29:24] (0x00-0x3F)
 	 * ECCB1DLLPICODER?[29:24] (0x00-0x3F)
 	 */
-	reg = ECCB1DLLPICODER0 + (channel * DDRIOCCC_CH_OFFSET);
-	msk = (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24);
+	reg = ECCB1DLLPICODER0 + channel * DDRIOCCC_CH_OFFSET;
+	msk = 0x3f000000;
 	temp = (pi_count << 24);
 	mrc_alt_write_mask(DDRPHY, reg, temp, msk);
-	reg = ECCB1DLLPICODER1 + (channel * DDRIOCCC_CH_OFFSET);
+
+	reg = ECCB1DLLPICODER1 + channel * DDRIOCCC_CH_OFFSET;
 	mrc_alt_write_mask(DDRPHY, reg, temp, msk);
-	reg = ECCB1DLLPICODER2 + (channel * DDRIOCCC_CH_OFFSET);
+
+	reg = ECCB1DLLPICODER2 + channel * DDRIOCCC_CH_OFFSET;
 	mrc_alt_write_mask(DDRPHY, reg, temp, msk);
-	reg = ECCB1DLLPICODER3 + (channel * DDRIOCCC_CH_OFFSET);
+
+	reg = ECCB1DLLPICODER3 + channel * DDRIOCCC_CH_OFFSET;
 	mrc_alt_write_mask(DDRPHY, reg, temp, msk);
 
 	/*
@@ -864,24 +861,24 @@
 	 * CCCFGREG1[13:12] (+1 select)
 	 * CCCFGREG1[05:04] (enable)
 	 */
-	reg = CCCFGREG1 + (channel * DDRIOCCC_CH_OFFSET);
+	reg = CCCFGREG1 + channel * DDRIOCCC_CH_OFFSET;
 	msk = 0x00;
 	temp = 0x00;
 
 	/* enable */
-	msk |= (BIT5 | BIT4);
+	msk |= 0x30;
 	if ((pi_count < EARLY_DB) || (pi_count > LATE_DB))
 		temp |= msk;
 
 	/* select */
-	msk |= (BIT13 | BIT12);
+	msk |= 0x3000;
 	if (pi_count < EARLY_DB)
 		temp |= msk;
 
 	mrc_alt_write_mask(DDRPHY, reg, temp, msk);
 
 	/* error check */
-	if (pi_count > 0x3F)
+	if (pi_count > 0x3f)
 		mrc_post_code(0xee, 0xe6);
 
 	LEAVEFN();
@@ -906,10 +903,10 @@
 	 * CCPTRREG[31:28] (0x0-0xF)
 	 * CCPTRREG[27:24] (0x0-0xF)
 	 */
-	reg = CCPTRREG + (channel * DDRIOCCC_CH_OFFSET);
+	reg = CCPTRREG + channel * DDRIOCCC_CH_OFFSET;
 	temp = msg_port_alt_read(DDRPHY, reg);
 	temp >>= 24;
-	temp &= 0xF;
+	temp &= 0xf;
 
 	/* Adjust PI_COUNT */
 	pi_count = temp * HALF_CLK;
@@ -919,10 +916,10 @@
 	 * ECCB1DLLPICODER?[29:24] (0x00-0x3F)
 	 * ECCB1DLLPICODER?[29:24] (0x00-0x3F)
 	 */
-	reg = ECCB1DLLPICODER0 + (channel * DDRIOCCC_CH_OFFSET);
+	reg = ECCB1DLLPICODER0 + channel * DDRIOCCC_CH_OFFSET;
 	temp = msg_port_alt_read(DDRPHY, reg);
 	temp >>= 24;
-	temp &= 0x3F;
+	temp &= 0x3f;
 
 	/* Adjust PI_COUNT */
 	pi_count += temp;
@@ -938,17 +935,16 @@
  */
 void set_vref(uint8_t channel, uint8_t byte_lane, uint32_t setting)
 {
-	uint32_t reg = (byte_lane & 0x1) ? (B1VREFCTL) : (B0VREFCTL);
+	uint32_t reg = (byte_lane & 0x1) ? B1VREFCTL : B0VREFCTL;
 
 	ENTERFN();
 
 	DPF(D_TRN, "Vref ch%d ln%d : val=%03X\n",
 	    channel, byte_lane, setting);
 
-	mrc_alt_write_mask(DDRPHY, (reg + (channel * DDRIODQ_CH_OFFSET) +
-		((byte_lane >> 1) * DDRIODQ_BL_OFFSET)),
-		(vref_codes[setting] << 2),
-		(BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2));
+	mrc_alt_write_mask(DDRPHY, reg + channel * DDRIODQ_CH_OFFSET +
+		(byte_lane >> 1) * DDRIODQ_BL_OFFSET,
+		vref_codes[setting] << 2, 0xfc);
 
 	/*
 	 * need to wait ~300ns for Vref to settle
@@ -969,15 +965,15 @@
 {
 	uint8_t j;
 	uint32_t ret_val = sizeof(vref_codes) / 2;
-	uint32_t reg = (byte_lane & 0x1) ? (B1VREFCTL) : (B0VREFCTL);
+	uint32_t reg = (byte_lane & 0x1) ? B1VREFCTL : B0VREFCTL;
 	uint32_t temp;
 
 	ENTERFN();
 
-	temp = msg_port_alt_read(DDRPHY, (reg + (channel * DDRIODQ_CH_OFFSET) +
-		((byte_lane >> 1) * DDRIODQ_BL_OFFSET)));
+	temp = msg_port_alt_read(DDRPHY, reg + channel * DDRIODQ_CH_OFFSET +
+		(byte_lane >> 1) * DDRIODQ_BL_OFFSET);
 	temp >>= 2;
-	temp &= 0x3F;
+	temp &= 0x3f;
 
 	for (j = 0; j < sizeof(vref_codes); j++) {
 		if (vref_codes[j] == temp) {
@@ -997,7 +993,7 @@
  */
 uint32_t get_addr(uint8_t channel, uint8_t rank)
 {
-	uint32_t offset = 0x02000000;	/* 32MB */
+	uint32_t offset = 32 * 1024 * 1024;	/* 32MB */
 
 	/* Begin product specific code */
 	if (channel > 0) {
@@ -1040,8 +1036,8 @@
 	uint32_t address = get_addr(channel, rank);
 
 	/* initialise msk[] */
-	msk[0] = rcvn ? BIT1 : BIT9;	/* BL0 */
-	msk[1] = rcvn ? BIT0 : BIT8;	/* BL1 */
+	msk[0] = rcvn ? (1 << 1) : (1 << 9);	/* BL0 */
+	msk[1] = rcvn ? (1 << 0) : (1 << 8);	/* BL1 */
 
 	/* cycle through each byte lane group */
 	for (bl_grp = 0; bl_grp < (NUM_BYTE_LANES / bl_divisor) / 2; bl_grp++) {
@@ -1056,9 +1052,9 @@
 			 * DQTRAINSTS register
 			 */
 			sampled_val[j] = msg_port_alt_read(DDRPHY,
-				(DQTRAINSTS +
-				(bl_grp * DDRIODQ_BL_OFFSET) +
-				(channel * DDRIODQ_CH_OFFSET)));
+				DQTRAINSTS +
+				bl_grp * DDRIODQ_BL_OFFSET +
+				channel * DDRIODQ_CH_OFFSET);
 		}
 
 		/*
@@ -1076,7 +1072,7 @@
 					num_0s++;
 			}
 		if (num_1s > num_0s)
-			ret_val |= (1 << (bl + (bl_grp * 2)));
+			ret_val |= (1 << (bl + bl_grp * 2));
 		}
 	}
 
@@ -1116,10 +1112,10 @@
 			/* increase sample delay by 26 PI (0.2 CLK) */
 			if (rcvn) {
 				set_rcvn(channel, rank, bl,
-					 delay[bl] + (sample * SAMPLE_DLY));
+					 delay[bl] + sample * SAMPLE_DLY);
 			} else {
 				set_wdqs(channel, rank, bl,
-					 delay[bl] + (sample * SAMPLE_DLY));
+					 delay[bl] + sample * SAMPLE_DLY);
 			}
 		}
 
@@ -1129,7 +1125,7 @@
 
 		DPF(D_TRN,
 		    "Find rising edge %s ch%d rnk%d: #%d dly=%d dqs=%02X\n",
-		    (rcvn ? "RCVN" : "WDQS"), channel, rank, sample,
+		    rcvn ? "RCVN" : "WDQS", channel, rank, sample,
 		    sample * SAMPLE_DLY, sample_result[sample]);
 	}
 
@@ -1137,7 +1133,7 @@
 	 * This pattern will help determine where we landed and ultimately
 	 * how to place RCVEN/WDQS.
 	 */
-	for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) {
+	for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) {
 		/* build transition_pattern (MSB is 1st sample) */
 		transition_pattern = 0;
 		for (sample = 0; sample < SAMPLE_CNT; sample++) {
@@ -1202,7 +1198,7 @@
 		/* take a sample */
 		temp = sample_dqs(mrc_params, channel, rank, rcvn);
 		/* check all each byte lane for proper edge */
-		for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) {
+		for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) {
 			if (temp & (1 << bl)) {
 				/* sampled "1" */
 				if (direction[bl] == BACKWARD) {
@@ -1340,10 +1336,10 @@
 	lfsr = *lfsr_ptr;
 
 	for (i = 0; i < 32; i++) {
-		bit = 1 ^ (lfsr & BIT0);
-		bit = bit ^ ((lfsr & BIT1) >> 1);
-		bit = bit ^ ((lfsr & BIT2) >> 2);
-		bit = bit ^ ((lfsr & BIT22) >> 22);
+		bit = 1 ^ (lfsr & 1);
+		bit = bit ^ ((lfsr & 2) >> 1);
+		bit = bit ^ ((lfsr & 4) >> 2);
+		bit = bit ^ ((lfsr & 0x400000) >> 22);
 
 		lfsr = ((lfsr >> 1) | (bit << 31));
 	}
@@ -1362,16 +1358,16 @@
 	for (channel = 0; channel < NUM_CHANNELS; channel++) {
 		for (bl = 0; bl < NUM_BYTE_LANES; bl++) {
 			mrc_alt_write_mask(DDRPHY,
-					   (B01PTRCTL1 +
-					   (channel * DDRIODQ_CH_OFFSET) +
-					   ((bl >> 1) * DDRIODQ_BL_OFFSET)),
-					   ~BIT8, BIT8);
+					   B01PTRCTL1 +
+					   channel * DDRIODQ_CH_OFFSET +
+					   (bl >> 1) * DDRIODQ_BL_OFFSET,
+					   ~(1 << 8), (1 << 8));
 
 			mrc_alt_write_mask(DDRPHY,
-					   (B01PTRCTL1 +
-					   (channel * DDRIODQ_CH_OFFSET) +
-					   ((bl >> 1) * DDRIODQ_BL_OFFSET)),
-					   BIT8, BIT8);
+					   B01PTRCTL1 +
+					   channel * DDRIODQ_CH_OFFSET +
+					   (bl >> 1) * DDRIODQ_BL_OFFSET,
+					   (1 << 8), (1 << 8));
 		}
 	}
 
@@ -1412,7 +1408,7 @@
 		break;
 	}
 
-	for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) {
+	for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) {
 		switch (algo) {
 		case RCVN:
 			DPF(D_INFO, " %03d", get_rcvn(channel, rank, bl));
diff --git a/arch/x86/cpu/quark/mrc_util.h b/arch/x86/cpu/quark/mrc_util.h
index f0ddbce..a63d1f9 100644
--- a/arch/x86/cpu/quark/mrc_util.h
+++ b/arch/x86/cpu/quark/mrc_util.h
@@ -41,40 +41,6 @@
 #define LEAVEFN(...)	debug_cond(D_FCALL, "</%s>\n", __func__)
 #define REPORTFN(...)	debug_cond(D_FCALL, "<%s/>\n", __func__)
 
-/* Generic Register Bits */
-#define BIT0		0x00000001
-#define BIT1		0x00000002
-#define BIT2		0x00000004
-#define BIT3		0x00000008
-#define BIT4		0x00000010
-#define BIT5		0x00000020
-#define BIT6		0x00000040
-#define BIT7		0x00000080
-#define BIT8		0x00000100
-#define BIT9		0x00000200
-#define BIT10		0x00000400
-#define BIT11		0x00000800
-#define BIT12		0x00001000
-#define BIT13		0x00002000
-#define BIT14		0x00004000
-#define BIT15		0x00008000
-#define BIT16		0x00010000
-#define BIT17		0x00020000
-#define BIT18		0x00040000
-#define BIT19		0x00080000
-#define BIT20		0x00100000
-#define BIT21		0x00200000
-#define BIT22		0x00400000
-#define BIT23		0x00800000
-#define BIT24		0x01000000
-#define BIT25		0x02000000
-#define BIT26		0x04000000
-#define BIT27		0x08000000
-#define BIT28		0x10000000
-#define BIT29		0x20000000
-#define BIT30		0x40000000
-#define BIT31		0x80000000
-
 /* Message Bus Port */
 #define MEM_CTLR	0x01
 #define HOST_BRIDGE	0x03
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index dccf7ac..25edcf7 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -6,6 +6,8 @@
 
 #include <common.h>
 #include <mmc.h>
+#include <netdev.h>
+#include <phy.h>
 #include <asm/io.h>
 #include <asm/pci.h>
 #include <asm/post.h>
@@ -116,3 +118,20 @@
 	return pci_mmc_init("Quark SDHCI", mmc_supported,
 			    ARRAY_SIZE(mmc_supported));
 }
+
+int cpu_eth_init(bd_t *bis)
+{
+	u32 base;
+	int ret0, ret1;
+
+	pci_read_config_dword(QUARK_EMAC0, PCI_BASE_ADDRESS_0, &base);
+	ret0 = designware_initialize(base, PHY_INTERFACE_MODE_RMII);
+
+	pci_read_config_dword(QUARK_EMAC1, PCI_BASE_ADDRESS_0, &base);
+	ret1 = designware_initialize(base, PHY_INTERFACE_MODE_RMII);
+
+	if (ret0 < 0 && ret1 < 0)
+		return -1;
+	else
+		return 0;
+}
diff --git a/arch/x86/cpu/quark/smc.c b/arch/x86/cpu/quark/smc.c
index e34bec4..3ffe92b 100644
--- a/arch/x86/cpu/quark/smc.c
+++ b/arch/x86/cpu/quark/smc.c
@@ -60,7 +60,7 @@
 	ENTERFN();
 
 	/* clear the PMSTS Channel Self Refresh bits */
-	mrc_write_mask(MEM_CTLR, PMSTS, BIT0, BIT0);
+	mrc_write_mask(MEM_CTLR, PMSTS, PMSTS_DISR, PMSTS_DISR);
 
 	LEAVEFN();
 }
@@ -101,47 +101,47 @@
 
 	wl = 5 + mrc_params->ddr_speed;
 
-	dtr0 &= ~(BIT0 | BIT1);
+	dtr0 &= ~DTR0_DFREQ_MASK;
 	dtr0 |= mrc_params->ddr_speed;
-	dtr0 &= ~(BIT12 | BIT13 | BIT14);
+	dtr0 &= ~DTR0_TCL_MASK;
 	tmp1 = tcl - 5;
 	dtr0 |= ((tcl - 5) << 12);
-	dtr0 &= ~(BIT4 | BIT5 | BIT6 | BIT7);
+	dtr0 &= ~DTR0_TRP_MASK;
 	dtr0 |= ((trp - 5) << 4);	/* 5 bit DRAM Clock */
-	dtr0 &= ~(BIT8 | BIT9 | BIT10 | BIT11);
+	dtr0 &= ~DTR0_TRCD_MASK;
 	dtr0 |= ((trcd - 5) << 8);	/* 5 bit DRAM Clock */
 
-	dtr1 &= ~(BIT0 | BIT1 | BIT2);
+	dtr1 &= ~DTR1_TWCL_MASK;
 	tmp2 = wl - 3;
 	dtr1 |= (wl - 3);
-	dtr1 &= ~(BIT8 | BIT9 | BIT10 | BIT11);
+	dtr1 &= ~DTR1_TWTP_MASK;
 	dtr1 |= ((wl + 4 + twr - 14) << 8);	/* Change to tWTP */
-	dtr1 &= ~(BIT28 | BIT29 | BIT30);
+	dtr1 &= ~DTR1_TRTP_MASK;
 	dtr1 |= ((MMAX(trtp, 4) - 3) << 28);	/* 4 bit DRAM Clock */
-	dtr1 &= ~(BIT24 | BIT25);
+	dtr1 &= ~DTR1_TRRD_MASK;
 	dtr1 |= ((trrd - 4) << 24);		/* 4 bit DRAM Clock */
-	dtr1 &= ~(BIT4 | BIT5);
+	dtr1 &= ~DTR1_TCMD_MASK;
 	dtr1 |= (1 << 4);
-	dtr1 &= ~(BIT20 | BIT21 | BIT22 | BIT23);
+	dtr1 &= ~DTR1_TRAS_MASK;
 	dtr1 |= ((tras - 14) << 20);		/* 6 bit DRAM Clock */
-	dtr1 &= ~(BIT16 | BIT17 | BIT18 | BIT19);
+	dtr1 &= ~DTR1_TFAW_MASK;
 	dtr1 |= ((((tfaw + 1) >> 1) - 5) << 16);/* 4 bit DRAM Clock */
 	/* Set 4 Clock CAS to CAS delay (multi-burst) */
-	dtr1 &= ~(BIT12 | BIT13);
+	dtr1 &= ~DTR1_TCCD_MASK;
 
-	dtr2 &= ~(BIT0 | BIT1 | BIT2);
+	dtr2 &= ~DTR2_TRRDR_MASK;
 	dtr2 |= 1;
-	dtr2 &= ~(BIT8 | BIT9 | BIT10);
+	dtr2 &= ~DTR2_TWWDR_MASK;
 	dtr2 |= (2 << 8);
-	dtr2 &= ~(BIT16 | BIT17 | BIT18 | BIT19);
+	dtr2 &= ~DTR2_TRWDR_MASK;
 	dtr2 |= (2 << 16);
 
-	dtr3 &= ~(BIT0 | BIT1 | BIT2);
+	dtr3 &= ~DTR3_TWRDR_MASK;
 	dtr3 |= 2;
-	dtr3 &= ~(BIT4 | BIT5 | BIT6);
+	dtr3 &= ~DTR3_TXXXX_MASK;
 	dtr3 |= (2 << 4);
 
-	dtr3 &= ~(BIT8 | BIT9 | BIT10 | BIT11);
+	dtr3 &= ~DTR3_TRWSR_MASK;
 	if (mrc_params->ddr_speed == DDRFREQ_800) {
 		/* Extended RW delay (+1) */
 		dtr3 |= ((tcl - 5 + 1) << 8);
@@ -150,24 +150,24 @@
 		dtr3 |= ((tcl - 5 + 1) << 8);
 	}
 
-	dtr3 &= ~(BIT13 | BIT14 | BIT15 | BIT16);
+	dtr3 &= ~DTR3_TWRSR_MASK;
 	dtr3 |= ((4 + wl + twtr - 11) << 13);
 
-	dtr3 &= ~(BIT22 | BIT23);
+	dtr3 &= ~DTR3_TXP_MASK;
 	if (mrc_params->ddr_speed == DDRFREQ_800)
 		dtr3 |= ((MMAX(0, 1 - 1)) << 22);
 	else
 		dtr3 |= ((MMAX(0, 2 - 1)) << 22);
 
-	dtr4 &= ~(BIT0 | BIT1);
+	dtr4 &= ~DTR4_WRODTSTRT_MASK;
 	dtr4 |= 1;
-	dtr4 &= ~(BIT4 | BIT5 | BIT6);
+	dtr4 &= ~DTR4_WRODTSTOP_MASK;
 	dtr4 |= (1 << 4);
-	dtr4 &= ~(BIT8 | BIT9 | BIT10);
+	dtr4 &= ~DTR4_XXXX1_MASK;
 	dtr4 |= ((1 + tmp1 - tmp2 + 2) << 8);
-	dtr4 &= ~(BIT12 | BIT13 | BIT14);
+	dtr4 &= ~DTR4_XXXX2_MASK;
 	dtr4 |= ((1 + tmp1 - tmp2 + 2) << 12);
-	dtr4 &= ~(BIT15 | BIT16);
+	dtr4 &= ~(DTR4_ODTDIS | DTR4_TRGSTRDIS);
 
 	msg_port_write(MEM_CTLR, DTR0, dtr0);
 	msg_port_write(MEM_CTLR, DTR1, dtr1);
@@ -191,25 +191,25 @@
 
 	/* Disable power saving features */
 	dpmc0 = msg_port_read(MEM_CTLR, DPMC0);
-	dpmc0 |= (BIT24 | BIT25);
-	dpmc0 &= ~(BIT16 | BIT17 | BIT18);
-	dpmc0 &= ~BIT23;
+	dpmc0 |= (DPMC0_CLKGTDIS | DPMC0_DISPWRDN);
+	dpmc0 &= ~DPMC0_PCLSTO_MASK;
+	dpmc0 &= ~DPMC0_DYNSREN;
 	msg_port_write(MEM_CTLR, DPMC0, dpmc0);
 
 	/* Disable out of order transactions */
 	dsch = msg_port_read(MEM_CTLR, DSCH);
-	dsch |= (BIT8 | BIT12);
+	dsch |= (DSCH_OOODIS | DSCH_NEWBYPDIS);
 	msg_port_write(MEM_CTLR, DSCH, dsch);
 
 	/* Disable issuing the REF command */
 	drfc = msg_port_read(MEM_CTLR, DRFC);
-	drfc &= ~(BIT12 | BIT13 | BIT14);
+	drfc &= ~DRFC_TREFI_MASK;
 	msg_port_write(MEM_CTLR, DRFC, drfc);
 
 	/* Disable ZQ calibration short */
 	dcal = msg_port_read(MEM_CTLR, DCAL);
-	dcal &= ~(BIT8 | BIT9 | BIT10);
-	dcal &= ~(BIT12 | BIT13);
+	dcal &= ~DCAL_ZQCINT_MASK;
+	dcal &= ~DCAL_SRXZQCL_MASK;
 	msg_port_write(MEM_CTLR, DCAL, dcal);
 
 	/*
@@ -218,9 +218,9 @@
 	 */
 	drp = 0;
 	if (mrc_params->rank_enables & 1)
-		drp |= BIT0;
+		drp |= DRP_RKEN0;
 	if (mrc_params->rank_enables & 2)
-		drp |= BIT1;
+		drp |= DRP_RKEN1;
 	msg_port_write(MEM_CTLR, DRP, drp);
 
 	LEAVEFN();
@@ -238,14 +238,14 @@
 	ENTERFN();
 
 	/* Set COLDWAKE bit before sending the WAKE message */
-	mrc_write_mask(MEM_CTLR, DRMC, BIT16, BIT16);
+	mrc_write_mask(MEM_CTLR, DRMC, DRMC_COLDWAKE, DRMC_COLDWAKE);
 
 	/* Send wake command to DUNIT (MUST be done before JEDEC) */
 	dram_wake_command();
 
 	/* Set default value */
 	msg_port_write(MEM_CTLR, DRMC,
-		       (mrc_params->rd_odt_value == 0 ? BIT12 : 0));
+		       mrc_params->rd_odt_value == 0 ? DRMC_ODTMODE : 0);
 
 	LEAVEFN();
 }
@@ -263,7 +263,7 @@
 	uint8_t bl_grp;	/*  byte lane group counter (2 BLs per module) */
 	uint8_t bl_divisor = 1;	/* byte lane divisor */
 	/* For DDR3 --> 0 == 800, 1 == 1066, 2 == 1333 */
-	uint8_t speed = mrc_params->ddr_speed & (BIT1 | BIT0);
+	uint8_t speed = mrc_params->ddr_speed & 3;
 	uint8_t cas;
 	uint8_t cwl;
 
@@ -286,21 +286,21 @@
 		if (mrc_params->channel_enables & (1 << ch)) {
 			/* Deassert DDRPHY Initialization Complete */
 			mrc_alt_write_mask(DDRPHY,
-				(CMDPMCONFIG0 + (ch * DDRIOCCC_CH_OFFSET)),
-				~BIT20, BIT20);	/* SPID_INIT_COMPLETE=0 */
+				CMDPMCONFIG0 + ch * DDRIOCCC_CH_OFFSET,
+				~(1 << 20), 1 << 20);	/* SPID_INIT_COMPLETE=0 */
 			/* Deassert IOBUFACT */
 			mrc_alt_write_mask(DDRPHY,
-				(CMDCFGREG0 + (ch * DDRIOCCC_CH_OFFSET)),
-				~BIT2, BIT2);	/* IOBUFACTRST_N=0 */
+				CMDCFGREG0 + ch * DDRIOCCC_CH_OFFSET,
+				~(1 << 2), 1 << 2);	/* IOBUFACTRST_N=0 */
 			/* Disable WRPTR */
 			mrc_alt_write_mask(DDRPHY,
-				(CMDPTRREG + (ch * DDRIOCCC_CH_OFFSET)),
-				~BIT0, BIT0);	/* WRPTRENABLE=0 */
+				CMDPTRREG + ch * DDRIOCCC_CH_OFFSET,
+				~(1 << 0), 1 << 0);	/* WRPTRENABLE=0 */
 		}
 	}
 
 	/* Put PHY in reset */
-	mrc_alt_write_mask(DDRPHY, MASTERRSTN, 0, BIT0);
+	mrc_alt_write_mask(DDRPHY, MASTERRSTN, 0, 1);
 
 	/* Initialize DQ01, DQ23, CMD, CLK-CTL, COMP modules */
 
@@ -310,14 +310,14 @@
 		if (mrc_params->channel_enables & (1 << ch)) {
 			/* DQ01-DQ23 */
 			for (bl_grp = 0;
-			     bl_grp < ((NUM_BYTE_LANES / bl_divisor) / 2);
+			     bl_grp < (NUM_BYTE_LANES / bl_divisor) / 2;
 			     bl_grp++) {
 				/* Analog MUX select - IO2xCLKSEL */
 				mrc_alt_write_mask(DDRPHY,
-					(DQOBSCKEBBCTL +
-					(bl_grp * DDRIODQ_BL_OFFSET) +
-					(ch * DDRIODQ_CH_OFFSET)),
-					((bl_grp) ? (0x00) : (BIT22)), (BIT22));
+					DQOBSCKEBBCTL +
+					bl_grp * DDRIODQ_BL_OFFSET +
+					ch * DDRIODQ_CH_OFFSET,
+					bl_grp ? 0 : (1 << 22), 1 << 22);
 
 				/* ODT Strength */
 				switch (mrc_params->rd_odt_value) {
@@ -337,20 +337,20 @@
 
 				/* ODT strength */
 				mrc_alt_write_mask(DDRPHY,
-					(B0RXIOBUFCTL +
-					(bl_grp * DDRIODQ_BL_OFFSET) +
-					(ch * DDRIODQ_CH_OFFSET)),
-					(temp << 5), (BIT6 | BIT5));
+					B0RXIOBUFCTL +
+					bl_grp * DDRIODQ_BL_OFFSET +
+					ch * DDRIODQ_CH_OFFSET,
+					temp << 5, 0x60);
 				/* ODT strength */
 				mrc_alt_write_mask(DDRPHY,
-					(B1RXIOBUFCTL +
-					(bl_grp * DDRIODQ_BL_OFFSET) +
-					(ch * DDRIODQ_CH_OFFSET)),
-					(temp << 5), (BIT6 | BIT5));
+					B1RXIOBUFCTL +
+					bl_grp * DDRIODQ_BL_OFFSET +
+					ch * DDRIODQ_CH_OFFSET,
+					temp << 5, 0x60);
 
 				/* Dynamic ODT/DIFFAMP */
-				temp = (((cas) << 24) | ((cas) << 16) |
-					((cas) << 8) | ((cas) << 0));
+				temp = (cas << 24) | (cas << 16) |
+					(cas << 8) | (cas << 0);
 				switch (speed) {
 				case 0:
 					temp -= 0x01010101;
@@ -368,247 +368,199 @@
 
 				/* Launch Time: ODT, DIFFAMP, ODT, DIFFAMP */
 				mrc_alt_write_mask(DDRPHY,
-					(B01LATCTL1 +
-					(bl_grp * DDRIODQ_BL_OFFSET) +
-					(ch * DDRIODQ_CH_OFFSET)),
-					temp,
-					(BIT28 | BIT27 | BIT26 | BIT25 | BIT24 |
-					BIT20 | BIT19 | BIT18 | BIT17 | BIT16 |
-					BIT12 | BIT11 | BIT10 | BIT9 | BIT8 |
-					BIT4 | BIT3 | BIT2 | BIT1 | BIT0));
+					B01LATCTL1 +
+					bl_grp * DDRIODQ_BL_OFFSET +
+					ch * DDRIODQ_CH_OFFSET,
+					temp, 0x1f1f1f1f);
 				switch (speed) {
 				/* HSD#234715 */
 				case 0:
-					temp = ((0x06 << 16) | (0x07 << 8));
+					temp = (0x06 << 16) | (0x07 << 8);
 					break;	/* 800 */
 				case 1:
-					temp = ((0x07 << 16) | (0x08 << 8));
+					temp = (0x07 << 16) | (0x08 << 8);
 					break;	/* 1066 */
 				case 2:
-					temp = ((0x09 << 16) | (0x0A << 8));
+					temp = (0x09 << 16) | (0x0a << 8);
 					break;	/* 1333 */
 				case 3:
-					temp = ((0x0A << 16) | (0x0B << 8));
+					temp = (0x0a << 16) | (0x0b << 8);
 					break;	/* 1600 */
 				}
 
 				/* On Duration: ODT, DIFFAMP */
 				mrc_alt_write_mask(DDRPHY,
-					(B0ONDURCTL +
-					(bl_grp * DDRIODQ_BL_OFFSET) +
-					(ch * DDRIODQ_CH_OFFSET)),
-					temp,
-					(BIT21 | BIT20 | BIT19 | BIT18 | BIT17 |
-					BIT16 | BIT13 | BIT12 | BIT11 | BIT10 |
-					BIT9 | BIT8));
+					B0ONDURCTL +
+					bl_grp * DDRIODQ_BL_OFFSET +
+					ch * DDRIODQ_CH_OFFSET,
+					temp, 0x003f3f00);
 				/* On Duration: ODT, DIFFAMP */
 				mrc_alt_write_mask(DDRPHY,
-					(B1ONDURCTL +
-					(bl_grp * DDRIODQ_BL_OFFSET) +
-					(ch * DDRIODQ_CH_OFFSET)),
-					temp,
-					(BIT21 | BIT20 | BIT19 | BIT18 | BIT17 |
-					BIT16 | BIT13 | BIT12 | BIT11 | BIT10 |
-					BIT9 | BIT8));
+					B1ONDURCTL +
+					bl_grp * DDRIODQ_BL_OFFSET +
+					ch * DDRIODQ_CH_OFFSET,
+					temp, 0x003f3f00);
 
 				switch (mrc_params->rd_odt_value) {
 				case 0:
 					/* override DIFFAMP=on, ODT=off */
-					temp = ((0x3F << 16) | (0x3f << 10));
+					temp = (0x3f << 16) | (0x3f << 10);
 					break;
 				default:
 					/* override DIFFAMP=on, ODT=on */
-					temp = ((0x3F << 16) | (0x2A << 10));
+					temp = (0x3f << 16) | (0x2a << 10);
 					break;
 				}
 
 				/* Override: DIFFAMP, ODT */
 				mrc_alt_write_mask(DDRPHY,
-					(B0OVRCTL +
-					(bl_grp * DDRIODQ_BL_OFFSET) +
-					(ch * DDRIODQ_CH_OFFSET)),
-					temp,
-					(BIT21 | BIT20 | BIT19 | BIT18 | BIT17 |
-					BIT16 | BIT15 | BIT14 | BIT13 | BIT12 |
-					BIT11 | BIT10));
+					B0OVRCTL +
+					bl_grp * DDRIODQ_BL_OFFSET +
+					ch * DDRIODQ_CH_OFFSET,
+					temp, 0x003ffc00);
 				/* Override: DIFFAMP, ODT */
 				mrc_alt_write_mask(DDRPHY,
-					(B1OVRCTL +
-					(bl_grp * DDRIODQ_BL_OFFSET) +
-					(ch * DDRIODQ_CH_OFFSET)),
-					temp,
-					(BIT21 | BIT20 | BIT19 | BIT18 | BIT17 |
-					BIT16 | BIT15 | BIT14 | BIT13 | BIT12 |
-					BIT11 | BIT10));
+					B1OVRCTL +
+					bl_grp * DDRIODQ_BL_OFFSET +
+					ch * DDRIODQ_CH_OFFSET,
+					temp, 0x003ffc00);
 
 				/* DLL Setup */
 
 				/* 1xCLK Domain Timings: tEDP,RCVEN,WDQS (PO) */
 				mrc_alt_write_mask(DDRPHY,
-					(B0LATCTL0 +
-					(bl_grp * DDRIODQ_BL_OFFSET) +
-					(ch * DDRIODQ_CH_OFFSET)),
-					(((cas + 7) << 16) | ((cas - 4) << 8) |
-					((cwl - 2) << 0)),
-					(BIT21 | BIT20 | BIT19 | BIT18 | BIT17 |
-					BIT16 | BIT12 | BIT11 | BIT10 | BIT9 |
-					BIT8 | BIT4 | BIT3 | BIT2 | BIT1 |
-					BIT0));
+					B0LATCTL0 +
+					bl_grp * DDRIODQ_BL_OFFSET +
+					ch * DDRIODQ_CH_OFFSET,
+					((cas + 7) << 16) | ((cas - 4) << 8) |
+					((cwl - 2) << 0), 0x003f1f1f);
 				mrc_alt_write_mask(DDRPHY,
-					(B1LATCTL0 +
-					(bl_grp * DDRIODQ_BL_OFFSET) +
-					(ch * DDRIODQ_CH_OFFSET)),
-					(((cas + 7) << 16) | ((cas - 4) << 8) |
-					((cwl - 2) << 0)),
-					(BIT21 | BIT20 | BIT19 | BIT18 | BIT17 |
-					BIT16 | BIT12 | BIT11 | BIT10 | BIT9 |
-					BIT8 | BIT4 | BIT3 | BIT2 | BIT1 |
-					BIT0));
+					B1LATCTL0 +
+					bl_grp * DDRIODQ_BL_OFFSET +
+					ch * DDRIODQ_CH_OFFSET,
+					((cas + 7) << 16) | ((cas - 4) << 8) |
+					((cwl - 2) << 0), 0x003f1f1f);
 
 				/* RCVEN Bypass (PO) */
 				mrc_alt_write_mask(DDRPHY,
-					(B0RXIOBUFCTL +
-					(bl_grp * DDRIODQ_BL_OFFSET) +
-					(ch * DDRIODQ_CH_OFFSET)),
-					((0x0 << 7) | (0x0 << 0)),
-					(BIT7 | BIT0));
+					B0RXIOBUFCTL +
+					bl_grp * DDRIODQ_BL_OFFSET +
+					ch * DDRIODQ_CH_OFFSET,
+					0, 0x81);
 				mrc_alt_write_mask(DDRPHY,
-					(B1RXIOBUFCTL +
-					(bl_grp * DDRIODQ_BL_OFFSET) +
-					(ch * DDRIODQ_CH_OFFSET)),
-					((0x0 << 7) | (0x0 << 0)),
-					(BIT7 | BIT0));
+					B1RXIOBUFCTL +
+					bl_grp * DDRIODQ_BL_OFFSET +
+					ch * DDRIODQ_CH_OFFSET,
+					0, 0x81);
 
 				/* TX */
 				mrc_alt_write_mask(DDRPHY,
-					(DQCTL +
-					(bl_grp * DDRIODQ_BL_OFFSET) +
-					(ch * DDRIODQ_CH_OFFSET)),
-					(BIT16), (BIT16));
+					DQCTL +
+					bl_grp * DDRIODQ_BL_OFFSET +
+					ch * DDRIODQ_CH_OFFSET,
+					1 << 16, 1 << 16);
 				mrc_alt_write_mask(DDRPHY,
-					(B01PTRCTL1 +
-					(bl_grp * DDRIODQ_BL_OFFSET) +
-					(ch * DDRIODQ_CH_OFFSET)),
-					(BIT8), (BIT8));
+					B01PTRCTL1 +
+					bl_grp * DDRIODQ_BL_OFFSET +
+					ch * DDRIODQ_CH_OFFSET,
+					1 << 8, 1 << 8);
 
 				/* RX (PO) */
 				/* Internal Vref Code, Enable#, Ext_or_Int (1=Ext) */
 				mrc_alt_write_mask(DDRPHY,
-					(B0VREFCTL +
-					(bl_grp * DDRIODQ_BL_OFFSET) +
-					(ch * DDRIODQ_CH_OFFSET)),
-					((0x03 << 2) | (0x0 << 1) | (0x0 << 0)),
-					(BIT7 | BIT6 | BIT5 | BIT4 | BIT3 |
-					BIT2 | BIT1 | BIT0));
+					B0VREFCTL +
+					bl_grp * DDRIODQ_BL_OFFSET +
+					ch * DDRIODQ_CH_OFFSET,
+					(0x03 << 2) | (0x0 << 1) | (0x0 << 0),
+					0xff);
 				/* Internal Vref Code, Enable#, Ext_or_Int (1=Ext) */
 				mrc_alt_write_mask(DDRPHY,
-					(B1VREFCTL +
-					(bl_grp * DDRIODQ_BL_OFFSET) +
-					(ch * DDRIODQ_CH_OFFSET)),
-					((0x03 << 2) | (0x0 << 1) | (0x0 << 0)),
-					(BIT7 | BIT6 | BIT5 | BIT4 | BIT3 |
-					BIT2 | BIT1 | BIT0));
+					B1VREFCTL +
+					bl_grp * DDRIODQ_BL_OFFSET +
+					ch * DDRIODQ_CH_OFFSET,
+					(0x03 << 2) | (0x0 << 1) | (0x0 << 0),
+					0xff);
 				/* Per-Bit De-Skew Enable */
 				mrc_alt_write_mask(DDRPHY,
-					(B0RXIOBUFCTL +
-					(bl_grp * DDRIODQ_BL_OFFSET) +
-					(ch * DDRIODQ_CH_OFFSET)),
-					(0), (BIT4));
+					B0RXIOBUFCTL +
+					bl_grp * DDRIODQ_BL_OFFSET +
+					ch * DDRIODQ_CH_OFFSET,
+					0, 0x10);
 				/* Per-Bit De-Skew Enable */
 				mrc_alt_write_mask(DDRPHY,
-					(B1RXIOBUFCTL +
-					(bl_grp * DDRIODQ_BL_OFFSET) +
-					(ch * DDRIODQ_CH_OFFSET)),
-					(0), (BIT4));
+					B1RXIOBUFCTL +
+					bl_grp * DDRIODQ_BL_OFFSET +
+					ch * DDRIODQ_CH_OFFSET,
+					0, 0x10);
 			}
 
 			/* CLKEBB */
 			mrc_alt_write_mask(DDRPHY,
-				(CMDOBSCKEBBCTL + (ch * DDRIOCCC_CH_OFFSET)),
-				0, (BIT23));
+				CMDOBSCKEBBCTL + ch * DDRIOCCC_CH_OFFSET,
+				0, 1 << 23);
 
 			/* Enable tristate control of cmd/address bus */
 			mrc_alt_write_mask(DDRPHY,
-				(CMDCFGREG0 + (ch * DDRIOCCC_CH_OFFSET)),
-				0, (BIT1 | BIT0));
+				CMDCFGREG0 + ch * DDRIOCCC_CH_OFFSET,
+				0, 0x03);
 
 			/* ODT RCOMP */
 			mrc_alt_write_mask(DDRPHY,
-				(CMDRCOMPODT + (ch * DDRIOCCC_CH_OFFSET)),
-				((0x03 << 5) | (0x03 << 0)),
-				(BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 |
-				BIT3 | BIT2 | BIT1 | BIT0));
+				CMDRCOMPODT + ch * DDRIOCCC_CH_OFFSET,
+				(0x03 << 5) | (0x03 << 0), 0x3ff);
 
 			/* CMDPM* registers must be programmed in this order */
 
 			/* Turn On Delays: SFR (regulator), MPLL */
 			mrc_alt_write_mask(DDRPHY,
-				(CMDPMDLYREG4 + (ch * DDRIOCCC_CH_OFFSET)),
-				((0xFFFFU << 16) | (0xFFFF << 0)),
-				0xFFFFFFFF);
+				CMDPMDLYREG4 + ch * DDRIOCCC_CH_OFFSET,
+				0xffffffff, 0xffffffff);
 			/*
 			 * Delays: ASSERT_IOBUFACT_to_ALLON0_for_PM_MSG_3,
 			 * VREG (MDLL) Turn On, ALLON0_to_DEASSERT_IOBUFACT
 			 * for_PM_MSG_gt0, MDLL Turn On
 			 */
 			mrc_alt_write_mask(DDRPHY,
-				(CMDPMDLYREG3 + (ch * DDRIOCCC_CH_OFFSET)),
-				((0xFU << 28) | (0xFFF << 16) | (0xF << 12) |
-				(0x616 << 0)), 0xFFFFFFFF);
+				CMDPMDLYREG3 + ch * DDRIOCCC_CH_OFFSET,
+				0xfffff616, 0xffffffff);
 			/* MPLL Divider Reset Delays */
 			mrc_alt_write_mask(DDRPHY,
-				(CMDPMDLYREG2 + (ch * DDRIOCCC_CH_OFFSET)),
-				((0xFFU << 24) | (0xFF << 16) | (0xFF << 8) |
-				(0xFF << 0)), 0xFFFFFFFF);
+				CMDPMDLYREG2 + ch * DDRIOCCC_CH_OFFSET,
+				0xffffffff, 0xffffffff);
 			/* Turn Off Delays: VREG, Staggered MDLL, MDLL, PI */
 			mrc_alt_write_mask(DDRPHY,
-				(CMDPMDLYREG1 + (ch * DDRIOCCC_CH_OFFSET)),
-				((0xFFU << 24) | (0xFF << 16) | (0xFF << 8) |
-				(0xFF << 0)), 0xFFFFFFFF);
+				CMDPMDLYREG1 + ch * DDRIOCCC_CH_OFFSET,
+				0xffffffff, 0xffffffff);
 			/* Turn On Delays: MPLL, Staggered MDLL, PI, IOBUFACT */
 			mrc_alt_write_mask(DDRPHY,
-				(CMDPMDLYREG0 + (ch * DDRIOCCC_CH_OFFSET)),
-				((0xFFU << 24) | (0xFF << 16) | (0xFF << 8) |
-				(0xFF << 0)), 0xFFFFFFFF);
+				CMDPMDLYREG0 + ch * DDRIOCCC_CH_OFFSET,
+				0xffffffff, 0xffffffff);
 			/* Allow PUnit signals */
 			mrc_alt_write_mask(DDRPHY,
-				(CMDPMCONFIG0 + (ch * DDRIOCCC_CH_OFFSET)),
-				((0x6 << 8) | BIT6 | (0x4 << 0)),
-				(BIT31 | BIT30 | BIT29 | BIT28 | BIT27 | BIT26 |
-				BIT25 | BIT24 | BIT23 | BIT22 | BIT21 | BIT11 |
-				BIT10 | BIT9 | BIT8 | BIT6 | BIT3 | BIT2 |
-				BIT1 | BIT0));
+				CMDPMCONFIG0 + ch * DDRIOCCC_CH_OFFSET,
+				(0x6 << 8) | (0x1 << 6) | (0x4 << 0),
+				0xffe00f4f);
 			/* DLL_VREG Bias Trim, VREF Tuning for DLL_VREG */
 			mrc_alt_write_mask(DDRPHY,
-				(CMDMDLLCTL + (ch * DDRIOCCC_CH_OFFSET)),
-				((0x3 << 4) | (0x7 << 0)),
-				(BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 |
-				BIT0));
+				CMDMDLLCTL + ch * DDRIOCCC_CH_OFFSET,
+				(0x3 << 4) | (0x7 << 0), 0x7f);
 
 			/* CLK-CTL */
 			mrc_alt_write_mask(DDRPHY,
-				(CCOBSCKEBBCTL + (ch * DDRIOCCC_CH_OFFSET)),
-				0, BIT24);	/* CLKEBB */
+				CCOBSCKEBBCTL + ch * DDRIOCCC_CH_OFFSET,
+				0, 1 << 24);	/* CLKEBB */
 			/* Buffer Enable: CS,CKE,ODT,CLK */
 			mrc_alt_write_mask(DDRPHY,
-				(CCCFGREG0 + (ch * DDRIOCCC_CH_OFFSET)),
-				((0x0 << 16) | (0x0 << 12) | (0x0 << 8) |
-				(0xF << 4) | BIT0),
-				(BIT19 | BIT18 | BIT17 | BIT16 | BIT15 | BIT14 |
-				BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8 |
-				BIT7 | BIT6 | BIT5 | BIT4 | BIT0));
+				CCCFGREG0 + ch * DDRIOCCC_CH_OFFSET,
+				0x1f, 0x000ffff1);
 			/* ODT RCOMP */
 			mrc_alt_write_mask(DDRPHY,
-				(CCRCOMPODT + (ch * DDRIOCCC_CH_OFFSET)),
-				((0x03 << 8) | (0x03 << 0)),
-				(BIT12 | BIT11 | BIT10 | BIT9 | BIT8 | BIT4 |
-				BIT3 | BIT2 | BIT1 | BIT0));
+				CCRCOMPODT + ch * DDRIOCCC_CH_OFFSET,
+				(0x03 << 8) | (0x03 << 0), 0x00001f1f);
 			/* DLL_VREG Bias Trim, VREF Tuning for DLL_VREG */
 			mrc_alt_write_mask(DDRPHY,
-				(CCMDLLCTL + (ch * DDRIOCCC_CH_OFFSET)),
-				((0x3 << 4) | (0x7 << 0)),
-				(BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 |
-				BIT0));
+				CCMDLLCTL + ch * DDRIOCCC_CH_OFFSET,
+				(0x3 << 4) | (0x7 << 0), 0x7f);
 
 			/*
 			 * COMP (RON channel specific)
@@ -618,66 +570,43 @@
 			 */
 			/* RCOMP Vref PU/PD */
 			mrc_alt_write_mask(DDRPHY,
-				(DQVREFCH0 +  (ch * DDRCOMP_CH_OFFSET)),
-				((0x08 << 24) | (0x03 << 16)),
-				(BIT29 | BIT28 | BIT27 | BIT26 | BIT25 |
-				BIT24 | BIT21 | BIT20 | BIT19 | BIT18 |
-				BIT17 | BIT16));
+				DQVREFCH0 +  ch * DDRCOMP_CH_OFFSET,
+				(0x08 << 24) | (0x03 << 16), 0x3f3f0000);
 			/* RCOMP Vref PU/PD */
 			mrc_alt_write_mask(DDRPHY,
-				(CMDVREFCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				((0x0C << 24) | (0x03 << 16)),
-				(BIT29 | BIT28 | BIT27 | BIT26 | BIT25 |
-				BIT24 | BIT21 | BIT20 | BIT19 | BIT18 |
-				BIT17 | BIT16));
+				CMDVREFCH0 + ch * DDRCOMP_CH_OFFSET,
+				(0x0C << 24) | (0x03 << 16), 0x3f3f0000);
 			/* RCOMP Vref PU/PD */
 			mrc_alt_write_mask(DDRPHY,
-				(CLKVREFCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				((0x0F << 24) | (0x03 << 16)),
-				(BIT29 | BIT28 | BIT27 | BIT26 | BIT25 |
-				BIT24 | BIT21 | BIT20 | BIT19 | BIT18 |
-				BIT17 | BIT16));
+				CLKVREFCH0 + ch * DDRCOMP_CH_OFFSET,
+				(0x0F << 24) | (0x03 << 16), 0x3f3f0000);
 			/* RCOMP Vref PU/PD */
 			mrc_alt_write_mask(DDRPHY,
-				(DQSVREFCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				((0x08 << 24) | (0x03 << 16)),
-				(BIT29 | BIT28 | BIT27 | BIT26 | BIT25 |
-				BIT24 | BIT21 | BIT20 | BIT19 | BIT18 |
-				BIT17 | BIT16));
+				DQSVREFCH0 + ch * DDRCOMP_CH_OFFSET,
+				(0x08 << 24) | (0x03 << 16), 0x3f3f0000);
 			/* RCOMP Vref PU/PD */
 			mrc_alt_write_mask(DDRPHY,
-				(CTLVREFCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				((0x0C << 24) | (0x03 << 16)),
-				(BIT29 | BIT28 | BIT27 | BIT26 | BIT25 |
-				BIT24 | BIT21 | BIT20 | BIT19 | BIT18 |
-				BIT17 | BIT16));
+				CTLVREFCH0 + ch * DDRCOMP_CH_OFFSET,
+				(0x0C << 24) | (0x03 << 16), 0x3f3f0000);
 
 			/* DQS Swapped Input Enable */
 			mrc_alt_write_mask(DDRPHY,
-				(COMPEN1CH0 + (ch * DDRCOMP_CH_OFFSET)),
-				(BIT19 | BIT17),
-				(BIT31 | BIT30 | BIT19 | BIT17 |
-				BIT15 | BIT14));
+				COMPEN1CH0 + ch * DDRCOMP_CH_OFFSET,
+				(1 << 19) | (1 << 17), 0xc00ac000);
 
 			/* ODT VREF = 1.5 x 274/360+274 = 0.65V (code of ~50) */
 			/* ODT Vref PU/PD */
 			mrc_alt_write_mask(DDRPHY,
-				(DQVREFCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				((0x32 << 8) | (0x03 << 0)),
-				(BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8 |
-				BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0));
+				DQVREFCH0 + ch * DDRCOMP_CH_OFFSET,
+				(0x32 << 8) | (0x03 << 0), 0x00003f3f);
 			/* ODT Vref PU/PD */
 			mrc_alt_write_mask(DDRPHY,
-				(DQSVREFCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				((0x32 << 8) | (0x03 << 0)),
-				(BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8 |
-				BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0));
+				DQSVREFCH0 + ch * DDRCOMP_CH_OFFSET,
+				(0x32 << 8) | (0x03 << 0), 0x00003f3f);
 			/* ODT Vref PU/PD */
 			mrc_alt_write_mask(DDRPHY,
-				(CLKVREFCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				((0x0E << 8) | (0x05 << 0)),
-				(BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8 |
-				BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0));
+				CLKVREFCH0 + ch * DDRCOMP_CH_OFFSET,
+				(0x0E << 8) | (0x05 << 0), 0x00003f3f);
 
 			/*
 			 * Slew rate settings are frequency specific,
@@ -685,273 +614,227 @@
 			 * - DQ/DQS/DM/CLK SR: 4V/ns,
 			 * - CTRL/CMD SR: 1.5V/ns
 			 */
-			temp = (0x0E << 16) | (0x0E << 12) | (0x08 << 8) |
-				(0x0B << 4) | (0x0B << 0);
+			temp = (0x0e << 16) | (0x0e << 12) | (0x08 << 8) |
+				(0x0b << 4) | (0x0b << 0);
 			/* DCOMP Delay Select: CTL,CMD,CLK,DQS,DQ */
 			mrc_alt_write_mask(DDRPHY,
-				(DLYSELCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				temp,
-				(BIT19 | BIT18 | BIT17 | BIT16 | BIT15 |
-				BIT14 | BIT13 | BIT12 | BIT11 | BIT10 |
-				BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 |
-				BIT3 | BIT2 | BIT1 | BIT0));
+				DLYSELCH0 + ch * DDRCOMP_CH_OFFSET,
+				temp, 0x000fffff);
 			/* TCO Vref CLK,DQS,DQ */
 			mrc_alt_write_mask(DDRPHY,
-				(TCOVREFCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				((0x05 << 16) | (0x05 << 8) | (0x05 << 0)),
-				(BIT21 | BIT20 | BIT19 | BIT18 | BIT17 |
-				BIT16 | BIT13 | BIT12 | BIT11 | BIT10 |
-				BIT9 | BIT8 | BIT5 | BIT4 | BIT3 | BIT2 |
-				BIT1 | BIT0));
+				TCOVREFCH0 + ch * DDRCOMP_CH_OFFSET,
+				(0x05 << 16) | (0x05 << 8) | (0x05 << 0),
+				0x003f3f3f);
 			/* ODTCOMP CMD/CTL PU/PD */
 			mrc_alt_write_mask(DDRPHY,
-				(CCBUFODTCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				((0x03 << 8) | (0x03 << 0)),
-				(BIT12 | BIT11 | BIT10 | BIT9 | BIT8 |
-				BIT4 | BIT3 | BIT2 | BIT1 | BIT0));
+				CCBUFODTCH0 + ch * DDRCOMP_CH_OFFSET,
+				(0x03 << 8) | (0x03 << 0),
+				0x00001f1f);
 			/* COMP */
 			mrc_alt_write_mask(DDRPHY,
-				(COMPEN0CH0 + (ch * DDRCOMP_CH_OFFSET)),
-				0, (BIT31 | BIT30 | BIT8));
+				COMPEN0CH0 + ch * DDRCOMP_CH_OFFSET,
+				0, 0xc0000100);
 
 #ifdef BACKUP_COMPS
 			/* DQ COMP Overrides */
 			/* RCOMP PU */
 			mrc_alt_write_mask(DDRPHY,
-				(DQDRVPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				(BIT31 | (0x0A << 16)),
-				(BIT31 | BIT20 | BIT19 |
-				BIT18 | BIT17 | BIT16));
+				DQDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET,
+				(1 << 31) | (0x0a << 16),
+				0x801f0000);
 			/* RCOMP PD */
 			mrc_alt_write_mask(DDRPHY,
-				(DQDRVPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				(BIT31 | (0x0A << 16)),
-				(BIT31 | BIT20 | BIT19 |
-				BIT18 | BIT17 | BIT16));
+				DQDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET,
+				(1 << 31) | (0x0a << 16),
+				0x801f0000);
 			/* DCOMP PU */
 			mrc_alt_write_mask(DDRPHY,
-				(DQDLYPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				(BIT31 | (0x10 << 16)),
-				(BIT31 | BIT20 | BIT19 |
-				BIT18 | BIT17 | BIT16));
+				DQDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET,
+				(1 << 31) | (0x10 << 16),
+				0x801f0000);
 			/* DCOMP PD */
 			mrc_alt_write_mask(DDRPHY,
-				(DQDLYPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				(BIT31 | (0x10 << 16)),
-				(BIT31 | BIT20 | BIT19 |
-				BIT18 | BIT17 | BIT16));
+				DQDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET,
+				(1 << 31) | (0x10 << 16),
+				0x801f0000);
 			/* ODTCOMP PU */
 			mrc_alt_write_mask(DDRPHY,
-				(DQODTPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				(BIT31 | (0x0B << 16)),
-				(BIT31 | BIT20 | BIT19 |
-				BIT18 | BIT17 | BIT16));
+				DQODTPUCTLCH0 + ch * DDRCOMP_CH_OFFSET,
+				(1 << 31) | (0x0b << 16),
+				0x801f0000);
 			/* ODTCOMP PD */
 			mrc_alt_write_mask(DDRPHY,
-				(DQODTPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				(BIT31 | (0x0B << 16)),
-				(BIT31 | BIT20 | BIT19 |
-				BIT18 | BIT17 | BIT16));
+				DQODTPDCTLCH0 + ch * DDRCOMP_CH_OFFSET,
+				(1 << 31) | (0x0b << 16),
+				0x801f0000);
 			/* TCOCOMP PU */
 			mrc_alt_write_mask(DDRPHY,
-				(DQTCOPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				(BIT31), (BIT31));
+				DQTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET,
+				1 << 31, 1 << 31);
 			/* TCOCOMP PD */
 			mrc_alt_write_mask(DDRPHY,
-				(DQTCOPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				(BIT31), (BIT31));
+				DQTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET,
+				1 << 31, 1 << 31);
 
 			/* DQS COMP Overrides */
 			/* RCOMP PU */
 			mrc_alt_write_mask(DDRPHY,
-				(DQSDRVPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				(BIT31 | (0x0A << 16)),
-				(BIT31 | BIT20 | BIT19 |
-				BIT18 | BIT17 | BIT16));
+				DQSDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET,
+				(1 << 31) | (0x0a << 16),
+				0x801f0000);
 			/* RCOMP PD */
 			mrc_alt_write_mask(DDRPHY,
-				(DQSDRVPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				(BIT31 | (0x0A << 16)),
-				(BIT31 | BIT20 | BIT19 |
-				BIT18 | BIT17 | BIT16));
+				DQSDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET,
+				(1 << 31) | (0x0a << 16),
+				0x801f0000);
 			/* DCOMP PU */
 			mrc_alt_write_mask(DDRPHY,
-				(DQSDLYPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				(BIT31 | (0x10 << 16)),
-				(BIT31 | BIT20 | BIT19 |
-				BIT18 | BIT17 | BIT16));
+				DQSDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET,
+				(1 << 31) | (0x10 << 16),
+				0x801f0000);
 			/* DCOMP PD */
 			mrc_alt_write_mask(DDRPHY,
-				(DQSDLYPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				(BIT31 | (0x10 << 16)),
-				(BIT31 | BIT20 | BIT19 |
-				BIT18 | BIT17 | BIT16));
+				DQSDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET,
+				(1 << 31) | (0x10 << 16),
+				0x801f0000);
 			/* ODTCOMP PU */
 			mrc_alt_write_mask(DDRPHY,
-				(DQSODTPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				(BIT31 | (0x0B << 16)),
-				(BIT31 | BIT20 | BIT19 |
-				BIT18 | BIT17 | BIT16));
+				DQSODTPUCTLCH0 + ch * DDRCOMP_CH_OFFSET,
+				(1 << 31) | (0x0b << 16),
+				0x801f0000);
 			/* ODTCOMP PD */
 			mrc_alt_write_mask(DDRPHY,
-				(DQSODTPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				(BIT31 | (0x0B << 16)),
-				(BIT31 | BIT20 | BIT19 |
-				BIT18 | BIT17 | BIT16));
+				DQSODTPDCTLCH0 + ch * DDRCOMP_CH_OFFSET,
+				(1 << 31) | (0x0b << 16),
+				0x801f0000);
 			/* TCOCOMP PU */
 			mrc_alt_write_mask(DDRPHY,
-				(DQSTCOPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				(BIT31), (BIT31));
+				DQSTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET,
+				1 << 31, 1 << 31);
 			/* TCOCOMP PD */
 			mrc_alt_write_mask(DDRPHY,
-				(DQSTCOPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				(BIT31), (BIT31));
+				DQSTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET,
+				1 << 31, 1 << 31);
 
 			/* CLK COMP Overrides */
 			/* RCOMP PU */
 			mrc_alt_write_mask(DDRPHY,
-				(CLKDRVPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				(BIT31 | (0x0C << 16)),
-				(BIT31 | (0x0B << 16)),
-				(BIT31 | BIT20 | BIT19 |
-				BIT18 | BIT17 | BIT16));
+				CLKDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET,
+				(1 << 31) | (0x0c << 16),
+				0x801f0000);
 			/* RCOMP PD */
 			mrc_alt_write_mask(DDRPHY,
-				(CLKDRVPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				(BIT31 | (0x0C << 16)),
-				(BIT31 | (0x0B << 16)),
-				(BIT31 | BIT20 | BIT19 |
-				BIT18 | BIT17 | BIT16));
+				CLKDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET,
+				(1 << 31) | (0x0c << 16),
+				0x801f0000);
 			/* DCOMP PU */
 			mrc_alt_write_mask(DDRPHY,
-				(CLKDLYPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				(BIT31 | (0x07 << 16)),
-				(BIT31 | (0x0B << 16)),
-				(BIT31 | BIT20 | BIT19 |
-				BIT18 | BIT17 | BIT16));
+				CLKDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET,
+				(1 << 31) | (0x07 << 16),
+				0x801f0000);
 			/* DCOMP PD */
 			mrc_alt_write_mask(DDRPHY,
-				(CLKDLYPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				(BIT31 | (0x07 << 16)),
-				(BIT31 | (0x0B << 16)),
-				(BIT31 | BIT20 | BIT19 |
-				BIT18 | BIT17 | BIT16));
+				CLKDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET,
+				(1 << 31) | (0x07 << 16),
+				0x801f0000);
 			/* ODTCOMP PU */
 			mrc_alt_write_mask(DDRPHY,
-				(CLKODTPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				(BIT31 | (0x0B << 16)),
-				(BIT31 | (0x0B << 16)),
-				(BIT31 | BIT20 | BIT19 |
-				BIT18 | BIT17 | BIT16));
+				CLKODTPUCTLCH0 + ch * DDRCOMP_CH_OFFSET,
+				(1 << 31) | (0x0b << 16),
+				0x801f0000);
 			/* ODTCOMP PD */
 			mrc_alt_write_mask(DDRPHY,
-				(CLKODTPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				(BIT31 | (0x0B << 16)),
-				(BIT31 | (0x0B << 16)),
-				(BIT31 | BIT20 | BIT19 |
-				BIT18 | BIT17 | BIT16));
+				CLKODTPDCTLCH0 + ch * DDRCOMP_CH_OFFSET,
+				(1 << 31) | (0x0b << 16),
+				0x801f0000);
 			/* TCOCOMP PU */
 			mrc_alt_write_mask(DDRPHY,
-				(CLKTCOPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				(BIT31), (BIT31));
+				CLKTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET,
+				1 << 31, 1 << 31);
 			/* TCOCOMP PD */
 			mrc_alt_write_mask(DDRPHY,
-				(CLKTCOPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				(BIT31), (BIT31));
+				CLKTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET,
+				1 << 31, 1 << 31);
 
 			/* CMD COMP Overrides */
 			/* RCOMP PU */
 			mrc_alt_write_mask(DDRPHY,
-				(CMDDRVPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				(BIT31 | (0x0D << 16)),
-				(BIT31 | BIT21 | BIT20 | BIT19 |
-				BIT18 | BIT17 | BIT16));
+				CMDDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET,
+				(1 << 31) | (0x0d << 16),
+				0x803f0000);
 			/* RCOMP PD */
 			mrc_alt_write_mask(DDRPHY,
-				(CMDDRVPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				(BIT31 | (0x0D << 16)),
-				(BIT31 | BIT21 | BIT20 | BIT19 |
-				BIT18 | BIT17 | BIT16));
+				CMDDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET,
+				(1 << 31) | (0x0d << 16),
+				0x803f0000);
 			/* DCOMP PU */
 			mrc_alt_write_mask(DDRPHY,
-				(CMDDLYPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				(BIT31 | (0x0A << 16)),
-				(BIT31 | BIT20 | BIT19 |
-				BIT18 | BIT17 | BIT16));
+				CMDDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET,
+				(1 << 31) | (0x0a << 16),
+				0x801f0000);
 			/* DCOMP PD */
 			mrc_alt_write_mask(DDRPHY,
-				(CMDDLYPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				(BIT31 | (0x0A << 16)),
-				(BIT31 | BIT20 | BIT19 |
-				BIT18 | BIT17 | BIT16));
+				CMDDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET,
+				(1 << 31) | (0x0a << 16),
+				0x801f0000);
 
 			/* CTL COMP Overrides */
 			/* RCOMP PU */
 			mrc_alt_write_mask(DDRPHY,
-				(CTLDRVPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				(BIT31 | (0x0D << 16)),
-				(BIT31 | BIT21 | BIT20 | BIT19 |
-				BIT18 | BIT17 | BIT16));
+				CTLDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET,
+				(1 << 31) | (0x0d << 16),
+				0x803f0000);
 			/* RCOMP PD */
 			mrc_alt_write_mask(DDRPHY,
-				(CTLDRVPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				(BIT31 | (0x0D << 16)),
-				(BIT31 | BIT21 | BIT20 | BIT19 |
-				BIT18 | BIT17 | BIT16));
+				CTLDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET,
+				(1 << 31) | (0x0d << 16),
+				0x803f0000);
 			/* DCOMP PU */
 			mrc_alt_write_mask(DDRPHY,
-				(CTLDLYPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				(BIT31 | (0x0A << 16)),
-				(BIT31 | BIT20 | BIT19 |
-				BIT18 | BIT17 | BIT16));
+				CTLDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET,
+				(1 << 31) | (0x0a << 16),
+				0x801f0000);
 			/* DCOMP PD */
 			mrc_alt_write_mask(DDRPHY,
-				(CTLDLYPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				(BIT31 | (0x0A << 16)),
-				(BIT31 | BIT20 | BIT19 |
-				BIT18 | BIT17 | BIT16));
+				CTLDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET,
+				(1 << 31) | (0x0a << 16),
+				0x801f0000);
 #else
 			/* DQ TCOCOMP Overrides */
 			/* TCOCOMP PU */
 			mrc_alt_write_mask(DDRPHY,
-				(DQTCOPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				(BIT31 | (0x1F << 16)),
-				(BIT31 | BIT20 | BIT19 |
-				BIT18 | BIT17 | BIT16));
+				DQTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET,
+				(1 << 31) | (0x1f << 16),
+				0x801f0000);
 			/* TCOCOMP PD */
 			mrc_alt_write_mask(DDRPHY,
-				(DQTCOPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				(BIT31 | (0x1F << 16)),
-				(BIT31 | BIT20 | BIT19 |
-				BIT18 | BIT17 | BIT16));
+				DQTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET,
+				(1 << 31) | (0x1f << 16),
+				0x801f0000);
 
 			/* DQS TCOCOMP Overrides */
 			/* TCOCOMP PU */
 			mrc_alt_write_mask(DDRPHY,
-				(DQSTCOPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				(BIT31 | (0x1F << 16)),
-				(BIT31 | BIT20 | BIT19 |
-				BIT18 | BIT17 | BIT16));
+				DQSTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET,
+				(1 << 31) | (0x1f << 16),
+				0x801f0000);
 			/* TCOCOMP PD */
 			mrc_alt_write_mask(DDRPHY,
-				(DQSTCOPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				(BIT31 | (0x1F << 16)),
-				(BIT31 | BIT20 | BIT19 |
-				BIT18 | BIT17 | BIT16));
+				DQSTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET,
+				(1 << 31) | (0x1f << 16),
+				0x801f0000);
 
 			/* CLK TCOCOMP Overrides */
 			/* TCOCOMP PU */
 			mrc_alt_write_mask(DDRPHY,
-				(CLKTCOPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				(BIT31 | (0x1F << 16)),
-				(BIT31 | BIT20 | BIT19 |
-				BIT18 | BIT17 | BIT16));
+				CLKTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET,
+				(1 << 31) | (0x1f << 16),
+				0x801f0000);
 			/* TCOCOMP PD */
 			mrc_alt_write_mask(DDRPHY,
-				(CLKTCOPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
-				(BIT31 | (0x1F << 16)),
-				(BIT31 | BIT20 | BIT19 |
-				BIT18 | BIT17 | BIT16));
+				CLKTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET,
+				(1 << 31) | (0x1f << 16),
+				0x801f0000);
 #endif
 
 			/* program STATIC delays */
@@ -962,7 +845,7 @@
 #endif
 
 			for (rk = 0; rk < NUM_RANKS; rk++) {
-				if (mrc_params->rank_enables & (1<<rk)) {
+				if (mrc_params->rank_enables & (1 << rk)) {
 					set_wclk(ch, rk, ddr_wclk[PLATFORM_ID]);
 #ifdef BACKUP_WCTL
 					set_wctl(ch, rk, ddr_wctl[PLATFORM_ID]);
@@ -976,86 +859,80 @@
 
 	/* COMP (non channel specific) */
 	/* RCOMP: Dither PU Enable */
-	mrc_alt_write_mask(DDRPHY, (DQANADRVPUCTL), (BIT30), (BIT30));
+	mrc_alt_write_mask(DDRPHY, DQANADRVPUCTL, 1 << 30, 1 << 30);
 	/* RCOMP: Dither PD Enable */
-	mrc_alt_write_mask(DDRPHY, (DQANADRVPDCTL), (BIT30), (BIT30));
+	mrc_alt_write_mask(DDRPHY, DQANADRVPDCTL, 1 << 30, 1 << 30);
 	/* RCOMP: Dither PU Enable */
-	mrc_alt_write_mask(DDRPHY, (CMDANADRVPUCTL), (BIT30), (BIT30));
+	mrc_alt_write_mask(DDRPHY, CMDANADRVPUCTL, 1 << 30, 1 << 30);
 	/* RCOMP: Dither PD Enable */
-	mrc_alt_write_mask(DDRPHY, (CMDANADRVPDCTL), (BIT30), (BIT30));
+	mrc_alt_write_mask(DDRPHY, CMDANADRVPDCTL, 1 << 30, 1 << 30);
 	/* RCOMP: Dither PU Enable */
-	mrc_alt_write_mask(DDRPHY, (CLKANADRVPUCTL), (BIT30), (BIT30));
+	mrc_alt_write_mask(DDRPHY, CLKANADRVPUCTL, 1 << 30, 1 << 30);
 	/* RCOMP: Dither PD Enable */
-	mrc_alt_write_mask(DDRPHY, (CLKANADRVPDCTL), (BIT30), (BIT30));
+	mrc_alt_write_mask(DDRPHY, CLKANADRVPDCTL, 1 << 30, 1 << 30);
 	/* RCOMP: Dither PU Enable */
-	mrc_alt_write_mask(DDRPHY, (DQSANADRVPUCTL), (BIT30), (BIT30));
+	mrc_alt_write_mask(DDRPHY, DQSANADRVPUCTL, 1 << 30, 1 << 30);
 	/* RCOMP: Dither PD Enable */
-	mrc_alt_write_mask(DDRPHY, (DQSANADRVPDCTL), (BIT30), (BIT30));
+	mrc_alt_write_mask(DDRPHY, DQSANADRVPDCTL, 1 << 30, 1 << 30);
 	/* RCOMP: Dither PU Enable */
-	mrc_alt_write_mask(DDRPHY, (CTLANADRVPUCTL), (BIT30), (BIT30));
+	mrc_alt_write_mask(DDRPHY, CTLANADRVPUCTL, 1 << 30, 1 << 30);
 	/* RCOMP: Dither PD Enable */
-	mrc_alt_write_mask(DDRPHY, (CTLANADRVPDCTL), (BIT30), (BIT30));
+	mrc_alt_write_mask(DDRPHY, CTLANADRVPDCTL, 1 << 30, 1 << 30);
 	/* ODT: Dither PU Enable */
-	mrc_alt_write_mask(DDRPHY, (DQANAODTPUCTL), (BIT30), (BIT30));
+	mrc_alt_write_mask(DDRPHY, DQANAODTPUCTL, 1 << 30, 1 << 30);
 	/* ODT: Dither PD Enable */
-	mrc_alt_write_mask(DDRPHY, (DQANAODTPDCTL), (BIT30), (BIT30));
+	mrc_alt_write_mask(DDRPHY, DQANAODTPDCTL, 1 << 30, 1 << 30);
 	/* ODT: Dither PU Enable */
-	mrc_alt_write_mask(DDRPHY, (CLKANAODTPUCTL), (BIT30), (BIT30));
+	mrc_alt_write_mask(DDRPHY, CLKANAODTPUCTL, 1 << 30, 1 << 30);
 	/* ODT: Dither PD Enable */
-	mrc_alt_write_mask(DDRPHY, (CLKANAODTPDCTL), (BIT30), (BIT30));
+	mrc_alt_write_mask(DDRPHY, CLKANAODTPDCTL, 1 << 30, 1 << 30);
 	/* ODT: Dither PU Enable */
-	mrc_alt_write_mask(DDRPHY, (DQSANAODTPUCTL), (BIT30), (BIT30));
+	mrc_alt_write_mask(DDRPHY, DQSANAODTPUCTL, 1 << 30, 1 << 30);
 	/* ODT: Dither PD Enable */
-	mrc_alt_write_mask(DDRPHY, (DQSANAODTPDCTL), (BIT30), (BIT30));
+	mrc_alt_write_mask(DDRPHY, DQSANAODTPDCTL, 1 << 30, 1 << 30);
 	/* DCOMP: Dither PU Enable */
-	mrc_alt_write_mask(DDRPHY, (DQANADLYPUCTL), (BIT30), (BIT30));
+	mrc_alt_write_mask(DDRPHY, DQANADLYPUCTL, 1 << 30, 1 << 30);
 	/* DCOMP: Dither PD Enable */
-	mrc_alt_write_mask(DDRPHY, (DQANADLYPDCTL), (BIT30), (BIT30));
+	mrc_alt_write_mask(DDRPHY, DQANADLYPDCTL, 1 << 30, 1 << 30);
 	/* DCOMP: Dither PU Enable */
-	mrc_alt_write_mask(DDRPHY, (CMDANADLYPUCTL), (BIT30), (BIT30));
+	mrc_alt_write_mask(DDRPHY, CMDANADLYPUCTL, 1 << 30, 1 << 30);
 	/* DCOMP: Dither PD Enable */
-	mrc_alt_write_mask(DDRPHY, (CMDANADLYPDCTL), (BIT30), (BIT30));
+	mrc_alt_write_mask(DDRPHY, CMDANADLYPDCTL, 1 << 30, 1 << 30);
 	/* DCOMP: Dither PU Enable */
-	mrc_alt_write_mask(DDRPHY, (CLKANADLYPUCTL), (BIT30), (BIT30));
+	mrc_alt_write_mask(DDRPHY, CLKANADLYPUCTL, 1 << 30, 1 << 30);
 	/* DCOMP: Dither PD Enable */
-	mrc_alt_write_mask(DDRPHY, (CLKANADLYPDCTL), (BIT30), (BIT30));
+	mrc_alt_write_mask(DDRPHY, CLKANADLYPDCTL, 1 << 30, 1 << 30);
 	/* DCOMP: Dither PU Enable */
-	mrc_alt_write_mask(DDRPHY, (DQSANADLYPUCTL), (BIT30), (BIT30));
+	mrc_alt_write_mask(DDRPHY, DQSANADLYPUCTL, 1 << 30, 1 << 30);
 	/* DCOMP: Dither PD Enable */
-	mrc_alt_write_mask(DDRPHY, (DQSANADLYPDCTL), (BIT30), (BIT30));
+	mrc_alt_write_mask(DDRPHY, DQSANADLYPDCTL, 1 << 30, 1 << 30);
 	/* DCOMP: Dither PU Enable */
-	mrc_alt_write_mask(DDRPHY, (CTLANADLYPUCTL), (BIT30), (BIT30));
+	mrc_alt_write_mask(DDRPHY, CTLANADLYPUCTL, 1 << 30, 1 << 30);
 	/* DCOMP: Dither PD Enable */
-	mrc_alt_write_mask(DDRPHY, (CTLANADLYPDCTL), (BIT30), (BIT30));
+	mrc_alt_write_mask(DDRPHY, CTLANADLYPDCTL, 1 << 30, 1 << 30);
 	/* TCO: Dither PU Enable */
-	mrc_alt_write_mask(DDRPHY, (DQANATCOPUCTL), (BIT30), (BIT30));
+	mrc_alt_write_mask(DDRPHY, DQANATCOPUCTL, 1 << 30, 1 << 30);
 	/* TCO: Dither PD Enable */
-	mrc_alt_write_mask(DDRPHY, (DQANATCOPDCTL), (BIT30), (BIT30));
+	mrc_alt_write_mask(DDRPHY, DQANATCOPDCTL, 1 << 30, 1 << 30);
 	/* TCO: Dither PU Enable */
-	mrc_alt_write_mask(DDRPHY, (CLKANATCOPUCTL), (BIT30), (BIT30));
+	mrc_alt_write_mask(DDRPHY, CLKANATCOPUCTL, 1 << 30, 1 << 30);
 	/* TCO: Dither PD Enable */
-	mrc_alt_write_mask(DDRPHY, (CLKANATCOPDCTL), (BIT30), (BIT30));
+	mrc_alt_write_mask(DDRPHY, CLKANATCOPDCTL, 1 << 30, 1 << 30);
 	/* TCO: Dither PU Enable */
-	mrc_alt_write_mask(DDRPHY, (DQSANATCOPUCTL), (BIT30), (BIT30));
+	mrc_alt_write_mask(DDRPHY, DQSANATCOPUCTL, 1 << 30, 1 << 30);
 	/* TCO: Dither PD Enable */
-	mrc_alt_write_mask(DDRPHY, (DQSANATCOPDCTL), (BIT30), (BIT30));
+	mrc_alt_write_mask(DDRPHY, DQSANATCOPDCTL, 1 << 30, 1 << 30);
 	/* TCOCOMP: Pulse Count */
-	mrc_alt_write_mask(DDRPHY, (TCOCNTCTRL), (0x1 << 0), (BIT1 | BIT0));
+	mrc_alt_write_mask(DDRPHY, TCOCNTCTRL, 1, 3);
 	/* ODT: CMD/CTL PD/PU */
-	mrc_alt_write_mask(DDRPHY,
-		(CHNLBUFSTATIC), ((0x03 << 24) | (0x03 << 16)),
-		(BIT28 | BIT27 | BIT26 | BIT25 | BIT24 |
-		BIT20 | BIT19 | BIT18 | BIT17 | BIT16));
+	mrc_alt_write_mask(DDRPHY, CHNLBUFSTATIC,
+		(0x03 << 24) | (0x03 << 16), 0x1f1f0000);
 	/* Set 1us counter */
-	mrc_alt_write_mask(DDRPHY,
-		(MSCNTR), (0x64 << 0),
-		(BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0));
-	mrc_alt_write_mask(DDRPHY,
-		(LATCH1CTL), (0x1 << 28),
-		(BIT30 | BIT29 | BIT28));
+	mrc_alt_write_mask(DDRPHY, MSCNTR, 0x64, 0xff);
+	mrc_alt_write_mask(DDRPHY, LATCH1CTL, 0x1 << 28, 0x70000000);
 
 	/* Release PHY from reset */
-	mrc_alt_write_mask(DDRPHY, MASTERRSTN, BIT0, BIT0);
+	mrc_alt_write_mask(DDRPHY, MASTERRSTN, 1, 1);
 
 	/* STEP1 */
 	mrc_post_code(0x03, 0x11);
@@ -1064,30 +941,30 @@
 		if (mrc_params->channel_enables & (1 << ch)) {
 			/* DQ01-DQ23 */
 			for (bl_grp = 0;
-			     bl_grp < ((NUM_BYTE_LANES / bl_divisor) / 2);
+			     bl_grp < (NUM_BYTE_LANES / bl_divisor) / 2;
 			     bl_grp++) {
 				mrc_alt_write_mask(DDRPHY,
-					(DQMDLLCTL +
-					(bl_grp * DDRIODQ_BL_OFFSET) +
-					(ch * DDRIODQ_CH_OFFSET)),
-					(BIT13),
-					(BIT13));	/* Enable VREG */
+					DQMDLLCTL +
+					bl_grp * DDRIODQ_BL_OFFSET +
+					ch * DDRIODQ_CH_OFFSET,
+					1 << 13,
+					1 << 13);	/* Enable VREG */
 				delay_n(3);
 			}
 
 			/* ECC */
-			mrc_alt_write_mask(DDRPHY, (ECCMDLLCTL),
-				(BIT13), (BIT13));	/* Enable VREG */
+			mrc_alt_write_mask(DDRPHY, ECCMDLLCTL,
+				1 << 13, 1 << 13);	/* Enable VREG */
 			delay_n(3);
 			/* CMD */
 			mrc_alt_write_mask(DDRPHY,
-				(CMDMDLLCTL + (ch * DDRIOCCC_CH_OFFSET)),
-				(BIT13), (BIT13));	/* Enable VREG */
+				CMDMDLLCTL + ch * DDRIOCCC_CH_OFFSET,
+				1 << 13, 1 << 13);	/* Enable VREG */
 			delay_n(3);
 			/* CLK-CTL */
 			mrc_alt_write_mask(DDRPHY,
-				(CCMDLLCTL + (ch * DDRIOCCC_CH_OFFSET)),
-				(BIT13), (BIT13));	/* Enable VREG */
+				CCMDLLCTL + ch * DDRIOCCC_CH_OFFSET,
+				1 << 13, 1 << 13);	/* Enable VREG */
 			delay_n(3);
 		}
 	}
@@ -1100,30 +977,30 @@
 		if (mrc_params->channel_enables & (1 << ch)) {
 			/* DQ01-DQ23 */
 			for (bl_grp = 0;
-			     bl_grp < ((NUM_BYTE_LANES / bl_divisor) / 2);
+			     bl_grp < (NUM_BYTE_LANES / bl_divisor) / 2;
 			     bl_grp++) {
 				mrc_alt_write_mask(DDRPHY,
-					(DQMDLLCTL +
-					(bl_grp * DDRIODQ_BL_OFFSET) +
-					(ch * DDRIODQ_CH_OFFSET)),
-					(BIT17),
-					(BIT17));	/* Enable MCDLL */
+					DQMDLLCTL +
+					bl_grp * DDRIODQ_BL_OFFSET +
+					ch * DDRIODQ_CH_OFFSET,
+					1 << 17,
+					1 << 17);	/* Enable MCDLL */
 				delay_n(50);
 			}
 
 		/* ECC */
-		mrc_alt_write_mask(DDRPHY, (ECCMDLLCTL),
-			(BIT17), (BIT17));	/* Enable MCDLL */
+		mrc_alt_write_mask(DDRPHY, ECCMDLLCTL,
+			1 << 17, 1 << 17);	/* Enable MCDLL */
 		delay_n(50);
 		/* CMD */
 		mrc_alt_write_mask(DDRPHY,
-			(CMDMDLLCTL + (ch * DDRIOCCC_CH_OFFSET)),
-			(BIT18), (BIT18));	/* Enable MCDLL */
+			CMDMDLLCTL + ch * DDRIOCCC_CH_OFFSET,
+			1 << 18, 1 << 18);	/* Enable MCDLL */
 		delay_n(50);
 		/* CLK-CTL */
 		mrc_alt_write_mask(DDRPHY,
-			(CCMDLLCTL + (ch * DDRIOCCC_CH_OFFSET)),
-			(BIT18), (BIT18));	/* Enable MCDLL */
+			CCMDLLCTL + ch * DDRIOCCC_CH_OFFSET,
+			1 << 18, 1 << 18);	/* Enable MCDLL */
 		delay_n(50);
 		}
 	}
@@ -1136,54 +1013,47 @@
 		if (mrc_params->channel_enables & (1 << ch)) {
 			/* DQ01-DQ23 */
 			for (bl_grp = 0;
-			     bl_grp < ((NUM_BYTE_LANES / bl_divisor) / 2);
+			     bl_grp < (NUM_BYTE_LANES / bl_divisor) / 2;
 			     bl_grp++) {
 #ifdef FORCE_16BIT_DDRIO
-				temp = ((bl_grp) &&
+				temp = (bl_grp &&
 					(mrc_params->channel_width == X16)) ?
-					((0x1 << 12) | (0x1 << 8) |
-					(0xF << 4) | (0xF << 0)) :
-					((0xF << 12) | (0xF << 8) |
-					(0xF << 4) | (0xF << 0));
+					0x11ff : 0xffff;
 #else
-				temp = ((0xF << 12) | (0xF << 8) |
-					(0xF << 4) | (0xF << 0));
+				temp = 0xffff;
 #endif
 				/* Enable TXDLL */
 				mrc_alt_write_mask(DDRPHY,
-					(DQDLLTXCTL +
-					(bl_grp * DDRIODQ_BL_OFFSET) +
-					(ch * DDRIODQ_CH_OFFSET)),
-					temp, 0xFFFF);
+					DQDLLTXCTL +
+					bl_grp * DDRIODQ_BL_OFFSET +
+					ch * DDRIODQ_CH_OFFSET,
+					temp, 0xffff);
 				delay_n(3);
 				/* Enable RXDLL */
 				mrc_alt_write_mask(DDRPHY,
-					(DQDLLRXCTL +
-					(bl_grp * DDRIODQ_BL_OFFSET) +
-					(ch * DDRIODQ_CH_OFFSET)),
-					(BIT3 | BIT2 | BIT1 | BIT0),
-					(BIT3 | BIT2 | BIT1 | BIT0));
+					DQDLLRXCTL +
+					bl_grp * DDRIODQ_BL_OFFSET +
+					ch * DDRIODQ_CH_OFFSET,
+					0xf, 0xf);
 				delay_n(3);
 				/* Enable RXDLL Overrides BL0 */
 				mrc_alt_write_mask(DDRPHY,
-					(B0OVRCTL +
-					(bl_grp * DDRIODQ_BL_OFFSET) +
-					(ch * DDRIODQ_CH_OFFSET)),
-					(BIT3 | BIT2 | BIT1 | BIT0),
-					(BIT3 | BIT2 | BIT1 | BIT0));
+					B0OVRCTL +
+					bl_grp * DDRIODQ_BL_OFFSET +
+					ch * DDRIODQ_CH_OFFSET,
+					0xf, 0xf);
 			}
 
 			/* ECC */
-			temp = ((0xF << 12) | (0xF << 8) |
-				(0xF << 4) | (0xF << 0));
-			mrc_alt_write_mask(DDRPHY, (ECCDLLTXCTL),
-				temp, 0xFFFF);
+			temp = 0xffff;
+			mrc_alt_write_mask(DDRPHY, ECCDLLTXCTL,
+				temp, 0xffff);
 			delay_n(3);
 
 			/* CMD (PO) */
 			mrc_alt_write_mask(DDRPHY,
-				(CMDDLLTXCTL + (ch * DDRIOCCC_CH_OFFSET)),
-				temp, 0xFFFF);
+				CMDDLLTXCTL + ch * DDRIOCCC_CH_OFFSET,
+				temp, 0xffff);
 			delay_n(3);
 		}
 	}
@@ -1195,94 +1065,85 @@
 		if (mrc_params->channel_enables & (1 << ch)) {
 			/* Host To Memory Clock Alignment (HMC) for 800/1066 */
 			for (bl_grp = 0;
-			     bl_grp < ((NUM_BYTE_LANES / bl_divisor) / 2);
+			     bl_grp < (NUM_BYTE_LANES / bl_divisor) / 2;
 			     bl_grp++) {
 				/* CLK_ALIGN_MOD_ID */
 				mrc_alt_write_mask(DDRPHY,
-					(DQCLKALIGNREG2 +
-					(bl_grp * DDRIODQ_BL_OFFSET) +
-					(ch * DDRIODQ_CH_OFFSET)),
-					(bl_grp) ? (0x3) : (0x1),
-					(BIT3 | BIT2 | BIT1 | BIT0));
+					DQCLKALIGNREG2 +
+					bl_grp * DDRIODQ_BL_OFFSET +
+					ch * DDRIODQ_CH_OFFSET,
+					bl_grp ? 3 : 1,
+					0xf);
 			}
 
 			mrc_alt_write_mask(DDRPHY,
-				(ECCCLKALIGNREG2 + (ch * DDRIODQ_CH_OFFSET)),
-				0x2,
-				(BIT3 | BIT2 | BIT1 | BIT0));
+				ECCCLKALIGNREG2 + ch * DDRIODQ_CH_OFFSET,
+				0x2, 0xf);
 			mrc_alt_write_mask(DDRPHY,
-				(CMDCLKALIGNREG2 + (ch * DDRIODQ_CH_OFFSET)),
-				0x0,
-				(BIT3 | BIT2 | BIT1 | BIT0));
+				CMDCLKALIGNREG2 + ch * DDRIODQ_CH_OFFSET,
+				0x0, 0xf);
 			mrc_alt_write_mask(DDRPHY,
-				(CCCLKALIGNREG2 + (ch * DDRIODQ_CH_OFFSET)),
-				0x2,
-				(BIT3 | BIT2 | BIT1 | BIT0));
+				CCCLKALIGNREG2 + ch * DDRIODQ_CH_OFFSET,
+				0x2, 0xf);
 			mrc_alt_write_mask(DDRPHY,
-				(CMDCLKALIGNREG0 + (ch * DDRIOCCC_CH_OFFSET)),
-				(0x2 << 4), (BIT5 | BIT4));
+				CMDCLKALIGNREG0 + ch * DDRIOCCC_CH_OFFSET,
+				0x20, 0x30);
 			/*
 			 * NUM_SAMPLES, MAX_SAMPLES,
 			 * MACRO_PI_STEP, MICRO_PI_STEP
 			 */
 			mrc_alt_write_mask(DDRPHY,
-				(CMDCLKALIGNREG1 + (ch * DDRIOCCC_CH_OFFSET)),
-				((0x18 << 16) | (0x10 << 8) |
-				(0x8 << 2) | (0x1 << 0)),
-				(BIT22 | BIT21 | BIT20 | BIT19 | BIT18 | BIT17 |
-				BIT16 | BIT14 | BIT13 | BIT12 | BIT11 | BIT10 |
-				BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | BIT3 |
-				BIT2 | BIT1 | BIT0));
+				CMDCLKALIGNREG1 + ch * DDRIOCCC_CH_OFFSET,
+				(0x18 << 16) | (0x10 << 8) |
+				(0x8 << 2) | (0x1 << 0),
+				0x007f7fff);
 			/* TOTAL_NUM_MODULES, FIRST_U_PARTITION */
 			mrc_alt_write_mask(DDRPHY,
-				(CMDCLKALIGNREG2 + (ch * DDRIOCCC_CH_OFFSET)),
-				((0x10 << 16) | (0x4 << 8) | (0x2 << 4)),
-				(BIT20 | BIT19 | BIT18 | BIT17 | BIT16 |
-				BIT11 | BIT10 | BIT9 | BIT8 | BIT7 | BIT6 |
-				BIT5 | BIT4));
+				CMDCLKALIGNREG2 + ch * DDRIOCCC_CH_OFFSET,
+				(0x10 << 16) | (0x4 << 8) | (0x2 << 4),
+				0x001f0ff0);
 #ifdef HMC_TEST
 			/* START_CLK_ALIGN=1 */
 			mrc_alt_write_mask(DDRPHY,
-				(CMDCLKALIGNREG0 + (ch * DDRIOCCC_CH_OFFSET)),
-				BIT24, BIT24);
+				CMDCLKALIGNREG0 + ch * DDRIOCCC_CH_OFFSET,
+				1 << 24, 1 << 24);
 			while (msg_port_alt_read(DDRPHY,
-				(CMDCLKALIGNREG0 + (ch * DDRIOCCC_CH_OFFSET))) &
-				BIT24)
+				CMDCLKALIGNREG0 + ch * DDRIOCCC_CH_OFFSET) &
+				(1 << 24))
 				;	/* wait for START_CLK_ALIGN=0 */
 #endif
 
 			/* Set RD/WR Pointer Seperation & COUNTEN & FIFOPTREN */
 			mrc_alt_write_mask(DDRPHY,
-				(CMDPTRREG + (ch * DDRIOCCC_CH_OFFSET)),
-				BIT0, BIT0);	/* WRPTRENABLE=1 */
+				CMDPTRREG + ch * DDRIOCCC_CH_OFFSET,
+				1, 1);	/* WRPTRENABLE=1 */
 
 			/* COMP initial */
 			/* enable bypass for CLK buffer (PO) */
 			mrc_alt_write_mask(DDRPHY,
-				(COMPEN0CH0 + (ch * DDRCOMP_CH_OFFSET)),
-				BIT5, BIT5);
+				COMPEN0CH0 + ch * DDRCOMP_CH_OFFSET,
+				1 << 5, 1 << 5);
 			/* Initial COMP Enable */
-			mrc_alt_write_mask(DDRPHY, (CMPCTRL),
-				(BIT0), (BIT0));
+			mrc_alt_write_mask(DDRPHY, CMPCTRL, 1, 1);
 			/* wait for Initial COMP Enable = 0 */
-			while (msg_port_alt_read(DDRPHY, (CMPCTRL)) & BIT0)
+			while (msg_port_alt_read(DDRPHY, CMPCTRL) & 1)
 				;
 			/* disable bypass for CLK buffer (PO) */
 			mrc_alt_write_mask(DDRPHY,
-				(COMPEN0CH0 + (ch * DDRCOMP_CH_OFFSET)),
-				~BIT5, BIT5);
+				COMPEN0CH0 + ch * DDRCOMP_CH_OFFSET,
+				~(1 << 5), 1 << 5);
 
 			/* IOBUFACT */
 
 			/* STEP4a */
 			mrc_alt_write_mask(DDRPHY,
-				(CMDCFGREG0 + (ch * DDRIOCCC_CH_OFFSET)),
-				BIT2, BIT2);	/* IOBUFACTRST_N=1 */
+				CMDCFGREG0 + ch * DDRIOCCC_CH_OFFSET,
+				1 << 2, 1 << 2);	/* IOBUFACTRST_N=1 */
 
 			/* DDRPHY initialization complete */
 			mrc_alt_write_mask(DDRPHY,
-				(CMDPMCONFIG0 + (ch * DDRIOCCC_CH_OFFSET)),
-				BIT20, BIT20);	/* SPID_INIT_COMPLETE=1 */
+				CMDPMCONFIG0 + ch * DDRIOCCC_CH_OFFSET,
+				1 << 20, 1 << 20);	/* SPID_INIT_COMPLETE=1 */
 		}
 	}
 
@@ -1308,13 +1169,13 @@
 	mrc_post_code(0x04, 0x00);
 
 	/* DDR3_RESET_SET=0, DDR3_RESET_RESET=1 */
-	mrc_alt_write_mask(DDRPHY, CCDDR3RESETCTL, BIT1, (BIT8 | BIT1));
+	mrc_alt_write_mask(DDRPHY, CCDDR3RESETCTL, 2, 0x102);
 
 	/* Assert RESET# for 200us */
 	delay_u(200);
 
 	/* DDR3_RESET_SET=1, DDR3_RESET_RESET=0 */
-	mrc_alt_write_mask(DDRPHY, CCDDR3RESETCTL, BIT8, (BIT8 | BIT1));
+	mrc_alt_write_mask(DDRPHY, CCDDR3RESETCTL, 0x100, 0x102);
 
 	dtr0 = msg_port_read(MEM_CTLR, DTR0);
 
@@ -1327,8 +1188,8 @@
 	drp &= 0x3;
 
 	drmc = msg_port_read(MEM_CTLR, DRMC);
-	drmc &= 0xFFFFFFFC;
-	drmc |= (BIT4 | drp);
+	drmc &= 0xfffffffc;
+	drmc |= (DRMC_CKEMODE | drp);
 
 	msg_port_write(MEM_CTLR, DRMC, drmc);
 
@@ -1341,7 +1202,7 @@
 	}
 
 	msg_port_write(MEM_CTLR, DRMC,
-		(mrc_params->rd_odt_value == 0 ? BIT12 : 0));
+		(mrc_params->rd_odt_value == 0 ? DRMC_ODTMODE : 0));
 
 	/*
 	 * setup for emrs 2
@@ -1392,12 +1253,12 @@
 	 * 1** --> RESERVED
 	 */
 	emrs1_cmd |= (1 << 3);
-	emrs1_cmd &= ~BIT6;
+	emrs1_cmd &= ~(1 << 6);
 
 	if (mrc_params->ron_value == 0)
-		emrs1_cmd |= BIT7;
+		emrs1_cmd |= (1 << 7);
 	else
-		emrs1_cmd &= ~BIT7;
+		emrs1_cmd &= ~(1 << 7);
 
 	if (mrc_params->rtt_nom_value == 0)
 		emrs1_cmd |= (DDR3_EMRS1_RTTNOM_40 << 6);
@@ -1432,8 +1293,8 @@
 	 * BIT[02:02] "0" if oem_tCAS <= 11 (1866?)
 	 * BIT[06:04] use oem_tCAS-4
 	 */
-	mrs0_cmd |= BIT14;
-	mrs0_cmd |= BIT18;
+	mrs0_cmd |= (1 << 14);
+	mrs0_cmd |= (1 << 18);
 	mrs0_cmd |= ((((dtr0 >> 12) & 7) + 1) << 10);
 
 	tck = t_ck[mrc_params->ddr_speed];
@@ -1480,8 +1341,8 @@
 	ENTERFN();
 
 	dco = msg_port_read(MEM_CTLR, DCO);
-	dco &= ~BIT28;
-	dco |= BIT31;
+	dco &= ~DCO_PMICTL;
+	dco |= DCO_IC;
 	msg_port_write(MEM_CTLR, DCO, dco);
 
 	LEAVEFN();
@@ -1577,7 +1438,7 @@
 	/* need separate burst to sample DQS preamble */
 	dtr1 = msg_port_read(MEM_CTLR, DTR1);
 	dtr1_save = dtr1;
-	dtr1 |= BIT12;
+	dtr1 |= DTR1_TCCD_12CLK;
 	msg_port_write(MEM_CTLR, DTR1, dtr1);
 #endif
 
@@ -1596,7 +1457,7 @@
 					 * POST_CODE here indicates the current
 					 * channel and rank being calibrated
 					 */
-					mrc_post_code(0x05, (0x10 + ((ch << 4) | rk)));
+					mrc_post_code(0x05, 0x10 + ((ch << 4) | rk));
 
 #ifdef BACKUP_RCVN
 					/* et hard-coded timing values */
@@ -1606,10 +1467,10 @@
 					/* enable FIFORST */
 					for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl += 2) {
 						mrc_alt_write_mask(DDRPHY,
-							(B01PTRCTL1 +
-							((bl >> 1) * DDRIODQ_BL_OFFSET) +
-							(ch * DDRIODQ_CH_OFFSET)),
-							0, BIT8);
+							B01PTRCTL1 +
+							(bl >> 1) * DDRIODQ_BL_OFFSET +
+							ch * DDRIODQ_CH_OFFSET,
+							0, 1 << 8);
 					}
 					/* initialize the starting delay to 128 PI (cas +1 CLK) */
 					for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) {
@@ -1638,11 +1499,11 @@
 								} else {
 									/* not enough delay */
 									training_message(ch, rk, bl);
-									mrc_post_code(0xEE, 0x50);
+									mrc_post_code(0xee, 0x50);
 								}
 							}
 						}
-					} while (temp & 0xFF);
+					} while (temp & 0xff);
 
 #ifdef R2R_SHARING
 					/* increment "num_ranks_enabled" */
@@ -1653,7 +1514,7 @@
 						/* add "delay[]" values to "final_delay[][]" for rolling average */
 						final_delay[ch][bl] += delay[bl];
 						/* set timing based on rolling average values */
-						set_rcvn(ch, rk, bl, ((final_delay[ch][bl]) / num_ranks_enabled));
+						set_rcvn(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled);
 					}
 #else
 					/* Finally increment delay by 32 PI (1/4 CLK) to place in center of preamble */
@@ -1666,10 +1527,10 @@
 					/* disable FIFORST */
 					for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl += 2) {
 						mrc_alt_write_mask(DDRPHY,
-							(B01PTRCTL1 +
-							((bl >> 1) * DDRIODQ_BL_OFFSET) +
-							(ch * DDRIODQ_CH_OFFSET)),
-							BIT8, BIT8);
+							B01PTRCTL1 +
+							(bl >> 1) * DDRIODQ_BL_OFFSET +
+							ch * DDRIODQ_CH_OFFSET,
+							1 << 8, 1 << 8);
 					}
 #endif
 				}
@@ -1742,12 +1603,12 @@
 					 * POST_CODE here indicates the current
 					 * rank and channel being calibrated
 					 */
-					mrc_post_code(0x06, (0x10 + ((ch << 4) | rk)));
+					mrc_post_code(0x06, 0x10 + ((ch << 4) | rk));
 
 #ifdef BACKUP_WDQS
 					for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) {
 						set_wdqs(ch, rk, bl, ddr_wdqs[PLATFORM_ID]);
-						set_wdq(ch, rk, bl, (ddr_wdqs[PLATFORM_ID] - QRTR_CLK));
+						set_wdq(ch, rk, bl, ddr_wdqs[PLATFORM_ID] - QRTR_CLK);
 					}
 #else
 					/*
@@ -1760,7 +1621,7 @@
 					 * enable Write Levelling Mode
 					 * (EMRS1 w/ Write Levelling Mode Enable)
 					 */
-					dram_init_command(DCMD_MRS1(rk, 0x0082));
+					dram_init_command(DCMD_MRS1(rk, 0x82));
 
 					/*
 					 * set ODT DRAM Full Time Termination
@@ -1769,24 +1630,24 @@
 
 					dtr4 = msg_port_read(MEM_CTLR, DTR4);
 					dtr4_save = dtr4;
-					dtr4 |= BIT15;
+					dtr4 |= DTR4_ODTDIS;
 					msg_port_write(MEM_CTLR, DTR4, dtr4);
 
-					for (bl = 0; bl < ((NUM_BYTE_LANES / bl_divisor) / 2); bl++) {
+					for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor) / 2; bl++) {
 						/*
 						 * Enable Sandy Bridge Mode (WDQ Tri-State) &
 						 * Ensure 5 WDQS pulses during Write Leveling
 						 */
 						mrc_alt_write_mask(DDRPHY,
-							DQCTL + (DDRIODQ_BL_OFFSET * bl) + (DDRIODQ_CH_OFFSET * ch),
-							(BIT28 | BIT8 | BIT6 | BIT4 | BIT2),
-							(BIT28 | BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2));
+							DQCTL + DDRIODQ_BL_OFFSET * bl + DDRIODQ_CH_OFFSET * ch,
+							0x10000154,
+							0x100003fc);
 					}
 
 					/* Write Leveling Mode enabled in IO */
 					mrc_alt_write_mask(DDRPHY,
-						CCDDR3RESETCTL + (DDRIOCCC_CH_OFFSET * ch),
-						BIT16, BIT16);
+						CCDDR3RESETCTL + DDRIOCCC_CH_OFFSET * ch,
+						1 << 16, 1 << 16);
 
 					/* Initialize the starting delay to WCLK */
 					for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) {
@@ -1804,15 +1665,15 @@
 
 					/* disable Write Levelling Mode */
 					mrc_alt_write_mask(DDRPHY,
-						CCDDR3RESETCTL + (DDRIOCCC_CH_OFFSET * ch),
-						0, BIT16);
+						CCDDR3RESETCTL + DDRIOCCC_CH_OFFSET * ch,
+						0, 1 << 16);
 
-					for (bl = 0; bl < ((NUM_BYTE_LANES / bl_divisor) / 2); bl++) {
+					for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor) / 2; bl++) {
 						/* Disable Sandy Bridge Mode & Ensure 4 WDQS pulses during normal operation */
 						mrc_alt_write_mask(DDRPHY,
-							DQCTL + (DDRIODQ_BL_OFFSET * bl) + (DDRIODQ_CH_OFFSET * ch),
-							(BIT8 | BIT6 | BIT4 | BIT2),
-							(BIT28 | BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2));
+							DQCTL + DDRIODQ_BL_OFFSET * bl + DDRIODQ_CH_OFFSET * ch,
+							0x00000154,
+							0x100003fc);
 					}
 
 					/* restore original DTR4 */
@@ -1830,7 +1691,7 @@
 					 */
 					dram_init_command(DCMD_PREA(rk));
 
-					mrc_post_code(0x06, (0x30 + ((ch << 4) | rk)));
+					mrc_post_code(0x06, 0x30 + ((ch << 4) | rk));
 
 					/*
 					 * COARSE WRITE LEVEL:
@@ -1863,13 +1724,13 @@
 						coarse_result = check_rw_coarse(mrc_params, address);
 
 						/* check for failures and margin the byte lane back 128 PI (1 CLK) */
-						for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) {
+						for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) {
 							if (coarse_result & (coarse_result_mask << bl)) {
 								all_edges_found = false;
 								delay[bl] -= FULL_CLK;
 								set_wdqs(ch, rk, bl, delay[bl]);
 								/* program WDQ timings based on WDQS (WDQ = WDQS - 32 PI) */
-								set_wdq(ch, rk, bl, (delay[bl] - QRTR_CLK));
+								set_wdq(ch, rk, bl, delay[bl] - QRTR_CLK);
 							}
 						}
 					} while (!all_edges_found);
@@ -1878,11 +1739,11 @@
 					/* increment "num_ranks_enabled" */
 					 num_ranks_enabled++;
 					/* accumulate "final_delay[][]" values from "delay[]" values for rolling average */
-					for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) {
+					for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) {
 						final_delay[ch][bl] += delay[bl];
-						set_wdqs(ch, rk, bl, ((final_delay[ch][bl]) / num_ranks_enabled));
+						set_wdqs(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled);
 						/* program WDQ timings based on WDQS (WDQ = WDQS - 32 PI) */
-						set_wdq(ch, rk, bl, ((final_delay[ch][bl]) / num_ranks_enabled) - QRTR_CLK);
+						set_wdq(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled - QRTR_CLK);
 					}
 #endif
 #endif
@@ -1901,9 +1762,9 @@
 	ENTERFN();
 
 	dpmc0 = msg_port_read(MEM_CTLR, DPMC0);
-	dpmc0 &= ~(BIT16 | BIT17 | BIT18);
+	dpmc0 &= ~DPMC0_PCLSTO_MASK;
 	dpmc0 |= (4 << 16);
-	dpmc0 |= BIT21;
+	dpmc0 |= DPMC0_PREAPWDEN;
 	msg_port_write(MEM_CTLR, DPMC0, dpmc0);
 }
 
@@ -1966,7 +1827,7 @@
 			for (rk = 0; rk < NUM_RANKS; rk++) {
 				if (mrc_params->rank_enables & (1 << rk)) {
 					for (bl = 0;
-					     bl < (NUM_BYTE_LANES / bl_divisor);
+					     bl < NUM_BYTE_LANES / bl_divisor;
 					     bl++) {
 						set_rdqs(ch, rk, bl, ddr_rdqs[PLATFORM_ID]);
 					}
@@ -1981,7 +1842,7 @@
 			for (rk = 0; rk < NUM_RANKS; rk++) {
 				if (mrc_params->rank_enables & (1 << rk)) {
 					for (bl = 0;
-					     bl < (NUM_BYTE_LANES / bl_divisor);
+					     bl < NUM_BYTE_LANES / bl_divisor;
 					     bl++) {
 						/* x_coordinate */
 						x_coordinate[L][B][ch][rk][bl] = RDQS_MIN;
@@ -2011,7 +1872,7 @@
 	/* look for passing coordinates */
 	for (side_y = B; side_y <= T; side_y++) {
 		for (side_x = L; side_x <= R; side_x++) {
-			mrc_post_code(0x07, (0x10 + (side_y * 2) + (side_x)));
+			mrc_post_code(0x07, 0x10 + side_y * 2 + side_x);
 
 			/* find passing values */
 			for (ch = 0; ch < NUM_CHANNELS; ch++) {
@@ -2021,7 +1882,7 @@
 							(0x1 << rk)) {
 							/* set x/y_coordinate search starting settings */
 							for (bl = 0;
-							     bl < (NUM_BYTE_LANES / bl_divisor);
+							     bl < NUM_BYTE_LANES / bl_divisor;
 							     bl++) {
 								set_rdqs(ch, rk, bl,
 									 x_coordinate[side_x][side_y][ch][rk][bl]);
@@ -2041,9 +1902,9 @@
 								result = check_bls_ex(mrc_params, address);
 
 								/* check for failures */
-								if (result & 0xFF) {
+								if (result & 0xff) {
 									/* at least 1 byte lane failed */
-									for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) {
+									for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) {
 										if (result &
 											(bl_mask << bl)) {
 											/* adjust the RDQS values accordingly */
@@ -2072,13 +1933,13 @@
 													(y_coordinate[side_x][B][ch][bl] == y_coordinate[side_x][T][ch][bl])) {
 													/* VREF_EYE collapsed below MIN_VREF_EYE */
 													training_message(ch, rk, bl);
-													mrc_post_code(0xEE, (0x70 + (side_y * 2) + (side_x)));
+													mrc_post_code(0xEE, 0x70 + side_y * 2 + side_x);
 												} else {
 													/* update the VREF setting */
 													set_vref(ch, bl, y_coordinate[side_x][side_y][ch][bl]);
 													/* reset the X coordinate to begin the search at the new VREF */
 													x_coordinate[side_x][side_y][ch][rk][bl] =
-														(side_x == L) ? (RDQS_MIN) : (RDQS_MAX);
+														(side_x == L) ? RDQS_MIN : RDQS_MAX;
 												}
 											}
 
@@ -2087,7 +1948,7 @@
 										}
 									}
 								}
-							} while (result & 0xFF);
+							} while (result & 0xff);
 						}
 					}
 				}
@@ -2147,23 +2008,23 @@
 	/* perform an eye check */
 	for (side_y = B; side_y <= T; side_y++) {
 		for (side_x = L; side_x <= R; side_x++) {
-			mrc_post_code(0x07, (0x30 + (side_y * 2) + (side_x)));
+			mrc_post_code(0x07, 0x30 + side_y * 2 + side_x);
 
 			/* update the settings for the eye check */
 			for (ch = 0; ch < NUM_CHANNELS; ch++) {
 				if (mrc_params->channel_enables & (1 << ch)) {
 					for (rk = 0; rk < NUM_RANKS; rk++) {
 						if (mrc_params->rank_enables & (1 << rk)) {
-							for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) {
+							for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) {
 								if (side_x == L)
-									set_rdqs(ch, rk, bl, (x_center[ch][rk][bl] - (MIN_RDQS_EYE / 2)));
+									set_rdqs(ch, rk, bl, x_center[ch][rk][bl] - (MIN_RDQS_EYE / 2));
 								else
-									set_rdqs(ch, rk, bl, (x_center[ch][rk][bl] + (MIN_RDQS_EYE / 2)));
+									set_rdqs(ch, rk, bl, x_center[ch][rk][bl] + (MIN_RDQS_EYE / 2));
 
 								if (side_y == B)
-									set_vref(ch, bl, (y_center[ch][bl] - (MIN_VREF_EYE / 2)));
+									set_vref(ch, bl, y_center[ch][bl] - (MIN_VREF_EYE / 2));
 								else
-									set_vref(ch, bl, (y_center[ch][bl] + (MIN_VREF_EYE / 2)));
+									set_vref(ch, bl, y_center[ch][bl] + (MIN_VREF_EYE / 2));
 							}
 						}
 					}
@@ -2174,9 +2035,9 @@
 			mrc_params->hte_setup = 1;
 
 			/* check the eye */
-			if (check_bls_ex(mrc_params, address) & 0xFF) {
+			if (check_bls_ex(mrc_params, address) & 0xff) {
 				/* one or more byte lanes failed */
-				mrc_post_code(0xEE, (0x74 + (side_x * 2) + (side_y)));
+				mrc_post_code(0xee, 0x74 + side_x * 2 + side_y);
 			}
 		}
 	}
@@ -2197,7 +2058,7 @@
 						/* x_coordinate */
 #ifdef R2R_SHARING
 						final_delay[ch][bl] += x_center[ch][rk][bl];
-						set_rdqs(ch, rk, bl, ((final_delay[ch][bl]) / num_ranks_enabled));
+						set_rdqs(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled);
 #else
 						set_rdqs(ch, rk, bl, x_center[ch][rk][bl]);
 #endif
@@ -2258,7 +2119,7 @@
 			for (rk = 0; rk < NUM_RANKS; rk++) {
 				if (mrc_params->rank_enables & (1 << rk)) {
 					for (bl = 0;
-					     bl < (NUM_BYTE_LANES / bl_divisor);
+					     bl < NUM_BYTE_LANES / bl_divisor;
 					     bl++) {
 						set_wdq(ch, rk, bl, ddr_wdq[PLATFORM_ID]);
 					}
@@ -2273,7 +2134,7 @@
 			for (rk = 0; rk < NUM_RANKS; rk++) {
 				if (mrc_params->rank_enables & (1 << rk)) {
 					for (bl = 0;
-					     bl < (NUM_BYTE_LANES / bl_divisor);
+					     bl < NUM_BYTE_LANES / bl_divisor;
 					     bl++) {
 						/*
 						 * want to start with
@@ -2303,7 +2164,7 @@
 	 * until no failures are observed, then repeat for the RIGHT side.
 	 */
 	for (side = L; side <= R; side++) {
-		mrc_post_code(0x08, (0x10 + (side)));
+		mrc_post_code(0x08, 0x10 + side);
 
 		/* set starting values */
 		for (ch = 0; ch < NUM_CHANNELS; ch++) {
@@ -2312,7 +2173,7 @@
 					if (mrc_params->rank_enables &
 						(1 << rk)) {
 						for (bl = 0;
-						     bl < (NUM_BYTE_LANES / bl_divisor);
+						     bl < NUM_BYTE_LANES / bl_divisor;
 						     bl++) {
 							set_wdq(ch, rk, bl, delay[side][ch][rk][bl]);
 						}
@@ -2338,9 +2199,9 @@
 							/* result[07:00] == failing byte lane (MAX 8) */
 							result = check_bls_ex(mrc_params, address);
 							/* check for failures */
-							if (result & 0xFF) {
+							if (result & 0xff) {
 								/* at least 1 byte lane failed */
-								for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) {
+								for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) {
 									if (result &
 										(bl_mask << bl)) {
 										if (side == L)
@@ -2362,13 +2223,13 @@
 											 * notify the user and halt
 											 */
 											training_message(ch, rk, bl);
-											mrc_post_code(0xEE, (0x80 + side));
+											mrc_post_code(0xee, 0x80 + side);
 										}
 									}
 								}
 							}
 						/* stop when all byte lanes pass */
-						} while (result & 0xFF);
+						} while (result & 0xff);
 					}
 				}
 			}
@@ -2384,7 +2245,7 @@
 					/* increment "num_ranks_enabled" */
 					num_ranks_enabled++;
 #endif
-					for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) {
+					for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) {
 						DPF(D_INFO,
 						    "WDQ eye rank%d lane%d : %d-%d\n",
 						    rk, bl,
@@ -2396,7 +2257,7 @@
 #ifdef R2R_SHARING
 						final_delay[ch][bl] += temp;
 						set_wdq(ch, rk, bl,
-							((final_delay[ch][bl]) / num_ranks_enabled));
+							final_delay[ch][bl] / num_ranks_enabled);
 #else
 						set_wdq(ch, rk, bl, temp);
 #endif
@@ -2470,7 +2331,7 @@
 			 * get seed from system clock
 			 * and make sure it is not all 1's
 			 */
-			lfsr = rdtsc() & 0x0FFFFFFF;
+			lfsr = rdtsc() & 0x0fffffff;
 		} else {
 			/*
 			 * Need to replace scrambler
@@ -2491,10 +2352,10 @@
 	 * In cold boot, we have the last 32bit LFSR which is the new seed.
 	 */
 	lfsr32(&lfsr);	/* shift to next value */
-	msg_port_write(MEM_CTLR, SCRMSEED, (lfsr & 0x0003FFFF));
+	msg_port_write(MEM_CTLR, SCRMSEED, (lfsr & 0x0003ffff));
 
 	for (i = 0; i < 2; i++)
-		msg_port_write(MEM_CTLR, SCRMLO + i, (lfsr & 0xAAAAAAAA));
+		msg_port_write(MEM_CTLR, SCRMLO + i, (lfsr & 0xaaaaaaaa));
 
 	LEAVEFN();
 }
@@ -2511,20 +2372,20 @@
 	ENTERFN();
 
 	dsch = msg_port_read(MEM_CTLR, DSCH);
-	dsch &= ~(BIT8 | BIT9 | BIT12);
+	dsch &= ~(DSCH_OOODIS | DSCH_OOOST3DIS | DSCH_NEWBYPDIS);
 	msg_port_write(MEM_CTLR, DSCH, dsch);
 
 	dpmc0 = msg_port_read(MEM_CTLR, DPMC0);
-	dpmc0 &= ~BIT25;
+	dpmc0 &= ~DPMC0_DISPWRDN;
 	dpmc0 |= (mrc_params->power_down_disable << 25);
-	dpmc0 &= ~BIT24;
-	dpmc0 &= ~(BIT16 | BIT17 | BIT18);
+	dpmc0 &= ~DPMC0_CLKGTDIS;
+	dpmc0 &= ~DPMC0_PCLSTO_MASK;
 	dpmc0 |= (4 << 16);
-	dpmc0 |= BIT21;
+	dpmc0 |= DPMC0_PREAPWDEN;
 	msg_port_write(MEM_CTLR, DPMC0, dpmc0);
 
 	/* CMDTRIST = 2h - CMD/ADDR are tristated when no valid command */
-	mrc_write_mask(MEM_CTLR, DPMC1, 2 << 4, BIT4 | BIT5);
+	mrc_write_mask(MEM_CTLR, DPMC1, 0x20, 0x30);
 
 	LEAVEFN();
 }
@@ -2542,14 +2403,14 @@
 	ENTERFN();
 
 	dco = msg_port_read(MEM_CTLR, DCO);
-	dco &= ~BIT31;
+	dco &= ~DCO_IC;
 	msg_port_write(MEM_CTLR, DCO, dco);
 
 	drp = 0;
 	if (mrc_params->rank_enables & 1)
-		drp |= BIT0;
+		drp |= DRP_RKEN0;
 	if (mrc_params->rank_enables & 2)
-		drp |= BIT1;
+		drp |= DRP_RKEN1;
 	if (mrc_params->dram_width == X16) {
 		drp |= (1 << 4);
 		drp |= (1 << 9);
@@ -2570,8 +2431,8 @@
 
 	msg_port_write(MEM_CTLR, DRP, drp);
 
-	dco &= ~BIT28;
-	dco |= BIT31;
+	dco &= ~DCO_PMICTL;
+	dco |= DCO_IC;
 	msg_port_write(MEM_CTLR, DCO, dco);
 
 	LEAVEFN();
@@ -2600,18 +2461,18 @@
 	ENTERFN();
 
 	drfc = msg_port_read(MEM_CTLR, DRFC);
-	drfc &= ~(BIT12 | BIT13 | BIT14);
+	drfc &= ~DRFC_TREFI_MASK;
 	drfc |= (mrc_params->refresh_rate << 12);
-	drfc |= BIT21;
+	drfc |= DRFC_REFDBTCLR;
 	msg_port_write(MEM_CTLR, DRFC, drfc);
 
 	dcal = msg_port_read(MEM_CTLR, DCAL);
-	dcal &= ~(BIT8 | BIT9 | BIT10);
+	dcal &= ~DCAL_ZQCINT_MASK;
 	dcal |= (3 << 8);	/* 63ms */
 	msg_port_write(MEM_CTLR, DCAL, dcal);
 
 	dpmc0 = msg_port_read(MEM_CTLR, DPMC0);
-	dpmc0 |= (BIT23 | BIT29);
+	dpmc0 |= (DPMC0_DYNSREN | DPMC0_ENPHYCLKGATE);
 	msg_port_write(MEM_CTLR, DPMC0, dpmc0);
 
 	LEAVEFN();
@@ -2638,36 +2499,32 @@
 	for (channel = 0; channel < NUM_CHANNELS; channel++) {
 		if (mrc_params->channel_enables & (1 << channel)) {
 			/* Enable Periodic RCOMPS */
-			mrc_alt_write_mask(DDRPHY, CMPCTRL, BIT1, BIT1);
+			mrc_alt_write_mask(DDRPHY, CMPCTRL, 2, 2);
 
 			/* Enable Dynamic DiffAmp & Set Read ODT Value */
 			switch (mrc_params->rd_odt_value) {
 			case 0:
-				temp = 0x3F;	/* OFF */
+				temp = 0x3f;	/* OFF */
 				break;
 			default:
 				temp = 0x00;	/* Auto */
 				break;
 			}
 
-			for (bl = 0; bl < ((NUM_BYTE_LANES / bl_divisor) / 2); bl++) {
+			for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor) / 2; bl++) {
 				/* Override: DIFFAMP, ODT */
 				mrc_alt_write_mask(DDRPHY,
-					(B0OVRCTL + (bl * DDRIODQ_BL_OFFSET) +
-					(channel * DDRIODQ_CH_OFFSET)),
-					(0x00 << 16) | (temp << 10),
-					(BIT21 | BIT20 | BIT19 | BIT18 |
-					 BIT17 | BIT16 | BIT15 | BIT14 |
-					 BIT13 | BIT12 | BIT11 | BIT10));
+					B0OVRCTL + bl * DDRIODQ_BL_OFFSET +
+					channel * DDRIODQ_CH_OFFSET,
+					temp << 10,
+					0x003ffc00);
 
 				/* Override: DIFFAMP, ODT */
 				mrc_alt_write_mask(DDRPHY,
-					(B1OVRCTL + (bl * DDRIODQ_BL_OFFSET) +
-					(channel * DDRIODQ_CH_OFFSET)),
-					(0x00 << 16) | (temp << 10),
-					(BIT21 | BIT20 | BIT19 | BIT18 |
-					 BIT17 | BIT16 | BIT15 | BIT14 |
-					 BIT13 | BIT12 | BIT11 | BIT10));
+					B1OVRCTL + bl * DDRIODQ_BL_OFFSET +
+					channel * DDRIODQ_CH_OFFSET,
+					temp << 10,
+					0x003ffc00);
 			}
 
 			/* Issue ZQCS command */
@@ -2702,18 +2559,18 @@
 
 	/* Configuration required in ECC mode */
 	drp = msg_port_read(MEM_CTLR, DRP);
-	drp &= ~(BIT14 | BIT15);
-	drp |= BIT15;
-	drp |= BIT13;
+	drp &= ~DRP_ADDRMAP_MASK;
+	drp |= DRP_ADDRMAP_MAP1;
+	drp |= DRP_PRI64BSPLITEN;
 	msg_port_write(MEM_CTLR, DRP, drp);
 
 	/* Disable new request bypass */
 	dsch = msg_port_read(MEM_CTLR, DSCH);
-	dsch |= BIT12;
+	dsch |= DSCH_NEWBYPDIS;
 	msg_port_write(MEM_CTLR, DSCH, dsch);
 
 	/* Enable ECC */
-	ecc_ctrl = (BIT0 | BIT1 | BIT17);
+	ecc_ctrl = (DECCCTRL_SBEEN | DECCCTRL_DBEEN | DECCCTRL_ENCBGEN);
 	msg_port_write(MEM_CTLR, DECCCTRL, ecc_ctrl);
 
 	/* Assume 8 bank memory, one bank is gone for ECC */
@@ -2756,8 +2613,8 @@
 	ENTERFN();
 
 	dco = msg_port_read(MEM_CTLR, DCO);
-	dco &= ~(BIT28 | BIT29);
-	dco |= (BIT0 | BIT8);
+	dco &= ~(DCO_PMICTL | DCO_PMIDIS);
+	dco |= (DCO_DRPLOCK | DCO_CPGCLOCK);
 	msg_port_write(MEM_CTLR, DCO, dco);
 
 	LEAVEFN();
diff --git a/arch/x86/cpu/quark/smc.h b/arch/x86/cpu/quark/smc.h
index 46017a1..1582b87 100644
--- a/arch/x86/cpu/quark/smc.h
+++ b/arch/x86/cpu/quark/smc.h
@@ -24,46 +24,133 @@
 #define DPMC1			0x07
 #define DRFC			0x08
 #define DSCH			0x09
-#define DCAL			0x0A
-#define DRMC			0x0B
-#define PMSTS			0x0C
-#define DCO			0x0F
+#define DCAL			0x0a
+#define DRMC			0x0b
+#define PMSTS			0x0c
+#define DCO			0x0f
 #define DSTAT			0x20
-#define SSKPD0			0x4A
-#define SSKPD1			0x4B
+#define SSKPD0			0x4a
+#define SSKPD1			0x4b
 #define DECCCTRL		0x60
 #define DECCSTAT		0x61
 #define DECCSBECNT		0x62
 #define DECCSBECA		0x68
 #define DECCSBECS		0x69
-#define DECCDBECA		0x6A
-#define DECCDBECS		0x6B
+#define DECCDBECA		0x6a
+#define DECCDBECS		0x6b
 #define DFUSESTAT		0x70
 #define SCRMSEED		0x80
 #define SCRMLO			0x81
 #define SCRMHI			0x82
 
+/* DRP register defines */
+#define DRP_RKEN0		(1 << 0)
+#define DRP_RKEN1		(1 << 1)
+#define DRP_PRI64BSPLITEN	(1 << 13)
+#define DRP_ADDRMAP_MAP0	(1 << 14)
+#define DRP_ADDRMAP_MAP1	(1 << 15)
+#define DRP_ADDRMAP_MASK	0x0000c000
+
+/* DTR0 register defines */
+#define DTR0_DFREQ_MASK		0x00000003
+#define DTR0_TRP_MASK		0x000000f0
+#define DTR0_TRCD_MASK		0x00000f00
+#define DTR0_TCL_MASK		0x00007000
+
+/* DTR1 register defines */
+#define DTR1_TWCL_MASK		0x00000007
+#define DTR1_TCMD_MASK		0x00000030
+#define DTR1_TWTP_MASK		0x00000f00
+#define DTR1_TCCD_12CLK		(1 << 12)
+#define DTR1_TCCD_18CLK		(1 << 13)
+#define DTR1_TCCD_MASK		0x00003000
+#define DTR1_TFAW_MASK		0x000f0000
+#define DTR1_TRAS_MASK		0x00f00000
+#define DTR1_TRRD_MASK		0x03000000
+#define DTR1_TRTP_MASK		0x70000000
+
+/* DTR2 register defines */
+#define DTR2_TRRDR_MASK		0x00000007
+#define DTR2_TWWDR_MASK		0x00000700
+#define DTR2_TRWDR_MASK		0x000f0000
+
+/* DTR3 register defines */
+#define DTR3_TWRDR_MASK		0x00000007
+#define DTR3_TXXXX_MASK		0x00000070
+#define DTR3_TRWSR_MASK		0x00000f00
+#define DTR3_TWRSR_MASK		0x0001e000
+#define DTR3_TXP_MASK		0x00c00000
+
+/* DTR4 register defines */
+#define DTR4_WRODTSTRT_MASK	0x00000003
+#define DTR4_WRODTSTOP_MASK	0x00000070
+#define DTR4_XXXX1_MASK		0x00000700
+#define DTR4_XXXX2_MASK		0x00007000
+#define DTR4_ODTDIS		(1 << 15)
+#define DTR4_TRGSTRDIS		(1 << 16)
+
+/* DPMC0 register defines */
+#define DPMC0_PCLSTO_MASK	0x00070000
+#define DPMC0_PREAPWDEN		(1 << 21)
+#define DPMC0_DYNSREN		(1 << 23)
+#define DPMC0_CLKGTDIS		(1 << 24)
+#define DPMC0_DISPWRDN		(1 << 25)
+#define DPMC0_ENPHYCLKGATE	(1 << 29)
+
+/* DRFC register defines */
+#define DRFC_TREFI_MASK		0x00007000
+#define DRFC_REFDBTCLR		(1 << 21)
+
+/* DSCH register defines */
+#define DSCH_OOODIS		(1 << 8)
+#define DSCH_OOOST3DIS		(1 << 9)
+#define DSCH_NEWBYPDIS		(1 << 12)
+
+/* DCAL register defines */
+#define DCAL_ZQCINT_MASK	0x00000700
+#define DCAL_SRXZQCL_MASK	0x00003000
+
+/* DRMC register defines */
+#define DRMC_CKEMODE		(1 << 4)
+#define DRMC_ODTMODE		(1 << 12)
+#define DRMC_COLDWAKE		(1 << 16)
+
+/* PMSTS register defines */
+#define PMSTS_DISR		(1 << 0)
+
+/* DCO register defines */
+#define DCO_DRPLOCK		(1 << 0)
+#define DCO_CPGCLOCK		(1 << 8)
+#define DCO_PMICTL		(1 << 28)
+#define DCO_PMIDIS		(1 << 29)
+#define DCO_IC			(1 << 31)
+
+/* DECCCTRL register defines */
+#define DECCCTRL_SBEEN		(1 << 0)
+#define DECCCTRL_DBEEN		(1 << 1)
+#define DECCCTRL_ENCBGEN	(1 << 17)
+
 /* DRAM init command */
 #define DCMD_MRS1(rnk, dat)	(0 | ((rnk) << 22) | (1 << 3) | ((dat) << 6))
 #define DCMD_REF(rnk)		(1 | ((rnk) << 22))
 #define DCMD_PRE(rnk)		(2 | ((rnk) << 22))
-#define DCMD_PREA(rnk)		(2 | ((rnk) << 22) | (BIT10 << 6))
+#define DCMD_PREA(rnk)		(2 | ((rnk) << 22) | (0x400 << 6))
 #define DCMD_ACT(rnk, row)	(3 | ((rnk) << 22) | ((row) << 6))
 #define DCMD_WR(rnk, col)	(4 | ((rnk) << 22) | ((col) << 6))
 #define DCMD_RD(rnk, col)	(5 | ((rnk) << 22) | ((col) << 6))
 #define DCMD_ZQCS(rnk)		(6 | ((rnk) << 22))
-#define DCMD_ZQCL(rnk)		(6 | ((rnk) << 22) | (BIT10 << 6))
+#define DCMD_ZQCL(rnk)		(6 | ((rnk) << 22) | (0x400 << 6))
 #define DCMD_NOP(rnk)		(7 | ((rnk) << 22))
 
-#define DDR3_EMRS1_DIC_40	(0)
-#define DDR3_EMRS1_DIC_34	(1)
+#define DDR3_EMRS1_DIC_40	0
+#define DDR3_EMRS1_DIC_34	1
 
-#define DDR3_EMRS1_RTTNOM_0	(0)
-#define DDR3_EMRS1_RTTNOM_60	(0x04)
-#define DDR3_EMRS1_RTTNOM_120	(0x40)
-#define DDR3_EMRS1_RTTNOM_40	(0x44)
-#define DDR3_EMRS1_RTTNOM_20	(0x200)
-#define DDR3_EMRS1_RTTNOM_30	(0x204)
+#define DDR3_EMRS1_RTTNOM_0	0
+#define DDR3_EMRS1_RTTNOM_60	0x04
+#define DDR3_EMRS1_RTTNOM_120	0x40
+#define DDR3_EMRS1_RTTNOM_40	0x44
+#define DDR3_EMRS1_RTTNOM_20	0x200
+#define DDR3_EMRS1_RTTNOM_30	0x204
 
 #define DDR3_EMRS2_RTTWR_60	(1 << 9)
 #define DDR3_EMRS2_RTTWR_120	(1 << 10)
@@ -80,87 +167,87 @@
 #define DQOBSCKEBBCTL		0x0000
 #define DQDLLTXCTL		0x0004
 #define DQDLLRXCTL		0x0008
-#define DQMDLLCTL		0x000C
+#define DQMDLLCTL		0x000c
 #define B0RXIOBUFCTL		0x0010
 #define B0VREFCTL		0x0014
 #define B0RXOFFSET1		0x0018
-#define B0RXOFFSET0		0x001C
+#define B0RXOFFSET0		0x001c
 #define B1RXIOBUFCTL		0x0020
 #define B1VREFCTL		0x0024
 #define B1RXOFFSET1		0x0028
-#define B1RXOFFSET0		0x002C
+#define B1RXOFFSET0		0x002c
 #define DQDFTCTL		0x0030
 #define DQTRAINSTS		0x0034
 #define B1DLLPICODER0		0x0038
-#define B0DLLPICODER0		0x003C
+#define B0DLLPICODER0		0x003c
 #define B1DLLPICODER1		0x0040
 #define B0DLLPICODER1		0x0044
 #define B1DLLPICODER2		0x0048
-#define B0DLLPICODER2		0x004C
+#define B0DLLPICODER2		0x004c
 #define B1DLLPICODER3		0x0050
 #define B0DLLPICODER3		0x0054
 #define B1RXDQSPICODE		0x0058
-#define B0RXDQSPICODE		0x005C
+#define B0RXDQSPICODE		0x005c
 #define B1RXDQPICODER32		0x0060
 #define B1RXDQPICODER10		0x0064
 #define B0RXDQPICODER32		0x0068
-#define B0RXDQPICODER10		0x006C
+#define B0RXDQPICODER10		0x006c
 #define B01PTRCTL0		0x0070
 #define B01PTRCTL1		0x0074
 #define B01DBCTL0		0x0078
-#define B01DBCTL1		0x007C
+#define B01DBCTL1		0x007c
 #define B0LATCTL0		0x0080
 #define B1LATCTL0		0x0084
 #define B01LATCTL1		0x0088
-#define B0ONDURCTL		0x008C
+#define B0ONDURCTL		0x008c
 #define B1ONDURCTL		0x0090
 #define B0OVRCTL		0x0094
 #define B1OVRCTL		0x0098
-#define DQCTL			0x009C
-#define B0RK2RKCHGPTRCTRL	0x00A0
-#define B1RK2RKCHGPTRCTRL	0x00A4
-#define DQRK2RKCTL		0x00A8
-#define DQRK2RKPTRCTL		0x00AC
-#define B0RK2RKLAT		0x00B0
-#define B1RK2RKLAT		0x00B4
-#define DQCLKALIGNREG0		0x00B8
-#define DQCLKALIGNREG1		0x00BC
-#define DQCLKALIGNREG2		0x00C0
-#define DQCLKALIGNSTS0		0x00C4
-#define DQCLKALIGNSTS1		0x00C8
-#define DQCLKGATE		0x00CC
-#define B0COMPSLV1		0x00D0
-#define B1COMPSLV1		0x00D4
-#define B0COMPSLV2		0x00D8
-#define B1COMPSLV2		0x00DC
-#define B0COMPSLV3		0x00E0
-#define B1COMPSLV3		0x00E4
-#define DQVISALANECR0TOP	0x00E8
-#define DQVISALANECR1TOP	0x00EC
-#define DQVISACONTROLCRTOP	0x00F0
-#define DQVISALANECR0BL		0x00F4
-#define DQVISALANECR1BL		0x00F8
-#define DQVISACONTROLCRBL	0x00FC
-#define DQTIMINGCTRL		0x010C
+#define DQCTL			0x009c
+#define B0RK2RKCHGPTRCTRL	0x00a0
+#define B1RK2RKCHGPTRCTRL	0x00a4
+#define DQRK2RKCTL		0x00a8
+#define DQRK2RKPTRCTL		0x00ac
+#define B0RK2RKLAT		0x00b0
+#define B1RK2RKLAT		0x00b4
+#define DQCLKALIGNREG0		0x00b8
+#define DQCLKALIGNREG1		0x00bc
+#define DQCLKALIGNREG2		0x00c0
+#define DQCLKALIGNSTS0		0x00c4
+#define DQCLKALIGNSTS1		0x00c8
+#define DQCLKGATE		0x00cc
+#define B0COMPSLV1		0x00d0
+#define B1COMPSLV1		0x00d4
+#define B0COMPSLV2		0x00d8
+#define B1COMPSLV2		0x00dc
+#define B0COMPSLV3		0x00e0
+#define B1COMPSLV3		0x00e4
+#define DQVISALANECR0TOP	0x00e8
+#define DQVISALANECR1TOP	0x00ec
+#define DQVISACONTROLCRTOP	0x00f0
+#define DQVISALANECR0BL		0x00f4
+#define DQVISALANECR1BL		0x00f8
+#define DQVISACONTROLCRBL	0x00fc
+#define DQTIMINGCTRL		0x010c
 
 /* CH0-ECC */
 #define ECCDLLTXCTL		0x2004
 #define ECCDLLRXCTL		0x2008
-#define ECCMDLLCTL		0x200C
+#define ECCMDLLCTL		0x200c
 #define ECCB1DLLPICODER0	0x2038
 #define ECCB1DLLPICODER1	0x2040
 #define ECCB1DLLPICODER2	0x2048
 #define ECCB1DLLPICODER3	0x2050
 #define ECCB01DBCTL0		0x2078
-#define ECCB01DBCTL1		0x207C
-#define ECCCLKALIGNREG0		0x20B8
-#define ECCCLKALIGNREG1		0x20BC
-#define ECCCLKALIGNREG2		0x20C0
+#define ECCB01DBCTL1		0x207c
+#define ECCCLKALIGNREG0		0x20b8
+#define ECCCLKALIGNREG1		0x20bc
+#define ECCCLKALIGNREG2		0x20c0
 
 /* CH0-CMD */
 #define CMDOBSCKEBBCTL		0x4800
 #define CMDDLLTXCTL		0x4808
-#define CMDDLLRXCTL		0x480C
+#define CMDDLLRXCTL		0x480c
 #define CMDMDLLCTL		0x4810
 #define CMDRCOMPODT		0x4814
 #define CMDDLLPICODER0		0x4820
@@ -170,30 +257,30 @@
 #define CMDCLKALIGNREG0		0x4850
 #define CMDCLKALIGNREG1		0x4854
 #define CMDCLKALIGNREG2		0x4858
-#define CMDPMCONFIG0		0x485C
+#define CMDPMCONFIG0		0x485c
 #define CMDPMDLYREG0		0x4860
 #define CMDPMDLYREG1		0x4864
 #define CMDPMDLYREG2		0x4868
-#define CMDPMDLYREG3		0x486C
+#define CMDPMDLYREG3		0x486c
 #define CMDPMDLYREG4		0x4870
 #define CMDCLKALIGNSTS0		0x4874
 #define CMDCLKALIGNSTS1		0x4878
-#define CMDPMSTS0		0x487C
+#define CMDPMSTS0		0x487c
 #define CMDPMSTS1		0x4880
 #define CMDCOMPSLV		0x4884
-#define CMDBONUS0		0x488C
+#define CMDBONUS0		0x488c
 #define CMDBONUS1		0x4890
 #define CMDVISALANECR0		0x4894
 #define CMDVISALANECR1		0x4898
-#define CMDVISACONTROLCR	0x489C
-#define CMDCLKGATE		0x48A0
-#define CMDTIMINGCTRL		0x48A4
+#define CMDVISACONTROLCR	0x489c
+#define CMDCLKGATE		0x48a0
+#define CMDTIMINGCTRL		0x48a4
 
 /* CH0-CLK-CTL */
 #define CCOBSCKEBBCTL		0x5800
 #define CCRCOMPIO		0x5804
 #define CCDLLTXCTL		0x5808
-#define CCDLLRXCTL		0x580C
+#define CCDLLRXCTL		0x580c
 #define CCMDLLCTL		0x5810
 #define CCRCOMPODT		0x5814
 #define CCDLLPICODER0		0x5820
@@ -205,123 +292,123 @@
 #define CCCLKALIGNREG0		0x5850
 #define CCCLKALIGNREG1		0x5854
 #define CCCLKALIGNREG2		0x5858
-#define CCPMCONFIG0		0x585C
+#define CCPMCONFIG0		0x585c
 #define CCPMDLYREG0		0x5860
 #define CCPMDLYREG1		0x5864
 #define CCPMDLYREG2		0x5868
-#define CCPMDLYREG3		0x586C
+#define CCPMDLYREG3		0x586c
 #define CCPMDLYREG4		0x5870
 #define CCCLKALIGNSTS0		0x5874
 #define CCCLKALIGNSTS1		0x5878
-#define CCPMSTS0		0x587C
+#define CCPMSTS0		0x587c
 #define CCPMSTS1		0x5880
 #define CCCOMPSLV1		0x5884
 #define CCCOMPSLV2		0x5888
-#define CCCOMPSLV3		0x588C
+#define CCCOMPSLV3		0x588c
 #define CCBONUS0		0x5894
 #define CCBONUS1		0x5898
-#define CCVISALANECR0		0x589C
-#define CCVISALANECR1		0x58A0
-#define CCVISACONTROLCR		0x58A4
-#define CCCLKGATE		0x58A8
-#define CCTIMINGCTL		0x58AC
+#define CCVISALANECR0		0x589c
+#define CCVISALANECR1		0x58a0
+#define CCVISACONTROLCR		0x58a4
+#define CCCLKGATE		0x58a8
+#define CCTIMINGCTL		0x58ac
 
 /* COMP */
 #define CMPCTRL			0x6800
 #define SOFTRSTCNTL		0x6804
 #define MSCNTR			0x6808
-#define NMSCNTRL		0x680C
+#define NMSCNTRL		0x680c
 #define LATCH1CTL		0x6814
-#define COMPVISALANECR0		0x681C
+#define COMPVISALANECR0		0x681c
 #define COMPVISALANECR1		0x6820
 #define COMPVISACONTROLCR	0x6824
 #define COMPBONUS0		0x6830
-#define TCOCNTCTRL		0x683C
+#define TCOCNTCTRL		0x683c
 #define DQANAODTPUCTL		0x6840
 #define DQANAODTPDCTL		0x6844
 #define DQANADRVPUCTL		0x6848
-#define DQANADRVPDCTL		0x684C
+#define DQANADRVPDCTL		0x684c
 #define DQANADLYPUCTL		0x6850
 #define DQANADLYPDCTL		0x6854
 #define DQANATCOPUCTL		0x6858
-#define DQANATCOPDCTL		0x685C
+#define DQANATCOPDCTL		0x685c
 #define CMDANADRVPUCTL		0x6868
-#define CMDANADRVPDCTL		0x686C
+#define CMDANADRVPDCTL		0x686c
 #define CMDANADLYPUCTL		0x6870
 #define CMDANADLYPDCTL		0x6874
 #define CLKANAODTPUCTL		0x6880
 #define CLKANAODTPDCTL		0x6884
 #define CLKANADRVPUCTL		0x6888
-#define CLKANADRVPDCTL		0x688C
+#define CLKANADRVPDCTL		0x688c
 #define CLKANADLYPUCTL		0x6890
 #define CLKANADLYPDCTL		0x6894
 #define CLKANATCOPUCTL		0x6898
-#define CLKANATCOPDCTL		0x689C
-#define DQSANAODTPUCTL		0x68A0
-#define DQSANAODTPDCTL		0x68A4
-#define DQSANADRVPUCTL		0x68A8
-#define DQSANADRVPDCTL		0x68AC
-#define DQSANADLYPUCTL		0x68B0
-#define DQSANADLYPDCTL		0x68B4
-#define DQSANATCOPUCTL		0x68B8
-#define DQSANATCOPDCTL		0x68BC
-#define CTLANADRVPUCTL		0x68C8
-#define CTLANADRVPDCTL		0x68CC
-#define CTLANADLYPUCTL		0x68D0
-#define CTLANADLYPDCTL		0x68D4
-#define CHNLBUFSTATIC		0x68F0
-#define COMPOBSCNTRL		0x68F4
-#define COMPBUFFDBG0		0x68F8
-#define COMPBUFFDBG1		0x68FC
+#define CLKANATCOPDCTL		0x689c
+#define DQSANAODTPUCTL		0x68a0
+#define DQSANAODTPDCTL		0x68a4
+#define DQSANADRVPUCTL		0x68a8
+#define DQSANADRVPDCTL		0x68ac
+#define DQSANADLYPUCTL		0x68b0
+#define DQSANADLYPDCTL		0x68b4
+#define DQSANATCOPUCTL		0x68b8
+#define DQSANATCOPDCTL		0x68bc
+#define CTLANADRVPUCTL		0x68c8
+#define CTLANADRVPDCTL		0x68cc
+#define CTLANADLYPUCTL		0x68d0
+#define CTLANADLYPDCTL		0x68d4
+#define CHNLBUFSTATIC		0x68f0
+#define COMPOBSCNTRL		0x68f4
+#define COMPBUFFDBG0		0x68f8
+#define COMPBUFFDBG1		0x68fc
 #define CFGMISCCH0		0x6900
 #define COMPEN0CH0		0x6904
 #define COMPEN1CH0		0x6908
-#define COMPEN2CH0		0x690C
+#define COMPEN2CH0		0x690c
 #define STATLEGEN0CH0		0x6910
 #define STATLEGEN1CH0		0x6914
 #define DQVREFCH0		0x6918
-#define CMDVREFCH0		0x691C
+#define CMDVREFCH0		0x691c
 #define CLKVREFCH0		0x6920
 #define DQSVREFCH0		0x6924
 #define CTLVREFCH0		0x6928
-#define TCOVREFCH0		0x692C
+#define TCOVREFCH0		0x692c
 #define DLYSELCH0		0x6930
 #define TCODRAMBUFODTCH0	0x6934
 #define CCBUFODTCH0		0x6938
-#define RXOFFSETCH0		0x693C
+#define RXOFFSETCH0		0x693c
 #define DQODTPUCTLCH0		0x6940
 #define DQODTPDCTLCH0		0x6944
 #define DQDRVPUCTLCH0		0x6948
-#define DQDRVPDCTLCH0		0x694C
+#define DQDRVPDCTLCH0		0x694c
 #define DQDLYPUCTLCH0		0x6950
 #define DQDLYPDCTLCH0		0x6954
 #define DQTCOPUCTLCH0		0x6958
-#define DQTCOPDCTLCH0		0x695C
+#define DQTCOPDCTLCH0		0x695c
 #define CMDDRVPUCTLCH0		0x6968
-#define CMDDRVPDCTLCH0		0x696C
+#define CMDDRVPDCTLCH0		0x696c
 #define CMDDLYPUCTLCH0		0x6970
 #define CMDDLYPDCTLCH0		0x6974
 #define CLKODTPUCTLCH0		0x6980
 #define CLKODTPDCTLCH0		0x6984
 #define CLKDRVPUCTLCH0		0x6988
-#define CLKDRVPDCTLCH0		0x698C
+#define CLKDRVPDCTLCH0		0x698c
 #define CLKDLYPUCTLCH0		0x6990
 #define CLKDLYPDCTLCH0		0x6994
 #define CLKTCOPUCTLCH0		0x6998
-#define CLKTCOPDCTLCH0		0x699C
-#define DQSODTPUCTLCH0		0x69A0
-#define DQSODTPDCTLCH0		0x69A4
-#define DQSDRVPUCTLCH0		0x69A8
-#define DQSDRVPDCTLCH0		0x69AC
-#define DQSDLYPUCTLCH0		0x69B0
-#define DQSDLYPDCTLCH0		0x69B4
-#define DQSTCOPUCTLCH0		0x69B8
-#define DQSTCOPDCTLCH0		0x69BC
-#define CTLDRVPUCTLCH0		0x69C8
-#define CTLDRVPDCTLCH0		0x69CC
-#define CTLDLYPUCTLCH0		0x69D0
-#define CTLDLYPDCTLCH0		0x69D4
-#define FNLUPDTCTLCH0		0x69F0
+#define CLKTCOPDCTLCH0		0x699c
+#define DQSODTPUCTLCH0		0x69a0
+#define DQSODTPDCTLCH0		0x69a4
+#define DQSDRVPUCTLCH0		0x69a8
+#define DQSDRVPDCTLCH0		0x69ac
+#define DQSDLYPUCTLCH0		0x69b0
+#define DQSDLYPDCTLCH0		0x69b4
+#define DQSTCOPUCTLCH0		0x69b8
+#define DQSTCOPDCTLCH0		0x69bc
+#define CTLDRVPUCTLCH0		0x69c8
+#define CTLDRVPDCTLCH0		0x69cc
+#define CTLDLYPUCTLCH0		0x69d0
+#define CTLDLYPDCTLCH0		0x69d4
+#define FNLUPDTCTLCH0		0x69f0
 
 /* PLL */
 #define MPLLCTRL0		0x7800
@@ -332,17 +419,17 @@
 #define MPLLDFT			0x7828
 #define MPLLMON0CTL		0x7830
 #define MPLLMON1CTL		0x7838
-#define MPLLMON2CTL		0x783C
+#define MPLLMON2CTL		0x783c
 #define SFRTRIM			0x7850
 #define MPLLDFTOUT0		0x7858
-#define MPLLDFTOUT1		0x785C
+#define MPLLDFTOUT1		0x785c
 #define MASTERRSTN		0x7880
 #define PLLLOCKDEL		0x7884
 #define SFRDEL			0x7888
-#define CRUVISALANECR0		0x78F0
-#define CRUVISALANECR1		0x78F4
-#define CRUVISACONTROLCR	0x78F8
-#define IOSFVISALANECR0		0x78FC
+#define CRUVISALANECR0		0x78f0
+#define CRUVISALANECR1		0x78f4
+#define CRUVISACONTROLCR	0x78f8
+#define IOSFVISALANECR0		0x78fc
 #define IOSFVISALANECR1		0x7900
 #define IOSFVISACONTROLCR	0x7904
 
@@ -350,7 +437,7 @@
 
 /* DRAM Specific Message Bus OpCodes */
 #define MSG_OP_DRAM_INIT	0x68
-#define MSG_OP_DRAM_WAKE	0xCA
+#define MSG_OP_DRAM_WAKE	0xca
 
 #define SAMPLE_SIZE		6
 
@@ -377,9 +464,9 @@
 /* offset into "vref_codes[]" for minimum allowed VREF setting */
 #define VREF_MIN		0x00
 /* offset into "vref_codes[]" for maximum allowed VREF setting */
-#define VREF_MAX		0x3F
+#define VREF_MAX		0x3f
 #define RDQS_MIN		0x00	/* minimum RDQS delay value */
-#define RDQS_MAX		0x3F	/* maximum RDQS delay value */
+#define RDQS_MAX		0x3f	/* maximum RDQS delay value */
 
 /* how many WDQ codes to jump while margining */
 #define WDQ_STEP		1
diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S
index f51f112..2e5f9da 100644
--- a/arch/x86/cpu/start.S
+++ b/arch/x86/cpu/start.S
@@ -11,7 +11,6 @@
  */
 
 #include <config.h>
-#include <version.h>
 #include <asm/global_data.h>
 #include <asm/post.h>
 #include <asm/processor.h>
diff --git a/arch/x86/include/asm/config.h b/arch/x86/include/asm/config.h
index ff15828..3a891ba 100644
--- a/arch/x86/include/asm/config.h
+++ b/arch/x86/include/asm/config.h
@@ -7,7 +7,6 @@
 #ifndef _ASM_CONFIG_H_
 #define _ASM_CONFIG_H_
 
-#define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_LMB
 #define CONFIG_SYS_BOOT_RAMDISK_HIGH
 
diff --git a/board/BuR/common/bur_common.h b/board/BuR/common/bur_common.h
index 39afbba..e4896fb 100644
--- a/board/BuR/common/bur_common.h
+++ b/board/BuR/common/bur_common.h
@@ -16,10 +16,9 @@
 
 int load_lcdtiming(struct am335x_lcdpanel *panel);
 void br_summaryscreen(void);
-void blink(u32 blinks, u32 intervall, u32 pin);
 void pmicsetup(u32 mpupll);
 void enable_uart0_pin_mux(void);
-void enable_i2c0_pin_mux(void);
+void enable_i2c_pin_mux(void);
 void enable_board_pin_mux(void);
 int board_eth_init(bd_t *bis);
 
diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c
index 5ff8a7e..ccaa9c6 100644
--- a/board/BuR/common/common.c
+++ b/board/BuR/common/common.c
@@ -441,30 +441,12 @@
 #error "LCD-support with a suitable FB-Driver is mandatory !"
 #endif /* CONFIG_LCD */
 
-void blink(u32 blinks, u32 intervall, u32 pin)
-{
-	gpio_direction_output(pin, 0);
-	int val = 0;
-
-	do {
-		val ^= 0x01;
-		gpio_set_value(pin, val);
-		mdelay(intervall);
-	} while (blinks--);
-
-	gpio_set_value(pin, 0);
-}
-
 #ifdef CONFIG_SPL_BUILD
 void pmicsetup(u32 mpupll)
 {
 	int mpu_vdd;
 	int usb_cur_lim;
 
-	/* setup I2C */
-	enable_i2c0_pin_mux();
-	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
-
 	if (i2c_probe(TPS65217_CHIP_PM)) {
 		puts("PMIC (0x24) not found! skip further initalization.\n");
 		return;
diff --git a/board/BuR/kwb/board.c b/board/BuR/kwb/board.c
index 892311e..6eed7e0 100644
--- a/board/BuR/kwb/board.c
+++ b/board/BuR/kwb/board.c
@@ -124,7 +124,8 @@
 	gpio_direction_output(LCD_PWR, 0);
 
 	/* setup I2C */
-	enable_i2c0_pin_mux();
+	enable_i2c_pin_mux();
+	i2c_set_bus_num(0);
 	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 
 	/* power-ON  3V3 via Resetcontroller */
diff --git a/board/BuR/kwb/mux.c b/board/BuR/kwb/mux.c
index 9f89b5e..2b1d8d3 100644
--- a/board/BuR/kwb/mux.c
+++ b/board/BuR/kwb/mux.c
@@ -180,7 +180,7 @@
 	configure_module_pin_mux(uart0_pin_mux);
 }
 
-void enable_i2c0_pin_mux(void)
+void enable_i2c_pin_mux(void)
 {
 	configure_module_pin_mux(i2c0_pin_mux);
 }
diff --git a/board/BuR/tseries/board.c b/board/BuR/tseries/board.c
index 9402aa4..89e989f 100644
--- a/board/BuR/tseries/board.c
+++ b/board/BuR/tseries/board.c
@@ -123,6 +123,10 @@
 	/* setup LCD-Pixel Clock */
 	writel(0x2, &cmdpll->clklcdcpixelclk);	/* clock comes from perPLL M2 */
 
+	/* setup I2C */
+	enable_i2c_pin_mux();
+	i2c_set_bus_num(0);
+	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 	pmicsetup(0);
 }
 
diff --git a/board/BuR/tseries/mux.c b/board/BuR/tseries/mux.c
index 2c87a63..ac7e885 100644
--- a/board/BuR/tseries/mux.c
+++ b/board/BuR/tseries/mux.c
@@ -226,7 +226,7 @@
 	configure_module_pin_mux(uart0_pin_mux);
 }
 
-void enable_i2c0_pin_mux(void)
+void enable_i2c_pin_mux(void)
 {
 	configure_module_pin_mux(i2c0_pin_mux);
 }
diff --git a/board/alphaproject/ap_sh4a_4a/lowlevel_init.S b/board/alphaproject/ap_sh4a_4a/lowlevel_init.S
index d5900a8..0c40a3c 100644
--- a/board/alphaproject/ap_sh4a_4a/lowlevel_init.S
+++ b/board/alphaproject/ap_sh4a_4a/lowlevel_init.S
@@ -5,7 +5,6 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <config.h>
-#include <version.h>
 #include <asm/processor.h>
 #include <asm/macro.h>
 
diff --git a/board/amcc/acadia/Kconfig b/board/amcc/acadia/Kconfig
index 033deaf..7c0ef53 100644
--- a/board/amcc/acadia/Kconfig
+++ b/board/amcc/acadia/Kconfig
@@ -9,4 +9,8 @@
 config SYS_CONFIG_NAME
 	default "acadia"
 
+config DISPLAY_BOARDINFO
+	bool
+	default y
+
 endif
diff --git a/board/amcc/bamboo/Kconfig b/board/amcc/bamboo/Kconfig
index c0bd40a..d44a36a 100644
--- a/board/amcc/bamboo/Kconfig
+++ b/board/amcc/bamboo/Kconfig
@@ -9,4 +9,8 @@
 config SYS_CONFIG_NAME
 	default "bamboo"
 
+config DISPLAY_BOARDINFO
+	bool
+	default y
+
 endif
diff --git a/board/amcc/bubinga/Kconfig b/board/amcc/bubinga/Kconfig
index 540d9b6..fc40f6e 100644
--- a/board/amcc/bubinga/Kconfig
+++ b/board/amcc/bubinga/Kconfig
@@ -9,4 +9,8 @@
 config SYS_CONFIG_NAME
 	default "bubinga"
 
+config DISPLAY_BOARDINFO
+	bool
+	default y
+
 endif
diff --git a/board/amcc/canyonlands/Kconfig b/board/amcc/canyonlands/Kconfig
index 848e08f..46efa7a 100644
--- a/board/amcc/canyonlands/Kconfig
+++ b/board/amcc/canyonlands/Kconfig
@@ -39,12 +39,4 @@
 config DM_SERIAL
 	default y
 
-config SYS_MALLOC_F
-	bool
-	default y
-
-config SYS_MALLOC_F_LEN
-	hex
-	default 0x400
-
 endif
diff --git a/board/amcc/ebony/Kconfig b/board/amcc/ebony/Kconfig
index 62394b6..ba73148 100644
--- a/board/amcc/ebony/Kconfig
+++ b/board/amcc/ebony/Kconfig
@@ -9,4 +9,8 @@
 config SYS_CONFIG_NAME
 	default "ebony"
 
+config DISPLAY_BOARDINFO
+	bool
+	default y
+
 endif
diff --git a/board/amcc/katmai/Kconfig b/board/amcc/katmai/Kconfig
index fc606cf..59d3ef5 100644
--- a/board/amcc/katmai/Kconfig
+++ b/board/amcc/katmai/Kconfig
@@ -9,4 +9,8 @@
 config SYS_CONFIG_NAME
 	default "katmai"
 
+config DISPLAY_BOARDINFO
+	bool
+	default y
+
 endif
diff --git a/board/amcc/kilauea/Kconfig b/board/amcc/kilauea/Kconfig
index 3f2f434..5dfd9eb 100644
--- a/board/amcc/kilauea/Kconfig
+++ b/board/amcc/kilauea/Kconfig
@@ -9,4 +9,8 @@
 config SYS_CONFIG_NAME
 	default "kilauea"
 
+config DISPLAY_BOARDINFO
+	bool
+	default y
+
 endif
diff --git a/board/amcc/luan/Kconfig b/board/amcc/luan/Kconfig
index 3df90af..36b44ff 100644
--- a/board/amcc/luan/Kconfig
+++ b/board/amcc/luan/Kconfig
@@ -9,4 +9,8 @@
 config SYS_CONFIG_NAME
 	default "luan"
 
+config DISPLAY_BOARDINFO
+	bool
+	default y
+
 endif
diff --git a/board/amcc/makalu/Kconfig b/board/amcc/makalu/Kconfig
index 31ce5f1..7f8498a 100644
--- a/board/amcc/makalu/Kconfig
+++ b/board/amcc/makalu/Kconfig
@@ -9,4 +9,8 @@
 config SYS_CONFIG_NAME
 	default "makalu"
 
+config DISPLAY_BOARDINFO
+	bool
+	default y
+
 endif
diff --git a/board/amcc/ocotea/Kconfig b/board/amcc/ocotea/Kconfig
index 18c1a15..489e8a4 100644
--- a/board/amcc/ocotea/Kconfig
+++ b/board/amcc/ocotea/Kconfig
@@ -9,4 +9,8 @@
 config SYS_CONFIG_NAME
 	default "ocotea"
 
+config DISPLAY_BOARDINFO
+	bool
+	default y
+
 endif
diff --git a/board/amcc/redwood/Kconfig b/board/amcc/redwood/Kconfig
index d710590..fee6441 100644
--- a/board/amcc/redwood/Kconfig
+++ b/board/amcc/redwood/Kconfig
@@ -9,4 +9,8 @@
 config SYS_CONFIG_NAME
 	default "redwood"
 
+config DISPLAY_BOARDINFO
+	bool
+	default y
+
 endif
diff --git a/board/amcc/sequoia/Kconfig b/board/amcc/sequoia/Kconfig
index 67ee3ca..6e6e408 100644
--- a/board/amcc/sequoia/Kconfig
+++ b/board/amcc/sequoia/Kconfig
@@ -9,4 +9,8 @@
 config SYS_CONFIG_NAME
 	default "sequoia"
 
+config DISPLAY_BOARDINFO
+	bool
+	default y
+
 endif
diff --git a/board/amcc/taihu/Kconfig b/board/amcc/taihu/Kconfig
index fc5cb1d..faafb08 100644
--- a/board/amcc/taihu/Kconfig
+++ b/board/amcc/taihu/Kconfig
@@ -9,4 +9,8 @@
 config SYS_CONFIG_NAME
 	default "taihu"
 
+config DISPLAY_BOARDINFO
+	bool
+	default y
+
 endif
diff --git a/board/amcc/taishan/Kconfig b/board/amcc/taishan/Kconfig
index abd07f5..9ad8a4c 100644
--- a/board/amcc/taishan/Kconfig
+++ b/board/amcc/taishan/Kconfig
@@ -9,4 +9,8 @@
 config SYS_CONFIG_NAME
 	default "taishan"
 
+config DISPLAY_BOARDINFO
+	bool
+	default y
+
 endif
diff --git a/board/amcc/walnut/Kconfig b/board/amcc/walnut/Kconfig
index 94e3dc9..d4c451d 100644
--- a/board/amcc/walnut/Kconfig
+++ b/board/amcc/walnut/Kconfig
@@ -9,4 +9,8 @@
 config SYS_CONFIG_NAME
 	default "walnut"
 
+config DISPLAY_BOARDINFO
+	bool
+	default y
+
 endif
diff --git a/board/amcc/yosemite/Kconfig b/board/amcc/yosemite/Kconfig
index dfa1068..ec51236 100644
--- a/board/amcc/yosemite/Kconfig
+++ b/board/amcc/yosemite/Kconfig
@@ -9,4 +9,8 @@
 config SYS_CONFIG_NAME
 	default "yosemite"
 
+config DISPLAY_BOARDINFO
+	bool
+	default y
+
 endif
diff --git a/board/amcc/yucca/Kconfig b/board/amcc/yucca/Kconfig
index 61d9589..338b6a9 100644
--- a/board/amcc/yucca/Kconfig
+++ b/board/amcc/yucca/Kconfig
@@ -9,4 +9,8 @@
 config SYS_CONFIG_NAME
 	default "yucca"
 
+config DISPLAY_BOARDINFO
+	bool
+	default y
+
 endif
diff --git a/board/armadeus/apf27/lowlevel_init.S b/board/armadeus/apf27/lowlevel_init.S
index 4293cb1..2f795e4 100644
--- a/board/armadeus/apf27/lowlevel_init.S
+++ b/board/armadeus/apf27/lowlevel_init.S
@@ -6,7 +6,6 @@
 
 #include <config.h>
 #include <generated/asm-offsets.h>
-#include <version.h>
 #include <asm/macro.h>
 #include <asm/arch/imx-regs.h>
 #include "apf27.h"
diff --git a/board/armltd/integrator/lowlevel_init.S b/board/armltd/integrator/lowlevel_init.S
index 0fb42ad..b50ba98 100644
--- a/board/armltd/integrator/lowlevel_init.S
+++ b/board/armltd/integrator/lowlevel_init.S
@@ -8,7 +8,6 @@
  */
 
 #include <config.h>
-#include <version.h>
 
 	/* Reset using CM control register */
 .global reset_cpu
diff --git a/board/armltd/versatile/lowlevel_init.S b/board/armltd/versatile/lowlevel_init.S
index 902d646..539ba41 100644
--- a/board/armltd/versatile/lowlevel_init.S
+++ b/board/armltd/versatile/lowlevel_init.S
@@ -8,7 +8,6 @@
  */
 
 #include <config.h>
-#include <version.h>
 
 /* Set up the platform, once the cpu has been initialized */
 .globl lowlevel_init
diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig
index 7d5e7be..f5693ae 100644
--- a/board/armltd/vexpress64/Kconfig
+++ b/board/armltd/vexpress64/Kconfig
@@ -1,16 +1,3 @@
-if TARGET_VEXPRESS64_AEMV8A
-
-config SYS_BOARD
-	default "vexpress64"
-
-config SYS_VENDOR
-	default "armltd"
-
-config SYS_CONFIG_NAME
-	default "vexpress_aemv8a"
-
-endif
-
 if TARGET_VEXPRESS64_BASE_FVP
 
 config SYS_BOARD
diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c
index de62864..876cb67 100644
--- a/board/armltd/vexpress64/vexpress64.c
+++ b/board/armltd/vexpress64/vexpress64.c
@@ -11,7 +11,6 @@
 #include <netdev.h>
 #include <asm/io.h>
 #include <linux/compiler.h>
-#include <asm/semihosting.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -33,101 +32,6 @@
 {
 }
 
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
-#ifdef CONFIG_SEMIHOSTING
-	/*
-	 * Please refer to doc/README.semihosting for a more complete
-	 * description.
-	 *
-	 * We require that the board include file defines these env variables:
-	 * - kernel_name
-	 * - kernel_addr_r
-	 * - initrd_name
-	 * - initrd_addr_r
-	 * - fdt_name
-	 * - fdt_addr_r
-	 *
-	 * For the "fdt chosen" startup macro, this code will then define:
-	 * - initrd_end (based on initrd_addr_r plus actual initrd_size)
-	 *
-	 * We will then load the kernel, initrd, and fdt into the specified
-	 * locations in memory in a similar way that the ATF fastmodel code
-	 * uses semihosting calls to load other boot stages and u-boot itself.
-	 */
-
-	/* Env variable strings */
-	char *kernel_name = getenv("kernel_name");
-	char *kernel_addr_str = getenv("kernel_addr_r");
-	char *initrd_name = getenv("initrd_name");
-	char *initrd_addr_str = getenv("initrd_addr_r");
-	char *fdt_name = getenv("fdt_name");
-	char *fdt_addr_str = getenv("fdt_addr_r");
-	char initrd_end_str[64];
-
-	/* Actual addresses converted from env variables */
-	void *kernel_addr_r;
-	void *initrd_addr_r;
-	void *fdt_addr_r;
-
-	/* Actual initrd base and size */
-	unsigned long initrd_base;
-	unsigned long initrd_size;
-
-	/* Space available */
-	int avail;
-
-	/* Make sure the environment variables needed are set */
-	if (!(kernel_addr_str && initrd_addr_str && fdt_addr_str)) {
-		printf("%s: Define {kernel/initrd/fdt}_addr_r\n", __func__);
-		return -1;
-	}
-	if (!(kernel_name && initrd_name && fdt_name)) {
-		printf("%s: Define {kernel/initrd/fdt}_name\n", __func__);
-		return -1;
-	}
-
-	/* Get exact initrd_size */
-	initrd_size = smh_len(initrd_name);
-	if (initrd_size == -1) {
-		printf("%s: Can't get file size for \'%s\'\n", __func__,
-		       initrd_name);
-		return -1;
-	}
-
-	/* Set initrd_end */
-	initrd_base = simple_strtoul(initrd_addr_str, NULL, 16);
-	initrd_addr_r = (void *)initrd_base;
-	sprintf(initrd_end_str, "0x%lx", initrd_base + initrd_size - 1);
-	setenv("initrd_end", initrd_end_str);
-
-	/* Load kernel to memory */
-	fdt_addr_r = (void *)simple_strtoul(fdt_addr_str, NULL, 16);
-	kernel_addr_r = (void *)simple_strtoul(kernel_addr_str, NULL, 16);
-
-	/*
-	 * The kernel must be lower in memory than fdt and loading the
-	 * kernel must not trample the fdt or vice versa.
-	 */
-	avail = fdt_addr_r - kernel_addr_r;
-	if (avail < 0) {
-		printf("%s: fdt must be after kernel\n", __func__);
-		return -1;
-	}
-	smh_load(kernel_name, kernel_addr_r, avail, 1);
-
-	/* Load fdt to memory */
-	smh_load(fdt_name, fdt_addr_r, 0x20000, 1);
-
-	/* Load initrd to memory */
-	smh_load(initrd_name, initrd_addr_r, initrd_size, 1);
-
-#endif				/* CONFIG_SEMIHOSTING */
-	return 0;
-}
-#endif				/* CONFIG_BOARD_LATE_INIT */
-
 /*
  * Board specific ethernet initialization routine.
  */
diff --git a/board/birdland/bav335x/board.h b/board/birdland/bav335x/board.h
index b598ce1..1ea681e 100644
--- a/board/birdland/bav335x/board.h
+++ b/board/birdland/bav335x/board.h
@@ -33,7 +33,7 @@
 	unsigned int  magic;
 	char name[HDR_NAME_LEN];	/* BAV3354 */
 	char version[4];		/* 0B20 - Rev.B2 */
-	char serial[12];
+	char serial[16];
 	char config[32];
 	char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
 };
diff --git a/board/espt/lowlevel_init.S b/board/espt/lowlevel_init.S
index c1d0966..ec9fb88 100644
--- a/board/espt/lowlevel_init.S
+++ b/board/espt/lowlevel_init.S
@@ -8,7 +8,6 @@
  */
 
 #include <config.h>
-#include <version.h>
 #include <asm/processor.h>
 #include <asm/macro.h>
 
diff --git a/board/freescale/m53017evb/u-boot.lds b/board/freescale/m53017evb/u-boot.lds
index de8d09b..b1cae59 100644
--- a/board/freescale/m53017evb/u-boot.lds
+++ b/board/freescale/m53017evb/u-boot.lds
@@ -13,8 +13,6 @@
   .text      :
   {
     arch/m68k/cpu/mcf532x/start.o	(.text*)
-    arch/m68k/cpu/mcf532x/built-in.o	(.text*)
-    arch/m68k/lib/built-in.o		(.text*)
 
     . = DEFINED(env_offset) ? env_offset : .;
     common/env_embedded.o	(.text*)
diff --git a/board/logicpd/imx27lite/lowlevel_init.S b/board/logicpd/imx27lite/lowlevel_init.S
index c286d0d..9cb702f 100644
--- a/board/logicpd/imx27lite/lowlevel_init.S
+++ b/board/logicpd/imx27lite/lowlevel_init.S
@@ -10,7 +10,6 @@
 
 
 #include <config.h>
-#include <version.h>
 #include <asm/macro.h>
 #include <asm/arch/imx-regs.h>
 #include <generated/asm-offsets.h>
diff --git a/board/mpl/vcma9/lowlevel_init.S b/board/mpl/vcma9/lowlevel_init.S
index ee9b7a9..c0d6cc8 100644
--- a/board/mpl/vcma9/lowlevel_init.S
+++ b/board/mpl/vcma9/lowlevel_init.S
@@ -13,8 +13,6 @@
 
 
 #include <config.h>
-#include <version.h>
-
 
 /* register definitions */
 
diff --git a/board/ms7722se/lowlevel_init.S b/board/ms7722se/lowlevel_init.S
index db859f4..a62404f 100644
--- a/board/ms7722se/lowlevel_init.S
+++ b/board/ms7722se/lowlevel_init.S
@@ -11,7 +11,6 @@
  */
 
 #include <config.h>
-#include <version.h>
 
 #include <asm/processor.h>
 #include <asm/macro.h>
diff --git a/board/ms7750se/lowlevel_init.S b/board/ms7750se/lowlevel_init.S
index c02306f..d61640d 100644
--- a/board/ms7750se/lowlevel_init.S
+++ b/board/ms7750se/lowlevel_init.S
@@ -10,7 +10,6 @@
 */
 
 #include <config.h>
-#include <version.h>
 
 #include <asm/processor.h>
 #include <asm/macro.h>
diff --git a/board/raspberrypi/rpi/Kconfig b/board/raspberrypi/rpi/Kconfig
deleted file mode 100644
index 6a538cf..0000000
--- a/board/raspberrypi/rpi/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_RPI
-
-config SYS_BOARD
-	default "rpi"
-
-config SYS_VENDOR
-	default "raspberrypi"
-
-config SYS_SOC
-	default "bcm2835"
-
-config SYS_CONFIG_NAME
-	default "rpi"
-
-endif
diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
index 50a699b..a105953 100644
--- a/board/raspberrypi/rpi/rpi.c
+++ b/board/raspberrypi/rpi/rpi.c
@@ -278,10 +278,17 @@
 	 * https://github.com/pimoroni/RPi.version/blob/master/RPi/version.py
 	 * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=99293&p=690282
 	 * (a few posts down)
+	 *
+	 * For the RPi 1, bit 24 is the "warranty bit", so we mask off just the
+	 * lower byte to use as the board rev:
+	 * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=98367&start=250
+	 * http://www.raspberrypi.org/forums/viewtopic.php?f=31&t=20594
 	 */
 	rpi_board_rev = msg->get_board_rev.body.resp.rev;
 	if (rpi_board_rev & 0x800000)
 		rpi_board_rev = (rpi_board_rev >> 4) & 0xff;
+	else
+		rpi_board_rev &= 0xff;
 	if (rpi_board_rev >= ARRAY_SIZE(models)) {
 		printf("RPI: Board rev %u outside known range\n",
 		       rpi_board_rev);
diff --git a/board/raspberrypi/rpi_2/Kconfig b/board/raspberrypi/rpi_2/Kconfig
deleted file mode 100644
index 032184d..0000000
--- a/board/raspberrypi/rpi_2/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_RPI_2
-
-config SYS_BOARD
-	default "rpi_2"
-
-config SYS_VENDOR
-	default "raspberrypi"
-
-config SYS_SOC
-	default "bcm2835"
-
-config SYS_CONFIG_NAME
-	default "rpi_2"
-
-endif
diff --git a/board/renesas/MigoR/lowlevel_init.S b/board/renesas/MigoR/lowlevel_init.S
index 63ea70a..322e177 100644
--- a/board/renesas/MigoR/lowlevel_init.S
+++ b/board/renesas/MigoR/lowlevel_init.S
@@ -11,7 +11,6 @@
  */
 
 #include <config.h>
-#include <version.h>
 
 #include <asm/processor.h>
 #include <asm/macro.h>
diff --git a/board/renesas/ap325rxa/lowlevel_init.S b/board/renesas/ap325rxa/lowlevel_init.S
index ead5310..867ca51 100644
--- a/board/renesas/ap325rxa/lowlevel_init.S
+++ b/board/renesas/ap325rxa/lowlevel_init.S
@@ -8,7 +8,6 @@
  */
 
 #include <config.h>
-#include <version.h>
 #include <asm/processor.h>
 #include <asm/macro.h>
 
diff --git a/board/renesas/ecovec/lowlevel_init.S b/board/renesas/ecovec/lowlevel_init.S
index e4c40c8..ab604c7 100644
--- a/board/renesas/ecovec/lowlevel_init.S
+++ b/board/renesas/ecovec/lowlevel_init.S
@@ -8,7 +8,6 @@
  */
 
 #include <config.h>
-#include <version.h>
 #include <asm/processor.h>
 #include <asm/macro.h>
 #include <configs/ecovec.h>
diff --git a/board/renesas/r0p7734/lowlevel_init.S b/board/renesas/r0p7734/lowlevel_init.S
index 62668a7..c2fa565 100644
--- a/board/renesas/r0p7734/lowlevel_init.S
+++ b/board/renesas/r0p7734/lowlevel_init.S
@@ -5,7 +5,6 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <config.h>
-#include <version.h>
 #include <asm/processor.h>
 #include <asm/macro.h>
 
diff --git a/board/renesas/r2dplus/lowlevel_init.S b/board/renesas/r2dplus/lowlevel_init.S
index f3392f0..33f6e07 100644
--- a/board/renesas/r2dplus/lowlevel_init.S
+++ b/board/renesas/r2dplus/lowlevel_init.S
@@ -5,7 +5,6 @@
 */
 
 #include <config.h>
-#include <version.h>
 
 #include <asm/processor.h>
 #include <asm/macro.h>
diff --git a/board/renesas/r7780mp/lowlevel_init.S b/board/renesas/r7780mp/lowlevel_init.S
index 471af1d..b27fe29 100644
--- a/board/renesas/r7780mp/lowlevel_init.S
+++ b/board/renesas/r7780mp/lowlevel_init.S
@@ -7,7 +7,6 @@
  */
 
 #include <config.h>
-#include <version.h>
 #include <asm/processor.h>
 #include <asm/macro.h>
 
diff --git a/board/renesas/rsk7203/lowlevel_init.S b/board/renesas/rsk7203/lowlevel_init.S
index c8494cc..ee472a4 100644
--- a/board/renesas/rsk7203/lowlevel_init.S
+++ b/board/renesas/rsk7203/lowlevel_init.S
@@ -5,7 +5,6 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <config.h>
-#include <version.h>
 
 #include <asm/processor.h>
 #include <asm/macro.h>
diff --git a/board/renesas/rsk7264/lowlevel_init.S b/board/renesas/rsk7264/lowlevel_init.S
index 1a7d27d..eae2703 100644
--- a/board/renesas/rsk7264/lowlevel_init.S
+++ b/board/renesas/rsk7264/lowlevel_init.S
@@ -8,7 +8,6 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <config.h>
-#include <version.h>
 
 #include <asm/processor.h>
 #include <asm/macro.h>
diff --git a/board/renesas/rsk7269/lowlevel_init.S b/board/renesas/rsk7269/lowlevel_init.S
index a2b174b..120bc6b 100644
--- a/board/renesas/rsk7269/lowlevel_init.S
+++ b/board/renesas/rsk7269/lowlevel_init.S
@@ -9,7 +9,6 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <config.h>
-#include <version.h>
 
 #include <asm/processor.h>
 #include <asm/macro.h>
diff --git a/board/renesas/sh7752evb/lowlevel_init.S b/board/renesas/sh7752evb/lowlevel_init.S
index 5643a69..cc8b8c0 100644
--- a/board/renesas/sh7752evb/lowlevel_init.S
+++ b/board/renesas/sh7752evb/lowlevel_init.S
@@ -5,7 +5,6 @@
  */
 
 #include <config.h>
-#include <version.h>
 #include <asm/processor.h>
 #include <asm/macro.h>
 
diff --git a/board/renesas/sh7753evb/lowlevel_init.S b/board/renesas/sh7753evb/lowlevel_init.S
index 21987a5..98551e1 100644
--- a/board/renesas/sh7753evb/lowlevel_init.S
+++ b/board/renesas/sh7753evb/lowlevel_init.S
@@ -5,7 +5,6 @@
  */
 
 #include <config.h>
-#include <version.h>
 #include <asm/processor.h>
 #include <asm/macro.h>
 
diff --git a/board/renesas/sh7757lcr/lowlevel_init.S b/board/renesas/sh7757lcr/lowlevel_init.S
index e4c5ea8..6db26d9 100644
--- a/board/renesas/sh7757lcr/lowlevel_init.S
+++ b/board/renesas/sh7757lcr/lowlevel_init.S
@@ -5,7 +5,6 @@
  */
 
 #include <config.h>
-#include <version.h>
 #include <asm/processor.h>
 #include <asm/macro.h>
 
diff --git a/board/renesas/sh7763rdp/lowlevel_init.S b/board/renesas/sh7763rdp/lowlevel_init.S
index e45fbbe..e8e3d6f 100644
--- a/board/renesas/sh7763rdp/lowlevel_init.S
+++ b/board/renesas/sh7763rdp/lowlevel_init.S
@@ -9,7 +9,6 @@
  */
 
 #include <config.h>
-#include <version.h>
 
 #include <asm/processor.h>
 #include <asm/macro.h>
diff --git a/board/renesas/sh7785lcr/lowlevel_init.S b/board/renesas/sh7785lcr/lowlevel_init.S
index 8b729ac..4bda38c 100644
--- a/board/renesas/sh7785lcr/lowlevel_init.S
+++ b/board/renesas/sh7785lcr/lowlevel_init.S
@@ -4,7 +4,6 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <config.h>
-#include <version.h>
 #include <asm/processor.h>
 #include <asm/macro.h>
 
diff --git a/board/samsung/goni/lowlevel_init.S b/board/samsung/goni/lowlevel_init.S
index d52bc09..fdb83e4 100644
--- a/board/samsung/goni/lowlevel_init.S
+++ b/board/samsung/goni/lowlevel_init.S
@@ -8,7 +8,6 @@
  */
 
 #include <config.h>
-#include <version.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/power.h>
diff --git a/board/samsung/smdk2410/lowlevel_init.S b/board/samsung/smdk2410/lowlevel_init.S
index 5de04f1..c3f4187 100644
--- a/board/samsung/smdk2410/lowlevel_init.S
+++ b/board/samsung/smdk2410/lowlevel_init.S
@@ -13,8 +13,6 @@
 
 
 #include <config.h>
-#include <version.h>
-
 
 /* some parameters for the board */
 
diff --git a/board/samsung/smdkc100/lowlevel_init.S b/board/samsung/smdkc100/lowlevel_init.S
index 65e6b7a..91e5357 100644
--- a/board/samsung/smdkc100/lowlevel_init.S
+++ b/board/samsung/smdkc100/lowlevel_init.S
@@ -7,7 +7,6 @@
  */
 
 #include <config.h>
-#include <version.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/power.h>
 
diff --git a/board/samsung/trats/setup.h b/board/samsung/trats/setup.h
index 2f5ccb1..990e5e2 100644
--- a/board/samsung/trats/setup.h
+++ b/board/samsung/trats/setup.h
@@ -11,7 +11,6 @@
 #define _TRATS_SETUP_H
 
 #include <config.h>
-#include <version.h>
 #include <asm/arch/cpu.h>
 
 /* CLK_SRC_CPU: APLL(1), MPLL(1), CORE(0), HPM(0) */
diff --git a/board/scb9328/lowlevel_init.S b/board/scb9328/lowlevel_init.S
index 2475ae8..d572724 100644
--- a/board/scb9328/lowlevel_init.S
+++ b/board/scb9328/lowlevel_init.S
@@ -5,7 +5,6 @@
  */
 
 #include <config.h>
-#include <version.h>
 #include <asm/arch/imx-regs.h>
 
 .globl lowlevel_init
diff --git a/board/shmin/lowlevel_init.S b/board/shmin/lowlevel_init.S
index 35c0945..53b3123 100644
--- a/board/shmin/lowlevel_init.S
+++ b/board/shmin/lowlevel_init.S
@@ -5,7 +5,6 @@
  */
 
 #include <config.h>
-#include <version.h>
 
 #include <asm/processor.h>
 #include <asm/macro.h>
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 9d0eb91..2fcab60 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -132,6 +132,10 @@
 
 endif
 
+config SYS_CLK_FREQ
+	default 912000000 if MACH_SUN7I
+	default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
+
 config SYS_CONFIG_NAME
 	default "sun4i" if MACH_SUN4I
 	default "sun5i" if MACH_SUN5I
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index ef3c937..be48213 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -21,6 +21,7 @@
 F:	configs/Auxtek-T004_defconfig
 F:	configs/mk802_a10s_defconfig
 F:	configs/r7-tv-dongle_defconfig
+F:	configs/UTOO_P66_defconfig
 F:	include/configs/sun6i.h
 F:	configs/CSQ_CS908_defconfig
 F:	configs/Mele_M9_defconfig
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index e1891d1..808bf82 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -215,7 +215,7 @@
 	 * assured it's being powered with suitable core voltage
 	 */
 	if (!power_failed)
-		clock_set_pll1(CONFIG_CLK_FULL_SPEED);
+		clock_set_pll1(CONFIG_SYS_CLK_FREQ);
 	else
 		printf("Failed to set core voltage! Can't set CPU frequency\n");
 }
diff --git a/board/ti/am335x/Kconfig b/board/ti/am335x/Kconfig
index 722f9d5..7cb006f 100644
--- a/board/ti/am335x/Kconfig
+++ b/board/ti/am335x/Kconfig
@@ -47,10 +47,4 @@
 config DM_SERIAL
 	default y if DM
 
-config SYS_MALLOC_F
-	default y if DM
-
-config SYS_MALLOC_F_LEN
-	default 0x400 if DM
-
 endif
diff --git a/common/board_f.c b/common/board_f.c
index 55ede07..f7ffa54 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -494,7 +494,7 @@
 
 #if defined(CONFIG_VIDEO) && (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) && \
 		!defined(CONFIG_ARM) && !defined(CONFIG_X86) && \
-		!defined(CONFIG_BLACKFIN)
+		!defined(CONFIG_BLACKFIN) && !defined(CONFIG_M68K)
 static int reserve_video(void)
 {
 	/* reserve memory for video display (always full pages) */
@@ -968,7 +968,7 @@
 	/* TODO: Why the dependency on CONFIG_8xx? */
 #if defined(CONFIG_VIDEO) && (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) && \
 		!defined(CONFIG_ARM) && !defined(CONFIG_X86) && \
-		!defined(CONFIG_BLACKFIN)
+		!defined(CONFIG_BLACKFIN) && !defined(CONFIG_M68K)
 	reserve_video,
 #endif
 #if !defined(CONFIG_BLACKFIN) && !defined(CONFIG_NIOS2)
@@ -1080,7 +1080,9 @@
 	/* NOTREACHED - board_init_r() does not return */
 	hang();
 }
-#else
+#endif /* CONFIG_X86 */
+
+#ifndef CONFIG_X86
 ulong board_init_f_mem(ulong top)
 {
 	/* Leave space for the stack we are running with now */
@@ -1098,4 +1100,4 @@
 
 	return top;
 }
-#endif /* CONFIG_X86 */
+#endif /* !CONFIG_X86 */
diff --git a/common/cmd_part.c b/common/cmd_part.c
index c99f527..d04588e 100644
--- a/common/cmd_part.c
+++ b/common/cmd_part.c
@@ -53,29 +53,57 @@
 {
 	int ret;
 	block_dev_desc_t *desc;
+	char *var = NULL;
+	bool bootable = false;
+	int i;
 
-	if (argc < 2 || argc > 3)
+	if (argc < 2)
 		return CMD_RET_USAGE;
 
+	if (argc > 2) {
+		for (i = 2; i < argc ; i++) {
+			if (argv[i][0] == '-') {
+				if (!strcmp(argv[i], "-bootable")) {
+					bootable = true;
+				} else {
+					printf("Unknown option %s\n", argv[i]);
+					return CMD_RET_USAGE;
+				}
+			} else {
+				var = argv[i];
+				break;
+			}
+		}
+
+		/* Loops should have been exited at the last argument, which
+		 * as it contained the variable */
+		if (argc != i + 1)
+			return CMD_RET_USAGE;
+	}
+
 	ret = get_device(argv[0], argv[1], &desc);
 	if (ret < 0)
 		return 1;
 
-	if (argc == 3) {
+	if (var != NULL) {
 		int p;
-		char str[512] = { 0, };
+		char str[512] = { '\0', };
 	  disk_partition_t info;
 
 		for (p = 1; p < 128; p++) {
+			char t[5];
 			int r = get_partition_info(desc, p, &info);
 
-			if (r == 0) {
-				char t[5];
-				sprintf(t, "%s%d", str[0] ? " " : "", p);
-				strcat(str, t);
-			}
+			if (r != 0)
+				continue;
+
+			if (bootable && !info.bootable)
+				continue;
+
+			sprintf(t, "%s%d", str[0] ? " " : "", p);
+			strcat(str, t);
 		}
-		setenv(argv[2], str);
+		setenv(var, str);
 		return 0;
 	}
 
@@ -98,7 +126,7 @@
 }
 
 U_BOOT_CMD(
-	part,	5,	1,	do_part,
+	part,	CONFIG_SYS_MAXARGS,	1,	do_part,
 	"disk partition related commands",
 	"part uuid <interface> <dev>:<part>\n"
 	"    - print partition UUID\n"
@@ -106,6 +134,7 @@
 	"    - set environment variable to partition UUID\n"
 	"part list <interface> <dev>\n"
 	"    - print a device's partition table\n"
-	"part list <interface> <dev> <varname>\n"
-	"    - set environment variable to the list of partitions"
+	"part list <interface> <dev> [flags] <varname>\n"
+	"    - set environment variable to the list of partitions\n"
+	"      flags can be -bootable (list only bootable partitions)"
 );
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index c2e596b..e580f22 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -10,7 +10,6 @@
 #include <spl.h>
 #include <asm/u-boot.h>
 #include <mmc.h>
-#include <version.h>
 #include <image.h>
 
 DECLARE_GLOBAL_DATA_PTR;
diff --git a/common/spl/spl_sata.c b/common/spl/spl_sata.c
index d9eb2d6..2a5eb29 100644
--- a/common/spl/spl_sata.c
+++ b/common/spl/spl_sata.c
@@ -15,7 +15,6 @@
 #include <sata.h>
 #include <scsi.h>
 #include <fat.h>
-#include <version.h>
 #include <image.h>
 
 DECLARE_GLOBAL_DATA_PTR;
diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig
index 48a0705..3e19424 100644
--- a/configs/A10-OLinuXino-Lime_defconfig
+++ b/configs/A10-OLinuXino-Lime_defconfig
@@ -7,3 +7,4 @@
 CONFIG_DRAM_CLK=480
 CONFIG_DRAM_ZQ=123
 CONFIG_DRAM_EMR1=4
+CONFIG_SYS_CLK_FREQ=912000000
diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig
index 5c23bc7..fa48331 100644
--- a/configs/Cubietruck_defconfig
+++ b/configs/Cubietruck_defconfig
@@ -1,6 +1,7 @@
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12),USB_EHCI"
 CONFIG_FDTFILE="sun7i-a20-cubietruck.dtb"
+CONFIG_GMAC_TX_DELAY=1
 CONFIG_VIDEO_VGA=y
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
diff --git a/configs/Linksprite_pcDuino3_fdt_defconfig b/configs/Linksprite_pcDuino3_fdt_defconfig
index 1504664..7690d1e 100644
--- a/configs/Linksprite_pcDuino3_fdt_defconfig
+++ b/configs/Linksprite_pcDuino3_fdt_defconfig
@@ -13,5 +13,3 @@
 CONFIG_DRAM_CLK=480
 CONFIG_DRAM_ZQ=122
 CONFIG_DRAM_EMR1=4
-CONFIG_SYS_MALLOC_F=y
-CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/am335x_igep0033_defconfig b/configs/am335x_igep0033_defconfig
index 8d38e26..7ff0a13 100644
--- a/configs/am335x_igep0033_defconfig
+++ b/configs/am335x_igep0033_defconfig
@@ -3,5 +3,3 @@
 CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_ARM=y
 CONFIG_TARGET_AM335X_IGEP0033=y
-CONFIG_SYS_MALLOC_F=y
-CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/birdland_bav335a_defconfig b/configs/birdland_bav335a_defconfig
index 60df411..54ac4d1 100644
--- a/configs/birdland_bav335a_defconfig
+++ b/configs/birdland_bav335a_defconfig
@@ -1,5 +1,8 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
 CONFIG_ARM=y
 CONFIG_TARGET_BAV335X=y
+CONFIG_DM=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_MALLOC_F=y
 CONFIG_BAV_VERSION=1
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
diff --git a/configs/birdland_bav335b_defconfig b/configs/birdland_bav335b_defconfig
index ed3f6fa..9046553 100644
--- a/configs/birdland_bav335b_defconfig
+++ b/configs/birdland_bav335b_defconfig
@@ -1,5 +1,8 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
 CONFIG_ARM=y
 CONFIG_TARGET_BAV335X=y
+CONFIG_DM=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_MALLOC_F=y
 CONFIG_BAV_VERSION=2
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig
index 2fd21cf..f10a5c2 100644
--- a/configs/cm_fx6_defconfig
+++ b/configs/cm_fx6_defconfig
@@ -5,5 +5,3 @@
 CONFIG_DM=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_SERIAL=y
-CONFIG_SYS_MALLOC_F=y
-CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/cm_t335_defconfig b/configs/cm_t335_defconfig
index 086e526..d189799 100644
--- a/configs/cm_t335_defconfig
+++ b/configs/cm_t335_defconfig
@@ -1,5 +1,3 @@
 CONFIG_SPL=y
 CONFIG_ARM=y
 CONFIG_TARGET_CM_T335=y
-CONFIG_SYS_MALLOC_F=y
-CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/gwventana_defconfig b/configs/gwventana_defconfig
index 6eab019..d6bbdc1 100644
--- a/configs/gwventana_defconfig
+++ b/configs/gwventana_defconfig
@@ -3,4 +3,3 @@
 CONFIG_ARM=y
 CONFIG_TARGET_GW_VENTANA=y
 CONFIG_SYS_MALLOC_F=y
-CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/mx6dlsabreauto_defconfig b/configs/mx6dlsabreauto_defconfig
index 47f3f87..8bc5e8b 100644
--- a/configs/mx6dlsabreauto_defconfig
+++ b/configs/mx6dlsabreauto_defconfig
@@ -1,7 +1,5 @@
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6dl.cfg,MX6DL"
 CONFIG_ARM=y
 CONFIG_TARGET_MX6QSABREAUTO=y
-CONFIG_SYS_MALLOC_F=y
-CONFIG_SYS_MALLOC_F_LEN=0x400
 CONFIG_DM=y
 CONFIG_DM_THERMAL=y
diff --git a/configs/mx6qsabreauto_defconfig b/configs/mx6qsabreauto_defconfig
index ab72942..ba9e512 100644
--- a/configs/mx6qsabreauto_defconfig
+++ b/configs/mx6qsabreauto_defconfig
@@ -1,7 +1,5 @@
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q"
 CONFIG_ARM=y
 CONFIG_TARGET_MX6QSABREAUTO=y
-CONFIG_SYS_MALLOC_F=y
-CONFIG_SYS_MALLOC_F_LEN=0x400
 CONFIG_DM=y
 CONFIG_DM_THERMAL=y
diff --git a/configs/mx6qsabresd_defconfig b/configs/mx6qsabresd_defconfig
index 112918b..1764b39 100644
--- a/configs/mx6qsabresd_defconfig
+++ b/configs/mx6qsabresd_defconfig
@@ -1,7 +1,5 @@
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg,MX6Q"
 CONFIG_ARM=y
 CONFIG_TARGET_MX6SABRESD=y
-CONFIG_SYS_MALLOC_F=y
-CONFIG_SYS_MALLOC_F_LEN=0x400
 CONFIG_DM=y
 CONFIG_DM_THERMAL=y
diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig
index cc82322..5c862cf 100644
--- a/configs/mx6sxsabresd_defconfig
+++ b/configs/mx6sxsabresd_defconfig
@@ -1,7 +1,5 @@
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg,MX6SX"
 CONFIG_ARM=y
 CONFIG_TARGET_MX6SXSABRESD=y
-CONFIG_SYS_MALLOC_F=y
-CONFIG_SYS_MALLOC_F_LEN=0x400
 CONFIG_DM=y
 CONFIG_DM_THERMAL=y
diff --git a/configs/nokia_rx51_defconfig b/configs/nokia_rx51_defconfig
index 1bb7664..20a51e1 100644
--- a/configs/nokia_rx51_defconfig
+++ b/configs/nokia_rx51_defconfig
@@ -4,5 +4,3 @@
 CONFIG_DM=n
 CONFIG_DM_SERIAL=n
 CONFIG_DM_GPIO=n
-CONFIG_SYS_MALLOC_F=y
-CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/pcm051_rev1_defconfig b/configs/pcm051_rev1_defconfig
index f417aac..08075e7 100644
--- a/configs/pcm051_rev1_defconfig
+++ b/configs/pcm051_rev1_defconfig
@@ -2,5 +2,3 @@
 CONFIG_SYS_EXTRA_OPTIONS="REV1"
 CONFIG_ARM=y
 CONFIG_TARGET_PCM051=y
-CONFIG_SYS_MALLOC_F=y
-CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig
index cc6f3f5..56deb48 100644
--- a/configs/pcm051_rev3_defconfig
+++ b/configs/pcm051_rev3_defconfig
@@ -2,5 +2,3 @@
 CONFIG_SYS_EXTRA_OPTIONS="REV3"
 CONFIG_ARM=y
 CONFIG_TARGET_PCM051=y
-CONFIG_SYS_MALLOC_F=y
-CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/pengwyn_defconfig b/configs/pengwyn_defconfig
index 9c6ddf4..6346b57 100644
--- a/configs/pengwyn_defconfig
+++ b/configs/pengwyn_defconfig
@@ -1,5 +1,3 @@
 CONFIG_SPL=y
 CONFIG_ARM=y
 CONFIG_TARGET_PENGWYN=y
-CONFIG_SYS_MALLOC_F=y
-CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/pepper_defconfig b/configs/pepper_defconfig
index e14b008..3b042ec 100644
--- a/configs/pepper_defconfig
+++ b/configs/pepper_defconfig
@@ -1,5 +1,3 @@
 CONFIG_SPL=y
 CONFIG_ARM=y
 CONFIG_TARGET_PEPPER=y
-CONFIG_SYS_MALLOC_F=y
-CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/ph1_ld4_defconfig b/configs/ph1_ld4_defconfig
index 292f2ca..aa1805b 100644
--- a/configs/ph1_ld4_defconfig
+++ b/configs/ph1_ld4_defconfig
@@ -2,6 +2,7 @@
 CONFIG_ARCH_UNIPHIER=y
 CONFIG_DM=y
 CONFIG_DM_SERIAL=y
+CONFIG_SPL_DM=y
 CONFIG_DM_I2C=y
 CONFIG_MACH_PH1_LD4=y
 CONFIG_PFC_MICRO_SUPPORT_CARD=y
diff --git a/configs/ph1_pro4_defconfig b/configs/ph1_pro4_defconfig
index 2021862..194f7a5 100644
--- a/configs/ph1_pro4_defconfig
+++ b/configs/ph1_pro4_defconfig
@@ -2,6 +2,7 @@
 CONFIG_ARCH_UNIPHIER=y
 CONFIG_DM=y
 CONFIG_DM_SERIAL=y
+CONFIG_SPL_DM=y
 CONFIG_DM_I2C=y
 CONFIG_MACH_PH1_PRO4=y
 CONFIG_PFC_MICRO_SUPPORT_CARD=y
diff --git a/configs/ph1_sld8_defconfig b/configs/ph1_sld8_defconfig
index cf229ae..e7e7fff 100644
--- a/configs/ph1_sld8_defconfig
+++ b/configs/ph1_sld8_defconfig
@@ -2,6 +2,7 @@
 CONFIG_ARCH_UNIPHIER=y
 CONFIG_DM=y
 CONFIG_DM_SERIAL=y
+CONFIG_SPL_DM=y
 CONFIG_DM_I2C=y
 CONFIG_MACH_PH1_SLD8=y
 CONFIG_PFC_MICRO_SUPPORT_CARD=y
diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig
index b539d4a..965fcae 100644
--- a/configs/rpi_2_defconfig
+++ b/configs/rpi_2_defconfig
@@ -1,4 +1,3 @@
 CONFIG_ARM=y
+CONFIG_ARCH_BCM283X=y
 CONFIG_TARGET_RPI_2=y
-CONFIG_SYS_MALLOC_F=y
-CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig
index 98d3199..8de1d9f 100644
--- a/configs/rpi_defconfig
+++ b/configs/rpi_defconfig
@@ -1,4 +1,3 @@
 CONFIG_ARM=y
+CONFIG_ARCH_BCM283X=y
 CONFIG_TARGET_RPI=y
-CONFIG_SYS_MALLOC_F=y
-CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/s5p_goni_defconfig b/configs/s5p_goni_defconfig
index 33e6fb8..618e590 100644
--- a/configs/s5p_goni_defconfig
+++ b/configs/s5p_goni_defconfig
@@ -2,5 +2,3 @@
 CONFIG_ARCH_S5PC1XX=y
 CONFIG_TARGET_S5P_GONI=y
 CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-goni"
-CONFIG_SYS_MALLOC_F=y
-CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 70f5b86..a216039 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -5,8 +5,6 @@
 CONFIG_FIT_SIGNATURE=y
 CONFIG_DM=y
 CONFIG_DEFAULT_DEVICE_TREE="sandbox"
-CONFIG_SYS_MALLOC_F=y
-CONFIG_SYS_MALLOC_F_LEN=0x400
 CONFIG_CROS_EC=y
 CONFIG_DM_CROS_EC=y
 CONFIG_CROS_EC_SANDBOX=y
diff --git a/configs/smdkc100_defconfig b/configs/smdkc100_defconfig
index e933a32..041030f 100644
--- a/configs/smdkc100_defconfig
+++ b/configs/smdkc100_defconfig
@@ -2,5 +2,3 @@
 CONFIG_TARGET_SMDKC100=y
 CONFIG_ARCH_S5PC1XX=y
 CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-smdkc100"
-CONFIG_SYS_MALLOC_F=y
-CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/snapper9260_defconfig b/configs/snapper9260_defconfig
index 3a47505..576d9c5 100644
--- a/configs/snapper9260_defconfig
+++ b/configs/snapper9260_defconfig
@@ -5,5 +5,3 @@
 CONFIG_DM=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_SERIAL=y
-CONFIG_SYS_MALLOC_F=y
-CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/snapper9g20_defconfig b/configs/snapper9g20_defconfig
index 1f0244b..07a2643 100644
--- a/configs/snapper9g20_defconfig
+++ b/configs/snapper9g20_defconfig
@@ -5,5 +5,3 @@
 CONFIG_DM=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_SERIAL=y
-CONFIG_SYS_MALLOC_F=y
-CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig
index 1c9ba88..e8cf311 100644
--- a/configs/stv0991_defconfig
+++ b/configs/stv0991_defconfig
@@ -1,7 +1,6 @@
 CONFIG_SYS_EXTRA_OPTIONS="stv0991"
 CONFIG_ARM=y
 CONFIG_TARGET_STV0991=y
-CONFIG_SYS_MALLOC_F=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_DM=y
 CONFIG_DM_SERIAL=y
diff --git a/configs/vexpress_aemv8a_defconfig b/configs/vexpress_aemv8a_defconfig
deleted file mode 100644
index 9f4b876..0000000
--- a/configs/vexpress_aemv8a_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_VEXPRESS64_AEMV8A=y
-CONFIG_DEFAULT_DEVICE_TREE="vexpress64"
diff --git a/doc/README.distro b/doc/README.distro
index dd0f1c7..0308a4c 100644
--- a/doc/README.distro
+++ b/doc/README.distro
@@ -1,6 +1,7 @@
 /*
  * (C) Copyright 2014 Red Hat Inc.
  * Copyright (c) 2014-2015, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (C) 2015 K. Merker <merker@debian.org>
  *
  * SPDX-License-Identifier:     GPL-2.0+
  */
@@ -339,3 +340,49 @@
 
   If you want to disable boot.scr on all disks, set the value to something
   innocuous, e.g. setenv scan_dev_for_scripts true.
+
+
+Interactively booting from a specific device at the u-boot prompt
+=================================================================
+
+For interactively booting from a user-selected device at the u-boot command
+prompt, the environment provides predefined bootcmd_<target> variables for
+every target defined in boot_targets, which can be run be the user.
+
+If the target is a storage device, the format of the target is always
+<device type><device number>, e.g. mmc0.  Specifying the device number is
+mandatory for storage devices, even if only support for a single instance
+of the storage device is actually implemented.
+
+For network targets (dhcp, pxe), only the device type gets specified;
+they do not have a device number.
+
+Examples:
+
+ - run bootcmd_usb0
+   boots from the first USB mass storage device
+
+ - run bootcmd_mmc1
+   boots from the second MMC device
+
+ - run bootcmd_pxe
+   boots by tftp using a pxelinux.cfg
+
+The list of possible targets consists of:
+
+- network targets
+  * dhcp
+  * pxe
+
+- storage targets (to which a device number must be appended)
+  * mmc
+  * sata
+  * scsi
+  * ide
+  * usb
+
+Other *boot* variables than the ones defined above are only for internal use
+of the boot environment and are not guaranteed to exist or work in the same
+way in future u-boot versions.  In particular the <device type>_boot
+variables (e.g. mmc_boot, usb_boot) are a strictly internal implementation
+detail and must not be used as a public interface.
diff --git a/doc/README.drivers.eth b/doc/README.drivers.eth
index eb83038..42af442 100644
--- a/doc/README.drivers.eth
+++ b/doc/README.drivers.eth
@@ -43,15 +43,16 @@
 {
 	struct ape_priv *priv;
 	struct eth_device *dev;
+	struct mii_dev *bus;
 
 	priv = malloc(sizeof(*priv));
 	if (priv == NULL)
-		return 1;
+		return -ENOMEM;
 
 	dev = malloc(sizeof(*dev));
 	if (dev == NULL) {
 		free(priv);
-		return 1;
+		return -ENOMEM;
 	}
 
 	/* setup whatever private state you need */
@@ -59,7 +60,8 @@
 	memset(dev, 0, sizeof(*dev));
 	sprintf(dev->name, "APE");
 
-	/* if your device has dedicated hardware storage for the
+	/*
+	 * if your device has dedicated hardware storage for the
 	 * MAC, read it and initialize dev->enetaddr with it
 	 */
 	ape_mac_read(dev->enetaddr);
@@ -74,8 +76,17 @@
 
 	eth_register(dev);
 
-#ifdef CONFIG_CMD_MII)
-	miiphy_register(dev->name, ape_mii_read, ape_mii_write);
+#ifdef CONFIG_PHYLIB
+	bus = mdio_alloc();
+	if (!bus) {
+		free(priv);
+		free(dev);
+		return -ENOMEM;
+	}
+
+	bus->read = ape_mii_read;
+	bus->write = ape_mii_write;
+	mdio_register(bus);
 #endif
 
 	return 1;
@@ -166,25 +177,33 @@
 	eth_halt()
 		dev->halt()
 
------------------------------
- CONFIG_MII / CONFIG_CMD_MII
------------------------------
+--------------------------------
+ CONFIG_PHYLIB / CONFIG_CMD_MII
+--------------------------------
 
 If your device supports banging arbitrary values on the MII bus (pretty much
 every device does), you should add support for the mii command.  Doing so is
 fairly trivial and makes debugging mii issues a lot easier at runtime.
 
 After you have called eth_register() in your driver's register function, add
-a call to miiphy_register() like so:
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
-	miiphy_register(dev->name, mii_read, mii_write);
-#endif
+a call to mdio_alloc() and mdio_register() like so:
+	bus = mdio_alloc();
+	if (!bus) {
+		free(priv);
+		free(dev);
+		return -ENOMEM;
+	}
+
+	bus->read = ape_mii_read;
+	bus->write = ape_mii_write;
+	mdio_register(bus);
 
 And then define the mii_read and mii_write functions if you haven't already.
 Their syntax is straightforward:
-	int mii_read(char *devname, uchar addr, uchar reg, ushort *val);
-	int mii_write(char *devname, uchar addr, uchar reg, ushort val);
+	int mii_read(struct mii_dev *bus, int addr, int devad, int reg);
+	int mii_write(struct mii_dev *bus, int addr, int devad, int reg,
+		      u16 val);
 
 The read function should read the register 'reg' from the phy at address 'addr'
-and store the result in the pointer 'val'.  The implementation for the write
-function should logically follow.
+and return the result to its caller.  The implementation for the write function
+should logically follow.
diff --git a/doc/README.generic-board b/doc/README.generic-board
index 37c1b03..bd8eae1 100644
--- a/doc/README.generic-board
+++ b/doc/README.generic-board
@@ -44,16 +44,18 @@
 
    arc
    arm
+   avr32
+   blackfin
+   m68k
+   microblaze
    mips
+   nios2
    powerpc
    sandbox
    x86
 
-If your architecture is not supported, you need to adjust your
-arch/<arch>/config.mk file to include:
-
-   __HAVE_ARCH_GENERIC_BOARD := y
-
+If your architecture is not supported, you need to select
+HAVE_GENERIC_BOARD in arch/Kconfig
 and test it with a suitable board, as follows.
 
 
diff --git a/doc/README.semihosting b/doc/README.semihosting
index 7248560..c016a4f 100644
--- a/doc/README.semihosting
+++ b/doc/README.semihosting
@@ -30,25 +30,10 @@
 absence of CONFIG_BASE_FVP. This change is tested and works on both the
 Foundation and Base fastmodel simulators.
 
-The level of semihosting support is minimal, restricted to just what it
-takes to load images to memory. If more semihosting functionality is
-required, such as file seek, outputting strings, reading characters, etc,
-then it can be easily added later.
+The semihosting code adds a command:
 
-We require that the board include file define these env variables:
-- kernel_name		e.g. "uImage"
-- kernel_addr_r		e.g. "0x80000000"
-- initrd_name		e.g. "ramdisk.img"
-- initrd_addr_r		e.g. "0x88000000"
-- fdt_name		e.g. "devtree.dtb"
-- fdt_addr_r		e.g. "0x83000000"
-
-Optionally, "fdt_high" and "initrd_high" can be specified as per
-their rules for allowing or preventing copying of these images.
-
-For the "fdt chosen" startup macro, this code will then define:
-- initrd_end (based on retrieving initrd_addr_r plus actual initrd_size)
+  smhload <image> <address> [env var]
 
-We will then load the kernel, initrd, and fdt into the specified
-locations in memory in a similar way that the ATF fastmodel code
-uses semihosting calls to load other boot stages and u-boot itself.
+That will load an image from the host filesystem into RAM at the specified
+address and optionally store the load end address in the specified
+environment variable.
diff --git a/doc/README.x86 b/doc/README.x86
index fb87682..0355d1c 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -105,6 +105,13 @@
 Rename the first one to fsp.bin and second one to cmc.bin and put them in the
 board directory.
 
+Note the FSP release version 001 has a bug which could cause random endless
+loop during the FspInit call. This bug was published by Intel although Intel
+did not describe any details. We need manually apply the patch to the FSP
+binary using any hex editor (eg: bvi). Go to the offset 0x1fcd8 of the FSP
+binary, change the following five bytes values from orginally E8 42 FF FF FF
+to B8 00 80 0B 00.
+
 Now you can build U-Boot and obtain u-boot.rom
 
 $ make crownbay_defconfig
diff --git a/drivers/mmc/bcm2835_sdhci.c b/drivers/mmc/bcm2835_sdhci.c
index 92f7d89..4ec2968 100644
--- a/drivers/mmc/bcm2835_sdhci.c
+++ b/drivers/mmc/bcm2835_sdhci.c
@@ -39,8 +39,8 @@
 #include <common.h>
 #include <malloc.h>
 #include <sdhci.h>
-#include <asm/arch/timer.h>
-#include <asm/arch-bcm2835/sdhci.h>
+#include <mach/timer.h>
+#include <mach/sdhci.h>
 
 /* 400KHz is max freq for card ID etc. Use that as min */
 #define MIN_FREQ 400000
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index b8b0803..3ff86b7 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -46,6 +46,7 @@
 obj-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o
 obj-$(CONFIG_NETCONSOLE) += netconsole.o
 obj-$(CONFIG_NS8382X) += ns8382x.o
+obj-$(CONFIG_PCH_GBE) += pch_gbe.o
 obj-$(CONFIG_PCNET) += pcnet.o
 obj-$(CONFIG_RTL8139) += rtl8139.o
 obj-$(CONFIG_RTL8169) += rtl8169.o
diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h
index 6d110eb..f3b77b1 100644
--- a/drivers/net/e1000.h
+++ b/drivers/net/e1000.h
@@ -430,12 +430,11 @@
 #define ENET_HEADER_SIZE	     14
 #define MAXIMUM_ETHERNET_FRAME_SIZE  1518	/* With FCS */
 #define MINIMUM_ETHERNET_FRAME_SIZE  64	/* With FCS */
-#define ETHERNET_FCS_SIZE	     4
 #define MAXIMUM_ETHERNET_PACKET_SIZE \
-    (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
+	(MAXIMUM_ETHERNET_FRAME_SIZE - ETH_FCS_LEN)
 #define MINIMUM_ETHERNET_PACKET_SIZE \
-    (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
-#define CRC_LENGTH		     ETHERNET_FCS_SIZE
+	(MINIMUM_ETHERNET_FRAME_SIZE - ETH_FCS_LEN)
+#define CRC_LENGTH		     ETH_FCS_LEN
 #define MAX_JUMBO_FRAME_SIZE	     0x3F00
 
 /* 802.1q VLAN Packet Sizes */
diff --git a/drivers/net/pch_gbe.c b/drivers/net/pch_gbe.c
new file mode 100644
index 0000000..976848d
--- /dev/null
+++ b/drivers/net/pch_gbe.c
@@ -0,0 +1,466 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Intel Platform Controller Hub EG20T (codename Topcliff) GMAC Driver
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <pci.h>
+#include <malloc.h>
+#include <miiphy.h>
+#include "pch_gbe.h"
+
+#if !defined(CONFIG_PHYLIB)
+# error "PCH Gigabit Ethernet driver requires PHYLIB - missing CONFIG_PHYLIB"
+#endif
+
+static struct pci_device_id supported[] = {
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_GBE },
+	{ }
+};
+
+static void pch_gbe_mac_read(struct pch_gbe_regs *mac_regs, u8 *addr)
+{
+	u32 macid_hi, macid_lo;
+
+	macid_hi = readl(&mac_regs->mac_adr[0].high);
+	macid_lo = readl(&mac_regs->mac_adr[0].low) & 0xffff;
+	debug("pch_gbe: macid_hi %#x macid_lo %#x\n", macid_hi, macid_lo);
+
+	addr[0] = (u8)(macid_hi & 0xff);
+	addr[1] = (u8)((macid_hi >> 8) & 0xff);
+	addr[2] = (u8)((macid_hi >> 16) & 0xff);
+	addr[3] = (u8)((macid_hi >> 24) & 0xff);
+	addr[4] = (u8)(macid_lo & 0xff);
+	addr[5] = (u8)((macid_lo >> 8) & 0xff);
+}
+
+static int pch_gbe_mac_write(struct pch_gbe_regs *mac_regs, u8 *addr)
+{
+	u32 macid_hi, macid_lo;
+	ulong start;
+
+	macid_hi = addr[0] + (addr[1] << 8) + (addr[2] << 16) + (addr[3] << 24);
+	macid_lo = addr[4] + (addr[5] << 8);
+
+	writel(macid_hi, &mac_regs->mac_adr[0].high);
+	writel(macid_lo, &mac_regs->mac_adr[0].low);
+	writel(0xfffe, &mac_regs->addr_mask);
+
+	start = get_timer(0);
+	while (get_timer(start) < PCH_GBE_TIMEOUT) {
+		if (!(readl(&mac_regs->addr_mask) & PCH_GBE_BUSY))
+			return 0;
+
+		udelay(10);
+	}
+
+	return -ETIME;
+}
+
+static int pch_gbe_reset(struct eth_device *dev)
+{
+	struct pch_gbe_priv *priv = dev->priv;
+	struct pch_gbe_regs *mac_regs = priv->mac_regs;
+	ulong start;
+
+	priv->rx_idx = 0;
+	priv->tx_idx = 0;
+
+	writel(PCH_GBE_ALL_RST, &mac_regs->reset);
+
+	/*
+	 * Configure the MAC to RGMII mode after reset
+	 *
+	 * For some unknown reason, we must do the configuration here right
+	 * after resetting the whole MAC, otherwise the reset bit in the RESET
+	 * register will never be cleared by the hardware. And there is another
+	 * way of having the same magic, that is to configure the MODE register
+	 * to have the MAC work in MII/GMII mode, which is how current Linux
+	 * pch_gbe driver does. Since anyway we need program the MAC to RGMII
+	 * mode in the driver, we just do it here.
+	 *
+	 * Note: this behavior is not documented in the hardware manual.
+	 */
+	writel(PCH_GBE_RGMII_MODE_RGMII | PCH_GBE_CHIP_TYPE_INTERNAL,
+	       &mac_regs->rgmii_ctrl);
+
+	start = get_timer(0);
+	while (get_timer(start) < PCH_GBE_TIMEOUT) {
+		if (!(readl(&mac_regs->reset) & PCH_GBE_ALL_RST)) {
+			/*
+			 * Soft reset clears hardware MAC address registers,
+			 * so we have to reload MAC address here in order to
+			 * make linux pch_gbe driver happy.
+			 */
+			return pch_gbe_mac_write(mac_regs, dev->enetaddr);
+		}
+
+		udelay(10);
+	}
+
+	debug("pch_gbe: reset timeout\n");
+	return -ETIME;
+}
+
+static void pch_gbe_rx_descs_init(struct eth_device *dev)
+{
+	struct pch_gbe_priv *priv = dev->priv;
+	struct pch_gbe_regs *mac_regs = priv->mac_regs;
+	struct pch_gbe_rx_desc *rx_desc = &priv->rx_desc[0];
+	int i;
+
+	memset(rx_desc, 0, sizeof(struct pch_gbe_rx_desc) * PCH_GBE_DESC_NUM);
+	for (i = 0; i < PCH_GBE_DESC_NUM; i++)
+		rx_desc->buffer_addr = pci_phys_to_mem(priv->bdf,
+			(u32)(priv->rx_buff[i]));
+
+	writel(pci_phys_to_mem(priv->bdf, (u32)rx_desc),
+	       &mac_regs->rx_dsc_base);
+	writel(sizeof(struct pch_gbe_rx_desc) * (PCH_GBE_DESC_NUM - 1),
+	       &mac_regs->rx_dsc_size);
+
+	writel(pci_phys_to_mem(priv->bdf, (u32)(rx_desc + 1)),
+	       &mac_regs->rx_dsc_sw_p);
+}
+
+static void pch_gbe_tx_descs_init(struct eth_device *dev)
+{
+	struct pch_gbe_priv *priv = dev->priv;
+	struct pch_gbe_regs *mac_regs = priv->mac_regs;
+	struct pch_gbe_tx_desc *tx_desc = &priv->tx_desc[0];
+
+	memset(tx_desc, 0, sizeof(struct pch_gbe_tx_desc) * PCH_GBE_DESC_NUM);
+
+	writel(pci_phys_to_mem(priv->bdf, (u32)tx_desc),
+	       &mac_regs->tx_dsc_base);
+	writel(sizeof(struct pch_gbe_tx_desc) * (PCH_GBE_DESC_NUM - 1),
+	       &mac_regs->tx_dsc_size);
+	writel(pci_phys_to_mem(priv->bdf, (u32)(tx_desc + 1)),
+	       &mac_regs->tx_dsc_sw_p);
+}
+
+static void pch_gbe_adjust_link(struct pch_gbe_regs *mac_regs,
+				struct phy_device *phydev)
+{
+	if (!phydev->link) {
+		printf("%s: No link.\n", phydev->dev->name);
+		return;
+	}
+
+	clrbits_le32(&mac_regs->rgmii_ctrl,
+		     PCH_GBE_RGMII_RATE_2_5M | PCH_GBE_CRS_SEL);
+	clrbits_le32(&mac_regs->mode,
+		     PCH_GBE_MODE_GMII_ETHER | PCH_GBE_MODE_FULL_DUPLEX);
+
+	switch (phydev->speed) {
+	case 1000:
+		setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_RGMII_RATE_125M);
+		setbits_le32(&mac_regs->mode, PCH_GBE_MODE_GMII_ETHER);
+		break;
+	case 100:
+		setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_RGMII_RATE_25M);
+		setbits_le32(&mac_regs->mode, PCH_GBE_MODE_MII_ETHER);
+		break;
+	case 10:
+		setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_RGMII_RATE_2_5M);
+		setbits_le32(&mac_regs->mode, PCH_GBE_MODE_MII_ETHER);
+		break;
+	}
+
+	if (phydev->duplex) {
+		setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_CRS_SEL);
+		setbits_le32(&mac_regs->mode, PCH_GBE_MODE_FULL_DUPLEX);
+	}
+
+	printf("Speed: %d, %s duplex\n", phydev->speed,
+	       (phydev->duplex) ? "full" : "half");
+
+	return;
+}
+
+static int pch_gbe_init(struct eth_device *dev, bd_t *bis)
+{
+	struct pch_gbe_priv *priv = dev->priv;
+	struct pch_gbe_regs *mac_regs = priv->mac_regs;
+
+	if (pch_gbe_reset(dev))
+		return -1;
+
+	pch_gbe_rx_descs_init(dev);
+	pch_gbe_tx_descs_init(dev);
+
+	/* Enable frame bursting */
+	writel(PCH_GBE_MODE_FR_BST, &mac_regs->mode);
+	/* Disable TCP/IP accelerator */
+	writel(PCH_GBE_RX_TCPIPACC_OFF, &mac_regs->tcpip_acc);
+	/* Disable RX flow control */
+	writel(0, &mac_regs->rx_fctrl);
+	/* Configure RX/TX mode */
+	writel(PCH_GBE_RH_ALM_EMP_16 | PCH_GBE_RH_ALM_FULL_16 |
+	       PCH_GBE_RH_RD_TRG_32, &mac_regs->rx_mode);
+	writel(PCH_GBE_TM_TH_TX_STRT_32 | PCH_GBE_TM_TH_ALM_EMP_16 |
+	       PCH_GBE_TM_TH_ALM_FULL_32 | PCH_GBE_TM_ST_AND_FD |
+	       PCH_GBE_TM_SHORT_PKT, &mac_regs->tx_mode);
+
+	/* Start up the PHY */
+	if (phy_startup(priv->phydev)) {
+		printf("Could not initialize PHY %s\n",
+		       priv->phydev->dev->name);
+		return -1;
+	}
+
+	pch_gbe_adjust_link(mac_regs, priv->phydev);
+
+	if (!priv->phydev->link)
+		return -1;
+
+	/* Enable TX & RX */
+	writel(PCH_GBE_RX_DMA_EN | PCH_GBE_TX_DMA_EN, &mac_regs->dma_ctrl);
+	writel(PCH_GBE_MRE_MAC_RX_EN, &mac_regs->mac_rx_en);
+
+	return 0;
+}
+
+static void pch_gbe_halt(struct eth_device *dev)
+{
+	struct pch_gbe_priv *priv = dev->priv;
+
+	pch_gbe_reset(dev);
+
+	phy_shutdown(priv->phydev);
+}
+
+static int pch_gbe_send(struct eth_device *dev, void *packet, int length)
+{
+	struct pch_gbe_priv *priv = dev->priv;
+	struct pch_gbe_regs *mac_regs = priv->mac_regs;
+	struct pch_gbe_tx_desc *tx_head, *tx_desc;
+	u16 frame_ctrl = 0;
+	u32 int_st;
+	ulong start;
+
+	tx_head = &priv->tx_desc[0];
+	tx_desc = &priv->tx_desc[priv->tx_idx];
+
+	if (length < 64)
+		frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
+
+	tx_desc->buffer_addr = pci_phys_to_mem(priv->bdf, (u32)packet);
+	tx_desc->length = length;
+	tx_desc->tx_words_eob = length + 3;
+	tx_desc->tx_frame_ctrl = frame_ctrl;
+	tx_desc->dma_status = 0;
+	tx_desc->gbec_status = 0;
+
+	/* Test the wrap-around condition */
+	if (++priv->tx_idx >= PCH_GBE_DESC_NUM)
+		priv->tx_idx = 0;
+
+	writel(pci_phys_to_mem(priv->bdf, (u32)(tx_head + priv->tx_idx)),
+	       &mac_regs->tx_dsc_sw_p);
+
+	start = get_timer(0);
+	while (get_timer(start) < PCH_GBE_TIMEOUT) {
+		int_st = readl(&mac_regs->int_st);
+		if (int_st & PCH_GBE_INT_TX_CMPLT)
+			return 0;
+
+		udelay(10);
+	}
+
+	debug("pch_gbe: sent failed\n");
+	return -ETIME;
+}
+
+static int pch_gbe_recv(struct eth_device *dev)
+{
+	struct pch_gbe_priv *priv = dev->priv;
+	struct pch_gbe_regs *mac_regs = priv->mac_regs;
+	struct pch_gbe_rx_desc *rx_head, *rx_desc;
+	u32 hw_desc, buffer_addr, length;
+	int rx_swp;
+
+	rx_head = &priv->rx_desc[0];
+	rx_desc = &priv->rx_desc[priv->rx_idx];
+
+	readl(&mac_regs->int_st);
+	hw_desc = readl(&mac_regs->rx_dsc_hw_p_hld);
+
+	/* Just return if not receiving any packet */
+	if ((u32)rx_desc == hw_desc)
+		return 0;
+
+	buffer_addr = pci_mem_to_phys(priv->bdf, rx_desc->buffer_addr);
+	length = rx_desc->rx_words_eob - 3 - ETH_FCS_LEN;
+	NetReceive((uchar *)buffer_addr, length);
+
+	/* Test the wrap-around condition */
+	if (++priv->rx_idx >= PCH_GBE_DESC_NUM)
+		priv->rx_idx = 0;
+	rx_swp = priv->rx_idx;
+	if (++rx_swp >= PCH_GBE_DESC_NUM)
+		rx_swp = 0;
+
+	writel(pci_phys_to_mem(priv->bdf, (u32)(rx_head + rx_swp)),
+	       &mac_regs->rx_dsc_sw_p);
+
+	return length;
+}
+
+static int pch_gbe_mdio_ready(struct pch_gbe_regs *mac_regs)
+{
+	ulong start = get_timer(0);
+
+	while (get_timer(start) < PCH_GBE_TIMEOUT) {
+		if (readl(&mac_regs->miim) & PCH_GBE_MIIM_OPER_READY)
+			return 0;
+
+		udelay(10);
+	}
+
+	return -ETIME;
+}
+
+static int pch_gbe_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
+{
+	struct pch_gbe_regs *mac_regs = bus->priv;
+	u32 miim;
+
+	if (pch_gbe_mdio_ready(mac_regs))
+		return -ETIME;
+
+	miim = (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
+	       (reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
+	       PCH_GBE_MIIM_OPER_READ;
+	writel(miim, &mac_regs->miim);
+
+	if (pch_gbe_mdio_ready(mac_regs))
+		return -ETIME;
+
+	return readl(&mac_regs->miim) & 0xffff;
+}
+
+static int pch_gbe_mdio_write(struct mii_dev *bus, int addr, int devad,
+			      int reg, u16 val)
+{
+	struct pch_gbe_regs *mac_regs = bus->priv;
+	u32 miim;
+
+	if (pch_gbe_mdio_ready(mac_regs))
+		return -ETIME;
+
+	miim = (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
+	       (reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
+	       PCH_GBE_MIIM_OPER_WRITE | val;
+	writel(miim, &mac_regs->miim);
+
+	if (pch_gbe_mdio_ready(mac_regs))
+		return -ETIME;
+	else
+		return 0;
+}
+
+static int pch_gbe_mdio_init(char *name, struct pch_gbe_regs *mac_regs)
+{
+	struct mii_dev *bus;
+
+	bus = mdio_alloc();
+	if (!bus) {
+		debug("pch_gbe: failed to allocate MDIO bus\n");
+		return -ENOMEM;
+	}
+
+	bus->read = pch_gbe_mdio_read;
+	bus->write = pch_gbe_mdio_write;
+	sprintf(bus->name, name);
+
+	bus->priv = (void *)mac_regs;
+
+	return mdio_register(bus);
+}
+
+static int pch_gbe_phy_init(struct eth_device *dev)
+{
+	struct pch_gbe_priv *priv = dev->priv;
+	struct phy_device *phydev;
+	int mask = 0xffffffff;
+
+	phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
+	if (!phydev) {
+		printf("pch_gbe: cannot find the phy\n");
+		return -1;
+	}
+
+	phy_connect_dev(phydev, dev);
+
+	phydev->supported &= PHY_GBIT_FEATURES;
+	phydev->advertising = phydev->supported;
+
+	priv->phydev = phydev;
+	phy_config(phydev);
+
+	return 1;
+}
+
+int pch_gbe_register(bd_t *bis)
+{
+	struct eth_device *dev;
+	struct pch_gbe_priv *priv;
+	pci_dev_t devno;
+	u32 iobase;
+
+	devno = pci_find_devices(supported, 0);
+	if (devno == -1)
+		return -ENODEV;
+
+	dev = (struct eth_device *)malloc(sizeof(*dev));
+	if (!dev)
+		return -ENOMEM;
+	memset(dev, 0, sizeof(*dev));
+
+	/*
+	 * The priv structure contains the descriptors and frame buffers which
+	 * need a strict buswidth alignment (64 bytes)
+	 */
+	priv = (struct pch_gbe_priv *)memalign(PCH_GBE_ALIGN_SIZE,
+					       sizeof(*priv));
+	if (!priv) {
+		free(dev);
+		return -ENOMEM;
+	}
+	memset(priv, 0, sizeof(*priv));
+
+	dev->priv = priv;
+	priv->dev = dev;
+	priv->bdf = devno;
+
+	pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
+	iobase &= PCI_BASE_ADDRESS_MEM_MASK;
+	iobase = pci_mem_to_phys(devno, iobase);
+
+	dev->iobase = iobase;
+	priv->mac_regs = (struct pch_gbe_regs *)iobase;
+
+	sprintf(dev->name, "pch_gbe.%x", iobase);
+
+	/* Read MAC address from SROM and initialize dev->enetaddr with it */
+	pch_gbe_mac_read(priv->mac_regs, dev->enetaddr);
+
+	dev->init = pch_gbe_init;
+	dev->halt = pch_gbe_halt;
+	dev->send = pch_gbe_send;
+	dev->recv = pch_gbe_recv;
+
+	eth_register(dev);
+
+	priv->interface = PHY_INTERFACE_MODE_RGMII;
+	pch_gbe_mdio_init(dev->name, priv->mac_regs);
+	priv->bus = miiphy_get_dev_by_name(dev->name);
+
+	return pch_gbe_phy_init(dev);
+}
diff --git a/drivers/net/pch_gbe.h b/drivers/net/pch_gbe.h
new file mode 100644
index 0000000..11329d4
--- /dev/null
+++ b/drivers/net/pch_gbe.h
@@ -0,0 +1,300 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Intel Platform Controller Hub EG20T (codename Topcliff) GMAC Driver
+ * Adapted from linux drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _PCH_GBE_H_
+#define _PCH_GBE_H_
+
+#define PCH_GBE_TIMEOUT		(3 * CONFIG_SYS_HZ)
+
+#define PCH_GBE_DESC_NUM	4
+#define PCH_GBE_ALIGN_SIZE	64
+
+/*
+ * Topcliff GBE MAC supports receiving ethernet frames with normal frame size
+ * (64-1518 bytes) as well as up to 10318 bytes, however it does not have a
+ * register bit to turn off receiving 'jumbo frame', so we have to allocate
+ * our own buffer to store the received frames instead of using U-Boot's own.
+ */
+#define PCH_GBE_RX_FRAME_LEN	ROUND(10318, PCH_GBE_ALIGN_SIZE)
+
+/* Interrupt Status */
+/* Interrupt Status Hold */
+/* Interrupt Enable */
+#define PCH_GBE_INT_RX_DMA_CMPLT	0x00000001
+#define PCH_GBE_INT_RX_VALID		0x00000002
+#define PCH_GBE_INT_RX_FRAME_ERR	0x00000004
+#define PCH_GBE_INT_RX_FIFO_ERR		0x00000008
+#define PCH_GBE_INT_RX_DMA_ERR		0x00000010
+#define PCH_GBE_INT_RX_DSC_EMP		0x00000020
+#define PCH_GBE_INT_TX_CMPLT		0x00000100
+#define PCH_GBE_INT_TX_DMA_CMPLT	0x00000200
+#define PCH_GBE_INT_TX_FIFO_ERR		0x00000400
+#define PCH_GBE_INT_TX_DMA_ERR		0x00000800
+#define PCH_GBE_INT_PAUSE_CMPLT		0x00001000
+#define PCH_GBE_INT_MIIM_CMPLT		0x00010000
+#define PCH_GBE_INT_PHY_INT		0x00100000
+#define PCH_GBE_INT_WOL_DET		0x01000000
+#define PCH_GBE_INT_TCPIP_ERR		0x10000000
+
+/* Mode */
+#define PCH_GBE_MODE_MII_ETHER		0x00000000
+#define PCH_GBE_MODE_GMII_ETHER		0x80000000
+#define PCH_GBE_MODE_HALF_DUPLEX	0x00000000
+#define PCH_GBE_MODE_FULL_DUPLEX	0x40000000
+#define PCH_GBE_MODE_FR_BST		0x04000000
+
+/* Reset */
+#define PCH_GBE_ALL_RST			0x80000000
+#define PCH_GBE_TX_RST			0x00008000
+#define PCH_GBE_RX_RST			0x00004000
+
+/* TCP/IP Accelerator Control */
+#define PCH_GBE_EX_LIST_EN		0x00000008
+#define PCH_GBE_RX_TCPIPACC_OFF		0x00000004
+#define PCH_GBE_TX_TCPIPACC_EN		0x00000002
+#define PCH_GBE_RX_TCPIPACC_EN		0x00000001
+
+/* MAC RX Enable */
+#define PCH_GBE_MRE_MAC_RX_EN		0x00000001
+
+/* RX Flow Control */
+#define PCH_GBE_FL_CTRL_EN		0x80000000
+
+/* RX Mode */
+#define PCH_GBE_ADD_FIL_EN		0x80000000
+#define PCH_GBE_MLT_FIL_EN		0x40000000
+#define PCH_GBE_RH_ALM_EMP_4		0x00000000
+#define PCH_GBE_RH_ALM_EMP_8		0x00004000
+#define PCH_GBE_RH_ALM_EMP_16		0x00008000
+#define PCH_GBE_RH_ALM_EMP_32		0x0000c000
+#define PCH_GBE_RH_ALM_FULL_4		0x00000000
+#define PCH_GBE_RH_ALM_FULL_8		0x00001000
+#define PCH_GBE_RH_ALM_FULL_16		0x00002000
+#define PCH_GBE_RH_ALM_FULL_32		0x00003000
+#define PCH_GBE_RH_RD_TRG_4		0x00000000
+#define PCH_GBE_RH_RD_TRG_8		0x00000200
+#define PCH_GBE_RH_RD_TRG_16		0x00000400
+#define PCH_GBE_RH_RD_TRG_32		0x00000600
+#define PCH_GBE_RH_RD_TRG_64		0x00000800
+#define PCH_GBE_RH_RD_TRG_128		0x00000a00
+#define PCH_GBE_RH_RD_TRG_256		0x00000c00
+#define PCH_GBE_RH_RD_TRG_512		0x00000e00
+
+/* TX Mode */
+#define PCH_GBE_TM_NO_RTRY		0x80000000
+#define PCH_GBE_TM_LONG_PKT		0x40000000
+#define PCH_GBE_TM_ST_AND_FD		0x20000000
+#define PCH_GBE_TM_SHORT_PKT		0x10000000
+#define PCH_GBE_TM_LTCOL_RETX		0x08000000
+#define PCH_GBE_TM_TH_TX_STRT_4		0x00000000
+#define PCH_GBE_TM_TH_TX_STRT_8		0x00004000
+#define PCH_GBE_TM_TH_TX_STRT_16	0x00008000
+#define PCH_GBE_TM_TH_TX_STRT_32	0x0000c000
+#define PCH_GBE_TM_TH_ALM_EMP_4		0x00000000
+#define PCH_GBE_TM_TH_ALM_EMP_8		0x00000800
+#define PCH_GBE_TM_TH_ALM_EMP_16	0x00001000
+#define PCH_GBE_TM_TH_ALM_EMP_32	0x00001800
+#define PCH_GBE_TM_TH_ALM_EMP_64	0x00002000
+#define PCH_GBE_TM_TH_ALM_EMP_128	0x00002800
+#define PCH_GBE_TM_TH_ALM_EMP_256	0x00003000
+#define PCH_GBE_TM_TH_ALM_EMP_512	0x00003800
+#define PCH_GBE_TM_TH_ALM_FULL_4	0x00000000
+#define PCH_GBE_TM_TH_ALM_FULL_8	0x00000200
+#define PCH_GBE_TM_TH_ALM_FULL_16	0x00000400
+#define PCH_GBE_TM_TH_ALM_FULL_32	0x00000600
+
+/* MAC Address Mask */
+#define PCH_GBE_BUSY			0x80000000
+
+/* MIIM  */
+#define PCH_GBE_MIIM_OPER_WRITE		0x04000000
+#define PCH_GBE_MIIM_OPER_READ		0x00000000
+#define PCH_GBE_MIIM_OPER_READY		0x04000000
+#define PCH_GBE_MIIM_PHY_ADDR_SHIFT	21
+#define PCH_GBE_MIIM_REG_ADDR_SHIFT	16
+
+/* RGMII Control */
+#define PCH_GBE_CRS_SEL			0x00000010
+#define PCH_GBE_RGMII_RATE_125M		0x00000000
+#define PCH_GBE_RGMII_RATE_25M		0x00000008
+#define PCH_GBE_RGMII_RATE_2_5M		0x0000000c
+#define PCH_GBE_RGMII_MODE_GMII		0x00000000
+#define PCH_GBE_RGMII_MODE_RGMII	0x00000002
+#define PCH_GBE_CHIP_TYPE_EXTERNAL	0x00000000
+#define PCH_GBE_CHIP_TYPE_INTERNAL	0x00000001
+
+/* DMA Control */
+#define PCH_GBE_RX_DMA_EN		0x00000002
+#define PCH_GBE_TX_DMA_EN		0x00000001
+
+/* Receive Descriptor bit definitions */
+#define PCH_GBE_RXD_ACC_STAT_BCAST	0x00000400
+#define PCH_GBE_RXD_ACC_STAT_MCAST	0x00000200
+#define PCH_GBE_RXD_ACC_STAT_UCAST	0x00000100
+#define PCH_GBE_RXD_ACC_STAT_TCPIPOK	0x000000c0
+#define PCH_GBE_RXD_ACC_STAT_IPOK	0x00000080
+#define PCH_GBE_RXD_ACC_STAT_TCPOK	0x00000040
+#define PCH_GBE_RXD_ACC_STAT_IP6ERR	0x00000020
+#define PCH_GBE_RXD_ACC_STAT_OFLIST	0x00000010
+#define PCH_GBE_RXD_ACC_STAT_TYPEIP	0x00000008
+#define PCH_GBE_RXD_ACC_STAT_MACL	0x00000004
+#define PCH_GBE_RXD_ACC_STAT_PPPOE	0x00000002
+#define PCH_GBE_RXD_ACC_STAT_VTAGT	0x00000001
+#define PCH_GBE_RXD_GMAC_STAT_PAUSE	0x0200
+#define PCH_GBE_RXD_GMAC_STAT_MARBR	0x0100
+#define PCH_GBE_RXD_GMAC_STAT_MARMLT	0x0080
+#define PCH_GBE_RXD_GMAC_STAT_MARIND	0x0040
+#define PCH_GBE_RXD_GMAC_STAT_MARNOTMT	0x0020
+#define PCH_GBE_RXD_GMAC_STAT_TLONG	0x0010
+#define PCH_GBE_RXD_GMAC_STAT_TSHRT	0x0008
+#define PCH_GBE_RXD_GMAC_STAT_NOTOCTAL	0x0004
+#define PCH_GBE_RXD_GMAC_STAT_NBLERR	0x0002
+#define PCH_GBE_RXD_GMAC_STAT_CRCERR	0x0001
+
+/* Transmit Descriptor bit definitions */
+#define PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF	0x0008
+#define PCH_GBE_TXD_CTRL_ITAG		0x0004
+#define PCH_GBE_TXD_CTRL_ICRC		0x0002
+#define PCH_GBE_TXD_CTRL_APAD		0x0001
+#define PCH_GBE_TXD_WORDS_SHIFT		2
+#define PCH_GBE_TXD_GMAC_STAT_CMPLT	0x2000
+#define PCH_GBE_TXD_GMAC_STAT_ABT	0x1000
+#define PCH_GBE_TXD_GMAC_STAT_EXCOL	0x0800
+#define PCH_GBE_TXD_GMAC_STAT_SNGCOL	0x0400
+#define PCH_GBE_TXD_GMAC_STAT_MLTCOL	0x0200
+#define PCH_GBE_TXD_GMAC_STAT_CRSER	0x0100
+#define PCH_GBE_TXD_GMAC_STAT_TLNG	0x0080
+#define PCH_GBE_TXD_GMAC_STAT_TSHRT	0x0040
+#define PCH_GBE_TXD_GMAC_STAT_LTCOL	0x0020
+#define PCH_GBE_TXD_GMAC_STAT_TFUNDFLW	0x0010
+
+/**
+ * struct pch_gbe_rx_desc - Receive Descriptor
+ * @buffer_addr:	RX Frame Buffer Address
+ * @tcp_ip_status:	TCP/IP Accelerator Status
+ * @rx_words_eob:	RX word count and Byte position
+ * @gbec_status:	GMAC Status
+ * @dma_status:		DMA Status
+ * @reserved1:		Reserved
+ * @reserved2:		Reserved
+ */
+struct pch_gbe_rx_desc {
+	u32 buffer_addr;
+	u32 tcp_ip_status;
+	u16 rx_words_eob;
+	u16 gbec_status;
+	u8 dma_status;
+	u8 reserved1;
+	u16 reserved2;
+};
+
+/**
+ * struct pch_gbe_tx_desc - Transmit Descriptor
+ * @buffer_addr:	TX Frame Buffer Address
+ * @length:		Data buffer length
+ * @reserved1:		Reserved
+ * @tx_words_eob:	TX word count and Byte position
+ * @tx_frame_ctrl:	TX Frame Control
+ * @dma_status:		DMA Status
+ * @reserved2:		Reserved
+ * @gbec_status:	GMAC Status
+ */
+struct pch_gbe_tx_desc {
+	u32 buffer_addr;
+	u16 length;
+	u16 reserved1;
+	u16 tx_words_eob;
+	u16 tx_frame_ctrl;
+	u8 dma_status;
+	u8 reserved2;
+	u16 gbec_status;
+};
+
+/**
+ * pch_gbe_regs_mac_adr - structure holding values of mac address registers
+ *
+ * @high	Denotes the 1st to 4th byte from the initial of MAC address
+ * @low		Denotes the 5th to 6th byte from the initial of MAC address
+ */
+struct pch_gbe_regs_mac_adr {
+	u32 high;
+	u32 low;
+};
+
+/**
+ * pch_gbe_regs - structure holding values of MAC registers
+ */
+struct pch_gbe_regs {
+	u32 int_st;
+	u32 int_en;
+	u32 mode;
+	u32 reset;
+	u32 tcpip_acc;
+	u32 ex_list;
+	u32 int_st_hold;
+	u32 phy_int_ctrl;
+	u32 mac_rx_en;
+	u32 rx_fctrl;
+	u32 pause_req;
+	u32 rx_mode;
+	u32 tx_mode;
+	u32 rx_fifo_st;
+	u32 tx_fifo_st;
+	u32 tx_fid;
+	u32 tx_result;
+	u32 pause_pkt1;
+	u32 pause_pkt2;
+	u32 pause_pkt3;
+	u32 pause_pkt4;
+	u32 pause_pkt5;
+	u32 reserve[2];
+	struct pch_gbe_regs_mac_adr mac_adr[16];
+	u32 addr_mask;
+	u32 miim;
+	u32 mac_addr_load;
+	u32 rgmii_st;
+	u32 rgmii_ctrl;
+	u32 reserve3[3];
+	u32 dma_ctrl;
+	u32 reserve4[3];
+	u32 rx_dsc_base;
+	u32 rx_dsc_size;
+	u32 rx_dsc_hw_p;
+	u32 rx_dsc_hw_p_hld;
+	u32 rx_dsc_sw_p;
+	u32 reserve5[3];
+	u32 tx_dsc_base;
+	u32 tx_dsc_size;
+	u32 tx_dsc_hw_p;
+	u32 tx_dsc_hw_p_hld;
+	u32 tx_dsc_sw_p;
+	u32 reserve6[3];
+	u32 rx_dma_st;
+	u32 tx_dma_st;
+	u32 reserve7[2];
+	u32 wol_st;
+	u32 wol_ctrl;
+	u32 wol_addr_mask;
+};
+
+struct pch_gbe_priv {
+	struct pch_gbe_rx_desc rx_desc[PCH_GBE_DESC_NUM];
+	struct pch_gbe_tx_desc tx_desc[PCH_GBE_DESC_NUM];
+	char rx_buff[PCH_GBE_DESC_NUM][PCH_GBE_RX_FRAME_LEN];
+	struct eth_device *dev;
+	struct phy_device *phydev;
+	struct mii_dev *bus;
+	struct pch_gbe_regs *mac_regs;
+	pci_dev_t bdf;
+	u32 interface;
+	int rx_idx;
+	int tx_idx;
+};
+
+#endif /* _PCH_GBE_H_ */
diff --git a/drivers/power/axp209.c b/drivers/power/axp209.c
index 4565398..f8c9b77 100644
--- a/drivers/power/axp209.c
+++ b/drivers/power/axp209.c
@@ -119,7 +119,7 @@
 	if (mvolt == -1)
 		cfg = 0x80;	/* determined by LDO3IN pin */
 	else
-		cfg = axp209_mvolt_to_cfg(mvolt, 700, 2275, 25);
+		cfg = axp209_mvolt_to_cfg(mvolt, 700, 3500, 25);
 
 	return axp209_write(AXP209_LDO3_VOLTAGE, cfg);
 }
diff --git a/drivers/rtc/mc146818.c b/drivers/rtc/mc146818.c
index c9d318c..44857a6 100644
--- a/drivers/rtc/mc146818.c
+++ b/drivers/rtc/mc146818.c
@@ -14,7 +14,6 @@
 #include <common.h>
 #include <command.h>
 #include <rtc.h>
-#include <version.h>
 
 #if defined(__I386__) || defined(CONFIG_MALTA)
 #include <asm/io.h>
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index 3fc7104..2de3737 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -16,8 +16,6 @@
 #include <dm/lists.h>
 #include <dm/device-internal.h>
 
-#include <ns16550.h>
-
 DECLARE_GLOBAL_DATA_PTR;
 
 /*
diff --git a/drivers/spi/cf_qspi.c b/drivers/spi/cf_qspi.c
index 6b85633..834c5bd 100644
--- a/drivers/spi/cf_qspi.c
+++ b/drivers/spi/cf_qspi.c
@@ -20,7 +20,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #define clamp(x, low, high) (min(max(low, x), high))
-#define to_cf_qspi_slave(s) container_of(s, struct cf_qspi_slave, s)
+#define to_cf_qspi_slave(s) container_of(s, struct cf_qspi_slave, slave)
 
 struct cf_qspi_slave {
 	struct spi_slave slave;	/* Specific bus:cs ID for each device */
diff --git a/drivers/spi/cf_spi.c b/drivers/spi/cf_spi.c
index 879a809..6ce1101 100644
--- a/drivers/spi/cf_spi.c
+++ b/drivers/spi/cf_spi.c
@@ -20,13 +20,6 @@
 	int charbit;
 };
 
-int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout,
-	       void *din, ulong flags);
-struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, uint mode);
-void cfspi_init(void);
-void cfspi_tx(u32 ctrl, u16 data);
-u16 cfspi_rx(void);
-
 extern void cfspi_port_conf(void);
 extern int cfspi_claim_bus(uint bus, uint cs);
 extern void cfspi_release_bus(uint bus, uint cs);
@@ -46,7 +39,12 @@
 #define SPI_MODE_MOD	0x00200000
 #define SPI_DBLRATE	0x00100000
 
-void cfspi_init(void)
+static inline struct cf_spi_slave *to_cf_spi_slave(struct spi_slave *slave)
+{
+	return container_of(slave, struct cf_spi_slave, slave);
+}
+
+static void cfspi_init(void)
 {
 	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
 
@@ -84,7 +82,7 @@
 #endif
 }
 
-void cfspi_tx(u32 ctrl, u16 data)
+static void cfspi_tx(u32 ctrl, u16 data)
 {
 	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
 
@@ -93,7 +91,7 @@
 	dspi->tfr = (ctrl | data);
 }
 
-u16 cfspi_rx(void)
+static u16 cfspi_rx(void)
 {
 	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
 
@@ -102,10 +100,10 @@
 	return (dspi->rfr & 0xFFFF);
 }
 
-int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout,
-	       void *din, ulong flags)
+static int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout,
+		      void *din, ulong flags)
 {
-	struct cf_spi_slave *cfslave = (struct cf_spi_slave *)slave;
+	struct cf_spi_slave *cfslave = to_cf_spi_slave(slave);
 	u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
 	u8 *spi_rd = NULL, *spi_wr = NULL;
 	static u32 ctrl = 0;
@@ -176,7 +174,8 @@
 	return 0;
 }
 
-struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, uint mode)
+static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave,
+					   uint mode)
 {
 	/*
 	 * bit definition for mode:
@@ -326,7 +325,9 @@
 
 void spi_free_slave(struct spi_slave *slave)
 {
-	free(slave);
+	struct cf_spi_slave *cfslave = to_cf_spi_slave(slave);
+
+	free(cfslave);
 }
 
 int spi_claim_bus(struct spi_slave *slave)
diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c
index 0ec5b9d..bf18362 100644
--- a/drivers/spi/davinci_spi.c
+++ b/drivers/spi/davinci_spi.c
@@ -32,9 +32,6 @@
 	if (!ds)
 		return NULL;
 
-	ds->slave.bus = bus;
-	ds->slave.cs = cs;
-
 	switch (bus) {
 	case SPI0_BUS:
 		ds->regs = (struct davinci_spi_regs *)SPI0_BASE;
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 2624844..8f5c0fc 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -164,13 +164,13 @@
 	if (!priv->fifo_len) {
 		u32 fifo;
 
-		for (fifo = 2; fifo <= 256; fifo++) {
+		for (fifo = 1; fifo < 256; fifo++) {
 			dw_writew(priv, DW_SPI_TXFLTR, fifo);
 			if (fifo != dw_readw(priv, DW_SPI_TXFLTR))
 				break;
 		}
 
-		priv->fifo_len = (fifo == 2) ? 0 : fifo - 1;
+		priv->fifo_len = (fifo == 1) ? 0 : fifo;
 		dw_writew(priv, DW_SPI_TXFLTR, 0);
 	}
 	debug("%s: fifo_len=%d\n", __func__, priv->fifo_len);
diff --git a/drivers/spi/ftssp010_spi.c b/drivers/spi/ftssp010_spi.c
index 267e4d8..c7d6480 100644
--- a/drivers/spi/ftssp010_spi.c
+++ b/drivers/spi/ftssp010_spi.c
@@ -431,7 +431,9 @@
 
 void spi_free_slave(struct spi_slave *slave)
 {
-	free(slave);
+	struct ftssp010_spi *chip = to_ftssp010_spi(slave);
+
+	free(chip);
 }
 
 int spi_claim_bus(struct spi_slave *slave)
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index 857b604..3356c0f 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -109,10 +109,17 @@
 	slave->op_mode_rx = 8;
 #endif
 
+#ifdef CONFIG_QSPI_QUAD_SUPPORT
+	memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
+			QSPI_SETUP0_NUM_D_BYTES_8_BITS |
+			QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
+			QSPI_NUM_DUMMY_BITS);
+#else
 	memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
 			QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
 			QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
 			QSPI_NUM_DUMMY_BITS;
+#endif
 
 	writel(memval, &qslave->base->setup0);
 }
diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c
index ba442d5..8f03a6b 100644
--- a/drivers/usb/gadget/ether.c
+++ b/drivers/usb/gadget/ether.c
@@ -68,7 +68,6 @@
 #define ETH_ZLEN	60		/* Min. octets in frame sans FCS */
 #define ETH_DATA_LEN	1500		/* Max. octets in payload	 */
 #define ETH_FRAME_LEN	PKTSIZE_ALIGN	/* Max. octets in frame sans FCS */
-#define ETH_FCS_LEN	4		/* Octets in the FCS		 */
 
 #define DRIVER_DESC		"Ethernet Gadget"
 /* Based on linux 2.6.27 version */
diff --git a/drivers/usb/gadget/rndis.c b/drivers/usb/gadget/rndis.c
index 404a7b9..62c9b2e 100644
--- a/drivers/usb/gadget/rndis.c
+++ b/drivers/usb/gadget/rndis.c
@@ -43,7 +43,6 @@
 #define ETH_ZLEN	60		/* Min. octets in frame sans FCS */
 #define ETH_DATA_LEN	1500		/* Max. octets in payload	 */
 #define ETH_FRAME_LEN	PKTSIZE_ALIGN	/* Max. octets in frame sans FCS */
-#define ETH_FCS_LEN	4		/* Octets in the FCS		 */
 #define ENOTSUPP        524     /* Operation is not supported */
 
 
diff --git a/drivers/usb/musb-new/musb_uboot.c b/drivers/usb/musb-new/musb_uboot.c
index 6e58ddf..51fb3fd 100644
--- a/drivers/usb/musb-new/musb_uboot.c
+++ b/drivers/usb/musb-new/musb_uboot.c
@@ -1,5 +1,8 @@
 #include <common.h>
 #include <watchdog.h>
+#ifdef CONFIG_ARCH_SUNXI
+#include <asm/arch/usbc.h>
+#endif
 #include <asm/errno.h>
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
@@ -186,8 +189,19 @@
 	power &= 0xf0;
 	musb_writeb(mbase, MUSB_POWER, MUSB_POWER_RESET | power);
 	mdelay(50);
+#ifdef CONFIG_ARCH_SUNXI
+	/*
+	 * sunxi phy has a bug and it will wrongly detect high speed squelch
+	 * when clearing reset on low-speed devices, temporary disable
+	 * squelch detection to work around this.
+	 */
+	sunxi_usbc_enable_squelch_detect(0, 0);
+#endif
 	power = musb_readb(mbase, MUSB_POWER);
 	musb_writeb(mbase, MUSB_POWER, ~MUSB_POWER_RESET & power);
+#ifdef CONFIG_ARCH_SUNXI
+	sunxi_usbc_enable_squelch_detect(0, 1);
+#endif
 	host->isr(0, host);
 	host_speed = (musb_readb(mbase, MUSB_POWER) & MUSB_POWER_HSMODE) ?
 			USB_SPEED_HIGH :
diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c
index 4d8c15a..90aaec6 100644
--- a/drivers/usb/musb-new/sunxi.c
+++ b/drivers/usb/musb-new/sunxi.c
@@ -261,7 +261,7 @@
 			}
 
 			err = gpio_get_value(vbus_det);
-			if (err) {
+			if (err < 0) {
 				gpio_free(vbus_det);
 				return -EIO;
 			}
diff --git a/drivers/video/mpc8xx_lcd.c b/drivers/video/mpc8xx_lcd.c
index faa58c0..b08576e 100644
--- a/drivers/video/mpc8xx_lcd.c
+++ b/drivers/video/mpc8xx_lcd.c
@@ -15,7 +15,6 @@
 #include <common.h>
 #include <command.h>
 #include <watchdog.h>
-#include <version.h>
 #include <stdarg.h>
 #include <lcdvideo.h>
 #include <linux/types.h>
diff --git a/drivers/video/pxa_lcd.c b/drivers/video/pxa_lcd.c
index 04105d4..64cef37 100644
--- a/drivers/video/pxa_lcd.c
+++ b/drivers/video/pxa_lcd.c
@@ -13,7 +13,6 @@
 
 #include <config.h>
 #include <common.h>
-#include <version.h>
 #include <stdarg.h>
 #include <linux/types.h>
 #include <stdio_dev.h>
diff --git a/include/config_cmd_default.h b/include/config_cmd_default.h
index 73c9544..e79a13b 100644
--- a/include/config_cmd_default.h
+++ b/include/config_cmd_default.h
@@ -21,6 +21,7 @@
 #define CONFIG_CMD_CONSOLE	/* coninfo			*/
 #define CONFIG_CMD_ECHO		/* echo arguments		*/
 #define CONFIG_CMD_EDITENV	/* editenv			*/
+#define CONFIG_CMD_ENV_EXISTS	/* query whether env variables exists */
 #define CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
 #define CONFIG_CMD_IMI		/* iminfo			*/
 #define CONFIG_CMD_ITEST	/* Integer (and string) test	*/
diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h
index 73f093f..d71e58d 100644
--- a/include/config_distro_bootcmd.h
+++ b/include/config_distro_bootcmd.h
@@ -213,7 +213,8 @@
 		"done\0"                                                  \
 	\
 	"scan_dev_for_boot_part="                                         \
-		"part list ${devtype} ${devnum} devplist; "               \
+		"part list ${devtype} ${devnum} -bootable devplist; "     \
+		"env exists devplist || setenv devplist 1; "              \
 		"for bootpart in ${devplist}; do "                        \
 			"if fstype ${devtype} ${devnum}:${bootpart} "     \
 					"bootfstype; then "               \
diff --git a/include/config_distro_defaults.h b/include/config_distro_defaults.h
index 1ecc0bb..8237239 100644
--- a/include/config_distro_defaults.h
+++ b/include/config_distro_defaults.h
@@ -20,10 +20,12 @@
 #define CONFIG_BOOTP_PXE
 #define CONFIG_BOOTP_SUBNETMASK
 
-#if defined(__arm__)
+#if defined(__arm__) || defined(__aarch64__)
 #define CONFIG_BOOTP_PXE_CLIENTARCH     0x100
 #if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__)
 #define CONFIG_BOOTP_VCI_STRING         "U-boot.armv7"
+#elif defined(__aarch64__)
+#define CONFIG_BOOTP_VCI_STRING         "U-boot.armv8"
 #else
 #define CONFIG_BOOTP_VCI_STRING         "U-boot.arm"
 #endif
@@ -31,7 +33,11 @@
 
 #define CONFIG_OF_LIBFDT
 
+#ifdef CONFIG_ARM64
+#define CONFIG_CMD_BOOTI
+#else
 #define CONFIG_CMD_BOOTZ
+#endif
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_EXT2
diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h
index 6630377..9390464 100644
--- a/include/configs/M5208EVBE.h
+++ b/include/configs/M5208EVBE.h
@@ -14,9 +14,6 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_MCF520x		/* define processor family */
-#define CONFIG_M5208		/* define processor type */
-
 #define CONFIG_MCFUART
 #define CONFIG_SYS_UART_PORT		(0)
 #define CONFIG_BAUDRATE			115200
diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h
index cde7305..e9424b4 100644
--- a/include/configs/M52277EVB.h
+++ b/include/configs/M52277EVB.h
@@ -18,8 +18,6 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_MCF5227x		/* define processor family */
-#define CONFIG_M52277		/* define processor type */
 #define CONFIG_M52277EVB	/* M52277EVB board */
 
 #define CONFIG_MCFUART
diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h
index 0f6e2f7..883347b 100644
--- a/include/configs/M5235EVB.h
+++ b/include/configs/M5235EVB.h
@@ -18,8 +18,6 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_MCF523x		/* define processor family */
-#define CONFIG_M5235		/* define processor type */
 
 #define CONFIG_MCFUART
 #define CONFIG_SYS_UART_PORT		(0)
diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h
index ae4fe45..60e5b45 100644
--- a/include/configs/M5249EVB.h
+++ b/include/configs/M5249EVB.h
@@ -18,9 +18,6 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_MCF52x2			/* define processor family */
-#define CONFIG_M5249			/* define processor type */
-
 #define CONFIG_MCFTMR
 
 #define CONFIG_MCFUART
diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h
index 3a1cbca..7421b57 100644
--- a/include/configs/M5253DEMO.h
+++ b/include/configs/M5253DEMO.h
@@ -7,8 +7,6 @@
 #ifndef _M5253DEMO_H
 #define _M5253DEMO_H
 
-#define CONFIG_MCF52x2		/* define processor family */
-#define CONFIG_M5253		/* define processor type */
 #define CONFIG_M5253DEMO	/* define board type */
 
 #define CONFIG_MCFTMR
diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h
index fabfdb9..8fd3907 100644
--- a/include/configs/M5253EVBE.h
+++ b/include/configs/M5253EVBE.h
@@ -8,8 +8,6 @@
 #ifndef _M5253EVBE_H
 #define _M5253EVBE_H
 
-#define CONFIG_MCF52x2		/* define processor family */
-#define CONFIG_M5253		/* define processor type */
 #define CONFIG_M5253EVBE	/* define board type */
 
 #define CONFIG_MCFTMR
diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h
index 4c84126..2c056b1 100644
--- a/include/configs/M5272C3.h
+++ b/include/configs/M5272C3.h
@@ -17,9 +17,6 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_MCF52x2		/* define processor family */
-#define CONFIG_M5272		/* define processor type */
-
 #define CONFIG_MCFTMR
 
 #define CONFIG_MCFUART
diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h
index 4dddab7..7eb3172 100644
--- a/include/configs/M5275EVB.h
+++ b/include/configs/M5275EVB.h
@@ -21,8 +21,6 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_MCF52x2			/* define processor family */
-#define CONFIG_M5275			/* define processor type */
 #define CONFIG_M5275EVB			/* define board type */
 
 #define CONFIG_MCFTMR
diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h
index fd970d0..569ad42 100644
--- a/include/configs/M5282EVB.h
+++ b/include/configs/M5282EVB.h
@@ -17,9 +17,6 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define	CONFIG_MCF52x2		/* define processor family */
-#define CONFIG_M5282		/* define processor type */
-
 #define CONFIG_MCFTMR
 
 #define CONFIG_MCFUART
diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h
index a100d9f..e3fa856 100644
--- a/include/configs/M53017EVB.h
+++ b/include/configs/M53017EVB.h
@@ -18,8 +18,6 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_MCF5301x		/* define processor family */
-#define CONFIG_M53015		/* define processor type */
 
 #define CONFIG_MCFUART
 #define CONFIG_SYS_UART_PORT		(0)
@@ -202,7 +200,7 @@
 /* Configuration for environment
  * Environment is embedded in u-boot in the second sector of the flash
  */
-#define CONFIG_ENV_OFFSET		0x8000
+#define CONFIG_ENV_OFFSET		(CONFIG_SYS_FLASH_BASE + 0x40000)
 #define CONFIG_ENV_SIZE			0x1000
 #define CONFIG_ENV_SECT_SIZE		0x8000
 #define CONFIG_ENV_IS_IN_FLASH		1
diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
index 78ea384..795f359 100644
--- a/include/configs/M5329EVB.h
+++ b/include/configs/M5329EVB.h
@@ -18,8 +18,6 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_MCF532x		/* define processor family */
-#define CONFIG_M5329		/* define processor type */
 
 #define CONFIG_MCFUART
 #define CONFIG_SYS_UART_PORT		(0)
diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h
index 849c265..d75b43c 100644
--- a/include/configs/M5373EVB.h
+++ b/include/configs/M5373EVB.h
@@ -18,8 +18,6 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_MCF532x		/* define processor family */
-#define CONFIG_M5373		/* define processor type */
 
 #define CONFIG_MCFUART
 #define CONFIG_SYS_UART_PORT		(0)
diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h
index 3d7dc1f..be1750f 100644
--- a/include/configs/M54418TWR.h
+++ b/include/configs/M54418TWR.h
@@ -18,8 +18,6 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_MCF5441x	/* define processor family */
-#define CONFIG_M54418		/* define processor type */
 #define CONFIG_M54418TWR	/* M54418TWR board */
 
 #define CONFIG_MCFUART
diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h
index 734a77f..1b3598a 100644
--- a/include/configs/M54451EVB.h
+++ b/include/configs/M54451EVB.h
@@ -18,8 +18,6 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_MCF5445x		/* define processor family */
-#define CONFIG_M54451		/* define processor type */
 #define CONFIG_M54451EVB	/* M54451EVB board */
 
 #define CONFIG_DISPLAY_BOARDINFO
diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h
index 2faf581..2288bff 100644
--- a/include/configs/M54455EVB.h
+++ b/include/configs/M54455EVB.h
@@ -18,8 +18,6 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_MCF5445x		/* define processor family */
-#define CONFIG_M54455		/* define processor type */
 #define CONFIG_M54455EVB	/* M54455EVB board */
 
 #define CONFIG_DISPLAY_BOARDINFO
diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h
index 2f4549f..91d6a1a 100644
--- a/include/configs/M5475EVB.h
+++ b/include/configs/M5475EVB.h
@@ -18,9 +18,6 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_MCF547x_8x	/* define processor family */
-#define CONFIG_M547x		/* define processor type */
-#define CONFIG_M5475		/* define processor type */
 
 #define CONFIG_DISPLAY_BOARDINFO
 
diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h
index 9aa02f7..ce9f3b0 100644
--- a/include/configs/M5485EVB.h
+++ b/include/configs/M5485EVB.h
@@ -18,9 +18,6 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_MCF547x_8x	/* define processor family */
-#define CONFIG_M548x		/* define processor type */
-#define CONFIG_M5485		/* define processor type */
 
 #define CONFIG_DISPLAY_BOARDINFO
 
diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h
index 73e1b0a..d5b6e37 100644
--- a/include/configs/amcc-common.h
+++ b/include/configs/amcc-common.h
@@ -10,6 +10,8 @@
 #ifndef __AMCC_COMMON_H
 #define __AMCC_COMMON_H
 
+#define CONFIG_SYS_GENERIC_BOARD
+
 #define CONFIG_SYS_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* Start of U-Boot	*/
 #define CONFIG_SYS_MONITOR_LEN		(0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE + 1)
diff --git a/include/configs/amcore.h b/include/configs/amcore.h
index 2a785b3..229fa5a 100644
--- a/include/configs/amcore.h
+++ b/include/configs/amcore.h
@@ -12,11 +12,6 @@
 #define CONFIG_AMCORE
 #define CONFIG_HOSTNAME			AMCORE
 
-#define CONFIG_SYS_GENERIC_BOARD
-
-#define CONFIG_MCF530x
-#define CONFIG_M5307
-
 #define CONFIG_MCFTMR
 #define CONFIG_MCFUART
 #define CONFIG_SYS_UART_PORT		0
diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h
index fa64a68..de837cf 100644
--- a/include/configs/astro_mcf5373l.h
+++ b/include/configs/astro_mcf5373l.h
@@ -39,16 +39,6 @@
 #error No card type defined!
 #endif
 
-/*
- * Define processor
- * possible values for Urmel board: only Coldfire M5373 processor supported
- * (please do not change)
- */
-
-/* it seems not clear yet which processor defines we should use */
-#define CONFIG_MCF537x			/* define processor family */
-#define CONFIG_MCF532x			/* define processor family */
-#define CONFIG_M5373			/* define processor type */
 #define CONFIG_ASTRO5373L		/* define board type */
 
 /* Command line configuration */
diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h
index 7a1499d..ed790cc 100644
--- a/include/configs/canyonlands.h
+++ b/include/configs/canyonlands.h
@@ -13,8 +13,6 @@
 
 #include <linux/kconfig.h>
 
-#define CONFIG_SYS_GENERIC_BOARD
-
 /*-----------------------------------------------------------------------
  * High Level Configuration Options
  *----------------------------------------------------------------------*/
diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h
index 4644369..b9f0b0b 100644
--- a/include/configs/cobra5272.h
+++ b/include/configs/cobra5272.h
@@ -25,16 +25,6 @@
 #define _CONFIG_COBRA5272_H
 
 /* ---
- * Define processor
- * possible values for Sentec board: only Coldfire M5272 processor supported
- * (please do not change)
- * ---
- */
-
-#define CONFIG_MCF52x2			/* define processor family */
-#define CONFIG_M5272			/* define processor type */
-
-/* ---
  * Defines processor clock - important for correct timings concerning serial
  * interface etc.
  * ---
diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h
index b927b1c..df32f2a 100644
--- a/include/configs/crownbay.h
+++ b/include/configs/crownbay.h
@@ -52,8 +52,20 @@
 #define CONFIG_MMC_SDMA
 #define CONFIG_CMD_MMC
 
+/* Topcliff Gigabit Ethernet */
+#define CONFIG_PCH_GBE
+#define CONFIG_PHYLIB
+
 /* Video is not supported */
 #undef CONFIG_VIDEO
 #undef CONFIG_CFB_CONSOLE
 
+/* Environment configuration */
+#undef CONFIG_ENV_IS_NOWHERE
+#undef CONFIG_ENV_SIZE
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE			0x1000
+#define CONFIG_ENV_SECT_SIZE		0x1000
+#define CONFIG_ENV_OFFSET		0
+
 #endif	/* __CONFIG_H */
diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h
index 8a7447d..56317ef 100644
--- a/include/configs/dbau1x00.h
+++ b/include/configs/dbau1x00.h
@@ -15,7 +15,6 @@
 #define CONFIG_DBAU1X00		1
 #define CONFIG_SOC_AU1X00	1  /* alchemy series cpu */
 
-#define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_DISPLAY_BOARDINFO
 
 #ifdef CONFIG_DBAU1000
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index dee2b11..8fe0e6c 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -77,6 +77,7 @@
 #define CONFIG_TI_SPI_MMAP
 #define CONFIG_SF_DEFAULT_SPEED                48000000
 #define CONFIG_DEFAULT_SPI_MODE                SPI_MODE_3
+#define CONFIG_QSPI_QUAD_SUPPORT
 
 /*
  * Default to using SPI for environment, etc.
diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h
index bdca705..e2b9326 100644
--- a/include/configs/eb_cpu5282.h
+++ b/include/configs/eb_cpu5282.h
@@ -15,9 +15,6 @@
  * High Level Configuration Options (easy to change)                    *
  *----------------------------------------------------------------------*/
 
-#define	CONFIG_MCF52x2			/* define processor family */
-#define CONFIG_M5282			/* define processor type */
-
 #define CONFIG_MISC_INIT_R
 
 #define CONFIG_MCFUART
diff --git a/include/configs/galileo.h b/include/configs/galileo.h
index d745f4e..288acf3 100644
--- a/include/configs/galileo.h
+++ b/include/configs/galileo.h
@@ -57,4 +57,17 @@
 #define CONFIG_MMC_SDMA
 #define CONFIG_CMD_MMC
 
+/* 10/100M Ethernet support */
+#define CONFIG_DESIGNWARE_ETH
+#define CONFIG_DW_ALTDESCRIPTOR
+#define CONFIG_PHYLIB
+
+/* Environment configuration */
+#undef CONFIG_ENV_IS_NOWHERE
+#undef CONFIG_ENV_SIZE
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE			0x1000
+#define CONFIG_ENV_SECT_SIZE		0x1000
+#define CONFIG_ENV_OFFSET		0
+
 #endif	/* __CONFIG_H */
diff --git a/include/configs/malta.h b/include/configs/malta.h
index 354672e..9445c9b 100644
--- a/include/configs/malta.h
+++ b/include/configs/malta.h
@@ -14,7 +14,6 @@
  * System configuration
  */
 #define CONFIG_MALTA
-#define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_DISPLAY_BOARDINFO
 
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
index 7378acd..e97c5e3 100644
--- a/include/configs/omap4_panda.h
+++ b/include/configs/omap4_panda.h
@@ -43,8 +43,13 @@
 #define CONFIG_CMD_GPIO
 
 /* ENV related config options */
-#define CONFIG_ENV_IS_NOWHERE
 
 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#define CONFIG_ENV_IS_IN_FAT
+#define FAT_ENV_INTERFACE               "mmc"
+#define FAT_ENV_DEVICE_AND_PART         "0:1"
+#define FAT_ENV_FILE                    "uboot.env"
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_ENV_OVERWRITE
 
 #endif /* __CONFIG_PANDA_H */
diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h
index 61e6af3..a1926bb 100644
--- a/include/configs/pb1x00.h
+++ b/include/configs/pb1x00.h
@@ -15,7 +15,6 @@
 #define CONFIG_PB1X00		1
 #define CONFIG_SOC_AU1X00	1  /* alchemy series cpu */
 
-#define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_DISPLAY_BOARDINFO
 
 #ifdef CONFIG_PB1000
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index 1548d3e..75da8a1 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -14,7 +14,6 @@
 
 #define CONFIG_QEMU_MIPS
 
-#define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_DISPLAY_BOARDINFO
 #define CONFIG_MISC_INIT_R
 
diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h
index 61cafad..b07ca4e 100644
--- a/include/configs/qemu-mips64.h
+++ b/include/configs/qemu-mips64.h
@@ -14,7 +14,6 @@
 
 #define CONFIG_QEMU_MIPS
 
-#define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_DISPLAY_BOARDINFO
 #define CONFIG_MISC_INIT_R
 
diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h
index e9ef7cc..c33f1cb 100644
--- a/include/configs/rcar-gen2-common.h
+++ b/include/configs/rcar-gen2-common.h
@@ -35,8 +35,6 @@
 #define CONFIG_SYS_THUMB_BUILD
 #define CONFIG_SYS_GENERIC_BOARD
 
-#define CONFIG_SYS_MALLOC_F_LEN	(1 << 10)
-
 /* Support File sytems */
 #define CONFIG_FAT_WRITE
 #define CONFIG_DOS_PARTITION
diff --git a/include/configs/sun4i.h b/include/configs/sun4i.h
index 1537e53..7cd5c69 100644
--- a/include/configs/sun4i.h
+++ b/include/configs/sun4i.h
@@ -11,7 +11,6 @@
 /*
  * A10 specific configuration
  */
-#define CONFIG_CLK_FULL_SPEED		1008000000
 
 #ifdef CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_SUNXI
diff --git a/include/configs/sun5i.h b/include/configs/sun5i.h
index e755531..e0470d4 100644
--- a/include/configs/sun5i.h
+++ b/include/configs/sun5i.h
@@ -11,7 +11,6 @@
 /*
  * High Level Configuration Options
  */
-#define CONFIG_CLK_FULL_SPEED		1008000000
 
 #ifdef CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_SUNXI
diff --git a/include/configs/sun6i.h b/include/configs/sun6i.h
index f5e11dd..617c1cd 100644
--- a/include/configs/sun6i.h
+++ b/include/configs/sun6i.h
@@ -14,7 +14,6 @@
 /*
  * A31 specific configuration
  */
-#define CONFIG_CLK_FULL_SPEED		1008000000
 
 #ifdef CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_SUNXI
diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h
index f817f73..7fa7cec 100644
--- a/include/configs/sun7i.h
+++ b/include/configs/sun7i.h
@@ -12,7 +12,6 @@
 /*
  * A20 specific configuration
  */
-#define CONFIG_CLK_FULL_SPEED		912000000
 
 #ifdef CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_SUNXI
@@ -21,8 +20,7 @@
 
 #define CONFIG_ARMV7_PSCI		1
 #define CONFIG_ARMV7_SECURE_BASE	SUNXI_SRAM_B_BASE
-#define CONFIG_SYS_CLK_FREQ		24000000
-#define CONFIG_TIMER_CLK_FREQ		CONFIG_SYS_CLK_FREQ
+#define CONFIG_TIMER_CLK_FREQ		24000000
 
 /*
  * Include common sunxi configuration where most the settings are
diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h
index 3bdedb3..79796d7 100644
--- a/include/configs/sun8i.h
+++ b/include/configs/sun8i.h
@@ -12,7 +12,6 @@
 /*
  * A23 specific configuration
  */
-#define CONFIG_CLK_FULL_SPEED	1008000000
 
 #ifdef CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_SUNXI
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index df89d14..d4688c5 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -1,6 +1,7 @@
 /*
  * Copyright (C) 2012-2015 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2015      Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -275,20 +276,13 @@
 #define CONFIG_SPL_TEXT_BASE		0x00100000
 #endif
 
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#endif
+#define CONFIG_SPL_STACK		(0x0ff08000)
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE)
 
-#define CONFIG_SYS_SPL_MALLOC_START	(0x0ff00000)
-#define CONFIG_SYS_SPL_MALLOC_SIZE	(0x00004000)
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_INIT_SP_ADDR		(0x0ff08000)
-#else
-#define CONFIG_SYS_INIT_SP_ADDR		((CONFIG_SYS_TEXT_BASE) - 0x00001000)
-#endif
+#define CONFIG_PANIC_HANG
 
 #define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_NAND_SUPPORT
 
 #define CONFIG_SPL_LIBCOMMON_SUPPORT	/* for mem_malloc_init */
@@ -298,4 +292,6 @@
 
 #define CONFIG_SYS_NAND_U_BOOT_OFFS		0x10000
 
+#define CONFIG_SPL_MAX_FOOTPRINT		0x10000
+
 #endif /* __CONFIG_UNIPHIER_COMMON_H__ */
diff --git a/include/configs/vct.h b/include/configs/vct.h
index 83e4163..88e58ec 100644
--- a/include/configs/vct.h
+++ b/include/configs/vct.h
@@ -25,7 +25,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_DISPLAY_BOARDINFO
 
 #define CPU_CLOCK_RATE			324000000 /* Clock for the MIPS core */
diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h
index 810eef1..c472143 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -15,20 +15,11 @@
 #ifndef CONFIG_SEMIHOSTING
 #error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING
 #endif
-#define CONFIG_BOARD_LATE_INIT
 #define CONFIG_ARMV8_SWITCH_TO_EL1
 #endif
 
 #define CONFIG_REMAKE_ELF
 
-#if !defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) && \
-    !defined(CONFIG_TARGET_VEXPRESS64_JUNO)
-/* Base FVP and Juno not using GICv3 yet */
-#define CONFIG_GICV3
-#endif
-
-/*#define CONFIG_ARMV8_SWITCH_TO_EL1*/
-
 #define CONFIG_SUPPORT_RAW_INITRD
 
 /* Cache Definitions */
@@ -47,8 +38,7 @@
 #define CONFIG_SYS_TEXT_BASE		0xe0000000
 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
 #else
-#define CONFIG_SYS_TEXT_BASE		0x80000000
-#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
+#error "Unknown board variant"
 #endif
 
 /* Flat Device Tree Definitions */
@@ -118,10 +108,9 @@
 #define GICD_BASE			(0x2C010000)
 #define GICC_BASE			(0x2C02f000)
 #else
-#define GICD_BASE			(0x2C001000)
-#define GICC_BASE			(0x2C002000)
+#error "Unknown board variant"
 #endif
-#endif
+#endif /* !CONFIG_GICV3 */
 
 #define CONFIG_SYS_MEMTEST_START	V2M_BASE
 #define CONFIG_SYS_MEMTEST_END		(V2M_BASE + 0x80000000)
@@ -200,12 +189,12 @@
 /* Initial environment variables */
 #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
 #define CONFIG_EXTRA_ENV_SETTINGS	\
-				"kernel_name=uImage\0"	\
-				"kernel_addr_r=0x80000000\0"	\
+				"kernel_name=uImage\0"		\
+				"kernel_addr=0x80000000\0"	\
 				"initrd_name=ramdisk.img\0"	\
-				"initrd_addr_r=0x88000000\0"	\
-				"fdt_name=devtree.dtb\0"		\
-				"fdt_addr_r=0x83000000\0"		\
+				"initrd_addr=0x88000000\0"	\
+				"fdt_name=devtree.dtb\0"	\
+				"fdt_addr=0x83000000\0"		\
 				"fdt_high=0xffffffffffffffff\0"	\
 				"initrd_high=0xffffffffffffffff\0"
 
@@ -213,24 +202,17 @@
 				"0x1c090000 debug user_debug=31 "\
 				"loglevel=9"
 
-#define CONFIG_BOOTCOMMAND	"fdt addr $fdt_addr_r; fdt resize; " \
-				"fdt chosen $initrd_addr_r $initrd_end; " \
-				"bootm $kernel_addr_r - $fdt_addr_r"
+#define CONFIG_BOOTCOMMAND	"smhload ${kernel_name} ${kernel_addr}; " \
+				"smhload ${fdt_name} $fdt_addr; " \
+				"smhload ${initrd_name} $initrd_addr initrd_end; " \
+				"fdt addr $fdt_addr; fdt resize; " \
+				"fdt chosen $initrd_addr $initrd_end; " \
+				"bootm $kernel_addr - $fdt_addr"
 
 #define CONFIG_BOOTDELAY		1
 
 #else
-
-#define CONFIG_EXTRA_ENV_SETTINGS	\
-					"kernel_addr_r=0x80000000\0"	\
-					"initrd_addr_r=0x88000000\0"	\
-					"fdt_addr_r=0x83000000\0"		\
-					"fdt_high=0xa0000000\0"
-
-#define CONFIG_BOOTARGS			"console=ttyAMA0,115200n8 root=/dev/ram0"
-#define CONFIG_BOOTCOMMAND		"bootm $kernel_addr_r " \
-					"$initrd_addr_r:$initrd_size $fdt_addr_r"
-#define CONFIG_BOOTDELAY		-1
+#error "Unknown board variant"
 #endif
 
 /* Do not preserve environment */
diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
index 994874c..b7dd63e 100644
--- a/include/configs/x86-common.h
+++ b/include/configs/x86-common.h
@@ -243,7 +243,34 @@
 
 #define CONFIG_CMD_USB
 
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	CONFIG_STD_DEVICES_SETTINGS
+/* Default environment */
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_HOSTNAME		"x86"
+#define CONFIG_BOOTFILE		"bzImage"
+#define CONFIG_LOADADDR		0x1000000
+
+#define CONFIG_EXTRA_ENV_SETTINGS			\
+	CONFIG_STD_DEVICES_SETTINGS			\
+	"netdev=eth0\0"					\
+	"consoledev=ttyS0\0"				\
+	"othbootargs=acpi=off\0"			\
+	"ramdiskaddr=0x2000000\0"			\
+	"ramdiskfile=initramfs.gz\0"
+
+#define CONFIG_RAMBOOTCOMMAND				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftpboot $loadaddr $bootfile;"			\
+	"tftpboot $ramdiskaddr $ramdiskfile;"		\
+	"zboot $loadaddr 0 $ramdiskaddr $filesize"
+
+#define CONFIG_NFSBOOTCOMMAND				\
+	"setenv bootargs root=/dev/nfs rw "		\
+	"nfsroot=$serverip:$rootpath "			\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftpboot $loadaddr $bootfile;"			\
+	"zboot $loadaddr"
 
 #endif	/* __CONFIG_H */
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 5ac515d..11a7b86 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -347,7 +347,10 @@
 
 /**
  * Look at the pci address of a device node that represents a PCI device
- * and parse the bus, device and function number from it.
+ * and parse the bus, device and function number from it. For some cases
+ * like the bus number encoded in reg property is not correct after pci
+ * enumeration, this function looks through the node's compatible strings
+ * to get these numbers extracted instead.
  *
  * @param blob		FDT blob
  * @param node		node to examine
diff --git a/include/net.h b/include/net.h
index 43e3d28..237c932 100644
--- a/include/net.h
+++ b/include/net.h
@@ -191,6 +191,8 @@
 /* Ethernet header size */
 #define ETHER_HDR_SIZE	(sizeof(struct ethernet_hdr))
 
+#define ETH_FCS_LEN	4		/* Octets in the FCS		*/
+
 struct e802_hdr {
 	uchar		et_dest[6];	/* Destination node		*/
 	uchar		et_src[6];	/* Source node			*/
diff --git a/include/netdev.h b/include/netdev.h
index 90140bd..c69533e 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -69,6 +69,7 @@
 int ne2k_register(void);
 int npe_initialize(bd_t *bis);
 int ns8382x_initialize(bd_t *bis);
+int pch_gbe_register(bd_t *bis);
 int pcnet_initialize(bd_t *bis);
 int ppc_4xx_eth_initialize (bd_t *bis);
 int rtl8139_initialize(bd_t *bis);
@@ -123,6 +124,9 @@
 #ifdef CONFIG_E1000
 	num += e1000_initialize(bis);
 #endif
+#ifdef CONFIG_PCH_GBE
+	num += pch_gbe_register(bis);
+#endif
 #ifdef CONFIG_PCNET
 	num += pcnet_initialize(bis);
 #endif
diff --git a/include/usb_ether.h b/include/usb_ether.h
index b38d037..23507e1 100644
--- a/include/usb_ether.h
+++ b/include/usb_ether.h
@@ -18,7 +18,6 @@
 #define ETH_ZLEN	60		/* Min. octets in frame sans FCS */
 #define ETH_DATA_LEN	1500		/* Max. octets in payload	 */
 #define ETH_FRAME_LEN	PKTSIZE_ALIGN	/* Max. octets in frame sans FCS */
-#define ETH_FCS_LEN	4		/* Octets in the FCS		 */
 
 struct ueth_data {
 	/* eth info */
diff --git a/scripts/kconfig/Makefile b/scripts/kconfig/Makefile
index 349f770..ff4ce6e 100644
--- a/scripts/kconfig/Makefile
+++ b/scripts/kconfig/Makefile
@@ -5,6 +5,12 @@
 PHONY += oldconfig xconfig gconfig menuconfig config silentoldconfig update-po-config \
 	localmodconfig localyesconfig
 
+# Added for U-Boot
+#  Linux has defconfig files in arch/$(SRCARCH)/configs/,
+#  on the other hand, U-Boot does in configs/.
+#  Set SRCARCH to .. fake this Makefile.
+SRCARCH := ..
+
 ifdef KBUILD_KCONFIG
 Kconfig := $(KBUILD_KCONFIG)
 else
@@ -104,6 +110,10 @@
 %_defconfig: $(obj)/conf
 	$(Q)$< --defconfig=arch/$(SRCARCH)/configs/$@ $(Kconfig)
 
+# Added for U-Boot (backward compatibility)
+%_config: %_defconfig
+	@:
+
 configfiles=$(wildcard $(srctree)/kernel/configs/$(1).config $(srctree)/arch/$(SRCARCH)/configs/$(1).config)
 
 define mergeconfig
diff --git a/scripts/multiconfig.sh b/scripts/multiconfig.sh
deleted file mode 100755
index cc8a787..0000000
--- a/scripts/multiconfig.sh
+++ /dev/null
@@ -1,102 +0,0 @@
-#!/bin/sh
-#
-# A wrapper script to adjust Kconfig for U-Boot
-#
-# This file will be removed after cleaning up defconfig files
-#
-# Copyright (C) 2014, Masahiro Yamada <yamada.m@jp.panasonic.com>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-set -e
-
-# Make a configuration target
-# Usage:
-#   run_make_config <target> <objdir>
-# <target>: Make target such as "config", "menuconfig", "defconfig", etc.
-run_make_config () {
-	# Linux expects defconfig files in arch/$(SRCARCH)/configs/ directory,
-	# but U-Boot has them in configs/ directory.
-	# Give SRCARCH=.. to fake scripts/kconfig/Makefile.
-	$MAKE -f $srctree/scripts/Makefile.build obj=scripts/kconfig SRCARCH=.. $1
-}
-
-do_silentoldconfig () {
-	run_make_config silentoldconfig
-
-	# If the following part fails, include/config/auto.conf should be
-	# deleted so "make silentoldconfig" will be re-run on the next build.
-	$MAKE -f $srctree/scripts/Makefile.autoconf || {
-		rm -f include/config/auto.conf
-		exit 1
-	}
-
-	# include/config.h has been updated after "make silentoldconfig".
-	# We need to touch include/config/auto.conf so it gets newer
-	# than include/config.h.
-	# Otherwise, 'make silentoldconfig' would be invoked twice.
-	touch include/config/auto.conf
-}
-
-cleanup_after_defconfig () {
-	rm -f configs/.tmp_defconfig
-	# ignore 'Directory not empty' error
-	# without using non-POSIX option '--ignore-fail-on-non-empty'
-	rmdir arch configs 2>/dev/null || true
-}
-
-# Usage:
-#  do_board_defconfig <board>_defconfig
-do_board_defconfig () {
-	defconfig_path=$srctree/configs/$1
-
-	if [ ! -r $defconfig_path ]; then
-		echo >&2 "***"
-		echo >&2 "*** Can't find default configuration \"configs/$1\"!"
-		echo >&2 "***"
-		exit 1
-	fi
-
-	mkdir -p arch configs
-	# prefix "*:" is deprecated.  Drop it simply.
-	sed -e 's/^[+A-Z]*://' $defconfig_path > configs/.tmp_defconfig
-
-	run_make_config .tmp_defconfig || {
-		cleanup_after_defconfig
-		exit 1
-	}
-
-	cleanup_after_defconfig
-}
-
-do_board_felconfig () {
-    do_board_defconfig ${1%%_felconfig}_defconfig
-    if ! grep -q CONFIG_ARCH_SUNXI=y .config || ! grep -q CONFIG_SPL=y .config ; then
-	echo "$progname: Cannot felconfig a non-sunxi or non-SPL platform" >&2
-	exit 1
-    fi
-    sed -i -e 's/\# CONFIG_SPL_FEL is not set/CONFIG_SPL_FEL=y\nCONFIG_UART0_PORT_F=n/g' \
-	.config
-}
-
-do_others () {
-	run_make_config $1
-}
-
-progname=$(basename $0)
-target=$1
-
-case $target in
-*_defconfig)
-	do_board_defconfig $target;;
-*_felconfig)
-	do_board_felconfig $target;;
-*_config)
-	# backward compatibility
-	do_board_defconfig ${target%_config}_defconfig;;
-silentoldconfig)
-	do_silentoldconfig;;
-*)
-	do_others $target;;
-esac
diff --git a/tools/mkenvimage.c b/tools/mkenvimage.c
index 6971b91..8eee72e 100644
--- a/tools/mkenvimage.c
+++ b/tools/mkenvimage.c
@@ -214,14 +214,10 @@
 		}
 		ret = close(txt_fd);
 	}
-	/* The +1 is for the additionnal ending \0. See below. */
-	if (filesize + 1 > envsize) {
-		fprintf(stderr, "The input file is larger than the environment partition size\n");
-		return EXIT_FAILURE;
-	}
 
-	/* Replace newlines separating variables with \0 */
-	for (fp = 0, ep = 0 ; fp < filesize ; fp++) {
+	/* Parse a byte at time until reaching the file OR until the environment fills
+	 * up. Check ep against envsize - 1 to allow for extra trailing '\0'. */
+	for (fp = 0, ep = 0 ; fp < filesize && ep < envsize - 1; fp++) {
 		if (filebuf[fp] == '\n') {
 			if (fp == 0 || filebuf[fp-1] == '\n') {
 				/*
@@ -249,6 +245,25 @@
 			envptr[ep++] = filebuf[fp];
 		}
 	}
+	/* If there are more bytes in the file still, it means the env filled up
+	 * before parsing the whole file.  Eat comments & whitespace here to see if
+	 * there was anything meaning full left in the file, and if so, throw a error
+	 * and exit. */
+	for( ; fp < filesize; fp++ )
+	{
+		if (filebuf[fp] == '\n') {
+			if (fp == 0 || filebuf[fp-1] == '\n') {
+				/* Ignore blank lines */
+				continue;
+			}
+		} else if ((fp == 0 || filebuf[fp-1] == '\n') && filebuf[fp] == '#') {
+			while (++fp < filesize && filebuf[fp] != '\n')
+			continue;
+		} else {
+			fprintf(stderr, "The environment file is too large for the target environment storage\n");
+			return EXIT_FAILURE;
+		}
+	}
 	/*
 	 * Make sure there is a final '\0'
 	 * And do it again on the next byte to mark the end of the environment.